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ABSTRACT

A DATA CONVERTER FOR AN ADAPTIVE
PROGRAMMABLE MEASUREMENT SYSTEM

BY

Sigurd L. Lillevik

A data converter for an adaptive programmable measurement
system has been specified, designed, constructed, and evaluated. Its
function is to sample analog voltages and translate them into digital
formats compatable with Computer Automation's Alpha-16 minicomputer.

The data converter has been designed to sample 32 analog volt-
age channels, upward expandable to 256 channels, at a maximum sampling
rate of 10,000 samples per second. These voltages may range from -5 V
to +5 V and have Thevenin series resistances of less than 1 k ohms.

The input impedance of the data converter is a shunt capacitance in
parallel with a resistance of 10 megohms. It is shown that as long

as the shunt capacitance is less than 0.16 microfarads, the analog
signals will not be significantly attenuated. Since the programmable
measurement system must be adaptive there are two modes of operation
(manual and automatic), each with three schemes of operation (sequential,
random, and static). Resolution of the data converter is 2.5 milli-
volts, and it has an accuracy better than 0.1% of full-scale. The output
of the data converter is a 12-bit binary word.

Several experiments were performed on the data converter for

the purpose of evaluating its performance. It was demonstrated that

Sigurd L. Lillevik

the data converter's control logic functioned as designed, and that the
accuracy (0.09% of'fUII-scale) exceeds the required accuracy (0.1% of

full-scale). An example is provided which illustrates the basic dynamic

properties of the data converter.

A DATA CONVERTER FOR AN ADAPTIVE

PROGRAMMABLE MEASUREMENT SYSTEM

BY
. CW.“ .
Sigurd L. LilleVik

A THESIS

Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

MASTER OF SCIENCE
Department of Electrical Engineering

and
Systems Science

1974

3° ACKNOWLEDGMENTS

I wish to thank my major professor, Dr. P. David Fisher, for
his guidance during the entire course of this research project. While
the thesis was being prepared he provided encouragement and inspiration,
for this I am deeply grateful.

Special appreciation is extended to Dr. L. J. Giacoletto, Dr. J. B.
Kreer, and Dr. G. L. Park for their thorough review of the thesis.
Others who have contributed to the completion of this research project
include: Mr. Stephen M. Welch for his advise on software decisions,

Mr. James W. Maine for his advise on hardware decisions, and Mr. Gary D.
Bauer for his diagnostic program. Finally, I wish to thank my wife,
Sandi, for her typing of the thesis and encouragement during the final

stages of this research project.

ii

TABLE OF CONTENTS
Chapter Page

I. INTRODUCTIONO00.0.0.0.0....0OO0.000.000.00.0000000.00 1
II. DESIGN SPECIFICATIONSOOO0OO00.00000000000000000000... 3

2.1 Output characteristics of the signal
conditioners ........ .................... ...... ..
2 Characteristics of the minicomputer I/O.........
.3 Transfer characteristics of the overall
system.............. ..... .. ..... ................
2 4 Environmental 1imitations....... ..... ...........
2.5 Ca1ibration.................. ......... ..........
2 6 Summary.................... ..... ................

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III. SIXTEEN-BIT INPUT/0mm MODUIE0.0.00...00.0000...... lo

3 1 General description............................. 10
3 2 Loading of the signal lines..................... 12
3.3 Software Implementation......................... 13
3 4 Summary......................................... 14

IV. CIRCUIT REALIZATION.................................. 15
4 1 Theory of operation............................. 15
4 2 Component identification........................ 18
4.3 Circuit description............................. 19
4 4
4 5

Construction of the prototype................... 36
smarYOOO0.000......0000000000000.0000000...0.. 38

V. PERFORMANCE00000..00.0..000.00....00.0.0.0....0000000 39
5 1 Verification of control logic................... 39
5 2 Calibration of the ADC.......................... 43
5.3 Determination of the static accuracy............ 45
5 4 An example of the dynamic response.............. 47
55 smnary0000000.0.0.0.0.00.00000000..0.0.0.0.0000 47
VI. SUMRY... OOOOOOOOOOOOOO 0.0000.00000000000000.0000... 51
mmmw80000.00000 ...... 0.00.00.00.00 00000 000...... 53
APPENDICES

A. Glossary. ........ ........................... 54

iii

B.
C.
D.
E.

16-bit I/O module signal definitions........
Data converter photographs..................
Data converter dynamic response program.....
Data converter parts list...................

iv

Page
56
59
63
72

LIST OF TABLES

Representative environmental data required.............

Experimental results used to determine static
accuracy0000000.0000000000...0..000.00.00.00.0.000000..

Results of the dynamic response test-
Without multiplexing000000...00.00..0.00.00.00.00.0.000

Results of the dynamic response test-
With multiplexing ......... .0.0.0000.00.000.00000000000.

Page

46

49

49

LIST OF FIGURES

Figure Page
1.1 Block diagram of the programmable measurement
system............................................. 2
3.1 Block diagram of the 16-bit I/O module............. 11
4.1 Block diagram of the data converter................ 16
4.2 Data converter lower register circuit.............. 20
4.3 Data converter upper register circuit.............. 22
4.4 Data converter switch register circuit............. 24
4.5 Data converter multiplexer circuit................. 26
4.6 Data converter DAS-l6 circuit...................... 28
4.7 Data converter control circuit..................... 30
4.8 Control circuit timing diagram..................... 31
4.9 Data converter I/O (1) circuit..................... 33
4.10 Data converter I/O (2) circuit..................... 34
4.11 Data converter I/O (3) circuit..................... 35
5.1 Data converter manual operation algorithm.......... 40
5.2 A program to verify the data converter's
automatic operation................................ 42
5.3 Calibration circuit for the data converter......... 44
5.4 Circuit used in the dynamic response test.......... 48
C.l Data converter, teletype, and Alpha-l6 mini-
computer........................................... 59
C.2 Computer Automation's Alpha-l6 and dual cassette
tape transport..................................... 60
C.3 Data converter front view.......................... 61
C.4 Data converter rear view........................... 62

vi

CHAPTER I INTRODUCTION

A programmable measurement system has been proposed for the pur-

(l)

pose of monitoring and managing pest-crop ecosystems. This facility
must be adaptive and must be capable of providing real-time environmen-
tal information in a form which is readily available to users involved
in the design and implementation of pest-management systems. One essen-
tial component in this measurement facility is the DATA CONVERTER (see
Figure 1.1). It links environmental signals with the minicomputer.
Specifically, its function is to sample the analog voltages on each
channel, and translate these into a digital format which is acceptable
to the minicomputer.

The purpose of the research project reported here was to specify,
design, construct, and evaluate the data converter. The output charac-
teristics of the programmable measurement system, its overall transfer
characteristics, and the I/O requirements of the minicomputer, establish
the design specifications for the data converter. These design specifi-
cations are described in Chapters II and III. The details of the proto-
typed circuit are presented in Chapter IV. Experimental procedures used

to evaluate the data converter are described in Chapter V. The exper-

imental results are also summarized in Chapter V.

 

 

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CHAPTER II DESIGN SPECIFICATIONS

The data converter is but one component in the overall pro-
grammable measurement system (see Figure 1.1) and, as such, must inter-
act with other components in the system. Its basic functions are to
select a predetermined analog signal line, sample the information on
the line, code it, and present it to the minicomputer for processing.
This sequence of events must be accomplished under program control with-
out the necessity of operator interaction. The principal design spec-
ifications placed on the converter depend upon the following:

1) the output characteristics of the signal conditioners,

2) the I/O properties of the minicomputer,

3) the transfer characteristics of the programmable measure-
ment system,

4) the environmental limitations, and
5) the calibration requirements.

These design specifications will be enumerated in this Chapter.
2.1 Output Characteristics of the Signal Conditioners

In the initial application of the programmable measurement
system 13 distinct types of environmental signals will be observed (see
Table 2.1)52)From discussions with the users of this equipment it was
felt that the data converter should be designed to multiplex 32 analog
channels. Also, in the event that, at some future time, it becomes
desirable to increase the number of channels, facilities for expansion
of up to 256 channels should be provided.

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Because of the widely differing characteristics of the environ-
mental data, two sampling modes are needed. The first mode involves a
fixed sampling rate, whereby the minicomputer changes channels according
to a predetermined pattern. The second mode uses a variable sampling rate,
the minicomputer samples channels only when it has received an external
stimulus (i.e., an interrupt).

To determine the maximum sampling rate of the data converter,

Table 2.1 can be employed as a useful guide. Wind speed has the great-
est rate of change of the parameter per unit time, and is found to be a
change of 60% of full-scale per second. If 100 microseconds are needed
for a complete conversion, then in one second 10,000 conversions are pos-
sible. As a worst case analysis, let us assume that 200 channels must be
multiplexed, then each channel receives 50 conversions per second. Now

if 5 readings are required to accurately determine a full-scale change,
then 10 full-scale changes per second will be achieved. Since only 1 full-
scale change per second is needed, a total conversion time of 100 micro-
seconds appears adequate for 200 signals similar to wind Speed. When fewer
than 200 channels are multiplexed, great improvements in the sampling rate
is realized.

The signal conditioners present the data converter with a Thevenin
equivalent voltage source that may swing -5 V to +5 V. and a Thevenin
series resistance of less than 1,000 ohms. The input impedance of the data
converter is a capacitance (due to the analog signal cables and other stray
capacitances) in parallel with a load resistance. This load resistance is
mainly due to the input resistance of the multiplexers. Because the load
resistance is much greater than the Thevenin equivalent series resistance

(10 megohms compared to 1,000 ohms) the signal conditioner and multiplexer

6
act as an RC low-pass filter. This RC low-pass filter model can be used
to determine the maximum allowable capacitance.

Of the environmental signals, wind speed has the highest frequency
--1 Hz (see Table 2.1), If we assume, as a worst case analysis, that the
highest frequency of the RC low-pass filter is 1,000 Hz, and that the series
resistance is 1,000 ohms, then the signal will attenuate 3dB when the cap-
acitance is 0.16 microfarads. As long as the combined capacitance of the
analog signal cable, and all associated stray capacitance, is less than
0.16 microfarads, the environmental signal will not be attenuated too
severely.

The data converter will have single-ended inputs, thus, there will
be a common signal ground for all channels. This analog signal ground
will be separate from the digital circuit ground, only coming together
at the system power supply ground mecca. This technique of using distinct
analog and digital grounds allows separate current returns for the low-
frequency components of the analog signals, and the high-frequency com-
ponents of the digital pulses. (For further details on this subject, An-

(3)

alog Devices has published "Analog-Digital Conversion Handbook." )

2.2 Characteristics of the Minicomputer I/O

Computer Automation'SAlpha-16 is a general purpose 16-bit word-
length digital minicomputer.(4) The I/O data lines transfer information
in bit-parallel, word-serial, manner. These lines conform to standard
TTL logic levels and loads, and operate asynchronously to accomodate many
peripherals with widely varying speeds. Because the minicomputer can per-
form the data transfers in the microsecond range, as compared to 100

microseconds required for the data converter to operate, time constants

in the I/O module are inconsequential with respect to data transfers.

7

Details of the minicomputer's I/O structure will be discussed in Chapter

III.
2.3 Transfer Characteristics of the Overall Measurement System

The measurement system must select a predetermined analog signal
line, sample the information on the line, code it, and present it to the
minicomputer for processing. This entire operation must be accomplished
without the loss of required information. Representing this loss of infor-
mation is the degree of accuracy required.

Accuracy is the difference between the measured value and the
actual value. This difference is usually expressed in terms of percent
of full-scale. As noted in Table 2.1 the required accuracy is 1% of full-
scale, to provide a margin of safety the overall accuracy of the data
converter will be .1% of full-scale.

The overall accuracy of the data converter can be understood in
terms of the following parameters:

a) repeatability,

b) linearity,

c) hysteresis,

d) sensitivity,

e) resolution, and

f) threshold.

Each of the above parameters have established meanings for measurement

5
systems (see "Measurement Systems: Application and Design", by Doebelin( )

),

and it will be required that the conglomeration of all these errors is no

greater than 1 LSB.

2.4 Environmental Limitations

The environmental limitations placed on the programmable
measurement systems, will determine the construction and packaging
constraints. It is envisioned that the entire system will be housed
in a standard 19" rack-type cabinet. This method of mounting is
desirable to compliment the rack cabinet of the minicomputer and asso-
ciated peripherals. The size and weight of the entire unit must be such
as to conveniently fit inside an 8 foot by 6 foot by 7 foot portable
utility trailer. Because the trailer may be moved from point to point,
steps must be taken to eliminate damage caused by excessive vibration.

Power will be available in the form of standard 117 V AC, 60 Hz,
presenting no problems. Three power supplies will be distributed through-
out the data converter, +15 V DC, -15 V DC, and +5 V DC. These three
power supplies will accomodate both analog and digital circuits.

The ambient temperature within the trailer can range from 0
degrees Celsius to 60 degrees Celsius, and the humidity may vary up to
100% noncondensing. In either extreme the measurement system.must be
operable. These design and packaging limitations should not be over-

looked, and must be included in the design considerations.
2.5 Calibration

Several aspects are involved in the measurement system's reali-
ability, or "trust—worthiness". Calibration is an important aspect, for
it guarantees that the measurement system has the required transfer
characteristics. To facilitate the calibration procedure, no special-
ized or sophisticated test equipment should be necessary--test equipment
should be "built-in" to the circuitry if possible.

Probability of failure should be lowered by providing means by

9

which the minicomputer can evaluate the integrity of major circuits. These
checks can be included in the initialization section of all software data
taking routines. When an error condition has been detected, some external
means of warning should be available. If these few aspects of calibration
are implemented into the design, the measurement system's realiability

will be increased.
2.6 Summary

At the present time, one can not purchase an "off-the-shelf" com-
mercially manufactured programmable measurement system which meets the
above requirements. In the future, it is expected, this will be possible;
however, until that time important biological research will be unnecess-
arily delayed.

An alternative approach is to have the programmable measurement
system custom designed, and a prototype built, by another firm. In terms
of man-years and cost this is a poor choice. Delivery dates and price
quotations can be exaggerated, causing the project time-table to be sig-
nificantly altered.

By designing and prototyping the measurement system from'within
the project group personnel, again in terms of man-years and cost, it is
usually found that results only differ slightly from an outside firm. Yet
several benefits will be derived from an inter-project effort, benefits
such as the experience and expertise gained in this area of instrumenta-

tion.

CHAPTER III SIXTEEN-BIT INPUT/OUTPUT MODULE

(6)

Computer Automation's "l6-Bit Input/Output Module" facilitates
the unambiguous exchange of information between the central processing
unit (CPU) and a peripheral device. The module is comprised of four
principal circuits: control, interrupt, input buffer and output buffer.

These four circuits are illustrated in Figure 3.1. A general descrip-

tion of each of these circuits will be provided below.

3.1 General Description

Control Circuits- The control circuits "select" and "sense" func-
tions both internal and external to the I/O module. The external control
circuits are of primary interest to the digital systems designer because
they allow the CPU, under program control, to select unique functions
within the peripheral (such as setting a flip-flop which enables the paper
tape punch of a teletype), or to sense the status of peripheral defined
functions (such as sensing a flip-flop output to determine whether the

paper punch of a teletype is indeed in the desired state).

Interrupt Processing Circuits- The interrupt processing circuits

 

respond to externally generated interrupt conditions and generate a vec-
tored interrupt request. The CPU responds by branching to the vectored
software address and executing the instruction at this address. The next
branching of the CPU would depend upon the nature of this instruction and
the priority level of the interrupt. As a specific example, the instruction

may authorize the CPU to jump to an address and enter a data acquisition routine.

10

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Input Buffer Circuits- The input buffer circuits temporarily

 

store peripheral input data until the CPU is ready to accept the data. If
the buffer is empty, the peripheral device places the input data on

the input lines and generates a strobe. The strobe clocks the data into
the input buffer register.

Output Buffer Circuits- The output buffer circuits temporarily

 

store CPU output data until the peripheral device can accept the data.
The CPU loads the data into the output buffer register. When the per-

ipheral device is ready, it reads the output buffer register.
3.2 Loading of the Signal Lines

The artificial boundary that exists between the I/O module and
the peripheral device is composed of 90 signal lines. For a more
detailed explanation, see Appendix B. All of these lines are uni-
directional, and each line terminates on the module at either a signal
driver (for output signals from the module) or a signal receiver (for
input signals to the module). The signal drivers are open-collector
NPN transistors. These driving transistors may each be "pulled-up" to
+15 V DC with a collector resistor, and can sink up to 40 milliamperes
when driven to ground. These open-collector drivers are very flexible,
and in some applications may be used as a "wired-or" gate. The signal
receivers present one TTL unit load to the peripheral device. (A standard
TTL load is -l.6 milliamperes into the module for a logical "0" volt-
age level, and 40 microamperes into the module for a logical "1" volt-
age level. Ideal TTL voltage levels are 4.5 V to 5.0 V for a logical

"l" or high, and 0.0 V to 0.8 V for a logical "0" or low57)

)
A standard TTL inverter, a 7404, is recommended by Computer

Automation as a peripheral signal driver because it has a fan-out of

13

10 unit loads. As a peripheral signal receiver, Computer Automation
recommends any standard TTL gate with the multiple emitter input transis-
tor. These loading requirements are very modest since the I/O module
was designed to see standard 7400 series TTL circuitry.

Computer Automation also recommends twisted-wire pairs be used
in the I/O cable, and that there be at least eighteen twists per foot.
With every twisted-wire pair one lead is always signal ground. To
terminate the I/O cable, at the peripheral, a 330 ohm 1/4 W 10% resistor
is recommended. Computer Automation suggests the use of a 220 ohm 1/4 W
10% resistor for the open-collector driver "pull-up". These strict
loading and matching rules will keep signal deterioration to a minimum

along the I/O cable.
3.3 Software Implementation

There exist four types of I/O instructions applicable to the
"l6-Bit Input/Output Module": Sense, Select, Input, and Output. Sense
instructions may be used to examine unique functions within the per-
ipheral (using ESOO-ESO7) and to perform conditional software branches
on the results of these status checks. The Select instructions may be
used to control a given function within the peripheral (using EXOO-
EX07). Input instructions read data from the input buffer into one of
two working CPU registers. The Input instructions may be combined with
the Sense instructions to form one conditional Input instruction. Out-
put instructions move data from one of two CPU-working registers to the
output buffer, and may be combined with the Sense instructions to form
one conditional Output instruction.

Two special features of the CPU are the ability to perform
8-bit (or byte) input and output transfers, and the ability to mask

(logically "And") input data with the receiving register. These two

14

special CPU features, along with conditional I/O, make the software
instruction set extremely flexible and powerful.

For high speed data transfers directly to or from memory and
the peripheral, Block I/O and Auto I/O instructions are used. Both
instructions have multiple word formats (two or three words), and dur-
ing execution, may be thought of as direct memory channels. Block
I/O has been designed for in-line programming, whereas Auto I/O for
servicing peripheral interrupts. These two high-speed instructions

may be used when I/O transfers must be made every 5 machine cycles.
3.4 Summary

The CPU can easily control and sense functions within the
peripheral and set up high and low-speed data transfers. The I/O
module provides two very convenient digital buffers, and has been
designed to see standard 7400 series TTL circuitry. Finally, the I/O
module will enable the peripheral to utilize the powerful and sophis-
ticated instruction set of the minicomputer.

Numerous trade-offs exist between the software and the hard-
ware. The module has been skillfully designed to encompass a wide
spectrum of applications, and because of this, unavoidable ambiguities
exist. Let's say ITRAN was enabling the input buffer continously, why
then is EST necessary? The obvious answer is that an EST strobe is
required when ITRAN is off. The computer can be programmed to operate
a peripheral in a sequential manner, and it may not be necessary to
use the buffer status lines (IBF, OBE). If the digital systems designer
takes advantage of these software-hardware trade-offs, the interface

design can be greatly simplified in certain applications.

CHAPTER IV CIRCUIT REALIZATION

The design specifications require that an analog—to-digital con-
verter (ADC) and an associated analog voltage signal multiplexer be inter-
faced to the minicomputer via the 16-bit I/O module. Realization of the
required circuitry involves the following sequence:

a) the theory of operation must be conceived,

b) specific components must be identified,

c) the circuit must be described (schematics drawn), and

d) the prototype must be built.

This chapter describes the above process, and reveals the implementation

of the design specifications delineated in Chapters II and III.

4.1 Theory of Operation

Either a minicomputer under program control or an operator must
be able to interact with the data converter so as to control the ADC,
select a multiplexer address, and read the converted data word. A gen-
eral block diagram of such a system is depicted in Figure 4.1.

Because both the minicomputer and the operator must be able to
have control of the data converter there are two fundamental modes of
operation: manual and automatic. To distinguish between these modes
a Gating scheme is employed.

The Multiplexer Address Generator (MAG) has been designed to scan
between a lower multiplexer channel limit and an upper channel limit minus

one. Upon loading new limits into the MAG, it presets the multiplexer

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17

to the lower limit. After the ADC has completed each conversion, the
MAG increments the multiplexer by one channel. When the upper channel
minus one is reached, the MAG automatically presets the multiplexer back
to the lower limit. The output of the MAG, the Multiplexer address, is
available to the operator on a light emitting diode (LED) display.

The MAG may be operated using one of the following schemes;
namely sequential, static, and random. When the MAG holds limits two
or more channels apart and the upper limit is greater than the lower
limit, sequential operation is possible. This type of operation involves
scanning from the lower channel to the upper channel minus one, presetting
back to the lower limit and so forth.

If the limits loaded in the MAG are one channel apart and the
upper limit is greater than the lower limit, then static operation will
occur During this type of operation the MAG increments the multiplexer
only one channel then reaches the upper limit. It then presets back to the
lower limit or original channel. Static operation enables one to
take multiple readings of the same Analog Voltage Channel.

The data converter can also be operated randomly by loading the
MAG with new limits (and presetting) before each ADC conversion. Random
operation requires an extra step (loading the MAG) compared to sequential
or static operation, but the data converter can "skip" channels, providing
maximum freedom.

The Multiplexer receives an address from the MAG and decodes it
to select an Analog Voltage Channel. The selected analog signal is "caught"
by a sample-and-hold circuit while being converted to a digital format
by the ADC. Results are available on a LED diplay, or can be read by

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18

4.2 Component Identification

After the basic theory of operation has been identified, specific
components must be selected. These components are of three classes:
linear, linear-digital, and digital. Justification for the selection of
the components to be discussed, is focused on the requirement that a .l%
of full-scale accuracy be maintained. The agglomeration of the selected
components must produce this accuracy, and experimental data verifying
this will be provided in Chapter V.

It was decided that the linear and linear-digital components be
obtained from Datel Systems, Inc58)The linear components include the MM8 eight
channel analog multiplexer, and the SHM—l sample—and-hold module. The
lone linear-digital component is an ADC—M128 converter, a 12-bit succes-
sive-approximation type analog-to-digital converter. Both the linear and
linear-digital components are available as a modular package (the DAS-l6).
This package also includes additional system control logic and an LED
display.

The digital components were purchased from Signetics, Corpfg) and
included the following:

a) 7400-Quad 2—Input Positive Nand Gate;

b) 7404-Hex Inverter;

c) 7475-Quad Latch;

d) 7485-4—Bit Magnitude Comparator;

e) 74121-Monostable Multivibrator;

f) 74l93-Synchronous Up/Down Binary Counter.

The digital components are all standard 7400 series TTL logic, and are

compatible with both the Datel product line and Computer Automation's

16-bit I/O Module.

19
Once the basic modules (the linear, linear-digital, and digital)

have been selected, the schematic diagrams must be drawn. This process
can be difficult due to the many subtleties involved, such as, maintaining
logic polarities and fan-out/fan-ins, matching module properties, cas-
cading similar components, and maintaining the prOper timing character-

istics.
4.3 Circuit Description

The circuit schematics are comprised of nine drawings, each rep-
resenting distinct aspects of the overall data converter. This section
will describe each drawing, delineating the data signal lines from the
control signal lines. It is important to note that the number within
each symbol corresponds to a physical location.

Lower Register- Figure 4.2 depicts the Lower Register. It acts

 

to store the MAG lower limit, and originates the Multiplexer address. Inte-
grated circuits (IC's) 1 to 6 are 7400 Quad Nand Gates and implement

the Gating scheme represented in Figure 4.1. These Gates accept the data
lines BCO-BC7 from the minicomputer (lower 8-bits) or the data lines
SRLWO-SRLW? defined by the operator. Control signals SRENBL and SRENEE'
select which set of data lines are to be presented to the 7475 Quad Latches
(IC's 7 and 8). These control signals are originated by the operator and
are changed by using a toggle switch. ,When the Quad Latches are strobed by
control signal CLK, the 74193 Binary Counters (IC's 9 and 10) are also
preset, by control signal PRESET, to the same number being strobed into the
Quad Latches. The Binary Counters are cascaded to form an 8-bit counter
whose output represents the output of the MAG. Control signal COUNT incre-
ments the counter, which changes the MPXO-MPX? lines and the Multiplexer

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To help illustrate the above consider the following example:
Suppose the minicomputer's output buffer contained 11110000 (lower 8-bits)
and SRENEI:were high, (SRENBL low). If CLK were strobed the Quad Latches
would store 11110000 (IC 7 all zeros), and if later PRESET were strobed
the counter would preset to 11110000. Now if COUNT were pulsed, then the
MPX lines would increment to the value 11110001.

Upper Register- This circuit is schematically illustrated in

 

Figure 4.3. It stores the MAG upper limit and compares the lower and
upper limits. In much the same manner as in the Lower Register, IC's 1
to 6 (7400 Quad Nand Gates) perform the Gating scheme of Figure 4.1.
These Gates accept the data lines BC8-BC15 from the minicomputer buffer
(upper 8-bits), or the operator defined data lines SRUPO-SRUP7. Control
lines SRENBL and SRENEE select which of these data lines will be pre-
sented to the Quad Latches (IC's 7 and 8, both 7475's), and stored when
control line CLK is strobed.

The 4-Bit Magnitude Comparitors (IC's 9 and 10, both 7485's)
monitor the output of the Quad Latches (the upper limit) and the MPXO-
MPX7 lines (the lower limit) originated in the Lower Register. When these
two sets of data lines are equal, control line A_;-E goes to ground. This
control signal will be utilized by the Lower Register to preset the 8-bit
counter to the lower limit.

An example that illustrates the Upper Register interaction with
the Lower Register is as follows: Suppose the upper limit is 00001000 and
the lower limit is 00000000. After seven COUNT pulses the MPX lines con-
tain 00000111, on the eighth COUNT pulse both limits are equal and AF;_§'
will go low. This change will cause PRESET to be pulsed and the MAG will

be preset to the lower limit, or 00000000.

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Switch Register- In the two previous diagrams (Lower Register
and Upper Register) the data lines which establish the lower and upper
limits were from the minicomputer, the BCO-BC7 and BC8-BC15 lines,
and the operator SRLWO-SRLW7 and SRUPO-SRLW7. The Switch Register
circuit (Figure 4.4) establishes the latter two data lines.

Both sets of data lines employ the same signal scheme, a SPST
toggle switch either closes (for a zero) or remains open. In the open
position a 4.7 K ohm l/4 watt resistor is used as a "pull-up" to provide
the 5 V "one" level. These signal lines are then used to establish
the lower and upper limits of the MAG in the manual mode.

Control signals also originate in the Switch Register circuit.
SRENBL and SRENEE are formed here by a DPDT switch. These control
lines establish the two basic modes of the data converter operation,
i.e., manual and automatic. TWO other control signals, LOAD and CNVRT,
are also found here. These signals are activated by depressing normally-
open momentary toggle switches. Through the use of RC contact bounce
elimination circuits, these toggle switches develop 1 microsecond
pulses.

The last circuit in the Switch Register is a LED driver and
display circuit. The LED's are to be read by the operator to deter—
mine the current Multiplexer (MPX lines) address. The drivers utilize

anRCAum

1c, the CA3081, which contains seven common-emitter NPN tran-
sistors. The transistors are biased "on" by the digital counter and are
essentially no "load" on the TTL logic due to the 10 K ohm base resistor.
The 150 ohm resistor in series with the LED's serve to limit the power
dissipated in the LED's. This type of driver circuit is ideal for this

application because it does not affect the fan-out of the digital logic.

24

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Figure 4.4 Data converter switch register circuit.

25

Multiplexer- This circuit accepts 32 analog voltages, decodes

 

the digital address received from the MAG circuitry, and provides two
analog outputs. The first analog output is for channels 1-16 and the
second for channels 17-32.

The analog signals are connected through a chassis mounted BNC,
and to a DPDT toggle switch (see Figure 4.5). In one position the
analog signal is sent to the MM8 multiplexers by a 28 AWG coaxial cable.
In the other position the MM8 input is "short-circuited", and the ana-
log signal is loaded by a 10 K ohm 1/4 watt resistor. This technique
is used to isolate and terminate the analog signals for testing purposes.

The Multiplexer has the first three channels dedicated to ref-
erence voltages of +5 V DC, ground, and -5 V DC. These voltage levels
arise from a resistance voltage divider across the +15 V and -15 V power
supplies. These voltage levels provide the ADC with full-scale, half-
scale, and zero readings.

Only the lower significant four bits of the MPX lines (MPXO-
MPX3) are needed in the multiplexer decoding circuits. The upper four
bits (MPX4-MPX7) are used by the DAB-16 ADC system. Because the DAS-16
has 16 channels of multiplexing each channel is sub-multiplexed by
another 16 channels. As a specific example suppose address 00010011 is
contained in the MPX lines, the second channel of the DAB-16 and the
third channel of all sub-multiplexers would be selected. Since only the
second channel of the DAS-l6 is selected, only the third channel's
signal of the second group would by converted by the ADC. All other
sub-multiplexer third channels would not pass through the DAS-l6 mult-
iplexers.

To achieve 16 channels of multiplexing from the MM8 modules

26

    
  

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27

(8 channels of multiplexing), they are cascaded using a 7404 Inverter.
This Inverter supplies the necessary condition to switch from one MM8

to the other. Following this idea MM8-l and MM8-2 are used for channels
1 to 16 (output is IN16HI), and MM8-3 and MM8-4 are used for channels

17 to 32 (output is INlSHI). The MM8 modules conform to standard
binary decoding, the MPXO line coresponds to the LSB.

DAS-l6- This ADC system includes 16 channels of multiplexing,

a sample-and-hold circuit, a successive approximation ADC, and internal
control logic. Inputs to the DAB-16 (see Figure 4.6) are the analog
voltages from the sub-multiplexers (INlHI, INlEW to IN16HI, IN16LW),
the address for these channels (RAIl to RAI4), and a CONVERT control
signal.

The DAS-l6 produces a 12-bit data word which is displayed by
LED's, or is read by the minicomputer. The other DAS-l6 output, the BUSY
line, changes logic level during a conversion, and is used fOr control
purposes within the data converter.

Operation of the DAS~16 system is as follows: When a multiplexer
address has been presented to the system, an analog voltage is con-
tinuously observed by the sample-and-hold module. At this time the
CONVERT line is pulsed and the signal is "held" by the sample-and-hold
circuit. During the converting process the BUSY output changes state,
returning to its original logic level at the conclusion of the conversion.
When the BUSY line returns to its normal level many circuits are affected,
this is discussed next.

Control- This circuit is responsible for distributing the con-
trol signals throughout the data converter and to the minicomputer. The

control signals cause the limits to be strobed into the lower and upper

28

 

Figure 4.6 Data converter DAS-l6 circuit.

29

buffer, provide a pulse used to increment the binary counter, pulse
the DAS-l6 to begin a conversion, and initiates an interrupt. The
Control diagram is Figure 4.7.

A timing diagram (Figure 4.8) has been constructed to aid in
understanding the control circuits. When the minicomputer executes
an output instruction and loads the output buffer, a pulse is sent out
on the STB line. Likewise, when the user presses the momentary LOAD
toggle switch a pulse is formed on the LOAD line. In either case, one
of these pulses (200 nsec) will trigger IC 3 (a 74121 Monostable).

The output from the IC is a pulse (CLK) used to strobe the lower and
upper buffer, and preset the binary counter using the PRESET line.

A length of time will go by, at least one machine cycle, and
the minicomputer will issue a SEL :12, 3 (Egg) instruction, or the
user will push the CNVRT toggle switch. At this time IC4 (a 74121
Monostable) will trigger. The result is a 5 microsecond pulse at CONj
VERT, on the trailing edge of this pulse the DAS-16 will begin convert-
ing. The trailing-edge triggering of the DAS-l6 is intentional since
it allows the sample-and-hold module 5 microseconds to settle. The conver-
sion process requires around 10 microseconds as shown on the OAS-16
BUSY line in Figure 4.8-

When the DAB-16 BUSY line returns to ground IC 1 (a 74121
Monostable) fires and is trailing-edge triggered. This pulse is used
to provide an external strobe (ESTB to the input buffer. When the EST
pulse is received by the input buffer, it acknowledges by sending back
A0. This A0 pulse is then looped back to the I/O Module to provide
an interrupt stimulus at RNTl. Thus, the minicomputer interrupts and

reads the input buffer which contains the ADC data word. Notice that

30

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32

EST is only generated when SRENEE is high. This is to prevent an inter-
rupt from occuring when the data converter is in the manual mode.

When EST goes high IC 2 (a 74121 Monostable) fires on the trail-
ing edge producing the 100 nonosecond COUNT pulse. This signal then
increments the binary counter, thus changing the multiplexer by one
channel. This completes the normal operation of the MAG unless the
binary counter has reached the upper limit, for when this occurs ATE-
goes low. When this happens IC 8 (a 74121 Monostable) triggers on the
leading edge of A_;_§: The pulse which IC 8 produces is sent to line
PRESET, putting the MAG back at its lower limit.

I-O Cable- The final three schematics deal specifically with
the I-0 cable. Figure 4.9 illustrates the input data lines, IDOO-IDlS,
to the minicomputer. The signal drivers, IC's 1 to 3 (7404 Hex Invert-
ers), cause the logic level to be inverted. This problem can be cor-
rected by simply grounding the IPOL line on the I/O module connector
(a ground logic level will then be interpreted as a one).

In Figure 4.10 the output data lines of the minicomputer are
shown. For each signal, BCOO-BClS, a 220 ohm open-collector "pull-up"
resistor (to +5 V DC) and a 330 ohm cable matching resistor (to ground)
is used. Both these resistors aid in maintaining the quality of the
digital signals.

The third drawing, Figure 4.11, depicts the E8 to E256 data
lines (which determine the vectored interrupt address), the interface
control signals (EST; STB, Ei3), and several lines used to establish the
digital ground return for the minicomputer and the data converter. If
the desired vectored interrupt address is :92 (hexadecimal), as was the

case, then switches E16 and E128 are left open while the remaining

33

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Figure 4.9 Data converter I/O(l) circuit.

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Figure 4.10 Data converter I/O(2) circuit.

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Figure 4.11 Data converter I.O(3) circuit.

36

switches are closed. Upon recognition of an interrupt, from the data
converter, the minicomputer will then vector to address :92 (hexa-
decimal).

The circuit is now completely described in terms of a theory,
specific components, and electrical schematics. What remains to obtain
realization of the circuit, is to construct the prototype. This step

is outlined in the next Section.
4.4 Construction of the Prototype

The data converter is housed in a standard 19" rack-type cabinet,
four panels are mounted. Each panel can be removed from the rack by
detaching a connector. One panel mounts the 32 BNC chassis connectors,
another the power supplies, a third holds the switch register (for
manual operation), and the fourth panel mounts a card cage assembly.

It is noted thatin Appendix C, several photographs of the data converter
are available.

The BNC panel also includes 32 DPDT on-off toggle switches for the
analog signals. Running from each BNC is a 28 AWG coaxial cable. These
cables are tied together to form a larger cable. This larger cable ends
at a card inserted into the card cage assembly. Located on this card,
besides the 32 coaxial cables, are four MM8 multiplexer modules.

The power supply panel has a +15 V DC and -15 V DC (at 300 milli-
amperes) analog supply and a 5 V DC, 3 ampere, logic supply. A toggle
switch controls the AC power, and a fuse is mounted to provide overload
protection. The voltage outputs are located on the back side of the
panel at a terminal strip, but may also be monitored on the front side

using bannana jacks.

37

The switch register has 19 toggle switches mounted on it. They
are situated on the panel in three groups: control, lower buffer, and
upper buffer. Also included on this panel are 8 LEDs, which display the
current multiplexer address (the MPX lines). The LED drivers are mount-
ed on a small board located on the back of the panel. Signals from the
switch register panel are sent to other circuits on a cable which stops
at a card inserted into the card cage assembly.

The fourth panel contains the card cage assembly which holds
nine cards. Each card slides into its own slot and plugs into its
own connector. Connections between cards are then accomplished by
wiring from connector to connector.

Whenever possible wirewrapping was employed. The IC packages
were inserted into wirewrap sockets, components were soldered to wire-
wrap stakes, and modules were plugged into wirewrap socket terminals.
Characteristics typical of wirewrapping are flexibility and density.
Both these characteristics are desirable whenprototyping.

The I/O cable was constructed with a twisted-pair 26 AWG ribbon
cable. Six lengths of this wire were necessary to send the required
minicomputer signals to and from the data converter. The ribbon cables
were tied together and ended at a card inserted into the cage assembly.
The other end of the I/O cable was wired to a plug which mates with the
16-bit I/O Module. Located on the card are the I/O signal receivers
and drivers, along with a special IC which contains miniature switches.
These switches are used to determine the vectored interrupt address.
This address can be easily modified by these switches.

Because the sockets into which the cage assembly cards are inser-

ted has wirewrap terminals, the backplane connections are wirewrapped.

38

This differs from the card wirewrapping only in wire size, 24 AWG
compared to 30 AWG.

The construction of a prototype involves numerous steps, many
of them too tedious to be discussed here. It is pointed out, though,
that these decisions must be made and can affect many aspects of the

resulting product.
4.5 Summary

Circuit realization can be achieved only after the design
specifications are known. The process begins with a theory of Operation,
components are then identified, next circuit schematics are drawn, and
finally the prototype is built. Before the prototype is installed in
the field, it must be tested to see if the design specifications have,

indeed, been met. Experimental procedures, results, and a discussion

of such tests are the subject of the next Chapter.

CHAPTER V PERFORMANCE

It was necessary to perform several tests on the data converter
to evaluate its actual capabilities. These tests can be grouped as fol-
lows:

l) verification Of control logic,

2) calibration of the ADC,

3) determination of the static accuracy, and

4) an example of the dynamic response.

The first test demonstrates that the data converter's control logic oper-
ates as designed. Calibration Of the ADC, the second test, adjusts the

ADC transfer characteristics for optimum accuracy. The final two tests,
determination of the static accuracy and an example of the dynamic response,
illustrates the DC and AC Operation of the data converter. These four

experiments will be outlined and discussed in.the Chapter.
5.1 Verification of Control Logic

As stated in Section 4.1, there exist two fundamental control logic
modes; namely, manual and automatic. Each of these modes has three schemes
of Operation: sequential, static, and random. Consequentially, six dis-
tinct sets of experiments are required to fully verify that the data con-
verter's control logic Operates as designed.

Verification of the manual mode follows the algorithm outlined
in Figure 5.1. Limits used in the sequential Operation test were 00
(hexadecimal) for the lower channel and 20 (hexadecimal) for the upper

39

4O

 

Select
MAN
mode

1

Set
Limits
in SR

7

Depress
LOAD

13.1)

Depress

 

 

 

 

 

 

 

 

 

 

 

 

 

CNVRT

V

 

 

 

 

Read
MAG LED
Display

 

 

 

   

     
   

Test
Finished
?

No

 

 

Figure 5.1 Data Converter Manual Operation Algorithm.

41
channel. Using these limits, and following the algorithm, the data con-
verter sequentially stepped from channel-to-channel, and preset, as re-
quired, when the upper limit was reached.

Static operation using the manual mode, was achieved by followb
ing the algorithm and loading such sets of limits as: 0-1, 5-6, A—B,
and 15-16 (all hexadecimal). In each case multiple readings of the lower
channel were observed. Random Operation using the manual mode, was
simultaneously verified in this test since the lower channel was changed
(preset) each time that new limits were loaded.

A small program, see Figure 5.2, was written and toggled into
memory to verify automatic operation. The program begins at address 100
(hexadecimal) by loading into the data converter the limits found in the
X register. After the ADC interrupt is reset and armed, the convert
instruction is given. Following the convert instruction is an endless
loop. The minicomputer will interrupt while in this endless loop and
vector to address 92 (hexadecimal). Here the input buffer, containing
the data word, is read into the A register and the program stops. At
this time the limits in the X register may be altered and the program
started again. If the limits are not to be changed the operator depresses
the run switch (on the minicomputer) to continue the program. The pro-
gram is continued and another conversion is made.

To verify each scheme of operation (sequential, static, and ran-
dom) in the automatic mode, identical limits as used in the manual mode,
were stored in the X register. In each case identical results were Ob-
tained; therefore, all six possible schemes of operating the data converter

were verified.

Address

92

93

94

95

100

101

102

103

104

105

42

nge_ Mnemonic
F201 JMP $+l
5896 INA :12,6
0800 HLT

F20C JMP $+:C
6E92 OTX :12,2
4090 SEL :12,0
4091 SEL :12,l
0A00 EIN

4093 SEL :12,3
F600 JMP $+O

Starting address- 100

Comment

Jump to next word
Read input buffer
Stop program

Jump to :101

Load Limits

Reset ADC interrupt
Arm ADC interrupt
Enable all interrupts
Convert

Loop to self

Figure 5.2 A program to verify the data

converter automatic Operation.

 

 

JillIIIIIII'IIII‘. '1 lfll“

 

( I. I‘ III I’W‘I‘ ‘

43

5.2 Calibration of the ADC

This process began after all equipment had been powered for one
hour. The circuit used for calibration is illustrated in Figure 5.3.

A battery was used as a reference voltage to eliminate any "ripple" that
might be associated with a power supply. The voltmeter used to cali-
brate the data converter, a Wavetek 201(}l) has an accuracy of (I)

.ll millivolts on the 10 volt range, and .01 millivolts on the 1 volt
range. Resolution of the voltmeter is to 5 decimal digits. The volt-
meter, then, has sufficient accuracy and resolution to be used for
calibration purposes.

Calibration requires the adjustment Of two miniature lO-turn
potentiometers located on the DAB-16. The two adjustments determine
the ADC off-set and gain.

The off-set is adjusted first by selecting a channel which pre-
sents exactly -5 V DC to the ADC (this voltage is monitored by the volt-
meter). The data converter is operated manually, and the Off-set is ad-
justed until the converted code is 000 (hexadecimal). This determines
the zero code of the ADC.

When the ADC off-set has been set, the gain adjustment is made.
The data converter is operated manually, selecting a channel which pre-
sents exactly 4.9975 V DC (as monitored by the voltmeter). This volt-
age is determined by subtracting 1 LSB from the full-scale voltage, or
2.5 millivolts from 5 volts. The gain adjustment is varied until a code
of FFF (hexadecimal) is displayed in the LED's of the DAS-l6. This

adjustment determines the full-scale code of the ADC.

When the Off-set and gain adjustments have been made, the data

44

 

 

 

 

 

 

22 Volt
(Burgess
5308 or
equiv.)

 

 

    

100 K ohm
Resistance
Decade Box

 

10 K Ohm
(lo-turn)

 

 

 

 

 

 

 

 

Voltmeter

(Wavetek 201)

 

 

 

Data Converter

 

 

 

Figure 5.3 Calibration circuit for the data converter.

45

converter is then fully calibrated. A convenient third voltage (the half-
scale value), analog ground, can now be checked and should yield a code

of 800 (hexadecimal). This type of coding is "off-set binary" since the
analog ground code is 800 (hexadecimal). For a detailed explanation of
the calibration procedure Datel has prepared "Applications Handbook For
Adjustment and Timing of Analog-To-Digital And Digital-To-Analog Con-

12)

(
verter Products".
5.3 Determination of the Static Accuracy

To determine the accuracy of the data converter a circuit iden-
tical to Figure 5.3 was employed. Data points were taken every 0.5 volts
and the results are tabulated in Table 5.1. The final column in the table,
total error, includes both the error of the data converter and the error

of the voltmeter used in the test. The largest error was found to be

9.21 millivolts or 0.0921% of full-scale. Since the required accuracy of
the data converter is 0.1% of full-scale, an experimentally determined

accuracy of 0.0921% of full—scale is, indeed, satisfactory.

The input voltage was varied in both the positive and negative
direction, and no hysteresis was found. To determine if all channels
were identical, in terms of accuracy, a 1.2 volt mercury battery was con-
nected (one at a time) to each analog voltage channel. For all 32 chan-
nels the DAB-16 output code was identical, thus, the calibration and
accuracy tests performed on only one channel are valid for all channels.
It can be deduced, therefore, that all 32 analog voltage channels main-

tain a .0921% of full-scale accuracy.

46

Table 5.1 Experimental results to determine the static accuracy.

 

Input Octal Output Error Voltmeter Total
voltage code voltage (mV) error (:mV) error(th)
-5.00 0000 -5.0000 0.0 0.61 0.61
-4.50 0312 -4.5068 6.8 0.56 7.36
-4.00 0626 -4.0087 8.7 0.51 9.21
-3.50 1144 —3.5053 5.3 0.46 5.76
-3.00 1460 -3.0078 7.8 0.41 8.21
-2.50 1776 -2.5048 4.8 0.36 5.16
-2.00 2317 -l.9946 -5.4 0.30 5.70
-1.50 2627 -1.5063 6.3 0.26 6.56
-l.00 3144 -1.0058 5.8 0.11 5.91
-0.50 3461 -0.5053 5.3 0.06 5.36
0.00 400 0.0000 0.0 0.00 0.00
0.50 4315 0.5004 0.4 0.06 0.46
1.00 4631 0.9985 -1.5 0.10 1.60
1.50 5147 1.5014 1.4 0.26 1.66
2.00 5463 1.9995 -0.5 .30 0.80
2.50 6001 2.5024 2.4 0.36 2.76
3.00 6316 3.0029 2.9 0.41 3.31
3.50 6634 3.5058 5.8 0.46 6.26
4.00 7151 4.0063 6.3 0.51 6.81
4.50 7465 4.5043 4.3 0.56 4.86
5.00 7777 4.9975 -2.5 0.60 3.10

47

5.4 An example of the dynamic response

The purpose of this experiment was to evaluate the basic dynamic
characteristics of the data converter. Figure 5.4 depicts the circuit
used in this test. The oscillator was adjusted to produce a sinusoidal
signal with an amplitude of 10 V peak-to-peak. A program was then exe-
cuted by the Alpha-16 (see Appendix D) which enabled the sinusoidal
waveform to be sampled several thousand times. The channels to be sam-
pled were specified by an operator via the teletype keyboard. This
program was designed to record both the maximum and minimum reading,
find the mean average all readings, and print out these results for each
channel.

The dynamic response test was performed using the static (without
multiplexing) and sequential (with 32 channels of multiplexing) schemes
of operating the data converter. Results of these two tests are tabulated
in Tables 5.2 and 5.3. It is noted that as the frequency of the oscillator
was increased the min and max values began to decrease. When this occurred
the sampling rate and the number of periods observed were not sufficient
to detect the desired min (-5.000) and max (4.997) values. If the sam-
pling rate, or the number of periods observed were increased, then both
min and max values would agree with the lower frequency cases. This of
course, is only true as long as the aperature time (5 microseconds) of
the sample-and-hold module is much less than the period of the sinusoidal

signal.
5.5 Summary

The results of the experiments described in this Chapter clearly
demonstrate that the data converter's control logic is functioning as

designed. Also, the experimental results verify that the accuracy of

 

 

Hewlett Packard
175B
oscilloscope

 

 

A

 

48

 

 

Hewlett Packard
200CD
oscillator

 

 

 

 

Alpha-l6

 

 

 

 

 

 

Data converter

 

Figure 5.4 Circuit used in the dynamic response test.

 

 

49

Table 5.2 Results of the dynamic response test-without multiplexing.

 

frequency(Hz) minimum(V) maximum(V) average(V)
0 -5.000 4.997 0.002
1K -S.000 4.997 0.002
10K —5.000 4.997 0.002
40K -5.000 4.997 0.002
50K -5.000 4.997 0.002
60K -4.978 4.997 0.002
70K -4.924 4.997 0.007
80K -4.909 4.995 0.007
90K -4.885 4.992 0.009
100K -4.836 4.963 0.009

Table 5.3 Results of the dynamic response

test-with multiplexing.

 

frequency(Hz) minimum(V) maximum(V) average(V)
0 -5.000 4.997 0.002
1K —5.000 4.997 0.002
10K -5.000 4.997 0.002
30K -5.000 4.997 0.002
40K -4.975 4.997 0.004
50K -4.963 4.997 0.004
60K -4.909 4.975 0.007
70K —4.904 4.956 0.007
80K -4.839 4.941 0.009
90K —4.819 4.904 0.009

50

the data converter exceeds the design requirements. A software package
for the data converter is currently under development; it will enable an
operator to conpletely evaluate the static and dynamic capabilities Of
the data converter. Some of the important features of this diagnostic

package are described in the next Chapter.

CHAPTER VI SUMMARY

An adaptive programmable measurement system has been proposed
for the purpose of monitoring and managing pest-crop ecosystems. One
component in this facility is the data converter. The purpose Of the
research reported here was to specify, design, construct, and evaluate
the data converter.

After carefully considering the overall programmable measure-
ment system requirements, the prototype data converter was designed,
constructed, and its performance tested. These performance tests demon-
strated that the data converter's control logic functioned as designed
and that its accuracy was better than 0.1% Of full-scale. An example
demonstrating the basic dynamic properties of the data converter was

included in the experimental tests.

To further evaluate the dynamic response and to facilitate the
maintainance of the data converter, a software diagnostic package is being
developed. This package will be Operator interactive--the desired tests
may be individually selected and executed. Static performance will be
evaluated in much the same manner as previously described in Chapter V.
The dynamic performance, however, will involve finding the time constants
and delays associated with converting a signal with a large time rate of
change. This may be accomplished by synchronizing (interrupting) the
minicomputer with a -5 V to +5 V ramp, and sampling it, on the order of,
50 times a period. By decreasing the period of this ramp signal these
time constants and delays will become measurable. The dynamic perfor-
mance tests described above will be included, along with others, in the

software diagnostic package.
51

52

In retrospect several design changes might be made to suit a
particular application. To reduce the cost of parts (see Appendix E)
the DAS-l6 ADC system could be eliminated, and separate ADC and sample-
and-hold modules could be substituted. The full capabilities the DAS-l6
system were not utilized in this design, nor could they be used in any
application requiring greater than 16 channels Of multiplexing. For this
reason a saving of $300, or 15% of the total cost of parts, would be
assured by implementing this substitution.

Additional cost-savings may be realized by deleting the manual
mode. The Gating scheme and the complete Switch Register circuit would
not be necessary, and about $100 could be shaved off the parts list.

A final recommendation to improve subsequent data converters in-
volves a third mode of operation. This mode eliminates the need to
execute a convert instruction for each conversion. Once the limits are
established in the MAG, a convert instruction is issued. The data con-
verter then provides its own CONVERT pulse (and all future pulses) for
each conversion.: When the upper limit is reached the MAG presets and
a second interrupt is issued which signifies an end-Of-block. By using
an AUTO I/O instruction and two vectored interrupts, one for each data
word and one for an end-of-block (or ECHO), this new mode could easily
and efficiently be programmed. Since the ADC would essentially be
"free-running" from lower to upper channel (once started), converted data
words would be available and read into the minicomputer every 15 micro-
seconds. Using this new mode of operation the data converter's sampling

rate would be increased by nearly a factor of 10.

‘ 1". Illx
\ \ Ill)|l III). 1 \llu'l' I] i .

 

 

REFERENCES

.ll ‘ , , I \‘l‘lll‘ 1 ‘ll’ \llll!

 

 

 

l)

2)

3)

4)

5)

6)

7)

8)

9)

10)

ll)

12)

REFERENCES

Dean L. Haynes, Richard K. Brandenburg, and P. David Fisher,
"Environmental Monitoring Network for Pest Management Systems",
Environmental Entomolpgy, Vol. 2, no. 5 (October 1973), 889.

 

Ibid., 895.

Analog-Digital Conversion Handbook, prepared by Analog Devices,
Inc. (1972), p. II-l64.

 

Alpha l6 & Naked Mini 16 Computer Reference Manual, prepared by
Computer Automation, Inc. (1971), pp. 1-1 to 1-28.

Ernest O. Doebelin, Measurement Systems: Application and Design
(New York, 1966), pp. 38-203.

l6-Bit Input/Oupput Module, prepared by Computer Automation, Inc.
(1972), pp. l—l to 4-16.

 

Sigpetics, prepared by Signetics Corp. (1972), p. 2-1.

A/D-D/A Converters And Accessories, prepared by Datel Systems,
Inc. (1973) PP. 1—33.

 

Sigpetics, prepared by Signetics Corp. (1972), pp. 2-1 to 2-173.

RCA Solid State Databook Series (SSD-201A), prepared by RCA Corp.
(1972), p. 170.

 

Voltmeter Model 201 Instruction Manual, prepared by Wavetek, Inc.
(1970), pp. 30-32.

 

Applications Handbook For Timing And Adjustment Of Analog-To-Digé
ital And Digital-To-Analog Converter Products, prepared by Datel
Systems, Inc. (1973), pp. 1-29.

 

53

1.] ‘lll
\(Jlllj‘lll ‘III

 

 

APPENDICES

APPENDIX A

GLOSSARY

 

.gl nfllllll [III‘III‘|[llIII|.I fl'lll‘llulll‘ I‘..l’.‘llulll| I'll I'll. I’ll

 

APPENDIX A
Glossary
Note- Definitions are from "IEEE Standard Dictionary of Electrical and

Electronics Terms", Std 100-1972.

asynchronous computer- A computer in which each event or the

 

performance of each Operation starts as a result of a signal generated
by the completion of the previous event or Operation, or by the avail—
ability of the parts of the computer required for the next event or
operation.

23E? A binary digit.

buffer- A storage device used to compensate for a difference
in the rate Of flow of information or time of occurance of events when
transmitting information from one device to another.

ppgf One or more conductors used for transmitting signals or
power from one or more sources to one or more destinations.

central processing unit- The unit Of a computing system that
includes the circuits controlling the interpretation and execution
of instructions.

conditional jump- To cause, or an instruction which causes, the

 

proper one of two (or more) addresses to be used in obtaining the next
instruction, depending upon some property of one or more numerical
expressions or other conditions.

decode- To produce a single output signal from each combination
of a group of input signals.

diagnostic routine- A routine designed to locate either a

 

54

55

malfunction in the computer or a peripheral device.

half duplex bus- A bus arranged to permit signal flow in either

 

direction but not in both directions simultaneously.

hardware- Physical entities such as computers, circuits, tape
readers, et cetera.

interrupt- To stop a process in such a way that it can be resumed.

interface- A shared boundary.

EEEET A pattern of characters that is used to control the reten-
tion or elimination of portions of another pattern of characters.

pgripheral device- A mechanical or an electric contrivance to
serve a useful purpose and is outside the computer.

real time- Pertaining to the actual time during which a physical
process transpires.

register- A device capable of retaining information, often that
contained in a small subset (for example, one word), of the aggregate
information in a digital computer.

routine- A set of instructions arranged in proper sequence to
cause a computer to perform a desired operation.

simplex bus- A bus arranged to permit signal flow in one direction
only.

software- Computer programs, routines, programming languages
and systems.

system- An integrated whole even though composed Of diverse,
interacting, specialized structures and subjunctions.

transfer- To transmit, or copy, information from one device to

another.

APPENDIX B

16-BIT I/O MODULE

SIGNAL DEFINITIONS

APPENDIX B
l6-bit I/O module signal definitions
Note- Definitions are from "l6-Bit Input/Output Module", prepared
by Computer Automation, Inc. (1972), pp. A-4 to A-8.
A9: Input buffer regenerated clock pulse.
BCOO-BClS- Output data lines to peripheral device. These lines

can be either positive or negative polarity. Polarity is defined by

use of the OPOL signal.

 

E8;E256- Interrupt address select lines. These lines are user
defined and ground-true.

ESO-ES7— External sense lines. These lines are positive-true.

EST: External strobe. Generated by the peripheral to strobe
input data into the input buffer register.

'EXO;E§7; External control lines. These lines produce an 800
nanosecond ground-true pulse when activated to control user defined
functions in the peripheral device.

I227 Input buffer full. Conveys input register status to the
computer and the peripheral device. A low output indicates that the
computer has accepted the last input data transfer. A high ouput indi-
cates that input data is currently stored in the input register but the
computer has not accepted it.

ID00-ID15- Input data lines from a peripheral device. These
lines can be either positive or negative polarity. Polarity is defined

by use of the IPOL signal.

56

57

£229: Input register polarity control. If the data lines are
ground-true logic, IPOL is strapped to ground. If positive logic is
used, IPOL is left Open.

ITRAN: Input transparent. Causes the input register to be trans-
parent, permitting peripheral input data to be applied directly to the
data bus.

92E: Output buffer empty. Used to convey ouput buffer register
status to the computer and peripheral device. A low ouput indicates
that new output data is in the ouput register and that a transfer is
imminent. A high ouput indicates that the output data from the last
transfer has been received by the peripheral device.

923g: Output buffer ready strobe. Generated by the peripheral
device to acknowledge receipt of output data. Causes the output empty
signal OBE to go high.

22927 Output register polarity control. Grounding this line
causes the BCOO-BClS outputs to be in inverted logic form (ground-true).
Leaving the line open causes the output data to be noninverted (pos-
itive-true).

FED-P84; Address select lines. These five lines determine the
16-Bit I/O Module user defined device address. These lines are ground-
true signals.

BEELET Interrupt request number 1

RNT_27 Interrupt request number 2.

55927 Interrupt request polarity control. A ground-true RPOL
signal causes a ground-true external interrupt to be recognized. Like-
wise, a positive-true polarity signal causes a positive-true external

interrupt to be recognized.

58
§EQET Peripheral strobe polarity control. A ground-true polarity
signal causes the EST and OBRS signals to be recognized if they are ground-
true. Likewise, a high polarity signal causes the EST and OBRS signals
to be recognized if they are positive-true.
STE: Output data strobe. Goes high for approximately 200

nanoseconds.

. ..3o0 .5... :-

APPENDIX C

Data converter photographs

a

i

b???

““5“
.u ,_
1' ' '1

I," .
’1
5 3.

\
If

‘1..."‘1 in 1 _ I

. igfii‘a,ta.-h~

. _ ..1 'V " :3- u o ‘
(Kg5 ,k,.-

' wit. 1? ~~- . ...

r- “; 1‘... rhythh 'r‘shl'ia

 

59

ter.

minicompu

Figure C.l Data converter, teletype, and Alpha-16

60

.uuommcwuu ommu ouummmmo Hmso pom OHlman< m.sOHumEOuo¢ Hmuomfiou N.O OHDOHE

 

 

61

'9

2'-

       

‘ ... ‘.‘ , . . .. .. .{d i;
' u ' . h . ' .-‘~ '.
; a“: A? M . ..
v ‘ '. ' - .. ," , L, .

 

--‘;: '_ Iii-3;...

,J l‘

\51

l

 
   

’5.
. y.
4.9V“ 7 '5, T.- -

“’J'Péa. ‘ ...;3'0 v'J. .

Figure C.3 Data converter front view.

“F.

‘

‘,"‘ o .4",
.' MY ‘ 6w. .-;

I
h

'v"’

.

"a-l

‘1‘.

.1"? ... . ?.
17'5".“5’3155 .

62

 

_I

 

Figure C.4 Data converter rear view.

APPENDIX D

DATA CONVERTER

DYNAMIC RESPONSE PROGRAM

XAO
PAGE
000!
0002
0003
0004
0005
0006
0007
0003
0009
0030
001!
0012
0013
0014
0015
'0016
0017
0013
0019
0020
0021
0022
0023
0024
0025
0026
0027
0023
0029
0030
003‘
0032
0033
0034
0035
0036
0037
0033
0039
0040
0041
0042
0043
0044
0045
0046
0047
0043
0049
0050
0051
0052
0053
0054

0000
0000
000!
0002
0003
0004
0005
0006
0007
0008
0009
000A
0008
0000
ICED
0008
000?
0010
III!
OOI2
0013
0014
0015
0016
0017

0918
0019
001A
0013

0092
0092
0093
0094

9912
once
0001

0000
3006

DID?
0123
0162
038?
0600
0260
0900
0700
0800
FDIO
3007

CODA
arr!
D8I9
r213
OIED

F893
0800
5096

a APPENDIX D
0
j
s DATA CONVERTER DNNAMIC RESPONSE PROGRAM
0
t
atteststttttstattattmttttttttssatststsaa
t a
a DATA CONVERTER DIAGNOSTIC t
s WRITTEN BY GARY D BAUER a
s 4/I8/I974 a
t a
*ttttt#*****#it*#****ttt*ttttttttttttttt
BIT ECU :12
RTC ECU 8
TTY EQU 7
EXTR CRID:
EXTR MPYS:
a
ABS O
LINE RES I CURRENT CHANNEL NUMBER
COUNT RES 1
TTYURD RES I TTY VORD INTERRUPT
TTYUCT DATA 0 TTY WORD COUNT
TTYBAD RES I TTY IYTE ADDRESS
NEUAD DATA *LIST-I MESSAGE ROUTINE ADDRESS
AP RES I ADDRESS POINTER TO PROCESSING
LIST DATA MAXMES MESSAGE ROUTINES
DATA AVCMES
DATA DONE.
BUFAD DATA BUF-I
MAXMAX DATA MAX
MINMIN DATA MIN
TOTAD DATA TOT
AVCAAD DATA AVOA
AVGXAD DATA AVCX
M768 DATA -768
ZERO DATA 80007
COUNTS RES I
BAD RES I
COUNT2 RES I
TEN DATA IO
LNUM RES I
FFF DATA :FFF
.
IMS RTCONT INCREMENT
RTCONT RES I TIME KEEPER
JST 135+! SYNC INTERRUPT
DATA TIMERR ‘
*
A85 :92
JST AIN WORD INTERRUPT LOCATION
AIN ENT
AIN BIToG TO READ SIGNAL

63

PAGE
9955
9956
9957
9958
9959
9969
9961

9962
9963
9964
9965
9966
9967
9968
9969
9979
9971

9972
9973
9974
9975
9976
9977
9978
9979
9989
9981

9982
9983
9984
9985
9986
9987
9988
9989
9999
9991

9992
9993
9994
9995
9996
9997
9998
9999
9199
9191
9192
9193
9194
9195
9196
9197
9198

9992
9995
9996
9997
9998
9999
9994
9999
9990
999D
999E
999F
9949
9941
9942
9943
9944

9199
9199
9191
9192
9193
9194
9195
9196
9197
9198
9199
919A
9198
919C
919D

919E
919F
9119
9111
9112
9113
9114
9115
9116
9117
9118
9119
911A
9118
911C
911D
911E
911F
9129
9121
9122

F998
4993
9499
F193
91F2
94CD
9499
9443
9449

2719
9999
5F5F
9899

9C99
4944
4999
9119
9893
F463
FFF8
9491
4892
F294
FASE
FFFA
9488
9899

9119
9899
B995
9896
F456
FFFD
9499
4938
5839
CIAE
F222
CIAD
F29E
C389
9939
29CF
D942
F291
F612
8899
8899

BITCNT RES
BITAD RES

EXIT
CHAD

AVGAD
MAXAD
MESAD
MINAD

SIGN

TTHOU

NINE
MULT
COR
*

START

READ

JST
SEL
EIN
RTN
DATA
BAC
BAC
BAC
BAC
RES
DATA
DATA
DATA
DATA

ABS
DIN
SEL
SEL
ZAR
STA
JST
DATA
BAC
SSN
JMP
JST
DATA
BAC
HLT

ZAR
STA
LDA
STA
JST
DATA
BAC
SEL
RDK
CXI
JMP
CXI
JMP
SXI
TXA
JAM
CMS
JMP
JMP
ADD
ADD

64

*CRAD
811,3

AIN
CHNDNE
MEND-I
MAVG‘I
MES+S
MNMES-I

24415
3809

:I98

RTC04
31750

TTYVCT
TTYMES
-8
SMES-1
9:2

GO
TTYMES
'6
RTMES-I

LINE
NEUAD

TTYMES
-3
READY-I
TTY.O
TTY.I

O O
LDONE
0-0
rx-a
:80

GO
NINE
5+2
GO
LINE
LINE

WORD COUNTER
VORD ADDRESS

END OF BLOCK

DO CONVERT

ENABLE INTERRUPTS
RETURN

MESSAGE ADDRESS
MESSAGE ADDRESS
TO PUT IN CHANNEL NUMBER
MESSAGE ADDRESS

SIGNAL CONVERSION VALUE
CORRECTIVE AMOUNT

DISABLE INTERRUPTS
CLEAR RTC

CLEAR 16¢BIT

TO

CLEAR TTY

PRINT MESSAGE
MESSAGE LENGTH
MESSAGE ADDRESS
CHECK FOR RTC
CONTINUE

PRINT MESSAGE
MESSAGE LENGTH
MESSAGE ADDRESS
UAIT'FOR CORRECTION

CLEAR A

AND LINE NUMBER
TO RESET

ADDRESS POINTER
PRINT MESSAGE
MESSAGE LENGTH
MESSAGE ADDRESS
SELECT AUTO ECHO
READ INPUT

SEE IF o

YES IT IS

SEE IF '-'

YES IT IS
CONVERT T0 BINARY DIGIT
PUT IN A

ERROR

COMPARE UITH 9
OH IF <

ERROR IF > 9

PAGE
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162

0003
0123
0124
0125
0126
0127
0128

0129
012A
0123
012C
0120
012E
012F
0130
0131

0132
0133
0134
0135
0136
0137
0138

0139

013A
0138
013C
013D
013E
013F
0140
0141

0142
0143
0144
0145
0146
0147
0148
0149
014A
014B
014C
014D
014E
014F
0150
0151

0152
0153
0154
0155
0156

8800
1352
8800
9800
9801
F612
0110
9801
5B39
CIAE
F20D
C380
0030
20E2
DOA2
F201
F625
8801
8801
8801
1352
8801
9801
F60F
B001
D000
F62F
0000
1357
A000
00D0
9800
0110
EOA4
00A8
9DOA
3842
B233
CSFF
9DOA
0128
3842
072A
9812
B000
4040
4042
FA02
0A00
F600

0800
4090

LDONE

STRTCH

EMA
LLA
ADD
STA
STA
JMP

ZAR
STA
RDX
CXI

JMP
SXI

TXA
JAM
CNS
JMP
JMP
ADD
ADD
EMA
LLA
ADD
STA
JMP
LDA
CNS
JMP
NOP
LLA
IOR
DAR
STA
ZAR
LDX
DXR
STA
JXN
LDA
LXM
STA
IXR
JXN
LAM
STA
LDA
SEL
SEL
JST
EIN
JMP

ENT
SEL

65

LINE

LINE
LINE
COUNT
READ

COUNT
TTYaI

LDONE
:80

GO
NINE
5+2
GO
COUNT
COUNT
COUNT

COUNT
COUNT
PX
COUNT
LINE
GO

8
LINE

LINE
COR

OtBUFAD
5-2
TTYAOB
255
0*BUFAD

5‘2

42
COUNT3
LINE
RTC)“
HTCaZ
STRTCH

81710

* BY 8 .
ENDS UP WITH ICLINE + A
STORE NEW LINE TOTAL

CONTINUE READING

CLEAR A

GET BYTE

SEE IF '.'

YES IT IS

CONVERT TO BINARY
PUT IN A

ERROR

COMPARE WITH 9

OK IF <

ERROR IF > 9

# BY 8
ENDS UP WITH IDCOUNT + A
CONTINUE READING

GET UPPER CNN

COMPARE WITH LOWER CRN
ERROR

SHIFT

CHANNEL WORD FOR CONVERSION
ADJUST TO CORRECT CHANNEL
STORE CHANNEL SELECTION
CLEAR A

GET TABLE SIZE

DECRENENT INDEX

CLEAR TABLE

LOOP UNTIL DOVE

TO RESET MIN

RESET INDEX

INCRNENT INDEX
LOOP UNTIL DONE
GET RANGE LIMIT
AND STORE IT

GET CHANNEL RAN GE
ENABLE RTC

ENABLE SYNC
SELECT CHANNELS
ENABLE INTERRUPTS
LOOP HERE

.16-BIT CHANNEL SELECTOR
CLEAR INTERFACE

PAGE
0163
0164
0165
0166
0167
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180
0181
0182
0183
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215
0216

0004
0157
0158
0159
015A
0150
015C
0150
015E
015F
0160
0161

0162
0163
0164
0165
0166
0167
0168
0169
016A
0160
016C
0160
016E
016F
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
017A
0170
017C
017D
0180
0181
0182
0183
0184
0185
0186
0187
0188

0189
018A
one:

6C92
4091
C705
9819
4092
BO0A
9896
B010
9895
4093
F70C

FA06
FFC4
0490
0814
0812
F221
F65A

0800
4090
4044
8003
3141
B200
9802
E607
B400
9AOA
0150
9803
B401
9A07
0150
9804
4938
F601
403C
6439

4030
0A00
B003
3141
4938
F601
403C
0C00
F402

0103
9801
B005

DONE

TTYMES

TTYAOB

I

MINMES

OTA
SEL
LAM
STA
SEL
LDA
STA
LDA
STA
SEL
RTN

JST
DATA
BAC
IMS
IMS
JMP
JMP

ENT
SEL
SEL
LDA
JAN
LDA
STA
LDK
LDA
STA
IAR
STA
LDA
STA
IAR
STA
SEN
JMP
SEL
AOB
RES
SEL
EIN
LDA

SEN
JMP
SEL
DIN
JMP

LAM
STA
LDA

66

BITCZ
BITJI
5 ,
RTCONT
B‘le
BUFAD
BITAD
M768
BITCNT
BITaa
STHTCH

TTYMES
'60.
MES-1
COUNT2
COUNT3
MINMES
GO

BIT00
RTC54
TTYUCT
5-1
TTYAOB
TTYWRD
TTYMES
00
TTYAOB+I

TTYUCT
01
TTYAOB+2

TTYBAD
TTY03
5'1
TTYCA
TTYoI
3 .
TTYOS

TTYUCT
5'1 .
TTYJ3
5‘1
T7704

02
3

COUNT
NEUAD

SELECT CHANNELS

ENABLE UORD INTERRUPTS

TO RESET RTC

COUNTER

ENABLE IND OF BLOCK INTERRUPT
GET BUFFER ADDRESS

STORE FOR AUTO'I-O

GET '768 FOR 3 CHANNEL LOOPS

ISSUE CONVERT INSTRUCTION
RETURN

PRINT MESSAGE

MESSAGE LENGTH

MESSAGE ADDRESS

INCREMENT CHANNEL NUMBER
INCREMENT NUMBER OF CNN LEFT
CONTINUE UNTIL FINISHED
START AGAIN

PRINTS TTY MESSAGES

CLEAR INTERFACE

DISABLE RTC

GET BYTE COUNT

CHECK FOR NOT BUSY

GET TTY AUTO I-O INSTRUCTION
STORE IN INTERRUPT

GET RETURN ADDRESS

GET BYTE COUNT

AND STORE

PUT FOR INTERRUPT
GET MESSAGE ADDRESS
STORE

AND FOR INTERRUPT
SEE IF TTY BUSY
YES IT IS

CLEAR TTY

START OUTPUT

SELECT WORD INTERRUPT
ENABLE INTERRUPTS

GET BYTE COUNTER
LOOP UNITL DONE

SEE IF TTY BUSY

LOOP UNTIL NOT

CLEAR TTY

DISABLE INTERRUPTS
RETURN

LOOP COUNTER
STORE LOOP COUNTER
GET ADDRESS POINTER

PAGE
0217
0218
0219
8228
0221
8222
0223
8224
0225
8225
8227
8228
8229
8238
0231
8232
8233
8234
8235
0236
8237
8238
8239
8248
0241
8242
8243
8244
0245
8245
0247
8248
8249
8258
0251
8252
8253
8254
0255
0256
8257
8258
0259
8258
0261
8252
0263
8254
8255
8255
0267
8258
8259
8278

0005
018C
0180
018E
018F
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
019A
0190
019C
0190
019E
019F
01A0
01A1

01A2
01A3
01A4
01A5
01A6
01A7
01A8
01A9
01AA
01AE
01AC
01A0
01AE
01AF
01B0
0101
0182
0103
01B4
01B5
0186
01B?
0108
01B9
018A
01BB
01BC
01B0
010E
01BF
01C0

9806
B093
9813
E014
0128
0110
0F00
F900
0015
0E00
8822
9913
C701
6803
8813
9813
0801
F60C
0F00
E014
E50C
B09F

E8A0
9813
C704
9801
0E00
0110
1903
0020
F202
0000
8823
8822
0813
9913
0801
F60A
0F00
BOA0
0813
0813
C503
E801
90A4
C4AB
3082
C4A0
0310
0E00
E913
0F00
EOA3

DLOOP

FIN

MINLOP

NINA

STA
LDA
STA
LDX
IXR
ZAR
SUM
JST
DATA
SBM
ADDB
STAB
LAM
SIN
ADD
STA
INS
JMP
SUM
LDX
LDX
LDA

STX
STA

STA
SBM
ZAR
LRL
CMSB
JMP
NOP
ADDB
ADDB
INS
STAB
INS
JMP
SUM
LDA
INS
INS
LXN
STX
SUB
LXP
JAP
LXP
NAR
SBM
STXB
SUN
LDX

67

AP
NESAD
BAD
COUNT2

cnzoi
TEN

ZERO
#BAD
1

2

BAD
BAD
COUNT
DLOOP

COUNT2

0*MINMIN

MINAD

SIGN
BAD

A
COUNT

4 -
TEN+1
NINA

ZERO+1
ZERO
BAD
*BAD
COUNT
MINLOP

SIGN
BAD
BAD

3
COUNT
COR
0+0
5+8

+BAD

MULT

AND RESET POINTER
GET BAD ADDRESS

GET CHANNEL NWBER
INCREMENT TO NEXT CHANNEL
CLEAR A

SET WORD MODE

I10

SET BYTE NODE

+8B0

STORE BYTE IN MESSAGE
TO DECREMENT ADDRESS
INHIBIT STATUS

INCRENENT LOOP COUNTER
CONTINUE

SET VORD MODE

GET CHANNEL NUMBER

GET CHANNEL MINIMUM
GET BUFFER ADDRESS

SAVE SIGNAL
RESET BYTE ADDRESS

STORE BYTE COUNTER
SET BYTE MODE
CLEAR A

MOVE DIGIT INTO A
COMPARE UITH 10

OK

+7

+380

INCRENENT POINTER
STORE IN MESSAGE
INCRENENT COUNTER
KEEP GOING

SET WORD MODE

GET SIGNAL

INCREMENT BYTE POINTER

THE NUMBER OF DECINAL
DIGITS

CORRECT SIGNAL

SET TO THIS SIGN INITIALLY
SKIP IF VOLTAGE IS +
ELSE SET AS -

AND CONVERT TO ABS VAL
SET BYTE NODE

STORE SIGN

SET WORD MODE

GET MULTIPLIER

PAGE
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282
0283
0284
0285
0286
0287
0288
0289
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
0305
0306
0307
0308
0309
0310
0311
0312
0313
0314
0315
0316
0317
0318
0319
0320
0321
0322
0323
0324

0006
01C1
01C2
01C3
01C4
01C5
01C6
01C7
0108
01C9
01CA
01CB
01CC
01C0
010E
01CF
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
010A
0100
01 DC
0100
010E

010F
01E0
01E1
01E2
01E3
01E4
01E5
01E6
01E?
01E8
01E9
01EA
01EB
01BC

01E0
01EB
01EF
01F0
01F1

01F2

F900
F900
00A1
C606
8813
9813
B013
0000
9813
0110
F900
0015
0E00
8822
9913
0F00
0801
F600
C702
8813
9813
0110
F900
0015
0E00
8822
9913
0F00
0806
F106

B090
E014
E50B
F640
B014
0048
8800
9A03
BSOE
ESOF
F900

009C
F64A

0800
FE85
FFF4
046B
F6E3

0800

MINB

MAXMES

AVGMES

TOTAL

TIMERR

*

JST
JST
DATA
LAP
ADD
STA
LDA
DAR
STA
ZAR
JST
DATA
SBM
ADDB
STAB
SUM
INS
JMP
LAM
ADD
STA
ZAR
JST
DATA
SBM
ADDB
STAB
SUN
INS
JMP

LDA
LDX
LDX
JMP

LDA
TAX
ADD
STA
LDA
LDX
JST
RES
LDA
JMP

ENT
JST
DATA
BAC
JMP

CHNDNE ENT

68

MPY51
CRI DI
TTHOU
6

BAD
BAD
BAD

BAD

CRID:
TEN

ZERO
*BAD

COUNT
MINB
2

BAD
BAD

cm 83
TEN

ZERO
*BAD

AP
*AP

MAXAD
COUNT2
O+MAXMAX
FIN

COUNT2

TOTAD
TOTAL
O+AVGAAD
O+AVGXAD
CRID:

I

AVGAD
FIN

TTYMES
'12
BMES-I
GO

Atx
l10000

TO ADJUST ADDRESS
CALCULATE NEU

ADDRESS

GET BUFFER ADDRESS
DECREMENT POINTER
STORE.NEV BUFFER POINTER
CLEAR A

/10

SET BYTE MODE

+300

STORE REMAINDER IN MESSAGE
SET WORD MODE

INCREMENT LOOP COUNTER

TO RESET
ADDRESS POINTER
CLEAR A

l10

SET BYTE MODE

+800

STORE IN BUFFER

SET VORD MODE

INCREMENT ADDRESS POINTER
GO TO ROUTINE

GET MESSAGE ADDRESS
GET CURRENT CHANNEL
GET CHANNEL MAXIMUM
FILL BUFFER

CURRENT CHANNEL
AS INDEX
ADDRESS OF TOTAL

GET
GET
GET

TOP TO AVG

GET BOTTOM OF AVG
GET AVG

NUMBER OF ELEMENTS
GET BUFFER ADDRESS
FILL MESSAGE

GET

PRINT INTERRUPT MESSAGE
PRINT MESSAGE

MESSAGE LENGTH

MESSAGE ADDRESS

RETURN

CHANNEL COMPLETION ROUTINE

PAGE
0325
0326
0327
0328
0329
0330
0331
0332
0333
0334
0335
0336
0337
0338
0339
0340
0341
0342
0343
0344
0345
0346
0347
0348
0349
0350
0351
0352
0353
0354
0355
0356
0357
0358
0359
0360
0361
0362
0363
0364
0365
0366
0367
0368

0369-

0370
0371
0372
0373
0374
0375
0376
0377
0378

0007
01F3
01F4
01F5
01F6
01F7
01F8
01F9
01FA
01FE
01FC
01FD
01FE
01FF
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
020A
0208
020C
0200
020E
020F
0210
0211
0212
0213
0214
0215
0216
0217
0218
0219
021A
021B
021C
0210
021E
021F
0220
0221
0222
0223
0224
0225
0226
0227
0228

B010
9814
EO0A
0E00
B001

9820
1328
6802
E8A0
6804
EOA0
C202
E8A0
B400
1303
A820
802E
2105
0F00
FE9D
FFEC
0477
F6FB
6803
13A8

B400
E020
0F00
1353
1303
050C
900C
0000
0500
F201

900B
1200
800F
3203
1350
1300
000E
9DOF
0E00
0130
0000
0000
F202
F613
3001

9820
0814
F62B
0F00

CLOOP

CBAD

CGOOD

NOV

OUT

LDA
STA
LDK
SBN
LDAB
STAB
LLX
SIN
STX
SIN
LDX
AXI
STX
LDAB
LRA
XORB
ANDB
JAZ
SUM
JST
DATA
BAC
JMP
SIN
LRX
LDA
LDXB
SUM
LLA
LRA
CNS
STA
NOP
CNS
JMP
STA
ROV
ADD
JOR
LLA
LRA
INS
STA
SBN
IXA
IMS
CMSB
JMP
JMP
LDAB
STAB
IMS
JMP
SUN

69

M768
COUNT2
BUFAD

LINE+1
LNUM+1
1

1

SIGN

3

SIGN

2

SIGN
00

a
LNUM+1
FFF
CGOOD

TTYMES
-20
CMES-I
GO

2

I

O0
LNUM+1

4
4
O+MINMIN
C+MINMIN

8+MAXMAX
8+2
0*MAXMAX

0*AVGXAD
NOV

1

I
0+AVGAAD
OtAVGXAD

O+TOTAD
LINE
OUT
CBAD
LINE+I
LNUM+1
COUNT2
CLOOP

GET -768

STORE UORD COUNTER

GET UORD INDEX

SET BYTE MODE

GET LOUER LIMIT

INITIALIZE CHECKER

CONVERT INDEX TO BYTE ADDRESS
INHIBIT STATUS

STORE INDEX

INHIBIT STATUS

GET INDEX

INCREMENT TO PROPER BYTE
STORE NEU INDEX

GET UPPER BYTE

SHIFT DOWN TO CHANNEL MOD
TEST WITH PROPER RESULT
MASK OFF LOVER 4 BITS
CHANNELS MATCH

SET UORD MODE

PRINT MESSAGE

NESSAGE LENGTH

MESSAGE ADDDRESS

RETURN

INHIBIT STATUS

CONVERT BYTE TO UORD ADDRESS
GET INPUT VORD

GET CURRENT CHANNEL NUMBER
SET VORD MODE

SHIFT OFF CHANNEL NOD
RESTORE TO POSITION
COMPARE VITH CHANNEL MINIMUM
REPLACE IF LESS

COMPARE UITH CHANNEL MAXIMUM
SKIP REPLACING

REPLACE IF GREATER

RESET OVERFLOU

ADD TO AVG

SKIP IF NO OVERFLOV

SHIFT OFF SIGN BIT
RESTORE TO POSITION
INCREMENT SIGNICANT PART
STORE LEAST SIGNICANT PART
SET BYTE MODE

INCREMENT TO NEXT CHANNEL
INCREMENT ELEMENT COUNTER
COMPARE UITH LIMIT

OK

ERROR

RESET TO 1$T CHANNEL
STORE NEXT CHANNEL

INNER LOOP COUNTER

KEEP GOING

SET UORD MODE

PAGE
0379
0380
0381
0382
0383
0384
0385
0386
0387
0388
0389
0390
0391
0392

0393

8394

0395
0396

0397
0398
0399
0400

0401
0402

0403
0404

0008
0229
022A
0220
022C
0220
022E
022F
0230
0231
0232
0233
0234
0235
0236
0237
0238
0239
023A
0238
023C
0230
023E
023F
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
024A
0240
024C
0240
024E
024F
0250
0251
0252
0253
0254
0255
0257
0258
0259
025A
0258
0250
0250
025E
0260

B000
FEDS
0812
F099
4090
0E00
E001
0030
9000
0F00
9812
E814
F6AC
CECF
AOC9
CED4
C502
0205
D004
C3C8
CICE
CECS
CCAO
CEDS
CDC2
C502
AOC5
D202
CF02
CECF
A002
D4C3
808A
CGC8
CED3
C3CE
808A
BE00
808A
AOA0
AOA0
AOCD
C9CE
BDAO

AOA0
AOAE
AOA0
AOA0
AOCD
C108
BDAO

AOA0

BMES

CMES

RTMES

SMES

READY

MES

MNMES

MAVG

LDA
JST
INS
JMP
SEL
SBN
LDXB
TXA
SUBB
SUM
STA
STX
JMP
TEXT

TEXT

TEXT

DATA
TEXT

DATA
DATA
DATA
TEXT

RES
TEXT

RES
TEXT

70

LINE GET CHANNEL SELECT
STRTCH SELECT CHANNELS
COUNT3 INCREMENT MASTER COUNTER
EXIT RETURN
BITo0 STOP READINGS
- SET BYTE MODE

LINE+1 GET 1$T CHANNEL NUMBER

PUT IN A
LINE - LAST CHANNEL

SET VORD MODE
COUNT3 NUMBER OF CHANNELS TO LIST
COUNT2 IST CHANNEL TO LIST
MINMES GO 00 MINIMUM
'NO INTERRUPT'

fCNANNEL NUMBER ERROR?

'No RTC'

:8D8A CRLF
'CHNSCNf

3808A CRLF
IBE00 '>'
8808A CRLF

' MIN- '

2

' o "A," '
2

' 0 AVG. .

PAGE

0405
0406

0407
0408
0409
0410
0411
0412
0413
0414
0415
0416
0000

0009
0261
0262
0263
0264
0265
0266
0267
0269
026A
026B
026C

0200
02C0
03C0
06C0
07C0
08C0
0900
0260

ERRORS

AOAE
AOA0
AOA0
AOC1
D6C7
BDAO

AOA0
AOAE
AOA0
AOA0
026D

MEND

MIN
BUF
MAX
AVGA
AVGX
TOT

RES

71

2

TEXT '

EOU
ORG
RES
RES
RES
RES
RES
RES
ORG
END

3260
256
768
256
256
256
256
END

START

SAVE ORIGIN

SET ORIGIN FOR STORAGE

RESET ORIGIN

APPENDIX E

DATA CONVERTER PARTS LIST

APPENDIX E

Data converter parts list

 

Item Quantity Description Unit cost ($) Total cost ($)
1. 15 7400 Quad 2-input Nand
gates 0.55 8.25
2. 5 7475 Quad latches 1.40 7.00
3. 3 74193 Binary counter 3.90 11.70
4. 3 7485 4-bit magnitude
cOmparator 7.00 21.00
5. 5 74121 Monostable multi-
vibrator 1.10 5.50
6. 6 7404 Hex inverter 0.70 4.20
7. 4 MM8 multiplexer 99.00 396.00
8. 1 DAS-l6 ADC system 695.00 695.00
9. 1 DPS-1 5V@3A power
supply 32.06 32.06
10. 1 BPM-15/300 115v@3oo mA
power supply 89.00 89.00
11. 1 MS-7 BPM socket 3.50 3.50
12. 40 10k ohm resistors 0.10 4.00
13. 20 220 ohm resistors 0.10 2.00
14. 20 330 ohm resistors 0.10 2.00
15. 10 2.2m ohm resistors 0.10 1.00
16. 10 150 ohm resistors 0.10 1.00
17. 10 1k ohm resistors 0.10 1.00
18. 10 10k film resistors 1.34 13.40
19. 50 0.01 mF capacitors 10WV 0.15 7.50
20. 20 TIL 210 LED 1.40 28.00
21. 32 BNC connectors 0.76 24.32
22. 3 3-termina1 connectors 0.55 1.65
23. 3 4-termina1 connectors 1.05 3.15
24. 1 AC line chord 1.50 1.50
25. 1 Pilot light 1.00 1.00
26. 1 Fuse holder/fuse 2.25 2.25
27. 1 Can of paint 1.75 1.75
28. l Bud relay rack (table) 18.00 18.00
29. 2 AMP DIP switches 3.73 7.46
30. 16 JBT SPST toggle switches 1.60 25.60
31. 33 JBT DPDT toggle switches 1.58 52.14
32. 2 JBT SPST momentary
toggle switches 1.90 3.80

72

73

 

Item Quantity Description Unit cost ($) Total cost ($)
33. 2 Bannana jacks-green 0.95 1.90
34. 2 Bannana jacks-white 0.95 1.90
35. 2 Bannana jacks-black 0.95 1.90
36. 2 Bannana jacks-red 0.95 1.90
37. 2 RCA CA3081 NPN transis- ' '

tor array 6.24 12.48
38. 1 Beldon 8700 28 AWG ‘

coaxial cable-50 feet 14.40 14.40
39. l Wirewrap wire-30 AWG 59.25 59.25
40. l Wirewrap wire-24 AWG 25.34 25.34
41. 1 Bag of 100 wirewrap

stakes 26.85 26.85
42. 10 Printed circuit card

connectors 3.90 39.00
43. 1 Bag of wirewrap sockets 12.30 12.30
44. 1 Universal card cage

assembly 31.44 31.44
45. l Bag of card guides 6.75 6.75
46. 10 Universal cards 6.18 61.80
47. 2 Boxes of 2-56 machine

screws 2.00 4.00
48. 2 Boxes of 2-56 nuts 2.00 4.00
49. 2 Boxes of #2 internal

tooth lockwashers 2.00 4.00
50. 1 100 foot roll of twisted-

pairs ribbon cable 48.00 43.00
51. 50 Augat 16-pin wirewrap

DIP sockets 0.89 44.50
52. 30 Augat l4-pin wirewrap

DIP sockets 0.79 23.70
53. 1 8"xl9" vector board 11.00 11.00
54. 1 Bag of 100 clear cable

ties 1.10 1.10
55. 1 Misc. aluminum & machin-

ing 50.00 50.00

TOTAL COST OF ALL PARTS- $1976.24