BUCK/BOOST CURRENT-SOURCE-INVERTER TOPOLOGIES, MODULATION AND APPLICATIONS IN HEV/EV MOTOR DRIVE by Qin Lei A DISSERTATION Submitted to Michigan State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Electrical Engineering 2012 ABSTRACT BUCK/BOOST CURRENT-SOURCE-INVERTER TOPOLOGIES, MODULATION AND APPLICATIONS IN HEV/EV MOTOR DRIVE By Qin Lei To provide higher boost ratio in motor drive or PV application, a new family of switched-coupled-inductor inverters has been proposed in this work, with voltage buck-boost function. The voltage-fed switched-coupled-inductor inverter has higher boost ratio and lower active device voltage stress than Z-source inverter at the same voltage gain, and has wider voltage buck/boost range than conventional boost-converter inverter. The current-fed switched-coupled-inductor inverter is a capacitor-less solution among the buck-boost inverters, which reduces the system size significantly. Compared to traditional boost-converter-inverter, it has less switch count, and less active device current stress. To achieve higher efficiency with a single-stage buck-boost inverter for HEV/EV motor drive application, a current-fed quasi-Z-source inverter topology has been selected and a 24kW prototype has been built in the lab. A zero vector placement technique in SVPWM has been proposed for this inverter to obtain lowest switching loss, lowest current ripple, lowest output harmonics and lowest voltage spike on the device in both constant torque and constant power operation regions, in order to achieve higher efficiency, higher power density and lower cost. A 24kW current-fed quasi-Z-source inverter has been built in the lab and tested. The full power rating efficiency reaches 97.6%, and peak efficiency reaches 98.2%, both of which have a 3%-4% improvement on traditional two stage configuration. The power density is 15.3KW/L, which also has 30% improvement on the commercial unit in HEV. To achieve higher switching loss reduction, a Space-Vector-Pulse-Width-Amplitude Modulation (SVPWAM) method has been proposed for buck-boost current source inverter. By using this method, the switching loss is reduced by 60%, and the power density is increased by a factor of 2 to 3, with a less output harmonic distortion than normal SVPWM method. A 1 kW boost-converter-inverter prototype has been built and tested using this method. The overall system efficiency at full power rating reaches 96.7% and the whole system power density reaches 2.3 kW/L and 0.5 kW/lb, all of which are remarkable at this power rating. As a result, the proposed SVPWAM can make the buck-boost inverter suitable for applications that require high efficiency, high power density, high temperature, and low cost, such as EV motor drive or engine starter/alternator. To implement buck-boost function on direct matrix converter, four control methods including simple maximum boost, maximum boost, maximum constant boost control and hybrid minimum stress control have been proposed for the newly proposed direct Z-source matrix converter, and verified with simulation/experiments. Two new discontinuous operation modes have been proposed for current-fed quasi-Z-source inverter topology. Simulation and experiment results are given to verify the theoretical analysis. A transient state-space model has been built for current-fed quasi-Z-source inverter to demonstrate its fast transient response in motoring and regenerating transition. The analytical, simulated and experimental results all show that the inverter only needs several switching cycle to complete the transition, which makes it suitable for HEV/EV motor drive application. Dedicated to: My parents, Chuping Lei and Airong Wang My husband Junjun Xin, And my brother Qiwei iv ACKNOWLEDGEMENTS I would like to thank all people who have helped and inspired me during my graduate study. I especially want to thank my advisor, Dr. Fang Z. Peng, for his guidance during my research and study. His perpetual energy and enthusiasm in research had motivated all his advisees, including me. His profound understanding and wide knowledge in power electronics field impressed me and made my research life become smooth and rewarding. I am also very grateful for my committee members, Dr. Bingsen Wang, Dr. Mitra Joydeep and Dr. Guoming Zhu for their suggestions and help. All my lab buddies at the Power Electronics and Motor Drive Laboratory (PEMD) made it a convivial place to work. In particular, I would like to thank Dr. Shuitao Yang for his helpful guidance in the micro-grid project and current-fed quasi-Z-source inverter project. It is my great pleasure and fortune to work with him in the second year of graduate study. His intelligence, patient and tireless teaching guided me into and love this promising field. I also want to give my special thank to Dr Julio Cesar Rosas Caro, who is my first collaborator in this lab. He taught me many basic knowledge and practical skills in power electronics research, which is quite helpful in the whole process of my graduate study. I also would like to thank Dr. Dong Cao for his collaboration in the current-fed quasi-Z-source inverter project. His great passion for research and exigency for the results inspired me to think more and more and finally leaded to the success of the project. v Many thanks are also extended to my colleagues in PEMD Lab for their delightful discussions and friendship, Dr. Baoming Ge, Ms. Xi Lu, Mr. Shuai Jiang, Dr. Honnyong Cha, Mr. Xianhao Yu, Mr. Sisheng Liang, Dr. Wei Qian, Mr. Craig Rogers, Dr. Yi Huang, Mr. Joel Anderson, Mr. Jorge G. Cintron-Rivera, Dr. Uthane Supatti, Mr. Jianfeng Liu, in research and life through our interactions during the long hours in the lab. Thanks. Finally and most importantly, I would like to thank my husband Junjun for his continuous support and encouragement, and numerous discussions. I also would like to thank my parents Chuping Lei and Airong Wang for their unconditional care for years. I also would like to thank my brother for his understanding and care. Their love to me and my love to them are the greatest motivation in my life. vi TABLE OF CONTENTS LIST OF TABLES--------------------------------------------------------------------------------------xi LIST OF FIGURES-----------------------------------------------------------------------------------xiii CHAPTER 1 INTRODUCTION----------------------------------------------------------------- 1 1.1. Problems of conventional current source topology------------------------------------------ 2 1.2. Problems of conventional current source inverter modulation----------------------------- 3 1.3. Topology synthesis literature--------------------------------------------------------------------7 1.4. Problems of traditional matrix converter------------------------------------------------------ 9 1.5. Scope of the dissertation-------------------------------------------------------------------------9 CHAPTER 2 CURRENT SOURCE INVERTER TOPOLOGIES-----------------------12 2.1. Introduction--------------------------------------------------------------------------------------12 2.2. Topology synthesis techniques----------------------------------------------------------------13 2.2.1. Graph Theory -----------------------------------------------------------------------13 2.2.2. Duality------------------------------------------------------------------------------- 14 2.2.3. Bilateral inversion transformation----------------------------------------------- 16 2.2.4. Cascade------------------------------------------------------------------------------ 16 2.2.5. Parallel------------------------------------------------------------------------------- 17 2.2.6. With transformers------------------------------------------------------------------ 18 2.2.7. Extension of canonical switching cell------------------------------------------- 20 2.3. Derivation of buck-boost Z-source inverters------------------------------------------------21 2.4. Newly derived inverter topologies with buck-boost function---------------------------- 24 2.5. Proposed switched-coupled-inductor inverter family with buck/boost function-------25 2.6. Direct Z-source matrix converter topology------------------------------------------------- 31 2.7. Summary---------------------------------------------------------------------------------------- 37 CHAPTER 3 STEADY STATE CIRCUIT ANALYSIS-------------------------------------40 3.1. Introduction------------------------------------------------------------------------------------40 3.2. Current-fed quasi-Z-source inverter--------------------------------------------------------43 3.2.1. Equivalent circuit states-----------------------------------------------------------46 3.2.2. Voltage gain and current gain-----------------------------------------------------48 3.2.3. Operation regions-------------------------------------------------------------------49 3.2.4. Calculation of the ac output voltage and current-------------------------------51 3.2.5. Passive component stress and total switching device power rating--------- 53 3.3. Current-fed Z-source rectifier---------------------------------------------------------------54 3.3.1. Equivalent circuit states-----------------------------------------------------------54 3.3.2. Voltage gain equation--------------------------------------------------------------57 3.3.3. Operation regions-------------------------------------------------------------------57 3.3.4. Calculation of the ac output voltage and current-------------------------------60 3.3.5. Design of Z-network L and C in continuous mode----------------------------61 3.4. Switched-coupled-inductor inverter---------------------------------------------------------63 3.4.1. Voltage-fed switched-coupled-inductor inverter-------------------------------64 3.4.1.1. Equivalent circuit states------------------------------------------------ 64 3.4.1.2. Voltage and current gain------------------------------------------------65 3.4.2. Current-fed Switched-Coupled-Inductor Inverter-----------------------------69 vii 3.4.2.1. Equivalent circuit sates-------------------------------------------------69 3.4.2.2. Voltage gain and current gain------------------------------------------69 3.4.2.3. Voltage and current stress comparison-------------------------------71 3.5. Direct Z-source matrix converter------------------------------------------------------------77 3.5.1. Voltage-fed Z-source matrix converter boost ratio----------------------------78 3.5.2. Voltage-fed quasi-Z-source matrix converter boost ratio---------------------83 3.6. Summary---------------------------------------------------------------------------------------87 CHAPTER 4 MODULATION-------------------------------------------------------------------90 4.1. Introduction--------------------------------------------------------------------------------------90 4.2. Discontinuous SVPWM and Equivalent Carrier-based modulation--------------------- 92 4.2.1. Selection of zero vector in terms of minimum switching times--------------93 4.2.2. Selection of switching sequence in each sector-------------------------------- 94 4.2.3. Equivalent reference-carrier modulation for DPWM--------------------------96 4.2.4. Numerical Spectrum analysis-----------------------------------------------------99 4.2.5. Analytical double Fourier analysis----------------------------------------------101 4.2.6. Simulation results-----------------------------------------------------------------103 4.3. Continuous SVPWM and Equivalent Carrier-based modulation-----------------------104 4.3.1. Selection of zero states in each sector------------------------------------------104 4.3.2. Equivalent carrier-based modulation for continuous SVPWM-------------105 4.3.3. Sequences of vectors in each switching cycle---------------------------------106 4.3.4. Numerical FFT spectrum analysis----------------------------------------------107 4.3.5. Simulation results-----------------------------------------------------------------108 4.4. Space-Vector-Pulse-Width-Amplitude-Modulation (SVPWAM)----------------------109 4.4.1. SVPWAM for Voltage Source Inverter(VSI)----------------------------------110 4.4.1.1. Principle of SVPWAM control in VSI-------------------------------110 4.4.1.2. Inverter switching loss reduction for VSI---------------------------115 4.4.2. SVPWAM for Current Source Inverter(CSI)----------------------------------117 4.4.2.1. Principle of SVPWAM in CSI----------------------------------------117 4.4.2.2. Inverter switching loss reduction for CSI---------------------------120 4.4.3. Spectrum Analysis of SVPWAM-----------------------------------------------121 4.4.3.1. Spectrum comparison between SPWM, discontinuous SVPWM and SVPWAM in VSI-------------------------------------------------------------121 4.4.3.2. Spectrum comparison between discontinuous SVPWM, continuous SVPWM and SVPWAM in CSI-------------------------------------------------128 4.4.4. Analytical double Fourier expression for SVPWAM------------------------140 4.4.5. Topologies for SVPWAM-------------------------------------------------------142 4.5. Summary CHAPTER 5 SVPWM FOR Z-SOURCE INVERTER — ZERO VECTOR PLACEMENT---------------------------------------------------------------------------------------142 5.1. Introduction------------------------------------------------------------------------------------144 5.2. The Influence of Zero Space Vector Placement-------------------------------------------147 5.3. Consequential modulation Implementation Issues--------------------------------------- 149 5.4. Zero Vector Placement For SVPWM of Voltage-fed Z-source Inverter--------------- 150 5.4.1. SVPWM control method for voltage-fed Z-source inverter---------------- 150 5.4.2. Vector placement for SVPWM control of voltage-fed Z-source inverter--152 5.4.3. Effect of vector placement for current ripple----------------------------------154 5.4.4. Effect of vector placement for output harmonics-----------------------------154 5.5. Zero Vector Placement For SVPWM of Current-fed Z-source Inverter---------------156 viii 5.5.1. SVPWM control method for current-fed Z-source inverter------------------156 5.5.2. Vector placement for SVPWM control of current-fed Z-source inverter---159 5.6. Case Study: 98% Efficiency 24KW Current-fed Quasi-Z-Source Inverter------------170 5.6.1. Power loss analysis for 24KW current-fed quasi-Z-source inverter--------170 5.6.2. Basic buck/boost function test on first version 5KW prototype----------- 174 5.6.3. Basic function and efficiency test on final 24KW prototype----------------183 5.6.4. Experiment results----------------------------------------------------------------184 5.6.5. Efficiency vs. voltage gain plot-------------------------------------------------187 5.6.6. Power Loss Breakdown----------------------------------------------------------191 5.7. Summary---------------------------------------------------------------------------------------193 CHAPTER 6 SVPWAM IN VSI AND CSI-EXPERIMENTAL DEMONSTRATION-194 6.1. Introduction-----------------------------------------------------------------------------------194 6.2. Case study 1: 1kW SVPWAM-controlled boost-converter-inverter system for EV motor drive-----------------------------------------------------------------------------------197 6.2.1. Basic principle---------------------------------------------------------------------197 6.2.2. DC link capacitor sizing----------------------------------------------------------198 6.2.3. Voltage constraint and operation region----------------------------------------199 6.2.4. Variable dc link SPWM control at high frequency---------------------------200 6.2.5. Simulation Results----------------------------------------------------------------203 6.2.6. Experiment results----------------------------------------------------------------204 6.2.7. Conclusion for SVPWAM in VSI---------------------------------------------- 220 6.3. Case study 2 : SVPWAM for normal current source inverter with 6 dc link current-----------------------------------------------------------------------------------------------220 6.4. Case study 3: SVPWAM for current-fed quasi-Z-source inverter---------------------222 6.5. Summary--------------------------------------------------------------------------------------225 CHAPTER 7 SVPWM FOR DIRECT Z-SOURCE MATRIX CONVERTER – SHOOT-THROUGH CONTROL-----------------------------------------------------------------226 7.1. Introduction-----------------------------------------------------------------------------------226 7.2. Quasi-SVPWM for Traditional Matrix converter---------------------------------------228 7.3. Simple boost, maximum boost, maximum constant boost shoot through control methods based on quasi-SVPWM---------------------------------------------------------------231 7.3.1. Principle of three control methods----------------------------------------------231 7.3.2. Voltage gain and stress equations for each method---------------------------233 7.3.3. The voltage gain comparison among three methods------------------------- 235 7.3.4. THD comparison among three methods--------------------------------------- 236 7.3.5. Switching loss comparison among three methods----------------------------239 7.4. Maximum Voltage Gain Control-----------------------------------------------------------241 7.5. Hybrid minimum voltage stress control--------------------------------------------------244 7.6. PWAM Control Method For Matrix Converter------------------------------------------246 7.7. CSR and VSI coordination-----------------------------------------------------------------254 7.8. New commutation and protection strategy-----------------------------------------------255 7.9. Protection strategy---------------------------------------------------------------------------258 7.10. Practical Implementation of Control Method-------------------------------------------259 7.11. Experiments results to demonstrate voltage boost function by using maximum boost control-----------------------------------------------------------------------------------------------262 7.12. Simulation and Experimental Results to demonstrate hybrid minimum stress control-----------------------------------------------------------------------------------------------268 7.13. Summary-------------------------------------------------------------------------------------278 ix CHAPTER 8 DISCONTINUOUS OPERATION MODE---------------------------------280 8.1. Introduction----------------------------------------------------------------------------------280 8.2. Two discontinuous modes when capacitance is small or load power factor is low-281 8.3. Capacitor voltage waveform in discontinuous modes----------------------------------284 8.3.1. SPWM Control -Maximum Constant Boost Control-------------------------287 8.3.2. SVPWM Control------------------------------------------------------------------290 8.4. Critical conditions for discontinuous mode----------------------------------------------291 8.4.1. Capacitor voltage ripple----------------------------------------------------------292 8.4.2. Critical Condition of different shoot through control methods in SPWM method-------------------------------------------------------------------------------------292 8.4.3. Critical condition for SVPWM method----------------------------------------294 8.5. Simulation and experimental demonstration--------------------------------------------295 8.6. Summary-------------------------------------------------------------------------------------299 CHAPTER 9 CIRCUIT MODELING AND TRANSIENT ANALYSIS----------------301 9.1. Introduction-----------------------------------------------------------------------------------301 9.2. Current-fed quasi-Z-source inverter-------------------------------------------------------305 9.2.1. Research target-------------------------------------------------------------------- 305 9.2.2. Circuit Modeling----------------------------------------------------------------- 306 9.2.3. Initial conditions and steady state conditions---------------------------------308 9.2.4. Solution for input current--------------------------------------------------------310 9.2.5. Simulation and experiment demonstration------------------------------------311 9.2.6. Conclusion-------------------------------------------------------------------------315 9.3. Three phase current-fed Z-source PWM rectifier---------------------------------------315 9.3.1. PWM rectifier state space model-----------------------------------------------315 9.3.2. Z-Source network state space model-------------------------------------------317 9.3.3. Current-fed Z-source rectifier dq state space model-------------------------318 9.3.4. Initial conditions and steady state conditions---------------------------------320 9.4. Switched-coupled-inductor inverter------------------------------------------------------ 322 9.4.1. Steady state analysis for voltage-fed topology--------------------------------322 9.4.2. Generalized state space model for the voltage-fed family-------------------325 9.4.3. Governing equations for voltage-fed family-----------------------------------327 9.4.4. Steady state analysis for current-fed family-----------------------------------329 9.4.5. Generalized state space model for current-fed family-----------------------329 9.4.6. Governing equations for current-fed family---------------------------------- 330 9.4.7. Simulation Results demonstration----------------------------------------------331 9.4.8. Conclusion for switched-coupled-inductor inverter--------------------------334 9.5. Summary--------------------------------------------------------------------------------------335 CHAPTER 10 CONCLUSIONS AND RECOMMENDATIONS---------------------------337 10.1. Contributions--------------------------------------------------------------------------------337 10.2. Recommendations for future works------------------------------------------------------338 BIBLIOGRAPHY------------------------------------------------------------------------------------341 x LIST OF TABLES Table 2-1.Voltage gain of current-fed Z-source inverter topologies in Fig. 2.8--------24 Table 3-1.The passive and device voltage in each circuit state--------------------------47 Table 3-2.Voltage gain and active/passive device stress for VF-SCII-------------------68 Table 3-3.Voltage Gain and Active/Passive Device Stress for CF-SCII----------------70 Table 4-1.Selection of vectors in each sector-----------------------------------------------93 Table 4-2.Conduction Time for S1 and S4 in Each Sector--------------------------------93 Table 4-3.Integration limit of S1 for sequence b------------------------------------------102 Table 4-4.Integration limit for Ia(t) of sequence b----------------------------------------103 Table 4-5.Selection of vectors in each sector in Continuous SVWPM----------------105 Table 4-6.Integration limit for switching function S1 (t ) ---------------------------------137 Table 4-7.Integration limit for switching function S3 (t ) ---------------------------------138 Table 4-8.Integration limit for line to line voltage Vab (t ) -------------------------------138 Table 5-1.Current-fed QZSI governing equations----------------------------------------158 Table 5-2.Control parameters and gain for current-fed QZSI---------------------------158 Table 5-3.Average and ripple current for input branches--------------------------------160 Table 5-4.Nineteen Switching Sequences for CF-QZSI SVPWM control------------160 Table 5-5.Switching loss for sequence I.A in group I------------------------------------162 Table 5-6.Switching loss for sequence II.A in group II----------------------------------163 Table 5-7.Switching loss for sequence III.B in group III--------------------------------164 Table 5-8.Inductor Voltage in buck mode and boost mode------------------------------171 xi Table 5-9.Different Operation Points in Simulation and Experiments-----------------177 Table 5-10.Experiment hardware part number and parameters------------------------184 Table 7-1.Shoot through reference and duty cycle---------------------------------------234 Table 7-2.Parameters used in the case study----------------------------------------------235 Table 7-3.Boost ratio and voltage gain of three methods-------------------------------236 Table 7-4.Maximum Gain of Each Method-----------------------------------------------236 Table 7-5.Control strategy for different G-------------------------------------------------245 Table 7-6.Voltage gain comparison at certain M-----------------------------------------278 Table 7-7.Voltage stress comparison at certain G----------------------------------------278 Table 8-1.Definitions of the variables----------------------------------------------------281 Table 8-2.Characteristics of different control strategies---------------------------------295 Table 9-1.Simulation results in mode change transition---------------------------------313 Table 9-2.Voltage gain and active/passive device stress for VF-SCII------------------328 Table 9-3.Voltage gain and active/passive device stress for CF-SCII------------------331 xii LIST OF FIGURES Figure 1.1. Conventional IGBTs and series diodes based CSI--------------------------------------2 Figure 1.2. Space vectors of the CSI (For interpretation of the references to color in this and all other figures, the reader is referred to the electronic version of this dissertation)----------- 4 Figure 2.1. Twelve basic dc-dc converter topology from graph theory ---------------------------4 Figure 2.2. Current source dc/dc converter from duality of voltage source converter---------15 Figure 2.3. DC/DC converter derivation from inverse transformation---------------------------17 Figure 2.4. Topologies generated by cascading basic circuit--------------------------------------17 Figure 2.5. Topologies derived from adding isolation transformer between input and output------------------------------------------------------------------------------------------------------19 Figure 2.6. Topologies derived from adding coupled inductor between input and output-----21 Figure 2.7. Voltage-fed Z-source inverter topologies derived from basic dc-dc converter (D is the shoot through duty cycle, Gv is the voltage gain between output equivalent voltage and input)------------------------------------------------------------------------------------------------------22 Figure 2.8. Current-fed Z-source inverter topologies derived from basic dc-dc converter (CF=current-fed; ZSI=Z-source inverter QZSI=quasi-Z-source inverter)-----------------------24 Figure 2.9. New inverter topologies with buck-boost functions derived from basic dc-dc converter (D is the shoot through duty cycle, Gv is the voltage gain between output equivalent voltage and input)--------------------------------------------------------------------------26 Figure 2.10. Voltage-fed switched-coupled-inductor inverter topologies and their original circuit------------------------------------------------------------------------------------------------------27 Figure 2.11. Current-fed switched-coupled-inductor inverter topologies and their original circuit------------------------------------------------------------------------------------------------------28 Figure 2.12. Topologies of (a-c) traditional matrix converter (d-l) direct Z-source matrix converter family------------------------------------------------------------------------------------------33 Figure 3.1. Traditional voltage source inverter and current source inverter---------------------44 Figure 3.2. (a) voltage-fed Z-source inverter (b) current-fed Z-source inverter-----------------45 Figure 3.3 (a)voltage-fed quasi-Z-source inverter (b) current-fed quasi-Z-source inverter---45 Figure 3.4. Equivalent circuits of the current-fed qZSI in continuous mode--------------------47 Figure 3.5. Operation region according to voltage gain vs. DA curve---------------------------49 xiii Figure 3.6. I L1 / Iin versus DOP of the current-fed qZSI--------------------------------------49 Figure 3.7. Current-fed Z-source rectifier------------------------------------------------------------54 Figure 3.8.Operation states of current-fed Z-source PWM rectifier------------------------------55 Figure 3.9. Voltage gain Vdc / Veq v.s. DA in all Dop ----------------------------------------58 Figure 3.10. Current gain I dc / I L vs DA in all Dop ------------------------------------------59 Figure 3.11. Current gain I L / I dc vs Dop in all Dop ------------------------------------------59 Figure 3.12. The dc output gain Vdc / Vsrms m and power factor, at Dop  0.65 ------------61 Figure 3.13. Voltage-fed switched-coupled-inductor inverter 2 (VF-SCII 2)-------------------64 Figure 3.14. Inverter b operating states (a) shoot through state D0 (b) non-shoot-through state 1  D0 ----------------------------------------------------------------------------------------------65 Figure 3.15 Current-fed switched-coupled-inductor inverter 2 (CF-SCII 2)--------------------69 Figure 3.16. Two operation states of CF-SCII 2----------------------------------------------------69 Figure 3.17. Comparison among the voltage-fed switched-coupled-inductor inverters-------71 Figure 3.18. Comparison among the current-fed switched-coupled-inductor inverters--------74 Figure 3.19. Voltage stress vs. voltage gain at n=0.5 for both voltage-fed switched-coupled-inductor inverter and voltage-fed Z/quasi-Z-source inverter----------------76 Figure 3.20. Voltage boost ratio B versus active duty cycle DA (0.866M) for current-fed qZSI and current-fed switched-coupled-inductor inverter------------------------------------------------77 Figure 3.21. Voltage-fed Z-source matrix converter------------------------------------------------79 Figure 3.22. Equivalent circuit states of Z-source matrix converter------------------------------79 Figure 3.23.Voltage boost ratio B vs D0 for Z-source matrix converter (MC)-----------------82 Figure 3.24.Phase angle between Va,b,c and Va',b',c' for Z-source MC------------------------82 Figure 3.25. Voltage-fed quasi-Z-source inverter---------------------------------------------------83 Figure 3.26. Equivalent circuit states for qZ-source MC-------------------------------------------84 xiv Figure 3.27.Voltage boost ratio B vs D0 of voltage-fed quasi-Z-source matrix converter----86 Figure 3.28.Phase angle between Va,b,c and Va',b',c' for qZ-source MC-----------------------86 Figure 4.1. Conventional current source inverter---------------------------------------------------90 Figure 4.2. Nine switching states for conventional current source inverter---------------------90 Figure 4.3 Conventional discontinuous modulation for current source inverter----------------91 Figure 4.4. Output current vector synthesis----------------------------------------------------------92 Figure 4.5. Four different switching sequences in sector I-----------------------------------------94 Figure 4.6. Switching state in 6 sectors for sequence c---------------------------------------------96 Figure 4.7. References for S1 and S4 and the output line current waveform--------------------97 Figure 4.8. PWM implementation for three sequences---------------------------------------------98 Figure 4.9. Numerical FFT results for b, c, d at m=0.8 for switching frequency range------100 Figure 4.10. Simulated phase a current after the C filter for sequence b, c, d-----------------104 Figure 4.11. Continuous SVPWM modulation switching states in Sector I--------------------105 Figure 4.12. Equivalent carrier-based modulation for continuous SVPWM-------------------105 Figure 4.13 Implementation of switching waveform in Figure 4.12 by carrier-based continuous SVPWM-----------------------------------------------------------------------------------106 Figure 4.14. Numerical spectrum analysis of phase current for continuous SVPWM at M=0.8----------------------------------------------------------------------------------------------------107 Figure 4.15. Switching waveform of continuous SVPWM---------------------------------------109 Figure 4.16. Simulated three phase output current after the filter-------------------------------109 Figure 4.17. Space-Vector-Pulse-Width-Amplitude-Modulation for VSI----------------------110 Figure 4.18 DC link voltage of SVPWAM in VSI-------------------------------------------------112 Figure 4.19. Vector placement in each sector for VSI---------------------------------------------113 Figure 4.20. Theoretic waveforms of dc link voltage, output line to line voltage and switching signals----------------------------------------------------------------------------------------------------114 Figure 4.21. Switch voltage and current stress when pf=1 (In shadow area)------------------115 xv Figure 4.22. (SVPWAM power loss / SPWM power loss) vs. power factor in VSI----------117 Figure 4.23 Current source inverter SVPWAM diagram-----------------------------------------118 Figure 4.24. DC current and output phase current waveform------------------------------------118 Figure 4.25. Vector placement for each sector for CSI--------------------------------------------119 Figure 4.26. Theoretic waveforms of dc link current, output line current and switching signals ------------------------------------------------------------------------------------------------------------120 Figure 4.27. Switching voltage and current when pf=1-------------------------------------------120 Figure 4.28. CSI switching loss SVPWAM/SVPWM vs. power factor------------------------121 Figure 4.29. Output line to line voltage waveform for three methods: (a) SPWM; (b) discontinuous SVPWM; and (c) SVPWAM--------------------------------------------------------122 Figure 4.30. Spectrum of SPWM: (a) zoom-in at fundamental frequency; (b) zoom-in at switching frequency; (c) zoom-in at double its own switching frequency---------------------124 Figure 4.31. Spectrum of discontinuous SVPWM: (a) zoom-in at fundamental frequency; (b) zoom-in at switching frequency----------------------------------------------------------------------126 Figure 4.32. Spectrum of SVPWAM: (a) zoom-in at fundamental frequency; (b) zoom-in at switching frequency-----------------------------------------------------------------------------------127 Figure 4.33. Numerical FFT results for b, c, d at m=0.8 for both fundamental frequency range and switching frequency range-----------------------------------------------------------------------129 Figure 4.34. Numerical spectrum of phase current for continuous SVPWM at M=0.8------133 Figure 4.35. theoretical output line current in SVPWAM----------------------------------------134 Figure 4.36. Numerical spectrum of output current for SVPWAM-----------------------------135 Figure 4.37 WTHD vs. M for different methods--------------------------------------------------136 Figure 4.38. Simulation results for SVPWAM CSI: (a) switching waveform (b) Input dc link current and output one phase current before the filter (c) input dc link current and output three phase current after the filter---------------------------------------------------------------------------139 Figure 4.39. Possible topologies for using SVPWAM--------------------------------------------141 Figure 5.1. Circuit configurations of Z-Source inverter------------------------------------------144 Figure 5.2 Centered PWM and back to back PWM and their corresponding current ripple-147 Figure 5.3. SVPWM control for voltage-fed Z-source inverter----------------------------------151 xvi Figure 5.4. Three equivalent circuit states for voltage-fed quasi-Z-source inverter----------151 Figure 5.5. Six sequences of the vector placement for SVPWM of voltage-fed Z-source inverter---------------------------------------------------------------------------------------------------153 Figure 5.6. Discontinuous vector placement sequence for SVPWM of voltage-fed Z-source inverter---------------------------------------------------------------------------------------------------153 Figure 5.7. Control diagram of space vector PWM method (SVPWM)------------------------157 Figure 5.8. Three basic circuit states of current-fed quasi-Z-source inverter------------------157 Figure 5.9. Modified discontinuous SVPWM in one switching period in sector III----------158 Figure 5.10. Switching losses (a) group I (b) group III-------------------------------------------164 Figure 5.11. Spectrum for representative sequences from each group in buck mode at M=0.8, Dop=0.3-------------------------------------------------------------------------------------------------166 Figure 5.12. THD for each representative sequence from each group vs. Modulation index in buck mode-----------------------------------------------------------------------------------------------169 Figure 5.13. Power loss percentage vs. voltage gain----------------------------------------------173 Figure 5.14. Efficiency measurement reference curve--------------------------------------------174 Figure 5.15. 5kW current-fed quasi-Z-source inverter prototype-------------------------------175 Figure 5.16. 5kW current-fed quasi-Z-source inverter with coupled inductors---------------175 Figure 5.17. Equivalent circuits in active state, short zero state and open zero state---------176 Figure 5.18. Simulation results: left figure (from top to bottom): output line to line voltage, output phase current, Z-source inductor current, input inductor current, input voltage; right figure: dc link voltage, dc link current, Z-source inductor current, input inductor current, input voltage--------------------------------------------------------------------------------------------178 Figure 5.19. Case 1-3: from top to bottom is output line to line voltage and input current; case 4: from top to bottom: input voltage, output phase current, output l-l voltage----------------182 Figure 5.20. Zoom in waveform for case 3 and 4: from top to bottom: DC link voltage, input voltage, Z-source inductor current, input current--------------------------------------------------182 Figure 5.21. Hardware picture-----------------------------------------------------------------------183 Figure 5.22. Three phase output line to line voltage and device voltage on curve 1----------185 Figure 5.23. Three phase output line to line voltage and device voltage on curve 2----------186 Figure 5.24. Output voltage, current, input current waveforms and its measured value for xvii operation curve from the power meter on curve 1-------------------------------------------------188 Figure 5.25. Output voltage, current, input current waveforms and its measured value for operation curve from the power meter on curve 2-------------------------------------------------190 Figure 5.26. Measured & theoretic efficiency vs. Voltage gain G on curve 1-----------------191 Figure 5.27. Measured & theoretic efficiency vs. Voltage gain G on curve 2, at constant P=15KW-------------------------------------------------------------------------------------------------191 Figure 5.28. Power loss break down-----------------------------------------------------------------192 Figure 6.1. SVPWAM based boost-converter-inverter motor drive system--------------------197 Figure 6.2. Operation region of the proposed boost-converter-inverter EV traction drive---199 Figure 6.3. Variable Carrier SPWM control in buck mode---------------------------------------200 Figure 6.4. Variable dc link SPWM control at output frequency 720 Hz, and dc link frequency 720×1 Hz------------------------------------------------------------------------------------------------202 Figure 6.5. Simulation results of SVPWAM at 60 Hz, 1 kW-------------------------------------203 Figure 6.6. Simulation results of SPWAM at 720 Hz, 1 kW-------------------------------------204 Figure 6.7. Hardware picture of the 1kW SVPWAM boost-converter-inverter-------------205 Figure 6.8. Output voltage and input current at Vin=20V, Vdc_avg=60 V ,Vlrms=46V, Po=40W, fo=60Hz, fsw=20KHz---------------------------------------------------------------------207 Figure 6.9. Output voltage and input current at Vin=60V, Vdc_avg=180 V, Vlrms=138 V, Po=360 W, fo=60Hz, fsw=20KHz-------------------------------------------------------------------207 Figure 6.10. Output voltage and input current at Vin=100 V, Vdc_avg=300 V, Vlrms=230 V, Po=1 kW, fo=60Hz, fsw=20KHz---------------------------------------------------------------------208 Figure 6.11. Output three phase line voltage and dc link voltage at Vin=100 V, Vdc_avg=300 V, Vlrms=230 V, Po=1 kW, fo=60Hz, fsw=20KHz------------------------------------------------208 Figure 6.12. The results of efficiency test at constant full power rating 1kW-----------------209 Figure 6.13. The efficiency test results when output power change proportionally with input voltage, in which the boost ratio of front dc-dc converter is constant; the waveforms have the same definition as Figure 6.12-----------------------------------------------------------------------211 Figure 6.14. The efficiency test at 1kHz: output l-l voltage, output current, input current---215 Figure 6.15. Measured overall efficiency when input voltage changes from 100 V to 200 V at 1 kW power rating corresponding to Figure 6.12 ( fo  60 Hz , f sw  20kHz , Vdc _ peak  325V , Vol lrms  230V )---------------------------------216 xviii Figure 6.16. The efficiency test results when output voltage/output power changes with a constant input voltage: at different voltage level including 100V, 120V and 150V from Figure 6.12 (a), Figure 6.13(d) and other result-----------------------------------------------------------216 Figure 6.17. The efficiency test curve when output power changes proportionally with input voltage (Vin from 50V to 150V, Po from 120W to 1kW), corresponding to experimental waveforms in Figure 6.13-----------------------------------------------------------------------------217 Figure 6.18. The efficiency test results corresponding to curve in Figure 6.17 Figure 6.19. Comparison between inverter power losses in the condition that dc link voltage changes from 0 to full rating at 300V--------------------------------------------------------------------------------217 Figure 6.19 Conventional current source inverter for PWAM---------------------------------219 Figure 6.20 Novel current source inverter for PWAM------------------------------------------220 Figure 6.21. Simulation results for PWAM CSI: (a) switching waveform (b) Input dc link current and output one phase current before the filter (c) input dc link current and output three phase current after the filter---------------------------------------------------------------------------221 Figure 6.22. Circuit configuration of current-fed Quasi-Z-Source-Inverter--------------------222 Figure 6.23. PWAM modulation principle----------------------------------------------------------223 Figure 6.24 Simulation results------------------------------------------------------------------------224 Figure 7.1. Equivalent circuit of direct matrix converter-----------------------------------------228 Figure 7.2. SVPWM modulation method for traditional matrix converter---------------------229 Figure 7.3. Third harmonic injection for traditional matrix converter--------------------------230 Figure 7.4. Shoot through control for Z-source Matrix Converter (a) simple maximum boost control (b) maximum boost control (c) maximum constant boost-------------------------------232 Figure 7.5. Voltage gain vs. modulation index for three methods-------------------------------235 Figure 7.6. Spectrum of different methods at fo  80 Hz ---------------------------------------238 Figure 7.7. Switching loss comparison at different G---------------------------------------------241 Figure 7.8. Maximum voltage gain vs. M----------------------------------------------------------242 Figure 7.9. Shoot through references to generate D0 (t )  0.5 -----------------------------------243 Figure 7.10. Control strategy selection at different gain ratio for ZS-MC---------------------244 xix Figure 7.11. Voltage stress at different voltage gain of hybrid control-------------------------245 Figure 7.12. Nine switch direct matrix converter--------------------------------------------------246 Figure 7.13. Equivalent decomposed circuit for nine switch direct matrix converter--------246 Figure 7.14. Current source inverter space vector modulation diagram------------------------248 Figure 7.15. Voltage source inverter space vector modulation diagram------------------------249 Figure 7.16. PWAM control (a) DC current waveform and switching pattern in different sections (b) Simulated output current, dc current and switching state--------------------------250 Figure 7.17. PWAM control +PWM control for low switching loss MC: (a) method 1: PWAM rectifier + PWM inverter (b) method 2: PWM rectifier +PWAM inverter---------------------252 Figure 7.18. PWAM control + PWM control for low switching loss MC----------------------253 Figure 7.19. (a) switching waveform for current source inverter (b) switching waveform for voltage source inverter--------------------------------------------------------------------------------253 Figure 7.20 (a) Coordination method 1 (b) coordination method 2-----------------------------255 Figure 7.21. Voltage-based four step commutation------------------------------------------------256 Figure 7.22. Traditional load current based four step commutation method-------------------257 Figure 7.23. Combined commutation method (a) current-based master voltage-based slave (b) voltage-based slave current based slave-------------------------------------------------------------258 Figure 7.24. Improved protection method for voltage-fed quasi-Z-source inverter-----------259 Figure 7.25. Transformation of the duty cycle-----------------------------------------------------261 Figure 7.26. Indicators of the voltage envelopes--------------------------------------------------261 Figure 7.27. Buck operation of the simplified voltage-fed ZS matrix converter: from top to bottom, four traces are the input line-line voltage to the Z-source network, the output line-line voltage from the matrix converter, the output phase current from the matrix converter, and the input phase current to the matrix converter---------------------------------------------------------264 Figure 7.28. PWM duty cycles, output currents of three phases from the matrix converter, and the matrix converter’s output phase voltage, from top to bottom, respectively----------------265 Figure 7.29. Boost operation of the simplified voltage-fed ZS matrix converter: from top to bottom, four traces are the input line-line voltage to the Z-source network, the output line-line voltage from the matrix converter, the output phase current from the matrix converter, and the input phase current to the matrix converter---------------------------------------------------------266 Figure 7.30. Transition from the buck mode to the maximum boost control: from top to xx bottom, four traces are the input line-line voltage to the Z-source network, the output line-line voltage from the matrix converter, the output phase current from the matrix converter, and the input phase current to the matrix converter---------------------------------------------------------267 Figure 7.31.Simulation results at non-shoot through at M=0.6----------------------------------269 Figure 7.32.Simulation results at maximum constant boost at M=0.6--------------------------270 Figure 7.33.Simulation results at maximum boost control at M=0.6---------------------------271 Figure 7.34.Simulation results at simple-max boost at M=0.6-----------------------------------272 Figure 7.35. Output line to line voltage at G=0.866 for three methods-------------------------274 Figure 7.36. Input line voltage right before matrix converter at G=0.866----------------------275 Figure 7.37. Voltage gain comparison at M=0.661: non-shoot-through control at t  [0, 0.1] and maximum constant boost control at t  [0.1, 0.2] ----------------------------------------------276 Figure 7.38.Voltage gain comparison at M=0.2: non-shoot-through control at t  [0, 0.1] ; maximum constant boost control at t  [0.1, 0.2] ; simple maximum boost control at t  [0.2, 0.4] ---------------------------------------------------------------------------------------------277 Figure 7.39 Voltage stress comparison at G=1.073: maximum boost control with M=0.542 at t  [0, 0.1] ; hybrid minimum voltage stress control with M=0.866 at t  [0.1, 0.2] --------277 Figure 7.40. Voltage stress comparison at G=0.8: Hybrid minimum stress control at t  [0, 0.1] ; simple maximum boost control at t  [0.1, 0.2] ; maximum boost control at t  [0.2, 0.4] ---------------------------------------------------------------------------------------------277 Figure 8.1. RB-IGBT based current-fed qZSI configuration with discontinuous input current---------------------------------------------------------------------------------------------------280 Figure 8.2. Possible operations modes of current-fed qZSI: (a) mode 1(b) mode 2, (3) mode 3, (4) mode 4, (5) mode 5--------------------------------------------------------------------------------282 Figure 8.3 Two discontinuous operation modes---------------------------------------------------285 Figure 8.4. Capacitor voltage waveforms at different modulation methods-------------------286 Figure 8.5. The factors causing discontinuous operation mode----------------------------------291 Figure 8.6. The circuit configuration in the experiment------------------------------------------296 Figure 8.7. (a) First version of 5kW current-fed quasi-Z-source inverter with separate inductors (b) second version of 5kW current-fed quasi-Z-source inverter with coupled inductors-------------------------------------------------------------------------------------------------296 Figure 8.8. Experimental results of the CVM condition under SVPWM control for voltage xxi buck operation (Vpn: DC link voltage across the inverter bridge; Vc: qZ-network capacitor voltage; Iin: input inductor current; Vab: load line to line voltage; Ia: load phase current)--------------------------------------------------------------------------------------------------297 Figure 9.1. Four operation modes of parallel hybrid vehicles (F: Fusion tank; E: Engine; B: Battery; P: Power converter; M: Motor; T: Transmission)---------------------------------------301 Figure 9.2. Four operation modes of series hybrid vehicles--------------------------------------302 Figure 9.3. Block diagram of transition from motoring mode to regenerating mode---------305 Figure 9.4. Circuit model for two basic circuit states---------------------------------------------306 Figure 9.5. Circuit configuration to monitor the transition process-----------------------------309 Figure 9.6. Calculated input current waveform in transition starting at t=0.2s----------------311 Figure 9.7. (a)Simulation results (1) Output phase A Current (2) output phase A Voltage (3) input inductor current (4) Z-source capacitor voltage in motoring to regeneration transition (at t=0.2s) (b) Zoom in results of (a)------------------------------------------------------------------312 Figure 9.8. Comparison between calculated Idc and simulated Idc-----------------------------314 Figure 9.9. Comparison between calculated Iga amplitude and simulated Iga amplitude------------------------------------------------------------------------------------------------314 Figure 9.10.Operation states of current-fed Z-source PWM rectifier---------------------------315 ^ ^ Figure 9.11 Frequency response of the transfer function of VC / dop -------------------------322 Figure 9.12. Inverter b operating states (a) shoot through state D0 (b) non-shoot-through state 1  D0 --------------------------------------------------------------------------------------------323 Figure 9.13. Two operation states of current source inverter h----------------------------------329 Figure 9.14 Simulation results for voltage-fed switched-coupled-inductor inverter 2 at M=0.6, n=2 (from the first to last: input voltage, dc link voltage before inverter bridge, input capacitor voltage, output line to line voltage)------------------------------------------------------332 Figure 9.15 Input inductor L1 and L2 current (from first to last, input inductor 1 current, input inductor 2 current)------------------------------------------------------------------------------333 Figure 9.16. Simulation results for voltage-fed switched-coupled-inductor inverter 5 at M=0.75, n=0.5------------------------------------------------------------------------------------------333 Figure 9.17. Input inductors L1 and L2 current----------------------------------------------------334 xxii CHAPTER 1 INTRODUCTION The Z-source inverters (ZSIs) have been proposed in [1] to overcome the limitations and problems of the traditional voltage-source inverter (VSI) and current-source inverter (CSI), which provide an attractive single-stage dc-ac conversion that is able to buck-boost voltage, increase efficiency and reduce cost. However, the ZSIs still have some drawbacks. The main drawback of the voltage-fed ZSI is that the input current is discontinuous in the boost mode and the capacitors must sustain at a high voltage, while the main drawback of the current-fed ZSI is that the inductors must sustain high currents. The quasi-Z-source inverters (qZSIs) have been proposed in [2] to further improve on the traditional ZSIs. Besides the advantages inherited from the ZSIs, the qZSIs also have their own merits, including reduced passive component ratings, continuous input current, a common dc rail between the source and inverter, and so on. Since the publication of ZSIs, the voltage-fed ZSI received more attention than the current-fed ZSI. The performance, control methods and applications of voltage-fed ZSI are well-investigated in [3]–[11]. Nevertheless, it has a significant drawback that cannot maintain bidirectional power flow. The bidirectional power flow can only be achieved by replacing the diode with a bidirectional conducting, unidirectional blocking switch [12]–[13]; however, in this case, the advantages of single-stage topology are missing. The current-fed ZSI/qZSI, unlike the voltage-fed ZSI/qZSI, is bidirectional with a diode. The regeneration capability with a single-stage configuration makes the current-fed ZSI/qZSI a competitive power converter topology. Moreover, with the newly developed reverse blocking IGBT (RB-IGBT), the CSI is becoming more efficiency and thereby more attractive [14], [15]. 1 1.1. Problems of conventional current source inverter topology I in L1 S1 S3 S5 Vin S 4 S6 S 2 a b c Figure 1.1. Conventional IGBTs and series diodes based CSI The conventional current-source inverter as shown in Figure 1.1 has two major problems: unidirectional power flow and voltage boost operation, which make it impossible to be used in many applications, such as hybrid electric vehicles and general purpose variable-speed motor drives. The CSIs are less investigated and applied, compared to the VSIs, partly because the switches of the CSI have to be reverse blocking. If IGBTs are used for the current-source inverter, the reverse blocking capability can only be achieved with diodes connected in series to the IGBTs as shown in Figure 1.1. This yields to relatively high semiconductor conduction loss. The newly developed RB-IGBT has the symmetrical voltage blocking characteristic. That is, it can block both forward and reverse voltage in its off state [14], [15]. The improvement of the semiconductor switches has made CSIs more attractive in several applications, as in uninterrupted power supplies (UPSs), ac drives and reactive power compensators due to its intrinsic output short-circuit protection, ruggedness and direct current control ability [16-17]. The conventional CSI has nine possible switch states, of which three are zero states (vectors) and six are active states. Three zero states can be assumed by turning ON an upper 2 switch (S1, S3 or S5) and a lower switch (S4, S6 or S2) from the same phase-leg. Six active states can be assumed by turning ON the switches from different phase-legs. A relationship between the rms value of output phase voltage ( Vo ), power factor ( cos  ), input dc voltage ( Vin ) and the modulation index ( m ) can be determined: Vo  2 2Vin 3 3m cos  (1.1) Equation (1.1) indicates the CSI can only boost voltage. For a given power factor load, decreasing m leads to higher output voltage, as in the boost converter the increment of the duty cycle leads to higher output voltage. When m is the maximum value (i.e. m  2 we can get minimum output ac voltage, Vo _ min  3 ), 2Vin . Let’s define two operation modes: 3cos  motoring operation (power flows from dc side to ac side) and energy regeneration operation (power flows from ac side to dc side). If cos   0 , the CSI can draw energy from ac side to dc side. However, the polarity of the input voltage in motoring and in energy regeneration operation is opposite from each other. Since the input voltage source, such as battery, cannot change the polarity in practice, the CSI is effectively unidirectional. In conclusion, the conventional CSI has two major problems: unidirectional power flow and voltage boost operation, which makes it impossible to be used in many applications such as hybrid electric vehicles (HEVs) and general purpose variable speed motor drives. 1.2. Problems of conventional current source inverter modulation 3 β  I 2 ( S1S2 )  I 3 ( S 2 S3 )  I T1  I1 T  I 8 ( S3S6 )  T2  I2 T  I 4 ( S3S4 )  I 1( S6 S1)   1 I 7 ( S1S4 ) I 9 ( S5 S2 )  I 6 ( S5S6 )  I 5( S4 S5 ) Figure 1.2. Space vectors of the CSI (For interpretation of the references to color in this and all other figures, the reader is referred to the electronic version of this dissertation) There are many kinds of modulation methods for current source inverter and voltage source inverter proposed previously. There are two basic types of modulation methods: carrier based regular sampled method (including continuous PWM[18-23] and discontinuous PWM[24-28]); space vector PWM control [27, 29-31]. Paper[22] utilized master and slave references to be compared with carrier directly to generate a switching pattern instead of using mapping method [20], but it didn’t reduce switching frequency or increase current utilization compared to SVPWM control. Paper[26] proposed two generalized discontinuous carrier-based pulse width modulation (GDPWM) methodologies for CSI to reduce the switching frequency further by 1/3. However, the discontinuous PWM introduces higher harmonics in the output and also higher temperature variation of the device package. paper[28] presented a vector PWM method to minimize the switching loss, by placing zero vector at proper sector and by injecting triplet harmonics. Similarly for current source inverter, the zero vectors can be intentionally arranged to bring down the switching loss. 4 Paper[24] presented a dead-band PWM pattern which makes a 33% switching frequency reduction for a equivalent harmonic spectrum, compared to SPWM, but it has the same problem as DPWM. Paper[34] concluded that the third harmonic injection method is better for low modulation but modified SPWM is better for high modulation in terms of harmonic and ripple current. Various types of Z-source inverter modulation have also been proposed in the old literatures. Papers [1, 4, 32-33] proposed the carrier-based PWM control method. Paper [4] presented a method utilizing the maximum shoot through duty ratio in order to achieve minimum voltage stress on active devices; however, the varied shoot through duty cycle may introduce six times base frequency harmonics in output. In order to overcome this problem, paper [32] proposed a maximum constant boost control which injects a zero sequence voltage in the reference to make the shoot through duty cycle constant. Papers [1, 33] presented a method which inserts the open zero state into the edge of PWM, in order to reduce the number of switching, however, it may cause larger power loss due to multiple times of diode reverse recovery. The evaluation process for different modulation methods has been researched by many papers [27, 35-38]. Basically the evaluation criteria includes switching losses[84, 27, 28, 38-40], current/voltage ripple[34], harmonics[29, 36, 41, 42] and implementation complexity. PWM sequence is defined as a function of modulation index and power factor. From the state average point of view, each switching vector can be displaced anywhere within the switching cycle because the displacement has no effect on the amp-second average of the resulting current pulses corresponding to the reference vector[39]. The sequence of switching 5 vectors should minimize the inverter switching loss, inductor current ripple and output voltage/current harmonics[31]. Paper[39] presented several kinds of switching sequences such as FSM, HSM, MHSM, MFSM, CSVM, and also concluded that CSVM is better than others if M<0.64. This dissertation selects the SVPWM control to achieve higher input current utilization, lower switching loss and lower total harmonic distortions. For both voltage-fed and current-fed Z-source inverter, there are four switching states at any switching cycle, including two active states, one short zero state (shoot through state in voltage-fed Z-source inverter), and one open zero state. So there is more flexibility to arrange them to get the same volt-second equation, but different performance. In the modified SVPWM control method for this circuit, different PWM sequences can lead to different switching loss, current ripple, total harmonic distortion, and also the voltage spike on the switching devices. For each optimizing target, several rules which results in better performance have been summarized. A group of sequences have been sieved according to these rules. A complete analysis has been given to select the optimized sequence. In order to further reduce the switching loss in the inverter, a space vector pulse-width-amplitude modulation (SVPWAM) has been proposed. If it is used in voltage source inverter, a front stage dc-dc converter is needed to generate a variable dc link voltage, and then fed to inverter. In HEV/EV motor drive application, the two stage boost-converter-inverter is a classical topology, since the battery voltage is designed to be lower or equal to half of the motor drive input voltage. Also because of this boost converter, the dc link voltage of inverter is possible to be controlled. A 1kW boost-converter-inverter 6 system is built here to demonstrate the power loss reduction of SVPWAM. Both simulation and experimental results are given. Secondly, for SVPWAM application in current source inverter, the topology “current-fed quasi-Z-source inverter” is selected to be a representative of a voltage buck/boost current source inverter. The dc link voltage can be controlled to be desired variable voltage by regulating the extra control freedom “open zero state duty cycle”. Simulation results are given to demonstrate the power loss reduction in this CSI case. 1.3. Topology synthesis literature The increasing diversity of possible applications and the continuous demand for smaller, lighter and more efficient power converters have spurred the interest in fundamental topological properties of PWM converter and the construction of new converter topologies. Converter synthesis method is procedure to generate a converter to implement the desired functions, which is also useful for getting a better understanding of conversion principles. A number of previous works related to the problem of synthesis have been reported, most of them are related to DC-DC conversion. Several circuit manipulations have been sued for converter synthesis: cascade connections of existing converters [45]; duality transformations [46, 47], inversion of source and the load [129], differential or parallel connections of two converters [129], recognition of topological properties and constrains [122-125], canonical switching cell [126-127]. An analytical approach for generating switched-mode converters is proposed in [130], the main idea of which is to find an algebraic representation for the converter topology so that synthesis of complete classes of converters can be reduced to synthesis of all possible algebraic representations. To extract the useful topologies in this method, some general properties and conditions for dc-dc conversion are established 7 [131-132]. In [133] and [134], there is a reexamination about the fundamental topological assumptions on PWM converters. This dissertation also tries to investigate the synthesis techniques for inverter topology and develop new topologies based on that. Some dc-dc conversion topology derivation technique have been reviewed and summarized first. One inverter derivation technique is summarized from the Z-source inverter topology. It has been applied on various types of basic dc-dc converter topologies and new converters with desired properties has been found. A new family of switched-coupled-inductor inverters has been proposed in this dissertation, with voltage buck-boost function. In voltage-fed switched-coupled-inductor inverter, a boost function can be implemented by introducing an extra shoot-through state on the inverter bridge. It utilizes the same principle as the Z-source inverter, but has higher boost ratio and lower active device voltage stress at the same voltage gain. It also has wider voltage buck/boost range than conventional boost-converter inverter. In current-fed switched-coupled-inductor inverter, a buck function can be implemented by introducing an extra open zero state on the inverter bridge. The current-fed topologies are capacitor-less solution among the buck-boost inverters, which reduces the system size significantly. In addition, compared to traditional boost-converter-inverter, it has less switch count, and less active device current stress. Compared to current-fed Z-source inverter, it has higher boost ratio and lower active device current stress. The inverter can sustain minimum voltage and current stress at a certain operation point, through adjusting the trans-ratio and the shoot through/open circuit duty cycle. The simulation results are given to verify the theory analysis and demonstrate the great merits of the switched-coupled-inductor inverter. It is beneficial to 8 be applied in dc-ac applications that demand a high voltage gain from a very low voltage dc source, such as the micro-inverter in photovoltaic, or G/M in HEV 1.4. Problems of traditional direct matrix converter The matrix converter (MC) is a direct ac/ac converter with sinusoidal input/output waveforms and controllable input power factor [49-51]. It has less passive component compared to the existing back-to-back converter. Its control methods, circuit operation and possible applications have been investigated in paper [52-70]. It has a good perspective especially when the reverse-blocking IGBT is available now. In a traditional matrix converter, the three switches on the same output phase leg can not be gated on at the same time because doing so would cause a short circuit(shoot through) to occur, which would destroy the converter. In addition, the maximum voltage gain can not exceed 0.866. These limitations can be overcome by Z-source matrix converter [1], which adds an ac impedance network (Z-network) in the input. The Z-source matrix converter advantageously utilizes the shoot through states to boost the ac voltage by gaiting on three switches on the same output phase leg, to boost the voltage to be greater than the input voltage. In addition, the reliability of the converter is greatly improved because the shoot through states can no longer destroy the circuit. The commutation steps can be simplified. Therefore, it provides a low-cost, reliable, and efficient structure for buck and boost ac/ac conversion. 1.5. Scope of the thesis This dissertation focuses on the following subjects: Chapter 2 explores the topology synthesis process for voltage/current-fed Z/quasi-Z/trans-Z 9 source inverter, direct Z-source matrix converter family, and proposes a new family of topology “switched-coupled-inductor inverter”, to provide a high boost ratio and compact solution for HEV/EV motor drive. Chapter 3 presents a comprehensive circuit analysis of five topologies: current-fed quasi-Z-source inverter, current-fed Z-source rectifier, switched-coupled-inductor inverter and Direct Z-source matrix converter. It includes the equivalent circuit states, voltage and current gain, operation regions, calculation of ac output voltage and current, passive component stress and active switch device power rating. Chapter 4 presents two modulation methods for current source inverter both in SVPWM point of view: DPWM and CSVPWM, and proposes the third method PWAM, all of which is based on different selection and placement of zero vectors. The different switching sequences are proposed and compared in terms of spectrum, THD and switching loss. Chapter 5 proposes the zero vector placement technique in SVPWM control of Z-source inverter, in order to achieve lower harmonics, lower switching loss, lower voltage spike and lower current ripple and also demonstrates it through a 24 kW current-fed quasi-Z-source inverter prototype experiments. Chapter 6 analyzes the switching loss reduction function and harmonic performance of SVPWAM method which has been proposed in chapter 4 for both VSI and CSI, through the 10 case studies. A 1kW boost-converter-inverter prototype has been built to experimentally demonstrate the stated advantages of the method. Chapter 7 proposes three shoot through control methods and the hybrid minimum stress control method for direct Z-source matrix converter family and demonstrates them through experiments. Chapter 8 presents the two new found discontinuous operation modes for current-fed quasi-Z-source inverter when the power factor is low or capacitance is small, and analyzes the capacitor voltage waveform and the critical conditions for this circuit at different modulation methods. Chapter 9 proposes the large signal and small-signal circuit model for current-fed quasi-Z-source inverter, current-fed Z-source rectifier and switched-coupled-inductor inverter. The transient performance of the first topology has been investigated and demonstrated through experiments. Chapter 10 discusses the major contributions of this dissertation and the future work recommendations. 11 CHAPTER 2 CURRENT SOURCE INVERTER TOPOLOGIES 2.1. Introduction The increasing diversity of possible applications and the continuous demand for smaller, ligher and more efficient power converters have spurred the interest in fundamental topological properties of PWM converter and the construction of new converter topologies. Converter synthesis method is procedure to generate a converter to implement the desired functions, which is also useful for getting a better understanding of conversion principles. A number of previous works related to the problem of synthesis have been reported, most of them are related to DC-DC conversion. Several circuit manipulations have been sued for converter synthesis: cascade connections of existing converters [45]; duality transformations [46-47], inversion of source and the load [129], differential or parallel connections of two converters [129], recognition of topological properties and constrains [122-125], canonical switching cell [126-127]. An analytical approach for generating switched-mode converters is proposed in [130], the main idea of which is to find an algebraic representation for the converter topology so that synthesis of complete classes of converters can be reduced to synthesis of all possible algebraic representations. To extract the useful topologies in this method, some general properties and conditions for dc-dc conversion are established [131-132]. In [133] and [134], there is a reexamination about the fundamental topological assumptions on PWM converters. The purpose of this chapter is to investigate the synthesis techniques for inverter topology and develop new topologies based on that. Some dc-dc conversion topology derivation technique have been reviewed and summarized first. One inverter derivation 12 technique is summarized from the Z-source inverter topology. It has been applied on various types of basic dc-dc converter topologies and new converters with desired properties has been found. Most importantly, a new family of switched-coupled-inductor-inverter topology has been proposed to implement high boost ratio single stage buck-boost function. It has less switching count, smaller passive size and less device stress than the other topologies with the same function. 2.2. Topology synthesis techniques 2.2.1. Graph theory Figure 2.1 Twelve basic dc-dc converter topology from graph theory In 1970s, based on the switching mode converter concept proposed by professor Middlebrook, various kinds of methods are proposed for topology derivation. The Caltech group proposed the mathematic method to derive topology based on connection matrix and the basic rules for the circuit existence [131]. They even developed the computer program to exhausting all the possible two state or three states converter topologies. A Poland professor 13 proposed how to derive the basic dc-dc converter from graph theory [122]. Figure 2.1 is a review for the twelve basic topology derived from the graph theory. They are classified into three categories. In the first group, the two trees are voltage source-capacitor branch and a dot; three circuits are formed by connecting the dot to two different nodes in the first tree, in which the connections means the switch. In second group, another branch is a two node capacitor; three circuits are formed by connecting the two nodes to a single node in the first tree. In third group, the branches are the same as the second group; but the two nodes are connecting to two different nodes in the first tree, to form six circuits. It is found that the Z-source and quasi-Z-source dc-dc converter appear in the last group. 2.2.2. Duality 14 Figure 2.2.Current source dc/dc converter from duality of voltage source converter In electrical circuits, electrical terms are associated into pairs called duals. A dual of a relationship is formed by interchanging voltage and current in an expression. The following is the list of electrical dualities: voltage and current; parallel and serial; resistance and conductance; impedance and admittance; capacitance and inductance; reactance and susceptance; short circuit and open circuit; Kirchhoff’s current law and Kirchhoff’s voltage law; Thevenin’s theorem and Norton’s theorem. Figure 2.2 listed some classical duality examples and also proposed the new duality circuits. As well known, Cuk converter is the dual of buck-boost converter. The voltage 15 source parallel resonant converter and current source one are dual. It is found that the recently proposed Z-source converter family also has dual circuit. The voltage-fed Z-source converter is dual of current-fed quasi-Z-source converter; the voltage-fed quasi-Z-source converter is dual of current-fed Z-source converter. This also means the derivation of previously proposed quasi-Z-source topology can start from applying duality on Z-source topology. As shown in Figure 2.1 the dotted line, the duality principle is like this: mesh is transformed into node; inductor changes to capacitor; capacitor changes to inductor; resistance becomes admittance; voltage source becomes current source, and the direction obeys right hand discipline. For the switch, it is special. Actually for duality circuit derivation, each switching state equivalent circuit needs to be transformed. For example, the two state dc-dc converter in Figure 2.1 left hand side. The duality needs to be applied to each state. Thus the switch is either on or off in each state. To transform to dual circuit, the switch on state needs to be changed to off; and off state needs to be changed to on. Thus the dual circuit for each state could be obtained. Finally, they are combined into one switching circuit. 2.2.3. Bilateral inversion transformation 16 Inverse Boost Buck Inverse Inverse up zeta down Inverse New 1 SEPIC Inverse Quasi-Z-Source New 2 Z-source Figure 2.3. DC/DC converter derivation from inverse transformation By inversing the input and output, a new group of dc/dc converter topologies can be derived from the existing 12 structures in Figure 2.1, as shown in Figure 2.3. The resulting voltage gain is equal to the inverse of the gain of the original circuit on the left. The original circuit which conducted quasi-Z-source and Z-source dc/dc converter is also featured as a buck-boost converter, with the voltage gain equal to 1  2D . 1 D 2.2.4. Cascade (a) Boost + Boost (b) Boost + Forward (c) Boost + Flyback Figure 2.4. Topologies generated by cascading basic circuit If the number of switches is allowed to exceed two, more combinations of circuits can 17 bring the advanced features. Like the ones shown in Figure 2.4, the cascade connection of the circuits increase the circuit boost ratio, and also add some new features such as isolation to the circuit. A good design makes them all only utilize one active switch. 2.2.5. Parallel (a) Multi-level current source inverter/converter (c) Interleaved boost converter (b) Multi-level CSI (d) Two level boost converter Figure 2.4. Topologies generated by paralleling basic circuit Another technique is paralleling circuit, in order to reduce the current stress, or form a interleaved circuit, or reduce the current ripple. Figure 2.4 lists some examples of the parallel connection. The multilevel voltage or current source converter/inverter is utilizing this parallel technique, as well as the interleaved converter. 2.2.6. With transformers 18 Buck Boost Cuk SEPIC Zeta (a) Isolated version of basic dc-dc converter Figure 2.5 Topologies derived from adding isolation transformer between input and output 19 Figure 2.5 (cont’d) (b) Coupled-inductor isolated basic dc-dc converter In some applications, the isolation between input and output is required, such as PV inverter. The isolated transformer can be used here to implement this goal. The place to add this transformer is the node that has zero voltage. Thus the transformer will not change the basic operation states of the circuit. There are two methods to apply the isolation: one is by transformer like Figure 2.5 (a) shows; the transformer is inserted between two capacitors, which are the split single capacitor in the original circuit; another is by coupled inductor like Figure 2.5 (b) shows; a single inductor is changed to coupled inductor with opposite coupling; 20 the energy will transform from one inductor to another one completely depending on the switching state. The new finding here is that: the so called “Walking-Johnson” circuit is derived from boost converter; the so called “Inverse Walking-Johnson” circuit is derived from buck converter; the flyback circuit is derived from buck-boost converter. The feature of this inductor that can be transformed is one of its terminals is connected to two complementary switch. 2.2.7. Extension of canonical switching cell Figure 2.6. Topologies derived from adding isolation transformer between input and output Another important technique to extend the converter topology is “switching cell”. If the number and kinds of passive components, and the number of switches are fixed, several different structures of switching cells can be constructed. Except for those that does not obey the basic circuit rule, each switching cell can be used for constructing several topologies, depending on the way to connect the source and load to it. Figure 2.6 lists some examples of the topologies deriving from the switching cells. They are referred to paper []. All those 21 mentioned topologies derived from duality, inversion and graph theory can all be derived by playing the switching cell. 2.3. Derivation of buck-boost Z-source inverters = 1 D 1-2D Voltage-fed quasi-Z-source Inverter 1 1 D 1-2D Voltage-fed quasi-Z-source Inverter 2 1 D 1-2D Voltage-fed Z-source Inverter 1 D D New buck-boost Inverter 1 1 n n Gv  1 D 1 1  (1  ) D n Inverse Walking-Johnson Voltage-fed tans-Z-source inverter Figure 2.7. Voltage-fed Z-source inverter topologies derived from basic dc-dc converter (D is the shoot through duty cycle, Gv is the voltage gain between output equivalent voltage and input) The voltage-fed Z-source inverter can all be derived from the converter, as Figure 2.7 shows. The left hand side of this figure shows the circuit (10),(12)，inverse-walking-Johnson 22 and (8) from the basic circuits in Figure 2.1. From dc-dc converter to inverter transformation, one special technique is used here: replacing one switch by inverter bridge. Thus the on state of this switch is corresponding the shoot through of the inverter bridge, the off stat of this switch is corresponding to the active and open zero state of the switch. For each dc-dc circuit, there are two ways of doing this replacement since they have two active switches. But some of new inverters do not have the voltage buck-boost function. As shown in Figure 2.7, the voltage-fed quasi-Z-source inverter is derived by replacing the lower switch of the left circuit by the voltage source inverter bridge. Similarly, another voltage-fed quasi-Z-source inverter topology and the voltage-fed Z-source inverter topology are obtained by replacing different switches in the left dc-dc converter respectively. These three Z-source topologies, their voltage gains are all (1  D) / (1  2 D) , which is a buck-boost function with the variation of D. The fourth inverter is the recently proposed voltage-fed tans-Z-source inverter[], which has extended voltage gain range than traditional Z-source inverter because of the trans-ratio. It can be derived by replacing one of the active switches in the inverse-Walking-Johnson circuit by an voltage source inverter bridge. This circuit works similarly to Z-source inverter, but with higher boost ratio. The energy transfers from one winding to another winding in the coupled inductor at different switching states. The fifth inverter is a new found circuit here, which is also a buck-boost inverter with gain (1  D) / D , from the transformation of the left side dc-dc circuit, which is also one of the basic 12 circuits. In summary, from this derivation principle, it can be seen that the inverter bridge has an extra shoot through state, in which all the switches are turned on. The more this shoot through state is applied, the more the voltage can be boosted. 23 The feature of this group is that all the circuits are the single-stage buck-boost inverter with only one diode in front. The advantages are: (1)voltage buck-boost function (2) shoot-through can be tolerated (3) less active switch (4) coupled-inductor can be utilized to reduce the size. The disadvantages include: (1) high current stress on the bridge switch (2) increased number of passive components.         Figure 2.8. Current-fed Z-source inverter topologies derived from basic dc-dc converter (CF=current-fed; ZSI=Z-source inverter QZSI=quasi-Z-source inverter) Table 2-1.Voltage gain of current-fed Z-source inverter topologies in Figure 2.8 Circuit CF-ZSI CF-QZSI CF-QZSI2 CF-trans-ZSI Voltage gain 1  2 Dop 1  2 Dop 1  2 Dop 1  (1  n) Dop DA DA DA DA The current-fed Z-source/quasi-Z-source/trans-Z-source inverter also can all derived 24 from the basic dc-dc converters, as shown in Figure 2.8. For current source inverter bridge, the corresponding unit in dc-dc converter is a series combination of one active switch and one capacitor, because the switch is equivalent to inverter bridge, and the capacitor is equivalent to output capacitor. The first dc-dc circuit generates current-fed Z-source inverter; the second dc-dc generates two current-fed quasi-Z-source inverters; the last group the current-fed walking-johnson dc-dc converter is first derived from the voltage-fed one, and then by using the same technique, the current-fed trans-Z-source inverter is derived. Therefore, the off state of the corresponding switch in dc-dc converter is transferred into the extra open zero state of current source inverter, which is not allowed in the traditional current-source inverter. This extra state brings the buck function to CSI, just as the voltage gain shown in the Table 2-1. DA represents active duty cycle, which is proportional to modulation index. And Dop represents extra open zero state duty cycle. The feature of this group is that all the circuits are the single-stage buck-boost current source inverter with only one diode in front. The advantages are: (1)voltage buck-boost function (2) regeneration with only a diode (3) open-circuit can be tolerated (4) less active switch (5) both output voltage and current are sinusoidal (6) coupled-inductor can be utilized to reduce the size. The disadvantage is high voltage stress on the bridge switch. 2.4. Newly derived inverter topologies with buck-boost function From other basic or extended dc-dc converters, by applying the same technique, some new topologies are derived here, as shown in Figure 2.9. Inverter (a) and (b) are similar, both of which have the mixed voltage/current source. The disadvantage of these two inverters is high voltage and current stress on the front active switch. Inverter (c) and (d) is buck-boost 25 Voltage gain Boost Gv  1 D D SEPIC 1 (a) Gv  Zeta 1 D D (b) 1 WalkingJohnson Gv  n 1 D Dn Gv  n 1 D n D (c) 1:n Flyback (d) Figure 2.9. New inverter topologies with buck-boost functions derived from basic dc-dc converter (D is the shoot through duty cycle, Gv is the voltage gain between output equivalent voltage and input) inverter with trans-ratio n. The coupled inductor implements two functions: isolation and voltage regulation. From the voltage gain equation, it can be found that it has one more control freedom, the trans-ratio n. Thus wider voltage buck/boost range can be achieved. Also for a certain voltage gain equation, the duty cycle D and trans-ratio n can be tuned at the same time to minimize the voltage and current stress on either active device or passive. 26 2.5. Proposed switched-coupled-inductor inverter family with buck/boost function 1:n 1 S2 n S1 S1 S2 1 n S2 S2 is D0 : G  (1  D0 ) 1  nD0 (a) G 1 M 1+nD0 (1  D0 )(n  1) (1  D0 )n  1 G (d) 1 1:n S1 G S1 S2 n 1 M (1  D0 )n  1 1 n S2 S1 n S2 G 1  D0 1-nD0 G (b) 1 n 1-D0 ) （ M (11, it can buck the voltage; when n goes to even bigger that n  1 , it enters into regeneration mode. D0 70 In each state, the similar state space equations can be built. The voltage gain, active and passive device stress can all be derived from the state equations. All the equations for current-fed switched-coupled-inductor inverter family are derived and demonstrated by simulation. They are shown in Table 3-3. 3.4.2.3. Voltage and current stress comparison The comparison among voltage-fed switched-coupled-inductor inverters are shown in Figure 3.17.The features of the family of voltage-fed SCI inverter are: (1) Only SCI 2, 4, 5 have boost function; (2) VF-SCII 2 has higher voltage stress than VF-SCII 5 when boost ratio is over 2, but VF-SCII 2 has lower current stress than VF-SCII 5 in the same condition. VF  SCII 2,5 n2 VF  SCII 1 VF  SCII 3 MB VF  SCII 4 & 6 0.6 0.8 M 1 1.2 (a) Voltage gain(MB) versus modulation index for voltage-fed switched-coupled-inductor inverter at n=2 Figure 3.17. Comparison among the voltage-fed switched-coupled-inductor inverters 71 Figure 3.17 (cont’d) 2.5 2 VF  SCII 2 VF  SCII 4 VF  SCII 5 n2 1.5 1 0.5 0 2 4 6 8 10 MB (b) Active switch voltage stress of voltage-fed switched-coupled-inductor inverter 1.5 n=0.5 1 VF-SCII 1 VF-SCII 2 VF-SCII 3 VF-SCII 4 VF-SCII 5 VF-SCII 6 MB 0.5 0 0.6 0.7 0.8 0.9 1 1.1 1.2 M (c) Voltage gain vs. M for voltage-fed topologies at n=0.5 72 Figure 3.17 (cont’d) 1 VF-SCII 2 VF-SCII 4 Vstress/MB 0.8 n=0.5 VF-SCII 5 0.6 0.4 0.2 0 2 4 6 MB 8 10 (d) Active switch voltage stress for voltage-fed topologies 1 n=0.5 Istress/MB 0.8 VF-SCII 2 VF-SCII 4 0.6 VF-SCII 5 0.4 0.2 0 2 4 6 MB 8 10 (e) Active switch current stress for voltage-fed topologies The comparison among the current-fed switched-coupled-inductor inverters are shown in Figure 3.18. The plot of voltage gain versus the modulation index and current stress versus voltage gain are shown in two cases: n=0.5 and n=2. When n=0.5 is chosen, inverter 1, 2, 3, 4, 6 all have voltage boost function. And inverter 4 and 6 have the lowest current stress among the five, at all gains bigger than 2. When n=2 is chosen, inverter 1, 3, 6 have voltage boost function, and the others can only buck voltage. Among the ones with boost function, 73 current-fed inverter 1 has much lower current stress than the other two. Since the voltage gain of current-fed switched-coupled-inductor inverters is a function of multiple variables: trans-ratio, open zero duty cycle and modulation index. Different trans-ratio and open zero duty cycle can be chosen to obtain minimum active switch or passive component voltage/current stress, at a certain voltage gain requirement. 3 CF-SCII 3 CF-SCII 4 CF-SCII 5 CF-SCII 6 n=0.5 CF-SCII 1 CF-SCII 2 2 1 0 -1 0.6 0.7 0.8 0.9 M 1 1.1 1.2 (a) Voltage gain vs. M at n=0.5 for current-fed topologies 6 n  0.5 5 CF  SCII 1 4 CF  SCII 2 CF  SCII 3 3 CF  SCII 4 CF  SCII 5 2 1 0 CF  SCII 6 2 4 6 MB 8 10 (b) Current stress vs. voltage gain at n=0.5 for current-fed topologies Figure 3.18. Comparison among the current-fed switched-coupled-inductor inverters 74 Figure 3.18 (cont’d) CF SCII 1 CF SCII 2 n2 CF SCII 3 CF SCII 4 CF SCII 5 CF SCII 6 (c) Voltage gain vs. M at n=2 for current-fed topologies 6 n=2 5 4 3 CF SCII 1 CF-SCII 3 CF-SCII 6 2 1 8 0 2 6 MB 4 8 10 (d) Current stress vs. voltage gain at n=2 for current-fed topologies The comparison between voltage-fed switched-coupled-inductor inverter and voltage-fed Z/quasi-Z-source inverter are shown in Figure 3.19. The comparison target is the voltage stress over voltage gain ratio at the same voltage gain. Among the buck-boost inverter topologies, voltage-fed Z/quasi-Z-source inverter has been found a good topology that has low cost, high reliability and low voltage stress. Thus the comparison has been made 75 between voltage-fed switched-coupled-inductor inverter 5 and voltage-fed Z/quasi-Z-source inverter. Their voltage stress versus voltage gain are shown in Figure 3.19. It can be seen that at the same voltage gain above 1, the proposed topology has lower voltage stress, which can Voltage stress/equivalent dc voltage bring lower cost and higher efficiency. Figure 3.19. Voltage stress vs. voltage gain at n=0.5 for both voltage-fed switched-coupled-inductor inverter and voltage-fed Z/quasi-Z-source inverter Comparison of voltage gain has been conducted between current-fed switched-coupled-inductor inverter and current-fed quasi-Z-source inverter, as shown in Figure 3.20. Recently published current-fed quasi-Z-source inverter also has similar voltage buck-boost function as the proposed current-fed SCII. By using active switch in front, both topologies have no upper limitation for the voltage gain. However, in terms of active switch current stress, the proposed topology has the same current stress as the current-fed qZSI in boost mode, but lower current stress in buck motoring mode and regeneration mode. The reason is for the two mentioned modes, at the same voltage gain, the current-fed SCII is 76 possible to use bigger modulation index, which brings smaller open zero duty cycle. According to equations in Table 3-3, lower active switch current stress can be obtain by decreasing the open zero duty ratio. In summary, compared to current-fed quasi-Z-source inverter, the current-fed switched-coupled-inductor inverter is more compact due to its capacitor-less feature, and has lower switch current stress at buck motoring and regenerative mode. Figure 3.20. Voltage boost ratio B versus active duty cycle DA (0.866M) for current-fed qZSI and current-fed switched-coupled-inductor inverter 3.5. Direct Z-source matrix converter A family of direct Z-source matrix converter (MC) is shown in Figure 2.12. For voltage-fed (VF) Z-source MC, its voltage gain can only reach 1.15, and also the phase shift caused by the Z-network makes the control not accurate. But for voltage-fed quasi-z-source matrix converter, there is no upper and lower limit for voltage gain, and in addition, the phase shift at two sides of quasi-Z-network is equal to zero, which can cause much less error in the 77 control. One of the quasi-Z MC topologies has continuous input current, which is beneficial to the input voltage source. Compared to traditional MC, voltage-fed Z-source and quasi-Z-source matrix converter both can boost voltage higher than 0.866. The boost ratio depends on the duty cycle of extra shoot through state, which has constrain that it is complementary with active state duty cycle. Z-source topology has lower voltage gain range than quasi-Z-source topology. Also the quasi-Z-source topology can conduct less voltage/current stress on the switch and passives, less input and output harmonics and higher power factor than Z-source matrix converter. In another word, compared to Z-source topology, quasi-Z-source matrix converter is a component less, size compact, high efficient, wide range buck-boost matrix converter. The boost ratio is derived for both topologies as follows. 3.5.1. Voltage-fed Z-source matrix converter Compared to matrix converter in circuit structure, Z-source matrix converter has extra L-C network and three switches in the input side. Compared to matrix converter in circuit states, the Z-source matrix converter has an extra shoot through state except the traditional 27 switching states of matrix converter. Figure 3.22 (a) and (b) show the two equivalent circuit states. In the shoot through state, the three switches on the same column, or two columns or all three columns will short together. At the same time, the front three switches are controlled to be open. In non-shoot through state, the front switches are turned on, and matrix converter part works like traditional case. The introduction of Z-source network into the conventional matrix converter is equivalent to cascade a boost converter in the front stage. The boost ratio of Z-source network can be derived by applying the volt-seconds balance on the Z-source inductors in the 78 state average model of the equivalent simplified ZS matrix converter [28]. Figure 3.21. Voltage-fed Z-source matrix converter a' b' c' (a) I: active state a' b' c' (b).II: shoot through state Figure 3.22. Equivalent circuit states of Z-source matrix converter For one switching cycle, Tc , assuming the interval of shoot-through state is T0 ; and the total interval of non-shoot-through states is T1 ; thus Tc=T0+T1 and the shoot-through duty ratio, D=T0/Tc. From Figure 3.22 (a), during the interval of non-shoot-through states, T1, one 79 has the following voltage equations: vab   vC1  v L 2   v   v    v   bc   C 2   L3   vca   vC 3   vL1        (3.48) vab   vC1   vL1   v   v   v   bc   C 2   L 2   vca   vC 3   vL3        (3.49) , where vL1 , vL 2 and vL3 are the voltages across the inductors L1, L2, and L3, respectively; vC1 , vC 2 and vC 3 are the voltages across the capacitors C1, C2, and C3 , respectively. vab ,vbc , and vca are the line-to-line voltages of the source and va’b’, vb’c’, and vc’a’ are the line-to-line voltages across the MC bridge. From Figure 3.22 (b), during the interval of the shoot-through states, T0, one can get  vC1   vL1  v   v   C 2   L2   vC 3   vL3      (3.50) In steady state, the average voltage of the inductors over one switching cycle should be zero, neglecting fundamental voltage drop and assuming the switching frequency is far greater than the fundamental frequency. From (3.48) and (3.50), one has DvC1  (1  D)(vC 3  vca )  0 DvC 2  (1  D)(vC1  vab )  0 (3.51) DvC 3  (1  D)(vC 2  vbc )  0 From (3.49) and (3.50), one has vC1  (1  D)vab vC 2  (1  D)vbc vC 3  (1  D)vca 80 (3.52) Assume that the source is a three-phase symmetric system, namely sin t vab     v   V sin(t  120 )   bc  i    vca  sin(t  120 )     (3.53) , where Vi and  are the voltage amplitude and angular frequency of the source. Assume the voltages across the capacitors have a phase difference C in reference to the source, i.e.,  sin(t  C )   vC1  v   V sin(t    120 )  C C   C2  sin(t  C  120 )  vC 3      (3.54) , where VC is the amplitude of capacitor voltages. Assume the voltage across the MC bridge has a phase difference m referred to the source, thus  sin(t  m )  vab   v   V sin(t    120 )  m m   bc  sin(t  m  120 )  vca      (3.55) , where Vm is the output voltage amplitude of Z-source network. From (3.51), (3.52), (3.53) and (3.54), we have  D sin(t  C )  (1  D) sin(t  C  120 )  sin(t  120 )     VC  D sin(t  C  120 )  (1  D) sin(t  C )   (1  D)Vi  sin t  (3.56)  D sin(t    120 )  (1  D) sin(t    120 ) sin(t  120 )  C C         Applying trigonometric functions, such as sin2t + sin2(t-120) + sin2 (t+120) =1.5, to (3.56), the relationship between the capacitor and source voltage amplitudes can be derived: 1 D VC  Vi 3D 2  3D  1 (3.57) So the boost ratio between Vm ' and Vm can be obtained: V ' 1 B m  Vm 3D02  3D0  1 (3.58) At the same time, the phase shift between source voltage Vabc and terminal voltage 81 Va' b' c' can be derived as: Z  arcsin 3D0 (3.59) 2 2 3D0  3D0  1 B( pu ) 2 1.8 1.6 1.4 1.2 1 0 0.2 0.4 1 0.8 0.6 D0 Figure 3.23.Voltage boost ratio B vs D0 for Z-source matrix converter (MC) Phase shift angle 80 Z  source MC 60 40 20 0 0 0.1 0.2 0.3 D0 0.4 0.5 0.6 0.7 Figure 3.24.Phase angle between Va,b,c and Va',b',c' for Z-source MC The maximum boost ratio 2 happens at D0  0.5 , as shown in Figure 3.23. Similarly to Z-source inverter, the voltage conversion ratio between output line voltage amplitude Vom and input Vm is: V M G  om  MB  Vm 3D02  3D0  1 82 (3.60) The phase shift between two voltage is a monotonic function of open zero duty cycle, as shown in Figure 3.24. The larger the D0 , the bigger the phase shift angle. This issue only happens at the topology in Figure 3.21 due to its twist structure of the Z-network. It is a disadvantage of this topology, because if the source voltage is taken as the reference waveform in generating the control PWM signal, this phase shift will cause the phase inaccuracy of the control signal. Of course, the terminal voltage can be taken as the reference waveform instead, however, this waveform is a discontinuous PWM type, which is hard to be used. Adding a low pass filter to purify the PWM waveform can create a smooth reference curve, but the filter itself also introduces a phase shift. This problem doesn’t exist in quasi-Z-source matrix converter topology, due to its phase-decoupled quasi-z-network structure. 3.5.2. Voltage-fed quasi-Z-source matrix converter a b c AC Source QZ source network A B C AC Load Figure 3.25. Voltage-fed quasi-Z-source inverter 83 a' b' c' (a) I: active state a' b' c' (b).II: shoot through state Figure 3.26. Equivalent circuit states for qZ-source MC As another example, the voltage-fed qZS-MC is deduced to compare its voltage gain with the simplified voltage-fed ZS-MC. During the interval of the shoot-through states, T0, the voltage-fed qZS-MC has equivalent circuits as shown in Figure 3.26 (b), and one can get vab  vCa1  vLa 2  vLb1  vCb 2   v   v   v    v    v   bc   Cb1   Lb 2   Lc1   Cc 2   vca   vCc1   vLc 2  vLa1  vCa 2            vCa1  vLa 2  vLa1  vCa 2  v   v   v   v   Cb1   Lb 2   Lb1   Cb 2   vCc1   vLc 2   vLc1   vCc 2          (3.61) (3.62) , where v denotes the voltage, and the subscript Cx1 and Cx2 are capacitors 1 and 2 of phase-x (x=a, b, c); Lx1 and Lx2 for inductors 1 and 2 of phase-x. During the interval of the non-shoot-through states, T1, its equivalent circuits is shown in Figure 3.26 (a), and one can get 84 vab  vCa1  vCa 2  vab  vCb1  vCb 2   v   v   v         bc   Cb1   Cb 2    vbc    vCc1    vCc 2   vca   vCc1   vCc 2   vca  vCa1  vCa 2              (3.63) vCa1  vLa1   v   v   Cb1   Lb1   vCc1   vLc1      (3.64) v La 2  vCa 2   v   v   Lb 2   Cb 2   vLc 2   vCc 2      (3.65) Due to symmetry of quasi-Z network, there are v La 2  vLa1  vCa1  vCa 2   v   v  ,  v   v   Lb 2   Lb1   Cb1   Cb 2   vLc 2   vLc1   vCc1   vCc 2          (3.66) In steady state, the average voltage of the inductors over one switching cycle should be zero, and (3.67) can be derived from (3.61), (3.64), and (3.66). vCb1  vCa1   v   v   D0  Cc1   Cb1  1  2 D 0 vCa1   vCc1      vab  v   bc   vca    (3.67) Due to symmetric voltages of three-phase capacitors, (3.67) becomes vCa1  vab  vca  v   D0 v  v   Cb1  6 D  3  bc ab  0  vCc1   vca  vbc      (3.68) Combining (3.63) in (3.68), there is vab  1 v    bc  1  2 D 0  vca    vab  v   bc   vca    (3.69) Similar to the process used for the simplified voltage-fed ZS-MC, the boost factor of the voltage-fed qZS-MC can be expressed as 1 V B m  Vi 1  2 D0 85 (3.70) From (3.68), the capacitor voltage amplitude is VC  D0 Vi 1 2 D0 (3.71) The phase shift between source and terminal voltage is: Z  0 Voltage gain 4 2 0 2 4 0 0.2 0.4 D0 0.6 0.8 1.0 Figure 3.27.Voltage boost ratio B vs D0 of voltage-fed quasi-Z-source matrix converter Phase shift angle 40 20 0 20 40 0 0.2 0.4 0.6 D0 Figure 3.28.Phase angle between Va,b,c and Va',b',c' for qZ-source MC The voltage boost ratio is plot as a function of D0 in Figure 3.27. This boost ratio is similar to the boost gain in quasi-Z-source VSI and quasi-Z-source dc/dc converter. The advantage of this topology is that there is no upper limit on the voltage boost ratio, thus it can bring the voltage much higher than Z-source MC topology. The phase shift between input source and the voltage at the terminals of matrix converter 86 is equal to zero, which is derived from equations, as shown in Figure 3.28. This is due to the decoupled quasi-Z-source network in qZ-source MC. There is no coupling between different phases. Also the small ac capacitor and inductor will not cause a big phase difference. This zero phase shift feature significantly reduces the control error. Thus the input current harmonics and output current harmonics are also minimized. 3.6. Summary In summary, the current-fed qZSI has the following advantages: 1) The current-fed qZSI can buck-boost voltage and achieve bidirectional power flow with a single stage configuration. 2) In motoring operation (power flows from dc source to ac side), the current-fed qZSI can work in region B as shown in Figure 3.5. The equivalent output voltage Vout  0 ~ 2Vin . 3) In energy regeneration operation (power flows from ac source to dc side), the current-fed qZSI can work in region C as shown in Figure 3.5, which can produce dc voltage from 0 ~ infinite theoretically. 4) By replacing the diode with a RB-IGBT, region A is also available for motoring operation which means the current-fed qZSI can completely overcome the voltage limitation and output any desired voltage theoretically in either motoring operation or energy regeneration operation. Because of the above advantages, the current-fed qZSI can be easily applied to HEVs and general purpose variable speed motor drives. Applying the current-fed qZSI in the HEVs as shown in Figure 3.1, both motor drive and the control of state of charge (SOC) of the battery can be implemented in a single stage configuration, which is less complex, more reliable and more cost effective when compared to conventional 87 two-stage configuration (i.e a bidirectional dc-dc converter combined with a VSI). In summary, the current-fed Z-source PWM rectifier has the following advantages: 1) It can buck/boost voltage which provides a wide range of output voltage as shown in Figure 3.9; 2) The bidirectional power flow can be achieved without replacing the diode with a bidirectional conducting, unidirectional blocking switch. 3) The current gain has a wide range from 1 to minus infinity theoretically. 4) The voltage gain can be varied by adjusting two independent degrees of control freedom, the duty ratios of active state and open zero state. The current gain can be varied by adjusting duty ratio of open zero state. In summary, for the proposed new family of buck-boost inverter topologies: voltage/current-fed switched-coupled-inductor inverter (SCII). The following features have been demonstrated by circuit fundamentals analysis and simulations: (1) At the correct selection of trans-ratio n and extra switching state duty cycle, both voltage/current-fed topologies have candidates that can buck-boost voltage. (1) Voltage-fed SCII has only half number of passive components compared to Z-source inverter, but higher voltage boost ratio and lower active switch voltage stress. (2) Voltage-fed SCII has less active switch, smaller size and higher reliability than two stage boost-converter-inverter. (3) Current-fed SCII is a capacitor-less solution, which is much more compact than the ones with capacitors (boost-converter-inverter and Z-source inverter) (4) Current-fed SCII has lower active switch current stress than current-fed Z/quasi-Z-source 88 inverter at the same voltage gain, in buck motoring and regeneration mode. (5) With active front switch, both voltage and current-fed SCII can have regenerative capability. Due to the benefits, this voltage-fed switched-coupled-inductor inverter is beneficial to be used in the dc-ac applications that demand a high voltage gain from a very low voltage dc source, such as the micro-inverter in photovoltaic, or G/M in HEV. The current-fed switched-coupled-inductor inverter is potential candidate for compact, regenerative, high temperature, high efficiency, low cost HEV/EV motor drive or engine starter. In summary for Z-source matrix converters, with only three additional switches, it can have the buck-boost function, which can reduce cost and increase reliability for those applications that have a requirement for wide input and output voltage ranges. All those features of each topology has been demonstrated by simulations and experiments in later chapters based on the modulation method proposed in chapter 4, 5, 6. All the experiment results can be found in chapter 5, 6, 7, 8 and 9. 89 CHAPTER 4 MODULATION 4.1. Introduction + - Figure 4.1. Conventional current source inverter Conventional current source inverter is composed of input current source, six active reverse-blocking switches, and three ac capacitors which is directed connected to the output lines. Figure 4.1 shows the basic circuit configuration.  I 1( S6 S1) S1 S3 S5    I 4 ( S3S4 ) I 5( S4 S5 ) I 6 ( S5S6 )   I 2 ( S1S2 ) I 3( S2 S3 ) v AB v AC vBC vBA vCA S 4 S6 S 2 (a) Conventional six active states    I 7 ( S1S 4 ) I 8( S3S6 ) I 9 ( S5S2 ) S1 S3 S5 S1 S3 S5 S1 S3 S5 S 4 S6 S 2 S 4 S6 S 2 S 4 S6 S 2 (b) Conventional three zero states Figure 4.2. Nine switching states for conventional current source inverter 90 vCB It has nine switching states: six active states and three zero states. In active state, one and only one switch on upper leg, and also one and only one switch on the lower leg conduct at any time; the three switches on either half leg turn on and off complementarily with each other. The reason for this is: the output three phases are connected with capacitors, thus if any two phase legs in the same half bridge are conducting at the same time, a short circuit can form. At the same time, the input current has to have path to flow, so one phase leg in each half bridge has to be conducted.  I 2 ( S1S2 )  I 3 ( S 2 S3 )   I 9 ( S5 S2 ) I 7 ( S1S4 )  I 8 ( S3S6 )  I 8 ( S3S6 )  I 4 ( S3S4 )  I 1( S6 S1)   I 7 ( S1S4 ) I 9 ( S5 S2 )  I 6 ( S5 S6 )  I 5( S4 S5 ) Figure 4.3 Conventional discontinuous modulation for current source inverter This section concentrates on the modulation of current source inverter. The most common modulation method is the space vector PWM control, which use active vectors and zero vectors to synthesize the rotating current vector. The block diagram is shown in Figure 4.3. The hexagon is composed of six vectors, each of which is corresponding to one active switching state. Thus the hexagon is divided into six sectors by these vectors, and each vector occupies sixty degrees. In each sector, usually the adjacent two active vectors are selected to generate output current, in order to utilize a common switch. The selection of zero vectors is 91 more flexible. One, two or three zero vectors can be selected in each sector. In the assumption of the three phase balanced system, the output current synthesis equation is: I ref Ts  IiTi  Ii 1Ti 1  I 0T0 (4.1) , where Ti , Ti 1, T0 are the dwell times for the adjacent vectors Ii , Ii 1 and I 0 respectively.  I 2 ( S1S2 )  I  I 3 ( S 2 S3 ) T1  I1 T  I 1( S6 S1)  T2  I2 T  I 4 ( S3S4 )  I 6 ( S5S6 )  I 5( S4 S5 ) Figure 4.4. Output current vector synthesis  I T T 1 1  1  2 sin(2 / 3) T sin(2 / 3   ) T sin(   / 3) (4.2) As shown in Figure 4.4, the synthesis process can be illustrated as follows: (1) project the output current vector into two adjacent vectors; (2) in the formed triangle, apply trigonometric theory that the division of side length to sin  is equal for each side; (3) express the angle in terms of current vector angle. Equation (4.1) is the resultant synthesis equation, from which, the time period for each active vector and zero vector can be derived. And their expressions are as follows: Ti  3 3 m sin(600   )  Ts ; Ti  m sin( )  Ts ; T0  Ts  Ti  Ti 1  Top 2 2 4.2. Discontinuous SVPWM and Equivalent Carrier-based modulation 92 (4.3) 4.2.1. Selection of zero vector in terms of minimum switching times Table 4-1.Selection of vectors in each sector Sector Vector1 Vector2 Vector0 Sector I I1 (S6S1) I2 (S1S2) I7 (S1S4) Sector II I2 (S1S2) I3 (S2S3) I9 (S2S5) Sector III I3 (S2S3) I4 (S3S4) I8 (S3S6) Sector IV I4 (S3S4) I5 (S4S5) I7 (S1S4) Sector V I5 (S4S5) I6 (S5S6) I9 (S2S5) Sector VI I6 (S5S6) I1 (S6S1) I8 (S3S6) Table 4-2.Conduction Time for S1 and S4 in Each Sector Sector I S1 1 Sector II 3 m sin(600   ) 2 Sector III 0 3 m sin(600   ) 2 3 m sin( )  2 0 3 m sin( ) 2 Sector IV Sector V Sector VI 1 S4 S1 3 m sin(600   ) 2 3 m sin( )  2 0 S4 1 3 m sin(600   ) 2 1 3 m sin( ) 2 0 In every sector, except the two active vectors, there are three zero vectors for selection. In order to reduce the switching times, the zero vector with the common switch in two active vectors is selected. For example, in sector I, two active vectors are S6 S1 and S1S2 , in which the common switch is S1 . So the zero vector I 7 which contains S1 is selected so that S1 has no PWM switching in the whole 60 degree region. Similarly, each switch only does PWM 93 switching in every other 60 degree, as shown in Figure 4.3. The selection of vectors in each sector is shown in Table 4-1, and the resultant conduction time is in Table 4-2. Sector I I1 I2 I7 I1 I2 I7 I1 I2 I7 I7 I2 S1 S2 S6 S4 S3 S5 S1 S2 S6 S4 S3 S5 a Switching I1 times 0 4 2 2 0 0 b I7 I7 I7 I1 I2 /2 /2 I2 /2 I7 I1 /2 I7 I7 I7 I7 I1 I1 /2 I2 /2 I2 /2 /2 0 4 4 4 0 0 S1 S2 S6 S4 S3 S5 0 4 2 6 0 0 S1 S2 S6 S4 S3 S5 d c Figure 4.5. Four different switching sequences in sector I 4.2.2. Selection of switching sequence in each sector As long as the Ampere-seconds in one switching period keeps constant, the sequences of vectors will not affect the output. However, it does affect the output THD and device switching loss. Taking sector I as an example, four switching sequences including symmetrical and unsymmetrical ones are shown in Figure 4.5. In these sequences, type a is an unsymmetrical sequence. In order to get the same harmonic performance as the other symmetrical ones, the switching frequency has to be doubled. In this case, the benefits of less switching counts in one switching period can not be 94 hold. Type b seems a good choice since the zero vector I 7 connects together, and I1 also connects together with the previous switching period, which reduces the switching counts. However, the zero vectors are all allocated in the middle, so the active vectors are pushed to the edge, not in the middle of every half switching cycle, which may increase harmonics. It can be illustrated by the input current ripple which has been shown as the red line in Figure 4.5. The input current will decrease in active state and increase in zero state. Since the zero vectors are connected together, as well as the active vectors, so the current ripple frequency is the same as switching frequency, which results in a double ripple amplitude. These low frequency and high amplitude harmonic contents are directly transferred into output current. Therefore, in the harmonics point of view, this sequence is not preferred. Type c makes an improvement for type b in terms of harmonics, by splitting the zero states into two parts, one of which is placed in the middle, and one of which is put at the side. The input current ripple amplitude changes to half of type b, and in addition, the ripple frequency is doubled, both of which decreases the size of the passive component, as well as lower the output harmonics. This is consistent with the statement that the output harmonics can be minimized by putting the active state in the middle of half switching cycle. Type d inserts each active state into separate zero states. The switching counts maintain the same as type b, but the ripple is unevenly distributed due to the non-middle allocation of active vectors, because of which it doesn’t have the same effect as type c in terms of harmonic reduction. 95 Sector II Sector I t0 /2 t1 t2 t0 t0 t0 t0 /2 t1 t2 /2 /2 I2 I1 /2 t0 t0 t0 /2 /2 I2 I1 /2 0 4 4 4 0 0 S1 S2 S6 S4 S3 S5 0 4 4 4 0 0 S2 S3 S1 S5 S4 S6 Sector III t0 t1 /2 t2 t0 t0 I2 /2 /2 Sector IV I1 t0 /2 S3 S4 S2 S6 S5 S1 t0 t1 /2 0 4 4 4 0 0 t2 t0 t0 I2 /2 /2 0 4 4 4 0 0 S4 S5 S3 S1 S6 S2 Sector V t0 t1 /2 S5 S6 S4 S2 S1 S3 t2 t0 t0 I2 /2 /2 I1 t0 /2 Sector VI t0 I1 /2 t0 t0 t0 I2 t1 t2 /2 /2 /2 S6 S1 S5 S3 S2 S4 0 4 4 4 0 0 I1 t0 /2 0 4 4 4 0 0 Figure 4.6. Switching state in 6 sectors for sequence c 4.2.3. Equivalent reference-carrier modulation for DPWM In the practical implementation, the SVPWM control could be transformed into equivalent carrier based control. The reference waveform instantaneous value of the switch is proportional to the corresponding conduction time at that moment t, as shown in Figure 4.7, where one is for S1 and one is for S4 . The switching functions generates the output current I ao in the form of 96 I ao  ( S1  S4 ) * I dc (4.4) 1 0.5 0 -0.5 0 0.005 0.01 0.015 0.02 0.025 0.03 0.03 Figure 4.7. References for S1 and S4 and the output line current waveform For the same output current requirement, there are infinite choices for S1 and S4. The aforementioned references definitely generate a sinusoidal waveform, as the dotted line. However, the switching function characteristics are little bit different from the voltage source inverter modulation carrier. The upper switch and the lower switch on the same phase leg are not necessary complementary to each other, but the three switches on the same half leg must be, like S1, S3 , S5 . Thus the PWM generated from reference waveform can not follow the rules that be positive if reference exceeds carrier, and be negative if reference is below carrier. A new group of three references have been designed to generate the correct PWM for CSI, which are proportional to ( T0 ), ( T0 + T2 ) and ( T0  T1  T2 ) respectively. The switches corresponding to the turn on time T0 , T1 and T2 are defined as Z 0 , Z1 and Z 2 respectively. The new rule is: if the carrier is below reference T0 , Z 0 is turned on; if the carrier is between T0 and T0 + T2 , Z 2 is turned on; if the carrier is between T0 + T2 and T0  T1  T2 , Z1 is turned on, just like Figure 4.8 (a). Different references and different placement sequences can be used for different switching sequence in Figure 4.5. But each 97 PWM T0+T1+T2 1 T0+T2 0.5 T0 0 T1 T2 T0 T2 0.0321 0.0323 T1 -0.5 -1 -1.5 0.0315 0.0317 0.0319 0.0325 (a) Sequence b T0/2+T2+T1 1 T0/2+T2 0.5 T0/2 0 T0/4 T1/2 T2/2 T0/2 T2/2 T1/2T0/4 -0.5 -1 -1.5 0.04410.04410.04410.04420.04420.04420.04420.04420.04430.04430.044 (b) Sequence c Figure 4.8. PWM implementation for three sequences 98 Figure 4.8 (cont’d) T0+T1+T2 1 T0+T2 T0/2+T2 0.5 T0/2 0 -0.5 -1 -1.5 0.015 0.0151 0.0151 0.0151 0.0151 0.0151 0.0152 (c) Sequence d waveform is generated when the carrier is between two reference waveforms, which make the three PWM for the upper switches complementary. The implementation method for sequence b, c, d are shown in Figure 4.8. 4.2.4. Numerical Spectrum analysis According to switching state assignment in Figure 4.4, switching time calculation from equation (4.2) and the switching waveform implementation in Figure 4.8, the numerical switching waveform in one fundamental cycle could be obtained for each DPWM sequence by using equation (4.3). Set the parameters as: M=0.8, fo =100Hz, f s =20kHz. The spectrum distribution diagrams of each sequence at switching frequency are shown in Figure 4.9 (a)(b)(c). The weighted THD has been used to be a criterion for evaluating the total harmonics distortion of each method. The definition of WTHD and results for each sequence 99 0.6     0.4  Vpn_FFT 0.2 0 4 1.910 210 4 2.110 4 2.210 4 2.31 fser (a) Sequence b WTHD  3.607 *103 0.6     0.4  Vpn_FFT 0.2 0 4 1.9 10 2 10 4 2.1 10 4 2.2 10 4 2.3 10 4 fser (c) Sequence c WTHD  2.663*103 Figure 4.9. Numerical FFT results for b, c, d at m=0.8 for switching frequency range 100 Figure 4.9 (cont’d) 0.6   Vpn_FFT 0.4 0.2 0 4 1.9 10 210 4 2.1 10 4 2.2 10 4 2.3 10 4 fser (c) Sequence c WTHD  3.306*103 are shown in the following:.   WTHD  2me 1 1 V pn _ FFT kk  ( kk  2 kk  )2 / V pn _ FFT 1 (4.5) 4.2.5. Analytical double Fourier analysis Since the SVPWM has two main frequency component: one is fundamental frequency, and the other is sitching frequency, an analytical double Fourier series form could also be derived for each sequence in DPWM, according to the rising edge and falling edge time point according to the time duration for each switch at different sector in Table 4-2 and the detailed PWM arrangement in Figure 4.8. Take DPWM sequence b as an example. The double Fourier expression for the DPWM is a sum of the integrations in six sectors since no general equation for the rising and falling edges in terms of angle in six sectors 101 exists, but does in one sector. Equation (4.6) gives the general double Fourier equation and Table 4-3 gives the integration upper limit and lower limit of S1 for sequence b in each sector. However, the FFT analysis target should be the line current, which can be represented by the subtraction of upper switching function to lower switching function in the same phase leg as shown in equation (4.4), which presents as an ac symmetric waveform. Table 4-3.Integration limit of S1 for sequence b ys(i) ye(i) 0  3 xr(i) 0  xf(i) 2 3 2 3 xr1  0; xr 2  T 2 (Ts  1 ) 2 Ts  2    2 3  3 2 m sin(  y) 2 3  4  3 4  3 2 T1 Ts 2 3 2 m sin(   y )) 2 3 x f 2  2 ( 0 0 T T 2 (Ts  1  2 ) 2 2 Ts 2 T1 T2 (  ) Ts 2 2 ( 3 2 m sin( y   )) 2 3 5  3  2    0 xr1  5  2 3 xf1   0 2 T1 Ts 2 xf1  3 m sin(2  y ) 2 xr 2   T T 2 (Ts  1  2 ) 2 2 Ts  2   3 2 m sin( y   ) 2 3 2 T1 T2 (  ) 2 Ts 2 3 4 m sin( y   ) 2 3 xf 2  3 4 m sin( y   ) 2 3 T 2 (Ts  1 ) Ts 2  2   3 m sin(2  y ) 2 The coefficient of S1(t ) is shown in Table 4-3. The coefficient of S4 (t ) is equal to the coefficient of S1(t ) in the sector of 180 degree apart. Thus the phase current double Fourier 102 integration limit is derived and shown in Table 4-4. According to the symmetry, the integration could be conducted in the positive half cycle, two times of which is the final coefficient, as shown in equation (4.6). Amn  jBmn  6 ye (i ) x f (i ) 1 2 2    I dc e j ( mx  ny ) dxdy (4.6) 1 ys (i ) xr (i ) Table 4-4.Integration limit for Ia(t) of sequence b i 1 2 3 4 Pulse I dc I dc ys(i) ye(i) 0  3  3 2 3 xr1(i) xf1(i) 0 2 3   I dc  4  3 0 4  3 5  3 0 5  I dc 6 I dc 5  3 2 2 T1 ( ) Ts 2 T0 2  2 TS  2 T1 ( ) Ts 2  0  I dc xr2(i) T 2 (Ts  1 ) Ts 2 2 T1  T2 ( 0 ) Ts 2  2 T0 ( ) Ts 2 2 T1 ( ) Ts 2 2 T1 ( ) Ts 2 2 T1  T2 ( ) 2 Ts T0 2  2 TS 2   2 T1  T2 ( ) Ts 2 2 T0 ( ) Ts 2 2  2  2 T1 ( ) Ts 2 2 T1  T2 ( ) 2 Ts 4.2.6. Simulation results A current source inverter with the configuration of Figure 4.1 is constructed in simulation with the parameters: Vin  100V , Lin  1mH , Co  30uF , Pr  1kW , fo  100 Hz, f s  20kHz Figure 4.10 shows the phase a current after the output capacitor for sequence b, c and d respectively. It is observed that they have the same fundamental rms value, but different switching ripple. Sequence c has lower current ripple than sequence b and d. 103 Ia of sequence B 40 20 0 -20 -40 0.005 0.01 0.015 0.02 0.015 0.02 0.015 0.02 t Ia of sequence C 40 20 0 -20 -40 0.005 0.01 t Ia of sequence D 40 20 0 -20 -40 0.005 0.01 t Figure 4.10. Simulated phase a current after the C filter for sequence b, c, d 4.3. Continuous SVPWM and Equivalent Carrier-based modulation 4.3.1. Selection of zero states in each sector If the zero states I7, I8 and I9 are all used in each sector, as shown in Table 4-5, all six switches will be switching on and off in each sector. The number of switching for each switch can be derived shown in Figure 4.11. The zero state period T0 is divided into 3 equal ones 104 and assigned to I7, I8, I9 respectively. Figure 4.11 shows one example in Sector I. The I9 and I8 are put at sides. Thus every switch has switching action in one switching period. The switching counts for each one is shown in the figure. The total switching counts is 20 in the example, which is 2.5 times of the previous proposed discontinuous SVPWM method. Table 4-5.Selection of vectors in each sector in Continuous SVWPM Sector Vector1 Vector2 Vector0 Sector I I1 (S6S1) I2 (S1S2) I7,I8,I9 Sector II I2 (S1S2) I3 (S2S3) I7,I8,I9 Sector III I3 (S2S3) I4 (S3S4) I7,I8,I9 Sector IV I4 (S3S4) I5 (S4S5) I7,I8,I9 Sector V I5 (S4S5) I6 (S5S6) I7,I8,I9 Sector VI I6 (S5S6) I1 (S6S1) I7,I8,I9 Sector I T0/3 I9 I8 I1 I2 I7 I7 I2 Switching times:20 2 6 4 2 4 2 I1 I8 I9 S1 S2 S6 S4 S3 S5 Figure 4.11. Continuous SVPWM modulation switching states in Sector I 4.3.2. Equivalent carrier-based modulation for continuous SVPWM S1ref S 4ref Ioaref 1 0.5 0 0.5 1 1.5 Switching waveform for S1 0 0.01 0.02 0.03 Figure 4.12. Equivalent carrier-based modulation for continuous SVPWM 105 1.5 PWM 1(t ) PWM 2(t ) 1 PWM 3(t ) PWM 4(t ) 0.5 PWM 5(t ) 0 Figure 4.13 Implementation of switching waveform in Figure 4.12 by carrier-based continuous SVPWM Similarly, the equivalent carrier based modulation for this method can be derived similarly as Table 4-2. The equivalent references for switch S1 and S4 are shown in Figure 4.12. The subtraction of S1 by S4 is the output current reference, which is a sinusoidal shown as the pink curve in Figure 4.12. Figure 4.12 also shows the switching waveform of switch S1, which is a continuous PWM as expected. Figure 4.13 shows the actual implementation process and final switching PWM in one switching cycle. 4.3.3. Sequences of vectors in each switching cycle For the sequences of the five vectors in half switching cycle, T1,T2, T7,T8,T9, there are many choices. Also the zero state time period is not necessary evenly divided into 3 to be assigned to three zero vectors. Different portion can be assigned to different zero vectors in different sectors. The basic principle to guarantee a lower harmonic content is to put the T1 and T2 in the middle of each half switching cycle. Compare the continuous SVPWM with the discontinuous SVPWM, it can be seen that discontinuous method has much lower switching times than the continuous one, so as the switching loss. However, in terms of spectrum, continuous SVPWM may have lower harmonics. This needs to be studied in the following. 106 4.3.4. Numerical FFT spectrum analysis 0.6   Vpn_FFT 0.4 0.2 0 0 200 400 600 fser 0.6  0.4  Vpn_FFT 0.2 0 3 910 4 110 4 1.110 4 1.210 4 1.310 fser Figure 4.14. Numerical spectrum analysis of phase current for continuous SVPWM at M=0.8 107 Figure 4.14 (cont’d) 0.6   Vpn_FFT 0.4 0.2 0 4 1.910 210 4 4 2.110 4 2.210 2.310 4 fser According to the selection in Table 4-5 and the sequence in Figure 4.11, the theoretical switching waveforms and also the phase current PWM form can be obtained. Set the parameters as: M  0.8, f o  100 Hz, f s  10kHz . Compared to continuous SVPWM, DPWM only has half fundamental period doing PWM switching. So in order to keep the same average switching frequency, the carrier frequency of continuous SVPWM is set to be half of DPWM, which is 10kHz here. The spectrum distribution diagrams at fundamental frequency and f sw, 2 f sw are shown in Figure 4.14. The WTHD in this case is 0.5107%. 4.3.5. Simulation results Figure 4.15 and Figure 4.16 shows the switching and output current waveforms. Compared to Figure 4.10, the output current contains higher switching ripple, thus higher total harmonic distortion. 108 1 0.8 0.6 0.4 0.2 0 0.01 0.012 0.014 0.016 0.018 0.02 Figure 4.15. Switching waveform of continuous SVPWM 30 20 10 0 -10 -20 -30 0 0.005 0.01 0.015 0.02 Figure 4.16. Simulated three phase output current after the filter 4.4. Space-Vector-Pulse-Width-Amplitude-Modulation (SVPWAM) PWM methods are all about zero vector selection and zero vector placement. In order to further reduce the switching times, at the same time not affect the output sinusoidal waveform, one method is to eliminate the zero state in each sector. The switching period for each switch reduces to only 120 degree per 360 degree. Take S1 as an example, it only has PWM switching in sector II and sector VI, so only for 120 degree. The elimination of zero state doesn’t affect the output waveform, but do affect the input current, which can not be a 109 dc current but a dc current with 6 ac ripple.  refers to the fundamental frequency. Thus a dc-dc stage or an integrated dc-dc stage like the Z-source network has to be cascaded in front to generate this 6 current on the dc link, instead of using of single stage inverter. Thus a new modulation method SVPWAM “Space-Vector-Pulse-Width-Amplitude-Modulation” is proposed here, in order to reduce the switching loss. The reason it is named as “Space-Vector-Pulse-Width-Amplitude-Modulation” is that the amplitude of carrier waveform is not a constant but a varied waveform, and also it is based on different zero vector selection in SVPWM method. In order to implement this method, a front stage regulator needs to be connected in series with CSI to generate this varied dc link voltage. 4.4.1. SVPWAM for Voltage Source Inverter(VSI) 4.4.1.1. Principle of SVPWAM control in VSI SV3 SV2 S1S3 S5 II III  T2 SV4 S1S3S5 I  T1 IV S1S3 S5 T1 600 SV1 VI S1 S3 S5 V SV6 SV5 S1 S3S5 S1 S3S5 Figure 4.17. Space-Vector-Pulse-Width-Amplitude-Modulation for VSI 110 The principle of SVPWAM control is to eliminate the zero vector in each sector. The modulation principle of SVPWAM is shown in Figure 4.17. This imposes zero switching for one phase leg in the adjacent two sectors. For example in sector VI and I, phase leg A has no switching at all. The dc link voltage thus is directly generated from the output line to line voltage. In Sector I, no zero vector is selected. Therefore S1 and S2 keep constant on, and S3 and S6 are doing PWM switching. As a result, if the output voltage is kept the normal three phase sinusoidal voltage, the dc link voltage should be equal to line to line voltage Vac at this time. In Sector II, it should be equal to Vbc . Other vectors are similar. Consequently the dc link voltage should present a 6 varied feature to maintain a desired output voltage. In another word, it should be designed as the envelope of maximum output line to line voltage:       Vdc         3V peak sin( f t   / 3) 3V peak sin  f t (0   f t   / 3) ( / 3   f t  2 / 3) 3V peak sin( f t   / 3) (2 / 3   f t   ) 3V peak sin( f t  2 / 3) (   f t  4 / 3) 3V peak sin( f t   ) (4 / 3   f t  5 / 3) 3V peak sin( f t  4 / 3) (5 / 3   f t  2 ) (4.7) , assuming that phase-a voltage reference starts from angle 0. V peak is the amplitude of the phase voltage. The dc link corresponding waveform is shown in solid line in Figure 4.18. A dc-dc conversion is needed in the front stage to generate this 6 voltage. The topologies to implement this method will be discussed later. 111 300 200 100 0 -100 -200 -300 0 0.005 0.01 0.015 Figure 4.18 DC link voltage of SVPWAM in VSI The benefit of this method is the significant switching loss reduction. In each sector, only two switches of the same phase leg are doing PWM switching. For each switch, it only does PWM switching in two sectors, which correspond 120 degrees in every fundamental cycle. Compared to conventional SPWM method, the switching frequency is reduced by 2/3. Compared to discontinuous PWM, the switching frequency is reduced by 1/3. The switching loss reduction can reach further to 87% if the power factor is unity, because the switching actions happen at the current zero crossing region. The details of switching loss reduction will be analyzed later. For the time period calculation in SVPWAM, the switching time period is varied if original equations are used for T1 and T2 : T1  3  3 m sin(   ); T2  m sin( ) 2 3 2 (4.8) , where   [0,  3] is relative angle from the output voltage vector to the first adjacent basic voltage vector as shown in Figure 4.17. If T1, T2 maintain the same value as equation (4.8), the total switching period at angle  is equal to the sum of these two since no zero vector is applied. This switching period is a varied value, which would cause additional 112 harmonic component in the output. Because the volt-seconds is the key point that affect the output voltage, a constant switching period can be used and two new active state period which holds the same proportion as the previous ones in eq. 4.8 can be created. Thus in order to keep the switching period constant but still keep the same pulse-width as the original one, the new time periods can be calculated in a constant proportion norm as: T1 ' T2 '  Ts T1 ' T1  Ts T1  T2 (4.9) T2 ' T2  Ts T1  T2 In this case, the pulse width doesn’t change while the switching period is kept constant. Sector II Sector I I1 I2 I2 I1 S1 S3 S6 S4 S2 S5 I1 I2 I1 S2 S4 S1 S5 S3 S6 I1 I2 I2 I1 I2 I1 Sector VI Sector V I1 I2 S3 S5 S2 S6 S4 S1 Sector IV S4 S6 S3 S1 S5 S2 I2 Sector III I1 I2 S5 S1 S4 S2 S6 S3 I2 I1 I1 I2 I2 I1 S6 S2 S5 S3 S1 S4 Figure 4.19. Vector placement in each sector for VSI The vector placement within one switching cycle in each sector is shown in Figure 4.19. In practical implementation, the two PWM waveforms generated from DSP can be assigned to different switches in different sectors. There are only two PWM for six switches. One in three original PWM has been eliminated. That is also corresponding to the switch that 113 generates zero vector, as shown in dotted line in Figure 4.19. The relative position of T1 and T2 can only have one choice, but the starting and ending time can be flexible, which may cause different output harmonics. In another work, how to assign the time period for each section of I1 or I 2 is flexible. Vdc 200 0 500 Vab 0 500 1 Sap 0 0 0.01 0.02 0.03 t(s) Figure 4.20. Theoretic waveforms of dc link voltage, output line to line voltage and switching signals Figure 4.20 shows the ideal waveforms of the bus voltage Vdc , the output line to line voltage of the first inverter phase leg, and the switching signals of S1 . Unlike the conventional SVPWM and SPWM control, the SVPWAM technique combines the pulse width modulation and amplitude modulation together such that each inverter phase leg only switches during one third of the fundamental period. The output line to line voltage partly overlaps with the dc link voltage, which potentially reduce the its harmonics content, as long as the dc link voltage doesn’t have high harmonics. However, the dc link voltage generated by dc-dc converter usually has switching ripple, which will add to the output line to line voltage of inverter. It 114 may increase the harmonic level also. 4.4.1.2. Inverter switching loss reduction for VSI For unity power factor case, the inverter switching loss is reduced by 86% although the switching phase-span has only been reduced by 2/3. Such difference is because the switching current is in zero crossing region, as shown in Figure 4.21. The phase voltage can be divided into four sections: [300 ,300 ],[300 ,1500 ],[1500 , 2100 ],[2100 ,3300 ] . During [300 ,1500 ] and [2100 ,3300 ] , the phase voltage exhibits the maximum and minimum voltage among the whole period, which is directed connected to the dc link voltage, so there is no PWM switching in these two periods. However, in another two 60 degree sections, the voltage is in middle range, so it is generated from PWM switching referenced to the 6 varied dc link voltage envelope. The PWM switching region is shown in the shadow area of Figure 4.21. The current is 300 around its zero point, as well as the phase voltage. The voltage and current slop is the slowest in this region among all 360 degree period. Va * Ia Figure 4.21. Switch voltage and current stress when pf=1 (In shadow area) In voltage source inverter, the voltage stress on the switch is equal to dc link voltage, and the current stress is equal to output current. Thus the voltage stress is always maximum line to line voltage and the current stress is always from I peak ( sin 300 ) to I peak (sin 300 ) . 115 The general equation for switching loss calculation of each switch is: PSW _ VSI  i V 1 2 ESR a DC  f sw dt 2 0 Vref I ref (4.10) , where ia represents the output current; VDC is the average dc link voltage, which is an approximate switching voltage here; and ESR , Vref , I ref are the switching energy, reference voltage and current, respectively. The total switching loss is 6  PSW _ I . Since the SVPWAM only has PWM switching in two 60 degree sections, the integration over 2 can be narrowed down into integration within two 60 degrees: PSW _ I  | I sin(t ) | VDC 1  /6 [ ESR m  f sw d t 2  /6 Vref I ref 7 /6 | I sin(t ) | VDC ESR m  f sw dt 5 /6 Vref I ref   (4.11) 2  3 I m VDC  ESR  f sw  Vref I ref The average value during each 60 degree section is:  /6 3 V peak cos  d   V peak  /6  VDC   (4.12) The switching loss for conventional SPWM method is: PSW _ I '  | I sin(t ) | VDC 1 2  f sw dt [  ESR m 0 Vref I ref 2 (4.13) 2 I V 2 I mV peak E f   m DC ESR  f sw    Vref I ref  Vref I ref SR sw In result, the switching loss of SVPWAM over SPWM is: f  2 3 3 2  /  12.8% . The    switching loss has been reduced by 87%. However, when the power factor decreases, the switching loss reduction amount decreases because the switching current increases. As shown in Figure 4.21, the voltage remains in that section but the current switching region shifts. Thus the equation (4.11) 116 should be re-written as: PSW _ I  | I m sin(t   ) | VDC 1  /6 [ E  f sw d t  /6 SR 2 Vref I ref 7 /6 | I m sin(t   ) | VDC E  f sw d t 5 /6 SR Vref I ref  (4.14) Figure 4.22 shows the relationship between the power loss percentage ratio and the power factor calculated according to eq. (4.14). Figure 4.22. (SVPWAM power loss / SPWM power loss) vs. power factor in VSI As indicated, the worst case happens when power factor is equal to zero, because the switching current is in maximum 60 degrees area. But the switching loss reduction in this case still reaches 50%. In conclusion, SVPWAM can bring the switching loss down by 50% ~ 87% according to different power factor. 4.4.2. SVPWAM for Current Source Inverter(CSI) 4.4.2.1. Principle of SVPWAM in CSI The principle of SVPWAM in current source inverter is also to eliminate the zero vectors. As shown in Figure 4.23, for each sector, only two switches are doing PWM switching, since only one switch in upper phase legs and one switch in lower phase legs are 117 conducting together at any moment. Thus for each switch, it only needs to do PWM switching in two sectors, which is 1/3 of the switching period. Compared to the SVPWM that with single zero vector selected in each sector, this method brings down the switching frequency by 1/3, since  I2 ( S1S2 )  I3  I1 ( S 2 S3 ) ( S6 S1)  I6  I4 ( S3S4 ) ( S5 S6 )  I 5 ( S4 S5 ) Figure 4.23 Current source inverter SVPWAM diagram Figure 4.24. DC current and output phase current waveform the previous one requires switch to do PWM switching in half switching period, but this one only 1200 . 118 Similarly, the dc link current in this case is a 6 varied current. It is the maximum envelope of six output currents: I a , Ib , I c ,  I a ,  Ib ,  I c , as shown in Figure 4.24. For example, in Sector I, S1 always keeps on, so the dc link current is equal to I a . In Sector II, S2 is constantly on, so dc link current is equal to - I c . Assume the output phase current reference starts from angle 0, the required dc link current is:  I peak sin( f t   / 3)   I peak sin  f t I  peak sin( f t   / 3) I dc    I peak sin( f t  2 / 3) I sin( f t   )  peak  I peak sin( f t  4 / 3)  (0   f t   / 3) ( / 3   f t  2 / 3) (2 / 3   f t   ) (4.15) (   f t  4 / 3) (4 / 3   f t  5 / 3) (5 / 3   f t  2 ) The time intervals for two adjacent vectors can be calculated in the same way as equation (2) and (3). The angle  is shown in Figure 4.23. According to diagram in Figure 4.23, the vector placement in each switching cycle for six switches can be plotted in Figure 4.25. II I I1 I2 I2 I1 S1 S2 S6 S4 S3 S5 I2 I2 I1 S2 S3 S1 S5 S4 S6 I1 S4 S5 S3 S1 S6 S2 I1 III I2 I2 I1 I1 I2 I2 I1 I1 I2 I2 I1 S3 S4 S2 S6 S5 S1 I1 I2 I2 I1 S6 S1 S5 S3 S2 S4 S5 S6 S4 S2 S1 S3 Figure 4.25. Vector placement for each sector for CSI 119 Figure 4.26 shows the ideal waveforms of the dc current I dc , the output phase a current and the switching signals of S1 . The switching signal has two sections of PWM in positive cycle, but no PWM in negative cycle at all. However, the conventional SVPWM with only one zero vector selected, has an additional 60 degree PWM section in negative half cycle. So the switching frequency is reduced by 1/3. Idc 20 10 S1 Ia 0 0 20 0.005 0.01 0.015 0.02 0.005 0.01 0.015 0.02 0.005 0.01 0.015 0.02 0 -20 0 1.5 1 0.5 0 -0.5 0 Figure 4.26. Theoretic waveforms of dc link current, output line current and switching signals 4.4.2.2. Inverter switching loss reduction for CSI Figure 4.27. Switching voltage and current when pf=1 120 SVPWAM / SVPWM Switching loss 1 0.8 0.6 0.4 0.2 1 0.5 0 pf 0.5 1 Figure 4.28. CSI switching loss SVPWAM/SVPWM vs. power factor In current source inverter, the current stress on the switch is equal to the dc link current, and the voltage stress is equal to output line to line voltage. The shadow area in Figure 4.27 shows the switching current and voltage in Sector I. For a single switch, the switching loss is determined by PSW _ CSI  2* i V 1 2 3 ESR a bc  f sw d t Vref I ref 2  3 (4.16) The voltage is within 300 of the zero-crossing region, and the current is at the maximum 600 area. Thus this switching loss is similar to the one in voltage source inverter. But the comparison object switching loss in SVPWM of CSI becomes only half of the SPWM if the same switching frequency is used. So the switching loss reduction relative to SVPWM method can be plotted with power factor in Figure 4.28. The value is half of the value in Figure 4.22. The maximum switching loss reduction is 73.2% at unity power factor. The minimum switching loss reduction is 4.3% at power factor equal to zero. 4.4.3. Spectrum Analysis of SVPWAM 4.4.3.1. Spectrum comparison between SPWM, DSVPWM and SVPWAM in VSI 121 1 0.6 0.2 Vab(t ) 0.2 0.6 1 0 0.012 0.024 t (a) Output line to line voltage in VSI at SPWM control 1 Ia(t ) 0 1 0 0.01 0.02 t ( s) (b) Output line to line voltage in VSI at discontinuous SVPWM control 1 Vab (t ) 0 1 0 0.015 t 0.03 (c) Output line to line voltage in VSI at SVPWAM control Figure 4.29. Output line to line voltage waveform for three methods: (a) SPWM; (b) discontinuous SVPWM; and (c) SVPWAM 122 The object of spectrum analysis is the output voltage or current before the filter, not a single switch. The output spectrum is different from a single switch because certain orders of harmonics can be eliminated by sum of subtraction of switching functions. In voltage source inverter, the output voltage is equal to half dc voltage times the summation of two switching functions on the same phase leg. However, in current source inverter, the output current is equal to dc current times the subtraction of upper switching function to lower switching function on the same phase leg. Their waveforms are shown in Figure 4.29. The comparison is conducted between SVPWAM, discontinuous SVPWM and continuous SVPWM in VSI. The switching frequency selected for each method is different, because the comparison is built on a basis of equalized average switching frequency over a whole fundamental cycle, in order to not sacrifice the output harmonic performance. Assume the base frequency is f0. Thus 3f0 should be selected for SVPWAM, 2f0 should be selected for discontinuous SVPWM and f0 should be selected for continuous SVPWM in VSI, since they switches for 120 degrees, 180 degrees and 360 degrees respectively for every 360 degree fundamental cycle. In CSI, 3f0, 2f0 and f0 should be selected for SVPWAM, discontinuous SVPWM, and continuous SVPWM, respectively, because the PWM switching range is 120 degrees, 180 degrees and 360 degrees respectively. In another word, only by increasing the average switching frequency of SVPWAM or discontinuous SVPWM to the same level of continuous SVPWM, the harmonics are comparable at both low modulation and high modulation range. Here the base switching frequency is selected to be 10.8 kHz, because it is the integer times of the fundamental frequency 60 Hz, which eliminates lots of sub-frequency harmonic component. . 123 The modulation index selected for all methods here is the maximum modulation index 1.15, since the SVPWAM always only has the maximum modulation index. In this case, the fundamental components are all 1. The dc link voltage is designed to be a constant for SVPWM and an ideal 6 envelope of the output six line to line voltages for SVPWAM. Thus the harmonic of the SVPWAM here doesn’t contain the harmonics from the dc-dc converter output. It is direct comparison between two modulation methods themselves from mathematics point of view, not involving the harmonics brought by other factors. In practice, the SVPWAM may have higher harmonic components because of the distortion in the dc link voltage/current. For example, if the front stage is a dc-dc converter, the dc link voltage contains switching frequency ripple. 1 0.8   Vpn_FFT 0.6 0.4 0.2 0 0 200 400 600 fser (a) Figure 4.30. Spectrum of SPWM: (a) zoom-in at fundamental frequency; (b) zoom-in at switching frequency; (c) zoom-in at double its own switching frequency 124 Figure 4.30 (cont’d) 1 WTHD=0.23% 0.8   Vpn_FFT 0.6 0.4 0.2 0 3 910 3 9.810 4 1.0610 1.1410 4 1.2210 4 4 1.310 fser (b) 1 WTHD=0.23% 0.8   Vpn_FFT 0.6 0.4 0.2 0 4 210 2.0610 4 2.1210 4 2.1810 fser (c) 125 4 2.2410 4 2.310 4 0.8   Vpn_FFT 0.6 0.4 0.2 0 0 200 400 600 fser (a) WTHD=0.16% 0.8   Vpn_FFT 0.6 0.4 0.2 0 4 210 4 4 2.110 2.210 4 2.310 fser (b) Figure 4.31. Spectrum of discontinuous SVPWM: (a) zoom-in at fundamental frequency; (b) zoom-in at switching frequency. 126 |Vpn_FFT| 1 0.5 0 0 200 600 400 (a) Spectrum at fundamental frequency 1 WTHD=0.13% 0.8   Vpn_FFT 0.6 0.4 0.2 0 4 3.1 10 3.16 10 4 3.22 10 4 3.28 10 4 3.34 10 4 3.4 10 4 fser (b) Spectrum at switching frequency Figure 4.32. Spectrum of SVPWAM: (a) zoom-in at fundamental frequency; (b) zoom-in at switching frequency Figure 4.30 – Figure 4.32 show the calculated spectrum magnitude at fundamental frequency range and integer times of switching frequency range for three methods. As mentioned before, 127 for a fair comparison, different switching frequency has been used for different methods, in order to reach the same average switching frequency. 10kHz, 20kHz and 30kHz have been used for SPWM, discontinuous SVPWM and SVPWAM respectively. The weighted total harmonic distortion (WTHD) is defined as:  N  VFFT kk    WTHD   kk  2  kk VFFT1   2 (4.17) The difference between WTHD and THD is the amplitude for certain order harmonics in WTHD needs to be divided by the order number. It can better represent the THD level for different methods because the importance of the harmonics decreases as the frequency increases. High frequency harmonics can be more easily reduced by the output low pass filter, but not the lower ones. WTHD is calculated to be 0.23% for SPWM, 0.16% for discontinuous SVPWM and 0.13% for SVPWAM. It can be concluded that the ideal switching function of SVPWAM has less or comparable harmonics with SPWM and DPWM. However, the 6 dc link voltage is generated by the front stage dc-dc converter, so it contains additional switching ripple from the dc-dc converter switching, which may increase the harmonic content in SVPWAM. From the numerical analysis of the simulation results, this increase has no significant increase for the THD of output waveform. Thus it can be concluded that the SVPWAM features better or at least comparable harmonic performance as the other modulation methods. 4.4.3.2. Spectrum comparison between discontinuous SVPWM, continuous SVPWM and SVPWAM in CSI (1) Discontinuous SVPWM 128 According to switching state assignment in Figure 4.5, switching time calculation from equation (4.2) and the switching waveform implementation in Figure 4.8, the numerical switching waveform in one fundamental cycle could be obtained for each DPWM methods. Set the parameters as: M=0.8, fo=100Hz, fs=20kHz. The spectrum distribution diagrams of each sequence at frequency range of fundamental frequency and switching frequency are shown in Figure 4.33 (a)(b)(c). The weighted THD has been used to be a criterion for evaluating the total harmonics distortion of each method. The definition of WTHD and results for each sequence are shown in equation (4.17). 0.6   Vpn_FFT 0.4 0.2 0 0 200 400 600 fser Figure 4.33. Numerical FFT results for b, c, d at m=0.8 for both fundamental frequency range and switching frequency range 129 Figure 4.33 (cont’d) 0.6   Vpn_FFT 0.4 0.2 0 4 1.910 4 4 210 2.110 4 2.210 4 2.310 fser (a) FFT for phase current of DPWM sequence b at m=0.8 0.6  0.4  Vpn_FFT 0.2 0 0 200 400 fser 130 600 Figure 4.33 (cont’d) 0.6 0.4   Vpn_FFT 0.2 0 4 1.910 4 4 210 2.110 4 4 2.210 2.310 fser (b) FFT for phase current of DPWM sequence c at m=0.8 0.6 0.4   Vpn_FFT 0.2 0 0 200 400 fser 131 600 Figure 4.33 (cont’d) 0.6   Vpn_FFT 0.4 0.2 0 4 1.910 210 4 2.110 4 2.210 4 2.310 4 fser (c) FFT for phase current of DPWM sequence d at m=0.8   2me 1 1 V pn _ FFT kk 2  WTHD  ( kk kk  2  V pn _ FFT 1 WTHD _ sequence _ b  3.607 *10 ) 3 (4.18) WTHD _ sequence _ c  2.663*103 WTHD _ sequence _ d  3.306*103 (2) Continuous SVPWM According to the selection in Table 4-5, and the sequence in Figure 4.11, the theoretical switching waveforms and also the phase current PWM form can be obtained. Set the parameters as: M=0.8, fo=100Hz, fs=10kHz. Compared to continuous SVPWM, DPWM only has half fundamental period doing PWM switching. So in order to keep the same average switching frequency, the carrier frequency of continuous SVPWM is set to be half of DPWM, 132 which is 10kHz here. The spectrum distribution diagrams at fundamental frequency and one and two times switching frequency are shown in Figure 4.34 (a)(b)(c). The WTHD in this case is 0.5107%. 0.6 0.4   Vpn_FFT 0.2 0 0 200 400 600 fser (a) 0.6   Vpn_FFT 0.4 0.2 0 3 910 4 110 1.110 4 4 1.210 4 1.310 fser Figure 4.34. Numerical spectrum of phase current for continuous SVPWM at M=0.8 133 Figure 4.34 (cont’d) 0.6  0.4  Vpn_FFT 0.2 0 4 1.910 4 210 4 2.110 4 4 2.210 2.310 fser (c) The output theoretical output line current could be calculated by equation (4.19), which is also shown in Figure 4.35. A FFT analysis is conducted based on this waveform and the results are shown in Figure 4.36. I a (t )  I dc (t ) *( S1(t )  S4 (t )) 0.5 Ia ( t ) 0  0.5 0 0.01 0.02 t Figure 4.35. theoretical output line current in SVPWAM 134 (4.19) 0.6   Vpn_FFT 0.4 0.2 0 200 400 600 fser WTHD=0.141% 0.6   Vpn_FFT 0.4 0.2 2.910 4 310 4 3.110 4 3.210 4 3.310 4 fser Figure 4.36. Numerical spectrum of output current for SVPWAM (3) Comparison of WTHD between discontinuous SVPWM, continuous SVPWM and SVPWAM in CSI The aforementioned three PWM methods for current source inverter can be compared in 135 THD, by using the same average switching frequency. The DPWM only switches for half cycle, and SVPWAM only switches for 1/3 cycle, but continuous SVPWM switches for the whole cycle. The WTHD presents different value in different modulation index. So Figure 4.37 shows the relationship between WTHD and the modulation index for each method. SVPWAM only has unity M, so it only shows one point. The plot indicates that SVPWAM has the smallest WTHD and DPWM C the second. Continuous SVPWM has the worst harmonic performance. 0.012 DPWM B DPWM C DPWM D Continuous PWAM 0.01 0.008 0.006 0.004 0.002 0 0.2 0.4 0.6 M 0.8 1 Figure 4.37 WTHD vs. M for different methods 4.4.3. Analytical double Fourier expression for SVPWAM In VSI, the general expression of double Fourier coefficient is: Amn  jBmn  1 2 2 6 ye (i ) x f (i )    Vdc e j ( mx  ny ) dxdy (4.20) 1 ys (i ) xr (i ) , where y[0, 2 ] represents the fundamental cycle; x[0, 2 ] represents one switching cycle. Since the PWM waveform for each switch in different sectors are known in Figure 136 4.19, and also the time for rising edge and falling edge for each switch in each switching cycle can be calculated from (4.8) and (4.9). Thus the double Fourier expression coefficients in (4.20) can then be derived. The output line to line voltage Vab of a voltage source inverter is used as an illustrative example. It can be expressed using switching functions as follows: Vab (t )  Vdc ( S1 (t )  S3 (t )) (4.21) So the double Fourier equation for Vab is transferred into the subtraction of double Fourier equation for S1 (t ) and double Fourier equation for S3 (t ) . The integration limits for S1 (t ) and S3 (t ) are shown in Table 4-6 and Table 4-7, and the corresponding line to line voltage integration limits are shown in Table 4-8. Table 4-6.Integration limit for switching function S1 (t ) i ys(i) ye(i) xr(i) xf(i) 0  3  2 3 2 3 3 2 3  0 0 4  4  3 0 0 5 4  3 5  3 6 5  3 2 1 2 0 xr1  0; xr 2 =2    xr1    sin(2 / 3  y ) sin y sin(5 / 3  y ) sin( y - ) sin(2 /3  y ) sin y  2 x f 1 = xf 2 x f 1  2    sin(5 / 3  y ) sin( y - ) 2 0 137 Table 4-7.Integration limit for switching function S3 (t ) i ys(i) ye(i) 1 2  /3 0 4 4 /3 5 4 /3 2 0   xf(i) sin( /3  y ) xf1  2    sin( y + /3) 0  /3 2 /3 3 2 /3 6 xr(i) sin( /3  y ) xr1    sin( y + /3) 2 xr1  0; xr 2 =2    5 /3 sin(4 /3  y ) sin( y  2 / 3) x f 1 =  sin(4 /3  y ) sin( y  2 / 3) x f 2  2 0 0 5 /3 2 0 0 Table 4-8.Integration limit for line to line voltage Vab (t ) i ys(i) ye(i) xr(i)  1 2 3 4 xr1  0; 0 3 xr 2 =2     2 3 xf(i) 3 2 xr    xf1    sin( y -2 / 3) 4  3 5  3 6 5  3 2 xr1    1 sin(5 / 3  y ) sin( y - ) sin(2 / 3  y ) sin y -1 2 xr  2 -  x  0; 4  r1 sin(4 / 3  y ) 3 xr 2 =2    5 sin( / 3  y ) ; sin( / 3  y ) x f 2 =2 0 3  sin( / 3  y ) sin( / 3  y ) sin(2 / 3  y ) sin y  xf1   Idc -1 sin(4 / 3  y ) ; sin( y -2 / 3) x f 2 =2 x f 1  2    sin(5 / 3  y ) sin( y - ) 2 0 -1 1 1 The coefficients finally could be simplified into a closed-form expression in terms of Bessel functions, according to the following basic equality 138  e j cos   J 0 ( )  2  j k J k ( ) cos(k ) (4.22) k 1 (a) 15 10 5 0 -5 -10 -15 0 0.005 0.01 0.015 0.02 (b) Figure 4.38. Simulation results for SVPWAM CSI: (a) switching waveform (b) Input dc link current and output one phase current before the filter (c) input dc link current and output three phase current after the filter 139 Figure 4.38 (cont’d) 15 10 5 0 -5 -10 -15 0 0.005 0.01 0.015 0.02 (c) For current source inverter SVPWAM, the theoretical output line current could be calculated, which is also shown in Figure 4.38 (b) the green waveform. The numerical FFT analysis shown in previous section is conducted based on this waveform For the theoretical double Fourier Series form derivation for the output current, the same general equation as (4.21) has been adopted, but different integration limits are assigned for SVPWAM. Take S1 as an example. For sector I, the integration limit for x is [0, 2 ] ; for sector III, IV and V, the limit for x is [0,0]; for sector II, the integration limit for x is [0, 2 T1 / Ts ] & [2  2 T1 / Ts , 2 ] ; for sector VI, integration limit for x is [2 T1 / Ts , 2  2 T1 / Ts ] . The time range in a certain sector for S4 is the same with the time range of S1 in a sector which is 180 apart from the sector of S4 .The detailed closed-form expression will not be discussed here in detail. 4.4.4. Topologies for SVPWAM 140 Basically the topologies that can utilize SVPWAM have two stages: dc-dc conversion which converts a dc voltage or current into a 6 varied dc link voltage or current; VSI or CSI for which SVPWAM is applied. However, the two stage conversion can also be implemented in a single stage in some topologies, such as Z/quasi-Z/trans-Z source inverter. Some examples from these two categories of topologies are shown in Figure 4.39. Topologies (a)(b)(c)(e)(f) are proposed in previous literatures [26-29]. Topology (d) is a newly proposed topology here. These inverters all have voltage buck-boost function. All topologies except (b) have regenerative capability. However, if the front diode in (b) is replaced by an active switch, it can also conduct power in both directions. (a) Boost converter inverter L1 D1 C1 C2 Vin a b c L2 (b) Voltage-fed Z-source inverter [26] Figure 4.39. Possible topologies for using SVPWAM 141 Figure 4.39 (cont’d) L3 Vin L1 C1 D1 C2 L2 (c) Current-fed quasi-Z-source inverter [27,28] (d) Buck-boost-inverter (e) Buck-boost-converter-inverter (f)Two stage boost converter using the neutral point of motor[29] 4.5. Summary This section gives the general theory for three PWM modulation methods for current 142 source inverter. The new contributions of this section over the previous literature are:  A SVPWAM method has been proposed for current source inverter, to reduce the switching loss;  DPWM, CSVPWM and SVPWAM are all derived from SVPWM theory, and their equivalent carrier based modulation has also been derived;  Double Fourier form of DPWM and SVPWAM have been derived;  WTHD has been compared for all methods and the conclusion is: SVPWAM < DPWM_c < DPWM_d < DPWM_b < CSVPWM;  The SVPWAM method reduces the switching loss by 90% in VSI, by 70% in CSI at unity power factor condition, thus the power density is increased and the cost is reduced. 143 CHAPTER 5 SVPWM FOR Z-SOURCE INVERTER —ZERO VECTOR PLACEMENT 5.1. Introduction For motor drive application, the Z-source inverter is a promising new inverter to achieve lower cost and higher efficiency, which has been discussed in several papers [1-13]. It can S1 S3 S5 D1 C1 Vin C2 a b c S4 S6 S2 L2 (a) Voltage-fed Z-source inverter L3 Vin L1 D1 C1 C2 S1 S3 S5 a b c S4 S6 S2 L2 (b) Current-fed Z-source inverter C2 L1 Vin D1 C1 L2 S1 S3 S5 a b c S 4 S6 S 2 (c) Voltage-fed quasi-Z-source inverter Figure 5.1. Circuit configurations of Z-Source inverter 144 Figure 5.1 (cont’d) L3 C2 S1 S3 S5 L1 D1 Vin C1 To AC Load or Source L2 S 4 S 6 S 2 a b c (d) Current-fed quasi-Z-source inverter buck/boost voltage in a single stage, which overcomes the efficiency problem of the traditional two stage boost converter inverter solution. There are many kinds of modulation methods for current source inverter and voltage source inverter proposed previously. There are two basic types of modulation methods: carrier based regular sampled method (including continuous PWM [18-23] and discontinuous PWM[24-28]); space vector PWM control [27, 29-31]. Paper[22] utilized master and slave references to be compared with carrier directly to generate a switching pattern instead of using mapping method [20], but it didn’t reduce switching frequency or increase current utilization compared to SVPWM control. Paper[26] proposed two generalized discontinuous carrier-based pulse width modulation (GDPWM) methodologies for CSI to reduce the switching frequency further by 1/3. However, the discontinuous PWM introduces higher harmonics in the output and also higher temperature variation of the device package. paper[28] presented a vector PWM method to minimize the switching loss, by placing zero vector at proper sector and by injecting triplet harmonics. Similarly for current source inverter, the zero vectors can be intentionally arranged to bring down the switching loss. Paper[24] presented a dead-band PWM pattern which makes a 33% switching frequency reduction for a equivalent harmonic spectrum, compared to SPWM, but it has the same 145 problem as DPWM. Paper[34] concluded that the third harmonic injection method is better for low modulation but modified SPWM is better for high modulation in terms of harmonic and ripple current. Various types of Z-source inverter modulation have also been proposed in the old literatures. Papers [1, 4, 32-33] proposed the carrier-based PWM control method. Paper [4] presented a method utilizing the maximum shoot through duty ratio in order to achieve minimum voltage stress on active devices; however, the varied shoot through duty cycle may introduce six times base frequency harmonics in output. In order to overcome this problem, paper [32] proposed a maximum constant boost control which injects a zero sequence voltage in the reference to make the shoot through duty cycle constant. Papers [1, 33] presented a method which inserts the open zero state into the edge of PWM, in order to reduce the number of switching, however, it may cause larger power loss due to multiple times of diode reverse recovery. The evaluation process for different modulation methods has been researched by many papers [27, 35-38]]. Basically the evaluation criteria includes switching losses[84, 27, 28, 38-40], current/voltage ripple[34], harmonics[29, 36, 41, 42] and implementation complexity. PWM sequence is defined as a function of modulation index and power factor. From the state average point of view, each switching vector can be displaced anywhere within the switching cycle because the displacement has no effect on the amp-second average of the resulting current pulses corresponding to the reference vector[39]. The sequence of switching vectors should minimize the inverter switching loss, inductor current ripple and output voltage/current harmonics[31]. Paper[39] presented several kinds of switching sequences such as FSM, HSM, MHSM, MFSM, CSVM, and also concluded that CSVM is better than others if M<0.64. This paper selects the SVPWM control to achieve higher input current utilization, lower 146 switching loss and lower total harmonic distortions. For both voltage-fed and current-fed Z-source inverter, there are four switching states at any switching cycle, including two active states, one short zero state (shoot through state in voltage-fed Z-source inverter), and one open zero state. So there is more flexibility to arrange them to get the same volt-second equation, but different performance. In the modified SVPWM control method for this circuit, different PWM sequences can lead to different switching loss, current ripple, total harmonic distortion, and also the voltage spike on the switching devices. For each optimizing target, several rules which results in better performance have been summarized. A group of sequences have been sieved according to these rules. A complete analysis has been given to demonstrate the performance of the selected sequence based on aforementioned four criterions. A 15kW rated current-fed quasi-Z-source inverter has been built in the lab. This inverter has buck-boost and regenerative function [81]. Space vector PWM with optimized vector placement has been utilized on the hardware. In order to bring the prototype into real application in hybrid electrical vehicle[82-84], the inverter efficiency is measured according to the motor P-V curve. The estimated efficiency curve and experiment results are plot and compared. The best efficiency at full power rating reaches 97.6% at unity voltage gain. The peak efficiency reaches 98.2%. The efficiency from 3.5KW to 15KW is between 94% and 98%. Compared to two stage boost-converter-inverter in traditional HEV system, the efficiency has been improved by 3-4%. The power density of the 15kW prototype is around 15.3KW/L, which is also 5KW/L higher than the commercial unit in HEV. 5.2. The Influence of Zero Space Vector Placement Inductor current ripple PWM Figure 5.2 Centered PWM and back to back PWM and their corresponding current ripple 147 The main function of any PWM strategy is to identify the active pulse width within each carrier interval which contributes the same fundamental volt-second average as the original target reference waveform over that interval. While the position of the pulse within the carrier interval does not affect its cumulative volt-second average over that interval, it does significantly influence the harmonic performance of the switched output voltage. This is illustrated in Figure 5.2, which shows two possible pulse placements for a 50% duty cycle switched voltage applied to an inductive load which has a back electromotive force (EMF) equal to half the switched voltage. While the average current is zero in both cases, the current ripple magnitude when the pulses are centered in the carrier interval is significantly less than the current ripple magnitude which occurs when the pulses are positioned back to back to span across two carrier intervals. Furthermore, when the switched pulses are centered in each carrier interval, the current ripple frequency is twice that of the back to back pulse placement (this reflects the switched output voltage harmonics seen by the load in both cases). The conclusion to be drawn from this simple example is that modulation strategies which place their switched pulses closer to the center of each carrier interval have a superior harmonic performance compared to those which do not center the pulses, irrespective of how the switched pulse width is calculated. For a three-phase system, the placement of the active voltage pulses is constrained by the need to balance the pulse position across all three phases. From the way of how the active voltage pulses are distributed within a carrier period for the first 120 degree of the fundamental component, for regular sampled PWM, PWM+3rd harmonic injection, and space vector modulation where the active space vectors have been explicitly centered in each half carrier interval, it can be seen how the progression from regular PWM through third harmonic injection to space vector modulation progressively centers and improves the voltage pulse placement. An alternative modulation strategy which also achieves an improved pulse placement is 148 to add a common mode third harmonic of 1/4 reference magnitude, instead of 1/6 as described before. This approach centers the space vector pulses at 30 degree steps during the fundamental cycle, with minor deviations from the center within each 30 degree interval. Note however that the maximum possible modulation range without saturating is slightly reduced to 00.866, maximum constant boost and maximum boost have similar efficiency, which coincides with the voltage stress analysis. The conclusion is non-shoot through control would achieve minimum switching loss at voltage gain G<0.866; and above that, maximum constant boost control and maximum boost control can either be selected to achieve minimum switching loss. 7.4. Maximum Voltage Gain Control In ZS-MC, the boost factor B is not a monofonic function of D0 like the traditional Z-source inverter, thus the maximum voltage gain is not necessarily achieved at maximum 241 available D0. In ZS-MC, voltage gain is the function of M and D0, as shown in Table 7-3, with the restriction that D0 (t )  1  M , in which the equal sign can only be obtained at maximum boost control. To get the maximum G, assume that D0 (t )  1  k  M ( k  1 ), thus: G  MB  The maximum G happens at k  M 1 2 1 3M 2 [(k  )  ] 2M 12M 2 1 , which leads 2M (7.10) D0 (t )  0.5. Considering the restriction D0 (t )  1  M , when M>0.5, D0 (t ) should be the maximum available D0 (t ) , which is 1-M, because B is a monotone increasing function at D0   0, 0.5 ; thus the control strategy is identical to maximum boost control. When M<0.5, D0 (t ) should be equal to 0.5. So the maximum gain control law is:  D0 (t )  0.5    D0 (t )  1  M  ( M  0.5) (7.11) ( M  0.5) And the voltage gain Gg equations are: Simple Maximum Boost Non-shoot-through Voltage Gain G 1.5 Maximum gain Maximum boost 1.155 1 0.94 0 0 0.2 0.4 0.5 M 0.6 Figure 7.8. Maximum voltage gain vs. M 242 0.8 ( M  0.5) Gg  2M  M G  ( M  0.5)  g 2 3M  3M  1  (7.12) As shown in the green line in Error! Reference source not found.7.8. To implement the constant D0 at M<0.5, the shoot through reference curve has to be located between MX and MXo, or between MNo and MN, while keeping D0 (t ) =0.5. Assume the upper and lower reference curves for maximum gain control at M<0.5 is Vsh1 and Vsh 2 , thus: V (t )  Vsh 2 (t ) D0 (t )  1  ( sh1 )  0.5 MX (t )  MN (t ) (7.13) Similar to the maximum boost control case, one choice of the two curves are MXo and MNo at a constant M=0.5. In summary, the Vsh1 , Vsh 2 equations for maximum gain control are: Vsh1  Max(Vxo, Vyo, Vzo ) (Vx, y, zo  0.5sin(ot  ) (M  0.5)) Vsh2  Min(Vxo, Vyo, Vzo ) (Vx, y, zo  M sin(ot  ) (0.5  M  0.866)) (7.14) Figure 7.9. Shoot through references to generate D0 (t )  0.5 They are compared with the triangle to generate the shoot through PWM, as shown in Error! 243 Reference source not found.7.9. the red line is reference curve at M<0.5. The shadow part is the available shoot through area. 7.5. Hybrid minimum voltage stress control At a given target voltage gain, one criterion to select the control strategy is to minimize the voltage stress on the switch. Take voltage-fed Z-source matrix converter in Figure 2.12 (f) as an example. The voltage stress in ZS-MC is equal to B times the input line to line voltage. B is illustrated in Table 7-3. Different from traditional Z-source inverter, B here is not a monotonic function of D0 thus the minimum voltage stress is not necessarily achieved at maximum available D0. 1.4 Simple maximum Maximum Maximum constant Non-shoot through Voltage Gain G 1.2 1 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 Modulation index M 0.8 Figure 7.10. Control strategy selection at different gain ratio for ZS-MC From equation “ G  MB ”, to minimize voltage stress ratio B for a defined G, M is required to be the biggest available M. From the G-M curves in Figure 7.10 for four control strategies, different control strategy can be selected during different voltage gain range to obtain the maximum modulation index. The dash symbols show the selection of different curves in different sections. The executive 244 law of this kind of hybrid control is illustrated in Table 7-5 according to the cross points of the four G-M curves. By following this hybrid control curve, minimum voltage and current stress on the device can be achieved. Table 7-5.Control strategy for different G TABLE V. CONTROL STRATEGY FOR DIFFERENT G Control strategy Non-shoot-through Range of G G  [0, 0.866] Maximum constant boost G  [0.866,1.114] Maximum Boost G  [1.114,1.155] In the third range, only maximum boost can be utilized even it has higher harmonics because only this method can achieve high voltage gain. G=f(M) function becomes a quadratic function of which the maximum M is obtained in the section of M   0.667, 0.866 at the same voltage gain. Figure 7.11. Voltage stress at different voltage gain of hybrid control From equations in Table 7-3, the voltage stresses across the devices with different control strategies are shown in Figure 7.11. As can be seen, the hybrid minimum stress 245 control has the smallest voltage stress at the whole voltage gain range. In conclusion, for minimum stress purpose, traditional non-shoot through control is selected when voltage gain G<0.866; maximum constant boost control is selected when voltage gain is within [0.866, 1.114]; maximum boost control is selected when voltage gain is within [1.114, 1.155], in order to achieve minimum voltage stress on the device in the whole voltage gain range. 7.6. PWAM Control Method for Matrix Converter Figure 7.12. Nine switch direct matrix converter Figure 7.13. Equivalent decomposed circuit for nine switch direct matrix converter The 9 switch matrix converter can be equivalent to a series connection of a six switch rectifier and a six switch inverter, as shown in Figure 7.12. The dc link is an imaginary dc 246 link. This equivalence happens when two groups of switching functions have the following relationship:  S Aa   S Ba  SCa  S Ab S Ac   Sup   S Bb S Bc    Svp SCb SCc   S wp    T Sun   Srp Srn    Svn   S sp S sn    S wn   Stp Stn    (7.15) This equation is derived by utilizing the concept: If same switching function is obtained from different topologies, the waveform will be exactly the same. Since in nine switch matrix converter, the relationship between input and output is:  v A   S Aa     vB    S Ba  vC   SCa    S Ab S Ac  va    S Bb S Bc  vb  SCb SCc  vc    (7.16) In equivalent circuit, the relationship between input and output can be derived through the middle imaginary dc link: v An   Sup    vBn    Svp vCn   S    wp   Sup Sun   VDC       Svp Svn    VDC     S S wn    wp   T Sun   Srp Srn  va      Svn   S sp S sn  vb    S wn   Stp Stn  vc      (7.17) If the equivalence concept is applied into these two topologies, (7.26) can be derived. The space vector PWM control if used for modulation of direct matrix converter, this equivalent circuit also will be utilized. In Figure 7.13, the left side can be considered as a current source inverter, and the right hand side is a voltage source inverter. The current source inverter SVPWM takes dc link current as reference, including six active vectors and three zero vectors. Its equation and control diagram are as follows: 247 ia   Srp Srn    I DC        ib    S sp S sn      I DC    ic  S S    tp tn    0 1  1 0    0 0   0 1  0 0   1 0    0 0 1 0    0 1     Srp Srn     S sp S sn     Stp Stn    d  Ii d 0 0 0 1    1 0    (7.18) 1 0  0 0     0 1  1 0  0 1    0 0   Figure 7.14. Current source inverter space vector modulation diagram The synthesis equation for input current vector is:      Ii  d  I1  d   I 2 (7.19) 1 0    As shown in Figure 7.14, the switching state for I1 is 0 1  and the switching state   0 0    1 0      for I 2 is  0 0  . d  Ts is the pulse width for vector 1 and d   Ts is for vector 2. 0 1    The dc current can have lots of choices. For example, the envelope of the maximum line current is one of them. According to the power balance, the dc link voltage waveform is the inverse of the current. The output voltage equation and SVPWM diagram are as follows: 248  v An   Sup    vBn    Svp   vCn   S    wp  0 1 1 0    1 0    0 1 1 0    0 1    Sup   Svp   S wp  d 1 0  1 0    0 1   d Sun   VDC    Svn    VDC    S wn    (7.20) Sun   Svn   1 0  S wn     01   0 1     Vo 0 1 0 1   1 0    1 0  0 1   1 0    Figure 7.15. Voltage source inverter space vector modulation diagram The output voltage synthesis process is similar to input current synthesis. The zero vector period calculation is different from the traditional matrix converter because there are two extra states: the open zero state in input current source inverter and the shoot through zero state in output voltage source inverter. The traditional zero state periods thus can be calculated as: t 0  1  t1  t 2  top t 0  1  t1  t 2  tsh 249 (7.21) MX MD Sector I Sector II Iao Ioc Sap * 1 Sbp 0 Scp Sector III Sector IV Sector V Ibo Sector VI Ioa Ico Iob * 0 0 0 0 * 1 * 0 * 0 0 0 * 1 San 0 0 0 * 1 * Sbn 1 * 0 0 0 * Scn 0 * 1 * 0 0 * : Switching between 0 and 1 MX: Maximum line current envelope, also the average DC link current Ipn MD: Medium line current, also the PWM reference (a) Figure 7.16. PWAM control (a) DC current waveform and switching pattern in different sections (b) Simulated output current, dc current and switching state 250 Figure 7.16 (cont’d) 100 Ia Ib Ic 0 -100 200 Ipn 100 0 100 I1 50 0 2 1 0 Sap 2 1 0 -1 2 1 0 -1 Sbp Scp 0.005 0.01 0.015 t(s) 0.02 0.025 0.03 (b) Figure 7.16. PWAM control (a) DC current waveform and switching pattern in different sections (b) Simulated output current, dc current and switching state PWAM method proposed in paper [7] can be used here to control either rectifier or inverter, in order to reduce the switching loss and frequency. For example, if PWAM method is used for current source inverter, the control diagram is shown in Figure 7.16(a). DC link current will be the maximum envelope of three phase current, which is a 6 ripple current. The switching state changes according to which current takes up the maximum envelope. The total switching time will be reduced by 1/3 compared to SVPWM method, as shown in Figure 251 7.16 (b). If the voltage source inverter utilizes this modulation method, the switching loss can be reduced by 87.6% because the switching current is within [-600, 600], which is the smallest switching current portion in one cycle. Matrix converter can be considered as a rectifier in series with an inverter with no dc link capacitor. Thus the dc link current or voltage has more plasticity. Two control methods are proposed based on PWAM strategy, to achieve smaller switching loss, as shown in Figure 7.16 (a) and (b). Figure 7.17. PWAM control +PWM control for low switching loss MC: (a) method 1: PWAM rectifier + PWM inverter (b) method 2: PWM rectifier +PWAM inverter 252 Figure 7.18. PWAM control + PWM control for low switching loss MC  3 2 3  3 2 3 Figure 7.19. (a) switching waveform for current source inverter (b) switching waveform for voltage source inverter The detailed control block diagram is shown in Figure 7.18. In this method, both input current and output voltage are controlled with desired waveform and power factor. The CSR bridge power loss can be reduced by 1/3 in unity power factor compared to SVPWM. The efficiency is greatly improved when the input current varies in a large range because the dc link current is regulated according to the input current reference. Method 2 is to assign Vdc according to the output voltage command, as shown in Figure 7.17 (b). In this method, both input current and output voltage are controlled with desired waveform and power factor. The inverter bridge power loss can be reduced by 86% in unity 253 power factor compared to SPWM. The efficiency is greatly improved when the output voltage varies in a large range (since the dc link voltage is changed with the output voltage). As shown in Figure 7.17(b), the switching only happens in 1/3 switching cycle, thus compared to 1/2 switching cycle in SVPWM, PWAM can reduce the switching frequency by 1/3, thus the switching loss by more than 1/2; compared to SPWM, PWAM can reduce the switching loss by 87% since all its switching are at small current region. Since Idc becomes zero when shoot through state happens, when this PWAM method is transplanted to quasi-Z-source matrix converter, Idc is a pulse type PWM, but its maximum envelope is still the maximum envelope of the six line to line current, which happens in active state, as shown in Figure 7.16 (a) and (b). Thus the active switching state remains the same just part of the zero state has been transported into shoot through state. Figure 7.16 (b) shows the simulation result of the dc link current Ipn and also the maximum envelope of input three phase current. 7.7. CSR and VSI coordination Two CSR commutation happens during zero state of VSI. Zero dc link current is obtained during zero state of VSI. The first method is shown in Figure 7.20 (a). Its VSI carrier rising and falling rate depends on the width of the CSR PWM. The advantages of this method include (1) CSR commutates with zero current, which eliminates the switching losses; (2) no need for overlap between switches. The disadvantages of this method include: (1) unsymmetric carrier waveform (2) variable zero voltage vector. 254 Figure 7.20 (a) Coordination method 1 (b) coordination method 2 The second method is shown in Figure 7.20(b). The principle is to make zero vector of VSI happen when Idc is zero. Thus the zero current period is controlled by the carrier of VSI. The benefit of this method is that it has constant zero vector duty cycle. The switching frequency of VSI is 2 times of switching frequency of CSR. 7.8. New commutation and protection strategy For the nine switch direct matrix converter switching functions, two constrains have to be satisfied in order not to cause the short circuit of input voltage or open circuit for output current: one is the switches on the same output phase leg need to have deadtime; the other is the switches on the same output phase leg need to have overlap. These two seems contradictory with each other. However, the four step commutation for the two bidirectional switches on different input phases can implement this. The four step commutation can take source voltage as criterion or 255 Va S1b S1a iload Vb S2b S2a VaVb S1a S1a S1b S1b S2a S2a S2b S2b Figure 7.21. Voltage-based four step commutation load current as criterion. Figure 7.21 shows the equivalent circuit in four step commutation and also the voltage based commutation method. The current will change from phase a to phase b, so S1a , S1b need to be turned off and S2a , S2b need to be turned on. If load current is flowing out of the terminal, if S1a needs to be turned off, S2a has to be turned on first to provide a path for the load current. Thus S2a is turned on first. This also avoid the short circuit because when va  vb , it is impossible for S2a and S1b to form short circuit, so they can have overlap. After that, S2b needs to be turned on before turning off S1b , in order to provide a path for current. The short circuit through S1a and S2b doesn’t exist because they have deadtime. Similar analysis can be given when va  vb . These two cases have different switching sequence. Thus the problem comes out at the zero line to line voltage. Due to the sensor delay or inaccuracy, the following case can happen: the actual voltage still maintains 256 va  vb , but the measurement already becomes va  vb , thus the switching sequence already becomes va  vb . As shown in Figure 7.21, in this condition, the overlap of S1a and S2b forms a short circuit between phase a and phase b, and also the deadtime between S2a and S1b forms an open circuit for output phase A current. These two will cause high current spike and high voltage spike in the devices. Va Vb S1a S2a S1b iload S2b iload>0 iload<0 S1a S1a S1b S1b S2a S2a S2b S2b Figure 7.22. Traditional load current based four step commutation method The output load current can also be taken as the criterion to do the commutation, as shown in Figure 7.22. When iload>0, S1b and S2a can not have overlap; S1a and S2b can not have overlap; but S1a and S2a needs to have overlap, as well as S1b and S2b . The similar process happens when iload<0. The disadvantage of this commutation method is that failure will happen when the load current crosses zero. For example, when the actual iload is smaller than zero, but the measured iload is still bigger than zero, the sequence will be judged by the measured iload. So the overlap between input two phases and open circuit in one output phase will happen, to cause high voltage and current spike on the device. 257 Figure 7.23. Combined commutation method (a) current-based master voltage-based slave (b) voltage-based slave current based slave To be concluded, for voltage based commutation, the failure will happen in the zero line voltage point, due to the misdetection of the line voltage polarity; this can be caused by the detection delay and sensor offset, and it will cause the short circuit of input voltage sources. For current based commutation, the failure will happen in the zero line current point, which will cause the open circuit of the output. In order to solve this problem, the voltage and current based method can be combined to be alternately used, as shown in Figure 7.23. When the output current is small, voltage-based commutation can be used, but current-based method will also be used when the line voltage approaches zero. Similarly, when the input voltage is small, current based method will be the master and voltage based will be the slave method when line current approaches zero. 7.9. Protection strategy 258 Figure 7.24. Improved protection method for voltage-fed quasi-Z-source inverter Since the commutation failure still may happen in every utility cycle, the protection for the output open circuit is very important [8-9]. The conventional protection double rectifier method [8] can not be directly used in z-source matrix converter because the condition that input voltage is higher than the output no longer exists. The proposed method inherits the double rectifier circuit, but moves the input connection to the other side of the z-source network, as shown in Figure 7.24. The voltage at a’, b’,c’ is a PWM voltage with boosted voltage envelope. Because the shoot through happens at the same time for the nine switches, the three line to line voltage at a’b’c’ reach zero level at the same time in each switching period. Thus the diode bridge capacitor voltage will be clamped at the maximum envelope of the PWM type voltage, which is higher than the output voltage. So in normal condition, the right hand side diode bridge will not work. However, when output open circuit fault happens, the high spike voltage in the output will be clamped at the capacitor voltage, the diode bridge provides a path for the output inductor current in this case. 7.10. Practical Implementation of Control Method 259 The proposed PWM control for the simplified voltage-fed ZS-MC can be implemented in simple way when a digital signal processor (DSP) and a complex programmable logic device (CPLD) are employed. Then the duty cycle, ton, is calculated as ton1  M sin t1  MN Tc  MX1  MN 2 ton 2  M sin t 2  MN Tc  2 MX 2  MN ton  ton1  ton 2 (7.22) (7.23) (7.24) where MX1 and MX2 are the voltage values of top voltage envelope at instants t1 and t2, respectively; MN is the voltage value of bottom voltage envelope at instant t2. This can be illustrated by Figure 7.25. The upper figure shows the original carrier variable triangle waveform and the sinusoidal reference; the lower figure shows the newly generated constant carrier and new reference waveform. They generate the same PWM for the switches. The same equations (7.22)-(7.24) can be applied to a three-phase system to produce three PWM pulse sequences SA, SB, and SC. The produced PWM pulse sequences should be distributed to 9 ac switches in order to generate the expected PWM pulses. For this purpose, six additional logical signals are used to help the PWM pulse generation, where Sz1, Sx1, and Sy1 denote the indicators for their respective phase-c, phase-a, and phase-b of the top voltage envelope. For example, Sz1=1 when phase-c voltage is the largest value among the three phase voltages. Sy2, Sz2, and Sx2 denote 260 Figure 7.25. Transformation of the duty cycle Figure 7.26. Indicators of the voltage envelopes 261 the indicators for their respective phase-b, phase-c, and phase-a of the bottom voltage envelope. For example, Sy2=1 when phase-b has the minimum voltage among the three phase voltages. 7.11. Experiments results to demonstrate voltage boost function by using maximum boost control A prototype of the simplified voltage-fed ZS-MC has been built in the laboratory. Simulations and experiments have been carried out to verify the concept and theoretical analysis. In the experiment, the simplified voltage-fed ZS-MC was fed from the grid (source) and a R-L load was connected to the output of the ZS-MC. System parameters for both simulations and experiments are as follows: the Z-source network with Lz=1mH, Cz=330µF, the R-L load with R=20Ω, L=6.3mH, and the grid source frequency is 60 Hz. In order to demonstrate the operation of the simplified voltage-fed ZS-MC and to verify the control method, three cases have been investigated: (1) buck mode without shoot-through; (2) boost mode; (3) transition from buck mode to boost mode. (1) Case 1: buck mode without shoot-through The simplified voltage-fed ZS-MC works in the buck conversion mode when no shoot-through is inserted, operating just like the traditional MC. Figure 7.27 (a) and (b) show the simulation and experimental waveforms for the buck operation: shoot-through duty ratio D  0 , boost factor B=1, and G  BM  0.5 . The voltage gain measured at 0.43, which is consistent with the theoretical value of 0.5 considering voltage drops across the line impedance and MC switches. Figure 7.28 shows the PWM duty cycles calculated by (29)-(31), output 3-phase currents, and output phase voltage. The output 3-phase currents are 262 perfectly sinusoidal, which verify the proposed PWM method based on (29)-(31), and the logical functions. (2) Case 2: Boost mode with shoot-through Figure 7.29 (a) and (b) show the simulation and experimental results, in which M=0.5 and the maximum boost control was employed to boost voltage. From (21) and Figure 3.23, we know that the boost factor B should be 2.0 and the voltage gain should be one, i.e., G=MB=1.0. The measured voltage gain from the experiment was 0.992, which agreed well with the theoretical value. In the simulation, source harmonics and line impedance were included to mimic the real source power from the grid. Both simulation and experiment agreed well with each other. (3) Case 3: Transition from buck mode to boost mode This case shows the transition process from the buck mode to boost mode. At the beginning, the simplified voltage-fed ZS-MC operates in the buck mode without inserting any shoot-through, shoot-through states were suddenly added in the PWM pulses. Figure 7.30 shows this transition. It can be seen that both output voltage and load current suddenly increased after the shoot-through with the maximum boost control was introduced. The voltage gain increased from 0.43 to 0.992. The well-agreed simulation and experimental results confirm the operation of the simplified voltage-fed ZS-MC. 263 (a) Simulation results (b) Experimental results Figure 7.27. Buck operation of the simplified voltage-fed ZS matrix converter: from top to bottom, four traces are the input line-line voltage to the Z-source network, the output line-line voltage from the matrix converter, the output phase current from the matrix converter, and the input phase current to the matrix converter. 264 Figure 7.28. PWM duty cycles, output currents of three phases from the matrix converter, and the matrix converter’s output phase voltage, from top to bottom, respectively 265 (a) Simulation results (b) Experimental results Figure 7.29. Boost operation of the simplified voltage-fed ZS matrix converter: from top to bottom, four traces are the input line-line voltage to the Z-source network, the output line-line voltage from the matrix converter, the output phase current from the matrix converter, and the input phase current to the matrix converter. 266 (a) Simulation results (b) Experimental results Figure 7.30. Transition from the buck mode to the maximum boost control: from top to bottom, four traces are the input line-line voltage to the Z-source network, the output line-line voltage from the matrix converter, the output phase current from the matrix converter, and the input phase current to the matrix converter. 267 7.12. Simulation and Experimental Results to demonstrate hybrid minimum stress control To verify the theory analysis of the four control strategies, the simulations are conducted with the following parameters: Vim  100V , fi  60 Hz , fo  85 Hz , L  600uH , C  200uF , Lo  6mH , Ro  4 Prated  2.5kW (1) Demonstration of voltage gain equations and output harmonics through simulation To demonstrate the G-M curves in Figure 7.8, maximum constant boost control, simple maximum boost control and maximum boost control are simulated under M=0.6. Figure 7.13 shows the input source line voltage, output line voltage for traditional non-shoot through control. Figure 7.14 shows the output line voltage, input current at the source, input current before matrix converter and also the input voltage before matrix converter, for maximum constant boost control. Compared with the first case, this method increases the voltage gain. Figure 7.15 and Figure 7.16 shows simulation results for simple-maximum boost control and maximum boost control respectively. It can be seen that for simple-max and max boost, the output line voltage and input current is distorted, although it preserves a little big higher gain. For maximum constant boost control, both output voltage and input line current are controlled in a good shape, which posses much lower THD. 268 (a) Input voltage source line to line voltage (b) Output line to line voltage at the resistive load Figure 7.31.Simulation results at non-shoot through at M=0.6 269 Maximum constant boost control 150 100 50 0 -50 -100 -150 0.01 0.015 0.02 0.025 0.03 0.035 0.04 t(s) (a) Output line to line voltage at the resistive load (b) Input current at the voltage source 100 Maximum constant boost control 50 0 -50 -100 0.01 0.015 0.02 0.025 t(s) 0.03 0.035 0.04 (c) Input current right before matrix converter Figure 7.32.Simulation results at maximum constant boost at M=0.6 270 Line to line voltage in front of 18switch matrix converter(V) Figure 7.32 (cont’d) (d) Input line to line voltage right before matrix converter Maximum boost control 150 100 50 0 -50 -100 -150 0.01 0.015 0.02 0.025 t(s) 0.03 0.035 0.04 (a) Output line to line voltage at the resistive load (b) Input current right before matrix converter Figure 7.33.Simulation results at maximum boost control at M=0.6 271 (a) Output line to line voltage at the resistive load (b) Input current right before matrix converter Figure 7.34.Simulation results at simple-max boost at M=0.6 (2) Demonstration of voltage stress comparison analysis through simulation and experiments To demonstrate the B-G curves in Figure 7.11, simulation waveforms with different voltage stresses at the same voltage gain G=0.866 are shown in Figure 7.36, in which the switch voltage stress is represented by input line to line voltage right before matrix converter. It can be seen that at the voltage gain smaller or equal to 0.866, non-shoot through control preserves smaller voltage stress on the switch. In this special case G=0.866, maximum 272 constant boost posses the same voltage gain and voltage stress. But when G<0.866, non-shoot through has lower stress. At any case, maximum boost control has the highest stress among the three. A prototype is built in the lab to verify the proposed control methods. A 18-switch 600V/200A RB-IGBT module from FUJI corp. has been used as the matrix converter. And a Z-network with the aforementioned simulation parameters has been built and installed between dc voltage source and matrix converter. An inductive load with 6mH inductance and 4ohm resistor has been utilized. Input voltage is set to be 100V, 60Hz. The output voltage frequency is set to be 30Hz. To demonstrate the G-M curves in Figure 7.8, experiment waveforms of different voltage gains at M=0.661 and M=0.2 of four control strategies (non-shoot-through, simple maximum boost, maximum boost and maximum gain) are shown in Figure 7.37 and Figure 7.38, where the voltage gain is represented by the load current. Table 7-6 lists the theoretical voltage gains and measured simulation and experimental voltage gains. It can be seen that the simulation and experimental results are consistent with the theory analysis at both M>0.5 and M<0.5 cases. To demonstrate the B-G curves in Figure 7.11, experimental results with different voltage stresses at the same voltage gain G=1.073 and G=0.8 respectively are shown in Figure 7.39 and Figure 7.40, in which the switch voltage stress is represented by line to line voltage right before matrix converter Va ' b ' . The theory analysis, measured simulated results and experimental results for voltage gain and voltage stress at the 273 Output Line to Line Voltage(V) 150 100 50 0 -50 -100 -150 0.01 0.015 0.02 0.025 t(s) 0.03 0.035 0.04 Output line to line voltage(V) (a) Maximum constant boost control maximum boost control 100 0 -100 0.01 0.015 0.02 0.025 t(s) 0.03 0.035 0.04 0.035 0.04 (b) Maximum boost control Output Line Voltage(V) 150 100 50 0 -50 -100 -150 0.01 0.015 0.02 0.025 t(s) 0.03 (c) Non-shoot through control Figure 7.35. Output line to line voltage at G=0.866 for three methods 274 VoltageStressOnSwitch 200 100 0 -100 -200 0.01 0.015 0.02 0.025 0.03 0.035 0.04 Voltage stress on device(V) (a) Maximum constant boost control 400 200 0 -200 -400 0.01 0.015 0.02 0.025 t(s) 0.03 0.035 0.04 0.035 0.04 (b) Maximum boost control Voltage stress(V) 200 100 0 -100 -200 0.01 0.015 0.02 0.025 t(s) 0.03 (c) Non-shoot through control Figure 7.36. Input line voltage right before matrix converter at G=0.866 275 Vxy 100V/div Ia 50A/ div Ix 2A/div Figure 7.37. Voltage gain comparison at M=0.661: non-shoot-through control at t  [0, 0.1] and maximum constant boost control at t  [0.1, 0.2] Va ' b ' 100V/div Vxy 100V/div Ia 50A/div Ix 2A/div Figure 7.38.Voltage gain comparison at M=0.2: non-shoot-through control at t  [0, 0.1] ; maximum constant boost control at t  [0.1, 0.2] ; simple maximum boost control at t  [0.2, 0.4] 276 Va ' b ' 100V/div Vxy 100V/div Ia 50A/div T1 Figure 7.39 Voltage stress comparison at G=1.073: maximum boost control with M=0.542 at t  [0, 0.1] ; hybrid minimum voltage stress control with M=0.866 at t  [0.1, 0.2] . Va ' b ' 100V/div Vxy 100V/div Ia 50A/div T1 T2 T3 T4 Ix 2A/div Figure 7.40. Voltage stress comparison at G=0.8: Hybrid minimum stress control at t  [0, 0.1] ; simple maximum boost control at t  [0.1, 0.2] ; maximum boost control at t  [0.2, 0.4] ; same G are shown in Table 7-6 and Table 7-7 and they are consistent with each other. It also can be seen that the hybrid control can achieve less voltage stress than other control strategies In conclusion, the simulation and experiment results demonstrate that maximum gain 277 can be achieved at the maximum gain control and minimum voltage stress across the switch can be achieved through hybrid minimum voltage stress control. Table 7-6.Voltage gain comparison at certain M theory M=0.661 Simulation Experiment theory M=0.2 Simulation Experiment G G G G G G N-S Simple-Max Max Max-Const 0.66 0.41 1.16 1.08 0.69 0.35 1.2 1.01 0.72 0.33 1.15 0.95 0.2 0.3 0.28 0.21 0.22 0.15 0.12 0.23 0.19 0.1 0.08 0.18 Table 7-7.Voltage stress comparison at certain G Minimum Maximum Simple stress Boost Max B 1.24 1.696 -- G=1.073 Simulation B 1.42 1.923 -- Experiment B 1.442 1.73 -- Theory B 1 -- 1.997 Simulation B 1 -- 2.08 Experiment B 1.08 -- 2.13 Theory G=0.8 7.13. Summary In Z-source matrix converter, the insertion of shoot through state brings the voltage boost function to the traditional matrix converter. This chapter proposes three methods to introduce shoot through state: simple maximum boost, maximum boost and maximum constant boost. In terms of voltage gain, maximum boost control and maximum constant 278 boost control can make voltage gain exceed 1. In terms of harmonic distortion, maximum constant boost control and non-shoot through control posses much lower THD than other methods. In terms of voltage stress and switching loss, maximum boost and simple maximum boost control would bring higher voltage stress and switching loss to the devices. In conclusion, at voltage gain smaller than 0.866, traditional non-shoot through control is the optimum control for Z-source matrix converter, and at voltage gain higher than 0.866, maximum constant boost control should be utilized. At voltage gain higher than 1.144, which is out of the voltage gain range of maximum constant boost control, maximum boost control can be used. The proposed hybrid minimum stress control has been fully demonstrate by simulations and experiments. In addition, a concept of Pulse-Width-Amplitude-Modulation (PWAM) has been proposed for Z-source MC control. In summary, the benefits of PWAM with maximum constant boost shoot through control for this circuit are (1) High efficiency at wide output voltage and current range;(2) low low-order output current harmonics;(3) low input current spike (lower input current value);(3)low input and output line voltage spike (Lower input and output voltage value);(4)low switch voltage and current stress;(5)high power factor. 279 CHAPTER 8 DISCONTINUOUS OPERATION MODE 8.1. Introduction The circuit analysis and control methods proposed for current-fed quasi-Z-source inverter are based on one important assumption: the capacitor voltage is almost constant and equal to the input voltage. This assumption becomes invalid when the capacitor is very small or the lower power factor is low in some applications that the volume is a very crucial factor. The capacitor voltage has high ripple or even becomes discontinuous in these cases. This is similar to the discontinuous operation mode of boost converter, which has discontinuous inductor current instead at low inductance and low power factor. In these cases, the circuit has two new operations modes except for the normal three modes, which is called discontinuous operation modes. This section analyzes the characteristics of the discontinuous operation modes, and derives the critical conditions for these new modes under different control strategies. Simulation and experiment results are given to verify the theoretical analysis. L3  L1 Vin D1  C1  C2 S1 S3 S5 a b c L2 S 4 S 6 S 2 Figure 8.1. RB-IGBT based current-fed qZSI configuration with discontinuous input current 280 Table 8-1. Definitions of the variables C L Capacitance of capacitors in Quasi-Z network Inductance of inductors in Quasi-Z network Input current of the current-fed qZSI Iin Current through the inductors of the Quasi-Z IL network Current through capacitors of the Quasi-Z network IC Current fed to the inverter bridge Ipn Current through the switch of inverter bridge Is Output peak phase current iac Output phase rms current Iorms Input dc bus voltage Vin Voltage across the capacitors of the Quasi-Z network VC Vl-lpeak Output peak line to line voltage Output phase rms voltage Vorms Modulation index M Open zero duty ratio Dop Current boost factor B Open zero state in one switching cycle Top Switching period Ts Load impedance Z cos(Φ) Load power factor 8.2. Two discontinuous modes when capacitance is small or load power factor is low 281 Figure 8.2. Possible operations modes of current-fed qZSI: (a) mode 1(b) mode 2, (3) mode 3, (4) mode 4, (5) mode 5 The novel current-fed qZSI can buck/boost voltage and achieve bidirectional power flow without replacing the diode with an active switch, due to the two extra open zero states. The basic control principle is to turn some of the short zero state into open zero state. Figure 8.2. (a) (b) (c) shows the equivalent circuits of the current-fed qZSI in continuous mode which is detailed analyzed in paper [3]. The basic operating principle assumes that the capacitor voltage is almost constant and equal to the input voltage. However, the capacitor voltage can have high ripple or even becomes discontinuous when the capacitance is low or the load power factor is low. So there are two additional operation modes in discontinuous mode, similar to the new modes in voltage-fed Z-Source inverter [4]. (Miaosen’s paper) Mode 1-3 (Continuous modes): Mode 1: active state, the inverter bridge is in an active state and the dc link voltage V pn is equal to the equivalent output voltage Veq ; the diode is off if the equivalent voltage satisfies Veq  2Vin . Mode 2: Short zero state, the inverter bridge is equivalent to a short circuit by turning on the upper and lower switches in the same phase leg 282 or in the same two phase legs, or three phase legs together. The dc link voltage is zero, so the diode is off. Mode 3: Open zero state, the inverter bridge is equivalent to an open circuit by turning off all the upper switches or turning off all the lower switches. The diode is turned on, so the dc link voltage is equal to sum of the two capacitor voltage. Mode 4 (Discontinuous mode I): In open zero state, the diode is on and the inverter bridge is off. So the capacitor is being charged. But in other two states, the capacitor keeps discharging because the unchanged inductor current. At the end of mode 2, if the capacitor voltage decreases to be smaller than half of the output line to line peak voltage in short zero state, at the moment that the inverter is switched to active state again, the diode in quasi-Z network will be turned on because the voltage drop on the diode is positive. But the diode in RB-IGBT will be reverse biased; the inverter is equivalent to an open circuit. The capacitor will be charged again in this new open zero state. This state is described in Figure 8.2(d). In mode 4, the capacitor voltage satisfies VC  Vl lpeak / 2 . Mode 5 (Discontinuous mode II): At the end of Mode 4, when capacitor voltage increases to be equal to half of the output peak line to line voltage and the inverter bridge is still switched in active state, the diode in QZ-network will be reverse-biased. So the capacitor voltage will stay at Vl lpeak / 2 until the end of active state. But the voltage drop on the RB-IGBT is still smaller or equal to be zero, the inverter bridge is still in open circuit state. The equivalent circuit of Mode 5 is shown in Figure 8.2(e). This mode will also happen when the capacitor voltage decreases to be equal to half of the Vl lpeak in mode 1. The switch will still be switched in active state, but the circuit will enter into mode 5 until the end of active state. In mode 5, the capacitor voltage and inductor current satisfies: 283 VC  Vl lpeak 2 , I I L   in 2 In this paper, the discontinuous mode is defined as a new mode when the capacitor voltage satisfies VC  Vl lpeak / 2 . In another word, when open zero state or critical open zero state happens during the time of active switching, discontinuous mode happens. So mode 4 and 5 are included in discontinuous mode. At the same time, two assumptions have been made to discuss these modes: (1) The inductor is big enough to maintain constant current direction in motoring mode; (2) RB-IGBT has enough voltage rating. To be concluded, mode 4 happens when capacitor voltage already falls below Vl lpeak / 2 when active state switching starts; in this case, the QZ source diode will be forced on and inverter switch will be reverse biased; the circuit is equivalent to the open zero state. Mode 5 happens when capacitor voltage increases from lower than Vl lpeak / 2 to equal in active state switching period; in this case, inverter switch will be reverse biased and capacitor voltage stays at Vl lpeak / 2 until the end of active state. These two discontinuous operation modes change: (1)voltage gain equation, due to that part of active states is transferred into open zero state, in which the output equivalent voltage is equal to two times of capacitor voltage, not the output line to line voltage; (2) capacitor voltage ripple, which becomes much bigger than continuous mode; (3) device voltage stress, because the device voltage stress is equal to two times of capacitor voltage, of which the maximum value is greatly increased. 8.3. Capacitor voltage waveform in discontinuous modes DCM has two basic degrees defined here: the first is the capacitor voltage decreases to below half of output line to line voltage but above zero; the second is the capacitor voltage 284 decreases to zero. In discontinuous mode, the capacitor voltage has big ripple. It decreases below half of output line voltage in mode 4 and keep equal to that in mode 5. When capacitance reduces even more, in mode 4, it may decrease to zero and maintain zero in mode 5. The advantages and disadvantages of these discontinuous operation modes are: this DCM mode if can be utilized, it will only need a much smaller capacitance. And the voltage boost ratio can go beyond 2; However, the voltage stress on the capacitor and device will be increased to even 2 times. Figure 8.3 Two discontinuous operation modes Different modulation methods will yield different discontinuous waveforms due to different sequences and combinations of the operation modes. The specialty of current-fed quasi-Z-source inverter is it has four basic circuit states in one switching cycle including two active states, one short zero state and one open zero state. Thus the switching sequence is more flexible and complex, which makes more variations in discontinuous mode characteristics. For example, in SPWM based modulation, different design and location of the shoot through control reference waveforms result in different control strategy, such as simple boost control, maximum boost control, maximum constant boost control etc. In SVPWM control, there are totally 24 sequences to place the four vectors. Although it is reduced to 19 after eliminating some redundant cases, the variation is still much bigger than 6 in three 285 Top Tsh Vc 2 2 TshTop 2 2 Top Tsh 2 2 2 3 TA 3 Tsh TA 2 2 4 5 25 3 TA TshTop 2 2 Tsh Top 2 2 Vlpeak 2 Mode 3 24 5 325 4 5 25 3 (a) Capacitor voltage waveform under SPWM control Vc Top TshT1 & T2Tsh Vc Top Tsh T1 & T2Tsh Vl-lpeak/2 Operation modes Vl lpeak 2 3 2 1 5 2 3 2 1 5 2 2 (b) Capacitor voltage waveform under SVPWM control sequence 1 (maximum constant boost control) Top TA Tsh Top TA Tsh Top Tsh TATsh Top Vc Vlpeak 2 Operation Modes (c). Capacitor voltage waveform under SVPWM control sequence 2 Figure 8.4. Capacitor voltage waveforms at different modulation methods 286 Figure 8.4 (cont’d) Top TA Tsh TA TshTop 2 2 2 2 2 2 Vc Vc Top TA Tsh TA TshTop 2 2 2 2 2 2 Vlpeak 2 Operation Modes 3 1 2 1 52 3 3 1 2 1 5 25 3 (d). Capacitor voltage waveform under SVPWM control sequence 3 Vc Top TA Tsh TA TshTop 2 2 2 2 2 2 Top TA Tsh TA TshTop 2 2 2 2 2 2 Vlpeak 2 Operation Modes (e). Capacitor voltage waveform under SVPWM control sequence 4 vector cases. Several examples from SPWM method and SVPWM method are listed below to present the different capacitor voltage waveforms. 8.3.1. SPWM Control -Maximum Constant Boost Control The SPWM control for traidtional current source inverter is based on the on-line carrier-based PWM pattern generator. The principle is to first generate the votage source inverter control signal and then map them into current source inverter through the state machine equations. The mapping equations are derived by matching the SVPWM diagram of 287 VSI and CSI. To be extended, the principle to control current-fed Z-source inverter in SPWM way is first to generate the control signals for voltage-fed Z-source inverter and then map them to current-fed ones. There are two differences from the traditional ones: 1) To utilize the extra switching state, part of traditiona state needs to replaced by new state; to implement this, an extra shoot through reference is utilized to also compared with the carrier voltage; by different waveforms and placement of the shoot through reference, the control method is categoried into simple boost control, maximum boost control, maximum constant boost control, and so on. 2) the shoot through state in voltage-fed ZSI is mapped into open zero state in current-fed ZSI; thus a new mapping equation about these two need to be built. In every switching cycle, one open zero state, one of the three short zero states are used along with two adjacent active states to synthesize the desired current. The basic principle of maximum constant boost control is to generate a maximum available constant shoot through duty ratio. It can not boost voltage as high as maximum boost control since the shoot through duty ratio is not the maximum all the time, but it can eliminate the low frequency current ripple, which greatly reduces the output harmonics. The side effect is to reduce the size of qZ-source network and at the same time, to reduce the current stress of the switches [5], by using a greater current boost for any given modulation index. The time sequence of the PWM is as following: Top , Tsh,T1, T2 , Tsh,Top . Assume the output voltage are the same in two active states during one switching cycle, then there will be two possible operation conditions, continuous voltage mode (CVM) and discontinuous voltage mode (DVM), shown as the second and the third waveforms in Figure 8.4 (a), respectively. The CVM is characterized as that the capacitor voltage is not decreased to zero. 288 The DVM is characterized as that the capacitor voltage falls to zero and stay in zero for a certain period of time, which happens when the capacitor is in a much smaller value or the power factor is very low. In each switching cycle, the circuit starts with an open zero state Top, during which the capacitor is being charged and the capacitor voltage increases with time. After Top, the inverter switches to traditional short zero state. The capacitor voltage keeps decreasing until it reduces to half of the output line to line peak voltage. If short zero state still doesn’t end at this point, the capacitor voltage will continue to decrease to be smaller than that. When active state starts, capacitor voltage begins to increase, which is characterized as mode 4. If it increases to be equal to half of output peak voltage before the active state ends, mode 5 comes into play by keeping the capacitor voltage almost constant and turning off the diode D until the end of active state. When the circuit turns into traditional short zero state the second time, the capacitor voltage will continue to decrease until the end of short zero state. During the whole switching cycle, the capacitor voltage is continuous; therefore this operation condition is termed as CVM. If the capacitance is extremely small or the load power factor is relatively low, it is possible that the capacitor voltage decreases to zero in the second half short zero state and remains zero until the next switching action. It is called DVM shown in the second one in Figure 8.4 (a). If the capacitor is even smaller, the capacitor voltage is also possible to fall to zero at the first time it enters into short zero state, as shown in the third figure of Figure 8.4 (a). At these two DCM case, the output voltage waveform will be affected and also the voltage gain will be tuned. 8.3.2. SVPWM Control 289 The basic idea of SVPWM control for current-fed qZSI is to turn some of the short zero states to open zero states [3]. In order to make the current stress on the inductor lowest, Dop should be designed to be zero at motoring operation and to be maximum at regeneration operation [3]. So the best operation point for voltage boost mode is when Dop  0 , which is same as traditional CSI; and the best operation point for voltage buck mode is when Dop  1  D A , which means turning all the short zero state into open zero state at a fixed modulation index [3]. The instantaneous Dop varies with time, but the average duty ratio in each sector is constant. In order to keep Dop a constant value during a whole switching cycle to reduce the output harmonics and switching current stress, the average Dop is used. So the short zero state still exists with open zero state. As long as the volt-seconds satisfy the voltage gain requirement, the division of the switching period and the placement of each vector can be flexible without affecting the output voltage waveform and value. The thing it affects is the input current ripple, device switching loss and output harmonics. Four examples of SVPWM have been given in Figure 8.4 (b), (c), (d). (e). Take sequence (c) as an example. Its sequence is Top , TA, Tsh . In Top , the capacitor voltage increases; in TA , capacitor voltage decreases. If it decreases to be equal to Vl lpeak / 2 before the active state ends, the circuit enters into mode 5, in which the capacitor voltage will keep at Vl lpeak / 2 level until the end of this active state. After that, in short zero state, the it will continue to decrease until the end, which is in mode 2. The next period starts with capacitor voltage being charging in open zero state. Thus there is only mode 5 in this sequence. In this process, if the capacitor is small enough or the power factor is extremely low, it is possible for the voltage to fall to zero during short zero state. In this 290 case, the mode 4 appears. The other sequences can be analyzed similarly to sequence (c). It is found that only sequence (e) has mode 4 & 5, and others only has mode 5 unless it enters into DCM. To be concluded, different modulation methods result in different capacitor voltage ripple; same modulation method but different switching sequences also cause different capacitor voltage ripple. Different ripple contributes to different output voltage ripple, thus harmonics. These differences also affect the critical conditions for discontinuous mode to happen. 8.4. Critical conditions for discontinuous mode Figure 8.5. The factors causing discontinuous operation mode Using a small capacitance can reduce the volumn and cost of the system, but at the same time, discontinuous operation modes will occur, in which the device understakes higher voltage stress. In addition, the current fed into the inverter is no longer always constant during active states, which causes additional harmonics in output voltage and current. So the critical condition of the discontinuous operation mode becomes important to the design of the capacitor. The basic discontinuous operation critical condition is: VC min  291 Vl lpeak 2 (8.1) To guide the design procedure, this condition has to be transformed into the inequality in terms of the circuit parameters or control parameters. The possible factors that affect this operation mode is shown in Figure 8.5. The following related variables or parameters is summarized: (1) output power factor (2) output impedance (3) Z-network dc capacitance (4) control methods and variables, such as modulation index, shoot through duty cycle etc. In order to derive this, the general capacitor voltage ripple equation has to be derived first, and then the basic critical condition can be applied to that to obtain a complete critical condition equation. 8.4.1. Capacitor voltage ripple As analyzed above, the capacitor voltage increases only in open zero state. So the peak to peak value of voltage ripple is: Vc  iCTop C  ( Iin  I L )Top C (8.2) Since the average capacitor voltage is equal to the input voltage [3], which can be obtained from input power and current, the minimum VC can be obtained from (3.2) and (8.2): VC min  Vin  Vc / 2  1  Dop P ( IinTop 2C ) Iin 1  2 Dop (8.3) Assume the load impedance is Z. From the power balance, the input power can be calculated by output current as: P 3 ˆ 2 Z (iac ) cos  2 (8.4) 8.4.2. Critical Condition of different shoot through control methods in SPWM method: 292 For maximum constant boost control, the basic principle is to make the open zero duty cycle constant at the maximum limit of available short zero state period. In order to make the open zero duty ratio constant and maximum, the maximum open zero duty ratio is achieved as: Dop  1  ( M sin   M sin(  2 ) 3 ) max  1  2 3 M 2 (8.5) , where  is the phase angle of current vector .The expressions for upper envelope V p and lower envelope Vn is similar to voltage-fed ZSI which has been derived in paper [5]. (to state this equation here for further references) Since the basic critical equation for the discontinuous mode is: VC min  Vl lpeak (8.6) 2 Substitute the derived maximum Dop into the equation for VC min , the critical condition for discontinuous mode can be derived as follows: 3M 3 (2  3M )Ts cos   1 6 CZ 2( 3M  1) (8.7) When this condition is satisfied, the circuit starts to have discontinuous modes. For constant boost control, the shoot through reference is equal to the modulation index M. The maximum open zero duty cycle is (1-M). Thus the critical condition can be expressed as: 2(1  M )Ts 3M  1 2(2M  1) 3ZC (8.8) For maximum boost control, Dop is maximum available open zero duty cycle at any moment, which varies with phase angle: Dop  1  ( M sin   M sin(  2 ) 2 293 3 ) (8.9) But its average value is a constant value, which can also be taken to calculate the critical condition:  /3 Dop  0 1 ( M sin   M sin(  2 )  /3 2 3 )  1 3 3M 2 (8.10) Together with the voltage gain equation, the critical condition of discontinuous mode for maximum boost control is: 3M  3(2  3 3M ) Ts 1 cos   CZ 2(3 3M   ) 2 2 (8.11) 8.4.3. Critical condition for SVPWM method The best operation point for voltage boost mode is when Dop  0 , which is same as traditional CSI; and the best operation point for voltage buck mode is when Dop  1  DA , which means turning all the short zero state into open zero state at a fixed modulation index [3]. The instantaneous Dop varies with time, but the average duty ratio in each sector is constant. In order to keep Dop a constant value during a whole switching cycle to reduce the output harmonics and switching current stress, the average Dop is used. So the short zero state still exists with open zero state. The average Dop can be calculated through integrating and averaging in one 600 sector:  Dop   3 (1  0 3 3 3  M sin(   ))d   1  M 3 2 3 2 (8.12) In order to achieve least switching times[3], choose the time sequence of the PWM in SVPWM control in voltage buck mode is as following: Top , T1, T2 , Tsh . The CVM and DVM condition are shown in Figure 8.4 (c). The critical condition for SVPWM control can be obtained from (8.3), (8.6) and (8.12) as follows: 294 3 2    3  2  cos  3 3 M 1 1 Voltage boost mode  (8.13) 1  3 3 M 2T s  1 Voltage buck mode 2 cos   6M 2 CZ  M  3 Table 8-2.Characteristics of different control strategies Control strategy B Dop 1 2M  1 Constant Boost Maximum Boost 1 3 3M 2 Maximum constant boost 1 1  M 3 3M   3 3M   1 3M  1 M 3M  1 3M 2 SVPWM(Buck Mode) M 2M  1 1-M 3 3 M 2 SVPWM(Boost Mode) Control Strategy 1 Iin 2M  1 M 3 3M   3 3M   Maximum constant boost SVPWM(Buck Mode) SVPWM(Boost Mode) 2 3 3M 1 Is Constant Boost  0 Maximum Boost G Critical Condition 2(1  M )Ts 3M  1 2(2 M  1) 3ZC  3M  3(2  3 3M ) Ts Iin cos   1 3 3M   CZ 2(3 3M   ) 2 2 Iin 3(2  3M )Ts 3M 1 cos   6CZ 2( 3M  1) 3M  1  Iin 3 3 M 2  3 3M 2Ts 1 cos   2 6 3M  2 CZ 3 3M   2 2 3 cos  Iin 1 2 3 3M /   1 At this point, all the critical conditions for different modulation methods have been derived and listed in Table 8-1. 8.5. Simulation and experimental demonstration 295 Iin L3 L1 iL1 C1 D1 iL 2 C2 V pn L2 Figure 8.6. The circuit configuration in the experiment Figure 8.7. (a) First version of 5kW current-fed quasi-Z-source inverter with separate inductors (b) second version of 5kW current-fed quasi-Z-source inverter with coupled inductors. 296 (a) From the top to bottom: device voltage stress, dc capacitor voltage, input current (b) From the top to bottom: device voltage stress, dc capacitor voltage (Zoomed in) Figure 8.8. Experimental results of the CVM condition under SVPWM control for voltage buck operation (Vpn: DC link voltage across the inverter bridge; Vc: qZ-network capacitor voltage; Iin: input inductor current; Vab: load line to line voltage; Ia: load phase current) 297 Figure 8.8 (cont’d) (c) From the top to bottom: output line to line voltage, output phase current To verify the aforementioned theoretical analysis, a RB-IGBT module based current-fed qZSI prototype has been built in the laboratory with the following parameters: C=1uF, L=1mH, Vin =100V, f s =10kHz, f=60Hz (output frequency), and Z  5 per phase Y-connection. Experiments of the system using SVPWM control and modulation index of 0.923 are performed. Under these parameters, the system works in CVM condition. Figure 8.8 (a) (b) (c) show the experimental results in voltage buck mode. The open zero duty ratio satisfies equation (8.12), which is set to be 0.19: In Figure 8.8 (a), V pn has four levels: the highest level is equal to two times of the capacitor voltage which happens in open zero states; two output line to line voltage, which happens in active states; and the zero level is corresponding to short zero states. The capacitor voltage increases in open zero state and decreases when it enters into active states; when it decrease to be equal to half of the output line to line voltage, it remains constant until the end of active state; when the short zero state starts, it decreases again until the next switching action. This waveform agrees with theoretical analysis result shown in Figure 8.4 very well. Figure 8.8 (b) is the enlarged 298 waveform for VC and V pn . It demonstrates the discontinuous mode 5. The maximum pn voltage is 375V, which is equal to two times of maximum capacitor voltage. It is obvious that the output voltage range becomes smaller than the continuous case because of the high ripple of the capacitor voltage Figure 8.8 (c) shows the output line to line voltage and phase current. The current gain in continuous mode with this parameter should be 1.75. But from the ˆ experiment results it can be seen that Iin =16.25A and iac =20A; so the current gain ˆ becomes iac / ( 3Iin / 2)  1.42 . It shows that the current boost factor in discontinuous mode is lower than in continuous mode with the same modulation index and the same control method, which is because some of the active states become open zero states in discontinuous operation, and make the inductor current decreases more than normal condition. The System specifications are: L1  L2  L3  1mH , (Coupled ), C1  C2  10uF , VIN  100V , fo  60 Hz , f sw  10kHz , Z  5; 8.6. Summary  The discontinuous modes can happen in the condition the capacitance in the quasi-Z network is small or the load power factor is low;  There are two discontinuous modes except the normal continuous modes;  The changed variable in discontinuous mode compared to continuous mode is the capacitor voltage; the non-changed variable is the output voltage and current.  Different control methods can yield different circuit characteristics due to different modulation methods and different switching sequences. The key point to derive the critical condition in order to avoid or utilize this discontinuous mode is to analyze the maximum available open zero duty cycle, since the maximum capacitor voltage 299 ripple VC is obtained at maximum open zero duty cycle. The critical condition for discontinuous mode is a function of dc capacitance, modulation index, load power factor, load impedance and switching frequency.  To be utilized, the discontinuous operation can reduce the requirement for capacitance, thus reduce the system size; in addition, its voltage boost ratio can exceed the limit at 2. However, the capacitor voltage rating and device voltage rating, as well as output voltage harmonics will be increased. From this stand point, this mode should be avoided. One method is to make the parameters not satisfy the critical condition; another method is to replace the diode with an active switch which can be controlled to be turned off at all active states and traditional short zero states. 300 CHAPTER 9 CIRCUIT MODELING AND TRANSIENT ANALYSIS 9.1. Introduction In hybrid electrical vehicle (HEV) motor drive, the operation mode changes from motoring to regenerating very frequently, either in decelerating period or braking period. In order to analyze precisely in which condition the motor drive inverter needs to do this transition, the complete operation modes of both parallel HEV and series HEV are illustrated as follows [3]. (a). Medium power operation mode 1 (b) High power operation mode 2 (c)Low power operation mode 3 (d)Regenerative braking operation mode 4 Figure 9.1. Four operation modes of parallel hybrid vehicles (F: Fusion tank; E: Engine; B: Battery; P: Power converter; M: Motor; T: Transmission) In parallel hybrid vehicle configuration, there are two independent paths connected with transmission line. One path is composed of fuel tank and engine. Another path is composed of battery, power inverter and motor. They both can provide power directly through the transmission line. It has four utilized operating modes [3] shown in Figure 9.1. and outlined in the following: 301 A. Mode 1, medium power At medium power, the power of vehicle traction motor is only provided by the engine. And the motor can operate as a generator to charge the battery when its SOC (State Of Charge) is low. B. Mode 2, high power During acceleration, both engine and battery will provide power to the motor. Battery speeds up the vehicle’s response time for acceleration and also maintains a safe and efficient operation point for engine. C. Mode 3, low power The engine efficiency decreases when operated under low power. So the engine is turned off and the traction motor is only driven by the battery. D. Mode 4, Regenerative braking During regenerative braking, the electric motor acts as a generator to generate electric power from the torque of the motor which slows down the vehicle. This electrical energy will be used to charge the battery. Thus the motoring to regenerating transition happens each time when the vehicle switch to either mode A or D. (a). Medium power operation mode 1 (b) High power operation mode 2 Figure 9.2. Four operation modes of series hybrid vehicles 302 Figure 9.2 (cont’d) (c). Low power operation mode 3 (d) Regenerative braking operation In series hybrid vehicle configuration, both of engine energy and battery energy go through power converter to drive the motor. It also has four utilized operating modes but different with the parallel hybrid vehicle since all the power in battery needs to be provided through power converter, as shown in Figure 9.2 with the following outline: A. Mode 1, medium power At medium power, the power of vehicle traction motor is provided by the engine; at the same time the engine needs to provide power through power generator side power converter to charge the battery when its SOC (State Of Charge) is low. At this moment, the generator side power converter operates at regeneration mode. B. Mode 2, high power During acceleration, both engine and battery will provide power to the motor. Battery speeds up the vehicle’s response time for acceleration and also maintains a safe and efficient operation point for engine. At the same time, the engine will charge the battery when its SOC becomes low. C. Mode 3, low power The engine efficiency decreases when operated under low power. So the engine is turned off and the traction motor is only driven by the battery. But at the same time, the engine will charge the battery through converters when the battery’s SOC is low. D. Mode 4, Regenerative braking 303 During regenerative braking, the electric motor acts as a generator to generate electric power from the torque of the motor which slows down the vehicle. This electrical energy will be used to charge the battery. To be concluded for series HEV, the transition from motoring to regenerating happens in all four modes when its SOC goes low. Therefore, a fast transient response is a necessary characteristic that the HEV motor drive converter should possess. The traditional motor drive is implemented by a series boost converter and a voltage source inverter, since the battery voltage is usually only half of the dc link voltage that the inverter needs. A approximate 2 boost ratio is required in the front stage of inverter. It is common sense that this topology can implement the transition from motoring to regenerating very fast, because the transition is presented in the form of input current direction change, which is supposed to be fast in voltage source inverter. Here comes the doubt about current source inverter: the big inductor in the input of current source inverter may cause a much slower response to the current direction change command. If this is a problem, the big inductor in boost converter also causes a slow transition response. If this problem can be overcame by properly designing the inductor and capacitor parameters in the circuit, the same procedure can be conducted for the single-stage current-fed quasi-Z-source inverter. The structure of this chapter: (1) A state space model has been built for current-fed quasi-Z-source inverter to demonstrate that it has fast transient response that it only needs several switching cycles to transfer from motoring mode to regeneration mode, which makes it very suitable to be used for HEV or EV motor drive. (2) Both abc and dq state space model 304 is built for current-fed Z-source rectifier to demonstrate its transient performance theoretically. (3) A generalized state space model based on connection matrix has been built for all the topologies in switched-coupled-inductor inverter family, in order to derive all the governing equations including voltage/current gain and voltage/current stress, and also for transient analysis. 9.2. Current-fed quasi-Z-source inverter 9.2.1. Research target Ig Vin Ig Vin Vg Vg Figure 9.3. Block diagram of transition from motoring mode to regenerating mode The research target topology is the current-fed quasi-Z-source inverter, which introduces the extra open zero states and makes buck-boost and regeneration capability possible. The plot of its voltage gain versus the active duty cycle DA has been shown in Figure 3.5. In motoring mode, the maximum voltage gain is 2. But the negative voltage gain in regeneration mode has no such limit. However the 2 boost ratio is enough for the normal design of battery voltage and dc link voltage. This section concentrates on the transition performance of this inverter from motoring operation mode to regenerating operation mode, which is presented in the form of that the input inductor reverses its current direction, as well as the output inductors, as Figure 9.3 shows. Theoretical model and simulation, experiment demonstrations will be given in the following parts to get the transition time duration for the reverse of input current. 305 9.2.2. Circuit Modeling I dc + Vin - Ldc L1 I dc + VC C2 - C1 + - L2 + Ldc L1 Vout VC C2 Vin L2 C1 - (a) (1- Dop) (b) Dop Figure 9.4. Circuit model for two basic circuit states (a) non-open-zero state (b) open zero state The mathematical model for this transition can be built to predict the transient performance of the pre-designed circuit, in terms of response time, voltage/current overshoot/undershoot amplitude and phase, rise time, settling time and so on, thus form a design guideline. The transient performance of the circuit can be simplified into the transient waveform of the input current. The basic idea is to obtain the input current waveform in the transition from solving the differential equations. The state average model method is used to solve the equation for the input dc current I dc in the transition. There are two basic circuit states (a) non open-zero state (b) open zero state shown in Figure 9.4. So the general state space equation of this switching mode circuit should have state space averaging method applied. In non open-zero state, the inverter is considered as a voltage source, and in open zero state it is an open circuit. The state average model of this equivalent circuit states are expressed in eq. (9.1):  dI L   0  dt      dVC   2 Dop  1    dt   C    dI dc    0  dt      1  2 Dop L 0 2 Dop L  0   Vout     I L    L (1  Dop )  Dop     0   VC    C   V  (1  D )V  I  in op out  r   dc       L  L  306 (9.1) , where the definitions of the variables are lined out in Figure 9.5 and also the inductance, capacitance satisfy: L1  L2  Ldc  L, C1  C2  C ; There are three differential equations in terms of three variables I L (Z-network inductor current), VC (Z-network capacitor voltage) and I dc (Input current). The Dop is considered as a constant in every steady-state, which is assigned by the voltage boost ratio requirement and also the best operation point constraint. The only unknown variable here is the average pn voltage in active state Vout ; however, it can be derived from voltage and the duty cycle function as: Vout  DaVca  DbVcb  DcVcc . In order to calculate Vout , assume the output capacitor voltage to be sinusoidal function with amplitude Vm as follows:   Vm sin(t )   vca    2      vcb Vm si n(t  3 )   vcc     2  Vm sin(t  ) 3   (6.2) The duty cycles can also be considered as sinusoidal with amplitude M (modulation index) and angle  with respect to voltage:    M sin(t   )   Da    2    Db  M sin(t    )    3   Dc     2   M sin(t    )  3   (6.3) , in which    for motoring mode, and    for regenerating mode. Through calculation it is found that the average pn voltage in active state is a constant value: Vout  3 M 'Vm 2 (6.4) ,where M '  M for motoring mode and M '   M for regenerating mode. So the final simplified equation with all variables known except the ones that is going to be solved is: 307  dI L  0  dt      dVC   2 Dop  1    dt   C    dI dc    0  dt      1  2 Dop L 0 2 Dop L   3 M 'Vm  0   2  (1  Dop )  IL    L Dop      (6.5) 0  VC   C       I dc   Vin  (1  Dop ) 3 M 'Vm  r  2      L   L  To be concluded, the state space average mode of this circuit in motoring and regenerating mode is shown in equation (6.5), with M’=M in motoring mode and M’=-M in regenerating mode. The next step is to solve the input current I dc from this equation. 9.2.3. Initial conditions and steady state conditions The transition process is simulated by connecting the current-fed quasi-Z-source inverter to the grid at the output side. The grid current is the control object. The motoring operation is equivalent to inject current to the grid, and the regenerating operation is equivalent to absorb current from the grid. The transition between the two starts from grid current control command change, and ends up with the output phase current and input inductor current reach a steady state with negative direction. Figure 9.5. shows the circuit configuration to demonstrate the transition performance. The current-fed quasi-z-source inverter is supplied by the dc source generated by the rectified grid voltage, and the inverter output is connected to grid to supply a constant current. An important note here is a resistor has to be connected in parallel with the dc link capacitor, to provide an energy consumption path for regeneration mode. Otherwise, the capacitor will be charged up continuously since the diode rectifier can 308 I dc Ldc I L L1 D1 C2 Rdc Cdc VC C L2 1 Vsa,b,c 6000uF = L1 C2 D1 C1 200 uF 8500 V 85  1200 V I gc Cs 1mH L3 1mH 0.3m, 0.1 Vga,b,c I ga I gb L2 0.3m, 1m 6500 V 65  1200 V 651200 V 60 uF 0.1 85120 V 0 Control Strategy M  Motoring 0.7  300 SPWM With open zero state Dop  0.1 0.7  1500 0.7  900 Mapping to CSI S1 S2 S3 S4 S5 S6 At t=200mS Regenerating 0.3371500 0.337300 0.3372700 SPWM With open zero state Dop  0.675 Mapping to CSI S1 S2 S3 S4 S5 S6 Figure 9.5. Circuit configuration to monitor the transition process not send the energy back to the input side. This circuit configuration actually is also similar to the series hybrid vehicle motor drive system, in which the input voltage is its generator and the output voltage is its traction motor. To simulate the transition process, the grid current I ga command is changed from 1800 A 309 to 181800 A (0 degree means the current is in phase with the grid voltage and 180 degrees means the current is out of phase with the grid voltage), so as the command of phase b and c, at the time of t=0.2s. The mathematical model for the transition has been built to calculate the transition time for the mode change. The reason to build this mathematics model is to form a pre-design guide line for the system. The transition time is defined by the time that the input dc current changes from positive direction steady-state to negative direction steady-state here. When the circuit mode changes from motoring to regenerating, the transient response of the output line current has the linear relationship with the input dc inductor current. If the input current can reverse its direction fast, the output current can also change its phase from 0 degree to 180 degree in a short time. The transient expression for the input dc inductor current as a function of time can be derived using the state space average model in equation (5). From t=0s, the circuit works in motoring mode and the grid current command is I gref  1800 A , which is in phase with the grid voltage. At t=200ms, the current command changes to I gref  181800 A , which is out of phase with grid voltage. The circuit is changed to regeneration mode. The direct command change according to the voltage and current ratio equation of this circuit, is: the modulation index and open zero duty cycle change from [0.65, 0.3] to [0.25, 0.6]. The initial conditions of the system are: I L (0 )  I L (0 )  0; VC (0 )  VC (0 )  Vin  100V ; I dc (0 )  I dc (0 )  30 A; Vm  85V M (0 )  0.65, Dop (0 )  0.03; M (0 )  0.25, Dop (0 )  0.6 And the parameters are: L=1mH, r=0.7, C=200uF; 9.2.4. Solution for input current 310 Simplify the differential equation into the single equation about Idc as the following third order differential equation: 1 7 19 1400 I dc ''' (t )  I dc '' (t )  I dc ' (t )  I dc (t )  6050  0 1.2e004 6 12 1.2e006 (6.6) The characteristic equation of this time domain differential equation is: s3  700s 2  19*1.2e006 / 6  s  1400*1.2e006 /12  0 And the roots are s1  37; (6.7) s2  331  j1915; s3  331  j1915 Solve the equation with the following initial and steady-state conditions: I dc (0 )  30 A; I dc ()  8.3 A; I dc '(0 )  132 Thus the final solution is： I dc (t )  3.79e37t  42.19e331t sin(1915t  1.4)  8.4 (6.8) Plot the I dc (t ) in Figure 9.5. It is shown that the transition time from motoring to regenerating tT  1ms , which is 10 switching cycles in this case (fsw=10kHz). Figure 9.6. Calculated input current waveform in transition starting at t=0.2s 9.2.5. Simulation and experiment demonstration In order to verify the theory analysis, the circuit in Figure 9.5 has been simulated with the following parameters: 311 Ldc  1m, rdc  0.7, Cdc  12000uF , Rdc  4.12; C1  C2  200uF , L1  L2  1mH Mode Cs  60uF ; Lg  0.3mH , rg  10m,Vga  8500V ; Rs  0.3m, rs  0.1m,Vsa  6300V . changes from motoring to regeneration at t=200ms. Figure 9.7. (a)Simulation results (1) Output phase A Current (2) output phase A Voltage (3) input inductor current (4) Z-source capacitor voltage in motoring to regeneration transition (at t=0.2s) (b) Zoom in results of (a) 312 Figure 9.7 (cont’d) Figure 9.7. (a)Simulation results (1) Output phase A Current (2) output phase A Voltage (3) input inductor current (4) Z-source capacitor voltage in motoring to regeneration transition (at t=0.2s) (b) Zoom in results of (a) The simulation results are shown in Figure 9.7. The mode changes from motoring to regenerating happens at t=200ms. The measured other variables changes are shown in Table 9.1: Table 9-1. Simulation results in mode change transition Ioa(A) Motoring 18∠0 Idc(A) Vin(V) M Dop 30 89 0.65 0.25 -14 103.89 0.03 0.6 transition time(s) 0.00109 Regenerating 18∠180 313 Figure 9.8. Comparison between calculated Idc and simulated Idc Iga magnitude(Calculated) Iga magnitude(Simulated) 40 Transition time t=1ms 30 20 I(A) 10 0 -10 -20 -30 0.198 0.2 0.202 0.204 t(s) 0.206 0.208 0.21 Figure 9.9. Comparison between calculated Iga amplitude and simulated Iga amplitude The simulation demonstrates that the transition time is around 10 switching cycles. The comparisons between calculated results in section I and the simulation results are shown in Figure 9.8. and Figure 9.9. It can be seen that the simulation results match with the theory equation (6.8) quite well. And the transition time from motoring to regenerating is about 10 switching cycles. The exact number of switching cycles that the transition requires is not a fixed one but not very different for different cases. 314 9.2.6. Conclusion The current-fed quasi-Z-source inverter exhibit a fast transient response when its operation mode changes from motoring to regenerating. It only needs several switching cycles to reach a steady state. This feature makes it suitable for HEV/EV application. The large signal state-space average model effectively estimates the transient. 9.3. Three phase current-fed Z-source PWM rectifier 9.3.1. PWM rectifier state space model (a). State I – Short Zero: Dsh (b). State II—Active: DA Figure 9.10.Operation states of current-fed Z-source PWM rectifier 315 Figure 9.10 (cont’d) (c). State III—Open Zero: Dop The equivalent circuit of modeling for current-fed Z-source rectifier has been shown in Figure 9.10 and all the variables are defined. The switching function of a switch in Figure 9.10 is defined as 1, switch closed  Si (t )   0, switch open  i  a, b, c (6.9) If the switching frequency is much higher than the utility frequency, the switching function Si can be replaced by its average value in non-open zero state of one switching period. The three-phase source voltages and the average switching function for each leg of the converter Dn (n  a, b, c) in non-open zero state are defined in (9.10).     Vm sin(t )   Dm sin(t   )   vsa     Da    2     2      vsb   Vm sin(t  3 )  ;  Db    Dm sin(t  3   )   vsc   D     2   c   2 Vm sin(t  )   Dm sin(t    ) 3  3    (6.10) ,where  stands for the angle between input current and phase voltage. From Figure 9.10, the input currents satisfy: 316 va,b,c 1 d r i1,2,3   i1,2,3  vC1,2,3  dt Ls Ls Ls (6.11) While in non-open zero state, I pn  2 I L  I dc  1 I dc 1  2 Dop (6.12) So the overall equation for capacitor voltage in non-open zero state and open zero state can be derived as: i1,2,3 i pn Da,b, c i1,2,3 d   vC1,2,3  (1  Dop )( )  Dop dt Cs Cs Cs i1,2,3  Da,b,c (1  Dop ) I 1  2 Dop dc Cs (6.13) For dc output voltage and current, one has : V r I V d I dc  dc  dc dc  D dt Ldc Ldc Ldc I V d Vdc   dc  dc dt Cdc Cdc R0 (6.14) The dc link voltage V pn has different expressions in open zero state and non-open zero state: non  open zero state  Da vC1  Db vC 2  DC vC 3 V pn   open zero state 2Vdc (6.15) The average value for V pn is V pn  (1  Dop )( Da vC1  Db vC 2  Dc vC 3 )  Dop  2Vdc (6.16) In Z-network, V pn  VC  VL and VD  VC  VL So VD  2VC  V pn  (1  Dop )( Da vC1  Db vC 2  DC vC 3  2Vdc ) 9.3.2. Z-Source network state space model 317 (6.17) From equivalent circuit for Z-network in Figure 9.10, one has: In non-open zero state (1  Dop ) , d    dt I L   0    d V   1  C   dt   C 1  1    I L   0  L   I dc  L         VC   1   V pn    0 0   C  (6.18) In open zero state Dop , d    dt I L   0   dV  1  C   dt  C 1 L   I L   0 0   I dc          VC   0 0   V pn    0    (6.19) So the overall state space equations for Z-network is 1  2 Dop d    dt I L   0 L   2 Dop  1 d     VC   0  dt   C Dop  1     I  0  L   I dc   L        VC   1  Dop   V pn    0      C  (6.20) 9.3.3. Current-fed Z-source rectifier dq state space model From Figure 9.10 and equations (6.9)-(6.20), the state model of current-fed Z-source rectifier can be obtained. It is a time varying three phase system because of the average switching functions; however, it can be converted into a rotating synchronous frame (d-q-0) using Park transformation, and the transformed matrix is shown in (6.21). 318 1  r  0 0 0 0 0  L   L   did  s  s   dt  r 1        0 0 0 0 0   diq   Ls Ls   dt    id   v Dd (1  Dop )    1 sd 0 0  0 0 0  dVcd     iq   Ls Cs Cs (1  2 Dop )   dt      V   v   Dq (1  Dop )   cd   sq  dVcq  0 1  0 0 0 0  Vcq   Ls Cs (1  2 Dop )  dt   Cs     dI dc   I dc  0 Dd (1  Dop )  Dq (1  Dop )  rdc 2 Dop  1     0 0   dt  0 0  Vdc  0 Ldc Ldc Ldc Ldc     dV   dc     I L  0  1 1 0 0    0  dt  0 0 0 0  Cdc Cdc R0   VC    dI   L   1  Dop 1  Dop 1  2 Dop    dt  0 0 Dd Dq 0 0 0  L L L  dVC        dt  0 0 0 0 1  Dop 0 2 Dop  1 0    C C                (6.21) The equivalent duty ratios in the d-q domain can be obtained form the Park’ transformations as given below: 1   d q   2 m cos       d d   1 m sin     2    (6.22) The obtained model is a non-linear time invariant system. Small signal linearization around its DC operating point can be done by assuming that: ^ ^ ^ ^ id  I d  id , iq  I q  iq , vCd  VCd  vCd , vCq  VCq  vCq , ^ ^ ^ ^ idc  I dc  I dc , vdc  Vdc  vdc , vC  VC  vC , iL  I L  iL ; ^ ^ (6.23) ^ dop  Dop  dop , d d  Dd  d d , d q  Dq  d q By substituting these equations into (6.21) and separating steady state components from dynamic variables, the small signal AC model can be obtained in equation (6.24). 319   d ^   r   1 0 0 0 0 0   id   Ls Ls   ^  dt     id  r 1  d ^    0  0 0 0 0     iq  Ls Ls ^   dt    iq  Dd (1  Dop ) d ^   1 0 0  0 0 0   ^   vcd  Cs (1  2 Dop )  Cs    dt    vcd  d ^  Dq (1  Dop ) 1  ^   vcq  0  0 0 0 0  C  vcq  Cs (1  2 Dop )  dt  s      d ^    ^  Dd (1  Dop ) Dq (1  Dop ) rdc 2 Dop  1  i 0 0  idc     dt dc  0 0  Ldc Ldc Ldc Ldc   ^     v  d ^   1 1  v   dc  0 0  dc  0 0 0 0   dt Cdc Cdc R0   ^   ^    iL  d i   1  Dop 1  Dop 1  2 Dop  ^  L  0 0 Dd Dq 0 0 0  dt   v  L L L    C  d ^    vC  0 0 0 0 1  Dop 0 2 Dop  1 0   dt     C C   0 0    0   0 0    0  ^  I dc (1  Dop )    0  vsd    Dd I dc 1 1  1 Cs (1  2 Dop ) ) (  L     2 4 ( Dop  1 )2  s    Cs  2 I dc (1  Dop )  ^ 0     vsq  C (1  2 D )  1  Dq I dc 1 1  s op (  )    ^    1 2 L  VCd (1  Dop ) VCq (1  Dop )   d d   Cs 2 4 ( Dop  2 )  ^  s       d0 p  0 Dq Ldc Ldc 2     ^   Dd  0 0 0   d q   L VCd  L VCq  L Vdc  dc dc 0    dc  1  Dop  0  1  Dop    VCd VCq 0     D V  D V  2V  L d Cd q Cq C 0  L     0 0    L 0    I  2I   dc L       C                         (9.24) 9.3.4. Initial conditions and steady state conditions The steady state operating point affects the dynamic response and it can be obtained from solving the state space equation (6.21). Assume that the position of q axis is the same as the ac side capacitor voltage space vector, which makes VCd  0 , so the solution can be 320 further simplified into: Vdc  Dq R0 (2 Dop  1)(1  Dop )( LsVsd  rVsq ) (6.25) (r 2 Dq 2   2 Dq 2 Ls 2 )(1  Dop )2  rR0 (1  2 Dop )2 Vcq  IL  Vdc (2 Dop  1) I dc (1  Dop ) (1  2 Dop ) Vc  (6.26) Dq (1  Dop )  Vdc (1  Dop ) (6.27)  R0 (1  2 Dop ) (1  Dop ) DqVcq 2 Dop  1  Vdc (6.28) , which are coincident with the circuit analysis in section III. From (44), due to the limit of voltage step down operation, i.e. the highest output voltage is determined by the maximum value of Dq , which is 0.5 from (38). Therefore the maximum output to input voltage conversion ratio for a given open zero duty cycle is given Dq (1  Dop ) (1  Dop ) V  , which is coincident with (3.23). as: dc  Vcq 2 Dop  1 2(2 Dop  1) 9.3.5. Initial conditions and steady state conditions Small-signal frequency analysis has been carried out to determine how certain rectifier state variables vary with input variables within a given frequency range. The general model for DC side variables can be obtained from the lower four rows of equation (6.24). ^ ^ The transfer function of VC / dop can be obtained as follows: ^ G1  VC ( s ) ^ dop ( s )  (2 Dop  1)(Vcq  2VC )  sL(2 I L  I dc ) s 2 LC  4 Dop 2  4 Dop  1 Dynamic response is shown in Figure 9.11 for the operation condition Vcq  64V , m  0.4, L  2mH, C  200uF, Dop  0.65,VC  Vdc  85V , IL  9.5A, Idc  8A; 321 (6.29) Based on this dynamic response, the closed loop controllers are adjusted for required bandwidth and phase margin. The details of the controller design will not be discussed here. 150 100 50 0 200 100 0 -100 1 10 100 1000 ( rad / sec) 4 10 5 10 ^ ^ Figure 9.11 Frequency response of the transfer function of VC / dop 9.4. Switched-coupled-inductor inverter 9.4.1. Steady state analysis for voltage-fed topology Take VF-SCII 2 as the representative of voltage source inverter. VF-SCII 2 has two operating states: shoot through state and non-shoot through state, as shown in Figure 9.12. Shoot through means turning on the upper and lower switches on the same phase leg at the same time. If the shoot through is chosen to happen during the normal zero state, it will not affect the output voltage and current. However, the front inductor gets charged during shoot through state, so the inverter can boost voltage. The two equivalent circuit states of VF-SCII 2 are shown in Figure 9.12. When the inverter bridge shoot through happens, the front diode automatically turns off, and inductor 2 gets charged. In non-shoot through state, the diode is 322 on, and inductor 1 gets discharged. The inverter can be considered as a current source with equivalent voltage Vout in this case. In the whole switching period, the energy in the coupled inductor gets balanced, which means the total turns current product (N*I) keeps constant. (a) (b) Figure 9.12. Inverter b operating states (a) shoot through state D0 (b) non-shoot-through state 1  D0 In shoot through state, L1 has zero current, but L2 is charged by C1. In non-shoot-through state, L1 and L2 are in series and charged by the voltage difference between source and capacitor. The inductor voltages in two states are: n 1  (Vin VC1); VL2_1   (Vin VC1) VL1_1   n 1 n 1  VL1_2  nVL2  nVC1; VL2_2  VC1  / /at (1 D0 ) (6.30) / /at D0 , in which n is the trans ratio between L1 and L2, and D0 is the shoot through duty cycle. Each inductor current is discontinuous since it has different expressions at different circuit states during one switching cycle. In another word, it has jump during one switching period. But the total flux in the inductor keeps constant. So a continuous unit inductor current can be defined here: iL  niL1  iL 2 (n  1) (6.31) This current can be taken as the state variable in the state space model since it is continuous. 323 Therefore, take unit inductor current iL and capacitor voltage VC as the state variables, then the state space equation of VF-SCII 2 is: 1 1  diL  L dt  1  n (VL1_1  VL 2 _1)  1  n (Vin  VC )   C dvC  i  n i L load  dt n 1  1  diL  L dt  1  n (VL1_ 2  VL 2 _ 2 )  VC   C dvC  (1  n)i L  dt   at (1  D0 ) (6.32)  at D0  The steady state solution for inductor current and capacitor voltage could be obtained by using state space average method. The average inductor current and capacitor voltage are:  diL 1  D0  (Vin  VC )  D0VC L  dt 1 n  C dvC  (1  D )(i  n i 0 L load )  D0 (1  n)iL  n 1  dt (6.33) The volt-seconds and ampere-seconds balances impose: L dv diL  0; C C  0; dt dt (6.34) Thus the averaged iL and vC can be derived as: IL  1  D0 n(1  D0 ) iload ; VC  Vin 1  nD0 1  nD0 (6.35) The equivalent output voltage in non-shoot-through state in average model can also be derived as: Vout  VC 1  Vin 1  D0 1  nD0 (6.36) Thus the boost ratio of the switched-coupled-inductor network is: B 324 1 1  nD0 (6.37) The voltage gain between input and output then can be expressed as, by using that D0  1  3M / 2 : G  MB  M  1  nD0 M 3 1  n(1  M) 2 (6.38) , from which it can be seen that this inverter has voltage buck-boost function. The current stress on the active devices in inverter bridge is equal to output current in non-shoot through state. But the maximum current stress depends on the current in shoot through state, which is the inductor 2 current in this case. According to the flux constant equation: (n  1) iL  1 iL 2 ' (6.39) The L2 current in shoot through state can be derived as: iL 2 '  n(1  D0 ) 1  nD0 (6.40) , which is also the current stress on the active device. 9.4.2. Generalized state space model for the voltage-fed family Assuming the non-shoot-through state is state I and shoot through state is state II, the generalized state space equation for all topologies in the voltage-fed family in no load case is: L 0      0 0  IL   C       FLC (n  1)   VC   K LC  FLC   FLg  K LC   I L         K Lg  Vin  V 0   C   FCg     (6.41) The definitions of the coefficients are: FLC : connection between L & C: when L charges C, FLC  1 ; when C charges L, FLC  1 ; when there is no connection FLC  0 ; 325 K LC : per unit number of turns of the inductor that injects current to capacitor; the base value is the smaller number of turns in two inductors. FLg : connection between L and source; if current flows from source to inductor, FLg  1 ; otherwise FLg  1 . FCg : connection between C and source; FCg  0 in this case. Therefore for each circuit state shown in Figure 9.12, a state space equation can be obtained for each circuit. The average capacitor voltage and average inductor current then can be derived by using average method. Their general forms are: [ D0 FLg1  (1  D0 ) FLg 2 ] K Lg1 K Lg 2 VC  V FLC1 FLC 2 in D0  (1  D0 ) K LC1 K LC 2 IL  (6.42) D0 FCg1  (1  D0 ) FCg 2 V FLC1 (n  1) FLC 2 (n  1) in D0  (1  D0 ) K LC1 K LC 2 (6.43) The general form for the voltage-fed switched-coupled-inductor inverter family can be further derived as:  diL  L dt  (1  h0 )  (GLC1vC  GLg1Vin )  h0  (GLC 2vC  GLg 2Vin )  riL  C dvC  (1  h )(G i  G v  G V ) CL1 L CR1 C cg1 in 0  dt   h0 (GCL 2iL  GCR 2vC  Gcg 2Vin )    M  Li dii  (hi  h0  1 ( hi  M  h0 ))(1  h0 )  dt M i 1   [Vin  kw (GLC1vC  GLg1Vin )]  vi (i  1, 2..M )   C dvi  i  vi (i  1, 2..M ) i  i dt R  , in which 326 (6.44) FLgi F F F ; GCgi  FCgi ; GLCi  LCi ; GCLi  CLi ; GCRi  CRi ; GLgi  K Li KCi R K Si i  1, 2,..N ( N is the number of circuit states in one switching cycle) Definition of the coefficients in the generalized state space equation of the voltage-fed SCII family: FCLi : FCLi   FLCi ; FCRi : when resistor current flows into positive side of capacitor, FCRi  1 ; when it flows into negative side, FCRi  1 ; when there is no connection, FCRi  0 . K Li : the total number of turns in per unit of the inductors that connect with the corresponding capacitor and also exchange energy with it. KCi : the number of turns in per unit of the single inductor that connects with the capacitor and also exchanges energy with it. K Si : the total number of turns in per unit of the inductors that connect with the voltage source and also exchange energy with it. K w : the number of turns in per unit of the inductors that between source and the inverter bridge; it is positive when the inductor voltage positive side connects with the source, and negative when the negative side connects with the source. K sw : per unit number of turns between input source and the dc side switch; it is positive when the source current flows into the positive side of the inductor with per unit 1 number of turns; otherwise it is negative. 9.4.3. Governing equations for voltage-fed family From the generalized state space equation, the governing equations for the inverter voltage 327 TABLE 9-2. VOLTAGE GAIN AND ACTIVE/PASSIVE DEVICE STRESS FOR VF-SCII Passive Stress Vc/Vin (1  D0 ) VF-SCII 1 1+nD0 Voltage Gain IL/iload n(1  D0 ) 1+nD0 Vout/Vin 1 1+nD0 VF-SCII 2 (1  D0 ) 1-nD0 -n(1  D0 ) 1-nD0 1 1-nD0 VF-SCII 3 (n  1)(1  D0 ) 1  n(1  D0 ) n(1  D0 ) 1+n-nD0 (n  1) 1  n(1  D0 ) VF-SCII 4 (n  1)(1  D0 ) 1  n(1  D0 ) -n(1  D0 ) 1-n+nD0 VF-SCII 5 n(1  D0 ) n(1  D0 )  D0 n(1  D0 ) (n  1) D0  n n n(1  D0 )  D0 VF-SCII 6 n(1  D0 ) n(1  D0 )  D0 -n(1  D0 ) (-n  1) D0 +n n n(1  D0 )  D0 n  1 1  n(1  D0 ) INV I Stress Frong Switch Stress Isw/Iload Vfs/Vin Ifs/Iload VF-SCII 1 n(1  D0 ) 1+nD0 1 n 1+nD0 1 1+nD0 VF-SCII 2 n(1  D0 ) 1-nD0 1 n 1-nD0 1 1-nD0 VF-SCII 3 n(1  D0 ) 1+n-nD0 1 1+n-nD0 1  n 1+n-nD0 VF-SCII 4 n(1  D0 ) 1-n+nD0 1 1-n+nD0 1  n 1-n+nD0 VF-SCII 5 (n  1)(1  D0 ) (n  1) D0  n n(1  D0 )  1 n(1  D0 )  D0 n nD0  D0  n VF-SCII 6 ( n  1)(1  D0 ) ( n  1) D0  n n(1  D0 )  1 n(1  D0 )  D0 n  nD0  D0  n gain, inverter switch current stress, capacitor voltage stress, inductor current stress and front switch voltage and current stress could be derived, as listed in Table 9-2. The trans-ratio are 328 defined in Figure 9.12. 9.4.4. Steady state analysis for current-fed family CF-SCII 2 is taken as an study example here. It has two operating states shown in Figure 9.13. The extra open zero state has a duty cycle of D0 . (b) open zero state D0 (a)Active state Figure 9.13. Two operation states of current source inverter h The volt-seconds equation on L1 leads to: (1  D0 )(Vin  Vout ) 1  D0Vin  0 1 n (9.14) Thus the expression for Vout / Vin is: Vout / Vin  1  nD0 1  D0 (9.15) Thus when n<1, it can boost voltage; when n>1, it can buck the voltage; when n goes to even bigger that n  1 , it enters into regeneration mode. D0 9.4.5. Generalized state space model for current-fed family Similar to previous voltage-fed equations, the generalized state space equation for the family of current-fed SCI inverter in no load condition is: 329 L  0     0 0  IL    C      FLC V    C  K LC FLC   FLg  K LC   I L         K Lg  Vin  V 0   C   FCg     (9.16) , which share the same definitions of the coefficients as voltage-fed equations. The generalized state space equation for the normal case is: M  di 1 1  (1  h0 )  (Vin   hi vi )   L L  h0  Vin  K sw kw  dt i 1   dvi v Ci  hi  iL  i R  dt (i  1, 2..M , h  h1  h2 , where h1 is the switching function for i i i i  upper switch, and h 2i is the switching function for lower switch)  9.4.6. Governing equations for current-fed family 330 (9.17) TABLE 9-3. VOLTAGE GAIN AND ACTIVE/PASSIVE DEVICE STRESS FOR CF-SCII Voltage Gain CF-SCII 1 Vout/Vin 1  nD0 1  D0 CF-SCII 2 1  nD0 1  D0 CF-SCII 3 n(1  D0 )  1 (n  1)(1  D0 ) Inductor current stress IL/(Vin/2R) 1 G 1  D0 1 G 1  D0 INV switch voltage stress Vsw/Vin (D0) 1  nD0 1  D0 1  nD0 1  D0 1 n(1  D0 )  1 G ( n  1)(1  D0 ) (n  1)(1  D0 ) CF-SCII 4 1  n(1  D0 ) (1  n)(1  D0 ) 1 G (1  n)(1  D0 ) 1  n(1  D0 ) (1  n)(1  D0 ) CF-SCII 5 n(1  D0 )  D0 n(1  D0 ) 1 G ( n  1)(1  D0 ) n(1  D0 )  D0 n(1  D0 ) CF-SCII 6 n(1  D0 )  D0 n(1  D0 ) 1 n(1  D0 )  D0 G (1  n)(1  D0 ) n(1  D0 ) Inverter switch Front switch stress current stress Isw/(Vin/2R) Vs/Vin Is/（Vin/2R) CF-SCII 1 1 G 1  D0 1 1  D0 1 n G 1  D0 CF-SCII 2 1 G 1  D0 1 1  D0 CF-SCII 3 1 G 1  D0 1 1  D0 CF-SCII 4 1 G 1  D0 1 1  D0 1 n G 1  D0 1 1 G (1  n) (1  D0 ) 1 1 G (1  n) (1  D0 ) 9.4.7. Simulation Results demonstration Take voltage-fed SCII 2 as an example. Figure 9.14 - Figure 9.15 shows the simulation results for voltage-fed switched-coupled-inductor inverter 2, at m=0.6, n=2. Figure 9.16 Figure 9.17 shows the simulation results for voltage-fed switched-coupled-inductor inverter 5, at m=0.75, n=0.5. The input voltage is fixed at 100V. From Figure 9.14, it can be seen that 331 the voltage has been boosted by 3 times. The dc link voltage is around 4.5 times of the input voltage, which Figure 9.14 Simulation results for voltage-fed switched-coupled-inductor inverter 2 at M=0.6, n=2 (from the first to last: input voltage, dc link voltage before inverter bridge, input capacitor voltage, output line to line voltage) is equal to the active switch voltage stress. Figure 9.15 demonstrates that both inductor current are discontinuous. However, the total ampere-turns keep the same. So the unit inductor current has been taken as the state 332 Figure 9.15 Input inductor L1 and L2 current (from first to last, input inductor 1 current, input inductor 2 current) Figure 9.16. Simulation results for voltage-fed switched-coupled-inductor inverter 5 at M=0.75, n=0.5 333 Figure 9.17. Input inductors L1 and L2 current variables in the equation. In Figure 9.16, the voltage has been boosted by 2.75 times in voltage-fed topology 5, at the control parameters set. In Figure 9.17, both inductors current are positive, but discontinuous still. These results have been measured accurately, to compare with the governing equations in Table 9-2 and Table 9-3. They match with each other very well, which verify the correctness of the previous analytical equations and theory analysis. 9.4.8. Conclusion for switched-coupled-inductor inverter This section proposed a new family of buck-boost inverter topologies: voltage/current-fed switched-coupled-inductor inverter (SCII). The following features have been demonstrated by circuit fundamentals analysis and simulations: (1) At the correct selection of trans-ratio n and extra switching state duty cycle, both voltage/current-fed topologies have candidates that can buck-boost voltage. (1) Voltage-fed SCII has only half number of passive components compared to Z-source inverter, but higher voltage boost ratio and lower active switch voltage stress. 334 (2) Voltage-fed SCII has less active switch, smaller size and higher reliability than two stage boost-converter-inverter. (3) Current-fed SCII is a capacitor-less solution, which is much more compact than the ones with capacitors (boost-converter-inverter and Z-source inverter) (4) Current-fed SCII has lower active switch current stress than current-fed Z/quasi-Z-source inverter at the same voltage gain, in buck motoring and regeneration mode. (5) With active front switch, both voltage and current-fed SCII can have regenerative capability. Due to the benefits, this voltage-fed switched-coupled-inductor inverter is beneficial to be used in the dc-ac applications that demand a high voltage gain from a very low voltage dc source, such as the micro-inverter in photovoltaic, or G/M in HEV. The current-fed switched-coupled-inductor inverter is potential candidate for compact, regenerative, high temperature, high efficiency, low cost HEV/EV motor drive or engine starter. 9.5. Summary This chapter analyzes the state space model for three circuits: current-fed quasi-Z-source inverter (CF-qZSI), current-fed Z-source rectifier (CF-ZSR), switched-coupled-inductor inverter family (SCII). The transient performance of CF-qZSI has been analyzed according to the state space model and also has been demonstrated by the simulation and experiments. A dq state space model has been built for CF-ZSR, from which a linearized transfer function for the rectifier is derived, in order to guide the control loop design. For SCII, a generalized state space model based on the connection matrix has been built for all the topologies of voltage-fed or current-fed family, in order to derive all the governing equations including 335 voltage/current gain and device/passive voltage/current stress equations. This chapter could be extended to closed-loop control for each topology in the future work. 336 CHAPTER 10 CONCLUSIONS AND RECOMMENDATIONS 10.1. Contributions This work has the following contributions:  A new family of switched-coupled-inductor inverters has been proposed in this work, with voltage buck-boost function. The voltage-fed switched-coupled-inductor inverter has higher boost ratio and lower active device voltage stress than Z-source inverter at the same voltage gain, and has wider voltage buck/boost range than conventional boost-converter inverter. The current-fed switched-coupled-inductor inverter is a capacitor-less solution among the buck-boost inverters, which reduces the system size significantly. Compared to traditional boost-converter-inverter, it has less switch count, and less active device current stress. The features of the circuit are verified with simulation results.  A zero vector placement technique in SVPWM has been proposed for current-fed quasi-Z-source inverter for HEV motor drive application, to obtain lowest switching loss, lowest current ripple, lowest output harmonics and lowest voltage spike on the device in both constant torque and constant power operation regions, in order to achieve higher efficiency, higher power density and lower cost. A 24kW current-fed quasi-Z-source inverter has been built in the lab and controlled by this technique. The full power rating efficiency reaches 97.6%, and peak efficiency reaches 98.2%, both of which have a 3%-4% improvement on traditional two stage configuration. The power density is 15.3KW/L, which is also 5KW/L higher than the commercial unit in HEV.  A Space-Vector-Pulse-Width-Amplitude Modulation (SVPWAM) method has been proposed for buck-boost current source inverter. By using this method, the switching loss is 337 reduced by 60%, and the power density is increased by a factor of 2 to 3, with a less output harmonic distortion than normal SVPWM method. A 1 kW boost-converter-inverter prototype has been built and tested using this method. The overall system efficiency at full power rating reaches 96.7% and the whole system power density reaches 2.3 kW/L and 0.5 kW/lb, all of which are remarkable at this power rating. As a result, the proposed SVPWAM can make the buck-boost inverter suitable for applications that require high efficiency, high power density, high temperature, and low cost, such as EV motor drive or engine starter/alternator.  Four control methods including simple maximum boost, maximum boost, maximum constant boost control and hybrid minimum stress control have been proposed for the newly proposed direct Z-source matrix converter, and verified with simulation/experiments.  Two new discontinuous operation modes have been proposed for current-fed quasi-Z-source inverter topology. The characteristics of the discontinuous operation modes have been analyzed and the critical conditions under different control have been derived. Simulation and experiment results are given to verify the theoretical analysis.  A transient state-space model has been built for current-fed quasi-Z-source inverter to demonstrate its fast transient response in motoring and regenerating transition. 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