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Michigan State
University

 

This is to certify that the
dissertation entitled

HIGH POWER DC-DC CONVERTER AND DISTRIBUTED
Z-SOURCE NETWORK DC—DC CONVERTER

Doctoral

 

presented by

Honnyong Cha

has been accepted towards fulfillment
of the requirements for the

degree in Electrical EngineerinL

 

 

TQMVZ-e—

 

 

Ma'jor Professor’s Signature

379 c. I51 200?

Date

MSU is an Affinnative Action/Equal Opportunity Employer

 

 

PLACE IN RETURN BOX to remove this checkout from your record.
TO AVOID FINES return on or before date due.
MAY BE RECALLED with earlier due date if requested.

 

DATE DUE DATE DUE DATE DUE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5/08 K:IProj/Acc&PrelelRC/Datoouo.Indd

 

 

 

HIGH POWER DC-DC CONVERTER
AND DISTRIBUTED Z-SOURCE
NETWORK DC-DC CONVERTER

By

Honnyong Cha

A DISSERTATION
Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of
DOCTOR OF PHILOSOPHY

Electrical Engineering

2009

 

 

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Part of t}

ABSTRACT

HIGH POWER DC-DC CONVERTER AND DISTRIBUTED Z-SOURCE NETWORK
DC-DC CONVERTER

By
Honnyong Cha

Dc-dc converters are extensively used for various applications in industry to regulate
output voltage when the input voltage of converter or output load changes. However, a lot
of research activities are focused mainly on small or medium power converters, for
example, less than 5 kW. High power dc-dc converters are now in great demand in many
applications such as renewable energy interface systems, utility power electronics,
electric vehicle system, and so on.

There are several challenging issues in designing high power and high frequency
transformer isolated dc-dc converters. First, selection of the switching devices and soft
switching techniques are essential to achieve high converter efficiency. Secondly, a high
power and high frequency transformer design is becoming more and more important as
power level of the power electronics systems increases. Thirdly, snubber or voltage
clamping circuit that prevent switching devices from high voltage overshoot is also
important.

In the second part of this dissertation, a 3 phase interleaved boost dc-dc converter for
series hybrid electric bus system is introduced. The converter is designed to meet both 30
kW average and 120 kW peak power demand of bus. Therefore, the dc-dc converter in
the HEV system plays an important role to maximize fuel efficiency. However, dominant
part of the boost converter, both in terms of size and cost, belongs to the magnetic

components. Consequently, better use of the magnetic content of the dc-dc converter may

 

COMET:

SOUICC

 

transfon
distnbu:

between

MOR‘OVQ

lead to substantial performance and cost improvements. In this section, a boost inductor
using integrated magnetic approach is used to minimize inductor volume and power loss.
In order to overcome theoretical barriers of the traditional V-source or I-source
converters, a novel dc-dc converter incorporating a distributed (or transmission line) Z-
source network to achieve the buck (step-down) and boost (step-up) function of a
transformer isolated dc-dc converter is presented in the third section. In this section, a
distributed Z-source network composed of an array of inductors and capacitors is coupled
between the power source and main switching devices. The great and unique feature
about the distributed Z-source network dc-dc converter is that unlike the traditional V-
source or I-source converters, it can be open- and short-circuited without damaging
switching devices. Therefore, the desired buck and boost function can be achieved.

Moreover, converter reliability can be greatly improved.

Dedicated to:

my grandmother, Woesung Kim

my parents, Sanghwa Cha and Deokin Bae

and my beloved family, J uhee Park, Yeonwoo Cha, Arin Cha

iv

ACKNOWLEDGEMENTS

With my heartfelt gratitude, I would like to thank my advisor, Dr. Fang Z. Peng for
his guidance, encouragement and continuous support throughout my studies here.
Without his guidance, I could not have finished this work. I am also very grateful to my
committee members, Dr. Schlueter, Dr. Strangas, and Dr. Jongeun Choi for their valuable
suggestions and help.

It has been a great pleasure to work with so many talented, creative and helpful
colleagues of the Power Electronics and Motor Drive Laboratory (PEMD) at Michigan
State University. Especially, I would like to express my special thanks to Mr. Qingsong
Tang, Dr. Miaosen Shen, and Dr. Lihua Chen for their assistance in the development and
testing of 260 kVA Auxiliary power supply, Mr. Bongki Yoo of Changsung corporation
for his support for supplying magnetic cores for the distributed Z-source network DC-DC
converter.

Many thanks are also extended to my colleagues in PEMD Lab. for their delightful
discussion and friendship, Dr. Yi Huang, Ms. Wei Qian, Mr. Craig Rogers, Mr. Uthane
Supatti, Mr. Irvine Balaguer, Mr. Dong Cao, Mr. Joel Anderson, Ms. Xi Lu, Ms. Qin Lei,
Mr. Sangrnin Han, Mr Shuai Jiang.

In addition to that, I would like to express my another special thanks to Dr.
Dongwook Yoo of Korea Electrotechnology Research Institute (KERI) for his
encouragement and guidance during my stay here.

Finally and most importantly, I would like to thank my wife, my daughters and my
parents for their sacrifice, support and unconditional care. Without their years of

encouragement and continuous support, I would not have reached this point.

TABLE OF CONTENTS

LIST OF TABLES ....................................................................................................... viii
LIST OF FIGURES ....................................................................................................... ix
Chapter 1. Introduction ....................................................................................................... 1
1.1. Motivations and Objectives of Research ................................................................. 1
1.2. Scope of the dissertation .......................................................................................... 4
Chapter 2. Design and Development of 210 kW DC-DC Converter for Auxiliary Power
Supply for Metro Vehicle ................................................................................................... 6
2.1. System Topology and Ratings ................................................................................. 6
2.2. Design of Isolated Full—Bridge DC-DC Converter .................................................. 8
2.2.1 Energy Recovery Passive Snubber Circuit ......................................................... 8
2.2.2 Selection of P888 and ERCC Parameters ........................................................ 13
2.2.3 Operational modes ............................................................................................ 14
2.2.4 Selection of PWM Control Method .................................................................. 16
2.3. Experimental Results ............................................................................................. 19
2.4. Conclusion ............................................................................................................. 21
Chapter 3. High Power Transformer and Inductor Design ............................................... 22
3.1. Losses in Magnetics ............................................................................................... 22
3.2. Transformer design ................................................................................................ 23
3.2.1 Core loss ........................................................................................................... 23
3.2.2 Winding (Copper) loss ...................................................................................... 26
3.3. Inductor design ...................................................................................................... 38
3.3.1 Inductance Calculation by Permeability vs. DC Bias Curves .......................... 39
3.3.2 Core loss ........................................................................................................... 41
3.3.3 Winding loss ..................................................................................................... 42
3.4. Conclusion ............................................................................................................. 43
Chapter 4. Voltage Oscillation Problem in Secondary Rectifier Diode ........................... 45
4.1 . Introduction ............................................................................................................ 45
4.2. Review of Previously Proposed ERCC ................................................................. 48
4.3. Proposed ERCC ..................................................................................................... 53
4.3.1 Principle Operation of Proposed ERCC ........................................................... 53
4.3.2 Simulation and Experimental Results ............................................................... 62
4.4. Conclusion ............................................................................................................. 71
Chapter 5. Power Loss Breakdown and Overall System Test .......................................... 72
5.1. Power loss breakdown ........................................................................................... 73
5.2. Overall system test ................................................................................................. 76
5.3. Conclusion ............................................................................................................. 79

Chapter 6. Integrated Magnetics for Interleaved Boost DC-DC Converter for Series
Hybrid Electric Bus ........................................................................................................... 80

vi

 

 

7.4. l'

 

6.1. Introduction ............................................................................................................ 80

6.2. Interleaved Boost Converter and Integrated Magnetics ........................................ 83
6.2.1 Review of Interleaved Boost Converter. .......................................................... 83
6.2.2 Integrated Magnetics ........................................................................................ 87

6.3. Design of High Efficient and High Density Integrated Magnetics ........................ 91

6.4. Experimental Results ........................................................................................... 101

6.5. Conclusion ........................................................................................................... 107

Chapter 7. Distributed Z-Source Network DC-DC Converter ........................................ 108

7.1. Introduction .......................................................................................................... 108

7.2. Why buck-boost converter? ................................................................................. 1 11

7.3. Literature Survey for Buck-Boost Converters ..................................................... 114
7.3.1 Non-Isolated Buck-Boost Topologies ............................................................ 114
7.3.2 Transformer Isolated Buck-boost Topologies ................................................ 117

7.4. The Z-Source Concept and Distributed Z-Source Network ................................ 126

7.5. Transmission Line Based Z-Source Network-Distributed Z-Source Network.... 128

7.6. Conclusion ........................................................................................................... 133

Chapter 8. Principle Operation of Distributed Z-Source Network DC-DC Converter... 135

8.1. Input Impedance of Distributed Z-Source Network ............................................ 135

8.2. Voltage and Current distribution along DZSN .................................................... 141

8.3. Output Voltage Control of the Proposed DZSN DC-DC Converter ................... 143
8.3.1 Buck mode (V in>Vo) ..................................................................................... 144
8.3.2 Boost mode (V in<Vo) .................................................................................... 148

8.4. Derivation of Voltage Gain .................................................................................. 152
8.4.1 Buck mode ...................................................................................................... 152
8.4.2 Boost mode ..................................................................................................... 154

8.5. Simulation and Experimental Results of the Proposed DZSN DC-DC Converter.

.................................................................................................................................... 157

8.6. Conclusion ........................................................................................................... 163

Chapter 9. Contributions and Future Works ................................................................... 164

9.]. Contributions ....................................................................................................... 164

9.2. Recommendations for future works ..................................................................... 165

Bibliography ............................................................................................................... 166

vii

Table
Table
Table
Table -
Table .
Table '
Table *
Table r
Table 6
Table 6
Table 6
Table 8.

Table 8.
COT“: en:

 

LIST OF TABLES

Table 2-1 Comparison of Power Loss ............................................................................. 19
Table 3-1 Current Waveform and Electrical Parameter of Copper Foil. ......................... 31
Table 3-2 Coupled inductor design parameters. .............................................................. 39
Table 4-1 Operational Conditions and Circuit Parameters of dc-dc Converter ............... 63
Table 5-1 Power loss breakdown in 70 kW dc-dc converter ........................................... 75
Table 6-1 Electrical Specifications of battery and boost dc-dc converter. ...................... 81
Table 6-2 Calculation of f (D) for N=2, 3 and 4 ............................................................ 84
Table 6-3 Basic Material Characteristics ......................................................................... 93
Table 6-4 Parameters of IM core ..................................................................................... 97
Table 6-5 Measured inductances of flat IM at 40 A ..... _ .................................................. 99
Table 6-6 Calculation of power losses in 1M ................................................................. 106
Table 8-1 Electrical specifications of DZSN. ................................................................ 139

Table 8-2 Test conditions and electrical specifications of proposed DZSN dc-dc
converter. ........................................................................................................................ 158

viii

 

 

 

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Figure 2

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Figure 3-

LIST OF FIGURES

Figure 1-1 A V-source FB PWM DC-DC converter. ........................................................ 3
Figure 1-2 An I-source F B PWM DC-DC converter. ........................................................ 3
Figure 2-1 Overall system configuration for 260 kVA auxiliary power supply ................ 7
Figure 2-2 Common IGBT snubber circuits ...................................................................... 8
Figure 2-3 Overall schematic of 70 kW DC-DC converter ............................................. 11
Figure 24 Energy recovery circuit .................................................................................. 12
Figure 2-5 Operational modes of dc-dc converter. .......................................................... 15
Figure 2-6 Duty cycle control .......................................................................................... 18
Figure 2-7 Phase-shift PWM control ............................................................................... 18
Figure 2-8 Transformer primary current and IGBT voltage waveforms ......................... 20

Figure 2-9 Recovery current in primary snubber resistor and IGBT voltage waveform. 20
Figure 3-1 Losses in Magnetics. ....................................................................................... 22
Figure 3-2 Core loss measurement .................................................................................. 24

Figure 3-3 Transformer voltage and current waveforms with secondary side open-

circuited ............................................................................................................................. 24
Figure 34 Core loss measurement waveforms ................................................................ 25
Figure 3-5 Core loss curves for 3C90 material. ................................................................ 25
Figure 3-6 Winding arrangement and MMF waveform in transformer with single
interleaved winding ........................................................................................................... 30
Figure 3-7 Primary winding loss in single interleaved winding. ..................................... 32
Figure 3-8 Secondary winding loss in single interleaved winding. ................................. 32
Figure 3-9 Winding arrangement and MMF waveform in transformer with double
interleaved winding ........................................................................................................... 34
Figure 3-10 Primary winding loss in double interleaved winding ................................... 35
Figure 3-11 Secondary winding loss in double interleaved winding ............................... 35

ix

 

 

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Figure

Figure 3-12 Transformer winding geometry .................................................................... 37

Figure 3-13 Transformer assembled with core and housed in aluminum case ................ 37
Figure 3-14 Block core assembly .................................................................................... 38
Figure 3-15 % permeability vs H curve of Changsung megaflux block core ................ 40
Figure 3-16 Copper resistivity vs. temperature ................................................................ 42
Figure 3-17 Inductor assembly (Side view) ..................................................................... 44
Figure 3-18 Inductor assembly (Top view) ..................................................................... 44
Figure 4—1 Voltage oscillation problem in secondary rectifier diode .............................. 45
Figure 4-2 RCD clamped circuit ...................................................................................... 46
Figure 4-3 Active clamp circuit ....................................................................................... 47
Figure 4-4 Voltage oscillation reduction circuit using Cb .............................................. 47
Figure 4-5 Energy recovery clamp circuit. ...................................................................... 48
Figure 4—6 ERCC modified from Figure 4-5 (ERCC #1) ................................................ 49
Figure 4-7 Diode voltage (Vrec) waveform of ERCC #1. ............................................... 49
Figure 4—8 Vrec_pk vs duty cycle (D) of ERCC #1 ......................................................... 50
Figure 4-9 ERCC modified from the circuit in [29] ........................................................ 52
Figure 4-10 Proposed ERCC. .......................................................................................... 54
Figure 4-11 Key waveforms of proposed ERCC. ............................................................ 54
Figure 4-12 Operational modes of proposed ERCC ........................................................ 55
Figure 4-13 Comparison of Vrec_ pk as a function of D. ............................................... 62
Figure 4—14 Simulation waveforms of proposed ERCC when D=O.483 ......................... 64
Figure 4-15 Simulation waveforms of proposed ERCC when D=0.8 ............................. 64
Figure 4-16 Experimental waveforms measured without calmp circuit .......................... 65
Figure 4-17 Experimental waveforms measured with proposed ERCC .......................... 65

 

 

 

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Figure 4-18 Experimental waveforms with proposed ERCC when D=O.483 ................. 66

Figure 4-19 Zoom-in waveforms of Figure 4-18 ............................................................. 66
Figure 4-20 Experimental waveforms using proposed ERCC when D=0.8 .................... 67
Figure 4-21 Zoom-in waveforms of Figure 4-20 ............................................................. 67
Figure 4-22 Experimental waveforms of ERCC #1 ......................................................... 69
Figure 4—23 Proposed ERCC ........................................................................................... 69
Figure 4-24 Measured and theoretical results of Vrec_ pk vs. C31. ................................. 70
Figure 4-25 Measured efficiency at 50 kW output power. .............................................. 70
Figure 5-1 3-D design of 70 kW dc-dc converter ............................................................ 72
Figure 5-2 Photo of 70 kW dc-dc converter .................................................................... 72
Figure 5-3 Loss breakdown of 70 kW dc-dc converter. .................................................. 76
Figure 54 Overall system configuration of 210 kW aux. power supply ......................... 77
Figure 5-5 210 kW system test ........................................................................................ 77
Figure 5-6 Power meter measurement of overall system test .......................................... 78
Figure 5-7 Transformer primary current of three DC-DC converter module. ................. 78
Figure 6-1 Overall system configuration of series hybrid electric bus ............................ 80
Figure 6-2 A 3-Phase interleaved boost converter ........................................................... 82
Figure 6-3 Normalized input current ripple of IBC ......................................................... 85
Figure 6-4 Inductor current interleaving when 0 < D <1/3 .............................................. 85
Figure 6-5 Inductor current interleaving when 1/3 < D <2/3. ......................................... 86
Figure 6-6 Inductor current interleaving when 2/3 < D <1 .............................................. 86
Figure 6-7 Core structure of 3 phase IM .......................................................................... 87
Figure 6-8 IM assembled with winding ........................................................................... 87
Figure 6-9 Reluctance model of 1M ................................................................................. 88
Figure 6-10 Normalized current ripple as a function of D for several values of k. ......... 91

xi

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Figure 6-11 Proposed flat IM. (Front view) ..................................................................... 95
Figure 6-12 Proposed flat IM. (Side view) ...................................................................... 95
Figure 6-13 % permeability vs. H curve of Changsung 40p block core ......................... 96

Figure 6-14 Modified reluctance model when a voltage is applied to only outer leg 2. . 98

Figure 6-15 Inductance measurement of 1M .................................................................... 99
Figure 6-16 Experimental waveforms of IBC using IM when D=0.5. .......................... 102
Figure 6-17 Experimental waveforms of IBC using 1M when D=2/3. .......................... 102
Figure 6-18 Inductor current and IGBT switching waveforms at 120 kW. ................... 104
Figure 6-19 Input current and IGBT switching waveforms at 120 kW. ........................ 104
Figure 6-20. Photo of prototype IM before molding. ..................................................... 105
Figure 6-21 Photo of molded IM after molding ............................................................. 105
Figure 6-22 Temperature increase of IM ....................................................................... 106
Figure 7-1 V-source FB PWM DC/DC converter. ........................................................ 109
Figure 7-2 I—source FB PWM DC/DC converter. .......................................................... 109
Figure 7-3 The effect of EMI or misgating on switching device ................................... 110
Figure 74 Buck converter ............................................................................................. 111
Figure 7-5 Boost converter ............................................................................................ 111

Figure 7-6 Input and output voltage range of buck, boost and buck-boost converter 112

Figure 7-7 Efficiency profile of buck, boost and buck-boost converter ........................ 112
Figure 7—8 Buck and boost two stage converter ............................................................. 114
Figure 7-9 Buck-boost converter ................................................................................... 115
Figure 7-10 Cuk converter ............................................................................................. 116
Figure 7-11 SEPIC converter ......................................................................................... 117
Figure 7-12 Flyback converter ....................................................................................... 118
Figure 7-13 Transformer model of flyback converter ................................................... 118

xii

 

 

 

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Figure 7-14 Isolated Cuk converter ............................................................................... 119
Figure 7-15 Back-to—back bi-directional converter ........................................................ 120
Figure 7-16 LLC series resonant dc-dc converter .......................................................... 121
Figure 7-17 Voltage gain of LLC series resonant converter .......................................... 121
Figure 7-18 Z-source dc-dc converter ............................................................................ 122
Figure 7-19 qZ-Source dc-dc converter. ........................................................................ 123
Figure 7-20 Key waveforms in buck mode .................................................................... 124
Figure 7-21 Key waveforms in boost mode ................................................................... 125
Figure 7-22 Voltage gain of Z(qZ)-Source dc-dc converter. ......................................... 126
Figure 7-23 A general topology of the Z-source converter. .......................................... 127
Figure 7-24 A general topology of the distributed Z-source converter [46] .................. 128
Figure 7-25 A basic structure of DZSN or transmission line network. ......................... 129
Figure 7-26 Electrical representation of DZSN. ............................................................ 129
Figure 7-27 Common-mode connected DZSN. ............................................................. 130
Figure 7-28 Differential-mode connected DZSN. ......................................................... 130
Figure 7-29 Photos of DZSN implemented (Top view) ................................................ 132
Figure 7-30 Photos of DZSN implemented (front view) ............................................... 132
Figure 7-31 Proposed DZSN dc-dc converter. .............................................................. 133
Figure 81 Input impedance measurement ..................................................................... 135
Figure 8-2 Simulation results of Z," with Z L = 0. ....................................................... 139
Figure 8-3 Zin measurement of DZSN with Z L = 0 (Magnitude) ............................... 140
Figure 8-4 Zm measurement of DZSN with Z L = 0 (Phase) ....................................... 140

Figure 8-5 Voltage and current distribution along DZSN when fax = fl , Quarter wave-

length condition (I = i1.) ................................................................................................. 142

xiii

 

 

 

 

 

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Figure 8-6 Voltage and current distribution along DZSN when fex = 2 f1 . Half wave-

length condition (I = g) ................................................................................................. 143
Figure 8-7 DZSN dc-dc converter. ................................................................................ 144
Figure 8-8 Operation point at buck mode (point “A”) ................................................... 145
Figure 8-9 Key waveforms of the proposed dc-dc converter at buck mode .................. 146
Figure 8-10 Voltage overshoot in Vpn at buck mode .................................................... 148
Figure 8-11 Operation point at boost bode (between point “A” and point “B”) ........... 149
Figure 8-12 Key waveforms of the proposed dc-dc converter at boost mode ............... 151
Figure 8-13 Waveforms at buck mode ........................................................................... 152
Figure 8-14 Waveforms at boost mode .......................................................................... 154
Figure 8-15 Relationship between fsw and D ............................................................. 156
Figure 8-16 Voltage gain of the DZSN dc-dc converter ................................................ 157
Figure 8-17 Simulation waveforms at buck mode (V in>Vo). ....................................... 159
Figure 8-18 Experimental waveforms at buck mode(Vin>Vo). .................................... 159
Figure 8-19 Simulation waveforms at boost mode (V in<Vo). ...................................... 160
Figure 8-20 Experimental waveforms at boost mode (V in<Vo). .................................. 160
Figure 8-21 Simulation waveforms at normal mode (Vin=Vo). ................................... 161
Figure 8—22 Experimental waveforms at normal mode (Vin=Vo). ............................... 161
Figure 8—23. Efficiency of proposed converter vs. input voltage. .................................. 162
xiv

Chapter 1. Introduction

1.1. Motivations and Objectives of Research

Dc-dc converters are extensively used for various applications in industry to regulate
output voltage when input voltage of the converter or the output load changes. However,
a lot of research activities are focused mainly on small or medium power converters, for
example, less than 5 kW. High power dc-dc converters are now in great demand in many
applications such as renewable energy interface systems, utility power electronics,
electric vehicle system, and so on.

There are several design issues and challenges for high power and high efficiency dc-
dc converters. In this dissertation, we focus on three major issues in high power
transformer isolated dc-dc converters especially for V-source type transformer isolated
dc-dc converters. The same problems in V-source converter exist in I-source type
converters as well.

First, an energy recovery passive snubber circuit is introduced to reduce voltage
spike and power loss in switching devices. With the energy recovery circuit, a
considerable amount of energy which is otherwise dissipated in conventional RCD
snubber circuits can be recovered back to the DC link and thus increases system
efficiency. Duty cycle and phase-shifted pulse width modulation (PWM) control methods
are compared in terms of power loss in switching devices and transformer.

Secondly, high frequency and high power transformers are not very common in
present day power supplies. A considerable effort has been directed towards high

frequency transformers in the low power range. For a transformer with a power rating

 

 

 

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dissertal‘.
interleai
findings
ruuflur

Thin
discusses
winge.e
the rectif.
bu and
chmamen

Anot
about ma:

aCl’llEVlng

fretilier d

than that

SYStem is \

 

In ad

Indiana}

 

around 100 kW, the core selection and structure design are quite challenging. In this
dissertation, the high frequency and high power transformer is designed using an
interleaved winding method in order to reduce the proximity effect in transformer
windings. An optimum copper (layer) thickness is found to minimize winding loss and
transformer size.

Thirdly, diode voltage oscillation problem in the secondary rectifier diode is
discussed and solutions are provided. For a PWM converter with a wide range of input
voltage, especially when duty cycle of the converter is less than 0.5, voltage stress across
the rectifier diodes could be very high. The use of higher voltage diodes increases power
loss and voltage overshoot because higher voltage diodes have poor recovery
characteristics.

Another important part for high power and high frequency dc-dc converter design is
about magnetics such as transformers and inductors. The magnetics design is essential for
achieving high efficiency and high density power converter design. Generally, the power
loss in transformer and inductor in dc—dc converter is smaller than that of IGBT and
rectifier diode. However, their thermal resistance from inside to outside is much greater
than that of IGBT and rectifier diodes. The high thermal resistance causes heat
accumulation inside transformer and inductor. As a result, it will leads to thermal
runaway and finally system failure. Thus, magnetic design in high power converter
system is very important and should not be overlooked

In addition to the above mentioned problems/issues, there is conceptual and
theoretical barriers in traditional transformer isolated dc-dc power conversion circuits.

Traditional transformer isolated dc-dc power conversion circuits are based on either a

voltage-source (V -source) or current-source (I-source) structure [1]. A V-source
converter is fed from a power source with relatively constant voltage that is generally
supported with capacitors. Figure 1—1 shows a V-source type full bridge (F B) pulse width
modulation (PWM) dc-dc converter. Likewise, an I-source converter is fed from a power
source with relatively constant current that is generally smoothed through inductors.

Figure 1-2 shows the I-source type FB PWM dc-dc converter.

} ‘J le

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S1 52
Vin 919 RL

S311 1941' ZISD3 D 4

2. «a «1

Figure 1-1 A V-source FB PWM DC-DC converter.
Lin
3,} 52) L”, N1 :N2 2EDi 21SDz
b
o o b

Vm Caz-'1' gRL

 

 

 

 

 

 

 

 

 

5ij 54 1| 2st 1‘04
H or r;

Figure 1-2 An I-source F B PWM DC-DC converter.

 

 

 

 

 

 

Bot
good p6
will be e

In 0
in Figun

proposed

1.2. So

Baset
converters
€lFlCl€TlC_V

Chap:

switching

 

Chapt
are made 1
gll'es min”
Chaprt
Classical Sr
A new and

with Cllfisi;

 

Chaplet

 

Both structures have been used in many industry applications and have shown quite
good performances. However, both converters have some conceptual limitations which
will be explained later in this dissertation.

In order to overcome the limitations of the conventional bridge type converter shown
in Figure 1-1 and Figure 1-2, a novel distributed Z-source network dc-dc converter is

proposed in this dissertation

1.2. Scope of the dissertation

Based on the aforementioned problems in conventional V-source or I-source dc-dc
converters, this dissertation is focused on the following subjects to increase converter
efficiency, reliability, and power density.

Chapter 2 discusses the dc-dc converter using an energy recovery passive soft
switching snubber circuit for a 210 kW auxiliary power supply for a metro vehicle.

Chapter 3 describes the 70 kW high power transformer and inductor design. Efforts
are made to reduce copper loss in transformer windings. Optimum copper thickness that
gives minimum copper loss is found.

Chapter 4 describes voltage oscillation problem in the secondary rectifier diodes.
Classical snubber and energy recovery circuits are reviewed and problems are addressed.
A new energy recovery clamp circuit is developed and its performances are compared
with classical ones.

Chapter 5 analyzes power losses of the 70 kW dc-dc converter developed in this

work and its losses are summarized.

 

Ch;
interleai
presente.

Cha;
are exarr.

Char
The oper
the grape

C hay

 

 

Chapter 6 shows design and development of the integrated magnetics for a 3 phase
interleaved boost converter for SHEB system. A very detailed design guideline is
presented and the analytical results are compared with experimental results.

Chapter 7 proposes a distributed Z-source network. Its properties and characteristics
are examined in great detail.

Chapter 8 presents novel dc-dc converter utilizing the distributed Z-source network.
The operational principle of the proposed dc—dc converter is analyzed. Performances of
the proposed dc-dc converter are verified experimentally.

Chapter 9 discusses future works that need to be done.

 

 

Cha
210 ‘*

Pow

2.1. $3

The

vehicles. l

 

stages. In
features T
transfonne
noise. F igi

for metro \

 

 

 

The el
(mono;
inverted in
various ele

heating, an.

Chapter 2. Design and Development of
210 kW DC-DC Converter for Auxiliary
Power Supply for Metro Vehicle

2.1. System Topology and Ratings

The energy supplied to the low-voltage equipment in systems, such as metro
vehicles, powered by a high dc voltage, typically goes through multiple power conversion
stages. In general, the dc-dc-ac structure with a high frequency isolation transformer
features many advantages over the traditional dc-ac structures with a 50/60 Hz
transformer. The major advantages include lower cost, smaller size and less acoustic
noise. Figure 2-1 shows the overall system configuration for an auxiliary power supply
for metro vehicle.

The electric power is transmitted to a train from a high dc voltage overhead line
(1000-2000 V) and is converted into intermediate dc voltage (750 V) which is then
inverted into a 3-phase ac voltage (e.g. 380V, 60Hz). The ac voltage supplies power to
various electrical loads in the train such as an air conditioner, air compressor, lighting,
heating, and etc.

The dc-dc converter is the key part of the whole dc-dc-ac system. In this dissertation,
the isolated dc-dc converter is divided into three modules as shown in Figure 2-1 in order
to use standard 1200 V IGBTs because IGBTs rated over 1200 V usually have very high
switching losses at switching frequencies higher than 10 kHz [2]. Therefore, each dc-dc

converter module carries 70 kW power for a combined 210 kW output power rating.

 

 

 

The
input vol
current. I
voltage is
three dc-c.

3.4and5

1000..
2000' mi

Flgllre

A5 SliOvt
lll' modules
the commic
0r I~50urce ty

B Selected

 

The primary sides of the dc-dc converters are connected in series to achieve high
input voltage and the secondary sides are connected in parallel to generate high output
current. Thus, each dc-dc converter accepts an input voltage of 333-666 Vdc, the output
voltage is regulated to 750 Vdc with maximum current of 93 A. The design of one of the

three dc-dc converter modules will be addressed in great detail in this chapter and chapter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3, 4 and 5
8.1
Q)
J a r is.
70 kW DC/DC Module 1
1000~ » ‘5
.— 750 Vdc DC/ AC 3'
2000 Vdc B Inverter g
E ;: J +:: ;: + '—O Q)
" '8
w— filter —0fi
70 kW DC/DC Module 2 M
T is
J a e
70 kW DC/DC Module 3

 

 

 

Figure 2-1 Overall system configuration for 260 kVA auxiliary power supply.

As shown in Figure 2-1, the 210 kW isolated dc-dc converter is divided into three 70
kW modules in order to use standard 1200 V IGBTs. As already mentioned in Chapter 1,
the conventional transformer isolated dc-dc converter consists of either a V-source type
or I-source type converter. In this work, a voltage source type FB PWM dc-dc converter

is selected.

 

2.2. Di

2.2.1

High
oscillatio:
inductant‘
spike pre.

interferer.

III OTt'

 

pa'Oposed.

in Figure

 

 

FiguI-e 1

l0
Elonad'

 

2.2. Design of Isolated Full-Bridge DC-DC Converter
2.2.1 Energy Recovery Passive Snubber Circuit

High power and high fiequency switching power converters experience high voltage
oscillation/spike problems across the switching devices due to the inherent circuit stray

inductances (Lsmy) associated with the physical circuit layout [2, 3]. The high voltage

spike presents significant stresses to the switch, increases loss and electromagnetic
interference (EMT) problems.
In order to reduce voltage spike in the switching devices, several methods have been

proposed. The conventional method is the use of an RCD clamp/snubber circuit as shown

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

in Figure 2-2 [2].
[astray Lstray Lstray
13‘6“ it??? "51‘?“
Cs a:
JK J DJK
SE RS SZDS SE £7)
3
D
Vm E CS it ‘t— Vin :2: Vin 9;;
«a
"6’5“ "3%“ ‘ u" u“ ‘
(a) (b) (C)

Figure 2-2 Common IGBT snubber circuits

Figure 2-2 (a) consists of a single low inductance film capacitor connected from C1

to E2 on a dual IGBT module or from P to N on a six pack IGBT module. In low power

designs, this snubber will often provide effective, low cost control of transient voltage.
As power level increases, snubber circuit (a) may begin to ring with parasitic bus

inductance, Lstmy unless Lyra},

is not minimized. Snubber circuit (b) solves this problem
by using a fast recovery diode to catch the transient voltage and block oscillations. As

power rating of the system increases, however, dual IGBT modules or six pack modules

may not be able to be used due to the IGBTs available in the market. In this case, Lmay

between the top and bottom IGBT of a phase would be bigger than that of dual IGBT
module or six pack modules because of physical layout. Therefore, the parasitic loop
inductance of snubber (b) may become too high for it to effectively control transient
voltage. In these high current applications, snubber circuit (c) is usually used. This
snubber functions similar to snubber (b) but it has lower loop inductance than snubber (b)
because it is connected directly to the collector and emitter of each IGBT. However, the

power losses in snubber resistors, RS , would be very high as the output power increases.

As a result, it degrades system efficiency.

From the above results, it is obvious that Lmay

between DC link capacitor and
IGBT phase legs should be well minimized to reduce voltage spike in IGBT. In addition

to that, L

stray

between the top and bottom IGBT should be minimized as well to further

reduce voltage spike in IGBT. One way among others that can effectively minimize

Lstmy between the top and bottom IGBTs of a phase is to use P-cell and N-cell structured

IGBT. This IGBT structure has already been suggested by Dr. Fang Z. Peng in several
previous literatures [4-6]. Added benefit of this structure is that it can also minimize

L

may between the DC link capacitor and IGBT phase leg, significantly. Recently,

 

several :I
tell stra
Ant

switchin

 

intrinsic
topolog}
leakage
hard 5w.

this. PS

 

 

 

interval,
Therefor

So f
PWM c
freeuhe
Voltage
iflput v(
1301 app

F ig
Clevek,
Sewn d

Spike

Capac

several semiconductor manufacturers are moving to the packaging based on the P- and N-
cell structures [6].

Another conventional method is using phase-shifted PWM (PS-PWM). Soft
switching operation is possible in PS-PWM by using transformer leakage inductance and
intrinsic capacitance of switches without an additional circuitry [7, 8]. However, this
topology requires that certain minimum commutation energy be stored in transformer
leakage inductance. If this energy is insufficient, the incoming device tum-on, which is
hard switched, leads to significant turn on loss due to the capacitor dump. In addition to
this, PS-PWM suffers from large circulating current problem during freewheeling
interval, which results in increased RMS crurent in switching devices and transformer.
Therefore, it increases conduction loss in IGBT and transformer.

So far, a couple of zero-voltage and zero-current—switching (ZVZCS) full-bridge (F B)
PWM converters have been presented and their primary currents are reset during
freewheeling period using the auxiliary circuit in secondary side [9, 10]. However,
voltage overshoot in the secondary rectifier diode could be very high when the converter
input voltage varies in a wide range. Therefore, all those topologies mentioned above are
not applicable to the system discussed in this dissertation.

Figure 2-3 shows overall circuit configuration of the 70 kW dc-dc converter
developed in this work to overcome the aforementioned problems in both primary and
secondary side. A passive snubber circuit, which consists of a diode/capacitor for each
leg, and an energy recovery circuit shared by two phase legs, is used to reduce voltage

spike and power loss in the IGBT. The snubber circuit includes a diode Dsp and a

capacitor Csp for the upper switching devices (SI and 52 ), and symmetrically D5,, and

10

C3,, for the lower switching devices (S3 and S4 ). The functions of the snubber diodes

Dsp and D”, and snubber capacitors CW and C3,, are very similar to those of the

traditional RCD snubber shown in Figure 2-2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Lstray Lstray
Rp R D SI 2
D Sp ’F Sp JK} 2: JK}
rep 0,,
' ‘ C ‘=C
:# T Ti 30 SO
Vin , R
1R»
DR" i~Csn JK} :: JK
R3,, Del." S3 N S4
Energy recovery Snubber Snubber
circuit circuit circuit
A L V0
D D6
1 n n J th
L . 3":
1" -——i<r
,: D32
072303 0,2
' - JUL 5
‘ t "60‘ "
01 {51,02 (3,,
E Vrec D31 ::
13323134 Dhl
energy recovery

clamp circuit

Figure 2-3 Overall schematic of 70 kW DC-DC converter

11

 

 

TheV' 3T ;

the mid

 

voltages
guarante

capacitor

and DR”
the snub?

Common

the loop I.

 

They are, however, arranged differently so that both snubber capacitors are connected to
the midpoint of the phase leg [11]. Therefore, the sum of both snubber capacitors’

voltages should remain constant and equal to the DC link voltage, which is further

guaranteed by a larger snubber capacitor C50 connected across the two snubber
capacitors.

The energy recovery circuit that is shared by all the snubber circuits has two diodes
DRp and DR", two resistors Rsp and R3,, , and a transformer TR. The two diodes, DRp
and DR" , guarantee the energy recovery current (power) flows in one direction, i.e., fiom
the snubber capacitors back to the DC link. The transformer T R is connected like a
common mode choke and thus presents a large inductance to loops I-IV as shown in

Figure 2-4. The resistors R57, and R3,, are used to further limit the circulating current in

the loop I—IV.

Loop l Loop ll

 

Loop m Loop lV

Figure 2-4 Energy recovery circuit

12

 

 

2.2.2

Pror
the dc-d.
and di 1.
a:

L

strut"
chosen a:
which co:
dc comer

The s
to calcula:
and snubb-
IGBI 0V'e:
1055 in snu
dfitfirmineg
power lOSs
Cm- The It
11] the Path
energy rE‘Co
imposes Si g

in
[Ru and

 

2.2.2 Selection of P885 and ERCC Parameters

Properly designed and selected snubber parameters are crucial to the performance of

the dc-dc converter with passive soft switching snubber (PSSS) technology. The dv/ dt

and di / dt are determined by the snubber capacitors, Csp and C

571’

stray inductance

L

may , and partially by the load current. Theoretically the capacitance C so should be

chosen as high as possible to lower the harmonics as well as the mean value of VCso ,

which contributes to limit both dv/ dt and di / dz. In the development of the 70 kW dc-

dc converter, we selected 0.47 pF for C so.
The selection of optimum snubber capacitors, Csp and C 5,, , are somewhat complex

to calculate because they are related to busbar stray inductance, IGBT voltage overshoot
and snubber diode power loss. When the snubber capacitors are big, for example, the
IGBT overshoot and IGBT tum-off switching loss will be decreased. However, the power
loss in snubber diodes will increase. Therefore, the optimum snubber capacitance can be
determined through experiment in practice by considering IGBT voltage overshoot and

power loss in the snubber diode. In this work, 30 nF capacitors are chosen for C510 and

C s". The resistors inserted in the energy recovery circuit are to reduce circulating current

in the path shown in Figure 2-4. Theoretically, these resistors are not necessary in an

energy recovery circuit because the transformer T R has an airgap in its ferrite core, which

imposes significant inductance in current loop I-IV. In this work, 8.6 Q resistors are used

for Rsp and R3,, to firrther reduce circulating current.

13

 

 

The

shown 1?.

err:
lep r

Starts dist

initial co

 

 

frequency

sun CO“

d

and Snubb

2810‘ AS a

inplll F’Olta

2.2.3 Operational modes

The operational modes of leading leg switches in the duty cycle control method are

shown in Figure 2-5. The lagging leg switch operation can be analogously explained.

Mode 1: SI and S4 are on and input power is delivered to output. During this mode,

VCSP remains at zero and Va," is equal to VCSS .
Mode 2: S1 and S4 are turned off and snubber capacitor C Sp starts charging and C 5,,

starts discharging through snubber diode Dsp. By solving differential equations with

initial conditions VCsp (0‘) = 0 , IL, (0’) = 10 and VCSS (0") 2 Vin , VCSp can be expressed

 

 

as
V- V- _ I .
VCsp (t) = j?- —[-£l— VCSp (0 )jcos(w0t) + WOOCS sm(w0t) (2.1)
. C s 1 .
In (2.1), snubber capacrtance C s = C 5,, : — and wo = rs resonant
2 2LsCs
frequency.

Mode 3: When VCSp reaches VCSS and Vcsn becomes zero, the diode D3,, and D3
start conducting. Therefore, the upper snubber capacitor voltage VCSP can be clamped to

VCSS . After this mode, there is a resonance between transformer leakage inductance (M)

and snubber capacitance until current in the transformer leakage inductance decreases to

zero. As a result, snubber capacitor voltage VCSp and VCsn is maintained at half of the

input voltage.

14

 

 

 

 

 

l
I

I'll

W,

5 .

 

 

 

 

 

 

 

 

 

it

I»

 

 

 

 

 

 

 

 

 

 

 

 

Dsn < Mode 1 > Dsn < Mode 2 >
——Trr~ ‘ 2w <

 

 

 

 

 

 

D (Mode 4>

 

 

 

 

 

 

 

v

 

 

 

 

 

 

 

 

 

 

 

 

 

 

  

 

 

 

 

 

 

 

D
S" 5) <Mode 5>

xxx
VV VV

 

 

1

 

Figure 2-5 Operational modes of dc-dc converter.

15

 

operation
again thn
As a resu'
initial cor

expressed

capacitor c

Therefore, 7
2.2.4 5.

The {Lj

 

Control 0r pl
became Iran

1) A dtt
Used to r 6d.

[hinges [Ian

I
l
l

 

_M_oje_4: S2 and S3 are turned on and S3 carries load current —10. As the same
operation in mode 2, snubber capacitor CSP starts charging and C5,, starts discharging
again through snubber diode Dsp and this causes additional current flow in switch S3.
As a result, there is an additional power loss incurred by capacitive turn on. With the

. . . _ V- _ _
initral conditions VCSp(0 )=—§l , 1L,(0 )=0 and VCSS(0 )=V,-,, , ,and, VCSP can be

expressed as
Vin
VCSP (t) = Vin — Vin -——2— cos(wot) (2.2)

Mode 5: The operation of this mode is quite similar to mode 3 except that snubber

capacitor charging and discharging current flows through S3 instead of body diode D3.

Therefore, the upper snubber capacitor voltage VCSP is clamped to VCSS again.

Mode 6: S3 carries only load current.

2.2.4 Selection of PWM Control Method

The full bridge converter shown in Figure 2-3 can be operated by a duty cycle
control or phase shift PWM (PSPWM) control. In this work, duty cycle control is chosen
because transformer leakage inductance is minimized due to the following reasons.

1) A double interleaved winding method, which is explained later in chapter 3, is
used to reduce the proximity effect in transformer winding and this winding method

reduces transformer leakage inductance by a factor of 4 [12].

16

 

 

Z) A
rectified
ratio to c
0f the SL’
snubberi
inductanc

Figur
current (.
compares
transform,
at the lead

As sh
Cllll'y Q’Cit
capitCitiV'e
device is F.

negligible

 

the [[311st

2) A large leakage inductance decreases the effective duty cycle in the secondary

rectified voltage, Vsec (see Figure 2-3), therefore, requiring a larger transformer turns

ratio to compensate for the reduced duty cycle, which eventually increases voltage stress
of the secondary rectifier diodes [13], [14]. Therefore, power loss in the secondary
snubber (or clamp) circuit will be increased. In this work, measured transformer leakage

inductance in the primary side is around 0.25 pH .
Figure 2-6 and Figure 2-7 depict the IGBT switching (Vce) and transformer primary
current (1),) waveforms for both duty cycle and PS-PWM control methods. Table 2.1

compares power loss in the IGBT and transformer based on the assumption that the
transformer leakage inductance is not sufficient to achieve zero voltage switching (ZV S)
at the leading leg switches.

As shown in Table 2-1, turn-on and tum-off losses in the IGBT are same with both
duty cycle and PS-PWM control methods. However, duty cycle control has lower
capacitive turn-on loss and conduction loss than PS-PWM because the voltage across the
device is half of the input voltage during the turn—on and tum-off transitions. It also has
negligible circulating current during free-wheeling period because leakage inductance of

the transformer is very small.

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

s1 &s4
32 &s,
V _. .___... V
ce ._. _53 .__. 4:5.
I Capacitive
i k turn-on loss
tr i . r i i "10
Figure 2-6 Duty cycle control
Sr __l l | L_
S3 '1 l 1 l—
Sz l I | _
S4 __—
ob.
Vac] in i; Vi"
E t
Capacrtive
i turn-on loss
tr T i I - l \ n10

 

 

 

 

V‘T’i 1
Additional
conduction loss

Figure 2-7 Phase-shift PWM control

18

 

 

 

 

The '
built and

“"aV'cf‘Om

Table 2-1 Comparison of Power Loss
Phase-shift PWM control

 

Duty cycle control

 

V.
[Eon'fil'fswj'z

 

 

 

 

 

 

 

 

 

Km
Tum-on loss E0" --2—- fsw -4
VCC CC
fit;
2 Vin
Tum-offloss 5017 °-I-/—-j}w -4 [Eofir -7—-fsw]-2
CC CC
1 V- 2 1 2
Capacitive turn-on '2""(2Cs)["12l] 'fsw '4 (E'(2Cs)'Vin 'fswj'z
loss 2
:Cs'Vinz'fsw :2.C3.Vi" 'fsw
(v 1 -nl ~D)-4
Conduction loss (vce_sa, 4110 -D)-4 ”-3" 0
+ additional conduction loss
Transformer RMS .
current 7110 J5 n10 JD < yams < n10
switching energy of IGBT under the test condition of V c = 600V , n :

* Eon, Eofl I

transformer turns ratio, 10 : Output current

1” Cs = Csp = Csn

2.3. Experimental Results

The 70 kW dc-dc converter using energy recovery passive snubber circuit has been
built and tested to verify the principle of operation. Figure 2-8 shows the experimental

waveforms of primary transformer current and the IGBT collector-emitter voltage (V e)

19

 

 

watef'or

 

.__4

FIEUre 2‘9

 

waveforms of the dc-dc converter developed in this work under the test condition of

V," =666V,Vo =750 V, 1:, =70 kad f, =13 kHz.

 

V Transformerxprimary current
[40o A/div] .._

  

 

""""" [F-‘l'KVceBSOV/drv]

[1 0 [1s / div]

 

 

 

Figure 2-8 Transformer primary current and IGBT voltage waveforms

 

REcovery current [1 A/div]
' ¢ lavg=0.68 A, |rms=0.8 A

      

Vce[250 V/div] , l

i.‘ t... - l—i- , l—-

[20,115 / div]

 

 

 

Figure 2-9 Recovery current in primary snubber resistor and IGBT voltage waveform.

20

 

(lisp am.
the ma
respectit

energy r.

power It

operation

2.4. Co

In 111%
Voltage 0.
Phase-5hr;
devices, (
CmBria f0

measmed .

 

As shown in Figure 2-8, voltage spike in the IGBT was well clamped to
approximately 1.2 times of the input voltage.
Figure 2-9 shows the recovery current waveform of the primary snubber resistor

(Rsp and Rs") and is synchronized with the Vce waveform. With input voltage of 666 V,

the measured RMS and average current in each snubber resistor was 0.8 A and 0.68 A,
respectively. Thus, the total amount of power recovered to the DC link through the

energy recovery circuit can be calculated as (2x0.68)x666=906W , while the total

power losses in the snubber resistors were only (0.82x8.6)x4=22W at firll-load

operation.

2.4. Conclusion

In this chapter, an energy recovery passive snubber circuit is proposed to reduce EMI,
voltage overshoot, and switching loss of the semiconductor devices. A duty cycle and
phase-shifted PWM control method are compared to analyze power loss of the switching
devices. Operating modes of the passive snubber circuit is explained and the design
criteria for selecting snubber parameters are presented. The experimental results are

measured to show performance of the energy recovery snubber circuit.

21

 

 

Cha
Illdl

3.1. L

Atr
through
this ener
shows [1'
general. 1
Umufinn.
because :

the eddy .

 

Chapter 3. High Power Transformer and

Inductor Design

3.1. Losses in Magnetics

A transformer is a device that transfers electrical energy from one circuit to another
through inductively coupled conductors—the transformer's coils. Unfortunately, not all of
this energy is recoverable in electrical form: a fraction is lost as heat [15]. Figure 3-1
shows the general losses of magnetic devices such as transformers and inductors. In
general, the losses in magnetic device are consisted of core loss and winding loss. For the
transformers designed with ferrite cores, the eddy current loss is ahnost negligible
because the resistivity of ferrite core is much higher than other materials [16]. Therefore,

the eddy current loss in core is not considered in this work.

 

 

 

 

 

 

 

Lossesin
magnetics
l
l . l
[ Core loss I Copper lossl

 

 

 

l
l I F l

F—lysteresis Eddy current 2 DC winding IAC winding
loss loss loss loss

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3-1 Losses in Magnetics.

22

 

3.2. T

3.2.1

Cor

 

acore rr.
[15]. F0
design tI
In tl‘
rating. I
is 14 in.
shows a
Hansfom
applied it
In g

is PTOpo
[Tansfom
Maintain
Slim of

Core IOS

negaIIV"

3.2. Transformer design

3.2.] Core loss

Core loss is caused by the energy required to effect a change in the magnetization of
a core material. This power loss can be observed electrically as hysteresis of the B-H loop
[15]. For a high frequency and high power transformer, the core selection and structure
design face many difficulties.

In this work, 6 pairs of U93/76/30-3C9O ferrite cores are used to achieve high power
rating. The number of turns in the primary winding is 6 turns and the secondary winding
is 14 turns considering input and output voltage range and duty cycle loss. Figure 3-2
shows a test setup for the transformer core loss measurement. To measure core loss, the
transformer secondary winding is open circuited and a square voltage waveform is
applied in the primary winding to magnetize the core.

In general, the core loss can be represented by a resistance RC because the core flux

is proportional to the applied voltage. Lm represents magnetizing inductance of the

transformer. A core with finite permeability requires a magnetizing current I Lm to
maintain mutual flux in the core. Therefore, the transformer primary current Ipn- is the
sum of [RC and IL," . In Figure 3-2, transformer leakage inductance and winding

resistance are not included in the transformer model to make analysis simple.
Figure 3-3 shows theoretical waveforms of the transformer current and voltage when
core loss in considered. When the transformer voltage changes polarity from positive to

negative, there is a drop in transformer current waveform which is labeled as 21 x . This is

23

 

 

the ind.
and cur
Figure 3'

ln 1
on the ii

34. The

Figure

 

the indication of core loss in the transformer. In addition to this, the transformer voltage
and current are not 90 degree apart. Instead, there is a phase difference labeled as 6‘ in

Figure 3-3. This is another indication of core loss in the transformer.

In this work, core loss is measured by integrating the product of voltage and current

on the winding by using an oscilloscope and the resultant waveforms are shown in Figure

3-4. The measured core loss was around 110 W.

 

 

I - 1 =0
P .
e —-> - AI l.n sec
Vpr'llll. RC Lm l V539
c -

 

Figure 3-2 Core loss measurement

 

 

V

pri

 

 

 

V

 

 

 

 

 

 

‘P' 0.0...
: V
.2. - '
t.’
H
V

T -
O

 

 

 

\/ \

 

 

 

 

’3.

I
0

o
role)
a
N
«‘1

Figure 3-3 Transformer voltage and current waveforms with secondary side open-

circuited

24

 

 

OI] .

tune pr

 

density (

and freon

 

   

 

 

[20,113 / div]

m ‘m in town unmrzwu my:
amount: it

Figure 34 Core loss measurement waveforms

On the other hand, transformer core loss can also be found by using the core loss

curve provided by the manufacture [17]. Figure 3-5 shows the calculated core loss
. . 3 . . . . AB
densrty (PC) in kW/ m of the 3C90 femte material plotted agarnst flux dener (—2—)

and frequency ( f”) with sinusoidal excitation.

10

_r
O
N

P, [kW/m3]
8‘

_r
O
o

 

10 10 10°
AB/2[T]

Figure 3-5 Core loss curves for 3C90 material.

25

 

 

Fri-

(3.1).

By
inductor

E Follm

 

Tiles

frequi’my

From the core loss curves, we can derive the core loss equation for 3C90 material as

(3.1).

AB 2.64
Pm =65.3x(fSW/1000)l'36x[7) [kW/m3] (3.1)

By choosing 6 turns for the primary winding and the resultant magnetizing

inductance (Lm) was 1.7 mH . Flux swing (AB) of the transformer can also be calculated

as follows

AB =M=0.424T (3.2)
Np x Ae

where, T0,, = 38.5 #3, A, = 50.4 on2
From (3.1), (3.2) and by multiplying total core volume (Ve) of the transformer to

(3.1), the calculated core loss becomes (3.3).

1.36
)

Pm = 65.3x(f,w/1000 x3164 xVe = 101W (3.3)

where, f,,, =13 kHz, B = 1.11x-é2'ig V, = 1782000 mm3

The core loss calculated in (3.3) is close to the measured value.

3.2.2 Winding (Copper) loss

The skin effect increases resistance and copper loss in the conductors since high-

frequency currents do not penetrate to the center of the conductor. Thus, the effective

26

 

Do:
Howeicl
copper it
high-Fret
known a
for foil -.
transforn
of layers

An a

harmonic

 

 

the losses

hft'tiionic

wire cross-sectional area is reduced which results in increased ac resistance (R06) [15],
[18].

Dowell solved this problem for sinusoidal waveforms in his 1966 paper [19].
However, skin effect alone is not sufficient to explain the increased high-frequency
copper losses observed in multiple-layer transformer windings. A conductor that carries a
high-frequency current induces copper loss in an adjacent conductor by a phenomenon
known as the proximity effect [12], [15], [19-22]. In a multiple layer winding, especially
for foil windings, the proximity effect is the main efficiency killer of high frequency

transformers because Rae caused by the proximity effect increases greatly as the number

of layers increases.

An arbitrary periodic current waveform is represented by its Fourier series and all the
harmonic components are orthogonal so that the total power loss is equal to the sum of
the losses calculated by Dowell’s formula for the amplitude and frequency of each

harmonic in turn. Therefore, the total power loss due to all the harmonics is expressed as

P—E’I2 Train—12 34
‘dcdcT dcz Rn ()

n=1

where E; is dc winding resistance/tum, [dc is the dc component of current, It is
harmonic number, and 1,, is the RMS value of the nth harmonic. For the transformer
winding, the first term in (3.4) becomes zero because there is no dc component in current.

F R is expressed as

F_R=Jr7o[(2m2 -2m+1)G1(\/I—1¢)—4m(m—1)G2(Jr_1(0):l (3.5)

27

 

In;

.5 r—_
GIN,“

When
Sides of U

“mdlngs l

 

T312) [15]

In (3.5), (p is the ratio of the layer (copper) thickness h to the skin depth 6 ,

016/309) and Gz (Jr—2(0) are expressed as follows

 

 

 

G = sinh(2~/;¢) + sin(2~/;(0) 3.6
[(609) cosh(2\/;¢) — cos(2\/;i¢) ( )
G ___ sinh(J;¢)cos(./Zo)+cosh(./Zgo)sin(./Z¢) .
2 (5” cosh(2\/r_r¢) - cos(2\/r—r¢) (3 7)
The value for m in (3.5) is defined as follows.
m = F(h) (3 8)
F(h) —F(0) '

where, F (0) and F (h) are the magneto-motive-force (MMF) for the left and right
sides of the layer of thickness h [15]. To calculate the total power loss in an M layer
winding, F R is found by summation a over all of the layers as

FR = 121-FEE! J72¢[(2m2 —2m+1)Gi (J;¢)‘4m(m‘1)Gz(\/;¢)] (3.9)
m=l

m=l

With the help of identities expressed in (3.10) and (3.11), (3.9) can be rewritten as

(3.12) [15]

Ag mzw (3_10)
m=l

112g m2 _ M(M+1)(2M+l)
m: 6

 

(3.11)

28

 

,whe

 

 

 

In th
reduced ‘
Added b
with Iitz

To

2
FR = MJ;¢[GI(JZ¢)+-3-(M2 -1)(Gr(\/;r0)- zoztfioifl (3.12)
Therefore, the total power loss in an M layer winding is expressed as

13...; = Rd. 35 bis/5401 (MH-i—(MZ —1>(G.(JZ¢)—262(JZ¢))] (3.13)

n=1

,where Rdc is the total dc winding resistance in an M layer winding and is equal to
Rdc = MEI-1c- -

In this work, copper foil is used rather than litz wire because transformer size can be
reduced by using copper foil because higher fill factor than litz wire can be achieved.
Added benefits of using copper foil are better heat transfer capabilities than those wound
with litz wire especially for air cooled transformers, and low leakage inductance.

To reduce the proximity effect mentioned above, the number of layers should be
reduced by breaking up the windings into smaller sections through interleaving.

Figure 3-6 shows the winding geometry and MMF waveform in the window region
of the core with single interleaved winding. The 6 primary turns are split into two sets of
3 turns which sandwich the 14 secondary turns.

To calculate the m values for each layer, it is assumed that the transformer primary

N
winding carries current i. Therefore, 31' (=—1VP-i ) current flows through the secondary
S

winding. In the leftmost primary winding of Figure 3-6, the layer carries current i. The
MMF changes from 0 to i. The m value for this layer is found by using the definition

shown in (3.8) as.

29

l

 

m=&=;=1 (3.14)
F(h)—F(O) 1-0

secondary

 

Figure 3-6 Winding arrangement and MMF waveform in transformer with single

interleaved winding
For the leftmost secondary winding of Figure 3-6, the layer carries current -:—i and

the MMF changes from 3i to (3i-gi ). It should be noted that the roles of F (O) and

F (h) can be interchanged when F (0) is greater than F (h) [15]. Therefore, the value m

for this layer can be calculated as

30

 

“ Tah
indin
g
using th
loss W]
P0
wer It

fr
equen
c

 

' V'i

l

[77
W

3i

 

m: = =7
F(0)—F(h) 3i—(3i—3i/7)

All the values for m in can be calculated similarly.

Table 3-1 lists the transformer current waveforms in both primary and secondary
windings and the electrical parameters of copper foil used to calculate winding loss. By
using the equation (3.13) and the electrical parameters listed in Table 3-1, total power

loss versus no, for several values of M , is plotted in Figure 3-7 and Figure 3-8. The total

power loss is calculated up to the 29th harmonics of current. With the switching

frequency of 13 kHz, the skin depth at 100 °C is calculated as

5=L cm

J7

Table 3-1 Current Waveform and Electrical Parameter of Copper Foil.

75

Jl3000

= 0.658 mm

 

Vin=500, D=0.32, Po=70 kW, fs=l3 kHz

 

Primary current

in nun

Frat Kl

‘
r

 

 

 

l_l/I 93A --
I\l

 

 

 

 

 

Secondary current ;
Faye
Copper width 100 mm
Insulation 0.13 mm Nomex paper
Mean length / turn 460 mm

 

 

31

Power loss [W]

Power loss [ W]

.A
O

-1

10

10'

 

 

 

 

 

‘5‘““5 sé‘sssw“

 

 

 

 

' vv' v v

b

 

- All

 

 

A - AJ ALL

5 s assas-

 

 

10'

h 10
¢=-

6

II II II II II
N W #- UIONQOO

=8
=7
=6
=5
=4
=3
=2
m=1

Figure 3-8 Secondary winding loss in single interleaved winding.

32

 

strap.
.1! a1
is a‘
CUP?
suhd

fins

.2)
1

31¢

loss

5311

l‘

.s‘

As shown in Figure 3-7 and Figure 3-8, the total winding loss increases greatly due

to the proximity effect as M increases. Larger copper loss is obtained for small (p

simply because the layer is thin and hence the dc resistance of the layer is large. For large
M and q), the proximity effect leads to large power loss. Between these extremes, there
is a value of 40 which minimizes the layer copper loss [15]. When the ac resistance of a
copper foil is too high because the copper thickness is too great, it is tempting to simply
subdivide it into several thinner strips, insulated from each other. It should be noted that
this does not work unless they are twisted like litz wire [12]. From the result of Figure
3-7 forM = 3 , the first half of the primary windings yield a minimum power loss of 40 W
at ¢=0.6 (point “A”). Similarly, from Figure 3-8 for M =7 , the first half of the
secondary windings yield a minimum power loss of 30 W at (0 = 0.3 (point “B”). As a
result, total minimum power loss in the transformer winding is 2 x (40 + 30) = 140 W .

In this work, the transformer winding is interleaved again to further reduce power
loss and the resultant winding geometry and MMF waveform are shown in Figure 3-9

The 6 primary turns are split into 3 sets of 2 turns. Again the 14 secondary turns are
sandwiched evenly between the primary turns. The m values are calculated using the

same method used for single interleaved winding. For the leftmost secondary winding of

Figure 3-9, for example, the layer carries current %i and the MMF changes from 21' to

(21' ~34). Therefore, the m value for this layer is

m: F(O) =_ 2' :2 (3.17)
17(0) — F(h) 21 — (21 — 31/ 7) 3

 

33

 

 

 

All I
Similarly.
Emeline
binding t
ime’s’ifrs. 1
Venus (0 1

Then
IOSS I'Ersui

r6311115 are

 

 

secondary primary secondary

 

Figure 3-9 Winding arrangement and MMF waveform in transformer with double

interleaved winding

All m values for the primary and secondary winding in Figure 3-9 can be calculated
similarly. However, m values for the secondary winding in this case are not integers.
Therefore, we cannot use equation (3.13) to calculate the total power loss in an M layer
winding because (3.13) is derived by using (3.10) and (3.11) which are only valid for
integers. In order to find the total power loss when m is not integers, the power loss
versus (0 is first plotted for each layer using (3.5) and the m values in Figure 3-9

Then the power loss in each layer is simply added together to plot the total power
loss versus (a. The total power loss and optimum layer thickness can be found and the

results are shown in Figure 3-10 and Figure 3-11.

34

 

 

 

 

 

 

 

 

105 j V 'T V T
E

103%.,
E t '
V:
'6
s. c r
L .
Q) .goII-uouom
e . '“1/‘— i
Q” 1012' \Y

0

1o 4; .1 n r In.“ 4 L

10'2 10‘1 h 10°

(D=-

6

Figure 3-10 Primary winding loss in double interleaved winding

 

 

 

 

 

 

3
10 , r r * T *‘ ' " .
1., 3
i '0’...
2 r .0. d
'o
10 f .0.... ...ll.......:i
: . ‘ :
\l ...A_ .g...‘ m
a 1
o 10 r .m
N I .m
A“, i .4 i
3 P ‘g ‘m
o ' ~m
Q’ ‘100 r a
a :m
.1 1 A 4 A ALLAI A
10 -2 -1 o 1
10 10 h 10 10
(0:;

II II II II
\roov-n—
\

b) (Mum

II
u:

11
N 4}
\ \
DJ 03

Figure 3-1 1 Secondary winding loss in double interleaved winding

35

 

Th1
power 1.
loss in ti
likewis
winding
power It
with sir.
depth \‘5

secondar

 

The power loss in each layer is plotted (solid line) and is added to plot the total
power loss (dotted line). From the result of Figure 3-10, the first half of minimum power

loss in the primary winding occurs at point “C” where the power loss is 26 W at p = 1.0.
Likewise, from Figure 3—11, the first half of minimum power loss in the secondary
winding occurs at point “D” where the power loss is 20 W at g) = 0.45 . Therefore, total
power loss in both the primary and secondary winding is 2 x (26 + 20) = 92W . Compared
with single interleaved winding, there is 35 % reduction in winding loss. With the skin
depth value calculated in (3.16), the copper (layer) thickness in both the primary and

secondary winding can be calculated as follows

h
om ‘3 —> h = om x6: 1x0.658; 0.658 mm (3.18)
h ~
cases. = 3 —> h = (0..., x 6 = 045x 0.658 = 0.296 mm (3.19)

From Figure 3-6 to Figure 3-11, the double interleaved winding has lower copper
loss than the single interleaved winding. It also decreases transformer leakage inductance
since the peak value of MMF in double interleaved winding is less than the value of the
single interleaved winding. Reduced leakage inductance is helpful in minimizing voltage
overshoot in the rectifier diodes. In this dissertation, at standard 0.6 mm and 0.4 mm
thickness copper foil are used for primary winding and secondary winding, respectively.

Figure 3-12 and Figure 3-13 show 3-D pictures of the 70 kW transformer designed in
this work. After assembled with ferrite cores, the transformer was molded in an
aluminum case to prevent the transformer from vibration and other possible mechanical

stresses. Finally, the transformer is mounted on the main heatsink for heat dissipation.

36

 

Secondary 1
Figure 3-12 Transformer winding geometry

 

Figure 3-13 Transformer assembled with core and housed in aluminum case

37

3.3. Inductor design

For the output filter inductor of the DC-DC Converter, Changsung megaflux block
core is used for core material. Since two inductors are used in the output of the converter,
a coupled inductor is used for those two windings. By using a coupled inductor structure,
the inductor volume can be reduced significantly because two windings are wound on the
same core and the system performance can be improved [23], [24].

Two different sizes of distributed air-gap block core (BK10225+BK8225) are used to
form a rectangular core structure as shown in Figure 3-14. In order to reduce the number
of turns in the inductor winding and copper loss, 5 pairs of rectangular cores are stacked
together. Table 3-2 shows the detailed information of the coupled inductor designed in

this work.

 

 

Figure 3-14 Block core assembly

38

ill

-1

H

 

 

 

.Whe
mdUCtor
mducram
milligram

{1

441177

Table 3-2 Coupled inductor design parameters.

 

 

Assembled AL Magnetic Core Window
Core Unit core value path cross- area Volume
[WXLXH 2 length sectional 2 [cm3]
[nH/N] 2 [cm]
m] [cm] area [cm ]
BKl 0225-10

PCS +
BK8225- 80X 150)( 100 362 33.85 25 30 891

1 Opes

 

 

 

 

 

 

 

 

 

3.3.1 Inductance Calculation by Permeability vs. DC Bias

Curves

In this work the output inductor value was calculated with maximum input voltage
because inductor current ripple is maximum at this condition if output voltage is
regulated (constant). The inductor current ripple is set to 30 % of output current in this

design. Therefore, the inductance value desired can be calculated easily as

(an —V0)XDT _ 2.33x666—750x 750

s ’ 0.3x93x26000 2.33x666

 

L =24an = = 534,11H (3.20)

,where VL is voltage across the inductor, D is duty cycle, I; is period and AI is

inductor current ripple. It should be noted that the inductance calculated in (3.20) is the
inductance value when two inductor windings are connected in series. Therefore, the
inductance value measured at one side with the other side open-circuited would be

534pH/4=133.5,uH.

39

A~
increas

contig.

the to-

 

calcula:

The
increase
durene

11%»
“L1 \FII

 

Fl,

As already shown in Figure 3-14, 5 pairs of block core are stacked together to
increase core cross-sectional area (Ae) and to reduce the number of turns. With this core
configuration, the AL value was 362 [nH / N 2] and 23 T is wound in each winding of
the coupled inductor. From the AL values and number of turns, the inductance can be

calculated as follows.
L@0A =362 on462 =766 ,uH (3.21)

The inductance calculated in (3.21) is the inductance value at 0 A. As current
increases, however, the inductance value decreases because permeability of the core
decreases. This is a typical characteristic of power (or distributed airgap) core which is

different fi'om ferrite core.

 

 

 

 

 

 

 

% permeabI/Ify vs H curve »
BrockCom'Dcam wmgfrngi ‘
ex ..............,. ,,,, ‘
m4 .

_E 150: -

g 5.: .

o. ‘O'I '

a? 30. _

20.. _

.o.‘ .

0"“a'maar3to' 200250300 an...
munching" Foroe[0e]

 

 

 

Figure 3-15 % permeability vs H curve of Changsung megaflux block core

40

increas

 

Or.
in Figu
perinea'."
its initia

A) is ca]

3.3.2

 

 

lhef

Figure 3-15 shows the change in core permeability as magnetizing force (H )

increases. To determine H in Figure 3-15, Ampere’s law is applied as

 

 

_ ,uoNI _ 0.47rx46x93
l 33.85

m

H = 158.8 [0,] (3.22)

Once H is found, % permeability of the core can be estimated fi'om the curve shown
in Figure 3-15. According to the H value calculated in (3.22) and Figure 3-15, %
permeability is almost 70 %. This means that permeability of the core rolls off to 70 % of
its initial value when current flow is 93 A. Therefore the inductance at rated current (93

A) is calculated as

L@93A = 0.7 x 766 pH = 536 ,uH (3.23)
3.3.2 Core loss

Core loss can be calculated by using the core loss equation given by the

manufacturer. Eq. (3.24) is the core loss equation for Changsung megaflux core [25].

1;. = 1.785.3105 x f1-535 [mW/cm3] (3.24)

, where B is flux density in kilogauss, f in kHz, and Ve is the total core volume.

The flux density (AB) can be calculated as

A3: VLxTon = ("Vin—V0)an
Ner Ner

 

(3.25)
(2.33x666-750) x 750

= =0.I3T
46x25x10'4x26000 2.33x666

 

41

 

[Olfll Ct‘

 

33.3

Figu

resistii'in

With the flux density (AB) calculated in (3.25) and core volume in Table 3-2, the

total core loss is calculated as follows

P,,,, = 1.78x 32-05 x f1-535 x V, =120 W (3.26)

where, fsw = 26 kHz, B =1.llx-A—2§, Ve =891 cm3

3.3.3 Winding loss

Figure 3-16 shows the copper resistivity as copper temperature varies. The copper

resistivity p increases as temperatures increases [26]. For example, p at room
temperature (25 °C) is about 17 an or 1.7 chm. However, p at 125 °C is almost 1.4

times bigger than that of at room temperature. Therefore, care should be taken in

calculating copper loss of the inductor. In this work, copper loss was calculated at 125 °C.

40
35

30

25* /L/-
20‘ /
15‘ /_..o
10‘ /.«l
5.

#/

 

 

/.

 

 

 

 

 

 

 

 

Copper resistivity [nohm.m]

-5 I
-10

 

 

 

 

 

 

 

 

 

 

 

-300 -200 -100 0 100 200 300
Temperature [Celcius]

Figure 3-16 Copper resistivity vs. temperature

42

 

Th 1-

this calc:
with DC
1201‘98 :

F igur

designed 1

 

A 10 mmX3 mm rectangular copper wire is used and the total winding length of 46 T

inductor is approximately 0.31 M x46 = 14.26 M . Therefore, the total DC winding

resistance is calculated as

14.26

RDC=1.4x17x10“9x————=11.3 mg (3.27)
30x 10‘6
Thus, the winding loss of inductor at 93 A is
PW -_-932><11.3x10‘3 =98 W (3.28)

The AC winding loss caused by the skin and proximity effect is not considered in
this calculation because AC ripple current of the inductor is relatively small compared
with DC current. From the above calculated results, total loss of the output inductor is

120+98=218 W.

Figure 3-17 and Figure 3-18 are the side and top view of the coupled inductor

designed in this work.

3.4. Conclusion

In this chapter, a 70 kW high power and high frequency transformer and inductor are
designed. To reduce proximity effect in the transformer, two winding structures were
invoked and its copper losses were calculated and compared. The optimum copper
thickness which gives minimum power loss was found. Thus, the power loss and
transformer size can be minimized with this approach.

The output coupled inductor is designed with the distributed airgap core. The very

detailed design procedures are explained and core and winding losses are calculated.

43

 

 

 

 

 

 

(TL-V hole to hole center : (p7 (151mm x 117mm)

Figure 3-18 Inductor assembly (Top view)

 

_AF'

Ch

Sec

4.1. I

located

 

 

 

Chapter 4. Voltage Oscillation Problem in
Secondary Rectifier Diode

4.1. Introduction

Besides the two key issues addressed in previous chapters in designing high power
dc-dc converters, one more important issue in full-bridge dc-dc converters employing a
diode rectifier in the output is voltage oscillation problem in the rectifier diodes. This

oscillation is caused by the resonance between junction capacitances (C j) of the rectifier

diodes and leakage inductance (le) of the transformer since the rectifier diodes are

located between the two current sources, i.e. transformer leakage inductance and output

filter inductor (L0) [27, 28].

Figure 4-1 shows a conventional V-source type transformer isolated dc-dc converter.

L

.nnnuunuunnnn-l 0

- - rim
Ztlcj

CI
_TDz

1:
D

A

nigh}
Mi) my?
a]? 541535

'

 

 

 

131:1”

.- P--------

9

 

 

m"I

 

 

 

 

 

 

 

—_l_Cj C'

v

---IF--- ----

 

 

 

 

 

 

Figure 4-1 Voltage oscillation problem in secondary rectifier diode

45

across
I:
and ca

voltage

I I
l

 

loss 3:.
recover
In
prei'iou
which c
[:7]. Fit

increase

 

 

The

HOWEV’e

Moreover, reverse recovery current of the rectifier diodes increases the voltage spike
across the diode significantly [29]. Therefore, it increases the diode voltage rating, cost
and causes EM] problem. As the output voltage of the dc-dc converter increases, higher
voltage diodes are required. However, the use of a higher voltage diodes increases power
loss and voltage overshoot in the diodes because higher voltage diodes have poor
recovery characteristics.

In order to reduce voltage spike in the rectifier diodes, several techniques have
previously been proposed. The conventional method is the use of an RCD snubber circuit

which consists of diode (D3 ), capacitor (C, ), and resistor (Rs) as shown in Figure 4-2
[27]. However, power loss in the snubber resistor R, is very high as the output power

increases. As a result, it degrades system efficiency.

- C}. .
isn't—13S SZJE’} LII: 1:n D'JDZZF}

nifi 5.15} D31CD471EF .

Figure 4-2 RCD clamped circuit

 

 

 

 

.V

 

 

 

 

 

 

 

 

 

 

 

 

The active clamp method shown in Figure 4-3 can solve the efficiency degradation
problem and the voltage overshoot can be clamped effectively with this method.

However, this method degrades system reliability and increase complexity because

46

 

Lin”

1‘ ;
[2011

S‘
l+/——

K

 

 

 

 

3th the
fittiiier

desirabi.

additional switching device and gate drive signal are required to control the switch, Q,-

[30]. Therefore, it is not desirable in high-power applications, either.

L

0

e - - from
zFlcj bCH
s,_ll= SZI': L,,r 12,, DIJDZ C,
1— l—i C C 1 Q3
SLIfi} S4Ifi} D31D4fij_

Figure 4-3 Active clamp circuit

 

 

1_.

 

 

 

 

 

 

 

 

 

 

The converter circuit shown in Figure 4—4 uses a capacitor (Cb) connected in series

with the transformer to eliminate the voltage oscillation problem in the secondary
rectifier diode and showed good performance [31]. However, this method is also not

desirable in high power applications due to the series connection of the bulky capacitor.

L0
- - 51m
Si-lfi Sz-IE’} L17: l:n £96,152ng +
.(it) % Cb . V
S3.l Pi} S4..l E} QE‘Cb4ficj _

v f

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4-4 Voltage oscillation reduction circuit using C b

47

 

4.2.

To
(ERCC
cmplm

and my

 

l-‘l

4.2. Review of Previously Proposed ERCC

To overcome the aforementioned problems, several energy recovery clamp circuits
(ERCC) have been proposed [9, 10], [32-34]. Figure 4-5 shows one example of an ERCC

employed in a V-source type PWM dc-dc converter [9]. It consists of one capacitor (C3)
and two diodes (Dsl , D32) to clamp diode voltage and there is no dissipative resistor.

Therefore, the circuit can achieve lossless clamping function and no active switches are

used.

A A

slit—I} Szl a} L”, M DIEC£2ECI+
VMCLD mg g 14....
53] fl $4.] H 03 1%,??? _

Figure 4-5 Energy recovery clamp circuit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4-6 shows the ERCC slightly modified from Figure 4-5 and is labeled as
ERCC #1 in this dissertation. In this dissertation, the transformer secondary winding is
split into two windings to achieve high output voltage and to use standard 1200 V diodes.
Two rectifier bridges are used and their outputs are connected in series. With this
configuration, each bridge needs to sustain only one half of the output voltage.

Transformer turns number is set to 6:7:7 (N p :N 31 :st) by considering the duty cycle

loss caused by transformer leakage inductance and others. le is the transformer leakage

48

 

 

Tr‘
Figure

Flg’flfi 1

 

l,l__

inductance reflected to the secondary side of the transformer. In Figure 4-6, the switching
devices in the transformer primary side are not included for the sake of simplicity.
The same ERCC used in Figure 4-5 is attached to the top and bottom rectifier of

Figure 4-6. Therefore, operation of the circuit is exactly the same as the one shown in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4-5.
L0 V0
Cs]
Dsl ;
.L
Dhl CS“ CON;
0 — 5
:FH: %| - - 3RL
ti I":
+ 0’12 Cs12 Cok’o‘
o D 2
V...c V,“ 32 -
| .._n -
D __l C 2
glflcflhcj its [fix

Figure 4-6 ERCC modified from Figure 4-5 (ERCC #1)

""""" Vrec_pk : (2 " D)Vsec

  

 

Vsec

 

 

 

)1

Figure 4-7 Diode voltage (Vrec ) waveform of ERCC #1.

49

 

 

Fig‘

consider

tapacito

 

usumpt;
Stray ind

Clo-$610 l

   

 

 

Vrec_pk A
2Vsec """""" J: --------- E"
1°5Vsec """""" i """""" z“
Vsec """""" 1: """"""" i -
0 0:5 1' ’
Duty cycle (D)

Figure 4-8 Vrec_ pk vs duty cycle (D) of ERCC #1

Figure 4-7 depicts the peak voltage V k across the rectifier diodes without

rec __ p
considering diode reverse recovery current and with the assumption that snubber

capacitors, C51 and C32 , are much bigger than diode junction capacitance, C j. With this
assumption, Vrec_ pk can be expressed as (4.1) [9]. Cs“ and C322 are added to minimize

stray inductance of the clamp path and they can be removed if output capacitor is very

close to ERCC.

V V V
Vrec_pk :2(Vsec __22)+—§_=2Vsec _70:(2-D)Vsec (4'1)

where, Vin is input voltage of the dc-dc converter, n is transformer turns ratio

(n: 1=Ns2
NP NP

 

 

), Vsec is voltage in the transformer secondary winding (= an ), V0 is

 

output voltage and D is duty cycle of the converter (= £- :0 ).

SCC

50

 

666 \'

CVCIC .

Prom ..

C 0
diodes =

inthis

 

Figure 4-8 shows the Vrec pk as D changes. In this work, Vin changes from 333-

666 V and V0 is regulated to 750 V. With this input voltage range, the minimum duty

cycle can be determined as.

 

E; 7i)
Dmin = V2 = 7 2 40.483 (4.2)
56¢ —6-x666

From (4.1) and (4.2), Vrec_ pk can be calculated as.

V,“ pk = (2 - D)Vsec = (2 — 0.483) x g-x 666 = 1180 V (4.3)

Considering the reverse recovery current in the rectifier diodes, the voltage stress in
diodes would be easily higher than 1200 V. Thus, we cannot use standard 1200 V diodes
in this case. Again, the use of higher voltage diodes increases power loss and voltage
overshoot across diodes because higher voltage diodes have poor recovery
characteristics. Therefore, the ERCC #1 shown in Figure 4-6 is not applicable to the
system described in this work, although it has the advantages of resetting circulating
current in the primary side and achieves zero-voltage and zero-current switching
(ZVZCS) in switching devices using the phase shift PWM control method [9].

Figure 4—9 shows another example of an ERCC modified from [29]. In [29], the two
top and bottom output filter inductors are positioned to face each other at the middle of

the circuit. The circuit in [29] works only when Vsec is less than V0 (i.e., D > 0.5) and the

Vrec_ pk is clamped to V0. However, when Vsec is higher than V0 (i.e.,D<0.5 ), this

51

circuit does not work because a huge current will flow through snubber diodes, 051 and

D

S

2 , eventually destroying them. One possible way is to insert additional snubber

resistors, R51 and R52, as shown in the dashed box in Figure 4-9. By inserting R31 and

R32 in the discharging path of snubber capacitors, CS, and C32 , a portion of energy

stored in LII: is dissipated in R31 and R32 , and the rest of the energy can be transferred

to the output capacitor. The total power loss in R51 and R52 is calculated as (4.4).

V —V 2 —2DV 2
P=PR31+PR52=2( rec_pk 0) =2( _pk sec)
RS RS
where, Rs=Rs1=Rs2.
Vo
L D D62E1
lznzn 1k _TCj _Tc.

 

 

 

 

 

 

 

 

 

 

O“... m“!

 

 

 

 

 

 

 

 

 

 

le D] c?
o 4
VSCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4-9 ERCC modified from the circuit in [29]

52

R1.

(4.4)

 

 

 

are DUI

Fig
the We
in “hit
and re]

and Cs

Compared with conventional RCD snubber circuits, such as the one shown in Figure

4-2, the power loss in R51 and R52 is reduced significantly because the voltage across
R31 and R32 can be reduced a lot [35]. The power losses in RSI and R32, however, are

not negligible when D varies in a wide range. Therefore, the ERCC shown in Figure 4-9
also suffers from the efficiency degradation problem and are not applicable to the system

discussed in this dissertation.

4.3. Proposed ERCC
4.3.1 Principle Operation of Proposed ERCC

The two ERCCs discussed in Figure 4-6 and Figure 4-9 have some limitations and
are not desirable for systems with wide ranges of input voltage, especially when D < 0.5 .

Figure 4-10 shows the ERCC proposed in this work that overcomes the drawbacks of
the previously proposed circuit. The proposed circuit employs a simple auxiliary circuit
in which neither lossy components nor active switches are used. Therefore, the efficiency

and reliability of the dc-dc converter can be improved with this proposed ERCC. C 311
and C322 are added to minimize stray inductance of the clamp path
The transformer secondary current 11k (t) and diode voltage Vrec (t) waveforms are

sketched in Figure 4-11.The output filter inductor L0 is assumed big enough and thus I 0

can be modeled as constant. Operational modes of the proposed ERCC are explained as
follows and are shown in Figure 4-12. For the sake of simplicity, only the diode rectifier
located at the bottom is considered and analyzed because the top and bottom rectifiers

operate in the same manner.

53

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4-10 Proposed ERCC.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

  

 

 

 

 

 

 

 

 

 

.. .. .... I §
» \
. q )
wnthout
,o'ainubber
i Vsec
VCSI: I ”W I I“. ......=..
ll
V0 II
II I
_L . 3) V01
t' tt' tx ( '
0 1 2 3 t4 t5t6 t7

Figure 4-1 1 Key waveforms of proposed ERCC.

54

 

 

 

 

l ~|°V +

 

p
- .9
\l
I
:2;
oh

 

 

 

 

 

 

 

 

 

 

4.”
~
.9
. .9;
, .3
a
E 2‘.
0' °h
g3
#—
l N '0‘ +

 

 

 

 

 

I ~|°V +

 

 

 

 

 

 

 

 

I [QIQV 4"

 

 

 

 

 

<M0de 2,3 >

Figure 4-12 Operational modes of proposed ERCC

55

Figure 4-12 continued.

 

_—
‘

 

322

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

<M0de 5 >

56

 

 

 

Figure 4-12 continued.

 

 

 

l NIQV +

 

\I

ll
an
N

 

 

 

 

 

 

\
ll
0

 

 

 

 

 

 

 

 

D
9: .9
:29
cm
I NIQV 4"

 

 

 

 

 

I MIQV +

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14le C}2 )- =ECsl 0 +
4+ V.
D31 C0 ?
D3? 13%} TDhl szll ’
C1 C; ,
<M0de 7>

57

 

Figure 4-12 continued.

 

:: 322

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

03 §C€4§Cj

<M0de 8>

 

- Mode 1 (~t0 ):S1 —S4 turned off and rectifier diodes are in freewheeling period.

Vsec remains zero. D1 - D4 are on and each diode carries —0—
2

- Mode 2 (to—t1 ): S1 and S4 turn on. Vsec changes from zero to nVin and

transformer secondary current builds up linearly with the slope of n—V'i until it reaches
Ik

10. The current in D1 and D4 increases, while the current in D2 and D3 decreases in

this mode.

- Mode 3 (t1 — t2 ): reverse recovery period of D2 and D3. The current in D1 and D4

”Vin

 

builds up with the same slope of until Dz and D3 turn off at 12.

L1]:

58

At t: t2 , the current in L”. becomes 10 + 21,, , where 1,, is the reverse recovery current
of the rectifier diode. Until this mode, Vrec remains zero because D2 and D3 are still on

(conducting).

- Mode 4 (t2 —t3 ):D2 and D3 snap off at t2 and its junction capacitors, C -, start
resonance with L“. During this mode, Vrec and 1le are expressed as follows with the

initial conditions Vm (O) = O , 1 L1). (0) = 10 + 21,, .
Vrec (t) = nVin [l — cos(w0t)] + (IRZc)sin(wot) (4.5)

1le (t) = I 0 + "71/i’1-sin(wot)+ I R cos(w0t) (4.6)
C

L11:

1
-——, w =——, IR = 21
2CI 0 JLIkQCj) "

- Mode 5 (t3 —t4 ): When Vrec reaches V0 at t3 , Dsl starts conducting and there is

where, Z c =

another resonance between C51 and le . Because C51 is much bigger than C - , the
current flowing through C j can be ignored in this mode analysis. C511 is added to

minimize circuit stray inductance in the snubber path, C31 —Dsl ‘Csll , and can be

assumed large enough because it is connected in parallel with the output capacitor.

During this mode, Vrec and 1le are expressed as (4.7) and (4.8) with the initial

conditions Vrec(0) = V0 , 1le (0) = 1p. [p is the current at t=t3 and can be calculated

from (4.5) and (4.6).

59

 

z .
Vm(t) = V0 + (n V," — V0)[l — cos(wdt)]+ -Z—d-\/(IRZC)2 + 2nV,,,V0 — V02 sm(wdt) (4.7)

C

 

--V 122+2VV_V2
IL (0:10 +———an °sin(wdt)+J( R C) n m 0 o
1k 24 2,,

LI): ’le 1
where, Z = —, Z = —, w =
c J 2C} d C51 d \lLIszl

At t= t4 , V,“ (t) reaches its peak value Vrec pk because 1le (t) becomes equal to

 

cos(wdt) (4.8)

 

10 at this point. From (4.7) and (4.8), Vrec_ p), can be derived as.

 

L 2C-
Vm p1 = an + Jo: V," — V0)2 4—1’L1R2 +—L(2nV,.,,V0 — V02) (4.9)
- Cs] Cs]

V0 can be expressed as

V0 =2xDanm (4.10)

Substituting (4.10) into (4.9) yields

 

V,ec_ p1 = an +\/[nV,-,,(1—2D)] “LC—”(1.1192 +Fll-(an)24D(1—D) (4.11)
S S

- Mode 6 (t4 —t5 ): when 1 L11: is equal to 10 at t4, Dsl st0ps conducting and there is a
resonance between Lu and C j. This resonance is similar to that of Mode 4. During this

mode, V

m. and 1le starts decaying with oscillation and finally converges to nVin and

I , res ctively. The voltage in C is kept constant to V during this mode.
0 p6 Sl CS]

60

- Mode 7 (t5 —t6 ):S1 and S4 turned off at 15. 1le and V start decreasing.

rec

- Mode 8 (t6 —t7 ): Vrec is equal to VCSl at t6 and D,” starts conducting at this point. C31
can be discharged through Dhl and supplies a portion of the load current 10. VCS1 is

fully discharged at (7 and D] — D4 turn on and start freewheeling after t7 .

The operational mode analysis shown above is applied to the condition of D < 0.5

(i.e., V

SCC

>V0). For D>O.5, V,

ec_ pk (= VCSl +V0) is almost equal to V0 because the

current in the transformer leakage inductance is not sufficient to charge C31. From the

results mentioned above, Vrec_ pk can be expressed as (4.12) and (4.13) forD < 0.5 and

D > 0.5 , respectively. It should be pointed out that reverse recovery current of the

rectifier diode is not included in (4.12) and (4.13) for the sake of simplicity.

V

mm. = 2(1/sec — V0) + V0 = 2(1— 1))Vsec (D < 0.5) (4.12)

V

rec

V
_psz0=2x-2£=2DVsec (D>O.5) (4.13)

Using (4.12) and (4.13), V,

8C_p

k of the proposed ERCC is plotted in Figure 4-13 as
a function of D with Vsec and V0. Vrec_pk in Figure 4-8 is plotted again for comparison
with the proposed ERCC. As shown in Figure 4-13, Vrec_ pk is clearly reduced by using

the proposed ERCC within the duty cycle range of 0<D< 2/3 . When D=O.5 , for

example, Vrec_ pk of the proposed ERCC is VSec (or V0) while Vrec_pk of ERCC #1 is

1.5xV

sec

(or l.5x V0 ). Thus, there is a 50 % reduction in Vrec_ pk by using the proposed

61

ERCC, which enables the use of low voltage diodes and leads to higher efficiency of the

dc-dc converter.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vrec_ pk Vrec_ pk
‘2’ng Q
1.5V,.,c .. ‘
..‘~‘ 1.5V “ .
VSCC . V00 “~ Q
0.5V0
0 0.5/k 1 ’D 0 0.5/ IVD
D. = 2- D‘ = E
3 3
------- ERCC #1

 

Proposed ERCC

Figure 4-13 Comparison of Vrec_ pk as a function of D.

Although the proposed ERCC has higher voltage spike when D > 2 / 3, it does not
degrade performance of the proposed ERCC because diode voltage rating is determined
with maximum input voltage or minimum duty cycle of converter. In other words, the

increased voltage spike when D > 2 / 3 is still within the range of diode voltage rating.

4.3.2 Simulation and Experimental Results

A 70 kW prototype dc-dc converter employing the proposed ERCC has been built
and tested to verify the principle of operation and is compared with simulation results.

Table 4-1 shows operational conditions and circuit parameters of the dc-dc converter

developed in this work.

62

Table 4-1 Operational Conditions and Circuit Parameters of dc—dc Converter

 

 

 

 

 

 

 

 

 

 

Input Voltage 333 - 666 Vdc
Output Voltage / Current 75 0 Vdc / 93 A
Switching frequency 13 kHz
IGBT Powerex CM600HU-24F (1200V, 600 A)
Rectifier Diode Powerex QRD1230T30 (1200 V, 150A)
(D1 -D3) m=130 ns, Irr=30 A
Transformer turns number 6: 7 :7
Transformer leakage
inductance (Lu) in 1 ,uH
secondary
C J- 1 nF
C31, C32 100 nF
C511 , C522 470 nF

 

Dsl ’ D32 ’ Dhl ’ Dh2

IXYS DSEI 2 X61-12

 

L0

500 pH

 

 

CO

 

9.4 mF

 

 

Figure 4-14 and Figure 4-15 shows the simulation results of the dc-dc converter

when D=O.483 and 0.8, respectively. The simulation waveforms shown in Figure 4-14

are well consistent with theoretical ones shown in Figure 4-11. When D > 0.5 , Vrec pk
is almost clamped to V0 as expected because the current in L1]: is not sufficient to charge

snubber capacitors, Cs] and C52.

63

 

Guano

 

  

 

 

 

 

 

 

 

 

W115)
10.113)
Transformer secondary current —
; 10.110)
100.01 ---------- &' - u' $A$m§l~;$. ‘ ' ___"
2 o 0
Output current
00. ........... j ................. j ........
001(8)
1200.0
1000.0
800.01» - -
600.0.
2
400.01
200.0.
0.0-
.2000 '
0.13375 013376 0.13377

1(a)

 

 

 

Figure 4-14 Simulation waveforms of proposed ERCC when D=O.483

 

 

 

mpno
1mm
’°°° ' ' ' ' I
Transformer secondary current - -—-1
I ' ' 1mm
1W0 ................... 1m---‘——.-..._‘z---._.--.

 

 

 

 

 

 

0 i 1(3)

 

 

 

 

 

 

 

Figure 4—1 5 Simulation waveforms of proposed ERCC when D=0.8

64

 

 

 

*7 ”0171511“ 1‘ l

......... Vrecpk =1100V Vrec [ZOOV/div]..

 

.................................................................................................

..................................................................................................

 

...........................................

 

 

 

 

Figure 4-16 Experimental waveforms measured without calmp circuit

 

:<< MornJlOk f):

...................................................................................................

---------------------------------------------------------------------------------------------------
.....

V,¢[200V/diV]""i ......... ....... Vrec.pk =500V--

. . .
. . . . .
.x . - . ‘1. t.
. . . . 1. - r .
........... .. .,.0 ..........~ t
I ' li- ' . ‘1. .l :h..- - ' I In.
, ‘ ‘- 1 "1 . “1,. . .... . 1:1 ‘
a ." . ,f‘ l n'
. I
.

'.' -Pu‘ a.“ -1qu M ' ‘94-!

1' ’

.‘l ' 'v

v . | )

.z I. I

- 5- 1- 0

t I O

.....-.............~u.-.-...I.-.a...o.-..--.-.oqovvu-..~o§-..-.1.- ...............................

.i-n...*.."_.'__._ _g..‘o‘.¢--u—.._.......’p{(l§n‘q,d;,...',‘_‘..‘...~¢- ”.2... .fl‘!‘rW-: uuuuuuu 51-

 

 

[20 ps } div]

 

Figure 4-17 Experimental waveforms measured with proposed ERCC

Figure 4-16 shows Vrec measured without clamp circuit under the test conditions of
Vin = 328 V, V0 =374Vand P0 =14kW . Without the clamp circuit, Vrec_ pk was
increased to 1100 V when transformer secondary voltage Vsec was 328x (7 / 6) z 383 V .

was almost 2.9 times that of V because the reverse recovery currents of the

38C

Vrec _ pk

rectifier diodes contribute significantly to this voltage overshoot.

65

Figure 4-17 shows V,“ measured with the proposed ERCC under the same test
conditions above. As shown in Figure 4-17, V,“ pk was well clamped to almost 1.3
times that of Vm with the proposed ERCC.

ransforrner ' current
[200 A/div]

Vm [500V/div]

[10 ,us / div]

 

Figure 4-18 Experimental waveforms with proposed ERCC when D=O.483

Transformer primary current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

........... f)...” 200 A/le
" ‘ V/ a [a 5 ]
Vrec.pk =1000V free [500V/:div]
' ' t r__ 1:71" E
............. 1. ”flvM/VAMM ..
_ r .........
[500 ns/div]

 

 

 

 

Figure 4-19 Zoom-in waveforms of Figure 4-18

66

Transformer primary current
[200 A/div]

V0 [500V / div] Vm [500V/div]

[10 ps / div]

 

Figure 4-20 Experimental waveforms using proposed ERCC when D=0.8

 

'2 TWINE-$1 1);

' Transformer primary current,

"""" fl / [200 A/div] """"

/ '1." v‘v '—'

 

 

 

 

 

 

 

 

V0[500V/div] ? 5
- .Vrec[500V/dw] ........

y» ......... I

 

 

 

 

 

 

 

[500 ns / div]

 

 

 

 

 

 

 

Figure 4-21 Zoom-in waveforms of Figure 4-20

Figure 4-18 shows the experimental waveforms of the transformer primary current

and Vrec using the proposed ERCC under the worst case conditions of

Vin 2 666 V, V0 = 750V, D =0.483 and P0 = 70kW. Due to the physical layout of the

secondary busbar, transformer primary current is measured instead of secondary. Figure

67

 

—

:21

4-19 shows the expanded waveforms of Figure 4-18. Vm_ pk is effectively clamped to

almost 1000 V . The current and voltage waveforms in Figure 4—19 are compatible to
those of theoretical waveforms shown in Figure 4—11 and simulation waveforms shown in
Figure 4-14.

Figure 4-20 shows the experimental waveforms of transformer primary current and

V

rec

using the proposed ERCC under the test conditions of
Vin =400V, V0 =750V, D=0.8 and Po =70kW . Vrec_pk is almost clamped to V0 as

expected and is close to the simulation results shown in Figure 4-15
Figure 4-22 and Figure 4-23 shows the zoom in waveforms of transformer primary

current and Vrec when Vin = 600 V, V0 = 670 V, D = 0.48 and B, = 50kW to compare the

performance of the proposed ERCC with ERCC #1. V,

ec_p

kwas decreased from 1060 V
to 850V with the proposed ERCC which is almost 30 % reduction in Vrec_ pk . In addition
to voltage reduction in Vrec_ pk , the proposed ERCC has lower transformer peak current

than the ERCC #1. This is because snubber capacitors C51 and C32 in the proposed

. . V . .
ERCC start chargrng when Vrec reaches V0 1nstead of. 30—. Therefore, 1t wrll decrease

conduction loss in transformer and IGBT which results in improved system efficiency
(see Figure 4-25).

Figure 4-24 shows the measured Vrec_ pk as Cs] (or C32) changes from 10 nF to

600 nF under the test conditions of Vin = 450 V, V0 = 510V and 10 = 55A . The

measured Vrec pk is compared with the theoretical results plotted using (4.11).

68

 

 

 

1 k 2:460:21 mg...» Transformer primary
----- current [200 A/div]

V“ P". =1060V y

    
     

o o
............................................................

 

 

"w; ......... ..... ......... ........ ......... ......... g ...................
[500nS/div]

 

Figure 4-22 Experimental waveforms of ERCC #1

 

A : 211M1r923“. ‘1’;
_ 390A . . ‘

""""" pic-1111b") . Transfomier primary current
/ [200 A/div]

 

 

 

[5 00 nS / div]

Figure 4-23 Proposed ERCC

The measured Vrec pk is very close to the theoretical value. Vec _pk is inversely

proportional to snubber capacitance C51 In this work, a 100 nF capacitor is selected for

C31 and C 2 because a larger than necessary capacitor will increase current 1n the

transformer and IGBT. Therefore, converter efficiency will be decreased

69

 

Figure 4-25 shows the measured efficiency of dc-dc converter using the proposed
RCC and is compared with the efficiency measured with ERCC #1. Efficiency of the

proposed converter was almost the same as ERCC #1 when Kn is low and slightly

improved as Vin towards maximum value as expected. In the test, a digital power meter

(YOKOGAWA, W'I'1600) was used to measure the input and output power and the

output power was 50 kW.

 

 

 

 

  

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1200 ---;— i i i
5 3 Calculation
1100 “‘ ——-— Measurement ”‘
E 1000
"S. .
6 900
k2 1
800
700
600
0.0 0.1 0.2 0.3 0.4 0.5 0.6

Csl’CSZ [#1:]

Figure 4-24 Measured and theoretical results of Vrec_ pk vs. C 31 .

97.0
96.8
96.6
96.4
96.2
96.0
95.8
95.6
95.4
95.2

95.0
300 350 400 450 500 550 600

Vin [V]

Efficiency [%]

—I— ERCC #1
——¢— Proposed ERCC

 

?

Figure 4-25 Measured efficiency at 50 kW output power.

70

 

4.4. Conclusion

In this chapter, a novel ERCC for PWM dc-dc converters for wide ranges of input
voltage is introduced. The limitations and drawbacks of previously proposed ERCCs
have been pointed out. Detailed analysis has been presented and performance of the
proposed ERCC was compared with the previously proposed ERCCs.

A 70 kW prototype dc—dc converter employing the proposed ERCC has been built
and tested to verify the principle of operation. The proposed ERCC consists of two small
capacitors and two diodes in each bridge. Neither lossy components nor additional active
switches are used to clamp diode voltage. Therefore, the efficiency and reliability of the
dc-dc converter can be improved by using the proposed ERCC. The proposed ERCC is
very promising for high voltage and high power dc-dc converters with wide ranges of

input voltage.

71

Chapter 5. Power Loss Breakdown and

Overall System Test

Figure 5-1 and Figure 5-2 show 3-D design of 70 kW dc-dc converter developed in

this work.

 

Figure 5-1 3-D design of 70 kW dc-dc converter

 

Figure 5—2 Photo of 70 kW dc-dc converter

72

5.1. Power loss breakdown

From the results of Chapter 2-4, the power loss breakdown of converter system can
be made. Following are the loss calculations in each component in the 70 kW dc-dc
converter and its associated power losses are tabulated in Table 5-1.

1. Power losses in IGBT [36]
0 Switching loss/IGBT

- Tum-on loss: 12me13 kHzx§3§=65 W

- Turn-offloss: 28mlxl3kHzx-2—3%=152 W

0 Conduction loss: vce_sa, x 13w x D = 1.5 x 220x 0.32 =106 W

0 Capacitive turn-on loss in snubber capacitor (C s , Cm ):
%(2C)(-%'3-)2f.w = %(2x15 nF)x(¥)2 x 13kHz = 12.2 W

0 Total power loss in 4 IGBT:

PIGBT =(Psw+P H”

CO" C

ap)x4 = (217 +106+12.2)x4=1341W
2. Power loss in primary snubber resistor (Rsnub)

2xR

Still

bx4=0.82x8.6x4=22W

[ms
3. Power loss in DC link capacitor
1",} x12“, =1062 x15 m0 = 169 W
4. Power loss in transformer

0 core loss: [10 W

0 copper loss: 92 W

73

 

 

0 total power loss in transformer : 202 W
5. Power loss in inductor
0 core loss: 121 W
0 copper loss: 98 W
0 total power loss : 219 W
6. Power loss in secondary rectifier diode
o conduction loss: 707 W
0 recovery loss: 68 W
0 total power loss : 775 W

7. Others: 100 W

Figure 5-3 shows loss breakdown of the 70 kW dc-dc converter. As shown in Figure
5-3, most of the power loss occurs in the IGBT and rectifier diodes. Power loss in
transformer and inductor takes significant portion as well.

It should be noted that although the power loss in transformer and inductor is smaller
than that of IGBT and rectifier diodes, their thermal resistance from inside to outside is
much greater that of IGBT and rectifier diodes. The high thermal resistance causes heat

accumulation inside transformer and inductor. As a result, it will leads to thermal
runaway and finally system failure. Thus, magnetic design in high power converter

system is very important and should not be overlooked

74

Table 5-1 Power loss breakdown in 70 kW dc—dc converter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Loss component loss
Tum-on 260 W
Switching loss 868
Tum-off 608 W
IGBT Conduction loss 424 1341 W
Capacitive turn-on loss in
49 W
snubber capacitor

Primary snubber resistance (Rsnub) loss 22 W
Power loss in ESR of DC link capacitor 169 W
Core loss I 10 W

Transformer 202
Copper loss 92 W
Core loss 121 W

Inductor 219
Copper loss 98 W
Rectifier Conduction loss 707 W

775
diode Reverse recovery loss 68 W
Others 100 W
Total 2 8 I 8 W

 

 

75

 

 

 

 

1400

 

1200 -—ii ‘

a; g

 

1000 ~—

 

 

 

 

 

 

 

 

 

4 0 ‘0 é a 0‘ 0 ct
\ 0 Q- 9 \0 ° 0
\. Q 9 0 fl 0
0 ‘\\° 0 q.
0
18 0° Q'

power loss[W]
B h
o o 8
Pi i -
a ,
_—

 

Figure 5-3 Loss breakdown of 70 kW dc-dc converter.

5.2. Overall system test

The overall system configurations are redrawn in Figure 5-4. The three 70 kW dc-dc
converter modules are connected in series at the input and in parallel at the output. In this
configuration, the duty ratio to all the converter modules connected in input-series and
output-parallel (ISOP) configuration is made common. Therefore, this configuration does
not require a dedicated input-voltage or load-current share controller. It relies on the

inherent self-correcting characteristic of the ISOP connection when the duty ratio of all

the converters is the same [37, 38].

To verify operation of the whole system, three dc-dc converter modules are
connected in series at the input and a 260 kVA inverter is connected as shown in Figure

5-4 to produce the desired 3-phase output. In this test, 1500 Vdc is applied to the input of

the dc-dc converter.

76

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t1 __
1 :1 e
H __
70 kW DC/DC Module 1
1000~ ’— 750Vdc DC/AC E
2000 Vdci __ J é: + g I Inverter 3
A r-\ '1‘ ‘3
1.. T + a
0— filter —0”§
70 kW DC/DC Module 2 "’1
b— as _—
1 :1 E
__l
70 kW DC/DC Module 3

 

 

 

Figure 5-4 Overall system configuration of 210 kW aux. power supply

Figure 5-5 shows photo of the whole system test with three 70 kW converters are

connected for a combined 210 kW.

Module #2 T .-'
'1. \ ’ '. l, .
_- (4-, Module #3

 

Figure 5-5 210 kW system test

77

 

M:--—w—- In: 6.! m

Vin _111949720 ° "'5 76.12 1+ "'"‘ lo@module#2

"n —E.l.>ll9.35 1 .... 76.07 14--— Io@module#3
v0 —n>0.7497 w H 5935 1*
lo©nodule #1 —n> 75.99 1 R 56.97 N

Am.

 

Pin
Po

  

 

 

 

 

Figure 5-6 Power meter measurement of overall system test

Module #1,#2, #3
[200 Aldiv]

     

 

 

 

Figure 5-7 Transformer primary current of three DC-DC converter module.

Figure 5-6 shows the power meter measurement of the system test. The output power
drawn from each dc-dc converter module is almost 57 kW, thus 57 kWX3=l7I kW is

drawn from dc-dc converter and output of the converter is maintained at 750 V. The three

78

output currents of the dc~dc converter module are quite well balanced as expected. Due to
the isolation voltage limitation of the power meter, three input voltages of the DC-DC
converter were not monitored. Instead, a multi-meter is used to monitor these voltages.
The three input voltages of the DC-DC converter were also well balanced. Figure 5-7

shows the transformer primary current of each converter module measured during the

system test.

5.3. Conclusion

In this chapter, a power loss breakdown is performed and its losses are compared.
Three dc-dc converter modules are connected to test the whole system operation. The
input voltage of dc—dc converters are connected in series and the output currents are

connected in parallel. Due to the active voltage balancing and current sharing of the

system, the system operation was performed successfully.

79

Chapter 6. Integrated Magnetics for
Interleaved Boost DC-DC Converter for
Series Hybrid Electric Bus

6.1. Introduction

In order to reduce C02 emission and to increase fuel efficiency of vehicles, electric
vehicles (EVs), hybrid electric vehicles (HEVS), plug-in hybrid electric vehicles
(PI-IEVs), and fuel-cell electric vehicles (FCEV) are now in increasing demand [39].

Figure 6-1 shows the overall system configuration of a series hybrid electric bus
(SHEB). Mechanical energy from the diesel engine is first converted to electrical energy
by the generator and this energy is used to drive motors through traction inverters.

Traction
Generator Motor

   

 
  
  
 

Diesel Engine

' 7500 O

      
  
    
 

Traction
Inverter

  

Inverter

Traction

Battery Inverter

Traction
Motor

Figure 6-1 Overall system configuration of series hybrid electric bus

80

 

To maximize engine (fuel) efficiency, a battery is coupled to the dc link of the
traction inverters through a bi-directional dc-dc boost converter. The dc-dc converter
supplies battery energy to traction motors to meet the high power demand of traction
motors during startup or acceleration and it delivers regenerated braking energy from the
traction motors to the battery.

Table 6-1 shows electrical specifications of the battery and boost dc-dc converter
considered in this work. Typically, dc-dc converters in HEV systems should handle both
average and peak power demand. Therefore, the dc-dc converter in the HEV system plays
an important role to maximize fuel efficiency. However, the dominant part of the boost
converter, both in terms of size and cost, belongs to the magnetic components.
Consequently, better use of the magnetic content of the dc-dc converter may lead to

substantial performance and cost improvements.

Table 6-1 Electrical Specifications of battery and boost dc-dc converter.

 

0 Voltage range: 240 — 340 VDC

 

Battery
0 Maximum current: 500 A
0 Average power: 30 kW
0 Peak power: 120 kW
DC-DC
0 Input voltage: 240 — 340 VDC
converter

0 Output voltage: 600-700 VDC

0 Switching frequency: 15 kHz

 

 

 

 

81

 

 

 

For the SHEB system considered in this work, a 3-phase interleaved boost converter
(IBC) is considered and its schematics are shown in Figure 6—2. A 3-phase topology is
chosen in order to meet the high power demand of the system and a standard six-pack
IGBT module is used for this.

As already well known, the input (battery) current and output voltage ripple of IBC
can be minimized by virtue of an interleaving operation [40—43]. Moreover, the converter
input current can be shared among the phases, which is desirable for heat dissipation.
Therefore, the converter reliability and efficiency can be improved significantly.

In this chapter, a very detailed design procedure for the integrated magnetic (IM) is
presented and efforts are made to minimize core and winding loss of the IM. The input
and inductor current ripples of IM are calculated theoretically and compared with
measurements to verify the design of the IM. A 30 kW average and 120 kW peak power

prototype IBC is built for the SHEB system and tested.

 

1:?
\I
ll
:5:

 

 

 

 

 

 

 

 

4.31.: IHiJ

Figure 6-2 A 3-Phase interleaved boost converter

82

 

 

6.2. Interleaved Boost Converter and Integrated Magnetics
6.2.1 Review of Interleaved Boost Converter.

As already well known, the relationship between input current ripple (Aim) and

inductor current ripple (AIL_d,-s) in a multi-phase IBC is expressed as [40], [44].

AI in = f (D)AIL.dis (8.1)

,where A1 L .dis is the current ripple of a discrete (or non-coupled) per-phase inductor,
Ldis- The generalized equation for f (D) for multi phase IBC is shown in (6.2). The

derivation of f (D) is out of the scope of this chapter and it is well explain in [40].

 

Non+l—ND _yfl
f(D)—( 1_D )[1 ND) (6.2)

,where N is the number of phase and N0" is the number of switches that are always in

the ON state during the sub-period, r = %.

Table 6-2 summarizes f (D) derived for several values of N. From Table 6-2, the

input current ripple normalized with respect to the inductor current ripple can be plotted
for several multiphase IBC and the results are shown in Figure 6-3.

With the help of the interleaving effect, the input current ripple can be reduced
significantly and the current interleaving effect becomes better as N increases. The effect
of interleaving on the input current of 3 phase IBC, for example, is depicted in Figure 6-4,

Figure 6—5 and Figure 6-6 for each converter duty cycle range.

83

Table 6-2 Calculation of f (D) for N=2, 3 and 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N=2
l l
OSDS— —SDSI
2 2
Non 0 1
l—2D 2D—l
D ___—- ___.
fl ) l—D D
N=3
OSDSl lSD_<_Z -2-SD_<_1
3 3 3 3
Non 0 l 2
l—3D 2-3D 1 3D—2
— 1—11-4 —
l—D l—D 3D D
N=4
OSDSl lSDS-z- ESDSE *3-SDSI
4 4 4 4 4 4
No,, 0 l 2 3
_ 2-4D 1 3—41) 1 _
f(D) —‘ 4” (1-1;)(‘75M‘1—5X‘E) —-‘”’ 3
1—D D

 

 

 

 

 

84

 

 

 

Normalized input current ripple

 

 

 

 

 

mag: “cmtzo

0.8

0.6

Duty cycle

0.4

0.2

 

 

Figure 6-3 Normalized input current ripple of IBC

 

 

 

 

 

 

 

 

 

 

 

 

TSTJ-Vll ILll

 

 

 

 

 

Figure 6-4 Inductor current interleaving when 0 < D <1/3.
85

l

k

v'I'-

 

 

 

v""

 

 

 

l
r
I
I

1L3

e261.-

 

r'll'

 

 

 

 

 

 

 

 

 

 

 

 

 

TS .I-Ill 'III'- ' '1 """" II T3
2
L...
9.7+.- ..... -.l _- --. ..... #4...
.I..L
1.3-Y..-- 1:. - -- ...... 1......
T:
D
0* , _ :- /ll
1.... 1.... so rm

 

Figure 6-5 Inductor current interleaving when 1/3 < D <2/3.

III'I

 

 

 

 

v|'|'

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I
T: 1V 111111111 2 1 I. 111111 I T..
1....

Ts » T...
.._.i ...... -....- I...
7....

Ta...
1.31-1.1--- - lo 1....
$1 9.... v.6: Lm

Figure 6-6 Inductor current interleaving when 2/3 < D <1.
86

6.2.2 Integrated Magnetics

Recently, an interesting integrated magnetic (IM) structure having 3 outer legs and
one common leg using different core material for outer and common legs was introduced
in [44]. Figure 6-7, Figure 6-8, and Figure 6-9 show the core structure, winding
geometry, and the reluctance model of M, respectively. Two different core materials are
used for common leg and outer legs. The 3 phase windings are wound on each outer leg.

The RL and RC in Figure 6-9 represent the reluctance in outer and common leg,
respectively. N is the number of turns in each winding. I“, In , [13 represent the

winding current in the IM core.

' Common leg
I
Outer leg

 

. Common leg

'
-‘ Outer leg

 

Figure 6-8 IM assembled with winding

87

 

RL RL RL R

C
¢Ll ¢L2 ¢L3

¢c

 

Figure 6-9 Reluctance model of IM

'15

The common leg flux (¢C) is equal to the sum of the three outer leg fluxes (951,1, 151,2 2

d

9013) due to the IM core structure shown in Figure 6-7. In this case, the common leg flux 1...

ripple ( A¢C) can be reduced due to flux interleaving. The relationship between A¢C and

A¢L is expressed as follows.

 

1—31) 1
——A ,ost—
(l-D) ¢L 3
2-3D l l 2
A = DA = —— 1-—A ,—st— 6.3
.. f... (,_,)( 3,). 3 3 ..
3D—2 2
—A ,—stl
. i D i” 3

where, D is duty cycle of the converter.
From (6.1) and (6.3), one can notice that the relationship between A¢C and A¢L in
(6.3) is exactly the same as the relationship between A1)” and A1 L.dis in (6.1) because

they are governed by the same principle called interleaving. The only difference is the
object of interleaving. The former (Eq. (6.1)) is current and the latter (Eq. (6.3)) is flux.
Therefore, the flux ripple waveforms in IM can be similarly represented as the current

waveforms in Figure 6-4, Figure 6-5 and Figure 6-6 . From the reluctance model in

88

gure 6-9, the outer leg fluxes and the winding currents in the IM core are related by

4]
1L1 1 RL + Rc Re Rc 451.1
11.2 = W Re R1. + Re Rc ¢L2 (6-4)
I L3 Rc Rc RL + Rc ¢L3

Therefore, the inductor current ripple is expressed as

41.. = $113.40. +RCA¢.) (6.5)

It should be noted in (6.5) that the inductor current ripple is related to both outer leg
and common leg flux ripple through the multiplication of reluctance values. However, the
common leg flux ripple is relatively small compared with outer leg flux ripple due to the

flux interleaving. Therefore, by making RCA¢C term dominant in (6.5) A1 U can be
reduced significantly. In other words, RC should be bigger than R L .
In Figure 6-2 1- is the sum of the three inductor currents. Thus, the relationship

2":

between A1)" and A¢C is found from (6.4) as

' _ RL + 3RC
A1m ‘( N JA¢C (6'6)
MC in (6.6) is expressed as

13¢. =f(D)A¢L =f(D)[Q;VD—5] (6.7)

The discrete per-phase inductance Ldl-S is

89

V..DT.

Ld' = (6.8)
Is A[Ldis
Therefore, from (6.1), (6.6), (6.7) and (6.8), Ldis can be derived as
N2
Ldis = “___ (69)
RL + 3RC

In this work, Ldis is chosen to have the same flux ripple (waveform) in both non-

integrated inductor and IM implementation.

The relationship between A1 L and AILdis can be determined from the above

equations as

 

1+%-I(D) 1.__f(D)
A] L = L AILdi-s = _i— AILdis (6'10)
R, 3
1+3— 1+—
RL k

From (6.10), one can notice that the inductor current ripple of IM (A1 L ) is related to
AILdis by the ratio of RL to RC , which is defined as k in this work.
By using (6.1) and (6.10), A1," and A1 L normalized with respect to AILdis are

plotted in Figure 6-10 as a firnction of D for several values of k. As shown in Figure

6-10, AI," (dotted line) was reduced significantly by the effect of interleaving and A1 L is

strongly related to k. Therefore, k should be kept low to reduce A1 L .

90

 

 

Current ripple
O
.5

 

 

 

 

 

 

 

Figure 6-10 Normalized current ripple as a function of D for several values of k.

6.3. Design of High Efficient and High Density Integrated
Magnetics

The previously proposed scheme shown in Figure 6-7 used ferrite core for outer leg
and powdered iron core for the common leg in order to maintain low values of k because
the permeability of ferrite core is several hundred times bigger than that of powdered iron
core. Therefore, inductor current ripple in IM can be reduced significantly. In addition to
this, core loss in the outer legs can be minimized by using ferrite core.

Although the core loss of powdered iron core used for common leg is typically
higher than ferrite, the core loss in the common leg in this structure, however, can also be
minimized because A¢C is reduced significantly through flux interleaving. As a
consequence, the IM showed good performance, low total core loss, and minimized

inductor size.

91

 

However, there are some limitations of using ferrite core in high current and high
temperature applications such as HEVs, EVs, and PHEVs for the following reasons.

First, the peak power of dc-dc converters used in HEVs or EVs is usually 3-5 times
greater than the average power of dc-dc converter to meet the high power demand of
traction motors during startup and acceleration (see Table 6-1). Thus, the maximum
inductor current is greater than nominal inductor current by the same amount as power. In
this condition, inductor design using ferrite core is very difficult because the maximum

flux density (Bmam ) of ferrite core is usually low (z0.4-0.45 T) when compared with that

of distributed airgap cores such as MPP, high flux, mega flux, etc [16], [45].

Secondly, the Bmax of fenite cores usually decreases as core temperature increases.

The result is earlier saturation of the core than designed when ambient temperature is
high.
In order to be applicable to high current and high temperature systems, the core

Bmax should be high enough and be kept fairly constant even at elevated core

temperature.

Table 6-3 compares the key properties of several magnetic powder cores considered
in this work and they are compared with ferrite core [25]. From the results of Table 6-3,
the “high flux” core is selected for core material for both outer and common leg in this
work because it has low core loss, high saturation flux density, and good temperature
stability. The core loss of “high flux”, however, is normally higher than that of ferrite.
This will increase core loss and temperature in outer legs and eventually decreases

converter efficiency.

92

Table 6-3 Basic Material Characteristics

 

 

 

 

 

 

Saturation
Core Core Permeability Temperature
Cost Flux density
materials loss vs. DC bias stability
(Gauss)
MPP Lowest Better High 7,000 Best
High flux Low Best Medium 15,000 Better
Iron Highest Poor Lowest 10,000 Poor
Amorphous
Medium Better Highest 15,000 Poor
(gapped)
Ferrite
Lowest Poor Low 4,500 Poor
(gapped)

 

 

 

 

 

 

 

 

* 1 Tesla=104 Gauss

However, there are several ways of minimizing core loss in the outer legs. 1)
Increase number of turns to reduce flux swing of core, but it will increase winding loss of
inductor. 2) Reduce core volume because core loss is directly proportional to core
volume. However, the core cross-sectional area should not be reduced. Otherwise, the
flux swing will increase and result in higher core loss.

In this work, the height of IM is reduced as much as possible while maintaining same
outer leg core cross-sectional area for the following reasons: 1) Core loss in the outer leg

is the dominant loss factor because the flux in this leg is not interleaved. Thus, one can

93

reduce outer leg core loss with minimized core height. 2) Thermal resistance from the
inside of the core to the outside can be decreased with this flat inductor approach, which
is good for heat dissipation.

However, 3mx of the core increases as core height decreases because the airgap in

powder (or distributed airgap) core is also reduced when core height decreases. The result
is that the magnetic core is more susceptible to core saturation [16].

In this work, however, the core saturation problem caused by reduced core height
can be resolved by using “high flux” core that has high saturation flux density (see Table
6-3). In addition to that, the core saturation problem in the outer leg can be mitigated by

using low permeability core material for the common leg because it will decrease Bm,Ix
of the outer leg core. Therefore, Bmax of the outer and common leg core can be

controlled to a reasonable number by the optimal combination of outer leg and common
leg core structure and selection of core permeability. This will be explained later in this
section.

Figure 6-11 and Figure 6-12 show the core structure of the flat IM designed in this
work. In this work, the magnetic core surrounded by inductor winding is defined as outer
leg and the rest of them are defined as common leg.

The reluctance RL and RC are calculated by using the following equation as [16]

R-L" (mu

_mmS

 

where, I”, is the magnetic path length of IM, pa = 47rx10—7 is the permeability in air,

,u, is the relative permeability of “high flux” core and S is the core cross-sectional area.

94

However, permeability of the distributed airgap core rolls off as the DC magnetizing

force (H [0e]) increases [25].

 

 

180 mm

. Outer leg (4011 high flux)
@ Common leg (26p high flux)

Figure 6-11 Proposed flat IM. (Front View)

130 mm ,30 mm

5 1 H

  
  

 

70 mm

 

 

 

  

l 90 mm .
<—> Outer leg magnetic path length
41-) Common leg magnetic path length

 

Figure 6—12 Proposed flat IM. (Side view)

95

 

 

 

 

 

 

 

 

3.411.;-
0 co 5} ., .
/6 permeab/IIO/ vs H curve .,
Block Cores DOB!” MW WV»;
100 .fi.--”.....,.........,-........,.... '
90~ [ ——CKBlockCone40u] ~
wd ‘ I
J
70.. .-
5‘ eo- ~
' a
‘3 50- -
E ..
as 30: .
20L
.0. . .._ .
d I 1 4
0 frfrrrrrri""r"f'r'fr'I'rr'rr'"r"'*
o so 100 15o zoo zoo 300 350 400
WmForeflOe]

 

 

Figure 6-13 % permeability vs. H curve of Changsung 40|J block core

Figure 6-13 shows one example of this characteristic. Thus, care must be taken when
designing inductors with distributed airgap cores.

H is calculated by using Ampere’s law as follows and its unit is oersteds.

 

_ 0.47.1111

H [De] (6.12)

m

In (6.12), I is the DC current that flows through the inductor and [m is the magnetic

path length in cm. Detailed parameters for calculating reluctances are summarized in
Table 6-4. In Table 6-4, the core cross-sectional area for the common leg is calculated

separately because of its structure. (see Figure 6-11 and Figure 6-12). Therefore, the RC
is also calculated individually and they are added together to make total RC. The %

permeability of “high flux” core is obtained from the manufacturer datasheet.

96

Table 6—4 Parameters of IM core

 

 

 

 

 

 

 

 

 

 

 

 

Outer leg (4011) Common leg (26p)
Top and Bottom piece:
_ 2
Core cross- 30 30:900 2 180><20—3600 rmn
x mm . . . _
sectional area (S) Mlddlle prece.
l80><30=5400 mmz
Magnetic path
10+10+30=50 mm 60+60+50=170 mm
length (1",)
H@40A 0.4x7rx28x40=281[oe] 0.4x7rlx728x40z83[0e]
% permeability 50 96
V. @40 A 40x0.5=20 26x0.96=24.96
Reluctance 2687952 1358625
R
k =_L. k = 2687952 =l.978
RC 1358625

 

 

 

 

In this work, I is set to 40 A, which is the nominal DC current at 30 kW average
power. If I is known, H can be determined from (6.12). Therefore, the permeability at
this point is determined from the % permeability curve and they are shown in Table 6-4

as 50 % and 96 % for outer leg and common leg core, respectively.

With the parameters in Table 6-4, the RL and RC can be calculated by using (6.11)

and the results are also shown in Table 6-4.

97

In order to verify the reluctance values calculated in Table 6-4, a square wave
voltage is applied to the winding of outer leg 2, and the windings in outer leg I and 3 are

left open-circuited. Figure 6-14 shows the modified reluctance model with this condition.

 

 

RL =2 RL R1,; R. ; ¢L2
> R R +3R
2 - 1 RL + 211,
NiLz

 

 

 

 

 

 

 

 

Figure 6-14 Modified reluctance model when a voltage is applied to only outer leg 2.

When the windings are left open-circuited, the mmfs in those windings become zero
because there is no current that flows in those windings. Therefore, the mmfs in winding
1 and 3 are short-circuited as shown in Figure 6-14 and the circuit is simplified to one
mmf and one reluctance value.

From Figure 6-14, the inductance in leg 2 is calculated as follows

N2 (RL+2RC) =233..H (6.13)

L 1:404 =
(@ ) RL(RL +3RC)

The inductances in leg I and leg 3 can be calculated with similar method and they
should be the same as the inductance in leg 2 if they experience the same flux path.

In order to confirm the calculated inductance value in (6.13), a square wave voltage
is applied in each winding one by one and the corresponding inductances are measured.
Figure 6-15 shows the inductances in each leg measured by increasing applied current.

As we expected, the inductance drops as current increases.

98

Inductance Measurement of Flat IM

Inductance [uH]

 

0 20 40 60 80 100 120 140 160 180
Current [A]

Figure 6-15 Inductance measurement of TM
The measured and calculated inductances are shown in Table 6-5 for comparison.

Table 6-5 Measured inductances of flat IM at 40 A

 

Calculation Measurement

 

 

 

L1, (Leg 2,3 open) 233 ,uH 186 #H
Inductance @ 40 A L2, (Leg 1,3 open) 233/1H 224 yH
L3, (Leg 1,2 open) 233 pH 180 ,uH

 

 

 

 

 

 

99

From the results of Table 6-5, the measured inductance is smaller than the calculated
ones. This is caused by the unwanted airgap that inserted between block cores when they
are glued together. In addition to that, the three measured inductances are not the same
because the magnetic path length of each leg is different. For example, the magnetic path
length in leg 2 is shorter than that of leg 1 and 3. Therefore, leg 2 has greater inductance
than leg 1 and leg 3.

With the reluctance values calculated in Table 6-5, the inductance value of a non-
coupled inductor can be calculated by using (6.9) as follows

N2

=—————z116 H 6.14
RL+3RC rt ( )

Ldis

The dc-dc converter discussed in this paper should operate at 120 kW peak power
during startup and acceleration and the battery (or input) current is 500 A at this
condition. Therefore, the maximum inductor current (ILmax) becomes 500 A/3=167 A.
The magnetic cores used in IM should not be saturated at this harsh condition. Maximum

flux density in the outer leg (BLmax) and common leg (BCmax) are calculated using the

following equations as

 

31...... = Nx'L-max e0.69T (6.15)
51.09. +3Rc)
30m, :22: 39 = 3Nx’L-"fl—e052T (6.16)

 

SC SC SC(RL+3RC)

100

where, S L and SC are the core cross-sectional area of the outer leg and common leg,

respectively. From (6.15) and (6.16), the maximum flux density of both outer and

common leg is well below “high flux” core saturation flux density which is 1.5 T.

6.4. Experimental Results

A 30 kW average and 120 kW peak power IBC using TM is built and tested. Figure
6-16 shows the experimental waveforms of the dc-dc converter with the test conditions of

Vin=300 V, Vo=600 V, D=0.5, fsw=15 kHz and Po=37 kW.

Current ripple of the non-coupled inductor, AILdis , at this condition can be

calculated as

VinxD _ 300x05 ~
Ldisxfsw 116pHx15kHz

 

 

86A (6.17)

Therefore, AI," and AIL of IM are calculated by using (6.1), (6.10) and the k value in

Table 6-4 as
N in = f (0)131 L.dis z 29 A (6.18)
H f(D)
1+ I

The measured current ripples of TM in Figure 6-16 are close to the calculated current
ripple in (6.18) and (6.19).
The current ripple in outer leg 1 (A1“) is bigger than that of leg 2 (Mn) because

the inductance of leg 1 is smaller than leg 2 (see Table 6-5).

101

[50 A/div]

1L2 [

Vce2 [500 V/ div]

 

[20 ps/div]

Figure 6—16 Experimental waveforms of IBC using IM when D=0.5.

: 11.. [50 A/div]

Vce2 [500 V/diV]

 

[20 |JS/le]

Figure 6-17 Experimental waveforms of IBC using IM when D=2/3.

102

Figure 6-17 shows the experimental waveforms of IIVI when Vin=200 V, Vo=600 V,

D=2/3, fsw=15 kHz and Po=37 kW. From the curves shown in Figure 6-10, AI,” when

D=2/3 is ideally zero and AIL is calculated as

1+f(D)
k 1
A1]. = —3— AILdis = ——3' AILdis ”304 (620)
1+- 1+—
k k

The experimental waveforms are also close to theoretical analysis.

Figure 6—18 and Figure 6-19 show the inductor and input current waveforms when
Vin=300 V, Vo=600 V, D=0.5, fsw=15 kHz and Po=120 kW. At this peak power
condition, the input and inductor current are 500 A and 167 A, respectively. When
compared with 30 kW average power, the input and inductor current increase to 4 times.
The increased currents cause more roll-off in core permeability. As a consequence,
inductance drops and current ripple increases.

Figure 6-20 shows a photo of the prototype IM developed in this work. In order to
protect the inductor from mechanical vibration and other stresses, the IM is molded in an
aluminum case and the final assembly is shown in Figure 6-21. An added benefit of the
molded inductor is better heat dissipation than an air cooled inductor.

In order to calculate the core loss in both outer and common leg, a peak-to-peak flux
swing of the core is calculated. Table 6-6 summarizes detailed parameters of the IM and
calculated core and winding loss of the IM.

To confirm the calculated power loss in Table 6-6, internal temperature of the IM is
measured. Figure 6-22 shows the measured temperature increase under the test condition

of Vin=330 V, Vo=660 V, D=0.5, fsw=15 kHz and Po=33 kW. Afier 1 hour and 40

103

minutes of operation at 60 °C ambient temperature, the internal temperature was almost

saturated to 93 °C.

 

2<< Horr‘GlOk >> I

 

  

 

Vce2 1200 v/div1

ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

 

 

 

 

 

 

[20 us/div]

 

ISA‘

Figure 6-18 Inductor current and IGBT switching waveforms at 120 kW.

 

I(\ Hamill” >2 1

 

 

 

 

 

 

[.20 115/div]

 

 

 

Figure 6-19 Input current and IGBT switching waveforms at 120 kW.

104

 

Figure 6-20. Photo of prototype IM before molding.

 

Figure 6-21 Photo of molded IM after molding

105

Table 6-6 Calculation of power losses in IM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 Thickness: 0.533 mm
. _ 0 Width: 25.4 mm
Copper wmdmg
0 Mean length/turn: 188 mm
o No. of turns: 28
Total winding loss @ 40 A 44 W
Outer leg 0. 4 T
Flux swing
Common leg 0.03 T
Outer leg 25 W
Core loss 33 W
Common leg 8 W
Total power loss in IM 77 W
100
i n u
90
SE 80
o
g 70
E
8. 60
as) .
I- 50
.1
40 '
o V20 40160.80 100

Time [minute]

Figure 6-22 Temperature increase of IM

106

 

 

6.5. Conclusion

In this chapter, a very detailed design procedure, for designing high efficient and
high density 1M for 3-phase interleaved boost dc-dc converter for series hybrid electric
bus, is presented. A flat IM is designed to reduce core loss in the outer leg. Theoretical
calculation of inductor and input current ripples are compared with experimental
waveforms to verify the performance of IM. A 30 kW average and 120 kW peak power

IBC was built and successfially tested to verify the operation of IM.

107

Chapter 7. Distributed Z-Source Network
DC-DC Converter

7.1. Introduction

As already mentioned and pointed out in Chapter 1, traditional transformer isolated
dc-dc power conversion circuits are based on either a voltage-source (V-source) or
current-source (I-source) structure. A V-source converter is fed from a power source with
relatively constant voltage that is generally supported with capacitors (Figure 7-1) and an
I-source converter is fed from a power source with relatively constant current that is
generally smoothed through an inductor (Figure 7-2) [46]. The V-source FB converter
shown in Figure 7-1 has the following limitations [1], [46].

o The output voltage of converter is always lower than input voltage. In other
words, the input voltage has to be greater than output voltage.

0 The upper and lower devices of each phase leg cannot be gated on
simultaneously either by purpose or by EMI noise. Otherwise, a shoot-through
would occur and destroy the devices. The shoot-through problem by
electromagnetic interference (EMI) noise’s misgating-on is a major killer to the
converter’s reliability.

0 The voltage overshoot problem in secondary rectifier diodes is severe [27], [9],
[47]. Therefore, a voltage snubber (or clamp) circuit is required to limit voltage
overshoot in rectifier diodes. The added circuitry, however, may decrease

converter efficiency and system reliability.

108

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SI} S2) le N1 2N2 ’ Dl D2
Vin t Caz: $121,
S3/1 541' ilSDB TD4
.1, =1} .11.}
Figure 7-1 V-source FB PWM DC/DC converter.
Lin
S } s‘J LII: N:N 211’1J‘132
l 2 l 2
O O i >
Vin :- C 0:: 3R1,
s3 «31 S4 /| {03 71504

 

 

 

 

 

 

Figure 7-2 I-source FB PWM DC/DC converter.

Likewise, the I-source FB converter shown in Figure 7-2 has the following limitations.
° Output voltage of the converter is always greater than input voltage. In other
words, the input voltage has to be smaller than output voltage.

At least one of the upper devices and one of the lower devices have to be gated on

and maintained on at any time. Otherwise, an open circuit of the dc inductor

109

would occur and destroy the devices. The open-circuit problem by EMI noise’s
misgating-off is a major concern of the converter’s reliability.

0 The voltage overshoot problem in primary switches (SI-S4) is also a big concern

[48-51].

From the aforementioned reasons, the two traditional circuits shown in Figure 7-1
and Figure 7-2 can only produce output voltage smaller than or greater than input
voltage. Therefore, there is only buck (step down) or boost (step up) function in
conventional bridge-type converters and they do not have both the buck and boost

function.

 

 

V—source type ~ l-source type

Figure 7-3 The effect of EMI or misgating on switching device.

Figure 7-3 summarizes the effect of EMI noise or misgating on/off on switching
devices. The left circut in Figure 7-3 shows the switch failure mechanism of V-source
type converter system where upper and lower devices of each phase leg are connected in
series with source. When there is a misgating-on in the gate signal, the phase leg is short-
circuited and the input capacitor will be discharged through the phase leg. Therefore, the

switching devices in the phase leg would be damaged by over current.

110

Similarly, when there is a misgating-off in the gate signal of an I-source type
converter system shown in the right of Figure 7-3, the energy stored in the input inductor
will be transferred to the junction capacitance of the switching devices. Therefore, the
switching devices in the phase leg would be damaged by over voltage. From the reasons
mentioned above, the conventional V-source or I-source converters are very vulnerable to

EMI noise. As a result, system reliability of these converters is greatly impaired.

7.2. Why buck-boost converter?

In section 7.1, it is mentioned that the conventional dc-dc converters have only buck
or boost function and they do not have the desired buck and boost fimction. In this
section, a buck-boost converter is examined and its main advantages over buck (or boost)
converter will be addressed. Figure 7-4 and Figure 7-5 show the two very basic converter

t0pologies used in power electronics; buck converter and boost converter.

 

 

 

 

Figure 7-5 Boost converter

lll

Figure 7-6 depicts the input and output voltage relationships of the buck, boost and
buck-boost converter. For the buck converter, the output voltage is always equal or
smaller than minimum input voltage. For the boost converter, the output voltage is
always equal or greater than maximum input voltage. For the buck-boost converter,

however, the output voltage lies in between the input voltage range of the converter.

W

Boost converter 1 V

 

o_boost
Vin_max ""_— <
V Buck-Boost > V
x . converter o_buck_boost
Vim. ‘ <.

Buck converter * V0_buck

 

 

0V1

Figure 7-6 Input and output voltage range of buck, boost and buck-boost converter

>

Buck-Boost converter

Efficiency

 

converter BUCK
converter

 

 

 

 

> V-

m

 

Vin_min Vx Vin_max

Figure 7-7 Efficiency profile of buck, boost and buck—boost converter

112

Figure 7-7 shows an efficiency map of the buck, boost and buck-boost converter as
converter input voltage varies within its minimum and maximum value.

Generally speaking, efficiency of the power electronics converter becomes
maximum when the input and output voltage difference is minimum. For example,
efficiency of the buck converter shown in Figure 7-4 reaches maximum value when the
input voltage is equal to output voltage, i.e., when duty cycle is one. This means that the
switch (S) is always turned on to transfer energy to the load. With this condition, there is
minimum power loss in the switching device and freewheeling diode (D), and minimum
core and winding loss in the inductor. Therefore, the efficiency would be maximum at
this condition.

As input voltage increases, D decreases to regulate the same output voltage. In this
case, power loss in the switch and diode increases because its RMS current increases. In
addition to that, core and winding loss of the inductor increases because the flux swing of
the inductor increases. As a consequence, the converter efficiency will decrease. The
same explanation can be applied to the boost converter.

Unlike the buck converter or boost converter mentioned above, output voltage of the
buck-boost converter is within the input voltage range as shown in Figure 7-6. Therefore,
the input and output voltage difference of the buck-boost converter either in buck mode
or boost mode becomes narrower than that of the buck converter and boost converter.
Therefore, the converter efficiency can be improved for the same reasons mentioned

above.

113

7.3. Literature Survey for Buck-Boost Converters

7.3.1 Non-Isolated Buck-Boost Topologies

The most basic converter in power electronics is the buck converter as show in
Figure 7-4. It is so named because it always steps down, or bucks, the input voltage. The

output of the converter is given by

V0 = 0V," (7.1)

Interchange input and output of the buck converter, we have the second basic
converter — the boost. The boost always steps up, hence its name. The output voltage is

always higher than the input voltage, and is given by

m (7.2)

 

When we need an application where we need to both step up and step down,
depending on the input and output voltage, we could use two cascaded converters — a

buck and a boost as shown in Figure 7-8.

 

Boost converter Buck converter

 

   

 

 

 

 

 

 

 

Figure 7-8 Buck and boost two stage converter

114

Unfortunately, this requires two separate controllers and switches. Moreover, the
efficiency of this topology is low because it has two stages of power conversion. The

effective power-conversion efficiency is the product of both the buck regulator’ s and
boost converter’ 5 efficiencies. Typical efficiency numbers for buck-and-boost

converters are between 90-95 % each. Therefore, the total converter efficiency would be
between 81-90%. The two separate converters increase the number of parts and increase
the size of system. An additional drawback is the additional cost associated with two

separate converters.

 

 

 

D
j. I l -
fl
Vm S L Co RL V0
1 .

 

Figure 7-9 Buck-boost converter

The buck-boost converter shown in Figure 7-9 has the desired step up and step down
functions and it can be realized with a single power conversion stage. The output voltage

is given by

V = —— V. (73)

A distinct drawback of the buck-boost converter is that its output is inverted as
illustrated in (7.3). Therefore, switch (S) and diode (D) voltage rating should be high

enough to sustain the sum of Vin and V0. The use of high voltage rating device will

115

reduce converter efficiency. This is one of the reasons why the buck-boost converter
shown in Figure 7-9 cannot achieve high efficiency in practice. Furthermore, the input
current is discontinuous because the switch is connected in series with the input voltage
source.

In order to overcome the input current discontinuity of the buck-boost converter, the
Cuk converter was invented by California Institute Professor Slobodan Cuk in 1976 [52],
[53]. This converter performs a dc conversion function similar to the buck-boost
converter and it operates via capacitive energy transfer. It can either increase or decrease
output voltage. Compared with the buck-boost converter shown in Figure 7-9, input and
output current of the Cuk converter is continuous because the two inductors in the input
and output surround the switch. However, its output voltage polarity is still inverted like

the buck-boost converter shown in Figure 7-9.

 

 

 

Figure 7-10 Cuk converter

One converter that can provide both step up and step down of the input voltage,
while maintaining the same polarity is the SEPIC (single ended primary inductor
converter) [15]. Figure 7-11 shows the SEPIC and it shares the same input and output
ground reference. Like the Cuk converter, the SEPIC uses two inductors. The SEPIC

transposes the position of the inductor and the diode so that the output voltage is positive.

116

The input current is non-pulsating because the input inductor is connected in series with
input voltage. However, the pulsating current has to charge the output capacitor.

L1 C1 D

+

'—
Vin S _J:} IQ Co RL V0

 

 

a

Figure 7-11 SEPIC converter

7.3.2 Transformer Isolated Buck-boost Topologies

The dc-dc converters shown in the previous section are all non-isolated converters.
In other words, the input and output of the converter are not electrically isolated. In many
practical dc-dc power converters, however, an electrical isolation between the input and
output port is frequently required primarily due to safety considerations. The most
common and easiest way is to insert an isolation transformer in the middle section of the
converter because transformers can transfer electrical power without any electrical
connection between primary and secondary. It transfers power through magnetic coupling.
Moreover, transformers can convert voltage and current easily by simply changing
transformer tums ratio. Thus one can get any desired voltage and current by using a
transformer.

The flyback converter depicted in Figure 7-12 is a very typical example of a
transformer isolated buck-boost converter. It is evolved from the buck-boost converter
shown in Figure 7-9 by adding an isolation transformer and simplifying the resulting

circuit. The flyback converter has a very simple structure with a minimal component

117

count, while providing desired input-to-output isolation. The flyback converter has thus
been widely used in cost-sensitive commercial applications, such as consumer electronics

and low-power home applications.

 

Figure 7-12 Flyback converter

Transformer model
D
lzn 1 $1 I +
O
CO RL V0
. 1 _

51%}

Figure 7-13 Transformer model of flyback converter

 

 

 

 

Lm

 

 

 

 

 

 

 

 

 

 

 

The transformer polarity marks are reversed to obtain a positive output voltage.
Unlike the ideal transformer, current does not flow simultaneously in both windings of
the flyback transformer [15]. Figure 7-13 illustrates the practical configuration of the

flyback transformer. Energy from the DC source is stored in magnetizing inductance Lm

when switch is on. When diode D conducts, this stored energy is transferred to the load,

118

with the inductor voltage and current scaled according to the [:71 turns ratio. Therefore,

the voltage conversion ratio of the flyback converter is

 

(7.4)

If the transformer turns ratio is 1:1, the voltage gain of flyback converter is equal to
that of buck-boost converter.

Figure 7-14 shows the isolated Cuk converter derived from the basic non-isolated
Cuk converter shown in Figure 7-10 [15]. The energy transfer capacitor in the

nonisolated Cuk converter is split into two series capacitors, C1 and C2. A transformer
can now be inserted between these capacitors because C1 and C2 ensure that no dc

voltage is applied to the transformer. The polarity marks in the transformer have been
reversed, so that a positive output voltage is obtained. Similar to the flyback converter,
the isolated Cuk converter can only be applied to low power systems requiring several

hundred watts. This is because the capacitors C1 and C2 are used as the main energy

 

 

 

transfer element.
L C
1 l
j l +
O
Vm S J V0

 

 

 

 

Figure 7-14 Isolated Cuk converter

119

In order to meet high power demand, buck and boost function and transformer
isolation, a back-to-back bi-directional dc-dc converter is introduced in several
applications [54, 55].

Figure 7-15 shows one example of such a converter. By replacing rectifier diodes
with active switches in the transformer secondary side and adjusting phase angle between
transformer primary and secondary, a desired buck-boost operation is achieved in this
topology. However, active switches are needed in the transfonner secondary side to have

buck-boost fimction. Therefore, it will increase system complexity and cost of the

 

 

 

 

 

 

 

 

 

converter.
S1} 52) L11. N1:N2 )55 } S6
Vm 1: C01: RL
5 1 s x 157 x 58
3 1 4 | l i

 

 

 

 

' v

 

 

 

2.5110sz

Figure 7-15 Back-to-back bi-directional converter.

 

Another circuit topology that can achieve buck and boost function is LLC series
resonant converter (LLC SRC) shown in Figure 7-16 [56, 57]. This circuit uses
transformer magnetizing inductance to have both boost and soft-switching fimction of
converter. The voltage gain of LLC SRC is shown in Figure 7-17. This circuit is mainly
used for front-end dc-dc converter for distributed power system and showed good

performances such as high density, high efficiency especially at light load condition.

120

However, the attainable voltage gain of the LLC SRC decreases as Q factor (or load)
increases as shown in Figure 7-17. The reason for this is that the LLC SRC is basically a
variation of the traditional SRC, but it uses low transformer magnetizing inductance.
When the load becomes heavy, the effect of magnetizing inductance becomes less and

this circuit eventually takes properties of the SRC.

 

 

 

 

 

 

 

 

 

V0
S1: S2: Lr . Cr 1:” D1 D2
W
VinCD Lm 1 7‘ 03:11.
S3 A/ 194/ #1)} %D4
_l____1 ~

4212:0111

Figure 7-16 LLC series resonant dc-dc converter

Voltage gain

    

1
fsw/fr

Figure 7-17 Voltage gain of LLC series resonant converter

121

This problem can be solved by either reducing magnetizing inductance of the
transformer or reducing characteristic impedance of the resonant network. In this case,
however, current flowing through the magnetizing inductance becomes big. This will
increase switch turn-off current and results in efficiency drop. Thus, the LLC SRC is not
applicable to the system that requires wide input voltage and load variation.

Figure 7-18 shows a transformer isolated Z—source dc-dc converter. The Z-source
concept which was originally developed as a Z-source inverter by Dr. Peng can also be
applied to a Z-source dc-dc converter [1], [58, 59]. The great and unique feature of the Z-
source converter/inverter is that it can be short and open circuited without damaging
switching devices. Therefore, the converter reliability can be greatly improved. However,
the main drawback of the Z-source converter (or inverter) is that the input (source)
current is discontinuous because the input source of the converter is connected in series
with a diode which is periodically on and off by switching action of switching devices.
Therefore, an input LC filter or C filter should be included between the DC source and
diode to smooth out pulsating input current especially when the source is a fUCI cell or

battery.

 

 

 

 

 

 

 

 

 

 

'

 

 

 

 

 

Figure 7-18 Z-source dc-dc converter

122

 

 

 

 

 

 

Lz D Lz Vpn L0
51/ 52; 1 n 1314S Dz}; +
V- CD C291: +V Ttr) ' % C0==RL V
m _ tr- 0
gfi afi q¥a% _

 

 

 

 

 

 

 

 

421410151

Figure 7-19 qZ-Source dc-dc converter.

 

In order to overcome the aforementioned drawback of the Z-source converter (or
inverter), a quasi Z-source inverter was pr0posed recently [60-62]. The qZ-source
inverter can also be applied to qZ-source dc-dc converter as shown in Figure 7-19. In this
scheme, one of the Z-source inductors in Figure 7-18 is placed in series with DC the
source without sacrificing the circuit operation. Thus, the converter input current can be
continuous in this structure, which is a great advantage over the original circuit shown in
Figure 7-18.

Figure 7-20 shows the Z(or qZ)-source dc-dc converter operating at buck mode. In
this mode, there is open-circuit interval in gate signal to step down output voltage. The
input and output voltage relationship is exactly same as the conventional buck type

converter and is expressed as

—0— = nD (75)

NV

123

Figure 7-21 shows the Z(or qZ)-source dc-dc converter operating at boost mode. In
this mode, there is short-circuit interval in gate signal to step up output voltage. The input

and Z-source capacitor voltage (ch ) relationship is

 

322—: I‘DS (7.6)
V l-2D

, where D. Figure 7-20 is shoot-through duty cycle and is equal to (1 —D). Similarly,

input and VP" voltage relationship is

 

 

 

 

 

 

 

 

 

 

 

V
P" = 1 (7.7)
Vin 1— 2Ds
Open circuit period
5, &S4 __11'—— L.
52 &s3 — ' '
Vin = Vc
VP" )1
— K" = VC
V. w
<—D—>
1 . I_. V0
Vrec >t
1,, > t

 

 

 

 

 

 

 

 

Figure 7-20 Key waveforms in buck mode

124

In boost mode, the output voltage is equal to ch . Therefore, input and output

voltage relationship is

V0 1—1), D

V," = 1-21), = 213—1

 

(7.8)

Short circuit period

 

 

 

 

 

 

 

 

 

 

 

 

 

t ° :1
516254 ‘ fi - f;
32 as, —"1 113:5. ""
#3811 3'; D3 Viv-*5“
_ 1—1 1 1— . Vx
V r)
“ V...
Vpn > 1
VI
.,__. —
Vtr > t
D -V,
Vrec > t
L2 } t
I” > t

 

 

 

 

 

 

 

 

Figure 7-21 Key waveforms in boost mode

125

From (7.5) and (7.8), the overall voltage gain of Z-source dc-dc converter can be

drawn and is shown in Figure 7-22.

 

 

 

 

 

A 1
£0. 1’.
Vin 1. Boost
.‘
‘
\
\
‘
‘.
1 ..
/ Buck
1 ’ D
0 0.5 1

Figure 7-22 Voltage gain of Z(qZ)-Source dc-dc converter.

The Z—source (or qZ-source) converter mentioned above, however, has a bulky
inductor in the output to make a fairly constant DC output. In this case, there exists high
voltage oscillation across the diode rectifier due to resonance between the transformer
leakage inductance and junction capacitance of the rectifier diodes. This voltage
oscillation problem is already discussed in great detail in Chapter 4. In addition to that,
the diode in the Z-source network makes additional power loss.

In order to solve these problems, a novel dc-dc converter using a distributed Z-

source network is proposed in this chapter and is shown in the next section.

7.4. The Z—Source Concept and Distributed Z-Source Network

The Z-source power converter provides a new converter topology and theory with

the intention to overcome the problems of the traditional V-source and I-source

126

converters [1]. The Z-source converter comprises an impedance network to couple the
main converter circuit to the power source or load, which is different from the V-source
and I-source converters and has none of the previously mentioned problems.

Figure 7-23 shows a general topological arrangement of the Z-source concept [46]. A
two-port network that consists of inductors LI and L2 and capacitors CI and C2
connected across both sides is employed to provide an impedance source (Z-source)

coupling the converter (or inverter) to the dc source or load.

 

 

 

 

 

 

 

 

Z-source Converter
DC source network [Inverter
JUL; 1
I \ L1 / ___,
C C
(Dore) 1 2 [I Load
L2 1
1‘6‘0"

 

 

 

 

 

 

 

 

 

 

 

Figure 7-23 A general topology of the Z-source converter.

The great and unique feature about the Z-source network is that unlike the traditional
V-source or I-source, it can be open and short-circuited, which provides a mechanism for
the main converter circuit to step-up or step-down voltage as desired. The Z-source
network provides great flexibility for the source, main circuit, and load. The Z-source
network shown in Figure 7-23 can be short- and open-circuited on either side. Therefore,
the Z-source concept can be generalized as to provide a two-port network (or circuit) that
can be short- and open-circuited at any time according to operation needs. These two-port
circuits include a transmission line and a capacitor-inductor hybrid that have been

investigated by many contributors for other purposes [63-68].

127

7.5. Transmission Line Based Z-Source Network-Distributed

Z-Source Network

A transmission line network is a two-port network and naturally satisfies the Z-
source concept’s requirements: that is, the network can be open- and short-circuited by
switching devices [46]. Because the capacitance and inductance are distributed along the
network, this type of networks is called “distributed Z-source network”. Efforts have
been made to utilize the parasitics and transmission line networks in power electronics
circuits [64, 65].

Figure 7-24 illustrates a general topology of the transmission line based power
conversion or distributed Z-source network (DSZN) power converter. The proposed
DZSN intentionally utilizes the parasitics and distributed inductance and capacitance for

power conversion and at the same time for EMI attenuation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DC (voltage or
current) source or Converter
load or Inverter
1 Line length (I)
I J '
a C ————->
_< \flL—O- 000 { Load (DC
(DLLCD 2.2,... 1 4 .rgssz.
__J
Distributed Z-Source
network

Figure 7-24 A general topology of the distributed Z-source converter [46].

Recently, an interesting Z-source network which has similar functions as the
conventional Z-source network shown in Figure 7-23, but a little different in structure, is

introduced and its basic conceptual structure is shown in Figure 7-25 [46], [69].

128

Line length (l)

 

Dielectric _ .
b Metal d

 

 

 

Figure 7-25 A basic structure of DZSN or transmission line network.

Line length (I)

LMC
_LJ__|__LJ__LJ_J_ L;
b = d

 

Figure 7-26 Electrical representation of DZSN.

The structure is a typical parallel plate two-port network (or transmission line
network) with line length I. It consists of two conductors with dielectric insulation in the
space between the conductors. The top and bottom conductors sandwich dielectric
material to form capacitance. At the same time, the two current carrying conductors are

insulated by magnetic core to form inductance. Figure 7-26 shows the electrical

representation of the two-port network shown in Figure 7-25.

In order to implement the proposed network, the DZSN can be implemented in either
common-mode or differential-mode connected structures. Figure 7-27 and Figure 7-28
show a common-mode connected and differential-mode connected DZSN, respectively.
The L and C represent the total inductance and capacitance of the line. M is the mutual

inductance of the coupled inductor. The LAX and CAx is the inductance and capacitance

129

in each cell, where Ax is the line length of each cell. In Figure 7-27 and Figure 7-28, the

winding resistance and conductance of the network are neglected for the sake of circuit

 

 

 

 

 

 

simplicity.
Line length (1)
¢
a LAx LAx LAx c
“PW—w— \DJLJ——0—
O 0
(MAX :1: Cszz o o 0 cm::
b O O 0 d
_<,_r‘6*0'\___r*6*6\__ m+
LA: LA: LAx
4—-—-P
x x + Ax
Figure 7-27 Common-mode connected DZSN.
Line length (I)

 

1
i4 D
1 LAX LA):

a LA): )2-

Mtgwwc. W ..
b A ,d_

i. LAx LA): LA):

x x+Ax

 

 

Figure 7-28 Differential-mode connected DZSN.

Although, the two common-mode and differential-mode DZSN have slightly
different structures, they both have very similar electrical properties to that of a
transmission line network. This is well explained in [70].

The two inductors in each cell can be either tightly or loosely coupled and can be

built in one core. For example, the inductors in common-mode connected DZSN should

130

 

be loosely or non-coupled inductors. Otherwise, there is a flux cancellation between top
and bottom conductors, which results in very small (leakage) inductance in each cell. On
the other hand, the inductors in differential-mode connected DZSN should be tightly or
non-coupled inductors to have a high or moderate inductance value. In this dissertation,
common-mode connected DZSN is selected because it is relatively easy to build.

Figure 7-29 and Figure 7-30 show a photo of the prototype DZSN developed in this
work. Two small toroidal powder cores are inserted in each conductor to make
inductance and to avoid magnetic coupling between them and a small value of capacitor
is connected across the top and bottom conductors. Thus, the two inductors and one
capacitor form a single cell and many of these cells are connected in series in a similar
fashion as shown in Figure 7-25 to form (or mimic) the characteristics of a transmission
line network. The inductance and capacitance values used in each cell are 2X66 nH and
3.3 nF, respectively. 80 cells are connected in series to set the operating frequency of the
converter in a reasonable range.

Figure 7-31 shows the overall circuit configuration of the proposed dc—dc converter
using DZSN. In order to achieve the buck and boost function of the proposed dc-dc
converter, the DZSN is coupled between power source and main switching devices. The
great and unique feature about the DZSN is that it can be open- and short-circuited by
switching devices like the conventional Z-source converter shown in Figure 7—23. As a
result, the proposed DZSN dc-dc converter has buck and boost firnctions, which cannot
be obtained with the traditional transformer isolated FB dc-dc converters shown in Figure

7-1 and Figure 7-2.

131

 

 

Figure 7-30 Photos of DZSN implemented (front view)

132

Line length (I)

    

 

 

 

 

 

   

 

 

 

m a A
b
Distributed Z-Source 1

network r!“ V0

Dz
__ <:
__ <,
+ Cour R L‘

03% D4

 

 

 

Figure 7-31 Proposed DZSN dc-dc converter.

Compared with the Z-source (or qZ-source) dc-dc converters mentioned before, the
proposed DZSN dc-dc converter does not suffer from the rectifier diode oscillation
problem because an output filter capacitor is connected to the rectifier diode directly. No
diode is needed in the Z-source network while maintaining the same buck-boost function

as the Z-source dc-dc converter.

7.6. Conclusion

In this chapter, a conventional non-isolated and transformer isolated buck-boost dc-
dc converters are reviewed. Limitations of the conventional buck-boost dc-dc converters
are addressed. A distributed Z-source network composed of an array of inductors and

capacitors is introduced and its properties and characteristics are examined in detail. The

133

proposed DZSN can be used as a dc-dc converter that can overcome the theoretical

barriers of the conventional dc-dc converters.

134

Chapter 8. Principle Operation of
Distributed Z-Source Network DC-DC

Converter

8.1. Input Impedance of Distributed Z-Source Network

The input impedance (Zin) of DZSN plays an important role in the operation of the

proposed DZSN dc-dc converter. The unit of measurement is the ohm, but we cannot
simply attach an ohm-meter to the network to measure its impedance. Figure 8-1 shows

the measurement setup for the input impedance Z in of DZSN. In order to measure Z in of
the network, the line is terminated with a load (Z L) and Z in is measured on the other

end.

Line length (I)

a ———I-\QL—O 000::
com Lam S
—l"O'U‘—v ".1,

Distributed Z-Source
network

 

 

To

“T

 

 

 

Figure 8-1 Input impedance measurement.

As already well known, the Z," of a lossless transmission line terminated with a load

is defined as follows [67, 68], [71]

135

gi+tanh(yl)
Z Z

in :26 Zc (81)
214mm)“

C

 

In (8.1), Z L is the load resistance connected to one end of the two-port network. Zc

is the characteristic impedance and y is the propagation constant of the network and they

are defined as

_ [Z(LLM)
zc .. C, (8.2)

y = ij2(L '- M')C' (8.3)

 

,where L , C i and M i are the per-unit length self inductance, capacitance and mutual
inductance of the line, respectively.
The Z: of a line is not dependent on its length but on the physical arrangement of

the size and spacing of the conductors. From (8.1), Z in of the lossless transmission line is

a transcendental function with an infinite number of j-axis poles and zeros [64, 65].

In this dissertation, Z in is measured with a short-circuited load ( Z L = 0) because the

one (left) port of DZSN of proposed dc-dc converter is connected to DC voltage source

and we measure Z1" from the other side (right) of network (see Figure 7-31).
When the line is terminated in a short circuit, then Z," = Z6 tanh(yl). The zeroes of

Zm lie at s = jwv, where

V]?

= or v = O, 2, 4,... (8.4
21J2(L'—M')C' f )

Wv

136

Likewise, the poles of Z in are located at odd multiples (v = 1,3, 5, ....) of the principal
quarter-wave resonance, wl. In order to understand the characteristics of the DZSN, and

to calculate the pole and zero frequencies of the network, the following definitions are

necessary.

First, the wave velocity on the line is defined as

1

= 8.
v ,f2(L'—M')C' ( 5)

 

Secondly, the travel time, Td , (or transmission delay) of the electric signal on the

line is defined as

rd =3 (8.6)

Thirdly, the wavelength A. of electric signal is

2 = (8.7)

l
f
,where f is applied frequency to line. From (8.5)-(8.7), the principal quarter-

wavelength (1 = % ) resonant frequency, f1 can be calculated as

l 1

f1 =4—T;=4Ifi(L'—M)C'

(8.8)

137

From definitions, L = , M i =2; , where L, C and M are the total

inductance, capacitance, and mutual inductance of the network, respectively. Therefore,

 

 

 

(8.8) can be expressed as
1 l 1
= = = 8.9
f‘ 47;, 41J2(L'—M')C' 4f2(1.-M)C ( )
Eq. (8.9) can also be expressed using a number of cells as follows.
f1 1 xi (8.10)

41/20de ‘ M cell)Ccell "

,where L=nL , C =nC , M =nM , n is the number of cells and
cell cell cell
Lee”, Cce”, and Ma,” are the inductance, capacitance, and mutual inductance of each

cell of the n cell network, respectively.
Table 8-1 summarizes the electrical specifications of the prototype DZSN shown in
Figure 7-29. From the information in Table 8-1 and Eq. (8.10), the principal quarter-

wavelength resonant frequency f1 was 150 kHz. Figure 8-2 shows the simulated
magnitude response of Z," of DZSN. As expected, the j] is placed at 150 kHz and all
the other poles and zeroes are located at the integer multiple of f1 . Since the network is

assumed as lossless transmission line, there is no high frequency attenuation in

magnitude.

138

Table 8-1 Electrical specifications of DZSN.

 

Magentic core: Changsung Sendust core
0 Part number: CS102125

o permeability ( p F125

Distributed Z-source

 

 

network 0 AL value=66 nH / N 2
Capacitor: WIMA
Electrical values n = 80, LC,” = 66 mar. c...” = 3.3 nF, M...” = 0
Characteristics

{2(L—M) ,2x66nH
Z : _-— = —— = .
impedance of network 0 C 3,3,1}? 6 320

 

 

1 1

= X ‘—
4fia’cell — M cell )Ccell n

resonance frequency 1 x 1 150 kH
= — z 2
4J2x66on33nF 80

Principal quarter wave f1

 

 

 

 

6°' f1 34 5f1

40- . .

20>

Zin [dB]

 

“20' 2f1 4f1 6f1

 

 

o 5 1b 15
fiequency [Hz] )1 105

 

 

 

Figure 8-2 Simulation results of Z," with Z L = O.

139

 

 

 

 

 

,
its
_l
jh-‘E
..‘m;
:91
.5

 

 

 

   

I A l A HAIL
, 1.
i 1
1
: 2 1

 

Magnitude [ohm]
8

.. .H ... . ... .L ....j.... . .. - ..r v - ,. -. .- j .. -.
.. .. . . . - .. . .. ., .4 . . . . . ‘t .. .,
.. . V . .. - A .. . -. . .. . .. . . .. . ... .. . . .. .. .. -
. . 1 . 1 . . . .1 . . . . . . 1 . _ . . . . L . _.
.. ... .. . . . - ... . . .. . . .. ... .. ... ... . . .. .... . . . .. .. .. -... ... _. , . _. .. .. .
. .... .... , ... . ... .... ... ..L . .. .4 7,. .. ... .1 .. . ... .. .. ,. ... . .. . .. . 1
L + . .. .. \ .. . .. .. .. . _. ... . ... . . 1. 7
. i - a
.. .. .. . . .. .. . .... . . .. ... . .. .. ... ... ._ .. . . . ... .... .. .. . .. ..- .. .. ..
' 1 . .
. . . 1
y
a. . . .1 . .. ., .. . . .. . . .
I . . . . L . . . . .. . . - .. .. .. ,. .. ... 1 .. . , .. .. ...
. . . ... . .. _ .I, . .. .. 1 .. .. ,. 1. .. .. . ... .L... ,.....,..
.. .- .. -. - 1 .. .. - - .. ,. . . . .. _ .. a. -
. .. . . .. 4. . -. ..
. .

' 5‘21.

 

 

—L

1 A Lilli.

 

1 .

'250.00k'500.00k'750i00k' 1.00M ' 1.25M ' 1.50M
Frequency [Hz]

1.1..

 

 

 

 

 

 

 

 

Figure 8-3 Z in measurement of DZSN with Z L = O (Magnitude)

 

 

 

 

 

 

 

....

; ,1- /\/ V

1L

60 . . ”,g

0°
C

 

Phase [dog]
1

 

 

(b
O
"1

 

 

 

1'»
o

 

1'0
0

 

 

 

 

 

 

 

 

 

250.0016500.00kr750.00k' 1.00M ' 1.25M ' 1.50M
Frequency [Hz]

 

 

Figure 84 Z in measurement of DZSN with Z L = 0 (Phase)

140

 

Figure 8-3 and Figure 8-4 show the measured magnitude and phase response of Zin
of the prototype DZSN shown in Figure 7-29 when Z L is zero (shot-circuited). An HP
4194 impedance analyzer is used to measure Z)". The f1 was very close to 150 kHz.

However, there is quite considerable attenuation in magnitude and phase as frequency
increases. This is because the AC winding resistance, caused by skin and proximity effect,

becomes dominant at high frequency.

8.2. Voltage and Current distribution along DZSN

From the impedance measurement of Figure 8-3, the Z,” of DZSN varies as the
excitation frequency fax changes. Therefore, the voltage and current distribution along
DZSN change, too. fex is twice the switching frequency ( fsw) of the dc-dc converter

because of the full-bridge circuit configuration.

Figure 8-5 and Figure 8-6 show the DZSN terminated with a DC voltage source at
left end and the input impedance is seen at the right end where switching devices are
present. The rest of the F B circuit is omitted for the sake of simplicity. Figure 8-5 shows
the voltage and current distribution when fax is set to f1 , the principal quarter wave
resonance frequency. In this condition, the line length of the network is one quarter wave-
length and the input impedance of the network is very high-approaching infinity. This
result can also be expected from the impedance measurement shown in Figure 8-3. On
the other hand, impedance at the DC source (short-circuit) is zero.

Figure 8-6 shows the voltage and current distribution when fex is set to 2 f1 , the half

wave resonance frequency. In this condition, line length of the network is equal to one

141

 

half wave length and input impedance of the network becomes minimum or equal to

impedance at the DC source. This result can also be expected from the impedance

measurement shown in Figure 8-3.

Voltage Vpn measured at the switching side is equal to input voltage Vin at this

condition, which is a unique and interesting phenomenon of DZSN. In other words, Vpn

is forced to be equal to Vin due to the waveform shaping fimction of DZSN. However,

impedance at the middle of the line length is high.

 

 

 

 

x=0 L. le h :1
'09 "gt (1) .
a >— _TflL—I. on; >£ +
I/in COAX LOAX 1 VP"

>_ __‘LW ...1. -

b " a
i Zin
V
b.....‘ \

 

 

  

 

 

 

 

   

w.....

 

—>
1 1
low high
impedance impedance

Figure 8-5 Voltage and current distribution along DZSN when fex = fl , Quarter wave-

length condition (I = %)

142

x=0 . x=l
Line length (I)

a ,. c
W o 00:: )— +

K" COAX LOAx i Vpn
_iqnyx. 'l -

 

 

 

 

 

 

 

 

1 1 1
low high low
impedance impedance impedance

Figure 8-6 Voltage and current distribution along DZSN when fex = 2 f1 . Half wave-

length condition (I = 5%)

8.3. Output Voltage Control of the Proposed DZSN DC-DC

Converter

The overall circuit configuration of the proposed DZSN dc-dc converter is shown
again in Figure 8—7 for mode analysis. The transformer turns ratio is set to 1:1 for the
sake of simplicity. The necessary voltage and current are labeled in this figure.

The proposed dc-dc converter shown in Figure 8-7 can be short- and open-circuited
without damaging switching devices because DZSN is coupled between DC source and

switching devices. In this section, detailed operating modes will be explained to illustrate

143

the buck and boost function of the proposed dc-dc converter. Voltage gain of the

proposed DZSN dc-dc converter in both buck and boost mode will be derived.

Line length (I)

    

 

 

 

 

 

 

 

 

 

 

 

Figure 8-7 DZSN dc-dc converter.

8.3.1 Buck mode (V in>Vo)

Figure 8-8 shows the operation point at buck mode. From the result of Figure 8-6,

Vpn is clamped to Vin when fex =2 f] or fsw = fl (point “A”). fsw is the switching
frequency of the converter. Thus, the proposed dc—dc converter at this half wave length
condition becomes similar to the conventional V-source type PWM dc-dc converter

shown in Figure 7-1 because Vpn is equal to V1". However, the proposed converter
cannot have an output filter inductor to control V0. Otherwise, V0 cannot be boosted in

boost mode operation.

144

In this dissertation, transformer leakage inductance le is used to control V0 , instead.

Therefore, a conventional duty cycle control method with fixed switching frequency can

be used to control V0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x = Line length (I) x = 1
ad 1 w 000 )2- +
V}?! ¢ COAX T LOA-x ! Vpn
b<' _ m ...( 12. -
, Zin
point “8"
point “A”: fsw=f1
point “B”: fsw=f1l2
Vin
xxx / i >
Iciw 1111111 low

impedance impedance impedance
Figure 8-8 Operation point at buck mode (point “A”)

Figure 8-9 depicts the key waveforms in buck mode. The proposed dc-dc converter
at this mode operates with duty cycle control by modulating open circuit duty cycle as the
conventional V-source F B PWM converter. However, the conventional V-source
converter suffers from the shoot-through problem caused by EM] misgating-on and can
destroy switching devices because the input DC link capacitor is directly discharged
through the switching devices.

On the other hand, the proposed converter can be short-circuited without damaging

switching devices because all the capacitors in the network can only be discharged

145

through the inductors that are distributed along the network and the capacitance of each

cell is very small. Therefore, current flowing in the switching device is limited by

distributed inductors.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A Open circuit period
sl as4 __1 .L..
52 as,
Vpn _" Vin
+1
Vin
Vrr.pri > t
V
Vtrsec 0) t
'14—'Vin + V0
Vin _ V0
Vuk > t
1 .
l"
Itr .2 >1
fi-I k
/.1 4 /&_ 1”
[rec .r 0 >1
’0 ’1’2 ’3

 

 

 

 

Figure 8-9 Key waveforms of the proposed dc—dc converter at buck mode

146

The operational modes of the proposed converter in buck mode are explained as

follows.

- Mode 1 (~10 ): All switches and rectifier diodes are turned off and VP" is equal to

Vin . Transformer voltage and currents are zero.

- Mode 2 (to —t1):S1 and S4 turn on and D2 and D3 start conducting. Therefore,

V", is applied to the transformer primary winding. Transformer current starts increasing

. V- — V . .
wrth the slope of 437—0 untrl t1 . The peak transformer current 1s calculated as
[k

Vin — V0
111

T0,, (7.1 1)

 

[pk =i(tl)=

,where T 0,, is switch turn-on time.
- Mode 3 (11 —t2 ): S1 and S4 are turned off and the transformer current flows

- V," is applied to the

through the anti-parallel diodes of Sz and S3 . Therefore,

transformer primary winding. The transformer current starts decreasing with the slope of

V- + V . . . . .

%—‘L untrl it reaches zero at t2. In thrs mode, D2 and D3 are strll conducting because
lit

the transformer current is positive. Thus, transformer current is regenerated into DZSN.

The voltage overshoot in Vpn is caused by this regenerated current.

- Mode 4 (t2 — t3 ): The transformer current reaches zero at t2. D2 and D3 are turned

off and transformer secondary voltage becomes zero. This is the end of half cycle

operation.

147

 

 

L021): -’ ->
Distributed Z-Source
network

 

 

 

Figure 8-10 Voltage overshoot in Vpn at buck mode

Figure 8-10 explains the mechanism of voltage overshoot in VP" in more detail. The
voltage overshoot in Vpn when switch off is caused by the regenerative energy stored in

L”. that flows back to DZSN through body (anti parallel) diodes of switch. Unlike the
conventional V—source type converter which has big DC link capacitance, the capacitance
value of each cell of DZSN is very small, 3.3 nF. Therefore, even a small amount of

energy that flows back to DZSN is high enough to make a voltage overshoot in Vpn.

8.3.2 Boost mode (Vin<Vo)

Figure 8-11 shows the operation point at boost mode. In this mode, a short circuit
interval is required to store energy in the DZSN as the conventional I-source PWM
converter shown in Figure 7-2.

As already mentioned in buck mode operation, the short circuit at point “A” or short

circuit at fm = fl will not damage the switching devices, but efficiency of the system at

this condition would be low because the input impedance at point “A” is minimum. In

148

this dissertation, fsw is decreased in order to increase input impedance of the network. At
the same time, the short circuit duty cycle (D3) of the converter is increased to boost V0.

The fsw and D3 change from point “A” to point “B” linearly as shown in Figure 8-11.

 

 

 

 

 

 

 

 

 

 

 

 

For example, 1;“, becomes i;— and D3 is 0.5 at point “B”, quarter wave length condition.
x = 0 Line length (I) x =1
0 c
TQM 000; >— +
Vm COAX I LOAx i Vpn
b 0.. )d— -
Zin
point “B", 1,”, l, D, t
.
point “A”: fsw=f1 ,, ”N’s
point “B”: fsw=f1l2 // \
' ‘
V... f #—
‘L. point “A”
\\ / ;
‘\.\‘--..,__ J... r" i L
low 1111111 Iciw

impedance impedance impedance

Figure 8-11 Operation point at boost bode (between point “A” and point “B”)

The proposed dc-dc converter at this mode operates with duty cycle control by
modulating a short circuit duty cycle as the conventional I-source PWM converter.
However, the conventional I-source converter suffers from the open-circuit problem
caused by EMT misgating-off. Therefore, the switching devices are damaged by
overvoltage because the input inductor has no path to discharge its energy and it will

finally charge the junction capacitance of the switching devices.

149

On the other hand, the proposed converter can be Open-circuited in this mode
without damaging switching devices because the inductors in DZSN are connected
between capacitors distributed along the network. Thus, energy stored in the distributed
inductors of the network can be transferred to capacitors distributed along the network
and the inductance of each cell is very small. Therefore, voltage overshoot in the
switching device is limited by distributed capacitors in the network. Figure 8-12 depicts
key waveforms at boost mode.

Operational modes of the proposed converter in boost mode are explained as follows.

- Mode 1 (~ to )2 All switches are on and the rectifier diodes are all off. Vpn is equal

to zero. Transformer voltage and currents are zero. Input energy is stored in DZSN.

- Mode 2 (to —t1):S2 and S3 turn off and D] and D4 start conducting. In this mode,
Vpn becomes a little greater than V0 because there is a voltage drop across le. This
voltage is labeled as Vx in Fig. 12.

Therefore, VJr is applied to the transformer primary winding and transformer

secondary voltage is equal to V0. Transformer current starts increasing with the slope of

x—Vo

L11

 

until ’1 .
- Mode 3 (t1 —t2 ): S2 and S3 turn on again and VP" becomes zero. The transformer
. . V0 . .
current starts decreasmg wrth the slope of —— untrl it reaches zero at t2. Transformer

er

secondary voltage is maintained to V0 because D1 and D4 are still conducting.

150

 

- Mode 4 (t2 —t3 )2 The transformer current becomes zero at 12. D1 and D4 are

turned off. This is the end of half cycle operation.

 

Short circuit period
t /

s1&S4 T

$28.53 '"r—‘V'fi

 

 

 

 

-11

- . -;.-' I “- -' 1 ~:.:-;~“-':‘-..:«‘»‘-.-.-:'
. .- ‘ - . . .'.' -_.. n. ..r
1‘ < - . . . ' .' . ...... "‘." :' .

 

pn

 

Vrr.pri ’ t

 

 

Vrr.sec 1 > t

 

 

 

VLIk

 

 

[tr 1 L1

 

 

 

4r / / /. .,

’0 ’1’2 ’3

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 8-12 Key waveforms of the proposed dc-dc converter at boost mode

151

8.4. Derivation of Voltage Gain

8.4.1 Buck mode

In order to derive voltage gain at buck mode, the transformer leakage inductance

voltage “’11” and the rectified transformer current (1m) waveforms in Figure 8-9 are

shown again in Figure 8-13.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A
S1&S4
S2&S3 _.
H (Vin—Va)
VLIk >1
—(V +Vo)->-
/ /\+ka
10
1'“ t a <— N
D D
0 A .7; r,
2

Figure 8-13 Waveforms at buck mode

Defining duty cycle D as the time interval when the switches are closed over the

half switching period (7} / 2) and D A as the time interval when transformer current

returns to zero from its peak value ( I pk ), average voltage across the transformer leakage

inductance (le) during this half switching cycle must be zero due to flux balance

condition on le. The results is expressed as

152

D(Vin_Vo):DA(Vin+Vo) (8-12)

V0 _D-DA
D+DA

 

(8.13)

Similarly, the average value of rectified transformer current (1,“) is output current and it

is represented as

 

1 V
E(D+DA)IPk=—R—0— (8.14)
,where [pk is defined as
V- —V
[pk =[i—1]D—Ti (8.15)
L1,. 2
From (8.14) and (8.15), D A can be found as
V0
RL D

Therefore, voltage gain at buck mode can be found from (8.13) and (8-16) as follows

 

_Vi _ J(2DZ + 102 + 8K1)2 —(2122 + K)
V... M

 

(8.17)

,where K is defined as 4_L;’$_f51v_ in (8.17) for the sake of simplicity.
L

153

8.4.2 Boost mode

Voltage gain at boost mode is a little more complex than that of buck mode because

both the switching frequency and duty cycle of converter changes in this mode. The VP" ,

transformer leakage inductance voltage (VLIk) and the rectified transformer current (1,“)

waveforms in Figure 8-12 are shown again in Figure 8-14 to derive voltage gain.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

s] as, '——
52 as,
Vx
V... V1.”
(VJ: _ V0) _-
K
V1.11: > t
_VO + _l
/\ /1\“ 1.1
1 ’°
1 rec 47 t
. 1+
2

Figure 8-14 Waveforms at boost mode

Defining duty cycle D as the time interval when only two diagonal switches (S1, S4
Or S2,S3) are closed over the half switching period (7;. /2) and D A as the time interval
When transformer current returns to zero from its peak value (ka ), average voltage

across the DZSN inductor and transformer leakage inductance (le) during this half

Switching cycle must be zero due to flux balance condition.

154

First, the average value of VP" is equal to input voltage V,-,,. This relationship is

expressed as

W. —V1.)=(1—D)V.-. (8.18)
Vx _i
7- D (8.19)

Secondly, the average value of V L ,k during the half switching interval is zero. Thus

 

D(Vx — V0) = D AV, (8.20)
V
Vx D+DA

Thirdly, the average value of rectified transformer current (1m) is output current

and it is represented as

1
— D+D I =—9— 8.22
,where 1 pk is defined as
V _
,p, _[__L:_]Da (.23,
L1,( 2

In this boost mode, the converter switching frequency changes with D

proportionally and the relationship is explained in Figure 8-15.

155

 

 

 

 

 

L)- " fswzfoD
2 ,

 

 

 

 

 

>D
0 0.5 1

Figure 8-15 Relationship between fsw and D

In Figure 8-15, f0 is defined as the frequency when D is equal to 1. Thus, f0 is

150 kHZ.
From (8-19), (8-21), and the equation in Figure 8-15, the voltage gain at boost mode is

expressed as

V ‘/P2 +4—13- —P
—0—— D (8.24)

 

,where P is defined as RL in (7-24) for the sake of simplicity.
41'1ka

From (8-17) and (8-24), overall voltage gain of the proposed DZSN dc-dc converter

is plotted in Figure 8-16.

156

 

 

Voltage gain
...-I
-~ '01 N
z 1 z
i i i

.°
0:
l
l

 

 

O
I'-

 

0 0.2 0:4 0:6 0.8 1
Duty cycle (D)

Figure 8-16 Voltage gain of the DZSN dc-dc converter

8.5. Simulation and Experimental Results of the Proposed
DZSN DC-DC Converter.

Based on the above mentioned theoretical analysis, a prototype using DZSN was
built and tested to verify the operation of proposed dc-dc converter and its results are
compared with simulation results.

Table 8-2 summarizes the test conditions and electrical specifications of the

proposed converter. In this work, transformer leakage inductance ( le) is almost 2 pH .

Figure 8-17 and Figure 8-18 show the simulation and experimental results of the
proposed dc-dc converter operating at buck mode. In this mode, an open circuit gate

signal is employed and its gate signals are modulated to control V0.

The experimental waveforms in Figure 8-18 are measured when Vin=70 V, Vo=50

V, Po=500 W and fsw=150 kHz. As can be seen, the simulation and experimental

157

waveforms are quite well matched. In this paper, the voltage overshoot in Vpn is

measured without any snubber or clamp circuit. In practical use, a snubber or clamp

circuit may have to be used to suppress the overshoot.

Table 8-2 Test conditions and electrical specifications of proposed DZSN dc-dc

 

converter.
o Vin =30 -70 V
0 V0 =50 V
Electrical specifications o Po =500 W
0 RL = SQ
o le = 2 pH

 

0 MOSF ET: IRFB4620 (200 V/25 A),
_ 2 in parallel
Devrces used

0 Diode: Schottky STPS41L6OCG

(60 V/20 A), 2 in parallel

 

Switching Buck mode 150 kHz

frequency

 

Boost mode 75 kHz — 150 kHz

 

 

 

 

 

The waveforms at boost mode operation are shown in Figure 8-19 and Figure 8-20.
In order to boost output voltage, a short circuit gate signal is used. Duty cycle and

switching frequency of the converter are modulated to control V0. The experimental

waveforms are measured when Vin=30 V, Vo=50 V, Po=500 W and fsw=75 kHz. As can
be seen, the simulation and experimental waveforms are quite well matched. The output

voltage is clearly boosted in this mode.

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161

Figure 8-21 and Figure 8-22 show the simulation and experimental waveforms tested

at normal mode when Vin is equal to V0. In this mode, the converter duty cycle is set to

0.5 and there is no open- or short-circuit in gate signal. Since transformer leakage
inductance is used between input and output of the converter, there is a voltage drop

across leakage inductance. Thus V0 is slightly lower than Vin.

Finally, efficiency of the proposed converter is measured when input voltage
changes from 30 V to 70 V. Figure 8-23 shows the measured efficiency curve of the
proposed converter. Maximum 94 % efficiency is achieved with the proposed dc-dc
converter. The efficiency in buck mode is lower than that of boost mode. This is mainly
caused by the switching loss in MOSFET because the switching frequency in buck mode
is higher than that of boost mode. However, efficiency of the proposed converter can be

improved if a soft switching method such as PSPWM is used.

 

 

 

 

 

 

 

 

Vo=50 V, Po=500 W
100 . , p .
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70 a . . 1 . . .
30 40 50 60 70
Input Voltage [Vin]

 

 

Figure 8—23. Efficiency of proposed converter vs. input voltage.

162

8.6. Conclusion

In this chapter, a novel power transfer concept has been proposed. The proposed
distributed Z-source network dc-dc converter has the desired buck and boost converter
functions. The advantages of the proposed dc-dc converter are as follows.

0 The proposed dc-dc converter has buck and boost function. The output voltage
can be greater than or smaller than input voltage. Therefore, the proposed dc-
dc converter is a very desirable circuit topology when the input voltage range
of the converter is wide.

0 The proposed converter can be short- and open-circuited without damaging
switching devices. Thus, it is very strong to EMI, and converter robustness
and reliability are significantly improved.

0 No snubber circuit is required in the output of the converter because a bulky

output inductor is removed. Therefore, a low voltage diode can be used, which

results in improved efficiency.

A 500 W prototype has been built and tested to verify the principle operation of the

proposed converter.

163

 

Chapter 9. Contributions and Future
Works

9.]. Contributions

This dissertation has the following contributions

0 The soft switching passive snubber circuit is introduced to minimize the
switching loss and voltage overshoot in IGBT. Its performances are verified
with experimental results.

0 A very compact and high efficiency transformer was designed to improve
converter efficiency. Very detailed analysis on proximity effect was
conducted and optimum copper thickness was found to minimize the
proximity effect. The efficiency of transformer designed in this work is over
99.5 %.

o The voltage oscillation problem in transfonner secondary rectifier diodes is
introduced and several voltage clamping methods were compared. Finally, a
new energy recovery clamp circuit is proposed. Neither lossy components nor
additional active switches are used to clamp diode voltage. Therefore, the
proposed ERCC is very promising for high voltage and high power dc-dc
converters with wide ranges of input voltage.

0 The 3 phase interleaved boost dc-dc converter using the integrated magnetic
was developed for the series hybrid electric bus. Detailed design steps for the

compact and high efficiency inductor was presented.

164

o In order to overcome the limitations of traditional V-source and l-source dc-dc
converters, a novel dc-dc converter using the distributed Z-source network
was introduced. The main properties of the distributed Z-source network was
analyzed.

0 The output voltage control method of the proposed dc-dc converter was
presented. The proposed dc-dc converter can be short and open-circuited
without damaging switching devices and it has the desired buck and boost
function. Therefore, reliability of the proposed converter can be greatly

enhanced

9.2. Recommendations for future works

The proximity effect in transformer winding is related to the distance (or space)
between layers (or windings). Thickness of the insulation material (for example, the
thickness of nomex paper) will have some effect on the proximity effect. However, this
effect is not included in this work. Further research work should be done on this.

The proposed distributed Z-source network dc-dc converter was developed and
tested with 500 W output power in this dissertation to prove the basic concept and
principle of converter. Further work should be continued to extend power rating of the
proposed converter and to increase converter efficiency. In addition to that, the core loss
in network should be minimized to improve efficiency either by using ferrite core or by

changing network structure.

165

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