PI... 3}... nav.||..'AIi\ . f... .f‘ . Ht: » d .) .I it.“ ’2. Q ill..VIIQ 1‘56 3.. .1- : I‘leiu liuiuv II ( “ .‘l. 3:) nlxxizwlnh uni! $93.31.?! 9 - £..lu¢!c!.\ v smmfiw. . 5%}. .. 2t 0.! I! I 'i. v2.3.2:- 11 23.3.3.9. {.filhfigu :la?3.s£ol2 a!) butt-‘13.}- i 3251.. .1. ng‘u! it ills-xv‘velul 1|: it}? :3 ill. A. 3A....btiitt i.tsI\.-!Anb§.r1 .15 ‘1! slii..§1!‘h|..|¢nr.$o «IND. I! .I 1‘. c; \I‘xlls 493.! .:4|..I.l 1V '7'! if; . 3113‘!!! THESIS ’2. 2‘0 i (3 LIBRARY Mic! .2;:..‘. State University This is to certify that the thesis entitled ELECTRONICS SYSTEM FOR A LOW FREQUENCY ULTRASOUND PHASED ARRAY presented by JASON DAVID BIEL has been accepted towards fulfillment of the requirements for the MS. degree in Electrical Emineering ‘v I; "I: "rofessor’s Signflirt; Sepf. 24,, 2007 Date MSU is an Affirmative Action/Equal Opportunity Employer . --_._A...—-—--o--o-l- PLACE IN RETURN BOX to remove this checkout from your record. To AVOID FINES return on or before date due. MAY BE RECALLED with earlier due date if requested. DATE DUE DATE DUE DATE DUE A. 35%? 25.349513 5/08 K'IProj/Aoc&PresIClRCIDateDm.indd ELECTRONICS SYSTEM FOR A LOW FREQUENCY ULTRASOUND PHASED ARRAY By Jason David Biel A THESIS Submitted to Michigan State University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE Electrical Engineering 2009 ABSTRACT ELECTRONICS SYSTEM FOR A LOW FREQUENCY ULTRASOUND PHASED ARRAY By Jason David Biel An electronics system that allows for the independent control of all transducers in a 13 element low frequency (80kHz) phased array has been constructed and tested. The independent control of each transducer’s driving waveform allows for the control of the position and intensity of the focused pressure field. Each channel can deliver up to 25W continuous wave to a 509 load over a frequency range of 20Hz to 200kHz. Arbitrary waveforms are defined by a numeric array of 2048 8-bit values on a computer and sent to the controlling electronics and stored in memory. The waveforms have a resolution of 320ns and 4mV. Pulsed waveform trains can have a programmed delay ranging from Os to 167ms between cycling through the waveforms in memory. The pressure field in the water tank is measured over a 200x200x300 mm grid. The focus can be moved up to 30 mm from the geometric focus before grating lobes, due to the geometry of the transducer array, significantly distort the resulting pressure field. This work is dedicated to my parents, David and Janet Biel, my wife, Saori Obayashi, and my children Benjamin and Ethan Biel. iii ACKNOWLEDGMENT I want to thank my parents, David and Janet Biel, who have encouraged and supported my education throughout my life. Without their love and support I would not have been able to complete my education. I also thank Dr. Robert J. McGough for his support, patience and guidance in pursuing my masters degree. He gave me the freedom to explore and learn while providing direction when needed. I also thank Dr. Gregory M. Wierzba for the serving on my committee, for sharing his knowledge of circuits and giving me the opportunity to learn and teach with him. I know as much as I do about circuits because of his classes. I feel that I could not have learned about circuits as thoroughly from anyone else. My time helping teach his laboratories was one of the greatest experiences in my education. I thank Dr. Shantanu Chakrabartty for the serving on my committee and sharing his knowledge of circuits. I thank Dr. Edwin Loh for his support and encouragement during my undergrad- uate education, without it I would not have been able to pursue a masters degree. I learned a tremendous amount from his patient mentoring while working with him. I thank Brian Wright and Greg Mulder for their technical support and expertise. Their help allowed me to focus on my research. I thank Don Chorman for building the ultrasound array. I thank Don Vanderlaan, Matt Jennings, Marko Gerhard, Chris Mosser, and Paul Schmalenberg for their assistance in gathering data and building the system. I would like to thank all of the members of the Biomedical Ultrasonics and Elec— tromagnetics Laboratory that I have worked with over the years: Don Chorman, Don Vanderlaan, Matt Jennings, James Kelly, Duo Chen, Xiaozheng Zeng, Khawar Khur- shid, Marko Gerhard, Chris Mosser, Lioung Wu, Ruihua Ding, Paul Schmalenberg, iv Phil Gresock, and Josh Wong. I thank Roxanne Peacock for her assistance in helping me get the supplies I needed to finish my project. I thank Yasutaka and Michiko Obayashi for their support during my masters studies. Finally I want to thank my wife, Saori Obayashi, and my children Benjamin and Ethan Biel. Without Saori’s tough love to keep me on task I would not have been able to complete my thesis. Benjamin and Ethan have been a constant source of joy and inspiration that have provided needed stress relief and motivation during the difficult times. TABLE OF CONTENTS List of Tables ................................. viii List of Figures ................................ ix Introduction .................................. 1 Water Tank and Ultrasound Phased Array .............. 5 Control ..................................... 11 3.1 Waveform Specification .......................... 12 3.1.1 Commands ............................ 12 3.2 USB Interface ............................... 14 3.2.1 Software .............................. 14 3.2.2 Digital Board ........................... 14 3.3 Digital Board ............................... 16 3.3.1 Communications ......................... 18 Receiver .............................. 18 Transmitter ............................ 23 3.3.2 Communications State Machine ................. 26 3.3.3 Clock Generation ......................... 29 BAUD Clock ........................... 29 BAUD Clock synchronization .................. 30 DAC Clock ............................ 34 3.3.4 Memory .............................. 36 Port A: Computer Read and Write ............... 42 Port B: Computer Read and Write ............... 44 3.3.5 DAC Controller .......................... 46 3.3.6 I/O ................................. 52 3.4 DAC Board ................................ 58 3.4.1 Digital to Analog Converter ................... 58 Theory of Operation ....................... 58 Stability .............................. 60 3.4.2 Output Filter ........................... 63 Implementation .......................... 69 3.5 Amplifier .................................. 74 3.5.1 Types of Power Amplifiers .................... 74 3.5.2 Amplifier Design ......................... 83 3.5.3 Stability .............................. 90 vi 3.5.4 Performance ............................ 100 3.6 Impedance Matching ........................... 100 3.6.1 transducer impedances ...................... 100 3.6.2 Matching Networks ........................ 117 Pressure Field Measurement ....................... 152 4.1 Hydrophone Positioning ......................... 152 4.2 Hydrophone Measurements ........................ 153 4.3 Calibration ................................ 153 4.4 Pressure Observation ........................... 158 Results ..................................... 161 5.1 Pressure Linearity ............................. 161 5.2 Focussing ................................. 161 Discussion ................................... 172 6.1 Serial DAC ................................ 172 6.2 Additional Memory ............................ 173 6.3 Multiple Delay Patterns ......................... 174 6.3.1 Firmware Implementation .................... 174 6.3.2 Live Updating Implementation ................. 174 6.4 Power ................................... 175 Conclusion ................................... 176 Bibliography ................................. 178 vii 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.1 4.2 4.3 4.4 4.5 LIST OF TABLES Low level AWG Matlab commands. ................... 12 AWG high level commands. ....................... 13 AWG command summary. ........................ 26 Butterworth filter standard capacitor values. .............. 68 Amplifier classification summary. .................... 74 Ideal gain of common op-amp topologies ................. 91 Transducer impedances at 80kHz. .................... 103 Matching network element values ..................... 137 Impedances of matched transducers .................... 138 Positioner Matlab commands. ...................... 153 GPIB Matlab commands. ........................ 154 Oscilloscope Matlab commands. ..................... 154 Calibration Matlab commands. ..................... 155 Pressure field measurementss Matlab commands. ........... 159 viii 1.1 1.2 2.1 2.2 2.3 2.4 2.5 3.1 3.2 3.3 3.4 3.5 3.6 3.7 LIST OF FIGURES Block diagram of the low frequency ultrasound phased array system. Low frequency ultrasound system including the water tank, hydrophone, positioning system, and driving electronics ................ Water tank. ................................ 80KHz transducer array. ......................... Transducer positions viewed from the top. ............... Transducer array X and Y axis definition viewed from the top ..... 3-D Positioning System with water tank and driving electronics. . . . Overview of the control system. ..................... USB interface schematic [14]. ...................... Block diagram of the AWG firmware. ................. Block diagram of the communications portion of the firmware. UART receiver reading word state machine. This state machine waits for a new word to start on the Rx signal, reads serial 8 bits into a register, and waits for the next word to start. ............. UART receiver reading word timing waveforms. ............ UART receiver new word available and sync state machine and timing waveforms. New-Word_Available is asserted after a new word is avail- able from the receiver state machine. The sync signal is asserted for on FPGA clock cycle after the start of a new word is detected ..... ix 10 11 15 17 19 20 21 22 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 UART transmitter sending word state machine. When SEND-WORD is asserted each bit of WORD_OUT is placed on the TX serial signal. UART transmitter sending word waveforms. This waveforms shows the timing of the TX signal with respect to the baud clock for sending the value 0x33 including the start and stop bits ............. Communications state machine. ..................... Memory addressing for the AWG. .................... BAUD clock state machine ........................ BAUD clock synchronization. ...................... BAUD clock synchronization waveforms. ................ DAC clock generation. .......................... Xilinx Spartan-3 memory structure [11]. ................ Memory structure with 2048 addressable 8—bit words per block of RAM in 16 blocks of RAM ............................ Xilinx memory schematic [11] ....................... Memory timing requirements for dual port read first [11] ........ Schematic for dual port read first operation [11] ............. Memory timing requirements for dual port write first [11]. ...... Schematic for dual port write first operation [11]. ........... Memory timing waveforms ........................ Memory schematic for channel 0. The same connections are made for channels 1—15. ............................... DAC timing requirements [13] ....................... AWG DAC timing waveforms ....................... Pulsed waveform and cycle padding .................... 24 25 27 28 30 32 33 35 36 37 38 39 40 41 42 43 45 47 48 50 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.37 3.38 3.39 3.40 3.41 3.42 3.43 3.44 3.45 3.46 3.47 3.48 3.49 Cycle padding waveforms. ........................ 51 AWG I/ O connector J3 [5] ......................... 53 AWG I/O connector J4 [5] ......................... 54 AWG I/ O connector J5 [5] ......................... 55 AWG 1/ O Connector J6 [5]. ....................... 56 16 channel DAC I/ O resources. ..................... 57 8 channel pairs DAC I / 0 resources .................... 57 DAC with Butterworth filter. ...................... 58 DAC simplified schematic ........................ 59 DAC circuit with stabilizing capacitor. ................. 60 Example of DAC instability for a ramp function input. ........ 61 Example of stabilized DAC for a ramp function input .......... 62 DAC output without filtering. ...................... 64 DAC output after 3rd order Butterworth filter .............. 65 DAC output after 5th order Butterworth filter .............. 66 Butterworth filter schematic ........................ 67 2-channel DAC layout. .......................... 70 6-channel DAC layout .......................... 71 2-channe1 DAC board. .......................... 72 2-channel DAC board. .......................... 73 Class A amplifier .............................. 75 Class B amplifier .............................. 76 xi 3.50 3.51 3.52 3.53 3.54 3.55 3.56 3.57 3.58 3.59 3.60 3.61 3.62 3.63 3.64 3.65 3.66 3.67 3.68 3.69 3.70 Class C amplifier .............................. 78 Complementary Pair Class B amplifier .................. 79 Class D amplifier .............................. 80 Class AB amplifier ............................. 82 Bridged amplifier topology ......................... 84 Darlington pair transistors [18] ..................... 85 Inverting amplifier design. ........................ 86 N on-inverting amplifier design ....................... 87 Amplifier layout. ............................. 88 Assembled amplifier. ........................... 89 Inverting amplifier topology. ....................... 92 Non inverting amplifier topology. .................... 92 Differential amplifier topology ....................... 93 Inverting amplifier 6 network. ...................... 94 Non inverting amplifier 6 network. ................... 95 Differential amplifier 6 network ...................... 96 Bode plot of [Adm] and g for different feedback networks and the corresponding plot of PM [21] ....................... 97 Bode plot showing the ROC of unstable amplifier ............ 98 Bode plot showing the ROC of a stabilized amplifier. ......... 98 Plot of the open loop Bode plot and 1/6 to determine the ROC of power amplifier ............................... 99 Amplifier output. ............................. 101 xii 3.71 3.72 3.73 3.74 3.75 3.76 3.77 3.78 3.79 3.80 3.81 3.82 3.83 3.84 3.85 3.86 3.87 3.88 3.89 3.90 3.91 Amplifier bode plot. ........................... 102 Channel 1 transducer impedance. .................... 104 Channel 2 transducer impedance. .................... 105 Channel 3 transducer impedance. .................... 106 Channel 4 transducer impedance. .................... 107 Channel 5 transducer impedance. .................... 108 Channel 6 transducer impedance. .................... 109 Channel 7 transducer impedance. .................... 110 Channel 8 transducer impedance. .................... 111 Channel 9 transducer impedance. .................... 112 Channel 10 transducer impedance. ................... 113 Channel 11 transducer impedance. ................... 114 Channel 12 transducer impedance. ................... 115 Channel 13 transducer impedance. ................... 116 Z-plane to Z-Smith chart mapping. ................... 118 Y—plane to Y-Smith chart mapping. .................. 119 Combined Y and Z Smith chart mapping. ............... 120 Effect of adding a capacitor or inductor in series or parallel with an impedance. ................................ 121 Arcs of constant resistance and conductance plotted through the start and conjugate desired impedances. ................... 122 Two possible paths on the Smith chart transforming impedance start to desired conjugate impedance. .................... 122 L-Network Topologies .......................... 124 3.92 L-network impedance matching on a Smith chart for R3 < RL. 3.93 L-network impedance matching on a Smith chart for R3 > RL. 3.94 Transformed start and load impedances on a Smith chart. ...... 3.95 L matching networks for the array transducers. ............ 3.96 Channel 1 matched transducer impedance. .............. 3.97 Channel 2 matched transducer impedance. .............. 3.98 Channel 3 matched transducer impedance. .............. 3.99 Channel 4 matched transducer impedance. .............. 3.100Channel 5 matched transducer impedance. .............. 3.101Channel 6 matched transducer impedance. .............. 3.102Channel 7 matched transducer impedance. .............. 3.103Channel 8 matched transducer impedance. .............. 3.104Channel 9 matched transducer impedance. .............. 3.105Channel 10 matched transducer impedance. .............. 3.106Channel 11 matched transducer impedance. .............. 3.107Channel 12 matched transducer impedance. .............. 3.108Channel 13 matched transducer impedance. .............. 4.1 Superimposed responses of each individually excited transducer with no time delay ................................ 4.2 Superimposed responses of each individually excited transducer with calculated delays. ............................. 5.1 Summed response of individually excited transducers and the response of all transducers excited. ........................ xiv 125 126 127 137 139 140 141 142 143 144 145 146 147 156 157 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.1 3 dimensional scan of the pressure field with no delays applied to the transducers. ................................ 163 Array focused at (0,0,-25). ........................ 165 Array focused at (0,10,-25). ....................... 166 Array focused at (0,20,-25). ....................... 167 Array focused at (0,30,—25). ....................... 168 Array focused at (0,40,-25). ....................... 169 Array focused at (0,50,—25). ....................... 170 Array focused at (0,60,-25). ....................... 171 Serial DAC I/ O resources. ........................ 173 XV Chapter 1 Introduction Cavitation is the generation of small bubbles in a liquid due to rarefraction [9, 16]. Cavitation has many medical applications such as non invasive surgery, tissue ero- sion, kidney stone disintegration and drug delivery [3, 2, 23, 20]. Since cavitation bubbles are generated during the negative pressure cycle, a longer period increases the chance for cavitation to happen and therefore lower frequencies should produce more cavitation at a given amount of power input from a transducer [9, 16]. This thesis describes a system that has been built to test and develop medical applications for cavitation. Some systems can produce cavitation at higher frequencies and without the abil— ity to adjust the output power [1, 8]. The electronics system described in this thesis has been designed to allow for the independent control of all transducers in the low frequency (80kHz) phased array, including the shape, amplitude and phase of the driv- ing signal. The electronics system was also designed for the readout of the resulting pressure field from the water tank. The low frequency ultrasound system is comprised of a transducer array and hy— drophone in a water tank, a computer, and several custom and commercial electronic subsystems. The system block diagram is shown in Figure 1.1. A picture of the system 1 is shown in Figure 1.2. The computer controls the electronics that drive the trans- ducer array, controls the position of the hydrophone in the water tank, and records the pressure reading from the hydrophone. A digital circuit stores digital waveforms in memory and outputs the digital waveforms and control signals to an array of digital to analog convertors (DACs), where the digital waveforms are transformed into ana- log waveforms. The analog waveforms are the input to an array of power amplifiers that drive the transducer array. A hydrophone is positioned at several points in the tank with a 3-D positioning system in order to measure the pressure throughout the water tank. At each point, the voltage waveform from the hydrophone is captured with an oscilloscope and read back and recorded by the computer. 00:550.. 35:03:30. 05.8. <23 fi 530.. 42.: 00 13.2039. 1.2.3 2.9.5 ‘ 23.9.52 ' Emma» Figure 1.1: Block diagram of the low frequency ultrasound phased array system. Figure 1.2: Low frequency ultrasound system including the water tank, hydrophone, positioning system, and driving electronics. Chapter 2 Water Tank and Ultrasound Phased Array The extent of the water tank is 380 by 380 by 470 mm. The water tank is shown in Figure 2.1. The transducer array is placed in the center bottom of the water tank. It is a 13 element spherically focused array as shown in Figure 2. The transducers are driven at 80kHz, which corresponds to a wavelength of 18.7mm in water. Each transducer is 40mm in diameter and they are spaced approximately 65mm from cen- ter to center. This spacing corresponds to a 3.5/\ spacing in water at 80kHz. The transducers are labeled as shown in Figure 2.3. A hydrophone is suspended in the water tank from a 3-D positioning system. The coordinate system is defined such that the X and Y axis are centered approximately above the center transducer. The Z axis is centered about 200 mm above the center transducer face. The X and Y axis definitions are shown in Figure 2.4. The positioning system can travel 200 mm in the X and Y direction and 300 mm in the Z direction. The resolution of the positioning system specified by Parker Hannifin is 200nm. The positioning system has a 195nm resolution. This was determined by instructing the positioning system to move 1,000,000 steps, measuring the distance travelled, and 5 dividing the distance travelled by 1,000,000 steps to determine the distance travelled in one step. The positioning system is shown in Figure 2.5. Figure 2.1: Water tank. (a) Transducer array viewed from the top. (b) Transducer array viewed from the bottom. Figure 2.2: 80KHz transducer array. O® 0 .® ®®®®O @ @ Figure 2.3: Transducer positions viewed from the top. .flflf\/\/\c Figure 2.4: Transducer array X and Y axis definition viewed from the top. to Figure 2.5: 3—D Positioning System with water tank and driving electronics. Chapter 3 Control The control circuit produces analog waveforms to drive the transducer array. The control portion of the system is made up of the following: a computer to define the waveforms, a digital circuit, called the arbitrary waveform generator (AWG), that cycles through the digital waveforms, an array of DACS that convert the digital waveforms into analog waveforms, and an array of matching networks and power amplifiers that drive the transducers. Figure 3.1 shows an overview of the control system. Ampllfler Array Figure 3.1: Overview of the control system. 11 3.1 Waveform Specification The computer interface to control the transducer array and transducer readout is implemented in Matlab ® . Arrays defining the waveforms are generated and sent to the AWG using Matlab m-files. The waveforms are stored in memory on the AWG and output to the DACs. 3.1.1 Commands Matlab M-files are used to store basic commands for the digital board. A list of these basic commands are shown in Figure 3.1. These commands read and write words from and to the AWG, setting the global and per-channel enable signals, and a command to define a wait period while cycling through values in memory. More complicated tasks can be created by calling these basic commands along with other Matlab code. These tasks include defining and programming some basic waveforms such as pulsed and continuous sine, ramp, square and triangle waves. A list of these complex functions are shown in Figure 3.2. [ Command [ Description write_word Write a single word to the AWG read-word Read a single word from the AWG set_enable_mask Enable any combination of channels set_global.enable Enable or disable all channels Pad.delay Set a time delay between cycling through digital waveforms stored in memory Table 3.1: Low level AWG Matlab commands. 12 [ Function LDescription program-pulsed_sine_wave program_pulsed.sine_wave _all_channels_cmdln program_pulsed_sine_waves _all_channels programsine_waves .all_channels pulsed _ramp-array pulsed_sine‘.array pulsed _square_array pulsed _tria-array ramp_array set.pad_delay sine-array square-wave_array tria_wave_array Program a pulsed sine wave to a specified channel Program a pulsed sign wave to all channels. This ver- sion is self contained and can be run from the com- mand line Program a pulsed sine wave to all channels Program all channels with a specified sine wave Compute a numeric array that defines a pulsed ramp Compute a numeric array that defines a pulsed sine wave Compute a numeric array that defines a pulsed square wave Compute a numeric array that defines a pulsed trian- gle wave Compute a numeric array that defines a repeating ramp Program the AWG with the pad time between cycling through values stored in memory Program a sine wave to a specified channel Program a square wave to a specified channel Program a triangle wave to a specified channel Table 3.2: AWG high level commands. 13 3.2 USB Interface A USB connection is used to communicate between the computer and the AWG. This makes connecting to the AWG easy since all modern computers have a USB port, so additional custom I/ O cards for the computer are not needed. A USB connection also allows for faster communication that a standard RS232 interface. A USB to RS232 converter is used on the AWG to simplify the USB implementation on the AWG. 3.2. 1 Software On the computer, the virtual comm driver from F TDI® is used to interface with the external hardware through the USB port [15]. The driver makes the USB port look like a standard serial communications port (comm port). This simplifies the program interface because the only commands needed are read from and write to a standard serial port. In Matlab, text strings are written to and read from a serial port. This is accom- plished with the scanf and printf commands by passing a handle to the serial port that is associated with the USB controller. 3.2.2 Digital Board The digital board uses an F TDI UM232R development board to convert between USB on the PC and RS-232 on the AWG digital board [14]. Figure 3.2 shows the schematic for the connection between the AWG and the FTDI UM232R development board. 14 <8 u w.m< I m< w363 00.335.03.030 U>...> .3030. .m 0.00: m w h m c a n S .W. 90.0 :00 00.0.. s Fl..l,| I :l I I. magma—5. .. .. l 0.00: . 0032.0. 00.5.0.5. U>0 0.00: Figure 3.3: Block diagram of the AWG firmware. 17 3.3.1 Communications The communications portion of the firmware communicates with the computer through the RS232 port. In the AWG, there is a receiver that triggers on new words trans- mitted into the serial port, converts them into an 8—bit parallel word and sends out clock signals to trigger and synchronize other parts of the firmware. The communi- cations portion of the firmware also has a transmitter that sends data back to the computer. There is a state machine that parses words from the computer and sets address lines and control signals for the internal memory and the DAC controller. The communications firmware block diagram is shown in Figure 3.4. Receiver The receiver portion of the firmware triggers on new words arriving on the RS232 interface, sends a synchronize signal to the clock generator when a new word starts, and converts the serial word into a parallel word. The state diagram for the receiver state machine is shown in Figure 3.5. The timing diagram for the receiver signals is shown in Figure 3.6. The transcoding of the serial word to a parallel word is performed in the communications state machine. The communications state machine waits for the start bit on the RX signal from the RS232 port, and when the start bit is detected, each subsequent bit is put into ascending bits of the received parallel word. After the bit 7 is read, the New_WordAvailable signal is asserted until the stop bit is detected, and the communications state machine starts over and waits for the next start bit. When the beginning of a new word is detected, the SYNC signal is asserted for one FPGA clock cycle in order to synchronize the external and internal baud clocks. The Baud_CLK signal is the internally generated baud clock. The discrepancy between the Baud-CLK timing and the RX signal as well as the need for the SYNC signal is described in Section 3.3.3. The New.Word_Available_AND_SYNC state diagram and signal waveforms are shown in Figure 3.7. 18 .3030. 0.00: 300022 — U>._.> 205. .20.... ><0..00.0 m<30333.n0 4.030.359. 0033.33.02.03 90.0 ....003.30 2030:0598 33533330399 ox>zzmrimz>mrmcmé or00>F01>zszmz>mrm -.] :mziimfimbr: — miamae. 0<0_.m-3meni3302|omr><§e Figure 3.4: Block diagram of the communications portion of the firmware. 19 ' WAIT_FOFl_ START__B|T RX=0 WAITING_FOR_ ',._ STOKE“ UART_RX_Reading_Word State Machine Transistions on BAUD_CLK edges X / x / WORD-OUT(0) = Rx bit-count = 0 bi t_count Z 7 Word_0ut(b1t.-count) = __ , bit_count = 0 READING_ WORD Word-Out(bit_count) = Rx bit_count < 7 bit_count = +1 Figure 3.5: UART receiver reading word state machine. This state machine waits for a new word to start on the Rx signal, reads serial 8 bits into a register, and waits for the next word to start. 20 w>COIOCA 03.0 m... .. m... N w... Q m... 0 m3. m w... m w 3. u mZD m... .. m M m m m W W W W W W m m wa>marm.4im.0 W W m M W W W Lm 0403-03.90 _Ill_.| Figure 3.6: UART receiver reading word timing waveforms. 21 New_Word_Available and SYNC State Machine unsure = WAITIORSTARTBIT Rx = 0 Transistions on New_Word_Available = 0 FPGA_GCLK SYNC = 0 rising edge WAITAFOFL START Rx = l New-Word.Available = 0 SYNC = l RD-STATE = WAIT_FOR.STARI[‘_BIT RD_STATE = WAIT_FOR_STOP_BIT New_Word Available = l SYNC=0 WAIT__FOR_END RD_STATE 72 WAIT_FOR.STOP_BIT / New_WordAvailable = 0 SYNC = o FPGA_GCLK RD_STATE WAIT_FOR_START_BIT BIT 7 WAIT_FOR_STOP_BIT WAIT_FOR_START_BIT Rx ] SYNC [ | New_Word_Available ] [ Figure 3.7: UART receiver new word available and sync state machine and timing waveforms. New_Word_Available is asserted after a new word is available from the receiver state machine. The sync signal is asserted for on FPGA clock cycle after the start of a new word is detected. 22 Transmitter The transmitter portion of the AWG firmware takes an 8—bit parallel word, serializes it, and sends it back to the computer by way of R8232 communication with the F TDI UM232R development board [14]. Figure 3.8 shows the state diagram for the transmitter state machine and Figure 3.9 shows the timing diagram for the TX signal. Once the SEND-WORD signal is asserted by the communications state machine, the transmitter state machine take WORD_OUT, serializes it, and puts each bit on the TX serial signal. A start bit is asserted before the data word, and a stop bit is appended after the word. 23 Tx = O SEND_WORD — 0 / Tx-CLK = O WAIT_FOR__ SEND_WORD SEND_WORD = 1 / Tx = 1 X Tx = 1 Tx-CLK = 1 Tx-CLK = O STOP_BlT UART_TX_SENDING_Word State Machine START_BIT Transistions on BAUD_CLK edges X b‘t—CO‘mt Z 7 Tx = woan_our(0) Tx = Word_Out(bit_count) Tx-CLK = 0 bit.count = O Tx-CLK = 0 SENDING_WORD . bit_count = +1 Tx 2 Word_Out(bit_count) bit-count < 7 / Tx-CLK = 0 Figure 3.8: UART transmitter sending word state machine. When SEND_WORD is asserted each bit of WORD_OUT is placed on the TX serial signal. 24 mo‘onve Figure 3.9: UART transmitter sending word waveforms. This waveforms shows the timing of the TX signal with respect to the baud clock for sending the value 0x33 including the start and stop bits. 25 3.3.2 Communications State Machine The communications state machine waits for commands from the computer, parses the commands, and sets internal control signals and address values. The communication state machine also sends words back to the computer. The state diagram for the communication state machine is shown in Figure 3.10. There are 9 commands that can be sent to the AWG. The commands are sum- marized in Table 3.3. Some commands require a single word, while others require additional words to be sent after the command. [Command(Hex) [Description [ Secondary Word [ Tertiary Word [ 4th Word ] 00 Reset 01 Start 02 Stop 03 Set Enable Mask Enable Mask High Enable Mask Low 04 Write Address High Address Low Data 05 Status 06 Read One Address High Address Low 07 Read All 08 Pad Cycle Pad Value Table 3.3: AWG command summary. The Reset command puts the AWG firmware into the startup state. This is the default state in case there is an error in communications. The Start command asserts the global enable signal. The Stop command deasserts the global enable signal. The Set Enable Mask command sets the enable mask on a per channels basis allowing for none, all or a subset of the channels to be enabled. When a channel is enabled, its memory contents are output to the DAC. When a channel is disabled, an idle value is output to the DAC. The Enable Mask is a 16—bit word; therefore, two 8-bit words must be sent from the computer to the AWG: Enable Mask High specifying bits 815 and a Enable Mask Low specifying bits 0—7. The Write command writes a word to an address in memory. There is 16k of addressable memory per channel; therefore, a 26 ‘H— .I he» . ) i. . 3003 <33 0:330 0.3m. $031.0? 003.3033 .uwaoi 003303.. <<33.m , 043cm g - . m0.l 00:00. . , . Emma . nmaol 030330. m033 . 0030.. <33. <33. 300312. , 00990.0 .000 .0. 0003 039.000 3.. 0.. 90330.0 Communications state machine. Figure 3.10 27 14 bit address is needed. The address format is shown in Figure 3.11. Bits 0—5 of the secondary command word sets bits 8-13 of the address. The tertiary command sets bits 0—7 of the address. The 4th command is the data word that is written to memory. The Status command sends the enable mask back to the computer. The Read One command reads one word from a specified address. Bits 0—5 of the secondary command word sets bits 8-13 of the address. The tertiary command sets bits 0-7 of the address. The Read All command sends all of the contents of memory back to the computer. The Pad Cycle command sets the delay time between cycles of outputting memory contents to the DACs. This is described in Section 3.3.5. ' ”WEE-.-.. u”..- . i x <15 - 0> , <2047 — 0> ’ r . "J. .-. ' 7' . AdQ‘QESSLZSDW .- . 2.. 7, . .. ._«.v-.., .. . . _ _,. - .. , -.. . . . -- . _ _ ,-._.._ »- . .. .. _. ,_ 1, _. ..... ‘_ ,_.._,...,. j ... . ' v' ‘4‘“ if”; "31* ~.:;‘.-: - ""3 ~ {uh-‘1‘- ‘ . I. - ' Jf' I'M-{kt . " 3......4'3- '_ ,7 , .‘1 .z .-‘ vn". 1':- “ . «Lea - 9 . ' :m- h; ‘-1 Rich-"'63. - .‘- - r. .L- .» 5‘ I . _ I... ~. - 1‘ . ‘ - . - I» . r5 .-.- 1 -.. ,, . ' ., ... _. .4 fl . . ‘» ‘ -__ j, <- .- . ~l., .. _ —_. ‘ . j . _ .‘ ~‘ ' . ~ 7mg"; ~- y 1.} '. . u C -. . ;' I ’ 'I‘ 4' nh‘m ] ‘ L " ‘ ’1 fllk' " L' -i' I - ' »-I' ' 'A’uuv ‘J‘J ..- a“! -‘ 1. :1) ”:13" | of L; ‘“ ”3'0" 7"" ‘1‘5' .‘ ' f. 4 u- 4" A — u: .- '.‘ ‘ ‘ ‘ , adress High . .--. .--—L. ...... .-..LL-I'..-._..-‘..- '__-.;-_‘.-._ A;.',_.-_.. .--. ..'-.J- \ \.. -_ - Figure 3.11: Memory addressing for the AWG. 28 3.3.3 Clock Generation The clock for the AWG firmware is the external 50MHz F PGA clock. It is used to generate the other clocks needed for the AWG. The other clocks generated are the BAUD clock for RS232 communication and the DAC clock used to update the DAC control and data signals. BAUD Clock The BAUD clock generation state diagram is shown in Figure 3.12. The BAUD clock is generated from the FPGA clock with a clock divider implemented with a counter. A desired clock rate and duty cycle are specified in the firmware code, and a roll over count is computed for the clock divider. The relation is shown in Equation (3.1). The Divider signal is how many FPGA clock cycles there are in one baud clock cycle. The High_Cycles signal is how many FPGA clock cycles the baud clock is to be asserted. The FTDI UM232R can have baud rates defined by the Equation (3.4) [14]. I nput_C lock_F req Dwzdcr‘ = BAUD_Rate (3.1) D' 'd _ .l High_Cycles : 2m er * Duty Cyc e (3.2) 100 (3.3) BR = 3000000 (34) n + :r n e [20, 214] (3.5) 1 1 3 1 5 3 7 $6 {0,-8-,Z’§,—2—’§,Z,—8-} (3.6) The counter increments until it reaches a value of Divider, then it resets to 0. The 29 BAUD_CLK is asserted when the counter is less than High_Cycles. If the count is greater than High_Cycles then BAUD_CLK is deasserted. The timing waveform for the BAUD_CLK is shown in Figure 3.12. BAUD Clock Generator BAUD Counter ”W CLK_lN . CLKJN Rising Edge ’ .. Rising Edge BAUDfiCLK = . NOT CLK70UT ”—0” = “‘9“ ‘ (3.33:3, ‘ ‘ CLK_OUT = Low BAUD Clock Generation BAUD_CLK Count 0 1 2 3 High Cycles - l Divider - 1 Figure 3.12: BAUD clock state machine BAUD Clock synchronization The FTDI UM232R has a reference clock of 48MHz, and the AWG has a reference clock of 50MHz [14]. This difference in clock speed can potentially cause a skew in the BAUD clocks in the UM232R and the AWG that would allow for a bit to be skipped. This is illustrated in Figure 3.13. In order to prevent a bit from being skipped, the clock edges of the two BAUD clocks on the FTDI UM232R and the AWG 30 are synchronized at the beginning of each word that is sent. This is accomplished with the SYNC signal from the receiver state machine that was described in Section 3.3.1. The SYNC signal is asserted for one FPGA clock cycle when a new word is received. This resets the internal BAUD clock so that its edges are coincident with the FTDI UM232R clock edges. The SYNC signal generation state diagram and timing waveforms are shown in Figure 3.14. The timing diagram for the synchronization is shown in Figure 3.7. 31 EEO 0.00:0 m<303qoafion .203 3009 0.. 0.. a. 0.. .33 w>c0i0rx 03.3 m: o m: . m: N m: a m... s m: m m: m m: u mzo w... 0: 3x 0 o o mzo 025 0.00.8 3o. 930333.000 5.02. 3003" o. 8.. 0. 0.93) m>co..0..x ma 3 mzo a? m: o m: . a: N m... 0 a: s m: m w: m m: u m: ....x Figure 3.13: BAUD clock synchronization. 32 m<20 4.3.3 .u.um>10.0..x mx m4>m4 mco 0.00: 030333.030: 3. ms: 0.. m: . w: o mCD 0.00: ...os. £30: mco 0.00: :63 £303 w333 0.63-9... _ _ 0354 0.3 0.3 _ Il— 0403 m.4 w.4 Figure 3.14: BAUD clock synchronization waveforms. 33 DAC Clock The DAC clock generation state diagram and timing waveform is shown in Figure 3.15. The DAC clock is generated from the FPGA clock using a clock divider im- plemented with a counter. A desired clock rate and duty cycle are specified in the firmware code and a roll over count is computed for the clock divider. The relation is shown in Equation (3.7). The divider needs to be calculated in two ways since Divider * Duty_Cycle / 100 produces a negative number for frequencies 1 Hz and lower because Divider * Duty-Cycle sets bit 32 of Divider high, which is interpreted as a negative number. The sign is preserved when the next operation, divide by 100, occurs. If the divide by 100 operation is performed first, bit 32 is never asserted and the result is never considered negative. This does not work for frequencies less than Input_Clock_Frequency*100 because Divider/ 100 < 1, which is rounded to 0. Then, High_Cycles is 0, and the clock never changes. I nput-Clock_F req D' 'd = .7 2m er OutpuLFreq (3 ) D t _ l High_Cycles = Divider * #Ogy—C—e- (3.8) D' 'd HighL‘ycles = 2:30” * DutyL‘ycle (3.9) 34 00:38. mvm>|00rx mafia mama 00:2 A 0?qu L 095. n 00:3 + A OCA10_< 0:65 05% 03068. mvo>lmorx 2min mamm 09:: Au 16:90.8 L 9x52 Au :6: OEAuDZ An roé III_ 09:: o A m w mvo>100rx Egg I6: 923 . A Ll UZEQ - A Figure 3.15: DAC clock generation. 35 3.3.4 Memory The Xilinx Spartan 3 XC400 FPGA that is on the MEMEC Spartan-3 LC Devel- opment Kit has 16 RAM blocks that each have 16Kb of addressable data [11]. One block of RAM is used to store the digital waveforms for a given channel. Each block of memory can be configured for a different number of addressable words of differ- ent lengths as shown in Figure 3.16. The memory organization chosen for the RAM blocks is 2K words by 8—bits. Since the DACs inputs are 8—bit numbers, each address stores one value that is output to the DACs. Two bytes are needed in order to address the words in each channel. Eleven bits are needed to address a word in the block of RAM, and four bits are needed to select the block of RAM for desired channel. Figure 3.17 summarizes the memory block organization. Total RAM bits, including 18,432 (16K data + 2K parity) Parity Memory Organizations 16le 8Kx2 4Kx4 2Kx8 (no parity) 2Kx9 (x8 + parity) 1Kx16 (no parity) 1Kx18 (x16 + 2 parity) 512x32 (no parity) 512x36 (x32 + 4 parity) 256x72 (single-port only) Parity Available and optional only for organizations greater than byte—wide. Parity bits optionally available as extra data bits. Performance 240+ MHz (refer to individual FPGA family data sheet) Timing Interface Simple synchronous interface. Similar to reading and writing from a register with a setup time for write operations and clock-to-output delay for read operations. Single-Port Yes Figure 3.16: Xilinx Spartan-3 memory structure [11]. 36 RAMB16_SQ 2048 8-bit words Channel 7 Word Figure 3.17: Memory structure with 2048 addressable 8-bit words per block of RAM in 16 blocks of RAM. Each memory block is implemented within dual port memory with independent address, enable, and clock signals. The schematic for the memory block is shown in Figure 3.18. For the AWG firmware, Port A is used to write values for the DAC . waveforms into memory and to output the contents of memory back to the computer via the communications state machine. Port B is used to output the waveforms to the DACs from the contents of memory, where the input to Port B is not used. There are two read/ write modes for the Xilinx memory that were utilized in the AWG firmware: read first and write first. Write first is used on Port A because the new values being written into memory are also ouptut to the DACS. Read first is used on Port B because the input to Port B is not used and the contents of memory are always the source of the output. The memory timing requirements specified by Xilinx for dual port read first are shown in Figure 3.19 and the schematic is shown in Figure 3.20. When Write Enable (WE) is low, ENABLE is asserted, and there is a rising Clock (CLK) transition, data is read out from the specified address and the data input (DATAJn) is ignored. When WE is high, ENABLE is high, and there is a rising edge on CLK, Data_in is stored at the specified address and the old contents at that address are output to Data_out. The memory timing requirements specified by Xilinx for dual port write first are shown in Figure 3.21 and the schematic is shown in Figure 3.22. When WE is low, ENABLE is asserted, and there is a rising CLK transition, data is read out from the 37 WEA ENA SSRA CLKA t V V ADDRA[rA—1 :0] D|A[wA—1 :0] DIPA[3:O] WEB t ENB SSRB CLKB ii if ADDRB[rB—1 :0] DIB[wB—1 :0] DIPB[3:O] "V RAMl 6_WA_WB DOPA[p —1:O] A > DOA[wA—1 :0] > DOPB[p 4:01 B) DOB[wB-1 :0] > (a) Dual-Port Figure 3.18: Xilinx memory schematic [11]. 38 XW‘. / llll ! ixw' x Xm: .\ ’ r |G=9nfiu~1no cnfiau GIDHEWW‘ei}I{ f “-np x100: Figure 3.19: Memory timing requirements for dual port read first [11]. 39 Data_in —> —> Data_out WE —-> EN ——> CLK ——> > Address —T[ RAM Location WRITE_MODE = READ_FIRST Figure 3.20: Schematic for dual port read first operation [11]. specified address and Data_in is ignored. When WE is high, ENABLE is high, and there is a. rising edge on CLK, Data_in is stored at the specified address and is output to Data_out. The timing waveforms generated in the AWG memory operations are shown in Figure 3.23. The address and data signals are set in the communications state machine for a write cycle. The enable signal is asserted, and one FPGA clock later, the write clock (WE signal) is asserted for one FPGA clock period. On the following rising edge of the FPGA clock, the memory at the address specified is changed to the new data. The overall schematic for the memory interface is shown in Figure 3.24. Port A is used for read and writing information to memory from the computer via the communications state machine. Port B is used to output the contents of memory to the DACS. 40 l I ltlt X X Kim in X )L‘W! “-m was (99me w J Figure 3.21: Memory timing requirements for dual port write first [11]. 41 Data__in >- —>— Data_out WE ———> EN ———>~ CLK ———> > Address . RAM Location J WRITE_MODE .-. warre_l=|nsr Figure 3.22: Schematic for dual port write first operation [11]. Port A: Computer Read and Write The clocks that are fed into the blocks of RAM are the 50MHz FPGA_CLK attached to RAM block port CLK and the write clock (WR-CLK) attached to RAM block port WEA. The FPGA clock clocks both read and write actions and the WR_CLK clock selects a read or write cycle for Port A. The address in (ADDRJN) is a 15-bit address that specifies which channel (block of RAM) to program and which word in that block of RAM to read and write. The 4 highest bits (ADDRJN(14:11)) select which block of RAM is being addressed. They are passed through a 4:16 decoder to assert a single enable signal (ENA) to one of the blocks of RAM. The lower 11 bits (ADDRJN(10:O)) are passed to ADDRA to specify which word in the block to address. The data input (DJN) is an 8-bit word that is passed to DIA of each block of RAM as shown in Figure 3.24. Data parity is not used so port DIPA is held high [11]. Port A is not considered in a reset operation because its output goes to the transmitter and not to the DACs so SSRA is set low. 42 226 96.6 Dome 966 0.3. g goo. mg mz L m mz Em Em U >34 X >69 X D. Vb DOE ivA 2.6302 dvq 063638. Figure 3.23: Memory timing waveforms 43 Port B: Computer Read and Write The global enable (GlobaLEnable) and per channel enable (Per_Channel_Enable) sig- nals allow the memory contents to be output to the DACs when asserted or output a predefined constant value when deasserted. The global enable and per channel enable signals are AN Ded together and fed to SSRB for each block of RAM. If the global enable is low or the per channel enable for that block of RAM is low, the SSRB is low and the SSRVAL specified in the VHDL code is output to the DAC. Otherwise, if both are asserted, then SSRB is high and the contents of that block of memory are output to the DAC. The DAC clock signal is fed into the CLKB port of each block of RAM. The clock period is defined by the timing requirements of the DACs and is discussed in Section 3.3.6. The address out signal (ADDR_OUT) specifies which word in memory is output to the DACS. The bus select out signal specifies if even or odd channels are updated during the current memory cycle. The motivation for multiplexing between even and odd channels is discussed in Section 3.3.6. Since Port B is used only to output the memory contents to the DACs, write actions on Port B are disabled, and Port B is always set to read. This is done by setting WEB to low and ENB high. DIB is also held high in order to prevent the data inputs from floating. Data parity is not used so port DIPB is held high. 44 0:88 s63 .83 and 2 3 0:256. 0 039336."... $5-0; _IIIV _ £m> 6032 663-2293 . mz> mimanmoumo 602.8. o>4>uosno mm?» 3.6 98 o>4>noSL 95.2 “V ~98 .33 noon . 6-03-239 >663 .239 H _ 669.2299 6323.2 629.05.: .. . 05 so o>q>uoccm 61.2an ”V o_o_>_o__ o2; .....— 68:05:93 23 60622 mzm so; m. 60632 analogue or0m>rnmz>mrm' V. mmmm 65,18: mmnwmmnnumr ' V . _ 0:6 m 6-05-233 05-05 NY 63285. 3:65.: mcm 9a 0.23. o>a>uoSL m 663-93390 mchOSIw¢_oQ 0 0:88 563 :03 oloo_0ox O>O 30302 >383 Ocnimcmlmmaofi U>OIZ03IO=AIOS 450302102905 028 95 rmnozmonv Omfiv U>O 58:33 U>O 58: 0032.08 mwammumm _ 4 it? _ _ _ _ _ 4w .3 4m 0 A Mwhmmumo Figure 3.26: AWG DAC timing waveforms. 48 Figure 3.27 shows a pulsed waveform repeating. The maximum time between a pulsed wavefrom is 655/13 because there are 2048 words per channel in memory and the DACs values are updated by cycling through the words every 320ns, where 320ns*2048 = 655us. If more time is required between pulses, then a wait time between cycling through values in memory is added. This added wait time is the padding. This padding is accomplished by adding a programmable counter into the address count. The counter increments in time units of 655/13, or increments of memory cycle time. This is shown in Figure 3.27. The memory timing waveforms are shown in Figure 3.28. There is a master count that increments every FPGA clock cycle (20ns). There is a cycle count that increments every 16 FPGA clock cycles (320ns). This count generates the DAC memory clock. The DAC address updates every 320ns as well. The DAC address cycles from 0 to 2047. After cycling through all the DAC addresses, the master count is reset and held constant, the DAC address stops incrementing and the DAC memory clock stops pulsing. The pad count then starts incrementing to a programmed count. After the pad count stops, the pad count resets, the master count starts incrementing again, the DAC memory address starts incrementing, and the DAC memory clock starts pulsing again. 49 mam c0 30x 000200: All 00.000 30x 0:0 .0 l1 30302 000.: ..3..0..0: —lli <0..._00 .0 30302 Li 00:30“ iv- 320000 00.02 000200: 00.000 02 Al 0000.00 030 00.200: 00.000 02 020.30 36:00 $0.50 .0 30302 2:... 0 000304 V Figure 3.27: Pulsed waveform and cycle padding. 50 All 000 0003010030300 _ 39.83. ELICICIE _ _ _ .0040300.Iz.0302|>004000 3008410000. 022010000. 000400010003 000:0003 o o o mmumw wmumh wmwmm wmumm wmwmu o o o o o o o o o o o o 0000.10.06? 320300.:30302100000 2.0302 00.000 520303.00 _ _ 2006410000. _ o . m w 0 m m wmumo wmum. wmvmm 0300 wmwmn wwumm unumm wmumu _ 020.0I00c0. _ o . m w a m m m m .o .. .m .w .3 .m _ O O 0 006001080. " 0 o o o o o o 003 003 003 003 003 003 003 003 “ 000:0003 _ o o o o o o o o o o o o o o o _ A 000 0000.04 50303.00 s28... g .020300.I.,._0302I>00q000 2.0080003. 0290:0000. >00800|0003 00010003 0000 4000 N000 00000 #000 01000 03000 \1000 0000 (0000 Figure 3.28: Cycle padding waveforms. 51 3.3.6 I/O There are 97 10 pins available on the headers of the MEMEC Spartan-3 LC Develop- ment Kit using the P160 Proto Board [5]. The headers on the P160 Proto Board are standard 40 pin dual row with one—tenth inch spacing. The pinouts and associated FPGA pin nets are shown in Figures 3.29 - 3.32. The required signals for the AWG design are the following: communications signals TX, Rx, CTS, and RTS, and DAC signals for 16 channels. The signals needed per channel are: Data(7:0), WR_B, and (38.3 If each DAC is updated independently and simultaneously, then 164 signals would be needed. This is summarized in Figure 3.33. If 2 DAC channels are updated serially, then they can share a common data bus and 8 8-bit data busses would be needed instead of 16 8-bit data busses, reducing the needed I/O lines by a factor of 2. 92 10 pins are needed to implement this arrangement, which is summarized in Figure 3.34. This arrangement would minimize the time between DAC updates by allowing for parallel updates to happen between 8 DACs at a time while reducing the number of pins needed by sharing a data bus between 2 DACs and satisfying the I / 0 pin constraint. 52 A 3.3V 2.5V A J3 3 4 RIOA1 0— 5 6 — RIOAZ 0— 7 8 —OLIO.Bs Lion 0— 9 10 —OLIOB10 LIO.B11 u0320 norm 0- 21 22 —OLI0322 Lions 0— 23 24 —OL101324 LIOBZS 0— 25 26 -°LIOBZB LIO.BZ7 0— 27 28 *—OLIO.m Lion. 0—29 30 —Ou01330 LIOBB1 0— 31 32 -OLIOB:32 LIO.BB3 0— 33 34 —OLI0534 LIO.B35 0— 35 36 —OLI0336 LIO.B37 0—37 38 —°UOB38 LID.” 0—39 40 ‘—®LIO.B40 CON2X20 33 user signals 3 channel pairs Figure 3.29: AWG I/O connector J3 [5]. 53 CON2X20 A 3.3V 2.5V A A J4 3 4 —ORIOBZ TCK 0—5 6 —OLIOA9 TDO ”—7. 8 -UOA11 TDI 0—9 10 —OIJOA13 TMS E 11 12 -<3>LIOA15 FPGABrTSTREAM ”—13 14 ‘—°LIOA17 SMDOUT/EJSY 0—15 16 —OLJOA19 FPGA.CCLK ”—17 18 —OUOA21 DONE l>-19 20 —®UOA23 lNlTn 0—21 22 -OLIOA25 PROGRAMn ”—23 24 —OLJOA27 ‘25 26 —OLIOA29 27 28 —OUOA31 29 3O *—OIJOA33 31 32 —®LIOA35 33 34 —OlJOA37 35 36 —OIJOA39 37 38 —ORIOA39 39 4O ‘—ORIOA40 19 user signals 1 channel pairs Figure 3.30: AWG I/O connector J4 [5]. 54 VIN 19 user signals 1 channel pairs Figure 3.31: AWG I/O connector J5 [5] 55 VI 2.5V RIOA4 RIOAB RIOAB RIOA1O RIOA12 RIOA14 RIOA16 RIOA18 RIOAZO RIOA22 RIOA24 RIOA26 RIOA28 RIOABO RIOA32 RIOA34 RIOA36 RIOA38 2 3.3V r 4RIOA3/USEFLED 8 4RIOA5 9 1 0 ”RICA? 1 1 12 —°RIOA9 1 3 1 4 4RIOA1 1 1 5 1 6 4RIOA13 1 7 1 8 4RIOA15 1 9 20 —ORIOA1 7 —ORIOA19 23 24 4RIOA21 25 26 —°RIOA23 27 28 4RIOA25 29 30 —ORIOA27 31 32 "—ORIOAZQ 33 34 4RIOA31 35 36 4RIOA33 37 38 ”RIOABS 39 40 —°RIOA37 CON2X20 iiiiiiiiigiiiiiiii 36 user signals 3 channel pairs Figure 3.32: AWG I/O Connector J6 [5]. 56 16 Independent DAC Channels Function Signal Per Channel Per Chip RS-232/USB ’ ’ ' " ‘ " Figure 3.33: 16 channel DAC I/O resources. 8 Channel Pairs Function Per Channel Per Chip RS-232/USB " '. , ~~ has, DAC - . 'v | ~ .~ 1 ' "‘ . ‘ ‘ V, t ‘~ T7, 7, 1M)"; ' 7' I , ), ‘ l 0 ~ 1 , . n x 1' V I. ‘ l r - > .r . ,’ , . ' ,—‘ . ‘ I , f I ' ». 7-."‘ T ’ . ‘fi . i . . , , . Figure 3.34: 8 channel pairs DAC I/O resources. 57 3.4 DAC Board 3.4.1 Digital to Analog Converter The Digital to Analog Converter (DAC) converts 8—bit words from the AWG to analog voltages. There are 16 channels in the DAC array. As described in section 3.3.6, 2 channels share the same data bus. A DAC channel consists of a DAC circuit followed by a Butterworth filter to reduce ringing in the output. Figure 3.35 shows the DAC circuit overview. The DAC circuit consists of a Texas Instruments TLC7254 8—bit DAC chips and an op-amp. The Butterworth filter is implemented with 3 op—amps and several resistors and capacitors. Noisy Filtered . . A 1 [its ...... an: 8 bit DAC Output Buttemorth Filter Figure 3.35: DAC with Butterworth filter. Theory of Operation The DAC circuit functions as an inverting amplifier as shown in Figure 3.36. The TLC7254 varies the resistance Rim, a resistor between a constant reference voltage, and an output pin attached to ground. This varies the current flowing through Rim and the feedback resistor R fb and in turn the output voltage. The output of the DAC is hooked up to the negative input of an op-amp with the positive input attached to ground. This provides the ground reference for Rdnt- The output of the op—amp is fed back to the DAC, where an internal resistor connects it to the current output of 58 R fb- In this configuration, the DAC and op—amp form an inverting amplifier with a constant input voltage and a variable gain. The transfer function of the amplifier is be Rint Vout = _Vref * . (3.10) The resistance Rint is controlled by the digital input. A negative voltage reference is used so that the output varies from 0V to [16ml . A potentiometer is placed in series with Vint to provide an output range calibration. The potentiometer can increase the resistance between Vint and ground, changing Rim in the transfer function and thus changing the gain and output voltage range. f— + Vout Figure 3.36: DAC simplified schematic 59 Stability The output of the DAC circuit was initially unstable because of the high bandwidth of the op—amp. The unstable output is demonstrated in Figure 3.38. A pole was added to the transfer function by adding a 2pF capacitor between the op—amp output and the negative input as shown in Figure 3.37. The stabilized output is shown in Figure 3.39. | _________ TLC7254 I I 1 Fixed I l _E— + Vout Figure 3.37: DAC circuit with stabilizing capacitor. 60 9— a— (Slewu o r01- 0'! Voltage(V) 9... €— 8" L 0 L 3 8 V _ ,, , Figure 3.38: Example of DAC instability for a ramp function input. 61 Voltage(V) GI ('11 L do .1; L o l I l I I Figure 3.39: Example of stabilized DAC for a ramp function input. 8— (s)eun_|_ 0 I OL 62 3.4.2 Output Filter The output of the DAC contains a significant amount of ringing. The ringing is shown in Figure 3.40. A filter was added after the DAC circuit to reduce the ringing on the output. The filter chosen was a Butterworth filter because of the balance between the filter cutoff and step response [21]. A cutoff frequency of 200Hz was chosen and the component values were scaled by 100. A fifth order filter was implemented because a 3rd did not reduce the ringing to less than 15mV. The filtering result with a 3rd order filter is shown in Figure 3.41. The filtering result with a 5th order filter, implemented by cascading 2nd and 3rd order filters, is shown in Figure 3.42. A lookup table was used to determine the values of the components. The schematic for the filter is shown in Figure 3.43. The calculations for the capacitor values are as follows: Cl 2 100* 2:1;22 20063 2 13'9579"F 02 = 100*?)31220083 =10.7748nF C3 = 100 * 2:27;; 200e3 : 3'3534nF C4 =100*%l§38§20063 =25.7433nF C5 = 100 * 2.»: 7r * 200e3 = 2458”]: The closest standard values for the capacitors are listed in Table 3.4. 63 (3.11) (3.12) (3.13) (3.14) (3.15) (3.16) Voltage(V) .5 o -* N so I 01 O 01 -* 01 N 01 GD 01 “‘ I r I I I I l I b _ I .0 _ O) I _o _. A I .o I— m d 3 o — in: .0 _ N .0 ._ .k 0 '0) I" .0 _ m —L o c'» _. L Figure 3.40: DAC output without filtering. 64 Voltage(V) 9'0 —l -‘ 01 N I I I 9'0- l— (S)8U.l!_|_ 0 3'0- 7‘0- 9'0- 8'0- l l T l 30 I 7'0 8'0 g_0I Figure 3.41: DAC output after 3rd order Butterworth filter. 65 9'0- L— Voltage(V) 9'0 170" 9'0“ 8'0- 3'0- 8'0 7'0 9'0 8'0 g_0I I (S)ewu o I Figure 3.42: DAC output after 5th order Butterworth filter. 66 10nF ll IF C1 100 100 100 «gr—W 'wv—o—Ivv» + R1 R2 R3 Vin ”- _- - § ::8 . __8 / 33nF 22nF II II C4 100 100 ’VVV—“JVVV + R4 R5 - V + u_____ __ (S __3 Vout Figure 3.43: Butterworth filter schematic. 67 I Capacitor I Calculated IStandard I C1 13.9579nF 10nF C2 10.7748nF 10nF C3 3.3534nF 3.3nF C4 25.7433nF 22nF C5 2.4581nF 2nF Table 3.4: Butterworth filter standard capacitor values. 68 Implementation The DAC board schematics were captured using Cadence® design tools. The design was implemented in a hierarchical fashion in order to be able to reuse as much work between the channels as possible. The hierarchical design meant that the schematic for the DAC and Butterworth filter only had to be entered once and instanced for each channel. It was also possible to reuse or copy the layout of the first channel for the remaining channels. The DAC circuit boards were designed to fit in a rack mount cage that had 6.25 inch tall slots. Only 6 channels could be fit into this space, therefore two boards were designed: a 2—channel board that utilized the connection to the AWG with connectors J4 and J5 since they had only enough pins for one channel pair each, and a 6-channel board that utilized J3 and J6 on the AWG because those connectors had enough pins for 3 channel pairs each. The layout of the 2-channel DAC board is shown in Figure 3.44, and the layout for the 8-channel DAC board is shown in Figure 3.45. The assembled 2—channel board is shown in Figure 3.4.2, and the assembled 6-channel board is shown in Figure 3.4.2. 69 06001 , 7 I W 7, 0000? l O Figure 3.44: 2—channel DAC layout. 70 Figure 3.45: 6—channel DAC layout 71 (a) 2-channel assembled DAC board viewed from the top. (b) 2—channel assembled DAC board viewed from the bottom. Figure 3.46: 2—channel DAC board. 72 (a) 6—channel assembled DAC board viewed from the top. (b) 6—channel assembled DAC board viewed from the bottom. Figure 3.47: 2-channel DAC board. 73 3.5 Amplifier The power amplifier takes the signal from the analog output of the DAC and provides a voltage and current gain so that the output of the power amplifier can drive up to 25W into a 5052 load. 3.5.1 Types of Power Amplifiers There are many different types of amplifiers with tradeoffs between signal integrity, efficiency and design complexity. The amplifier types are summarized in Table 3.5. I Class I Complexity I Signal Integrity IEfficiency I A Low High Low B Low Low Medium C Low Low High Complementary Pair B Medium Medium Medium D High High High AB High High Medium Table 3.5: Amplifier classification summary. Class A amplifiers are simple with great signal integrity but poor efficiency. They have good signal integrity because they pass the whole signal without the transistor changing its region of operation. Class A has poor efficiency because the transistor is biased so that it stays on when there is no signal. A Class A amplifier is shown in Figure 3.48. Class B amplifiers are as simple and are more efficient than Class A but have poor signal integrity. Class B amplifiers are simple because have the same components as Class A. The difference between Class A and B amplifiers is how the transistors are biased. Class B are more efficient than Class A because when there is no signal the transistor does not draw any current. Class B has poor signal integrity because it only passes half of the input signal. A Class B amplifier is shown in Figure 3.49. 74 PPA inoA G > Figure 3.48: Class A amplifier. 75 Figure 3.49: Class B amplifier. 76 PP/\ Class C are as simple as the Class A and B amplifiers with high efficiency and poor signal integrity. Again, the difference is how the transistor is biased. They are similar to Class B in that they turn on when the input exceeds a certain threshold voltage. They pass less than half the input signal so their signal integrity is poor. They have high efficiency becasue they pass so little of the input signal. A Class C amplifier is shown in Figure 3.50. A Complementary Pair Class B amplifier design is more complex than a Class B but has similar efficiency and improved signal integrity. A Complementary Pair Class B amplifier consists of two Class B amplifiers placed in series between the power supplies. One amplifier passes the positive half of the signal and the other passes the negative half of the signal. Ideally, the two amplifiers would pass exactly half of the input signal, but because of the voltage needed to turn on transistors, there is a dead zone around zero input where neither amplifier follows the input. This effect is known as cross over distortion. This can be minimized with providing high gain feedback from the output of the amplifier to the input. This reduces the input voltage range that causes no change at the output. A Complementary Pair Class B amplifier is shown in Figure 3.51. Class D is a complex design with good signal integrity and efficiency. Class D uses the concept of pulse width modulation. The output transistors pull the output to Vsupply or 0V. The output is averaged over time, so for a higher signal, a higher duty cycle is used. Likewise, for a lower output value, a lower duty cycle is used. The output needs to be filtered in order to average the signal and to eliminate the undesired higher frequencies that arise from switching. A Class D amplifier is shown in Figure 3.52. Class AB is a complex design with good signal integrity and efficiency. Class AB is a combination of Class A and Class B. Class AB is a complementary pair configuration where one amplifier drives the output when the signal is positive and 77 T JHOA C Figure 3.50: Class C amplifier. 78 PP/\ ID—p7x T lflOA C Figure 3.51: Complementary Pair Class B amplifier. 79 498A dwog Jegng w Figure 3.52: Class D amplifier. 80 _l.:__ the other drives the output when the signal is negative. Both amplifiers conduct a small amount of current when there is no signal. This eliminates the cross over distortion but decreases the amplifier efficiency. Also, a Class AB amplifier needs a biasing network that dissipates additional energy. Since Class AB is a linear amplifier and not a switching amplifier like Class D, there is not any switching noise that needs to be filtered. A Class AB amplifier is shown in Figure 3.53. 81 .|I_o PPA PPA Figure 3.53: Class AB amplifier. 82 3.5.2 Amplifier Design A Class AB amplifier was implemented because of the improved signal integrity with moderate efficiency and design complexity and the lack of harmonic noise from a switching design. The load is assumed to be 500 and the largest desired output is 25W when driven by a continuous sine wave. In order to get 25W out of 509, a 70Vrm3 or 100Vpk—pk sine wave is needed. In order to maximize the voltage output, two amplifiers are connected together in a bridge topology instead of a single ended configuration. This topology in shown in Figure 3.54. Instead of attaching one side of the load to ground, one amplifier output is attached to one side of a load and another amplifier, with a gain of -1 relative to the first amplifier, is attached to the other side of the load. This allows for twice the voltage to be applied across the load for a given power supply voltage and eliminates any DC offset on the output. Each of the amplifiers has two parts: a voltage gain stage and a current gain stage. The voltage gain stage amplifies the input voltage, where the input voltage is at most 1Vpk—pk- In order to obtain a 100Vpk—pk output across the load, each amplifier in the bridge must produce 50Vpk—pk- With an input of IVpk-pk’ a gain of 50 is needed to produce 50Vpk—pk- An op-amp is used to provide the voltage gain because op—amps are inexpensive and small , and they admit straightforward designs. The OPA552 is chosen because of its availability, cost, and performance. It has a bandwidth of 12MHz, a large supply voltage range of :tBOV, a large output current, and an available spice model. The large bandwidth facilitate the design of this 80kHz amplifier. The large supply range makes a 100Vpk—pk output possible, even with dropout voltage across the op—amp and output transistors, and the ability to simulate the circuit in Spice allows for fast design refinement with fewer design cycles. The current gain stage consists of a biasing network and a complimentary pair of 83 1110A Figure 3.54: Bridged amplifier topology. 84 power transistors. The biasing network makes the amplifier Class AB. The network biases the output transistors so that each transistor is conducting a small amount of current when the input is 0V. This configuration consumes energy all of the time, even without a signal, but signal distortion is minimized. The output transistors, MJH11021(PNP) and MJH11022(NPN), are a complimentary pair of Darlington BJTs. The complimentary pair aspect of the transistors means that they have similar characteristics, such as base-emmitter on voltage (VBE_0,,) and current gain, so they can be easily used in a complementary pair topology and the waveform will still be symmetric. The Darlington aspect of the BJTs means that two BJTS are cascaded as shown in Figure 3.55. This increases the current gain dramatically, which is needed in a power amplifier. The output of the op—amp can supply 200mA of current. The current needed for a 50V signal across a 509 load is 1A, therefore a current gain of 5 is needed. This is well within their minimum rated AC current gain of 75. PNP NPN L---- L-—--J Figure 3.55: Darlington pair transistors [18] The complete amplifier design for the inverting amplifier is shown in Figure 3.56 and the non-inverting amplifier is shown in Figure 3.57. The amplifiers are attached to the load as shown in Figure 3.54. The layout of the amplifier is shown in Figure 3.58. The assembled board is shown in Figure 3.59. 85 1k I R11 + l S 2.2k 1k 2.2k 1k 5 R7 R6 R5 2.2k 2.2k # R8 100nF 100nF R3 | I C3 C2 :I 7 1 1 < 0‘ 0 o o. ‘” "’ R10 R9 -' Q ¢ Figure 3.56: Inverting amplifier design. 86 )I117 3 I I :1001 [H W >11 - + II I—o 3 o + I E 2.2k 1k 2.2k 1k 3 if}. R7 R6 R5 R4 2.2k 2.2k R8 100nF 100nF R3 1 D—l l—fl C3 C2 In 0 1 1 o E V' N R10 R9 ‘ ‘1 I I I—0 g< + Figure 3.57: Non-inverting amplifier design. Figure 3.58: Amplifier layout. 88 Figure 3.59: Assembled amplifier. 3.5.3 Stability Circuit stability is analyzed using Rate of Closure (ROC) [21] which predicts the stability of an amplifier from inspecting the open loop gain of the amplifier and the gain of the feedback network. The transfer function of an op—amp circuit with feedback is shown in Equation (3.17). = K— (3.17) K is the ideal gain. The values of K for different topologies are shown in Table 3.6. The op—amp topologies are shown in figures 3.60 - 3.62. The error multiplier (EM) is defined in Equation (3.18). EM = ———1—— (3.18) 1 1 + Adm:8 Adm is the open loop gain of the op—amp. fl is the gain of the feedback network from the output of the op—amp to the input terminals of the op-amp as shown in figures 3.63 - 3.65. 6 is defined for each topology in Equation (3.19). _K2__ 21 _Vl—Zl-I-ZQ (3 (3.19) The term Admfi is the loop gain G. The phase margin (PM) is defined as 180° — ZIG I at the frequency fc where |G| = 1. If PM S 0° then the amplifier is unstable. If 0° < PM < 45° then the amplifier is marginally stable. If PM 2 45° then the amplifier is stable [21]. 1 3 decrease PM by 90°. Each pole of Adm changes the PM can be predicted by inspecting the magnitude Bode plots of Adm and . Each 1 ’6 1 slope of the magnitude Bode plot of Adm by —200 and each zero of 3 changes the pole of Adm and and zero of 90 l r3 of the magnitude Bode plots of Adm and g— at fc will determine how many poles and slope of the magnitude Bode plot of by +200. Taking the difference in the slopes zeros and are in Adm and % up to fc and determine PM. This difference is the ROC and is shown in Equation (3.20). Figure 3.66 shows an example plot of IAdmI and % for different feedback networks and the corresponding ROC and PM values. An example plot for an unstable amplifier is shown in Figure 3.67 and Figure 3.68 shows the Bode plot for a stabilized amplifier. An amplifier is stable if ROC < 40dB/dec because PM 2 45° [21]. ROC = slope 1 — —slo-eA fiI pl dmI 1 (3.20) Evaluated at fc —+ IAdmI = IEI Topology Ideal Gain(K) Inverting :Z—Zlg Non inverting 1 + Q Zr Z Differential E:— Table 3.6: Ideal gain of common op—amp topologies. The ROC for the designed amplifier is 20dB/dec and is shown in Figure 3.69. 91 r——I L_F ZI G—CZI—O— - .I. Vin + Figure 3.60: Inverting amplifier topology. Vout Figure 3.61: Non inverting amplifier topology. 92 Vout Figure 3.62: Differential amplifier topology. 93 I___l 21 T + I + Vout Z2 0 + V2 21 V1 c - Figure 3.63: Inverting amplifier 6 network. 94 Vout V2 21 V1 Figure 3.64: Non inverting amplifier ,8 network. 95 r—'—1 |___l + Vout Z2 0 + V2 21 V1 0 _ Figure 3.65: Differential amplifier 6 network. 96 dB A Adm 100 80 = I ROC 20dB/deC = 1000 60 I 3 ZOdB/dec < ROC < 40 dB/dec ' 1 I I I ROC = 40dB/dec 1 20 l l _‘210 I I I 1 I l .... 40dB/dec < ROC < 60 dB/dec ' / 13 I H Y . . ‘K 10 100 1k 10k 100k f(Hz) I V -450 PM~90° l | | I | I I I I | -1 35° I | I I I | | I I I I I I —180° I I -225° V PM 1 Figure 3.66: Bode plot of IAdmI and B- for different feedback networks and the cor- responding plot of PM [21]. 97 dB A Adm 1 00 80 60 40 ROC = 40d B/dec 1 20 — \fl 0 I > 10 100 1k 10k 100k f(Hz) Figure 3.67: Bode plot showing the ROC of unstable amplifier. dB A Adm 100 80 60 40 / 5 ROC = 20d B/dec o . > . \ 10 100 1k 10k 100k f(Hz) 20 Figure 3.68: Bode plot showing the ROC of a stabilized amplifier. 98 dB It) .11. ll» | —L _a. 0 U! 0 01 01 0 01 .40 0 0 0 0 0 0 0 O I I I I I 0 —Il 0’ ._ N 33L _ 04> : (D 3 0 Li I 12‘, A 0* _ O) —l 01- _ (D > (1 3 Figure 3.69: Plot of the open loop Bode plot and 1 /6 to determine the ROC of power amplifier. 99 3.5.4 Performance The pulsed output of the amplifier with a 1Vpk' -— pk input and a 100Vpk — pk output across a 50!) load is shown in Figure 3.70. The simulated bandwidth of the amplifier is 380kHz. The lower —3d B frequency is 15Hz and the upper —3d B frequency is 380kHz. The Bode plot of the amplifier is shown in Figure 3.71. The measured bandwidth of the constructed amplifier is 160kHz. The limiting elements in the simulation are the output BJTs. A discrepancy in the model and the acutall transistors could explain the difference in simulated and measured bandwidth. 3.6 Impedance Matching Impedance matching is used to maximize power transfer and eliminate reflections [22]. 3.6.1 transducer impedance.s The impedance of each transducer was measured with a HP4194A Impedance An— alyzer and is shown in Figures 3.72 -3.84. Each channel has a unique impedance. The impedance of each channel at 80kHz is summarized in Table 3.7. The resistance varies from 1519 to 3180 and the reactance varies from —167f2 to 250. This is a large variation in the impedances of the transducers, so each channel will be uniquely matched. 100 Voltage(V) ‘00 mo mo 00 No INC 15 Imo I I I .x 3 Im Figure 3.70: Amplifier output. 101 (zHMouenbeId 901 170L 80|. OI L0L OOI 901 I [IIIUYF l [I‘lirj . /. . / : l E I L I I ' I : I : I E I / I / .. / . . / E 'r I L . / . I 1’ . 3. g 0: co I- \ K m D . x .2 g (D :- - ~ \ \ I: - ~ ~ 2 a. I ~ CD " I I J l ' ‘I - 00 I: a) \l co 0 01 o 01 o Phase(Degrees) Figure 3.71: Amplifier bode plot. 102 I Channel I Resistance(Q) I Reactance(fl) I 226.60 231.60 245.11 218.07 217.69 254.65 318.20 318.23 151.90 238.58 196.82 237.13 232.82 15.36 25.31 -35.31 -22.96 -29.76 12.52 -5.58 167.74 -6.53 -8.65 -34.99 -35.50 -66.26 Table 3.7: Transducer impedances at 80kHz. 103 039 40:00:00. .30000300 0» moxIN 300sz u mmmb 9. 5.093035 0 8.0 b s . 2.09.800 I 00 ..... 0:000 . I 00 a 0 I) do AW m I; m m 0 .m m. 9 I00 m a M h P L0 100 100 I :00 ADM _ _ P «05.0 0.05.0 005.0 005.0 005.0 3000002 2.5 Figure 3.72: Channel 1 transducer impedance. 104 Magnitude (9) 0:00 40:00:02 .30000300 0” moxIN 300.3 0 N: .0 5. 3.003023 n 00.0 b 3003.800 ..... 0:000 Am 00x10 300:0:0v~ AINV mmxI~ 0230 Phase (Degrees) Figure 3.73: Channel 2 transducer impedance. 105 Magnitude (52) 0:00 40:00:84 5:000:00 0" 00:5 300sz u 000.: 9. 5.005023 0 I000 b 0 . - 3002800 I 00 ..... 0:000 - .. 00 :0 0 A 0 I00 I00 I00 I00 I40 I I00 ADM _ _ _ 405.00 4mxI~ 00x10 00x1~ 00.0.04. 3.00:0:3. 0.5 Phase (Degrees) Figure 3.74: Channel 3 transducer impedance. 106 Magnitude (£2) 0:00. 40:00:00. 5:00:00 00 00xI~ 300sz u 0.0.: 0. 50050025 u I000 00 . 7002.800 I 00 ..... 0:00 I 00 :0 0 I: 0 I00 I00 I00 I40 I I00 ..0N _ _ P - 40wI~ 40.0.0 00x10 mmxIN 00x10 300:0:2 3.0 Phase (Degrees) Figure 3.75: Channel 4 transducer impedance. 107 0:00 40:00:004 5:00:00 00 00xIN 300sz n 34.4 9. 5003023 u I000 00 4 . 2002800 I 00 ..... 0:000 . I 00 :0 0 ) :0 .00. I00 6 d U ..n 0. I00 8 M I0 I00 -40 I I00 ‘0” _ _ _ 405.0 40sz 005.0 005.0 00sz 000:0:2 AINV Phase (Degrees) Figure 3.76: Channel 5 transducer impedance. 108 0:00 48:00:00.. _Bumamzom 3 35¢. 33.3 n 80.0 a. _BmostANv u 0pm .3 0 . 7:003:30 I 00 ..... _uzmmm , I 00 a 0 ) 00 M . I00 6 d m m I00 3 M I3 I00 I00 I I00 40” _ p _ 35¢ 34: 85¢ 00x5 00x1~ 3000002 AINV Phase (Degrees) Figure 3.77: Channel 6 transducer impedance. 109 Magnitude (S2) 0:3 0.8000000. 50000000 0” moxIN 300sz u Ban 5. 5005023 ..I. no.0 b 2.003.800 I 00 ..... «5000 I 00 I :0 0 I00 I00 L0 I00 , .\. / I I00 \ \ ./. \. \ \ l \. / ............. I I00 JON _ _ _ uoxIN umxI~ moxIN mmxIN 00x1~ 3000003 AINV Phase (Degrees) Figure 3.78: Channel 7 transducer impedance. 110 0:00 #0000000. 36000000 0: 00:1». 300sz u 0:0.» 5. 5003035 uLmNV .0 . 7:000:80 I 00 ..... 0:000 . I 00 . I :0 0 ) 00 m :0 I:0 m 9 m m. .m I00 0. m 0.. L0 I00 I00 I I00 AON _ . _ ~0xI~ umxIN 00xIN mmxI~ 00xI~ 3000003 AINV Figure 3.79: Channel 8 transducer impedance. 111 Magnitude (£2) 0:00 #0300000. 56000000 0: 00xIN 300sz u :0: .0 3. 500.2023 u :00 b . III 2.003.800 I 00 ..... _u:000 .I ./ . 00 :0 0 I: 0 I00 L0 I00 I00 I00 ._ON 0 _ p «0:1». «0:10. 00xI~ 00xI~ 00xIN 3000003 :15 Phase (Degrees) Figure 3.80: Channel 9 transducer impedance. 112 Magnitude (S2) 0:: 0 040000000. 500000000 0: 00xIN 000.3 u 000.0 9. 50030303 u 0.4 b . 700000000 I 00 ..... 0:000 I 00 .\. ./ 1 0m .\ / 0 I:0 I00 L0 I00 I00 I I00 AON _ _ b 00sz «0.0.0 000.0 000.0 0050 0300002 A13 Phase (Degrees) Figure 3.81: Channel 10 transducer impedance. 113 Magnitude (Q) 0::: 040000000. .30000000 0: 00x10 000sz n :00.0 9. 500.0023 n :00.0 b . 2.0000000 I 00 ..... 00000 I 00 :0 0 :0, I:0 m 0. mw I00 0 a .n 0. I00 I00 I00 I I00 dON _ _ _ 00.0.0 000.0 000.0 00.0.0 00.0.0 0.000002 AINV Figure 3.82: Channel 11 transducer impedance. 114 Magnitude (Q) 30000000 ..... 0:000 _s O 0:: 0 040000002 000000000 0: 005.0 000.3 n 000.: 9. 00003023 n :00.0 D _ 00:10 3.000002 AINV 00x10 Phase (Degrees) Figure 3.83: Channel 12 transducer impedance. 115 Magnitude (S2) i 2.0000000 ..... 0:000 0:: 0 #0000000. .30000000 0: 00.0.0 000.3 u 000.0 m. 3.00.0023 n 00.0 b _ _ 00x10 00x10 00x10 0.000002 .13 00x10 Phase (Degrees) Figure 3.84: Channel 13 transducer impedance. 116 3.6.2 Matching Networks A Smith chart can be used to determine the elements needed to transform the trans- ducer impedance to 500. A Smith chart is a graph of the impedance and admittance planes where impedances and admittances are mapped directly. The impedance (Z) plane in Figure 3.85(a) is transformed to the impedance (Z) Smith chart in Figure 3.85(b). The circles in Figure 3.85(b) are of constant resistance. The arcs in Figure 3.85(b) are of constant reactance. The admittance plane is transformed in to the Smith chart in Figure 3.86. The circles in Figure 3.86(b) are of constant conduc- tance. The arcs in Figure 3.86(b) are of constant susceptance. The impedance and admittance Smith charts can be overlaid such that impedances and admittances map directly as is shown in Figure 3.87. This is because Z = 32;, so point A (Z = 0 + Oj) on the Z graphs maps to infinity on the Y graphs. This point is on the far left of Figure 3.87. Likewise, point E (Y = O + Oj) on the Y graphs maps to infinity on the Z graphs, which is on the far right in Figure 3.87. 117 A X A A : B(0+lj) X=1 D(0+1j) ‘ r 0 .-I a; .2 4R x=0 L A (0+0j) C(1+0j) 4 X=‘1 L ‘ r v l (a) Z cartesian plane. B(0+lj) <15} 9" A (0+0j) C(1+0j) =00 (b) Z Smith graph. Figure 3.85: Z—plane to Z-Smith chart mapping. 118 A A B B(0 + 1j) B_1 D(0 + 1j) 4 — > C H II H U U G A (o + Oj) C(l + 05) 4 3:4 > v ‘7 (a) Y cartesian plane. F(0+lj) G=oo E(0+0j) _ (b) Y Smith graph. Figure 3.86: Y—plane to Y—Smith chart mapping. 119 Figure 3.87: Combined Y and Z Smith chart mapping. 120 Computing the impedance transformation of a passive network can be accom- plished using Smith charts. Inductors placed in series with a circuit moves the impedance upwards along the lines of constant resistance. A capacitor placed in series with a circuit moves the impedance downwards along the lines of constant re- sistance. An inductor placed in parallel with a circuit moves the admittance upwards along the lines of constant conductance. A capacitor placed in parallel with a circuit moves the admittance downwards along lines of constant conductance. These paths are shown in Figure 3.88. Constant G Constant R Figure 3.88: Effect of adding a capacitor or inductor in series or parallel with an impedance. In order to transform an impedance using a Smith chart, a point is plotted for the starting impedance and one for the conjugate of the desired impedance on the Smith chart. Arcs are drawn along paths of constant conductance and resistance through the points of starting and desired conjugate impedance. This is shown in Figure 3.89. Matching networks can be realized with paths from arcs of both points that intersect. Figure 3.90 shows two possible paths for the given example. 121 pI Figure 3.89: Arcs of constant resistance and conductance plotted through the start and conjugate desired impedances. Desired* Figure 3.90: Two possible paths on the Smith chart transforming impedance start to desired conjugate impedance. 122 "_l I .- ' “a W“ 1!.- There are several topologies for impedance matching: 2 element L—networks; 3 element 7r and T-networks; and 4 element cascaded 2 element networks. All networks can transform the magnitude of the source to load impedances. L-networks are simple but have a fixed selectivity and pass high or low frequencies. T and 7r-networks are more complicated but allow for a designed selectivity. Cascaded networks allow for a band pass filters and larger source to load impedance ratios. For simplicity, the initial matching is done with L—networks. L—networks are simple 2 element networks that match the impedance and act as a low-pass or high-pass filters. Figure 3.91 shows the two basic topologies of an L- network. Z 3 is the output impedance of the source and Z L is the input impedance of the load. Z1 and Z2 can be capacitors, inductors or resistors, but inductors and capacitors are typically used so that power is not lost in a resistive element. Choosing which topology to use depends on the difference of the real parts of ZS(R3) and ZL(RL). If R5 is larger than RL then Z1 is placed in parallel with Z S to lower the source impedance and Zg is placed in series with RL to raise the load impedance as is shown in Figure 3.91(a). If RL is larger than R3, then Z2 is placed in parallel with Z L in order to lower the load impedance and Z1 is placed in series with Z S raise the source impedance as shown in Figure 3.91(b). This can be seen on the Smith charts in Figure 3.6.2. Impedances with larger R, to the right on the Smith chart, move along arcs of constant conductance implying reactive elements being placed in parallel. Impedances with smaller R, to the left on the Smith chart, move along arcs of constant resistance implying reactive elements being placed in series. A 2 element L-network is either a high pass or low pass filter. Whether it is high 9888 or low pass depends on the choice of where the inductor and capacitor is placed. For the case of R 3 < R L in Figure 3.92, if a capacitor is used for Z1 and an inductor iS used for Z2, then the L-nework is a low pass filter. Conversely, if an inductor is 123 used for Z1 and a capacitor is used for Z2, then the L-network is a high pass filter. For the case of R5 > R L in Figure 3.6.2, if a capacitor is used for 21 and an inductor is used for Zg, then the L—nework is a high pass filter. Conversely, if an inductor is used for Z1 and a capacitor is used for Z2, then the L-network is a low pass filter. Z2 _“l T7 “Ml - (a) L-network for ZS > Z L- Z1 (b) L-network for Z3 < Z L. Figure 3.91: L-Network Topologies 124 o (a 9 g. —:N 5 N 3. T H i H § a U! V! 11 :2 — H E a: o Figure 3.92: L-network impedance matching on a Smith chart for R3 < RL. 125 O 0 o O : I. I—FOUUOLw ..N I ..N l— 6' O E i a a U! m _— .'-T (D (D W 0 o o i Figure 3.93: L-network impedance matching on a Smith chart for R3 > RL. 126 Whether X1 and X2 is a capacitor or an inductor depends on if R3 > RL or R3 < RL. First consider a matching network where RS > RL. To calculate the values of X1 and X2, the impedances of the source is transformed with X1 to 21 at point C and the impedance 21 is transformed with X2 from point C to Load* in Figure 3.94. The transformed impedance Zg is set equal to the conjugate load impedance and the values X1 and X2 are calculated. Z] A C 1 0'0". ¥ / \ / \ Source 0 Figure 3.94: Transformed start and load impedances on a Smith chart. 127 The source impedance is ZS = R3 + jXS. (3.21) The load impedance conjugate is given by ZL = RL + jXL, (3.22) 22 = RL — jXL. (3.23) The source impedance is transformed to Z1 at point C by adding X1 in series as is shown in Equation (3.24). Z1=R5+ j(XS+X1) (3.24) (3.25) The admittance Y1 at point C is 1 1 Y1_ Zl _ 35+ f(Xs+X1) (3.26) Rs+ 1(Xs+XI) Rs-- j(Xs+XI> ' RS ' (X3 + X1) (3.28) : R§+(X3+X1)2 _ JR§+(X3+X1)2 The admittance Y1 is transformed to the admittance Y2 by adding G2 = 1/X2 in parallel With Y1 . Rg + (X5 + X.)2 Rg + (XS + X.)2 + 02 (3.29) Y2 128 The admittance Y(L*) from eq (3.23) is 1 y* = ...: = _._ 3.30 L ZL RL __ JXL ( ) 1 RL-l- jXL = . . 3.31 RL-JXL RL+JXL ( ) — ——RL+ jXL (3 32) — 2 2 ' RL , XL :9: L = 2 2 + J 2 2 (3-33) RL+XL RL+XL Y1”: = (12+ sz (3.34) The admittances Y; and Y2 are equal. Setting the real and imaginary parts equal RL RS __ = (3.35) Ri+X§J R§+(XS+X1)2 RS 0* = (3.36) L Rg+(XS+X1)2 . X . X +X 3%? = —] 2( 3 1) 2 +G2 (3.37) * - .- (XS+X1) i B =-— +0 3.38 L J _R§+(X3+X1)2 2 ( ) In Equation 3.36 the known quantities are the conjugate load conductance (GE), the source resistance (RS), and the source reactance (X S)- Solving Equation 3.36 for X1 yields two answers, a value for a low pass and a high pass matching network. In Equation 3.38 the known quantities are the conjugate load susceptance (Bi), the source reactance (X S), the source resistance (RS), and the reactance X1 from Equation 3.36. Solving Equation 3.38 for two answers, a value for a low pass and a high pass matching network. The Matlab code to implement the L network matching component calculations is shown in Listing 3.1. If RS < R L then a series element is attached between the 129 source and load (X 1) and an element is placed in parallel with the load (G2). If R S > R L then a series element is attached between the source and load (X2) and an element is placed in parallel with the source (G1). If X1 is negative then E1 is a capacitor and E2 is an inductor. If X1 is positive then E1 is an inductor and E2 is a capacitor. If X2 is negative then E3 is a capacitor and E4 is an inductor. If X2 is positive then E3 is an inductor and E4 is a capacitor. 130 Listing 3.1: L matching network calculations Matlab code. function [E1,E2,E3,E4] = L_matching(z_source ,z_load ,freq) 70 L-matching(z-source , z_load , freq) % % This function determines the capacitance and inductance 70 for elements in L matching networks. The inputs are the 70 source and load impedance and the operating frequency. % The outputs are the capacitance and inductance of the low 70 pass L matching network followed by the capacictance and % inductance of the high pass L matching network. % % The elements are returned in the following structure: ”/0 struct( ’ualue ’,0, ’prefix ’, ’ ’, ’unit ’, ’ ’, ’topology ’, ’ ’) % value: {Numeric value of component} % prefix: Unused 70 unit: {’H’, ’F’}. This indicates if the element is an 70 inductor, H for Henries, or a capacitor, F for % Farads. 70 topology: {’Source_Parallel ’, ’Source_Series ’, 70 ’Load_Parallel ’, ’Load_Series ’}. 70 This indicates where the element is in the L 70 network. ’Source_Parallel ’ indicates in % parallel with the source. ’Load_Parallel ’ % indicates in parallel with the load. 70 ’Source_Series ’ and ’Load_Series ’ indicate the % element is in series between the load and 131 70 source. % % Ezrample: [E1 E2 E3 E4] = L-matching(50, 25 + 103', 1e6) E1 struct( ’value’,O,’prefix’,”,’unit’,’ E2 struct(El); E3 = struct(El); E4 = struct(El); if real(z_source) < real(z_load) % Series element attached to source. % Parallel element attached to load. R = real(z_source); X = imag(z_source); y = 1/z_load; ys = conj(Y); Gs = real(ys); B3 = imag(ys); else % Series element attached to load. % Parallel element attached to source. R = real(z_load); X = imag(z_load); y = 1/z_source; 3’5 = COHJ'W): Gs = real(ys); Bs = imag(ys ); 132 7 .’t0p010gy’.”); Pawn-nu- .«L '10- .1 end Be = subs(solve( ’R=(Gs)/(Gs‘2H+H(BsH+UB)“2) ’ , ’B’ )); Xe = (—(Bs + Be)./(Gs“2 + (BS + Be).‘2)) — X; if real(z_source) > real(z_load) % Source element moves along constant conductance circles. % Load element moves along constant resistance circles. 70 Series element attached to source. % Parallel element attached to load. if Xe(1) < 0 % X1 Capacitive % X2 Inductive E1.value = —1/(Be(l)*2*pi*freq); E1.unit = ’H’; E1. topology=’SourceuParallel ’ ; E2.value = 1/(Xe(1)*2*pi*freq); E2.unit = ’F’; E2. topologyz’LoadHSeries ’; else % X1 Inductive % X2 Capacitive E1.va.lue = Be(1)/(2*pi*freq); E1.unit = ’F’; El. topologyz’SourceuParallel ’ ; E2.va1ue = —Xe(1)/(2*pi*freq); 133 ‘J‘ "' E2.unit = ’H’; E2. topology=’LoadsSeries ’; end if Xe(2) < O % X3 Capacitive % X4 Inductive E3.value = -—1/(Be(2)*2*pi*freq); E3.unit = ’H’; E3. topology=’SourcesParallel ’; E4.value = 1/(Xe(2)*2*pi*freq); E4. unit = ’F’; E4. topology=’LoadsSeries ’; else % X3 Inductive 70 X4 Capacitive E3.value = Be(2)/(2*pi*freq); E3.unit = ’F’; E3. topology=’SourcesParallel ’; E4.va1ue = —Xe(2)/(2*pi*freq); E4.unit = ’H’; E4.t0p010gy=’LoadsSeries ’ ; end else % Source element moves along constant resistance circles. %Loa,d element moves along constant conductance circles. % Series element attached to load. 134 70 Parallel element attached to source. if Xe(l) < 0 70 X1 Capacitive % X2 Inductive E1.value = —1/(Xe(1)*2*Pi*fTBQ); E1.unit = ’F’; El. topology=’SourcesSeries ’; E2.value = 1/(Be(1)*2*pi*freq); E2.unit = ’H’; E2. topology=’LoadsParallel ’; else % X1 Inductive 70 X2 Capacitive E1.va1ue = Xe(1)/(2*pi*freq); E1.unit = ’H’; E1. topology=’SourcesSeries ’; E2.va.lue = —Be(1)/(2*pi*freq); E2.unit = ’F’; E2. topology=’LoadsParallel ’; end if Xe(2) < 0 70 X3 Capacitive 70 X4 Inductive E3.va1ue = —1/(Xe(2)*2*pi*freq); E3.unit = ’F’; E3. topologyz’SourcesSeries ’; 135 E4.value = 1/(Be(2)*2*pi*freq); E4.unit = ’H’; E4. topologyz’LoadsParallels ’; else 70 X3 Inductive 70 X4 Capacitive E3.value = Xe(2)/(2*pi*freq); E3.unit = ’H’; E3. topology=’SourcesSeries ’; E4.value = —Be(2)/(2*pi*freq); E4.unit = ’F’; E4. topologyz’LoadsParallels ’; end end Figure 3.95 shows the matching networks. The L matching network calculated for each channel is listed in Table 3.8. The output impedance of the amplifier (Ampout) is assumed to be 509 and the transducer impedance is assumed to be larger than 500. The matching network with values E1 and E2 is used because it is a high pass filter and any DC signal across Ampout will be blocked. The resulting impedance transformations of the transducers with the matching networks are summarized in Table 3.9 and shown in Figures 3.96 — 3.108. 136 Ampout Ampout Figure 3.95: L matching networks for the array transducers. E1 ll - 0 ll 32 E3 ::E4 X Ducer X Ducer Lohanneilmm) 1192(9) LEsm) 7134(9) 1 2.11e-08F 2.49e-O4H 1.87e-04H 1.71e—08F 2 2.076081: 2.57e-04H 1.91e—O4H 1.72e—08F 3 1.996081: 2.32e-04H 1.99e-04H 1.48e-08F 4 2.15e-08F 2.25e—04H 1.84e-04H 1.57e-08F 5 2.15e—08F 2.22e—04H 1.84e-O4H 1.54e-08F 6 1.96e-08F 2.57e-04H 2.02e-O4H 1.62e-08F 7 1.72e-08F 2.71e-O4H 2.30e-O4H 1.44e—08F 8 1.496-08F 2.53e—04H 2.66e—04H 1.05e—08F 9 2.78e-08F 2.06e—04H 1.42e-04H 1.81e-08F 10 2.0560817 2.40e-04H 1.93e-04H 1.59e—08F 11 2.27e-08F 2.10e—O4H 1.74e—04H 1.54e—08F 12 2.036081? 2.2860411 1.95e-O4H 1.49e-08F 13 1.98e-08F 2.18e-04H zone-om wee-oar Table 3.8: Matching network element values. 137 rm film'- .‘ ' ‘- l Channel ] Magnitude(§l)l Phase(Degrees) I 50.32 50.19 49.65 50.31 50.18 48.81 49.09 50.12 50.96 49.79 49.71 50.13 49.70 0.84 -0.37 -0.31 0.34 0.19 0.93 0.30 -0.55 0.28 0.54 0.66 0.80 0.34 In. Table 3.9: Impedances of matched transducers. 138 Magnitude (Q) p raga-iii; 0:3 Iamfiozma 48:828. .Bumamaom 2 85¢. 33sz u mob b. .385m23 u ob 9 $0 ..... 35% 2.828% am ..oi 00 #0 mo am we _ _ VoxIN. _ meIN moxI~ mmxIN moxIN 33:33 AINV Phase (Degrees) Figure 3.96: Channel 1 matched transducer impedance. 139 Magnitude (Q) In osomlamazma assuage. .3333ko 2 moxIN 38.sz u mo.» D. .33.:miNv n no; 3 inc 2.8::ch 3m 00 No we hm mo 4m NOxIN _ meIN mOxIN mmxIN moxln 38:33. 2.5 Phase (Degrees) Figure 3.97: Channel 2 matched transducer impedance. 140 Magnitude (£2) ..iullLIL o:omn3m8:ma ...qmamacomq .32588 2 85¢ 38sz n 8.4 E. 583325 u rob a ..... _u:mmm 2.8::ch _ P _ :mo 1.5m 3x1». umx1~ moxIN mmxI~ 385:3 AINV moxIN Phase (Degrees) Figure 3.98: Channel 3 matched transducer impedance. 141 Magnitude (Q) o:oa|3m8:¢a #8882 58338 .3 85¢ 38sz u mob, b. .38.:m23 u ob b ..... _u:mmm Z8283 — _ _ l 50 i now VoxIN wmxIN moxIN mmxIN 385:3 2.5 moxIN Phase (Degrees) Figure 3.99: Channel 4 matched transducer impedance. 142 Magnitude (S2) o:om|3m8:8 #8859 555:5 2 85.5 38sz u mo.» 9. 585933 n o.» b ..... 385 2.8265 P _ _ 35.5 35.5 85.5 mmxIN 385:3 2.5 AND 3m Iwo Lu ooxIN Phase (Degrees) Figure 3.100: Channel 5 matched transducer impedance. 143 Magnitude (9) 3083288 #8859 555:8 m. 8sz 38sz u 8b 9. 58.523 u ob @ i.mo 2.83.85 ..... firmmm 1 .8 ,.\./.\ 1 O .o. . . 1 Lu . .. two 15 . _ _ 3.4.». «$5 85¢ mmxIN 85¢ 385:3 AINV Phase (Degrees) Figure 3.101: Channel 6 matched transducer impedance. 144 Magnitude (9) 8315388 38855.. 555:5 m. 85.5 38.3 n s2... 9. 58.523 u oh my 2.8:..ch ..... .u:mmm .MO I .om P .l .3qu meIN mOxIN mmxIN moxIN 385:3 .15 Phase (Degrees) Figure 3.102: Channel 7 matched transducer impedance. 145 Magnitude (Q) osomlamazma 4838.32 583.25 a moxIN 2.83.83 ..... _uzmmm do] mmmsz u mo; 5. 535.325 u nob 5 So a 1 dom F b F uoxI~ meIN moxIN mmxIN moxI~ 33.832 2.5 Phase (Degrees) Figure 3.103: Channel 8 matched transducer impedance. 146 oyomlamfiozma 4838.89 _Bumamaom m" moxIN 39.“.sz u mfo b. _BmQSmJANV u oh 9 Magnitude (S2) _smcazcam ..... prmmm not 1 AND 1 ..om _ uoxIN umxIN _ moxIN 33532 2.5 moxI~ Phase (Degrees) Figure 3.104: Channel 9 matched transducer impedance. 147 Magnitude (£2) . ill.- mill-3.. afielamazma ...qmzmacomq _Sumamsom m” moxIN 33sz u sob E. 535935 u Pm b _smoazcam ..... _uzmmm 1 ‘mo 1.5m ad ,. , L .5 1 .8 _ _ _ L LG 35%. ii... 8.3 mmxIN SEN 385:2 A15 Phase (Degrees) Figure 3.105: Channel 10 matched transducer impedance. 148 Magnitude (Q) «..llqrr .... .IPZI 03‘ 73.3838 3.33852 _Snmam3om m: moxIN $2.sz u am..\ 3. _BmoSmJANV u cu m ..... _u3mmm 2.83.3.3 _ h _ limo 140m uoxIN umxIN moxIN mmxIN 33533 A15 woxIN Phase (Degrees) Figure 3.106: Channel 11 matched transducer impedance. 149 Magnitude (Q) i‘l. i 03 9.32038 4:338:02 333.338 m3 85¢ 38sz u mo; 9. 53.323 n Po 9 2.83.83 ..... _u3mmm 4 ..MO 1 3m uoxIN umxIN _ moxIN 38:32 AINV _ mmxIN moxIN Phase (Degrees) Figure 3.107: Channel 12 matched transducer impedance. 150 Magnitude (S2) 03 wlamfiosma 3.63382 _Bnmam3om m: moxIN :83:ch ..... _ozmmm do: \ 40R] 33sz u #94 3. 58.323 n oh 5 J 50 1 ..om rmo 1V0 1 km 1 3m 3sz umxIN _ moxIN 33.532 AINV mmxI~ 8.3». Phase (Degrees) Figure 3.108: Channel 13 matched transducer impedance. 151 Chapter 4 Pressure Field Measurement A pressure field measurement entails positioning the hydrophone in the desired loca- tion, exciting the transducer array, and capturing the resulting pressure data. This process is repeated for each location in the desired area over which the pressure field is measured. In order to focus the field in a particular location, the delays for each transducer must be set such that the pressure from each transducer constructively interferes at the desired location. 4.1 Hydrophone Positioning The hydrophone is positioned using a Parker® 3-D positioning system. The posi- tioner is controlled by the computer over an RS-232 port. Each axis is independently controlled by passing character string commands over the serial port. Each controller will echo the command and send back any requested information such as the status of the controller. Control was implemented using Matlab m-files. Table 4.1 summarizes the commands that control the positioning system. 152 [ Command [ Description I pos_home Send the positioner to the home position. pos_in_position Check to see if a specified axis or all axis are in position. pos_init Initialize the positioner communication settings and motor profiles and send to the home position. pos_is_moving Check to see is a specified axis or all axis are moving. pos_map Define the geometry of the positioning system. pos.move Move the positioner in 3 dimensions specified in mm. pos_move_axis1 Move the positioner along the X-axis specified in mm. pos_rnove_axi82 Move the positioner along the Y-axis specified in mm. pos_move.axis3 Move the positioner along the Z-axis specified in mm. a: posmovestep Move the positioner in 3 dimensions specified in steps. f1 pos_read Read a line from the motor controller and return it as a string. pos_read_a.ll Read lines from the motor controller and return them as several strings until an empty string is read. pos_readJegister Read the contents of a specified register. pos_write Write a command over the serial port to the motor controllers and return the response. ...- Table 4.1: Positioner Matlab commands. 4.2 Hydrophone Measurements The relative pressure field value is collected from the output of the hydrophone, which passes through a pre-amplifier into an oscilloscope. The oscilloscope digitizes the analog waveform, and the resulting digital waveform is sent to the computer over the GPIB bus. Basic commands to interface with the GPIB bus were implemented with Matlab using m-files. The commands are summarized in Table 4.2. Using the GPIB commands and other Matlab commands, higher function m-files were created to control and communicate with the oscilloscope. These are summarized in Table 4.3. 4.3 Calibration In order to focus the field in a particular location, the delays for each transducer must be set such that the pressure from each transducer constructively interferes at 153 [ Command I Description GPIB_close Close the specified GPIB port. GPIB_init Open and initialize the specified GPIB port. GPIB_query Send a command and read back the response into a string. GPIB_read Read a single line from the GPIB port and place it in a string. GPIB_read_all Read a line from the GPIB port and place it in a string until a null string is read. GPIB-write Write a command to a specified GPIB port. Table 4.2: GPIB Matlab commands. [ Command 1 Description ] scope_capture_wave_fast Capture the waveform from the oscilloscope and return the data array. This function does not set the GPIB address, save the data, or return the time array. scope_init Initialize the oscilloscope to a predefined state. This file should be copied and editied for each experiment so that the state is preserved for each experiment and not overwritten by subsequent ones. scope_make_time_array Query the oscilloscope to determine the time settings and number of points a waveform and then return a time array that matches this criteria. scope_set_channel Change the selected channel on the oscilloscope. scope This is a macro command that sets the oscilloscope resolu- tion, captures the waveform from the oscilloscope, saves the data to a specified file, and displays a plot of the data. Table 4.3: Oscilloscope Matlab commands. the desired location. There are two ways to determine the delays needed to focus the pressure field at a specific location: measure the delays from each transducer at the desired location and use correlation to determine the needed delays; calculate the delays based on the geometry of the transducer array, the frequency at which the transducers are driven at, and the position of the desired focus [17]. The geometry of the array has yet to be measured in detail so the former method is used. Figure 4.1 shows the responses from each transducer superimposed on each other. The delays were calculated, and Figure 4.2 shows the resulting waveforms measured at the same location with the applied delays. Table 4.4 contains a summary of commands that 154 are used for the calibration process. Listing 4.1 shows an example m-file that focuses the array at a single location. I Command {Description I calibrate_all_transducers A macro function to calibrate all transducers at a specified position and save the calibration data to a specified direc- tory. calibrate_reference This function measures and records the hydrophone wave- forms at a specified location. calibrate_sing1e_transducer A macro function to calibrate a single transducer at a spec- 3““ ified position and save the calibration data to a specified directory. delay-calculations This function calculates the delays needed to make the pres- sure from each transducer coherent at a sampled position. The waveforms from a calibration test with no delays ap- plied are read in from the specified directory and root file name. delay_check This function measures and records the hydrophone wave- forms at a specified location using calculated delays. delay-reference This function calculates the delays from saved waveform re- sponses for each transducer at one location and saves the results to a file. plot_calibrated_delayed This function plots the waveforms saved from the cali- brate_all-transducers function. The directory and file names should be the same that were used when calling cali- brate_all_transducers. The waveforms are saved in PDF for- mat. plot_calibratedJeference This function plots the waveforms saved from the cali- brateJeference function. The directory and file names should be the same that were used when calling cali- bratexeference. The waveforms are saved in PDF format. Table 4.4: Calibration Matlab commands. 155 VOHaQOM ...m .. K, I .0 01 I —h Q ..fim . ..., a. a.‘ ’3 . ax , ., é. a _ mmo .. \ \ . a: e... _ mum .3. n. a Z ~ , z .0 a ( § _ wmo as 3.1 .3 g a? : .. s _ wmm ,. an... > an. \3 2 . _ So 3323 .93 z 6.3 x. 33. an, _ mum .3 _\ z «9 > ‘4’ \ n. n...“ 6,. _ mmo , < n.3, > .. J, mam ,4 . ......“ ...,s. .33... o; .33. _\ 3,. n _ wmo \ . \ a... “a, an ‘ , _ mmm Figure 4.1: Superimposed responses of each individually excited transducer with no time delay. 156 Voltage(V) 998 098 098 (smewu 988 088 9L8 are 998 068 968 Figure 4.2: Superimposed responses of each individually excited transducer with calculated delays. 157 Listing 4.1: Example Matlab m-file that measures the transducer response. position = [0 —10 —25] directory = ’(x,x,—25) ’; file = ’(O,—10,—25)’; calibrate_reference (position , directory , file) delay_reference(directory , file) delay-check(position ,directory , file) plot-calibrated_reference (directory , file) plot_calibrated_delayed (directory , file) 4.4 Pressure Observation The positioner and oscilloscope commands are used with other Matlab commands to define functions that measure the pressure in the water tank. These commands are summarized in Table 4.5. Listing 4.2 is an m—file example of a pressure field observation. The delays from the calibration observation performed in Listing 4.1 are load into the array and the pressure field is measured over the specified plane. The variable dimension specifies how large the plane is on each side in mm. The variable resolution specifies the distance between each observation in mm. The variable origin specifies the least coordinate in the plane to be measured. The directory and file need to be the same as specified in Listing 4.1. 158 [gommand I Description pm-calc Calculate the magnitude of a voltage waveform. pos_scan-cube measure scanJine measure-pressurefield scan_plane plot _one transient _movie x Scan a cube of a specified dimension, resolution, and starting location and record the data to a specified directory. Capture a waveform from the oscilloscope and save the data to a specified file. Scan a line of pressure parallel to the X-axis in a specified direction, distance, and resolution. Measure the pressure over the specified dimension starting at the specified origin and moving in a positive direction. The waveforms from the pressure field measurements are stored in the specified directory with the specified root file name. Scan a plane of pressure normal to the Z-axis in a specified direction, distance and resolution. Plot the results from a single plane pressure field scan. Make a movie out of the oscilloscope traces over a plane. This movie shows the pressure field in the plane over time. .w "5"} Table 4.5: Pressure field measurementss Matlab commands. 159 ”It'lunln. ._I| Pitta» ' Listing 4.2: Example Matlab m-file to measure a pressure field. clear all % Define paths to matlab m—files common_path = ’ . . / . . /Common/ ’ ; addpath (common_path) path_defs (common_path) 07 M7 70 Load delays position = [O ——10 —25] directory = ’(x,x,—25)’; file = ’(0,—10,—25)’; data-file-name = ... sprintf( ’../ Calibrate/%s/%s_ref_delays .mat ’ ,directory , file ); load(data_file_name ); oz /U 70 Focus at home position 70 10077077. plane with 2rmn resolution % dimension 2 160; resolution = 2; origin = {—80 —80 —25]; 7o measure_pressure-field(delays ,directory ,file ,dimension , resolution ,origin ,.5); 'WLm-I 160 Chapter 5 Results 5. 1 Pressure Linearity Since the pressure from each transducer adds linearly, the pressure measured from exciting each transducer individually should add up to the pressure measured from exciting all the transducers. This assumption is confirmed and shown in Figure 5.1. 5.2 Focussing In order to determine where the geometric focus of the transducer array is, a cube of the pressure field was scanned without any delays applied to the transducers. The resulting pressure field is shown in Figure 5.2. The geometric focus was estimated to be at -25 mm below the hydrophone home position. The array was calibrated to focus at points evenly spaced in the geometric focal plane between (0,0,-25) mm and (0,60,—25) mm. The resulting pressure fields are shown in Figures 5.3 - 5.9. There are large grating lobes about 60 mm from the focus. As the focus moves away from the geometric focus and a grating lobe moves 161 Voltage(V) I on O) -b N O N h 0) CD 52 m I I I IV“ I \‘\'.\ I II) .I /',l co 8' / on O'— 01 on O).— o on O).— 01 :1 Eco ms:— §° - v I l o: . \“ >02 01 =,: “’0 Do. on 3 0°“ 93.5 0 mg: rxns. 9.2 ~"m (p— 83— “Q0 0" x:- mm 33 g2 00 (021')