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II

MICHIGAN STATEU

II III III II IIIIII II IIII III III

23 00551 4595

LIBRARY I
Michigan State
University I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This is to certify that the

thesis entitled

TESTABILITY DESIGN OF THE DKS CHIP
presented by
TEJ PAL SINGH

has been accepted towards fulfillment
of the requirements for

Master's degree in Electrical Engineering

fiajor professor

0-7639 MS U is an Affirmative Action/Equal Opportunity Institution

 

 

 

 

MSU

LlBRARlES
“

 

 

RETURNING MATERIALS:
Place in book drop to
remove this checkout from
your record. FINES will
be charged if book is
returned after the date
stamped below.

 

 

 

 

TESTABILITY DESIGN OF THE DKS CHIP
By

Tej Pal Singh

A THESIS

Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

MASTER OF SCIENCE

Department of Electrical Engineering

1988

ABSTRACT
TESTABILITY DESIGN OF THE DKS CHIP
By

Tej Pal Singh

A VLSI chip has been recently proposed to calculate the Direct Kinematic Solution
(DKS) for real time rob0tic control. It was not considered feasible to implement such a
complex chip without any testability features integrated into it during the design Stage.
Standard Design-for-Testability (DPT) structured approaches require a lot of area over-
head (upto 20%). Thus a modification of the existing DPT techniques called Bus Scan
Testing (BST) has been developed that makes use of the internal bus available on the
chip to access all the storage components in the circuit. The design modifications
required to implement BST on the DKS chip “are described. The test vectors required to
test the DKS chip are generated and lastly, the test application process is simulated. Per-
formance evaluation results indicate that BST required lesser area overhead, shorter test

vector length, and lesser test application time than LSSD.

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

I.
II.

III

IV.

VI.

INTRODUCTION
BACKGROUND
2.1 Design for Testability
2.1.1 Ad Hoc Techniques
2.1.2 Structured Techniques
2.1.3 Analysis of Structured Techniques
2.2 The Direct Kinematic Solution (DKS) Chip
TESTABILITY CONSIDERATIONS FOR THE DKS CHIP
BUS SCAN TESTING
4.1 Design Modifications
4.2 Operation
4.3 Performance
DKS CHIP TESTABILITY AND INPUT/OUTPUT DESIGN
5.1 Design Modifications
5.2 Input/Output Design
TEST GENERATION
6.1 Test Generation Methods
6.2 Test Vector Generation

6.3 Test Generation for Combinational Circuits

iii

Page

vi

ONON

18
18
22
27
31
39
43
45
45
5o
53
54
55
57

VII. TESTING THE DKS CHIP 64

7.1 Test Application Process 64
7.2 Performance Evaluation 69
VIII. CONCLUSION 67
APPENDIX A 75
APPENDIX B 78
APPENDIX C 91

BIBLIOGRAPHY 106

iv

1.1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5. 1
6.1

LIST OF FIGURES

The DKS chip block diagram.

Raceless D-type flip-flop with scan path.
Configuration of Sean Path in circuit.

Shift Register Latch

Level Sensitive Scan Design. .

LSSD double latch design.

LSSD L1/L2* latch design.
Polarity-hold-type addressable latch.
Set/Reset type addressable latch.

Scan/Set logic.

LFSR as a parallel signature analyzer.
Generalized internal bus architecture system.
Implementation of BST.

Three designs for TSRL.

TSRL cells interconnected to form a shift register.

SRL cells at the output of control logic section.

SRL and TSRL cells connected in to a single shift register.

Extra SRL cells for providing additional control signals.
BST implemented on circuit with two internal busses.

BST implemented on the DKS chip.

Various test vectors applied to a slice of the RCA adder.

Page

10
10
12
12
13
13
16
16
17
17
28
3O
32
35
35
36
36
42
46

60

5.1
5.2
5.3
6.1
6.2
6.3
6.4
6.5
7.1
7.2

LIST OF TABLES

Control signals added to the DKS chip for implementing BST.

I/O pins required for testing the DKS chip.

I/O pins required for the DKS chip.

D-propagation table for an Inverter.

D-propagation table for an AND Gate.

D-propagation table for an AND Gate.

Partial D-propagation table for a Full Adder.
D—propagation table for a 2-to-1 multiplexer.

Test application time for various modules in the DKS chip.

Comparison of the estimated overheads for the DKS chip.

vi

Page
49
49
52
58
58
58
59
59
72
72

I. INTRODUCTION

The number of components on a single IC has been steadily increasing over the last two
decades. Due to this, more complex circuits in terms of both transistor count and circuit func-
tion are being built and the problem of testing such circuits has become critical. Currently, a
significant effort is being devoted to the aspect of Design-For-Testability (DFI') in which the

circuitry for testing the chip is incorporated onto the chip during the design process.

In the past, rigorous testing was only carried out on military and aerospace projects [1].
But now, the requirements and usage of integrated circuits in everyday life have become so
great that the reliability of such circuits has become essential. The progress in DFI‘ and IC
testing techniques has only partially offset the increasing complexity of the systems. One rea-
son for this state of affairs is that the equipment to test a particular circuit must be an order of

magnitude faster than the circuit itself [2].

Various factors affect the testing cost of a circuit and there is a tradeoff between the test
cost and the repair cost. The cost of testing will be less if the fault coverage of the tests is less,
which leads to higher repair costs in the system. It has been estimated that if the cost of testing
an IC is 3 cents, then the cost of testing the same on a board is 30 cents, on the system is $3,
and in the field is $30 [3]. Thus, it is of utmost importance that the chips be properly tested

first and only then inserted into boards and systems.

Test generation for M81 and LSI was initially done by a functional model or by a heuris-
tic approach rather than by logic simulation and fault simulation techniques. The reason was
that there was little interaction between the design engineer and the test engineer. The test
engineer usually got the device from a product engineer without much documentation. Full

logic information was rarely available to the test engineer or the user. This led to a time

consuming, costly, and ineffective test process which was often an overkill for the device [4].

With the advent of VLSI, some efficient test generation algorithms were developed based
mostly on stuck-at fault models. The test vectors could then be generated by fault simulation,
which further requires good logic simulation. Many CAD systems have been developed to han-
dle logic and fault simulation. However, even with these efficient algorithms and increasing
CPU speeds, the time required to generate test vectors for complex VLSI devices is often
intolerable. This is especially true for sequential circuits because the output of such circuits
depends on the current state of the circuit apart from the primary inputs. Algorithms for for test
generation of sequential circuits are still in the research stage. Thus methods to decrease the

cost and time required to generate and verify test vectors must be found.

The concept of DFT has evolved from the realization that the only method to significantly
reduce the cost of testing is to include circuiU'y on each chip to facilitate such testing. This has
led to the development of some techniques which the designer can incorporate into a design
with various degrees of effort. They result in reduction of the complexity of the full testing
process from test generation and verification to test application, which makes testing faster and
more economical. These DFT techniques are, in some cases, general guidelines to improve tes-
tability; others are hard and fast rules. The designer can select among these techniques depend-
ing on their cost of implementation, specific test requirements and their effectiveness on

specific types of circuits.

Recently, a single chip implementation of a circuit to find the Direct Kinematic Solution
(DKS) of a robot arm was developed which has an internal bus architecture [5]. Figure 1.1
shows the block diagram of this DKS chip. The aim of the designer was to do all the calcula-
tions on a single custom designed IC. The chip is expected to reduce the computation time for
the DKS by three orders-of-magnitude when compared to the time required by a 16-bit
microprocessor [5]. However, for reasons enumerated earlier, it was not considered feasible to

implement this complex chip without any testability features on it.

 

 

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Figure 1.1. The DKS chip block diagram [5].

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Systems with bus architectures have been identified as being relatively easy to test. In
fact, bus architecture itself is one of the ad hoc approaches to DFI‘ suggested in the literature.
But, it has always been assumed that the bus is available externally and thus can be easily
observed. However, on a chip with an internal bus architecture, the bus is not available at the
pins and the problem of testing becomes as complex as any other IC. Such is the case with the

DKS chip.

Scan design methodology has emerged as one of the most promising DFI‘ techniques
being implemented to test sequential circuits. These techniques conceptually convert a sequen-
tial circuit to a combinational one so that well proven combinational testing techniques can be
used. Moreover, they provide a structured approach to the problem and thus can be easily
adapted to design automation. Various scan techniques could be applied to the DKS chip.
Though Level Sensitive Scan Design (LSSD) and Random Access Scan (RAS) techniques
seemed to be good choices at first glance, they don’t exploit the internal bus available on the
chip. It seems obvious that if somehow the bus could be used to access all the components
connected to it on the chip, the overhead in area required for extra testability components may

be reduced.

This thesis begins with a background section (Chapter II) which is divided into two parts.
The first part explains the importance of DFI‘ and the various techniques that have been
developed. The second part then gives a brief overview of the DKS chip, its importance, its
development, and its structure. In the Chapter III of the thesis, the DKS chip is studied in con-
text of its testing problems. The applicability of the various DFT techniques are then discussed.
Finally, the justification for modifying the earlier scan techniques to apply them to the DKS
chip is given.

In the Chapter IV of this thesis, a new DFI' technique called Bus Scan Testing (BST) is
developed that can be applied to circuits with an internal bus architecture. The design
modifications required to implement BST are first discussed. This is followed by the descrip-

tion of its operation on a chip. The advantages and disadvantages of BST over other scan

techniques are also presented.

The next three chapters of the thesis are devoted to the specific testing aspects of the
DKS chip. First, the modifications required in its design to incorporate BST are presented in
Chapter V. Next, the test vectors required to test the chip are generated in Chapter VI assum-
ing a functional fault model for the circuit. Then, the actual test application process is

described and simulated in Chapter VII.

Finally, the performance of the DKS chip with BST is evaluated and compared with the
estimated figures for other DPT techniques in Chapter VIII. The thesis concludes with a sum-

mary and directions for future work in this area.

II. BACKGROUND

The problem of testing can be divided into three parts: test generation, test verification,
and test application. The test generation problem is to generate a set of test patterns that can
adequately exercise the system by providing a sufficient fault coverage. The generation of tests
is subject to constraints imposed by circuit access, the tester, and time required to run the tests.
The test vectors are generated so as to test specific faults ( single stuck-at, bridging, etc. ) or to
test the functionality of the circuit. Test verification evaluates the test vectors and tries to prove
that they are effective (sufficient) towards the end goal of verifying the correct functioning of
circuit. This is usually done by making use of logic fault simulators. The last part of the testing
process is the actual application of the tests to the circuit. Automatic Test Equipment (ATE)
and in-circuit board testers are use to apply the tests, make and record measurements, and in

some cases trace the fault to specific areas in the circuit.

2.1. Design For Testability

All the three parts of the testing process are becoming more complex as the ratio of
number of devices per chip to the number of pins increases. The costs of testing have gone up
considerably. This has given rise to the concept of Design For Testability (DPT) to reduce the

cost and effort required to test ICs.

The goal of DFI‘ is to ease the process of test generation and verification by taking some
steps during the design process itself. Some extra effort during the design process can save a
lot of effort during the test and can also help automate the testing in certain ways. It is
appropriate here to note that we are talking here about explicit testing which is carried out while

the circuit is not in use, as opposed to implicit/concurrent testing which refers to on-line testing

to detect errors that occur during system operation.

The first task here is to define what is meant by testability of a circuit, and how is it

quantified. Testability can be loosely defined as follows [6]:

A circuit is testable if a set of test patterns can be generated, evaluated and applied in
such a way as to satisfy pre-defined levels of performance, defined in terms of fault-
detection, fault-location, and test application criteria, within a pre-defined cost budget

and timescale.

Controllability and observability are the two measures used to quantify testability of a
given circuit. Controllability refers to the ease of producing a specific internal signal value by
applying signals to the circuit input leads, while observability is the ease with which the state
of internal signals can be determined at the circuit output leads. Various methods have been
proposed which estimate the testability of a circuit without having to run an Automatic Test
Pattern Generation Program (ATPG). ATPG will of course be the direct way to measure testa-
bility but it turns out to be very expensive in terms of both cost and time. It may also not give

clear indications as to how testability of a particular circuit can be improved.

Several programs have been developed to measure the testability of a circuit. TMEAS
(Testability Measure Program) [7], SCOAP (Sandia CY/OY Analysis Program) [8],
CAMELOT (Computer Aided Measure for Logic Testability) [9], and VICTOR (VLSI
Identifier of CY,TY,OY, and Redundancy) [10], are some of the programs written for this pur-
pose. TMEAS and CAMELOT calculate two values (controllability and observability) for each
node of the circuit, while SCOAP calculates a vector of six values for each node. VICTOR can

only be used for measuring the testability of combinational circuits.

The main objective of DFI‘ techniques is to increase the controllability and observability
of a circuit. The techniques developed for DFI‘ have been classified into two categories: ad hoc
techniques and structured techniques. The ad hoc techniques are aimed at the designer and
present him with a set of design features which case the testing of a chip. They are not always

applicable to all types of designs. The structured techniques on the other hand can be applied

to almost all types of designs. They provide the designer with a set of rules leading to the

design of a testable circuit.

2.1.1. Ad Hoc Techniques

The ad hoc techniques present the designer with a list of design features that help increase
the testability of the circuit and points to those features that create testing problems for the cir-
cuit. Some ad hoc techniques identify alternative preferable implementations where ever appli-

cable. Some aspects of the important ad hoc techniques are listed below [3,6,11].

1) Extra Test Points: The most direct way to enhance the testability of an IC is to add extra
test points at critical places in the circuit. Multiplexers and demultiplexers may be used to keep

the pin count down and still provide more access to the circuit.

2) Initialization Circuitry: Initialization of all stored logic devices to a known state is impor-
tant before carrying out any test. It is even more helpful if all such devices can be individually

initialized to specific values.

3) Partitioning: It has been shown that the cost of testing a circuit increases from somewhere
in between square to cube of the complexity of the circuit. Thus partitioning the circuit into
smaller parts and testing them part by part is much cheaper and easier than testing the full cir-

cuit as an entity.

4) External Test Clock: It should be possible to disconnect an IC’s internal clock, if any, and
connect an external test clock in its place. Thus the tester is able to perform single step opera-

tions, and reduce the speed of the circuit if required.

5) Feedback Loops: If all feedback loops present in the circuit can be broken, then the test-
ing becomes much easier. Tristate control and tester inhibit logic are some of the ways of
achieving this objective.

6) Bus Architecture Systems: If a bus architecture is used, it then becomes possible to test

each component connected to the bus individually by floating all other components. This serves

to partition the circuit.

Some other design features that are to be avoided to maximize testability during circuit
design are wired logic, high fanout points, deep sequential circuits (like counters), monostables,
potentiometers, and asynchronous logic. It has been found that such features on a chip make
their testing more complex. AnOther suggestion that is given with respect to the test program is
to avoid its dependency on ROM type devices which are more subject to changes during and

after the design process.

2.1.2. Structured Techniques

The techniques to be described under this section reduce the sequential complexity of the
system thus increasing the circuits’ controllability and observability. They provide access to
many points in the IC without assigning one pin to each point; typically four pins are required
irrespective of the number of test points. They also transform a sequential circuit into a combi-
national circuit thus drastically reducing the number of vectors required to test it. The cost of
all this, however, is that the test process becomes serialized, i.e., all vectors in to and out of
the 1C are transmitted in serial. Also, most of these techniques require a large area overhead
(up to 20%). However, these disadvantages are often offset by their advantages for most of the

complex chips. The various techniques will now be explained.

1) Scan Path: The scan path technique was the first structured approach to DFI‘ and was intro-
duced by members of Nippon Electric Co., Ltd. in 1975 [13]. It makes use of raceless Dtype
flip-flops which have two latches connected in series where the first latch has two inputs and
two clocks as shown in Figure 2.1. All latches in the circuit under test are converted to these
raceless D-type flip-flops. There are two modes of operation for the flip-flops: normal mode
and test mode. In the normal mode, the flip—flop works as usual with a D input and C output
using the system clock 1. However, during the test mode, the flip—flop takes its input from
scan-in and uses test clock 2. The first flip-flop in the circuit is connected to a Scan-In (SI)

line. After that, the input of each flip-flop is connected to the output I of the previous flip-flop.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3
3

 

 

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Output

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(scan out)

 

 

 

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Latch 1

Clock 1 DC>——‘

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Latch 2

Figure 2.1. Raceless D-type flip-flop with scan path [3].

 

 

 

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Figure 2.2. Configuration of Scan Path in circuit [3].

10

11

The output I of the last flip-flop goes to a pin called Scan-Out (SO). This essentially produces
a long shift register spanning all the latches in the circuit (Figure 2.2). The test is carried out

in following steps:

Step 1: Shift in and out a test pattern through the shift register. This tests all the flip-

flops for correct operation.

Step 2: Shift in a test pattern and set all the primary inputs of the circuit to a test vector

value.

Step 3: Apply one system clock to latch the response of the combinational networks in

the circuit into the flip-flops.

Step 4: Scan out the contents of the shift register. The next test pattern can be scanned-

in from the SI pin concurrently.

During normal operation of the circuit, the SI inputs and SO outputs of the flip-flops are
not used and clock 2 is kept at 1 for the entire period. Thus the raceless D-type flip-flop acts
just like a normal D—latch. Since only one system clock is used here, the circuit is exposed to a
race condition between the two latches in series. The next approach uses two system clocks to

rectify this problem.

2) Level Sensitive Scan Design: This technique (LSSD for short), was first presented by T.
W. Williams and E. B. Eichelberger of IBM Corp. [14]. Since then many modifications have
been suggested [15,16,17,18] and it has gained large popularity 'among other manufacturers.
LSSD is similar to Scan Path, but because it is level sensitive, the constraints on circuit excita-
tion, logic depth, and handling of clocked circuitry are not imposed. It uses a Shift Register
Latch (SRL) as shown in Figure 2.3 as the basic design elements instead of raceless D-type
flip-flops,. The SRL contains two latches in series operated by separate non-overlapped clocks
to avoid races. These SRLs are again threaded, as in the case of Scan Path, to act as a shift
register during test mode while they act as normal D-latches during normal system operation

(see Figure 2.4). To operate the SRL, scan clock A is set to 1 to enable data from Scan In (SI)

+Ll

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Figure 2.4. Level Sensitive Scan Design [3].

12

 

   

   

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Figure 2.5. LSSD double latch design [3].

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Figure 2.6. LSSD L1/L2* latch design [6].

l3

14

to be latched into L1. Scan clock A is then returned to 0, latching SI and then B is set to l to

transfer data from L1 to L2. Data is finally latched in L2 when B returns to zero.

Two configurations using these SRLs are possible. First is a double-latch configuration as
shown in Figure 2.5, where the output of the SRL is taken from L2 for both system mode and
test mode. Here, both the latches are in the system path thus increasing the propagation delay.
A single-latch configuration (Figure 2.3), on the other hand, takes system output from latch L1
and test output from latch L2. Thus only latch L1 remains in the system path. This also implies
that now latch L2 is redundant during system operation, leading to a significant hardware over-
head cost for improving testability. A modification of the single-latch configuration was
recently suggested [17], where L2 is also used as an independent latch during normal system
operation. This Ll/L2* latch (Figure 2.6), thus results in a very small hardware overhead. The

only restriction is that now both the inputs can not be taken from the system simultaneously.

3) Random Access Scan: The objective of Random Access Scan (RAS) is the same as that the
earlier two methods i.e. to reduce a sequential circuit to a combinational circuit and to have
complete controllability and observability. However, RAS does not uses a scan path for this
purpose. It allows each latch in the circuit to be separately accessed to clear/preset it or
observe it using an addressing scheme (thus the name random-access) [19]. Polarity-hold type
or set/reset type addressable latches can be used (Figures 2.7 and 2.8). They are addressed by a
shift register and a decoder. The working of RAS is described next.

The address of the latch to be controlled or observed is entered serially from the scan
address line using the scan clock and decoded using the latch select decoder. The latch is then
cleared or preset using the CLR or PR line respectively. The procedure is repeated for all the
applicable latches and then primary inputs are applied to the IC. After one system clock, all the
applicable latches are again addressed one by one and data observed at the SDO pin. It should
be noted here that data can be scanned out even during normal system operation. Also, the test

is slow because each latch has to be separately addressed and set before each test and then

15

read after each test.

4) Scan/Set Logic: This scheme is also similar to the first two techniques. Here also there is
no scan path present like RAS. The shift registers are present, but they are not in the system
path. They are independent of all the latches in the system. In a single clock the full shift
register is loaded with values from the system latches. Then the data is shifted out from the
shift register using the scan clock (Figure 2.9). The reverse operation is followed to load the
system latches, i.e., first data is scanned in to the shift register and then loaded into the system
latches by a single system clock [20]. An advantage of scan/set logic is that the data can be

clocked in and out of the shift register while the main circuit is in full operation.

5) Built-In Self Tests: This approach of Built-in Self Test (BIST) is a widely used method for
testing ICs as well as boards. There are quite a few methods available to employ self testing
in a circuit. Built-in Logic Block Observation (BILBO) [21], syndrome testing [22], testing by
verifying Walsh coefficients [23], and autonomous testing [24] are some of the techniques
available. The advantages of these techniques is that they use an on-chip pseudo random test
generation process. However, they only give a golno-go indication for the chip without any
diagnostics.

6) Signature Analysis: [25] Signature analysis lies somewhere between the ad hoc and struc-
tured techniques. It requires that some design rules be followed during the design stage, but its
objective is not the same as for structured techniques (to increase controllability and observa-
bility of the circuit). Signature analysis is based on Linear Feedback Shift Registers (LFSR) as
illustrated in Figure 2.10. These are shift registers with feedback tapped off from some inter-
mediate points and fed to the input through XOR gates to preserve linearity. The circuit is first
initialized and a fixed number of clock pulses applied to it. The resultant value in the shift

register is the signature to be compared with a correct signature.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

r .90.}
SDI C,P
PDQ—d ’
-CK O ‘ 0
fit)
scx o——Do_J soo
X.Adr C} r
Y-Adt o

 

 

Figure 2.7. Polarity-hold-type addressable latch [3].

Data

-CK

- CL
PR

X-Adr
Y-Adt

 

Figure 2.8. Set/Reset type addressable latch [3].

l6

64 btt seroal

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

shill requster
”—‘l 1 Sit-FCN
Scan 1000! o——-—u—t l 2 o e e 64 r—O Scan Output
\ ll 1 San-Hm ll
I 0....l SVStem Sequence Logic r—O W
0—1 ”'0
S m o 0 System
1:33:13 __: : LOutputs
LO—l "—0 J
Figure 2.9. Scan/Set logic [3].
Z1 ’22 ‘23 24
~11 0 ~10 0 ~10 0 ~10
?C I 7 Cl 7 C 1 Cl
Clock -
Pulses 01 02 O 3

 

 

 

Figure 2.10. LFSR as a parallel signature analyzer [12].

17

 

 

 

18

2.1.3. Analysis of Structured Techniques

The various structured techniques described above can drastically reduce the effort
required for IC testing by adding some extra effort during the design phase. Moreover, each is
easy to automate, because of their strict structured approach. Several companies such as IBM,
Fujitsu Ltd., Sperry-Univac, and Nippon Electric Co., who are basically mainframe manufac-
turers, have realized the importance of DFI' and have ongoing research efforts in this area.
Despite the advantages of these techniques, there has been a slow growth in their usage

because of two main disadvantages.

Firstly, most of the techniques require an extra silicon area overhead and an increased
number of pins to implement them on an IC. LSSD and scan path have a 4 to 20% area over-
head associated with them and RAS may require up to twice that figure [3]. Thus it is impor-
tant to somehow modify the existing techniques to decrease the area overhead. All the scan

techniques also require at least 4 pins on the 1C dedicated to testing.

Secondly, these techniques tend to serialize the test process because the full test vector
has to be scanned in and out one bit at a time. The process is repeated for each test pattern
applied to the circuit, though the next vector in sequence can be scanned in during the same
time as the current pattern is being scanned out. The test application times increase consider-
ably because of this serialization. Built-in tests and signature analysis do better in this aspect,

since they use an on-chip pseudo-random test generation process.

2.2. The Direct Kinematic Solution (DKS) Chip

A robotic manipulator with multiple degrees of freedom can be controlled by a computer-
ized system for automatic or remote operation. However, the computer must accurately know
the position (usually an angle) of each joint of the robot at all times. For this purpose, one
transducer is required for each joint of the robot. These transducers feed back the position
information to the computer at regular intervals. The computer can thus calculate the position,

velocity, and acceleration of the arm of the robot at any given time. It is conventional to

19

express all the positions in terms of a reference world coordinate system. The Direct Kinematic
Solution (DKS) converts the joint angle vector received from the robot to the reference

system’s coordinates.

A homogeneous transformation method has been developed to solve the DKS effectively.
The method requires successive multiplications of transformation matrices. Any joint i is
represented by the angle 9, in its own coordinate system. A,, a function of 6,, maps vector in
the link i‘“ coordinate system to link i-l”‘ coordinate system. Thus the joint space to cartesian

mapping is:
T: Al'Az‘Ag'A4'A5‘A6 = [n S a p] [2.1]
where n, s, and a give the orientation of the wrist and p gives the arm position.

It has been shown in [5] that the matrices A2, A3, and A, can be modified to make them more
symmetric without any change in the final result. The values of the matrices A,- before (2.2) and

after (2.3) the modification are as follows:

C10 “510 Cz-Szoazcz C30 53 03C:
A 510 C10 A- 52 C200252 A 5304530353
1" 0-100 2'0014, 3"0100
o o 01 o o 01 oo o 1
c.0—s,o C505“, C,-s,00
__ 5,0 40 _ Sso-Cso sCsoo
A“ o-1o d, A5“ 010 0 A6" 0 01416 [23]
o o 01 oo 01 o o 01
C2 "-520 0 C30 53 a; gt 0 -54 a3
_ SzCzoazSo __ Sao—Cao _ 40 40
‘2‘ o 01d2 ‘3‘ 010 0 A4“ 0—1 0 d, [23]
0 0 01 00 01 0 0 01

 

Also only two out of the three orientation vectors are required to fully specify the orien-

tation of the wrist. Thus s can be dropped making A, a 4-by-3 matrix.

In real-time robotic systems, this computation may have to be carried out tens or even
hundreds of times a second to track the exact position of the robot arm. This requires a lot of

computations and a computer (or a controller as the case may be) may not be able to handle it

20

especially along with the other computations required for proper operation of the robot. Thus,
it is necessary to either decrease the computation time of the DKS or to use a coprocessing

chip dedicated to compute the DKS in real-time.

A VLSI ASIC design to calculate the DKS in hardware has been recently developed [5].
It was shown that it would reduce the computation time by three orders-of-magnitude over that
required by a 16-bit microprocessor. This was further verified when the design was imple-
mented on a general-purpose signal-processor [26] and the results showed a marked improve-
ment in the time required to calculate the DKS. However, the chip has still not been imple-
mented in ASIC form. The main reason is that it is not considered feasible to implement such

a complex chip without any testability features on it.

Figure 1.1 shows the block diagram of the DKS chip as in [5]. It assumes MOS technol-
ogy and uses a two-phase nonoverlapped clock. It shows that the chip is based on two internal
busses A and B. The input from the robot is latched in a register, and after processing, the
results are stored in an output register. The circuit is organized as a finite state machine and the
control section, along with a counter, controls the flow of data on the chip. The basic computa-
tional structure consists of a two-stage multiplier and an adder in a pipeline, both using two’s
complement fixed-point arithmetic. They are supported by a number of registers to store inter-
mediate results. The control logic, constants and all table values for the calculation of sines and

cosines are stored in a ROM.

The first step is to compute sines and cosines of the input angles. A method for sine-
generation proposed by Ruoff was found to be best suited for the chip [27,5]. It is based on a
ROM look-up table with linear interpolation using the multiplier-adder pipeline available on the
DKS chip. It was shown that an 18-bit word length of 256 entries would be required to get the

accuracy necessary for DKS calculation [5].

The algorithm to calculate the full DKS was developed and described in RTL [5]. Sym-
bolic simulation showed that once the six input angles are stored in the angle registers, it takes

73 steps (system clocks) to calculate the full DKS using this circuit [5].

'21

It was estimated that about 4,300 standard cells are required to implement the DKS chip,
assuming a 10% estimation error and a 70% cell utilization. The IBM’s Master Image approach
shows that the chip can be implemented with 1.25 pm NMOS technology with a chip edge of
about 5.6 mm. The CMOS chip will require a total of 5,317 cells with the chip edge being
about 6.34 mm thus verifying the feasibility of the DKS chip using current technology [5].

III. TESTABILITY CONSIDERATIONS FOR THE DKS CHIP

The DKS chip has been designed for the PUMA robot. But, before it can be manufac-
tured, a prototype will have to be fabricated to verify the design and logic on the chip. This
requires better diagnostic capability for the tests to do design verification for the circuit, apart
from testing for interconnection faults on the chip. Further, the chip will have to be modified a
little to use it for other robots, and again new prototypes will have to be made for each new
design. Thus, the testability design should be such that it will work for all of them and is
geared towards prototype testing rather than manufacturing testing, the latter being applicable to

those chips which are manufactured in large quantities.

Why is testing the DKS chip so difficult? Well, consider the possibility that the chip is to
be tested by the same method as is used for small ICs, which is exhaustive testing. The
number of test patterns required to test any sequential circuit is at least 2"“), where m is the
number of primary inputs to the circuit and n is the number of latches in the circuit [3]. The
DKS chip has a 12-bit primary input and has nineteen 18-bit latches, six 12-bit latches, one 1-
bit latch, one 7-bit counter and one 36-bit latch taking the total number of latches to 458. Thus
the number of test vectors required to test the DKS chip by exhaustive testing is at least 247° !

Even if one pattern is applied to the chip every 1 usec, it will takeilo127 years to test it!

Apart from this problem, which is common to every large sequential circuit, the DKS
chip also has a ROM which stores the control logic, values for sine and cosine generation, and
constants of the transformation matrices of the DKS. Since the contents of the ROM will differ
for each robot, the values stored in it must be verified for correct results. Each cell in the ROM
should be individually verified as some of the locations are used more than the others during

normal robot operation, and a functional test may not be able to detect all the errors. The ROM

22

23

is embedded within the chip and thus not accessible from any primary inputs and outputs. Thus
any testing procedure for the DKS must be able to test the ROM by exhaustive testing.

In conclusion, it can be summarized that the following two problems have been identified

for testing the DKS chip:

0 To test the complex sequential circuit effectively without having to resort to exhaus-

tive testing.
0 To test the embedded ROM exhaustively.

With these goals in mind, methods to solve these problems can be scrutinized to select
the one which is closest to the goals and economical too. As mentioned in the last chapter,
DFI‘ techniques are being adopted widely to resolve testing problems. So, first the list of
important ad hoc techniques can be discussed to see if any of them is applicable to the DKS

chip [3,6,11], otherwise one of the structured techniques can be used.

The first ad hoc approach is to add extra test points on the chip to increase its controlla-
bility and observability directly. This method requires one pin for each node in the circuit that
needs to be controlled and observed. Clearly, this is not practical for any chip of the size of the

DKS chip.

The second approach is to partition the circuit so that each part of the circuit can be
tested independently of the others. Though the DKS chip can be very easily partitioned because
of its bus architecture, still it does not in any way increase its controllability and observability.

Since this approach does n0t meet our test goals, it is not suitable for the DKS chip.

The next ad hoc approach is bus architecture systems which is very close to the
specifications of the DKS chip which also has a bus architecture. But again the same problem
arises that the DKS chip uses internal busses that are neither controllable nor observable. So

this scheme is also not directly suitable for the DKS chip.

Signature analysis is a DFI‘ technique that lies between ad hoc and structured techniques.
It can be applied to most of the circuits and requires some modifications during the design

stage. The drawback of this approach is that it lacks diagnostic ability and is thus only used to

24.

give a go/no-go decision for a chip. This is hardly the problem for the DKS chip where the
main objective is to get good diagnostic information to test the prototype. There are some other
built-in and self-test techniques available but they also lack on the same grounds and are more

useful for implicit testing which is carried out when the chip is on-line in a system.

One of the structured approaches to DFT may be applied for testing the DKS chip as
they are general in nature and applicable to all types of circuits. The main objective of the
Structured DPT approaches is to increase the controllability and observability of all the storage
components in the circuit. If all the storage components in the circuit can be set directly from
outside the chip, the circuit is transformed into a combinational circuit for testing purposes.
Thus efficient and automatic test generation and verification algorithms that have been
developed for combinational circuits can be applied. The same mechanism is also used to pro-
vide access to the embedded ROMs in the circuit, thus solving both the problems for testing

the DKS chip.

The structured techniques, however do have some drawbacks. One is that they serialize
the test application process which further results in long test vectors and long test application
time. They also require up to 20% silicon overhead on the chip as well as 4 to 6 extra pins on
the chip dedicated to testing [3]. In some of the techniques, the system performance also
decreases when simple latches are converted to more complex ones to make them easily

testable.

The DKS chip has to be first studied to decide which of the structured techniques is most
applicable to it. Referring Figure 1.1 and [5], it is observed that most of the latches in the DKS
chip are connected to either of the busses A or B. Only the outputs of M1, M2, A1, and A2
latches are not connected to the bus, and M3, delay latch, and the angle registers are not con-
nected to the bus at all. The angle registers are 12-bit wide and they can be set directly from
the input port pins. All the other latches, registers and both the busses are 18 bits wide, and the
output port is 16 bits wide. There are 11 control signal fields spanning 36 bits, and therefore a

36-bit control signal latch is required at the output of the control logic section.

25 .

The latches in the circuit can thus be classified into the following five categories with

most of them falling into the second one:
1) The 12-bit angle registers.
2) The 18-bit latches that are connected to the bus.
3) The l8-bit latches that are not connected to the bus.
4) The 36-bit control signal latch and the 7-bit counter.
5) The l-bit delay latch.

If any of the scan techniques is applied to the DKS chip, all of these latches
behave in a similar manner as far as required design modifications are concerned. For
example, if LSSD or scan path technique are used, all of these latches can be con-
verted to polarity hold Shift Register Latches (SRL) or raceless D-type flip-flops
respectively, and then interconnected to form a single long shift register. These SRLs
operate as normal latches during normal system operation, but during the test mode
they act as a shift register so that the data can be scanned into the register from one
pin on the IC and scanned out through another pin. Thus using only these two pins for
I/O and two pins for clock signals, the full problem of controllability and observability
is resolved. A quick calculation shows that if either of LSSD or scan path technique is
applied to the DKS chip, the resultant test vector length will be 470 bits (12-bit pri-
mary input and 458 latches), and the area overhead as will be shown in Chapter VIII

would be approximately 17%.

The scan/set testing, and RAS testing techniques approach the problem in a
slightly different manner. Scan/set testing also employs a shift register to scan data in
and out of the chip, but the register is not in the system path. This register can set and
load data from up to 64 points in the circuit. The DKS chip has 458 latches, so this
scheme is not feasible if all of the latches have to be made controllable and observable.
RAS on the other hand employs an addressing scheme to select each latch uniquely

and can both set it and observe it just as random access memory works. This approach

26

requires more area overhead and more extra pins than the other scan techniques and
thus is rejected.

Thus, LSSD and scan path techniques are the only ones which closely meet the
specific testability requirements of the DKS chip. LSSD is always preferable to scan
path because it provides a level-sensitive hazard free design and some improvements to
basic LSSD are also available to closely match the requirements of the chip under test.
But LSSD requires a 20% area overhead on the chip. The next logical step is to look
for ways to somehow decrease the area overhead by taking advantage of the particular

architecture of the DKS chip.

Earlier in the ad hoe techniques, it was noticed that partitioning and bus architec-
ture system techniques came very close to solve the DKS chip’s testing problem. The
only reason that they could not be applied to the DKS chip was that they did not pro-
vide access to storage components in the circuit which is precisely the objective of the
structured techniques. It seems quite obvious that if the busses can be somehow util-
ized to get access to the latches that are already connected to them (category 2), the
area overhead may be reduced by a significant amount. It was this idea that prompted
the development the Bus Scan Testing (BST) technique, which is applicable to all
internal bus architecture systems. It takes the concepts of circuit partitioning and bus
architecture systems, and modifies LSSD to provide access to the bus and other parts
of the circuit. The following chapter describes BST and how it can be applied to any

internal bus architecture system.

IV. BUS SCAN TESTING

Bus Scan Testing (BST) has been developed for those integrated circuits which use one
or more internal busses to transfer data within the chip. Usually bus architecture systems are
considered very easy to test as compared to other circuits, as explained earlier in the ad hoc
techniques. The reason is that such systems are usually divided into modules which use the bus
to transfer data among them. Thus, partitioning is inherent in these systems and partitioning a
circuit always reduces the complexity of the testing process. Each module of the circuit can be
tested independently of the others by putting all the other modules in high impedance state.
However, in the internal bus architecture ICs like the DKS chip, the bus is itself not accessible
and it is very difficult (if not impossible) to put circuit modules on the chip to high impedance
states directly from the outside of the chip. BST uses a modification of the earlier scan tech-
niques to make the bus accessible at the pins of the ICs and to control data flow on the bus
inside the chip.

The philosophy behind BST is the same as that of the structured scan techniques. That is,
if all the latches on a chip can be controlled and observed from the pins of the IC then the
sequential circuit is transformed into a combinational one for testing purposes. Doing so
enables the test engineer to use efficient algorithms and design automation tools that have been
developed only for combinational circuits for generating and verifying test vectors for the cir-
cuit.

Consider a hypothetical circuit with an internal bus architecture to understand how the
BST technique can be applied and how it works. Figure 4.1 shows the block diagram of such a
system. The circuit block has various combinational and sequential parts, communicating

through the internal bus. The control section manages the flow of data through the bus, and in

27

 

 

 

 

 

 

 

 

 

 

 

 

 

r”_.__._.
M1
0 -——>
I] M2
N L
T
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l-—>
L C
CI
(3 H
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———>
Mn

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I.

 

 

 

 

 

 

 

F"—_—F—60_TP_D'T_§1I_ ——————————

M Combinational

Circuit Modules

Figure 4.1. Generalized internal bus architecture system.

28

i, CLOCK U, INPUTS

—_

[I]

 

 

S Sequential Circuit
or
Storage Elements

fl

_I

29

and out of the chip. The input and output blocks may consist of just buffers/drivers, or they
may be circuits in themselves. To make the circuit as general as possible, it will be assumed

here that they are in fact sequential circuits.

The following assumptions will be made for the circuit to explain the design

modifications and operation of the BST technique:

0 The circuit uses synchronous logic with an external two phase non-overlapped

clock.
0 The bus is precharged before any data transfers take place on it.

o All data transfers on the bus are deterministic.

o The control logic section provides signals for all data transfers on the bus and its

output latch is operated by the system clock.

The first step to implement BST is to logically partition the circuit under test. For bus
architecture circuits, this only amounts to clearly identifying the various circuit modules con-
nected to the bus. Though no restrictions are placed on the structure of the modules, some of
the modules will be easier to test than the others. The modules which consist only of a combi-
national network with at the most one latch at its input, or the ones which consist of only
storage components, will require less test time than those where a lot of combinational as well
as sequential networks are intermixed. Thus the partitions should be kept as simple and homo-
geneous as possible. The reason will become clear when the operation of the BST technique is
explained. It is also assumed here that each module in general may have a combinational net-
work as well as some storage components (latches) in it. Since the process to test combina-
tional circuits is independent of the process to test the storage components, so if one of them

does not exist in the module under test, then the respective part of the test can be skipped.

First, the design modifications required to implement BST on the chip will be discussed.

Then the procedure for testing such a chip will be explained in detail and lastly, its perfor-

mance will be evaluated.

_l
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r____i£Q%_____flJEEL____

 

—_l_——.__

 

 

 

 

 

 

M8
M3
T's'ZlF—__—

M1

 

 

 

 

 

 

 

 

 

 

 

fifi

B

9 \7 9 9
_ _ _

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SRL SRfiI

CONTROL LUGIC _

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l
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Figure 4.2. Implementation of BST.

30

31

4.1. Design Modifications

Figure 4.2 shows the proposed scheme applied to the type of circuit earlier shown in Fig-
ure 4.1. The part of the circuit which is based on the bus architecture will be considered first.
Testability considerations for the rest of the circuit will be dealt with later in this section. The
objective of BSI‘ is to exploit the bus to access those latches that are already connected to it.
Thus individual circuitry to access each latch can be avoided, thereby decreasing the area over-
head. At this point it is observed that the problem can be split into two parts. One is to provide
access to the bus (and thus all latches connected to it) and other to provide means to control
data flow on the bus from outside of the chip. BST requires two modifications to resolve these

problems and each of them will be explained in detail now.

To get full access to the bus, a logic structure is needed that can perform the following
three functions :
o Shift (scan) in and out test vectors.
0 Set the bus to the test vector value.

0 Load data from the bus.

It would seem that a shift register with parallel load can satisfy these requirements. How-
ever, this presents two problems. First, the outputs of each shift register cell are the same
points at which it is to be loaded in parallel. Second, its output will have to be tristate since it

is to be connected directly to the data bus.

80, the basic shift register should be modified to satisfy the above mentioned require-
ments. We chose to modify the Shift Register Latches (SRL) used in LSSD for this purpose
because they are level-sensitive and thus less prone to logic hazards and race conditions. A
Two-way SRL (TSRL) is proposed to provide two-way (bi-directional) access to the bus. Vari-
ous logic structures were considered and three of them seemed to be quite promising. Figures

4.3 shows the structure of all three TSRL candidates.

The first structure, Figure 4.3a, can shift data from SI to 80 when the two-phase non-

overlapped clock (A & B) is applied to it. Its other output is through a tristate buffer so that it

(a)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31
b
A ( )
B
1310
E
E _L_
7L are
$1 [:14
A 1: L2 (C)
""'____ II
En 2 —<I so
3 a

 

 

 

 

 

 

Figure 4.3. Three designs for TSRL.

32

33

can be safely connected to the bus. This buffer is controlled by the it? signal which is provided
at one of the pins of the 1C. To load the bus, the bus is also connected to the input of the first
latch and is controlled by a signal E that is provided internally by the control logic of the IC.
This design suffers from two drawbacks. One is that it is susceptible to a race condition
because both the input and output of L1 are connected to the bus. The second drawback is that
although A and B is a set of two phase non-overlapped clocks, E and B is not, and it would
have to be somehowinsured that B does not go high when E is high to avoid any hazard con-
dition.

The second design, Figure 4.3b, resembles the first one except for the fact that bus input
along with the signal E are now moved to the second latch. Thus it does not suffer from the
race condition but still the second drawback is there. Here, A and E should not go high at the

same time.

From the above two designs it was realized that we would have to use only one bidirec-
tional line from the TSRL to the bus. 80 the third design, Figure 4.3c, was developed. It
satisfies all the requirements and does not suffer from any hazards. It is now explained here in
detail.

The TSRL of Figure 4.3c consists of two D flip-flops, L1 and L2, connected in series.
The first latch L1 is a clocked D flip-flop with a tristate output. The input to L1 is Scan-In
(SI), the clock is test clock A, and the tristate output is controlled by the enable signal EX. The
output of L1 is connected to the bus line through a transmission gate (a pass transistor in
NMOS), as well as to the input of L2. The transmission gate is controlled by the complemen-
tary signals E and E. This gate can thus transfer data from output of L1 to the bus and from
the bus to the input of L2. L2 is a clocked D flip-flop with clock B and output Scan-Out (SO),
which is not a tristate output. If A and B are two-phase non-overlapped clocks then this struc-

ture does not suffer from any of the hazard conditions.

The TSRL works in two modes: normal mode and test mode. In the normal mode of opera-

tion, the signal E is kept low so that the output BIO is in a high impedance state and thus does

34

not interfere with the bus signals. The circuit can function normally as if the TSRLs were not
present on the chip. In the test mode, however, the TSRL has been designed to perform the
previously mentioned three fitnCtions. Firstly, it can act as a cell of a shift register with input
SI and output 80. The output $0 of each TSRL is connected to the input 81 of the next TSRL
to make a shift register. In this SHIFT operation, E and E? are both held low to disable the
transmission gate and enable the tristate output of L1. A and B are two phase non-overlapped
test clocks to avoid-any hazard conditions. The number of shifts is equal to the number of

periods for which this test clock is applied.

The other two Operations of the TSRL are used to SET and LOAD the bus respectively.
The SET operation is used to set the bus line connected to BIO from the contents of the L1. In
this case E7 is held low to enable the output of L1, and E is held high to enable the transmis-
sion gate. Lastly, the LOAD operation latches the data on the bus line into L2. For this opera-
tion, E; and E are both held high to disable the output of L1 and enable the transmission gate.

Then a single pulse of the B clock is applied to latch the bus data into L2.

Once these TSRL cells are connected to each line of each internal bus in the circuit and
interconnected to form a shift register, full access to the bus is available from the external pins
as shown in Figure 4.4. A test vector can be shifted into them from the Scan Data In (SDI) pin
and the bus can be set to that vector through the transmission gates. To remove a test vector,
first the data from the bus can be loaded into the TSRL cells and then can be shifted out
through the Scan Data Out (SDO) pin.

The second modification to implement BST is required to gain control over the data flow
on the bus from outside the chip. To achieve this objective, the output latch of the control logic
section is converted into polarity hold Shift Register Latch (SRL) of the type used in LSSD
(Figure 2.3). These SRL cells are also arranged into a shift register and connected in the same
scan path as that of the TSRL cells as shown in Figures 4.5 and 4.6. The SRL also has the
same two modes of operation, but works in a little different way. In the normal mode, it just

acts like a normal latch with input D and output +L1 using the system clock C. In the test

BUS

 

 

 

 

SDO(-———

‘ TSRL

 

 

 

 

 

 

TSRL

 

 

 

 

 

 

 

 

TSRL

SO

 

 

 

TSRL

(3'— SDI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slim”

Figure 4.4. TSRL cells interconnected to form a shift register.

 

 

CONTROL LOGIC

 

 

 

 

 

 

 

 

 

 

I.)

SDI ———)

SRL

 

 

 

 

 

 

 

I

 

 

 

 

 

 

 

 

Control

 

 

 

Signals

 

 

 

 

 

 

 

c
A
l l l B
‘9’SRL L9 SRL 9L9 SRL
. Ia +I_2a soo
+L1

Figure 4.5. SRL cells at the output of control logic section.

35

 

CONTROL LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

c
A
B
I I I I
SRL 9 SRL —> SRL 9-) SRL L2
. . . . _.—l) |+—-_>SDO
r-i-—---i--“i ———————— 1—-—:
I Control Signals +LI I
I I
I CIR c u I T I
I I
I B U S I
I L T I
I._....._ ______________ ...ll. _____ L.._......_I
TSRL E . TSRL TSRL so TSRL‘ESI SDI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

elm

 

Figure 4.6. SRL and TSRL cells connected in to a single shift register.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GNDJ:
"3" c
A
I I l l B
9 SRL L91 SRL 9 SRL 9—) SRL
SDI —-9 i - - - - ———'—) 11:29 To other
, SRLs

 

 

 

 

 

 

 

 

 

 

 

 

I I I I“

Control Signals E

Figure 4.7. Extra SRL cells for providing additional control signals.

36

37

mode, however, it takes its input from I, uses test clocks A and B and its output +L2 is con-

nected to the input I of the next latch in sequence.

This arrangement of an SRL at the control output makes it possible to set the control
latch directly during the test mode, bypassing the control logic. When the next system clock is
applied, then data transfers on the bus take place according to the current control signals in the
control latch which have been set in the test mode. It should be made sure that all system
operations are clocked, otherwise inadvertent operations are possible when test vectors are

scanned in and out of the SRL cells.

The input of the first SRL cell in the scan path is connected to the external pin SDI and
the output of the last one is connected to the input of the first TSRL cell. Then, the output of
last TSRL cell is connected to the external pin SDO as shown in Figure 4.6. Test clocks A and
B and the enable signal 51' are also provided through external pins. The other enable signal E
for the transmission gates of the TSRL cells is provided internally in the following manner. It
is the output +L1 of a SRL cell, whose normal input D is connected to ground (Figure 4.7),
and the input I and output +L2 are connected to other SRL cells. Thus in normal circuit opera-
tion, E is always low and in the test mode it can be set to any value just like any other SRL. E
is just the complement of E and thus can be taken directly from the same cell’s output. This
SRL cell can be visualized as an extension of the control latch and the TSRL as just another
register connected to the bus. All data transfers through the bus are thus controlled by the SRL

which can be set from outside.

The SRL and TSRL cells form the basic structure of the BST technique through which
the bus is made fully controllable and observable. However, there may be some storage com-
ponents in the circuit which are not connected (partially or fully) to the bus. The design
modifications required for them and rest of the circuit which is not based on the bus architec-
ture are similar and are described next. Again, the objective to test the rest of the circuit is to
convert it to a combinational one and this is only possible if all the storage components are

made fully controllable and observable. There are two methods available in BST to attack this

38

problem and both are described now along with their pros and cons.

One method is to connect all the inputs and outputs of such storage components to the
bus. The points will have to be connected using tristate buffers, pass transistors, or transmis-
sion gates (depending on the technology), so as not to interfere with the normal operation of
the bus. Control signals would have to be added to transfer data between these latches and the
bus. Note that these control signals need not appear in the control logic section as they are not
required for normal circuit operation. Only the output latch of the control logic needs to be
extended to include these extra control signals in the same way as it was added to provide the
E and E signals of the TSRL. One SRL cell will have to be added for each group of latches
connected to the bus, and the input D of each cell is connected to ground permanently so that
the transmission gates are off during normal circuit operation. Thus, the latches that were not

connected to the bus earlier can now transfer data to and from the bus during the test mode.

The second method of providing access to the registers is to convert them to SRL cells
and connect them in the scan path exactly as is done in LSSD. Thus they can be set and
scanned using the LSSD approach as such. Therefore, LSSD and BST can co-exist on the
same chip, BST for testing the bus architecture part of the circuit and LSSD for rest of the cir-

cuit.

The second method of using LSSD requires more area in most cases than the first
approach of connecting the latches to the bus. It also lengthens the size of the test vectors. But
in some cases, using LSSD may reduce the total test time, if one part of the circuit is quite
independent of that part of the circuit which is connected to the bus. This would allow some
tests to be done in parallel which is otherwise not possible with BST. LSSD will also have to
be used if the width of the latch under question is not the same as the bus-width.

39

4.2. Operation

The testing process is generally divided into three parts: test generation, test verification,
and test application. Tests can be generated automatically on computers for all the combina-
tional networks in the circuit using one of the available algorithms (like the D-algorithm,
PODEM—X, adaptive random test generation, or compiled code Boolean simulation). Test
verification is a little more complicated, but mostly a single stuck-at fault model is assumed
sufficient to find the fault coverage [9,36] for the test vectors generated earlier (fault simula-
tion). A fault coverage of 95 to 98% is considered sufficient to test any circuit economically
[9]. Lastly, these test vectors are applied to the circuit. This is a 3+n step process for the BST

technique (where n is the number of partitions of the circuit), and is now explained in detail.

1. Test the SRL and TSRL cells: Scanning in a set of vectors and then scanning them out tests
all the SRL and TSRL cells in the scan path. Flush test and shift test are usually considered
sufficient to test shift registers [9]. In flush test, first a single one in a set of zeroes is passed
through the register followed by a zero in a set of ones. In shift test, the sequence 00110011...
is shifted through the register. The SHIFT operation of the TSRL is used for this purpose.
These tests don’t test the transmission gates in the TSRL cells, which are tested along with the

bus in the next step.

2. Test the internal bus(ses): The test vector is scanned into the TSRL using the SHIFT opera-
tion. Then a SET and a LOAD operation is performed consecutively in the same clock cycle to
test the bus. The latched data is then scanned out and compared with the input that was
applied. If the vectors are not the same, then there is a fault on the corresponding bus lines,
transmission gates, or any one of the modules connected to them. Faults on busses are usually
very difficult to locate and fault diagnosis in this case is limited to identifying the bus lines on

which faults exist.

3. Test the control logic: The control logic is usually either hardwired, or microcoded in a
ROM with a counter at its address lines. To test the control logic, the circuit is first RESET to

initialize the system, and then one system clock is applied. This latches the first control

40

sequence into the control logic’s SRL. This sequence can be shifted out through the SDO pin
by the SHIFT operation. Another system clock will latch the second control sequence into the
SRL, which can be then similarly observed. This process continues until all states of the con-
trol logic have been verified and the system returns to its original state. If the control logic is
microcoded, the counter’s latch cells will also have to be converted to SRL cells, included in

the scan path, and tested with the other SRL cells in step 1.

4. Test the circuit modules: Since the circuit has already been partitioned into n modules, this
step has to be repeated 11 times to test each of them separately. The test vectors required to test
each module are generated ahead of time. The procedure to test any one part of the circuit
involves the testing of the latches in that module first, and then the application of test vectors
to those latches and primary inputs to test the combinational part of the module. The following

steps are required to test each latch in that module:

a) Shift the test vector into the TSRL shift register and the control vector into the SRL shift

register of the control latch (SHIFT operation).

b) Apply one system clock. The control signals are set such that they transfer data from
TSRL to the latch under test during the first phase of the clock and from the latch to the
TSRL during the second phase.

c) Shift the TSRL’s data out through the SDO pin (SHIFT operation). (Actually this step can
be combined with step a such that when the data in the TSRL is being shifted out, the next

test vector can be shifted in at the same time.)

After all the input and output latches in the module have been tested, the combinational

network can then be tested using the following steps :

a) Set all the latches and primary inputs that directly effect the combinational network under
test. Each latch/register can be set by a SHIFT operation followed by 3 SET operation with
appropriate control signals. If the module under test is a fully combinational one, then the

input to the network can be applied directly from the TSRLs.

41

b) Apply one system clock to do a single operation of that module. The output of the module
may go to an output latch or directly to the TSRL through the bus. If the output goes to an
output latch then control signals to transfer data from that latch to the TSRL are scanned in
and a LOAD operation performed. It is for this reason that the SRLs are kept in the scan
path before the TSRLs, so that if the TSRLs are not required to be set to any particular

value it is then possible to scan in just the control vector itself.

c) The result which is now latched in the TSRL is scanned out. Again this step can be
merged with step a and the next test vector can be scanned in simultaneously with this
step.

The testing of that part of the circuit which is based on the internal bus architecture is
now camplete. The procedure to test the rest of the circuit depends on which of the two
options was used during the testability design of that circuit. If all the latches in that part of the
circuit were connected to the bus then that circuit acts just like one more module in the bus

architecture and is tested accordingly, as explained in the previous few paragraphs.

On the other hand, if the second option is used then all the latches are converted to SRLs
and the LSSD technique can be used. The testing of these parts can thus be carried out using
LSSD in parallel with the testing of the other parts of the circuit using BST. When the test
vector is scanned in, it includes the values for all the SRLs as well as the TSRLs. Next, when
a system clock is applied, the data from the SRL cells is applied to the combinational circuit

and latched into its output SRL cells. This data can be shifted out and verified for correctness.

One more thing needs to be pointed out before completing the discussion of BST. If there
is more than one internal bus in the circuit, BST can still be applied with the same
effectiveness. The other busses may be internal or external and controlled from inside or from
outside the chip, as long as data transfers on them are deterministic. Figure 4.8 shows an
example of how BST can be implemented on a circuit with two internal busses. It can be
easily extended to any number of busses. The same E signal can be used for all of them to

transfer data from and to the TSRLs at the same time.

.1
I
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_
_
_
_
_ O
Ilm TSRL I TSRL TI _ vw
s: \u/ A? \ufl —
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r____sIe_9E£391<_____fliN£U_T.5______

S R L AI—SRHmlwI

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A,B,En SDI

Figure 4.8 BST implemented on circuit with two internal busses.

42

43

4.3. Performance

The reduction of silicon overhead from LSSD to BST can be quickly figured out by
using a simple example. If a circuit has 10 registers of 16 bits each wnnected to the bus, and
the LSSD approach is used, it would be required to convert all the 160 latches involved to
SRL cells. In BSI‘, however, only 16 TSRL cells need to be added to the circuit and the con-
trol latch converted to SRL cells to access the the 16-bit bus and thus all of the 10 registers. In
fact, the number of TSRL cells will remain constant at 16 irrespective of the number of latches
connected to the bus. Only the control signal latches have to be converted to SRLs. Thus, the
more the number of latches connected to the bus, the lesser the proportional area overhead.

This is unlike all Other scan techniques, where the area overhead increases in direct proportion

with the number of latches in the circuit.

The second advantage of using BST over other scan techniques is that there is no perfor-
mance degradation during normal operation of the circuit. To implement LSSD or scan path in
a circuit, all latches in the system have to be modified resulting in an increased time delay for
each of them. In BST, no such modifications are required thus avoiding any performance

degradation for those modules in the circuit that are connected to any of the busses.

Another advantage of using BST is that it results in shorter test vectors than either of
LSSD and scan path techniques. This directly follows from the fact that there are less SRL and
TSRL cells in BST than the others. Thus at any time, fewer of these cells have to be set in

BST leading to shorter test vector lengths.

BST, however, does suffer from one disadvantage when compared to the other tech-
niques. Since many latches are connected to a bus, only one of them can be set from the
TSRLs at one time. Further, the structure of BST had been optimized to test one circuit
module at a time. Both of these characteristics of BST lead to longer test application times than
would be required by LSSD for the same circuit. LSSD can set all the latches in the circuit at

one time and can thus test most of the circuit modules in parallel.

44 .

In conclusion, it can be adjudjed that the advantages of reduced area overhead, no perfor-
mance degradation, and shorter test vectors because of partitioning outweigh the only disadvan-
tage of a little longer test application time. Thus BST should be used for testing all internal bus
architecture systems. The area overhead in BST can be further reduced by converting one of
the system latches into TSRL cells, instead of adding extra TSRL cells at the expense of a

more complicated design.

V. DKS CHIP TESTABILITY AND INPUT/OUTPUT DESIGN

The testability considerations for the DKS chip were presented in chapter 111 and a deci-
sion was justified that one of the scan techniques must be used to improve its testability. Then,
a new technique Bus Scan Testing was presented in Chapter IV. Since the DKS chip has two
internal busses, the advantages of using BST over the other scan techniques make it the obvi-
ous choice. This chapter explains what modifications are required in the design of the DKS
chip for the purpose of incorporating BST. The input/output design is then presented which
completes the design of the DKS chip in all respects.

5.1. Design modifications

The basic Strength of the bus architecture (and thus BST) lies in their ability to be
quickly partitioned. One glance at the DKS chip’s block diagram (Figure 1.1) gives clear evi-
dence to that effect. It is observed that most of the blocks are connected to the bus and are
either purely sequential or purely combinational in nature. The only sequential circuits present
on the chip are the latches and registers and the most complicated combinational networks are
the two stage multiplier and the adder. Thus each block in Figure 1.1 can be considered a

module and each of them can be tested independently.

Now that the DKS chip is partitioned, each module or a group of modules can be
analyzed one by one to take appropriate steps to make each of them easily testable. Since the
main objective of the BST approach is to make all the storage elements in the circuit controll-
able and observable, design modifications are required only for such modules which have one

or more storage elements. The latches and registers in the DKS chip have been classified into

45

ooooooooooooooooooooooooooooooooooooo

Angle Reglsters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

. we r
2"":5LDELk—I er/cns ]
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7F ‘1' ’ ’ ’ ' ' \II \I/ v
SDI 015 014 01 00 sec

Figure 5.1 BST implemented on the DKS chip.

46

47

be discussed now.

The latches of category 2 and 4 are easily dealt with by using the basic BST structure.
Since the latches of category 2 are already connected to the bus and conn'ol signals which
transfer data among them through the busses already exist, they meet exactly the specifications
of the BST design. Thus one TSRL cell is connected to each bus line of both the busses,
which are then interconnected to form a shift register. Next, all the output latches of the control

logic section and the counter (category 4) are converted to SRL cells.

One SRL cell is added to provide the E and E signals to the TSRL cells. The input D of
this SRL is connected to ground so that during normal circuit operation, E is always low thus
keeping the output of TSRLs in a high impedance state. Finally all of these SRL and TSRL
cells are interconnected to form a single shift register, the input of which is from the external

pin SDI and output to another pin SDO.

Most of the latches of category 2 have either their input or their output connected to the
bus, but not both. To make them fully controllable and observable, they should have their
inputs as well as outputs connected to the bus. Thus the outputs of M1, M2, A1, and A2
latches and the output of the adder which feeds Creg, Sreg and the register file are connected
to the bus through transmission gates as shown in Figure 5.1. One control signal will be
required for each set of transmission gates connected to the bus. So five SRL cells are added in
the scan path to control the 5 sets of transmission gates with their D-inputs connected to

ground to disable the transmission gates during normal circuit operation.

The remaining latches of categories 1, 3, and 5 are those which are not connected to the
bus. Since there are two options available for the purpose, each option will be assessed for
each category of latch separately. The first option is to connect both their inputs and outputs to
the bus and the second one is to use the LSSD approach which converts each latch to an SRL.
LSSD will be preferred only if the latches in question are quite independent of the part of the
circuit based on the bus structure or if the width of the latch is greater or much less than the

bus width.

48

The angle registers of category 1 are 12—bits wide and their input is directly connected to
the input pins of the IC. Thus they are already controllable so only their output needs to be
made observable. If LSSD is used 72 (12x6) of these latches will have to be converted to SRL
cells and the test vector length will also increase by the same amount. On the other hand, if
their 12-bit output is connected to the least significant 12 bits of one of the two 18-bit busses,
the overhead will be 12 transmission gates and one SRL cell, and the test vector length will
only increase by one bit. The most significant 6 bits of the bus can be ignored when the angle
registers are scanned out through the bus. Thus this alternative is much more economical than
using LSSD in this case. So 12 transmission gates are added to connect the output of the angle
registers to bus A and one SRL cell is added in the scan path to control these transmission

gates with its D-input connected to ground.

The only latch that falls into category 3 is M3. Since it is 18-bits wide and is in middle
of the part of the circuit based on the bus architecture, there is no reason to use LSSD. So 18
transmission gates are used to connect the input of M3 to bus A and the same number to con-
nect its output to bus B. Two SRL cells are added in the scan path to control the two set of

transmission gates with their D-inputs connected to ground.

The last category (5) contains just a single l-bit delay latch. Since its 1-bit widm is far
less than the 18-bit bus width, it is best to use LSSD in this case. The delay latch only needs
to be converted to an SRL cell and then connected in the scan path with other SRL and TSRL

cells. The resultant increase in test vector length is only one bit.

This concludes the design modifications required on the DKS chip to be able to use the
BST technique for testing it. The various control signals that have been added to the chip in

the process are summarized in Table 5.1. The next section now describes the 110 design of the

DKS chip.

Table 5.1. Control signals added to the DKS chip for implementing BST.

 

 

 

 

 

 

 

 

No. Control Signal Function
1 EXGt Enable transmission gate of TSRL
2 MO Connect M1 to bus A and M2 to bus B
3 A0 Connect A1 to bus A and A2 to bus B
4 M31 Connect bus A to input of M3
5 M30 Connect output of M3 to bus B
6 Av Connect angle registers to bus A
7 AT Connect bus A to register file

 

 

 

 

 

Table 5.2. U0 pins required for testing the DKS chip.

 

 

 

 

 

 

No. 1/0 pin Normal Connection
1 A clock Ground
2. B clock Ground
3 En +5V
4 SDI Ground
5 SDO Open

 

 

 

 

 

49

50

5.2. Input/Output Design

When the DKS chip design was presented in [5], the I/O design was not finalized

because it was assumed that DFI‘ will have an impact on its design. Now that the design of the

DKS chip is complete in all other respects, the 110 design can be finalized. The U0 signals can

be broadly classified into two categories: test I/O and operational U0. The five test I/O pins

required to implement BST have already been described in the previous section. These pins are

only used during the testing process. Table 5.2 summarizes the various test pins and at what

values to tie them during normal system operation of the circuit.

The operational I/O signals are used in both the normal as well as test mode of the cir-

cuit. They include all power lines, control signals, as well as data I/O lines. Following is a

brief description of all the pins required on the IC.

1.

3.

V“ and Ground: These two pins provide power to all the chip circuitry. Since TTL compati-
ble CMOS technology is being used for the IC, the V“, pin has to be connected to the posi-

tive terminal of a +5V power supply and Ground pin to its negative terminal.

411 and 62: The DKS chip requires an external two-phase non-overlapped clock which is
provided through these two pins.

RESET: This pin is connected to the counter of the control logic section and to all Other
latches and registers in the circuit which have a CLEAR signal available. It is an active high
signal. Externally, it can be connected to the controlling computer and/or to a small

power-on reset circuitry.

Chip Select (ES): The U0 of DKS chip is designed so that it can serve as a part of a full
robot control system. Most computerized systems use data and address busses to transfer
data from the CPU to all the other chips in the system. When a chip is selected by the
CPU, the address is decoded and then an appropriate chip is selected by the CE signal. It is
an active low signal, thus it allows data transfers to and from the system bus only if this

signal is held low.

.51..

5. SITE and DINO — DINll: These 13 pins work together to input data from the system into the
angle registers of the chip. Data input DINO to DINll is the 12-bit input port of the chip
which is connected to the input angle register-S. If STE- (Shift and Input Latch Enable) and
a are both law, then during phase one of the system clock, data from all angle registers is
shifted to the next lower register in sequence and data at the input port is latched into
angle register-5. Thus all the six angle registers can be set in six system clocks by applying

one angle in each clock cycle in sequence from 0 to 5.

6. m Once all the angle registers are set, then calculation of the DKS can begin. The
changing of this signal START from high to low signals the counter of control logic to start
counting until all the 73 states required to calculate the DKS are over. If at the end of 73
states, m7 is still low, the calculation starts all over again otherwise the counter stops

and the chip does nothing until some other external signal becomes active.

7. W DVAL, andDOUTI) — DOUT 15: These pins provide the final values from the register
file to the output port. The 00070 to DOUT 15 (Data Output) pins provide the 16-bit tristate
output that can be connected to the system data bus. When SO—UT (Shift Out) and CE are
both low then during phase one of the system clock data from each register in the register
file is shifted to the next higher register and the contents of register-8 are provided at the
output pins. The DVAL (Data Valid) pin is then taken high at the end of phase 1 of the
system clock to signal the system that data on the bus is valid data. DVAL is kept high

until either C—S goes high or until the beginning of the next clock cycle.

8. HALT: This is an emergency signal that stops all operations on the chip by stopping the
control logic state counter. The data in the chip is undefined after this signal is given so

that the only valid operations after a HALT signal are a RESET or a SILE with CE and DIN.

Table 5.3 summarizes all the operational I/O signals for the DKS chip. There are a total
of 38 pins including the 12-bit input data and the 16-bit output data pins. The number of pins
required to implement BST is five taking the grand total to 43. This number is well within the
capacity of the inexpensive Dual-in Line Packages (DIPs).

Table 5.3. 1/0 pins required for the DKS chip.

 

 

 

 

 

 

 

 

 

 

I/O Pin Function
Vcc +5V Power supply
GND Power supply ground
¢i phase 1 clock
¢2 phase 2 clock
RESET Reset all latches
_ ES Chip Select
S7175- Shift and input latch enable
DINO - DIN 11 12 bit angle input
@173? Start DKS claculation

 

DOUTO - DOUTIS

16 bit data output

 

 

 

 

SOUT Shift out data
DVAL Data valid at DOUT pins
HALT Emergency stop

 

 

 

VI. TEST GENERATION

Test generation involves finding a set of input vectors for the circuit under test which
allow for the detection of faults by observing the primary outputs of a circuit. One such set of
vectors is the complete set of all possible input vectors of the circuit under test (Exhaustive
testing). Though such a test would test the circuit for all possible faults, it requires a very long

time to run, especially for complex sequential circuits, and thus, is not practical.

Success of a testing process is generally measured in terms of the percent fault coverage
against a pre-defined set of faults. Many different types of faults can occur on an IC. Stuck-at-
zero, stuck-at-one, bridging faults, open circuit faults and CMOS-stuck-open faults are just a
few categories. There may also be multiple faults in the circuit. Usually a single stuck-at fault
model is assumed and then test vectors generated for the model. It has been shown that this
model is able to detect many of the bridging, open circuit, and multiple faults too, and is thus

considered sufficient for the testing of most circuits [3].

It is here, during the test generation process, that the importance of the DFI‘ techniques is
realized. All the structured DFI‘ techniques are aimed at reducing sequential circuits to combi-
national ones for testing purposes. Further, the circuit can be partitioned along functional lines
and test vectors can be generated for each of the partitions independent of the others. This
becomes possible with the DFI‘ techniques because they provide full access to all the partitions
in the circuit.

The goal of test generation for the DKS chip is severalfold and in the order of impor-
tance is:

1. chip design verification;

2. fault detection using fault simulation;
53

.54.

3. manufacturing testing.

Only the first two are of our interest here because the chip is being initially fabricated as
a prototype. If manufacturing testing is to be done eventually, the test vectors developed here

can be applied and more added to increase the fault coverage if necessary.

There are two types of test strategies that can be used to test a circuit. One is structural
testing and the other is behavioral (or functional) testing. Structural testing requires a low level
(at least gate level) description of the circuit and a fault model. It is used to verify the physical
device against the logic design, which is assumed to be correct. Thus a design verification is

not possible by this method.

Behavioral testing, on the other hand, tests the functional behavior of the circuit. Various
device descriptions above the gate level can be used to test a circuit. It is usually used when a

gate level description of the circuit is not available.

The test goals for the DKS chip at this stage closely match the requirements of
behavioral testing. One reason is that gate level description of the circuit is not available and
second is that design verification is required for it. Thus if test vectors could be generated to

test the functionality of the circuit, then they can be used independently of the implementation.

6.1. Test Generation Methods

There are four methods available to generate tests for a circuit: manual test generation,
universal tests, pseudo-random test patterns, and algorithmic methods. Manual test generation
is only possible for very small circuits or some special components like RAMs. It is usually

based on the intuition of the designer with no guarantee for success.

Universal tests provide a general set of vectors to test all or a subset of any circuit
without any calculation or simulation. Exhaustive testing lies under this category, which is
obviously impractical for large circuits. Some other test sets have also been prepared for PLAs
and a few specific types of circuits. However, at this time no universal tests really exist that

can handle all circuits.

55

Pseudo-random testing technique uses random numbers as test vectors for the circuit.
Still, a fault model and description of the circuit is required to calculate the fault coverage.
Probabilistic methods are also being used nowadays to find the expected fault coverage using

random patterns [29,30,31]. It is very difficult to do a design verification using this method.

The most widely used test generation method is the algorithmic approach. This approach
is mostly based on path sensitization techniques whose aim is to provide a path from the pri-
mary inputs to all points in the circuit and then from there to the primary outputs. D—algoridrm
[28,32], PODEM [33], and compiled code Boolean simulation [34] are a few of the algorithms
developed for this purpose. Most of these algorithms are deterministic and can find a test vec-
tor if it exists. However, even such techniques become very time consuming for large circuits

and thus are not very attractive for VLSI.

Since the DKS chip has been partitioned into modules and all the modules can be tested
independently, the type of test generation method used for each can be selected individually.
The next section deals with the selection of the test process as well as actual test vector gen-

eration for each type of module in the chip.

6.2. Test Vector Generation

The various circuit modules on the DKS chip can be classified into the following six
categories:
0 SRL and TSRL cells;
0 control logic ROM;
0 busses A and B;
0 ROM to store table values;
0 storage latches (LX, M1, M2, M3, Al, A2, Creg, Sreg, and 2-stage delay);
0 shift registers (angle registers and register file);

0 combinational circuits (MPYl, MPYZ, and Adder).

-S6

The test patterns required to test the SRL and TSRL cells are specified in the BST tech-
nique. The same two tests (shift test and flush test) can be used here without any further
changes. Similarly the procedure to test the control logic ROM and the internal busses has
been completely specified in the BST procedure. Thus no test vectors are required to be gen-

erated for the first three categories of modules.

The next category of modules is the ROM to store table values. There is no other method
to test a ROM other than by exhaustive testing. Moreover, it can be easily used now since the
input and output of ROM are both accessible through the TSRL cells. Since the input angles
are 12 bits each, 212 (4096) test patterns are required to verify all the ROM contents along with
the SIN/COS combinational circuitry at its input. Five test vectors are also required to verify

the contents of the ROM used to store the five constants.

Test vectors for all the latches are required next. Since the latches are only used to store
18 bit data and are not intended for any other special operation, they can be simply tested by
using the following four vectors for each latch. First is a set of all zeroes, then a set of all
ones, then a sequence of 00110011.... and lastly a sequence of 11001100... . These vectors can

detect all stuck-at faults as well as most of the shorting and bridging faults in the latches.

The six angle registers and the nine registers in the register file constitute the sixth
category. As has been already identified in Chapter IV, shift tests and flush tests have been
found sufficient to test all shift registers. Thus the same tests that are used to test SRL and

TSRL cells can be used here also.

The last category of modules is the combinational circuits. The 18-bit Baugh-Wooley
multiplier and the 18-bit Ripple Carry Adder (RCA) are the only two combinational circuits on
the chip. Test vector generation of these circuits is not as easy as has been for the other
modules. Thus various test generation methods are discussed in the next section and one of

them chosen to test the combinational circuits.

57

6.3. Test Generation for Combinational Circuits

The first and the easiest method would be to do an exhaustive test of each combinational
circuit. Since each of these circuits operates on two 18-bit operands, the number of test vectors
required to exhaustively test them will be 23‘ each. Since it requires approximately 100 clock
cycles to apply one test vector to each circuit and assuming a clock speed of 10 MHz (since
the DKS chip has been designed for l to 14 MHz), the time required to test each of them is
about 8 days. Such a long time to test any circuit is totally unacceptable, so this method is dis-

carded.

The next method is to generate test vectors manually. This is also not suitable considering
the size of the 18-by-18 multiplier and adder. Test generation by hand usually relies on intui-

tion of the designer who observes the truth table of the circuit and decides what tests to use.

AnOther method is to use pseudo-random test patterns. Though random patterns have
been used to test many circuits with good results, their disadvantage is that they do not pro-
vide ample capability for the type of design verification which is important for the DKS chip
as a prototype.

The last method is to use one of the algorithmic methods to generate teSt vectors for each
of the modules. Computerized test generation programs are usually used for all large combina-
tional circuits. Since both the multiplier and the adder have very regular structures, the
extended D-algorithm as proposed in [35] was chosen to generate test vectors for the functional
tests. The extended D-algorithm was chosen because it is a simple extension of the D-
algorithm, which is the most widely used algorithm for generating test vectors for combina-

tional circuits.

The basic components used for the adder and the multiplier are inverters, AND gates,
XOR gates, Full Adders (FA), and 2-to-1 multiplexers. The D-propagation tables for these
components are first made as shown in Tables 6.1 to 6.5. The tables show how a logical value
D at one of the component’s inputs will be reflected at its output. The aim of D-algorithm is to

provide test vectors so that each node in the circuit can reach the value D from its primary

Table 6.1. D-propagation table for an Inverter.

 

Input Output

 

UIUHO
UUIOH

 

 

 

 

Table 6.2. D-prOpagation table for an AND Gate.

 

 

 

AND 0 1 D D x
o 0 0 o 0 0
1 o 1 D D X
D o D D o x
D o D o D x
x o x x x x

 

 

 

 

 

 

 

 

Table 6.3. D-propagation table for an XOR Gate.

 

 

 

 

 

 

 

 

 

XOR 0 1 D D x
o o 1 D D x
. 1 1 o D D x
D D D 0 1 x
D D D 1 0 x
x x x x x x

 

 

58

Table 6.4. Partial D-propagation table for a Full Adder.

 

OODD

 

Sum Cout

D DDD

D

 

ODIO

 

000.1

1

DD0

1D

 

 

ABCin

 

DODD

D

DDD

DD

 

 

Table 6.5. D-propagation table for a 2-to-1 multiplexer.

 

 

 

 

 

m 101DD0D_D1
C 01101DDDD
B X01XD0101
A 1XXDX0011

 

 

 

59

b1 0|

 

 

 

 

 

 

 

* o
8A2 ———)o M u x é—SM

 

 

o ' * 0
81°12 ——)~ M u x '6—3‘“

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

n 1
1 n
D (3.3

n 0 c F A ‘ H

c.(—— F A 'é—CH ' f

_’ 5

n
s.
s,
(a) (b)
_b| 0|
b1 _ °I D I 1
1 n
1 1 {—o—sm
o 3A2——) M u x '
saa ————) M U x 'é—SM
1
1 n D
o D (.1...C

€— ‘ 1
C1 D ‘ F A CH C. F A '-

 

 

 

UI
<-——i
”22:.

(c) (‘1’

Figure 6.1. Various test vectors applied to a slice of the RCA adder.

6O

61

inputs and its effect should be directly observable at the circuit’s primary outputs.

To generate test patterns for the adder, consider the slices of the RCA adder as shown in
Figure 6.1. Each of the slices shows a different input vector being applied to it and the output
that it will produce (which is incidentally the same in all the cases). Each figure actually
represents two tests since each D has to first be replaced by a 0 and then by a 1. Observe that
ifalltheseeighttestsareperformed,theneachnodeinthecircuitgoestoa0aswell astoal

at one time or another.

The inputs to each slice can be set independently of the others except for the carry-in
which is propagated from the previous slices. A carry-in of 0 for each slice can easily be
achieved by forcing all the inputs of all other slices of the adder to zeroes. The only exception
is the first slice where the carry-in is connected to SA. For the first three vectors when SA-O,
the first slice behaves in a manner similar to the others. However, when SA-l (fourth vector),

the sum is equal to D and carry out is 1.

Thus eight tests are required to test each of the slices in the adder, taking the total
number of test vectors for the adder to 144 (18x8). Appendix A shows all the test vectors gen-
erated for the Adder. Only four test vectors are shown for each slice. The D can be first
replaced by a 0 and then by a l to get the actual eight vectors. Again, since the expected result

for each set of four test vectors is the same, one result is shown after each set of four vectors.

The last module in the circuit for which tests have to be generated is the multiplier,
which is an 18-by-18 Baugh-Wooley array multiplier. It is the most complex module of the
DKS chip with regard to size. It is made of 309 full adders, 324 AND gates, and 36 inverters.

The whole array is regularly structured except for the last two rows and the last slanting
column. On close observation it is found that if the sum and carry outputs of each of the full
adders is set to D and is made observable at the output, all stuck-at faults at the nodes can be
detected. From the D-propagation table of the full adder, it is seen that if one of the inputs is
0, another is 1, and yet another is D, then the sum is D— and the carry-out is D. The sum can be

propagated down to the output if all the carry-ins for other FAs are zeroes. That can easily be

62-

achieved with a (0,0,0) input to all other adders. The carry-out can be similarly propagated
down in the next higher column. So two tests are required to test the output nodes of each of
the FAs, one with D=0 and the other with Dal. Thus the expected result will be all zeroes

except for a 5 in that column and a D in the next higher bit column.

However, there are a few complications. One is that when trying to set a particular node
to 1 or D, the inputs to some other full adders may also be set to a non-zero value in the pro-
cess. This will be reflected in the output as a 1 or a D in those particular columns. So the
expected result has to be changed in those columns. Another piculiarity is the last FA for 83,
where one of the inputs is always set to 1. When testing the FA above it which has 27,-, and I?”
as its inputs, the last FA receives a D carry-in and a 0 from the carry-out of its predecessor. So

its output is equal to 5 instead of a D.

Based on these observations, test vectors were generated for all the PAS. Since there are
309 full adders and the lowermost row of 19 FAs is tested at the same time as the one above
it, 580 (29OX2) test vectors are required to test the multiplier. Appendix B gives the full list of

test vectors along with the expected results for each vector.

This completes the test generation process for the DKS chip. A few things need to be
pointed out regarding the matter of test verification, which always follows a test generation
process. The purpose of test verification is to prove that the test vectors that have been gen-
erated are sufficient to test the circuit. The latches and registers in the DKS chip use standard
shift and flush tests, so there is no need to verify the vectors. Similarly, the ROMs are being
tested exhaustively, so the question of test verification does not arise at all. The only modules

that need test verification are the adder and the multiplier.

Fault coverage for a circuit is measured in terms of the percentage of faults covered by
the tests with respect to the fault model of the circuit. For both the adder and the multiplier, a
functional stuck-at model was assumed to generate test vectors. Since test vectors to test each
node in the functional circuit were individually generated by hand, a 100% fault coverage was

achieved. However, it has to be emphasised that a general stuck-at fault model was not

63-

assumed, so the fault coverage with respect to such a model will be less than the 100% figure
shown here.

The expected results for each test vector were generated with respect to the circuit con-
nections. To confirm that the results actually matched the test vector inputs to the adder and
multiplier, a random sample of 30 vectors for each of them was selected. More vectors were
selected near the boundaries where probability of error is higher. The input vectors for the
adder were then added by hand and the results always matched the expected results generated
(see Appendix A). Similarly for the multiplier, the test vectors were multipled by hand and
again results matched the expected results shown in Appendix B.

This concludes the test generation and verification process for the DKS chip. The next

chapter deals with the process of applying these vectors to the chip once it has been fabricated.

VII. TESTING THE DKS CHIP

Test application is the final phase of a testing process and can begin after the chip has
been fabricated and test vectors generated and verified. The tests are applied to the chip under
test with the help of Automatic Test Equipment (ATE). The ATE consists of a test bed on
which to place the chip under test. It is then programmed to apply the test vectors to the chip
and store the results in its memory. Most ATEs can also compare the results with the expected

results and generate diagnostics, depending on their capability.

The procedure to test a chip without any structured DFI‘ features is different from the
procedure for a chip with DFI‘. Further, it also depends on which of the DFI‘ techniques has
been used. In the earlier chapters, it was shown that BST is the most suitable technique for the
DKS chip. The process to test a chip with BST in general was explained in Section 4.2. It
involves testing each module on the chip one at a time independently of the others. The pro-
cedure to test the DKS chip in particular is explained in the first section of this chapter. The

second seetion then evaluates the performance of the testing process.

7.1. Test Application Process

The DKS chip has been partitioned into modules and each of them is tested indepen-
dently of the others. Since there are two internal busses on the DKS chip, it is possible to test
two modules at a time. So an effort is made to test two modules in parallel whereever possible.
To test any two modules in parallel, it should be possible to set both of them independently,
but at the same time. Also, it should be possible to scan out their outputs without any resource

conflicts.

64

65

The procedure to test each module depends on its type: whether it is a ROM, a latch, a
register, a delay element, or a combinational circuit. Also, the sequence in which some of the
modules have to be teSted is crucial because some of the modules are accessed through some
other ones. The sequence in which the various modules are tested for the DKS chip is listed

next.

1) Test the SRL and TSRL cells.

2) Test the bus and the transmission gates of TSRL cells.
3) Test the control logic ROM.

4) Test the angle registers and constants ROM.

The input of the angle registers is from the chip’s primary inputs and the ROM does
not require any input except for the address which is provided from the control logic. The
output of angle registers is through bus A TSRLs and of the constants ROM through bus B
TSRLs. Thus their are no resource conflicts among these two modules. Though the angle
registers require more test vectors than the ROM, some time is still saved by testing both of
them at the same time.

To test the angle registers, first set all of them to the test vector values using the normal
DKS chip’s input process. Then, scan in control signals to transfer data from one of the
registers and one of the constants to the TSRLs of bus A and B respectively. Apply one
system clock and scan out the TSRL contents to verify the results. The procedure is

repeated for each test vector and then for each angle register and each constant in the ROM.

5) Test the M1 and M2 latches.

Since M1 uses bus A for both its input and output, and M2 uses bus B, there are no
resource conflicts among them. To test these latches, test vectors for each of them along
with the control signals required to set them, are scanned in. One system clock is applied
and then control signals to transfer data into the TSRLs are scanned in. Again one system

clock is applied to transfer the data and the results are scanned out.

.66

6) Test the A1 and A2 latches.

The same procedure that was used to test M1 and M2 can be used here.

‘7) Test the LX latch and the C-register.

The LX latch uses the angle registers for its input, and M1 latch and bus A for its out-
put. On the other hand, the C-register uses bus B for its input as well as output, so both of
these latches can be tested at the same time. Since the angle registers and M1 have already
been tested at this point, they can now be used for providing access to the LX latch.

To test them, set one of the angle registers to the LX latch’s test vector value and set
TSRL for bus B to the test vector value of the C-register. Transfer data from that angle
register to LX latch and then to the M1 latch. Now load the TSRLs of bus A from M1 and

of bus B from C-register and scan them out. Repeat the procedure for all the test vectors.

8) Test the two-stage delay (LA) and the S-register.

The two stage delay uses bus A for its input, and A1 and bus A again for its output.
The S-register, on the other hand, uses bus B for its input as well as output. Since there are
no resource conflicts among them, they can be tested in parallel.

First the test vectors for both of them are scanned into their respective TSRLs and then
one system clock is applied to set them. Two more system clocks are applied to give two
clock delays and set the A1 latch from the two stage delay’s output. Lastly, A1 and the C—
register are both loaded into the TSRLs, the data in which is then scanned out.

9) Test the M3 latch and the register file.

The M3 latch uses bus A for its input and bus B for its output, while the register file
uses bus B for its input and bus A for its output. Each register in the register file is to be
tested independently of the others. So the M3 latch can be tested while testing one of the
registers and rest of the registers can be tested alone.

To test both of the modules together, both sets of TSRLs are set to test vector values.
One system clock is then applied to transfer data to M3 and the register under test. Control

signals to transfer data back into the TSRLs from the modules are scanned in and one

67

system clock is applied to load the TSRLs. The data in the TSRLs is then scanned out.

10) Test Dx and Tx ROM tables.

There is only one input for the two parts of the table ROM and it is through the angle
registers. The output of Dx is through bus B and the output of Tx is through bus A. Since
the ROM is to be tested exhaustively, the small combinational circuit at its input can also
be included in the tests. The test vector is first scanned into one of the angle registers and is
applied to the ROM during the next system clock cycle. The data at their output is then
transfened to the respective TSRLs and scanned out.

11) Test the MPYl unit.

The first part of multiplier requires two inputs: one from the M1 latch through bus A
and the other from the M2 latch through bus B. Since it utilizes both the busses for its
inputs, nothing else can be tested in its parallel. First, both its input latches M1 and M2 are
set to test vector values through the TSRLs. One system clock is applied and the result of
the operation is stored in the M3 latch, which can be scanned out through the TSRLs of the
bus B. The prowdure is repeated for all the test vectors.

12) Test the MPYZ unit.
The procedure to test MPY2 is the same as for MPYl except that only M3 needs to be
set to the test vector value. Its output is latched into A2 and is scanned out through the

TSRLs of bus B.

13) Test the adder.
The procedure to test the adder is exactly the same as for MPYl, except that Al and A2
are used for input instead of M1 and M2, and its output is directly latched into the TSRLs
of bus B through the pass transistors.

This completes the test application process for the DKS chip. To show that this applica-
tion process is really feasible and adequate for testing the DKS chip, the process was simu-
lated. Appendix C gives the complete listing of the simulation program. Given the structure of

the DKS chip along with the modifications suggested in Chapter V to implement BST, the

68

objective of the simulation is to show that this application process provides access to all the
modules on the chip through the scan path. Following is an explanation of the simulation pro-
gram.

The chip structure is simulated in two functions: phase_ane and phasc_two. Each of the
functions simulates all the operations performed during the respective clock cycles. The only
parameters that can be passed or accessed from these functions are the control signals and
TSRL cell values. Also, no other function in the rest of the program can use or set any of the
modules in the circuit except for the control signals and the TSRL cells that are accessible
through the scan path and the I/O signals.

The main program first initializes the ROM contents to some specific values and sets all
control signals, latches, and registers to an undefined value (-1). Then the main program calls
one function each to test each / each-pair of the modules, as numbered in sequence from 2 to
13 earlier in this Chapter. Thus each of the modules is tested independently of the odrers. The
module number 1 is the shift register of SRL and TSRL cells themselves that are assumed to

be accessible and thus do not need any simulation.

Each function to test modules, first prints the name of the module it is testing and then
reads the number of test vectors from the test vector file. The steps required to actually test the
modules are exactly as explained in that particular section in this Chapter and they are all
repeated for the number of test vectors for that module. The only operations that these func-

tions can perform are:
0 set SRL control signals;
0 set TSRL cells (from the test vector file);
0 reset the chip (set the counter of control logic to zero);
0 set I/O signals;

0 call phase_onc and phase_lwo functions;

69

0 print the contents of TSRL cells.

Restricting the operations that can be performed by the modules to these is in accordance

with the objective of the simulation.
The simulation ran successfully showing that it is possible to access all circuit modules of
the DKS chip using the SRL and TSRL cells. It also verified the test application process as

detailed earlier in this Chapter. The simulation proves the feasibility of using BST on the DKS
chip. The performance of the DKS chip with BST is now evaluated in the next section.

7.2. Performance Evaluation

The performance of a DFI‘ technique can be evaluated in terms of the following parame-

ters:
1. Area overhead required on the chip to implement the technique;
2. Number of 1C pins dedicated to testing;
3. Test application time;
4. Test vector length.

The performance of the testing process of the DKS chip will be compared among the
three possibilities that are present to test it. First is to design the chip without any testability
features and test it. The other two are to either implement LSSD or BST during the design pro.
cess and then test it. A measure of performance for each of the four parameters above will be

calculated for the three test possibilities.

The first parameter is the area overhead required to implement the DFI‘ technique.
Clearly, there will be no area overhead if none of the DFI‘ techniques is used at all. If LSSD is
used then all 458 latches have to be converted to SRLs. This amounts to an area overhead of
17%. On the other hand, if BST is used then 44 latches have to be converted to SRLs, and 7
SRLs. 36 TSRLs, and 138 pass-transistors have to be added. This is equivalent to an area
overhead of a little less than 10% on the DKS chip.

70

The second parameter of performance is the number of additional pins required on the
chip that are dedicated to testing. These pins do not provide any function during the normal
operation of the circuit and since I/O pins are very precious in VLSI, every effort should be
made to keep them to a minimum. Of course, if none of the DFT technique is used, no extra
pins will be required. LSSD requires four extra pins (SDI, SDO, and clocks A and B), while
BST requires five of them (the above four and 271').

The primary and the most important measure of a testing process is the test application
time. The objective of the DFI‘ techniques is to reduce the time required to test the chip. Since
the DKS chip has a 12-bit data input and 458 latches, the number of test vectors required to
test the chip exhaustively is 2‘2“" = 2‘”. This converts to a testing time of 10‘” years. If BST
is used then the chip is partitioned and each module is available separately for testing. Table
7.1 shows the number of test vectors and the corresponding time required to test each of the
modules. It has been assumed that 100 clocks at 1 MHz clock speed are required to apply one
test vector, since the length of the scan path is 80 and a few system clocks may have to be
applied in the process. The total number of test vectors required are 5,629, so the total time

required to test the DKS chip using BST is 0.56 secs.

If LSSD is used, then the length of scan path is 458 and thus 458 useconds are required
to apply each test vector. However, all the modules can be tested in parallel now. So the total
time required to test the DKS chip will be the same as for the module which has the most
number of test vectors. Table 7.1 shows that the ROM requires 4096 test vectors, so the t0tal

time required to test the chip is 4096x458usecs - 187 secs = 3 mins.

The last parameter for measuring the performance of a DF’I‘ technique is the test vector
length. If none of the DFI‘ techniques is used, then the only access to the chip circuitry is
through the 12-bit data input pins on the chip. Thus the test vector length is only 12 bits. How-
ever, if some structured DFI‘ technique is used, then the test vector also includes all cells in its
scan path, in addition to the 12-bit primary data input. Larger test vector lengths require ATEs

with greater capacities to handle them, so it should be kept as small as possible. Since the

71

number of latches in the DKS chip is 458, the test vector length is 458 + 12 a 470. On the
other hand, if BST is used, two sets of TSRLs are added (2xlS = 36), control logic output latch
is converted to SRLs (37), and 7 SRLs are added to control extra signals, taking the total test
vector length to (36 + 37 + 7 + 12) or 92.

The various performance measures are summarized in Table 7.2. LSSD requires more
time for testing the chip, a larger area overhead, and a longer test vector length as compared to
BST. The only disadvantage of using BST is that it requires an extra pin over LSSD. Since the
advantages of BST far outweigh its only disadvantage, it is concluded that BST should be

implemented on the DKS chip to improve its testability.

Table 7.1. Test application time for various modules in the DKS chip.

 

 

 

 

 

Module Number of Total time
name test vectors (msec)
SRL and TSRL cells 4 0.4
Busses 4 0.4
Control logic 73 7.3
Angle registers 24 2.4
Constants ROM 5 *
M1 and M2 4 0.4
A1 and A2 4 0.4
LX 4 0.4
C-register 4 *
LA 4 0.4
S-register 4 *
Register file 36 3.6
M3 4 *
Dx and Tx ROM 4096 409.6
MPYl 616 61.6
MPY2 616 61.6
Adder 144 14.4
TOTAL 5629 562.9

 

 

 

Table 7.2. Comparison of the estimated overheads for the DKS chip.

 

 

 

 

 

 

 

DFT Area Overhead Number of Test vector Test Application
technique (%) extra pins length (bits) time (secs)
none - — 12
LSSD 17 4 458 187
BST 10 5 85 0.56

 

 

I"The time taken to test these modules is not used in the calculation of the total time because they are tested in parallel

with other modules.

72

 

VIII. CONCLUSION

The objective of this thesis is to incorporate DFT into the design of the DKS chip. It has
been recognized that testing VLSI chips is by no means a trivial process. Design for testability
techniques are being used nowadays to design the chips in such a way that they are easily
testable. This is especially true for semi-custom ASICs that require fast turnaround times and
can pay the price of a little area overhead on the chip. For these reasons, it was decided that

some DFI‘ technique must be implemented on the DKS chip.

The DKS chip has two internal data busses and it was observed that if they could be
somehow used to provide access to the majority of the storage elements on the chip, then the
area overhead required to implement a DFT technique can be reduced. This idea developed
into a new DFT technique - Bus Scan Testing (BST), that can be applied to all internal bus
architecture systems. BST integrates the concepts of partitioning, bus architecture systems and
scan techniques to provide access to all the storage elements in the circuit It results in a reduc-
tion of area overhead and shortens the test vector length. However, in some cases it may result

in longer test application times than the other structured DFT techniques.

Appropriate modifications were made in the design of the DKS chip to implement BST.
TeSt vectors were then generated separawa for each of the partitioned modules in the DKS
chip. The test application procedure for the DKS chip was then drawn out that included the
sequence in which various modules had to be tested and the steps to test each of them. A
simulation was then carried out to show that the modifications made on the DKS chip and the
test application process can provide access to all circuit modules and is sufficient to test the
DKS chip. Lastly, the testability design of the DKS chip was evaluated which confirmed that
BST was the best available DFT technique that could be applied to the DKS chip.

73

74

The BST technique, as described, provides many advantages over Other DFT techniques
for internal bus architecture systems. However, there is still further scope of improvement. One
is to try to convert one of the circuit latches themselves to TSRLs and then use BSI‘. Though
the idea seems to be plausible, further simulations and tests are required to prove that it will

not cause problems during normal circuit operation.

One area in which BST lacks diagnostic abilty is bus faults. Though BST detects most of
the bus faults on the chip, it does not give any indication as to the location of the faults. If
such a system can be developed, then even the control busses can be tested in addition to the

data busses being tested now.

APPENDICES

APPENDIX A

APPENDIX A

TEST VECTORS FOR ADDER
g = 3
ba ba ba ba ba ba ba ba ba ba ba ba ba ba ba ba ba ba 8A1 8A2

bit#17 161514131211 1009080706050403020100

O oooooooooooooooooooooooooooooooooom 0 0
0 01010101010101010101010101010101011g
oooooooooooooooooooooooooooooooooooar O 0

.—
0

Result: 000000 00000000 00dg
0 1010101010101010101010101010101010g101
Result: 00000000000000001d

000000000000000000000000000000001d00
010101010101010101010101010101011g01

00m0000000000000000000000000000d100
10101010101010101010101010101010g110

e-Ir-Ie-Ir-e
000—0
#000

Result: 00 0000 0000 0000 Odgx

0000000000000000000000000000001d0000
010101010101010101010101010101lgOlOl
000000000000000000000000000000le000
1010101010101010101010101010 lOgl 1010

NNNN
00H0
H000

Result: 00 0000 0000 0000 ngx

oooooooooooooooooooooooooooordoooooo
0101010101010101010101010101 13010101
oooooooooooooooooooooooooooodroooooo
101010 1010 1010 10101010 10 lOlOgl 101010

00:00
00H0
~000

Result: 00 0000 0000 000d gOOx

4 OOOOOOOOOOOOOOOOOOOOOOOOOOldOOOOOOOO 0 0
4 01 0101 01010101010101 01 01 01 1g01 010101
4 OOOOOOOOOOOOOOOOOOOOWOOOOleOOOOOOO 0 0

3.:
O

75

4

76

10101010101010101010101010 g1 10101010

Result: 00 0000 0000 OOdg 000x

MMMUI

DONOOOOOOOOOOWOOOOOOOOIdOOOOOOOOOO
010101010101010101010101 1g0101010101
OOOOOOOOOOOOOOOOOOOOOOOOdIOOOOOOOOOO
101010101010101010101010g1 1010101010

ResultOOOOOOOOOOOnglXJOx

0000

00000000000000000000001d000000000000
0101010101010101010101 1g010101010101
MCDOOOOOOOOOOOOOOOOWleOOOOOOOOOOO
101010101010101010 10 10 gl 101010101010

Result: 00 0000 0000 ngO 000x

~3~J~l~l

00m00000000000000001d00000000000000
01010101010101010101 1g01010101010101
00w0000000000000000d100000000000000
10101010101010101010g110101010101010

Result: 00 0000 000d gOOO 000x

cococeoo

OOWOOOOOOOOOOOOOOldOOOOOOOOOOOOOOOO
010101010101010101 1g0101010101010101
OOWOOOOOOOOOOOOOOleOOOOOOOOOOOOOO
101010101010101010gl 1010101010101010

Result: 00 0000 OOdg 0000 000x

O‘D‘O‘O

OOWOOOOOOOOOOOOIdOOWOOOOOOOOOOOOOO
01010101010101011g010101010101010101
OOWOOOOOOOOOOOOdIOOWOOOOOOOOOOOOOO
1010101010101010gl 101010101010101010

Result: 00 0000 0ng 0000 000x

10
10
10
10

00w00000000001d00000000000000000000
010101010101011301010101010101010101
oooooooooooooodloooooooooooooooooooo
10101010101010g110101010101010101010

Result: 00 0000 ngO 0000 000x

ll

OOWOOOOOOOOMOOOOOOOOOOOOOOOOOOOOOO

00—‘0 00~0 00I-‘0 00H0 00-‘0

00H0

#000 #000 H000 #000 H000

H000

77

ll 010101010101lg0101010101010101010101
11 oooooooooooodroooooooooooooooooooooo
11 101010101010g1 1010101010101010101010

Result: 00 000d gOOO 0000 000x

12 00m0000001d000000000000000000000000
12 01010101011g010101010101010101010101
12 oooooooooomoooooooooooooooooooooooo
12 1010101010g11010101010101010 101010 10

Result: 00 00dg'0000 oooo 000x

13 oooooooordoooooooooooooooooooooooooo
l3 010101011g01010101010101010101010101
l3 OOOOOOWdIOOOOOOOOOOWOOWOOOOOOOOOO
13 10101010g1 10101010101010101010101010

Result: 00 Ong 0000 0000 000x

l4 oooooordoooooooooooooooooooooooooooo
14 0101011g0101010101010101010101010101
14 000000d10000000000000000000000000000
14 101010gl1010101010101010101010101010

Result: 00 ngO 0000 0000 000x

15 oooordoooooooooooooooooooooooooooooo
15 0101 1g010101010101010101010101010101
15 OOWdIWOOOOOOOOOOOOWOOWOOOOOOOOOO
15 1010g1 101010101010101010101010101010

Result: 0d g000 0000 0000 000x

16 oordoooooooooooooooooooooooooooooooo
16 01 1g0101010101010101 0101010101010101
16 00d1oooooooooooooooooooooooooooooooo
16 10 gl 10101010101010101010101010101010

Result: dg 0000 0000 0000 000x

17mmmmmmmmmmmmmmmmmm
17 1g 01 0101010101 0101 01 or 01 or or 0101 0101
17mmmmmmmmmmmmmmmmww
17 gl 10101010 10101010 10 1010 10 10 1010 1010

Result: g0 0000 0000 0000 000x

00-‘0 00-‘0 00~0 00H0 00v-e0 .-

00-‘0

H000 #000 #000 #000 #000

H000

APPENDIX B

APPENDIX B

TEST VECTORS FOR MULTIPLIER

ba ba ba ba ba ba ba ba ba ba baba ba ba ba ba ba ba
171615141312111009080706050403020100
000000000000000000000000000000001d11
00000000000000000000000000000000d0g1
OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOdll 10
OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOdOgIO
OOOOOOOOtDOOOOOOOOOOOOOOOOOOOOldOOll
0000000000000000000000000000000ddg01
00000000000000000000000000000d011010
OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOdOglOO
00000000000000000000000000000d1001 10
000000000000000000000000000000ddg010
OOOOOOOOOOOOOOOOOOOOOOOOOOOOIdOOOOll
OOOOOOOOOOOOOOOOOOOOOOOOOOOOOdOngOl
000000000000000000000000000d01001010
00000000000000000000000000000d0g1000
OOOOOOOOOOOOOOOOOOOOOOOOOOOdOOIIOOIO
00000000000000000000000000m0ddg0100
OOOOOOOOOOOOOOOOOOOOOOOOOOOleOOOl 10
0000000000000000000000000000d0dg0010
OOOOOOOOOOOOOOOOOOOOOOOOOOIdOOOOOOll
OOOOOOOOOOOOOOOOOOOOOOOOOOOdOOngOOl
OOOOOOOOOOOOOOOOOOOOOOOOOdOlOOOOlO 10
OOOOOOOOOOOOOOOOOOOOOOOOOOOOdOglOOOO
oooooooooooooooooooooooooaooor 100010
OOOOOOOOOOOOOOOOOOOOOOOOOOOOdnglOOO
OOOOOOOOOOOOOOOOOOOOOOOOOdOOIOOIOOIO
OOOOOOOOOOOOOOOOOOOOOOOOOOOdOngOlOO
0000000000000000000000000le00000110
00000000000000000000000000d00dg00010
OOOOOOOOOOOOOOOOOOOOOOOOldOOOOOOOOll
0000000000000000000000000d000d300001
00000000000000000000000d010000001010
000000000000000000000000000d0g100000
00000000000000000000000d000100100010
OOOOOOOOOOOOOOOOOOOOOOOOOOOdnglOOOO
oooooooooooooooooooooooaoooouooooro

78

a3b3
a2b4
a2b4
ale
ale
a0b6
a0b6
a6b1
a6b1
a5b2
a5b2
a4b3
a4b3
a3b4
a3b4
a2b5
a2b5
a1b6
a1b6
a0b7
a0b7
a7b1
a7b1
a6b2

a5b3
a5b3
a4b4
a4b4
a3b5
a3b5
a2b6
a2b6
alb7
a1b7
a0b8
a0b8
a8bl
a8b1
a7b2
a7b2
a6b3
a6b3
a5b4
a5b4
a4b5
a4b5

79

mmmmmmmmmmmmmwumwm
mmmmmmmmmmmmmmmmmw
mmmmmmmmmmmmmmummm
wmmmmmmmmmmwmmmmmm
mmmmmmmmmmmmmmummw
mmmmmmmmmmmmwmmmmu
mmmmmmmmmmmwmmammm
mmmmmmmmmmwmmmmmmm
mmmmmmmmmmmmmwymmm
mmmmmmmmmmwmmmmmmm
mmwmmmmmmmmmmmwwmm
mmmmwmmmmmwmmmwmmw
mmmmwmmmmmwmmwwmmm
mmmmmmmmmmmmmmmmmw
mmmmmwmmmmmmwmwmwm
mmmwmmmwmmwmwmmmmm
wmmmmmmmmmmwmwwmmm
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mmmwmmmmmmmwmwwmmw
mmmmwmmmmmmmmmwmmu
mmmmmmmmmmwmmwwmmm
mmmmmmmmmwmmmmmmmm
mmwmmmmmmmwmwmwmmm
mmmmmmmmwmmmmmmwmw
mmmmmmmmmmmmmgmmmm
wmmmmmmmmmmmmmmmmm
mmmmmmmmmmmmwammmm
mmmmmmwmmmmmmummmw
mmmmmmmmmmmwmummmm
mmmmmmmmmwwmwmmmmw
mmmmmmmmmmmmmgmmmm
mmmmmmmmmmmwmmmmmw
mmmmmmmmmmmmmummmm
mmmmmmmmmmmmmmmmmw
mmwmmmmmmmwmmqmmmw
mmmmmwmmmmmmmmmmmu
mmwmmmmmmwmmmummmm
mmmmwmmwwmmwmmmmmm
mmmmmmmmmmmmwymmmm
mmmmmmmmmmmmmmmwmw
mmmmmmmmmmmmwwmmmm
mmwmmmmmwmmmmmmmmm
mmmmmmmmmmmmmmmmmm
mmmmmmmmwmmmmwmmwm
mmmmmmmmmmmwwwmwmm
mmmmmmmmmmmmwmmmmm
mmmmmmmmmmmmwmmmmm

a3b6
a3b6
a2b7
a2b7
a1b8
a1b8
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aOb9
a9b1
a9b1
a8b2
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a7b3
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a5b6
a5b6
a4b7
a4b7
a3b8
a3b8
a2b9
a2b9
alblO

80

oooooooooooooooooaooooroooooorooooro
00(X)00(X)00(X)00(X)00(X)d0(X)0d1§)00(1)10(X)
oooooooooooooooooaoomooooooooorooro
00(1)(XIOO(I)001]3(K)00(k1(Kl00(klgOlJ)(X)01(X)
oooooooooooooooooaroooooooooooooor 10
(X)00(X)00(XJOO(X)00(X)d0(X)00(klg0(X)00(X)10
00(X)00(X)00(X)00(X)lle)00(X)00(X)00(X)00111
(X100(X)00(X)00(X)00(k100(X)00(k1g0(X)00(X)01
OOOOWOOWOOOOOdOIOOOOOOOOWOOOOIO 10
00(X)00(X)00(X)00(X)00(X)00(k10giK)00(X)00(X)
oooooooooooooooaooorooooooooooroooro
00(X)00(X)00(X)00(X)00(X)00(Xldglll(X)00(X)00
oooooooooooooooaooooorooooooroooooro
00(X)00(X)00(X)00(X)00(X)00<K)dg(X)10(X)00(X)
oooooooooooooooaooooooorooroooooooro
00(X)00(X)00(X)00(X)00(X)0d(1)dg(X)01(X)OO(X)
00(XJOO(X)OO(X)00(X100(X)OO(X)11.00(X)00(X)10
OOlX)00(X)00(X)00(X)00(X)d0(X)dg(X)002H)00(X)
oooooooooooooooaooooooroooorooooooro
00(X)00(X)00(X)00(X)00(k100(1)dg1])(K101(1)00
000000000000000d00001000000001000010
00(X)00(XJOO(X)00(X)00tK)OO(X)dg(X)00(X)10(X)
oooooooooooooooaooroooooooooooorooro
00(1)00(X)00(X)00(X)0d(X)00(X)dng)00(X101(X)
oooooooooooooooaroooooooooooooooor 10
00(X)00(X)00(X)00(X)d0lX)00(X)dg(X)00(X)002H)
00(X)00(I)(K)00(X)1leJCK)00(1)(K)00(X)(X)00 11
00(X)00(X)00(X)00(klOOlX)00¢X)dg(IJCK)00(X)01
oooooooooooooaorooooooooooooooooro 10
00(X)00(X)00(X)00(X)00(X)00(Klgl(X)00(X)00(X)
oooooooooooooaooorooooooooooooroooro
00(X)001!)00(X)00(X)00(X)00<k1g0‘H)(K)00(X)OO
oooooooooooooaooooorooooooooroooooro
OOOOWOOWOOOOOOOOOOOdOngOlOOOOOOOO
oooooooooooooaooooooorooooroooooooro
00(X)00(X)00(X)00(X)00(X)d0(klg0(X)lOlX)00(X)
oooooooooooooaoooooooom 100000000010
00(X)OO(X)00(X)00(X)OO(X100(Xlg0(X)01(X)00(X)
OOOOMOOWOOOdOOOOOOOOlOOlOOOOOOOOlO
00(X)00(X)00(X)OO(X)00<K)00(klgO(X)001H)00(X)
oooooooooooooaooooooroooooorooooooro
00(X)OO(X)00(X)00(X)Od(X)00(klg0(I)(KIOI(X)00
oooooooooooooaooooroooooooooorooooro
00(X)00(X)00(X)00(X)d0(X)00(klgO(X)00(X)10(X)
oooooooooooooaooroooooooooooooorooro
00(X)00(X)00(X)00(XIOO(X)00(11g0lX)00(X)01(X)
oooooooooooooaroooooooooooooooooor 10

alblO
aObll
a0b11
allbl
allbl
a10b2
alOb2
a9b3
a9b3
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a8b4
a7b5
a7b5
a6b6
a6b6
a5b7
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a4b8
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a2b10
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albll
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a12b1
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a10b3
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a7b6
a7b6
a6b7
a6b7
a5b8
a5b8
a4b9
a4b9
a3b10
a3b10

81

00(X)00(X)00(X)00<K)00(X)00(klg0(X)00(X)00‘HJ
00(X)00(X)00(X)ldll)OOlX)00(X)00(X)OO(X)00'11
00(X)00(X)00(X)0d(X)00(X)00(klg0(X)00(X)00l11
oooooooooooaorooooooooooooooooooro 10
00(X)00(X)00(X)00(X)00(X)0dlhg10(X)OO(X)00(X)
oooooooooooaooorooooooooooooooroooro
00(X)00(X)00(X)00(X)00(X)0dtkg01(X)00(X)00(X)
oooooooooooaooooorooooooooooroooooro
(X)00(X)00(X)00(X)00(1)00tKJdg(I)10(X)00(X)00
oooooooooooaooooooorooooooroooooooro
(X)00(X)00(X)00(X)00(X)0d(X)dg(X)01(X)00(X)00
ooooOooooooaooooooooorooroooooooooro
(X)00(X)00(X)00(X)00(X)d0(X)dg(XJOO3H)00(X)00
(X)00(X)00(X)0d(X)00(X)00(X)11(X)00(X)00(X)10
00(X)00(X)00(X)00(X)0d(X)00thg00(X)Ol(XIOOtX)
oooooooooooaooooooooroooorooooooooro
(X)00(X)00(X)00(X)00<K)00(X)dg(X)00(X)10(X300
oooooooooooaoooooorooooooomooooooro
(X)00(X)00(X)00(X)0d(X)00(X)dg(X)00(X)01(X)00
oooooooooooaooooroooooooooooorooooro
(X)00(1)00(X)OO(X)dO(X)00(X)dg(X)00(X)002H)00
oooooooooooaooroooooooooooooooorooro
00(X100(X)00(X)0d(X)00(X)00tn;00(X)00(X)01(X)
oooooooooooaroooooooooooooooooooor 10
(X)00(X)00(X)00(K)00(X)00(X)dg(X)00(X)00(X)10
00(X)00(X)00‘h100(X)00(X)00(X)00(X)00(X)00'Il
(X)00(X)00(X)0d(X)00(X)00(X)dg(X)OO(X)OO(X)01
oooooooooaorooooooooooooooooooooro 10
(X)00(X)00(X)00(X)00(X)00(K)gl(X)00(X)00(X)00
oooooooooaooorooooooooooooooooroooro
00(X)00(X)00(X)00(X)00(X)dd14)10(X)00(X)00(X)
oooooooooaooooorooooooooooooroooooro
00(X)00(X)00(X)00(X)OOlXIOdgflIOI(X)00(X)00(X)
oooooooooaooooooorooooooooroooooooro
(X)00(X)OO(X)OO(X)00(X)d0(klg01X)10(X)00(X)00
oooooooooaooooooooorooooroooooooooro
(X)00(X)00(X)00(X)00(k100(k1g0(X)01(X)00(X)00
OOOOWOOOdOOOOOOOOOOOl IOOOCDOOOOOOIO
00(X)00(X)00(X)00(X)d0(X)0dt§)00(X)10(X)00(X)
oooooooooaooooooooooroorooooooooooro
00(X)00(X)00(X)00(k100(X)OdtK)00(X)01(X)00(X)
OOOOWOOOdOOOOOOOOIOOOIDOlmOOOOOOlO
(X)00(X)00(X)00(X)d0(X)00(Xlg0(X)00(X)10(X)00
OOOOWOOOdOOOOOOIOOOOOWOOOlOOOOOOlO
(X)00(X)00(X)00(klOOlX)00(klg0(X)00(X301(X)00
oooooooooaooooroooooooooooooorooooro
00(X)00(X)OO(X)d0(X)00(X)0dg$)OO(X)00(X)10(X)

a2b11
a2b11
a1b12
a1b12
a0b13
a0b13
a13b1
a13b1
a12b2
a12b2
a11b3
a11b3
a10b4
a10b4
a9b5

a9b5

a8b6

a8b6

a7b7

a7b7

a6b8

a6b8

a5b9

a5b9

a4b10
a4b10
a3bll
a3b11
a2b12
a2b12
albl3
alb13
a0b14
a0b14
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a14b1
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a13b2
a12b3
a12b3
a11b4
a11b4
a10b5
a10b5
a9b6

a9b6

a8b7

82

mmmmwmwmmmmmmmmmwm
mmmmmwmmmmwwmmmmmw
mmmwmwmmmmmmmmmmmw
mmmmmwmmmmwmmmmmmm
mmmmmmmmmmmmmmmmmn
mmmmwmmmmmmmmmmmmm
mmmmmmmmmmmmmwmmmm
mmmmmmmmmmmmmmmmwm
mmmmmmmmwmmmmmmmmw
mmmmmmmmmmmmmmmmmm
mmmmmmmmmmmmmmmmmm
mmmmmmmmmwmmwmmmmm
mmmmmmmmmmmmmmmmmw
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mmmwmmmmmmmmmmmmmm
mmmmmmmwmmammmmmmm
mmmmmmmmmmummmmmmw
mmmmmmmwmmqmmmwmmm
mmmmmmmmmmmmmmmmmm
mmmmmmmmmmnmmmmmmm
mmmwmmmmwmmmmmmmmw
mmmmmmmwmmammmmwmm
mmmmmmmmmmmmmmmmwm
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mmmmmmwmmmmmmmmmmm
mmmmmwmmmmammmmwwm
mmmmmwmmmmmmmmmmmm
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mmmmmmmmmmmmmmmmmw
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mwmwmmmmmmummmwmmm
mmwmmmmmmmmmmmmmww
mmmmmmmmmwymmmmmmm
wmwmmmmwmmmmmmmmmw
mmmmmmmmmwwmmmmmmm
wmwmmmmmmmmmmmwmmw
mmmmmmmmmwwmmmmmmm
mmwmmmmmmmmmmmmmmw
mmmmmmmmwmwmmmmmmm
mmwmmmmmmmmmwmmmmm
mmmmmmmwmmwmmwmmmw
mmwmmmmmmmmwmmmmmm
mmmmmmmwmmwmmwmmmm
mmwmmmmmmmwmmmmmmw

a8b7

a7b8

a7b8

a6b9

a6b9

a5b10
a5b10
a4b11
a4b11
a3b12
a3b12
a2b13
a2b13
a1bl4
a1bl4
a0b15
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a9b7

a8b8

38b8

a7b9

a7b9

a6b10
a6b10
a5b11
a5b11
a4b12
a4b12
a3b13
a3b13
a2b14
a2b14
alb15
alb15

83

00(X)00(X100(X)Od(X)00(klgOlI)CK101(X)00(X)00
oooooaooooooooooooroorooooooooooooro
00(X)00(X)00(X)d0(X)00(k1g0(X)00(I)10(X)00(X)
oooooaooooooooooroooooorooooooooooro
00(X)00(X100(k100(X)00(k1g0(110011101(X)00(X)
oooooaooooooooroooooooooorooooooooro
00(X)00(X)00(K)00(X)00(k1g0(X)00(X)00‘HDCKlOO
00000d000000100000000000000100000010
00(X)00(X)0d(X)00(X)00(klg0(1)00(IJCK)01(X)00
oooooaooooroooooooooooooooooorooooro
00(X)00(X)d0(X)00(X)00(klg0lX)00(X)00(X)lOlX)
oooooaooroooooooooooooooooooooorooro
00(X)00(k100(X)00(X)00(k1g0(X)00(X)OO(X)01(X)
oooooaroooooooooooooooooooooooooor 10
00lX)00tK)00(X)00(X)00(klg0lX)00(X)00(X)00 H3
00(X)ld(X)00(X)00(X)00(X)00(X)OO(X)00(X)00111
00(X)0d(X)00(X)00(X)00(k1g0lX)00(X)00(X)00401
oooaorooooooooooooooooooooooooooro 10
00(X)00(X)00(X)00(X)0d(h;10(X)00(X)00(X)00(X)
oooaooorooooooooooooooooooooooroooro
00(X)00(X)00(X)00(X)Od<h;01(X)00(X)00(X)00(X)
000d00000100000000000000000010000010
(X)00(X)00(X)00(X)00tK)dg(X)10(X)00(X)00(X)00
000d00000001000000000000001000000010
(X)OO(X)00(X)00(X)0d(X)dg(X101(X)00(X)00(X)00
oooaooooooooorooooooooooroooooooooro
00(X)00(X)00(X)00<K)00¢h;00(I)10(X)00(X)00(X)
oooaooooooooooorooooooroooooooooooro
00(X)00(X)00(X)0d(X)00th;00(X)01(X)00(X)00(X)
oooaoooooooooooooroowooooooooooooro
(X)00(X)00(X)00<K)00(X)dg(X)OO(X)lOlX)00(X)00
00(klOOlX)00(X)00(X)OO111(X)00(X)(X)00(X)00 H0
(X)00(X)00(X)0d(X)00(X)dg(X)OO(X)01(X)00(X)00
oooaooooooooooooroooorooooooooooooro
00(X)00(X)00tfl)00(X)00¢h;00(X)00(X)10(X)00(X)
oooaooooooooooroooooooorooooooooooro
00(XJOO(X)0d(X)00(X)OO<h;00(1)00(X)01(X)00(X)
oooaoooooooorooooooooooooroooooooom
(X)00(X)OOtK)OO(X)00(X)dg(X)00(X)00(X)10(X)00
000d00000010000000000000000100000010
(X)OO(X)0din00lX)00(X)dg(X)00(X)00(X)01(XIOO
000d0000100000000000000000m01000010
00(X100(K)OO(X)00(X)00<u;00(X)00(X)00(X)101])
oooaooroooooooooooooooooooooooorooro
00(X)0d(X)00(X)00(X)00<u;00(X)00(X)00(X)01(X)
oooa1oooooooooooooooooooooooooooor 10
00(X)d0(X)00(X)00(X)00<h;OOIX)OO(I)00(X)OO H3

a0b16
a0bl6
ale2
a15b2
al4b3
a14b3
a13b4
a13b4
a12b5
al2b5
a11b6
a11b6
a10b7
a10b7
a9b8

a9b8

a8b9

a8b9

a7b10
a7b10
a6b11
a6b11
a5b12
a5b12
a4bl3
a4b13
a3b14
a3bl4
a2b15
a2b15
a1b16
a1b16
a0b17
a0b17
a15b3
a15b3
a14b4
a14b4
a13b5
a13b5
a12b6
a12b6
a11b7
a11b7
a10b8
a10b8
a9b9

34

mmmmmmmmmmmmmmmmmn
mmmmmmmmmqmmmmmmmm
mmmmmmmmmmmmmmmwwm
mmmmmmmmmwmmmmmmmm
mmmmwmmmmmmmwmmmwm
mmmmmmmmmwwmmmmmmm
mmmmmmmmmmmmmwmmwm
mmmmmmmmwwmmmmmmmm
mmmmmmmmmmmmmmmmwm
mmmmmmmwmwmmmmmmmm
mmmmmmwmmmmmmmmmmm
mmmmmmmmwwmwwmmmmm
mmmmmmmmmmmmmmmmwm
mmmmmmmmwmmmwmmmmm
mmmmmmmmmmmmmmmmmm
mmmmmmwmwwmmwmwmmm
mmmmmmmmmwmmmmmmwm
mmmmwwmmmwmmmmmmmm
mmmmmmmmmmwmmmmmwm
mmwmmmmmmwmmmwmmmm
mmmmmmmmmmmmmmmmmm
mmmmwmmmmwmmmmmmmm
mmmmmwmmmmmmwmmmwm
mmmmmmmmmwmmmmwmmm
mmmmwmmmmmmmmmmmwm
mmmwmmmmwwmmmmmwmm
mmmwmmmmmmmmmmmwmm
mmmmmmmmmwmmmmmwmm
mmwmmmmmmmmmmmmmww
mmwmmmmmwwmmmmmmmm
mummmmmmmmmmmmmmmm
mmmmmmmmmwmmmmmmmm
wmmmmmmmmmmmmmmmmw
mwmmmmmmmwmmmmmmmw
mmwmmmmmmmmmmmmmmm
mmmmmmmMgwmmmmmmmm
mmmmmmmmmmmmmmmmmm
mmmmmmwmuwmmmmmmmm
mmmmmmmmmmmmmmmmmm
mmwmmmmmammmmmmmmm
wmmmmmmmmmmmmmmwmm
mmmmmmmmmmmmmmmmmm
mmmmmmwmmmwmmmmwmm
mmmmmmmmummwmmmmmm
mmmmmmmwmmmmmmmmmm
mmmmmmmmnmmmmmmmmm
mmmmmmmmmmmmmmmwmm

a9b9

a8b10
a8b10
a7b11
a7b11
a6b12
a6b12
a5b13
a5b13
a4b14
a4b14
a3b15
a3b15
a2bl6
a2bl6
a1b17
a1b17
a15b4
a15b4
a14b5
a14b5
al3b6
a13b6
a12b7
a12b7
a11b8
a11b8
a10b9
a10b9
a9b10
a9b10
a8b11
a8b11
a7b12
a7b12
a6b13
a6b13
a5b14
a5b14
a4b15
a4b15
a3bl6
a3b16
a2b17
a2b17
ale5
ale5

85

mmmmmmmmummmwmmmmw
mmmmmmmwmwmmmmmmmm
mmmmmmwmqmmmmmmmmm
wmwmmmwmmmwmmmmwmm
mmmmwmmmummmmmmmmm
mmmmmwmmmmmmmmmmmm
mmmmmmmmummmmwmmmm
mmmmwmmmmmmmwmmwmm
mmmwmmmmummmmmwmmm
mmmwmmmmmmmmmmmwmm
mmmmmmmmammmmmwmmm
wmwmmwmmmmwmmmwmmm
mmmmmmmmqmmmmmmwmm
mnmmwmmmmmmmmmmmmm
mmmmmmmmqmmmmmmmmm
mmmmmmmmwwmmmmmmwm
mmmmmmmmmmmmmmmmwm
mmmmmmmmmmmmmmmmmm
mmmmmmmgwmmmmmmmmm
mmmwmmmmmmmmmmwmmm
mmmmmmmmwwmmmmmmmm
mmmmwmmmmmmwwmmmmm
mmmmmmmwwwmmmmmmmm
mmmmmwmmmmwwmmmmmm
mmmmmmwmwmwmmmmmmm
mmmmmmwmmmmmmmmmmm
mmmmmmmwwmmmmmmmmm
mmmmmmmwmmmmmmwmmm
mmmmmwmmwmmwmwmwmm
mmmmmmmmmmmmmmmmmm
mmmmmmmwwmmwmmmmmm
mmmmmmmmmwmmmmwmmm
mmmmmmmwwmmmmmmmmm
mmmmmwmmmmmmmmwwmm
mmmmmmmwwmmmmmmmmm
mmmmwmmmmmmmmmwmmm
mmmmmmmwwmmmmwmmmm
mmmmmmmmmmmmwmwmmm
mmmmmmmwwmmmmmmwmm
wmmmmmwmmmmmmwmmmm
mmmmmmmwwmmmmmmmmm
mummmmmmmmmmmmmmmm
mmmmmmmmwmmmmmwmmw
wmmmmmmmmmmmmmwwmm
mwmwmmmmwmmmmmmwmm
mmmmmmmmmmmmwwmmmm
mmmmmmmgmmmmmmmmmm

a14b6
a14b6
a13b7
a13b7
a12b8
a12b8
a11b9
a11b9

a10b10
a10b10

a9b11
a9b11
a8b12
a8b12
a7b13
a7b13
a6b14
a6bl4
a5b15
a5b15
a4b16
a4b16
a3bl7
a3b17
a15b6
a15b6
al4b7
a14b7
al3b8
a13b8
ale9
ale9

a11b10
a11b10
a10b11
alObll

39b12
a9b12
a8b13
a8bl3
a7b14
a7bl4
a6b15
a6b15
a5bl6
a5b16
a4bl7

86

0001000d0000000000000010001000000000
00(X)00(X)00(X)01(h;0d(X)00(X)00(X)00(X)00(X)
oooroooooaoooooooooorooooorooooooooo
(X)00(X)00(X)00iH)dg(X)d0(X)00(X)00(X)00(X)00
oomoooooooaoooooorooooooorooooooooo
(X)00(X)00(X)01(X)dg(X)0d(X)00(X)00(X)00(X)00
oooroooooooooaoorooooooooorooooooooo
(X)00(X)00(X)10(X1dg(XJOOtKJOOlX)00(X)00(X)00
000100000000001d00000000001000m0000
(X)00(X)00(H.00(X)dg(X)00(XIOO(X)00(X)00(X)00
oooroooooooorooooaoooooooorooooooooo
(X)00(X)00IHJOO(X)dg(X)00(X)d0(X)OO(X)00(X)00
oooroooooorooooooooaoooooorooooooooo
(X)00(X)01(X)00(X)dg(X)OO(X)0d(X)00(X)00(X)00
0001MOO1000000000000d00001000000000
(X)00(X)10(X)OO(X)dg(X)00(X)00<K)00(X)00(X)00
00010010000000000000000d001000000000
00(X)01(X)OO(])(K)dg(X)00(X)00(X100(X)00(X)00
0001 IOOOWOOOOOOOOOOOOWOdIOOOOOOOOO
00(X)10(X)00(])(X)dg(X)00(X)00(X)d0(X)00(X)00
00‘11(X)00(I)OO(X)00(X)00(X)00(X)1d(X)00(X)00
(X)01(X)00(X)00(X)dg(X)00(X)00(X)0d(X)00(X)00
10010000m000000000000m00100d000000
(X)10(X)00(X)00(X)gd(X)OO(X)00(X)001fl)00(X)00
00010d00m00000000000010100000000000
(X)00(X)00(XJOOth;gle)00(X)00(X)00(X)00(X)00
0001000d0000000000001000100000000000
oooooooooooordgoaooooooooooooooooooo
oooroooooaoooooooorooooorooooooooooo
(X)00(X)00(X)01(klg0(k100(X)00(X)00(X)00(X)00
oooroooooooaoooorooooooorooooooooooo
(X)00(X)00(X)10(klgOlX)d0(X)00(X)00(X)00(X)00
OOOIOOOOWOOOleOOOOOOOOIOOOOOOOOOOO
(X)00(X)00(H100(k1g0(X)0d(X)00(X)00(X)00(X)00
oooroooooooowoaoooooooorooooooooooo
(X)00(X)001K)00(klg0(X)00tK)00(X)OO(X)00(X)00
oooroooooorooooooaoooooorooooooooooo
(X)00(X)01(1100(k1g0(X)00(k100(X)00(X)00(X)00
oooroooorooooooooooaoooorooooooooooo
(X)00(X)10(X)00(klg0(X)00(X)d0(X)00(X)00(X)00
000100100000000000000d00100000000000
00(X)01(X)OO(X)0d1fl)00(X)00(Xl00(X)00(X)00(X)
0001 1000(D0000000000000d10m00000000
(X)001H)00(X)00(Xig0(X)00(X)00tK)OO(X)00(X)00
(X)ll(X)00(I)00(XIOOlX)OO(X)00IkiOOlX)00(X)00
(X)01(X)00(X)00(klgOlX)00(X)00(klOO(X)00(X)00
rooroooooooooooooooooooorowoooooooo

a4b17
a15b7
a15b7
a14b8
al4b8
a13b9
al3b9

a12b10
a12b10
allbll
allbll
a10b12
a10b12

a9b13
a9b13
a8b14
a8b14
a7b15
a7b15
a6b16
a6bl6
a5b17
a5bl7
a15b8
ale8
a14b9
a14b9

a13b10
a13b10
a12b11
a12b11
a11b12
a11b12
alOb13
a10b13

a9b14
a9b14
a8b15
a8b15
a7b16
a7b16
a6b17
a6b17
a15b9
a15b9

87

001H)00(X)00(X)0gtfl)00l])(K)00(X)g0(X)00(X)00
oomoaooooooooooooooro IOOOWOOOOOOOO
00(X)00(X)00(klgg<K)00(X)00(X)00(X)00(X)00(X)
oooroooaoooooooooorooorooooooooooooo
(X)00(X)00(X)01th;0d(X)00(X)00(X)00(X)00(X)00
000100000d00000010000010000000000000
00(X)00(X)001H)dg(X)d0(X)00(X)00(X)00(X)00(X)
oooroooooooaoorooooooorooooooooooooo
00(X)00(X)01(deg(X)0d(X)00(X)00(X)00(I)00(X)
oooroooooooordoooooooorooooooooooooo
00(X)00(X)10(X3dg(X)DOCK)00(X)00(X)00(X)00(X)
oooroooooorooooaoooooorooooooooooooo
(X)00(X)01(XJOOth;00(X)0d(X)00(X)00(X)00(X)00
oooroooorooooooooaoooorooooooooooooo
00(X1001H)OO(X)dg(X)00(X)d0(X)00(X)00(X)00(X)
oooroorooooooooooooaoorooooooooooooo
00(X)01(X)OO(X)dg(X)00(X)0d(X)00(X)00(X)00(X)
0001 1000m00000000000d1000m00000000
00(X)10(X)00(X)dg(X)00(X)00tX)00(X)00(X)00(X)
(X)11(X)00(X)00(X)00(X)00(X)1d(X)00(X)00(X)00
(X)01(X)00(X)00<h;00(X)00(X)0d(X)00(X)00(X)00
10010000m000000000000100dm00000000
00100000m00gd0000000000g0m00000000
00010d00m0000000010 rooooooooooooooo
00(X)00(X)00th;gle)00(X)00(X)OO(X)00(X)OO(X)
oooroooaoooooooorooorooooooooooooooo
00(X)00(X)00ihlgOtK)00(X)00(X)00(X)00(X)00(X)
oomoooooaoooorooooorooooooooooooooo
00(X)OO(X)01(k1g0lklOOlX)00(X)00(X)00(X)00(X)
00010000li0000000100000®00000000
00(X)00(X)lOlklgOlX)dO(X)00(X)00(X)00(X)00(X)
oooroooooorooaoooooorooooooooooooooo
00(X)00(H100(klg0(X)0d(X)00(X)00(X)00(X)00(X)
000100001000000d00001000000000000000
(XJOOCX)10(X)0d1§)00(X)d0(X)00(X)00(X)00(X)00
oooroorooooooooooaoorooooooooooooooo
00(X)01(X)00(klg0(X)00(klOOlX)00(X)OO(X)00(X)
0001 lOOONOOOOOOOOOleCDOOWOOOOOOOO
00(X)lOlX)00lklg0lX)00(X)d0(X)00(X)00(X)00(X)
00‘[100(X)00(X)00(X)00(X)lle)00(X)00(X)00(X)
(X)01(X)00(X)0dtfl)00(X)00(k100(X)00(X)00(X)00
roorooooooooooooooooromoooooooooooo
(Kl10(X)00(X)0gIfl)(K)00(XJ(X)g0(X)(X)00(X)(K)00
oooroaooooooooooro IOOOOOOOWOOOOOOOO
(X)00(X)00(klggtK)00(X)00(X)00(X)OO(X)00(X)00

al4b10 oomoooaoooooorooorooooooooooooooooo
mummmmmmuwmmmmmmmmmmm

al3bll
a13b11
a12b12
a12b12
a11b13
allbl3
a10b14
a10b14
a9b15

a9b15

a8b16

a8b16

a7b17

a7b17

a15b10
a15b10
al4b11
al4b11
a13b12
al3b12
a12b13
a12b13
allb14
a11b14
a10b15
a10b15
a9b16

a9b16

a8b17

18b17

alell
alell
a14b12
a14b12
al3bl3
al3b13
al2b14
a12bl4
allblS
a11b15
a10b16
a10bl6
a9bl7

88

000100000d00100000100000000000000000
(X)00(X)001H)dg(X)d0(X)00(X)00(X)00(X)00(X)00
oooroooooordoooooorooooooooooooooooo
(X)00(X)01(X)dg(X)0d(X)00(X)00(X)OO(X)00(X100
oooroooorooooaoooorooooooooooooooooo
(X)00(X)10(X)dg(X)00tK)OO(X)OO(X)00(X)00(X)00
oooroorooooooooaoorooooooooooooooooo
(X)00(H.00(XJdg(XJOO(XIOO(X)00(X)OO(X)00(X)00
0001 roooooooooooouooooooooooooooooo
(XJOO1H)00(X)dg(X)00(X)d0(X)00(X)00(X)OO(X)00
(X)11(X)00(X)00(X)00(X)lle)00(X)00(X)OO(X)00
(X)01(X)00(X)dg(X)00(X)0d(X)00(X)00(X)00(X)00
roorooooooooooooooroOdoooooooooooooo
00IN)00(X)001y100(X)00(X)g0(X)00(X)00(X)00(X)
00010d00m000010 rooooooooooooooooooo
00(X)00(X)dgtulOOlX)00(X)00(X)00(1)00(X)00(X)
oooroooaoooomoorooooooooooooooooooo
000000001ng$000000000000(1)00000000
oooroooooarooooowoooooooooooooooooo
(X)00(X)01(klgO(klOOlX)00(X)00(X)00(X)00(X)00
oooroooorooaoooorooooooooooooooooooo
(X)00(X)10(k1g0ll)d0(X)00(X)00(X)00(X)00(X)00
0001001000000d001000000000m00000000
(X)00(H.00(klg0lX)0d(X)00(X)00(X)00(X)00(X)00
000110000000000d10000000000000000000
(X)001H3001k1g0(X)00tK)00(X)00(X)00(X)00(X)00
(X)11lX)00lX)00(X)00ik100(X)00(X)00(X)00(X)00
(X)Ol(X)00(klg0(X)00(klOOlX)OO(X)00(X)00(X)00
roorooooooooooooroOdoooooooooooooooo
(X)10(X)00(h;d0lX)00(X)g0(X)00(X)00(X)00(X)00
00010d00m0010 rooooooooooooooooooooo
00(X)00(k1ggtK)00(X)00(X)00(X)00(X)OO(X)00(X)
oooroooaoorooorooooooooooooooooooooo
(X)00(X)01tug0d(X)00(X)00(X)00(X)00(X)00(X)00
oooroooordoooorooooooooooooooooooooo
00(XJOOiHJdg(X)d0(X)00(X)00(X)00(X)00(X)00(X)
oooroorooooaoorooooooooooooooooooooo
00(X101(deg(X)0d(X)00(X)00(X)00(I)OO(X)00(X)
0001 1000CDOOOd100000000000m00000000
00(X)lOlX)dg(XJOO(K)OO(X)00(X)00(X)00(X)00(X)
(X111(X)00(X)00(X)1d(X)00(X)00(X)00(X)00(X)00
(X)01(X)00th;00(X)0d(X)00(X)00(X)00(X)00(X)00
rooroooooooooomoaoooooooooooooooooo

a9b17 OOIOOOOOngOOOOOgOOOOOOOOOOOOOOOOOOO

a15b12
a15b12
a14b13

00010d00m10 rooooooooooooooooooooooo
00(X)00tk;gle)00(X)00(X)00(X)00(XI00(X)00(X)
oooroooarooorooooooooooooooooooooooo

a14b13
a13b14
a13b14
a12b15
312b15
allbl

a11b16
a10b17
a10b17
a15b13
a15b13
a14b14
al4bl4
al3b15
al3b15
a12b16
312b16
a11b17
allbl7
alel4
a15b14
a14b15
a14b15
a13bl6
al3b16
a12bl7
312b17
a15b15
a15b15
al4bl6
a14b16
a13bl7
al3b17
a15b16
a15b16
a14b17
a14b17
a15b17
a15b17
a16b17
al6bl7
al6b16
al6b16
a16b15
a16b15
a16bl4
a16b14

89

mwmmmmmmmmmmmmwmmm
mmmmmmmmmmwmmmmmmw
mmmmmwmmmmmmmmmmmm
mmmmmmwmmmmmmmmmmm
mmmmwmmmmmmmmmmmmm
wummmmmmmmmmmwmmmm
mmmwwmwmmmmmmmwmmm
wmmmmmwmmmmmmmmmmm
wmmwwmmwwmmmwmmmmm
mmmmmwwmmmwmmmmmmm
mmwgwmmmmmmmmmwmmm
mmmmmwmmmmmmmmmmmm
mmmqmmwmmmmmmmmmmw
mmmmmmmmmmmmmmmmmm
mmwummmmmmmmmmmmmm
mummmwmmmmmmmmmmmm
mmmumwmmmmmmmmmmmm
mmmmmwwmwmmmmmmmmm
mwmmmmwmmmmmmmmmmw
mmwwwmmmmwmmmmmmmm
wwawmwmmmmmmmmmmmm
mmwwwmmwmmmmmmmmmm
mmmwmmmmmmmmmmmmmm
mummmmmmmmmmmmmmmm
mmwwwmmmmmwmmmmmmm
wmmmwwwmmwmmmmmmmm
mwmwmwmmmmmmmmmmmm
mmmmmmmmmmmmmmmmmm
mmuwmmmmmmmmmwmmmm
mummmmmmmmmmmmmmmm
mmuwmmmmmmmmmmmmmm
wmmwmmmmmmmmmmmmmm
mmmmwmmmmmmmmmmwmm
muwmmwmmmmmwmmmmmm
muwmmmmwmmmmmmmmwm
mmwmmmmmmmmmwmmwmm
mmwwmmmmmmmmmmmmmm
muwmmwmmmwmmmwmmmm
wgwmmmmmwmmmmmmwmm
nwmmmmmwmmmmmmmmmw
mwwmmmmmmmmmmmmmmm
mmmmmmmwmmmmmmmmmm
mmmmmmmmmmmmmmmmmm
mwwmmmwmmmmmmmmmmm
mmwmmmmmmmmmmmmmmm
mmmmmmmmmmmmmmmmmm
mwmmmmmmmmmmwmmmmm

al6b13
a16b13
a16b12
a16b12
al6b11
a16b11
a16b10
al6b10

a16b9
a16b9
a16b8
a16b8
al6b7
a16b7
a16b6
a16b6
al6b5
a16b5
a16b4
a16b4
al6b3
al6b3
al6b2
al6b2
a16bl
al6b1
a16b0
a16b0

90-

(H.0le)00ifl)00(X)00(X)00(X)00(X)00(X)00(X)00
(X)00(H.d0(X)00(X)00(X)00(X)00(X)00(X)00(X)00
01(k100(])(X)10(XJCX)00(X)(K)00(X)(X)00(X)(X)00
00(X)00'hth)00(X)(K)00(X)OO(X)(X)00(X)(X)00(I)
(H.0d(X)00(X)OOIK)00(X)00(X)00(X)00(X)00(X)00
lX)OO(X)01(I)00(X)00(X)00(X)00(X)00(X)00(X)00
(H.0d(X)00(X)00(X)10(X)00(X)00(X)00(X)00(X)00
00(X)00(X)1d(X)00(X)00(X)00(X)00(X)00(X)00(X)
01(XIOO(X)00(X)00(X)10(X)00(X)00(X)00(X)00(X)
00(X)00(X)01(K)OO(X)00(X)00(X)00(X)00(X)00(X)
(M.0d(X)00(X)00(X)00(X)10(X)00(X)00(X)00(X)00
(X)00(X)00(X)ld(X)00(X)00(X)00(X)00(X)OOCX)00
01(klOOlX)00(X)OO(X)00(X)10(X)00(X)00(X)00(X)
00(X)00(X)00(M.d0(X)00(X)00(X)00(X)00(X)00(X)
(H.0d(X)00(X)00(X)00(X)00(X)10(X)00(X)00(X)00
00(X)00(X)00(X)1d(X)00(X)00(X)00(X)OO(X)00(X)
01(k100(X)00(X)00(X)00(X)00(X)10(X)00(X)00(X)
00(X)00(X)00(X)01(K)00(X)00(X)00(X)00(X)00(X)
(M.0d(X)00(X)00(X)00(X)OO(X)00(X)10(X)00(X)00
(X)00(X)00(X)00(X)1d(X)00(X)00(X)00(X)00(X)00
01(k100(X)00(X)00(X)00(X)00(X)00(X)10(X)00(X)
(X)00(X)OO(X)00(X)01<fl)00(X)00(X)00(X)00(X)00
(H.0d(X)00(X)00(X)00(X)00(X)00(X)00(X)10(X)00
00(X)00(X)00(X)00(X)lle)00(X)00(X)00(X)00(X)
01(k100(X)00(X)OO(X)00(X)00(X)00(X)00(X)10(X)
00(X)00(X)00(X)00(X)01<K)00(X)00(X)00(X)00(X)
01(klOOlX)00(X)00(X)00(X)00(X)00(X)00(X)00'H)
(X)00(X)00(X)00(X)00(X)lle)00(X)00(X)00(X)00

amnmummmmmmmmmmmmmwmm
unnuwmmmmmmmmmmmmmmmm

APPENDIX C

APPENDIX C

SIMULATION PROGRAM FOR TESTING OF THE DKS CHIP

#include <stdio.h>
#include <ctype.h>

static int shift_register [31];

static int *EnLl .. shift_register ;
static int *EXGt - shift_register + 1;
static int *MO - shift_register + 2;
static int *AO - shift_register + 3;
static int *Av = shift_register + 4;
static int *M3I - shift_register + 5;
static int ‘M3O - shift_register + 6;
static int ‘AT - shift_register + 7;
static int ‘Ev - shift_register + 8;
static int ‘V - shift_register + 9;
static int ‘sc - shift_register + 10;
static int ‘Et - shift_register + 11;
static int *EM - shift_register + 12;
static int ‘Madr - shift_register + 13;
static int ‘T - shift_register + 14;
static int *TRadr= shift_register + 15;
static int *L - shift_register + 16;
static int ‘LRadr- shift_register + 17;
static int ‘Ml - shift_register + 18;
static int ‘M2 - shift_register + 19;
static int ‘Alzd - shift_register + 20;
static int *Albs - shift_register + 21;
static int ‘A2 .. shift_register + 22;
static int ‘Gate - shift_register + 23;
static int ‘CTRL - shift_register + 24;
static int *SGN - shift_register + 25;
static int *Lc - shift_register + 26;
static int ‘Tc - shift_register + 27;
static int *Ls = shift_register + 28;
static int ‘Ts - shift_register + 29;
static int *Etla = shift_register + 30;

static int tsrl_A, tsrl_B, one_delay[2];
91

92

static int Adder, MPYI, MPYZ, LX__latch, LA_latch[3], constants [5];
static int A1_latch, A2_latch, M1_latch, M2_latch, M3_latch;

Static int c_register, s_register, register__file[9], angle_register[6];
static int counter, TXPORT‘, DXPORT, Tx, Dx;

static int sile.din;
static int bus_A, bus_B, Sign_Al, Sign_A2;
static int test_stepS. test_vector;

FILE ‘0);

/* Program to simulate the testing of the DKS chip *7

main()

{
set__undef(); /"' Set all signals to undefined value */
init_rom 0; /* Initialize ROM contents */

fp - fopen ( 'tvfile" , "r" ); /" Open the test-vector file *I
/* Test all modules in parallel where possible */

test_bus ();
test_con_logic ();
test_angle_and_cons ();
test_M1__M2 ();
test_A1_A2 ();
test_LX_creg ();
test_LA_sreg 0;
test_M3__rfile 0;
test_Dx_Tx ();
test_MPYl ();
test_MPY2 ();
test_Adder 0;

}

test_bus ()

{

int i;

printf ("\nTest Bus " );
test_steps - getvec (); /"‘ Read number of test patterns */

/* Repeat the following procedure for all test patterns */

93

for ( i-l ; i<-test_steps ; i++ ) {
reset_signals (); /"' Set TSRLs and SRLs */
tsrl_A - getvec ();
tsrl_B - getvec 0;
‘EnLl - *EXGt - 1;SRLs

phase_one (); /"' Apply phase one of system clock */

tsrl_A - tsrl_B - 0;
*EnLl - 0;
phase_one ();

dump_scan_path O; /‘ Scan-out results "'I
}

return (0);

}

test_con_logic ()
{
int i;
printf ("\nTest control logic ”):

reset 0; /* Reset the control logic counter */
/" Repeat the following procedure 73 times to test each state *I

for (i=0 ; i<-7 ; i++) {
phase_one 0; /* Apply one system clock */
phase_two 0;
dump_srls 0; I“ Scan out SRL contents */
printf (”\n");

}

return (0);

}

test_angle_and_cons 0
{
int i;
printf ("\nTest angle registers and constants");

for ( i=0 ; i<-5 ; i++ ) { /* First set all the angle-registers */
reset_signals ();
sile - 1;
din - getvec (); /“' from the test vector file. */
Phase_0ne O;

phase_two 0;

}

for( i-O;i<-5 ;i++ ){
reset_signals 0; /* Now transfer each angle-register */
*V - *Madr - i; /"‘ and constant one at a time to */

*Av - ‘EM = ‘EXGt = 1; /"‘ TSRLs of bus A and B respectively */

Phil-90.006 0;
Phase_two 0;

dump_scan_path 0; /* and scan-out the results. */
1;

return (0);

}

test_M1_M2 ()
{

int i;

printf ("\nTest M1 and M2 " );
test_steps - getvec 0;

for ( i-l ; i<=test_steps ; i++ ) {
reset_signals 0;
‘MI - 2;
‘M2 - *EnLl - ‘EXGt = 1;
tsrl_A - getvec 0;
tsrl_B - getvec ();

phase_one 0:
Phasc_two O;
reset_signals 0;
‘MO - ‘EXGt - 1;
Phase.0ne 0;
Phase_tw0 O;
dump_scan_path 0;
}

return (0);

}

test_Al_A2 ()
{

int i;

printf ("\nTest Al and A2 " );
test_steps - getvec 0:

 

95

for( i=1 ; i<=test_steps ; i++) {
reset_signals O;
‘Albs - *A2 - 2;
*EnLl - ‘EXGt - 1;
tsrl_A - getvec ();
tsrl_B - getvec O;
phase_one 0;
phase_two O;
reset_signals 0;
‘A0 I *EXGI - I;
phase_one 0;
phase_two 0;
dump_scan_path O;

}

return (0);

}

tes t_LX_creg ()

{
printf ("\nTest LX and C-register " );
reset_signals ();
sile - 1;
din - getvec ();
tsrl_B - getvec 0;
911888308 0;
phase_two O;
reset_signals 0;
‘EV - l;
‘V - 5;
Phasaone 0:
phase_two ();
reset_signals 0;
*AT - *EnLl - *EXGt - *Ml - l;
Phil-tame O;
Phase_two 0;
reset_signals ();
*EXGt - ‘MO - *T‘c = 1;
phase_one O:
PhaSC_tw0 O;

dump_scan_path 0;

return (0);

}

test_LA_sreg ()

96

printf ("\nTest LA and S-register " );
reset_signals 0;

‘Etla - ‘EXGt - ‘EnLl = *AT‘ = 1;
tsrl_A - getvec ();

tsrl_B - getvec ();

Phase_0ne 0;

phase_two 0;

phase_one ();

phase_two 0:

reset_signals ();

*Alzd - 1;

phase_one O;

phase_two O:

reset_signals ();

‘EXGt - ‘AO - ‘Ts 1;
phase_one ();

phase_two O;

dump_scan_path 0;

return (0);

}

test_M3_rfile ()
{

int i;
printf ("\nTest M3 and Register file " );

for(i-0;i<-8;i++){
reset_signals 0;
*M31 - *AT - *EXGt - *EnLl = 1;
tsrl_A - getvec ();
tsrl_B - getvec ();
*LRadr - i;
13118863030:
phase.two 0;
reset_signals 0;
*M30 - ‘T‘ =- ‘EXGt = l;
*TRadr a i;
phase_one ();
phase_two ();

dump_scan_path ();

97

return (0);

}

tes t_Dx_Tx ()

{
printf ("\nTest Dx and Tx " );

reset_signals ();
sile = 1;

din - getvec O;
*V - 5;
Phase.one O:
phase_two ();
reset_signals ();
*Ev - 1;

‘V - 5;
Phase_one 0;
phase_two ();
reset_signals 0;
*Et - *EXGt - 1;
phase_one ();
phase_two ();

dump_scan_path 0;

return (0);

}

test_MPYl ()
{
int i;
printf ("\nTest MPYl " );

test_steps - getvec 0;
for ( i-l ; i<-test_steps ; i++ ) {
reset_signals 0;
*M1 - 2;
‘M2 - ‘EXGt - 'EnLl -= 1;
tsrl_A - getvec ();
tsrl_B - getvec ();
Phaseyne 0:
Phase_tw0 O;
reset_signals ();
phase_one 0;
phase_two ();
reset_signals 0;
*M30 - ‘EXGt - l;

. "El-\III' _

 

98

phase_one O;
phase_two ();

dump_B_only 0;
}

return (0);

}

test_MPYZ ()
{
int i;
printf (”\nTest MPYZ " );

test_steps - getvec 0;

for ( i-l ; i<-test_steps ; i++ ) {
reset_signals 0;
*M31 - *EXGt - *EnLl = 1;
tsrl_A = getvec ();
phase_one ();
phase_two 0;
reset_signals 0;
*A2 - 1;
phase_one O;
phase_mo O;
reset_signals 0;
*A0 :- ‘EXGt = 1;
phase_one 0;
phase_two ();

dump_B_0n1Y ()3
}

return (0);

}

test_Adder ()
{
int i;
printf ("\nTest Adder " );

test_steps == getvec 0:
for ( i-l ; i<-test_steps ; i++ ) {
reset_signals ();
*Albs - ‘A2 a 2;
*EXGt =- ‘EnLl = 1;
tsrl_A = getvec O:

tsrl_B - getvec ();
Phase.0ne O;
phase_two O;
reset_signals 0;
‘Gate - ‘EXGt - 1;
Phase_0ne 0;

Phasatwo O;

dump_B_only 0;
}

return (0);

}

/* This function simulates all functions performed in the phase-one
of the system clock of the DKS chip ‘/

phase_one ()
{
int i;
int error_code = 0;

counter ++ ;

if(‘EnLl +‘MO+"AO+*AV+*T+*Et>l)
error_code-1;

if(*EnLl +‘MO+"‘AO+*TC+*Ts+*EM+*M30+ *Gate+ *Et> l)
error_code - 2;

if ( ‘EnLlul && ‘EXGtu-l ) {
bus_A - tsrl_A;
bus_B - tsrl_B;

}

if ( ‘MOul ) {
bus_A - Ml_latch;
bus_B - M2_latch;
}

if ( ‘AO-ml ) {
bus_A - A1_latch;
bus_B - A2_latch;
}

if ( *Avnl ) {
bus_A a angle_register [‘V];

100

}

if ( *Tc-al ) {
bus_B - c_register;

}

if ( ‘Ts-al ) {
bus_B - s_register;
}

if( ‘EMul ) {
bus_B - constants [*Madr];

}

if ( *TB-l ) {
bus_A - register_file [‘T'Radr];
}

if ( *M30=-1 ) {
bus_B - M3_latch;
}

if ( *Gatenl ) {
bus_B - Adder;
}

if ( ‘Etnl ) {
bus_A - TXPORT;
bus_B - DXPORT;
}

if ( sile--l ) {
for (i=0 ; i<-4 : i++)
angle_register [i] - angle_register [i+1]:

angle_register [5] .. din;
}

if ( *Ev--l ) {

TXPORT - Tx;

DXPORT - Dx;

LX_latch - angle_register [*V];
}

if(*M1 a- 1 ){
Ml_latch - LX_latch;
}

101

if ( ‘Ml -- 2 ) {
Ml_latch - bus_A;
}

if ( *M2==1 ) {
M2_latch - bus_B;
}

one_delay [l] - one_delay [0];
LA_latch [2] - LA_latch [l];
LA_latch [l] =- LA_latch [0];

if( *Alzd && *Albs)
error_code - 3;

if( *Alzd u 1 ) {
A1_latch .. LA_latch[2];
}

if( *Alzd == 2) {
A1_latch =- 0;
}

if( *Ale --1){
A1_latch - Adder;
}

if("'A1bs--2){
A1_latch - bus_A;
}

if ( *A2 -- 1 ) {
A2_latch - MPYZ;
}

if ( *AZ -- 2 ) {
A2_latch . bus_B;
}

if ( *M3l ) {
M3_latch = bus_A;
}
else {
M3-latch = MPYl;
}

}

102-

if ( I'Etlaas-l ) {
LA_latcth] - bus_A;
}

if((‘AT&&‘Lc)||(*AT&&"Is))
error_code-4;

if ( ‘ATnl ) {
c_register - bus_B;
s_register - bus_B;
register_file [*Uladr] - bus_B;
} .

if ( ‘L--l ) {
register_file [‘LRadr] - Adder;
}

if( ‘15“1 ) {
c_register - Adder;
}

if ( ‘LS==1 ) {
s_register - Adder;

}

if( ( l‘EnLl-nl ) && *EXGt==1 ) {
tsrl_A = bus_A;
tsrl_B - bus_B;

}

if ( error_code != 0 )
printf ( "Error code - %d \n“, error_code );

return (0);

/"' This function simulates all functions performed in the phase-two

of the system clock of the DKS chip */

phase_two ()

{

int i;

bus_A = -l;
bus_B = -l;

MPYl = Ml_latch * M2_latch / 2;

103

MPYZ .. 2 * M3_latch;

if ( ! *CI'RL) {
Sign_Al .. one_delaym;
}

else {
Sign_Al - 0;
Sign_A2 - ‘SGN;
}

if ( Sign_Al==1 )

A1_latch - -A1_latch;
if ( Sign_A2=-1 )

A2_latch - -A2_latch;
Adder - A1_latch + A2_latch;

Tx = Dx = angle_register [*V];

for ( i=0 ; i<-30 ; i++ )
shift_register [i] - counter " 10;

return (0);

}

/"' Scan out (print) the contents of both sets of TSRLs */
dump_scan_path ()
{

printf (“\ntsrl_A s %d", tsrl_A );

printf (“\ntsrl_B - %d\n", tsrl_B );

return (0);
}

/‘ Scan out (print) the contents of TSRLs of bus B only */
dump_B_only ()
{

printf (”\ntsrl_B - %d\n", tsrl_B );

return (0);

}
/* Print contents of all the SRLs in the scan path */

dump_srls 0

104

int i;

for(i-0;i<-30;i++)
printf (( i9610 - 0) ? ”\n%d " : "%d ”, shift_register[i] );
return (0);
}

/"' Reset the control logic counter and all control signals */
reset ()
{

counter - 0;

reset_signals 0;

retum(0);

}

/* Reset all control signals */
reset_signals ()
{
int i;
for(i-0;i<-30;i++){
shift_register [i] - 0;
}
‘EnLl - 0:
‘EXGt - 0;
sile - 0;
din -0;
retum(0);

}
/* Initialize ROM contents at beginning of the program */

init_rom ()
{
int i;
for(i=0;i<-4;i++){
constants [i] - i "' 25;

}

retum(0);

}
/"' Set all latches and registers to undefined values. */
set_undef ()

{

int i;

105

counter -= Adder - MPYl - MPY2 - -1;

LX_latch .. LA_latch [0] - LA_latch [1] -= LA_latch [2] :- -1;
A1_latch - A2_latch - -1;

Ml_latch a: M2_latch :- M3_latch = -1;

c_register - s_register .. -1;

sile - din - -1;

tsrl_A - tsrl_B - -1;

for(i-O;i<-8;i++)
register_file [i] - -1;

for(i-0;i<-4;i++)
angle_register [i] a -1;

for ( i=0 ; i<-3O ; i++)
shift_register [i] - -1;

retum(0);

}

getvec ()

{

int temp;

fscanf ( fp, "%d\n", &temp );
return ( temp );

}

BIBLIOGRAPHY

10.

ll.
12.

13.

14.

15.

16.

BIBLIOGRAPHY

P. K. Lala, "Fault Tolerant and Fault Testable Hardware Design", Prentice Hall, 1985.

R. G. Bennetts. "Introduction to Digital Board Testing", Crane, Russack, and Co., Inc.,
1982.

r.w. Williams, and K. P. Parker, "Design for Testability - A Survey", Proc. of the
IEEE, Vol. 71, no. 1, Jan 1983, pp. 98-112.

E. R. Huatek, "Integrated Circuit Quality and Reliability", Mercer Dekker, 1987.

S. S. Leung, and M. A. Shanblatt, "A VLSI Chip Architecture for the Computation of
the Direct Kinematics Solution", Dept. of Electrical Engineering, Michigan State
University.

R. G. Bennetts, "Design of Testable Logic Circuits", Addison-Wesley Publishing Co.,
1984.

J. E. Stephenson, and I. Grason, "A Testability Measure for Register Transfer Level
Digital Circuits", Proc. 6th IEEE Fault Tolerant Computing Symp., 1976, pp. 101-117.

L. H. Goldstein, "Controllability/Observability Analysis for Digital Circuits", IEEE
Tran. Circuits and Systems, CAS-26, No. 9, 1979, pp. 1685-1693.

R. G. Bennetts, C. M. Maunder, and G. D. Robinson, "CAMELOT: a Computer-Aided
Measure for Logic Testability", IEE Proc., Vol. 128, Part E, no. 5, pp. 177-189.

I. M. Ratiu, et. a1. , "VICTOR: A Fast VLSI Testability Analysis Program" Proc. IEEE
Test Conf., 1982, pp. 397-401.

J. P. Roth, "Computer Logic, Testing, and Verification", Pitman, 1980.

E. J. McCluskey, "Logic Design Principles: with emphasis on Testable Semicustom
Circuits", Prentice Hall, 1986.

S. Funatsu, N. Wakatsui, and T. Arima, "Test Generation SyStems in Japan", Proc.
12111 Design Automation Systems, June 1975, pp. 114-122.

T. W. Williams and E. B. Eichelberger, ”A Logic Design Structure for Testability",
Proc. 14th Design Automation Conference, 1977, pp. 463-468.

G. H. Stange, "A Test Methodology for Large Logic Networks", Proc. IEEE 15th
Design Automation Conference, pp. 103-109.

T. P. Singh, S. S. Leung, and M. A. Shanblatt, "Bus Scan Testing for lntemal Bus
Architecture Systems", Sixth IEEE VLSI Test Conf., Mar. 1988.

106

17.

18.

19.

20.

21.

22.

23.

24.

25.

26.

27.

28.

29.

30.

31.

32.

107

M. G. Mercer, and M. A. Breuer, "Scan Path with Look Ahead Shifting (SPLASH)",
1986 Intl. Test Conference. pp. 696-704.

M. R. Mercer, and V. D. Agrawal, "A Novel Clocking Technique for VLSI Circuit
Testability", IEEE J. of Solid State Circuits, Vol. SC-19, No. 2, Apr. 1984, pp. 207-
211.

H. Audo, "Testing VLSI with Random Access Scan", Digest IEEE Compcon, 1980,
80CH1491-OC, pp. 50-52.

James H. Stewart, "Future Testing of Large LSI Cards", Dig. Papers 1977 Semicon-
ductor Test Symp., Oct. 1977, pp. 6-17.

B. Konemann, J. Mucha, and G. Zwiekoff, "Built—In Logic Block Observation Tech-
nique", Pmc. IEEE Test Conf., pp. 37-41.

J. Savir, "Syndrome Testable Design of Combinational Circuits", IEEE Trans. Comput-
ing, Vol. C-29, June 1980, pp. 442-451.

A. K. Susskind, "Testing by Verifying Walsh Coefficients" Proc. 11th Ann. Symp. an
Fault Tolerant Computing, June 1981, pp. 206-208.

E. J. McCluskey and S. Bozorgui, "Design for Autonomous Test", IEEE Trans. Com-
puting, Vol. C-30, Nov. 1981, pp. 866-875.

H. J. Nodig, "Signature Analysis - Concepts, Examples, and Guidelines", Hewlett
Packard J., May 1977, pp. 15-21.

V. Seshadri, "A Real_Time VLSI Architecture for Direct Kinematics", Robotics and
Automation Conf., 1987.

C. F. Ruoff, "Fast Trig Functions for Robot Control", Robotics Age in the beginning,
ed. by C. T. Helmets, Hayden Book, 1983.

S. K. Jain, and V. D. Agrawal, "Test Generation for MOS Circuits Using D-
algorithm", Proc. 20th Design Automation Conference, June 1983, pp. 65-70.

J. Savir, G. Ditlow, and P. H. Bardell, "Random Pattern Testability", Proc. 13th Intl.
Symp. on Fault Tolerant Computing, June 1983, pp.80-89.

P. Agrawal, and V. D. Agrawal, "Probalistic Analysis of Random Test Generation
Method for Irredundant Combinational Networks", IEEE Trans. Computers, Vol. 024,
No. 7, July 1975. PP.691-695.

E. B. Eichelberger, and E. Lindbloom, "Pattern Coverage Enhancement and Diagnosis
for LSSD Logic Self-Test, IBM J. of Research and Development, Vol. 27, No. 3, May
1983, pp. 265-272.

J. P. Roth, "Diagnosis of Automata Failures - A Calculas and a Method", IBM J. of
Research and Development, Vol. 10, July 1966, pp.278-291.

i,li lititillt’lll. ii

33.

34.

35.

36.

37.

108

P. Goel, and B. C. Rosales, "An Automatic Test Generation System for VLSI Logic
Structures", Proc. 18th IEEE Design Automation Conference, 1981, pp. 260-268.

V. Agrawal and P. Agrawal, "An Automatic Test Generation System for ILLIAC IV
Logic Boar ", IEEE Trans. Computers, Vol. C-21, No. 9, Sept. 1972, pp. 1015-1017.

Y. H. Levendel, and P. R. Menon, "Test Generation Algorithms for Computers HDLs",
IEEE Trans. Comp., Vol. C-31, No. 7, July 1982, pp. 577-588.

J. P. Mucha, "VLSI Testing - Problems and Solutions", VLSI 85, Elsivier Science
Publishers B. V., 1986. PP. 363-370.

Stephen Y. H. Su, and Tonysheng Lin, "Functional Testing Techniques for Digital
LSI/VLSI Systems", ACM/IEEE 2lst DAC Proc., 1984, pp. 517-528.