I v, H. ”Li! Y
‘ 41$. 1:. ....»17 v 1.. A

 

 

 

 

 

«MO/557‘ 8 II”'“‘"””“IIII‘IIT'I IIIIIIIIII

 

 

LIBRARY
Michigan State
University

 

 

 

This is to certify that the

dissertation entitled

Fault Prediction and Diagnosis
In Large Analog Circuit Networks

presented by

Benlu Jiang

has been accepted towards fulfillment
of the requirements for

Ph.D. ndegreeinjlmmL
Engineering

WEE/00} (0, I? if

MS U is an Affirmative Action/Equal Opportunity Institution

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 1293 00602 4453

””7

042771

PLACE IN RETURN BOX to remove this checkout from your record.
TO AVOID FINES return on or before due due.

 

DATE DUE DATE DUE DATE DUE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSU Is An Affirmdive ActlorVEquel Opportunity Institution

FAULT PREDICTION AND DIAGNOSIS
IN
LARGE ANALOG CIRCUIT NETWORKS

By

Benlu Jiang

A DISSERTATION

Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

DOCTOR OF PHILOSOPHY

Department of Electrical Engineering

1989

L904 00¢)?

ABSTRACT

FAULT PREDICTION AND DIAGNOSIS
IN LARGE ANALOG CIRCUIT NETWORKS

By

Benlu Jiang

Electronic circuits and systems have become so versatile and useful that they are
indispensable in modern society. With the electronic systems continuously growing in
the significance and pcrvasiveness of application, their testing becomes increasingly
important and also more and more complex, difficult, and costly.

Most of the automatic testing and fault diagnosis algorithms proposed in literature
work well only when nonfaulty components assume their nominal values exactly. In a
practical circuit, the values of nonfault components may deviate from their nominal
values within a predefined tolerance, and the faulty components may not be properly
located or even be detected unless the system fails. This becomes the bottleneck of ana-
log fault diagnosis. For a reliable design, we should identify potential faulty components
as soon as possible before the system fails instead of doing fault location after the system
fails.

In this dissertation, the fault prediction problem is initiated and a fault prediction
algorithm is presented. For the case that the parameters of potential faulty components
are assumed to change gradually during each maintenance period, by continuously moni-
torin g the responses of the network, the proposed algorithm can precisely predict whether

any of the network components are about to fail.

In order to apply the proposed algorithms to large circuit networks with reasonably
high speed, a decomposition approach fault prediction algorithm is proposed. The
approach can be used hierarchically to decompose a network into any desired level to
predict and diagnose faulty subnetworks.

Due to technical limitation, it is difficult to provide proportionately more accessible
terminals for testing purpose in large circuit networks. To deal with this problem, an
analog build-in self-test (ABIST) structure is proposed which can provide more test
points while still keeping low pin overhead and acquire test data at various test points
simultaneously. It is the first analog BIST structure ever proposed for analog fault diag-
nosis. In order to properly design diagnosable networks, an efficient algorithm is
developed to select an appropriate minimum set of test points.

In summary, this dissertation focuses on fault prediction and diagnosis. The pro-
posed decomposition approach, ABIST structure and diagnosability design provide a use-

ful means for fault prediction and diagnosis in large analog circuit networks.

To my parents:

Dazong Jiang and Zongxin Huang

iv

ACKNOWLEDGEMENTS

I would like to thank Professor Chin—Long Wey, my thesis advisor, for his valuable
inspiration and guidance throughout my graduate study. I would like to thank members
of my thesis committee, Professors Greg Wierzba, Donald Reinhard, Edwin Kashy, and
Michael Shanblatt, for their continual encouragement and many excellent comments dur-

ing the course of my dissertation research.

I would like to acknowledge all the faculty members and students who gave me
help and assistance during my studying at Michigan State University, and many friends

who showed their support and concern.

I am very grateful to my parents Dazong Jiang and Zongxin Huang, for their years
of concern, encouragement and support; to my husband Youran for his constant
encouragement and direct assistance in the preparing of this manuscript; and to my

daughter Lana for being so understanding.

TABLE OF CONTENTS

List of Tables .............................................................................................................. ix
List of Figures ............................................................................................................. x
Chapter 1 Introduction ............................................................................................ 1
1.1 Difficulty of Analog Fault Diagnosis ..................................................... 2
1.2 Methods and Comparison ...................................................................... 4
1.3 Motivation .............................................................................................. 6
1.4 Thesis Organization ...... ‘ ......................................................................... 7
Chapter 2 Fault Diagnosis ....................................................................................... 9
2.] Diagnosis Equation ................................................................................ 9
2.2 Fault Location ........................................................................................ 12
2.3 Fault Evaluation .......................................... _ ........................................ 1 3
2.4 Equivalent Fault Sets ............................................................................. 15
2.5 Software Implementation ....................................................................... 17
2.6 Examples ................................................................................................ 19
Chapter 3 Fault Prediction ..................................................................................... ' 28
3.1 Error Effect Analysis of Component Tolerance .................................... 29
3.2 Basic Concept of Fault Prediction ......................................................... 31
3.3 Fault Prediction Approach ..................................................................... 34
3.4 Examples ................................................................................................ 36
3.5 Discussion and Summary ....................................................................... 39
Chapter 4 Decomposition Approach Fault Prediction ......................................... 40
4.1 Decomposition Approach ...................................................................... 41
4.2 Fault Prediction Approach ..................................................................... 47
4.3 Extension to Nonlinear Circuit Networks .............................................. 53

Chapter 5 BIST Structure ....................................................................................... 58

5.1 BIST Structure ....................................................................................... 58

5.2 Analog BIST Structure .......................................................................... 62

5.3 Simulation and Hardware Implementation ............................................ 66

5.4 VLSI Implementation ............................................................................ 71

5.4.1 Analog Switchs ............................................................................ 71

5.4.2 Voltage Followers ........................................................................ 72

5.4.2 Physical Layout ............................................................................ 77

Chapter 6 Design for Diagnosability ...................................................................... 79
6.1 Diagnosability Measurement ................................................................. 80

6.2 Test Point Selection ............................................................................... 82
Chapter 7 Conclusions ............................................................................................. 91
7.1 Summary of Major Contributions .......................................................... 91

7.2 Directions for Future Research .............................................................. 93

7.2.1 Automatic Testing and Diagnosis ................................................ 93

7.2.2 Time Domain Analysis ................................................................ 93

7.2.3 Fault Diagnosis for Analog/Digital Hybrid Circuits ................... 93

7.2.4 BIST Implementation .................................................................. 95
Appendices ................................................................................................................. 97
Bibliography .............................................................................................................. 1 12

vii

LIST OF TABLES

Table 2.1 W]; and Ax; of Different Types of Components ......................................... 11
Table 2.2 Substituted Sources of Different Types of Components ........................... 14
Table 2.3 W matrix of Example 2.1 ........................................................................... 21
Table 2.4 Simulation Data of Example 2.1 ................................................................ 22
Table 2.5 Component Evaluation .............................................................................. 23
Table 2.6 Component Values of Example 2.2 ........................................................... 24
Table 2.7 W matrix of Example 2.2 ........................................................................... 25
Table 2.8 Simulation Data of Example 2.2 ................................................................ 26
Table 2.9 Simulation Results of Example 2.2 ........................................................... 27
Table 3.1 Simulation Data 1 of Example 3.1 ............................................................. 37
Table 3.2 Simulation Data 2 of Example 3.1 ............................................................. 37
Table 3.3 Simulation Data of Example 3.2 ................................................................ 38
Table 4.1 First Level Decomposition of Example 4.1 ............................................... 44
Table 4.2 Second Level Decomposition of Example 4.1 .......................................... 45
Table 4.3 First Level Decomposition of Example 4.2 ............................................... 45
Table 4.4 Second Level Decomposition of Example 4.2 .......................................... 46
Table 4.5 First Level Decomposition of Example 4.3 ............................................... 49
Table 4.6 Second Level Decomposition of Example 4.3 .......................................... 49
Table 4.7 Component Values of Example 4.4 ........................................................... 51
Table 4.8 Simulation Result of Example 4.4 ............................................................. 52
Table 4.9 Analysis in One Time Step ........................................................................ 53
Table 4.10 Simulation Result 1 of Example 4.5 ......................................................... 56
Table 4.11 Simulation Result 2 of Example 4.5 ......................................................... 57
Table 6.1 Device Parameters ..................................................................................... 73
Table 6.2 Device Area ............................................................................................... 76
Table 6.3 Simulation Result of an Op-amp Design ................................................... 76
Table 7.1 Identical Groups of Example 7.1 ............................................................... 84
Table 7.2 Test Point Selection and Compaction ........................................................ 84

viii

Figure 2.1
Figure 2.2

Figure 2.3
Figure 2.4
Figure 2.5
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Figure 5.1

Figure 5.2

Figure 5.3

LIST OF FIGURES

Circuit Networks .....................................................................................
Equivalent Faulty Network .....................................................................
A Resistor Network .................................................................................
Equivalent Faulty Network of Figure 2.3 ................................................
An Active Circuit ....................................................................................
Circuit Networks .....................................................................................
Basic Concept of Fault Prediction ...........................................................
Prefault and Postfault Networks ..............................................................
All Active Filter .......................................................................................
A Subnetwork S,- with m,- Extemal Nodes ...............................................
A Linear Network ....................................................................................
Decomposed Subnetworks SI and S 2 .....................................................
Decomposed Subnetworks S 3 and S 4 .....................................................
A Signal Filter Circuit .............................................................................
Decomposed Subnetworks ......................................................................
(a) A Network (b) Decomposed Subnetworks ........................................
BIST Design of Digital Circuit: (a) Scan Design Using SRL;

(b) SRL; and (c) a Shift Register with 3 SRLs .......................................

BIST Structure with Analog Shift Register
(a) Analog Shift Register ASRi; and (b) Schematic Diagram ..................

An Analog BIST Structure (ABIST) .......................................................

Figure 5.4 Switching Operation of the ABIST Structure:

(a) Parallel Loading; (b) & (0) Serial Passing .........................................

ix

10
13
19
23
24
29
32
34
38
41
43
43
44
50
51
55

6O

61
62

64

Figure 5.5 Timing Diagram of ABIST Structure ...................................................... 65

Figure 5.6 Clock Circuit ........................................................................................... 66
Figure 5.7 PSPICE Simulation Results: (a) DC; (b) AC; and (c) Partion of (b)

Figure 5.7 Continuted ............................................................................................... 69
Figure 5.8 Observed Outputs from an Oscilloscope: (a) DC; and (b) AC ................ 70
Figure 5.9 CMOS Analog Switch ............................................................................. 71
Figure 5.10 CMOS Op-amp with N Channel Input ................................................... 72

Figure 5.11 Simulation Results:
(a) Input CMR Simulation; (b) Transient Response;

(c) Magnitude Response; and ((1) Phase Response. ................................. 74
Figure 5.11 Continuted .............................................................................................. 75
Figure 5.12 ABIST Layout (a) one-stage (b) 4 Stage ................................................ 78
Figure 6.1 The Network in Example 6.1 .................................................................. 81
Figure 6.2 A Ten Band Octave Equalizer ................................................................. 88
Figure 6.3 A Decomposition of the Octave Equalizer .............................................. 89
Figure 7.1 A Block Diagram of ATE ....................................................................... 94
Figure 7.2 ABIST Array ........................................................................................... 96

CHAPTER 1

INTRODUCTION

 

Electric circuits and systems have become so versatile and useful that they are
indispensable in modern society. With the electronic systems continually growing in the
significance and pervasiveness of application, their testing becomes increasingly impor-
tant and also more and more complex, difficult, and costly.

Electronics design has become more and more sophisticated since the last quarter
of this century. Graphical algorithms have been replaced by CAD (Computer-Aided
Design), and features of design implementation can be studied by simulation rather than
requiring extensive breadboarding. Electronics maintenance, however, has changed
very little during the same period. Therefore, our ability to design and manufacture
complex electronic circuits is quickly outstripping our ability to maintain them, and the
price reductions which have accompanied the new electronics technology are being
offset by increased maintenance costs. Indeed, many industries are finding that the life
cycle maintenance costs for their electronic equipment now exceeds their original capi-
tol investment.

It is becoming apparent that the electronics maintenance process, like the design
process, must be automated. For more than two decades, the subjects of automatic test-
ing and fault diagnosis of electronic circuits have been of interest to researchers in the
areas of circuits and systems [8, 25, 32, 33, 38]. Recently, with the rapidly increasing

complexity and size of modern electronic systems, these subjects become more and

1

more important and critical.

The main problems in network testing are fault detection, fault location and fault
prediction [3]. Fault detection refers to the discovery of something wrong in a circuit.
Fault location concerns the identification of faults with components, functional modules,
or subsystems, depending upon the requirement. Fault prediction alludes to the continu-
ous monitoring of network responses so that any of the network elements which is about
to fail can be identified. Fault diagnosis includes fault detection and location.

By a fault we mean, in general, any variation in component value, with respect to
its nominal value which can cause the failure of the whole circuit. Two forms of faults
are generally considered: catastrophic fault (hard fault), where the faulty element pro-
duces either a short circuit or an Open circuit, and deviation fault (soft fault), where the
faulty element deviates from its nominal value without reaching its extreme bounds.

The soft faults are usually due to manufacturing tolerances, aging, or parasitic effects.

1.1 DIFFICULTY OF ANALOG FAULT DIAGNOSIS

The research and theory development of digital testing started in the mid 1960’s
when the large-scale computers were readily available. The first commercialized test
program did not become available until a decade later. Several digital automatic test
program generation systems have been developed and widely used by both the military
and industrial communities. From the mid 1970’s, the test technology community began
to face up to the analog test problem. Indeed, even in a predominantly digital world,
analog systems were not disappearing. Analog systems were proving to be among the
most unreliable and least readily tested of all electronic systems [26]. Presently, it is
estimated that even though 80% of all boards are digital, 80% of the problems are ana-
log.

Given our experience with the digital test problem and the analog computer-aided

design problem, one might initially assume that the analog test problem could be

resolved simply by integrating the tools and techniques of these two well-established

fields. Unfortunately, the tremendous strides which have been made in digital test tech-

nology have not been paralleled by equal progress in the analog area. Fault diagnosis

for analog circuits, in fact, has been found to be an extremely difficult problem to solve.

The difficulty arises from a number of characteristics of the analog problem [3, 26] as
listed below:

(1)

(2)

(3)

Tolerance: The actual values of analog components almost always deviate from
the nominal values.

Modeling: An analog system has an infinite number of possible failures which may
range from short circuit to Open circuit. It leads the lack of good fault models for
analog components such as the stuck-at-one and stuck-at-zero fault models which
are widely accepted by the digital testing.

Measurement: An analog system usually has only a few nodes accessible for
measurement and testing. Without breaking connection, it is difficult to measure

currents.

(4) Nonlinear nature: If a parameter value changes by a certain factor, the responses

do not change by the same factor, i.e., the relationship between network responses

and component characteristics is nonlinear, even though the circuit may be linear.

The nonlinear nature of the diagnosis problem can be observed from the following

discussion. Consider a simple linear equation [26]:

Px =b (1.1)

y = Cx (1.2)

where b is the input-vector, y is the output-vector, x is the internal-vector, and P and C
are compatible matrices. Suppose that P is changed to P+AP, with b fixed, x will

change to x-l-Ax accordingly, i.e.,

(P+AP)(x+Ax) = b (1.3)
Hence,

Ax = (P+AP)‘1b—P‘1b (1.4)
and

Ay = amp ;P,b,C) = C(P +AP)‘1b—CP‘1b (1.5)

The problem of solving for Ay from a given AP is a well-known sensitivity prob-
lem. Conversely, solving for AP from a given Ay is called the diagnosis problem.
Because the above diagnosis function 4) may be highly nonlinear even for this simple
linear equation, the inherent difficulty of the diagnosis problem is readily apparent.

Let n be the size of the system and m be the number of test points, the dimensions
of AP and Ax are thus nxn and mxl, respectively. An important feature in the diagnosis
equation (1.5) is that m<n, that is, the number of equations is much less than the

number of unknowns. This leads to the difficulty of solving the diagnosis equation.

1.2 CLASSIFICATION AND COMPARISON

In order to solve fault diagnosis problems, various fault diagnosis algorithms have
been proposed. These diagnosis algorithms can be roughly classified into two categories
[36]:

(1) Pre-Test Simulation Technique,

(2) Post-Test Simulation Technique.

The pre-test simulation technique requires the simulation of various possible faults
and the storage of the results as a dictionary [12]. In other words, for each possible AP,
corresponding Ay is calculated and stored in a dictionary. The faulty network responses
measured are compared with the dictionary entries and the closest entry to the responses
by a certain measure determines the possible fault. This technique is commonly
employed in digital testing and is characterized by minimal on-line computational
requirements. However, the high cost of analog circuit simulation coupled with the
large number of potential fault models limits the applicability of this algorithm.

The post-test simulation technique is to solve the diagnosis equation for AP by
either increasing the number of equations or decreasing the number of unknowns. It can
be further divided into simulation with sufficient measurement and simulation with
failure bounds. The former is to increase the number of equations by obtaining
sufficient measurements from various test points [34, 40, 42]. The latter is to decrease
the number of unknowns by first assuming some components that are good and verifying
them later [15, 43, 48, 49, 50].

Since sufficient measurements are needed in the former approach, multiple fre-
quencies are applied and exu'emely expensive on-line computation is required to solve
the high complexity of the nonlinear diagnosis equation. In contrast, the latter approach
requires only a single frequency for the measurement and performs a simple on-line
computation.

To evaluate a practical analog diagnosis algorithm, the following criteria are con-
cerned [36]: computational requirements, number of test points and test vector
employed, robustness to tolerance effects, availability of models, and the degree to
which the algorithm is amenable to parallel processing. Based on the above criteria, the

Post-Test Simulation with Failure Bounds is better than others in test application.

1 .3 MOTIVATION

The research of analog fault diagnosis in the past years has posed several important
and challenging problems [26]. First, a component tolerance problem is concerned.
Some proposed algorithms work well for the case that the nonfault components assume
their nominal value exactly. However, the values of nonfault components in a practical
circuit may deviate from their nominal value within a predefined tolerance. As a result,
the fault components may not be properly located or even be detected. This motivates
the study of an algorithm that can alleviate the error effect due to component tolerance.

With the rapidly increasing complexity and size of modern electronic systems, the
ability to adequately design a diagnosable system is a prime requisite for rapid fault
location. Some fault location and prediction algorithms can precisely locate and predict
faulty components for small size networks. Due to the substantial increase of on-line
‘ computation for a large network, however, direct implementation of such algorithms for
a practically large circuit network would be impractical. In practice, a faulty network
generally has failures in a small portion of the network and the remaining parts are
fault-free. Decomposing a large circuit network into several small subnetworks seems a
very attractive idea, and, thus, serves as motivation to study a decomposition approach
fault diagnosis and fault prediction algorithm for large analog circuit networks.

Usually, more test points can faster and more precisely locate faults, but, unfor-
tunately, modern electronic systems are often multi-layered and/or coated, thereby limit-
ing the accessibility of test points which are available at the externally accessible termi-
nals of a printed circuit board. As the number of components in a unit increases, it is
difficult to provide proportionately more 1/0 terminals. It limits the implementation of
many fault diagnosis algorithms. In order to provide sufficiently more test points while
still keeping low pin overhead for analog circuit testing, an analog Built-in Self-test

structure (ABIST) is motivated.

Although an ABIST structure may provide as many test points as required for a cir-
cuit under test, the number of test points should not be indefinitely increased because of
the placement and routing problems. Therefore, it is necessary to select an appropriate
minimum set of test points that is sufficient to diagnose a circuit, as well as to develop

an efficient test point selection algorithm.

1 .4 THESIS ORGANIZATION

This dissertation is organized as follows. In the next chapter, a fault location algo-
rithm is presented. Basically, faults are located by checking the consistency or incon-
sistency of a set of linear equations. An Analog Automatic Test Program Generator
(AATPG) software package is developed for fault diagnosis use. Some examples are
presented which demonstrate that the proposed algorithms can precisely locate faults in
analog circuits.

In Chapter 3, a fault prediction approach is proposed. For the case that the parame-
ters of a potential faulty component are assumed to change gradually during each
maintenance period, by continuously monitoring the responses of the network, the pro-
posed fault prediction algorithm can predict whether or not any of the network com-
ponents is about to fail. The predicted fault components are then replaced before the
system actually fails.

In Chapter 4, a decomposition approach fault diagnosis and fault prediction algo-
rithm for large circuit network is addressed. Basically, a large circuit network is decom-
posed into several small subnetworks. Also the error effect due to component tolerance
in practical circuits can be alleviated and faults in large circuit networks can be precisely
predicted. Also this approach can be extend for nonlinear circuits.

In Chapter 5, an analog Built-in Self-test (ABIST) structure is proposed. This
structure not only provides more test points for analog circuit testing, but also acquires

test data at various test points simultaneously. The detailed structure and its operations

are described, the simulation result and hardware implementation of the design are
presented, and the VLSI implementation of the ABIST structure is discussed.

In Chapter 6, testability design principle is first outlined. Based on the design prin-
ciple, the issues of diagnosability and test set generation are addressed.

Finally, the last chapter summarizes the work of this dissertation research and

presents suggestions for related future research.

CHAPTER 2

FAULT DIAGNOSIS

 

Fault diagnosis includes both fault detection and fault location. Fault detection is
obviously a minimum requirement for fault location. When a circuit fails to a functional
test, a diagnostic test is carried out to identify faulty components and to evaluate the
faulty component values for studying the cause of failure. The information is fed back
to the designer for further improvement. In this chapter, the emphasis is placed on the
fault location of analog circuit networks. A diagnosis equation is derived first, followed
by fault location and fault evaluation approach. An efficient fault location algorithm is
presented and an AATPG that generates test programs for fault diagnosis use is dis-
cussed. Some examples are presented which demonstrate that the proposed algorithms

can precisely locate faults in analog circuits.

2.1 DIAGNOSIS EQUATION

Based on Tellegen theorem [13] and the concept of the adjoint network [7], a diag-
nosis equation describing the relationship between the variation of component parameter
and the change of voltage at accessible nodes is derived for a linear network. Consider a
linear network, N, that has b internal branches and m accessible terminals. Let N and N
be a faulty network and the adjoint network of N, respectively. The adjoint network N is

topologically identical to the original network N [7].

10

 

 

 

 

 

 

 

V 1 . V " . .
' °——'" Linear '1 ° . Fault v“ ° . Adjomt
Network - Network - Network
VP, 0— VPI. C . VP] 0——.-——
v e _ e A e
P" o——— . me e _ V1»: 0— .. ..
“W lit.th lieu}

 

 

 

 

 

 

 

 

 

Figure 2.1 Circuit Networks.

 

Based on Tellegen theorem, we have

b .. tn ..
For N: 2 (Vkik—Vkik) = - 2 (I’m ipj_vpj ipj) (2.1)
Ic=1 j=1
- b .. . . 1‘ m .. . . ~ ':
For N: Z [Vk(lk+Alk)—(vk+Avk)lk] = — 2 [vpj (lpj+Alpj vaj +Avpj )lpj] (2.2)
k=l j=l

Subtracting Equation (2.2) from Equation (2.1), we get

b x m x
z (VkAik-Avkik) = - 2 (I’m Aipj—Avpj ipj) (2.3)
k=l j =1
With branch constraints

it: = Yth. ik+Aik = O’ki'AyltXVlt'l'AVk). and it = yka9

Equation (2.3) yields
b A
X kak = AP (2.4)
k=l
where
Ax): = Ayk(vk+AVk) = MM. (25)
"' r .. .
Ap = 2 (Avpjtpj-vijtpj) (2.6)

1=1

1 1
A generalized form of Equation (2.4) can be expressed as
b
2 kaxk = Ap (2.7)
k=1

where W; and Ax; are listed in Table 2.1.

Table 2.1 w and Axk of Different Types of Components

 

 

 

Component type wk Ax;
admittance y Pk Ayk (vk+Avk)
cccs it Match/MIL)
controlled vccs 1;: Agk(VIt+AVIt)
sources ccvs it A7.(i£+AiI)
vcvs it Alldvii'AVIt)

 

 

 

 

 

 

(Note: superscripts h and j represent controlled and controlling

branches of a controlled source, respectively.)

Consider a matrix form for Equation (2.7)

WAX=AP (2.8)
where
W11 W12 Wlb
W21 W22 “’21:
W: . . . .
wml Wm2 me

 

 

AX=[Ax1Ax2°~Axb]T

AP=IAP1AP2"'APmlT

12

Note that wij = it?) represents the calculated voltage of the jth branch of the adjoint
network when a unity current excitation is applied at the itlr accessible terminal, and
Apj =Avpl- =ij—vpj is the voltage difference at the j-th terminals of both faulty and

nonfaulty networks.

2.2 FAULT LOCATION

Generally, the number of components in a circuit is always much more than the
number of test points, i.e., b>m. As a result, there is no unique nontrivial solution for
(2.8). In practice, however, it is reasonable to assume that there are only a few faulty
components in a reliably designed network. Of course, we do not know how many
faulty components exist, or where they are located in advance.

Let f be the number of faulty components. Without loss of generality, we assume
that the first f components are faulty and the others are nonfaulty, i.e., Ayk=0, or Axk=0,
for k=f +1, - - - ,b. Therefore, Equation (2.8) can be reduced as

WfAXf=AP (2.9)
where
”W11 W12 Wlfq
W21 W22 W2;
Wf= . . . .
Wml sz Watt

 

 

AXf= [A11 A12 ° ' ° AxflT
Equation (2.9) has a unique nontrivial solution only if
rank[Wf I AP] = rank[Wf] = f (2.10)

The condition (2.10) determines the number of faulty components and also
identifies the faulty components. The detailed fault location process is described in

Algorithm 1.

13

2.3 FAULT EVALUATION

Once the faulty components are identified, we may evaluate the faulty component
values to study the cause of the failures. Suppose that a matrix Wf of the corresponding
faulty components satisfies condition (2.10), with the existence of the generalized

inverse of Wf, Equation (2.9) yields
AX, = (Wftwfrl WIAP (2.1 1)

which gives the values of Axk, for k=l,2, ° ° - , f . The next step is to find all node vol-
tages.

Suppose that the admittance of a faulty component is changed from y to y+Ay.
This is equivalent to y connecting in parallel with Ay. According to the substitution
theorem [13], Ay can be substituted by a current source Ax, which depends on the devia-
tion Ay and its branch voltage, i.e., Axk=Ayk(vk+Avk). Similarly, the deviation of the
controlled sources can be substituted by a source, referred to as substituted source, as
illustrated in Table 2.2. Thus, a faulty network is equivalent to the corresponding non-

faulty network N connecting with some substituted sources Axk, as shown in Figure 2.2.

 

 

 

 

 

Figure 2.2 Equivalent Faulty Network.

 

14

Table 2.2 Substituted Sources of Different Types of Components

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IsI

 

 

 

 

type faulty components substituted sources
+ iii-AI; + G iii-AI;
y +A )(v +Av )
vk+Avk 0" yk k k vk+Avk h Ayk(v,+Av,)
- j - o
+ i2+Ai2 + i2+Aifi
G
CCCS t. t. ' ' It h
v +Av +A +A v +Av - -
k I: (Bk BUM; VI) It k Pk ABAVHAVD
— 3 - c
c_
VCCS It It (8k+A8t)(Vi+AVI) v"+Av" - .
"“5"" g? " * g. Asttvtmvi)
— — e
+ ifi+Aifi + ii+Aii 7:
o._———
ccvs ,, ,. - ' l. h
v,,+Av,z (YfiA'YkXVi'I’AVi) Vii-Av; . .
AYtMt‘tAVi)
_ - c
+ i2+Ai2
vcvs vim: walttxumvi

Aut(v{+Av£)

 

 

15

For a nonfaulty network N the nodal equation is expressed as follows

[H] [V”] =11..l (2.12)

1N

where H is the nodal admittance matrix, VN is the node voltage vector, IN is the current
vector of the voltage controlled sources, and 1,, is the node current source vector. Simi-
larly, the nodal equation of the faulty network of Figure 2.2 is expressed as

t7
[H] [7” =11..1—le;1 (2.13)
N

 

where 17” and 7N are the node voltage and current vectors of the faulty network, where
AX f is the substituted source vector. Since the matrix H, vectors I”, and AX f are all
known, Equation (2.13) can be solved for the vector 17” and 7N. Once both I7” and IN are

computed, the faulty component deviation Aef can be evaluated by AX f.

2.4 EQUIVALENT FAULT SETS

The number of faulty components and the faulty components can be determined by
checking Equation (2.10). If a set of components satisfies the condition in Equation
(2. 10), the sets of components are referred to as fault set candidates. In practice, how-
ever, more than one candidate may be concluded. Moreover, only one candidate that
contains all faulty components is the actual fault set, and the remaining candidates,
referred to as equivalent fault sets, that contain some nonfaulty components, but they

produce the same responses as the actual fault set at the accessible terminals. In other

words,
rank [Wfl AP] = rank[Wf(ac,) |AP]=f

The existence of the equivalent fault sets is attributed to either the topological

structure, or test points. The details are shown in the following properties.

16

Property 2.1
If the actual fault set contains a subset that consists of either
a) 1 components in loop L which consists of 1+] components, or
b) lcomponents in cutset C which consists of 1 +1 components incident to an inacces-
sible node,
then an f-component-set formed by a combination of any I components of loop L or
cutset C together with other f —l components of the actual fault set, is an equivalent fault

SCI.

Property 2.2
If m-f +1 row dependence of Wf is consistent with row dependence of Wflm), and

rank [WI] = f, the f-component-set corresponding to Wf is an equivalent fault set.

The proofs of Properties 2.1 and 2.2 are shown in Appendix 1.

Recall that, in the fault location process, Equation (2.9) is used to estimate the
number of faulty components and to evaluate the faulty component values. The under-
lying assumption for that process is Axk=0, for k=k+1, - - - ,b, i.e., the components that
are not in the fault set under processing, are faulty-free. The assumption is true only if
the actual fault set is processed. Therefore, the evaluated values of the components in
the actual fault set are virtually the same irrespective of the locations of the external
excitations and the applied frequencies. However, the assumption is not true when the
equivalent fault set is processed, because some Axk’s are not zeros. As a result, with the
application of different frequencies or different locations of the excitations, the
estimated values of the components in equivalent fault sets will be different. Based on
this concept, we may identify the actual fault set either by applying a different fre-
quency, or by relocating the external excitation for fault diagnosis use. In other words,
if more than one fault sets are obtained in the fault location process, properly relocating
the excitation is needed. From the component values estimated under two different

excitations, we should be able to identify the actual fault set.

17

2.5 SOFTWARE IMPLEMENTATION
The fault location algorithm discussed above is summarized in Algorithm 1.

Algorithm I .

(off-line phase)

Step 1. Input the network topology and its component nominal values to construct the
nodal admittance matrix H.

Step 2. Apply a unit current excitation to the ith accessible terminal of an adjoint net-
work. Construct the matrix W by the computer branch voltages v?)
(i=1,2, -~ ,b, i=l,2, - - - ,m) of adjoint networks

Step 3. Calculate the voltage V at the accessible terminals of the fault-free network N.

(on-line phase)
Step 1. Obtain the voltages I7 measured at the accessible terminals of a faulty network,
(either from the ATE or by simulation.)
Step 2. Load the data generated in the off-line phase and initialize r=1.
Step 3. Repeat
3.1. pick up a combination of r columns of matrix W to form W,;
3.2. Check if rank [W, | AP] = rank[W,] = r;
3.3.1. Calculate the following equations for the actual component value eh;
(a). AXf =(W}W,)‘1waP
(b). IHlIV.1=lI..l—IAX,1
(c). Aykfik) = Axk, where k=l,2, - - - ,f
((1). ct =yk+Ayb where k=l,2, - ~ - ,f
3.3.2. If ek >0, record this fault set; Until all combinations are applied.
Step 4. If no fault set is identified, then r=r+1, and Go To Step 3.
Step 5. If only one possible fault set is concluded, then faulty elements are located, and

the process is terminated.

18

Step 6. (more than one possible fault sets)
Apply the second excited source, and input the voltages measured at the acces-
sible terminals of a faulty network.
Repeat
6.1. Take a fault set at a time;
6.2. Calculate the equations (a) to (d) of step 3.3.1 for ek;
6.3. If e), <0, eliminate this set;
Until all fault sets are applied.
Step 7. Compare two ek’s obtained from Steps 3.3 and 6.2 for each fault set. If they

are equal, then this set is the actual fault set.

All Analog Automatic Test Program Generator (AATPG) that generates test pro-
grams for fault diagnosis use has been developed based on Algorithm 1. The process is
divided into two phases: off-line and on-line [23].

The off-line phase, corresponding to the test system design stage, is used by the test
system designer to input nominal network specifications and generate a data base which
is used by the on-line phase. The input requirements in the test program generation are
circuit description, input frequency, and accessible test terminals. During the on-line
phase, the data generated by off-line phase (the admittance matrix H, the matrix W, and
the accessible terminal voltage V) are loaded. The test data are acquired either by fault
simulation or from ATE (Automatic Test Equipment). With the measured voltages,
Algorithm I is carried out to identify the faulty components and evaluate the component
values.

In both off-line and on-line phases, AATPG provides user-oriented interfaces to
simplify the process of generating a new test program. The AATPG has been imple-
mented on VAX 8600 (ULTRIX) in Fortran and C [23].

19

2.6 EXAMPLES

In order to demonstrate the effectiveness of the proposed fault location algorithm,
two examples are given.
Example 2.1

Consider a linear resistive network, as shown in Figure 2.3, consisting of all unity

resistances. Suppose that nodes 1, 6 and 7 are taken as the test points.

 

 

Figure 2.3 The Resistor Network in Example 2.1.

 

In the off-line phase, the W-matrix and the voltages that are measured at the test points
when the network is fault-free, must be established before the test is conducted. Accord—

ing to the schematic circuit diagram of Figure 2.3, the H-matrix is generated as follows

N
O

3-1-1—10000000
-13oo-1—1ooooo
—103-100-10000
-10—14—100—1000
0—10—14—100—100
H: 0—100—13000-10
00—10003—100—1
000—100-14-10—1
0000—100—14-10
00000-100-130
_oooooo—1—1oo3,

 

 

Taking the H-matrix, the W-matrix is constructed as follows. We first apply a unity
excitation current to the node 1 of the adjoint network N, and then calculate the branch
voltages of the network N, which is listed in the first column of W-matrix in Table 2.3.
The remaining columns of the W-matrix are formed in a similar way. The computed
voltage vector V for the nominal network is shown in the second column of Table 2.4.
When the test is being conducted, the measured test data may be obtained from an
automatic test equipment (ATE). In this moment, however, the ATE is not available and
thus a set of simulated test data is employed. In this example, we assume that the com-
ponents 2 and 18 are faulty with r2=0.4§2 and r13=1.5(2. Column 3 and 4 of Table 2.4

list the measured test data V and the voltage difference, AP=V-V, respectively.

Table 2.3 W Matrix of Example 2.1

21

 

 

 

element (1) (6) (7)

1 3.50008—01 -l.37508-01 1.12508—01
2 3.00008 -01 8.33338 —02 -1.16678-01
3 3.50008 -01 5.41678 -02 4.16678-03
4 1.50008—01 7.91678 -02 2.91678 -02
5 2.00008 -01 -2.16678—01 8.33338 --02
6 5.00008 —02 -2.9l678 —02 1.20838 —01
7 1.50008—01 -l.12508—01 1.37508—01
8 5.00008 -02 —2.95838—01 5.41678 —02
9 2.50008 —01 1.12508 —01 --2.37508 -—01
10 2.50008 —01 1.37508 -01 -1.25008-02
11 2.50008-01 2.62508 -01 1.12508-01
12 2.50008 -01 4.87508 —01 1.37508-01
13 5.00008 -02 -4.16668 -03 3.45838 —01
14 1.50008 —01 1.25008 -02 2.62508—01
15 5.00008 -02 -7.08338 -02 7.91678 -02
16 2.00008—01 1.16678 —01 4.16678-01
l7 1.50008—01 1.20838 -01 7.08338 —02
18 3.5000e—01 3.4583e—01 2.9583e-01
l9 3.00008-01 4.16678 -01 2.16678-01
20 3.50008 -01 2.37508 -01 4.87508 -01

 

 

 

 

 

22

Table 2.4 Simulation Data of Example 2.1

 

Node V V AP

 

1.10008 +00 1.07508 +00 —2.50268 —02
5.50008 -01 5.77518 —01 2.75058 —02
5.50008 —01 6.19608 -01 6.95998 —02

 

 

 

 

 

 

Since we do not know how many faulty components exist, we will first check the
number of faulty components. Specifically, we start with f =1 for Equation (2.10) and

find that the following matrix satisfies Equation (2. 10) when f =2,

I 2 18 AP
1 3.0000e-01 3.5000e—01 -2.5026e-02
6 8.33338—02 3.45838-01 2.7505e—02
7 _—1.1667e—01 2.95838—01 6.95998—02 .

 

 

Since the fault set {2,18} is the only candidate, the components 2 and 18 are identified
as faulty.

The values of the faulty component 2 and 18 can be computed as follows. First,
Equation (2.11) is used to calculate AX f, which is listed in the second column of Table
2.5. Then, two substituted current sources AXf, i.e., Ax2 and Axlg, are connected in
parallel with corresponding components 2 and 18, as shown as Figure 2.4. The Vectors
VN and IN of the substituted network are computed from Equation (2.13). In this exam-
ple, the branch voltage vector VN for components 2 and 18 are listed in the third column
of Table 2.5. The computed branch voltages are used to evaluate the component devia-
tion, i.e., Ay=Axk/Vk, k=2,18. Finally, the faulty component values are detemrined by e).

= )’k+A)’ttt or r2 = 1/ 8]; = 0.4 and r13 = 1.5.

23

Table 2.5 Component Evaluation

 

 

 

Component AX f branch voltage Ay,c "F'el'
It
2 2.4512e-01 1.6341e-01 1.5000e+00 4.0000e-01
18 -1.3860e-01 4.1579e-01 -3.3334e—01 l.5000e+00

 

 

 

 

 

 

 

 

Figure 2.4 Equivalent Faulty Network in Figure 2.3.

 

 

24

Example 2.2

Consider a linear active circuit with a controlled source, as shown in Figure 2.5.
The component values are listed in Table 2.6, and the nodes 1, 2, 4 and 5 are taken as

the test points.

 

 

|__2 3 ll 4 II5
II II

- c
v r5 __.c5 7 13 6'11

 

 

- 6

"1 ’3 ‘ _I_ ' r10 r12
r8 T69
—_J_—

Figure 2.5 All Active Circuit.

 

Table 2.6 Component Values of Example 2.2

 

 

Component Value Component Value
r1 2052 r3 300
82 20u.F c9 10uF
r3 759 r 10 100
r4 109 6'11 20uF
r 5 4052 r 12 109
c5 15111-7 g 13 10
C7 25uF

 

 

 

 

 

 

 

25

Table 2.7 W Matrix of Example 2.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

element (1) (2) (4) (5)
l (6.1229e+00 (6.1229e+00 ( 1.2229e-03 ( 1.2357e-03
-1.3835e-02) -8.3133e-03) -1.6108e-02) -1.6107e-02)
2 (5.7220e-06 ( 3.3379e-06 ( 6.4091e-06 (6.4089e-06
-5.5215e-O3) 2.4362e-03) 4.8615e-07) 4.9174e-07)
3 (6.1229e+00 (6.1229e+00 ( 1.2164e-03 ( 1.2293e-03
-8.3133e-03) -l.0750e-02) -l.6109e-02) -1.6108e-02)
4 ( 6.1221e+00 ( 6.1221e+00 (-7.7410e-04 (-7.8222e-04
7.8425e—03) 5.4066e-03) 1.0202e-02) 1.0201e-02)
5 ( 7 .2482e-04 (7.2227e-04 ( 1.86l9e-03 ( 1.8702e-03
-6.4148e-O3) -6.4151e-03) -1.0403e-02) -1.0401e-02)
6 (7.2482e-04 (7.2227e-04 ( 1.8619e-03 ( 1.8702e-03
-6.4148e-03) -6.4151e—03) -1.0403e-02) -1.0401e-02)
7 (-2.0568e-05 (-2.0569e—05 (-4.1600e-05 (-4.6664e-05
-1.0487e-06) -l.0394e-06) 6.3636e-03) 6.3636e-03)
8 (6.9070e-05 (6.5195e-05 ( 1.2868e-04 ( 1.4134e-04
-9.7410e-03) -9.741 1e-03) -1.5908e-02) -l .5908e-02)
9 (6.9070e-05 (6.51956-05 ( 1.2868e-04 ( 1.4134e-04
-9.7410e-03) -9.741 1e-03) - l .59086-02) -1.5908c-02)
10 ( 8.1446e-04 ( 8.0803e-04 (2.0322e-03 (2.0582e-03
-1.61556-02) -l.6155e-02) -3.2674e-02) -3.2672e-02)
1 l (-1.2855e-05 (-1.2855e-05 (-2.6000e-05 (-3.2331e-05
-6.5751e—07) -6.5379e07) -1.6354e-06) 7.956le-03)
12 (8.2731e-04 ( 8.2089e-04 ( 2.0582e-03 (2.0905e-03
-1.6154e-02) -1.6154e-02) -3.2672e-02) —4.0628e-02)
13 (7.4539e-04 (7.4284e-04 ( 1.9035e-03 ( 1.9168e-03
-6.4137e-03) -6.4l40e-03) -1.6766e-02) -1.6765e-02)

 

 

 

 

 

 

26

Similar to Example 2.1, the W-mauix is computed as shown in Table 2.7, and the
voltage vector V is listed in the second column of Table 2.8. If we assume that the com-
ponents r4 and g 13 are faulty with r4=209 and g13=50, the faulty components are

located in accordance with the measured voltage vector V and AP shown in Table 2.8.

Table 2.8 Simulation Data of Example 2.2

 

 

Node V V AP
1 (6.1229e+00,-1.3835e—02) (8.82448 +00,-7.4l49e —03) (27015.: +00,6.4l998—03)
2 (6.12298 +00,-8.3l33e —o3) (8.8244e +00,—2.9683e ~03) (2.7015e +00,5.3449e—03)
4 (l.2229e—03,—l.6108e—02) (3.16708—03,—l.(X)20e —02) (l.9442e—03,6.08818—03)
5 (12357.: -03,—1.6107e—02) (3.1750e—03,-1.0018e—02) (1.9393e —03,6.08968 —o3)

 

 

 

 

 

 

Table 2.9 illustrates all fault set candidates that satisfy Equation (2.10). In order to
precisely identify the actual fault set, the unity excitation current is relocated at node 5.
Table 2.9 lists the evaluated component values for these two excitations. From the
differences listed in Table 2.9, the actual fault set {4,13} is identified, i.e., the com-
ponents 4 and 13 are known as faulty with r4=1/0.05=20, and g 13 =50, which are con-

sistent with the given simulated fault values.

27

Table 2.9 Simulation Results of Example 2.2

 

 

 

 

 

 

 

 

 

 

 

Fault values evaluated
Fault
set Excitation at node 1 Excitation at node 5 Difference
3 (1.93418—02,-1.038le—02) (2.0956e+01, 7.52648+00)
9.9934e—01
4 (4.40088-02, 1.0394e—02) (1.8184e+01, 3.0937e+00)
4 (5.00068-02, 2.473968—06) (5.0627e—02,—8.8866e—O3) ”336“”
5 (5.8136e+01,-l.8496e+01) (5.8135e+01,-1.8504e+01) '
4 (5.0006e-02, 2.47408-06) (5.0627e—02,-8.8866e-03) 17336641
6 (924868-100, 1.2056e+01) (9.24858+00, l.2055e+01) ’
(4.99928—02,—5.56118—06) (424468-02, 100268—02) 91597 _01
. e
7 (1.0575e +00, 2.2879e +00) (2.0806e+01, 1.2509e+01)
4 (5.0005e—02, 3.33738-06) (5.2221e-02,-8.87388—03) 17273 _01
’ . e
8 (290678-101, 5.6407e+00) (2.9068e+01, 5.6390e+00)
4 (5.0005e—02, 3.33738—06) (5.22218—02,—8.87388—03) 17273 —01
. e
9 (462098-100, 1.0898e+01) (4.6211e+oo, 1.0897e+01)
4 (5.0003e—02, 1.49048—06) (5.1185e—02,—4.1434e-03)
2.09968—01
10 (7.96988 +00, 1.9130e +00) (6.2489e+00, 1.91858+OO)
4 (5.0000e-02, 1.80728—10) (5.0000e-02, 3.74338-08) 82385 _05
. e
13 (5.000e+01, 3.488598—03) (5.0008+Ol,-1.5038e—04)

 

 

 

 

 

CHAPTER 3

FAULT PREDICTION

 

For the case that the nonfaulty components assume their nominal value exactly,
referred to as the ideal case, the proposed fault location algorithm can precisely locate
faults. On the other hand, for the practical case that the nonfaulty component values
may deviate from their nominal values with a predefined component tolerance, the algo-
rithm still can locate the most of the faults. In some situations, however, the deviation
may affect the determination of the system status even though all components are fault-
free. This accumulation is referred to as the error efi'ect. In the ideal case, the error
effect is merely the truncation error of the computer. In the practical case, however, the
error effect highly depends on the predefined deviation percentage of the nonfaulty com-
ponents.

Our study has found that if the predefined deviation percentage is within 5%, the
proposal location algorithm can confidently locate those (soft) faulty components whose
values are deviated, at least, 50% of the nominals. When the fault deviation is less than
50%, however, it is really difficult to determine whether the system failed. Moreover, if
we assume that the parameters of a potential faulty component are changed gradually,
the faulty components can then be detected after system failed. For a reliable design,
the potential faulty components should be identified as soon as possible and replaced

before the system fails. Therefore, a fault prediction algorithm is motivated.

28

29

Of course, not all failures can be predicted. For example, there is little hope of
predicting component failure due to random external effects (improper operation, lightn-
ing, etc.). However, there is a significant experimental evidence to suggest that when
electronic components fail due to permanent overstress (high temperature, continued
overload operation, material fatigue, etc.), their parameters change sufficiently slowly
thus enabling a prediction of the time at which they will go out of tolerance by statistical

trending techniques [2,37].
3.1 ERROR EFFECT ANALYSIS FOR COMPONENT TOLERANCE

Consider a faulty network N’, whose nonfaulty component values deviate within a
prescribed tolerance. It is shown in Figure 3.1 along with corresponding nonfaulty net-

work N and adjoint network N.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V - ’ "
P1 c Linear VP1 O-—-.— Fault VP 1 O—:—-J AdjOint
Network - Network - Network
”m c VM' 0;- ij °_'__
N j 117’ 10
v", c ' V I . - f, . a
{1" Vt} m {it’Jt’I m Iii. 6k}
Figure 3.1 Circuit Networks.
Based on Tellegen theorem for N’, we have
b .. . T , — , ‘.‘ m a . T , — ‘3
Z [vk(lk+Alk )—(vk+Avk )lk] = —2 [ij (lpj-I-Alpj )—(vpj+Avpj ')t,,,-] (3.1)
k=1 j=1
Subtracting Equation (3.1) from Equation (2.1), we get
b A .7 I - I? m A T I - I?
2 (VkAlk -Avk 1*) = - Z (ijAlpj —Avpj lpj) (3.2)
k=1 j=1

30

If Ay,‘ and Ayk' are the deviations due to fault and component tolerance, respec-

tively, then, with the branch constraints for N’
intuit: = (awry )(vtmvt')

where Aik’ = Ayk+Ayk’, the left hand of Equation (3.2) is expressed as

210ka -Avk it) - 2 (VkAyk VI: )= EVAN/WAY]; )Vk
k=1 k: 1

b b
= Z (VkAYkI-k) + Z [VkAYk' Vk'+VkA)’k(Vk'-Vlt)]
k=1

k=1
Equation (3.2) yields
b A
“2 vaxk- — Ap’—Ae' (3.3)
where
Ax]: = Akak
I m - I? “ 7 I
AP = 2 (Mp1 'pj-ijA‘pj) (3'4)
i=1
’ b A I- I A I —
A8 = 2(VkAYk Vk MAW. ‘Vk)). (3.5)
k=1

note that 7,, is the kth branch voltage of a faulty network without tolerance, and Vk’ is the
kth branch voltage of a faulty network with tolerance.

Comparing Equation (3.3) with (2.4) in these two different cases, the only differ-
ence is that there exists an additional term —A8’ in the right-hand side of Equation (3.3).
This term, referred to as the error term, is caused by the component tolerance. In the
ideal case, b0th Ayk’ and (if—7k) are zero, hence Ae’=0. In practice, we must face the
problem of A830. If we directly implement the algorithm developed for the ideal case
to practical case, the error term Ae’ will be ignored. When fault deviation is larger than

50%, that is, Ay is more than 10 times larger than Ayk’, the ignoring of Ayk’ may not

31

cause any problem. But when fault deviation is less than 50%, a large error effect may
be caused so that the faulty components sometimes cannot be precisely located.

Now, let us closely examine the error term Ae’. Consider the second term of Equa-
tion (3.5), the deviation (if—7k) due to the component tolerance is generally small for a
reliable design even if the circuit fails. Thus, the second term can be neglected if a
parameter of a potential faulty component is changed gradually.

The first term of Equation (3.5) can be neglected only if v'k’ is very small for all
branches in the given circuit. This is virtually impossible in many practical circuits.
Therefore, the error effect due to the error term in Equation (3.3) cannot be eliminated

and will limit the implementation of the fault location process in the practical case.

3.2 BASIC CONCEPT OF FAULT PREDICTION

Our objective is to keep the error term within a reasonably small range so that one

can locate the faulty components precisely and evaluate the component values correctly.

32

 

 

 

 

 

 

( C) ( d)
Component with nominal value
Component with tolerance

Fault component

Equivalent current source
due to component tolerance

 

 

®®§§U

Equivalent current source
due to fault

Figure 3.2 Basic Concept of Fault Prediction.

 

33

Consider a network N1, as shown in Figure 3.2 (a). Each component in N1 is
assumed to have a predescribed component tolerance. According to the substitution
theorem, the component with a tolerance can be modeled by a current source (for com-
ponent tolerance) connected in parallel with the component having its nominal value.
Therefore, network N 1 is modeled as shown in Figure 3.2(b). On the other hand, con-
sider a network N2, as shown in Figure 3.2 (c), having the same topological structure
and component values as N1, except that component #2 is assumed to be faulty. Faulty
component #2 can be modeled by connecting an additional current source (for fault) in
parallel with the component, as shown in Figure 3.2 ((1). Suppose that the corresponding
components in both networks N 1 and N 2 have the same component tolerance, which
implies that the corresponding current sources modeled for component tolerance are the
same. Therefore, by the superposition theorem [13], the corresponding current sources
due to component tolerance can be canceled by each other. The resultant circuit (Figure
3.2 (e)) shows each component with its nominal.

In practice, it is very difficult to predict whether the corresponding components in
both N1 and N 2 have the same component tolerance. However, for a reliable circuit
design, it is reasonable to assume that the nonfaulty component parameters have virtu-
ally no change during a reasonably short period of time. In other words, if a network is
continuously monitored, then the component tolerance of the nonfaulty components are
virtually the same. In the fault prediction approach, these two consecutive measure-
ments obtained from the same network can be treated in the same way as the measure-

ments obtained from two networks N 1 and N2. Therefore, the above argument applies.

34

3.3 FAULT PREDICTION APPROACH

As mentioned previously, in order to weaken the error effect due to component
tolerance, the error term must be kept as small as possible. One way to solve this prob-
lem is to monitor the voltage measurements at the accessible terminals continuously at
each periodic maintenance.

The voltage measurements monitored in two consecutively scheduled mainte-
nances are assumed to be the voltages measured at accessible terminals of network N’
and N’. It is reasonable to assume that network N’ is nonfaulty, since the fault predic-
tion process for the previous maintenance has predicted no faulty component in N’.
However, network N’ may or may not be faulty. If N’ is faulty, then networks N’ and N’

are referred to as the prefault and posdault network with tolerance, respectively.

 

 

 

 

 

 

 

V 1' V ' A . .
P ° Prefault ' ‘ °_— Postfault v" ° _ Adjornt
. Network - Network - Network

vpj c . VP}! o__.____ ij °__._

N : N’ N
vfl’c . V ’ . I; '

. I I put o-———I — _ ’ P“ O——-‘ a: A

“k 1 142v. } lav.)

 

 

 

 

 

 

 

 

 

Figure 3.3 Prefault and Postfault Networks.

 

Consider networks N’, N’, and the adjoint network N, as shown in Figure 3.3.

Based on Tellegen theorem, network N’ has

b 5 e e I l: m 5 . . p 7
2 [VkOk-I-Alk )—(Vk+AVk')lk] = -2 [11” (lpj-i-Alpj )—(ij+Aij ’)lpj] (3.6)
k=1 j=1

Subtracting (3.6) from (3.1), we have

b —. A A m — A
Z [(vaik’_AVk’ik HVkAik"AVk'ik)] = - 2 [ij (ipj "in 34ij "ij 31°ij (37)
1:1 i=1

35

With the branch consuaints,
ik' = yk'Vk', ik+Aik' = (Viti'Ayk'XV/t‘tAVk').
I-k' = 2151/. IRA}? = (yk+Ayk’)(vk+AVk’)r
and

4571/ = AYt'+A)’k

b
LHS of (3.7) = )3 (va5»',.’ Vk'—vtAyt' vt’ )
k=l

b
= Z [VAN/K +19ka '-VltA)’k' Vk']
k=1

b b
= 2 (VkAYk Vkl‘l’ Z [VkAyk' (Vk'rV/t' )-V AV). (Vt'-Vk)]
k=1 k=l

Therefore, Equation (3.7) can be written as

b
2 91AM, = Ap”-Ae” (3.8)
k=1
where
Axk = Aykvk

m A _.
I, _ O I. C I . e —A I . e ’— . e
AP - 2 [GP] VP! )9)! ”It (In! In 3]

i=1
II b A I I " I '-
Ae = Z [VkAYk (Vt —Vk ')+VkA)’k (Vt —Vk)]
k=1

Ayk, Ayk’, '17,, and 32’ are the same as defined preciously, (if—v0 is the difference of the
kth branch voltages of prefault and postfault networks, and (7227),) is the difference of
the kth branch voltages of the faulty network with and without component tolerance.
Similar to the Ap of Equation (2.7), Ap” is the difference of two voltage measure-
ment at the same jth terminals of N’ and N’. Consider error term Ae”, the second term

of A8” is the same as that of Ae’. Thus, this term has been shown to be negligible.

36

Furthermore, it is obvious that the deviation (if—v23 of A8” is much smaller than vk’ of
A8’ in the first term. In the case that components fail due to permanent overstress, the
component parameters change sufficiently slow. The resulting deviation (172%va is so

small that the error effect of Ae” can be totally negligible.

The fault prediction algorithm is summarized as follows:
Algorithm II.
Step 1. Retrieve the previous measurements vpj’ from the database.
Step 2. Input the voltage ij’ measured at the jth terminal.
Step 3. Check whether or not the system is functioning in a specific safety range.
Step 4. If so, GOTO Step 2. Otherwise, GOTO Step 5 to predict and locate the faulty
components.
Step 5. Calculate Apj” =ij’-vpj’, j =1,2, - ° - ,m.
Step 6. Similar to the Step 3 in Algorithm 1, locate and evaluate the component values.
Step 7. Check whether or not the components deviated within the prescribed tolerance.

Step 8. If so, GOTO Step 2. Otherwise, display the faulty components that have been
predicted.

3.4 EXAMPLES

In order to demonstrate the effectiveness of the proposed fault prediction algo-

rithm, two examples are given as follows.

Example 3.1

For the same network as shown in Figure 2.3, assume that component tolerance is
within :l:5%. Suppose that faulty components are r2=0.5 and r13=0.5. If we directly use
the fault location algorithm shown in Section 3.1, the computed node voltages V and

measured node voltages V’ and AP’ are listed in Table 3.1.

37

Table 3.1 Simulation Data 1 of Example 3.1

 

 

 

 

 

 

Node V V’ AP’
1.1000008 +00 9.6593058 —01 —1.3406958—01
5.5000008 —01 4.6386568 —01 —0.8613448—01
5.5000018 —01 5.1533738 —01 —0.346627e—01

 

Similar to the fault location process discussed in Example 2.1, with the use of the
W-matrix in Table 2.3, we cannot find the fault set candidate that satisfies the condition
rank[Wfl AP’]=rank[Wf]=f, i.e., the faulty components cannot be located properly.

With the proposed fault prediction algorithm, the voltage measurements monitored

in prefault and postfault network V’ and V’ are listed in Table 3.2.

Table 3.2 Simulation Data 2 of Example 3.1

 

 

 

 

 

 

Node V’ 17' AP”
1.110968e+00 9.6593058-01 —1.450375e—01
5.6704168 -01 4.638656e -01 -1.03l760e—01

7 5.6680638—01 5.153373e-01 —0.5146908-01

 

With the same W—matrix of Table 2.3, we find the set {2,18] is the actual fault set, i.e.,
the components 2 and 18 are known as faulty, and their component values are estimated

as r2=0.494 and r 13:0.468, which are very close to the given simulated fault values.

Example 3.2

Consider an active filter whose component nominal values are shown in Figure 3.4.

Assume component tolerance is within 15%. Suppose that a voltage source of 0.5v at

lOkHz is applied. Assume that faulty component R 8=1500§2 is simulated.

 

 

38

 

 

 

 

 

 

 

 

15L
L_J
2.992].
C} I 5.32»
I f
R
10]:

 

 

 

 

Figure 3.4 All Active Filter.

 

The voltage measurements monitored in prefault and postfault networks, V’ and V’,

are listed in Table 3.3.

Table 3.3 Simulation Data of Example 3.2

 

Node V’ V’

 

(—5.486664e —04,—1.6325758 —02) (—1.354974e —04,—7.8952288 --03)
6 ( 1.6355278 —01,—5.407 3898 —03) ( 7.9094348 —02,—1.3143128 -03)
7 (—1.5583358 -01, 4.9799978 —03) (—7.5360098 —02, 1.1637448 -03

 

 

 

 

 

Following the fault prediction procedure, we can find that the set {8} is the actual fault
set , i.e, the component 8 is known as faulty, and its component value is estimated as

R 3:14879, which is very close to the given simulated fault values.

39

3.5 DISCUSSION AND SUMMARY

In Chapters 2 and 3, fault location and fault prediction algorithms are presented, in
which faults can be precisely located and potential faulty components can be predicted
before the system actually fails.

In the fault location and prediction algorithms discussed in Algorithms I and II, the
major computational requirement in the off-line phase are (1) to construct matrix H; (2)
to calculate branch voltages 175’.) for adjoint networks to build matrix W; and (3) to calcu-
late node voltages V for the fault-free network N. In the on-line phase, the computation
includes the rank checking in Equation (2.10) for all possible matrices Wf’s. When the
size of the circuit network is reasonably small, the dimensions of matrices and equations
will also be small. Consequently, the computation requirement for both on-line and off-
line may not dominate the speed of diagnosis. However, when the size of the circuit is
increased, both the dimensions of matrices and equations in the off-line phase and the
component combinations for the rank checking in the on-line phase are increased. That
results in the requirement of expensive off-line and on-line computations. Therefore,
the proposed algorithm is not feasible to diagnose faults in large networks.

However, if a practical large network can be decomposed into several small sub-
networks, then the proposed fault location and prediction algorithms can be applied to
diagnose the subnetworks with a reasonably high speed. This motivates the develop-
ment of a decomposition approach fault diagnosis algorithm for large circuit networks,

which will be discussed in the next chapter.

CHAPTER 4

DECOMPOSITION APPROACH FAULT PREDICTION

 

With the rapidly increasing complexity and size of modern electronic systems, the
ability to adequately design a diagnosable system is a prime requisite for rapid fault
location. The fault location and prediction algorithms discussed in previous chapters
can precisely locate and predict faulty components for small size networks. Due to the
substantial increase of on-line computation for a large network, however, direct imple-
mentation of such algorithms for a practically large circuit network would be impracti-
cal.

In practice, a faulty network generally has failures in a small portion of the network
and the remaining parts are fault-free. Decomposing a large circuit network into several
small subnetworks seems a very attractive idea. Recently, a decomposition approach
fault diagnosis process has been proposed [39]. The approach can precisely locate faults
when component values assume their nominal. However, the error effect due to com-
ponent tolerance in practical circuits may drastically affect the identification of the
faulty components.

In this chapter, the decomposition approach originally proposed by [39] is dis-
cussed. The inherent problems in such an approach are also pointed out. In order to
alleviate error effect, a decomposition approach fault prediction algorithm is presented

to precisely predict faults in large circuit networks.

41

4.1 DECOMPOSITION APPROACH

Consider the original decomposition approach proposed by Salama, Starzyk, and
Bandler [39]. In this approach, a nodal decomposition of a network into smaller uncou-
pled subnetworks is canied out; The measurement nodes (or, accessible nodes) must
include the nodes of decomposition (for simplicity, these nodes are referred to as D-
nodes); The voltage measurements are employed to isolate the faulty subnetworks; The
incidence current relation between subnetworks are checked against the KCL
(Kirchhoff’s Current Law) to determine the status of those D-nodes; And a logic

analysis of the results is carried out to identify faulty subnetworks.

 

 

 

Figure 4.1 A Subnetwork S,- with m,- Extemal Nodes.

 

Consider a linear subnetwork S,- as shown in Figure 4.1. It consists of n,- internal
nodes and connects to other subnetworks through the m,- extemal nodes. Let V"‘ and Vm‘
be the voltage vectors of the n,— intemal nodes and m,- extemal nodes, respectively, and
1'”i be the incidence current vector of the subnetwork S,- fiom the m,- extemal nodes, the
nodal equations of the subnetwork S,- then are expressed as follows

[Yr-m Ymtnt] [Vm‘] _ [mi 4'12"]
Yum Yum V"‘ —

I: (4.1)

 

42

where

m,
8
a]

- I
H

is the current sources associated with the subnetwork.

Eliminating the n,- intemal nodes yields [39]
1’"; =31? ’ Ymtnt Y;1'1"i [31+ [Ymtm " Ymtnt Yin-1m Yntmt] th (42)

The sum of the computed currents associated with each D-node is checked against the
KCL. If the computed currents satisfy the KCL at a D-node, all subnetworks connected
to this node are fault-free. Otherwise, at least one of these subnetworks is faulty. In
fact, if the currents associated with a fault—free node satisfy the KCL, the sum of such
currents should be zero. In practice, however, a reasonably small tolerant term 8 is used
as the bounds. In other words, if the sum of the currents is less than a predefined
tolerant term 8, then the node is fault-free; otherwise the node is faulty.

In order to demonstrate the decomposition approach proposed in [39], two exam-
ples are discussed. Example 4.1 will show that the approach can identify the faults pre-
cisely when the component values assume their nominals. Followed by Example 4.2
which illustrates the approach for the case that each component deviates from its nomi-

nal within 5%.

Example 4 .1 .
Consider a linear network as shown in Figure 4.2 [10], the component values

assume their nominals exactly.

43

 

 

 

 

 

G, 1.5 G-, 3.0
G2 1.8 G; 1.3
G; 2.0 Go 2.3
G4 0.5 610 3.1
G, 2.6 G“ 2.9
6'6 1.2 012 0.8

 

 

 

 

 

 

 

 

Figure 4.2 A Linear Network.

 

Suppose that component 7 is faulty and its component value is changed from G7 = 3.0
to 2.0. We first decomposed the network of Figure 4.2 into S1 and S 2 as shown in Fig-

ure 4.3, where nodes 1, 4, and 7 are selected as D-nodes.

 

 

 

 

 

 

 

 

 

 

Figure 4.3 Decomposed Subnetworks S 1 and S 2.

 

Table 4.1 shows the simulation results of the first level of decomposition, where 1;
represents the incidence current of the subnetwork S,- from the D-node j, and 2 1"",

Column 6 of Table 4.1, denotes the sum of the computed currents at the D-node j.

Column 6 shows that the summation of currents at the node 1 is approximately zero, and

44

concludes that the node 1 is fault-free. Since the current summations at both nodes 4
and 7 are far away from zero, both nodes are determined as faulty. Therefore, the sub-
network S 1 is determined as fault-flee, but S2 is as faulty. From Figure 4.3, the faulty

component is indeed contained in S 2.

 

 

Table 4.1
Node j v”"' I, Subnetworkl Subnetwork 2 21""
1 1.721510 2.00000 1}: 2.00000 — -5.551115e-17
4 0.410680 0.00000 11:0.66922 1% =0.74504 -7.582164e-2
7 0.571673 1.00000 - 1%:097943 2.056651e-2

 

The faulty subnetwork may be decomposed further if necessary. Figure 4.4 shows
that the faulty subnetwork S 2 is further decomposed into S 3 and S 4, where the nodes 4,

6, and 7 are selected as D-nodes, and the current source 151 is obtained from the previ-

ous level of decomposition, i.e., I S1 = J}; =0.66922 (Table 4.1).

 

 

 

 

 

 

 

Figure 4.4 Decomposed Subnetworks S 3 and S 4.

 

Table 4.2 lists the simulation results and concludes that subnetwork S 4 is fault-free,

but S3 is faulty.

45

Table 4.2

 

Node j v” I, Subnetwork 3 Subnetwork 4 z 1""

 

4 0.410680 0.66922 12:0.88125 12:0.12879 -8.323550e-2
6 0.271258 0.00000 1g=0.81803 Ig=-0.87121 5.317849e-2
7 0.571673 1.00000 — 13= 1.00000 5.551115e-17

 

Example 4.2.

Consider the same network of Figure 4.2, but with component values deviating
from their nominal values within a random tolerance of 5%. Suppose also that the com-
ponent 7 is faulty. Similar to the procedures discussed in Example 4.1, Table 4.3 lists
the simulation results of the first level of decomposition that decomposes the network

into S1 and S 2 with the same external nodes.

 

 

Table 4.3
Node j V’"‘ 18 Subnetwork 1 Subnetwork 2 z 1”"
1 1.716525 2.00000 1]: 1.9894 — 1.064765e-2
4 0.417103 0.00000 11 =0.65933 1§=0.77128 —l.l 19470e-l
7 0.568505 1.00000 — 13:0.96353 3.647195e—2

 

With an predefined tolerant term 8, it is still possible to conclude that both nodes 4 and 7
are faulty, but node 1 is fault-free. Consequently, the subnetwork S1 is determined as
fault-free, but S2 is as faulty.

For the next level of decomposition, Table 4.4 lists the simulation results.

46

Table 4.4

 

Node j V""' 18 Subnetwork 3 Subnetwork 4 z 1""

 

4 0.417013 0.65933 12:0.89364 12=—0.12112 -l.131928e-l
6 0.276830 0.00000 12:0.83693 12=-0.84586 8.922686e-3
7 0.568505 1.00000 — 1:}: 0.96698 3.302115e-2

 

If we denote 1,, as the sum of computed currents associated with the D-node k,
Column 6 of Table 4.4 shows that 14 > 1:7 > 15. We claim that it is impossible to find
any tolerant term 8 to precisely identify the faulty component 7 in this approach. Two
cases can be identified for the range of the 8: either it lies between t5 and 1:7, or between
1:4 and 17. If 8 lies between 16 and 17, then both nodes 4 and 7 are determined as faulty,
but node 6 is fault-free. Further, since all the subnetworks connected to a fault-free node
are fault-free and node 6 is fault-free, both subnetworks S 3 and S4 are thus fault-free.
This implies that both nodes 4 and 7 must be fault-free, which contradicts the above
determination.

On the other hand, if we assume that 8 lies between 14 and 17. This yields that
nodes 6 and 7 are fault-free, but node 4 is faulty. Similarly, subnetwork S3 is concluded
as fault-free and results that node 4 must be fault-free which is also a conuadiction.
Therefore, it is impossible to predefine a tolerant term to determine the faulty com-

ponent in this approach.

Example 4.2 shows that the decomposition approach in [39] may not precisely
identify the faulty components when the component tolerance is taken into account. The
fact is that an error effect due to the component tolerance could affect the fault
identification process. In our observation, the major problem of that decomposition
approach is that the error effect is induced not only by the component tolerance, but also

by the accumulation of the computation error. More specifically, in the second level of

47

decomposition, for example, the current source 15,, as shown in Figure 4.4, is obtained
from the results computed in the first level of decomposition. In Example 4.2, I St = ~11
= 0.65933, which differs from the current 131 = J}, =0.66922 obtained in Example 4.1.

This computed error is carried forward for the computation for the next level of decom-
position. As a result, as more levels of decomposition are executed, the higher the
induced error accumulation may be. In fact, the error effect can be alleviated if the com-
puted current is avoided. This motivates the development of a decomposition approach

fault prediction algorithm that is presented in next section.

4.2 FAULT PREDICTION APPROACH

Consider Equation (4.1), if we reorder the equation as

Yntnt Yntmt V"" = 1?
Ymtnt Ymtmt Vm‘ l"“+l'g"‘

and apply the forward—elimination steps of the Gaussian elimination method to Equa-

(4.3)

 

 

tion (4.3), then we obtain

Uni": V," = I?“ (44)
0 Ymtmt Vm‘ I""'+l;"" '

where U is an nixn; upper triangular matrix with all 1’s in the major diagonal, and 0 is

 

an mixn; zero matrix. Equation (4.4) gives the following nodal equation of mi’s external

nodes

Ymm' v"" =IZ'"+I’"‘ (4.5)
01'

1”” = 4;" + YWW' V"" (4.6)

where Ymm" can be computed off-line using component nominal values. Denote vectors

VT and V2" as the voltages at external nodes of a subnetwork S,- measured at two

48

consecutive cycles. From Equation (4.6), we have
Ymim" v’f“ =1?" + 13'” (4.7)
YM' v3" =1?" + 1’2"“ (4.8)
Subtracting Equation (4.7) from (4.8)
Mm.- =I'2'" -l't"" = Y....’ W?" - Vi”) = Yam; AV... (4.9)

It should be pointed out that the computation of Equation (4.6) is much simpler
than that of Equation (4.2). This gains a significant improvement in computation. Also,
Equation (4.9) shows that the external currents I? are eliminated and thus the error
effect can be alleviated significantly.

Based on the above concept, the decomposition approach fault prediction algorithm

is summarized in Algorithm HI.

Algorithm III
Step 1. Decompose the network at all the accessible (external) nodes (by logically
breaking the connection at the nodes) to obtain smallest possible subnetworks.

Step 2. Compute Ymm’ by using the nominal parameter values of each subnetwork S 5.

Step 3. Retrieve the previous measurement V’f‘ from the data base.

Step 4. Input the Voltage V? measured at decomposition nodes.

Step 5. Calculate AV", = V? -V’1" and check whether the system is properly functioning
in a specified safety range.

Step 6. If so, ( no fault is detected) GOTO Step 4.
Otherwise, (to identify the faulty subnetworks).

Step 7. AIW=Y,,,'.,,,,’AV,,,‘

Step 8. If the computed currents satisfy KCL at a D-node, all the subnetworks con-

nected to this node are fault-free. Otherwise at least one of these subnetworks

is faulty.

49

In order to demonstrate the effectiveness of the proposed algorithm, Example 4.3 is

discussed below.

Example 43.

Consider the same network and same conditions as in Example 4.2. Following

Algorithm III, Tables 4.5 and 4.6 list the simulation results for two levels of decomposi-

tion illustrated in Table 4.3 and 4.4, respectively.

 

 

 

 

 

Table 4.5
Node v’l’" v3" AV,“ 2A5",
1.706806 1.716525 9.718500e-3 -2.112174e-4
4 0.397415 0.417103 1.968805e-2 -8.283782e-2
0.568300 0.568505 2.045350e-4 2.318341e—2
Table 4.6
Node V’f" v3" AVmi 2 A1,,
0.397415 0.417103 1.968805e-2 -7.657193e-2
0.281749 0.276830 -4.919049e-3 5.806152e-2
0.568300 0.568505 2.045350e—4 7.284202e-4

 

In contrast to Example 4.2, it is possible to consistently select a tolerant term that

can precisely determine the faulty component 7 from both Tables 4.5 and 4.6.

Example 4.4

Consider a signal filter circuit shown in Figure 4.5. Its component values are listed

in Table 4.7. The network is decomposed into six subnetworks, as shown in Figure 4.6,

where decomposition nodes are 1, 3, 5, 11, 13, 15, 21, and 22.

50

"r

 

 

20
727

 

 

 

 

 

II

 

 

. i

 

11

I

 

11

Figure 4.5 A Signal Filter Circuit.

 

51

Table 4.7 Component Values of Example 4.4

 

 

Component value Component value
€1,615 0.11113 r8,r23 15m
82, cu 0.111F r9, r24 750m
C3, 613 0.111F r10,r25 2209
c4, (:19 2.21113 r11, r26 39k!)
es, 620 2.2uF r12, r27 1k!)
(:5, 621 0.01uF r13, r23 56k!)
r7, r22 56k!) r14, r29 5609

 

 

 

 

 

 

 

 

' 'JI

S3 021

 

22

 

 

-3sin 4001::

Figure 4.6 Decomposed Subnetworks.

 

Assume that r9 is simulated as faulty component with r9=7.5k. A transient

analysis is performed with a bus time step. The simulation results are listed in Table

52

4.8, and the simulated results at t=10ms are summarized in Table 4.9.

Table 4.8 Simulation Result of Example 4.4

 

 

 

 

 

Time node 1 node 3 node 5 node 21
0.000E+00 0. e+00 0. e+00 0. e+00 0. e+00
1.000e-03 2.849e-18 3.532e-05 6.372e+01 2.787e—21
2.000e-03 1.761e-18 -9.680e-05 2.716e+01 3.892e-20
3.000e-03 -1.760e-18 -8.152e-05 -7.678e+01 -1.028e-19
4.000e-03 -2.849e-18 5.648e-05 -9.200e+01 0.000E+00
5.000e-03 -3.463e-16 1.223e-04 1.035e+01 2.787e-21
6.000e-03 2.849e-18 2.249e-05 9.335e+01 -1.028e-19
7.000e-03 1.761e-18 -1.065e-04 4.490e+01 4.797e-20
8.000e-03 -1.760e-18 -8.720e-05 -6.657e+01 9.727e-20
9.000e-03 -2.849e-18 5.318e-05 -8.619e+01 -l.042e-19
1.000e-02 3.139e-18 1.205e-04 1.364e+01 -l.084e-19

Time node 11 node 13 . node 15 node 22
0.000E+00 0. e+00 0. e+00 0. e+00 0. e+00
1.000e-03 -2.849e-18 6.018e-20 -1.109e-14 2.432e-20
2.000e-03 -l.761e-18 2.662e-21 3.158e-14 -5.142e-20
3.000e-03 1.760e-18 4.000e-21 3.477e-14 -2.545e-20
4.000e-03 2.849e-18 -3.497e-20 2.41 1e-l4 2.787e-21
5.000e-03 3.463e-16 -5.399e-21 3.687e-14 -2.787e-21
6.000e-03 -2.849e-18 2.908e-20 3.551e-14 2.571e-20
7.000e-03 -1.761e-18 1.102e-20 2.934e-14 4.864e-20
8.000e-03 1.760e-18 1.798e-20 3.257e-14 2.467e-20
9.000e-03 2.849e-18 2.019e-21 2.746e-14 -5.700e-20
1.000e-02 -3.139e-18 -5.880e-20 5.981e-14 -5.421e-20

 

 

 

 

 

 

53

Table 4.9 Analysis in One Time Step

 

 

 

 

 

 

 

node AV," 2A1 subnetworks incident at node
1 -l.3658-04 3.139—18 S1
6.7278 —01 1.205—04 S1, S 2
5 5.0808—01 1.364+01 S2,S3,S15
21 —1.352e+00 -1.084e—19 S3
11 —2.514e-09 -3.139e—18 S4
13 4.9668 —05 -5.880e —20 S4, S 5
15 1.9058—05 5.9818—14 S3,S5,S15
22 1.8458+00 —5.4218—20 S 5

 

Table 4.9 shows that the currents associated with the decomposition nodes 1, 11,
13, 15, 21 and 22 satisfy the KCL, and the currents at nodes 3 and 5 do not satisfy the
KCL. This implies that the nodes in the former group are fault-free, and nodes 3 and 5
are faulty. As a result, the subnetwork S2 connected to both faulty nodes 3 and 5 is
known as faulty. As shown in Figure 4.5, the faulty component r9 is, in fact, contained

in this subnetwork.

4.3 EXTENSION TO NONLINEAR CIRCUIT NETWORKS

Typically, the nonlinear network is dominantly linear with a few nonlinear com-
ponents [39]. In general, the nonlinear components are "linearized" in order to be
modeled by a digital computer. After linearization, even the most complex models con-
tain only two different types of circuit components [9]: a resistor (impedance) and a
current source, which may be voltage-dependent. Therefore, the decomposition
approach developed for linear circuit networks can be applied for nonlinear networks.
Basically, the nodes of decomposition are chosen such that the network is decomposed

into blocks that contain the nonlinear components and a number of subnetworks that

54

contain only linear components. In order to analyze the nonlinear subnetwork we use
the SPICE program [30] as the network solver. A set of voltage controlled voltage
sources are added to all decomposition nodes of the original circuit to accept the vol-
tages measured at two consecutive cycles. The transient analysis is used to calculate the

sum of currents flowing into the decomposition nodes at each time step.

Example 45

Consider a nonlinear network as shown in Figure 4.7 (a), which consists of all linear
resistors except component 13, where the nominal values of the linear resistor are 19
and the nonlinear resistor with the function i =2v3. Suppose that components deviate
from their nominal values within a random tolerance of 5%. The network is first decom-
posed into four subnetworks S1, S2, S 3, and S4, as shown in Figure 4.7 (b), where S4
only consists of the nonlinear component r13, and decomposition nodes are l, 3, 7, 8, 9,

and 11.

55

 

 

 

 

 

r14

 

 

 

 

(a)

   

 

  

I in=2sin 1201

(b)

Figure 4.7 (a) A Network (b) Decomposed Subnetworks.

 

56

Two cases are simulated in this example: (1) the nonlinear component r 13 is faulty;

and (2) two linear components r1 and r9 are faulty.

In the former case, the i-v function of the component r13 is assumed to be changed

to i =4v3+1. Following Algorithm III, the voltages measured at the decomposition nodes

and the sum of computed currents associated with each decomposition node at one time

step are listed in Table 4.10.

Table 4.10 Simulation Result 1 of Example 4.5

 

 

node AV," 2A1 subnetworks incident at node
1 1.434e—01 —4.163e-06 s1
3 18258—0] -1.3968—01 S1, S4
7 1.0448-01 -2.0488-04 S1, S2
8 —7.8258 -02 1.3988 -01 S 2, S4
- 9 -5.2158 —02 -6.8018—05 - S2, S3
11 -2.611e-02 6.8018 —05 s2, 83

 

 

Table 4.10 shows that the currents associated with the decomposition nodes 1, 7, 9,
and 11 satisfy the KCL, and the currents at both nodes 3 and 8 do not satisfy the KCL,
which are thus claimed as the faulty nodes. As a result, subnetwork S4 connected to
these two nodes is found as faulty. In fact, the faulty nonlinear component r13 is in this
subnetwork.

In the latter case, linear components with r1=59 and r9=1052 are simulated as
faulty. Following Algorithm III, the voltages measured at the decomposition nodes and

the Sum of computed currents associated with each decomposition node at one time step

 

are listed in Table 4.11.

 

 

 

57

Table 4.11 Simulation Result 2 of Example 4.5

 

 

node AV", 2A] subnetworks incident at node
1 —1.563e —01 2.7808 —01 S1
3 6.4528 —02 —3.073e —01 S 1, S 4
7 -6.034e —02 8.6018 —02 S 1, S 2
8 4.5258 —02 —6.0338 —05 S 2 , S 4
9 3.0158 —02 3.9328 —05 S 2, S3
11 1.5108—02 —3.9328—05 S2, S3

 

 

 

 

 

 

Table 4.11 shows that the currents associated with the decomposition nodes 8, 9,
and 11 satisfy the KCL, and the currents at nodes 1, 3 and 7 do not satisfy the KCL,
which are thus claimed as the faulty nodes. As a result, the subnetwork S1 that connects
to these three nodes is found as faulty. As shown in Figure 4.7, the faulty components

r1 and r9 are, in fact, contained in this subnetwork.

CHAPTER 5

BIST STRUCTURE

 

As discussed previously, faults can be precisely located at any desired level if
sufficiently many test points are provided. Unfortunately, modern electronic systems are
often multi-layered and/or coated, thereby limiting the accessibility of test points which
are available at the externally accessible terminals of a printed circuit board. As the
number of components in a unit increases, it is difficult to provide proportionately more
I/O terminals. 1

The built-in self-test (BIST) design [27, 28] has been commonly implemented for
digital circuit testing. The BIST design virtually increases the number of test points
while still keeping low pin overhead. Circuits that generate test patterns and analyze the
output responses of the functional circuitry are included on the same chip or elsewhere
on the same board.

In this chapter, the concept of BIST design developed for digital circuits is adopted
to the testing of analog circuit networks. An analog BIST structure is proposed and its

simulation and hardware implementation are also presented.

5.1 BIST STRUCTURES

In digital circuit, most BIST designs use some scan-path techniques, as shown as
Figure 5.1(a), with shift register latchs (SRL). Figure 5.1 [4] shows that SRL contains
two latches, L1 and L2. L1 constitutes the normal stored-state holding device with

58

59

system date (D) and system clock input and system data output. In normal operation,
scan clocks A and B are both held low. Latching of system data then occurs as the sys-
tem clock is returned low from an active high value.

To operate the SRL as part of a scan path, scan clock A is set to 1. This enables
data on the Scan-in to be latched directly into latch L1. Scan clock A is then returned
low (to latch the value into L1) and scan clock B raised high. This causes u’ansfer of the
latched L1 value into latch L2 with permanent latching in L2 as B is returned low. The
SRLs are connected to form a scan-path shift register by connecting the L2 output of one
SRL to the input of another SRL. The two scan clocks, A and B, are common to all
SRLs. A shift register with a chip containing 3 SRL’s is shown in Figure 5.1 (c)

By adopting a design concept similar to a digital shift register, one may intuitively
design an analog shift register (ASR), as shown in Figure 5.2 (a). The latch of the SRL
in Figure 5.1 (b) can be realized by an sarnple-and-hold circuit. A BIST structure with
analog shift registers is illustrated in Figure 5.2(b). Each unit (corresponding to a test
point) requires a test point buffer B,- and an analog shift register ASR1, where each ana-
log shift consists of two simple sample-and-hold (S/H) circuits. (Each S/H circuit con-
tains an analog switch, a holding capacitor, and a voltage follower.) The test point
buffer B,- is used to isolate the test circuit from the UUT, so the test circuit will not affect
the UUT, thus we can acquire voltage at the test point more accurately. In practice, a
voltage follower having a very high input impedance and a low output impedance is
employed. The buffer can then hold the test data without affecting the voltage level of

the system during data sampling periods.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Inputs_, 1—> Outputs
Sequential
System Function
Scan in——.. ' ° ° ——> Scan out
Shift Register
(a)
I" """""""""""""" “I
System Data (D

S t DtaOt
System Clock ys em a u

Scan Data In

     

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Scan Clock (A Scan Data Out
Scan Clock (B
L ________________________ .1
(b)
{iii} """"" ; sat; """"" I {3112; """"" I
1.. .2 ; ii i 8:"

 

 

 

w
L—

 

 

 

 

(C)

Figure 5.1 BIST Design of Digital Circuit:
(a) Scan Design Using Shift Register; (b) SRL;
and (c) a Shift Register with 3 SRLs.

 

61

 

*0:
I
I
E:
I
J

 

 

 

 

 

 

 

P1)“

I \. SW“ 1
I —/ 40

Q_,_' SW12 I

I VFn VF12 I

E l Cil I CIZ E

L- _ .7. ................ 3‘ .......... J
(a)
U U T

?m1 ?m2 e e e 3'":

 

 

 

SI

 

fimflfiflj I S: I151 In"?
I l l 1 :1

 

 

Figure 5.2 BIST Structure with Analog Shift Register:
(a) Analog Shift Register ASR1; and (b) Schematic Diagram.

 

62

This BIST structure allows the test data to be parallel sampled and serial shifted out
for analog circuit testing, so the test data at various test points can be acquired simul-
taneously. The structure also virtually increases the number of test points while still
keeping low pin overhead for analog circuit testing. However, each unit ASR1 requires
two sample-and-hold circuits. Such design could increase chip area and decrease the

operational speed. This motivates the following modification.

5.2 Analog BIST (ABIST) Structure

Figure 5.3 illustrates an analog BIST (ABIST) structure. Each unit (corresponding
to a test point) of a ABIST structure requires a test point buffer 8;, an analog pass buffer
APB1, and a pass switch SP1. Each analog pass buffer contains only one sample-and-hold

circuit.

 

 

 

PI U U T 20

 

 

 

 

 

 

SI

 

 

 

 

 

SO

 

‘1’
2L

r--:- ---

 

 

 

 

Figure 5.3 An Analog BIST Structure (ABIST).

 

63

A ABIST structure operates in two modes: normal operation mode and test mode.
In the normal operation mode, all switches SW11’s are turned off and no test data are
sampled. In the test mode, the test data are obtained in a fashion of "parallel load and
serial pass".

During the "loading" period, all switches SW1 are turned on as shown in Figure 5.4
(a), thus the test data at the various test points are simultaneously loaded to the
corresponding holding capacitors C,- ’s. This is followed by the "serial passing" process.

For simplicity of discussion, four test points are assumed in the UUT. First, switch
SP4 is turned on and remained at the on-state in the entire process, as shown in Figure
5.4(b). The test datum held on holding capacitor C4 is passed to the terminal SO
through both voltage follower VF 4 and the output buffer VF 0,11. Secondly, switch SP3
is turned on, as shown in Figure 5.4(c), the test datum held on holding capacitor C3 is
then passed to the output. The subsequent test data are processed in the same way. The
operation is carried out continually until the test datum held in holding capacitor C 1 is
finally passed. The serial passing process is completed. The order of output sequence is
"first stage last out".

Once the "serial passing" process is completed, the entire "loading and passing"

process can then be carried out again.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5.4 Switching Operation of the ABIST Structure:
(a) Parallel Loading; (b) & (c) Serial Passing.

 

65

Figure 5.5 shows the timing diagram of the switching operation, where clock sig-
nal 60 controls all switches SW1’s and clock signal 4),- controls corresponding switch SP1,
for i =1,2, - - - ,4. respectively.

 

 

t. J— *—

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

¢4 —_
63 —1
92 i L—
11 7

 

 

 

 

 

Figure 5.5 Timing Diagram of ABIST Structure.

 

66

The clock signals can be generated by the circuit of Figure 5.6, where each stage
requires a D flip-flop and a 2-input OR gate.

 

 

 

 

 

 

I94 I93 I92 J61
“D4 Q4 D—D3 Q3 ':>_Dz Q2 .__)—Dr Q1

 

 

 

 

 

 

IQI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clerk

 

Figure 5.6 Clock Circuit.

 

It should be noted that the ABIST is self-testable by using the scan method. The
extra pin overhead of the ABIST structure is the two pins, 81 and SO. During the scan
test process, switch SWIN is turned on so that the test input signals can be applied to the
passing buffers through the terminal SI (Scan-In). From output signals observed at ter-
nrinal SO (Scan-Out), any mismatched signals indicate that faults occur in the passing

buffers.

5.3 SIMULATION AND HARDWARE IMPLEMENTATION

The circuit simulation software package PSPICE is used to simulate the ABIST
structure. For simplicity, a unity-gain op-amp model is used to simulate the voltage fol-
lower and the test point buffer. A PSPICE analog switch model is used to simulate the
analog switches. The PSPICE input data for both DC and AC cases are shown in

67

Appendix 2, and the outputs are plotted in Figure 5.7.

A prototype of a 6-stage ABIST structure using buffer amplifier HA-5002 [11] and
CMOS analog switch DG201A [41] has been implemented. In order to observe the out-
put waveforms, an oscilloscope is connected to pin S0 of the ABIST structure. Figure
5.8 displays the output waveforms of the experiments for both AC and DC analyses.

In our implementation, the output of the ABIST structure is connected to an AID
converter to record the test data for fault diagnosis use. However, the salient feature of
the ABIST structure also allows the designer to simultaneously monitor several nodes of
a circuit. In other words, the designer may use one channel of an oscilloscope to moni-
tor multiple output waveforms, as shown in Figure 5.6. Moreover, the use of the ABIST
structure for such implementation, particularly for AC analysis, may have a minor prob-
lem in phase shifting due to the clock frequency and applied frequency. More
specifically, consider an n-stage ABIST. Let f, be the applied fi'equency of the circuit
under test and fc be the clock frequency of the loading switch. The delay time T11I and

phase shifting th of kth stage input can be predicted as follows

 

 

-k l
T = ” — 5.1
d" n+1fc ( )
n-k fs
Q4, 8f. a, 21:"+1 f. ( )

Consider the output waveform of Figure 5.7(b), where f,=1kHz and fc= 40kHz,
that is tc = 25118. For a four stage ABIST structure, n=4, the delay time T4=(4—k)5m.
For example, the delay time of the second stage is T4, = 10 us. In order to illustrate the
delay time of each stage, part of Figure 5.7(b) is shown in Figure 5.7 (c). In Figure 5.7
(c), the point b is at the end of loading time of the ABIST structure, and the point b’ is
the time when the test data held in the second stage is observed at S0 pin. Therefore,

the time difference T42 = t3 - tb' = 1011s, which matchs the the results calculated by

Equation (5.1).

68

Similarly, T41=15us, T455115. and T450115. In other words, the stage that is
closest to the output pin SO has least phase shifting. In addition, Equation (5.2) shows
that the phase shifting is also dependent on the applied frequency f. and clock frequency
fc. Decreasing f, or increasing fc will decrease the phase shifting. Of course, no phase

shifting occurs in the DC case, due to f,=0.

 

 

 

 

 

 

 

 

 

 

 

 

s 00v+ ------------- + ------------- +— ------------ + ------------ + ------------- +
2 00v ' . . , . . . . . . ____§_
0 00v+ . . . . . . . . , . _ . +

(a)

Figure 5.7 PSPICE Simulation Results: (a) DC;
(b) AC; and (c) a portion of (b).
(continued on next page )

 

69

 

5.0V“

 

 

 

 

 

 

 

 

 

 

 

 

.
oovtfl -

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

\ ’ I
«XI/#3

5 k, /C 5
-S,0V+ ------------- +— ---------------- -'----+- ------------ + ------------- +

.+
Ous lOOus 200us 300us 400us SOOus

 

 

 

 

 

 

 

 

 

 

 

 

(b)
S.ov+ ------------- +- --------- 1--+ ------------- + ------------- + ------------- +

- the end of loading time

 

 

I: ' ---~: __

KR ‘ .
0 0VI E I .\I “w... Swot” I

I
j? “
l
I
I

 

 

 

 

 

 

 

 

 

.- \\ L... .5
fix— “: A-tj.
5‘18“ N

 

 

 

 

 

 

—s , 0v 1 ------------- +- ------- '33;- --+ ------------- 4- ------------ + ------------- +
120us 140us . 160us 180'us 200us 220us

(C)

Figure 5.7 ( Continued )

 

70

 

 

(b)

Figure 5.8 Observed Outputs from an Oscilloscope: (a) DC; and (b) AC.

 

71

5.4 VLSI IMPLEMENTATION
In this section, the design and layout of the two basic components, analog switches

and voltage followers, for VLSI implementations of the ABIST structure are discussed.
5.4.1 Analog Switches

Figure 5.9 shows a CMOS analog switch. It is controlled by a pair of complemen-
tary clock signals 0 and 6. When 6 is low, both transistors are off, creating an effective
open circuit. When 4) is high, both transistors are on, giving a low impedance state.
The ON resistance of the CMOS switch can be lower than lkfl while the OFF leakage
current is in the ten picoampere range. The bulk potentials of the p-channel V131: and the

n-channel VBN are taken to the highest and lowest potentials, respectively.

 

15
___T£L__.
VBP

VBN

L—jIr—
I t

Figure 5.9 CMOS Analog Switch.

 

 

 

The CMOS switch has two advantages over the sin gle-channel MOS switch . The
first advantage is that the dynamic analog-signal range in the ON state is greatly

increased. The second one is that since the n- and p-channel devices are in parallel and

“l

72

require opposing clock signals, the feedthrough due to the clock will be diminished in

some cases through cancellation.

5.4.2 Voltage Followers (VF)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8 Von
M3 :II—H ti“
In ‘#I M6
I 4 5
M1 2 2 '6
H h
J3
:11 M51 1':
M8 I 7 Ifi j M7
9 V83

Figure 5.10 CMOS Op-amp with N Channel Input.

 

Figure 5.10 shows a voltage follower that is implemented by a CMOS unity-gain
op-amp. The aspect ratios (W/L) of transistors and the capacitance are determined by
the design specification and device parameters. They can be calculated according to the
design procedure discussed in [1]. For example, consider the device parameters, as
listed in Table 5.1, and the following design specification.

A, > 4000 CL =2pF VDD=6V Vss=-6V

GB = lMHz SR = lOv/us V011, range = :l:4V

CMR = i 3V, P1113, < 10 mW, Channel length = 4.5 pm

73

Table 5.1 Device Parameters

 

 

 

 

 

 

 

Typical Parameter Value
Parameter Parameter
Symbol Description NMOS PMOS Unit
Threshold Voltage
V20 0.83 -0.89 volts
(Vbs = 0)
Transconductance
Km’ parameter 32.9 15.3 uA/voltz
(in saturation)
Bulk Threshold m
7 1.36 0.88 (volts)
parameter
Surface potential at
2 I (pp | 1 1 0.6 0.6 volts
strong mversron
LD Lateral diffusion 0.28 . 0.28 pm

 

 

 

 

 

 

 

The aspect rations (W/L) of the transistors and the compensation capacitance Cc are cal-
culated in Appendix 3, and listed in Table 5.2. The op-amp design has been simulated
by SPICE, where the SPICE input file is listed in Appendix 4. The simulation results for

input CMR, frequency response and slew rate are plotted in Figure 5.11, and also listed
in Table 5.3.

74

 

 

5..
4-
3-
2-
1_
V0111 0-
-1-
-2_
-3-
-4_.
-5-

 

 

 

N—
u.)—
4;...
Ur—
05

I
-6-5-4-3-2-101

 

 

2 -I EfrfiA—r

14

Volts 0 -I

 

 

 

 

'3 I l I

I l
0 2.5 5 7.5 10 12.5 15 17.5 20
time(11S)
(b)

 

Figure 5.11 Simulation Results: (a) Input CMR Simulation; (b) Transient Response;
(c) Magnitude Response; and ((1) Phase Response. (Continued on next page)

 

LII]

75

 

Gain

 

 

 

 

 

 

 

 

 

 

 

1.5
1
0.5—
0 l l T l l I
1 10 100 1000 10000 100000 1e+06 le+07
Frequency
(C)
180
90-1
0
-90-
“180 l r l l l I
1 10 100 1000 10000 100000 1e+06 1e+07
Frequency
(d)

Figure 5.11 (Continued ).

 

76

Table 5.2 Device Area

 

ASpect ratio (W/L) urn/um
M1,M2 4.5/4.5
M3,M4 4.5/4.5
M5 4.5/4.5
M6 20/4.5
M7 10/4.5
M8 4.5/4.5

Compensation capacitance 0.44pF

 

 

 

 

Table 5.3 Simulation Result of an Op-amp Design

 

 

Specification Design Simulation
Unity gain 1 1
Unity gain bandwidth (MHz) 1 1
Input CMR (V) 13 +5.4,-5
Slew Rate (V/IJSOC) 10 10
Pdgss (mW) <10 0.18
VDD’VSS (V) 21:6
Output resistance (Q) - 208
Input resistance (9) - 108
Load capacitance (pF) 2 2

 

 

 

 

 

Table 5.3 shows that the op-amp design has a very low output resistance (208 Q)
and a very high input resistance (1089), it is well suitable for the use of the both vol-
tage follower and test point buffer.

It should be noted that the input CMR is an important parameter for the implemen-
tation of ABIST structure. The input CMR (Common Mode Range) means that the unity

gain voltage is held within the range specified. In other words, if the input voltage is out

77

of this range, then the output voltage will not be equal the input voltage. Since the sys-
tem power supplies are :tSV, the voltages measured at various test points are also within
this range. As a result, the linearity of the input CMR insures the unity-gain of the op-
amp. However, the only drawback of this design is that the power supplies for the op-
amp are 21:6V. The use of the extra power supplies is inevitable. If we use the same
power supplies for the op-amp, i.e., :tSV, the input CMR is ranged from -4V to +4.2V,
which would loss the linearity at both ends. As an result, the measured data are inaccu-

rate.

5.4.3 Physical Layout

Figure 5.12 shows a 4-stage ABIST structure, which has been layouted using 3
micron CMOS technology. This physical layout follows the design rules supported in
Magic on SUN3 workstations.

The design began with the design of basic cells such as the CMOS op-amp and
CMOS switch. Then, an one-stage ABIST module is formed in terms of these basic
cells with necessary modification and interconnection, which is shown in Figure 5.12
(a). Finally, the 4—stage ABIST are constructed by duplicating the one-stage ABIST
module and adding the routing to I/O connection. The complete layout for 4-stage
ABIST structure is shown in Figure 5.12 (b). The total chip area is 143 A by 673 2.. The
scale factor is 1.5 um / 3», so the size is 216537 umz. The ABIST structure has not yet
been fabricated at this moment. The layout is given to show the approximate dimension

of the op-amp design.

78

 

 

(b)

(a)

Figure 5.12 The ABIST Structure (a) one-stage; and (b) 4-stage.

 

CHAPTER 6

DESIGN FOR DIAGNOSABILITY

 

Given the fact that future electronic systems will rely heavily on CAD tools to
reduce design costs, increase design accuracy, and reduce development time, it is clearly
important that testability factors be integrated into these CAD tools. Testability as it
now stands in the industry is a "bottom-up" process. Virtually, all the known techniques
need a detailed circuit design before the testability can be measured. Design, however,
is a "top down" process. A design engineer is given requirements for design, creates a
design approach, analyzes it for performance, finally is involved in structural design that
can be analyzed for testability.

For testability to become an effective part of the CAD process, the testability pro-
cess will need to become more of a top-down approach instead of a bottom-up tech-
nique. Therefore, if one can define a condition for testability which depends only on the
topological structure of the designed circuit, not on the component values, then the
design for testability can be established before analyzing the circuit performance [15,
45].

Although the proposed ABIST structure may provide as many test points as
required for a circuit under test, the number of test points should not be indefinitely
increased because of the placement and routing problems. It is necessary to select an
appropriate minimum set of test points that is sufficient to diagnose a circuit In this

chapter, based on the above testability design principle, the issues of diagnosability and

79

 

80

test set generation are addressed.

The former issue concerns the diagnosability measurement of a circuit with a given
set of test points. On the other hand, the latter issue deals with selecting an appropriate
set of test points to meet the required diagnosability. These two issues are clearly

important to the design engineers, especially for highly complex circuit designs.

6.1 DIAGNOSABILIT Y MEASUREMENT

According to the decomposition approach discussed in Chapter 4, a large network
is decomposed into smaller subnetworks and its decomposition nodes are taken as the
initial set of test points. The voltages measured at these test points are applied to check
whether or not the network is t-diagnosable. A network is said to be t-diagnosable if,
under the assumption that the network contains at most t faulty subnetworks, all the

faulty subnetworks can be located.

Let NS=(NS,°,- )nxm be a diagnostic matrix, where n and m are the numbers of

decomposition nodes and subnetworks, and each entry NS,-j is defined as follows,

1 if the jth subnetwork is connected the ith decomposition nodes
NS-- =
u 0 otherwise

Theorem 6.1 [31]

A Network is t-diagnosable if and only if the columns of matrix
D=[D 1,02, - ' ~D,]

are all distinct, where D1 = NS and D,- is a nx [fl-mauix, whose column is constructed

by logical ORing of any i columns of NS.

81

Example 6.1
Consider a network shown in Figure 6.1. The network is decomposed into 5 sub-

networks:S1,Sz,S3,S4 andSs.

 

 

Figure 6.1 The Network in Example 6.1.

 

The diagnostic matrix NS is formed as follows

51 52 53 S4 55

l 1 0 0 O 0

2 1 l 0 0 O
NS=3 1 1 0 1 0
4 0 l l O 0

5 O 1 I 1 0

6 0 0 1 0 1

7 0 0 O l l

 

 

This network is l-diagnosable, because the columns of matrix NS are all distinct.

82

Sr52535455512513514515523524525534535545
1 1 0 0 O 0 1 1 1 1 0 0 0 0 0 0
2 1 1 0 0 0 1 1 l 1 1 l 1 0 0 0

D=[Dl,Dz]=3 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 (6.1)

4 0 l l 0 0 1 1 0 0 l 1 l 1 l 0
5 0 1 l l 0 1 l 1 0 1 1 l 1 l 1
6 0 0 1 0 1 0 l O 1 l 0 l 1 l l
7 0 0 0 1 l 0 0 1 l 0 1 1 1 1 l

 

 

where Si} means S,-S,-, or logical ORing of S,- and S j. Since the columns of matrix D are

all distinct, by Theorem 6.1, the network is also 2-diagnosable.

For a given set of test points, Theorem 6.1 provides a simple way to check the
diagnosability of the circuit. In practice, however, the dimension of the matrix D is
grown with the complexity of the circuit. In order to reduce the memory space and com-

putational complexity, Theorem 6.1 is modified as follows.

Theorem 6.2
A network is t—diagnosable, :22, if and only if it is (t—1)-diagnosable and the

columns of matrix [D,_1,D,] are all distinct.

The proof of Theorem 6.2 is shown in Appendix 5. Theorem 6.2 checks the diag-

nosability recursively.

6.2 TEST POINTS SELECTION

Suppose that a t-diagnosable circuit network is designed, and the decomposition
nodes are taken as the initial set of test points. Theorem 6.2 is applied to measure the
diagnosability of this circuit, say, k-diagnosability. If k2t, then the set of test points is
sufficient to diagnose the network. On the other hand, if k <t, more test points are

needed to increase the desired diagnosability.

83

According to Theorem 6.2, a network is (lc-l)—diagnosable, but not k-diagnosable,
means that some columns of [Dk_1,Dk] are identical. Mathematically, one way to dis-
tinguish two identical columns of the matrix [Dk_1,Dk] is to add an additional row that
contains different bit patterns in these two columns. Similarly, if there are r identical
columns in that matrix, the use of q additional rows can make the identical columns all
distinct, where [ logzr'l S q S r.

In order to find the minimum set of test points, two steps of the test point selection
process are implemented: selection and compaction. The former step is to identify those
groups containing the identical columns and to add some additional rows. The latter step

is employed to compact the row patterns selected in the first step.

Example 6.1 (continued)

Using the matrix D 1, 03 is constructed as follows

F .
S123 S124 S125 S134 5135 5145 $234 $235 5245 5345

l 1 1 1 1 l 1 0 0 0 0

2 1 1 1 l 1 1 1 1 l 0
03 =3 1 1 1 1 l 1 1 1 l 1

4 l l 1 l 1 0 l 1 l l

5 1 l 1 1 1 1 1 l l 1

6 l 0 1 1 1 1 l l 1 l

7 O l 1 1 l l 1 1 1 l J

 

 

We can easily find that some columns of matrix [D 2,03] are identical. The groups of
identical columns are listed in Table 6.1. By Theorem 6.2, this implies that the network
is 2—diagnosab1e, but not 3-diagnosable.

In order to design a 3-diagnosable circuit, some additional test points are needed.
Specifically, to distinguish the identical columns in each group listed in Table 6.1, we
may simply add [ logzr ] rows to each group, where r is the number of identical
columns in that group. For instance, we may add 2 extra rows for group 3. In other
words, it requires at least 6 additional rows in this example for 3-diagnosability. How-

ever, it is possible to merge some rows to compact the test point set.

84

Table 6.1 Groups with Identical Columns in Example 6.1

 

Groups Identical columns

 

1 513.5123

2 534.5345

3 5125513415135

4 52.115234323515245

 

 

 

 

Table 6.2 Test Point Selection and Compaction

 

columns 1 2 3 4 5 group

 

51310100
$12311100

 

S34 00110

 

 

$25 0 1 o o 1
$234 0 1 1 1 o 4
$235 0 1 1 o 1
3245 o 1 o 1 1

 

 

 

 

 

A compaction step is followed. We first list the elements contained in each group
as shown in Table 6.2. In group 1, for instance, S 123 means the logical ORing of S 1 , S 2,
and S 3, we mark "1" at bits 1, 2, and 3, and "0" to others. Since the bit patterns of S 13
and S 123 are different in bit 2, hence, bit 2 can be used to distinguish these two identical

columns in Group 1. Similarly, S 125, S 134, and S 135, in Group 3, can be distinguished

"L

85

by bits 2 and 5, or bits 3 and 4, or bits 3 and 5. Therefore, the compaction problem is
turned into the following optimization problem.
. 8 .
G = Mm U{mrnG,-} (6.2)
i=1

where G, i =1,2, - - - , g, is a collection of all possible bit patterns that can distinguish all
identical columns in Group i, and min G,- is a subset of G; that contains all minimized bit
patterns. (A minimized bit pattern is the pattern that is not contained in any other pat-

terns in min G,-.) For example,

minGl={2}
min02=l51
minG3={{2,5},{3,4},{3,5}}
minG4={{3,4}]

Therefore, G = { 2, 3, 4, S }. In other words, four extra test points are needed to design

a 3-diagnosable circuit. The new matrix [02,D 3] is formed as follows,

[02.03]
512 513 514 S15 523 324 325 534 535 545 5123 Sm Sm 3134 5135 5145 5234 5235 3245 3345
1 1 l 1 l 0 0 0 0 0 0 l 1 l l l l 0 O 0 0
2 1 l l l l l l 0 0 0 l l l l l l l l l 0
3 1 l 1 l l l l 1 0 1 l l l 1 l 1 l 1 l l
4 l 1 0 0 1 1 l 1 1 0 l l 1 l l 0 l l l 1
=5 1 1 l 0 1 l l 1 l l 1 l l l 1 l l 1 1 1
6 0 l 0 l l 0 1 1 l 1 1 0 l 1 l l l l l l
7 0 0 1 l 0 l l l l 1 0 1 l 1 l l l 1 l l
a l 0 0 0 l l l 0 0 0 l l l 0 0 0 l l l 0
b 0 1 0 0 l 0 0 1 l 0 l 0 0 1 l 0 l l 0 l
C 0 0 l 0 0 1 0 1 0 l 0 l 0 1 0 1 l 0 l l
d 0 0 0 1 0 0 1 0 1 l 0 0 l 0 l l 0 l 1 l

 

where the rows a,b,c, and d are the additional test points and they are respectively
representing the elments of G. These rows are constructed as follows. For the row a, all
columns in [D 2,03] with "2" in subscripts of S are marked to "1" and others are "0".

Similarly, all columns with subscripts "3", "4", and "5" are marked to "l" to the rows

 

86

b, c, and d, respectively.
The above example shows that the circuit is 3-diagnosable if the above 4 extra test

points are added. Interestingly, with the following matrix D4,

q

S 1234 S 1235 51245 51345 52345

E

II
o—hu—tu—u—H—Av—nu—n—nc—n—t
t—IOu—th—Iu—tt—tr—bh—It—ir—I—d
u—tn—IOt—II—It—It—II—tt—tt—II—I
u—ID—IHOh-Ir—it—iI—It—It—It—I
t—n—A—iu—u—n—H—A—n—Io

 

 

R.“ 3‘8 dam-th—t

d

we also find that the network is 4—diagnosable without adding any other additional test

points.

The selection and compaction processes discussed above is summarized as follows.

Procedure Select-Compact()
Step 1. (Selection)

1.1 Identify the groups of identical columns in [Dk_1,Dk], and construct the

table as Table 6.2.

1.2 Find min G,- for each group.
Step 2. (Compaction)

2.1 Find G of (6.2). Say, G = { g1, ° ° - ,gp}

2.2 For i=1 to p

Add a TOW R; to matrix [Bk-1 ,Dk]

mark 1 to those column with subscript 3,-

Step 3. The circuit is k—diagnosable.

 

87

The entire test points selection procedure is summarized as follows.
Algorithm IV
Step 1. Construct the diagnostic matrix NS (= D 1), and set k=1.
If columns of D1 are all distinct, GOTO Step 2;
otherwise GOTO Step 3.

Step 2. (Diagnosability Measurement)

If (th) GOTO Step 4, otherwise k=k+l; and construct Dk.
If some columns of [Dk_1,Dk] are identical, GOTO Step 3;

otherwise, repeated this step.

Step 3. (Test Point Selection and Compaction )
Call procedure Select-CompactO to make the circuit k-diagnosable.
GOTO Step 2.

Step 4. The circuit is t-diagnosable.

88

Example 6.2
Figure 6.2 shows a ten band octave equalizer, where nodes 1, 3, 4, and 6 are
chosen as decomposition nodes. The circuit is decomposed into 12 subnetworks, as

shown in Figure 6.3.

 

 

 

 

 

 

 

 

 

 

 

”’VV—W—
,1.
"W
l " ‘_‘ ‘ 32Hz
—— — 64Hz
__/\ A ,_ _ # 125112
1 _ _.
O—’\/\, \ 2 3 2501-12 4
/ — — 500Hz “—0
i I — fl lkHz
:- 7 — — 2kHz _
A A A A — 4kHz
i — 8kHz

 

In} 16km

 

 

 

’V\/-‘

Figure 6.2 A Ten Band Octave Equalizer.

 

 

Figure 6.3 A Decomposition of the Octave Equalizer.

 

We first construct the NS matrix for this circuit.

S132 53 S4 55 S6 S1 58 59 S10 S11512

 

 

”5:1100000000000
2111111111110
3011111111111
4000000000001

Since columns S 2 through S 11 are identical, the circuit is not l-diagnosable. Fol-

lowing Algorithm IV, 10 extra test points are added as follows.

 

S132 53 S4 55 Se 57 58 S9 310 S11512

00110000000000

01100000000001

01100000000010

01100000000100
01100000001000
01100000010000
01100000100000
01100001000000
01100010000000
01100100000000

01101000000000

11000000000000

 

1234abcdef8hij

.-
m

Since all columns are distinct, the network is l-diagnosable. With such set of test

points, the network is also 12-diagnosable.

CHAPTER 7

CONCLUSIONS

 

This chapter summarizes the major contribution of this dissertation research and

outlines the directions for future research.

7.1 SUMMARY OF MAJOR CONTRIBUTIONS

For more than two decades, the subjects of the automatic testing and fault diagnosis
of electronic circuits have been of interest to researchers in the areas of circuits and sys-
tems. Recently, with the rapidly increasing complexity and size of modern electronic
systems, these subjects become more and more important and critical.

A fault location algorithm and an AATPG (Analog Automatic Test Program Gen-
erator) have been developed to precisely locate faults in analog circuits.

For a reliable design, potential faulty components in a system should be identified
as soon as possible and be replaced before the system fails. A fault prediction problem
has been initiated and a fault prediction algorithm has been presented, which can predict
if any of the network components is about to fail, so that the potential faulty components
can be predicted and replaced before the system actually fails.

In order to diagnose large circuit networks with reasonably high speed, a decompo-
sition approach fault prediction algorithm is proposed. The algorithm can be used
hierarchically to decompose a network into any desired level. In order to precisely

locate the faults at a specific level, it is necessary to provide sufficiently many accessible

91

92

nodes for voltage measurement. Unfortunately, modern electronic systems are often
multi-layered and/or coated, thereby limiting the accessibility of test points. It is
difficult to provide proportionately more 1/0 connections as the number of components
in a unit increases. This becomes the bottleneck of analog fault diagnosis problem.

In this dissertation, an Analog Built-In Self-Test (ABIST) structure has been pro—
posed which provides more test points while still keeping low pin overhead. It is the
first Built-In Self-Test structure for analog fault diagnosis. Included in this study are
topological structure and operation of the ABIST structure, simulation results and a
hardware implementation indicating the principle works well, and the design and simu-
lation of the basic ABIST components. A detailed layout of the structure has been done
using 3 micron CMOS technology. The ABIST structure can be used to acquire test
data at various test points simultaneously, a very important requirement for diagnosis. In
addition to the fault diagnosis use, the proposed ABIST structure also allows system
designers to use one channel of an oscilloscope to simultaneously monitor multiple out-
put waveforms of a circuit or system.

Although the proposed ABIST structure may provide as many test points as
required for a circuit under test, the number of test points should not be indefinitely
increased because of the placement and routing problems. It is necessary to select an
appropriate minimum set of test points that is sufficient to diagnose a circuit. Therefore,
an efficient algorithm to select test points for the design of a t-diagnosable network has
been proposed.

In summary, this dissertation focuses on fault prediction and diagnosis in large cir-
cuit networks. It is novel in the sense that it is the first analog BIST structure ever pro-
posed for analog fault diagnosis. This structure will be very helpful in developing

efficient and practical fault diagnosis algorithms for large circuit networks.

93

7.2 DIRECTIONS FOR FUTURE RESEARCH
Some practical issues in analog fault diagnosis are addressed here for further study.
7.2.1 Automatic Testing and Diagnosis

In this dissertation, an ABIST structure and an AATPG software package have
been presented. However, the development of an Automatic Test Equipment (ATE)
[24], required for automatic testing and diagnosis, has not yet been discussed. Basically,
the functions that can be performed by the ATE include (1) supply test stimuli; (2)
obtain output response; and (3) diagnose faults. A block diagram of an ATE system is
shown in Figure 7 .1. A microprocessor acts as the center of the ATE, which controls the
stimulus unit to stimuli the input signal to UUT and sends a clock signal to the clock cir-
cuit in order to form a set of proper clock signals to control analog switches of the
ABIST structure. The analog test data acquired from pin SO of the ABIST structure are
first converted to digital signals by the A/D converter, which are then sent to the
microprocesser and transferred as the input data of AATPG software package [16, 17,
18]. AATPG is used to diagnose faults.

7.2.2 Time Domain Analysis

The proposed AATPG software package can handle both DC and AC analysis for
linear circuits very well. For nonlinear circuits, however, the SPICE is employed to
handle the transient analysis in time domain. In practice, it is difficult to directly send
test data to the SPICE program at every time step. This poses an interesting research
topic for either developing a transient analysis program for time domain, or modifying

SPICE by adding an interface program.
7.2.3 Fault Diagnosis for Analog/Digital Hybrid Circuit

Typically, a practical circuit may consist of both analog and digital components.

Several fault diagnosis algorithms for digital circuit, or analog circuits, have been

94

 

 

 

AATPG

 

 

 

 

 

 

 

 

 

 

 

Stimulus

SI

 

Microprocessor

 

Output

 

 

 

 

 

 

 

Clock
Circuit

 

 

 

 

 

 

 

 

 

 

PI

 

BIST
Structure

SO

 

 

 

 

 

 

 

 

 

 

Figure 7.1 A Block Diagram of ATE.

 

UUT

 

 

 

 

 

 

 

95

developed, but, there are no general methods available for fault diagnosis of
analog/digital hybrid circuit [35]. Since the proposed ABIST structure provides the pos-
sibility to acquire test data for the analog/digital hybrid circuit, the structure will be very
helpful to develop an efficient fault diagnosis algorithm for the analog/digital hybrid cir-

cuit.
7.2.4 BIST Implementation

Unlike the digital BIST structure used to input test patterns and acquire output
responses, the proposed ABIST is only employed to acquire test data. In some analog
diagnosis algorithms, applying external excitation to some test points is required. In that
case, the proposed ABIST structure can be modified to apply the required excitation.

According to the switching operation of the proposed ABIST structure shown in
Figure 6.4, the datum holding at first stage of the buffers will be passed out last. As a
result, the capacitance required in that stage must be sufficient enough to hold the datum
before it is passed out. In other words, the greater thenumber of stages, the greater the
capacitance that must be designed. However, the greater capacitance requires more chip
area. For this reason, it is necessary to provide a precise measurement as a criterion to
determine the number of stages.

In practice, it is possible to lower the capacitance by reducing the number of stages.
This can be accomplished by using more scan out pins. The structure is suggested in
Figure 7.2, where each lane has its own scan out pin and connects to an A/D converter.

There is a trade-off between the chip area and pin overhead.

‘

96

 

SI

 

 

 

 

$01

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ABIST1 ‘ A ID —°
503 o
ABISTZ A ID
so
ABIST" —“1 A /D —°

 

 

Figure 7.2 ABIST array.

 

 

 

 

APPENDICES

APPENDIX 1

Equivalent Fault Set

 

Property 2.1
If the actual fault set contains a subset consisting of either
a) I components in loop L which consists of I +1 components, or
b) I components in cutset C which consists of [+1 components incident to an inacces-
sible node,
then an f-component-set formed by a combination of any I components of loop L or
cutset C together with other f -1 components of the actual fault set, is an equivalent fault

SCI.

Proof: a) Assume that components of the actual fault set are numbered as
(1,2, - - ° ,I,q, - ~ - ,f), where the faulty components, 1,2, . - - , and I are in loop L which
consists of I +1 components, the other faulty components are not in this loop. For a

actual fault set, we have

FA A A A A .-
vgn ,rl) ,5» ,9) v?)

Wf(act) = (1)

 

 

,3.) .:. ,5.) .:. ,4., .:. ,4..

According to KVL, in a loop L,

1+1 .
Emu-=0, where ki=i1.
'=l

One of the component voltages is the linear combination of other I component voltages,
97

98

thatis
A 1 1+1 .
vj=-—— z kivi, where j=1,2,~-,l+1. (2)
k1“ i=1,i¢j

Substituting equation (2) for {3,- in equation (1)

 

 

Par «1 1"“1 «1 .1 Ar .1 «1‘
v3) v§_)1__:_ 2 kwi’ V§+)1 v3) v5?) Vi)
Ji=1,i¢j
Wf(act)=
~(m) ~<m) 1 ”'1 «m «(m) “Y” 4m) ~(m)
v1 v1-1 -f 2 kiv, vj+1 v vq vf
Ji=1.i¢j

Through I times column basic transformation, we get

”at ~1 ~1 «1 .1 ~1 al‘
,3) v§31 ,531 ,g) V531 ,3) ,0

II
S.

 

9(1'") {3m 95.3] W") {.533 93") 95:")

 

and
rank[Wfl AP] = rank[Wf(ac,) IAP]

Since AP is a linear combination of all columns of Wm“), and WHO“) is
equivalent to Wj , thus AP is also linear combination of all columns of W}. This implies
that

rank [wjl AP] = ranktWI] =f
b) According to the KCL, in a cutset C which incident to an inaccessible node,
1+1 ..

2k;i,-=O, where k;=i1.
.___1

Assume i =vg, then

(+1
2k;g,-v,~=0, where ki=i'1.

i=1

99

One of the component voltages is the linear combination of other I component voltages,

that is
A 1 1+1 A
Vj =-— 2 kigivi, where j=1,2, ' ' ' ,I+1.
kigj i=l.i¢j

Through a similar deriving as that in (a), we get

rank[W}I AP] = rankmfl = f

Property 2.2
If m—f +1 row dependence of Wf is consistent with row dependence of Wm”), and

rank[Wf] = f, the f-component-set corresponding to Wf is an equivalent fault set.

Proof: Assume that the first row of Wflm) is linearly dependent on the last m—f

rows, we have

 

 

I W510) wg) w}? '
W = W551) wg) . Wig)
“ac” kiwila) krwgr) ' MW}?

km—fWS‘a’ km—fWS‘a’ km-fw I.)

In the actual fault set, we know

f (1)
Apt = 2W”: Ax}
i=1

and then

f (M) f (1) f (I) .
Apf+i= 2W” AXj= 2km” AXj=ngWJa AXj=kiAph where 1:1,2, -°-,m—f.
i=1 i=1 i=1

Therefore,

AP=IAP1,AP2. °°°,Apf.k1AP1.”°km-fAP1]T

100

As the given condition, m-f +1 row dependence of Wf is consistent with row

dependence of Wf(ac,), then:

 

 

I wg) wg) “’5‘” Apr
WV) wg) . w )
WIN’: 1) 1) . Y1) f
kiwi krwi krW} krAPI
k...fwl" Jews” k...fw}" km.pr1

Through m—f times basic transformation, we have
twp) wg) . . . WI” Apr“

WY) Wg) . wy)Apf
WfAP: o o - 0 o

 

 

0 O'HO 0

Thus, rankaAP = f. Also, as the given condition ranka = f, we have
rank[WfAP] = ranka = f.

' 1.

APPENDIX 2

PSPICE Code for ABIST Simulation

 

"I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

.J

 

 

it)
II
V
p—t
: +
C

O

r.

I

I

I

I

l

I

L__--
I||——

I

   

 

 

Figure a.1 Unity-gain Opamp Micromodel

A Four Stage ABIST Structure in DC
.probe

vc 5 O 0 pulse(0 5 0.01u 0.01u 0.01u 4.9u 25u)
re 5 O IOOmeg

v0 4 0 2V

x0 1 2 opamp

x10 4 3 opamp

sO 1 3 5 0 on

00 1 0 5p

*

v1 14 O 4v

x1 11 12 opamp

x11 14 13 opamp

$1 11 13 5 0 on

c1110 5p
101

 

102

$11 2 11 16 O on

vol 16 0 0 pulse ( O 5 20u 0.01u 0.01u 4.9u 25u)
ml 160 lOOmeg

a.

v2 24 0 -IV

x2 21 22 opamp

x12 24 23 opamp

$2 21 23 5 O on

c2 21 0 5p

s12 12 2126 0 on

vc2 26 O 0 pulse ( 0 5 15u 0.01u 0.01u 9.9u 25u)
rc2 26 O 100meg

a.

v3 34 0 3V

x3 31 32 opamp

x13 34 33 opamp

$3 31 33 5 O on

c3 31 0 5p

313 22 3136 0 on

v03 36 O 0 pulse ( O 5 lOu 0.01u 0.01u 14.9u 25u)
r03 36 0 100meg

1.

x4 41 42 opamp

$14 32 41 46 0 on

vc4 46 O 0 pulse ( O 5 Su 0.01u 0.01u 19.9u 25u)
rc4 46 O IOOmeg

r142 O IOmeg

a.

.subckt opamp 1 2

i1 1 0 1p

ea 2 0 1 O 1

.ends

103

*

model on vswitch (ron=1m roff=100meg von=4.9 voff=0. 1)
.tran lu 50u
.print tran v(42)

.end

A Four Stage ABIST Structure in AC

.probe

vc 5 0 0 pulse(0 5 0.01u 0.01u 0.01u 4.9u 25u)
re 5 0 lOOmeg

v040sin (022000)

x0 1 2 opamp

x10 4 3 opamp

s0 1 3 5 0 on

c0 1 0 5p

1.

v1 140sin (0520000090)

x1 11 12 opamp

x11 14 13 opamp

$1 11 13 5 0 on

c1 11 0 5p

81] 2 11 16 0 on

vcl 16 0 0 pulse ( 0 5 20u 0.01u 0.01u 4.9u 25u)
rcl l6 0 lOOmeg

II!

v2 2403in (0220000045)

x2 21 22 opamp

x12 24 23 opamp

32 21 23 5 0 on

c2 21 0 5p

51212 2126 0 on

vc2 26 0 0 pulse ( 0 5 15u 0.01u 0.01u 9.9u 25u)

104

rc2 26 0 lOOmeg

*

v3 34 0 sin (0 4 2000 0 0135)

x3 31 32 opamp

x13 34 33 opamp

S3 31 33 5 0 on

c3 31 0 5p

$13 22 3136 0 on

vc3 36 0 0 pulse ( 0 5 1011 0.01u 0.01u 14.9u 25u)
r03 36 0 lOOmeg

g.

x4 41 42 opamp

s14 32 4146 0 on

v04 46 O 0 pulse ( 0 5 Su 0.01u 0.01u 19.9u 25u)
r04 46 0 lOOmeg

r142 0 lOmeg

at

.subckt opamp 1 2

i1 1 0 1p

ea 2 0 l 0 1

.ends

1.

.model on vswitch (ron=1m roff=100meg von=4.9 voff=0.1)
.tran lu 500a

.opfioniflS=0

.end

APPENDIX 3

Design Procedure of a CMOS Opamp

 

Using the material and device parameter given in Table 5.1, according to the
design procedure discussed in [1], design an amplifier similar to that shown in Figure
5.10 that meets the following specifications

Av > 4000 CL =2pF VDD=6V VSS=-6V

GB = lMHz SR = 10v/tts Vow range = i4V

CMR = i 3V, Pd“, < 10 mW, Channel length =-4.5 mm

1. Calculate the minimum value of the compensation capacitor Cc

Cc > 0.2ch = (2.2/10)(2pF) = 0.44pF

2. Determine the minimum value for the "tail current" (15) from the slew-rate

specification and Cc

15 = SRch = (0.44x10‘12)(10x106) = 4.41m

3. Design for (W/L)3 from the maximum input voltage specification

15

(W/L)3 = . 2
K 3 [Von-Vin (max )- | VT03 ' (max HVn (mm)]

 

4.4x10‘6

= =0.033
(15.3x10‘6)(6—3—0.89+0.83)2

 

105

106

Design for (W/L); to achieve the desired GB
gm 2 = GB ch = (2)(3.14)(1x106)(0.44x10’12) = 2.765uS

83.2 _ (2.765x10’6)2

_ = .053
kzls (32.9x10‘6)(4.4x10'6)

 

(W/L)2 =

Design for (W /L)5 from minimum input voltage. First calculate VDss(sat) then find

(W/L)5

0.5
. 15
VvdS = Vin (mm )-Vss- [KI "VTI (max)

4.4x1o-6
(32.9x10‘6)(0.053)

 

1/2
= (-3)-(-6)- [ ] -0.83 =0.581

Using V055 calculate (W /L)5

215 1— 2(4.4x1o-6) =
K5[VDss(sat)]2 (32.9x10’6)(0.5812) °

 

 

(W/L)5 =

Find (W/L)5 by letting the second pole (p2) be equal to 2.2 times GB. Assume that

VDS6 = VDso(Sat) = VDD - Vout(max)
gm; = 2.2gm2(CL/Cc) = 2.2(2.765x10‘6)(2/0.44)=27.65u./S

gm6 _ 27.65x10’6

W/L = _ = .
( )6 KsVos6(sat) (15.3x10'6)(1)

 

 

Calculate I 5

 

2 —62
80:6 _ (27.65x10 ) —13~8I1A

I = - —
6 2K6(W/L)5 (2)(15.3x105)(1.81)

Design (W /L)7 to achieve the desired current ratios between I 5 and 16

13.8x10‘6
W/L = I /I W/L =0.792———-=2.484
( )7 (6 s)( )5 4.4x10‘6

107

9. In the final step, find W from W/L ratio. Therefore, we have
W1=W2=4.5um
W3=W4=4.5um
W5=4.5um
W6=1.81(4.5—0.28x2)=7.13um

W7=2.484(4.5-0.28x2)=9.79um

10. Readjust W5 for proper balance.

2W7 W6 th W 10 2.20
W5 W4 en 6 11m

APPENDIX 4

SPICE Code for CMOS Opamp

 

CMOS Op-amp Circuit

.width out=80

vin+ 1 0 0 ac 1 pulse(-2 2 Su 0.1u 0.1u 10u)

vdd 4 0 dc 6

vss 0 5 do 6

c1 3 0 2p

x1 1 3 3 4 5 opamp

.subckt opamp 1 2 6 8 9

m1 4 2 3 3 nmosl w=4.5u1=4.5u

m2 5 1 3 3 nmosl w=4.5u1=4.5u

m3 4 4 8 8 pmosl w=4.5u l=4.5u

m4 5 4 8 8 pmosl w=4.5u1=4.5u

m5 3 7 9 9 nmosl w=4.5u1=4.5u

m6 6 5 8 8 pmosl w=20u l=4.5u

m7 6 7 9 9 nmosl w=10u1=4.5u

m8 7 7 9 9 nmosl w=4.5u l=4.5u

cc 5 6 0.44p

ibias 8 7 4.4u

.model nmosl nmos level=2 ld=0.28u tox=50n nsub=1e16

+ vto=0.827125 kp=32.86649u gamma=1.35960 phi=0.6 uo=200.00
+ uexp=l.001m ucrit=999000 delta=l.24050 vmax=100000. xj=0.4u
+ lambda=0.01604983 nfs=1.234795e+12 neff=1.001e-2 nss=0. tpg=l.
+ rsh=25 mj=0.5 mjsw=0.33 cgso=520p cgdo=520p cj=320u cjsw=900p

108

109

.model pmosl pmos level=2 ld=0.28u tox=50n nsub=1.121088e14

+ vto=-0.894654 kp=15.26452u gamma=0.879003 phi=0.6 uo=100.00
+ uexp=0.153441 ucrit=16376.5 delta=1.93831 vmax=100000. xj=0.4u
+1ambda=0.04708659 nfs=8.788617e+11 neff=1.001e-2 nss=0. tpg=-1.
+ rsh=95 mj=0.5 mjsw=0.33 cgso=400p cgdo=400p cj=200u cjsw=450p
.ends

.op

.options limpts=501

.tf v(3) vin+

.dc vin+ -6 6 0.2

.ac dec 10 1 lOmeg

.trans 0.1u 20u

.print trans v(l) v(3)

.print dc v(3)

.print ac vm(3) vp(3)

.end

APPENDIX 5

Diagnosability Measurement

 

Theorem 6.2
A network is t-diagnosable, :22, if and only if it is (t-1)-diagnosable and the

columns of matrix [D,_1,D,] are all distinct.

Lemma 6.1
If the columns of [D 1,02] are all distinct, and the columns of [D 2,0 3] are also all

distinct, then the columns of [D 1,0 3] are also all distinct.

Proof: Let c,- and cm be any columns of DI and D 3, respectively, and Cg be a column
of Dz. We claim that c,- is distinct to cm. Assume that they are identical, i.e., ci=cju.
This implies that for every element t, c5 = c574 =x, where x can be either 0 or 1. Two
cases can be identified. Case 1, Ifx=1, then cf,- = cf + cj- =1 =x, i.e. cf = “ii; and Case 2,
if x=0, then 05-“ = cj- + cfc +cf=0 => cj-=0 =x = cf]. Both two cases conclude that cf = cf,-
for every t, or c,- = 6,3, which contradicts to the fact that the columns of [D 1,02] are all

distinct. Therefore, any“, or columns of [D 1,0 3] are all distinct.

Lemma 6.2
If the columns of [D,-1,D,] are all distinct and the columns of [D,-,D,_1], for i<t,
are also all distinct, then the columns of [D;,D,] are all distinct.

Proof: The proof is similar to Lemma 6.1.

110

111

Proof of Theorem 62: If network N is t-diagnosable, by Theorem 6.1, the columns of
D=[D1,Dz, ° ' - D,__1,D,] are all distinct. This implies that the columns of
[D 1, - - - ,D,_1] are all distinct and the columns of [D,_1,D,] are also all distinct. Again,
by Theorem 6.1, the former implies that the network is (t—1)-diagnosable.

On the other hand, if the network is (t—1)-diagnosable, then columns of
[01, - - - ,D,_1] are all distinct. This implies that the columns of [D,-,D,_1] , for i<t-1,
are also all distinct. Further, since the columns of [D,_1,D,] are known to be all distinct,
by Lemma 6.2 the columns of [D,-,D,], for i<t are all also distinct. In the other words,

the columns of D=[D 1 , - ’ - ,D,_1,D,] are all distinct. This results that the network is t-

diagnosable.

BIBLIOGRAPHY

BIBLIOGRAPHY

 

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

Allen, RE. and DR. Holberg, CMOS Analog Circuit Design, Holt, Rinehart and
Winston, Inc., New York, NY., 1987.

Allen, R. J ., "Fault Prediction Employing Continuous Monitoring Techniques,"
IEEE Trans. on Aerosp. Support Conf. Procedures, Vol. AS-l, pp. 924930, 1963.

Bandler, J. W. and A. E. Salama, "Fault Diagnosis of Analog Circuit," IEEE
Proceedings, Vol. 73, No. 8, pp.1279-1325, Aug. 1985.

Bennetts, R. 6., Design of Testable Logic Circuits, Addison-Wesley Publishing
Company, 1984.

Berkowitz, R. 8., "Conditions for Network-Element-Value Solvability," IRE Trans.
Circuit Theory, Vol. CI'-9, pp. 24-29, Jan. 1962.

Biernacke, R. M. and J. W. Bandler, "Multi-fault Location in Analog Circuits,"
IEEE Tans. on Circuits and Systems, ms, Vol. CAS-28, No. 5, pp.361-3666, May
1981.

Chua, L. O, and P. M. Lin, Computer-Aided Analysis of Electronic Circuits: Algo-
rithm and Computational Techniques, Prentice-Hall, 1975.

Duhamel, P. and J. C. Rault, "Automatic Test Generation Techniques for Analog
Circuits and Systems: A Review," IEEE Trans. Circuits and Systems, Vol. GAS-26,
pp. 411-440, July 1979.

Greenbaum, J. R., L. Besser, B. Biehl, B. D. Pollard and R. Osann, Analysis and
Design of Electronic Circuits using PCs, Van Nostrand Reinhold Company, New
York, 1988.

[10] Gupta, H., Bandler, J.W., Starzyk, J.A., and J. Sharma, "A Hierarchical Decompo-

sition Approach for Network Analysis," Proc. of IEEE International Symp. on Cir-
cuits and Systems, Rome, Italy, pp.643-646, 1982.

112

113

[11] Harris Incorporation, Analog Product Data Book, 1986.

[12] Hochwald, W. and J. D. Bastian, " A dc Approach for Analog Fault Dictionary
Determination," IEEE Trans. Circuits and Systems, Vol. CAS-26, pp. 523-529,
July 1979.

[13] Huang, T. S. and R .R Parker, "Network Theory: an Introductory Course",
Addison-Wesley, 1971.

[14] Huang, Z. F. and R. Liu, "Analog Fault Diagnosis with Tolerance," Proc. 1986
IEEE Int. Symp. on CAS, San Jose, CA. PP. 1332-1335, May 1986.

[15] Huang, Z. F. , C. S. Lin and R. Liu, "Node-Fault Diagnosis and a Design of Testa-
bility," IEEE Trans. on Circuits and Systems, Vol. GAS-30, No. 5, pp. 257-265,
May 1983.

[16] Jaeger, R. C., "Tutorial: Analog Data Acquisition Technology, Part II Analog-to-
Digital Conversion," IEEE Micro, pp. 46-56, Aug. 1982.

[17] Jaeger, R. C., "Tutorial: Analog Data Acquisition Technology, Part 111 Sample-
and-holds, Instrumentation Amplifiers, and Analog Multiplexers," IEEE Micro, pp.
20-36, Nov. 1982. I

[18] Jaeger, R. C., "Tutorial: Analog Data Acquisition Technology, Part IV System
Design, Analysis, and Performance," IEEE Micro, pp. 52-60, Feb. 1983.

[19] Jiang B. L. and L. J. Fan, "Multiple-fault Diagnosis of Analog Circuit with InacCes-
sible Nodes," Proc. 27th Midwest Symp. on Circuits and Systems, West Virginia
pp. 626-631, June 1984.

[20] Jiang, B. L. and C. L. Wey, "Multiple Fault Diagnosis with Failure Bound for Ana-
log Circuits," Proc. 1986 IEEE Int. Symp. on Circuits and Systems, San Jose, CA,
pp. 1261-1264, May 1986.

[21] Jiang, B. L., C .L. Wey and L. J. Fan, "Fault Prediction for Analog Circuits," Jour-
nal of Circuits, Systems and Signal Processing, Vol. 7, No. 1, pp. 95-109, Jan.
1988.

[22] Jiang, B. L. and C. L. Wey, "Fault Prediction Precess for Large Analog Circuit
Networks," International Journal of Circuit Theory and Applications, Vol. 17, No.
2. PP. 141-149, April 1989.

114

[23] Jiang, B. L., AATPG User Manual, Dept. of Electrical Engineering, Michigan
State University, 1989.

[24] Liguori, F ., Editor, Automatic test Equipment: Hardware, Software, and Manage-
ment,, IEEE Press, New York, 1974.

[25] Liu, R., Analog Fault Diagnosis, IEEE, PRESS, 1987.

[26] Liu, R., C. S. Lin, Z.F. Huang and L. Z. Hu, "Analog Fault Diagnosis: a New Cir-
cuit Theory," Proc. 1983 IEEE int. Symp. Circuits and Systems, Newport Beach,
CA. Pp. 931-939, May 1983.

[27] McCluskey, E. J., "Built-In Self-Test Technique," IEEE Design and Test of Com-
puters, Vol. 2, No.2, pp. 21-28, April 1985.

[28] McCluskey, E. J., "Built-In Self-Test Structures," IEEE Design and Test of Com-
puters, Vol.2, No.2, pp. 29-36, April 1985.

[29] Milor, L. and V. Visvanathan, "Efficient GOING-GO Testing for Analog Circuits,"
Proc. of IEEE 1987 Int. Symp. on Circuits and Systems, Philadephia, PA, pp. 414—
417, May 1987.

[30] Nagel, L. W., "SPICEZ: A Computer Program to Simulate Semiconductor Cir-
cuits," Univ. of California, Berkeley, 1975.

[31] Ozawa, T., J.W. Bandler, and A. E. Salama, "Diagnosability in the Decomposition
Approach for Fault Location in Large Analog Network," IEEE Trans. on Circuits
and Systems, Vol. OAS-32, No.4, pp. 415-416, April 1984.

[32] Plice, W. A., "Automatic Analog Testing -1979 Style," Computer, pp. 40—47, Oct.
1979.

[33] Plice, W.A.', "Overview of Current Automated Analog Test Design," IEEE Test
Conference, Cherry Hill, New Jersey, pp. 128-136, 1979.

[34] Rapisarda, L. and R. DeCarlo, "Analog Multifrequency Fault Diagnosis," IEEE
Trans. on Circuits and Systems, Vol. CAS-30, pp. 223-234, 1983.

[35] Reisig, D. and R. DeCarlo, "A Method of Analog-Digital Multiple Fault Diag-
nosis," Int. Journal of Circuit Theory an Applications, Vol. 15, pp. 1-22, April,
1987.

115

[36] Sacks, R., "Criteria for Analog Fault Diagnosis," in Nonlinear Fault Analysis,
Technical report. Texas Tech U., Lubbock, Texas, pp.19-28.

[37] Sacks. R., "An Experiment in Fault Prediction," Proc. 1976 Autotestcon, Arlington,
TX., pp. 53, Nov. 1976.

[38] Sacks. R. , and S. R. Liberty, Rational Fault Analysis Marcel Dekker, 1977.
[39] Salama, A. E., J. A. Starzyk and J. W. Bandler, "A Unified Decomposition

Approach for Fault Location in Large Analog Circuits," IEEE Trans. on Circuits
and Systems, Vol. CAS-31, No.7, pp. 609-622, July 1984.

[40] Sen, N. and R. Sacks, "Fault Diagnosis for Linear System via Multifrequency
Measurements," IEEE Trans. on Circuits and Systems, Vol. CAS-26, pp. 457-465,
1979.

[41] Siliconix Incorporated, Integrated Circuit Data Book, 1988.

[42] Starzyk, J. A. and H. Dai, "Multifrequency Measurement of Testability in Analog
Circuits," Proc. 1987 IEEE int. Symp. Circuits and Systems, Philadelphia, PA, pp.
884-887, 1987.

[43] Trick T, N. , w. Mayeda, and A. A. Sakla, "Calculation of Parameter Values from
Node Voltage Measurements," IEEE Trans. Circuits and Systems, Vol. CAS-26,
pp. 440-457, 1979.

[44] Tsui, F.F., LSI/VLSI Testability Design, McGraw-Hill, 1986.

[45] Wey, C. L., "Design for Testability for Analogue Fault Diagnosis," International
Journal of Circuit Theon and Applications, Vol. 15 , pp. 123-142, April, 1987.

[46] Wey, C.L., B.L. Jiang and G. Wierzba, "Built-In Self-Test for Analog Circuit Net-
works," Proc. 31th Midwest Symp. on Circuits and Systems, St. Louis, MO. August
1988.

[47] Wey, C.L., B.L. Jiang and G. Wierzba, "Built-In Self-Test (BIST) Design of
Large-Scale Analog Circuit Networks," Proc. IEEE Int. Symp. on Circuits and Sys-
tems, Portland, OR. May 1989.

[48] Wey, C. L. and R. Sacks, "On the Implementation of Analog ATPG: The Linear
Case," IEEE Trans. on Instrumentation and Measurement, Vol. IM-34, pp. 442-
449, September, 1985.

116

[49] Wey, C. L. and R. Saeks, "On the Implementation of Analog ATPG: The Nonlinear
Case," IEEE Trans. on Instrumentation and Measurement, Vol. IM, pp. 442-449,
June,1988.

[50] Wu, C.-c., K. Nakajima, C. L. Wey, and R. Sacks, "Analog Fault Diagnosis with
Failure Bounds," IEEE Trans. on Circuits and Systems, Vol. CAS-29, No.5, pp.
277-284, May, 1982.

   

HICHIGAN STATE UNIV. LIBRARIES
IIIllWIIIIWIWWIUIIHIVIIWIIIIHIWIWUI
31293006024453