llll”Ill'llllllHlllllllUlllllllllllIllllllllllllllllll 300794 5201 This is to certify that the thesis entitled Test Generation and Concurrent Error Detection for Current-mode A/D Converters presented by Sondes Sahli has been accepted towards fulfillment of the requirements for Master Q: Science degree in Electrical Engineering 424% [Jr Major professor QM? [$1, 9; 0-7639 MS U is an Affirmative Action/Equal Opportunity Institution l’ "\ LIBRARY Michigan State 1 University PLACE IN RETURN BOX to remove this checkout from your record. TO AVOID FINES return on or before date due. DATE DUE DATE DUE DATE DUE Jl I __l JL _JL =7l== MSU Is An Affirmative Action/Equal Opportunity lnstltution chS-pd TEST GENERATION AND CONCURRENT ERROR DETECTION IN CURRENT-MODE AID CONVERTERS By Sondes Sahli A THESIS Submitted to Michigan State University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE Department of Electrical Engineering 1 992 ABSTRACT TEST GENERATION AND CONCURRENT ERROR DETECTION IN CURRENT-MODE AID CONVERTERS BY Sondes Sahli Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or self-calibrating tech- niques have been employed in Analog-to-Digital (AID) converters to eliminate errors caused by offset and low frequency noise, and to cancel switching error effects and non- linearities. For real-time applications, however, it is rather difficult to achieve validation of the converted data in the presence of faulty switching element(s). In this thesis, the effects of stuck-at-ON/OFF faults on the switching elements of a current-mode AID converter are demonstrated, and the generation of test patterns for such a circuit is also addressed. Results show that the converter achieves full testability with two test currents. In addition, the AID converter can be enhanced with concurrent error detection capability for real time applica- tions. To my parents Habiba Boumaiza and Mohamed Cherzf Sahli, my brothers Montassar, Nizar and Ahmed and my sister Sonia. iii ACKNOWLEDGEMENTS First I would like to thank Allah (SWT) for providing me with the ability to complete this work. I would like to thank Professor Chin-Long Wey, my thesis advisor, for his valu- able inspiration and guidance. 1 would like to thank my friend Shoba for her continua] sup- port and help. I am in debt towards my country, Tunisia, for providing me with the necessary sup— port to get both my Bachelor and Master degrees. I am very grateful for my parents for their years of concern and patience and to my sister and brothers for their encouragement. iv TABLE OF CONTENTS List of Tables List of Figures Chapter One Introduction 1.1 Motivation 1.2 Problem Statement 1.3 Thesis Organization Chapter Two Background 2.1 Design 2. 1.1 Conversion Principle 2.1.2 Conversion Techniques 2.1.2.1 High-Speed AID Converters 2.1.2.2 Medium-Speed AID Converters 2.1.2.3 Low-Speed AID Converters 2.1.3 Converter technologies / Converter Microcircuit 2.1.3.1 Discrete Component Converters 2.1.3.2 Hybrid Converters 2.1.3.3 Monolithic Converters 2.1.4 Solutions to Some Limitations on the Performance of AIDS 2.1.4.1 Voltage-Mode AIDs 2.1.4.2 Current-Mode A/Ds 2.2 Testing and Verification 2.2.1 Testing Techniques 2.2.2 Test Generation 2.3 Testing of AID Converters viii ©©\IO\O\MAN NNNNNNNNNNNt—‘H WQOGMMUJt—‘OOOQN 2.3.1 Functional and Parametric Testing 2.3.2 Fault Testing 2.3.3 Concurrent Error Detection Chapter Three Current Mode AID Converters 3.1 Current Copiers 3.2 Current Matching AID Converter Design and Operation 3.3 CMOS Current Copier 3.4 Summary Chapter Four Test Generation and Concurrent Error Detection 4.1 Fault Model and Fault Effects 4.1.1 Type 1 Fault Effect 4.1.2 Type 2 Fault Effect 4.1.3 Type 3 Fault Effect 4.2 Test Generation and Fault Coverage 4.3 Concurrent Error Detection 4.3.1 Proposed Concurrent Error Detectable A/D Converter Design and Operation 4.3.2 Fault Model and Fault Effects 4.3.2.1 Type 1 Errors 4.3.2.2 Type 2 Errors 4.3.2.3 Type 3 Errors 4.3.2.4 Type 4 Errors 4.3.3 Fault Coverage Chapter Five Conclusions 5.1 Summary of Major Contributions 5.2 Directions for Future Developments List of References vi 29 30 30 33 35 35 39 45 45 46 47 47 48 50 50 52 55 56 57 59 61 63 63 64 65 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 4.5 LIST OF TABLES Type 1 Errors - DliD'z V IIN =>Definitely detectable Type 2 Errors - D1=Dz V IIN => Definitely undetectable Type 3 Errors - D1 correct or D1¢Dz => Fault secure Type 4 Errors - Random data => Most likely detectable Concurrent Error Detection vii 56 57 59 60 61 Figure 1.1 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 4.1 Figure 4.2 LIST OF FIGURES Testing of the AID Converter Ideal Transfer Characteristic in a 3-bit AID Converter Block Diagram of a Flash AID Converter Block Diagram of a Time Interleaved AID Converter Block Diagram of Subranging AID Converter Block Diagram of a Pipelined A/D Converter (a) Block Diagram of a Successive-Approximation AID Converter (b) Exemplary Voltage Waveform Illustrating the Operation Principle Block Diagram of a Interpolative AID Converter The Concept of Time Redundancy Current Copiers (a) NMOS Copier (b) PMOS Copier (c) NMOS Copier with Op. Amp. Current-Mode AID Converter (a) Schematic Diagram (b) Switching Sequence A Simple Current Comparator Modified Current-Mode AID Converter CMOS Copier Where Iin = Idn - Idp (a) Pspice Output (b) Experimental Output CED Structure With AL Implementation Proposed Current-Mode AID Converter With CED Design (a) Schematic Diagram (b) Switching Sequence viii 11 ll 13 14 19 31 34 36 38 38 40 43 51 53 CHAPTER ONE INTRODUCTION After the recent progress in digital signal processing, there has been a trend towards an “all-digital” realization of devices and systems. Historically, the field of data conversion emerged from two sources: the interest in coding and decoding techniques primarily for telephone communication and the development of low cost digital computing power [1]. Today, conversion systems include circuits and systems that interface between the analog world and the digital world of communication, processing, storage and display. The field of signal conversion encompasses a broad range of disciplines including sampled data theory, communication theory, noise theory, probability theory, numerical analysis, process manufacturing, instrumentation testing, etc. A conversion system in- volves numerous components such as sensors, operational amplifiers, isolators, sample and hold circuits, comparators, power supplies, analog-to-digital (AID) converters, digital-to- analog (D/A) converters, etc. Among the critical properties to be considered when design- ing a data conversion system are resolution, accuracy, sampling rate, throughput, signal conditioning, intended disposition of the converted data, level of the system user, cost, dy- namic range, environment conditions, tolerated level of complexity and required fault tol- erance. Accordingly, the designer must carefully choose the system architecture that meets the requirements pertaining to his/her specific application. Typical configurations include direct conversion, sample and hold then conversion, prearnplification, filtering, multiplex- ing, post processing, pipelining, buffering, error detection, etc. Commercially available data conversion systems range from basic analog to digital converter on a single monolithic chip to a completely integrated system that includes even a digital processor. Mixed mode analog/digital circuit represent a new fast growing trend in electronic systems. Circuits combine the properties of both analog and digital units ideally fabricated on the same chip to increase speed and area efficiency. Hence there is a need for a unified fabrication technology for both analog and digital circuits. Due to the present dominance of digital technologies, the architecture of analog circuits must be compatible with these technologies. Typical mixed mode circuits include digital processing units and analog-to- digital converters that link the analog signals to the digital processing power. The fabrica- tion of AIDS should use the available digital fabrication technologies. The widespread use of MOS technology, with its ability to accurately store and transfer voltages or charge pack- ets, led to the development of analog-integrated circuit techniques in which voltage was used as the active circuit parameter [2]. 1.1 MOTIVATION Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves [3]. Self-correcting, self-compensating, or self-calibrating tech- niques eliminate errors traditionally associated with analog circuits. They eliminate offset and low frequency noise and cancel the error effect [4]. Self-compensating techniques can be used to cancel nonlinearities [5,6]. For real-time applications, however, it is rather dif- ficult to achieve validation of the data generated from AID converters in the presence of faulty element(s). In general, the validation is accomplished by using an extra D/A convert- er and an analog window comparator, as shown in Figure 1.1, where a high resolution and accuracy digital-to-analog (D/A) converter is needed [7] and the comparison is performed in an analog manner. Therefore, the validation must highly depend upon the reliability of both the D/A converter and the window comparator. Although their reliability may be im- Analog Current 53111513 AID _ Digital Input fig” Converter v output Error . Window Indication Comparator I D/A Converter Figure 1.1 Testing of the AID Converter. proved by using sophisticated testing schemes to weed out faulty components [8], such off- line or static tests cannot identify the transient faults that occur during on-line operation. It would be preferable for the circuits to be designed such that they will indicate malfunction during normal operation and will not produce an erroneous result without an error indica- tion. As pressures increase on VLSI designers to use a lower supply voltage of 3.3 V rather than the present 5V, current-mode signal processing techniques will surely become increas- ingly important and attractive [9]. Current-mode circuits offer two potential advantages: improved dynamic range and improved operating speed [2]. Recently, an algorithmic AID converter that combines current-mode and dynamic techniques has been presented [10] and some alternative current-mode AID and D/A converters and their array structures have been studied [11]. These architectures represent an answer to the increasing proliferation of ap- plications requiring larger signal bandwidth such as medical imaging where small differ- ences in image density obtained from digitizing data collected at the scanning receptors are important for diagnosis. The converter does not rely on high gain amplifiers or well- matched components to achieve high resolution and is inherently insensitive to the ampli- fier’s offset voltage. However, the converter is susceptible to faulty switching elements even though mismatched components are allowed. 1.2 PROBLEM STATEMENT In order to enhance the reliability of data processing systems during real-time opera- tion, a concurrent error detection (CED) mechanism is added to the design of a current- mode AID converter. During manufacturers testing, it is necessary to generate test vectors which when applied to the device under test (DUT) reveal faults. The first question that nat- urally arises concerns the types of faults that a test experiment is to detect. The fault model considered in this study is the stuck-at-ON/OFF fault at the switching elements of a current- mode AID converter. Based on this fault model, the objectives of this thesis are (l) to ex- plore the fault effects of a single faulty switching element, (2) to develop a concurrent error detecting structure for real-time applications and (3) to find a finite set of test patterns that detects all single stuck-at faults at the switching elements during the manufacturing test. 1.3 THESIS ORGANIZATION This thesis is organized as follows. The next chapter presents necessary background information. The first section deals with the design of AID converters by introducing some conversion algorithms and their circuit implementation. A distinction is made between voltage-mode and current-mode converters. Section two is concerned with the issue of test- ing. General definitions and description of testing strategies are included. In particular, con- current error detection theory is detailed. In chapter three, current-mode devices where the processed signal is current instead of voltage are described. The basic building cells used in current-mode devices are intro- duced. The design and operation of an algorithmic current-mode AID [10] is presented. Chapter four focuses on the testing of the current-mode converter. First the fault ef- fects are analyzed assuming a single stuck-at fault model at the switching elements. This lead to the generation of a finite set of test vectors that detect these faults. In order to en- hance the reliability of the current-mode converter for real-time operation, an alternative converter architecture with concurrent error detection capability is proposed. An analysis of this new converter is carried out. Finally, the last chapter summarizes the work of this thesis and presents suggestions for future related research. CHAPTER TWO BACKGROUND This chapter introduces two important issues concerning A/D converters: design and test The design issue is presented as an overview of the conversion algorithms, and their circuit implementation. A distinction is made between voltage-mode and current-mode A/ D converters. The subject of testing is first described as a general philosophy. Next, stan- dard and novel test techniques applied to AID converters are presented. 2.1 DESIGN There is a vast number of conceivable approaches for AID conversion. The most pop- ular of these are: successive-approximation, integration, counter and servo, parallel and modified parallel. Each approach has characteristics that make it most useful for a specific class of applications based on speed, accuracy, cost, size and versatility. Because AID con- verters have been developed for different applications in various disciplines with little re- lationship to each other it is rather difficult to establish a unified classification of all known kinds of conversion techniques. Converters have been manufactured using first discrete components; then hybrid and monolithic technologies. In this section, the circuit techniques used in building Ale will be presented with emphasis put on the monolithic processes. Even though designers of monolithic converters have been successful in employing ingenious circuit techniques to achieve a high level of performance, they are still faced with performance limitations im- posed by the inherent properties of monolithic technologies [12]. These limits will be dis- cussed. Most of the currently available AID converters are called voltage-mode AID convert- ers since the converted data is a voltage signal. A general discussion of voltage-mode con- verters is included. Recently, a new class of AID converters, namely current-mode AID converters, is being developed as an answer to the new challenges faced by the designer of AID converters. Current-mode AID converters process current signals instead of voltages. 2.1.1 Conversion Prlnclple Functionally, a linear electronic AID converter is a device that accepts an input signal, Xm, voltage or current and yields at its output a set of electronic signals representing a nu- meric code whose magnitude is in proportion to an internal or external reference signal, X' and the input signal. An ideal AID converter can be described by a transfer function as shown in Figure 2.1. If the range of input signals is either positive or negative then the con- verter is described as unipolar; otherwise it is labeled as a bipolar AID converter. Since an N-bit binary code can produce only 2N distinct digital numbers, an N-bit converter also has 2N quantization levels. In a fixed point digital representation these levels are equidistant and the distance q, denoted by 1 LSB (Least Significant Bit), is referred to as a quantization step or interval. The smallest quantization step is equal to the full-scale (FS) signal divided by the number of quantization increments, i.e., FS/ZN. Hence, even an ideal AID converter introduces a quantization error bounded between 1/2 LSB, i.e. one half of the smallest quantization interval. The quantization error can be reduced to any desired level by increas- ing the number of output bits. The quantization error is often referred to as quantization noise because for analog signals with sufficient amplitude variation it has a noise-like char- acter. The smallest quantization step, FS/ZN, is also referred to as the resolution of the con- verter. The resolution is generally specified assuming an ideal converter; therefore, it does 111 110 101 100 011 010 001 000 A Digital 011W“t Nominal mid-range value Ideal transition ‘ .I I I Analog 1 LSB input I l L T. 1 l 1 l 4’ 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Quantization error A “2 LSB l\l\l\l\'l\ \ l\ _ - 1/2 LSB ................ \I\I\I\\I ........ Analog mput Figure 2.1 Ideal Transfer Characteristic in a 3-bit AID Converter. not reflect the actual performance of the converter which may be different due to some par- asitic phenomena; e. g. internal noise exceeding the quantization error. Thus the perfor- mance of a practical AID converter should be measured by an “effective-bits” resolution. The transfer characteristic of an ideal AID, would be invariant with variations in time, temperature and power supply. It would also be insensitive to interfering electronic and magnetic fields and power supply noise. Thus the ideal AID converter would have perfect absolute or relative accuracy, linearity, differential linearity, degree of precision, no vari- ance or noise in its output, ultimate stability, total monotonicity, zero offset, no transients, zero settling time, no missing code and would be capable of being updated to accommodate inputs of every frequency range or bandwidth. In practice such an ideal behavior is unat- tainable and quantitative measures must be introduced to describe practical behavior and assess the different AID conversion circuits. 2.1.2 Conversion Techniques Depending upon the speed of conversion, AID converters are classified under three large groups: high-speed, medium-speed and slow-speed [11].Typical conversion algo- rithms pertaining to each group are described. It has not been always easy to implement these conversion techniques for a reasonable degree of resolution and accuracy in parts be- cause the processed variables involve a continuum of voltage or current rather than a 0-1 logic. 2.1.2.1 High-Speed AID Converters High speed AID converters are sometimes called video Ale since such converters find application in the encoding of composite video signals as required for example in dig- ital television receivers [1 1]. Parallel or flash converters are the fastest and largest of this 10 group. Both subranging, pipelined and time interleaved array converters offer a fast con- version rate and a smaller circuit. Parallel or Flash AID Converters: A simplified block diagram of a flash AID is shown in Figure 2.2. Two reference signals can be used thus allowing for greater input range flexi- bility. The difference between the reference signals, Xfl - sz, is divided into 2N nominally equal segments thus generating all possible signal quantization levels. Simultaneously, dur- ing the same cycle, each of these levels is compared with the input signal Xin. If the input signal is higher than the quantization level under consideration, an output bit of l is gener- ated; otherwise an output bit of O is produced. This “thermometer” like digital code is con- verted to the desired binary code by an encoder circuit. The main advantage of flash AID converters is their high conversion rate. However the exponential increase in the number of comparators as a function of resolution limits the practicality of such converters. Time Interleaved Array AID Converters: In this structure It identical N-bit AID convert- ers with 8/11 stages are connected in n parallel channels Figure 2.3. In each channel, the input signal is sampled and held then converted at a rate of l/nT. By staggering the 8/11 stages in time such that the sampling in the second channel is T seconds behind that in the first channel and so on, the input signal can be sampled and held each T seconds by a dif- ferent AID converter in the structure. Hence, the overall system achieves a conversion rate n times higher than that of the building AID subconverter. A buffer and a digital multiplexer stage is used at the output to service the conversion channels one at a time. For high-speed input signals very stable and regular sampling intervals are required. Even a small, devia- tion from the nominal sampling frequency of 1/nT may cause considerable error since it leads to overlapping the input signals. A high-speed analog demultiplexer can be used to relax the sampling accuracy requirement by converting the analog input signal into n lower- speed sampled and held data signals which are fed into the appropriate sample and hold stage. ll Comparator Analog Input S/H S/H Comparator k 33 Digital 8 P _/ [S outpm Comparator Comparator Ax = Xrl _ Xr2 Figure 2.2 Block Diagram of a Flash AID Converter. AID 2 AID 2 Buffer and Digital . . —-> digital Output multiplexer AID 2 S/H Figure 2.3 Block Diagram of a Time Interleaved AID Converter. 12 Subranging and Pipelined AID Converters: One possible approach to increase the reso- lution capability and/or to reduce the size and the cost of fast AID converters is to imple- ment two or more stages of flash converters. Such techniques usually have cascaded structures i.e. the input signal is processed sequentially in consecutive stages. In a subranging converter, there is no SIH device between the stages and the signal must propagate through all the stages before a new conversion can be started. Figure 2.4 depicts a two-stage subranging AID converter. The operation consists of two steps. During the first step, a coarse M-bit flash converter gives an approximation of the M most signifi- cant bits. In the second step, the fine flash converter gives the least significant bits. The in- put S/H stage is used to reduce the aperture effect and to optimize the performance. A general structure of the pipelined AID converter architecture is shown in Figure 2.5. The pipe consists of m basic stages where each stage consists of a SIH circuit and a low resolution low speed AID converter. The input signal flows sequentially through successive stages, so the converter produces an N-bit digital word over several sampling periods rather than over one period. The main idea of a pipelined AID converter is to insert SIH structures between the subconverter stages in order to operate all the stages concurrently thus achiev- ing a high conversion rate which is almost independent of the number of stages. The prin- cipal disadvantage of pipelining is the requirement of high speed and high precision SIH SIIUCIUI‘CS. 2.1.2.2 Medium-Speed AID Converters A slower class in common use is the successive-approximation converter. Cyclic or algorithmic [l3] converters are also employed. Both techniques offer a relatively good speed-size performance. l3 Alialog Coarse ut M- ° p S/H ”" Flain Xin A/D M-bit M-bit DAC Fine L-bit Flash Output register and correction Logic i Ni... Digital output L-bit Figure 2.4 Block Diagram of Subranging AID Converter. l4 Analog Inpuit Nl-bit N l-bit N2-bit N2-bit x- 3’“ AID DAC A/D DAC rn Nl-bit N2-bit Output register and correction logic 1 Digital output Figure 2.5 Block Diagram of a Pipelined AID Converter. 15 Successive-approximation AID Converters: The successive-approximation AID convert— ers belong to the class of medium speed converters. Their implementation requires the use of the following building blocks: a SIH stage, a signal comparator, a DAC and a digital con- trol logic often called a successive approximation register (SAR). These building blocks are connected in a feedback arrangement as shown in Figure 2.6. The input SIH stage is used to hold the analog input signal constant during the conversion process. The converter operates on the following principle: after the reset in the first conver- sion step, the SAR sets the DAC output to XJ2. Hence, the MSB, d1, is assumed to be one whereas all other bits are set to zero. If the input is higher than X,/2, the MSB is left at one; otherwise, it is reset to zero. In the next step, the DAC output is set to X r/ 2 i X r/ 4 where the plus sign is taken if (11 = l and the minus sign if d1 = O. This signal is again com- pared with the input and the second most significant bit is determined depending on the re- sult of comparison. In the following step, the output of the DAC is to be incremented or decremented by X r/ 8 and a third comparison is performed leading to d3. The process con- tinues until all bits of the output word have been determined. Such a converter requires only N clock cycles to complete an N-bit conversion. Mathematically, the algorithm which de- scribes the operation of the successive approximation AID can be represented as follows: (—1)"*-‘ X(k) = X(k—1)— k 2 X (2.1) r dk = liinn>X(k) and dk = 00therwise, X(0) = X, andk = 1,2,...,N. A bipolar AID conversion can be achieved by introducing a sign bit do to select either +Xr or -X,. l6 Reset Analog + . In t —>pu SIH f » SAR <——CIOCk Xin - X(i) DAC 6 V Digital Output (a) I X(i) x,/2 ,_ / xi“ / ——1 Xr/4 ,. it d1=0 (12:1 d3=1 (14:0 d5=1 (b) Figure 2.6 (a) Block Diagram of a Successive- Approximation AID Converter. (b) Exemplary Voltage Waveform Illustrating the Operation Principle. 17 Cyclic or Algorithmic AID converters: The key operations in the cyclic AID converter are SIH, multiplication by two, subtraction and comparison. Conversion is based on hold- ing the reference signal constant and multiplying the signal to be converted by two during each conversion cycle. Conversion begins with sampling the input signal, Xi”, doubling it, then comparing it with X, in order to generate the MSB (11. If 2X,,, 2 X, then (11 is set to 1, X, is subtracted from 2X,n and the difference is multiplied by two. Otherwise, (11 is set to O and Xin is mul- tiplied by two. This procedure continues according to the algorithm described by the next set of equations until the desired resolution is achieved. X(k) = 2X(k—l) + (—1)d"“Xr (2.2) dk = 1ifX(k) ZOand dk = 00therwise, X(O) = Ximdo = 0andk = 1,2,...,N. 2.1.2.3 Low-Speed AID Converters High resolution converters can be obtained using one of the described conversion techniques at the expense of costly fabrication technology and/or complicated circuitry. Two alternative techniques achieve high resolution without these burdens. However, the conversion speed is negatively affected. Integrating Type AID: Usually the conversion cycle consists of two separate integration intervals. In the first interval the analog input signal is integrated up for a fixed and known period of time T1. Typically T1 equals 2N/fc where fc is the clock frequency and N is the desired resolution. In the second interval T2 the reference signal -X, is integrated down until the integration output returns to zero. The time period T2 is proportional to the input signal l8 X-m. At the start of conversion, the integrator and the counter are both zeroed. From the above considerations it follows that T1 T2 1 1 Ti JXindt— 7.; [xrdt _ 0 (2.3) 0 0 where T, is the integration time constant. Thus we can write where Xin is the average value of the input signal. Taking into account that N 2 D T = —— and T = — (2.5) l fc 2 fc D = zNfl (2.6) The important feature of this result is that the digital number D is independent of the inte- gration time constant T, and of the clock frequency f, since these parameters affect both the first and the second interval in the same ratio. Oversampling AID Converters: In oversampling AID converters, the input signal is sam- pled at a rate much higher than the Nyquist rate; then it is converted to a digital stream in an interpolative modulator. A block diagram of an interpolative AID converter, a typical class of oversampling Ale, is depicted in Figure 2.7. The quantized approximation of the input signal is subtracted from it and the difference is integrated. The integrator in the loop tends to minimize the average difference of the sampled analog input and the quantized ap- proximation. The output of the estimator goes to a digital-low-pass filter which averages and decirnates this coarse estimate to get a finer approximation at a lower sampling rate. l9 Integrating Digital filter Estimator l e.g M-brt AID A... l .. mp3? + Digital —-> SIH —>O—> H(z) —> 3.115 F low-pass -——> Xin - filter * M+L bits . . Digital Dlgltal . / Output approxrmatron Of Xin M-bit DAC ‘ Figure 2.7 Block Diagram of a Interpolative AID Converter. 20 2.1.3 Converter Technologies! Converters Mlcrocircults This section provides an overview of the circuit technologies used in building A/D converters. Early AIDS have been of the discrete component type. Later, hybrid and mono- lithic converters have been developed. Advances in integrated circuit fabrication along with the development of new circuit techniques still contribute to the improvement of monolithic converters. 2.1.3.1 Discrete Component Converters Early AID converters were made of discrete components. It was possible to individ- ually select and provide a set of optimal components such that high speed comparators and low temperature coefficient resistors to be used in building the AID converter. The result was high performance fast and stable converters. 2.1.3.2 Hybrid Converters One may think of hybrid processing as reducing a printed circuit to the level of a sin- gle component producible in large economical quantities. Hybrid circuit design is almost as flexible as prom-boarding except for two limitations. The first limitation is a result of the fact that not all components used in building the converter are available in chip form. The second limitation concerns the number of chips which must be minimized for economical production. Hybrid design is particularly useful when the components to be used are avail- able in technologies that are normally incompatible and can not be integrated in a single chip. Several factors such as availability of low cost chips, development of efficient AID designs which minimize the used circuitry and production of high precision components contributed to improving hybrid AIDS. 21 2.1.3.3 Monolithic Converters Monolithic converters are generally below discrete and hybrid ones in performance due to the impossibility of fabricating high performance components such as matched ca- pacitors, stable resistors, etc. However, these converters currently dominate the AID con- verter field due to their economical production and mostly to the possibility of integrating them as part of the integrated data systems. In general monolithic converters have been fab- ricated with either bipolar, CMOS or BiCMOS technology. The bipolar technology is used to fabricate many popular logic families such as 'I'I‘L and its derivatives. However, there are significant differences in the processes used for lin- ear bipolar circuits and digital bipolar circuits. For example, bipolar digital circuits are gen- erally designed for relatively low breakdowns and high speed. Linear circuits on the other hand, need a wider supply spread in order to accommodate larger signal swings. Achieving an acceptable dynamic range requires higher breakdowns thus dictating larger geometries and leading to lower speeds. Therefore, it is difficult to produce both high precision linear circuits and digital functions on the same chip using either the standard linear bipolar pro- cess or digital bipolar process. An approach that has been successful is the addition of the logic functions to a pre- dominantly linear circuit using the integrated-injection logic (12L) process. This allows in- cluding reasonably dense logic on the same chip along with high breakdown linear circuitry. The CMOS technology is superior to other processes in power requirements and packing density. Hence larger conversion systems including a microprocessor are possible. In addition, CMOS offers the AID designer with a simple and efficient switching subcir— cuit. Unfortunately, the lack of CMOS low-noise reference sources and gain stages (oper- ational amplifiers and comparators) handicaps this technology. In fact, most CMOS 22 converters are designed for use with an external reference, since high performance bipolar Zener and bandgap references are available with low drift and noise. BiCMOS, a generic name applying to several manufacturing processes combines bi- polar and MOS transistors on one chip. This process is considered to be the most promising technology for future data converters. It benefits from the advantages of both processes and avoids both of their short coming. Independent of the particular conversion technique being used, properties of the tech- nology in which the analog to digital converter is implemented place limits on the circuit performance [12]. For example, implementation in CMOS puts limits on the voltage dy- namic range and speed of AIDS. Specifically, the process of sampling and holding (SIH) the converted Signal also stores the thermal noise on the SIH circuitry on the holding capac- itor. The noise appears as a random variable with a variance equal to k—g , where k is Boltz- man’s constant, T is the temperature in degree Kelvin and C is the value of the sampling capacitor [12]. AS the technologies is scaled down, the capacitance value shrinks and the thermal noise phenomenon represents a limit on the achievable dynamic range per sample. Speed is ultimately limited by the use of a comparator, an essential element in voltage- mode AIDS. The conversion time is limited by many factors but cannot be Shorter than some multiple of the comparator delay. Monolithic analog to digital converters are at the present time far from the fundamen- tal limits imposed by comparator delay and SIH noise. Presently, performance levels are dictated by practical circuit, technology and packing limitations. Examples include undes- ired coupling between the analog and digital portions of the circuitry within the converter, charge injection from the switches, offsets in operational amplifiers and comparators, com- ponent mismatch and so forth. Perhaps the single most important factor limiting the linear- ity of those AID converters which are based on conversion algorithms requiring either a divide or multiply by two scheme is the component mismatch problem. As the converter 23 resolution increases the effect of mismatching becomes more pronounce. The comparator and/or the operational amplifier’s offset is more important in high resolution converters where the per-sample signal is low. 2.1.4 Solutions to Some Limitations on the Performance of AIDS During the last few years monolithic AIDS have improved dramatically in speed and accuracy. These improvements in performance are made possible by new converter archi- tectures and improved semiconductor processes. To obtain matching in components their geometrical Size and therefore the area of the circuit has to increase. To overcome this drawback, component adjustment techniques such as laser trimming or thin-film resistor networks have been introduced. Although these methods yield components matched to ex- tremely high precision, they have the disadvantage that extra area is needed for placement of the components to be trimmed or a different substrate has to be used for the passive com- ponents [14]. A common way of handling the component matching problem is to develop circuit techniques which eliminate the matching requirement. Two main approaches have emerged. The first consists of improving the currently available voltage-mode converters while the second proposes a novel class of AIDS i.e. current-mode converters. 2.1.4.1 Voltage-Mode AIDS The development of AID converter circuits was dominated by voltage-mode devices because of the availability of voltage-mode supporting circuitry such as reference generat- ing units, switching circuits, sample and hold circuits, comparators and operational ampli- fiers, etc. Voltage-mode AID converters evolved from vacuum tube and resistive ladder implementations to transistor and switched capacitor systems. When faced with perfor- 24 mance limitations due to mismatching monolithic converter designers have been quite suc- cessful in employing circuit techniques such that self-calibration [15], reference refreshing [l6], charge balancing, dynamic element matching, ratio-independent converters [17] and digital error correction [18]. Each technique is appropriate for a Specific conversion algo- rithm and a specific implementation of this algorithm. It is worth noticing that most of these techniques pertain to either successive approximation or cyclic AID converters. As a matter of fact, most of the monolithic AIDS implement these two algorithms since they represent one of the best approaches to achieving a minimum area AID which in turn is easily inte- grated as part of a single chip data processing systems [7]. The self-calibration technique applies to both successive-approximation and cyclic AID conversion methods. Correction terms are properly added during the normal conver- sion cycles to cancel the nonlinear effects due to capacitor mismatch. Relatively high res- olution is achieved at the expense of increasing the complexity of the control logic for an extra calibration cycle. In the reference refreshing technique the error is reduced by circulating both the ref- erence voltage and the signal being converted around the loop. This method is not only ca- pacitor ratio independent, it also compensates the error due to non-ideal operational amplifier gain. However, it tends to increase the circuit complexity and the number of tasks to be carried out during each conversion cycle. Charge balancing and dynamic element matching apply to successive approximation converters by improving the accuracy of the digital to analog converter used as part of the circuit. The error due to capacitor mismatch can also be improved by using a ratio-indepen- dent algorithmic conversion technique. The exact integral multiplication of the signal re- quired by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS integrator and exchange of the sampling and the integrating 25 capacitors. A first-order cancellation of the charge injection effect from MOS transistor switches is attained with a combination of differential circuit implementation and optimum timing scheme [14]. Error-compensation AIDS belong to two general classes. The first class comprises those AIDS that achieve data accuracy via digital error correction. An example is given in [18] where the concept of variable conversion rate has been used by only allocating longer conversion cycles for the least Significant bits and hence minimizing the time overhead in- troduced for error compensation. The use of both analog and digital circuitry and the extra compensation time are the main disadvantages of these AIDS. The second class consists of those AID that use analog circuit schemes and a modified converting sequence where spe- cial cycles are allocated for charge redistribution for the purpose of error compensation [19]. Hence compensation involves almost no change to the AID circuit; however the con- version speed is affected. 2.1.4.2 Current-Mode AIDS An alternative approach to the design of AIDS is to use the current instead of voltage to represent the Signal. This approach offers a number of advantages such as improved ac- curacy, higher sampling rates and reduced chip area. Irnprovements in accuracy are achieved because the usual problem of switch induced charge injection encountered in volt- age based systems has no effect on the Signal in current based systems. Improvements in speed can be achieved by reducing the time required for the voltage to settle on the capac- itors at the various circuit nodes. The settling time can also be reduced by minimizing the voltage swing required for a given signal dynamic range. This can be done by using CMOS devices always operating in the saturation region where a doubling of the transistor’s gate voltage is all that is required to provide a four fold increase in the Signal or current level. Since the signal is represented by current, there is no need for a large capacitor array with 26 its significant charge and discharge times. As a result, the concept of using current to rep- resent the Signal in an AID leads to higher sampling rates as well as reduced chip area. Chapter three expands on the concept of current-mode analog-to-digital conversion. 2.2 TESTING AND VERIFICATION During the last few years the theory and practice of testing electronic products have changed considerably. The continuing revolution in electronic circuitry in terms of size and speed have increased the problems of testing. In fact, in the field of electronics methods of testing and measurement have always had complex relationship with the products being tested. The technology of testing is bound to exploiting the available technologies of the day to their limits in order to answer the increasing demands for reliability. The philosophy of testing has evolved from merely measuring electrical parameters at many points in the device under test to integrating testing in every step of the device design and development. A whole field of testing has emerged. The following section presents a brief introduction to some important testing concepts. 2.2.1 Testing Techniques A test is a means by which the existence and quality of certain attributes within a sys- tem are determined [20]. The testing of any system or device is vital to achieving high re- liability, safety, maintainability, cost effectiveness, fault tolerance, or other design requirements. The testing process attempts to determine if the device under test (DUT) works and if it possesses its complete capability. There exists various testing techniques that can be used to achieve this goal. In general testing techniques use two major approach- es: built-in test and external test [20]. External test techniques are typically performed with the DUT removed from its operating environment and various tests applied to it using ex- ternal equipment. Built-in test techniques usually incorporate testing as part of the design 27 of the device; thus no external testing equipment is needed. Built-in techniques can follow either a concurrent or a nonconcurrent approach [20]. Nonconcurrent test techniques re- quire that the operation of the DUT be halted before beginning the test. Concurrent test techniques allow a device to be tested while in normal operating mode. Whether the test mechanism is built-in or external, three major types of tests are pos- sible: functional, parametric and fault testing. The purpose of functional testing is to verify the functional specifications that the DUT was designed to achieve assuming error free components and proper usage. Parametric testing checks if certain parameters of the DUT are within a required range. Fault testing determines if the DUT suffers from any faults. Each of these three tests can be performed in either a static or a dynamic manner [20]. A static test only investigates the steady-state or DC. characteristics of the device’s re- sponse. The time response of the DUT overlooked in static tests is used during dynamic testing to evaluate the DUT. A subset of dynamic testing is the at-speed testing where a de- vice is tested at, or above, its normal operating speed. 2.2.2 Test Generation The test generation process includes fault modeling and reduction, test pattern gener- ation, fault simulation, fault coverage evaluation, and the production of fault dictionary. The first step consists of developing a fault dictionary for the circuit, i.e. modeling the faults that are assumed. Next test vectors and/or test patterns are generated to test for the set of faults being considered. The test patterns are then simulated against the faulted circuit and the fault coverage is evaluated. If the fault coverage is inadequate, the process of test pat- tern generation and fault Simulation are repeated. To be practical and cost effective for large scale integrated circuits, the test generation process should be automated. Fault modeling is very important in developing cost effective test strategies for elec- tronic circuits. A fault is a physical defect imperfection, weakness, or flaw that occurs with- 28 in some hardware or software component [20]. A Fault manifest itself as an error(s) i.e. deviation(s) from accuracy or correctness. Many different physical defects can occur in a circuit. A fault model maps this relatively large number of defects into a small number of modeled faults. The selection of adequate fault models is crucial to achieving high quality testing because the efficiency of a test scheme is limited accuracy of the chosen fault model. If the model fails to capture the important characteristics of the actual fault, the test based on this model will fail to detect the actual fault. For circuits containing switching elements the logical stuck-at model is appropriate, effective and simple to work with. This model is based on two assumptions [20]. The first States that a Stuck-at fault results in the circuit responding as if the faulty node is physically connected to 0 or 1. The second assumption is that the basic functionality of the circuit is not affected by the fault. This implies that the circuit continues to behave as expected of it given the existence of the fault. 2.3 TESTING OF AID CONVERTERS The revolution in circuit fabrication technology and architectures led to a shift from analog design of electronic systems to all—digital implementations. The decreasing cost of implementing digital solutions and algorithms for data processing, system monitoring and control resulted in rich variety of digital systems. AID and D/A converters are the answer to linking the analog world of signals to this digital processing power. Applications using converters are found whenever a digital system is used in conjunction with analog data, that is almost everywhere. The properties of the converter to be used for each system are impor- tant. Reliability is crucial for some of the converter applications, such as power plant mon- itoring, medical diagnosis and industrial automation. For example, an erroneous digital data generated by an AID converter reading the radioactivity level near a nuclear reactor may fail to flag some equipment failure and result in a nuclear catastrophe. Hence, spending 29 fortunes improving the monitoring processor and the sensing devices will not be enough for a secure plant if the bridge between the controlling tools and the sensors output is de- fective. Both less dramatic consequences of converter failure and worse ones exists. They all stress the importance of converter reliability and the reliability of any electronic circuit in general. Different strategies can be taken to achieve different level of reliability depend- ing on the device’s objective. 2.3.1 Functional and Parametric Testing Functional and parametric tests check the design and specifications of the DUT. In the case of AID converters, these tests answer the following questions: does the DUT pro- vide good AID characteristics and what are the restrictions and properties of the used com- ponents that are detrimental to the performance of the AID converter? The first step in performance evaluation consists of generating the transfer function of the AID converter i.e. for an N-bit resolution AID converter finding 2N transition points. Next, the transfer function of the A/D converter is tested for offset error, gain error, differential linearity and integral non-linearity. These errors reflect either a bad design, too many non-idealities, or a wide tolerance in the fabrication process. Several test methods such as Crossplot and ATE are known for voltage-mode converters [7]. Current-mode converter represent a relatively novel architecture without any well known functional and/ or parametric test procedures. Functional and parametric tests are crucial for the designer in proving the merit of a given AID conversion architecture. An AID converter passing such test(s) is expected to operate within its intended specifications. In fact, the investigated specifications determine the converter’s usefulness for specific applications. 30 2.3.2 Fault Testing Proving the correctness of an AID converter can be achieved by functional and para- metric test types. However, in general, the success of these tests does not guarantee that the AID will operate correctly thereafter. In fact, faults may occur only after the device has been used for a period of time. Also the effect of some faults may only appear during device operation. In addition the device may be fault free and Still fails to function correctly due to misuse. Parametric and functional tests perform design verification; however, fault test- ing aims at fault immunization i.e. monitoring device reliability. This work approaches re- liability at the level of data validation. Hence its objective is to achieve an AID conversion circuit that does not produce erroneous output data without indicating that it is erroneous. The error flag does not give any information about the occurring fault and no mechanism has been devised to retrieve the correct data. There exist several techniques for designing and or modifying electronic circuits providing them with data validation capabilities i.e. with fault tolerance properties. On-line concurrent error detection (CED) methods achieve such a goal. Built-in concurrent error detection avoids several difficulties involved with external testing of analog circuits, such as loading by the test equipment Moreover, this strategy solves the problem of existing disparity between the testing equipment and the DUT. Concurrent error detection is implemented by slightly modifying the topology of the current-mode AID. The new AID architecture possesses a built-in concurrent data valida- tion mechanism. 2.3.3 Concurrent Error Detection All CED schemes detect errors through conflicting results generated from operations on the same operands. CED can be achieved through Space or time redundancy, or Space/ time hybrid redundancy [21-27]. Time redundancy employs only one single set of hardware to carry out the repeated operations. Since the same hardware is used, the repeated opera- 31 Time ‘0 input x f f(x) Time t1 “’P‘“ x C , Figure 2.8 The Concept of Time Redundancy. 32 tion, in the presence of faults, is liable to produce the same erroneous result as that of the first step. To avoid this problem, the operand must be coded in the repeated cycle. The re- sult thus obtained must be decoded back to the appropriate form for meaningful compari- son. Two simple time redundancy techniques have been reported: RESO (REcomputing with Shifted Operands) [21,24,25] and AL (Alternating Logic) [26,27]. Among existing CED techniques, both RESO and AL have unique features of transient fault detection and require only a moderate increase in hardware. Consider a time redundancy technique Shown in Figure 2.8 [21]. Let x be the input of the computation unit f and let fp(x) and f(x) be the outputs with and without encoding-de- coding operations, respectively. Two fundamental requirements must be satisfied in these operations. First, the coding function 0 must not interfere with the original function f. In other words, for a selected coding function c, there must exist a decoding function C‘1 such that fprx) = c“(f(c .9 T ,3. Comparato + Amplifi f e r I —o Comparator Output (to latch) C1 I (a) MSB previous bit = 1 previous bit = 0 Sr l——L_ S2 l—LJ—|_ |_|__|—l_ I_L_|—|_ 83 L l_L__ FL— 34 __J—l_ n _J_l_ 55 I I _I—L m 56 _l—_| l | S7 | | m [_L_ 58 _I_| __J I l_|— Latch ___]_‘| ___["| __[_| (b) Figure 3.2 Current-Mode AID Converter. (a) Schematic Diagram. (b) Switching Sequence. 37 olution and are inherently insensitive to the amplifier’s offset voltage. In order to Speed up the conversion time, while still keeping the converter circuit Simple, a current-mode AID converter has been proposed [10] in which the following recursive conversion algorithm was employed, 11m = 1k - qk [REF/2k+1;k=0,l,...,N-l (3.1) where lozllN, d0=1, q0=1, and 1 if dk=l, i.e., I,“ _>. 0, (3.2) qk : I If dk=0, i.e., Ik+l < 0. The bit values of dk and qk are determined by the polarity of the current Ik+1 Figure 3.2 Shows the schematic circuit diagram of the current-mode AID converter [10]. The converter is comprised of two NMOS current copiers, one PMOS copier, an op- amp, and a current comparator. The converter starts converting for the most significant bit (MSB) of an input current IIN by first switching on 51, S2, and S3 to cause the current in N1 to be set to IIN- Once N1 is set, S2 and S3 are switched off while S4 and 85 are on to copy [IN to N2. Once the input signal has been Stored in N1 and N2, twice the input signal is loaded into P1 by turning off S] and 85 while switching on S2, S6, and 8-,. After P1 is set, S2, S4 and S7 are turned off while 810 is turned on, thus allowing the comparator to sense the current imbalance and hence determine if the signal, 21m, is greater than IREFo If the signal exceeds the reference, the MSB will be a "1" otherwise it will be a "O." This com- pletes the conversion for the MSB. The current comparator, Figure 3.3, operates as follows: the current imbalance flows through the large equivalent gate to source input impedance presented by the CMOS structure, the resulting drain voltage reflects the current direction. The remaining (N-l) bits are then converted in the same manner. The Signal held in P1 is loaded to N1 by turning on S6, S2 and S3. If the preceding bit was a "1," 510 is also turned on to subtract the reference from the signal in P1. On the other hand, if it was a "O," 38 we Figure 3.3 A Simple Current Comparator. —o Comparator Output (to latch) Figure 3.4 Modified Current-Mode AID Converter. 39 510 is off so that the signal remains unchanged. Once N1 is set, N2 is set by the same pro- cedure. The Signal is then doubled and stored on the gate of P1. Finally, it is compared with the reference. This sequence is repeated until the desired resolution has been achieved; an end of conversion pulse is then generated to signal the end of conversion. The converter needs 4N clock cycles for an N—bit data conversion. An extensive discussion of the limitations and the practical design issues involved in implementing the described current matching AID converter is presented in [30]. The pro— totype circuit has been fabricated using a 3-um CMOS technology. It achieved a resolution of 10 bits with a maximal sampling rate of 25 KHz, or 40 usec conversion time, a power consumption of only 3.5 mW and an area of 0.32mm2. The power supply was +5V and the reference current was lOOuA. The gain error at full scale was -2.29 LSB and the offset error was equal to 0.03 LSB. The integral nonlinearity varied between i0.92LSB, while the dif- ferential nonlinearity was bound between 0.10LSB and -0.87LSB. It should be mentioned that, since the input current is needed during the first two clock cycles for converting the MSB, a sample-and-hold (SIH) circuit is required for the input current [10]. However, the SIH circuit can be omitted by holding the input IIN in P], where the polarity of the input current is changed as Shown in Figure 3.4. 3.3 CMOS CURRENT COPIER Consider the current-mode AID converter in either Figure 3.2 or Figure 3.4. In the presence of a stuck-at-ON fault at S3 (SS) and during the copying of the current held in N1 (N2) to P1, the CMOS structure N2-P1 (NI-P1) act as the copier. Conventional NMOS and PMOS copiers can be used for memorizing only input cur- rents that flow in the same direction as the drain current. To accommodate applications where currents in both directions are present a CMOS current copier is designed. Experi- IIN Sw ST SQ \ lldp —-—o S C, I Idn 0 Figure 3.5 CMOS Copier Where IIN = 1d,, - Idp. 4] mental and simulation results Show that the proposed copier can precisely memorize bipo- lar input currents within a specific range Figure 3.5 shows the proposed CMOS current copier with op-amp, where the dual power supplies i2.5V are employed. During the copying, both switches SW and SQ are turned on; the capacitor will charge up to the gate voltage needed by both NMOS and PMOS transistors to achieve a current equal to the input current IIN=Idanpr where [(11, and 1d,, are the drain currents of the NMOS and PMOS transistors, respectively. If the polarity of the current [IN is positive, then 1d,, < ldn’ otherwise 1d,, > Idn- Note that Idpzldn if IIN=0. The op-amp is used to force the drain voltages of both transistors to be zero so that they are operating at the saturation region. After the copying, switches SW and SQ are turned off to disconnect the cell from the input current source and then the cell is ready to source or Sink current when connected to a load. When switch ST is turned on, the op-amp again forces the drain voltages of both transistors to be zero and ensures that both transistors are oper- ating at the saturation region and thus the proper current can be extracted. A prototype CMOS current c0pier, which is comprised of a CD4007 dual comple- mentary pair chip and a uA741 op-amp, has been implemented. The experimental results are plotted in Figure 3.6(a), where the capacitance C=46.035pF and the applied input cur- rents range from -2.2mA and +2.2mA. Both drain currents 1d,, and 1d,, are measured by two current meters. Since both PMOS and NMOS transistors in the CD4007 chip have virtually the same device transconductance parameters k=k’(W/L), the plot is nearly symmetrical. Results Show that Id=2.0mA and Idn=0mA if IIN=-2.OmA; Idp=1.18mA and Idn=0.08mA if IIN=-l.10mA; Idp=ldn=0.49mA if IIN=OmA; Idp=0.06mA and 1d,,=1.15mA if IIN=+1.O9- mA; and Idp=0mA and Idn=2.0mA if IIN=2.OmA. For reliable operation of the copier it is necessary that the PMOS and NMOS transis— tors be operating either at the saturation region or at the cutoff region depending upon the relationship between the power supplies and the threshold voltage difference (Vm-th), the 42 CMOS copier with uA741 op. amp. Date/Time run: 12/11/91 22:11:48 Temperature: 27.0 2mA 1» ------------------ +- ----------------- +— ----------------- + ----------------- 1 .OmA 8mA i 1 ml + 4mA l J, 2mA I I OmA l = = ------------- +- -------------- ' —l OmA —O.SmA 0.0mA SmA 1.0mA a Idp I Idn IIN . I o 2.5 . .dp . Id" . 0° 2 *- °o°° _‘ 1.5 ~ I . 3| 000° ‘ I. 0.. l ID(mA) 1 — ‘ l o °° o 0.5 — . 0225.991 - o°°° 000 0 mnoowoowooo - . . . . NMOS ”mu-on °' cue-uncouuozc-nuu PMOS lrn . ___p NMOS linear NMOS cuto f PMOS 83mm“ PMOS cutoff _O.5 r r r r r r r r —2 -1.5 —1 —O.5 0 0.5 1.5 2 IIN (mA) Figure 3.6 (a) Pspice Output. (b) Experimental Output. 43 input currents can be improved by increasing the aspect ratios (WIL),l and (W/L)p, as shown in (2) and (3), but at the cost of larger chip area. 3.4 SUMMARY The presented current-mode AID has a number of features that make it attractive for designers of VLSI systems. Its favorable speed/area trade-off makes it well suited for use in large Signal processing systems. Further circuit refinements should allow better perfor- mance. For example, speed can be quadrupled by using a pipelined architecture. Special at- tention should be given to minimize errors inherent to the current copier cell. Inevitable circuit nonidealities will cause the current retrieved from the cell to differ from the copied current. Mechanisms of error include switch charge feedthrough, limiting the initial accu- racy of the current sample; channel length modulation, producing a change in the retrieved current as the voltage VDS changes; junction leakage, associated with the resistance of the switch in the off State causing a steady discharge of the storage capacitor; and llf and ther- mal noise, limiting the accuracy of the current sample and varying the current during re- trieval [31]. Circuit techniques for reducing these errors range from proper choice of the parameters of the circuit components to altering the Circuit’s topology as in the case of add- ing an operational amplifier. CHAPTER FOUR TEST GENERATION AND CONCURRENT ERROR DETECTION The objective of this chapter is first to address the fault effects and test generation of the current-mode AID converter proposed in [10], where the Single stuck-at fault model is assumed for switching elements. Further, in order to enhance the reliability of AID convert- ers for real-time operations, an alternative current-mode AID converter with CED capabil- ity is proposed to detect transient and permanent faults. 4.1 FAULT MODEL AND FAULT EFFECTS Although mismatched components are allowed in the converter of Figure 3.4, the converter is still susceptible to faulty switching elements. Any faulty switching element may result in an incorrect converted data. The single stuck-at fault model, commonly em- ployed for digital test generation, will be used. In this implementation, it is assumed that only one faulty switch occurs at a time and the faulty switch is permanently stuck-at ON state (S/ON) or OFF state (S/OFF). In general, the faults may be caused by either a mal- functioning clock generator, i.e., one bit may be permanently stuck-at-l (or 0) causing the controlled switch to be S/ON (or S/OF F), or by malfunctioning transistor switches. The analysis of the faulty switches in the converter of Figure 3.4 revealed that the fault effects can be classified into three types: Type 1 fault effect occurs when the faulty switch results in the same conversion output regardless of the values of the input current. 45 Switches 81, S2, S4, S7, and 810 being S/ON and S], 82, S4, S6, and 810 being S/OFF illus- trate this fault behavior; Type 2 occurs when the faulty switch renders the conversion out- put dependent on the initial condition of the active capacitors. Switches S3, SS, S7 lead to this condition when S/OFF; and Type 3 faults make the result of the conversion process dependent on the CMOS structure P1/N1 (or P1IN2) when S3 (or 55) is being S/ON. Throughout the next analysis, [pl (1N1, or 1N2) will denote the current held in P1 (N 1, or N2) 4.1.1 Type 1 Fault Effect Consider the case when S] or 86 is S/OF F, the input current will not be copied into P1; this is effectively equivalent to an input current of zero. Consequently, the conversion process results in a string of zeros. When S2 (S4) is S/OF F , the input current in P1 will never be doubled. In fact, S2 (S4) being open circuited results in N1 (N2) contributing zero current to P1 during the copying of the sum current IN1+IN2. Hence the comparison of current in P1, i.e., [IN and IREF always results in a zero bit. Sm being S/OFF leads to the current in P1 being compared to zero instead of [REF- Hence conversion results in a string of ones. When 81 is S/ON, P1 gets the input current; however when P1 is being copied into N1 (N2), N1 (N2) gets the difference current (Ipl-IIN)=O. The comparison of [pl (=IN1+IN2+IIN) and IREF produces a zero MSB. Next, instead of P1 being copied into N1, the zero current dif- ference (Ipl-IIN) is copied into N1. Hence conversion results in a string of zeros. At the end of every conversion, the capacitors are left charged. This charge represents the last current that has been copied into the corresponding transistor. Since N1 and N2 copy either the current [p], when [p] < IREF’ or the current difference (Ipl-IREF), when [pl > IREF’ the current in the corresponding NMOS, at any instant, is bounded between zero and IREFo If S2 is S/ON, both the initial current 1N1 and the input current [IN will be copied to P1, i.e., P1 gets IIN‘I‘INlo Then P1 is successfully copied into N1. However, when P1 is being copied into N2, the current in N1 is subtracted from it resulting in copying zero current into 46 N2. Hence the current in P1, will not be doubled. During the comparison phase, the com- parator senses the unbalanced current, ‘IREF’ from P1, N1, and IREF- Thus, a zero bit always results. Similarly, when S4 is S/ON, a string of zeros is generated. While comparing P1 and [REF with S7 being S/ON, P1 will first c0py [REF due to S7 being ON. At the end of the comparison cycle, the difference between IP1=IREF and [REF will be compared leading to a conversion bit of 1. This scenario is repeated for all conversion bits. Thus, a String of ones results. 4.1.2 Type 2 Fault Effect When S3 is S/OFF, the transistor N1 cannot copy any current because the capacitor C1 has no charging path. Thus, N1 will retain the current it has copied prior to the occur- rence of the fault. This current will be held constant since the capacitor can only leak its charge through the gate to source impedance. In the presence of such a fault, conversion proceeds as follows: [IN is copied into P1; P1 copy to N1, but N1 still holds the constant current 1,; P11 is copied to N2; P1 gets IN1+IN2, or Ix+IIN3 finally, the current held in P1 is compared to [REF and the proper conversion bit results. Similarly, the S/OFF faulty switch 85 has the same fault effect When S7 iS S/OF F , the transistor P1 cannot copy any current. Thus, the constant current in P1 is compared to IREF for the output. 4.1.3 Type 3 Fault Effect In the presence of S/ON faulty switch S3, conversion starts off with successfully copy- ing [IN into P1; P1 into N1, and P1 into N2. Then, instead of copying IN1+IN2 into P1, N2 will source its current [IN to the CMOS Structure, comprised of P1 and N1, due to S3 being S/ON. Since the current copied in the CMOS structure is positive P1 ends up with a positive current greater than or equal to the current supplied by N2 (=IIN). The conversion proceeds 47 such that at the end of the km cycle the currents in the transistors P1 and N1 are given by the following recursive formula: Ip1(k)-IN1(k) =Ip1(k-l) - d(k-1) * [REF (4.1) Ip1(k) = K’, (1/2) (W/L)p (V600 - vDD - V,,,)2 (4.2) 1N1(k) = K’n 11/2) (WIL)n (VG(k) - v,s - Vm)2 (4.3) d(k) = 1 if Ipl-IREF 2 0 and 0 if Ipl-IREF < 0. (4.4) where k = 1, 2,...,N, 191(0) =11N, um) = 0, d(k) is the 16“ conversion bit, vGas) is the com- mon node voltage at the gate of P1 and N11 during the km cycle and KP, th, (W/L)p, K’n, Vm and (W/L)n are the parameters of the respective P and N transistors. Similarly, the S/ 0N faulty switch 85 has the same fault effect. 4.2 TEST GENERATION AND FAULT COVERAGE According to the fault effects discussed previously, in the presence of a Type 1 fault, i.e., S/ON faulty switch SI, S2, or S4, or S/OFF faulty switch SI, S2, S4, or S6, conversion results in a string of zeros. Thus, any nonzero input current can detect such a fault. Similar- ly, in the presence of S/ON faulty switch 810 or S/OF F faulty switches S7 or Sm, conver- sion results in a string of ones. Thus, a zero test current can detect the fault. For Type 2 fault effect, in the presence of S/OFF faulty switch S3, transistor N1 can- not copy any current because there is no charging path to the capacitor C1. In fact, N1 re- tains the current it has copied prior to the occurrence of the fault. This current referred to as Ix remains almost constant since C1 can only leak its charge through the high gate to source impedance of the transistor N1. Consequently, the current held in P1 in the step is equal to IIN'I'Ix~ Two test currents, IIN=O and IREF, can detect such a fault for any value of Ix. Specifically, for IIN=O, during the MSB conversion, the comparison of [pl (=IIN+Ix= x) 48 and IREF generates a zero MSB except when Ix=IREF° During the k-th bit conversion, 1p]:- ka generates a zero bit except for Ix 2 [REP/k. Hence the conversion of IIN=O generates at least one nonzero bit in the k-th bit position. The result of conversion follows the general pattern of O...1xxx, and the first nonzero bit detects the fault. On the other hand, for IIN= IREF, the comparison of [PI (=IIN+IX= IREF'I'Ix) and [REP leads to an MSB of 1. The k-th comparison involving 11:1:ka and [REF produces a one bit except Ix S [REP/k. Hence the result of conversion follows the pattern 1...0xxx i. e. the result contains at least k zero bits after MSB where k is the smallest integer such that kIx < IREF- The first occurrence of a zero bit detects the fault. This concludes that these two test currents can detect the fault re- gardless of the value of 1,. Similarly, these two test currents can detect the S/OF F fault on switch SS. Consider the presence of S/OFF faulty switch S7, the fault effect shows that the current, ly, copied in prior to the fault will not change. During normal non-faulty conver- sion P1 copies either IIN S IREF’ 21m S ”REF, or 21Z S ZIREF where I2 = [P] if 1131 < [REF and I2 = lpl-IREF if Ipl 2 IREF- Thus the constant current Iy held in P1 is bounded between 0 and 2 IREF- Thus, the above two test currents, namely 0 and IREF’ can also detect the fault. More specifically, [IN=0 and 1m: [REF detect the fault in cases Iy < [REF and I), 2 IREFt respectively. For Type 3 fault effect, in the presence of S/ON faulty switch S3, the transistor N2 will source its current [IN to the (Pl/N1) CMOS structure. This results in [pl-IN1=IN2=IIN, where the values of Ipl and 1N1 depend on the characteristics of the CMOS structure. For example, based on the parameters given in the M0818 2um CMOS technology, when the aspect ratios of P1 and N1 are mum/211m and 4um/2um, respectively, Pspice simulation results Show that, for IIN=O, the currents Ip1=IN1=0.1483mA, and the current In increases as the positive current [IN increases. Thus, the converted data will definitely include at least a 1 in the presence of such a fault and the test current IIN=O detects the fault. The number of conversion cycles needed to detect the fault depend on the transistor parameters and con- 49 sequently on the fabrication technology. Similarly, the test current also detects the S/ON fault on switch 55. In summary, two test current IIN=0 and IIN= [REF can detect all S/ON and S/OFF switches in the converter of Figure 3.4. Thus, the converter achieves full testability. Not only is the test set finite and easily generated; the testing sequence is also Simple and cheap. In fact, testing consists of merely converting zero and [REF then checking the output It can be seen that it is not always possible to locate the erroneous element from examining the output resulting from the conversion of the test vectors. 4.3 CONCURRENT ERROR DETECTION In order to enhance the reliability of AID converters for real-time applications, an al- ternative current-mode AID converter which possesses the CED capability to detect tran- sient faults and permanent faults, is proposed. 4.3.1 Proposed Concurrent Error Detectable AID Converter Design and Operation Figure 4.1 illustrates a CED scheme with the AL implementation. First, the input cur- rent ltl=IIN is converted during the first time step (or, normal operation phase) and the re- sulting digital data is Stored in a digital Shift register. Then, the complemented current Ia=IREF 'IIN is converted during the second time step (or, recomputing phase). The digital data resulting from both phases are compared to identify an error, if it exists. If the convert- er is fault-free, the converted data resulting from both phases must be bitwise complements of each other. For example, with the reference current suggested in [10], i.e., IREF=100uA, the input current 27uA and its complement 7311A are converted to the 10~bit data D1=(0100010100) and D2=(1011101011), respectively, where both D1 and D2 are bitwise complements. Since the comparison is in a digital manner, a totally self—checking ( T SC) 50 ll... IIN (III) . . —>> AID Converter ‘ > Dlgltal Output Shift Register Time II I l I I I— 1-out-of-2 Time t2 l[REF checker Totally ,REF _ 1341.2) - " Self-Checking ' (TSC) . —bl AID Converter % Comparator Figure 4.1 CED Structure With AL Implementation. 51 checker can be used to identify the error and also to ensure the correctness of the checker circuit. Therefore, a reliably converted data can be attained. Figure 4.2(a) shows the proposed current-mode AID converter with the CED capa- bility. The input current [IN is sampled only once and the current is stored in P1. In order to store the current (IREF-IIN), an additional PMOS current c0pier is needed to hold the cur- rent at the beginning of the data conversion. The input current [IN is copied and stored in P1 by turning on Switches S], S6, and S7, while the current difference (IREF'IIN) is loaded to P2 by turning off S] and S7 and turning on $3, 89, and 810. Once both currents are stored, the current held in P1 and the current held in P2 are converted. The results from both con- versions are compared to identify an error, if it exists. The data conversion process is ex- actly the same as presented previously. Figure 4.2(b) illustrates the switching sequence. In the next section fault diagnosis of the preposed converter is performed to determine the effectiveness of the CED scheme. The fault model underlying this analysis is presented. In this case transient characteristics of the faults are considered. 4.3.2 Fault Model and Fault Effects Similar to the fault model and fault effects discussed previously, a Single stuck-at fault model is also considered. Only one faulty switch occurs at a time and a faulty switch may be permanently or temporarily S/ON or S/OF F. By temporary faults, or transient faults, we mean that the duration of fault behavior is sufficiently short. Transient faults have been very common in today’s digital VLSI design. Since all switches in the AID converter are controlled by the digital clock Signals, a Signal may temporarily change its value from 0 to 1 or from 1 to 0 and cause the switching elements to temporarily malfunction. By per- manent faults we mean the duration of the fault behavior is sufficiently long. In general, the duration of a transient fault is sufficiently short. It is most likely Shorter than the conversion time for the converter, i.e., 4N clock cycles. Here, a fault may occur C4 P2 S9 —o Comparator Output 88 (IO latch) r + I I Plifi 81 S10 32 S4 - IrN IREF N1 83 N2 85 l—r’ IT) in i C‘ I C2 (a) Current NORMAL OPERATION PHASE RECOMPUTATION PHASE SIH MSB Previous bit=l Previous bit=0 MSB Previous bit=1 Previous bit=0 31 [‘fl ‘ 32 _JFLl_L I—Ll—L l—Ll—L l_|_J—L l’Ll‘L l_Ll_L 84 _'§__|—L _i'_L .1—L _l—L J_L __I_L 55 l’l _l—|_ _l—L_ _l—L__ _l_l_ __|—l_ Sal I r—— 87 l—LLJ—L __I_L __l_l_ 38 __ l I I So l‘L ___l_|_ _J_L s. ELI _| l— __n __l‘l —I 1— __rl (b) Figure 4.2 Proposed Current-Mode AID Converter With CED Design. (a) Schematic Diagram. (b) Switching Sequence. 53 during the first time step, or during the second time step, or overlap in both time steps (but the duration is shorter than 4N). If the fault occurs only during the first time step, i.e., the fault disappears during the second time Step, then the converted data D2 is reliable and can be used to check D1 for identifying an error, if it exists. Thus, the fault is detectable. Sim- ilarly, the fault that occurs only during the second time step is also detectable. Now, if the fault occurs after the r—th bit of D1 is being converted and disappears after the (r-l)-th of the D2, for any integer r, then at least the first (r-l) bits of D1 are reliable and can be used to identify the fault. Thus, the fault is detectable and the proposed design can detect all tran- sient faults. If the duration of fault behavior is longer than the time required to complete the first time step and the second time step, all time redundancy CED schemes will no longer pos- sess the property of disjoint error sets, and the errors, thus, cannot be detected. This implies that not all permanent faults are detectable. It would be preferable for the circuits to be de- signed such that they will indicate malfunction during normal operation and will not pro- duce an erroneous result without an error indication. In these circuits, any failures will cause a detectable erroneous output during normal operation, and each fault must not cause an erroneous output without also producing an error signal. The circuits that possess this property are referred to as fault secure circuits. In the presence of single stuck-at faults at the switching elements in the proposed A/ D converter design, four types of errors may be identified. Tables 4.1-4.4 illustrate these error types and their fault effects. The errors that can be definitely detected by the CED scheme are referred to as Type 1 errors, i.e., a Type 1 error causes D1¢D2 for all possible input currents. The errors that cannot be detected are referred to as Type 2 errors, i.e., a Type 2 error causes D1=D2 for all possible input currents. In some cases D1¢D2 for all possible input currents except a few. For these few where D1552, if the resulting data D1 is reliable even in the presence of 54 fault(s), then the circuit is fault secure and such an error is referred to as Type 3 error. On the other hand, if the resulting data D1 is not reliable in the presence of fault(s), then the fault cannot be detected for the application of such input and this error is referred to as Type 4 error. 4.3.2.1 Type1 Errors Type 1 errors occur due to S/ON faults at S2, S3, S4 and 85 and S/OFF faults at S2 and S4. Consider a S/OFF faulty switch S2, the first time step results in D1=(00...0) regardless of the value of the input current being converted. Similarly, during the second time step, the conversion of the complemented current IREF'IIN results in an output data D2=(00...0), i.e., D1¢D2 for all possible input currents. Thus, this is a Type 1 error. Similarly, the S/OF F fault of switch S4 and the S/ON faults of switches S2 and S4 have the same fault effect. Consider the S/ON faulty switch S3. During the first time step, the fault leads to con- structing a P1/N1 CMOS structure, as discussed in Section 2.2. Experimental results have shown that D1=(00...0) and D2=(10...0) for a sufficiently low input IIN; D1=(10...0) and D2=(00...0) for a sufficiently high input IIN; and D1=(00...010...0) and D2=(00...010...0) for the others. Obviously, the error can be detected for either case. Thus, it is a Type 1 errors. Similarly, the S/ON fault of 85 has the same fault effect. 55 Table 4.1: Type 1 Errors - D1¢D2 V IIN =>Definitely detectable Fault Analysis Fault Effects I s2 (s4) S/OFF Zero current held in N1 (N2). _ D1=D2=(00...00) Current not doubled. S2 (S4) S/ON N1 (N2) cancels current from P1 or P2. D1=D2=(00...00) N2 (N 1) holds zero current. Current not doubled. S3 (35) S/ON Output depends on the CMOS structure Pll One bit of D1 equals N1 (Pl/N2). the respective of D2. 4.3.2.2 Type 2 Errors Type 2 errors include S/ON fault at 810 and S/OFF faults at S1, S6 and 510- These errors are caused by either not reading the input current (S/OFF fault at SI), or not reading the reference current (S/OFF fault at 310), or the equivalent fault effects. For example, a S/ OFF fault at 81 implies that a zero current is copied into P1 and thus IREF is copied into P2. Thus, D1=(00...0) and D2=(1 l... 1), i.e., D1=D2 for all possible input currents. Such a Type 2 error is definitely undetectable. Similarly, the S/OFF faults of switch S6 has the same fault effect. Consider a S/OFF fault at Sm. The fault is equivalent to the AID converter using a zero reference current. First, the input current [IN is copied into P1. Then, P2 was expected to copy a current equal to (IREFIIN). However, the zero reference current results in a neg- ative current, 'IIN’ being forced into P2. The operational amplifier saturates, P2 cuts off, and its corresponding storage capacitor charges to the amplifier’s negative saturation voltage. During the first conversion step this capacitor gradually discharges to ground. At the start of the second conversion step, the current in P2 is supposed to be copied into N1; however the new feedback connection presented to the operational amplifier results in a different drain to source voltage for P2. This voltage depends on the charge of the storage capacitor of P2 and of the parameters of both P2 and N1 i.e. of the equivalent impedance of the P2- 56 N1 connection. The current to be converted in the second time step depends on the circuit parameters. Hence it may be effectively regarded as random. Since, during the first time step, P1 holds the current [IN and the reference current IREF=0, the resultant data is D1=(11...1). Since the second conversion step may result in D2=(00...0). D1 may equal D2 for all possible input currents and the error is of Type 2. A S/ON fault at 810 has the same fault effect. In fact, the first conversion step resolves the current Im+IREF resulting in D1=(11...1). The current held in P2 to be converted in the next step is equal to IREF‘ (IIN-I-IREF) l..C 'IIN’ Table 4.2: Type 2 Errors - D1=D2 V IIN => Definitely undetectable Fault Analysis Fault Effects 81 S/OFF Equivalent to 121:0. 15 1=Dz=(00...00) P1 holds zero and P2 holds IREF S6 S/OFF P1 never copies current. D1=D2=(00...00) 1P2 holds IREF. Sm S/OFF Equivalent to IREF=O. D1=D2=(11...11.) ’IIN forced into P2 S10 S/ON [REF always added to the current copied into P1. D1=D2=(11...11.) ’IIN forced into P2 4.3.2.3 Type 3 Errors This set includes S/ON faults at S6, S7, Sg and S9 and S/OFF faults at Sgand 59. Con- sider a S/ON fault at S6. According to switching sequence Shown in Figure 4.2(b), 86 is on for the entire conversion cycle during the first time step. Thus, the resultant data is still cor- rect even in the presence of such a fault. On the other hand, at the end of the first time step, the current held in P1 is 1,, where Ix is less than 1 LSB if the last bit of D1 is 1; otherwise Ix is greater than 1 LSB. Due to the faulty switch S6, the current, Ix, held in P1 is always available during the second time step. This is equivalent to converting the sum of 1,, and the current held in P2 for each bit conversion. If D1¢D2, then the checker will indicate an error. 57 On the other hand, if D1=D2, the converted data D1 is reliable. Thus, the circuit is fault se~ cure and the error is of Type 3. Similarly, a S/OFF fault that occurs at Sg or $9 and a S/ON fault at 89 do not affect the conversion in the first time Step, i.e., D1 is reliable. However, the S/OF F faulty switches Sg and Sp results in D2=(00...0), while the S/ON faulty switches 89 may cause P2 to source a random current. In fact, P2 stores the last current copied into P1. Thus, the circuit is fault secure in the presence of such fault(s) and the error is of Type 3. In the same manner, a 8/ ON faulty switch 88 results in D1=(11...1) for all possible input currents, but provides a re- liable data D2. If there exists, at least, one l-bit in D2, the comparison will identify an error. On the other hand, if D2=(00...0), then D1 provides a reliable result. Thus, the circuit is also fault secure in the presence of such a fault. Consider the S/ON faulty switch S7. The fault causes the current held in P1 to be changed whenever the op-amp is in use. For example, after the input current IIN is loaded into P1, the current (Iret‘lIN) is copied into P2. The faulty switch S7 will cause the gate- source voltage of P1 to equal that of P2. Thus, Inf will be approximately divided between P1 and P2, reflecting any mismatch between the two transistors. During the normal operation phase, when the current held in P1 is compared to the reference current Inf to determine the converted bit value, the faulty switch S7 causes the current held in P1 to be Imf and thus a " 1" results. This implies that D1=(1 1..1 1). Since the fault does not affect the conversion of the current held in P2,the converted data D2 corresponds to approximately Imf/Z. This would have been a Type 1 error if it were not for the case of [IN equal to approximately 1,6,72. 58 Table 4.3: Type 3 Errors - D1 correct or D1¢D2 => Fault secure. Fault Analysis Fault Effects S6 S/ON Normal operation phase not altered. D1 correct. Residual current in P1 always sourced dur- D2 random. ing recomputation phase. S7 S/ON During comparison P1 initially copies 1,“ D1=(11...1 l). and then gets compared. D2: code for Recomputation phase converts a current approximately Inf/2. equal to approximately Imp/2. 88 S/ON Residual current in P2 always sourced dur- D1 random. ing normal operation phase. D2 correct. Recomputation phase not altered. So S/ON Normal operation phase not altered. D1 correct. During comparison P2 initially copies Imf D2=(l 1...11). and then gets compared. Sg S/OFF Normal Operation phase not altered. D1 correct. P2 never copies current. D2=(00...00). 89 S/OFF Normal operation phase not altered. D1 correct. Residual current in P2 always compared D2 random. with Imp 4.3.2.4 Type 4 Errors Type 4 errors include S/ON fault at 81 and IOFF faults at S3, 85 and S7. Consider the S/ON faulty switch S 1. It is assumed that the input current will be varying for real-time ap- plications. The fault implies that the data is converted in the environment where the noise is equivalent to the varied input currents. Thus, D1 and D2 can be any random results. Sta- tistically speaking, the probability of having two random data D1 and D2 as complements to each other is very low. Thus, this is a Type 4 error. Due to the S/OF F faulty switch S7, the current copier with P1 cannot copy any cur- rent. Thus, the current, Ix, held in P1 is the one remained in the previous operation. This results in D1=(00...O) if Ix < IREFr or D1=(1 1...1) otherwise. Since P1 can still source the 59 current 1,, the current held in P2 is (IREF'Ix) and the resultant data D2 is reliable. Therefore, D1=D2 only if either Ix or (IREF'Ix) is less than 1 LSB, D1¢D2 otherwise. This is a Type 4 error. Similarly, due to S/OF F faulty switch S3 the current cepier with N1 cannot copy any current. Assume that the current held in N1 is 1,. then the conditions for D1 to be comple- mentary to D2 can be determined. First, an input current IIN is assumed. Next, two inequal- ities involving IIN’ Ix and [REF are derived based on the assumption that IIN and (INIREF) result in complementary MSBS. If the inequality does not contradict any initial assump- tions, it is kept. The derivation continues for the next bit, and a new set of inequalities are determined and checked for contradictions against the assumptions and the previous ine- qualities. The result, is summarized as follows: MSB=O 80 that IIN S. Ix < [REF-IIN Bit 1 = 1 so that (IREFfImyZ _<_ I, < (IRWIN/2 Bit k = I SO that (kIREF'IIN)/(k +1) S Ix < (IREFI-IIN)/(k+l) where k=0,l,...,N-l, and N is the converter’s resolution. Hence D1=D2 only if IR is very close to [REP/2, and D1¢D2, otherwise. For a reliable design, the chance that the fault oc- curs when the current held in N1 is [REF/2 is rare. Due to the analog nature, this error is of Type 4. Similarly, the fault of S/OF F switch 85 has the same fault effect. 60 Table 4.4: Type 4 Errors - Random data => Most likely detectable Fault Analysis Fault Effects - — S1 S/ON Varyihg IIN afiays sourced to the circuit. D1 and D2 random S3 (S5) S/OFF N1 (N2) do not copy any current but its D1 and D2 random residual current is sourced. S7 S/OFF Residual current in P1 always compared D1 and D2 random Recomputation phase converts the com- plement of this residual current. 4.3.3 Fault Coverage Table 4.5 summarizes the status of error detection for all possible stuck-at faults that may occur at the switching elements in the proposed AID converter design. There exist eight Type 1 errors, four Type 2 errors, five Type 3 errors, and three Type 4 errors. If the fault coverage is defined as the total number of Types 1, 3, and 4 errors over all possible errors, the fault coverage of permanent faults is 80%. A novel current-mode AID converter design with CED capability, where a time re- dundant CED scheme is implemented. The original AID converter [10] is modified by add- ing an extra PMOS current copier to provide the CED capability, thus making the validation of the converted data more reliable. Results have shown that the proposed design can detect all transient faults that occur at the switching elements and most of the perma- nent faults. Some permanent faults cannot be detected due to the unavailability of test pat— terns for real-time applications. However, as discussed previously, two test patterns can be employed to detect the permanent faults. Therefore, it is suggested to randomly apply the two test patterns to the proposed AID converter detecting the permanent faults. The drawback of the proposed design with CED capability is approximately 100% overhead in time which is inherent in all time redundancy schemes. Judging from the VLSI performance measure of AT2 (where A is the chip area and T is the operation cycle time), 61 this is rather a high price to pay. However, the performance penalty associated with time redundancy can be absorbed by the inherent idleness of the processing element [25]. The proposed design is perfectly applied to those systems or subsystems in which the time to process the converted data is as much as twice of the conversion time. The other salient fea- ture is that the proposed design allows users to easily switch between an AID converter with and without CED capability by simply changing the switching sequence without causing any performance degradation. Table 4.5: Concurrent Error Detection Switches S/ON S/OFF Type Type 31 4 2 s2 1 1 s3 1 4 s4 1 1 85 1 4 $6 3 2 S7 3 4 SS 3 3 59 3 3 Sm 2 2 CHAPTER FIVE CONCLUSIONS This chapter summarizes the major contributions of this thesis and outlines the direc- tions for future developments. 5.1 SUMMARY OF MAJOR CONTRIBUTIONS This thesis achieves test pattern generation for the current-mode AID converter pro- posed in [10]. Results Show that during the manufacturing test, the converter circuit can be tested for all Single stuck-at faulty switching elements by applying two test currents at the input. In addition a novel current-mode AID converter design with CED capability, where a time redundant CED scheme is implemented. The original AID converter [10] is modified by adding an extra PMOS current copier to provide the CED capability, thus insuring the validation or rejection of the converted data in the presence of any stuck-at-fault model at the switching elements during real-time operation. Results have shown that the proposed design can detect all transient faults and most of the permanent faults. The other salient fea- ture of the proposed design is its versatility. The user can easily switch between an AID converter with and without CED capability without causing any performance degradation by simply changing the switching sequence. 62 63 5.2 DIRECTIONS FOR FUTURE DEVOLOPMENTS In the process of fault effect analysis, a new current cepier cell has been established. The CMOS current copier has the advantage of handling bipolar currents making it attrac- tive for circuit application where the direction of the current(s) is not known a priori. A new successive-approximation current-mode converter is being developed where the CMOS copier represents the core of the reference generation circuit [32]. This work has focused on fault diagnosis pertaining to a Specific fault model at Spe- cific elements of the converter circuit. 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