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This is to certify that the
dissertation entitled

An Investigation of Hot Electron
Induced Degradation for Silicon
Bipolar Transistors

presented by

Chi-Jung Huang

has been accepted towards fulﬁllment
of the requirements for

PhD

 

degree in Electrical Engineering

 

M47» professor

DatelZ17/l992

MS U 1': an Afﬁrmative Action/Equal Opportunity Institution 0-12771

 

, LIBRARY
1 Michigan State
i Universlty ‘

 

 

 

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TO AVOID FINES return on or before due due.

DATE DUE DATE DUE DATE DUE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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T—T-FT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AN INVESTIGATION OF HOT ELECTRON
INDUCED DEGRADATION FOR SHJCON
BIPOLAR TRANSISTORS

By

Chi-Jung Huang

A DISSERTATION
Submitted to
Michigan State University

in partial fulfillment of the requirement
for the degree of

DOCTOR OF PHILOSOPHY

Department of Electrical Engineering

1992

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ABSTRACT

AN INVESTIGATION OF HOT ELECTRON INDUCED DEGRADATION FOR
SILICON BIPOLAR TRANSISTORS

By

Chi-Jung Huang

Bipolar transistors were electrically stressed at -75, 23, 175, and 240 C for up to
1000 hours with a constant reverse bias of 4 volts applied to the emitter-base junction.
Additionally, electrical stress experiments were performed for reverse biases of 3.5, 4.0,
4.5, and 5.0 volts for 200 hours at 23 C. The rate of degradation was observed to be
dependent on the stress voltage and the ambient temperature. .For larger reverse bias
voltages, the rate of degradation was larger, and for higher temperatures, the rate of
degradation was generally smaller. However the 23 C degradation was greater than the
-75 C degradation for the ﬁrst few hours of stress. '

An investigation of the degradation was done by developing an electron energy
simulation program. The electron energy simulation program was used to solve for the
electron energy under experimental stress conditions. The simulator had a band-to-band
tunneling model implemented to solve for the reverse-bias stress current. For the
experimental stress conditions, the number of hot electrons above a threshold damage
energy was seen to be primarily controlled by the tunneling process with a larger number
of hot electrons at higher temperatures. The simulations explain the increasing
degradation rate when the ambient temperature changes from -75 to 23 C.

The decreasing degradation rate from 23 to 240 C was studied by using post-
degradation annealing experiments. A simultaneous annealing effect was found to

repassivate some of the hot electron produced states at higher ambient temperatures. A

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degradation/annealing model is proposed to include both degradation and annealing
effects. The simultaneous annealing effect explains the decreasing degradation rate for
ambient temperatures from 23 to 240 C. The degradation/annealing model predicts the
saturation of the degradation phenomena at higher stress temperatures.

A degradation model which relates the surface recombination velocity to the
number of interface states was implemented into a device simulation program. The
device simulation program which includes the energy simulation technique can be
applied to predict the rate and magnitude of the hot electron induced damage when the

device geometry, doping level, or stressing/operating conditions are varied.

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ACKNOWLEDGNIENTS

I would like to thank my academic advisor, Dr. Timothy A. Grotjohn. This
dissertation would not have been produced without the many valuable suggestions and
inspiring discussions from Dr. Grotjohn.

I would also like to acknowledge my appreciation to C. J. Sun and Professor D.
K. Reinhard for their assistance during this investigation.

This work was performed as part of a research contract from IBM Corporation,
East Fishkill, NY. The suggestions and comments of C.-C. W. Yu (IBM Corporation,
Kingston, NY) are acknowledged and appreciated.

Finally, I am grateful to my wife, Su-Yun, for her support and encouragement.

iii

 

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Table of Contents

LIST OF TABLES .......................................................................................... vii

LIST OF FIGURES ......................................................................................... viii

Chapter 1. Introduction .................................................................................... 1
1.1 Motivation ...................................................................................... l
1.2 Review of Previous Work ............................................................... 4

1.2.1 Hot Electron Induced Degradation Experiments and

hFE or Base Current Degradation Modeling ...................... 4

1.2.2 I-lot Electron Induced Degradation Mechanism

Modeling ......................................................................... 8

1.2.3 Hydrodynamic Transport Model ...................................... 11

1.3 Statement of Purpose ...................................................................... 12

1.4 Thesis Preview ............................................................................... 13
Chapter 2. Experimental Bipolar Transistor Degradation Studies ..................... 15
2.1 Device Description ......................................................................... 15

2.2 Device Characterization .................................................................. 19

2.3 Unstressed BJT Characteristics ....................................................... 22

2.4 DC Reverse Bias Stressing Experiments ....... q .................................. 22

2.4.1 Temperature Dependence of Reverse Bias Induced
Degradation Experiment .................................................. 22
2.4.2 Voltage Dependence of Reverse Bias Induced
Degradation Experiment .................................................. 35
2.4.3 Short Time Scale Stress ................................................... 45
2.4.4 Temperature Dependence of the Pre-stress and Post-

stress Base Current ........................................................... 49

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2.5 AC Stressing .................................................................................. 54
2.6 Thermal Annealing Experiments .................................................... 56
Chapter 3. Numerical Models of Bipolar Junction Transistor ........................... 62
3.1 Model History ................................................................................ 62
3.1.1 Moment Equations ........................................................... 63

3.1.2 Drift-Diffusion Model ...................................................... 65

3. 1.3 Hydrodynamic Transport Model ...................................... 66

3.2 Numerical Solution Implementation ............................................... 68
3.2.1 Discretization ................................................................... 68

3.2.2 Box Integration Method ................................................... 72

3.2.3 Grid Structure .................................................................. 73

3.2.4 Numerical Solution .......................................................... 76

3.2.5 Boundary Conditions ....................................................... 81

3.3 Physical Effects .............................................................................. 82
3.3.1 Bandgap Narrowing and Auger/SRH Recombination ....... 82

3.3.2 Band-to-Band Tunneling Mechanism ............................... 84

3.4 Simpliﬁed Hydrodynamic Transport Model ................................... 87
3.5 Monte Carlo Method for HTM Parameter Extraction ...................... 91
3.6 List of Parameters for Device Simulations ...................................... 92

Chapter 4. Analysis and Simulation of Unstressed Bipolar Transistor

Device Characteristics .................................................................... 97
4.1 Reverse Bias Stress Conditions ....................................................... 97
4.2 Gummel Characteristics .................................................................. 105

Chapter 5. Simulation of Hot Electron Induced Degradation for Bipolar

Transistors ...................................................................................... l 12

 

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vi
5.1 Hot Electron Current Simulations ................................................... 1 12
5.2 Degradation Model ......................................................................... 113
5.3 Simulation of Degraded Characteristics .......................................... 117
Chapter 6. Degradation/Annealing Model for Bipolar Transistors .................... 123
6.1 Hot Electron Current Simulations ................................................... 123
6.2 Degradation and Annealing Model ................................................. 126
6.3 Temperature Dependence ............................................................... 129
Chapter 7. Conclusions .................................................................................... 136
Appendix A. Discretization of J and S in Scharfetter-Gummel Form ............... 139
Appendix B. Input File Description for Device Simulation Program ................ 144
Appendix C. Device Simulation Program Structure Outline ............................. 158

LIST OF REFERENCES ................................................................................. 161

 

 

LIST OF TABLES

Table Page
3.1 5 and T. at -75, 23, 175, and 240 C ........................................................... 95
3.2 Parameters for device simulation program ................................................. 96
4.1 The -4 V reverse bias current at -75, 23, 175, and 240 C ............................ 106
6.1 Parameters for ﬁtting Equation (6.3) to the experimental data .................... 134

vii

 

 

LIST OF FIGURES

Figure Page
1.1 Schematic diagram for transistor geometry ................................................ 2
1.2 Hot electron induced degradation mechanisms ........................................... 3
2.1 Layout of TIN3 transistors ......................................................................... 16
2.2 Layout of TOUT transistors ....................................................................... 17
2.3 Pin out conﬁguration of transistors ............................................................ 18
2.4 Doping proﬁle for devices used in this study .............................................. 20
2.5 Circuit conﬁguration for measurement ....................................................... 21
2.6 Diagram for measurement setup ................................................................. 23
2.7 Forward biased IEBO versus VBE characteristics .......................................... 24
2.8 Reverse biased 11330 versus Vera characteristics ........................................... 25
2.9 Forward biased ICBO versus VBC characteristics .......................................... 26
2.10 Reverse biased ICBC versus VBC characteristics ......................................... 27
2.11 Current gain characteristics of TIN3 and TOUT transistors ...................... 28
2.12 Gummel characteristics of TIN 3 and TOUT transistors ............................ 29
2.13 Circuit for stressing transistors ................................................................. 30

2.14 The use of environmental chamber or oven to provide ambient

temperature ............................................................................................. 30
2.15 Current gains for stressing at -75 C for various times ............................... 32
2.16 Gummel plots for stressing at -75 C for various times .............................. 33
2.17 Gain degradation versus time for several devices stressed at -75 C ........... 34

2.18 Normalized current gain for stress temperatures of -75, 23, 175, and
240 C ...................................................................................................... 36
2.19 Base current change versus charge at -75, 23, 175, and 240 C .................. 37

viii

 

 

ix
2.20 Pre-stress and post-stress IEBO versus VBE ................................................. 38
2.21 Circuit diagram for stressing TOUT transistors ........................................ 39 .

2.22 Gummel plots for unstressed and 3.5, 4.0, 4.5, 5.0 volts reverse bias

stressed characteristic .............................................................................. 41
2.23 Base current change versus stress charge for 3.5, 4.0, 4.5, 5.0 volts

reverse bias stressed characteristics ......................................................... 42
2.24 Reverse bias stress current versus time for transistors stressed at 3.5,

4.0, 4.5, and 5.0 volts. ............................................................................. 43
2.25 Base current change for transistors stressed at -4.5 volts .......................... 44
2.26 Fluctuations of the current gain for transistors subjected to short

stress periods ........................................................................................... 46
2.27 Base and collector current fluctuations for transistors subjected to

short reverse stress periods ...................................................................... 47
2.28 Base and collector current ﬂuctuations for transistors subjected to

short reverse stress periods followed by subsequent forward biases ......... 48
2.29 Gummel characteristics for a pre-stress TIN3 transistor at -60, -30, 0,

30, 60, 90, 120 C ..................................................................................... 50
‘ 2.30 Gummel characteristics for a post-stress TIN3 transistor at -60, -30,
0, 30, 60, 90, 120 C ................................................................................. 51

2.31 Comparison of nonideal tunneling current model to measured base

current at -60, -30, 0, 30, 60, 90, 120 C ................................................... 55
2.32 AC stressing results .................................................................................. 57
2.33 Base current change versus annealing time at 175 and 240 C ................... 59
2.34 Base current change versus annealing time at 240 C ................................. 61
3.1 Notation for mesh points used in discretization .......................................... 69
3.2 Physical quantities and unit normal vector for box integration method ....... 74

3.3 Three common grid structures .................................................................... 75

x

3.4 Example mesh and point assigning scheme for terminating line mesh ........ 77
3.5 Diagram of band-to-band tunneling mechanism ......................................... 86
3.6 Comparison of DD and HTM for a reverse biased pn junction .................. 90

3.7 Electron mobility versus electron temperature at ambient temperatures

of -75, 23, 175, and 240 C .......................................................................... 93
3.8 Electric ﬁeld used and the ﬁt of simpliﬁed HTM to Monte Carlo

simulation results at 23 C ........................................................................... 94
4.1 BJT structure for PISCES-II simulation ..................................................... 98
4.2 Lateral electric ﬁeld for reverse biases of 2, 3, 4 volts for extrinsic

base and emitter spacings of 0.4 and 1.0 um .............................................. 100
4.3 Measured reverse bias stress current versus VBE 101
4.4 Potential plots for reverse biasing a transistor with and without oxide

ﬁxed charge ............................................................................................... 103

4.5 Reverse bias stress currents and lateral doping proﬁles predicted by

band-to-band tunneling model .................................................................... 104
4.6 Simulated unstressed current gain characteristics ...................................... 107
4.7 Comparison of simulated current gain to measured data ............................. 108
4.8 Electric ﬁeld along emitter, base, collector of transistor ............................. 109

4.9 Comparison of simulated unstressed Gummel characteristics to

measured data ............................................................................................ 111
5.1 Bipolar transistor structure simulated ......................................................... 114
5.2 Hot electron current densities for reverse biases of 3.5, 4.0, 4.5, and

5.0 volts ..................................................................................................... 115
5.3 Simulated surface recombination velocities for stress times of 1, 24,

and 500 hours ....................................................................... . ..................... l 18
5.4 Simulated surface recombination velocities for reverse biases of 3.5,

4.0, 4.5, and 5.0 volts ................................................................................. 1 l9

 

 

 

xi
5.5 Comparison of simulated and measured base current for stress times of
0, l, 24, and 500 hours ............................................................................... 121
5.6 Comparison of simulated and measured base current for reverse biases
of 3.5, 4.0, 4.5, and 5.0 volts ...................................................................... 122
6.1 Hot electron current densities for -4 V reverse bias at -75, 23, 175, and

240 C ......................................................................................................... 124

6.2 Experimental and modeled degradation and annealing data ........................ 128
6.3 Changes in the base current for the modeled and measured values ............. 130
6.4 Annealing data for devices stressed at different temperatures ..................... 131
6.5 Annealing of base current for annealing at 175 and 240 C .......................... 133
8.1 Example grid structure layout .................................................................... 146
8.2 Doping proﬁle by FIY command ..................................................... ~ .......... 150
C1 Device simulation program algorithm ........................................................ 159

Chapter 1

Introduction

1.1 Motivation

With each advancement in the technology of semiconductor device design and
fabrication, the associated reliability problem has always been an important issue. In
particular, an understanding of the degradation mechanisms and the establish of a
degradation model are essential for the prediction and improvement of device lifetime.

For silicon bipolar transistors, current gain (13) degradation as a result of
avalanching the emitter-base junction was observed before 1970 [1-3]. The cause of the
avalanche induced degradation was ﬁrst thought to be related to ionic contamination
existing within the device oxide [2]. Collins [3] and McDonald [1] were able to show
that the avalanche induced degradation for low current gain was in fact due to hot
carriers creating surface states within a transistor's depletion region. Several later
improvements were made to avoid operating BJT's at avalanching biases, an example is
the termination of input lines by clamping diodes in integrated logic systems.

Recently, the trends in bipolar transistor scaling have resulted in highly energetic
carriers at the reverse biased emitter-base junction for below-avalanche voltages. A
schematic diagram of the BJT geometry and the local high ﬁeld region where damage is
most likely to occur is shown in Figure 1.1 [4]. Hot carriers were reported to cause
degradation in advanced technology transistors operated at biases which were less than
avalanche bias conditions in several studies [5-17]. The reported mechanisms include hot
carrier created interface states formed by breaking bonds at the interface and/or injected

carriers trapped in the oxide producing oxide ﬁxed charges as shown in Figure 1.2.

 

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region is the local high ﬁeld region where hot electron induced damage is most

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Based on their experimental results, several researchers developed degradation models
that predict the degradation rate as a function of the stress conditions. These works were
either based on simpliﬁed approximations for the hot electron energies or were empirical
and modeled the macroscopic quantities. The exact amount of hot carriers responsible for
the degradation was not solved by these works and a device level model suitable for the
prediction of device degradation when a device design changes is yet to be established.
The purpose of this study is to analyze the hot electron induced degradation
mechanism produced by degradation conditions and to provide a relationship, at a device
level, between the degradation and the hot electrons produced. This will be done by ﬁrst
using hot electron induced degradation experiments from which the actual degradation
process is recorded. Second, by using an electron energy simulation technique which
solves for the hot electron current along the surface high ﬁeld region for bipolar
transistor structures. By correlating these two results, an understanding of the mechanism
and process of hot electron induced degradation can be improved. Additionally, a device
degradation model that predicts device degradation based on the device operating
conditions is established so that the reliability problem can be evaluated at the time of

device design by simulation techniques.

1.2. Review of Previous Work

1.2.1 Hot Electron Induced Degradation Experiments and hFE or Base Current
Degradation Modeling

Experimental degradation and reliability studies for the bipolar transistor can be
traced back several years. The degradation process and mechanism vary depending on
the device design and the technology of fabrication. This study will focus only on the hot
electron induced degradation in advanced bipolar transistor structures.

Hot electron induced degradation in advanced self-aligned sidewall spacer NPN

bipolar transistors was observed by Petersen et. a1. [6]. The transistors were operated

 

 

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with their emitter-base junctions reverse biased and collectors opened. The caniers were
injected by illumination near the edge of the emitter-base depletion region with a 5 mW

He-Ne laser source. After the application of the reverse-bias produced hot electrons, the

forward base current was measured as a Gummel plot (13, IC vs. VBE for VBC = O) to

determine the amount of current change A13. The measured characteristics taken before

and after the constant current stress showed that the increase of the low level base current
after stress was accompanied by a shift in the ideality factor from near 1 to almost 2. This
indicated the probable cause for the higher base leakage current to be an increase of

interface state density in the sidewall oxide between the emitter and base. The plot of

AIB versus stress charge Q(m'-t) through the emitter base junction for various applied

stress voltages showed that the AIB increased nonlinearly with Q for stress voltages

above a critical value.

The work done by Joshi [8] showed hot carrier induced degradation in a poly-
emitter bipolar transistor fabricated by a BiCMOS process. Transistor gain degradation
was studied by reverse biasing the emitter base junction under DC, pulsed, and AC
conditions. For the ceramic packaged devices, extended temperature (-55 C to 175 C)
tests were performed. The B degradation was seen at both low emitter-base forward bias
current levels (IC =10 HA) and high current levels (IC = 1 mA). From the Gummel plot,
the emitter-base ideality factor ﬁrst increased from 1 to 2 for low current levels and
subsequently for the entire range of IB up to the Gummel knee current. Constant current
stressing of the reverse biased E-B junctions revealed that B degradation depends on the
stress current IR and the stress duration t. An excellent correlation was observed between
the stress charge defined as IR-t and B degradation. Joshi thus proposed the model

éﬂ=K110gQ+K2 ;Q>QC (1.1)

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where AB is the change in the current gain after stress, [30 is the initial current gain, K,
and K2 are ﬁtting constants, and QC is the critical charge beyond which the degradation

cannot be recovered by annealing at elevated temperatures.

Burnett et. al. [9] investigated Joshi's model over a range of reverse bias currents
and device sizes for self-aligned polysilicon emitter transistors. Unlike the result of
Joshi's model, AB/Bo for different values of IR did not fall on the same curve and the
individual curves were not straight lines. Burnett, instead, plotted the logarithm of A13

versus logarithm of Q and found that the plots are straight lines with approximately the

same slope for various IR. Burnett proposed the empirical model
AIB=C-I§‘*“-t“ (1.2)
where m, n, and C are ﬁtting parameters.

Li et. al. [7] and Hackbarth et. a1 [10] investigated the current components for
both the inherent and stressed induced leakage currents for heavily doped emitter-base
junctions of polysilicon self-aligned bipolar transistors. By using devices with various
perimeter dimensions and by investigating the temperature dependence of bipolar
transistor I-V characteristics for both forward and reverse bias voltages over a
temperature range of 90 to 390 K, a band-to-band tunneling current and a trap-assisted
tunneling component were found to be the inherent reverse leakage component in [7] or
[10], respectively. Reverse-bias stress was found to produce interface states which
induced a Poole-Frankel electric ﬁeld enhanced generation/recombination leakage
current [10] or to cause an increase in trap densities and subsequently a trap-assisted
tunneling nonideal current [10]. The induced Al}; was observed to eventually saturate at
some maximum level [11]. A ﬁrst order relation between A1}; and stress charge Q was

found as
A13: AIB,sat(l-exp(-Q/a)) (1.3)

where A135,“ indicates the maximum current degradation the device will be subjected to,

and (1 indicates at what accumulated charge the device degradation will become

 

 

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considered two time constants: the surface state generation time constant 18 and the

healing time constant I h,

a “T”;— (1.4)

where N is the total number of interface states that can be created, and ANSS is the newly

created surface states. The stress induced leakage current is proportional to ANSS and

rises according to (1.3).

A temperature dependence study on the emitter-base reverse bias stress
degradation was done by Momose et. al. [13] for npn bipolar transistors fabricated by a
ion-implanted emitter BiCMOS- process. They found that the reverse-bias stress-induced
degradation is largest around 50 C. By applying a MOSFET structure simulation, they
modeled both trapped electrons and interface state creation for the degraded
characteristics. The interface state creation in the oxide near the emitter-base junction
was modeled using an increase in the recombination velocity at the surface and was
found to be in agreement with experimental results. They concluded that interface state
creation is the dominant degradation mechanism.

In 1990, Burnett et. a1. [15] reported the reverse bias induced degradation at 110
and 300 K for BJT's fabricated by BiCMOS technology. The rate of degradation was
observed to be four times larger at 110 K than at 300K for the same reverse voltage and
ten times larger for the same stress current. The increased degradation at lower
temperature is consistent with the increase severity of hot carrier damage in MOSFET's
at lower temperatures [18,19]. The BIT degradation was modeled as *

A1,, = Drgratc (1,6)
where IC is the collector current density. D, a, b, and c are ﬁtting parameters.

Although the empirical models developed can be used for lifetime prediction,

they provide little insight in the degradation for different device designs. An

 

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the ﬁtting parameters.

1.2.2 Hot Electron Induced Degradation Mechanism Modeling

One of the earlier works of modeling the avalanche induced degradation
mechanism was done by McDonald [1]. He was able to explain the degradation current
by an increase in the surface recombination velocity So as a result of avalanche induced
surface state formation within the surface depletion region. Bysumming the uniform,
nonavalanche associated surface recombination velocity So and the localized avalanche-

induced surface recombination velocities 80A, a total surface recombination velocity was

obtained. To obtain the degradation current, a summation of the surface recombination
current in each of n intervals along the surface depletion region was calculated where in

each interval the surface recombination rate US]. was calculated. The total degradation

current was expressed as

n
Ims(Vg) = C12, Usj(VG)Asj (1.7)
j=1

where VG is the applied gate voltage and As]. is the area associated with interval j. An
agreement between the experiment and the model was found by assuming an avalanche
induced surface recombination velocity of 100 cm/s localized within 0.1 um on either
side of the emitter-base metallurgical junction. Experimental evidence was also presented
for localized charge trapping within the oxide over the emitter-base junction as a result of
avalanching condition.

Bulucea [20] developed a theory to calculate the injection probability deﬁned as
the fraction of the avalanching electrons which acquire sufﬁcient energy to surmount the

Si-SiO2 energy barrier. The number of these high energy electrons actually entering the

oxide is determined by a scattering function which allows some high energy electrons to

 

enter the oxide uh:

eicctrun energy in t.

where a = 1.874. b

Bergeron e1
mused by oxide tr
collector and em:
injected and ‘ .en 1
her formed lead

*3 PV-bability 0f

1there A‘ is the l

aimed min the \

Where jt is ‘hc it
.nl‘lﬁl’ and Colic

‘0‘“
«'1va

“Warm in th

35% .
“3mm

9

enter the oxide while the rest are reflected. By assuming a Maxwellian distribution of

electron energy in the avalanche current, the injection probability is derived to be
P1= anp(-EB lkTe) for 133/10e 2 4 (1.8)

where a = 1.874, b = 0.926, BB is the energy barrier, and Te is the electron temperature.
Bergeron et. al. [5] proposed a model for the failure of lateral bipolar transistors
caused by oxide trapped charge forming a short-circuiting inversion layer between the
collector and emitter. The trapped charge in the model was due to the electrons being
injected and then trapped in the oxide. Once enough electrons were trapped, an inversion
layer formed leading to the transistor failure. By assuming a Schottky emission process,

the probability of electrons entering the oxide is given by

_ * 2 _ ¢B
P_A (ch) exp[ kT] (1.9)

e

 

where A* is the Richardson constant, and in; is the energy barrier. The electron density

injected into the oxide at any time t is given by
t
1 .
=§£Pcht (1.10)
where jc is the junction leakage current. By examining the inversion layer between the

emitter and collector, the time of failure is deﬁned to be the time to reach the onset of
inversion produced by the trapping of hot electrons in the dielectric region. The electron

temperature in this model was calculated based on the given electric ﬁeld as
31:

32 (1.11)

Tcs'l‘E
C

where ll is the mobility, c is the velocity of sound, and E is the electric ﬁeld [21].

So far in the literature, the device level modeling of the hot electron degradation
for bipolar transistor has not been discussed in detail due to (1) the complexity of
extracting the electron energy when operating at hot electron induced conditions and (2)

the much more difﬁcult task of simulating an advance technology transistor. On the other

 

hand. the mode}
this a few of the

Robiin et
elation density 1
trapping probahii

the interface is

“here 1. is the 1
and E and 03 3,
studies [1.1] hzne
C

A. The pruhdhm

tu me mﬁ‘ut‘e u

10

hand, the modeling of MOSFET degradation has been very active, the following lists
only a few of the studies that represent this approach for MOSFET degradation. .

Roblin et. al. [22] modeled the hot electron trapping rate by considering the
electron density in the channel, the frequency of ballistic launching of electrons, and the

trapping probability. The probability P12 of a hot electron overcome the barrier height at

the interface is
1 ﬂe-¢B/E}‘

P125-
4%

where A, is the mean free path (assumed constant) of hot electrons between collisions,

(1.12)

and E and 11’s are the electric ﬁeld and the energy barrier at the interface. Experimental
studies [14] have reported 1 to be a function of electron energy and is between 72 to 135
X. The probability P3 of an electron scattered at a distance y from the interface traveling
to the interface without further collision is given by

P3 = e'“, (1.13)
And the probability P4 of an electron injected in the SiO2 being captured by empty traps
is given by

P4 = (NM — N,,.,,p(t))o,,.,p (1.14)
where Nmax is the initial density of empty traps per unit area, Nmpu) is the density of
traps ﬁlled per unit area, and am, is the trapping cross section that depends on the

fabrication technology. The product P12P3P4 represents the probability for a ballistic

electron located in the channel at a distance y from the oxide interface becoming trapped

in the oxide. Finally, the rate for hot-electron trapping in the oxide was expressed as

dN ..
d‘f" = P4(I)IORb(E)°P12(E)' P3(y)n()’)dy (1.15)

where Rb is the launching frequency [23] and n is the carrier density. (1.15) as well as the

 

two dimensional simulation program PISCES [24] was then used for the MOSFET

structure by iteratively solving (1.15) and simulating a PISCES solution.

 

Man) “1‘
electron stress. :11
using surface scat

These w"
the carrier energj
and 'he electric ti
these semiernpiri.

Hunuchi
dimensional sim

model that relate.

113 Hydrod} n:

Numeric:
01 semiconductu
htices include
electron coming}
Meade! I'HTMJ. t
elem” and hvl

that the Valuer

Cl

Skunk-(m £11.30 \

11

Many works closely parallel Roblin's work, they are [25] which did AC hot
electron stress, and [26] which incorporated the degradation of the surface mobility by
using surface scattering due to interfacial charges.

These works were based on the classical drift-diffusion model. which determined
the carrier energy by using semiempirical relationships between the carrier temperature
and the electric ﬁeld. For nonequilibrium hot carrier energy calculations, the accuracy of
these semiempirical relationships becomes questionable.

Horiuchi et. al. [27] included the carrier energy transport physics in a two
dimensional simulation for the MOSFET structure. Their purpose was to establish a

model that related the device lifetime with hot electron substrate current produced.

1.2.3 Hydrodynamic Tramport Model

Numerical simulations have been widely used to provide insight into the physics
of semiconductor devices. Two numerical models for the solution of semiconductor
devices include (1) the Drift-Diffusion (DD) model, which solves for the Poisson,
electron continuity, and hole continuity equations, and (2) the Hydrodynamic Transport
Model (HTM), which solves for the Poisson, electron continuity, hole continuity, and
electron and hole energy conservation equations. The classical DD simulation assumes
that the carrier energies are in equilibrium with the lattice temperature, whereas the HTM
simulation also solves for the carrier energies.

The method of including the carrier energy in the device simulation is to solve the
energy conservation equation in addition to the continuity equation and Poisson equation
[28,29]. The HTM models the carrier mobility as a function of the average carrier energy
instead of the local electric ﬁeld. Thus, the carrier energy can be different from the lattice
temperature. Particularly in submicron GaAs devices where carriers exhibit strong
nonstationary behavior, many researchers found the HTM model more accurate since it

includes the momentum and energy relaxation effects [30,31]. Only a few papers have

 

apﬂlc‘d [116 1

active mode
DD and the 1
transpirt. Fo'
emitter voila:
region when
exceeding 2'“
found that th
equilibrium ‘
Sulhxlugh this
3.1. [:91 par,
ccefticients v
parameters (
parameters. t
13:1 Simulate
1‘56szth 1
111m 911'; K.
’45s emitter or
SO fa
1* WVersc
mime bias
h§rhdﬁliﬂn‘
11TH to Cu:

“”161 51nd th

12

applied the HTM simulation method to silicon bipolar transistors. In 1983, Cook [28]
ﬁrst applied the HTM to simulate simpliﬁed one-dimensional bipolar transistors for the
active mode of operation. The same device structure was simulated using the classical
DD and the HTM simulation methods to compare the effects of including the hot-carrier
transport. For an npn bipolar transistor with a base width of 150 nm and a collector to
emitter voltage of 2.5 V, carrier heating was seen to occur in the collector-base depletion.
region where the potential drop accelerates the electrons. An electron temperature
exceeding 2000 K was observed for a collector current density of 0.086 mA/ 1.1 m2. It was
found that the classical DD assumption, which assumes that the carriers are in thermal
equilibrium with the lattice, is invalid for the BJT device electron energy simulated,
although this does not greatly affect the terminal I-V characteristics. The work by Du et.
al. [29] paralleled that of Cook's work, but differed in that the carrier transport
coefﬁcients were introduced in a more general form and that the effects of various model
parameters on the hot carrier phenomena were examined. With proper choice of
parameters, the carrier temperature results were similar to Cook's work. Forghieri et. al.
[32] simulated an npn bipolar transistor in a two dimensional structure. For a BJT of
base-width 100 nm, VBE of 0.67 V and VCE of 1.67 V, the peak electron temperature was
about 900 K. The temperature maximum occurred near the collector-base junction under
the emitter contact where the current density is nearly parallel to the electric ﬁeld.

So far in the literature, there has been no modeling study devoted to the emitter-
base reverse bias condition of bipolar transistors. In order to explore the energies of
reverse bias induced hot electrons and to relate the hot electrons with BJT performance
degradation, this study developed an electron energy simulation technique based on the
HTM to extract the number of hot electrons in reverse biased conditions. The HTM

model and the electron energy simulation technique are described in Chapter 3.

 

13 Statement 1

The purpo
degradation pheni
the hot electron 1
induced degradati.
this research is to

'f‘iECd L111 del'lCC’ d8

1,4 Thesis Pre‘

Chapter 3
measurement pro
experiments are dc

The numer
simulation prograr
forward bias degra

he HTM is dexelt

\A
v‘. 3'1

1:9-

.u.tions. The m
m condition is
C‘ i "

n. simulation p
harmed.

Chapter 4 a
Emir. -
g 4 4nd reve
milllfillt'
.111 resul ‘
.. L811
Charter 5 d

ﬁltra- .-

13
1.3 Statement of Purpose

The purpose of this work is to improve the understanding of the hot electron
degradation phenomena in silicon bipolar transistors. In particular, this work quantiﬁes
the hot electron induced degradation in silicon bipolar transistors using hot electron
induced degradation experiments and electron energy simulations. Another objective for
this research is to develop a model that is suitable for the prediction of device lifetime

based on device designs and device operating conditions.

1.4 Thesis Preview

Chapter 2 describes the bipolar transistors used in this study. The stressing and
measurement procedures are explained. The results of several BJT degradation
experiments are described in this Chapter.

The numerical models for BJT's are described in Chapter 3. A classical DD
simulation program is used both to extract the reverse bias stress conditions and the
forward bias degraded characteristics. An electron energy simulation technique based on
the HTM is developed to extract the hot electron current during BJT reverse bias stress
conditions. The implementation of the band-to—band tunneling mechanism for the reverse
stress condition is also shown in this chapter. Finally, the use of a single particle Monte
Carlo simulation program to extract energy related parameters for the HTM model is
presented.

Chapter 4 analyzes the unstressed BJT characteristics in both the emitter-base
forward- and reverse-bias current regions. Measurement results are compared to
simulation results for unstressed BJT characteristics.

Chapter 5 develops the hot electron degradation model by using the electron
energy simulation technique and a surface state creation model. The subsequent
prediction of degraded transistor characteristics and their comparison to experimental

degradation results are also shown in this chapter.

 

empirical dc:
and annea'ir
temperature.

Final:

14

Chapter 6 applies the electron energy simulations to extract the amount of hot
electrons at four different temperatures. At higher temperatures, a simultaneous
annealing effect is found to be important in describing the degraded characteristics. An
empirical degradation/annealing lifetime model is formulated to describe the degradation
and annealing behavior for BJT's stressed in ambient temperatures other than room
temperature. 9

Finally, conclusions and contributions are summarized in Chapter 7.

 

Experlm

2.1 DeViCe D

O't'dr :1
Each (‘11? Cm
iabncak‘d 1‘} L‘
1361.1th “1‘“
[mcﬂble “5 [1‘
had Semis.) 3‘
snail) “5 UN?
ml) in the e'
degradalit‘n ‘5

layouu 101 TD

h .
upping proﬁle

except for the
current due 10 1

381106
as we“
.e p

s'. it) '
rlgtt base cont
Ce." '

curnc packagr.
3335 “

Chapter 2

Experimental Bipolar Transistor Degradation Studies

2.1 Device Description

Over 200 wire bonded chips were provided to Michigan State University by IBM.
Each chip contained three test devices (named TIN3, TOUT, and TD4) which were
fabricated by conventional oxide isolation methods and had a base width of 0.35 pm
[36]. These devices did not include emitter or base polysilicon structures. The chips were
traceable as to location on the wafer, wafer number, and job number. TOUT and TD4
had Schottky diode clamps and TIN3 did not. The device used most extensively in this
study was TIN3 which had an emitter area of 4.3 [,me 2.5 1.1m. TOUT devices were used
only in the experiments of studying voltage dependence of reverse bias induced
degradation as described in Section 2.4.2 and had the same emitter area as TIN3. The
layouts for TIN3 and TOUT transistors are shown in Figures 2.1 and 2.2 respectively.
All I—V characteristics measured for different TIN3 and TOUT devices show only slight
device to device variations. The fact that the TIN3 and TOUT devices had the same
doping proﬁle and emitter region layout resulted in almost identical I-V characteristics
except for the collector-base junction. TOUT devices showed higher collector base
current due to the Schottky diode clamp between the collector-base junction. All three
devices were provided with double collector contacts, double emitter contacts, and a
single base contact as shown in Figure 2.3. The chips were wired bond by IBM in 28 pin
ceramic packages. For TIN3, the pin-to-pin resistance between the two collector contacts
was approximately 21 9 whereas for TOUT, the resistance was approximately 5.2 (2.

For the two common emitter contacts, the pin-to-pin resistance was approximately 8.5 Q.

15

 

Col

 

[3356

0ft“

 

 

 

 

 

10.3

\\\\\\\\\\\\\\\\\\\\\\\\\\\

i

h

Collector\

 

§\\\\\\\\\\\\\\\\\\\\

 

 

Figure 2.1: Top view of TINS device layout showing the contact regions, the
base diffusion region, and the ﬁrst level metals. The dimensions are in units
of um. Actual metal regions exceed the plotted metal regions.

 

Base

Colleen

 

F1gllre 2.:
base diffu
Of “In. AC

 

 

\\\\\\\\\\\\\\\\\\\\\\

\\\\\%\\\

 

 

 

. ure OUT cm W:
ase difusr the f tals. The dim are uni
Oan. metal

 

 

18

11 12 13 l7 19 20
10: TOUT 14: TD4 18 TIN3

15 16

 

Figure 2.3: Pin out conﬁguration of the transistors. The three transistors have

two common emitter pins.

 

 

Bum reﬂector centre
Mbillt‘ resistance e

[as].

2.2 Deuce Char

The I-\' em
staging legan and
dumg me sire». Tr}

\’ measuremenbf

(6, Fur
Figure 2.5 shows the
lsed for the emitter e.
on a Hewlett-Packard

ume mode. except fer

 

“3 “56¢ lite med‘

measurement while ”

, 2‘1. .
fatten-on of the HP
memrement The w ' "

~ mm aceura.
ﬁre» I
“lput current and

   
 

 

The measurem-
it .

”mtnla] [ham k .

19

Both collector contacts and both emitter contacts were used during stressing to reduce
parasitic resistance effects. The doping proﬁle for these devices is shown in Figure 2.4

[36].

2.2 Device Characterization
The I-V characteristics of the transistor being stressed were measured before any

stressing began and at cumulative stress times of 1, 4, 24, 100, 200, 500, and 1000 hours
during the stress. The I-V characteristics measured consisted of the following set of six I-
V measurements:

(1) IEBO forward, 0 S VBE S 0.8 V andI S lmA.

(2) IEBO reverse, -2 S VBE S 0 V.

(3) ICB0 forward, 0 S VBC S 0.8 V and I S lmA.

(4) ICBO reverse, -5 S VBC S 0 V.

(5) 1C, IB withVBC = 0 and 0 S VBE S 0.8 V, I S 1 mA. (Gummel plot)

(6) Family of curves, IC versus VCE and [3.
Figure 2.5 shows the circuit conﬁguration for each of the tests. Double contacts were
used for the emitter and collector during device testing. Measurements were performed
on a Hewlett-Packard 41453 Semiconductor Parameter Analyzer in the long integration
time mode, except for the family of curves for which the medium integration time mode
was used. The medium integration time mode takes 16.7 msec for each current
measurement while the long integration time mode takes 270 msec. The minimum

resolution of the HP 4145 is 1 mV for the source voltage and l pA for the current

measurement. The voltage accuracy is :t( 0.1% measured values + 10 mV + 0.4 Q * Io )

and the current accuracy is :I:( 1% measured values + 6 pA + 20 fA * V0 ). I0 and V“ are
the output current and output voltage, respectively.
The measurements were performed at T: 23 C :t 1 C in a Thermotron S1.2

environmental chamber. The data collected was then transferred to a Unix computer

_.--\-J

n
MU.

.
0
Qt

 

.FM 1 I J .11
& s /I W a
. (It! W

I

- 1- - - -lqa m we
0 0C n
H PM 0
m C

 

1 ‘. ‘.Jll‘ |.jz‘l‘+‘
-
III
a
1

N
a
1

CO.¢Q&¢CGUCGU 0C~Q°U

 

 

doping concentration

20

 

   

 

 

 

 

 

to“ -
I
1
1
1
1
10" 1
1
q
1
1
1
1 o 0
; ExtrmsmBasc
1P-~~~
4 “
‘\
l"‘ \
’ \
10 .. ’ \
10 1 ’ x ‘
I ’ \ ‘
1 ’ . . . \ \\
r’llmtnnacBm\ "“
q -
l \
1
to" 1
I
1
1
1
1
10“ I r 1 r 1 r Y
0.00 .200 #00 .600 .000 1.00 1.20

U01

Figure 2.4: Doping proﬁle for the devices used in this study. The impurity

concentrations are in units of cm-3.

1.'+0

 

Fio
c
TBVE

CUn

21

 

 

 

 

 

0 11090
Three
(n) 1.0 (b) Iceo
Ic
.19.. PC ,+
' CE
(c) ICJB (d) Family of Curves

Figure 2.5: Circuit conﬁguration for the measurements: (a) 1530 forward and

reverse, (b) Icao forward and reverse, (c) Gummel plot, and (d) family of

curves.

 

there a datin-

‘6

b. o

2.3 Unstress
the‘ai
the device to d
Var 1.01 1.0m a:
resistors. Fig
T36 TOLT de
died-3 Chumps.
Gummel Dhtt \-
shﬁ-wn in F

10”
:u

devices. the m .

ﬁgure 2‘ 1: 5h\

2.4 DC Re VG

2.4.1 Tempe”!

At a vet:
’heeireuit she
ﬁremitter Vt
:ttt'tru:tnmental .

231th 10:13pm

22

where a database was created. A diagram for the measurement setup is shown in Figure

2.6.

2.3 Unstressed BJ T Characteristics

Typical unstressed BJT characteristics are plotted in Figures 2.7 to 2.12 showing

the device to device variation for TIN3 and TOUT. Figures 2.7 and 2.8 show IEBO versus
VBE for forward and reverse bias of a population of six TIN3 transistors and six TOUT

transistors. Figures 2.9 and 2.10 show ICBO for forward and reverse bias VBC voltages.

The TOUT device shows larger collector base current due to the presence of Schottky
diode clamps. The characteristics studied most extensively were the current gain and
Gummel plot curves. The unstressed characteristics measurements for these devices are
shown in Figures 2.11 and 2.12. Figure 2.11 shows that in a total population of 12

devices, the maximum and minimum gain are 71 and 57 for VBE = 0.6 V, respectively.

Figure 2.12 shows the Gummel plots for the 12 devices.

2.4 DC Reverse Bias Stressing Experiments

2.4.1 Temperature Dependence of Reverse Bias Induced Degradation Experiment

. At a variety of temperatures from -75 C to 240 C, transistors were stressed with
the circuit shown in Figure 2.13 which reverse bias stressed the TIN3 transistors with a
base-emitter voltage of -4 volts. The transistors during stressing were placed in an
environmental chamber or oven as shown in Figure 2.14 in order to provide the desired
ambient temperature. The Thermotron 81.2 environmental chamber was used to provide
ambient temperatures of -75, 23, and 175 C. The temperature of the Thermotron 81.2 is
automatically controlled by the built-in thermocouple sensor and a heater/refrigerator
unit. The accuracy of the temperature is i l C. A Blue M model OV-18SA oven was

used to provide ambient temperatures of 175 and 240 C. The temperature of the Blue M

23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Thermorron
Environmental
Chamber
HP 4145B
l Semiconductor
“ Parameter
Analyzer
Test Device
in Low Noise IEEE 488
Fixture Bus
PC
Ethernet
MSU
Work Stations

 

 

 

Figure 2.6: Diagram for the measurement setup.

24

to“3 a

to” —

10* a

10‘7 —

10‘8 —

Iebo (Qmp)

y—a
C)

l
p...
D

L

 

 

10-12 r 1 t I
00.0 .200 .000 .600 .800 1.00

Ube (Uolt)

 

Figure 2.7: Forward biased 1580 versus VBE characteristics of a population of

six TIN3 transistors (solid lines) and six TOUT transistors (dashed lines).

25

 

 

 

10‘9 ~
10““—
A
CL
6
(E
\J
0
.0
cu
1041‘
10-18 l l l l l
—a.oo -1.60 —1.20 -.800 —L+00 000
Ube (Uolt)

Figure 2.8: Reverse biased IEBO versus VBE characteristics of a population of

six TIN3 transistors (solid lines) and six TOUT transistors (dashed lines).

26

10-2 '1

10"“ _ I

105 —

cho (Qmp)

10‘9 —

10'11 _1

      

 

10-12 9, l I
00.0 .200 .900 .600 .800 l 00

ch (Uolt)

Figure 2.9: Forward biased ICBC versus VBC characteristics of a population of

six TIN3 transistors (solid lines) and six TOUT transistors (dashed lines).

27

 

 

10'9 —
10'104
A
O.
E
CI:
\./
O \
r3 \\
U \\ \
H \
\ \
\
-11 \\ \
10 ",\ \ \\
\ \\ \\ \
x \ \
\x \\ \\ \
\\\ \ \
n\ \ \
\\ \ \
‘\\ \ \
\‘ \\ \ \
\V_ ‘5? \ \
\\ \H- \ \
\\_ x“ \\
\_ \\ \
\ _\ \\\
\\ \ \\\
10-13 ‘ r l L \$ r I
“5.00 -‘+ 00 -3.00 -2.00 -1.00 00.0
ch (Uolt)

Figure 2.10: Reverse biased ICEo versus VBC characteristics of a population of

six TIN3 transistors (solid lines) and six TOUT transistors (dashed lines). All

six TIN3 transistors had currents of less than 1 pA.

 

 

It!

Q00

evil

(I)

(A

VV

“A
V»

 

A
U
0A
~
VV
AA
_
VV
AA
‘
Vv
AA
VV '4
I
i
PA
DJ \
tn“ A
V9 V

hﬁTE

100.0

80 00

60 .00

L+0 00

80 00

00 00

00.0

1

l

l

 

28

 

.200

.000 .600 .800 1.00
Ube (Uolt)

I

Figure 2.11: Current gain characteristics of a population of six TIN3

transistors (solid lines) and six TOUT transistors (dashed lines).

29

Ic,Ib (Qmp)

10-9 —

10‘10 ~

 

 

 

10-12 r
00.0 .200 .000 .600 .800 1 00

Ube (Uolt)

Figure 2.12: Gummel characteristics of a population of six TIN3 transistors
(solid lines) and six TOUT transistors (dashed lines).

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.. § Ri=10 Kg
75—: V00 5
g VCC = 4 V
\ Environmental
Chamber
Figure 2.13: Circuit for stressing the transistors.
Thermotron HP 6621A
Environmental DC Power Supply
Chamber, or
Blue-M oven

 

 

 

 

Test Devices

 

 

 

 

|
1 Bias Circuit

 

 

 

 

Figure 2.14: The transistors were placed in an environmental chamber or oven

to provide the desired ambient temperature.

.ytezt tt
r-Jjuste
ll M

,.
“SR.

.5143-

“Luca
It't‘i'ﬁ :1

31

oven was monitored by using a mercury thermometer of resolution 1 degree Celsius and
adjusted by turning the analog dial on the front panel. The temperature provided by Blue
M was controlled within is C. The detailed stress conditions used in this experiment
were:

0 -75 C for 1000 hours (12 TIN3 devices)

0 +23 C for 500 hours (12 TIN3 devices)

0 +175 C for 1000 hours (12 TIN3 devices)

0 +240 C for 1000 hours (12 TIN3 devices)

For the above listed stress experiments, each group of 12 devices were equally
divided between two job numbers and each subgroup of 6 devices contained one chip
from each of the 6 possible wafer locations. This mixing of job numbers and chip
locations was done to reduce the inﬂuence of job number and chip location on the ﬁnal
results. Missing devices and bad devices caused some minor deviations from this overall
strategy. In addition to the devices being stressed, for each temperature stress condition
two chips were used as control devices which were exposed to the same temperature as
the stressed devices, but not the electrical stress. The control devices were seen to exhibit
no change in the electrical characteristics measured.

A reverse bias stress of -4 volts caused a degradation in the current gain versus
VBE as shown in Figure 2.15 for stressing at -75 C. The largest change in the current gain
occurred at base-emitter voltages less than 0.9 volts. Gain degradation is due to the
increase in the base current as shown in Figure 2.16. The base current changes are the
changes most expected since the base current is most susceptible to non-ideal transistor
effects. And it is at lower biases that the changes in the base current are most signiﬁcant
percentage-wise. The collector current is unaffected by the reverse bias stress condition.
The gain degradation versus time at VBE = 0.6 volts for several individual devices is
shown in Figure 2.17 where it can be noted that the gain degradation occurred with a

similar behavior in all devices. A comparison of the normalized current gain [stressed

 

Figt

lime

32

 

 
    

H1105“

 

 

 

1.2

Figure 2.15: Current gain versus VBE for stressing at -75 C for various stress

times up to 1000 hours.

 

Heath

1000 hOUl’s

33

 

 

 

 

 

Figure 2.16: Gummel plots for stressing at -75 C for various stress times up to
1000 hours.

 

DUI

-
-
‘V U
Q. A
,‘ ‘
U U
r- a
K C
v- ‘
A
:‘ -
q
’ v
a
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‘.“ ~
-
" u
I. Q
i v ‘
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v v -
‘Q

F1820:

I‘ll-1‘.

34

IHGIVICQel Devtces at T=-7S Reverse Stress

800']

700

 

100‘

 

 

0 00 ﬁ r f f l v v I 7 ﬁ

10'1 10° 101 to2 103
TIME

Figure 2.17: Gain degradation versus time at Var-2 = 0.6 V for several

individual devices stressed at -75 C.

eunent gain .1” p1
C. 241:: Cl is. she
armature. A.
wafer location r
The has;
deﬁned as the p
mtg, )
110111.111 ILmPCf
17.329 11A, am
53355 mmPL’Y‘dtu
Af'LCI re
A; - 1 .
Lxluntllttn W
1331:1573 Cuncnl

[310 Verses V.
n?

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1d0r 1
it}? [h .

35

current gain / prestressed current gain] for the four stress temperatures (-75 C, 23 C, 175
C, 240 C) is shown in Figure 2.18. The largest degradation occurred at the lower ambient
temperature. Additional examination of the experimental degradation results revealed no
wafer location or job number variation in the degradation.

The base current change can be plotted as a function of the stress charge which is
deﬁned as the product of stress time and stress current. The stress current increases as the
ambient temperature increases. The currents for typical devices were 28.3 nA, 54.3 nA.
0.329 11A, and 1.94 11A for ambient temperatures of -75, 23, 175, and 240 C,
respectively. Figure 2.19 shows the base current change versus stress charge for the four
stress temperatures. 0

After reverse stressing, the forward and reverse characteristics of the collector-
base junction were seen to be unchanged and the emitter-base junction exhibited higher
leakage current in both forward and reverse characteristics. The pre-stress and post-stress

11230 verses VBE characteristics is shown in Figure 2.20 for stressing at -75 C for 1000

hours.

2.4.2 Voltage Dependence of Reverse Bias Induced Degradation Experiment
The voltage dependence of the degradation rate was investigated by stressing

TOUT transistors with a range of reverse bias voltages. The bipolar transistors were
stressed at room temperature with reverse biases of 3.5, 4.0, 4.5, and 5.0 volts. The
circuit diagram of the stress setup is shown in Figure 2.21 where a voltage divider is used
for the circuit to provide the four voltages simultaneously. The detailed stress conditions
were

0 -3.5 volts for 200 hours (3 TOUT devices)

0 -4.0 volts for 200 hours (3 TOUT devices)

0 -4.5 volts for 200 hours (3 TOUT devices)

- ~5.0 volts for 200 hours (3 TOUT devices)

N0

Figtm

Cune,

36

 

0.8 -

0.4 —

 

 

 

02 l ‘l l
10‘1 10° 101 to2 103 104
Time(hours)

 

Figure 2.18: Normalized current gain [stressed current gain / prestressed

current gain] for stress temperatures of ~75, 23, 175, and 240 C.

37

 

   
 

 

 

 

10’8
10‘9 _
Ala
(Amp)
I : -75 C
10"10 .. :1: +23 C
4: +175 C
+: +240 C
10.11 I l
10-5 10'3 10‘1 101

Charge(Columb)

Figure 2.19: Base current change versus stress charge for stress temperatures

at -75, 23, 175, and 240 C.

0‘-“

.V

.a-7

‘v

'0‘8

A . T: .1-.. V

T-vaT c -

tn‘9

 

Hebo|<nmp>

38

-L+
10 7

10‘6 _.

10‘7 ~

10"8 _.

10'9 a

10'10 a

10‘11

 

 

 

10‘13 r r .
-a 00 —1 50 -1 00 -.500 00.0

Ube (Uolt)

 

Figure 2.20: Pre-stress (solid line) and post-stress (dashed line) IIEBOI versus

VBE for a device stressed at -75 C for 1000 hours.

 

Vcc = 5.0 V

 

 

39

Vcc = 5.0 V
" 5.0 V

4.5 V

{-55, =-

4.0 V

$ R3
3.5 V
i ii g I;
Figure 2.21: Circuit diagram for stressing TOUT transistors. The resistors
used are: R1 = R2 = R3 = 47 ohm, R4 = 317 ohm, and all other resistors are

 

 

 

 

100 kohm.

 

In addition to the
measurement 00 1ee
dnlees showed no

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40

In addition to the 12 stressed devices, two control device went through the same
measurement procedure but had no electrical bias applied during stressing. The control
devices showed no change in the characteristics measured.

The stressing were interrupted at cumulative stress times of l, 4, 24, 100, and 200
hours for the characterization of the changes in the BJT characteristics. The measurement
setup was the same as that described earlier in Figure 2.6, i.e., 23 C in a temperature
controlled chamber and I-V characteristics measured with the HP 41458. The I-V

measurements taken for this experiment were

(1) IEBO forward, 0 S VBE S 0.6 V and I S lmA.
(2)1R (Reverse stress current), VB = 0, VC = 0 and 0 S VE S VSTRESS.
(3) IC, IB with VBC = 0 and 0 S VBE S 0.8 V (Gummel plot).

The Gummel plots showing the base and collector currents versus VBE for the
unstressed and stressed characteristics are shown in Figure 2.22. The degradation
increased substantially as the base-emitter reverse bias voltage increased. Figure 2.23
shows the amount of the base current degradation increase at VBE = 0.6 volts versus the
total stress charge which flowed across the base emitter junction. The amount of
degradation depends on the stress charge and the stress voltage. The reverse bias stress
current was measured versus time for the transistors at all four different stress voltages as
shown in Figure 2.24. It shows that for a given stress voltage. the stress current did not
differ signiﬁcantly between devices. For example, devices 62, 35, and 73 were all
stressed with VBE = -4.5 volts and they all showed about the same leakage current at this
voltage. It can also be noted in this ﬁgure that the stress current changed little as the
experiment proceeded out to 200 hours. Figure 2.25 shows the degradation for each of
the devices stressed at -4.5 volts. By comparing this ﬁgure with Figure 2.24, it can be
seen that the device with a slightly higher leakage current shows a slightly larger

degradation.

41

 

  

Reverse

Bias
13’ IC '8
(Amp.) 10 _

10-lo _

10"12 _

 

 

 

10-14

0 02 0.4 0.6 0.8 1 12
VBEW 01!)

Figure 2.22: Gummel plots for the unstressed and the four stressed
characteristics. TOUT devices were stressed for 200 hours at -3.5, -4.0, -4.5,

and -5.0 volts.

 

Flgul

TOL‘

42

 

10.7 " rev
10'. —l M/
era/9X63 ”v
N. 4.0V
(Ame) 10‘, d f
10“0 -l ”v

10'12

 

 

 

I I I l
10" 10" 10'3 10'2 10'1 1 10
Charge (Cohmb)

Figure 2.23: Base current change versus stress charge at VBE = 0.6 volts.

TOUT devices were stressed for 200 hours at -3.5, -4.0, -4.5, and -5.0 volts.

10'5 .7.

rt"

10%

Stress
Current
Wurst

10:7 1

10‘s .

43

 

 

 

 

 

 

 

 

 

 

 

 

10-5
V35 = ~5.0 V
L’—
Pr,
bit
10.6 4
SM Mm” V85 3 -4.5 V
Current l
(Amps) 1‘
10‘7 _ 1...... ”'73 VBE = 4.0 v
V35 = -35 v
8
10- T I I
o 50 too 150 200
Stress Time (ham)

Figure 2.24: Reverse bias stress current versus time for the transistors stressed

at the four stress voltages.

{Am p5

Fi

 

  
 

 

 

 

10-8
Module 62
Module 35 Module 73
($1,391 0-9 .-
1 0_10 I F l
10"1 10° 101 1o2 103

Stress Time (hours)

Figure 2.25: Base current change versus time for TOUT devices stressed at

-4.5 volts.

 

113 Short Time 3
The, 001 ele
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45
2.4.3 Short Time Scale Stress

The hot electron degradation phenomena was also investigated on a short time
scale where the Gummel plot was measured after ﬁxed stress times that were selected in
the range from l/60th of a second to 10 seconds. In order to obtain precise timing of the
stress/measurement procedure, the HP 4145B was used for both stressing and
measurement. By using the IEEE 488 interface bus, the HP 4145B was automatically
controlled by a personal computer on which a stressing and measurement C program was
executed. A TIN3 transistor was placed in the low noise test ﬁxture for the stressing and
measurement at T = 23 C.

These short stress-time degradation experiments showed that ﬂuctuations of the
base current occur as the degradation proceeds. The fluctuation is demonstrated in Figure
2.26 which shows the current gain of a transistor after being subjected to short stress
periods of 10 seconds. The current gain changes are caused by fluctuations in the base
current as shown in Figure 2.27. The data shows that over an extended period of time,
there is a net decrease in the current gain over many stress periods. On a shorter time
scale, the base current may either increase or decrease from one stress period to another.
These ﬂuctuation increases in the base current are caused by hot electrons which increase
the number of degradation produced states. The ﬂuctuation decreases in the base current
are caused by a repassivation or simultaneous annealing process. This observation is
consistent with measurements performed by Wachnik et. al. [17] who saw ﬂuctuations
attributed to forward stress created hot electrons via the Auger recombination process. To
evaluate the possibility of the gain recovery being caused by the forward bias
measurement of the current gain, an experiment was performed where after each short
time interval of reverse bias stress, the transistor was forward biased for 60 seconds
before the current was measured. This experiment still showed signiﬁcant ﬂuctuations of
the base current with both increases and decreases in the base current observed, although

to a reduced extent as shown in Figure 2.28. Figure 2.26 demonstrates that the hot

46

 

 

 

 

60
SO-l ‘1
‘ \
hp; 40- ' l
30—.
20 l r l l
0 20 40 60 80 100

Measurement Number

Figure 2.26: Fluctuations of the current gain at Var-z = 0.45 volts for transistors

being subjected to short stress periods of 10 seconds. A control device
subjected to the same measurement procedure with no reverse-bias stress

showed current gain values changing over the range from 55 to 58 only.

 

47

Reverse Stress @T=83

 

 

10.10 '1
10'11 _.
/'\
O.
E
(I:
v
0 ":3
H ’ 0 0
c: ‘6‘ '90“. .91 .o
‘ a 0 ‘5, '9‘." ‘0'. 4’ v: 0:, 0‘. ') 0 "'vs/
D 10'1 .. u ‘09 . .0 0.“. :zg, (=14
H “0;" m?" " "
0
10-13 I I I I I
00.00 20.00 L10.00 6000 80.00 100 0

MEQSUREMENT NUMBER

Figure 2.27: Base and collector current ﬂuctuations for a transistors being

subjected to short stress periods of 10 seconds.

AU
AU

IV .-, AV
AU
AU

65?:
.8
.2‘3

1 —r
|
l
l
l
l
l
l
l
l
l
l
l
U
r...
\
A 0
ﬁnd .1-
v
N

RIV
A A .Epk .V

~I {

thure 7 7‘

 

1C (Qmp)

ID.

48

Reverse Stress @T=83

 

 

 

104°—
0 ﬂ
0 0 .0. of... )t" 0 4:0 0 ”a".
0 . -. .‘e v'. 0 .‘ 3... .. .. , 3, q
42b 5 0 u 0 e 0 0 "'\‘=T;~‘ ““39 ""“o~"¢ ”'0 0 " "JP 0’
(a o ‘ v " 9 v a ’v 00 ‘2 0
- ’ .~ .“ \‘ IF}. I I) 0 "' 00
‘5}, ‘3’ "0;"? “a, $612..- 'o"‘; ” ‘0' 0
7' 0 0
10 -13 r l I I 1
00 00 20.00 L10.00 60 00 80 00 100 0

MEQSUREMENT NUMBER

Figure 2.28: Base and collector current ﬂuctuations for a transistor being
subjected to short stress periods of 1 second followed by a subsequent forward

bias of 0.6 volt for 60 seconds.

\0 \
00'» I:“ '0
6

existing

11.4 it

the are
pith 1‘1.
121C it
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51411

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49

electron induced leakage states are not all permanent with only a subpopulation of states

existing for a long time.

2.4.4 Temperature Dependency of the Pre-stress and Post-stress Base Current

I-V characteristics were measured at various temperatures in order to determine
the type of leakage current caused by the reverse bias stress conditions. The Gummel
plots of a TIN3 transistor were measured for temperatures ranging from T = ~60 C to T =
120 C in 30 C increments at a pre-stress time and at a 1000 hours post-stress time. For
the temperature range of ~60 C to 60 C, the measurements were performed by using the
low noise test ﬁxture provided with the HP 4145B. The test ﬁxture was placed in the
Thermotron 81.2 environmental chamber. For the temperatures of 90 and 120 C, a circuit
board that could withstand high temperatures was built and placed in the environmental
chamber for measurements. Figure 2.29 shows the prestress characteristics for the
collector and base currents. The nonideality factor n [which gives the base current
dependence on voltage IB cc exp(VBE/nkT) ] is found to be 11 = 1.03 at T = ~60 C and n =
1.01 at T = 120 C. These low non-ideality values demonstrate that the base current in a
prestress device is primarily the ideal diffusion current. The post-stress characteristics are
shown in Figure 2.30. The non~ideality factors for low current values are n = 2.44 at T =
~60 C and n = 1.26 atT = 120 C.

The technical literature has attributed increases in the base current to three
possible mechanisms [7,10,11,37] which include Schockly-Reed-Hall (SRH)
recombination current, Poole-Frenkel electrical ﬁeld enhanced recombination current,

and trap-assisted tunneling current (or excess current). Assuming the trap level is in the

middle of energy gap, the SRH recombination R8 for a surface can be expressed as
2
“P "' "t

 

RS=—l—(n+n)+—l—(p+n.) (2])
Sop ' Son ' '

50

 

10'”

10'5

1018 10'6

(Amp)
10 '7

 

 

 

 

000 180

VBE (V0118)

Figure 2.29: Gummel characteristics for a pre-stress TINB transistor at

temperatures of ~60, ~30, 0, 30, 60, 90, and 120 C.

51

 

10'”

10 ‘5
10 IB
(Amp) 10 -6

10"

 

 

 

 

0.00 .800 .“100 .600 .800 1.00 1.20

Figure 2.30: Gummel characteristics for a stressed TINB transistors at
temperatures of ~60, ~30, O, 30, 60, 90, and 120 C. The transistor was stressed

at ~75 C for 1000 hours.

.7571 0» 0.51.1 I;
.3 I II p -

.l
I .'

52

where the hole and electron surface recombination velocities can be expressed as

S = Opva. (2.2)

op
Son = onvthNt (2-3)
op, on, vm, and Nt are the hole capture cross section, electron capture cross section,
thermal velocity of the carriers, and trap density respectively. Assuming the hole and
electron surface recombination velocities are the same, assuming maximum

recombination rate throughout the depletion region, i.e., n, p >> ni, and using

2 V/kT . . . .
up = n, 6“ , allows RS to be srmplrfred grvrng

ﬂ
RS = _22nieZkT (2-4)

where 80 = Sop = S The SRH current can be approximated by integrating the

OD'

recombination rate over the depletion area A giving
1‘1.

So
Is... .. °A7°i°m (2.5)

Taking into account the temperature dependence of ni, the SRH current can be arranged

in the following form which shows the temperature dependence and voltage dependence

relationship to be

qV

E
IQRH 2: kl . T3/2 . exp —.__..§_. . eXP(—) (2.6)
‘ 2kT ZkT

where k’ is a temperature and voltage independent constant.

The SRH current has a nonideality factor of 2. The larger non~ideality factor at
lower temperatures in the experimental data indicates the presence of additional
contributions to the base current [38]. The second mechanism possible is the Poole-
Frenkel enhanced surface SRH recombination current reported by Woo et. al. [37] and
Hackbarth et. al. [10,11]. The carrier emission coefﬁcient is enhanced due to the Pool~
Frenkel effect when a high electric ﬁeld is present. The capture rate for electrons and

holes are enhanced by the following

53

o UZEl/Z
C11 = O’Vm = Cn exp(1§_l-(T—_) (2.7)
- _ o qu/ZEl/Z
Cp - (YVuI — Cp exp(T) (2.8)
where
l3= -q- (2.9)

at»:
E is electric ﬁeld, and e is the high frequency dielectric constant which has a value
between free space dielectric constant and the static dielectric constant. Similar to the

derivation of (2.6), the Poole-Frenkel recombination current can be expressed as

1/2 1/2
E E qV
I_ zk’on-ex ———qB -ex --——3 .ex [—)
PF 2 p[ 2kT p 2kT p 2kT (2'10)

where the temperature and voltage dependencies are shown.

The Poole-Frenkel effect can have a nonideality factor greater than two only at
very low temperatures (< ~150 C) [7,10,11]. Attempts of ﬁtting (2.10) to the degraded
characteristics in the temperature range of ~60 to 120 C were unsucessful. A third
possible degradation current, i.e., the tunneling current, is examined below.

By examining the temperature and voltage dependence of each of these leakage
currents, the best ﬁt of the experimental data to the calculated model is obtained by
assuming a trap-assisted tunneling current The forward-bias tunneling model adopted is
that developed by Del Alamo and Swanson [39]. This model gives the total forward
current as the sum of the trap-assisted tunneling current and the ideal diffusion current.
The trap-assisted tunneling current, IT, is given by

IT = l0T exp (VNT) (2.11)
where ICT is the tunneling saturation current and VT is the characteristic tunneling
voltage. The tunneling saturation current has the form

Ior = C exn t-B EgtT» (2.12)

where C and B are constants and EG(T) is the temperature dependent bandgap.

 

'3
at?

at
n.

o -
(In

their:

U1

54

The ﬁtting of (2.11) to the degraded characteristics produces the plot shown in
Figure 2.31 where experimental and calculated base currents are compared for
temperatures of ~60, ~30, 0, 30, 60, 90, and 120 C. The parameters used are B = 146, VT
= 0.053, C = 3X10”, and EG(T) is [4]

4.73><10"'T2
T+636 (2.13)

 

EG (T) = 1.170-

Degradation current due to the excess tunneling mechanism is also reported by Li
et. al. [7]. They showed an exponential dependence of the base current on the energy gap
and identiﬁed the degraded characteristics as the excess tunneling current. So far in the
literatures, however, excess tunneling mechanism has not been implemented in a device
level simulation program. In addition to its complex quantum mechanical treatment, lack
of a detailed knowledge of the surface state energy distribution created by hot electrons
makes the device level implementation most difﬁcult. On the other hand, it had been
shown that at room temperature the degraded characteristics can be modeled by an
increase of surface recombination rate due to an increase in the surface state density
created by the hot electrons [1]. The implementation of the surface state creation to

model the base current degradation will be used in this work and described in Chapter 3.

2.5 AC Stressing
To investigate the effect of non-DC stressing, transistors were stressed under two
conditions:
- VBE switching from ~4 to 1 volts for 1950 hours (6 TIN3 devices).
a VBE switching from ~4 to 0 volts for 1800 hours (6 TIN3 devices).

In the ﬁrst group of six transistors, a lKHz alternating reverse-bias to forward-bias (~4 to
+1 V) pulse train was applied to the base-emitter junction with the collector-base
junction shorted. The duty cycle was 50% so that the devices were in forward bias for

half the time and reverse bias for half the time. In the second group, an alternating

55

Total current compar151on

 

10" -

to" .

10" 4

10", -l

10'" «

 

 

 

 

Figure 2.31: Comparison of nonideal tunneling current model (solid lines) to
the experimental (dashed lines) base current for temperatures of ~60, ~30, 0,
30, 60, 90, and 120 C.

18W

. x‘

to: t

htth :
. e;

h
.135 01

def
tee

56

reverse bias-to-zero (~4 to 0 V) pulse train was applied so that the devices were unbiased
for half the time and reverse biased for half the time. Self heating of the devices is in
both cases not sufﬁcient to cause thermal annealing effects because with a 1 V forward
bias on the base-emitter junction, the base current measured is less than 10 mA and the
device power dissipation is a maximum of 10 mW. The thermal resistance of a
rectangular emitter on a wafer surface is R,h = g / k [40,41], where k is the thermal

conductivity of the silicon ( 1.45 W/cm °C at 300 K) and g is the geometrical factor

sinh'l(b/ c) + sinh_l(c/ b)
rtb nc

 

deﬁned as where b and c are the width and length of the

emitter. For the emitter dimensions of the transistors used in this study, g is 0.17 tun-1
and the thermal resistance is 1.2 C/mW. The resulting temperature rise of 12 C is below
the temperature required for thermal annealing effects.

Previous reports on AC stressing have indicated various results. In one report, a
signiﬁcant difference in degradation between stress cycles which included a forward-bias
cycle and a stress cycle without forward-bias was reported [8]. In that work, at a stress
charge of 6 X 105 Columb (about 10 minutes stress time), the 0 to ~5 V cycles resulted in
a decrease of gain of 14 % whereas the +1 to -5 V cycles resulted in a decrease of gain of
6 %. However, a second study did not report any difference between the two stressing
modes for less than one hour of reverse-bias-on time [42]. Our results for AC stressing
for up to 1950 hours are shown in Figure 2.32. For the ﬁrst 100 hours, no apparent
distinction is observed between the two stressing conditions. However, with longer stress
times, a decrease in degradation rate is observed for the devices receiving forward-bias
pulses. After 1800 hours, hm has degraded to 26% of the original value for reverse bias
only stressing, and has degraded to 45% of the original value for stressing which

included forward-bias pulses.

57

 

l-r

'v"

- """"V

0.8 4:

Normalized
hr:
V” - 0.6 V 0.6 -

0.4 ..

 

 

 

0.2

 

l l l l
0 400 800 11!) 1500 2000

Stressing Time (hows)

Figure 2.32: AC stressing results for stressing with and without a forward bias

cycle.

58
2.6 Thermal Annealing Experiments

The temperature dependence of the reverse bias degradation as shown earlier in
Figure 2.19 can be attributed to two phenomena. One is the temperature dependence of
the number of hot electrons. At higher temperatures, a reduced mean-free path between
electron scattering events leads to a decrease in the average electron energy. On the other
hand, an increase in the stress current (the number of electrons passing through the space
charge region) at higher temperatures could still result in an overall larger number of hot
electrons. Another phenomena is the simultaneous repassivation of degraded states which
occurs signiﬁcantly more often at the higher ambient temperatures. This repassivation of
degraded states was investigated with two annealing experiments.

In the ﬁrst experiment, transistors degraded at 23C for 500 hours were annealed
by placing the transistors in an ambient temperature (50 C to 240 C) without electrical
connections. At preselected times the annealing was stopped and the transistor
characteristics were measured at 23 C to assess the annealing rate and magnitude. In the
second experiment, annealing at 240 C of transistors previously degraded at 240 C for
1000 hours was done in order to compare the annealing characteristics between devices
degraded at different temperatures. A detailed description of the two experiments
includes:

0 degradation at 240 C with VBE = ~4 V for 1000 hours, annealing at 240 C for

200 hours (3 TIN3 devices), and
- degradation at 23 C with VBE = ~4 V for 500 hours, anneal at 23, 50, 100, 150,
175 and 240 C for up to 500 hours (3 TIN3 devices).

Post degradation gain recovery by annealing at elevated temperatures was
observed at temperatures of 150, 175 and 240 C for devices which received previous
reverse bias stressing at 4 volts for 500 hours in an ambient temperature of 23C. The
degree of post-degradation recovery is highly temperature dependent. Annealing for one

hour recovered about 50% of the current gain drop which occurred during the 500 hour

59

10“

 

 

 
  

 

 

 

 

 

(Amp) 175 C Annealing
(113510,, (0) ...._ ...........................

Narrowm) _ ........ '3.

240 C Annealing

-10
10 I I I l
0 100 200 3(1) 400 500,
Time(hours)

Figure 2.33: Base current change versus annealing time for annealing at 175

and 240 C. Transistors were originally degraded at 23 C for 500 hours.

60

degradation when the annealing temperature was 240 C. At annealing temperatures of
175 C and 150 C the gain recovery was 30% and 20%, respectively. Figure 2.33 shows
the change in base current at VBE = 0.6 V versus annealing time at 175 and 240 C. The
zero hour time point on this plot indicates the degradation amount after a 500 hour stress
at 23 C. The annealing data shows two distinct regions. For the ﬁrst few hours of the
annealing process the recovery is rapid and for the longer times (greater than 24 hours)
the recover continues but at a slower rate. Figure' 2.34 shows another annealing
experiment in which transistors degraded at 240 C for 1000 hours are annealed at 240 C.
The Figure 2.34 result for annealing of 240 C degraded devices shows a smaller recovery
for the ﬁrst few hours of annealing time when compared to the result of Figure 2.33
which shows annealing results for 23 C degraded devices. This difference is attributed to
a simultaneous repassivation of a portion of the degradation-produced states during the
higher 240 C degradation condition. In particular, the portion of the states which
repassivated during the higher temperature degradation are believed to be the same states
which show very rapid annealing in Figure 2.33. Once the easily annealed out states have
been removed, the longer annealing time data of Figures 2.33 and 2.34 show similar
behavior. These two different repassivation rates will be referred to as the slow
repassivation and the fast repassivation components. The portion of the total
repassivation attributed to the fast and the slow components is temperature dependent. At
higher temperatures the fast component is larger as indicated by the larger rapid recovery

at 240 C as compared to 175 C in Figure 2.33.

61

10‘8

 

AI -
(Ame)lo 9 _\*\

 

 

10—10

 

l T l
0 50 100 150 200

Time(hours)

Figure 2.34: Base current change versus annealing time for annealing at 240

C. Transistors were originally degraded at 240 C for 1000 hours.

Chapter 3

Numerical Models of Bipolar Junction Transistors

In this chapter, numerical models are presented and developed to investigate the
physical phenomena of bipolar transistor operation including hot electron induced
degradation. Section 3.1 introduces the model history and explains the formulation of the
Drift-Diffusion Model (DD) model and the Hydrodynamic Transport Model (HTM).
Section 3.2 discusses the implementation of numerical solutions for semiconductor
devices utilizing these models. Section 3.3 presents physical effects included in the
simulation program, e.g., bandgap narrowing, Auger and SRH recombination/generation.
and band-to-band tunneling. Section 3.4 develops the model used for extracting the
number of hot electrons, namely, the simpliﬁed Hydrodynamic Transport Model. The
use of the Monte Carlo simulation technique for determination of energy dependent
parameters is presented in Section 3.5. Finally, all parameters used in the device

simulations of this study are listed in Section 3.6.

3.1 Model History

The behavior of charge carriers can be described by the Boltzmann transport

equation (BTE). The unknown to be solved for is the distribution function, f(r,k,t), in the

seven dimensional space (the phase space) consisting of spatial coordinate r, momentum

coordinate k, and time t. The distribution function determines the carrier density per unit

volume of the phase space. The BTE can be written as
3f i F 8f 3f )c

swasmrf‘s

where F represents external forces, m* is particle effective mass, and v is group velocity

 

(3.1)

of the carriers. The right hand side includes the randomly-timed scattering events that the

62

63

particles experience. The density of particles n(r, t) can be determined by integrating the

distribution function over all momentum volume as

n(r,t)= [attends (3.2)

To directly solve the BTE for a semiconductor device would be formidable, an
alternative is to make a series of simplifying assumptions to obtain the semiconductor
equations. The ﬁnal form of these equations may depart signiﬁcantly from the original
form of the BTE. In the following, the DD and HTM models are constructed by

obtaining the moment equations for the BTE .

3.1.1 Moment Equatiom

The moment equations are obtained from (3.1) by multiplying it by various
functions of velocity, <b(v), and integrating over velocity space. Various <D(v) functions
include 1, v, and W, etc. which give rise to the zero-order, ﬁrst-order, and second order,
etc. moment equations. The procedure is straightforward, though tedious for higher
orders. It replaces an equation for the distribution function, f(r,v,t), by equations that are
functions of r and 1 only.

The average over velocity space of an arbitrary function 0 is deﬁned by

l _
=—_ 9 9 9 9 d
((11) n(r,t)‘[¢(r v t)f(r v t) v (3.3)

where n(r, t) is deﬁned in (3.2). Hence, multiplying (3.1) by <1>(v) and integrating over

velocity space, the general moment equation may be written as

atn<<b>> 3 me 99; _ .3.
at + ar-(n<v<b>)— m. Eet av» [at(rl<<l>>)]c

 

(3.4) -

where F is replaced by eE where E is the electric ﬁeld.
Thus the BTE for the distribution function f is replaced by a set of equations
containing averaged quantities. By using the following functions of (N"), the ﬁrst three

moment equations are derived to be [43,44]:

64

 

 

Zero-order: (NV) = 1
a
1+V.(n<v>) : —R (3.53)
at
First—order: <D(v) = m*v
8v qE 1 v
—+v-Vv+—.+ . V nan)=——
at m m n ( 17,, (35b)
Second-order: <D(v) = §m*vv
3§ é-i
—+V-S— -E=- °
at J R (3.5c)

where R is the recombination rate, 17 and I, are momentum and energy relaxation times,

'1‘n is the electron temperature, and S is the energy ﬂow ﬂux given by

_ dT kBT
s — 'K(T)E§'_J6(T)T (3.6)

where 8 (T)kBT is the average kinetic energy transported per charged carrier arising from
the current ﬂow and K(T) is thermal conductivity of the carrier where the Wiedemann-

Franz relationship can be used [29,45] to give

 

2
n(T) kB
—= — A T T
M) [q] ( ) (3'7)
5 (T) and A (T) are dimensionless transport coefﬁcients given by [45,46]
_ < 1&2 >
6(T)— (1:) (3.8)

2
_ <r§3>_ <r§2> 2
.-.,_[___<,§> [TM/m

Where 1"; is the total carrier energy given by

1:: .3. nkBTn + i m‘n(v)2. (3.10)
Equation (3.5a) is the particle conservation equation, Equation (3.5b) is the momentum
conservation equation and Equation (3.5c) is the energy conservation equation. Each
moment equation introduces the next higher-order velocity moment due to the second
term in (3.4). If it is assumed that the distribution function is symmetric about the

av . . . . . . . . .
erage velocity in momentum space, as it rs for a displaced Maxwellian drstrrbutron,

65

then third and higher order moments of the distribution function vanish [44]. This

approximation uses the ﬁrst three moments of BTE to calculate carrier transport.

3.1.2 Drift-Diffusion Model

The Drift-Diffusion (DD) Model consists of solving the Poisson equation and the
continuity equation (3.5a). This model makes a simpliﬁed approximation for the
momentum equation (3.5b) and neglects the energy conservation equation. The DD
model assumes that the carriers are at thermal equilibrium with the lattice and that the
carrier temperature gradient is zero. These two assumptions resulted in equation (3.5c)
not being used. The simpliﬁed approximation for the momentum conservation equation
leads to the expression for the current density. This is done by assuming that a quasi-
steady-state model is adequate, i.e., avl at = 0, and that v.Vv is negligible compare to
other terms. With these assumptions, the momentum conservation equation (3.5b)

becomes

1
v =-q pE-kT 52‘-

n t t '
m mpﬂ 1:

 

(3.11)

 

If the mobility and diffusion parameters 1.1“, Dn are deﬁned as

 

(11p
I'll) = :3 (3.12)
m
and
RT
Dn = :un , (3.13)

then the expression for the carrier velocity can be written as

D
VI) = ~(unE+ —n—“Vn) (3.14)

and the electron current density becomes
Jn = .ann = qnllnE+ anVn, (3.15)
This representation of carrier transport is referred to as the 'Drift-Diffusion' model

and can be extended similarly for holes in semiconductor devices involving both holes

66

and electrons. The semiconductor equations in the DD model for two carriers are the
Poisson equation, the electron continuity equation, and the hole continuity equation. One

such Drift-Diffusion simulation program is PISCES-II [24].The equations it solves are

v°w=-%(p-n+ND-NA) (3.16a)
v.jn_q.ﬁ=q.R (3.16b)
at
811 .
V-Jp+q.—a?=-q.R (3.161,)
where the electron and hole current density 1,, and .1p can be expressed as
J. = qntlnE+ anvn (3.16m
and
Jp = qptlpE- quVP. (3.16e)

3- 1-3 Hydrodynamic Transport Model

The DD transport model derived above assumes that the carrier velocities are
instantaneous functions of the local electric ﬁeld and that the mobility and diffusion
coefficients are functions of local electric ﬁeld alone. In reality, the carriers do not
reAil-"0nd instantaneously to a change of the electric ﬁeld. A more complete model
requires inclusion of the momentum and energy relaxation effects included in the HTM
m0del presented in this section.

The HTM model consists of solving self-consistently the Poisson equation and
the first three moment equations, i.e., continuity equation (3.5a), momentum
conservation equation (3.5b), and energy conservation equation (3.5c). In a similar
manner as the derivation of the velocity equation in the DD Model, the momentum
consel‘vation equation leads to the expression for the velocity equation as

1
vn =-u(Tn)E—;V(D(Tn)n) (3.17)

Where the mobility and diffusion coefﬁcients are functions of the carrier temperature.

They are

67

qt (Tn)
p.(Tn)=——'iT— (3.18)
m
and
k Tnu(Tn)
DVIL)""——‘—'—B q (3.19)

Thus for the HTM model, the electron current density is
Jn = qnun (Tn )E+ qV (“Du (Tn )) (3.20)

For steady state, the energy conservation equation becomes

.V~S=J-E—-§:§£ (3.21)

The energy conservation equation states that the rate of change of energy ﬂow is given
by the balance of the Joule heating rate and the energy absorption rate. The energy
absorption rate due to carrier phonon collisions and recombination can be expressed in a
different way as nCn+wnR, where C, is the energy absorption rate function and wn is the

average electron energy taken to be %an. Following Cook [28], the expression for the

energy absorption rate C“ is
Where rm, is the energy relaxation time for electrons and p0 is reference hole density.
Finally the energy conservation equation used in this study is

v .511 = Jn -E- nCn(Tn,Tp)— ngnR (3.23)
The Do value is 1013 cm'3 [28].

The derivation for the momentum conservation and the energy conservation
equations can be extended to describe the holes. The HTM method for semiconductor
deViCes involving both electrons and holes solves self-consistently the Poisson equation,
the Continuity equation for electrons, the continuity equation for holes, the energy
cons(il'vation equation for holes, and the energy conservation equation for electrons.
These equations for the steady state case are

V2 =3 _ -
W a“) “ND NA) (3.24:1)

68

V J“ = qR (3.24b)

V -Jp = -qR (3.24c)

V -S.. = Jn-E- nCn(T..Tp)-%anR (3.24a)

v .sp = Jp -E— pCp(Tn,Tp)- ngpR (3.24e)
where the electron and hole energy ﬂuxes are

3,. = --1'E(T,,)V'I'n -J,,5(Tn )kBTn / q (3240

Sp = —1<(Tp )VTp + .11.,6(Tp)kBTp /q (3249
and the electron and hole current densities are

Jn = qnlln(Tn)E+ (TV (th(Tn)) (3,2411)

Jp = qpllp(Tp)E-qV(pr(Tp)) (3.24”

3-2 Numerical Solution Implementation

In this section, the implementation of numerical solutions for the models
discussed in the last section will be presented. To solve the semiconductor device model
numerically involves discretization of the equations at a set of grid points. Setting up the
discretized equations for the grid points constructs a nonlinear matrix problem which
tYpically needs to be solved iteratively. If the iterations result in a convergent solution,

the unknowns on the grid points are solved. The details of the scheme are presented

below,

3'24 Discretization

The numerical solution of the semiconductor equations requires the discretization
0f theSe equations (3.24a ~ 3.24e) for an appropriate grid structure superimposed on the
Simlllated device geometry. For the discussion of the discretization schemes, the notation
for the mesh points is shown in Figure 3.1.

The discretization of the Poisson equation is done using a 5-point ﬁnite difference

approximation which gives

69

 

 

 

Figure 3.1: The notation for the mesh points used in the discretization of

semiconductor equations.

70
W1.”- WiJ _ ‘Vid — WM.)- “11.141" Wu _ ‘l’i.j - Wi.j—1

 

 

 

31 21H + bi bi-1
ai+ai_1 bj‘l' bj-l
2 2
q
= ‘ E'(Pi,j — “Li + NDLj + NA”) (3.25)
For the electron current continuity equation, (3.24b) can be written as

a a
$1.... + $1“ = qR (3.26)

where Inx and Iny are the x and y components of the electron current density vector .1“.
Using a 5-point ﬁnite difference approximation. the discretized current continuity

equation can be expressed as
_ - JHXLI J

* id 2'1

1] i . R
a1+ ai-l + b. + b._ _ q ivj (3.27)
2 2

Jnxi

 

 

where the electron current densities are evaluated at the mid points shown in Figure 3.1.

The hole current continuity equation is discretized as

 

 

JPX. 1 . - Jim-J. JPY-- r - JP)’. ._1
"2", l 2.] + 1.1+?- l.) 2 _ _ R -
ai + ai_1 bj + bj-l q 1‘] . (3'28)
2 2

The derivation of the discretized forms of In and Jp follows the work of Tang [46] which

is closely related to the Scharfetter-Gummel expression [47] in the DD approximation.
The classical Scharfetter-Gummel expression involves the use of the Bernoulli function
to include the exponentially varying electron and hole concentration as a function of
POSition and is numerically more accurate. The electron current density has been

discretized as

J n = _ q(‘l’i+l ‘WO + kB(Ti+1'—Ti) . [Ulla (T)]i B(-0)—[nttn (T)]i+1B(9)
xkh x1+1 -x. xt+1 ‘Xi 9

(3.29)

Where B(x) is the Bernoulli function deﬁned by

71

 

 

 

 

B(x) = xx . (3.30)
e _
9 represents
9=-(am+1)ln(Ti+l/Ti) (331)
and am is given by
= _ QWM - Vi)
m kB(Ti+l - Ti) ' ' (3'32)
Similarly, the hole current density can be expressed as
J. = _ q(“Vi+l -\Vi) - kB(Tl+l -Ti) . [pup(T)]i B(—e’)— [pup(T)]i+l B(e’)
px“% xi+l —xi xi+l _xi 0’
(3.33)
where
9’ = —(0t;u + 1)1n(Ti+1 IT.) (334)
and
( '+ - -)
I _QW11 WI . (3.35)

m _ kB(Ti+l - Ti)

The detail derivation for the discretization of the electron and hole current density is

documented in Appendix A.
For the discretization of the energy conservation equation, the VS term is

discretized similar to the V-J term of the continuity equation. The J E term is taken as

the average between the mid points as

Jn ‘E= Janx + JnyEy (3.36)
where
l
Janx = Eb“. l.17“. 1.+ Jn,1.E.1]
[+5.] “-2-" l-EJ l‘ 5']
1 Wi+1.j - ‘l’i.j 1 Wu - \Vi-1.j
= "In. ..———‘§Jn. ._———
lo 5.] ai “5‘1 al-l (3.37)

The energy conservation equation for electrons is discretized as

3 -Sn, Sn...-Sn._,

11. . . .
|*%‘J l-§‘l l.J‘§ ‘—

1 . . ' + 1b— b.
f(ai+al—l) ‘2( 1+ j-l)

1 Wi+l.j " WI] 1 WiJ " wi-IJ
_ 7J1] l — 7]“
"“75 ai “:1 ai-l
1] W13+1 W1] 1 J ViJ - WiJ-l
- 7 n. . 1 b 7 D. . 1 b
[1+1 j 1.1—j J-l
. . . ._ a . . ‘
- “1.1% 2 ”11.314 (3.38)

The energy conservation equation of holes is similar to that of the electrons and is simply

the substitute of p for n in (3.38). The details of the discretization of electron and hole

energy flux densities Sn and 8p is shown in Appendix A.

3.2.2 Box Integration Method
The general form of the semiconductor equation. e.g.. the Poisson equation, the

continuity equation, or the energy conservation equation, can be expressed as

V - F(u,u) = c(u,u) (3.39)
where F represents the electric ﬂux density D for the Poisson equation, the current flux
density J for the continuity equation, and the energy flux density S for the energy
conservation equation. u represents the unknown state variables which are being solved,
38., W, n, p, Tn, and Tp. The divergence theorem states that for a generalized function F,
the Volume integral can be transformed into the surface integral by the relationship

{v .de= {F-ndA (3.40)

Where n is the outgoing unit vector normal to surface dA. Applying (3.40) to (3.39) gives

1[Ii-ndA={cdv (3.41)

For the two dimensional case, (3.41) becomes
JF-nd = chxdy
1 A (3.42)

73

where n is the outgoing unit vector normal to the perimeter d1 of the rectangular around
the grid point as shown in Figure 3.2. By taking the line integral of the left hand side and
assuming the value c is constant in the area dxdy, (3.42) becomes
(F35 ‘ F13 )dy + (F34 ' F23 )dx = C(dXXdY) (3.43)
where F 13 is the physical quantity from point 1 to 3, F35 is the physical quantity from
’ point 3 to 5, etc. The box integration method numerically solves for the semiconductor
equations of the form of (3.43), i.e., for the Poisson equation,
(D35 " D13 )dy + (D34 " D23 )dx = (KP - n + ND ‘ NA )(dx)(dy) (3.44)
for the continuity equation,
(135 -Jn)dy+(134 -123)dx =qR(dx)(dy) (3.45)

and for the energy conservation equation,

3
(335 -S,3)dy+(S34 423m ,.( 1.2—men -—2—kTR)(dx)(dy). (3.46)

The box-integration method, which can be understood as a ﬁnite-difference on a
rectangular elements, has been proven to work satisfactorily in semiconductor device
applications [48]. Similar as above, the box integration method can be applied to
triangular elements [24]. This research uses the box integration method on a rectangular
mesh structure to set up the matrix elements for iterative solutions. The box integration

method was chosen to facilitate the use of a terminating line mesh structure as discussed

in the next section.

313 Grid Structure
For semiconductor device simulations, three types of grid structure are commonly
uSﬁd: ( 1) non-uniform rectangular mesh, (2) triangular mesh, and (3) terminating line
remangular mesh structures as shown in Figure 3.3. The non-uniform rectangular mesh is
easiest to implement and its numerical properties are well known. The disadvantage of
the non-uniform rectangular mesh is that it would take the most mesh points among the

three grid structures. The triangular mesh structure has a similar form to the

74

 

 

 

 

 

1]
7r
'5‘ F23
n
<— —> n
F 13 1:35
V

1:34

 

 

 

 

Figure 3.2:The physical quantities and the unit normal vectors for the box

integration method.

75

 

(C)

Figure 3.3: Three commonly used grid structure: (a) non-uniform rectangular
mesh, (b) triangular mesh, and (3) terminating line mesh. Dashed lines

indicate pn junctions.

76

ﬁnite-element method and is more ﬂexible when applied to irregular boundary conditions
but is more difﬁcult to implement. The third kind of mesh structure is the terminating
line mesh structure which improves the non-uniform rectangular mesh structure by (1)
not extending the mesh lines to where physical changes are slow and by (2) reducing the
number of mesh points. The structure of the grids employed by this work is the
terminating line mesh structure [49].

The mesh and point assigning scheme for an example grid is illustrated in Figure
3.4. The use of the terminating line mesh structure requires that a "book-keeping" be
done to record and use the grid. For each point, a list of its right and left neighbors are
kept The number of the ﬁrst point in each column is stored in an array NLOC. To locate
a point from its column and row number, the following equation can be used

N = NLOC(i) + j (3.47)

where i and j are the column and row number.

The location for each column and row are kept in two arrays, XLOC and YLOC.
The position of each grid point can be identiﬁed from its row and column number by x =
XLOC(i) and y = YLOCU). Layout of the mesh structure as speciﬁed in the user's input
ﬁle includes the location of a speciﬁc mesh line and the distance ratio between the mesh
lines. The mesh lines in the y direction can be speciﬁed to be shorter than the device
depth, giving rise to a terminated mesh line. If, in the y direction, all mesh lines are
speciﬁed to be equal to the device depth, all lines are nonterminated and the mesh
structure reduces to the nonuniform rectangular mesh structure. The details for describing

the layout of a mesh in the input ﬁle are explained in Appendix B.

3.2.4 Numerical Solution
The solution of the discretized semiconductor equations on a grid of N nodes
involves a total of 5N unknowns for the HTM since at each point the unknowns are W, n,

P. T... and Tp. The system of 5N discretized equations including the Poisson equation, the

77

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)

 

 

l

3-22

J

 

 

 

 

 

 

 

 

 

 

 

2.x

 

 

 

 

 

 

 

 

 

(b)

Figure 3.4: (a) An example mesh and (b) its point assigning scheme for

terminating line mesh.

78

continuity equations for electrons and holes, and the energy conservation equations for

electrons and holes are
”Fw(w,n,p,Tn,Tp)"
Fm(w,n,p,Tn,Tp)
F(w,n,p,Tn,Tp)= Fcp(\v.n.p.T...Tp) =0
Fm(w,n,p,Tn,Tp)
_Ftp(\p,n,p,Tn,Tp)_

(3.48)

 

 

where F“, denotes the system of the N Poisson equations, Fcn and Fcp denote the system
of the 2N continuity equations for electrons and holes, and Fm and Ftp denote the system

of the 2N energy conservation equations for electrons and holes. Two principle methods

of solving (3.48) are the Newton method and the decoupled method or Gummel method.
The Newton's method linearizes the system of partial differential equations and.

by starting from an initial guess, the solution of the nonlinear equations is obtained by

iterating the matrix equation

 

 

 

 

 

 

 

 

 

[an 8F“, at:w at:V aFv ‘ k
W 3n— 3p 31“,, arp
are“ arm as.“ 35% 311.. FM“
aw an ap 8Tn BTP Arr“
are? arep as“, asap apcp A k
aw an ap arn arp " k
9g 6F... 8F... 8F... 8F... ”I;
aw an ap at, arp -ATp -
arm 35,, an, at:up as.p
[sz— an ap arn arrp .

 

 

"Fw(wk,n",pk.r,f,rg)'
F...(w“.n“.p“.T.l‘.T$‘>
= — Fcp(wk,nk,pk,T:,T:)
mek,nk,pk,T:’—rg) (3.49)
_Flp(wk,nk,pk,T:,Tg)_

 

 

79

where k denotes the iteration count. The correction vector for the k-th iteration is given

by
M!" = W“ - Wk (3.50a)
Ank = nk+1- nk (3.50b)
Ar)k = pk+l - pk (3.50c)
AT: = T5” - T: , (3.50d)

1: [(+1 k
ATP = Tp — Tp (3.508)

The Gummel method decouples the equations such that each system of equations
can be treated independently for each iteration cycle. Each system of equations are
solved sequentially and the variables are updated along each solutions. When all the
updates are less than a set of criterion for an iteration, the convergence is reached. The

Gummel method can be written as

 

 

 

 

 

 

-aFw(wk,n;:k,Tg,T§)]_Mk = _ W(\Vk.nk,Pk9T:~T;) (3.51a)

ZaFcn(‘|’k+l"la:’pk’T:’T:)]-Ank = _Fcn(wk+r.nk,pk,le.T;) (3,511))

[BFchkH’";l’pk’T:’T;)].Ap" = _Fcp(wk+1,nk+1.pqu:.Tg) (3.510

[3Fm(\llk+l,ﬂ:;,Pk+l’T:’T;)].AT; = _Fm(-Wk+1,nk+1'pk+1,T:‘T:) (3.5”)
n

[aF‘P(wk+l’nkgphl’Trl’Tp}AT: = "Ftp(‘vk+l’nk+l’pk+l'Tnk+l‘T;) (3.51e)
p

where (3.513) to (3.51e) are solved sequentially. At each stage only one semiconductor
equation is being linearized and solved by the Newton method, so the matrix being
solved has N rows by N columns regardless of the number of coupled equations being
solved. Whereas in the full Newton's method, all of the coupling between variables are

taken into account and the matrix size will be SNx 5N.

80

Because of the tight-coupling, the full Newton's method requires a smaller
number of iterations for convergence, however, since the matrix size is larger, it takes
more time to solve for each iteration. The Gummel method usually takes considerably
more iterations to reach the convergence while the time for each iterations is often less
than the Full Newton method because of the smaller matrix size. Depending on the
numerical technique and the exact device structure to be solved, the least time for a
solution to converge could be achieved either by a full Newton method or a Gummel
method [24]. However, when the limiting factor is the load of the computer memory, the
Gummel method is preferred because of the smaller matrix size.

Another technique to further alleviate the memory load and the computation time
required is the sparse matrix solution technique which has the following general features
[50]:

1. Only nonzero elements with necessary indexing information are stored.

2. Operations involving zeros are not performed.

The procedure of the sparse matrix solution Ax=B typically involves the following steps:

(1) Symbolic LU Decomposition: First, the nonzero elements of A are setup and the
location of the nonzero elements are recorded. Second, a symbolic LU
decomposition is performed Which does not actually perform a numerical value
computation but merely determines the new nonzeros (ﬁll-in) that will appear
after an actual LU decomposition. The locations of these ﬁll-ins are than used
to adjust the new data structure to include the location of the ﬁll-ins.

(2) Numerical LU Decomposition: This LU decomposition performs the numerical
calculations. The scheme used for LU decomposition is the Dolittle scheme
[50]. After the LU decomposition, the A matrix is now decompose into a L
matrix and a U matrix which is expressed as

A = LU (3.52)

where the L and U are upper and lower triangular mauices respectively.

81

(3) Solving for y from Ly = B followed by x from Ux = y gives the x solution
vector.
Special care is taken throughout the steps not to stored any zero elements and to index

the nonzero elements such that only nonzero element operations are involved.

3.2.5 Boundary Conditiom
The set of semiconductor equations are solved on the device grid points by the

methods described above. The grid point values located on the device electrodes are
predetermined by the boundary conditions. The boundary conditions used for the
simulation program are ohmic contact conditions which assume that the contact is
perfectly conducting. The potential on the electrode grid points are predetermined to be

‘1’ = \l’s + W8 (3.53)
where \Vb represents the built—in potential between the electrodes, and Va is the applied
bias to the electrode. The carrier concentration is determined by assuming thermal
equilibrium and vanishing space charge at the ohmic contacts,i.e.,

n p-n?=() (354)
and

P-n+ND-NA=0 (3.55)
Finally for the HTM device simulations, carriers at the electrode are assume to be in
thermal equilibrium with the contacts

n=n=n am)

where To is the ambient temperature of the device.

The boundary conditions along non-electrode boundaries are

82

 

8v
_=0
an
an,
an (3.57)
8T
n=0
an
er,
__—_0
an

Throughout the simulation, it is assumed that physical quantities have no variation in the
direction normal to the domain boundary, thus, no energy flux or current can flow

through non-electrode boundaries.
3.3 Physical Effects

3.3.1 Bandgap Narrowing and Auger/SRH Recombination
The recombination term implemented in this study includes both Schockley-

Reed-Hall and Auger recombination, i.e.,

 

 

 

R=RSRH + RA“g . (3.588)

where

’)
Rsau = "p' "‘1’ 3 58b
El - Ei Ei " El ( ° )
tp n+ nie exp kBT + 13n P+ “re exp kBT
and

R,” = c,,(pn2 - nnizc)+ 090192 - pnize) (3.58c)

In the above, Ei is the intrinsic Fermi energy, Et is the trap energy level, In and ID are
electron and hole lifetimes, cn and cp are Auger coefﬁcients, and nie is the effective

intrinsic concentration. The electron and hole concentrations using a Fermi-Dirac

distribution and a parabolic distribution of the density of states are given by

1
n = NC F112 {Fr-[EFT] - Ed} (3593)

83
1
p = Nv F1/2 iﬁEv - EFp] (3.591))

where NC and NV are the effective density of states in the conduction and valence bands.
EC and Ev are the conduction and valence band energies, BF“ and EFp are the electron and

hole Fermi energies, and F1,2 is the Fermi-Dirac integral. For the range of operation of

most semiconductor devices. Boltzmann statistics is a good approximation to the Fermi-

Dirac distribution and n and p can be simpliﬁed to
1 1'
n = NC exp{ﬁ[Ep. - 5.: ]}= n... exp

q 3‘
EW— 4).. )J (3.6()a)

‘—

 

 

1 ] ' q '
=N ex — -E =n-ex—- -)
P v p{kT[ v Eb]I re P_kT(¢p VJ (3.6%)
where rye can be expressed as the following by neglecting the band gap narrowing

effects:
nie(T) = «Nch exp(-—- Eg /2kT) (3.61)

In heavily doped semiconductor devices where the band gap narrowing effect can not be

ignored, nie is modeled as

9x 10’3q N(x,y) I: N(x,y)]2 1 I
n- X. = n- —-—-—-—- l —-——— ln —-
re( y) ,exp{ ZRBT [ n 1017 + 1017 + 2 (3.62)

where N(x,y) is the local (total) impurity concentration. The band gap narrowing effect

 

 

also requires adjustment of the electric ﬁeld terms in (3.24) as the following

' kT
En = -V “1+ :1“ Niel (3.63;!)

h

P

 

 

E ”1
p = ‘V ‘4” K ""ie (3.63b)

1.. .1

Energy gap and density of states are temperature dependent, their temperature

dependence can be expressed as
orT2

E T=E 0————
g() g() “MS

(3.64)

T 3/2 .
N m=(_) N 300 .
c 300 c( ) (3.65.1)

84

T 3/2
N T: — N 300
v() (300) v( ) (3.65b)

By assuming Boltzmann statistics, the diffusivities and mobilities can be related

by
kT
Du = :11.) (3.66a)
kT .
Dp = ‘q—llp (3.66b)

The low ﬁeld mobility model adopted by this study included the ionized impurity

scattering in silicon and is temperature dependent as [54]

 

2 -2.33
cm T
2 -o.57 1252 —— (—)
”a = 88 cm T + Vs 300K (3 67a)
Vs 300K 1+ C1 '

 

T )2546

1.432-1017cm’3(—
300K

for electrons and

 

2 -2.33
cm2 T ‘0'” 407 C31 [303K]
ll =54. — —— + S (3 67b)
P Vs 300K 1+ CI ~

 

25
2.67-10’7cm'3(—T—) 46
300K

for holes. T is the ambient temperature and CI is the sum of all ionized impurity species
times the magnitude of their charge state. In this work, CI is assumed to be the total
impurity concentration N(x,y). Equations (3.67) are supposed to be accurate to within a
maximum error of 13% in a temperature range of 250 to 500 K for a total ionized
impurity concentration range of 1013 to 1015 cm-3 [54]. (3.67) is the mobility model
suitable for DD simulations, for the HTM model, however, an energy dependent mobility
model is required. The use of Monte Carlo simulations to extract the energy dependent

mobility model will be discussed in Section 3.5.

85
3.3.2 Band-to-Band Tunneling Mechanism

The emitter and extrinsic base regions are close enough together in advanced
technology transistors that when the emitter-base junction is reverse biased, the stress
current is mainly a band—to-band tunneling current [33]. In most device simulation
programs, the tunneling mechanism is not included due to the complexities of treating the
quantum mechanical effects. The reverse bias stressing condition, therefore, can not be
solved in these device simulators. Recent work by Endoh et. al. [52] has included the
calculation of tunneling current for MOSFET structures. In this study, Endoh's work has
been extended to BJT device level simulations and applied to the experimentally stressed
BJT structure.

When transistors are operated at large enough base-emitter reverse bias conditions
the electrons in the valence band on the base side can tunnel to the conduction band on
the emitter side as shown in Figure 3.5. Following Kane's work, the band-to-band

tunneling rate can be described as a function of electric ﬁeld as [51-53]

2 1/2 2 “ml/213312
“3:12.171. xp[______sa_e.]

2 1/2 3.68
21th Egap thE ( )

where P is the tunneling rate per second per cubic centimeter, E is the electric ﬁeld, Egap

is the semiconductor band gap, and m is the reduced mass deﬁned as

$

22.12);
m; + m: (3.69)

where m: and m: are the effective mass for electrons in conduction band and valence

band respectively. Note that, (3.68) is numerically a factor of 9 times larger than the
original expression of Kane's as suggested by Chakraborty et. al. [53].

Although this model is valid only when the electric ﬁeld is uniform along the
tunneling path, the local average electric ﬁeld over the distance of the tunneling path is

used for the tunneling rate calculation. Endoh et. al. [52] has shown this approximation

86

 
 
 
 

Base Generation
of electron

O 0

Generation
of hole

   
 

Emitter

Figure 3.5: The band-to-band tunneling mechanism Showing the electron
tunneling from the valence band of the base to the conduction band of the

emitter.

87

to be valid even when the electric ﬁeld in the silicon is strong enough for band-to-band
tunneling.

The band-to-band tunneling has been implemented into the device simulation
program by treating the tunneling process as the generation of holes on the base side and

a simultaneously generation of electrons on the emitter side at values given by
gm = P(E) (tunneling end point) (3.70a)

G2", = P(E) (tunneling initiation point) (3.701))

where Gfun and Gﬁm are the generation terms to be included in the electron and hole

continuity equations for the device simulation program. The device simulation program
calculates tunneling (generation) at each point after each potential solution. By solving
current continuity equations along with appropriate generation terms the tunneling
current mechanism can be accounted for satisfactorily.

The tunneling current calculation is implemented by considering each grid point
in the simulation to be the beginning location for a tunneling event. All other grid points
in an extended neighborhood are then checked as possible termination locations for the
tunneling process. The neighboring point having the largest tunneling rate is chosen as
the tunneling termination point. The tunneling termination point must be spatially close
enough to the tunneling beginning point and at a potential that permits tunneling to
occur. If both of these conditions are met then a generation rate for electrons and holes is
calculated according to (3.68). The comparison of the reverse stress current predicted by
the band-to-band tunneling model with the experimentally measured values will be done

in Chapter 4.

3.4 Simpliﬁed Hydrodynamic Transport Model
When the emitter-base' junction is reverse biased, the electrons, as minority
carriers, in the base region (p-type) move into the emitter region (n-type) due to the

electric ﬁeld in the (depletion region. The HTM solves for the average electron

88

temperature (or energy) for the electron population. The averaging of the energies of hot
electrons which originate in the base region with the much larger population of electrons
in the emitter region causes the electron energy information to often be inaccurate due to
numerical accuracy limitation. In order to examine the behavior of only the hot electrons,
a simpliﬁed Hydrodynamic Transport Model (SHTM) based on the energy conservation
equation is developed in this section.
Equation (3240 gives the electron energy ﬂux as
Su = -)<(Tn )VTn - .I,,5('1'.,)k13'l”u /q. (3.71)

The ﬁrst term on the left hand side is neglected because the thermal conductivity is small
in the depletion region due to the small electron concentration (see (3.7), the
Wiedemann-Franz relationship). Due to a very strong electric ﬁeld in the depletion

region, the dominant current is the drift current. This allows the electron current density

Jn to be approximated by

J .. = qnunﬂ‘. )E. (3.72)
Since the SHTM will be applied to the surface portion of the depletion region, (3.71) can
be reduced to a scalar equation as

Sn z nunEﬁkBTn ' (3.73)
Note that when reducing to a scalar quantity, the electric ﬁeld is in the opposite direction

of the energy flux and was substituted by a -E term.

Neglecting the recombination term and using §-—§ as the energy absorption
1

6

rate, the energy conservation equation (3.24d) is expressed as

(isn 3 Tu -ro
—d—x—=JnE-n§k8 ‘tc (374)

 

Substitute (3.73) into (3.74) and assume that the dominant change in the energy flux is
due to the energy (electron temperature) change, the energy conservation equation can be

reduced to be

qE 3 T—T

_____ n 0

dx _ 5kB 2 “(Tn)5ETc. (3.75)

The use of (3.75) to solve for the electron temperature with the electric ﬁeld
extracted from a DD device simulation will be referred to as the 'Simpliﬁed
Hydrodynamic Transport Model' (SHTM). SHTM can be treated as an extension of the
DD model by solving an additional simpliﬁed energy conservation equation. The
consistency of the scheme adopted by SHTM can be veriﬁed by examining the electric
ﬁeld intensity and the electron population solved by full HTM device simulations and
DD device simulations. If the number of hot electrons is small compared to the overall
population, most of the macroscopic quantities are unchanged by this subpopulation of
electrons. Figure 3.6 shows the comparison of the electric ﬁeld and electron
concentration for a pn junction doped with 1018 cm'3 (p-type) and 1020 cm:3 (n-type)
operated at -4 V of reverse bias. This comparison shows that the SHTM is valid in the
reverse bias stress conditions.

Another way of deriving (3.75) is to consider the rate of gaining and losing

energy for electrons as

L15 — E

dx _ q (Energy Increase) (3.76)
d -

3% = -——§ 1:0 (Energy Decrease) (3.77)

e

The total energy increase of the electrons traveling a distance dx can thus be written as

 

dE, §-§ dt
_= E————°—
dx q 1,, dx, (3.78)
Assuming dx/dt = v = “E and § = 3kBTn/2, (3.78) can be expressed as
dTn __ qE _ Tu -'I'0
dx ng tcu(Tn)E . (3.79)

The similarity between (3.79) and (3.75) indicates that the SHTM can be

correlated to classical mechanics by suitably choosing the parameters 8 , 11, and re. The

9O

 

 

 

 

 

 

 

 

 

 

 

1024
1018 _ ’7
n 12
(cm—3) 10 _
106 ..
100 l l l
0.0 0.05 0.1 0.15 0.2
x(wn)
(a)
1.5
1.0 -
E
(106V/cm)
0.5 _
0.0 1 l 1
0.0 0.05 0.1 0.15 0.2
mun)
(b)

Figure 3.6: Comparison for (a) the electron concentration and (b) the electric
ﬁeld for a pn junction at -4 V reverse bias. Solid line is from DD model and
dashed line is from HTM model.

91

use of the Monte Carlo particle simulation technique to extract these material parameters
is explained in the next section.

It is assumed in the simpliﬁed HTM model that the interface states are created by
hot electrons and not hot holes. This approximation is made because the hot electrons
occurred spatially at positions where the depletion region is present during forward bias.
The hot holes occur more towards the base side of the depletion region and under
forward bias conditions this region is not in the depletion region. Any interface states

created by hot holes, therefore, do not expect to alter the forward bias electrical

characteristics.

3.5 Monte Carlo Method for HTM Parameter Extraction

To use the simpliﬁed HTM model requires the material parameters 8 , H, and re
as functions of energy or electron temperature. The Monte Carlo method is a particle
simulation which records the state of simulated particles before and after each scattering
event. The physical quantities such as the velocity, the location, and the energy at a
speciﬁc time can be derived from the information provided by the recorded states. The
scattering mechanisms included in this Monte Carlo method are ionized impurity
scattering, acoustic phonon scattering, and intervalley optical phonon scattering. The
band structure used was a nonparabolic band structure. In this section, the use of single
particle steady state and transient Monte Carlo simulations to extract the material
parameters will be explained.

The mobility 11 versus electron temperature is determined by using steady state
Monte Carlo simulations on an uniformly doped region for electric ﬁeld intensities
ranging from 5 X 104 V/cm to 1 X 106 V/cm. From Monte Carlo simulation, the average
velocity and energy at a speciﬁc electric ﬁeld is obtained. The electron temperature is

derived from the average energy E, as

92
3
§=§kBTm _ (3.80)

The mobility is derived by using the average velocity v and electric field E as

v(T )
T = “
(K I,) E .

 

(3.81)

The Monte Carlo simulations have been done to obtain the mobilities at lattice
temperatures of -75, 23, 175. and 240 C. Combining the energy independent mobility
model as described in (3.67) for the low energy limit with the Monte Carlo simulated
mobility versus electron temperature for impurity concentrations of 1015 cm:3 and 1018
cm-3 , the results shown in Figure 3.7 are obtained.

The material parameter 8 determines the rate of energy increase versus position
due to the external electric ﬁeld and 1, determines the saturation value of energy once 11
and 8 are ﬁxed. These two parameters are determined by ﬁtting the simpliﬁed HTM to a
transient Monte Carlo simulation. By using the electric ﬁeld extracted from DD
simulations for the transistor operating at -4 V reverse bias (see Figure 3.8a), the
transient Monte Carlo simulations were used to record the energy versus position as
shown in Figure 3.8(b). The simpliﬁed HTM was solved for the same electric ﬁeld
proﬁle. By adjusting the values of 6 and re , a best ﬁt was achieved. The same procedure
was used for extracting these two parameters at lattice temperatures of -75, 23, 175, and
240 C. The electric ﬁeld proﬁle and the ﬁt of simpliﬁed HTM to Monte Carlo simulation
at 23 C are shown in Figure 3.8(a) and 3.8(b) respectively. 8 and 1:, determined by this

method are listed in Table 3.1 for the four lattice temperatures.

3.6 List of Parameters for Device Simulations
For all the device simulations done throughout this research, the numerical values
of the material parameters and their corresponding equation numbers are listed in Table

3.2.

93

 

 

 

 

 

 

 

 

 

100 l I I l
0.0 2000 4000 6000 8000 10000
Tn(K)
10‘
N=1018 cm”3
103—
(b) u“ 102- -75C
(cmz/Vs)
240C
101_
100 T l l l
0.0 2000 4000, 6000 8000 10000
Tn(K)

Figure 3.7: The electron mobility versus electron temperature at lattice
temperatures of -75, 23, 175, and 240 C for doping concentrations of (a) 1015

cm‘3 and (b) 1018 cm-3.

94

1.5

 

1.0-Ill

E
“0 (106V/cm)

0.5 -

 

 

00 l 1 1 T
5.74 5.76 5.78 5.80
(11m)

 

2.0

 

1.5a

B
(b) “argyle—
(eV)

  

I I HTM
—- : Monte Carlo
0.5 _

 

 

 

0 l ' I r I
5.74 . 5.76 5.78 5.80
(11m)

Figure 3.8: (a) The electric ﬁeld proﬁle and (b) the ﬁt of simpliﬁed HTM

with the Monte Carlo simulation results at 23 C.

95

 

 

 

 

 

 

 

 

8 Te
(dimensionless) (psecond)
-75 C 2.0 0.13
23 C 2.0 0.15
__ 175 C 2.0 0.17
1‘ 240 C 2.0 O. 17

 

Table 3.1: 5 and 12e at four temperatures determined by ﬁtting the SHTM

with the Monte Carlo simulation.

 

96

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter Equation Number ‘ Value Unit

tp (3.58b) 1.0-10‘7 second

1:, (3.58b) 1.0107 second

C. (3.58c) 2.8-10-43 mi/s

cp (3.58c) 0.99.1043 ’ m6/s
E. (3.58b) E. eV

NC(300K) (3.65a) 2.81025 m'3
Nv(300K) (3.65b) 1.04.1025 m-3
EG(0K) (3.64) 1.17 eV

or (3.64) 4.73104 eV/ 0K

_ B (3.64) 636 0K
[\ 1nr (3.71) 0.14mO kg

 

Table 3.2: Parameters for device simulation program.

 

Chapter 4

Analysis and Simulation of Unstressed Bipolar
Transistor Characteristics

Before simulating the amount of hot electron produced degradation, the
unstressed characteristics must ﬁrst be simulated in order to establish an accurate
simulation model for the bipolar transistor. In this chapter, the unstressed bipolar
transistor characteristics will be analyzed and simulated for both the reverse bias stress
conditions and the forward bias Gummel measurement conditions. By ﬁrst obtaining a
good match between measurements and simulations for these unstressed conditions, a

more accurate simulation of the hot electron current and the degradation rate can be

achieved.

4.1 Reverse Bias Stress Conditions

The reverse bias stress condition will ﬁrst be analyzed by using PISCES-II [24]
simulations followed by using the device simulator developed in this work. Simulation
Studies using the PISCES-II simulator were conducted for TIN3 and TOUT devices
using the BJT structure as shown in Figure 4.1(a) in order to match the experimental
Characteristics of the unstressed transistors. The bipolar structure simulated has a length
of 9 11m and a depth of 1.4 um. The su'ucture includes an oxide interface in the region of
the base-emitter junction. Figures 4.1(b) and 4.1(c) show the actual and enlarged grid
structure used in the PISCES-II program for the BJT structure. The doping proﬁle
includes the intrinsic and extrinsic base regions, the emitter region, and the collector
region [36] as shown previously in Figure 2.4.

The PISCES-II simulator has been used to investigate the electric ﬁelds present in

the bipolar structure. The reverse bias stress conditions produced signiﬁcant hot electron
' 97

(a)

(b)

(C)

98

BASE OXIDE mm

 

 

 

 

 

         
 

  
     
 

 
 

 

   

    

        

E7 Lsaéueu§

t—t_‘_:_, ﬁftf‘cf‘.“

_.___“‘_;_; ‘ {3 ‘*

qggg—t‘gtc LL ugggm‘
‘5‘

 

1‘
§
géggi‘umm
E“§§L‘L‘L‘k\‘

   

 

 

Figure 4.1: (a) The BJT structure with 0.1 um thickness of oxide simulated

by the PISCES-H device simulator. (b) The actual grid structure for device

simulation. (c) The enlarged grid structure of (b).

99

degradation (see Chapter 2) which occurs at the oxide interface of the base and emitter
junction. Figure 4.2 shows the electric ﬁeld in the lateral direction at the emitter-base
junction just below the oxide interface for simulation bias values of -2, -3, and -4 volts.
The ﬁgure shows the electric ﬁelds calculated assuming two different lateral doping
proﬁles. The calculated electric ﬁeld assuming a spacing between the extrinsic base and
the emitter region of 0.4 [ml and lateral doping diffusions having the same form as the
vertical doping diffusions but shrunk by 60% are in the range of 0.7 x 106 to 1.1 x 106
V/cm. Alternatively, the calculated electric ﬁeld assuming a spacing between the
extrinsic base and the emitter region of 1.0 [1111 are in the range of 4 x 105 to 6 x 105
V/cm. These electric ﬁelds are sufﬁciently large to produce hot electrons. The presence
of large electric ﬁelds at the emitter-base junction is also indicated by the reverse bias
emitter-base junction current characteristics as shown in Figure 4.3. This reverse bias
characteristic shows a large leakage component which is likely a tunneling leakage
current [16]. Also present in the reverse bias characteristics is a more rapid increase in
the reverse current in the voltage range of 4.5 to 5 volts which corresponds to the start of
junction breakdown. Reverse bias breakdown voltages in this range are usually attributed
to breakdown by tunneling which requires an electric ﬁeld of approximately 1 x 106
V/cm [4].
The reverse bias electric ﬁeld was also simulated with a ﬁxed charge placed at the
Oxide interface. These simulations were done to assess the inﬂuence of oxide ﬁx charge
on the electric ﬁelds in the bipolar transistor, in particular, the vertical component of
these electric ﬁelds. In the simulator, the oxide ﬁxed charge concentration is varied by
the PISCES-II parameter Q,. The effect of this parameter is to provide a boundary
condition for the Poisson equation which determines the surface band bending at a given
bias voltage. With a relatively large reverse bias, however, band bending will be
determined by the bias voltage. For example, a large oxide ﬁxed charge concentration of

1 x 1012 cm-2 produced only a minimal change in the electric ﬁeld for stress condition

100

 

 

 

 

 

 

 

l 20
\of‘ too «
o
v-d
x
800 -
A
e
u
3
(a) v 600 "
U
.4
a)
LL "100 "
U
o
L: 200 1
000 f T
6 oo 6 10 6.90 6 so
urn
10" 6.00
O
H
x
6 oo -
A
e
t’
(b) 5
v M1 00 "
’3
m l
(I 2.00 .
6’
[3 oooJ . . .

 

 

 

6.00 6.10 6.20 6.3 6.90

UM

Figure 4.2: The lateral electric ﬁeld below the oxide interface with reverse
bias voltages of -2, -3, -4 volts for assumed spacings between the extrinsic

base and emitter region of (a) 0.4 um and (b) 1.0 pm.

101-

10‘4

 

10‘<5 -

-8_
(Amp )10

10‘10 a

 

 

10-12

 

1 1 l
0 l 2 3 4 5

VsnuissW 01t8)

—

Figure 4.3: The measured data of reverse bias stress current versus VBE at

room temperature.

102

reverse bias voltages. This change was observed as a small vertical electric ﬁeld
component as shown by the potential plots in Figure 4.4. This vertical ﬁeld component is
signiﬁcantly smaller than the lateral electric ﬁeld component. An absence of strong
vertical electric ﬁelds would suggest that the hot electron process proceeds as an
acceleration of the electrons in the lateral direction followed by an elastic or inelastic
(with only a small change in the electron energy) collision event which changes the
direction of the electron so that it interacts with the oxide interface breaking bonds or
becoming trapped in the oxide.

Since PISCES-II simulations do not include the band-to—band tunneling current
calculation, the predicted reverse bias stress current can not be compared to the measured
data. In the rest of this section, the reverse bias stress condition is simulated by using the
device simulator developed in this study. The bipolar simulations were done using both
the HTM and DD models. For the emitter-base reverse bias conditions, no difference was
observed in the currents and electric ﬁelds calculated by the two models.

The bipolar transistor simulated has the same emitter area as the one used in
PISCES-II simulations. The lateral doping proﬁle has been examined by ﬁtting the
reverse bias stress current to the measurement data. Figure 4.5 shows the reverse bias
stress currents for three different base doping levels with corresponding surface base
doping of l.lX1018, 5.6X1017, and 2.2X1017 cm-3. Since Figure 4.5 indicates that the
surface base doping of 5.6><10l7 cm-3 gives the best ﬁt to the experimental data, this
proﬁle was used for the extraction of the hot electron quantities as will be explained in
Chapter 5. The emitter doping profile in the lateral direction is the same as the vertical
doping proﬁle but is shrunk by 60%.

The electric ﬁeld for the 5.6X1017 cm-3 surface base doping BJT structure
operating at -4 V reverse bias has a peak value of l.3><106 V/cm comparing to the
l.l><106 V/cm predicted by PISCES-II simulation mentioned earlier. The temperature

dependence of the reverse bias stress current exhibits tunneling type characteristics.

103

Base _ Emitter

 

Enlarged Area —> -\L E

 

 

A A l A A A A l

 

 

Collector

(a)

 

 

 

(b) (C)

Figure 4.4: The potential plots for reverse biasing the transistor showing (a)
the transistor structure indicating the enlarged region, (b) the potential plot
without oxide ﬁxed charge, and (c) the potential plot with the oxide ﬁxed

charge.

 

104

 

 

_ C
10 12 l I l

2 3 4 5 6
Vsmrass(V01tS)

 

 

 

1028

 

Base Emitter

1026—

Doping
‘9 (mi)

10“.-

 

 

 

 

 

1022

 

 

 

1 1 l l
5.0 512 5.4 5.6 5.8 6.0 6.2
um

Figure 4.5: The reverse bias stress currents and their respective lateral doping

proﬁles showing: (a) The simulated reverse bias stress current and the

measured current versus V“. The dashed line is the measured data. (b) The

lateral doping proﬁles of different base doping level.

105
Table 4.1 lists the reverse bias stress current at VBE = -4V for the measured data and the

simulated data for temperatures of -75, 23. 175, and 240 C.

4.2 Gummel Characteristics

Simulations of the forward Gummel characteristics were also performed by using
both the PISCES-II simulator and the simulator developed in this study. By using the
same doping structure found in the previous section, PISCES-II produces the unstressed
current gain characteristics of the transistors at room temperature as shown in Figure 4.6.
The phenomena included in the simulations were bandgap narrowing. incomplete
ionization of donors and acceptors, Fermi-Dirac statistics, Auger recombination, and
Schockley-Reed-Hall (SRH) recombination. This ﬁgure shows the simulated values of
current gain, has, with all effects included (curve IFSBA), with Auger recombination not
considered (curve IFSB), and with Auger and SRH recombination not considered (curve
IFB).

The simulated transistor gain characteristics including all the above mentioned

phenomena are compared to the minimum and maximum measured gain characteristics

for the transistors in Figure 4.7. The midrange VBE values from VBE = 0.4 to VBE = 0.8
volts show good agreement. The low voltage region (VBE < 0.4 volts) of the
experimental data is undeterrninable because the current is less than I picoampere (the
limit of the measurement equipment). The high voltage region (VBE > 0.8 volts) shows
discrepancies which may be attributed to parasitic effects not included in the simulation
such as lateral device resistance and metalization voltage drops.

The forward-active bias conditions were also simulated to determine the electric
ﬁeld. Figure 4.8 shows the electric ﬁeld in the vertical direction along a line which
passes through the emitter, base, and collector. The collector-base voltage was 2 volts
and the base-emitter voltages were 0.6, 0.7, 0.8, 0.9, 1.0, and l. l. The electric ﬁeld at the

base-emitter junction was found by the simulation to be less than 0.5 x 105 V/cm. This

106

 

 

 

 

 

 

IR (Measurement) IR (Simulated)
(Amp) (Amp)
-75 C 2.83108 4.6910-8
23 C 5.43108 6.8810-8
175 C 3.29107 1.3910-7
240 C 1.94106 1.98107

 

 

 

 

Table 4.1: The reverse bias stress current at -4 V reverse bias for temperatures of -75, 23,

I75, and 240 C.

107

 

 

 

 

 

00.0 -
70.0 n
60.0 n
30.0 1
111:5 ~10 04
30.04 ' t:
a
30.0 . IFSBA ..
‘ IFSB ‘
10.0- . IFB
0.00‘1 v u t I l
0.00 .200 .900 .600. - . .000 1.00 1.20
VBE

Figure 4.6: Unstressed current gain characteristics at room temperature.
IFSBA curve included incomplete ionization, Fermi-Dirac statistics, SRH
recombination, bandgap narrowing, Auger recombination. IFSB curve does
not include Auger recombination. IFB curve does not include Auger and SRH

recombination.

108

 

70.0'I

50.0-I

 

-

30.0“ i “

20.0‘ I
) a SIMULATION

‘ MIN. 0F ”£95.
9 MAX. 0F HERS.

10.0-I

 

 

 

0.00 T V Y Y .
0.00 .200 .900 .600 .000 1.00 1.20

V1313

Figure 4.7: Simulated current gain compared to the minimum and maximum

measured current gain characteristics.

109

E19: Field (v/cm)

 

1 000

5000 ‘

0000 ‘

' $000 ‘

(x105)

“1.000 ‘

-l 500 ‘

 

 

 

 

‘2 000 I r I
0 00 300 600 900, 1 20 l 50

LN“

Figure 4.8: Electric ﬁeld siruulated in the vertical direction along the emitter,
base, and collector for v0, = 2 v and vBE = 0.6, 0.7, 0.8, 0.9, 1.0, and 121

volts.

110

magnitude of electric field is not suggestive of the creation of hot electrons. The electric
ﬁelds at the collector-base junction in Figure 4.8 show that there is only a minimal
movement of the peak electric ﬁeld into the collector region as the current increases. This
occurs because the collector doping is large enough to minimize the Kirk effect. The
electric ﬁeld for these forward bias conditions was also checked at the emitter-base
junction close to the oxide interface. For forward bias conditions, the electric ﬁeld in this
region was again less than 0.5 x 105 V/cm for VBE > 0.5 volts.

The device simulation program developed in this study was also used to simulate
the unstressed characteristics. The simulated Gummel plot including bandgap narrowing,
SRH recombination, and Auger recombination effects is compared in Figure 4.9 with the
room temperature experimental value. The simulated Gummel characteristic shows a
smaller collector current but gives a good ﬁt to the base current. The discrepancy for the
collector current is acceptable since (1) the goal of this simulation is to best match the
unstressed base current and (2) the degradation model to be developed will be based on
the changes in the unstressed and stressed base currents. The use and the development of

the degradation model will be described in Chapter 5 and 6.

111

10‘2

 

10‘4 a
10'6 .-

I , IC -3
(15ml?) 10 ..
10—10 _

10-12 _

 

10-14

 

 

 

0 0.2 0.4 0.6 0.8 l 1.2
VBE(Volt)

Figure 4.9: Simulated unstressed Gummel characteristics (solid line)

compared to the measured unstressed Gummel characteristics (dashed line).

Chapter 5

Simulation of Hot Electron Induced Degradation for
Bipolar Transistors

With appropriate degradation models, a device level simulation program can
provide a microscopic view of the degradation giving more insight for device lifetime
improvements. A complete analysis for the degradation of bipolar transistors must
consider both calculations of the number and energy of the carriers producing the
damage and the signiﬁcant tunneling currents at device degradation voltages.

This chapter presents the results of device level simulations that: (1) extract the
reverse bias stress currents including the band-to-band tunneling current mechanism, (2)
use the simpliﬁed Hydrodynamic Transport Model (SHTM) to solve for the number of
hot electrons per unit time adjacent to the Si-SiO2 interface where the damage occurs, ( 3)
predict the increase of surface recombination velocity based on an interface state creation
model calculated from the quantity of hot electrons, and (4) predict the voltage
dependence and time progression of the hot electron induced degradation. The

procedures are detailed in the following sections.

5.1 Hot Electron Current Simulations
The simulation of hot electron degradation at the reverse-biased base-emitter

junction in bipolar transistors begins by simulating the number of electrons passing

adjacent to the Si-SiO2 interface per unit time with enough energy to cause damage. This

quantity is best represented as the hot electron current density, Jhot.

As described earlier in Chapter 3, the electron energy solutions for reverse bias

junctions can be decoupled from the Poisson and the two continuity equations. By using

112

113

DD device simulations, the electric ﬁeld and the electron current density for reverse bias
stress conditions were extracted. The simulated BJT structure is shown in Figure 5.1. The
vertical doping proﬁle used was shown earlier in Figure 2.4. The simpliﬁed HTM model
is then used for the calculation of the average electron energy. To include the tunneling
generated electrons, the depletion region is divided into small intervals where in each
interval an SHTM energy calculation was applied to the subpopulation of electrons

generated due to tunneling in this interval. An average of electron energy is then

calculated to obtain the electron temperature Tn. Jhot is determined from the reverse bias
current density Idep and from the electron temperature Tn of the electrons originating in
the depletion-region according to the expression
Jhot =Jdep 'eXP(‘¢/knTn) (5.1)

where 0 is the energy threshold (2.0 eV) capable of producing hot electron damage [17].
Figure 5.2 (a) shows the hot electron current versus position for reverse biasing the
emitter-base junction of the bipolar transistors at room temperature for voltages of 3.5.
4.0, 4.5, and 5.0 volts. At higher reverse bias voltages, the hot electron current is higher
due to a higher electric ﬁeld. At higher electric ﬁelds, both the tunneling rate and the
electron temperature are increased leading to a larger Jhot. Figure 5.2(b) shows the
electron tunneling rate versus position for the corresponding reverse bias voltages. By
comparing Figure 5.2(a) and 5.2(b) it can be seen that the hot electron current originates
mostly from the band-to—band tunneling process. The magnitude of the hot electron
current originating from the base side is about 4 orders of magnitude smaller than that

originating from the tunneling process as seen by comparing 1,“,t at 5.75 rm to Jhot at

locations > 5.77 pm where tunneling is signiﬁcant.

114

 

 

 

 

  

 

 

x
6.0 8.5
1 l
Oxide
0
r Extrinsic ..
Base ........ . Intrinsic Base
Y P """
_1.4 Collector

 

 

 

 

Figure 5.1: Bipolar structure simulated. The dimensions are in micrometers.

115

103..

101-
Jhot 5.0V
(A/mz) _,

10 a

104..

10'5

 

 

 

 

 

5.7 5 .75 5.8
um
(21)
1035
103'3 .-
GTUN
(s-lm-3)
1031 _
1029

 

 

 

5.7 5 .175 5.8
-- rum
0»

Figure 5.2: (a) Hot electron current densities versus position for reverse bias

voltages of 3.5, 4.0, 4.5, and 5.0 volts. (b) The corresponding electron

tunneling rate versus position.

l 16
5.2 Degradation Model

In this section, the hot electron induced degradation is modeled by an increase in
the density of interface states resulting from hot electron damage of the Si-SiO2 interface.
The interface states give rise to an increase of the surface recombination velocity and
thus, the base leakage current.

From earlier MOSFET work [14—16], the interface state creation from a current

with energetic hot electrons can be written as

. I
N‘ 0‘ _d_ '¢/kBTn n
“ (t w e ) (5.2)

assuming the energy distribution of the hot electrons is Maxwellian. Id is the drain
current, W is the channel length, I is the stress time, Tn is the electron temperature. kB is
the Boltzmann constant, 0 is the critical energy for the breaking of a Si-H bond, and n is
the ﬁtting parameter for the relationship between the number of hot electrons present and
the number of interface states created. For BJT simulation, it is found that the rate of
creation of interface states has a different time dependence [7,8]. Equation (5.2) is
modiﬁed to become
Ni. ... (t)“‘ (J ho.)“= (5.3)

where nl and 112 are parameters which are adjusted to achieved a best fit for the
dependence on the stress time and the hot electron current density.

After the hot electron current is solved along the Si-Si02 interface, the number of
reverse bias induced interface states in the base-emitter depletion region is imported into
the forward bias Gummel characteristics calculations. The increase of the interface state
density results in an increase of the surface recombination velocity which is expressed as

So = “MN it (5.4)
where 6 is the scattering cross section and vm is the electron thermal velocity. Equation
(5.3) and (5.4) can be combined to formulate an expression suitable for device simulation

programs. The combined equation for the surface recombination velocity is

117

so = 6(1)“! '(J,,(,,)'12 (5.5)
where c is a ﬁtting parameter which includes the effects of scattering cross section and
the thermal velocity for electrons in silicon. In the forward Gummel measurement where
the electric ﬁeld is weak, the thermal velocity and scattering cross section can be
assumed to be constants for a given ambient temperature. Therefore, 0 is a constant for a
given device fabrication technology and ambient temperature.

The surface recombination velocity increases the surface recombination rate
which is implemented in the device simulation program by using an equivalent surface
recombination life time given as [24]

__ Ai .
17SUR — S d. (5.6)

 

where A. and di are the area and length of the interface associated with grid point i. The

total effective recombination lifetime can be written as
1 1 l

— +
Terr Isun 1:snri - (5'7)

This effective lifetime is used for recombination rate calculations in the device
simulation program in order to model the increase of base leakage current due to the
increase of the surface recombination velocity. The simulated degraded characteristics

are presented in the next section.

5.3 Simulation of Degraded Characteristics
To calculate the forward degraded characteristics, the surface recombination

velocity along the interface is ﬁrst calculated based on the stress time and the appropriate

lb“. The surface recombination velocity values along the oxide interface for reverse

biasing the emitter-base junction at -4 V for stress times of l, 24, and 500 hours are

shown in Figure 5.3. The parameters used for Equation (5.5) is c = 3.8, 111 = 0.35, and 112

= 0.8. The surface recombination velocities for a stress time of 200 hours at reverse bias

voltages of 3.5, 4.0, 4.5, and 5.0 volts are shown in Figure 5.4.

118

 

104..

S
(cn‘i/s)
102 .4

 

 

 

5.7

 

Figure 5.3: The simulated surface recombination velocities for a reverse bias

of -4 V after stress times of l, 24, and 500 hours.

119

 

 

 

 

 

Figure 5.4: The simulated surface recombination velocities for reverse bias

voltages of 3.5, 4.0, 4.5, and 5.0 volts after 200 hours stress time.

' 120

Since the Gummel characteristics measurement has a zero collector-base voltage
while the emitter-base voltage is forward biased, the electron temperature throughout the
device is not high. Therefore, the forward Gummel characteristics resulting from the
calculated surface recombination velocity proﬁle is simulated by the Drift-Diffusion
model to obtain the degraded characteristics. By using the degradation model described
above, the degraded characteristics are simulated and compared to the experimental
studies as described inChapter 2. For an example of the modeling of the rate of hot
electron induced degradation, Figure 5.5 compares the simulated and measured base
currents for stress times of 0, l, 24, and 500 hours at -4 volts 23 C. For the modeling of
the voltage dependence of hot electron induced degradation, Figure 5.6 compares the
simulated and measured base current at reverse biases of 3.5, 4.0, 4.5, and 5.0 volts for a
stress time of 200 hours. The parameters c, 111, and 112 were obtained by ﬁtting the
measured and simulated data in Figures 5.5 and 5.6. Figures 5.5 and 5.6 show an
excellent ﬁt to the measured results except for stressing the BJT at 5 volts for 200 hours.
The discrepancy is understandable since the 5 volts reverse bias is near breakdown
voltage and the hot electron degradation process could be altered.

The good agreement for the predicted results for the voltage dependence and time
evolution of the degraded characteristics indicates that the degradation model is suitable
for implementation into a device level simulation program to predict the change of
device degradation when the device design changes. For operating the transistors at
temperatures other than room temperature, temperature effects must be carefully

evaluated. The next chapter presents a model that includes the temperature effects.

121

 

 

 

 

1.2

 

Figure 5.5: Comparison of experimental (solid lines) and simulated (dashed

lines) base currents versus VBE for stress times of O, l, 24, and 500 hours at a

stress voltage of -4 volts.

122

 

 

 

 

 

Figure 5.6: Comparison of experimental (solid lines) and simulated (dashed
lines) base currents versus V315 for stress times of 200 hours at stress voltages
of -3.5, 4.0, -4.5, and -5.0 volts. Also shown is the initial base current

characteristic.

Chapter 6

Degradation/Annealing Model for Bipolar Transistors

The study of the temperature dependence of the rate of hot electron induced
degradation is presented in this chapter. The temperature dependence is discussed in view
of the hot electron current densities simulated and the experimental data on degradation
and post-degradation annealing. A model is developed to describe the temperature

dependence of degradation and post-degradation annealing.

6.1 Hot Electron Current Simulations

The simulation of hot electron currents for different temperatures at 4 volts
reverse-biased on the base—emitter junction follows the same procedure as that described
in Section 5.1. The hot electron current density, Jhm. along the base-emitter oxide
interface for the bipolar transistor is solved by using the simpliﬁed HTM model at
temperatures of -75, 23, 175. and 240 C. The simulated BJT structure is the same as that
described in Chapter 5.

Figure 6.1 shows the hot electron current densities versus position for
temperatures of -75, 23, 175, and 240 C. The magnitude of the hot electron current

density originating from the base side (hot electrons at positions less than 5.76 pm) is

seen to be smaller than that from the tunneling process. In particular, at -75 C, 1,“,t is
about 4 orders of magnitude smaller, while at 240 C. lhot is only about 2 orders of
magnitude smaller for the hot electron current originating from the base. This occurs

because the minority carrier concentration is more temperature sensitive than the

tunneling process. At a speciﬁc location, Jhot is seen to increase with increasing

123

124

 

 

 

 

 

105
103 —.
Q
1013 240 C ’l \
Jhot
(Almz)
lo—l _ I
—75 C
10'3 .-
10-5 r K
5.7 5.75 5.8
l.lrn

Figure 6.1: Hot electron current densities versus position for the bipolar
transistors operated at -4 volts reverse bias for temperatures of -75, 23, 175,
and 240 C.

125
temperatures. The temperature dependence of Jhot can be explained by examining the

expression deﬁned earlier in Chapter 5, namely,
JhOl .2]de ’exp(-¢/kBTn) (6.1)

where Jdcp is the reverse bias current density and Tn is the electron temperature. The
dominant reverse bias current is the band-to-band tunneling current and since the energy
gap monotonically decreases with increasing temperature, the reverse bias current

increases with increasing temperature resulting in the value of Jhot increasing. On the

other hand, the electron temperature decreases with increasing ambient temperature due
to the increased phonon scattering rate. This reduces the value of 1,“. Depending on
whether the dominant change comes from the increasing reverse bias stress current or the
decreasing electron temperature, the number of hot electrons capable of device damage
could either increase or decrease with increasing temperature. For the TIN3 devices
operated at constant reverse bias, the simulation study shows that the electron
temperature has a weak dependence on the ambient temperature due to the very short
depletion width and high electric ﬁelds at the emitter-base junction. For this case, the
electric ﬁeld plays a dominant role in determining the electron energy as shown in (3.75).
Since the electric ﬁeld for a constant voltage biased emitter-base junction is weakly
temperature sensitive, the increase of the reverse bias current dominates over the electron
temperature change and is responsible for the increase of the Jhot value.

In general, for advanced technology transistors where the depletion width is
narrow and the electric ﬁeld is strong, it is more likely that the tunneling current
dominates and a larger number of hot electrons is expected at higher temperature whereas
for transistors with lower doping levels (e.g. no extrinsic base region) a smaller number
of hot electrons is expected at higher temperatures. In Burnett’s work [15] where
transistors with base doping level of 1014 cm‘3 were used, a larger degradation was found
for transistors stressed at 110 K than at 300 K. In Momose's work [13] which did not

report the doping level of the transistors. for a temperature range of -10 to 200 C, the

126

degradation at 50 C was found to be larger than at -10 C. It is speculated that in [13]. a
higher doping level for the base diffusion was used resulting in larger degradation at 50
C. The degradation at 200 C was also seen in [13] to be smaller than at 50 C. This occurs
because an additional annealing effect at higher temperatures takes place. This effect is
also consistent with the degradation data in this work to be described below and

previously in Chapter 2.

6.2 Degradation and Annealing Model

The hot electron current density increases with increasing ambient temperature
for the transistors reverse biased at -4 volts on the emitter-base junction. The rate of
degradation as described earlier in the experimental study of Chapter 2, however, is
generally smaller at higher temperatures. This occurs because at higher temperatures a
simultaneous annealing effects can happen such as shown in Figure 2.33 where a portion
of the degraded base current can be annealed out within a very short time. The fact that
the hot electron produced states are not all permanent is also indicated by the fluctuation
of the base current in the short time scale stress experiment as described earlier in Section
2.4.3. Therefore. at high temperatures, even though the hot electron current creates more
leakage states. more states are simultaneously removed. The overall effect is less
degradation.

In order to include the phenomenon of simultaneous annealing or repassivation in
a BJT degradation lifetime model, the degradation model of Burnett and Hu [9] has been
extended. The model is developed by writing the degradation/annealing rate as

dAIB —¢

=CI ex
dt ”‘ “kg,

 

)g(AIn)"C2AIB (6.2)

 

where A13 is the change in base current, g(AIB) is the dependence of the degradation rate

on the previous degradation, IR is the reverse bias stress current, 4) is the electron energy

needed to produce damage, Tc is the electron temperature, and Cl and C2 are coefﬁcients

127

that are temperature dependent. The term gmlg) is given a form (Ala)—h following the
work of Burnett and Hu. The ﬁrst term on the right side of (6.2) models the degradation
process caused by hot electrons where the exponential function gives the number of hot
electrons available at a given electron temperature. In this work, this corresponds to the
hot electron current. JhaLpr, where L1, is the emitter perimeter and 2p is the maximum
effective distance from the oxide-silicon interface that hot electrons can be created and
still reach and damage the interface. The C2AIB term in (6.2) models the repassivation

component, and it is an addition to [9]. The solution for AIB is

AIB = [%'L"—(l-exp(-C2(1+h)t))] (6.3)

2

where n=l/(1+h). The 1..p and Zp quantities have been incorporated into the CI quantity.

The role of the C2 term is to cause a reduction in the net degradation rate as A19

increases and an eventual saturation of the degradation in base current. This saturation

value, (1113),... according to (6.3) is
c J “
(AIB)sat = [A] (6-4)

The application of this model to the experimental stress results is shown in Figure
6.2 which plots the base current change AIB versus stress time for degradation and
subsequent annealing at 240 C. Equation (6.3) contains four parameters including lb", 11
or h, C,, and C2. Of these four parameters, two of them (C1 and n) are obtained by ﬁtting
to the degradation data shown in Figure 6.2(a). The value of I,“ used is the peak value of
the hot electron current density obtained previously in Section 6.1. The C2 value is

obtained from the annealing data of Figure 6.2(b) by ﬁtting the annealing data to

Equation (6.2) after setting the stress currenth to zero giving
dAlB
dt

 

= -C2AIB ‘ (6.5)

Solving (6.5) gives
AlB = AIB (0)exp(-C2t) (6.6)

128

10’8

 

 

 

 

10'11
-l 10 11 I l
10 10 10 102 103 104
Time(hours)
8 (a)
10"

 

10-9 -k

(Amp)

10-10 _

 

 

10-11

 

1 l 1

0 50 100 150 200
Time(hours)
(b)

Figure 6.2: Experimental (squares) and modeled (solid line) degradation and
annealing data. (a) Degradation at 240 C. (b) Annealing at 240 C.

129

where AIB(0) is the post-degradation value of A13. The annealing data from Figure

6.2( b) gives a value of C2=O.0014.

The ﬁt of Equation (6.3) to the experimental data for degradation at T=240 C
using the already determined 1,0, and C2 values gives n=0.5 and C,=l.4><1024.
Speciﬁcally, when the degradation of base current versus time is plotted on a log-log

scale. the data for times less than 100 hours forms a line of slope n.

6.3 Temperature Dependence
The temperature dependence of the degradation is determined by the number of
hot electrons and the repassivation rate of hot electron created states. The values of n,

Jhm, C,, and C2 for temperatures of -75, 23, 175, and 240 C are given in Table 6.1 with

the ﬁt of the model to the experimental data given in Figure 6.3.

Jhot is determined by simulating the current flow and electron energy at the
various temperatures. It is signiﬁcant to note that for constant voltage stressing the
number of electrons with an energy above 0 increases as the temperature is increased due
to the increase in reverse bias current

The determination of C, and C2 as a function of ambient temperature requires a
closer look at the annealing behavior of the degraded bipolar transistors. The annealing
rate at a given annealing temperature depends on the degradation conditions used. This is
illustrated in Figure 6.4 where two groups of devices were degraded at 23 C and 240 C
respectively. The degradation was stopped when the base leakage current at VBE = 0.6
volts had increased by l nanoamp. To produce this equal level of degradation the 240 C
degradation took 1000 hours and the 23 C degradation took about 100 hours. The
subsequent annealing of these two groups of devices at 240 C for 200 hours showed two
different annealing behaviors. The 240 C degraded devices showed only a slight
recovery, whereas, the 23 C degraded devices showed a substantial recovery with the

largest recovery occurring almost immediately (within 1 hour) upon the initiation of the

10'8

10‘11

130

 

 

    

-75 C 23 C

+:+240C
-: model

 

10‘1

I I I
10° 101 102
Time(hours)

1

103

 

104

Figure 6.3: Change in base current at V312 = 0.6 V versus time. The solid lines

are calculated values from (6.3). The symbols are experimentally measured

values.

131

10‘8

 

 

AI
(Amixlw'9

 

 

 

 

 

 

Figure 6.4: Annealing data for two groups of devices. Group 1 was degraded
at 240 C for 1000 hours and group 2 was degraded at 23 C for 100 hours. Al,3

values are for vars = 0.6 volts.

132

annealing process. The physical process of degradation believed to be occurring is that
hot electrons are creating surface states at the silicon-silicon dioxide interface. A portion
of these surface states are repassivated as seen earlier in Figure 2.26 which showed
spontaneous gain recovery during the stress. It is further believed that the size of this
repassivation increases as the temperature increases. Hence, net degradation at a high
temperature is much slower because a large portion of the surface states are annealed out

shortly after their creation. This portion of the repassivation that occurs quickly will be

referred to as rapid repassivation. In Equation (6.2), the C, term has a temperature
dependence due to the number of hot electrons given by 1,0, and by the amount of rapid
repassivation which is included by reducing Cl as the temperature increases.

Another feature of Figure 6.4 is that after the ﬁrst few hours of annealing, the
annealing rate as indicated by the slope of logarithm A13 versus time is similar for both
the 23 C and the 240 C degraded devices. This indicates that once the rapid repassivation
portion of the states have been annealed out, the annealing process proceeds in a similar
manner regardless of the degradation temperature. These long time annealing

observations are used to determine the value of C2 as a function of temperature. Figure

6.5 shows the results of annealing devices at T =175 C and 240 C which were originally
degraded at 23 C for 500 hours. The values of C2 are determined by ﬁtting the annealing

data for long annealing times to

AI,3 = A135,“, (0)exp(-C2t) (6.7)
which is a modiﬁcation of (6.6) where A135,”, (0) is the post-degradation value of the
slow repassivation portion of A13. The temperature dependent C2 values are given in

Table 6.1. Since no annealing is observed at -75 and 23 C, the C2 value is negligible. An

-EA
kT
A ﬁt of the two measured C2 values gives C20 = 0.0134 and E A = 0.10 eV. The C2 value is

 

alternative model for C2 is an activation energy relationship where C; = C20 6Xp( ).

133

 

 

 
  

 

 

 

 

 

10"
“B 10‘9
(Amp) 175 C Annealing
81......0 . ........................... 4
AIB.slow(o) - ........
240 C Annealing A
o
10.1 f I I 1
o 100 200 300 400 500
Time(hmm)

Figure 6.5: Annealing of the base current at VBE = 0.6 volts versus time for

the two annealing temperatures of 175 and 240 C. The symbols indicate

experimental data and the dotted line is the ﬁt of the data to (6.7). The
transistors were ﬁrst degraded for 500 hours at VBE = -4 volts at room

temperature.

134

 

 

 

 

 

 

 

 

 

 

T Jhot ‘ C1 C2
(0 C) (A/m-Z) (Am-1) (hr-1)
-75 193.6 5,0x 10-23 (small)
23 C 274.5 5,0X 10'23 (small)
175 519.9 6.4x 10‘24 1.0X 10'3
240 758.4 1.4x 10‘24 1.4x 10‘3

 

Table 6.1: Parameter values for the ﬁtting of Equation (6.3) to the

experimental data as shown in Figure 6.3.

135
also used to model the data in Figure 6.3. C2 is important in determining the saturation

value of the degradation as indicated by Equation (6.4). The ﬁt at the higher temperatures
of 175 C and 240 C is good, at -75 and 23 C no saturating effect is predicted by
simultaneous annealing. After stressing for longer than 100 hours, both -75 and 23 C
degradation rates are lower than that predicted by Equation (6.3) possibly attributed to a
limit being reached at higher degradation levels in the number of interface states formed.
This limiting effect was found in earlier work by Hackbarth and Tang[ 10].

Without the simultaneous annealing effect, the degradation rate is expected to be
larger at higher ambient temperatures for transistors dominated by band-to-band
tunneling in reverse bias as found in many advanced technology transistors. Including the
simultaneous annealing effect, the degradation rate decreases with increasing
temperatures once the annealing takes place. The overall result can then be an increasing
degradation rate with temperature at lower temperatures followed by a decreasing
degradation rate at higher temperatures with the maximum degradation rate
corresponding approximately to the onset of simultaneous annealing. This temperature
dependence is seen for the ﬁrst few (time < 10 hours) data points of Figure 6.3 with the
23 C data exhibiting the largest degradation rate. In Momose's work [13], the same
phenomena was measured with the peak degradation rate at a ambient temperature of 50

C.

Chapter 7

Conclusions

The degradation of bipolar transistors caused by hot electrons was investigated at
room temperature for emitter-base junction reverse biases of 3.5, 4.0, 4.5, and 5.0 volts
for up to 1000 hours. The degradation was also investigated at a constant reverse bias of
4 volts for temperatures of -75, 23, 175 and 240 C. The interface states created by the hot
electrons provide sites for surface recombination-generation to occur leading to base
surface leakage currents and a reduced current gain. For constant temperature stresses.
larger voltages of reverse bias were seen to create more degradation. At a constant
voltage, reverse bias stressing at higher temperatures was seen to generally cause less
degradatiom

The temperature dependence of the annealing of the states created was studied by
using post-degradation thermal annealing experiments at a temperature range of 50 to
240 C for transistors stressed at room temperature and at 240 C. The states removed by
the thermal annealing were found to be distinguishable into fast and slow repassivation
components with the fast component being easily annealed out and the slow component
being resistive to annealing. The ratio of these two components was found to be very
temperature sensitive, i.e., a larger portion of the interface states for the fast repassivation
component at a higher temperature.

Short time scale stress experiments were conducted to examine the lifetime of the
states created by hot electrons. The results showed ﬂuctuations of the base current
indicating the hot electron created states were not all permanent. AC experiments for
50% reverse bias stress cycling time only and for 50% reverse and 50% forward cycling

time were performed. The transistors stressed with forward bias cycles showed less

136

137

degradation indicating the removal of hot electrons created states by the forward bias
applied voltage.

In order to solve for the reverse bias stress conditions, a band-to-band tunneling
model was implemented into a device simulation program developed for this study. The
hot electron current density was calculated by a simpliﬁed Hydrodynamic Transport
Model (HTM) and related to the interface states created in a spatially dependent,
microscopic fashion. The increase of the surface recombination velocity due to the
increase of interface states was taken into account by a two-dimensional device
simulation program to predict the base leakage current.

The device level band-to-band tunneling was implemented by an electron and
hole generation rate model calculated based on the band bending and electric ﬁeld
information. The reverse bias stress current predicted by the band-to-band tunneling
model was in good agreement with the measured data. The band-to-band tunneling
mechanism provides a microscopic view for the behavior of the tunneling electrons under
reverse bias stress conditions.

HTM and the drift-diffusion (DD) model simulations were done for the reverse
bias stress conditions. The results were compared and no signiﬁcant difference was
observed in the I-V characteristics. The conclusion is that the energy conservation
equation can be decoupled from the full HTM model for reverse-biased junctions with
sufﬁciently low current densities. A simpliﬁed HTM model is proposed which is based
on a decoupled solution of the DD model and the energy conservation equation. This
model predicts the electron energy under .various reverse bias stress conditions.

In order to analyze the magnitude and location of hot electron generation, a hot

electron current density, lbw was proposed which conveniently represents the number of
hot electrons passing a local region per unit time above a threshold damage energy. 1,“, is
the portion of the total electron current density that is responsible for the device interface

state creation. The hot electron current densities were solved for these stress conditions,

138

namely, for reverse biases of 3.5, 4.0, 4.5, and 5.0 volts at 23 C, and for a 4 volt reverse
bias at temperatures of -75, 23, 175, and 240 C. Comparisons were made for the
magnitude of the hot electron current densities originating from the base side and from
the tunneling process. The results showed that the majority of the hot electrons originate
from the tunneling process indicating the importance of including band-to-band tunneling
process into the reverse bias calculations. For the constant voltage-different temperature
stresses, the hot electron current densities were found to be increasing with increasing
ambient temperatures. This phenomena was caused by the more rapid increase of the
tunneling rate as compared to the decrease of the electron temperature as the ambient
temperature increases.

For higher temperatures of reverse bias stressing, an additional annealing effect
was found to take place which removes some of the interface states created by hot
electrons. This phenomena was studied by using the hot electron current density
simulations and the post-degradation annealing experiments. Despite the larger hot
electron current density at higher temperatures, a simultaneous annealing removed many
states created by the hot electrons resulting in a smaller degradation rate at higher
temperatures. The degradation/annealing model developed in this study extends the
degradation model developed by Burnett and Hu and includes the saturation of the
degradation and the simultaneous degradation/annealing effect not accounted for in
previous models.

By using the hot electron current density simulated and a surface recombination
velocity model, the degraded characteristics and subsequent device lifetime of bipolar
transistors can be determined. The model can be applied in the prediction of the device
lifetime due to hot electron induced degradation as the geometry. doping proﬁle.

temperature, and stressing/operating conditions are varied.

Appendix A

Discretization of J and S in Scharfetter-Gummel Form

Discretization of J:
The discretization of the electron and hole current densities starts with the

expression for electron current density [46].

J = anJ(T)E + anu(T)%I+ kBT (11.111109)
X

dx , (A1)
Or, (Al) can be rearranged as

(“011(0) 91 ] _
kBT(x) dx + [nu(T)(qE+ 1‘8 dx - J. (A2)

dT
Assuming E, 5;, and J are all constants across the spacing between grid points. (A2) can

bewrittenas

dT
d(nll(T)) + “n(quE + kB 3;) J

 

 

 

 

dx kBT(X) = kBT(X) (A3)
From a general mathematical handbook [55], the solution of (A3) is
x1+l qE ‘1’ kZdT
nu(T) exp( ——-x——dX)

_ I, kBT(X)

x1.1 J 1"1.1 qE+ deT

= [ —exp( [ ——£‘é—dx)dx+ C
xi kBT xi kBT(x) ( A4)

The left hand and right hand sides of (A4) can be solved to become

139

140

x. 1 ldT
dT " Td_x
. B—
LHS= nu(T)e ‘ dx
(qE+k dT)ln(T)——l—
B—

In T) (qE+ 1939:);—
= nu(T)[e ( ] dx deT/dx

= 1111(T)Ta+l (A5)
where
0, = _9_E_

and

 

 

Ta+l
= deT/dx ml

kg

 

I... . (A7)

Hence, (A4) is now expressed as
xi+l

 

nu(T)Ta+l Km = J To”1
x. deT/dx oc+ 1|»

 

 

 

(A8)
Rearranging (A8) yields
[nlI(T)l- .T-“i‘ — lnu(T)l- “11“”
J=k3ﬂ(a+l) 1+ 1: + . x
dx Tifll - Tia 1 (A9)
In the expression of (A6), or is discretized to be
or _ _ (“Wm - W1)
m _
kB(Ti+l - Ti). (A10)

Using (A10), (A9) can be written as

141
J _ [_ q(Wi+1- W1) + Rama - T9}
m _
Mn-Xi Mn-xi

[0110911419(am+l)mm"/Ti)- [n11(T)],
e(am-l»l)1[1('1",+1/'1‘,)_ 1 (A1 1)

 

(Al 1) can be simpliﬁed by the use of Bernoulli functions given by

e’x 1

 

 

 

=-—Bx
e_,_1 x () . (A12)
1 l
=-—B-x
e'x—l x ( ) , (A13)
where B(x) is deﬁned as
x
B =
(’0 ex_1 (A14)

Using (A12) to (A14), (Al 1) can then be expressed as
, = [_ clot... -\v.) + km... -T. )], [011m].B(-6)-[nll(T)lt+tB(6)

 

 

m x1+1 ‘ xi x1+1 ‘ xi 9
(A15)
where 6 represents
9 = -(01m + l)ln(T,+, /T,) (A16)
and Otm is given by
= _ (1(11’141- Wt)
m k13(1)“ - Ti) (A17)

(A15) is the discretized expression for the electron current density. For the hole current
density, similar expression can be derived following the same procedures. Note,
however, that if one substitutes E by -E, multiplies J by -1, and changes the electron
mobility to hole mobility the electron current density expression (Al 1) transforms to that

of the hole current density expression.

Discretization of S:
The discretization of electron and hole energy density ﬂux starts with the

expression for electron energy density ﬂux [46]

142
T

s = — k(T)£— J3(T)kB —
dx q (A18)

By using the Wiedemann-Franz relation,

2
km {53) A(T)T
qnu(T) Cl

 

(A19)

and substituting (A1), (A18) can be expressed as
2
s = {4152) A(T)qnu(T)Tﬂ
. 9 dx

_ qnu(T)E8(T)kB-E

_ kﬂWéﬂkB I

dT T
-k T—5Tk —
an)“ )dx ( ) Bq (A20)

Or, after rearranging terms, (A20) is written as

kBT —8(T)——— dlnuml
dx

1%, or
k35(T)E + —(A(T) + 5(T))— n|J.(T)T = — S
(1 dx . (A21)

(A21)canbefurther rearranged tobe
k A(T) dT
E L_
q + 5(T) dx = _ A
W Law
q (A22)

+ [nu(T)Tl

 

dlnu(T)Tl
dx

(A22) and (A3) are in similar forms. Equation (A22) can be developed parallel to that of

the discretization of I described in the above section, i.e., let
(“Witt-1 " W1)

or = -
m Ti+l - Ti (A23)

and one obtains the discretized electron energy density ﬂux as

143

S =_k35(T) _q(WI+l—Wi)+%kB(Ti+1-Ti) .
m q x. -x- xi+l""i

1+1 1
[[nmrmi+l exp[(0tm + %)ln(Ti+1 /T,)]- [nu(T)T],]

 

 

expﬂam + %)10(Ti+l/Ti)]- 1 (A24)
Similarly, for holes, the energy ﬂow can be written as
dT k T
sp = —k(T)—2-+,Jp6(r) B P
dx 9 (A25)

Parallel to that of developing electron energy ﬂow discretization equation, i.e. substitute

the Wiedemann-Franz relation and the expression of Jp,

d(pu) dT
J = - k T — k —
p qqu- B dx BPF1 dx (A26)

 

Sp can be expressed as
‘)
k " dT
Sp = {—3) A(T)qpll(T)T—
q dx

+ qpll(T)55(T)kBE

_. kBTWNTWB I.
dx q

dT T
_ kBpp.(T)—5(T)kB —
d" 9 (A27)

Comparing (A27 ) to (A20), it is seen that the discretized form of hole energy ﬂux can be
obtained by a simple substitution of E by -E, n by p, and electron mobility by hole

mobility in the expression for electron energy ﬂux.

Appendix B

Input File Description for Device Simulation Program

The input ﬁle speciﬁcation for this device simulation program is described in this
appendix. The input ﬁle must be saved as the ﬁle name 'input' and within the input ﬁle,
the entries are case-sensitive, i.e., upper case and lower case should be distinguished. The
simulation program ﬁrst executes various data input subroutines to provide necessary
information before it can performed the simulation. The program reads one 80 character
line at a time, analyzes the ﬁrst three letter, decides what information is contained in the
next few lines and reads the appropriate inforrnations. Typically, the ﬁrst three letters are
in upper case and acts like a command to the program. The program then appropriately
reads the next few lines which have the information data to be loaded or executed. Empty
lines are allowed in the input ﬁle to separate the commands and information data. The
empty lines are simply ignored. The following lists the allowed commands and the

appropriate information data:

COM

syntax COM<arbitrary user input characters>

description The comment line is used to let the user put some comments in the line.
The program does nothing with the line.

example COMMENT : This is the structure used in the research.
COM The extrinsic base doping proﬁle:

GRD
syntax GRD<arbitrary user input>

<yline number> <ylocation> <yratio>
144

description

example

CON

syn tax

145

<yline number> <ylocation> <yratio>

999 0.0 0.0
<xline number> <xlocation> <ylength>

<xline number> <xlocation> <ylength>

999 0.0 0.0

The GRD command ﬁrst reads y meshes speciﬁcations (horizontal mesh
line) then reads x meshes (vertical mesh line). The simulation program
reads in the line number and than the location. The ratio is the ratio
between the distances between the adjacent lines. The program will
automatically determine the distance between the lines to satisfy the ratio
speciﬁcation. Horizontal mesh lines are layout from boundary to
boundary; while vertical mesh lines can be terruinated according to the
speciﬁed ylength value. The program will automatically determine the
suitable terminating point (i.e. not violating the rules of having two
termination point in one segment of line).

The grid layout in Figure 8.1 is done by the following input entries:

GRD this grid will produce Figure BI

10 1.0 1.0

999 0.0 0.0

15 1.0 0.8 0.5

30 2.0 1.2 1.0

999 0.0 0.0 .

CON<arbitrary user input>

<contact number> <contact type> <xmin> <xmax> <ymin> <ymax>

146

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 8.1: An example layout of grid structure.

 

 

 

description

example

UNI

syntax

description

example

GAX

syn tax

description

147

The contact is speciﬁed by the contact number and its locations. So far,
the only contact type supported is 'ohm', the ohmic contact.

The following contact speciﬁcation put contacts 1 and 2 on top and
bottom surfaces of Figure B.l:

CON

1 ohm 0.0 2.0e-6 0.0 0.0

2 ohm 0.0 2.0e-6 1.0e-6 1.0e-6

UNI<arbitrary user input characters>

<impurity type> <concentration> <xmin> <xmax> <ymin> <ymax>

The uniform doping concentration are specify by this entry for its
impurity type (either 'nd' or ’na’), concentration magnitude (in m3), and
the region enclosed by xmin, xmax, ymin, ymax.

UNI

nd 1.9e22 0.0 1.0e-6 0.0 0.1e-6

GAX

<impurity type> <peak location> <peak concentration> <xchar> <ychar>
<ymin> <ymax>

GAX speciﬁes the Gaussian proﬁle along the x direction according to the

following relationship

 

-(§;x_0)2
ymin < y < yrnax N(X~)') = No6 x° (131)
I _(X—xo)2(y—ymin)2
y < ymin N(XJ) = Noe Xe y. (32)

_(x-x0)2(y—ymax)2

y > ymax N(x.y) = Noe x“ y‘ (B3)

 

example

GAY

syntax

description

example

FIY

syntax

description

148

where No is the peak concentration, x() is the location of the peak

concentration, and xc and yc are the characteristic lengths in the x and y

directions.
GAX
nd 0.0 2.0e24 0.1e-6 0.1e—6 0.1e-6 0.2e-6

GAY

<impurity type> <peak location> <peak concentration> <xchar> <ychar>
<xmin> <xmax>

GAY speciﬁes the Gaussian proﬁle along the y direction according to the

following relationship

 

 

-(ﬂﬁ

xmin < x < xmax N(XJ) = Noe yc (B4)
_(Y'YO)2(x‘xmin)2

x < xmin N(x,y) = No6 y. Kc (35)
_(y-y0 )2(X‘Xmax)2

x > xmax N(x,y) = Noe y° x° (136)

where No is the peak concentration, yo is the location of the peak

concentration, and xc and ye are the characteristic lengths in the x and y

directions.
GAY
nd 0.0 2.0e24 0.1e-6 0.1e-6 0.1e-6 0.2e-6

FIY<arbitrary user input characteristics>
<Impurity type> <xmin> <xmax> <ymin> <ymax> <lateral diffusion>

<C,> <Cz> <C3> <C4> <C5> <C6> <C7> <C8> <C.,> <C,,,>

FIY speciﬁes an arbitrary shape doping proﬁle along the y direction. The
doping proﬁle is speciﬁed by interconnecting the Ci values along equal

example

MET

syntax

description

149

spacing points in the y direction from ymin to ymax. A lateral diffusion
speciﬁes the lateral diffusion length as reference to the vertical diffusion
length (e.g. 0.6 for 60% lateral diffusion length of the vertical diffusion
length). Figure B.2 shows an example of the use of FIY. The vertical and
lateral diffusion proﬁle are also shown.

The following generates the extrinsic base doping of Figure 2.4:

FIY

na 0.0 5.575e-6 0.0 0.9e06 0.6

4.3e24 4.0e24 3.21e24 2.23e24 1.34e24 6.92e23 3.1e23 1.2e23 4.01e22
l.l6e22

MET<arbitrary user input characters>

<imax> <iinfo> <inﬁle> <imeshonly> <ibgn> <inter> <stress time>

<itun> <tunrange> <temperature> <C> <n,> <n2>

MET speciﬁes the solution parameters that can be controlled in the input

ﬁle. These parameters are described below:

<imax> : the maximum iteration count that can be performed by the
program. The value is set to limit the iteration when the solution is
diverging. When the iteration count of the solution exceeds the
<imax> number and no convergence is reached, the solution at that
point will be saved into a ﬁle 'diverg.dat', and the whole simulation
is aborted for the user to examine the problem of divergence.

<iinfo> : = 0 or 1. If iinfo is one, load the information ﬁle 'devinfo'.
'devinfo' stores the necessary information about the device such
that the simulation can simply load the ﬁle and start the solution.
'devinfo' includes the doping proﬁle, the data structure of the point

assignment scheme, the location of the rows and columns, the

150

 

 

 

 

 

Doping Doping

 

 

 

Line 1 Line 2

Figure B.2: The doping proﬁle speciﬁed by the use of FIY command.

151

results of the W matrix after symbolic LU decomposition etc. If iinfo = 0,
the device simulation program ﬁrst reads the necessary inforrnations (doping,
mesh, etc.) and then saves the information into 'devinfo' and starts the solution
iteration.
<inﬁle> : The device simulation program can iruport previous solutions as
the initial condition. If <inﬁle> is 'no', no importing of previous
solutions; otherwise, the device simulator reads the ﬁle name
speciﬁed in <inﬁle>.
<imeshonly> : If <imeshonly> = l, the device simulator only reads the
doping information and saves it to ﬁle 'meshndop'. This option is
used when the user only wishes to repeatedly check the doping
proﬁle and not solving any symbolic LU decomposition. If
<imeshonly> = 0, this option is disabled.
<ibgn> : use 1 to include bandgap narrowing effect; otherwise, use 0.
<inter> : This option is used for the easy extraction of top surface
properties. <inter> = 0, this option is disabled. <inter> = 2, the
simulator will import the ﬁle 'hotd' into the device simulation and
calculate the corresponding surface recombination velocity.
<stress time> : The value of stress time described in Equation (5.5).
<itun> : <itun> = l, the tunneling mechanism is turned on.
<tunrange> : Typically for two grid points having a long distance between
them, the tunneling current can be negligibly small. The simulator
checks the distance between any two points, if they are larger than
tunrange, the calculation for tunneling current is skipped.
<temperature> : The ambient temperature (lattice temperature) for the

simulation.

example

SOL

syntax

description

152

<C> : is used when calculating corresponding surface recombination
velocity calculation as describe in Equation (5.5).

<n,> : is the ﬁtting parameter adjusting the time dependence of surface

recombination velocity used in Equation (5.5).
<112> : is the ﬁtting parameter adjusting the voltage dependence of surface
recombination velocity used in Equation (5.5).
The entries below specify that the maximum iteration can be no more than
200, don't load from 'devinfo'. don't import an initial solution, mesh-only
option is turned off, include bandgap narrowing effect, disable interface

property extraction, tunneling current mechanism is turn on with the range

set at 0.1 11m, the lattice temperature is 296 K, C=3.8, n,=0.35, and
n2=0.8:
MET imax;info;inﬁle;imesh;bgn;int_;time;tun;tunr;temp;C;n 1 ;n2

200 0 'no' 0 1 0 0.0 l 0.1 296.0 3.8 0.35 0.8

SOL<arbitrary user input characters>
<solution number> <model> <Vl> <V2> (<V3>) <error> <output ﬁle>

<solution number> <model> <Vl> <V2> (<V3>) <error> <output ﬁle>

999 pois 0.0 0.0 1.0e-6 no (Or, 999 pois 0.0 0.0 0.0 1.0e-6 no)

The entries below SOL specify the solutions to be performed. <solution
number> speciﬁes the number of the solution, and is began from 1.
<rnodel> is either 'pois' for Poisson solution, 'drdi' for Drift-Diffusion
solution, or 'entr' for Hydrodynamic Transport Model solution. The details
for the algorithm of these solution methods will be described in Appendix
C. <Vl>, <V2>, and <V3> specify the voltage on the contacts. Typically

example

END
syntax

description

example

153

<Vl> is the reference potential and must be zero. If the input ﬁle specifies
3 contacts in the CON block, V3 must be speciﬁed. If the input ﬁle
speciﬁes only 2 contacts, no V3 can present. <error> speciﬁes the error
criterion of the solution iteration; when the updates of the solution results
in a value smaller than the criterion, a convergence is considered reached.
Finally, if the solution is to be saved in a ﬁle, specify the ﬁle name in
<output>. If <output> = 0, no solution is saved. When all solutions are
performed and 999 is reached, the simulation process is considered
successful and the program completed.

The following entries solve for a Poisson solution as the initial condition
and then solves for Vl = 0 and V2 = 0.1 volts by using Drift-Diffusion
model. The results are saved in a ﬁle called 'drOl':

SOL

l pois 0.0 0.0 1.0e-6 no

2 drdi 0.0 0.1 1.0e-6 drOl

999 pois 0.0 0.1 1.0e-6 no

END

END speciﬁes the end point that the simulator will be examining, i.e., any
input pass this point will simply be ignored by the simulator.

END '

one can store anything here since

anything here will never be seen by the device simulator.

In the following, two example input ﬁles are listed. The ﬁrst ﬁle was used in the

reverse bias simulation that extracted the solution at 4 volts of reverse bias at an ambient

154

temperature of -75 C. The second ﬁle was used in the forward degraded characteristic

calculation for a stress time of 1 hour.

Example input ﬁles:

COMMENT ::: The ﬁrst input ﬁle
COMMENT ::: This is a doping proﬁle for a TIN3 bjt
COMMENT ::: used for reverse bias study

GRD :::

10 0.4 1.0

999 0.0 0.0

15 5.5 1.0 1.4

20 5.625 1.0 1.4
120 5.875 1.0 1.4
135 8.5 1.0 1.4
999 0.0 0.0 0.0

COMMENT ::: Contact spec:

CON
1 ohm 0.0 2.8d-6 0.0 0.0

CON
2 ohm 6.0d-6 8.5d-6 0.0 0.0

COMMENT ::: Extrinsic Base doping:

FIY

na 0.00e-6 5.575e-6 0.0 0.9e-6 0.6

4.30e24 4.0e24 3.21e24 2.23e24 1.34e24 6.92e23 3.1e23 1.2e23 4.01e22 l.l6e22
COMMENT ::: Intrinsic Base doping:

GAY
na 0.2e-6 2.0e24 le-6 0.135e-6 0.0 8.5e-6

GAY
113 0498-6 4.0e23 le-6 0.076e-6 0.0 8.58-6

GAY
na 0.60e-6 2.0623 le-6 0.0758-6 0.0 8.56-6

155

GAY
na 0.,7e-6 8.0622 16-6 0.146-6 0.0 8.56-6

COMMENT ::: Emitter doping:

FIY
nd 606-6 856-6 0.0 0.456-6 0.6
3.31626 3.1626 2.52626 2.07626 1.77626 1.37626 8.44625 2.58625 2.61624 8.55622

MET :::Imax,iinfo,inﬁle,imesh,ibgn,inter,stt,itun,tunr,temp,c,n1,n2
200 0 'no' 0 1 O 0.0 1 0.1 198.0 3.8 0.35 0.8

SOL ::: No. : model : V1 : V2 : (V3) : erri : outﬁle
1 pois 0.0 0.0 1.06-6 no

2 drdi 0.0 0.2 1.06-6 no

3 drdi 0.0 0.4 1.06-6 no

4 drdi 0.0 0.6 1.06-6 no

5 drdi 0.0 0.8 1.06-6 no

6 drdi 0.0 1.0 1.06-6 no

7 drdi 0.0 1.2 1.06-6 no

8 drdi 0.0 1.4 1.06-6 no

9 drdi 0.0 1.6 1.06-6 no
10 drdi 0.0 1.8 1.06-6 no
11 drdi 0.0 2.0 1.06-6 no
12 drdi 0.0 2.2 1.06-6 no
13 drdi 0.0 2.4 1.06-6 no
14 drdi 0.0 2.6 1.06-6 no
15 drdi 0.0 2.8 1.06-6 no
16 drdi 0.0 3.0 1.06-6 no
17 drdi 0.0 3.2 1.06-6 no
18 drdi 0.0 3.4 1.06-6 no
19 drdi 0.0 3.5 1.06-6 no
20 drdi 0.0 3.8 1.06-6 no
21 drdi 0.0 4.0 1.06-6 dr_40
999 pois 0.0 0.0 1.06-3 no

END

COMMENT ::: The second input ﬁle.
COMMENT ::: This is a doping proﬁle for a TIN3 bjt
COMMENT ::: used in forward degraded char. simulation

GRD :::
20 1.4 1.0

156

999 0.0 0.0

16 2.625 1.0 1.4
116 2.875 1.0 1.4
1213.01.01.4
135 8.51.01.4
999 0.0 0.0 0.0

COMMENT ::: Contact spec:

CON
1 ohm 0.0d-6 2.8d-6 0.0 0.0

CON
2 ohm 6.0d-6 8.5d-6 0.0 0.0

CON
3 ohm 0.0 8.5d-6 1.4d-6 1.4d-6

COMMENT ::: Collector doping:

UNI
nd 1.9622 0.0 8.56-6 0.0 1.46-6

GAY
nd 1.46-6 2.3625 16-6 0.2066-6 0.0 8.56-6

COMMENT ::: Extrinsic Base doping:

FIY

na 0.006-6 5.5756-6 0.0 0.96-6 0.6

4.30624 4.0624 3.21624 2.23624 1.34624 6.92623 3.1623 1.2623 4.01622 1.16622
COMMENT ::: Intrinsic Base doping:

GAY
na 0.26-6 2.0624 16-6 0.1356-6 0.0 8.56-6

GAY
na 0.496-6 4.0623 16-6 0.0766-6 0.0 8.56-6

GAY
na 0.606-6 2.0623 16-6 0.0756-6 0.0 8.56-6

GAY
na 0.76-6 8.0622 16-6 0.146-6 0.0 8.56-6

157
COMMENT ::: Emitter doping:

FIY
nd 6.06-6 8.56-6 0.0 0.456—6 0.6
3.31626 3.1626 2.52626 2.07626 1.77626 1.37626 8.44625 2.58625 2.61624 8.55622

MET :::Imax,iinfo,inﬁle,imesh,ibgn,int6r,stt,itun,tunr,t6mp,c,n1,n2
200 0 'no' 0 l 0 1.0 0 0.1 300.0 3.8 0.35 0.8

SOL ::: No. : model : V1 : V2 : (V3) : erri : outﬁle
1 pois 0.0 0.0 0.0 1.06-6 no

2 drdi 0.0 0.0 0.0 1.06-6 no

3 drdi 0.0 0.1 0.1 1.06-6 no

4 drdi 0.0 0.2 0.2 1.06-6 no

5 drdi 0.0 0.3 0.3 1.06-6 no

6 drdi 0.0 0.4 0.4 1.06-6 no

7 drdi 0.0 0.5 0.5 1.06-6 no

8 drdi 0.0 0.6 0.6 1.06-6 no

9 drdi 0.0 0.7 0.7 1.06-6 no
10 drdi 0.0 0.8 0.8 1.06-6 no
999 pois 0.0 0.0 0.0 1.06-3 no

END

Appendix C

Device Simulation Program Structure Outline

The device simulation program consisted of about 60 subroutines in about 6,000
lines of FORTRAN language and is structured into the algorithm shown in Figure CI.
The program starts by reading the input ﬁle to decide important options such as whether
to read an initial solution, whether only to layout the mesh, whether to read the
preprocessed informations, etc.

If the input ﬁles speciﬁes 'do the preprocess step', the procedure does the
symbolic LU decomposition and saves the result in 'devinfo', etc. Otherwise, this step can
be skipped by simply loading from the ﬁle 'devinfo'.

The next step is to read from the input ﬁle the contact voltages. The program then
proceeds to solving the Poisson, electron continuity, hole continuity, electron energy
conservation, and hole energy conservation equations. The Poisson solution only
involves iteratively solving the Poisson equation, whereas the Drift-Diffusion solution
iteratively solves the Poisson, electron continuity, and hole continuity equations, and the
HTM solution solves the Poisson, electron continuity, hole continuity, electron energy
conservation, and hole energy conservation equations.

After each iteration, all the updates in the solution are examined. If all updates are
smaller than the error criterion speciﬁed, the solution is considered to be converged. The
program than proceeds to the output handling (saving output), and deciding whether to
go to the next solution. If any of the updates are larger than the error criterion, the
solution is iterated with the new solution as the initial condition.

The following lists the main subroutines for each of the function blocks:

Read Input File: readdop.f, readmesh.f, readcon.f, param.f

158

159

 

LRead Input File

 

 

 

1......1

 

 

 

Read Next
Output Handle ' Contact Voltage

Yes

' 333mm N LSDM P . l

7 t 4LPoissonModrel i

Solve Electron
Continuity

 

 

 

 

 

 

 

 

 

 

 

 

Solve Hole
Energy Conv.

 

 

 

HTM Model

Figure CI: The algorithm of the device simulation program.

160

Preprocess: readmet.f, loadhot.f, loadinfo.f, loadini.f, makeitypef,
symlu.f, scale.f, init.f, saveinfo.f, savemesh.f

Read Next Solution: readsol.f, bound.f, loadv.f, loadnp.f, loadt.f

Poisson solution: sparsep.f, funtp.f, solve.f, numlu.f

Electron continuity solution: sparsecn.f, funtcn.f, solve.f, numlu.f

Hole continuity solution: sparsecp.f, funtcp.f, solve.f, numlu.f

Electron energy comervation solution: sparsecn.f, funten.f, solve.f
numlu.f

Hole energy conservation solution: sparseep.f, funtep.f, solve.f, numlu.f

Convergence check: convchk.f

Output handle: saveout.f, printoutf, currcon.f

10.

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