CH BAN STATE USNIVER SITY I III III I IIIIIIIIIIIIIIIII 31293 00877 9203 IIIIII This is to certify that the dissertation entitled MACROMODELING OF IC VOLTAGE REGULATORS presented by KENNETH VINCENT NOREN has been accepted towards fulfillment of the requirements for Ph.D. Electrical degree in Engineering MS U is an A}__'Iirmum-c Action/Equal Opportunity Institution 0-12771 ___A__ ___—__ LIBRARY Michigan State University PLACE IN RETURN BOX to remove this checkout from your record. TO AVOID FINES return on or before date due. DATE DUE DATE DUE DATE DUE MSU Is An Affirmative Action/Equal Opportunity Institution omwmuflS-M By Kenneth Vincent Noren A DISSERTATION Submitted t0 Mi 1 . W State University in parhal' fulfillment of the requirements for the degree 0f DOCTOR 0F PHILosoPHY . Department of Electrical Engine . E 1992 :7: .. D ~' (7X-667X ABSTRACT MACROMODELIN G OF 10 VOLTAGE REGULATORS By Kenneth Vincent Noren When computer simulators are used in the design and analysis of electronic systems, it is necessary that the 10’s and discrete components being used are well modeled. The modeling of 10’s presents a special problem, and one solution to that problem is to develop a macromodel for the 10. A macromodel is an equivalent circuit, which is composed of simulator components, that can predict the linear and non-linear behavior of the 10. This macromodel can then be used in simulations of electronic systems which use the 10. In developing macromodels, it is necessary to choose device characteristics which will adequately describe the chip. Once the characteristics are chosen, and measured in lab, these characteristics become the device phenomenon to be modeled and Provide guidelines in model development. This dissertation will describe the development of macromodels for several voltage regulator 10’s for use in PSpice. .‘ ll momentum . ‘ ”Sandie National Laboratories for the opportunity to perform the .,; . ' I“, , ‘ “fl“! Won. The work was supported under Dept. of Energy contract 1.2 IwauldlihtothankDr.GregoryM.Wierzbaforhisguidanceinthe IwouldliketothankDr.JamesReshforsharinghistime and advice 2‘ ‘ fit-an Moment ofthe project. I would like to thank David lumen and M. James W b that outstanding performance in the laboratory which made the Wants possible and enabled completion of the project. TABLE OF CONTENTS LIST OF TABLES ........................................ vii LIST OF FIGURES ....................................... viii 1 Introduction and Background ................................. 1 1.1 Introduction ......................................... 1 1.1.1 Electronic System Design Involving IC’s ............... 2 1.2 Background ......................................... 3 1.2.1 Op-Amp Macromodels ............................ 4 1.2.2 Comparator Macromodels .......................... 6 1.2.3 Voltage Regulator Macromodels ..................... 6 1.2.4 Voltage Reference Macromodels .................... 10 1.3 Problem Statement ................................... 10 Terminology and Lab Apparatus ............................... 12 2.1 Introduction ........................................ 12 2.2 Temperature Considerations ............................ 12 2.3 Parameters ........................................ 15 2.3.1 Line Regulation, Ripple Rejection, and Line Transient Response ..................................... 15 2.3.2 Load Regulation, Output Impedance vs Frequency, and Load Transient Response ......................... 18 2.3.3 Quiescent Current .............................. 20 2.3.4 Reference Voltage .............................. 22 2.3.5 Dropout voltage, Dropout Characteristics ............. 22 2.3.6 Short Circuit Current Limiting, Foldback Current Limiting 23 2.3.7 Power Up and Down with Square Wave and Triangle Wave Inputs ................................... 24 2.4 Test Equipment ...................................... 25 SG7805/SG7812 Macromodel Development ...................... 26 3.1 Introduction ........................................ 26 3.2 Development ........................................ 27 3.2.1 The Reference Voltage Generator ................... 29 3.2.2 The Error Amplifier ............................. 31 3.2.3 Ripple Rejection Modeling ........................ 31 3.2.4 Output Impedance Modeling ...................... 33 3.2.5 Quiescent Current Modeling ....................... 34 3.2.6 Short Circuit Current Limiting and Foldback Current Limiting ...................................... 36 3.2.7 Power Up and Down Square Wave .................. 39 3.2.8 Dropout Characteristics ........................... 41 3.2.9 Other Modeled Characteristics ..................... 41 Design Procedure for a SG7 805 .......................... 42 Design Procedure Example .............................. 46 Modeling the SG7805 at -55 and 125 Degrees ............... 49 3.5.1 Strategy in Modeling the SG7805 Temperature Variations 49 3.5.2 Design Example to Include Temperature Dependence . . . . 52 3.5.3 Comparision of Macromodel Predictions with Lab Results . 57 3.6 Development of the SG7812 Voltage Regulator Macromodel ..... 69 3.6.1 Development of the Room Temperature Macromodel for the SG7812 .................................... 69 3.6.2 Development of the Model for -55°C and 125°C ......... 71 3.6.3 Comparison of Macromodel Predictions with Lab Results . 76 3.7 Test Circuits ........................................ 88 3.7.1 SG7805 Pspice Test Circuits ....................... 88 3.7.2 SG7812 Pspice Test Circuits ....................... 92 3.7.3 Measurement Test Circuits ........................ 97 SG7915 Macromodel Development ............................ 102 4.1 Introduction ....................................... 102 4.2 Development of the SG7915 Macromodel .................. 102 4.2.1 The Reference Voltage Generator .................. 103 4.2.2 The Error Amplifier ............................ 106 4.2.3 Ripple Rejection Modeling ........................ 107 4.2.4 Output Impedance Modeling ...................... 109 4.2.5 Quiescent Current Modeling ...................... 109 4.2.6 Short Circuit Current Limiting and Foldback Current Limiting ..................................... 113 4.2.7 Power Up and Down Square Wave ................. 116 4.2.8 Dropout Characteristics .......................... 118 4.2.9 Other Modeled Characteristics .................... 118 4.3 Design Procedure for a SG912 .......................... 119 4.4 Design Example for a SG7 915 .......................... 124 4.5 Modeling the SG7 805 at -55 and 125 Degrees .............. 127 4.5.1 Strategy in Modeling the SG7 915 Temperature Variations 127 4.5.2 Design Example to Include Temperature Dependence . . . 127 4.5.3 Comparision of Macromodel Predictions with Lab Results 133 4.6 Test Circuits ....................................... 145 4.7.1 Pspice Test Circuits ............................. 145 4.7.2 Measurement Test Circuits ....................... 150 CA3085 Macromodel Development ............................ 154 5.1 Introduction ....................................... 154 5.2 Development ....................................... 154 5.2.1 The Voltage Reference Amplifier Source ............. 157 5.2.2 The Frequency Compensated Error Amplifier ......... 160 V 5.2.3 Series Pass Amplifier ........................... 161 5.2.4 Ripple Rejection Modeling ........................ 161 5.2.5 Load Regulation ............................... 162 5.2.6 Quiescent Current Modeling ...................... 164 5.2.7 Short Circuit Current Limiting .................... 166 5.2.8 Dropout Characteristics .......................... 168 5.2.9 Power Up and Down, Square Wave and Triangle Wave . . 168 5.2.10 Ambient Temperature Sensing Circuiti'y ............. 170 5.2.11 Other Modeled Characteristics .................... 172 5.3 Design Procedure for a CA3085 ......................... 173 5.4 Design Procedure Example ............................. 176 5.5 Modeling the CA3085 at -55 and 125 Degrees .............. 178 5.5.1 Strategy in Modeling the CA3085 Temperature Variations 178 5.5.2 Design Example to Include Temperature Dependence . . . 179 5.5.3 Comparision of Macromodel Predictions with Lab Results 184 5.6 Test Circuits ....................................... 199 5.7.1 Pspice Test Circuits ............................. 199 5.7.2 Measurement Test Circuits ....................... 204 UA723 Macromodel Development ............................. 208 6.1 Introduction ....................................... 208 6.2 Development of the UA723 Macromodel ................... 208 6.2.1 The V“? Pin .................................. 211 6.2.2 The Error Amplifier ............................ 212 6.2.3 Ripple Rejection Modeling ........................ 213 6.2.4 Quiescent Current Modeling ...................... 214 6.2.5 Output Impedance Modeling ...................... 216 6.2.6 Short Circuit Current Limiting .................... 217 6.2.7 Power Up and Down with Square Wave ............. 218 6.2.8 Power Up and Down with Triangle Wave ............ 220 6.2.9 Dropout Characteristics .......................... 220 6.2.10 Line Transient Response ......................... 222 6.2.11 Ambient Temperature Sensing Circuitry ............. 222 6.2.12 Other Modeled Characteristics .................... 222 6.3 Design Procedure for a UA7 23 .......................... 224 6.4 Design Example for a UA723 ........................... 227 6.5 Modeling the UA723 at -55 and 125 Degrees ............... 229 6.5.1 Strategy in Modeling the UA7 23 Temperature Variations 229 6.5.2 Design Example to Include Temperature Dependence . . . 229 6.5.3 Comparision of Macromodel Predictions with Lab Results 234 6.6 Test Circuits ....................................... 245 6.6.1 Pspice Test Circuits ............................. 245 6.6.2 Measurement Test Circuits ....................... 249 SG137 Macromodel Development ............................. 253 7.1 Introduction ....................................... 253 7.2 Development of the SG137 Macromodel ................... 253 7.2.1 The Voltage Reference ........................... 254 7.2.2 The Error Amplifier ............................ 257 vi ‘1'" 7.2.3 Ripple Rejection Modeling ........................ 257 7.2.4 Output Impedance Modeling ...................... 259 7. 2. 5 Quiescent Current Modeling ...................... 259 7. 2. 6 Short Circuit Current Limiting and Foldback Current Limiting ..................................... 261 7.2.7 Power Up and Down, Square Wave ................. 263 7.2.8 Power Up and Down, Triangle Wave ................ 263 7.2.9 Dropout Characteristics .......................... 263 7.2.10 Other Modeled Characteristics .................... 266 7.3 Design Procedure for a SG137 .......................... 266 7.4 Design Example for a SG137 ........................... 271 7.5 Modeling the SG137 at -55 and 125 Degrees ............... 273 7.5.1 Strategy in Modeling the SG137 Temperature Variations 273 7.5.2 Design Example to Include Temperature Dependence . . . 273 7.5.3 Comparision of Macromodel Predictions with Lab Results 278 7.6 Test Circuits ....................................... 292 7.6.1 Pspice Test Circuits ............................. 292 7.6.2 Measurement Test Circuits ....................... 297 8 Design Issues ....................................... 301 9 Conclusions ....................................... 306 BIBLIOGRAPHY ....................................... 309 vii LIST OF TABLES Temperature dependent parameters and elements ................. 54 Temperauture coeficients .................................... 55 Macromodel comparisons with lab data, SG7805 ................... 68 Temperature dependent elements .............................. 73 Temperature coefficients ..................................... 73 Macromodel comparisons with lab data, SG7812 ................... 87 Temperature dependent parameters and elements ................ 130 Temperauture coeflicients ................................... 130 Macromodel comparisons with lab data ......................... 144 Temperature dependent components and parameters .............. 181 Temperauture coeflicients ................................... 181 Macromodel comparisons with lab data ......................... 198 Temperature dependent components and parameters .............. 231 Temperauture coefiicients ................................... 232 Macromodel comparisons with lab data ......................... 244 Temperature dependent components and parameters .............. 275 Temperauture coefiicients ................................... 276 Macromodel comparisons with lab data ......................... 291 .II; 1 a 7. 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LIST OF FIGURES Boyle macromodel for the bipolar op-amp ......................... 5 741 op-amp schematic ........................................ 6 LM78XX series macromodel by MicroSim ......................... 8 LM78XX series device level model .............................. 9 Test circuit No. 1 .......................................... 16 Test circuit No. 2 .......................................... 20 Test circuit No. 3 .......................................... 21 Functional block diagram for the SG78XX ....................... 27 Full macromodel for the SG78XX .............................. 28 Vow. vs Vm, measured ....................................... 30 Ripple rejection vs frequency, measured ......................... 31 AC equivalent circuit for the reference circuitry ................... 32 Output impedance vs frequency, measured ....................... 34 Quiescent current vs input voltage, measured ..................... 35 Maximum output current vs Vnm, measured ..................... 37 Power up and down, square wave, measured ..................... 40 Ripple rejection vs frequency, measured ......................... 57 Ripple rejection vs frequency, macromodel ...................... 57 Power up and down, square wave, measured ..................... 58 Power up and down, square wave, macromodel .................... 59 Power up and down, triangle wave, measured ..................... 60 Power up and down, triangle wave, macromodel ................... 61 Line transient response, measured ............................. 62 Line transient response, macromodel ........................... 63 Load transient response, measured ............................. 64 Load transient response, macromodel ........................... 65 Quiescent current vs input voltage, measured ..................... 66 Quiescent current vs input voltage, macromodel ................... 66 Maximum output current vs input voltage, measured ............... 67 Maximum output current vs input voltage, macromodel ............. 67 Ripple rejection vs frequency, measured ......................... 75 Ripple rejection vs frequency, macromodel ....................... 75 Output impedance vs frequency, measured ....................... 76 Output impedance vs frequency, macromodel ..................... 76 Power up and down, square wave, measured ..................... 77 Power up and down, square wave, macromodel .................... 78 Power up and down, triangle wave, measured ..................... 79 Power up and down, triangle wave, macromodel ................... 80 1X 5.10 5.11 Line transient response, measured ............................. 81 Line transient response, macromodel ........................... 82 Load transient response, measured ............................. 83 Load transient response, macromodel ........................... 84 Quiescent current vs input voltage, measured ..................... 85 Quiescent current vs input voltage, macromodel ................... 85 Maximum output current vs input voltage, measured ............... 86 Maximum output current vs input voltage, macromodel ............. 86 Basic PSpice test circuit for the SG7805 and SG7812 ............... 88 Test circuit No. 1 .......................................... 97 Test circuit No. 2 .......................................... 98 Test circuit No. 3 .......................................... 99 SG7915 functional block diagram ............................. 103 SG7915 macromodel ....................................... 104 IVomI vs IVmI, measured ................................... 105 Ripple rejection vs frequency, measured ........................ 107 Quiescent current vs Vm, measured ........................... 110 Maximum output current vs VD”, measured .................... 113 Power up and down, square wave, measured .................... 117 Ripple rejection vs frequency, measured ........................ 133 Ripple rejection vs frequency, macromodel ...................... 133 Power up and down, square wave, measured .................... 134 Power up and down, square wave, macromodel ................... 135 Power up and down, triangle wave, measured .................... 136 Power up and down, triangle wave, macromodel .................. 137 Line transient response, measured ............................ 138 Line transient response, macromodel .......................... 139 Load transient response, measured ............................ 140 Load transient response, macromodel .......................... 141 Quiescent current vs IVIN I, measured .......................... 142 Quiescent current vs IVIN |, macromodel ........................ 142 Maximum output current vs IVm I, measured .................... 143 Maximum output current vs IVIN I, macromodel .................. 143 Basic PSpice test circuit .................................... 145 Test circuit No. 1 ......................................... 150 Test circuit No. 2 ......................................... 151 Test circuit No. 3 ......................................... 152 Functional block diagram for the CA3085 ....................... 154 Macromodel for the CA3085 ................................. 155 Basic application circuit for the CA3085 ........................ 156 DC characteristics of the reference voltage, measured .............. 157 AC characteristics of the voltage reference, measured .............. 158 Ripple rejection vs frequency, measured ........................ 161 Quiescent current vs input voltage, measured .................... 164 Power up and down, square wave, measured .................... 169 Power up and down, triangle wave, measured .................... 171 Ripple rejection vs frequency, measured ........................ 184 Ripple rejection vs frequency, macromodel ...................... 184 x .. i I. r. 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Oil. 4.5... ‘Ilv nth Ail..- lhl- 9.1 Power up and down, square wave, T = -55, measured .............. 185 Power up and down, square wave, T = -55, macromodel ............ 186 Power up and down, square wave, T = 25, measured .............. 187 Power up and down, square wave, T = 25, macromodel ............. 188 Power up and down, square wave, T = 125, measured .............. 189 Power up and down, square wave, T = 125, macromodel ............ 190 Power up and down, triangle wave, measured .................... 191 Power up and down, triangle wave, macromodel .................. 192 Line transient response, measured ............................ 193 Line transient response, macromodel .......................... 194 Load transient response, measured ............................ 195 Load transient response, macromodel .......................... 196 Quiescent current vs input voltage, measured .................... 197 Quiescent current vs input voltage, macromodel .................. 197 Basic spice test circuit ..................................... 199 Test circuit No. 1 ......................................... 204 Test circuit No. 2 ......................................... 205 Test circuit No. 3 ......................................... 206 Functional block diagram for the UA7 23 ........................ 208 Macromodel for the UA7 23 .................................. 210 Application circuit for the UA7 23 ............................. 211 Vow. vs V1N characterisitics for the UA723 ...................... 212 Ripple rejection vs frequency, measured ........................ 213 Quiescent current vs input voltage, measured .................... 215 Power up and down, square wave, measured .................... 219 Power up and down, triangle wave, measured .................... 221 Line transient response, measured ............................ 223 Ripple rejection vs frequency, measured ........................ 234 Ripple rejection vs frequency, macromodel ...................... 234 Power up and down, square wave, measured .................... 235 Power up and down, square wave, macromodel ................... 236 Power up and down, triangle wave, measured .................... 237 Power up and down, triangle wave, macromodel .................. 238 Line transient response, measured ............................ 239 Line transient response, macromodel .......................... 240 Load transient response, measured ............................ 241 Load transient response, macromodel .......................... 242 Quiescent current vs input voltage, measured .................... 243 Quiescent current vs input voltage, macromodel .................. 243 Basic Pspice test circuit .................................... 245 Test circuit No. 1 ......................................... 249 Test circuit No. 2 ......................................... 250 Test circuit No. 3 ......................................... 251 Functional block diagram for the SG137 ........................ 254 Macromodel for the SG137 .................................. 255 Basic application circuit for the SG137 ......................... 256 Ripple rejection vs frequency, measured ........................ 257 Quiescent current vs IVm I, measured .......................... 260 n 7.29 Maximum output current vs VD“, measured .................... 261 Power up and down, square wave, measured .................... 264 Power up and down, triangle wave, measured .................... 265 Ripple rejection vs frequency, measured ........................ 27 8 Ripple rejection vs frequency, macromodel ...................... 278 Power up and down, square wave, T = -55, measured .............. 279 Power up and down, square wave, T = 25, measured .............. 280 Power up and down, square wave, T = 125, measured .............. 281 Power up and down, square wave, macromodel ................... 282 Power up and down, triangle wave, measured .................... 283 Power up and down, triangle wave, macromodel .................. 284 Line transient response, measured ............................ 285 Line transient response, macromodel .......................... 286 Load transient response, measured ............................ 287 Load transient response, macromodel .......................... 288 Quiescent current vs IVIN I, measured .......................... 289 Quiescent current vs |VIN |, macromodel ........................ 289 Maximum output current vs Wm I, measured .................... 290 Maximum output current vs le |, macromodel .................. 290 Basic PSpice test cicruit .................................... 292 Test circuit No. 1 ......................................... 297 Test circuit No. 2 ......................................... 298 Test circuit No. 3 ......................................... 299 xii CHAPTER 1 INTRODUCTION AND BACKGROUND 1.1 INTRODUCTION Computers play an important role in all branches of science. Analog electronic circuit design has seen its share of development due to the advancement of computer technology. In the past a designer would sit down and design a circuit based on past experience, intuition and knowledge. The circuit would then be breadboarded. Ifneed be - again based on past experience, intuition, knowledge and now measurements and analysis - the design would be altered. The process would repeat itself until an acceptable breadboarded circuit was Obtained. Computer-Aided Design (CAD) is nowadays a part of this procedure. CAD simulations play an important role in the design and analysis phase of electronic circuit design. Circuit simulators, such as SPICE, have grown out of this. There are misconceptions of the role of circuit simulators in electronic design. Human nature sometimes allows oneself to rely heavily on computer simulations as a substitution for intuition and breadboarding. This is not a correct use of the tool. This is precisely the argument opponents of circuit simulators in electronic design use to justify their non-use. Non-use is also an incorrect use of the tool. The nature of this tool is such that when used properly, it can enhance both intuition and . breadboarding. For these reasons, it is necessary that CAD in electronic circuits be further developed from it’s present immature state. One area which needs attention is the modeling of devices and 10’s for use in the circuit simulators. 1 2 17.1.1 Electronic System Design Involving 10’s It is rare today that analog electronic systems are built without at least one analog 10 in them. This presents a problem when the designer wants to do a computer simulation. This problem is how to model the IC in order to use it in the simulation package. A brute force method is to use a computer model for the 10 which is based on the individual components of the 10. This is called a device level model. The device level model can have at least two problems. First, an analog IC, may he composed of several, sometimes thousands of components. This gives rise to very large circuits and can translate into large computer time cost and memory problems, especially due to non-linear components. Secondly, the user seldom has the correct transistor and diode parameters necessary to model the individual components correctly. This translates into an accuracy problem. One proposed solution is to develop a macromodel for the IC. A macromodel by definition is a model for an IC which would predict ac, dc, and transient phenomenon, both linear and non-linear, of that IC. It is usually built out of the ideal components which are available to most circuit simulators. Normally a macromodel is much simpler and contains fewer components than the device level model. This solves the component size problem. Also because the model is normally simpler, the designer has better control over the macromodel characteristics than the design-level model. This means the designer can better fit the characteristics of the actual 10. This solves the accuracy problem. The designer can then use the macromodel for the ID in the computer simulation of the analog electronic system. 1.2 BACKGROUND The goal of a macromodel is then to obtain a circuit model of an IC which is of much less complexity than that 10 itself, using the components available to the circuit simulator. One standard for this is SPICE [1] because many other simulators have elements which are compatible with SPICE, in part because most of simulators are variants of SPICE. The simulator discussed hereafier is PSpice. PSpice has some elements and element definitions which are not compatible with the original SPICE. However all of the elements in SPICE can be used in PSpice. The use of PSpice is justified because it is probably the most widely used simulator in the academic arena. This is because an excellent, also very powerful, student version is available as freeware. Macromodels are typically built with two techniques. These are build up and simplification. In simplification, elements or subcircuits of the IC being used are modeled by simpler configurations of ideal elements which provide the same function of that subcircuit. Consider, for instance, that a differential pair can sometimes be modeled as a voltage-controlled voltage source in which the nodes of the differential input become the controlling nodes of the controlled voltage source. This procedure gives rise to macromodels which in terms of functionality, can look very similar to the original circuit. The build up technique, on the other hand, is used when circuit elements are used to build a subcircuit to provide the macromodel with specific Characteristics. This subcircuit may bear little resemblance to the elements or Nbcircuits actually contributing to the phenomenon. As stated before, one goal of the macromodel is to predict ac, dc, and transient, . _ as well as linear and non-linear phenomenon. In general, the principle of increased in“ ~.~- it“ In) L! 4 accuracy meaning increased complexity and numbers of components holds true. This fact can provide for different levels of macromodeling. Ifa user, for example is mainly interested in the small signal gain vs frequency response of an op-amp, so a macromodel developed for this use may not need to model higher order effects such as slew rate, voltage clamping, etc, and a simpler model than one modeling all of these efi‘ects can be used. In general, when designing macromodels, it is probably best to develop as high an order model as possible, and let the user make any simplifications. Credit is normally given for the first macromodel to Boyle, et al, in [2]. In [2] a macromodel was developed for integrated circuit op-amps which provides an excellent pin-for-pin representation. The driving force in it’s development was to have a model which provided circuit simulations which were much less time costly and used less memory. The full chip model for the 7 41 and it’s corresponding Boyle macromodel are shown in Fig. (1). The model predicted very good results, but as CAD evolved, weaknesses were exposed. 1.2.1 Op-amp Macromodels The macromodel developed by Boyle was actually more geared toward bipolar op-amps. From the Boyle model, macromodels were derived for MOSFET-bipolar and JFET-bipolar op-amps [3] and all MOS op-amps [4]. The model in [4] pays special attention to the simulation of settling time of the MOS op-amp. All of these can be considered deviations of the Boyle model. In more recent times, due to the maturing of CAD and computing in general, other macromodels for op-amps were developed by Precision Monolithics [5] and Linear Technology [7]. Both are alternative topologies to the Boyle model which attempt to improve the accuracy of characteristics to that beyond those of the Boyle model. Presently, MicroSim uses a modified Boyle model in their circuit simulator PSpice. In their library, they claim to have macromodels for many of the most popular op-amps. There are actually a few topologies. Bipolar input op-amps, for example, all share the same topologies, but may have different component values in those macromodels, in order to produce different device characteristics. 7 9 vs: ‘ ‘ R911: ;: R92 Jl ll 5: + VA ‘- G) a (:11 92:}! 3c} 1 ' b b 0" R ‘> $12 51:) V: :, E3 CE: :E RE ‘ ': GD 1:.-L IEE Figure 1.1 Boyle macromodel for the bipolar op-amp In an attempt to get people to design with their op-amps, many op-amp vendors also provide macromodels of their op-amps. Some of these are Burr-Brown, Comlinear, Harris Semiconductor, Linear Technology, Precision Monolithics, and Texas Instruments [8]. Texas Instruments publishes a data book, compatible with their other product data books, with listings of their op-amp models [9]. Some rather interesting macromodels for op-amps, more application specific, , '4 |! Bx or as on or: 014 m’ 02 2mm rm °‘ new 3 '5 :D 59K 'A'A or: = = c, us so i 1:: g I or: m on 5° am 0" on a 1’ * 5K its: 1: 3‘ Figure 1.2 741 op-amp schematic were developed in an effort to predict EMI effects in bipolar op-amps [10] [11]. The op-amp macromodeling is a well worked in area, although it may be debatable as to whether or not it is well developed. 1.2.2 Comparator Macromodels From the Boyle model, came a macromodel for an IC comparator [12]. MicroSim also provides macromodels for several commercial comparators, again each with the same topology, and based on that found in [2]. Comparator macromodeling is not well developed. 1.2.3 Voltage Regulator Macromodels MicroSim provides macromodels for several commercial voltage regulator IC’s. These are a LM78XX series fixed positive voltage regulator, the LM79XX series fixed negative voltage regulator, and the LM723 adjustable positive voltage regulator. The lexx series is a series of positive regulators which all share the same basic u. E . 9. ”he ! .‘i . C e,.";\ 7 topology, and perhaps even the same dies. The MicroSim macromodel for the LM78XX series is shown in Fig. (3) and the full chip model is shown in Fig. (4). By changing one resistor value in the model it is possible to have difi‘erent values for the output voltages. It is also a series which several companies manufacture. Some of these are National, Motorola, and Silicon General to name a few. The LM79XX series fixed negative regulators utilize this same idea MicroSim claims to model many different five volt regulators, made by different manufacturers. These are identical. By changing two parameters, MicroSim’s model can provide output voltages of 12 volts and 15 volts. This is exactly what is done to provide corresponding macromodels for all of their 12 and 15 volt fixed positive voltage regulators. The same topology is used to model the LM14O series and LM340 series, of 5, 12, and 15 volt regulators as well. The topology of the negative regulator macromodel is derived, in part, from that of the positive regulator. The same philosophy in modeling all of the -5, -12, and -15 volt regulators hold true for the negative regulator series as it did for the positive regulators. Several difi'erent companies also manufacture a 723 like chip. These are again Motorola, Fairchild, and Silicon General for example. Microsim has one 7 23 macromodel which is used to model all of these. MicroSim provides for variation in certain chip characteristics with ambient temperature. Specifically these are changes in quiescent current and regulated output voltage. Microsim provides no design formulas. Also, information of what phenomenon is modeled is provided. Mia-osim does not provide for variation in macromodels for regulators which QZDDmu o——Q no.0"?! T1>1>1 .SD> ax Figure 1.3 LM78XX series macromodel by MicroSim on In a II. b 1," i m h :' m ‘iil w ‘ m H v... ’ II D , a In 1 I“ j I. I as . . Figure 1.4 LM78XX series device level model ”If ‘5 10 may occur born manufacturer to manufacturer. Wierzba has a macromodel for an LMll7 adjustable positive voltage regulator [13]. Design formulas are given and information on what phenomenon is model is provided. Variation with ambient temperature is not included. The voltage regulator macromodels are not well developed. 1.2.4 Voltage Reference Macromodels There is one voltage reference macromodel based on a REFO2 topology. The macromodel was created by Analog Devices (formerly Precision Monolithics). The model has weaknesses based on laboratory measurements here. There are no design formulas given. The above statements show both interest in the macromodeling of voltage references and the need to further develop this area. 1.3 PROBLEM STATEMENT Because of the lack of work done in the area of voltage regulator macromodels, the motivation for voltage regulator macromodeling is clear. Macromodels need to be developed for several difi‘erent types of regulators. Design formulas need to be given so that users are able to fully utilize the macromodels. This dissertation will focus on the macromodeling of voltage regulator IC’s. Because of the heuristic nature of the problem, special techniques are required to present the work in document format. Consider the problem of building of a pc computer system, for example. An infinite number of solutions existed for this problem. One of these solutions solved the problem. As a result, we have an endless number of solutions to that problem and a wealth of knowledge arising from it. This 11 situation comes up time and time again in everyday life. This is the nature of the macromodel problem. The format of this dissertation to first explain some basic regulator terminology. This is done in Chapter 2. Chapters 37 explains the developed voltage regulator macromodels for the following voltage regulators: SG7 805, SG7812, SG7915, CA3085, UA723, and the SG137. This will provide adequate insight into the understanding of the macromodels. It is at this point, afier having read about how the models function, and questions have arisen, that the reader is now in a much better position to understand the development. Then, some design issues are discussed in Chapter 8. Finally, conclusions are presented in Chapter 9. up, ‘ . . ."--- V .-~ ‘- 5 on :1». we. fit . CHAPTER 2 TERMINOLOGY AND LAB APPARATUS 2.1 INTRODUCTION The voltage regulators which are being modeled are the CA3085, UA723, SG7805, SG7812, SG7915, and the SG137 voltages regulators. These regulators all fall under the category of series-pass voltage regulators. The SG7 805, SG7812, and the SG7915 are three-terminal fixed regulators, providing regulated voltages of 5, 12, and -15 volts respectively. The SG137 is a three-terminal, adjustable, negative regulator. The CA3085 is an 8-pin, programmable positive regulator. The UA723 is a 10-pin programmable, positive regulator. In the development of these models, certain chip characteristics and behavior are chosen as critical. These characteristics not only become the characteristics which are modeled, but also become ways of evaluating regulator performance. Before the models are developed, this short chapter will describe some the performance characteristics which the models are based on. This includes both terminology and laboratory techniques. If the reader has little background with voltage regulators, this chapter should be read before any of the individual chapters on any one of the models is read. Temperature considerations will be discussed first. 2.2 TEMPERATURE CONSIDERATIONS The temperature effects of the chip are of interest. Chip characteristics are subject to variations with temperature. Models will be provided for the following 12 2r .\. \91": i ‘ r I .9 l 13 temperatures: 455°C, 25°C, and 125°C. This means that all of the measurements performed will be at one of these temperatures. When referring to chip temperature, junction temperature of the device is being referred to. Junction temperature is a function of ambient temperature and power dissipation. A standard, textbook, formulais 1; = r, +0kxPD +OmeD, (2.1) where T1 is the junction temperature of the device in degrees celsius, T,I is the ambient temperature in degrees celsius, 0,, is the junction to case thermal resistance with units of °C/Watt, 0, is the case to ambient thermal resistance with units of °C/Watt, and PD is the average power dissipation of the chip in Watts. Note that the product 9,c x PD represents the difference in temperature between the case and the junction and that the product 9,,. x PD represents the difi'erence in temperature between the case and the ambient. 91c is normally given by the manufacturers in the data sheets. This figure depends primarily on the case style that the particular chip uses. 9,. can be determined by using a temperature probe to measure case and ambient temperatures and using the fact that AT“ = 9,, x PD, where AT, is the difference between the case and ambient temperatures. A heat sink is always used in these measurements, so 9e. is an indication of the thermal properties 0f the external case and the heat sink. The method described above is the standard textbook method of estimating the Man temperature. An alternative method was used based on these findings. filters] loads were hooked up to the regulator. For each load, the case and ambient 14 temperatures were measured and 9, was determined. A problem which occurred was that for difi'erent loads, 9,. was significantly difi‘erent. This is not in accordance with Mary. This lead to the following procedure. For each difi'erent load, a AT“ figure was calculated. This product was then substituted into Eqn. (2.1) to give 1; = r, + kaPD + AT“. (2.2) Evidently AT, holds fairly constant for different ambient temperatures for a given load. This was verified by measurement. The junction temperature for each load and ambient temperature is then calculated based on Eqn. (2.2). 91‘ is assumed to be correct. Because the models are developed based on junction temperatures, when desiring measurements at -55°C, 25°C, or 125°C, it may be necessary to set the ambient differently from these temperatures in order to compensate for changes in junction temperature due to power dissipation. The ambient temperature is usually lowered by an amount determined from Eqn. (2.2) to produce the desired junction temperatures of 55°C, 25°C, or 125°C. Several measurements are taken in a pulsed mode. This is when the input to the regulator is a pulsed input. When the regulator is pulsed, it has the efi'ect of turning the regulator off and on. If a duty cycle of say roughly 5% is used, the regulator is off much more than it is on and the average power dissipation is negligible. Then, the junction temperature g'ven by Eqn. (2.1) is roughly the ambient temperature. The ambient temperature of the chip is always set by putting the chip inside a temperature chamber with the specified ambient programmed into the . ' climber-'3 temperature controller. Non-pulsed measurements have a non-zero average "iv l p. , ‘5‘“. t l I 2 l i 15 power dissipation. This means that in order to produce the desired junction temperatures, this ambient must be changed in order to compensate for the change injunction temperature which arises from power dissipation. 2.3 PARAMETERS In this section, parameters which are used to describe the regulators behavior and the circuits used to measure these parameters are discussed. 2.3.1 Line Regulation, Ripple Rejection, and Line Transient Response An ideal voltage regulator provides a constant, stable, and temperature insensitive output voltage under all possible conditions. 10 regulators are very non- ideal. Line regulation, ripple rejection and line transient response reflect the non- ideal behavior of a varying output voltage caused by a varying input voltage. Line regulation is a measure of how the dc output voltage varies for a varying dc input voltage. It can be defined as A Vow LR = . AV," (2.3) The test circuit used to measure this is shown in Fig. (2.1). The box described as regulator circuit contains the regulator and any external components necessary for the regulator to regulate. This is done in order to view all regulators as a two-port, even the multi-terminal and adjustable regulators. Then, the measurements only deal with input and output terminal characteristics of the entire "regulating circuit" It is also a convenient way to generically look at all test circuits for all of the regulators without having to redefine test circuits. In the case of the three-terminal, adjustable Waters for example, the regulator circuit consists of the regulator and 2 external c” 1,. a O a. cg, 'a a". ., “-t Ilfl” 16 REGULATDR + [HRCUN‘ ‘ ‘0 4. VS 4. \GN RLUAD thT E 3 Figure 2.1 Test circuit No. 1 resistors needed to produce the regulated voltage. In the case of a three terminal, fixed regulator, the regulator circuit is simply the regulator circuit itself. In the case of the negative regulators, VDC becomes a negative voltage. Line regulation is a pulsed measurement. This means that in Fig. (2.1), VDC = 0 and V3 is a pulse generator. The change in magnitude of the output voltage pulse is compared to the change in the magnitude of the applied pulse and LR is computed. Ripple rejection is a measure of how much ac signal can pass through the regulator circuit, as a function of frequency. A formal, mathematical definition is _ Vout(s . RR(s) a 20 iogti—M‘MSM ). (2 4) Note that the definition is set up so that when the ratio of the output voltage H is! K]? . ~13 ‘T‘nr ."vL‘E K '3 (1;: 17 to the input voltage magnitude is small, the value for RR given by Eqn. (2.4) is large, indicating "good" ripple rejection. The measurement circuit for this is again Fig. (2.1) with Vs a sine-wave generator and VDc set to properly bias the regulator. V3 is the swept across the desired frequency range. The ac input voltage and the ac output voltage amplitudes, as well as the phase shift in the output relative to the input, can be then measured for each frequency. A Tektronix 11401 digitizing oscilloscope was used to measure the input and output waves. From the scope it is easy to measure both the amplitudes of the input and output signal and the time delays between them. These time delays then convert into phase shifts. This is not a pulsed measurement so the ambient of the chip must be adjusted. Note that the low frequency ripple rejection is a measure of line regulation. This is because the lower frequencies for ripple rejection can be interpreted as being dc, providing the first pole or zero is not near by. Low frequency ripple rejection is then dc ripple rejection. Dc ripple rejection reflects the changes in output voltage due to changing input voltage for dc, which is simply line regulation. Line transient response is a measure of how the output voltage changes due to a sudden change in the input voltage. This sudden change can be either positive or negative. The test circuit is Fig. (2.1) with VS a pulse generator and VDC set at a proper biasing level. The average power dissipation due to the pulsed voltage, for small duty cycles, is negligible. The average power dissipation due to the dc bias voltage must be taken into consideration and the ambient compensated accordingly. 0n the positive edge of the input pulse, efi‘ects on the output due to positive changes in input voltage are observed, and on the negative edge of the input voltage the effects on the output voltage due to negative changes in the input voltage are observed. 18 Ideally timing the positive and negative slopes of an applied pulse voltage, any capacitors are can be treated as short circuits and any inductors can be treated as open circuits, which is the exact behavior of these components at high frequencies. This means the ratio of the amplitudes of the change in output voltage to the change in input voltage during the positive and negative edges are a measure of high Muency voltage gain. This ratio is related to high frequency ripple rejection as seen from Eqn. (2.3). Thus, there is a relationship with the line transient response during the positive and negative edges of the input transient peak to ripple rejection. Theoretically, if the ripple rejection characteristics are known, line regulation and line transient response should match up with ripple rejection. When this was done with lab results, they are close, but not exact. It is up to the modeler to decide which of the parameters above should be used for the model. For example, in the model, low frequency ripple rejection and line regulation will be exact. In lab, they may not be. When modeling, it must be decided which one is most important, either the low frequency ripple rejection or the line regulation. Then, the chosen parameter will be used in determining the model and become both low fi'equency ripple rejection and line regulation. 2.3.2 Load Regulation, Output Impedance vs Frequency, and Load Transient Response Another ideal characteristic of a voltage regulator is that for changing loads, the output voltage should remain constant. This is to say that the regulator should have a zero value for it’s Thevenin output resistance. In practice, this does not happen. There are three parameters which reflect this type of non-ideal behavior and they are load regulation, output impedance vs frequency, and load transient response. 19 Load regulation can be defined as LDREGA — "0'”. (2.5) Mm This definition is just the definition of do output resistance. This is a pulsed measurement. The test circuit is Fig. (2.1) with Vs a pulse generator and VDC = 0. The resulting regulated voltages are then compared for each load, or more frequently, under a loaded and non-loaded condition. Output impedance vs frequency is a measure of how the output impedance of the regulator varies with frequency. Low fi'equency output impedance is just the load regulation. This is not a pulsed measurement. The test circuit is Fig. (2.1) with VS = 0 and VDc properly biased. The output impedance is then measured with an HP 4192A LF impedance analyzer set up in a four-wire probe configuration across the load. Load transient response is an indication of how the output voltage responds to either the sudden application of a load, or the sudden removal of a load. In computer Simulations, this can be handled with a current source in which the current is pulsed on and off. Practically, this cannot be done. The test circuit to look at these effects is Shown in Fig. (2.2). Here, a load is electronically Switched on and off at the output of the regulator. The electronic switching is done by the hjt transistor being pulsed. Note that V8 is a pulse generator with a duty cycle of roughly 5%. This means that the load is ungrounded, or the load is "switched ofi" 95% of the time, and therefore Dower dissipation of the chip is negligible. Because when sudden changes in output current occur the reactive elements ‘wll 20 REGULATOR - CIRCUIT Figure 2.2 Test circuit No. 2 behave as either open or shorts, the peak of the load transient response is a measure of the high frequency change in output voltage for a change in load current. This is just high frequency output impedance. Similar to ripple rejection, when the macromodel is used, the low frequency output impedance is equal to the load regulation and the high frequency output impedance is equal to the peak of the change in output voltage divided by the change in the output current. In lab, however, these results will be close, but not identical. Again, some trade-oil‘s as to which measurements will be used in the models must be made. 23.3 Quiescent Current Quiescent current is the amount of current which is required to properly bias -l" l 21 the regulator. A standard definition is IQ is In, — 10”,, (2.6) new - «o + + Vs CD VIN RLDAD VDUT ‘ IQ R0 _. i 53- Figure 2.3 Test circuit No. 3 where 1m is the current supplied to the regulator and circuit by the voltage source and low is the current supplied to the load, in the case of the three terminal, fixed, regulators. low is the current supplied the load plus any current required for any external resistors added, such as feedback resistors for the adjustable regulators. For the three terminal regulators, this is conveniently the current coming out of the third terminal. The test circuit is in Fig. (2.3). This is a pulsed measurement so V8 is a pulse generator. The measured voltage across RQ is used to determine the value of the quiescent current. For the adjustable regulators, the circuits for measuring mm . l. 22 quiescent current are slightly different and will be treated in their particular sections. Quiescent current is not constant. It typically varies with two parameters and these are input voltage and load current. The variations with input voltage are more severe than the variations with load current, so normally, modeling variations with load current is neglected. 2.3.4 Reference Voltage In the case of the CA3085 and the UA7 23, the user has access to the reference voltage in the regulator. Ideally, this reference voltage remains constant. In the case of the CA3085 and the UA7 23, it was found while measuring the reference voltage, that it varied with both input voltage and with frequency. It is believed that these variations with reference voltage have a significant influence on the line regulation and the ripple rejection. In the case of the three terminal references, access to the reference node is not available, but it is assumed, based on the findings for the CA3085 and the UA723, that the reference voltage varies with input voltage and frequency. These variations influence ripple rejection. The measurement circuits for these will be described in the appropriate sections for the CA3085 and the UA723, if they are made. 2.3.5 Dropout Voltage, Dropout Characteristics Voltage regulators require a minimum input voltage in order to produce the desired output voltage. This is mainly because the circuit needs to be properly biased in order for the regulator to be functioning as a linear device. The difi'erence between the input voltage and the output voltage, just at the point the output voltage begins to regulate, will be termed the dropout voltage. The dc transfer function between the input voltage and the output voltage will 7's. 5th Nu A W" 23 be termed either the dropout characteristics or VOUT vs Vm characteristics. The input voltage should be swept through some reasonable range, like zero to several volts above the point where the regulator regulates. The dropout characteristics, then, include the dropout voltage in their characteristics. The dropout voltage and the dropout characteristics vary with load. This is because the load current directly influences the region in which the output pass transistors must operate for proper regulator biasing. The test circuit for these is Fig. (2.1) with VDc = 0 and Vs a pulse generator, and it is a pulsed measurement. 2.3.6. Short Circuit Current Limiting, Foldback Current Limiting All of the regulators above offer short circuit current limiting, to protect against, for example, the possibility of accidently shorting the output. Short Circuit Current can also be defined as the maximum available output current. In the case of the three terminal regulators, the short circuit current limiting is done internally in the regulator, and cannot be changed. In the case of the CA3085 and the UA723, it is achieved by adding an external resistor. The value of the resistor can vary, giving rise to a user programmed value for short circuit current. Power dissipation of the regulators, in all cases, is a function of the voltage difi'erential across the chip, and the load current. The voltage difi'erential across the chip is the difl'erence between the input and output voltages of the regulator. As input voltage rises, power dissipation increases, and the potential for exceeding the chip’s maximum power dissipation limit and potential for destroying the chip increases. In order to ensure that the power dissipation does not exceed some maximum value, as the differential voltage increases, the maximum output current should decrease. This 24 is the case for the three terminal regulators, and this effect is known as foldback current limiting. In the case of the CA3085 and the UA723, there is no foldback limiting, although the user may choose to implement this through the use of external device connections. The test circuit is Fig. (2.1). These are pulsed measurements so VDc = 0 and Va is a pulse generator. Rm” is chosen to be a value low enough so that at the regulated voltage the resistor needs more current than the amount of current allowed in either the short-circuit current region or the foldback region. This of course cannot happen so the output voltage decreases to an amount equal to the maximum current multiplied by the load resistance. The voltage across RLOAD is measured and since the value of Rum, is known, the man'mum output current can be deduced. 2.3.7 Power Up and Down with Square Wave and Triangle Wave Inputs These characteristics are the response of the output waveform when the input of the regulator is powered up and down with either a square wave or a triangle wave. A characteristic found in data sheets which is an indication of how the chip responds to power up is the "turn on" time of the regulator. For the triangle wave, the results normally depend upon the slope of the wave. If the rate of change in voltage with time is not significant enough, then non-steady-state characteristics of the output may be lost. What results is just a dc transfer function. The dc function implemented with a triangle wave still provides enough information to include. Power up and down with square wave is done with Fig. (2.1). This is a pulsed measurement so VDc = O and VS is a pulse generator. For power up and down with triangle wave, V1m = 0 and V5 is a triangle wave. The triangle wave causes a non-zero average power dissipation, so the ambient temperature must be set. 25 This concludes the introduction to terminology and measurements. 2.4 TNTEQUIPMENT 1) 2) 3) 4) 5) 6) 8) 9) 10) 11) 12) The following is list of the equipment used: Tektronix 11401 Digitizing Oscilloscope, used to measure and observe waveforms. PM 5193 programmable synthesizer/function generator, used for sine wave generation. HP 214A pulse generator, used for square wave and pulse generation. Wavetek model 186 function generator, used for triangle wave generation. Fluke 8506A digital multimeter, used for measuring resistances and voltages. Fluke 8840A digital multimeter, used for measuring resistances and voltages. HP 4192A LF Impedance Analyzer, used for measuring output impedances and capacitances. Trygon model IMO-7 50 power supply, used to generate DC voltages between 0 and 20 volts. HP 6634A DC power supply, used to generate DC voltages between 0 and 20 volts. NJE model QRP-160-3 dc power supply, used to generate voltages greater that 50 volts. Thermatron $1.2 temperature chamber, used to control the ambient temperature of the chip. Thematron 2800 programmer/controller, used to control the temperature chamber. This is built right into the chamber. flu... . as i s . all; riv- . e 4W l. u N. PAIL h»! . um... ~u i -. N n. N firh. CHAPTER 3 SG7805 / SG7812 MACROMODEL DEVELOPMENT 3.1 INTRODUCTION The SG7805 and the SG7812 macromodels are done together. In the actual chips for these regulators, the SG7800 series shares the same topology, with the exception of one value for one of the resistors in the circuit. This resistor is such that changing its value results in changing the output voltage of the regulator. Hence, it is possible to have a basic topology provide for many different desired regulated output voltages. Of course, the more common output voltages of 5, 12, and 15 Volts, as well as less common values are manufactured. Because of this fact, it seems reasonable that the macromodel for the SG7805 and SG7812 are nearly identical. Thus, the macromdel for these are nearly identical. The SG7805 is developed first, at room temperature and then at -55°C and 125°C, then this model is adapted to the SG7 812. The macmmodel under development is referred to as the SG78XX model until adapted to one of the specific chips to be modeled. The functional block diagram for the SG78XX is shown in Fig. (3.1). Note that the feedback resistors are R2, and R2,. It is 132,,a that is changed in the chip and 26 VIN VD UT ". or - - ; t R83 ’: VREF 924 GRDUND Figure 3.1 thctional block diagram for the SG78XX macromodel to produce the difl‘erent regulated output voltages. 3.2 DEVELOPMENT The macromodel for the regulator is shown in Fig. (3.2). The voltage reference generator and bias current source shown in Fig. (3.1) are replaced by DZI, R23, R“, RR, Dav and L1. The error amplifier has been replaced by EA, Rom, RP, 09, EB, D“ D_, V,and E,. The resistors R2, and R,‘a are the feedback resistors. Finally the Darlington pair pass transistor has been replaced by one pass transistor and a small base resistance and these are Qp and RB, respectively. Additions not shown in the functional block diagram follow. DBL, Du, Rm, REC, Rm, QC“ and Dm are added to model the behavior of short circuit current limiting and foldback current limiting. GB and Rooms are added to model the quiescent current. Rc and Dc are added to model RED 28 V' b D €9> cu 1 1 so Figure 3.2 Full macromodel for the SG78XX .Olu 29 dropout voltage. R0 is added for output resistance and output impedance characteristics. Lastly, Bus is added to model the efl'ect of capacitive load discharge through the device. This gives a general overview of the macromodel, and now the details of the elements and formulas are given. 3.2.1 The Reference Voltage Generator The reference voltage generator consists of DZI, Rq, RR, Du, Ru, and L1 shown in Fig. (2). Note fi-om Fig. (3.1) that Ru V vow = [1 +%—)————l +_1_'[‘:+ Ru], (3.1) ADC where Am: is the dc gain of the error amplifier. This equation for the output voltage helps to show the effect that VREF has on the output if it varies with voltage and frequency. The reference voltage is taken across the resistor RR, the diode DH, and the inductor L,. Note how changes in the dc input voltage for a grounded regulator effect V“? by considering RQ and RR. This means that the reference voltage changes with input voltage producing a change in output voltage in accordance with Eqn. (3.1). This contributes especially to line regulation and ripple rejection. Likewise, the inductor L1 produces a changing reference voltage with changing input voltage frequency. This contributes to ripple rejection vs frequency. Finally, note that current flows through R]. In the regulator macromodel, this contributes to quiescent current. When VB, is changing and V“? is relatively constant, most of the change in input voltage is dropped across Rq, since in practice R9 > RR. In the modeling, this means that the current through RQ is changing and hence quiescent current is changing. In the macromodel, R0 is almost entirely responsible for changes in quiescent current due I!” " Li lL 30 VOUT vs VIN I. . SG7805 W . ”-. ml" .5 (In. [‘2‘ fag. \- l ' I , I ah" Y. be?" rm: .-' ‘l" 0‘.- l '- 20 25 m 15 VIN (volts) —-- Hood = 50 ohms temp s 23 degrees c Figure 3.3 Vow vs Vm, measured 1 t .. Vlflelingthe "on” voltage as V0N means or", .. Ya, In the actual chip measurements, it is determined that there is no activity and the output of the regulator for an input voltage from zero to anywhere between .75V and 1.5V. This is because overcoming one or more diode drops is necessary to begin to turn the chip "on". Note this in Fig. (3.3), which shows Vow. vs Vm for the SG7805 regulator. This efl'ect is modeled by the zener diode D“. V“, cannot begin to develop an voltage drop until the breakdown voltage of Dz, is overcome. This means the 5.» Wait shows no activity, since the circuit is dependent upon V“, for functioning. 31 3.2.2 The Error Amplifier The SG78XX series contains a frequency compensated error amplifier and this is modeled with a one pole amplifier. This is E A, EB, Rom, RP, and CP. The addition of E“ D” V, and D, provides positive and negative clamping for the error amplifier. Clamping is provided for since in the macromodel, ideal controlled sources are being used, and this means non-ideal voltages can occur in the model. The voltage across EA can get extremely high or low, in the kvolt or negative kvolt range. This can not happen in the real chip, and is taken care of here. The error amplifier contributes to output impedance vs frequency, ripple rejection vs frequency, and power up. 3.2.3 Ripple Rejection Modeling Ripple Rejection vs Frequency SG7805 -20lo voutlvm db 80 9! H ) 0.._L_L.I.IJ.U.LL__.I_LLLLLI.II Iumm 1 MW 1 10 100 1000 10000 100000 ‘000000 1000000 Frequency [Hz) -'- rload = 50 —+— (load = 500 + rload = 1000 T = 25 degrees C Figure 3.4 Ripple rejection vs frequency, measured Fig. (3.4) gives an examPle of ripple rejection vs frequency of the SG7 805 for difl'erent loads. In modeling the ripple rejection, the following approximations are made. First, it is be assumed that low frequency ripple rejection for all three loads 32 is be nearly equal. Secondly it is assumed that the first pole for ripple rejection vs frequency is almost equal for all three loads. GROUND Figure 3.5 AC equivalent circuit for the reference circuitry From the definition of ripple rejection, 3 zero in the transfer function, Eqn. (1), is a pole in the ripple rejection response. Note that because VREF is actually a function 0f VIN. Eqn. (3.1) becomes a transfer function relating VOUT to Vm- A zero of Veer is a pole of ripple rejection. It is necessary to find the zero in VREF. Fig. (3.5) gives the ac equivalent circuit for Vacs: neglecting Rm since Rm > rum. From this circuit, it is determined that v = R1 +rm +51.l v (33) NV 31. W Rs*'nn+Ra"nz1 "' r This shows that the first pole in the ripple rejection is, 33 P111 = RnZnn) (3.4) The formula for dc ripple rejection is also needed. This again comes from Eqn. (3.1). It is necessary to find the small signal, dc relationship for VREF with Vm- From, Fig. (3.5) this is R + r v = l m ”av (3.5) R3 + rm +RQ + run or R + r since in practice RQ is much larger than RR, rpm and r2,. This can be used with Eqn. (3.1) to solve for the formula for low frequency ripple rejection and it is £*5”illk'+'”) RR" = [Vin] = R24 R0 . (3.7) V“ Dc 1+;[14-fi) 40c R“ It can be seen from Fig. (3.4) that there is also a zero in the ripple 1‘ ejection response. This is modeled in the macromodel, and will not be determined by the ripple rejection response, but will be determined by the power up response, Since both are due to the capacitor 0?. 3.2.4 Output Impedance Modeling Output impedance vs frequency is shown in Fig. (3.6). Low fi'equency output impedance is determined primarily by R0. For changes in load, low frequency output imPEdance also changes due to the small signal parameters for QP changing. To select R0. the simple relationship 34 Output Impedance vs freq SG7805 Output Impedance (ohms) 1D 1 10 100 1000 10000 100000 10000001000000 Frequency (Hz) —'—rload = 50 —+- rload = 500 + rload =1000 T = 25 degrees C Figure 3.6 Output impedance vs frequency, measured Zorn-,1: - Ra (3.8) is used. The frequency characteristics of Zom«(s) are determined primarily by GP. As Stated with ripple rejection, this parameter is selected based on the power up 1' espouse. When this is done, this gives adequate results for the first zero in the Output impedance vs fiequency response. Variations in output impedance with load are modeled because of a correct choice in the topology, however these are not modeled with strict accuracy. 33-5 Quiescent Current Modeling In Fig- (3.2) the elements which contribute to quiescent current are GB, Rum, R0 and R74 Fig. (3.7) shows the measured quiescent current vs input voltage. The quiescent current modeling works in the following way. GB is a voltage dependent 35 IO vs VIN SG7805 I0 lamps] 0.005 0.004 ----------------------------------------------------------------------------------- 0.003 +- ----------------------------------------------------------------------------------- 0.002 ------------------------------------------------------------------------------------ 0.001 ---------------------------------------------------------------------------------- '0001 1 1 1 1 1 1 L 0 5 10 15 20 25 30 35 40 VIN (volts) T = 25 degrees C Figure 3.7 Quiescent current vs input voltage, measured current source which depends upon the voltage VREF. This simulates the realistic behavior of a current source gradually turning on until reaching it’s maximum value when the correct regulator biasing is achieved. Initially, IQ is zero, and no voltages appear in the macromodel as there is not enough voltage to overcome the breakdown Voltage of D2,. A8 Vm increases, VREF increases and thus GB increases. However, all of the current supplied by GB is drawn by Qp. This means that the quiescent current consists of only the current flowing through Roms and R2,. At the point where VOUT achieves regulation, QP enters into the active region. Since QP has a very large BF, during thil transistion it goes from drawing most of the current available fi'om GB to little of the current available fi'om GB. This causes the ’jump’ in quiescent current seen in the transfer function. The current from GB now contributes to quiescent current. Thismeans ~01 5w :0 M ’l‘ V :1 2 1 4. 1.1.71 36 AIQW = by." (3.9) Once regulation is achieved, there is little significant change in the quiescent current due to G3, Rooms» and R“. The changes in quiescent current with input voltage seen beyond this point are modeled by Ru. Large changes in input voltage efiect the reference voltage circuitry mainly as changes in the voltage drop across Rq, since VREF and the voltage across DZI are nearly constant. This means in this region 1— (3.10) Finally, just at the point where the regulated voltage occurs at the output of the regulator, the point right after the jump occurs in the quiescent current V V IQ = our + $+glvm (3.11) 3.2.6 Short Circuit Current Limiting and Foldback Current Limiting An example of measured short circuit current and foldback current limiting is shown in Fig. (3.8). The addition of short circuit current and foldback current are given by DCL, ch R001.» R“, Dm, and Rsc. The short circuit current works in the following way. Note that DBL prevents the controlled source EB from supplying any current to the base of QP. This means that GB supplies all of the current to Q9. This is an important point. As current flows out of the emitter of QP through R80 and to the load, a voltage is generated across the base emitter junction of QCL, due to the voltage drop across Rsc. If this voltage is large enough to turn ch. on, most of the current supplied by GE is drawn by the collector of QCL, since it’s needs are large compared to the current supplied by G3. The remaining current is suppied to the base of QP in .l ”MA ‘4' Vivi '13:) 7775; 37 ISO vs VDIFF SG7805 3 IO (amps) 0 5 10 (S 20 25 30 35 VDIFF(volts) T = 25 degrees C Figure 3.8 Maximum output current vs Vamp. measured order to produce the voltage across R50. If the base emitter voltage of ch, is not large enough to turn on QCL, it remains OE and draws no current. The maximum output current is then just the current required to turn QCL on. This is 1m [x — Rx' . (3.12) This is a very simplified explanation of how short circuit current works, however it serves to explain the fundamental operation. Under the short circuit mode, the base of Q9 still draws only a small amount of current. The collector of QC“ draws most of the current available from GB. This means that in Eqn. (3.10), me,‘CL can be estimated since the collector current of QCL can be estimated as approximately the total current supplied by G3, which is gBVREP. Using an approximation for the relationship between collector current and base emitter voltage and inserting into 38 Eqn. (3.10) gives gsym I VT h[ Isa J (3.13) Note the addition of DCL. This diode was added in order to prevent current fi'om coming in through the output pin and eventually flowing through the collector of an- This was witnessed in the computer simulations with the macromodel. Finally, foldback current limiting is provided with the addition of Dzre and Rm. An explanation follows. Foldback current is normally given as a function of difl'erential voltage. This is roughly the voltage drop across Rm, Dm, R301, and R50. When the differential voltage is less than the breakdown voltage of Dm, there is no drop across RF13 and very little drop across REL, due to little base current of ch and also R30, due to this having a small resistance. Once the differential voltage exceeds the breakdown voltage of Dm, the device enters into the foldback region. Now the difference between the chip’s differential voltage and the breakdown voltage of Dm, is largely dropped across R1.B and Ram.- The voltage drop across the base emitter junction of QCL is Vmm = 11mm“. (3.14) The turn on voltage of QCL is fixed, as well as the voltage drop across RBCL, for a given VD“. Since Rem. is no longer equal to zero in the foldback region, from Eqn. (3.14), it is seen that a smaller voltage drop across R50 is necessary to turn on ch- Hence a smaller output current will turn on Q1 and so a smaller maximum current is available to the output. As the difl‘erential voltage across the chip increases, the 39 voltage drop across RBCL increases, and maximum available output current decreases. This is how foldback current limiting is achieved. Since the foldback region begins at the point where the differential voltage across the chip, err: is equal to the breakdown voltage of Dzrsv arm-V” (3.15) where Vrs is the difl'erential voltage required to put the regulator into the foldback region. The values for RmL and RW can be selected by selecting a point in the foldback region which gives the maximum output current for a given difl‘erential voltage. Then, from Fig. (3.2) and Eqn. (3.14), it can be determined that RIC]. ______ 1 (3.16) Rn+Rn] + mRX' Vuka = (VM-Bl’m)( The first term in Eqn (3.16) is V“BCL and the second term is VRSC. 3.2.7 Power Up and Down, Square Wave Fig. (3.9) gives the measured power up square wave response. There are two main contributions to the power up square wave phenomenon. The first is the tum-on time. As seen in Fig. (3.9), there is a period of time it takes for the output voltage required to reach it’s steady state regulated output value. This time is mainly the time required to charge up the capacitor in the error amplifier, CP. This time is proportional to the time constant due to RP and CP. Presently, there is no formula for determining these values. They are adjusted empirically. Secondly, when the input makes the transistion from on to off and the load is capacitive, the load must discharge. This is normally the case for the SG7 805 where a capacitor is always required at the output for stability. The path for this discharge 40 3:22} 9v£9353§§°zfficsitt¥c°ii~ """laitfltxth’lbi'flibiie Tit - _ tun-l m a Lav - J“ r _ ‘ " "’ vr~v .r.- fig )— C .. ~_—...—._.~—__. _ " “V¢‘mliAmm'nvo-vvc - A; n..,. . .................... 1...,L ‘V 9" —— EN - w;— -~aeus T lBBue/dtv an“ Figure 3.9 Power up and down, square wave, measured 41 is through Dms and R0 and back into the power supply. This efi'ect was verified by measurements. Note in Fig. (3.9), the difference between the input and output voltage is roughly one diode drop. This is further justification for use of this Dms. Finally, if Dms is not used, the capacitor must discharge through the parallel combination of the load resistance, the feedback resistor R”, and quES. The simulations where DDIS is not present show that this discharge path is inadequate for the rapid discharge which is shown in Fig. (3.9). It is possible to model the voltage difl'erence between the input and output voltages by varying the parameter N in Dms. This again is done empirically. 3.2.8 Dropout Characteristics The dropout characteristics are controlled primarily by RC, DC and Qp. The dropout voltage is the voltage drop across these elements when QP is on the edge of saturation. Then VDO :- Imkc + Vac + Vane? (Inn), (3.17) where it should be noted that VS AT, Q9 is a function of the load current. Then N no can be chosen to realize a dropout voltage for a given load with I ma . lanai. NBC VTln [ 155:)..vmwum) (3.18) 3.2.9 Other Modeled Characteristics The characteristics presented are suficient to produce the macromodel of the SG7805. These characteristics give the guidelines in choosing components and parameters. Because of a correct choice of components and parameters, the macromodel can accurately predict other responses. These are: power up and down 42 With triangle wave, line transient response, load transient response, line regulation and load regulation. These responses are shown in a later section. 3.3 DESIGN PROCEDURE FOR A SG7805 Based on the equations and procedures shown in the last section, a design procedure will be developed in this section. Basic to the design procedure is a list of measurements required to base the design on. The following measurements should be taken in the basic regulator circuit: 1) 2) 3) 4) 5) 6) 7) 8) Measure Vou'r vs Vm with no load. Measure IQ vs VIN with no load. Measure Vom- for Vm = 10V, no load. Measure ripple rejection vs frequency, Rm“, = 509. Measure maximum output current vs voltage differential. Measure output impedance vs frequency. Measure dropout voltage with Rum, = 5012. Measure Rum). The component selection procedure is: 1) 2) 3) 4) Select EA and EB. This determines ADC. Select R2, = 18009 and RM = 6000. These selections are based on the actual chip component values. Select the amplifier clamping circuitry parameters, these are: Rom, V,, the gain of E” and the diode parameters for D, and D, Based on the vow vs VIN measurement, determine the input voltage required to begin to turn the circuit on, VON, then Vm (3.19) Select NBVom and R23 5) From the measured value of VOUT at VIN = 10V, and utilizing Eqn. (3.1), V 1 R23 RV = V = 0'” m _ , a m l R”) [1+ “(1.3%” (321» 1 + _ Ru Select NBVDm and R.m = lMEGQ. 6) Measure the slope of IQ vs Vm for the quiescent current measurement. Then from Eqn. (3.10), = fl, (3.21) A10 7) From the ripple rejection measurement, determine RR”. Then determine the small signal resistance of DZR. This is determined fi'om a trial macromodel run with PSpice. Then from Eqn. (3.7), r£+ ; [I + ED RR, _ ADC Ru _ (3.22) R: ‘ R0 r 023‘ 1 + g 1 3) From the ripple rejection measurement, determine P1“. Then from Eqn. (3.4), L _ RxT'zn (3.23) 1 - P1n 9) Select RP. 10) From the power up measurement, measure the turn-on delay and from 11) 12) 13) 14) 15) 16) 17) 18) 44 this measurement, determine CP empirically. Also from the power up measurement, and measuring the difference in the input and output voltage waveforms directly after power down, select and appropriate value for Nnms. From the IQ vs Vm measurement, determine the value of the jump in quiescent current just after regulation is achieved. Then from Eqn. (3.9), A10 3, = V“. (3.24) m From the IQ vs VIN measurement, determine the value of quiescent current at the point where regulation is achieved. Then from the value of VOUT at VIN = 10V, and fi-om Eqn. (3.11), VOUT Roam = ym ' (3.25) ’0 ‘ 7;; ’83Vm Select the parameters for the output transistor Qp. These are: BF, VAF, NF, and IS. Select RB. Select the parameters for the transistor QCL, these are: BFCL and ISCL. Select RECL. From the maximum output current vs voltage differential, select the value of ICL when the device is not in the foldback region. Then from Eqn. (3.13), 19) 20) 21) 22) 45 83V!” _ ISCL (3.26) SC swarm From the maximum output current vs voltage differential, select the value where the curve enters into the foldback region and call this voltage VFB. Then BVM. = 1V". (3.27) Select NBVDZFB. From the maximum output current vs voltage difi'erential, select a value for the maximum output current and it’s corresponding output voltage. Then from Eqn. (3.15), -BV R" = VD” DZ!" _1 Km], V Win 3, m ’quRsc Isa (3.28) From a trial run with the macromodel, determine the value for Vamp. Select RC. Select ISDC. Determine the value of the load current. From the measured dropout voltage, VDO, and Eqn. (3.18). = VDO’Ich'VuraP. I VT ln (fl) 1313c Nnc (3.29) From the output impedance vs fi'equency measurement, determine low frecluency output impedance for the no load condition. Then 46 R0 = 2001'". (3.30) 23) Select the parameters for the diodes DBCL and DCL, IS and N. These may be important for convergence reasons. This concludes the design procedure. All of the parameters for the macromodel have been selected. 3.4 DESIGN PROCEDURE EXAMPLE In this section, an example based on actual laboratory measurements will be presented, and a comparison of the predictions of the macromodel with lab results will be given. The design procedure is based on measurements in lab. The data, unless otherwise specified, is taken directly ofl‘ from the plots which are were shown previously in the document. 1) Set lEA = 300, EB = 2, so ADC = 600. 2) Set Rx, = 18009, R2‘ = 6000. 3) Set Rom = 259, V+ = -1V and E+ = 1. Let the diodes D+ and D, have the PSpice default parameters. This means that VMAX = (VIN - 0.3)V and VMIN = -0.7V if the voltage drops across the diodes are taken as 0.7V. 4) Based on the Vow vs Vm measurement, BVDZI = 1.5V. Select NBVDz1 = 0.01. This helps the voltage drop across Dzl be close to BvDZl' In fact, all of the diodes being used as zener diodes should have the parameter NBV set to 0.01 or 01. 5) Vow. = 5.027V, then anzs = 1.2651V. Set NBVDZR = 0.1. 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17) 18) 19) 20) 21) 22) 47 Based on the IQ vs Vm measurement, RQ = 1120900. RR” = 70db = .316228m and run = 4.220, then RR = 4.70. P1,m = 1785Hz, so L1 = .796mH. Set RP = 500. By iteration, CP = .5uF. By iteration, NDDIS = 0.7. The jump in the IQ vs Vm measurement is .6328mA, then gB = .5002m. The value of the quiescent current at the point where regulation is achieved is 4.2215mA. This gives Rooms = 33960. Set ISQP = 1e-12A, BFQP = 70k, and VAFQP = 150. Set R1, = 1000. Set BFCL = 1000. Set R301. = 16000. From the short circuit current measurement, ISC = 2.7688A, then Rsc = .2750. From the short circuit current measurement, the point at which foldback occurs is 15.26V, then BVDZFB = 15.26V. Set NBVDZFB = 0.01. From the short circuit current measurement, the point VDm. = 31.08V and IN = 1.06A was selected, then RFla = 621960. In lab, the dropout voltage for a 50 resistor was determined to be 1.59V, then NDC = 1.1617. Based on the low frequency, no load, output impedance vs frequency 48 measurement, R0 = 0.0250. Set N DCL = 2. This concludes the design procedure for the room temperature macromodel for the SG7805. The PSpice macromodel description is: .SUBCKT SG7805 1 2 3 * in out gnd * DZ1 4 1 DZ1 .MODEL DZ1 D (BV=1.5 NBV=0.01) RQ 4 17 112090 RR 17 18 4.7 DZR 16 18 DZR .MODEL DZR D (BV=1.2651 NBV=0.01) RZR 16 18 1MEG L1 16 3 .796M EP 22 3 17 15 300 R0 22 6 25 DC- 3 6 DCLAMP DC+ 6 19 DCLAMP .MODEL DCLAlVIP D V+ 19 23 DC -1 E+ 23 3 1 3 1 RP 6 7 50 CP 7 3 .5U GB 1 9 17 3 .5002M DBL 9 8 DBL .MODEL DBL D (IS: 1E-4 EG=0 XTI=0) EB 8 3 7 3 2 RC 1 14 .2 DC 14 13 DC .MODEL DC D(N=1.617) RB 9 11 100 13 11 5 QP .MODEL QP NPN (BF=70K VAF=150 IS=1E-12) DCL 9 10 DCL .MODEL DCL D (N=2 IS=1E-4) 10 20 12 QLIMIT .MODEL QLIMIT NPN (BF=100) 5 12 .275 RBCL 20 5 1600 49 RFBCL 1 21 62.196K DZFB 20 21 DZFB .MODEL 1)er D (BV= 15.26 NBV=.01) RQUIES 12 3 3396 R23 15 3 600 324 12 15 1300 ROUT 12 2 0.036 DDIS 2 1 DMOD .MODEL DMOD D (N=0.7) .ENDS SG7805 3.5 MODELING THE SG7805 AT -55 AND 125 DEGREES It is desired to produce models which work at -55 degrees and 125 degrees. These will be ambient models. It would be most desirable to have a model which predicted behavior throughout the entire range of temperatures, however this is not possible yet at this time. Instead, the extremes of -55°C and 125°C are used. These temperatures, along with room temperature, provide an adequate range of temperatures which the device can be swept through. Of course, the chip does not always work at ambient temperature. The model is set up so that the user must figure out the junction temperature of the chip, and add the .TEMP statement into the PSpice input file for the circuit which will be simulated. 3.5.1 Strategy in Modeling the SG7805 Temperature Variations The problem in modeling for difi'erent ambient temperatures is that certain parameters in PSpice have an automatic and preset dependance on temperature. One value is IS. Note also that VT exhibits a change with temperature since VT 11 E, (3.31) 4 Where q is the charge of the electron and k is Boltzman’s constant. Using a value of - ("I r 5 9“,. lat. 50 1.60218e-19 for q and a value of 1.38066e-23 for k gives values for VT of 0.0188V and 0.0343V at temperatures of -55°C and 125°C, respectively. Then parameters NBV, VAF, BF, and N for the diodes and transistors can not be made temperature dependent in PSpice. Finally, it is of importance to note that IS for the diodes and transistors exhibits the following temperature dependance .1. - E. m 18(1) = m¢(’- ll"”(_7_]‘~‘, (3.32) Fortunately BV for the diodes can show second order temperature dependance by specifying the parameters TBVl and TBV2. This gives BV a temperature dependance in accordance with the following equation, rm) = svmunnmnrymmsrf), (3.33) where BVMOM is the value of BV at the nominal temperature which is 27° by default in PSpice. Other temperature dependent elements are the resistors, capacitors, and diodes. These follow a temperature dependance much like the parameter BV, and these are Rm = Rm(1+TCI(AT)+1C2(AT)1), (3.34) em = cm,(1+1c1(Ar)+rc2(Ar)’). (3.35) and 141') = Lmu +1101 (Ar)+rc2(Ar)1). (3.36) for the resistors, capacitors and inductors. 1h.u . . {d 510 . u 5 Al I ~r|| I .51 h.l—\ - l ‘1. 1 1 . c . .u p. 1 In. . .lt K I We. 51 The following strategy is used in developing temperature dependent models. The room temperature model is developed first. The design procedure for an ambient temperature is almost identical to that of the room temperature model. The steps which need modifications are steps 4, 5, 6, 7, 8, 10, 13, 18, 19, 20, and 22. These will give rise to new values for BVDZI, BVDZR, Rq, RR, L1, 09, Remus, Rsc, BVDZFB, RFB, and R0. Selection of these values gives remarkable temperature predictions for the lab results of interest. Lab data is taken and the above parameters are selected. Most generally, there are three values, one for each temperature, for each of the parameters. Next, the temperature coefiicients of these parameters must be determined from these values. Consider BV(T) in Eqn. (3.33). Note fi'om Eqn. (3.33) that 51111 = (1+ 71m (”hum/11)?) (3.37) BVM ‘ This leads to the following system of equations with two unknowns, setting TN 0M = 25°C: (rm-55) "mu =:[410 640011310} (3 .33) BV(IZS) 100 10000 Inn ( BV,“, This can be solved to find the values of TBVl and TBV2. The passive component temperature coeficients can be solved in this same manner. Once these coeficients have been determined, they can be inserted into the room temperature macromodel which then becomes a model which is accurate between the temperatures of -55°C and 125°C. 52 3.5.2 Design Example to Include Temperature Dependance In this section the parameters for the model for -55°C and 125°C are developed. The temperature coeficients will be determined and then inserted into the room temperature model. This represents the fully developed, macromodel for the SG7805. Following the format of the first example for the -55 degree portion: 4) 5) 6) 7) 8) 10) 13) 18) 19) 20) 22) Based on the VOUT vs VIN measurement, BVDZI = 1.5V. VOUT = 4.875V, then BVDZR = 1.2269V. Based on the IQ vs VIN measurement, R1.1 = 773200. RR“ = 71.283db = .272793m and rDZR = 2.070, then RR = 3.23820. P11m = 1192Hz so L1 = .70875mH. By iteration, CP = .5uF. The value of the quiescent current at the point where regulation is achieved is 4.58mA. This gives Rooms = 25370. From the short circuit current measurement, ISC = 3.5A, then RSC = .24990. From the short circuit current measurement, the point at which foldback occurs is 17.87V, then BVDZFB = 17.87V. From the short circuit current measurement, the point err = 32.5V and 1m = 1A was selected, then Rm = 35855.930. Based on the low fi'equency, no load, output impedance vs frequency measurement, R0 = 0.0250. This concludes the design procedure for the -55 degree temperature macromodel for the 8G7 805. 53 Doing the same for the 125 degree model: 4) 5) 6) 7) 8) 10) 13) 18) 19) 20) 22) 23) Based on the VOUT vs Vm measurement, BVDZ, = 1V. Vow : 4.994V, then BVDZR = 1.2568V. Based on the IQ vs VIN measurement, RQ = 145596.60. RR“. = 69.06db = .3524m and rDZR = 6.850, then RR = 6.06260. P1“ = 1900Hz, so L1 = 1.0816mH. By iteration, CP = .5uF. The value of the quiescent current at the point where regulation is achieved is 3.406mA. This gives Rooms = 7315.270. From the short circuit current measurement, ISC = 1.762A, then RSC = .35260. From the short circuit current measurement, the point at which foldback occurs is 16.06V, then BVDZFB = 16.06V. From the short circuit current measurement, the point VDIFF = 31.79V and 1m = .53A was selected, then R“, = 56346.5480. Based on the low frequency, no load, output impedance vs frequency measurement, R0 = 0.040. Set EGDBL = OeV. Set X'I‘IDBL = 0. These are set to zero because it was determined by PSpice simulation that the dependance of ISDBL on temperature was causing problems in the 125 degree simulations. Specifically, ISDBL gets very high when the nominal value is set at 1e-4A. This allows EB to supply currents equal Ftfllhflnluuth ”50.100172 10L. 00411100....N10110K100... .Fpm \\ 54 to this saturation current, which were unacceptable. Setting these parameters to 0 renders ISDBL nearly temperature independent. A final summary of the temperature dependent parameters and elements follows. element or value at value at value at parameter 25 degrees -55 degrees 125 degrees svm 1.5 1.5 1 va 1.2651 1.2269 1.2568 12., 112090 77320 1455966 R, 4.7 3.233 6.0626 L; .7 96m .7087 53m 1.086m Rmm 3396 2537.12 7315.27 Rec .275 .25 .3526 va 15.26 17.37 16.06 Bra 62196 35355.03 56346.55 Ro 0.036 0.025 0.04 Table 3.1 Temperature dependent components and parameters F0 (we- 03.100.00.501. Fruits Wm.,.1tu- 0. a I. I, Ill 0. 55 Solving for the linear and quadratic coefficients gives Table (3.2). element or TCl or TBVl T02 or TBV2 parameter (linear coefi‘.) (quadratic coefi'.) BV,,Zl -0.001481 -1.85167e-5 BVDZR 1.805303e-4 -2.4614e-6 12Q 0.003433 -4.9343e-6 Rn .003449 -5.4953e-6 1., 0.00233 1.262816-5 qu 0.006336 4.655264e-5 Rsc 0.001885 9.3636e-6 BVM.B -9.547473e—4 1.478994e-5 R.PB 0.002523 -3.4635e-5 R0 0.002616 -1.50463e-5 Table 3.2 Temperature coefficients The final SG7 805 macromodel is: .SUBCKT SG7805 1 2 3 * in out gnd * DZ1 4 1 DZ1 .MODEL DZ1 D (BV=1.5 NBV=0.01) RQ 4 17 112090 TC=.003483,-4.9343E-6 17 13 4.7 TC=.OO3449,-5.495E-6 16 13 DR .MODEL DR D (BV=1.2651 NBV=0.01 TBV1=1.805303E-4 TBV2=-2.461378E-6) L1 16 3 IND1 .796M .MODEL IND1 IND (TC1=.00238 TC2=1.262851E-5) EP 22 3 17 15 300 R0 22 6 25 DC- 3 6 DCLAMP DC+ 6 19 DCLAMP .MODEL DCLAMP D 56 W 19 23 DC -1 3+ 23 3 1 3 1 RP 6 7 50 CP 7 3 .5U GB 1 9 17 3 50on DBL 9 3 DBL .MODEL DBL D (13:11:04 EG=0 XTI=O) EB 33732 RC 1 14 .2 DC 14 13 DC .MODEL DC D(N=1,617) RB 9 11 100 QP 13 11 5 QP MODEL QP NPN (BF=70K VAF=150 13:13-12) DCL 9 10 DCL .MODEL DCL D (N=2 IS=1E-4) QCL 10 20 12 QLIMIT .MODEL QLIMIT NPN (BF=100) R80 5 12 .275 TC=.001885,9.363636E-6 RBCL 20 5 1600 RFBCL 1 21 62.196K TC=.002523,-3.4635E-5 DZFB 20 21 DZFB .MODEL DZFB D (BV=15.26 TBV1=-9.5474743E-4 TBV2=1.478994E-5 NBV=.01) RQUIES 12 3 3396 TC=.006886,4.655264E-5 R23 15 3 600 R24 12 15 1800 ROUT 12 2 0.036 TC,=.002616,-1.50463E-5 DDIS 2 1 DMOD .MODEL DMOD D (N :07) .ENDS SG7805 :10 57 3.5.3 Comparison of Macromodel Predictions with Lab Results A comparison of macromodel predictions with lab results are presented for the SG7805 in this section. Rrpple Rejectron vs Frequency SG7805 -20Ioo(voutlvm) (db) BO 0 _L_L_LLLI.I.I1 1 1 1111111 1 11111111 1 1 1111111 1 1 1111111 1 1 1111111 1 1 11111 1 10 100 1000 10000 100000 10000001000000 Frequency (Hz) temp . -55 —1— temp - 25 + temp -125 RIO-d : 50 Figure 3.10 Ripple rejection vs frequency, measured RR.CIR ID temp - -55 degrees c ‘°‘ em: .' '23 d'eor'ee'e'é 'l' "' tuna - 125 degree. 1: 40-1 20- o 7 ' v ‘ 1.011 10011 1 .0101 101:11 1001111 1.01111 1011111 1611’ a o a-db( (2)1VI1)) Proq0lfl¢y Figure 3.11 Ripple rejection vs frequency, macromodel Fi 58 "010.19 E 3.1.. -. 31$ 5?:95'5HWF‘ ""‘lsa'tfltuie’lbi'fliaflv M ' . 6.03 m u 18‘! 1 ”at; ~— —-)--' ‘ 1‘ 1 i . 5 1 1 t l 7 1'1/ I 1 3 'dtui : ' l E 1 .1 t 3 1 ., ..__ t” * 3 1 ——.. use 1 I -..'..i ' ‘yonV' l : : ; .. 1 f 5 :: 0v —-— . '1 ' 1 ‘93“! lBBue/d to #‘h ._._\_ Figure 3.12 Power up and down, square wave, measured 59 PU.CIR 10v ; _ _ I - - sv- . . . . . . . , , _ l‘, (I 6v~ , |l 1v- ‘ II 2v- . . .' 0V , lu _ _ as D.m I l - I - ”(1] ”(8 0.41116 0.6ms 0.81116 1.01113 Time Figure 3.13 Power up and down, square wave, macromodel Figu 60 ii , 2‘3.‘ 9‘93‘159’919331‘rt9ffis (exp: fagggwfi’lMMTORQ H 1,. -13 w m (ease/div Figure 3.14 Power up and down, triangle wave, measured 61 PU.CIR 10V 8V~ 5V1 4V 2V1 0v 15005 ' ' ' uV(1) ”(2) 20005 250us 30005 350us Time Figure 3.15 Power up and down, triangle wave, macromodel 62 2} Oigiliii§°thstL°$C9PE- flxpr?6s.drq13.? trument l08.§070729 ssnmv t=—‘ we“ ‘r‘- 1,... . _. I‘IV ' 1' H4 W‘ [3V 1 ‘ T— tsenv l 1!” s31 1330\11 ’ t ' 1 gut. “ “““—‘”‘*““ , cm' 11”.“:1: . I ‘VAAAA k i v"‘ A v v. . ‘°"v Triad ..-~' f “d n _ 1 t 1 ......... ‘1‘-'i , ................ # ‘350017 ‘ . 11.5,. ‘9.8us ,. , lBBS/dlu --.ru Figure 3.16 Line transient response, measured 63 LTR.C|R 5.20V 5.15V- 5.12V- $.00V- 5.01% . L 5.00V- 1.95v . . . . a 05 2005 40us 6005 0005 100us nV(2) Trme Figure 3.17 Line transient response, macromodel Z P 3123} 9-19513—5'5319355LL"??? 5: . ""‘°' iaiefltfifie’lofl'fiaisiio M . Cred? w i l fl 8 Figure 3.18 Load transient response, measured P‘s 1 w." 501' 65 LDTR.C|R 5.00V 5.06V- - - - WIK 5.02V- 5.00V- 4.98V~ 4.96V . . . 1 06 10us 20us 30us 4005 5005 0V (2] Time Figure 3.19 Load transient response, macromodel 2 31,1 66 IO vs VIN SG7805 IQ (amps) 15 20 25 30 35 VIN (volts) -+— temp = 25 + temp =125 "‘— temp = -55 Figure 3.20 Quiescent current vs input voltage, measured IO.CIR 4.0mAq 0.0mA- temp-= -55 degrees c , 100193.25 soon“? 9 .................. temp — 125 degrees C 0V s'v 16v 15v 207 25v 30v 35v . ”(3011155) vm Figure 3.21 Quiescent current vs input voltage, macromodel 67 ISC vs VIN SG7805 4 ISO [amps] 3.5 -------------------- ..................................................................................... 2.5 - 1.5 - --------- : ----------------------------------------- OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO 0.5 ---- -0.5 15 20 25 30 35 VIN(voIts] —‘- temp = -55 -t- temp = 25 + temp :125 Figure 3.22 Maximum output current vs input voltage, measured CL.CIR 4.0A 3.01. ..... /. . . .temp. =. -55. degrees. 1. I temp - 2S dégreee C temp = 125 degrees C 25v 30v 35v 10v 15v Ev vm Figure 3.23 Maximum output current vs input voltage, macromodel FlllTIIIFIHLIlTI: [IILIbl Kl001Kl (IKK 68 Comparison of Macromodel parameters and Measured Parameters QUANTITY -55°C 25°C 125°C RR”, lab 71.3db 7 0.0db 69.1db model 71.4db 7 0.3b 69.0db P133 lab 1.192kHz 1.785kHz 1.900kHz model 1.176kHz 1.760kHz 1.941kHz IQ lab 4.58mA 4.22mA 3.41mA model 4.53mA 4.27mA 3.36mA AIQ/AVIN lab 12.93u 8.92u 6.87u model 13.29u 9.19u 7.08u max output current lab 3.50A 2.84A 1.7 6A model 3.53A 2.84A 1.84A dropout voltage lab 1.88V 1.59V 1.16V model 1.40V 1.46V 1.50V Rom. lab 0.025052 0.0369 0.049 model 0.027552 0.03929 0.04460 Table 3.3 Macromodel comparisons with lab data, SG7805 69 3.6 DEVELOPMENT OF THE SG7812 VOLTAGE REGULATOR MACROMODEL In the actual chip, the topology of the SG7812 voltage regulator is identical to the SG7805 voltage regulator, with the exception of one value of one of the feedback resistors, R23, being changed to produce an output voltage of 12V instead of 5V. It makes sense if the same feedback resistor R2, is varied in the macromodel to produce a 12V output, that this can now be used for the macromodel for the SG7812. This is the case, and in fact helps verify the correctness of the macromodeling methodologies which were used in developing the SG7805. It is only necessary to change the feedback resistor R23 and use the procedure developed in section 3.4.1 to create the macromodel for the SG7812. Section 3.5.2 is then be duplicated to include the effects of ambient temperature. Finally, lab results are be compared against the macromodel predictions. 3.6.1 Development of the Room Temperature Macromodel for the SG7812 As stated before, the procedure used in section 3.4.1 is used to develop the macromodel for the SG7812. The design procedure for the room temperature model follows. 1) set EA = 300, EB = 2, then ADC = 600. 2) Set RR = 51609 and Rm = soon. 3) Set Rom. = 100, V, = -1V and E, = 1. Let the diodes D, and D, have the PSpice default values for their parameters. This means that Vm = (va - 0.3)V and Vm = -0.7V if the voltage drops across the diodes are taken as 0.7V. 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17) 18) 19) 20) 70 Based on the VOUT vs VIN measurement, BVDZI == .7 5V. Select NBVDZI = 0.01 and Rm = 1MEGQ. VOUT = 11.894V, then BVDZR = 1.2588V. Set NBVDZR = 0.01. Based on the IQ vs VIN measurement, R, = 86343.849. RR”. = 62.8464db = .7206m and rDZR = 1.3452, then RR = 5.24470. P1,“. = 2933Hz so L1 = .3573mH Set RP = 5000. By iteration, CP = .1uF. By iteration, Nms = 0.7. The jump in the IQ vs VIN measurement is .6223mA, then gB = .4944m. The value of the quiescent current at the point where regulation is achieved is 3.8945mA. This gives Rooms = 10572.619. Set ISQP = 1e-12A, BFQP = 70k, and VAFQP = 150. Set R3 = 1009. Set BFCL = 100. Set RBCL = 2000. From the short circuit current measurement, ISC = 1.32A, then Rsc = .5789. From the short circuit current measurement, the point at which foldback occurs is 14.7 9V, then BVDZFB = 14.7 9V. From the short circuit current measurement, the point VDIFF = 33.89V Tue 21) 22) 23) 71 and Inux = .2826A was selected, then R“, = 6170.430. Set RC = 0.20. In lab, the dropout voltage for a 500 resistor was determined to be 1.59V, then NDC = 1.6339. Based on the low fi‘equency, no load, output impedance vs frequency measurement, R0 = 0.020. set ISDBL '3 ISDCL = 184A. SBt NDBL = 2. 3.6.2 Development of the Model for -55°C and 125°C. The following gives the model for -55°C: 4) 5) 6) 7) 8) 10) 13) 18) 19) 20) Based on the VOUT vs Vm measurement, anm = 1.3V. Vow. = 11.7 926V, then BVDZR = 1.2481V. Based on the IQ vs VIN measurement, RQ = 1104970. RR”. = 65.715db = .5179m and 1'an = 1.150, then RR = 4.90650. P1“ = 2 kHz so L1 = .4820mH. By iteration, CP = .08uF. The value of the quiescent current at the point where regulation is achieved is 4.27 6mA. This gives Rooms = 7469.50. From the short circuit current measurement, ISC = 1.553A, then RSC = .56340. From the short circuit current measurement, the point at which foldback occurs is 15.4V, then NBVnm = 15.4V. From the short circuit current measurement, the point VD!” = 33,06V and IMAX = .5634A was selected, then RPB = 5719.350. 22) 72 Based on the low fi‘equency, no load, output impedance vs frequency measurement, R0 = 0.0160. The following gives the model for 125°C: 4) 5) 6) 7) 8) 10) 13) 18) 19) 20) 22) 23) Based on the Von... vs Vm measurement, BVDZI = 1V. Vow. = 11.838V, then BVDZR = 1.2529V. Based on the IQ vs VIN measurement, RQ = 134495.640. RR”, = 60.0650db = .9925m and rDZR = 2.60, then RR = 11.52740. P1“ = 3.5kHz so L1 = .6424mH. By iteration, CP = .08uF. The value of the quiescent current at the point where regulation is achieved is 3.0112mA. This gives Rooms = 38992.150. From the short circuit current measurement, ISC = .8529A, then RSC = .7 2560. From the short circuit current measurement, the point at which foldback occurs is 15.15V, then NBVDZFB = 15.15V. From the short circuit current measurement, the point VDIFF = 34.98V and 1m = 0A was selected, then R1,B = 6208.170. Based on the low frequency, no load, output impedance vs frequency measurement, R0 = 0.010. set EGDBL = 08V and XTIDBL = O. A final summary of the temperature dependent parameters and elements follows. elem .111 1.. 1. .1. _-0.11100.._01_-0-_111r0_ 0.000: K- - .0; 1 L 1; L L L . .L L L L L \L 73 element or value at value at value at parameter 25 degrees -55 degrees 125 degrees BVDZI .75 1.3 1 BVDZR 1.2588 1.2481 1.2529 IiiQ 86343.84 7469.5 134495.64 R1, 5.2447 4.9065 11.5274 L, .3573m .482m .6424m CP .lu .08u .08u qus 10572.61 7469.5 38992.15 RSC .5780 .5634 .7256 anzrs 14.79 15.4 15.15 R“, 6170.43 5179.35 6208.17 R0 0.02 0.016 0.01 Table 3.4 Temperature components and parameters element or TCl or TBVl TC2 or TBV2 parameter (linear coefl‘.) (Quadratic coefi'.) BVDZI -0.001481 -1.85167e-5 anzs 1.805303e-4 -2.4614e-6 Rq 0.003483 -4.9343e-6 Ru .003449 -5.4953e-6 L1 0.00238 1.26281e-5 01» 0002 1e-4 Rams 0.006886 4.655264e-5 Rsc 0.001885 9.36360-6 anzss -9.547473e-4 1.478994e-5 Rm 0.001143 -1.081421e-5 R0 0.002616 -1.50463e-5 Table 3.5 Temperature coeficients 74 The full temperature dependent macromodel for the SG7812 is: .SUBCKT SG7812 1 2 3 * in out gnd 021 4 1 D21 .MODEL DZ1 D (BV=.75 NBV=0.01 TBV1=-0.003611 TBV2=6.9444E-5) RQ 4 17 86343.84 TC=5.3597E-4,5.0408E-5 RR 17 18 5.2447 TC=0.005772,6.2073E-5 DZR 16 18 DZR .MODEL DZR D (BV=1.2588 NBV=0.01 TBV1=3.820E-5 TBV2=-8.5068E-7) RZR 16 18 1MEG L1 16 3 IND1 .3573M .MODEL IND1 IND (TC1=0.001123 TCZ=6.8566E-5) EA 22 3 17 15 300 ROUT 22 6 10 D— 3 6 DCLAMP D+ 6 19 DCLAMP .MODEL DCLAMP D V+ 19 23 DC -1 E+ 23 3 1 3 1 RP 6 7 500 GP 7 3 CAPl .1U .MODEL CAPl CAP (TCl=-0.002 TC2=1E-4) GB 1 9 17 3 .4944M DBL 9 3 DBL .MODEL DBL D(IS=1E-4 EG=0 XTI=O) EB 33732 RC 1 14 .2 DC 14 13 DC .MODEL DC D(N= 1.6339) RB 9 11 100 QP 13 11 5 QP .MODEL QP NPN (BF=7OK VAF: 150 IS: 1E-12) DCL 9 10 DCL .MODEL DCL D (N=2 IS=1E-4) QCL 10 20 12 QCL .MODEL QCL NPN (BF=100) RSC 5 12 .5730 TC=0.00131,1.2433E-5 RBCL 20 5 200 RFB 1 21 6.17043K TC=0.001143,-1.081421e—5 DZFB 20 21 DZFB .MODEL DZFB D (BV=14.79 NBV=.01 TBV1=-1.78236E-4 TBV2=4.2164E-6) RQUIES 12 3 10572.61 TC=0.013985,1.28953E-4 R24 15 3 600 R23 12 15 5160 R0 12 2 0.02 110-4333331314. 1667E-5 DDIS 2 1 DMOD .MODEL DMOD D (N=0.7) .ENDS SG7812 18. l I‘IRH 75 3.6.3 Comparison of Macromodel Predictions with Lab Results A comparison of macromodel predictions with lab results are presented in this section. Ripple Rejection vs Frequency SG7812 O l 1 1111111 LJJLIIUI LJJJIIIJI LJJAIJJLI LLJLIIIII J l LILIML L l lLlll 1 10 100 1000 10000 100000 10000001000000 “—tomp s -55 "4— temp - 25 + temp -125 Hand 3 80 ohm- Figure 3.24 Ripple rejection vs frequency, measured RR.CIR 00 '10qu - -55 'dooroos c ' ,1 1+1 50-1 - . .. ; T temp - 25 degrees c . temp - 125 degrees c 404 20- o . . 1 1 . 1.0 10011 1.010: 101m 19mm 1.0% mum is 16 I: o a-dbaltzl’vt“), Iroqucncy Figure 3.25 Ripple rejection vs frequency, macromodel 'lc 76 Output Impedance vs Fre uenc SG7812 q y 0'1m:555:55555§5555555555555555555555555555553' ' 0.01l ' 11111111 ‘ lM—LI 1111111 1 11111 1 10 100 1000 10000 100000 10000001000000 Frequency (Hz) —°- temp = ~55 —°—tomp = 25 +temp =125 11000 = 00 OM"! Figure 3.26 Output impedance vs frequency, measured 20111.6”? 10 1.0- temp = 25 degrees C 100'.‘ o a e . n . . . . . e temp - -55 degrees c temp = 125 degrees C Y 101100“ 1611 101111 1 61:11 with 100101 1 our: 10Mh . . .V(2)II(IAC) Frequency Figure 3.27 Output impedance vs frequency, macromodel Fig 77 11121 0191112106.?aSELL933933. :: 1312111103-21131x13-3> 20V l .‘ .. W A WW1. t 1' l 1 1 s i l i l i 1 l l .- 1 l l 1 . 1 i 1 2V _ -,& ...-fu“, l «110! 12,211+- ._ 1 W A >__ “9’,“ .. l t : l —--.v"‘ .Lv—W.“V-_‘fi._ _ _' 4‘: ; 30°Md \~% T leans/div 7 Sagas Figure 3.28 Power up and down, square wave, measured 78 PU.C|R 20V + H _ II II II 10V- 1| ii ii ~11le : 1 \2'. H l 08 0.3.13 ' ' av“) ”(2) 0.41115 0.61116 0.8105 1.0106 Time Figure 3.29 Power up and down, square wave, macromodel 79 1122: °19131219619351LL9359358 1::e1a.212*101-31131:¢3-3> ;! -136ns :14. " BBBus/d 1 0 1.964019 Figure 3.30 Power up and down, triangle wave, measured 80 PU_TR| .0”? 20V 10V- 3 a -0V05 0.5m 1.0ms ' 151m 2.0ms nV(2) .vm Tm Figure 3.31 Power up and down, triangle wave, macromodel 81 0:22: °19011200°.9321LL335365. 11:21312121102-31131z0313» m - 4asmy . .. ”1&7. MM A ‘_ 7 .. _.._ zqv l E "'1 l 1—~_.. -._... 7c...” ' ’le' ’ ..... {El 1 .1 I 15‘1“" L. ' ‘5 l _. .. l $ (“puck 1.....4 Q“... “’Qpr IA-IJV ' "‘ Li M .1 A - I WA“ .4 1'. l ' V... ”-2,::; 1‘ L T .— M"? L f#‘A‘f- taid ‘ g i i 1' 1 . l 1 -- v _ '1 . “34SmV __jl9.8us lBflS/div 901:22 Figure 3.32 Line transient response, measured 82 LTR.C|R 12.04V 12.00V1 11.96V- 11.92V' 11.88V- 11.84v. 11.8w“ 20.05 4005 60,115 80115 100119 OV(2) Tlme Figure 3.33 Line transient response, macromodel 83 1:22: 019151513610251LL9?38?55 ::B:31§02‘?03'36181X63-3’ 119k - W fl - 198ml?“ ‘j ................. f“ ”v ; , 1 i 3 -—F—“- ............ l R“ - 19.11111“ _°' SBnV 191 l l 11.11” .................................. ....................... -3leV ~398us lBan/diu . .168232 Figure 3.34 Load transient response, measured 84 LDTR.C|R 12.00V 11.95V1 11.92V1 - - - [ 11.88V- 11. V . , . . “09 0.21115 0.4105 0.51116 0.01119 1.01119 oV(2) T1me Figure 3.35 Load transient response, macromodel 85 ®u1escent Current vs VIN SG7812 Quiescent Current [amps] 0.005 0,004 — -------------------------------- 1 .4 :— “---—3 ------------ 0.003 ................................. 7%: ....fl ............ 0.002 ---------------------------------------------------------------------------- 0.001 ------------------------------------------------------------------------------- 0 -0.001 4 L 0 5 10 15 20 25 30 35 Input Voltage (volts) -*- temp = -55 -+- temp = 25 + temp =125 Figure 3.36 Quiescent current vs input voltage, measured IG.CIR 5.0.0.1. t.” I '55 dOOfOOB C ' I \ -I If g: ‘ mt; --. . .\. . . ......... temp - 25 degrees C ..- ..... \ temp: - 125 degrees C 4.01011 1 4 . . . 0v 10v 15v 20v 25v 30v 35v s'v a o AlfRW1E5) VIN Figure 3.37 Quiescent current vs input voltage, macromodel 86 Maxrmum Output Current vs VIN SG7812 2 Output Current lamps) ~0.5 0 S 10 15 20 25 30 35 40 Input Voltage [voltsl -°- temp = -55 -+— temp = 25 41— temp =125 Figure 3.38 Maximum output current vs input voltage, measured CL.CIR temp . -55:degrees i: J . e i eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee _‘ v 1,01. ..... /-9P. -. 2.5 #1911". 9 .......... 0.5Ad e a e O ooooooooooooooooooooooooooooooooooooo I DA- ‘0.5A r ; .r 1. fi— # V IN 5V 10V 15V 20V 25V 30V 35V 40V 9 o A I(RLOAD) VIN Figure 3.39 Maximum output current vs input voltage, macromodel _r1.,0l_1101,_L10HIK-.0>1..\1 01K lb WKI K231 1K1.1KI-\\ 87 Comparison of Macromodel Parameters and Measured Parameters QUANTITY -55°C 25°C 125°C RR“, lab 65.7db 62.9db 60.1db model 65.5db 62.9b 60.0db P1,m lab 2.000kHz 2.933kHz 3.500kHz model 2.113kHz 2.996kHz 3.788kHz IQ lab 4.28mA 3.89mA 3.01mA model 4.43mA 3.99mA 3.05mA AIQ/AVIN lab 9.05u 11.58u 7 .43u model 9.12u 11.81u 7.78u max output current lab 1.55A 1.32A 0.853A model 1.55A 1.33A 0.877A dropout voltage lab 1.86V 1.59V 1.36V model 1.56V 1.58V 1.66V Rou'r lab 0.0160 0.020 0.010 model 0.02630 0.03140 0.02480 Table 3.6 Macromodel comparisons with lab data, SG7812 88 3.7 TEST CIRCUITS SG 78XX ,9 IN nur GRUUND VIN .9. .1.— E10119 FQCLDAD R>LDAD O + VDUT .15— Figure 3.40 Basic Pspice test circuit for the SG7805 and SG7812 A. SG7805 Pspice Test Circuits RR.CIR * *ripple rejection for the SG7 805 * VDC 3 0 DC 10 VAC 1 3 AC 1 RLOAD 2 0 51.081 CLOAD 2 10 5.478u RCLOAD 10 0 1.8934 XREG 1 2 0 SG7 805 DP .LIB SG7805.LIB .AC DEC 20 10 1MEG .TEMP -55 25 125 .PROBE .END 89 ZOUT. CIR * *output impedance for the SG7 805 * VDC 1 0 DC 10 RLOAD 2 0 51.081 CLOAD 2 10 5.478u RCLOAD 10 0 1.8934 XREG 1 2 0 SG7805 IAC 0 2 AC 1 .OP .LIB SG7805.LIB AC DEC 20 10 1MEG .PROBE .TEMP -55 25 125 .OPTION S N OPAGE .END PU. CIR * ‘power up and down, square wave, response for the SG7 805 * VPULSE 100 0 PULSE (O 10 100u 0 0 500u) ROUT 100 1 .1 XREG 1 2 0 SG7805 RLOAD 2 0 51.081 CLOAD 2 10 5.478u RCLOAD 10 0 1.8934 .OP .OPTION ITL5=0 ITL1=300 ITL2=300 .LIB SG7805.LIB .TRAN 2.5u 1000a O 2.5u .TEMP ~55 25 125 .PROBE .END 90 PU_TRI.CIR * ‘power up and down, triangle wave, response for the sg7805 * VPULSE 100 0 PULSE (0 10 20u 80u 80u 0.001u 161u) ROUT 100 1 .1 XREG 1 2 0 SG7805 RLOAD 2 0 51.081 CLOAD 2 10 5.478u RCLOAD 10 0 1.8934 .OP .OPI‘ION ITL5=0 ITL1=300 ITL2=300 .LIB SG7805.LIB .TRAN .5u 600u O .5u .TEMP -55 25 125 .PROBE .END LTR.CIR * *line transient response for the SG7805 * VIN 1 3 DC 10 VPULSE 3 0 PULSE (0 4 10u 0 0 50u) XREG 1 2 0 SG7805 RLOAD 2 0 51.081 CLOAD 2 10 5.478u IECEJLOAD 10 0 1.8934 .OPTION ITL5=0 .LIB SG7805.LIB TEMP .55 25 125 . .250 100u 0.2511 .PROBE .END 91 LDTRCIR * *load transient response for the SG7805 * VIN 1 0 DC 10 XREG 1 2 0 SG7805 VPULSE 20 0 PULSE (4.97 0 10u 0 0 25u 40u) RLOAD 2 20 51.081 CLOAD 2 10 5.478u RCLOAD 10 0 1.8934 .OP .LIB SG7805.LIB .OPTIONS ITL5=0 .TRAN .1u 50u 0 .1u .TEMP = -55 25 125 .PROBE .END _ IQ.CIR * *quiescent current for the SG7 805 * VIN 1 0 DC 10 RLOAD 2 0 IOOMEG CLOAD 2 10 5.478u RCLOAD 10 0 1.8934 RQUIES 3 0 99.65 XREG 1 2 3 SG7 805 .LIB SG7805.LIB .OPTIONS ITL1=200 ITL2=200 .DC VIN O 30 0.25 .TEMP -55 25 125 .PROBE .END (‘3 .- ‘~‘ “ r) EEmQC’gflfleag 8.5 92 CL.CIR 13 *current limiting for the SG7805 * VIN 1 0 DC 20 RLOAD 2 0 1.02 CLOAD 2 10 5.478u RCLOAD 10 0 1.8934 XREG 1 2 0 SG7805 .LIB SG7805.LIB .DC VIN 0 32.5 0.1 .TEMP -55 25 125 .PROBE .END B. SG7812 Pspice Test Circuits RRCIR * *ripple rejection for the SG7812 * VDC 3 0 DC 20 VAC 1 3 AC 1 RLOAD 2 0 67.449 CLOAD 2 10 .784U RCLOAD 10 0 2.138 léREG 1 2 0 SG7 812 . P .LIB SG7812.LIB .TEMP -55 25 125 .AC DEC 20 10 1MEG .PROBE .END 93 ZOUT.CIR * *output impedance for the SG7 812 * VDC 1 0 DC 20 RLOAD 2 0 67.449 CLOAD 2 10 .784U RCLOAD 10 0 2.138 XREG 1 2 0 SG7 812 IAC 0 2 AC 1 .OP .LIB SG7812.LIB .TEMP -55 25 125 .AC DEC 20 10 1MEG .PROBE .END PU.CIR * *power up and down, square wave, response for the SG7812 * VPULSE 100 0 PULSE (0 20 200U 0 0 500U) ROUT 100 1 0.1 RLOAD 2 0 67 .449 CLOAD 2 10 .784U RCLOAD 10 0 2.138 EEG 1 2 0 SG7812 .OPTION ITL5=0 ITL1=500 ITL2=500 .LIB SG7812.LIB TRAN 2.5U 1000U 0 2.5U .TEMP 25 .PROBE .END 94 PU_TRI. CIR * *power up response, triangle wave, for the SG7 812 * VPULSE 100 0 PULSE (0 20 10U 600U 600U .0001U 1201U) ROUT 100 1 .1 XREG 1 2 0 SG7812 CLOAD 2 10 .784U RCLOAD 10 0 2.138 RLOAD 2 0 67.449 .OP .OPTION ITL5=0 ITL1=300 ITL2=300 .LIB SG7812.LIB .TEMP=25 .TRAN 1U 2000U 0 1U .PROBE .END LTR.CIR * *line transient response for the SG7812 * VIN 1 3 DC 20 VPULSE 3 O PULSE (0 4 20U 0 0 50U) XREG 1 2 O SG7812 CLOAD 2 10 .784U RCLOAD 10 0 2.138 RLOAD 2 0 67.449 .OPTION ITL5=0 .LIB SG7812.LIB .TRAN 1U 100U 0 1U .TEMP 25 .PROBE .END 95 LDTRCIR * *load transient response for the SG7 812 * VIN 1 0 DC 20 XREG 1 2 0 SG7812 RLOAD 2 20 67.449 CLOAD 2 10 .784u RCLOAD 10 0 2.138 VPULSE 20 0 PULSE (11.8 0 200U 0 0 500U) .OP .LIB SG7812.LIB .OPTIONS ITL5=0 .PARAM VALUE = 1 .TRAN 1U IOOOU 0 1U .TENIP = 25 .PROBE .END IQ.CIR * *quiescent current for the SG7 812 * VIN 1 0 DC 20 RLOAD 2 O 100MEG CLOAD 2 10 .784U RCLOAD 10 0 2.138 RQUIES 3 0 99.650 XREG 1 2 3 SG7 812 .LIB SG7812.LIB OPTIONS ITL1=200 ITI.2=200 .DC VIN 0 30 0.25 .TEMP = -55 25 125 .PROBE .END 96 CLCIR :1: *current limiting for the SG7812 * VIN 1 0 DC 20 RLOAD 2 0 3.9295 CLOAD 2 10 .784U RCLOAD 10 0 2.138 XREG 1 2 O SG7 812 .LIB SG7812.LIB .TEMP -55 25 125 .DC VIN 0 35 0.1 .PROBE .END 97 3.7.3 Measurement Test Circuits SG78XX + 11 our ‘ C ‘ fl 5111111 1 m VIN V0111 RCLOAD L010) 1 J: _ 1 Figure 3.41 Test circuit No. 1 The conditions of test circuit N o. 1 are stated. CLOAD measured 5.47 8uF at 100kHz for the SG7805 CLOAD measured .784uF at 100kHz for the SG7812 LOAD represents the series resistance of CwAD and measured 1.89340 at 100kHz for the SG7805. RCLOAD measured 2.1380 at 100kHz for the SG7812. R1. R2. R3, R4, and R5 have nominal values of 1k0. + is a positive 50 volt dc power supply. - is a negative 10 volt dc power supply. 0A is a Burr-Brown OPA541 Op-Amp- The SG7805 and SG7812 reside inside a temperature chamber. Wires are connected at the terminals of the SG7 805 and SG7812 to allow them to be connected outside the chamber to the test circuit. 98 SG78XX + 01 OUT CLIJAD 2 1mm V111 V0111 RQUIES R0010 RLOAD 3.— : _ _ 21 Figure 3.42 Test circuit No. 2 The conditions of test circuit No. 2 are stated. CLOAD measured 5.47 8uF at 100kHz for the SG7805 CLOAD measured .7 84uF at 100kHz for the SG7812 Rcmm represents the series resistance of CLOAD and measured 1.89340 at 100kHz for the SG7 805. Row“) measured 2.1380 at 100kHz for the SG7812. R]. R2, R3, R4, and R5 have nominal values of 1k0. V1» is a positive 50V dc power supply. V- is a negative 10V dc power supply. 0A is a Burr-Brown OPA541 Op-Amp. The SG7805 and SG7812 reside inside a temperature chamber. Wires are connected at the terminals of the SG7805 and SG7 812 to allow them to be connected outside the chamber to the test circuit. RQUIES has a nominal value of 1000 99 SG78XX + 4" M -5 1. J10» GROUND 110111 VIN :3— Figure 3.43 Test circuit No. 3 The conditions of test circuit N o. 3 are stated. CLOAD measured 5.47 8uF at 100kHz for the SG7 805 CLOAD measured .784uF at 100kHz for the SG7812 Rcwm represents the series resistance of 0001.9 and measured 1.89340 at 100kHz for the SG7 805. Roman measured 2.1380 at 100kHz for the SG7812. R1, R2, R3, R4, and R5 have nominal values of 1k0. V+ is a positive 50V dc power supply. V- is a negative 10V dc power supply. 0A is a Burr-Brown OPA541 Op-Amp. The SG7805 and SG7 812 reside inside a temperature chamber. Wires are connected at the terminals of the SG7 805 and SG7812 to allow them to be connected outside the chamber to the test circuit. Ql is 3 2N4401 npn transistor. RB, has a nominal value of 10150. R132 has a nominal value of 11:0. 1) 2) 3) 4) 5) 6) 7) 100 Ripple rejection was done using test circuit 1. VA was connected to an ac function generator. VB was connected to a positive dc power supply. These were set to produce a 10V dc voltage at VIN for the SG7805 and a 20V dc voltage at VIN for the SG7812, with a sine wave superimposed for both. R1001) measured 51.0810 for the SG7805 and 67.4490 for the SG7 812. Voltages and phases were measured with a Tektronix 11401 scope. The Vm vs Vow for both chips, VOUT at VIN = 10V for the SG7805, and the VOUT at V101 = 20V for the SG7812 measurements were done using test circuit 1. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. VB was grounded. These were set to produce the necessary voltage at Vm- RLOAD, when used, measured 51.0810 for the SG7 805 and 67 .4490 for the SG7 812. Voltages were measured with a Tektronix 11401 scope. The power up and down square wave measurements were done using test circuit 1. VA was connected to an pulse generator. VB was grounded. Rm“, measured 51.0810 for the SG7 812 and 67.4490 for the SG7 812. Voltages were measured with a Tektronix 11401 scope. The power up and down triangle measurements was done using test circuit 1. VA was connected to an ac function generator, generating a triangle wave. VB was connected to a positive dc power supply. These were set to produce a triangle wave at VIN which has a maximum value of 10V for the SG7805 and 20V for the SG7 812, and a minimum value of 0V for both. RLOAD measured 51.0810 for the SG7812 and 67.4490 for the SG7812. Voltages were measured with a Tektronix 11401 scope. The quiescent current measurements were done using test circuit 2. VA was connected to an pulse generator and pulsed at 100112, with a duty cycle of 5%. VB was grounded. These were set to produce the necessary voltage at Vm- qu3 measured 99.650 for both the SG7805 and SG7812. Voltages were measured with a Tektronix 11401 scope. The voltage was measured across unms and divided by RQUIES to give the quiescent current. The load transient response measurements was done with test circuit 3. VA was grounded. VB was connected to a positive dc power supply to produce a dc voltage of 10V at VIN for the SG7805 and 20V at Vm for the SG7812. VP was pulsed to allow Q1 to function as a switch, connecting RLOAD on and off to ground to simulate the switching on and 00‘ of a load RLOAD measured 51.0810 for the SG7812 and 67 .4490 for the SG7812. The maximum output current vs VIN measurements were done using test circuit 1. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. VB was grounded. These were set to produce the necessary voltage at Vm- RLOAD measured 3.92950 for both the SG7805 and SG7812. Voltages were measured with a Tektronix 11401 scope. The voltage was measured at RLOAD was then converted to a current. 8) 101 The line transient response measurements was done with test circuit 1. VA was connected to a pulse generator. VB was connected to a positive dc power supply. These were set to produce a 10V dc voltage at VIN for the SG7805 and a 20V dc voltage at Vm for the SG7812, with a pulse superimposed. RLOAD measured 51.0810 for the SG7812 and 67 .4490 for the SG7812. Voltages were measured with a Tektronix 11401 scope. 4.1 5331] 0110 15an 121 CHAPTER 4 SG7915 MACROMODEL DEVELOPMENT 4.] INTRODUCTION This chapter describes the development of the SG7915 voltage regulator macromodel. The SG7915 is a three terminal, fixed, negative, voltage regulator. The format for this chapter is to develop the macromodel for the SG7915 for room temperature, then to adapt this macromodel to produce a model for the temperatures of -55°C to 125°C. Finally, lab results are shown. 4.2 DEVELOPMENT OF THE SG7915 MACROMODEL The functional block diagram for the SG7915 macromodel is shown in Fig. (4.1). This gives the starting point for the macromodel development. The macromodel for the SG7915 is shown in Fig. (4.2). The voltage reference and bias current source have been replaced by E0129 (the controlled source labeled VREF in Fig. (4.2)) and Fq. The voltage controlled voltage source EREP has VREF as it’s controlling voltage, and has a gain of 1. The error amplifier is replaced by EA, EB, R0, R9, CF, D“ D,, E“ V+ and V.. R22 and R23 are the same as depicted in the functional block diagram, replacing Rl and R2. The Darlington output pair has been replaced by one output transistor, Qp. Additions not shown in the functional block diagram will follow. E0143, qua, and the 102 103 VIN Figure 4.1 SG7915 functional block diagram resistors R0143, provide for quiescent current shaping as well as variations in quiescent current with temperature. L1, DZR, Rm R1,, Hg, and Dz1 provide the voltage reference, VREF, upon which Eaar depends. RB provides some output resistance for EB as well as base resistance for QP. Dms provides for capacitive load discharge through the device when the SG7915 is driving a capacitive load. R30 and 00c provide for frequency compensation for Q9. DDO and R00 provide for dropout characteristics. Finally, QL, Rm, Dzrs: QCL, RBCL, and Rm, provide for maximum output current limiting and foldback current limiting. This gives a general overview of the macromodel. The details of the elements and formulas follow. 4.2.1 The Reference Voltage Generator The voltage reference generator consists of L], D211: R23, R3,. Rq. D21. and E11312 104 Figure 4.2 SG7 915 macromodel wk. 1?? ’55 the. L 1'11 ‘19 ‘M‘ CITE} 105 shown in Fig (4.2). The controlled source EREF depends upon VREF and has a gain of one, so the entire reference voltage is determined by the voltage across the components L1, RR, and DZR. Em provides a voltage buffer between the reference and the rest of the circuit. It was determined that the SG7915 has an internal reference voltage of roughly 2.65V. This information was gathered from the data sheets. Note from Fig (4.1), V = [l +53l V” OUT Rfi)l 1 [1+2], (4.1) Rs +_._. Arc where ADC is the dc gain of the amplifier. This equation shows the effect that changes in Vm have on Vou'r- Note from the structure of the reference voltage generator, that VREP changes with both frequency and input voltage. The dc changes contribute to line regulation. The ac changes contribute to ripple rejection. Note the chip schematic for the SG7915 indicates a reference contains frequency dependent components. RQ provides variation in quiescent current with respect to input voltage while the regulator is at the regulated output voltage. For all practical purposes, during regulation, the voltage VREF and the voltage drop across Dz1 are constant. This means if the Groom; pin is grounded, the changes in input voltage result in identical changes in voltage drop across Rq. This results in the current in RQ changing. This current then flows through the ground terminal of the regulator which is the quiescent current. In the actual chip measurements, the output voltage remained zero for input voltages from 0 to anywhere between -1.5V to -2V. As with the SG78XX chips, there is an "on" voltage which the regulator is required to overcome. Note this behavior in . . . .1 . um _ . .a . 0N Rulrt .. 1|: Allv 1 I. I» «LL. MUM. - . 1 ml.“ 10 1.. m ... . 1 WV 0 ”‘11 I 1 ' 106 tvourt vs {VIN} SG7915 [VOUTI (volts) 16 14 |VIN| [volts] -+- rlond = 75 temp = 25 degrees C Figure 4.3 [Voml vs leI, measured Fig. (4.3) which shows measured IVOUTI vs lel characteristics for the SG7915. This effect is modeled by BVDZI. If the voltage at which activity in Fig. (4.3) begins to turn on is call VON, then this can be reproduced by setting BV,, = lel (4.2) Note that for all le1 less than IVONI the reference voltage VREF = 0 and the regulator shows no activity. 4.2.2 The Error Amplifier The error amplifier consists of EA, E3, R0, RP, 0?, D,, D,, E“ V+ and V, EA and EB are voltage controlled voltage sources whose product has a dc gain of ADC. This with CF, R1» and R0, provide for a one pole error amplifier. D,, D,, E,, V,, and V, provide for maximum and minimum clamping of the error amplifier. 1’10. 107 4.2.3 Ripple Rejection Modeling Fig. (4.4) gives an example of measured ripple rejection vs frequency for the SG7915 for several loads. In modeling ripple rejection, a couple of approximations are made. The first is that low frequency ripple rejection is assumed equal for all loads. The second is that the first pole in ripple rejection for all loads is assumed equal. Fig. R1pple Reiecuon vs Frequency SG7915 0 -20qu(voutlvrn) (db) 50‘ 50‘ 40 30 20 10 0 M—i—l I 111111 LLllllm L l llllllL _l LLLIJI“ | | 111“" I I I'll“ 1 10 100 1000 10000 100000 10000001000000 freq [Hz] -'— rload = 75 -+- rload = 750 + rload =1500 Temp : 25 degrees celsrus Figure 4.4 Ripple rejection vs frequency, measured (4.4) shows that these are reasonable approximations. The zero of Vm is the pole of ripple rejection which is seen from Eqn. (4.1). The zero generated by VREF is normally at a frequency much lower than any poles or zeros generated by any of the other reactive elements. It is necessary to find this pole. To find this, find the small signal relationship of V1130- to VIN. It is where rpm and rDZI are the small signal resistances of the diodes. Eqn. (4.3) describes 108 v = Rr*"m*-‘L1 v (43) '4 Rl+rm+Ro+rw 05:1,1 111' a simple voltage divider. Then, since the first zero of Eqn. (4.3) is the first pole of the ripple rejection, P1,, = R'Zm. (4.4) Next it is necessary to find the dc changes in output voltage, since this gives rise to low frequency ripple rejection. The dc changes in output voltage are modeled by allowing the reference voltage to vary with dc input voltage. At low frequencies Eqn. (4.3) reduces to v” = R3 + rm v“, (4,5) R. + rm -1- R0 1» run or R' ”on v (4.6) v” 1- Rlfl'm'tko er Inserting Eqn. (4.6) into Eqn. (4.1) gives £1+§IMJ . 31.011!) ... R2? “0 . (4.7) my [Aymnc 1+._l_(1+£’i) 4x Rn The high frequency ripple rejection cannot be measured, but is of interest because of it’s relationship with line transient response. The symbolic solution for the high frequency ripple rejection is determined from a symbolic circuit simulator, Sspice. The result is 0'0) 12. 109 1 mm“ RCL[1+RK)[ R” J (4.8) “R... 71." Ram. Note that R6,:L is the series resistance of the load capacitor. This series resistance must always be included for correct simulations. The SG7915 requires a load capacitor for stability. There are other poles and zeros in the ripple rejection. Most of these are beyond the range of our measurements. The reactive components which contribute to these are CBC, Cp, and CL. CL is the load capacitor, used for stability, and is not part of the actual macromodel, but must be used in the development. Cp is determined empirically by power up measurements. CBC is determined empirically by trying to match a zero in the macromodel ripple rejection response to the zero seen around 100kHz in Fig. (4.4). 4.2.4 Output Impedance Modeling We were not able to measure the output impedance of the SG7915. This is because the dc voltage of the SG7915 was out of range of the HP4192A impedance analyzer. Low fiequency output impedance, can however be deduced from load transient response measurements and load regulation measurements. The low frequency output impedance is just the output resistance of the SG7915, and this is determined in the macromodel by the relationship “our. 90791: = Roar (4’9) 4.2.5 Quiescent Current Modeling In Fig. (4.2), the elements which contribute to quiescent current are Fq, E01 43, V0103. and the resistors RQ1 4,. Due to the reference voltage drop across Rn, it too 1111' 110 IQ vs (VIN) 567915 10 (amps) 0.005 0.004 0.003 0.002 0.001 ol (VIN) (volts) "1— temp = 25 temp = 25 degrees C Figure 4.5 Quiescent current vs le ), measured contributes to quiescent current. This is deduced from Fig. (4.1). The measured quiescent current vs input voltage is shown in Fig. (4.5). The most interesting phenomenon here is the very sharp jump at roughly the point at which the chip goes into regulation. Because this is a complicated phenomenon to model, and gets even more complicated to model with temperature, there are many elements used to model this behavior. Quiescent current is modeled in the macromodel in the following way. For the analysis, it is convenient to label certain critical voltages and currents as well as slopes of curves. All voltages discussed will be taken in the positive sense. Using Fig. (4.5) as a reference, let the point at which the quiescent current just begins to flow be labeled VON. Let the point at which the first discontinuity occurs be labeled V1 and II. This is roughly at VIN = 6V in Fig. (4.5). Let the point at which the jump occurs be V2 and I2 and this occurs at roughly 16V. Let the point directly after the 31111 «av-J 3:1 I) :0 33031 -1 .- 111 jump be labeled Va and 1,, and note this occurs at approximately 16.5V. Finally, the let the slope of the Quiescent current vs lle l curve after this point be called (AIQ/AVINMG. The analysis follows. The current controlled current source FQ has the currents through the independent voltage sources VQW, as its controlling currents. FQ has the PSpice definition FQ 4 3 POLY (3) VQl VQ2 VQ3 0 1 1 -1 which means that [m = I”, +Im-IIIJ’ (4.10) since the voltage sources VQ1 43 are dc sources of 0V. The voltage controlled voltage sources Eel-ea all have the voltage drop between the ground and input terminals as their controlling voltage, and this is just V(1,3). Instead of the normal gain relationship between the controlled sources and V(1,3), the table look-up option of PSpice is used. This is done for convenience. The voltage controlled voltage sources are defined in the following manner: EQl 1000 0 TABLE {V(1,3)} (VON. 0) (V1. V1 - Von) qu 2000 0 TABLE {V(1,3)} (V1. 0) (V1. V2 - V1) E03 3000 0 TABLE {V(1,3)} (V2. 0) (V3. V3 - V2). Describing EQI, for example, note that there is zero voltage until V( 1,3) attains VON. When V( 1,3) attains V1, the voltage across the voltage source is V1 - VON, and the Voltage source retains this value for increasing V( 1,3). Note that Vl - V0N is the change in voltage that V(1,3) undergoes during it’s transistion from Van to V1. E92 and EQ3 follow the same pattern. 112 Now for V(1,3) = VD, fi‘om zero to VON, all of the controlled sources, as well as approximately Vm, are ofl‘ in the macromodel, so IQ = 0A. When VIN = VON, qu begins to turn on, but IQ is still equal to 0A. For Vm = VON to VIN = V,, E0243 are ofl‘, E01 is on, and current flows though VQ1 and hence Fq. This is the main contribution to quiescent current in this region. At VIN = V,, the current through FQ is I1 = IQ and this current is the current through V01, 01‘ 1, = ELLE". (4.11) Ra: At VIN = V1, EQ2 begins to turn on and hence IRQZ begins to contribute current. This occurs until VIN = V2. The current IQ now consists of current contributed from 1m], Inn, and R23, since at this point the voltage across R23 is VREF. Then Vm Vz’yi + 9 R2, Roe since the voltage across RQ2 at this point is V2 - V,. (4.12) 12"“ Finally at V2, EQ3 begins to turn on and Ines now contributes current to the quiescent current. This current, however, is subtracted from FQ which causes the "jump" seen in Fig. (4.5). At V3, 1EQ3 has reached its maximum value and (4.13) At this point, EQI-Q3 are no longer changing with input voltage, so there is no longer any variation in the current through the dependent source Fq. Note however, there is a slight increase in quiescent current with increasing Wm |. This change comes from Re. Since Vm and Voz: have little change in voltage with changes in 113 leI, all of the change in input voltage is dropped across RQ in the reference circuit. This means lAle = .______ (4.14) A10 4.2.6 Short Circuit Current Limiting and Foldback Current Limiting An example of measured short circuit current limiting and foldback current ISC vs VDIFF SG7915 ISC am a 3.5 l D] temp = 25 degrees C Figure 4.6 Maximum output current vs Vamp, measured limiting is shown in Fig. (4.6). The elements in the macromodel that contribute to short circuit current limiting and foldback current limiting are Groom» G3. D3» QCL» RscL: Roi.» Dm. R53, and Q1, The short circuit current works in the following way. Note the similarities with in the short circuit current limiting with the SG78XX and SG7915 voltage regulators. 114 DB prevents the controlled source E3 from supplying any current to the base of Q9. This means that GB is the only supplier of base current to Q9. Since the output voltage is negative, all of the load current must flow out of the load and through the collector of Q... This is approximately equal to the current flowing out of the emitter of Q,. As current flows out of the emitter of Q. through RCL, a voltage is generated across the base emitter junction of QCL. If this voltage is large enough to turn QCL on, the current supplied by GB is drawn by the collector of QCL, since its needs are large compared to the current supplied by G3. This means that QP begins to turn off. If the voltage is not large enough, QCL remains ofl‘, drawing no current and QP is active. The maximum output current is just the current necessary to turn ch. on. This is Vnoucz. - _____’__, (4.15) This is a very simplified explanation of how short circuit current works, however it serves to explain the fundamental operation. Under the short circuit mode, the base of QP actually draws a little current, but this is negligible. The collector of ch draws most of the current available from GB. Then, Vfimm,CL can be estimated since the collector current of QCL can be estimated as approximately the current supplied from G3, which is 813va Using an approximation for the relationship between collector current and base emitter voltage and inserting into Eqn. (4.15) gives v V, In [8' m) I ma Im Ra, (4.16) The voltage controlled current source G3 has V339 as its controlling voltage. The transconductance of GB, g, is set so that the total current flowing out of GB is 115 roughly 10mA when Vm attains its steady state value. The value of mm was selected based on the needs of CBC during the line transient response. During line transient response CBC needs to draw several milliamps of current and this is supplied by GB. If GB was added, and GCOMP was not added, this mm of current would add to the total quiescent current. This is undesirable as in the regulated state because the quiescent current is only about 1-2mA. To compensate for this, GCOMP was added GCOMP is defined identically to G3, except that it supplies current to pin 1, whereas GB draws current out of pin 1, and the net efl'ect on pin 1, and the net effect on quiescent current, is now 0A. Finally, foldback current limiting is provided with the addition of Dzrm RFD, and R301, Note the addition of QL as well. QL was added because it was noticed that quiescent current, upon the power up and down response, was inaccurate due to current flowing through Der- Placing QL here prevents this. Note that the placement of a transistor here is identical to what is found in the SG7915 schematic. An explanation of foldback current follows. The voltage differential is roughly the voltage drop across R93, DZFB, RBCL, and Ru, When the differential voltage is not large enough to place Dm in the breakdown region, there is no drop across RPB and very little drop across Rm, since the base current of QCL is small. Once the differential voltage is large enough to place DZFB in the breakdown region, the macromodel enters into the foldback region. Let this voltage be referred to as V1.3. Any further increase in the difi'erential voltage is mainly dropped across R“, and Ram; The voltage drop across the base emitter junction of QCL is ”a = vm+ m. (4.17) The turn on voltage of QCL is fixed, as well as the voltage across Vm. This is means 116 that, in the foldback region, a smaller voltage drop across Rex. is needed to turn on QCL, and hence a smaller maximum current is available to be supplied by the output. As the differential voltage across the chip increases, the voltage drop across Ram. increases, and the maximum available output current decreases. This is how foldback current limiting is achieved. Since the foldback region begins at the point where the differential voltage across the chip, V9,”, is equal to VFB and the voltage drop across R0,, DVD”, 1! V" - (”Rev (4.13) The components RBCL and RPB can be selected by selecting a point in the foldback region which gives the maximum output current for a given differential voltage. Then it can be determined that Rn VIACLGV = (Vom‘yn) {W]+Imkcr (4'19) Where V1,,” and Imrr represent the voltage and current at the selected point. 4.2.7 Power Up and Down, Square Wave Fig. (4.7) gives the measured power up and down response. There are two main contributions to the square wave input phenomenon. The first is the phenomenon which occurs as the input is powered up. As seen in Fig. (4.7), initially the output voltage peaks at a voltage slightly less than the input voltage, then oscillates before settling down to the regulated value. This is mainly due to the capacitor in the error amplifier, 0],. This effect is proportional to the time constant determined from R0 and CP, since it should be noted that R, is set very low. 117 rusting i 96; . ZAiSYX¢3 . 3 ) a 5:22: 959i5&333°.?§E¥LL9?53351 :: .3... ‘ hiflq’ ! l l l l ...—..‘- v- —. Md" El“ C trth . 5'! ..... v WV—fi vvfi— *ZBV -l98us Figure 4.7 Power up and down, square wave, measured lBBus/diu . BBBus [lit 42 volt tier tech 42.91 118 Presently, there is no formula for determining these values. They have been adjusted empirically. Secondly, when the chip is powered down, and the load is capacitive, the load must discharge. This will normally be the case for the SG7915 as a capacitor was always required on the output for stability. The path for this discharge is through ground, however this forces the need for a current to be supplied at the output pin. By measurement it is determined that the some supplies this current. Note that in Fig. (4.7) the difference between the input and output voltage at power down is roughly one diode drop, as with the SG781OC This is further justification for use of this ans- The parameters for DDIS can be selected empirically, although the default diode works well. 4.2.8 Dropout Characteristics The dropout characteristics are done primarily by DDO and Q9. The dropout voltage is then the voltage drop across these elements when QP is on the edge of saturation. Then VDO "‘ Vow * Var. or (1m) + [manna ’ (4'20) Where it should be noted that Vamp is a function of the load current. Then NDC can be chosen to realize a dropout voltage for a given load with I VDO " Nana Win (73%} VSAZQP(ILOID)+ILO‘DRIOID (4’21) 43.9 Other Modeled Characteristics The prior characteristics gives the characteristics modeled which are used to determine the proper choice of values for the components and the parameters of the 119 components for the SG7915 voltage regulator macromodel. Because of a correct choice of parameters, the macromodel can accurately predict other responses. These are: power up and down with triangle wave, line transient response, load transient response, line regulation and load regulation. 4.3 DESIGN PROCEDURE FOR A SG7915 Based on the equations and procedures shown in the last section, a design procedure will be developed in this section. Basic to the design procedure is a list of measurements required to base the design on. The following measurements should be taken in the basic regulator circuit: 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) Measure VOUT vs VIN with no load. Measure IQ vs VIN with no load. Measure VOUT for VIN = -20V. Measure ripple rejection vs frequency with a 750 load. Take a line transient response measurement with a 7 59 load, determine the ratio of the first peak to the change in input voltage, call this RR”. Measure maximum output current vs voltage differential. Take a load transient response measurement, determine the value of the difi‘erence in the steady state output voltages with and without RLOAD = 759. Measure dropout voltage with RLOAD = 759. Take a power up measurement with RwAn = 750. Measure Brow: this value gets used in all of the equations. Also 120 measure Com, the output capacitor, and Room. the effective series resistance of the capacitor. The component selection procedure is: 1) 2) 3) 4) 5) 6) 7) Select EA and EB , this will determine ADC. Select It,2 = 12.5kQ, R23 = 2.691(5), these selections are based on the actual chip component values. Select the amplifier clamping circuitry, these values are: V,, V,, E,, E,, and the diode parameters for D+ and D, Based on the VouT vs Vm measurement, determine the input voltage required to begin to turn the circuit on, Von. then BVM = lel. (4.22) Select NBVDZI. From the measured value of Vow. at VIN = -20V, and utilizing Eqn. (4.1), V arm = Vm = 0'” (1+Zl[1+%)). (433) Select NBVDZR and Rm. Measure the slope of IQ vs vs: for the quiescent current measurement. Then from Eqn. (4.14), lAVn/l. (4.24) From the ripple rejection measurement, determine RR”. Then determine the small signal resistance of DZR. This is determined from 8) 9) 10) 11) 12) 13) 121 a trial macromodel run with PSpice. Then from Eqn. (4.7), (ti-(“Ellmqm l + g ( R23 From the ripple rejection measurement, determine P1“, then from Eqn. (4.4), then L. = RR"M, (4.26) Flu Select R1,. From the power up measurement determine CP empirically. Also from the power up measurement, and measuring the difference in the input and output voltage waveforms directly after power down, select and appropriate value for NDDIS. From the quiescent current vs input voltage measurements determine V1, V2, V3, and I1, I2, and I3, then the table definitions for E1, E2, and E3 become (VON, O) (V 1, V1 - VON) (V1, 0) (V 1, V2 - V1) and (V2, 0) (V 3, V3 - V1). From the quiescent current vs input voltage measurements and Eqns. (4.11). (4.12), (4.13), VI " ym (4.27) 14) 15) 16) 17) 19) 20) 21) 22) 122 - Vz‘Vr Roe V.’ (438) lz-ll-E V—V “"4 =-~’ ’- 4.29 ”as ,3_,2 ( ) Select the parameters for the output transistor Qp. These are: BF, VAF, NF, and IS. Select RB. Select the parameters for the transistor QCL. QCL can normally be the default transistor specified in PSpice. Select the parameters for the transistor QL. QL can normally be the default transistor specified in PSpice. Select RBCL. From the maximum output current vs voltage difi‘erential, select the of ICL when not in the foldback region. Then from Eqn. (4.16), g,Vm Isa . (4.30) RC]. = VTln Isc From the maximum output current vs voltage differential, select the value where the curve enters into the foldback region and call this voltage V”. Then from Eqn. (4.18), ”Vans " Vn'lruxkcr “'31) Select NBVoer- From the maximum output current vs voltage differential, select a value 23) 24) 24) 25) 123 for the maximum output current and its corresponding output voltage, in the foldback region, call this VDIFF and IBM. Then from Eqn. (4.19), x” (4.32) From the line transient response, determine RRHF, then from Eqn. (4.8), 111—13134) For the ripple rejection vs frequency measurement, determine approximately where the third pole should lie. This is dificult, but it should be in the area of slightly greater than 100kHz. From Sspice, the result is, 1 E3 _ LRSCL)LRADC (4.34) C = n . 1” CrRaRl-Rr From a trial run with the macromodel, determine the value for VSAT QP. Select ISDC. Determine the value of the load current. From the measured dropout voltage, VDO, and Eqn. (4.21). _ mo'yunar‘lmwkod NM - I VTln[—m£ (4.35) am) From the load transient response measurement, measure the jump in the voltage when the 7 50 load is switched on and ofl’. Then from Eqn. (4.9). 124 Ra = A vow your, 1mm 26) Select the parameters for the diodes DBL and DCL, rm (4.36) IS and N. These may be important for convergence reasons. This concludes the design procedure. All of the parameters for the macromodel have been selected. 4.4 DESIGN EXAMPLE FOR A SG7915 An example of the design of the SG7915 will be shown in this section. The design is based on actual laboratory measurements. The data, unless otherwise specified, will be taken 03‘ the data shown previously. The load resistor was measured at 74.969. An output capacitor was required for stability. The capacitor had a series capacitance of .7561uF and a series resistance of .6156!) at 100kHz. Based on the procedure for parameter and component selection given in section 4.3, the component and parameter selection is: 1) Set EA = 600, EB = 1, then ADC = 600. 2) Set R22 = 12.5kfl and R,3 = 2.69m. 3) Set V, = -1V, V, = 1V, and the gain of E, to 1. This gives VMAX = 0.3V and VMIN = (V(3,1) + 0.3)V, assuming diode drops of roughly 0.7V. Select the parameters of the diodes D, and D, as N = 0.1, EG = OeV, XTI = 0, and CJO = 0F. Throughout the design example, several diodes will have the parameters EG and XTI set as above. This is done for convenience and renders IS for the diodes less temperature sensitive. Also, CJO will frequently be set to lpF. This is done because it helps 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 125 diodes converge better in PSpice. [VON] = 2V, so BVDz1 = 2V. Set NBV = 0.01, EG = O, and XTI = 0. Vow. = -15.17V, so BVDZR = 2.7117V set NBV = 0.01, RZR = 1MEG9. Rq = 42072.41919. RR”. = 61.1117db = 0.8799m and rum = .779, so RR = 5.84759. The first pole of ripple rejection, P1“, is 5.0667kHz. Then L1 = .2079mH. Set RP = 19. Based on the power up measurements, CI, = luF. Based on the power up measurements, Nnms = 1. From the Quiescent Current vs leI measurements, the following voltage and currents are found: 11 = 1.9999mA VI = 6.5V I, = 4.6570mA v2 = 16V 1, = 1.4391mA v, = 16.5V. Also IVONI = 2V. The voltage definitions give rise to the following definitions for the voltage controlled voltage sources EQ1 43: EQl 30 0 table {V(1,3)} (2,0) (6.5,4.5) EQ2 32 0 table (V(1,3)) (6.5,0) (16,9.5) EQ3 34 0 table {V(1,3)} (16,0) (165,5). From the information in 12), Run = 2251.12569 Ru: = 5757.80939 R93 = 155.389 14) 15) 16) 17) 18) 19) 20) 21) 22) 23) 24) 25) 126 Select the parameters for Qp: BF = 70k VAF = 150V IS = 1e-14A. The rest of the parameters are the PSpice default parameters. Set R.B = 5. Let ch. be the default transistor in PSpice. Let QL be the default transistor in PSpice. Set RBCL = 1000. From the maximum output current vs voltage difl'erential measurement, Iqu = 3.3A, then RCL = .21759. From the maximum output current vs voltage difi'erential measurement, VF13 = 8.57V, then BVDZFB = 7.8523V. From the maximum output current vs voltage difi‘erential measurement, Vmpp = 28.61V and IDIFF = 1.3064A, then R1.B = 46866.39. From the measured line transient response, RBC = 1762.019. Set CBC = 1nF. Set Rno = .19. V3“:QP = 0.077V and VDo = 0.94V for a 759 load, then NDDO = 1.0627. From the Load Transient Response Measurement, IAVoml = 18mV, with a 759 load, then R0 = 0.08919. The room temperature macromodel parameters have been selected. 127 4.5 MODELING THE SG7915 AT -55 AND 125 DEGREES The strategy for model the SG7915 is done the same way as the SG78XX for modeling at -55 degrees and 125 degrees. 4.5.1 Strategy in Modeling the SG7915 Temperature Variations The room temperature model is developed first. The steps which need modifications are steps 4, 5, 6, 7, 8, 10, 12, 13, 19, 20, 21, and 25. These will give rise to new values for BVDZI, BVozn: Rq, RR, L1, 0?, qum, RSC, BVoer: R“, and R0. Lab data will be taken and the above parameters will be selected Temperature coemcients are then selected base on the variation of the above parameters with temperature. 4.5.2 Design Example to Include Temperature Dependance In this section the parameters for the model for -55°C and 125°C will be developed. The temperature coeficients will be determined and then inserted into the room temperature model. This will represent the fully developed, macromodel for the SG7915. Based on the design example given in section 4.4, the design for the -55 degree temperature model is: 4) IVONI = 3V, so BVDz1 = 3V. 5) VOUT = -15.23V, so BVDZR = 2.7225V. 6) Rq = 542012212. 7) ,. = 61.7733db = 0.8153m and rm = .7149, so R, = 7.18549. 3) The first pole of ripple rejection, P1“, is 7.2333kHz. Then L1 = . 1738mH. 10) Based on the power up measurements, 0,, = luF. 12) 13) 19) 20) 21) 25) 128 From the Quiescent Current vs leI measurements, the following voltage and currents are found: I1 = 2.6898mA v, = 6.5V 1., = 6.4858mA v, = 16V 1, = 1.60897mA v, = 16.5V. At -55 degrees V1.3 are not exact, as the controlled sources E0193 have not been made temperature dependent. From the information in 12), R,21 = 1681.989 qu = 3654.349 R03 = 1029 From the maximum output current vs voltage differential measurement, Iso = 3.9A, then RSC = .21619. From the maximum output current vs voltage differential measurement, V“, = 9.47V, then BVDm = 9.1635V. From the maximum output current vs voltage difi'erential measurement, Vow. = 32.99V and IBM. = .88A, then Rm = 328469. From the Load Transient Response Measurement, IAVOUTfl = 9mV, with a 759 load, then R0 = 0.04439. The design for the 125 degree temperature is: 4) 5) 6) 7) 'VONI = 1.5V, 80 BVDZI = 1.5V. VOUT = -15.18V, so BV,”, .-. 2.7135v. R, = 132226.929. RR”, = 58.2383db = 1.2249111 and rm = 2.889, so R, = 26.07259. 8) 10) 12) 13) 19) 20) 21) 25) 129 The first pole of ripple rejection, P1“, is 3.1333kHz. Then L1 = 1.4706mH. Based on the power up measurements, CP = luF. From the Quiescent Current vs IVINI measurements, the following voltage and currents are found: 11 = 1.3192mA vi = 6.5V 12 == 3.0980mA V2 = 16V I3 = 1.1593mA V3 = 16.5V. At 125 degrees V” are not exact, as the controlled sources E9193 have not been made temperature dependent. From the information in 12), RQl == 3411.1589 R,12 = 13951.69 R93 = 257.99 From the maximum output current vs voltage differential measurement, ISC = 2.2556A, then RSC = .247 99. From the maximum output current vs voltage differential measurement, VPB = 8.1001V, then BVner = 7 .5408V. From the maximum output current vs voltage difl'erential measurement, Vnm, = 29.06V and Imp? = .8834A, then R“, = 61609.99. From the load transient response measurement, IAVOUTI = 20mV, with a 759 load, then R, = 0.09889. A final summary of the temperature dependent parameters and elements follows in Table 4.1. 130 element or as at v the at 3 at flame £8599 933933 93999 BV,", 2 3 1.5 , BVnm 2.7117 2.7225 2.7135 R0 42072.4191 54201.22 132226.92 R11 5.8475 7.1854 26.0725 LI 0.2079m .17 38111 1.4706m Co lu 1u 1u RQL 2251.1256 1681.98 3411.158 . rBQL 57 57 .8093 3654.34 13951.6 Rm 155.38 102 257.9 L331; .2175 .2161 .2479 Eva,“ 7.8523 9.1635 7.5408 Rm 46866.3 32846.0 61609.88 RQ 0.0891 0.0443 0.0988 Table 4.1 Temperature dependent parameters and elements Solving for the linear and quadratic coefficients for each of these components and parameters leads to the following results for Table 4.2 3mg: 13:521.” )1 5.352.133.3243 anm 0004583 2.08333e-5 BVMR -2.4708e-5 3.1346e-7 Rs 0.007522 1.390744 R11 .01378 2.0804e-4 14 0.02119 3.9548e-4 Cp 0 0 R9. 0.004046 1.1071e-5 133k 0.008862 5.3689e-5 R4... 0.005318 1.2798e-5 gm 6.659e-4 7.318e-6 va -0.001336 9.3921e—6 Rm 0.003476 -3.2975e—6 fig 0.003976 -2.8869e-5 Table 4.2 Temperature coefficients 131 The final macromodel for the SG7 915 follows. The macromodel includes the efi‘ects of temperature. .SUBCKT SG7915 1 2 3 11 GND OUT IN * L1 4 1 IND1 .2079m .MODEL INDl IND (TCl=0.021188 TCZ=3.9548E-4) DZR 29 4 DZR .MODEL DZR D (BV=2.7117 TBV1=-2.4708E-5 TBV2=3.1346E-7 NBV=0.01 EG=O =0 CJO=1P) RR 29 15 5.8475 TC=0.013783,2.0804E-4 RQ 15 22 420724191 TC=0.007522,1.3907E-4 D1 3 22 D1 .MODEL D1 D (BV=2 TBV1=-0.004583 TBV2=2.08333E-5 NBV=0.01 EG=O XTI=0 CJO=1P) FQ 1 3 POLY (3) VQ1 VQ2 VQ3 0 1 1 -1 EA 9 3 5 15 600 R0 6 9 200 D+ 6 20 DC E+ 20 21 1 3 1 V+ 21 3 -1 D- 19 6 DC .MODEL DC D (EG=0 XTI=0 CJO=1P) V- 19 3 DC 1 RP 6 7 1 CP 7 3 ID EQl 23 0 TABLE {V(1,3)} (2,0) (654.5) VQ1 23 24 DC 0 RQl 24 0 2300.0318 TC=0.004046,1.1071E-5 EQ2 25 0 TABLE {V(1,3)} (6.5,0) (16,9.5) VQ2 25 26 DC 0 RQZ 26 0 6670.73 TC=0.008862,5.369E-5 EQ3 27 0 TABLE {V(1,3)} (16,0) (16.5,.5) VQ3 27 28 DC 0 RQ3 28 0 155.4 TC=0.005318,1.2798E-5 GB 1 8 1 15 4M GCOMP 3 1 1 15 4M DB 8 18 DB .MODEL DB D (N=.1 EG=0 XTI=0 CJO=1P RS=.1) EB 18 3 7 3 1 RB 8 10 10 QL 1 14 14 QTEMP .MODEL QTEMP NPN RFB 12 14 46.8663K TC=.003476,-3.2976E-6 DZFB 13 12 DZFB 132 .MODEL DZFB D (BV=7.8523 TBV1=-0.001336 TBV2=9.3921E-6 NBV=0.1) QCL 10 13 3 QMOD RBCL 13 17 1000 RCL 17 3 .2175 TC=6.659E-4,7.318E-6 RBC 11 14 1762 CBC 10 11 IN QB 16 10 17 QMOD .MODEL QMOD NPN (IS=1E-14 BF=7000O VAF=150) DDO 14 30 DDO .MODEL DDo D (N=1.0627) RDO 30 16 .1 1123 1 5 2.69K 1122 5 14 12.5K ROUT 14 2 0.0891 TC=.003976,-2.8869E-5 DDIS 3 14 DDIS .MODEL DDIS D(IS=1E-12) .ENDS SG7915 133 4.5.3 Comparison of Macromodel Predictions with Lab Results A comparison of macromodel predictions with lab results is presented in this section. Ripple Rejection vs Frequency SG7915 -20log[voutlvm) (db) 7O D J L llllfl 1 .I 111119.] I 1 111111] I l I llllll 1 l lLle l l lllllll l 1 L11 1 ID 100 1000 10000 100000 10000001000000 freq (Hz) —— temp - -55 —+—temp - 25 + temp 2125 rload I 75 Figure 4.8 Ripple rejection vs frequency, measured I'l' Cll' _ _ torr'p I -55 doérooo c so- - - - tomp- - 12$ door... C 401 [W I 25 600?... C 201 ‘in): 1611 16011 1.0Kh 10301 106101 1 .51»! WW! . . ‘ -db(V(2)IV(1)) PPOQUOflCY Figure 4.9 Ripple rejection vs frequency, macromodel 134 11401 oxsrr 2 N6 SCIL 3.... 1.3—smile 1?... L9?28§’51 1:: #33258‘963361812463-3’ 8V —.—~ . . . .. . .3 was New" __{ 1‘ .l ? ; . l 5 3V 2' ~"div w —-If./6I 130431310 —“’ 88248 Figure 4.10 Power up and down, square wave, measured 135 pu.cir UV - e : : _ ; (”W (1 , . term --; 25 degrees C II 4) .. 1, U 0 -10v1 - - 1 T ' - l. L s s 4, ‘ . -20V , A. ; c , , 08 0.2171 0.401: 0.61118 0.9618 1.01719 oV(2) 0V(3) Figure 4.11 Power up and down, square wave, macromodel 136 11:21 3131332136.?323LL333333. i 3:8:35238‘Yoi'86181443-3’ ‘EBV 1_ . -756us EBan/d l v 1. 24458 Figure 4.12 Power up and down, triangle wave, measured 137 pu_trl.clr 4V 0V- -‘v. -ov. -12V- -16V~ ~20V Os ' ' ' nV(2) 'V(3) 0.5015 1.0111: 1.5ms 2.0m: Time Figure 4.13 Power up and down, triangle wave, macromodel 138 11123 3391312136.?323LL333933. 114133.2321113-33131113-31 M ~ ii. I _ "‘V-TILV High as i L. - , F9 '901/ L—. ,1 -S48m‘.’ w w- 1 W- 'W' - 19. ass 1811355119- 88-2113. Figure 4.14 Line transient response, measured 139 ltr.c1r temp =‘25 degrees C -15.1V- -15.2V- -1$.3V- . . . -1S.4V- -15.5V- 0: zn'us «in: soils 80a: ‘lllllus eV(2) Time Figure 4.15 Line transient response, macromodel 140 11323 13.91.11.2163329533235. 1141333.231511-3118114331 i '_" l i t 1 == ~ I l iSBmV r'd 1v! -- . . E i :3“: "MI“ 3 L .8 l . uo‘v ~995 V ‘ _, ‘ ’136143 288143 /d W 1. 884»; Figure 4.16 Load transient response, measured 141 ldtr.cir tew = 25 degrees C ~14.9V- -15.2V- . . . . -15.6V- 08 0.51116 1.6ms Lims 2.0ms nV(2) Time Figure 4.17 Load transient response, macromodel 142 IQ vs :VIN: SG7915 IQ [amps] |V|N| (volts) -*— temp = -55 -*— temp = 25 + temp =125 Figure 4.18 Quiescent current vs IVIN I, measured qu1e6.clr 8.0M4 ....................................... ‘—___1emp = -55.deorees 0 I em - 25 de reee C 4.0"“4 ________._.8. p g I e . . emp - 125 degrees C [OM-1 - - . . . . .......................... DA —. 1 , . . . . . 0" 0v 15v 20v 25v 30v 35v 40v 5V 1 - o altreules) vun Figure 4.19 Quiescent current vs IVmI» macromodel 143 ISC vs VDIFF SG7915 IQ am 3 5 ( pl 4... ....................................................................................... 3.. -------------------------------------------------------------------------------- 2.. ....... 1,1, .............. . ............................................. ...................................................... - ................. .3 i _1_ P L L J J L J D 5 10 IS 20 25 30 35 40 WW] (volts) Figure 4.20 Maximum output current vs le I, measured (2|.le - 1.04 L J ' ' ' g . V sv 10v 15v 20v 25v 30v 35v 40v 3 0 A l(r load) VI" Fligure 4.21 Maximum output current vs le l, macromodel 144 Comparison of Macromodel parameters and Measured Parameters QUANTITY -55°C 25°C 125°C RR“, lab 6 1.8db 61.1db 58.2db model 61.7db 61.2db 58.2db le lab 7 .233kHz 5.067kHz 3.133kHz model 6.558kHz 4.9506kHz 3.074kHz 131mm lab 6.486mA 4.657mA 3.098mA model 5.874mA 4.595mA 2.971mA I _ v lab 1.789mA 1.519mA 1.239mA model 1.194mA 1.542mA 1.073mA AIQ/AVin lab 18.45u 23.76u 7.56u model 18.045u 24. 1 1n 7.807 u maximum output current lab 3.947A 3.299A 2.303A model 3.893A 3.314A 2.265A dropout voltage lab .8V .94V .78V model 1.088V 1.0622V .924V output resistance lab 0.04439 0.08919 0.09889 model 0.0469 0.0919 .1039 Table 4.3 Macromodel comparisons with lab data This concludes the comparison of the macromodel with lab results as well as the description of the development of the SG7 915 macromodel. 145 4.6 TEST CIRCUITS 4.6.1 Pspice Test Circuits 3 367915 8 O _6 1 VDUT 10001 — Figure 4.22 Basic PSpice test circuit 146 RRCIR * *ripple rejection for the sg7 915 * VIN 3 0 DC ~20 VAC 1 3 AC 1 RLOAD 2 0 74.96 COUT 2 4 .7561u RCOUT 4 0 .6156 XREG 0 2 1 sg7 915 .OP LIB SG7915.LIB .OPTIONS NUMDGT=10 ITL5=0 ITL1=300 ITL2=300 .AC DEC 20 10 1MEG .TEMP ~55 25 125 .PROBE .END PU.CIR * *power up for the SC? 915 * ROUT 2 0 74.96 COUT 2 4 .7561u RCOUT 4 0 .6156 X1 0 2 3 SG7915 VP 5 0 PULSE (0 -20 200u 0 0 500u) RP 5 3 0.1 .OPTIONS NUMDGT=10 ITL5=0 ITL1=300 ITLZ=300 .LIB SG7915.LIB .TEMP -55 25 125 .TRAN 1u 1000u 0 1n .PROBE .END 147 PU_TRI.CIR * ’“power up, with triangle wave, for the sg7915 * ROUT 2 0 74.96 COUT 2 4 .7561u RCOUT 4 0 .6156 X1 0 2 3 sg7915 VP 5 0 PULSE (0 -20 0 600u 600u 1u 1202u) RP 5 3 0.0001 .OPTIONS NUMDGT=10 ITL5=0 .LIB SG7915.LIB .TRAN 2.5u 2000u 2.5u .TEMP -55 25 125 .PROBE .END LTRCIR * *line transient response for the sg’7 915 * ROUT 2 0 74.96 COUT 2 10 .7561u RCOUT 10 0 .6156 X1 0 2 3 sg7915 VIN 11 0 DC -20 VP 3 11 PULSE (0 -4 20u 0u 0u 60u) .OPTIONS NUMDGT=10 1T15=0 ITL1=300 ITL2=300 .LIB SG7915.LIB .TEMP -55 25 125 .TRAN .5u 100u 0 .5u .PROBE .END 148 LD’PRCIR * *load transient response for the sg7815 * VP 10 0 PULSE (-15 0 400u 0 0 20%) RLOAD 2 10 75 COUT 2 11 In RCOUT 11 0 1.5 X1 0 2 3 SG7 915 VIN 3 0 DC -20 .OPTIONS NUMDGT=10 ITL5=0 ITL1=300 ITL2=300 .TRAN 5u 2000u 0 5n .LIB SG7915.LIB .TEMP -55 25 125 .PROBE .END QUIES.CIR * *quiescent current for the sg7 915 * RQUIES 0 1 100.06 VIN 0 3 do 20 RLOAD 2 0 1e8 COUT 2 10 7.561e-6 RCOUT 10 0 0.6156 XREG 1 2 3 SG7915 .OPTIONS NUMDGT=10 ITL1=300 ITL2=300 .LIB SG7915.LIB .DC VIN 0 40 1 .TEMP -55 25 125 .PROBE .END 149 CL.CIR * *short circuit current for the sg7 915 * VIN 0 3 DC -10 RLOAD 0 2 1.0532 COUT 2 4 .7561u RCOUT 4 0 .6156 XREG 0 2 3 SG7915 .OPTIONS NUMDGT=10 ITL5=0 ITL1=300 ITL2=300 .LIB SG7915.LIB .TEMP -55 25 125 .DC VIN 0 33 0.5 .PROBE .END VDO.CIR * *dropout characteristics for the sg7915 * VIN 0 3 DC -10 RLOAD 0 2 74.96 COUT 2 10 .7561u RCOUT 10 0 .6156 XREG 0 2 3 sg7915 .OPTIONS NUMDGT=10 ITL5=0 ITL1=300 ITL2=300 .LIB SG7915.LIB .DC VIN 0 20 0.1 PM RES=75 .TEMP -55 25 125 .PROBE .END 150 4.6.2 Measurement Test Circuits 867915 1‘ 3 l Figure 4.23 Test circuit No. 1 The conditions of test circuit N o. 1 are stated. COUT measured .7561uF at 100kHz. Rcou-r represents the series resistance of COUT and measured .61569 at 100kHz. R3, R4, R5, and R,, have nominal values of 1k9. V+ is a positive 10V dc power supply. V- is a negative 50V dc power supply. 0A is a Burr-Brown OPA541 Op-Amp. The SG7915 resides inside a temperature chamber. Wires are connected at the terminals of the SG7915 to allow it to be connected outside the chamber to the test circuit. 151 3 867915 2 1 o T 1 100m - 0011:: Ram ”+0 + II 1) ill—0+ Figure 4.24 Test circuit No. 2 The conditions of test circuit No. 2 are stated. COUT measured .7561uF at 100kHz. Ream represents the series resistance of Cow and measured .61569 at 100kHz. R3, R0 R5, and R,3 have nominal values of 1k9. V+ is a positive 10V dc power supply. V- is a negative 50V dc power supply. 0A is a Burr-Brown OPA541 Op-Amp. The SG7 915 resides inside a temperature chamber. Wires are connected at the terminals of the SG7915 to allow it to be connected outside the chamber to the test circuit. RQUIES has a nominal value of 1009, and measured 100.069. 152 V+ VA R _ 3 4 867915 - - r 3 2 O ...... “I“ 11 11: + 4. WT V— G ‘V‘VA' AVAVAT JAVA VIN V 4 R5 R5 Figure 4.25 Test circuit No. 3 The conditions of test circuit N o. 3 are stated. Cour measured .7 561uF at 100kHz. Room represents the series resistance of COUT and measured .61569 at 100kHz. R3, R4, R5, and R,, have nominal values of 1k9. V+ is a positive 10V supply. V- is a negative 50V supply. 0A is a Burr-Brown OPA541 Op-Amp. The SG7 915 resides inside a temperature chamber. Wires are connected at the terminals of the SG7915 to allow it to be connected outside the chamber to the test circuit. Q, is a 2N4403 pnp transistor. RB, has a measured value of 5.526k9. RB, has a measured value of 62.4309. 1) 2) 3) 4) 5) 6) 7) 8) 153 Ripple rejection was done using test circuit 1. VA was connected to an ac fimction generator. VB was connected to a negative dc power supply. These were set to produce a -20V dc voltage at Vm, with a sine wave superimposed. Rm“, measured 74.969. Voltages and phases were measured with a Tektronix 11401 scope. The Vm vs V0,”. and V0,“. at V1,, = -20V measurements were done using test circuit 1. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. V,3 was grounded. These were set to produce the necessary voltage at Vm. R1010)» when used, measured 74.969. Voltages were measured with a Tektronix 11401 scope. The power up and down square wave measurements were done using test circuit 1. VA was connected to an pulse generator. VB was grounded. Ron measured 7 4.969. Voltages were measured with a Tektronix 11401 scope. The power up and down triangle measurement was done using test circuit 1. VA was connected to an ac function generator, generating a triangle wave. VB was connected to a negative dc power supply. These were set to produce a triangle wave at VIN which has a maximum value of 0V, and a minimum value of -20V. RLOAD measured 74.969. Voltages were measured with a Tektronix 11401 scope. The quiescent current measurements were done using test circuit 2. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. VB was grounded. These were set to produce the necessary voltage at Vm. Rooms measured 100.069. Voltages were measured with a Tektronix 11401 scope. The voltage was measured across Rooms and divided by Rooms to give the quiescent current. The load transient response measurement was done with test circuit 3. VA was grounded. VB was connected to a negative power supply to produce a dc voltage of -20V at Vm. VP was pulsed to allow Q1 to function as a switch, connecting RLOAD on and off to ground to simulate the switching on and off of a load. The maximum output current vs Vm measurements were done using test circuit 1. V, was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. VB was grounded. These were set to produce the necessary voltage at Vm. R.LOAD measured 1.05309. Voltages were measured with a Tektronix 11401 scope. The voltage measured at R1010) was then converted to a current. The line transient response measurement was done with test circuit 1. VA was connected to a pulse generator. VB was connected to a negative dc power supply. These were set to produce a -20V dc voltage at V3,, with a square wave superimposed. Rm“, measured 74.969. Voltages and phases were measured with a Tektronix 11401 scope. CHAPTER 5 CA3085 MACROMODEL DEVELOPMENT 5.1 INTRODUCTION This chapter describes the development of the CA3085 voltage regulator macromodel. The CA3085 is a 10-pin, programmable, positive voltage regulator. 5.2 DEVELOPMENT The CA3085 functional block diagram is shown in Fig. (5.1). Fig. (5.2) shows the mun W©®mmm WM») mm! mm lumen? I g j X3 mm M 1.11... V mu: 4 van- 5 GDINV Batman v-0 0 m1 Ominous Figure 5.1 Functional block diagram for the CA3085 154 argum— Dating Figure 5.2 Macromodel for the CA3085 155 CL pn macromodel for the CA3085. The voltage reference amplifier source is replaced by D,, D2111 Du, D2, R3,, RM, RM, Rq, LR, and ER. The current source is replaced by GB, and G3,. The Frequency Compensated Error Amplifier is replaced by ED, Rm, DL, D,, D-, E,, V,, V_, and R0. The Series Pass Amplifier is replaced by RB, Qp,, Q92, and R5. The Current Limiting block is replaced by Q, E, and Rm. VLDR and Hum are added to provide load regulation characteristics. 1,, GT, V,, R,,, R”, and RI.3 provide circuitry which detects the change in ambient temperature from a nominal value. Finally, Dms provides capacitive discharge characteristics. This gives an overview of the macromodel. CB @363 OUT R39 (D —+ CA3085 CL fie + V“ © © @413 6) IN— + M V ‘2‘ R2 J_CUUT IN T.“ ""'" RLEAD _ CC R, __ .11.. Figure 5.3 Basic application circuit for the CA3085 The basic application circuit for the CA3085 is shown in Fig. (5.3). Under normal Operating conditions, V(6) == VREP, VREF being the internal voltage reference. This gives the output voltage as 156 157 R. your a V +— ~ 5.1 m[1 R,) ( ) 5.2.1 The Voltage Reference Amplifier Source The voltage reference amplifier source consists of D,, D211» DZR, D2, Rm, R32, R3,, Rq, LR, and ER. The diodes, resistors and inductors provide both ac and dc characteristics. ER is used to deliver the voltage generated by the reference to the rest of the circuit, acting as a buffer between the circuit and the reference generator. VREF vs INPUT VOLTAGE CA3085 2VREF (volts) 30 40 50 60 VIN (volts) temp = 25 degrees C Figure 5.4 DC characteristics of the reference voltage, measured Fig. (5.4) gives the dc characteristics of the voltage reference, and Fig. (5.5) gives the ac characteristics of the voltage reference. In Fig. (5.4), note the labeling of V13 The slope of the curve between V, and V2 will be called (AWE/AWN)” the slope of the curve between V2 and V3 will be called (AVREFIAVINL, and the slope of the curve 1111 not 1; ("me We ( ' ' 5 :1). J 158 vref (ac) vs Frequency CA3085 vreflvm 10005-03__ 1.000E-U4 r 10 100 1000 10000 100000100000m000000 Frequencylku) temp = 25 degrees celsrns Figure 5.5 AC characteristics of the voltage reference, measured to the right of V3 will be called (AVREFIAVm). The dc operation of the circuit works in the following manner. For 0 S V,N s V,: using Fig. (5.4) as a reference, the drop across the circuit is not large enough to turn on D, and overcome the breakdown voltage of Dar Thus, no current flows in the reference circuit and VREF = 0. For V, S Vm s V,: At V,N = V,, the diodes D, and D2,, begin to conduct and current begins to flow through the reference circuit, resulting in the reference beginning to turn on. The diodes D, and DZR still remain 05. Thus V,IVD,+BVw (5.2) Once the voltage drop across the reference is great enough to allow D, and D2,, to conduct, the s10pe (AVREFJAVm), results from the resistive voltage divider 101! the the com] Com) Sltpe 159 combination of RQ and Rm. Thus, Arm _ Rn [ J- , (5.3) AV," 1 Rodin For V2 5 VIN S V,,: The voltage V2 is approximately a diode drop greater than V,, which suggests another diode turning on. This is modeled at the voltage in which D2 turns on. The slope (AVREFIVWL is determined by the parallel combination of RR2 and RR, in series with R, and [3.211] =_£E|£”__, (5,4) AV... , RnIRn*Ro For V3 S V,,,: At V,, the breakdown voltage of D211 is reached. The reference has now achieved its nominal value. This is approximately 1.6V. V3211 is now the voltage drop across DZR and the small resistor Rm. The slope (AVREFIAVm) is due to the small signal voltage divider produced by rm, rDZB, Rq, 1‘qu: and R3,. In practice, the series combination of rDZR and R1,, is much smaller than RR, and the series combination of rm, and R3, so the equivalent resistance produced by these series combinations being in parallel is simply the series combination of rDZR and R3,. The slope (AVREFJAVm) can then be described by EVE = 'MiRH . (5.5) AV," 'nza‘Rn +Roi'rmtrm The slope (AVnp/Vm) represents the change in reference voltage which occurs with input voltage after the reference has achieved its nominal value. This has an efiect on the output voltage which can be deduced by observing Eqn. (5.1). These changes in reference voltage with input voltage contribute to low frequency ripple rejection and 160 line regulation, as with the SG78XX and the SG7915. As seen in Fig. (5.5), the voltage reference has so characteristics which are inductive. These characteristics are introduced in the model by the inductor L3. This adds a zero to the reference voltage, which adds a zero to the output voltage frequency response, and in turn gives the ripple rejection a pole. Finally, ER is added to provide a bufl'er between the voltage reference and the rest of the circuit so that any chance of the rest of the circuit effecting the voltage reference characteristics are minimized. 5.2.2 The Frequency Compensated Error Amplifier The frequency compensated error amplifier is modeled by ED, Rm D,, D,, D,, E,, V,, V,, and R0. ED is a voltage controlled voltage source which has as its controlling voltage the voltage across RN. This amplifies the voltage difl'erence between V,,“. and the Inverting Input terminal. In the actual chip, this is just a differential pair. The voltage controlled voltage source provides an adequate model for the amplifying action seen by the differential pair. Although the functional block diagram states that this is a frequency compensated error amplifier, there is no indication that the amplifier is actually compensated in the chip. Compensation for the amplifier is normally provided for by an external capacitor. In Fig (5.3), this capacitor is Cc. D,, D,, E” V,, V., and R0 provide maximum and minimum clamping for the amplifier. The controlled source, E,, has as its controlling voltage the voltage across nodes 3 and 0, with a gain of 1. This means the voltage across E, is simply V,,, The voltage at the terminal of the resistor R0 which is not connected to V,, has a maximum and minimum value, with the clamping circuitry added. The maximum value is (5.6) The minimum value is = V - VD-' (507) 5.2.3 Series Pass Amplifier The series pass amplifier consists of Qp,, Q92, R, and RB. This is identical to what is found in the real chip, with the exception of the addition of R,3 which provides some base resistance for Q92. 5.2.4 Ripple Rejection Modeling Ripple Reiectlon vs Frequency CA3085 -20log[voutlvm) (db) 50 1 10 100 1000 10000 100000 10000001000000 -+—temp = 25 RLOAD = 300 ohms Figure 5.6 Ripple rejection vs frequency, measured Fig. (5.6) gives the measured ripple rejection vs frequency response. This was measured as a one pole response. The low frequency ripple rejection can be derived from Eqn. (5.1). From Eqn. 52 :Erm“ may: 162 (5.1), AVM = AVm[l +5} (5.8) R1 From Eqn. (5.5), AV - R” AV (5.9) m Ru +RQ W ’ neglecting rpm, rpm, and rm. Inserting this into Eqn. (5.8) gives AV... R... R. = = +—— 50 mu, (”“1” 3.1%[1 R1)” ( 10) with some slight manipulation. The pole of the ripple rejection response can also be derived from Eqn. (5.1). The pole of ripple rejection is the zero of VREF. This is the zero formed by the inductor L1 and Rm, neglecting run, so R P1" = —. (5.11) 1., 5.2.5 Load Regulation Hum and Vum are added to provide load regulation efl‘ects. Hum is a current controlled voltage source which has the current through Vum as its controlling current. In the application circuit in Fig. (5.3), note that the voltage reference is not connected to the external circuitry. Because the amplifier is configured in a feedback system, the effective voltage between the controlling nodes, the voltage across R1”, of the high gain amplifier ED, is nearly zero. This gives the voltage at the Inverting Input terminal a voltage almost equal to V1139. The voltage at this terminal is used in the external circuitry as the 1.6V reference. Hum then provides the Inverting Input 163 terminal with a slight difference in voltage from that of VREP. Since Hum depends on the current through Vunv which consists mainly of the load current, the voltage across HLDR changes with load current. This means the voltage at the Inverting Input terminal changes, so Vow, in accordance with Eqn. (5.1), varies with load current. Changes in VOUT with load current are just a load regulation characteristics. Note that AVOW ROW .- - Ala”. (5.12) Using Eqn. (5.1), and the fact that variations in reference voltage with load current are given by Ayn, = 4",,“ , (5.13) gives Roar = kin-[l .21} (5.14) To include variations with temperature, the general PSpice description of the controlled source, I-ILDR, is HLDR+n -n poly(2)VwRVT0a10034000aa Since I“DR = 10,”. and it is shown in section 5.2.10 thath = AT, where AT = TEMP - TNOM, the current through Hum is equal to 5.15 I”, = (”(01+a4AT+a,A1"). ( ) Which allows the controlled source quadratic temperature sensitivity. This allows for a new definition for hum: and that is 164 hum A (a,+a4AT+a'A1Q). (5.16) At room temperature, R0 = a [I 4» fl) (5 l7) UT 1.“! & ° . 5.2.6. Quiescent Current Modeling Qurescent Current vs VIN CA3085 1 I I I U I I l ' y r I I l I r! T' ' ' V ' .------------------------------.----------------------------------‘ ........................................................................... ........................................................................................ 15 20 25 30 35 VIN (volts) _*"‘ temp = 25 Figure 5.7 Quiescent current vs input voltage, measured Fig. (5.7) shows the measured quiescent current vs input voltage Characteristics. The quiescent current characteristics are modeled by G31, G32, and Rq. GB, and G32 are voltage controlled current sources which have the voltage across RR3 as their controlling voltage. The voltage controlled current source GB, is Slightly different from G32. It is defined generically in the macromodel as 165 GBl n+ n- poly(2) V(12,4) V(10000) 0 a1 0 0 a4 0 0 0 as. The voltage V(12,4) is the voltage across Rm, still one of the controlling voltages, but another voltage, V( 10000), is introduced as one of the controlling voltages. V(10000) has a voltage which is equal to AT. Again, this will be explain in more detail in section 5.2.10. From the PSpice definition for a two variable polynomial, the current produced by GB] is 16,, = a,V(12,4)+a,V(12,4)AT+a,V(12,4)A1‘1. (5.18) or I“, = V(12,4)(al +a4AT+a,ATZ). (5.19) A new definition can be introduced for gm, and that is (5.20) 831 5a, +a4AT+a.ATQ. This allows GBl to show quadratic temperature effects, as the passive devices do, and allows it to remain off if VREF is zero. Gm is the main contributor to quiescent current, and provides much of the changes in quiescent current with temperature. For the room temperature model, AT = 0, and 16,, = a,V(12,4). (5.21) After the reference voltage has achieved its nominal value, the current through G31 and G82 no longer changes. Note that the voltage across Rm was selected as a controlling voltage because it best fit the characteristics in Fig. (5.7) to the second break point, or discontinuity in the plot. From 0V to this second break point, at approximately VIN = 8.5V, the 166 contribution to quiescent current is primarily G31 and G32. This point will be labeled VQ1 and 1m. At this point, the reference voltage has achieved its nominal value, and so Rm has achieved its maximum value, so the currents through GBl and GB2 are constant. However, at this point (8.1 +8.3) (BVM- V02) + (V01 " Bymkj'oym " 3V0”) = 101° (5.22) After this point, the changes in quiescent current with input voltage come from Rq. Since the voltage VREF and the voltage drops across D1 and D2"}; are constant, any change in the input voltage across the reference voltage structure is dropped across R9. This contributes to a change in current through R0» and hence a change in quiescent current in accordance with, AIQ = AYE, (5.23) no and = flan (5.24) A10 5.2.7 Short Circuit Current Limiting The short circuit current circuitry is DL, QL, R315 and EL. The short circuit current circuitry work in the following way. For short circuit current limiting the CA3085 requires an external resistor, RSC in Fig. (5.3), to be attached the OUT and CL pins. All of the load current and current which biases R1 and R2, pass though Rsc. E, has the following PSpice definition, 167 EL n+ n- POLY(1) V( 10000) a, a2, From the Pspice definition of a one variable polynomial and using the fact that V( 10000) = AT, the voltage across EL can be described by the relationship V,, = a,Ar+a,(Ar)2. (5.25) This gives the voltage source a quadratic variation with temperature, with‘a value of 0 and the nominal temperature (room temperature, usually). EL does not come into the design procedure until the section on temperature modeling, so more information will be given in another section. DL prevents the controlled source ED from supplying any current to the base of Q”. This means that G132 supplies all of the drive current to sz, which in turn supplies the drive current to Qpl, which supplies the load current. If QP2 shuts off, QPl shuts off and no load current can be supplied. As current flows out of the emitter of Qpl through REL and to the load, a voltage is generated across the base emitter junction of QL. If this voltage is large enough to turn QL on, most of the current supplied by G132 is drawn by the collector of QL, since its needs are large compared to the current needed by the base of sz and the maximum available current from G32. Q92 begins to shut off. A very small amount of current can be suppied to the base of sz in order to supply the current to produce the voltage across RCL. If the voltage across Rm, is not large enough, QL remains off and draws no current. The maximum output current is the current necessary to turn on QL. This gives VIE-0W. (5.26) Under the short circuit mode, because the base of sz draws a small amount 168 of current, the collector of QL draws most of the current available from Gm. This means that in Eqn. (5.26), Venomqr. can be estimated since the collector current of QL can be estimated as approximately the total current supplied from G32. which is gQ2(VREF - Vm). Using an approximation for the relationship between collector current and base emitter voltage and inserting into Eqn. (5.26) gives 832 (V33?- V02) I - V (INF V In . (5.27) urRsc war. 1' [ IS When using Eqn. (5.27), note that IMAX is the sum of the maximum available current supplied to the load, plus the current required to bias R1 and R2 under the maximum output current condition. Then, since IR, = Im, [m = 1210mm. ”narrow- (5'28) 5.2.8 Dropout Characteristics For the macromodel, dropout voltage is a function of IS, NF, BF, and VAF for the transistors QP1 and Q92. No closed form solution, or even an approximation exists for the determination of the relationship between these parameters and the dropout voltage. An empirical method was used with good results. Given that NF, VAF, and BF are set for Q?1 and Q92, vary IS for the transistors until the correct dropout voltage is attained. The method was done for Rm“, = 3000, and trends were matched nicely for difi'erent loads and different temperatures. 5.2.9 Power Up and Down, Square Wave and Triangle Wave The measured power up and down with square wave is shown is Fig. (5.8). This is primarily a function of an external output capacitor charging up to its needed 169 PU.CIR DatelTime run: 07I28192 23:20:33 Temperature: 27.0 20V 15V- 10V- 5V- Dv *7 f I fi' Us 10005 20009 30005 40009 50005 W“) Time Figure 5.8 Power up and down, square wave, measured 170 voltage. Although the output capacitor was not needed for stability for this regulator, it was used solely on the power up and down with square wave to provide modeling insight. This charging is limited since the capacitor has a finite amount of current available due to the limited amount of current available from the regulator, since RSC limits the output current. Dms is added to the model for capacitive discharge which can be noted in Fig. (5.8), upon powering down. The measured power up and down with triangle wave is shown in Fig. (5.9). The controllable response is the slight delay seen at the base of the triangle wave output. This is due to the fact that CC in Fig. (5.3) must charge up, but has a limited amount of current available to it which results in slewing. The maximum current it has available is approximately 1032. The parameter gm is set empirically based on this response. 5.2.10 Ambient Temperature Sensing Circuitry If, R“, R1", are used to generate a voltage at node 10000 which is equal to the change in ambient temperature from the nominal temperature , AT. The description of the circuitry is IT 0 10000 do 1 RTl 10000 10001 100.00001 TC=0.01 RT2 10001 0 ~100.00001 This means that the total resistance seen by Ir is Rn + Rm. 01‘ R = 100000010 +(r— mom.01)+1oo. (539) Simtrlifying (5.29) and setting T - TNOM = AT gives 171 PU.CIR DateITr'mo run: 07129I92 02:30:55 Temperature: 27.0 25V ZUV‘ 1SV~ 10V< 5V4 (N r . T Us 505 1005 1503 2009 WM) Trme Figure 5.9 Power up and down, triangle wave, measured 172 R - AT. (5.30) Since IT has a dc value of 1A, the voltage at node 10000 is equal to AT. Controlled sources can now use this voltage as one of the controlling voltages which not only provide temperature dependent controlled sources, but provide conceptually easy to understand temperature dependent controlled sources. It is of interest to know why the values of the resistors were set to 1009 and - 1009 instead of 19 and -10 and TC to 0.01 instead of 1, which provides the same result as (5.30), but in a much more straight forward manner. The description of the resistor with TCl specified is R = Rma +101 AT). (5.31) Although Pspice allows for R and RNOM to become negative, it does not allow for the quantity in brackets to become negative. This is a subtle point which must be taken into consideration when temperature work is being done. The circuitry above generates a voltage which is equal to AT. It is desirable, with current controlled dependent sources for instance, to have a current which is equal to AT as well. This is provided for by G], VT and Rm. GT is a voltage controlled current source with a gain of one which has as its dependent voltage the voltage at node 10000, which has a value of AT. This current then flows through VT and RN, and VT acts as the sensing device for temperature dependent controlled sources. 5.2.11 Other Modeled Characteristics The prior characteristics shown are used to determine the values of the components and parameters. Other characteristics are modeled as well, because of a correct choice of parameters, and these are: line transient response, load transient 173 response and line regulation. 5.3 DESIGN PROCEDURE FOR A CA3085 Based on the equations and procedures shown in the last section, a design procedure will be developed in this section. Fundamental to the design procedure is a list of measurements required to base the design on. The following measurements should be taken in the basic regulator circuit: 1) 2) 3) 4) 5) 6) 7) 8) 9) Measure VREF vs VIN. Measure IQ vs Vm- Measure VOUT for VIN = 25V, with no load. Measure ripple rejection vs frequency with RLOAD = 3000. Measure Rom with RLOAD = 30051. Select RSC = 5.2.0. Measure maximum output current at VIN = 25V. Measure dropout voltage with Rum) = 3009. Take a power up and down with square wave and triangle wave input with RLOAD = 30052. Measure RLOAD, the external resistors R,, R2, R50, COUT, and the compensation capacitor CC. These measured values get used in all of the equations. Measure as well the capacitances of all capacitors and the series resistance of all capacitors at some representative frequency. The component selection procedure is: 1) 2) Select ED and ER. Select the amplifier clamping circuitry, these are the values and 3) 4) 5) 6) 7) 8) 174 parameters for: V,, V,, E,, R0, and the diode parameters for D, and D_. Select the parameters for the diodes D1 and D2. Based on the VREF vs Vm measurement, determine the input voltage required to begin to turn the reference on, VON, then, from Eqn. (5.2), arm = V,,,- Var (5.32) Select NBVDZB. From the measured value of VOUT at VIN = 25V, and utilizing Eqn. (5.1), (5.33) $0.?“ Select NBVDZR. Measure the slope of IQ vs VIN for the quiescent current measurement. Then from Eqn. (5.24), = 35!. (5.34) A10 From the measured Vans vs VIN plots, and Eqn. (5.3), 1 R = —————— n (Avast) R0 (5.35) 1 AV”, From the measured V,,”. vs Vm plots, and Eqn. (5.4), 9) 10) 11) 12) 13) 14) 15) 175 ( 1 -1 )4 AV [A59 (5.36) 2,, = ‘” 2 -i ( R0 Rn) From the ripple rejection measurement, determine RR”. Then from Eqn. (5.10), -1 l 4» R2 (5.37) From the ripple rejection measurement, determine PIER, then from Eqn. (5.11), R Ln:— ‘" . (5.3s) pr, From the power up and down triangle wave measurement, empirically determine gm. From the quiescent current vs input voltage measurement, determine the value of the quiescent current at the point where a steady value is achieved call this VQ1 and IQ]. The total quiescent current is the sum of the currents from G31, G32, and Rq. Using this fact and Eqn. (5.22), I _ (v0, —BVM - V,,, - rig) 01 R0 (5.39) _ 8”. Select R315. Select RB. Select the parameters BF, VAF, and NF for QP2 and Q91. Let the 176 transistors be identical. Based on the dropout voltage measurement, empirically determine IS 16) for the transistors. 17 ) Select IS and BF for Q,. From the short circuit current measurement, find 1W. Then, from Eqn. (5.27) and Eqn. (5.28), Inuit“. NF“ 3 ' (5 40) ”111(8'1 (Vw- 52)) ' [Soc 18) Determrn' e Rom from the Load Regulation measurement or Load Transient Response, from Eqn. (5.14), :2... hm R . 1+—1 1 s) (5.41) 19) Select the parameters for the diode Dms. This concludes the design procedure. All of the parameters for the macromodel have been selected. 5.4 DESIGN PROCEDURE EXAMPLE In this section, a design example will be given. The following components were measured and used for the modeling". R, = 100.19, R2 = 818.989, CC measured 113.01pF and negligible series resistance at 100kHz, Com. measured .9602uF and had a series resistance of 1.0349 at 100kHz, RSC = 5.6029. and RLOAD = 300.6179. For the room temperature modeling, set V,,, = V02 = 0.6V- 1) Set ED = 10000 and ER = 1. 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 177 Set V, = -1V, V, = 1V. Set the gain of E+ = 1. Let the diodes be the Pspice default diodes. Set R0 = 59. This means that the maximum amplifier voltage is about (V ,N - AW and the minimum amplifier voltage is .4V, if the diode drops are taken to be 0.6V. Let the diodes D, and D2 be the Pspice default diodes. V0N = 2.5V then BV,,ZB = 1.9V. Set NBVDZB = 0.01. V0,], = 15.03V then BV,,ZR == 1.637V. Set NBVDZR = 0.01. From the measured lepe of IQ vs VIN for the quiescent current measurement, R, = 34034.659. From the measured VREF vs VIN plots, RR2 = 43316.839 From the measured VREF vs VIN plots, Rm = 15853.649 From the ripple rejection measurement, determine RR“. = 42.08db = 0.0079, then 3,, = 29.309212. From the ripple rejection measurement, P1,", = 23kHz, then LR = .2028mH. From the power up and down triangle wave measurement, g132 was set to 2m. From the quiescent current vs input voltage measurement, V,,, = 7.5V and Iq, = 3.106mA, then g3, = .8999m. set R815 = 1.5m. Set RB = 109. Set BF, VAF, and NF for sz and Q9, to be 50, 150V, and 1.25. Based on the dropout voltage measurement, IS for Q9, and Q92 was set to 1e-16A. 178 128.5mA, then NFQL = 1.0667. 18) From the load transient response measurement Rom- = -0.49, then hum = -0.0436. 19) Let the diode Dms be the Pspice default diode. This concludes the design of the room temperature macromodel. The parameters for the room temperature macromodel have been selected. 5.5 MODELING THE CA3085 AT -55 AND 125 DEGREES 5.5.1 Strategy in Modeling the CA3085 Temperature Variations From the room temperature model, steps which need modifications are steps 4, 5, 6, 9, 10, 12, 17, and 18. These will give rise to new values for BV,,ZB, BVDZR, Rq, R3,, and LR. Rm and RR3 will not be varied with temperature. This will also be used to find the coefficients of the polynomials which describe hum, EL, and gm. Since the controlled sources have the same format as the Pspice defined temperature coefficients, they are solved in a similar way. The strategy for the temperature dependent sources G3,, and Hum is to first solve for the first coefficient a,, which is g3,(TN OM), since AT = 0. Then let g3,(T) = (a, + a,AT + a,AT”), as in Eqn. (5.20). Writing out g3, (T) at ~55°C and 125°C gives two equations and 2 unknowns since a, will be known from the room temperature design. This solution will yield a4 and a,,. The coeficients of Hum are handled identically to this. EL only depends on the temperature and VEL(T) = a,AT + a,AT”. At temperatures other than the nominal temperatures Eqn. (5.27 ) becomes 179 V run” - Vm- V,, +1VF V, In [Ea—5E), (5.42) which allow the maximum output current to vary with temperature. Solving for V,,,(T) at -55°C and 125°C again yields two equations and two unknowns and this is easily solved for. 5.5.2 Design Example to Include Temperature Dependance In this section the parameters for the model for 55°C and 125°C are developed. The temperature coefficients are determined and then inserted into the room temperature model. CA3085. This will represent the fully developed, macromodel for the Following the example in Sec. (5.4) for -55 degrees: Let VD, = D2 = 0.45V. 4) 5) 6) 9) 10) 12) 17) 18) VON = 3.5V then BVDZB = 3.05V. From the measured slope of IQ vs VIN for the quiescent current measurement, RQ = 29858.859. From the ripple rejection measurement, determine RRLP = 47.63db = 0.00415, then R,,, = 13.5169. From the ripple rejection measurement, P1RR = 12kHz, then LR = . 1793mH. From the quiescent current vs input voltage measurement, VQ1 = 7 .5V and Iq, = 2.942mA, then g3, = .4014m. 1mm = 136.3mA and IMAX = 150.07mA, then I?L = .0861. From the load transient response measurement Rom. = -3.75639, then 19) 180 hum = 0.4091. Let all of the diodes in the model have the parameters EG = OeV and XTI = 0 set. Following the example in Sec. (5.4) for 125 degrees: Let V,,, = V,,, = 0.75v. 4) 5) 9) 9) 10) 12) 17) 18) V01,, = 1.5V then Bvoza = .75V. V0,”. = 15.112V then BV,JZR = 1.6459V. From the measured slope of IQ vs VIN for the quiescent current measurement, R, = 40923.719. From the ripple rejection measurement, determine RR“. = 52.81db = 0.002287, then RR, = 10.19369. From the ripple rejection measurement, P1,m = 6kI-Iz, then LR = .2704mH. From the quiescent current vs input voltage measurement, V,,, = 7V and Iq, = 2.738mA. Then g3, = .9510m. Immw = 82.717mA and IMAX = 91.7263mA, then EL = -.0165V. From the load transient response measurement, ROUT = .4834m9, then hLDR = .5268. A final summary of the temperature dependent parameters and elements follows in Table 5.1. 181 element or value at value at value at parameter 25 degrees -55 degrees 125 degrees BV,,ZB 1.9 3.05 0.75 BV,,ZR 1.637 1.6394 1.6459 RQ 34.03465k 29.858851: 40.9237 1k RR, 29.3092 13.516 10.1936 LR .2028m .17 93m .27 04m g8, .8999m .4014m .9510m Hum -0.0436 -.4091 .5268 EL 0 .0861 -.0165 Table 5.1 Temperature dependent components and parameters Solving for the linear and quadratic coefiicients for these parameters results in Table 5.2. element or 'I‘Cl or TBVl TC2 or TBV2 parameter (linear coefl'.) (quadratic coeff.) BV,,ZB -6.8933e-3 8.4064e-6 BV,,ZR 1.3982e-5 4.0386e-7 Rq 1.7 516e-3 2.7248e-06 Rm 8.4331e-4 -7.3654e-05 LR 2.2862e-3 1.0471e-05 gm 3.6889e-6 -3. 17 79e-08 hum 2.734e-3 -2.293e-05 EL -6.7125e-3 5.0625e-6 Table 5.2 Temperature coeflicients The macromodel for the CA3085 follows: 182 .SUBCKT 3085 1 2 3 4 5 6 7 8 * VOUT I I I I I I l * CB I I I I I I * VIN I I I I | * V- I I I I * VREF I I I * IN- I I * COMPI * CLIMIT a: * D1 3 9 DMOD DZB 10 9 DZB . .MODEL DZB D (BV=1.9 TBV1=-6.8933E-3 TBV2=8.4064E-6 NBV=.01 EG=0 XTI=0) RQ 10 11 34.034K TC=1.7516E-3,2.7249E-6 DZR 13 11 DZR .MODEL DZR D (BV: 1.6370 TBV1=1.3982E-5 TBV2=4.0386E-7 NBV=.01 EG=O XTI=0) LR 14 4 IND1 .2028M .MODEL IND1 IND (TCl=2.2862E-3 TCZ=1.0471E-5) RRl 13 14 29.3092 TC=8.4331E-4,-7.3654E-5 D2 11 12 DMOD .MODEL DMOD D (EG=0 XTI=0) RR2 11 4 43.316K RR3 12 4 15.853K ER 541141 RIN 5 15 1000000 HLDR 15 6 POLY (2) VLDR VT 0 -.0436 0 0 0.002734 0 0 0 -2.2930E-5 0132 3 7 12 4 2M DL 7 17 DL .MODEL DL D (N=0.1 EG=O XTI=O) ED 13 4 5 15 10000 681 3 5 POLY (2) (12,4) (100000) 0 .8999M 0 0 3.6889E-6 0 0 0 -3.1779E-8 RTl 10000 10001 100.00001 tc=0.01 RT2 10001 0 -100 IT 0 10000 DC 1 GT 0 30000 10000 0 1 VT 30000 30001 DC 0 RT3 30001 0 1 R0 17 13 5 E+ 16 4 9 4 1 D+ 17 160 DMOD V+ 160 16 DC -1 DC- 40 17 DMOD V- 40 4 DC 1 RB 7 20 1o QP2 3 20 21 QMODl QP1 2 21 22 QMODl 183 VLDR 22 1 DC 0 .MODEL QMODl NPN (BF=50 VAF=150 IS=1E-16 NF=1.25) R5 3 2 500 R315 200 1 1.5K QL 7 19 8 QLIMIT EL 19 200 POLY (1) (10000,0) 0 -6.7125E-4 5.0625E-6 .MODEL QLIMIT NPN (IS=1E-14 BF=100 NF=1.0666) DDIS 1 3 DDIS .MODEL DDIS D (EG=0 XTI=0) .ENDS 3085 184 5.5.3 Comparison of Macromodel Predictions with Lab Results A comparison of macromodel predictions with lab results are presented in this section. Ripple Rejection vs Frequency CA3085 0 -20Iog(voutlvrn) (db) 0 LI lllllll 1 L1 nun 1 I 1111111 L 1 LillllL l 1 1111111 1 J lllllll L 1 11111 1 10 100 1000 10000 100000 10000001000000 —°—temp : -55 -+—temp = 25 + temp =125 RLmD I 300 ohme Figure 5.10 Ripple rejection vs frequency, measured RR.CIR 00 temp p 125 deareee c 50‘ 40. . . .T temp -:25 decreed C . . 30. . . ..I . . ..temp 8.-Sa:deoreen 0.: 204 10« g. on 1011 101311 1 . 0101 101(1) 100K!) 1 . DMH 10M!) - . e-dtitZJIvc1J) Frequency Figure 5.11 Ripple rejection vs frequency, macromodel 185 PU.CIR DateITIme run: 07(28192 23:03:25 Temperature: 27.0 20V 15V- IUVn 5V- 0V Us 10005 200119 30005 40005 $0005 °VI1) Tlme Figure 5.12 Power up and down, square wave, T = -55, measured 15MB PU.CIR 1 25V‘ 2 20V 2 : = II II 20V- 15V< ISV~ 10V« 10V- 5V- 5V~ J >> : _ 0v 0v _, = _ 40005 50005 20005 10005 clV(1) IZI I”(2) Trme Figure 5.13 Power up and down, square wave, T = -55, macromodel 187 PU.CIR DatelTIme run: 07I28192 23:20:33 Temperature: 27.0 20V 15Vu 10V- 5V< 0V 05 10005 2000: 30005 40005 $0005 °VI1) Time Figure 5.14 Power up and down, square wave, T = 25, measured 188 PU.CIR 1 25V' 2 20V : : = II II 20V- 15V5 : 0 15V« l' 10V‘ . 10V« I 0 5V« SV' .0 i. j >> _ 0V 0V , , , :7 . :i 05 10005 20005 30005 40005 50005 aV(‘I) m eV(2) Tune Figure 5.15 Power up and down, square wave, T = 25, macromodel 18%) PU.CIR DateITime run: 07/29/92 02:11:59 Temperature: 27.0 15V 12V- 8V~ 4v. 0V Us 0.2ms 0.1ms 0.505 0.0ms 1.0ms 0V[1) Time Figure 5.16 Power up and down, square wave, T = 125, measured 190 PU.CIR 1 25V- 2 20V : : : II II 20V- ISVT :, , (I 15V~ l 10V< II IOV- . E SV« SV- '0 J >> UV 0V , , : . : 0 0.4015 0.6105 0.8015 1.0105 Time Figure 5.17 Power up and down, square wave, T = 125, macromodel 191. PU.CIR DateITime run: 07129192 02:30:55 Temperature: 27.0 25V ZUV1 15V~ 10V- 5V- UV T I I 05 505 1005 1509 2005 evm Time Figure 5.18 Power up and down, triangle wave, measured 25V 192 PU_TRI.CIR 20V~ 15V‘ 10Vn 5V5 0V 0 ' v s I"((2) W“) 505 1005 15.05 2005 Time Figure 5.19 Power up and down, triangle wave, macromodel 193 LTFi.CiR DatelTime run: 07120192 16:42:46 Temperature: 27.0 15.05V 15.50V- 15.00V- 14.55V , 1 t 09 505 1005 1505 2005 OVI‘i) Time Figure 5.20 Line transient response, measured 194 LTR.CIR 17v 15V~ 15v- 14v~ Us 505 10,05 15105 2005 0V(2) TII'I'Ie Figure 5.21 Line transient response, macromodel 195 LTR.CIR DatelTime run: 07(20192 22:37:10 Temperature: 27.0 16.0V~ 15.5V4 15.0v~ 11.5V« 05 205 405 505 005 1005 W“) Time Figure 5.22 Load transient response, measured 196 LDTR.CIR 15.5V 15.4V- 15.3V~ 15.2V- 15.1w - . - i 15.0V‘ 14.9V . .4 . . 105 605 805 1005 05 205 OV(2] Time Figure 5.23 Load transient response, macromodel 197 Qurescent Current vs ViN CA3085 10 (amps) -0.001. ' 0 5 10 15 20 25 30 35 VIN (volts) -'- temp = ~55 -*— temp = 25 + temp =125 Figure 5.24 Quiescent ctn'rent vs input voltage, measured WIES.CIR 5 OM : temp -:25 degrees c I I I 4,0”. ........... .\ .................... 3.0m- ' ...................... 2 0M ................................ temp - -ss:degree5 p 1 DmA- ................................. on. ................................... -1.0mA L J 4' i . . . 0v v 15v 20v 25v 30v 35v 40v SV 10 9 0 OHWIES) VDC Figure 5.25 Quiescent current vs input voltage, macromodel 198 "' var—Fe" - —- "-55.5. "533-5: . L...- Comparison of Macromodel parameters and Measured Parameters QUANTITY -55°C 25°C 125°C RR”, lab 47.63db 42.08db 52.81db model 47.29db 41.93db 52.20db P1RR lab 12kHz 23kHz 6kHz model 12.4kHz 23.3kHz 6.5kHz IQ lab 2.942mA 3.106mA 2.738mA model 2.987mA 3.172mA 2.810mA AIQ/AVin lab 33.49u 29.38u 24.44u model 34.42u 31.17 u 25.11u max load current lab 139.5mA 115.88mA 82.72mA model 132.5mA 121.88mA 92.31mA dropout voltage lab 6.28V 2.84V 2.46V model 3.13V 2.82V 2.44V AVOU'I/AILOAD lab -3.759 -.40919 .483m9 model -3.719 -.3889 0.01179 Table 5.3 Macromodel comparisons with lab data 199 5.7 TEST CIRCUITS 5.7.1 Pspice Test Circuits V" R :c« @(‘D DUT 3‘3 CD e CA3085 4Q + + (5) CL T + @® @ REF N... 'M' Cour R8 —- i VIN §RLUAD V001 CC R, Rcuur 1|: III—O ( i— 4.— Figure 5.26 Basic PSpice test circuit 200 RRCIR * *RIPPLE REJECTION FOR THE CA3085 * VDC 7 0 DC 25 VAC 1 7 AC 1 RSC 6 2 5.602 CC 3 4 113.01P 112 2 4 818.98 R1 4 0 100.1 RLOAD 2 0 300.617 *PIN NO*1*2*3*4*5*6*7*8***** XREG 611054323085 .OP .OPTIONS ITL5=0 ITL1=300 ITL2=300 NOPAGE .LIB CA3085.LIB .OP .TEMP -55 25 125 .OPTIONS TNOM=25 .AC DEC 20 10 1MEG .PROBE .END PU.CIR * *POWER UP WITH SQUARE WAVE FOR THE CA3085 * VPULSE 1 0 PULSE (0 25 50U 0 0 250U) RSC 6 2 5.602 CC 3 4 113.01P R2 2 4 818.98 R1 4 0 100.1 RLOAD 2 0 300.617 COUT 2 100 .9602U ROUT 100 O 1.034 *PIN NO*1*2*3*4*5*6*7*8***** EEG 611054323085 .OPTIONS ITL5=0 ITL1=300 ITL2=300 TN OM=25 .TRAN 1U 500U 0 1U .TEMP = -55 25 125 .LIB CA3085.LIB .PROBE .END 201 PU_TRI.CIR * *POWER UP, WITH TRIANGLE WAVE, FOR THE CA3085 * VPULSE 1 0 PULSE (0 25 2U 8U 8U .01U 16.1U) RSC 6 2 5.602 CC 3 4 113.01P R2 2 4 818.98 R1 4 0 100.1 RLOAD 2 0 300.617 *PIN NO*1*2*3*4*5*6*7*8***** XREG 611054323085 .OP .OPTIONS ITL5=0 ITL1=300 ITL2=300 TNOM=25 .TRAN .1U 20U 0 .1U .LIB CA3085.LIB .TEMP 25 .PROBE .END LTRCIR * *LIN E TRANSIENT RESPONSE FOR THE CA3085 * VDC 7 0 DC 25 VPULSE 100 7 PULSE (0 4 4U 0 0 10U) ROUT 100 1 0.1 RSC 6 2 5.602 CC 3 4 113.01P R2 2 4 818.98 R1 4 0 100.1 RLOAD 2 0 300.617 *PIN NO*1*2*3*4*5*6*7*8***** XREG 611054323085 .OP .OPTIONS ITL5=0 TNOM=25 .TEMP = 25 .TRAN .1U 20U 0 .1U .LIB CA3085.LIB .PROBE .END 202 LDTRCIR at: *LOAD TRANSIENT RESPONSE FOR THE CA3085 * VDC 1 0 DC 25 VPULSE 7 0 PULSE (14.98 0 2U 0 O 4U 10U) RSC 6 2 5.602 CC 3 4 113.01P R2 2 4 818.98 R1 4 0 100.1 RL 2 7 300.617 *PIN NO*1*2*3*4*5*6*7*8***** XREG 611054323085 .OP .OPTIONS ITL5=0 TNOM=25 .LIB CA3085.LIB .TRAN .1U 10U 0 .1U .TEMP -55 25 125 .PROBE .END QUIES.CIR * *QUIESCENT CURRENT FOR THE CA3085 * VDC 3 0 DC 40 ROPENl 1 0 1000MEG ROPENZ 2 O 1000MEG RQUIES 4 0 100.383 ROPEN3 5 O 1000MEG ROPEN4 8 0 1000MEG CC 7 O 113P *PIN N0*1*2*3*4*5*6*7*8***** XREG 123450783085 .OP .DC VDC 0 35 .25 .OPTIONS ITL5=0 ITL1=300 ITL2=300 TNOM=25 .LIB CA3085.LIB TEMP = -55 25 125 .PROBE .END 203 DROPOUT. CIR * *DROPOUT CHARS FOR THE CA3085 * VDC 100 0 DC 20 ROUT 100 1 0.1 RSC 6 2 0.00001 CC 3 4 113.01P R2 2 4 818.98 R1 4 0 100.1 RLOAD 2 0 300.617 *PIN NO*1*2*3*4*5*6*7*8***** XREG 61 1054323085 .OP .OPTIONS ITL5=0 ITL1=300 ITL2=300 TNOM=25 .TEMP -55 25 125 .DC VDC 0 30 .25 .LIB CA3085.LIB .PROBE .END 204 5.7.2 Measurement Test Circuits VA R, V+ - V ®© (Dun RSC 3 R2 CIA ‘ CA3085 CL A V+ ® © V- + O A'L'Ar A'L'A R R R3: 4 3 VIN E :JFCDUT g RLDAD _ { i J- J.- Figure 5.27 Test circuit No. 1 The conditions of Test circuit N o. 1 are stated. R, measured 100.19. R, measured 818.89. RsC measured 5.6029. RLOAD measured 300.6179. Cour measured .9602uF and had a series resistance of 1.034 at 100kHz CC measured 113.01pF at 100kHz and had a neglible series resistance. R1. R2, R3, R4, and Rs have nominal values of 1k9. V+ is a positive 50V dc power supply. V- is a negative 10V dc power supply. 0A is a Burr-Brown OPA541 Op-Amp. The CA3805 resides inside a temperature chamber. Wires are connected at the terminals of the CA3085 to allow it to be connected outside the chamber to the test circuit. 205 3 Figure 5.28 Test circuit No. 2 IllL The conditions of Test circuit No. 2 are stated. RQmES measured 100.3839. CC measured 113.01pF at 100kHz and had a neglible series resistance. R,, R2, R3, R4, and R5 have nominal values of 1k9. V+ is a positive 50V dc power supply. V- is a negative 10V dc power supply. GA is a Burr-Brown OPA541 Op-Amp. The CA3805 resides inside a temperature chamber. Wires are connected at the terminals of the CA3085 to allow it to be connected outside the chamber to the test circuit. 206 5.? Figure 5.29 Test circuit No. 3 The conditions of Test circuit No. 3 are stated. R, measured 100.19. R2 measured 818.89. RSC measured 5.6029. RLOAD measured 300.6179. Coo-1- measured .9602uF and had a series resistance of 1.034 at 100kHz. Cc measured 113.01pF at 100kHz and had a neglible series resistance. R,, R,, R,,, R,, and R,, have nominal values of 1k9. V+ is a positive 50V dc power supply. V- is a negative 10V dc power supply. OA is a Burr-Brown OPA541 OpAmp. The CA3805 resides inside a temperature chamber. Wires are connected at the terminals of the CA3085 to allow it to be connected outside the chamber to the test circuit. Q, is 3 2N4401 npn transistor. R,,, has a nominal value of mm. R32 has a nominal value of 1k9. 1) 2) 3) 4) 5) 6) 7) 8) 207 Ripple Rejection was done using test circuit 1. VA was connected to an ac function generator. VB was connected to a positive dc power supply. These were set to produce a 25V dc voltage at VIN with a sine wave superimposed for both. Coo-r was not connected. Voltages and phases were measured with a Tektronix 11401 scope. The VIN vs Vour for both chips, Von-r at VIN = 25V for the CA3085 was done using test circuit 1. V,, was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. V,, was grounded. These were set to produce the necessary voltage at V0,. COUT was not connected. Voltages were measured with a Tektronix 11401 scope. The power up and down square wave measurements were done using test circuit 1. VA was connected to an pulse generator. V,3 was grounded. Voltages were measured with a Tektronix 11401 scope. The power up and down triangle measurements was done using test circuit 1. VA was connected to an ac function generator, generating a triangle wave. V,, was connected to a positive dc power supply. These were set to produce a triangle wave at VIN which has a maximum value of 25V and a minimum value of 0V. Com. was not connected. Voltages were measured with a Tektronix 11401 scope. The quiescent current measurements were done using test circuit 2. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. V,3 was grounded. These were set to produce the necessary voltage at Vm. qu3 measured 100.3839. Voltages were measured with a Tektronix 11401 scope. The voltage was measured across qus and divided by Rooms to give the quiescent current. The load transient response measurements was done with test circuit 3. VA was grounded. V,, was connected to a positive power supply to produce a dc voltage of 25V at V,,,. VI) was pulsed to allow Q1 to function as a switch, connecting Rum, on and off to ground to simulate the switching on and ofi' of a load. The maximum output current vs V,,, measurements were done using test circuit 1. V,, was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. V,, was grounded. These were set to produce the necessary voltage at V0,. RLOAD measured 100.3839. Voltages were measured with a Tektronix 11401 scope. The voltage across R1010) was measured and then converted to a current. The line transient response measurements was done with test circuit 1. V,, was connected to a pulse generator. V,, was connected to a positive dc power supply. These were set to produce a 25V dc voltage at Vm with a pulse superimposed. Voltages were measured with a Tektronix 11401 scope. CHAPTER 6 UA7 23 MACROMODEL DEVELOPMENT 6.1 INTRODUCTION This chapter describes the development of the UA723 voltage regulator macromodel. The UA723 is a ten pin, programmable, positive, voltage regulator. 6.2 DEVELOPMENT OF THE UA723 MACROMODEL V+ CDMP (PFREQENCY COMPENSATION r—() \/C TEMPERATURE CDMPENSATED ZENER INV. ERRDR VREF _ AMPLIFIER SERIES PASS + TRANSISTOR N I I I VDUT A VDLTAGE REFERENCE 1 CL CS AMPLIFIER CURRENT V- LIMITER Figure 6.1 Functional block diagram for the UA723 The functional block of the UA723 is shown in Fig. (6.1). This gives the 208 209 starting point for the macromodel development. The macromodel for the UA723 is shown in Fig. (6.2). The voltage reference amplifier, the temperature compensated zener, and the associated biasing current source have been replaced by D2,, D210 R,,, RM, R,,,, ER, LR, CR, and Ron- These elements provide the necessary reference for pin 5, labeled VREP in Figures (6.1) and (6.2). The error amplifier is replaced by EA, R,,, R0, DL, D“ D_, V,, V,, and E,. The series pass transistor is replaced by two transistors, Q9, and Q92. These transistors and RE are configured exactly as they are in'the actual UA723 chip. Associated with the transistors are a slight base resistance, R,,, and R52, some frequency response adding by Cm, Caz, RC3, and R032. Q, and EL provide the current limiting, replacing the current limiter in the functional block diagram. VLDR is a dc voltage source set to zero to sense output current and is used in the load regulation, along with Hum. Gq, and qu provide the UA7 23 with quiescent current. Temperature sensing circuitry is provided for by 1,, R,,, and R,, as well as G,, R,,, and V0,. Finally, DDIS is provided to add the capacitive discharge characteristics. This provides the necessary overview of the UA7 23 macromodel. The UA723 needs to be configured in a circuit to provide regulation, as did the CA3085. The test circuit chosen comes from the data sheets and is shown in Fig. (6.3). This is termed the high voltage application for the UA723. In this circuit, V,,“, = R3,. so this circuit provides a regulated output voltage of you, = Vm(l+%} (6.1) 210 u mu" I . e s avg )Lbb m = v xx 411 ><>4D 6 ; RV m Boo AT— munm @ 00> «.28 a... Figure 6.2 Macromodel for the UA723 211 V+ VCC *VREF' VEIUT R3 UA723 N.I. Figure 6.3 Application circuit for the UA7 23 6.2.1 The Vm Pin The reference voltage generator for pin 4 consists of Dz,, D210 Rm, R,,, Rm, Rm, LR, CR, and RC“. The UA7 23 provides a reference voltage of approximately 7V. This 7V is provided for mainly by DZR operating in the breakdown region, but the reference voltage is the total dc voltage across DZR and R,,,. R,,, is selected so that it does not contribute much to the overall 7V, but does provide for enough voltage variation with input voltage so that it is the main contributor to low frequency ripple rejection and line regulation. This comes directly from Eqn. (6.1). E, provides a buffer for the actual generated voltage reference characteristics to the rest of the circuit. LR, CR, R,,“, R3,, and R,,2 provide the reference with frequency response characteristics. This contributes to the ripple rejection vs frequency and line transient 212 response. Under dc operation, these elements do not effect the circuit. RQ provides for changes in quiescent current with changes in input voltage. It is much larger than the differential resistance of the diodes and R,,, and it functions identically to R,, in the circuits developed prior to the UA7 23. Note in Fig. (6.4), the Von-:- vs V,N characteristics, there is an associated "on" voltage with the circuit. This effect is modeled by the diode D2,. This gives VOUT vs VIN UA723 2 VOUT (volts) 10 15 20 25 VIN (volts) + RLOAD = 150 ohms temp : 25 degrees celsrus Figure 6.4 VOUT vs VIN characteristics for the UA7 23 (6e2) 6.2.2 The Error Amplifier The error amplifier is modeled as a simple voltage controlled voltage source with a dc gain. The controlling voltage is the voltage across R,,", which represents some input 213 resistance for the amplifier. R,,, D,, D,, V,, V,, and E, provide for maximum and minimum clamping for the amplifier. 6.2.3 Ripple Rejection Modeling Fig. (6.5) gives an example of ripple rejection vs frequency for the UA723. It is the usual one pole response which means a one-zero transfer function. In modeling Ripple Reiectron vs Frequency UA723 -20|og[voutlvrn) (db) 80 0 l [1111]] l l [[111]] l l 1111]“ l 1111““ I 11111111 I l lllllll l l llllll 1 10 100 1000 10000 100000 10000001000000 Frequency (Hz) -'-rload - 150 +rload - 300 +rload - 3000 +110 load temp = 25 degrees celsrus Figure 6.5 Ripple rejection vs frequency, measured ripple rejection vs frequency, the following approximations are made. The first approximation is that the low frequency ripple rejection for all the loads are the same. The second approximation is that the first pole in ripple rejection is the same for all loads. As seen in Fig. (6.5), the approximations are fair. It should be pointed out that for the UA7 23 ripple rejection vs frequency was very dificult to measure. The above assumptions are made in part because they held true in the full chip simulations. Note that the "no load" ripple rejection in Fig. (6.5) will be used for modeling. The low frequency ripple rejection is due primarily to dc changes in the reference voltage. Dc 214 changes in reference voltage with input voltage are given by, with R2,, > rDZR, r + AV = AV m R” 6.3 m I”I'mmu "on *0} ( ) and with a few approximations, AVmsAVm[5”LR"J. (6.4) Low frequency ripple rejection can be determined from Eqn. (6.1) as R: M AVG,” "3"(“717 (6.5) “' AV," AV," ’ and substituting Eqn. (6.4) into (5) gives r +R R2 R I u 1.5—J. (6.6) " ( Re R. The first pole of the ripple rejection is due to first zero of the voltage reference. This is 1:1" . R_". (6.7) 11 if R,, and R,,2 are large in comparison to R,,, and OR is very small. The capacitor C,,, as well as Ron, and R,,2 also contribute to the frequency response, but their effects show up mainly in the line transient response. 6.2.4 Quiescent Current Modeling Quiescent current vs input voltage is shown in Fig. (6.6). The elements which contribute to quiescent current are R,,, G011 and G02 GQ2 is voltage controlled current 215 Quiescent Current vs VIN UA723 0 IO [IO-4 amps) 0 10 20 30 40 so VIN (volts) temp = 25 degrees C Figure 6.6 Quiescent current vs input voltage, measured source which senses the voltage across the reference voltage. This provides it with the characteristics seen in Fig. (6.6). The voltage controlled current is defined generically in the macromodel as Gq, n+ n- poly(2) V,,EF V(100000) 0 a, 0 0 a, 0 0 0 a,,. Vase is one of the controlling voltages and V( 10000) is equal to AT. This is identical to what is found with the CA3085 temperature sensing circuit, and AT is generated from an identical circuit. Gq, is identical to GB, for the CA3085, so 1601 = a,Vm+a4VmAT+a'V.”A1¢, (608) 01‘ 216 1001 = Vm(a,+a,AT+a.AT’). (6.9) The quantity in brackets is the new gm. Gq, is the main contributor to quiescent current, and provides much of the changes in quiescent current variations with temperature. Note that for the room temperature model, AT = 0 and 160, = gym. (6.10) After the reference voltage has achieved it’s nominal value, the current through GQ, and Gc,2 no longer changes. The changes in IQ with VIN are due to R,,, then, = fir, (6.11) A10 6.2.5 Output Impedance Modeling Output impedance vs frequency is not modeled, however output resistance is modeled. Hum and VLDR are added to provide output resistance effects. HLDR is a current controlled voltage source which has the current through V,,DR as its controlling current. This functions exactly like in the CA3085 development. As with the CA3085, "our, (6.12) Aim Using Eqn. (6.1), and the fact that variations in reference voltage with load current are given by AV” = _hmloar’ (6el3) gives 217 Row = hm[1 +%} (6.14) 1 The general PSpice description of the controlled source, HLDR, is HLDR «in -n poly (2) VLDR V, 0 a, 0 0 a, 0 0 0 a,,, for temperature variations. Since IVLDR = IOUT and IVT = AT, the current through HLDR is equal to lam = [Law (a, +a,AT+a,AT’). (6°15) which allows the controlled source quadratic temperature sensitivity. This allows for a new definition for hum, and that is hm e (a, +a,AT+a.AT2). (6-16) At room temperature, Av... R. = = 1 + _ , (6.17) A100,. Roar “1,171.04 R2) 6.2.6 Short Circuit Current Limiting The short circuit current circuitry is DB, Q, and EL. The short circuit current circuitry ftmctions identically to that of the CA3085. EL carries the same PSpice definition EL n+ n- POLY(1) V( 10000) a, a,, where V( 10000) = AT, and the voltage across EL the following value For short circuit current limiting the UA7 23 requires an external resistor, RSC 218 V,, = a,Ar+a,(Ar)2. (6-13) in Fig. (6.3) to be attached between 1 and 10, also in Fig. (6.3). All of the load current and current which biases R, and R, must pass though RSC. The maximum output current is V - - ”m“. (6.19) V330,,QL can be estimated as V run” - mer V, in [‘RI’T‘"). (6.20) 01. As with the CA3085, IMAX is the sum of the maximum load current and the current biasing the external resistors at this point. For the UA723, it is sumcient to neglect the biasing current. 6.2.7 Power Up and Down, Square Wave Fig. (6.7) gives the power up and power down for the square wave. The delay time in achieving regulation is due the slewing of the external compensation capacitor C0. The slewing occurs because the capacitor must charge to a set value, but does not have enough current available to it to produce the change either nearly "instantaneously" or anywhere near several time constants of CC. CC has available to it a maximum current which is determined by Ger It must charge to a voltage which is the difference between pins 9 and 2. From Fig. (6.7), W9) is approximately the Ontput voltage plus two diode drops. From Fig (6.9). V(2) is approximately the reference voltage V,,“. From the definition of slew rate 219 33.22% TEES-$2"1.932952%??? is; éSREAE‘YAT'SAIStzfi-i” i .. l 2 r i s i I I I I I I I 1 i‘— 949V I ‘!\ T‘: I Figure 6.7 Power up and down, square wave, measured W laps/div 79.2us 220 At = CclA—V. (6.21) m and inserting the proper values gives V0111" 1.4 - Van (6.22) At = C c 8(2er The time delay seen can be estimated by Eqn. (6.22). It is desirable to determine an approximate value for ng with this formula, but tweek ng to match both power up and down square wave and power up an down triangle wave. D015 is added for capacitive discharge behavior, and the default diode works well. 6.2.8 Power Up and Down, Triangle Wave Fig. (6.8) gives the measured power up and down with triangle wave. The main component of power up and down which is modeled, and controlled by the user, is the slewing seen in the transistion from 0V to 3V. This, as with power up and down square wave, is due to the slewing of CC. 6.2.9 Dropout Characteristics The dropout characteristics are contributed by primarily by Qp, and Q92. The dropout voltage is the difference between the input voltage and the output voltage when the regulator begins functioning as a linear device, and regulated voltage is produced. When the regulator is not functioning as a linear device, the amplifier is saturated. This means that the voltage at the cathode and anode of DL is clamped, positive. By choosing E+ to be equal to V(8,1) = VIN for this circuit, and by correct choice of V+, the voltage at the anode of DL can be set approximately equal to VIN during op-amp saturation. HI“, = ILOAD/BF, ICQP, = ImAD/BF and ICQP2 = 11.040» Wth 221 1112: 3391112356.9221Ltt§1355. Ifiitéahgnt‘903'3018tléa'3’ M 15V I 1 I I — 9.93.. :33-8#3 -4 __ lBus/div 67.2us Figure 6.8 Power up and down, triangle wave, measured 222 neglects the current which biases R, and R2, and Qp, and QP2 have equal BF, IS, and NF, then Irma 11.040 100.41) VDO = (R,, +11”) +NF VTln +NF Vrln —_ . (6.23) BF: IS BF IS The first term in Eqn. (6.23) can be neglected for small R,,, and R32, and Eqn. (6.23) can be simplified to 12 VDO . NFVTIn m . (634) IS’BF 6.2.10 Line Transient Response Line transient response is shown in Fig. (6.9). This is controlled primarily by the frequency dependent components in the voltage reference, especially CR, RCR, and R32. No closed form solution exists, so these components are chosen empirically to provide an adequate fit to the line transient response. 6.2.11 Ambient Temperature Sensing Circuitry IT. R,,, Rn are used to generate a voltage at node 10000 which is equal to the change in ambient temperature from the nominal temperature , AT. GT, VT and R,,. provide the means to sense a current which has the value AT. This is identical to the tamperature sensing circuitry inside the CA3085. 6.2.12 Other Modeled Characteristics The prior characteristics are used in determining component selection. As a result of correct choice of parameters and topology the macromodel predicts other responses. These are: line and load regulation, and load transient response. 223 Figure 6.9 Line transient response, measured 224 6.3 DESIGN PROCEDURE FOR A UA723 Based on the equations and procedures shown in the last section, and design procedure will be developed in this section. Basic to the design procedure is a list of measurements required to base the design on. The following measurements should be taken in the basic regulator circuit: 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) Measure Vom- vs V,N with no load. Measure IQ vs VIN with no load. Measure V0,,r for VIN = -15V, with no load. Measure ripple rejection vs frequency with no load. Take a load transient response measurement with a 1509 load, to determine the ratio of the change in output voltage for no load and load steady state conditions. This determines ROUT. Select RSC = 5.29. Measure maximum output current at VIN = 15V. Measure dropout voltage with RLOAD = 1509. Take a power up and down with both triangle wave input and square wave input with R,,,AD = 1509. Take a power up and down with both triangle wave input and square wave input with RLOAD = 1509. Measure RLOAD, the external resistors R,, R,, R3, and the compensation capacitor CC. These measured values get used in all of the equations. Measure as well the capacitances of all capacitors and the series resistance of all capacitors at some representative frequency. The component selection procedure is: 1) Select EA. 2) 3) 4) 5) 6) 7) 225 Select the amplifier clamping circuitry, these values are: V,, V,, E,, R0, and the diode parameters for D+ and D,. Based on the VOUT vs Vm measurement, determine the input voltage required to begin to turn the circuit on, VON, then BVM = V,,, (6.25) Select NBVDZ,. From the measured value of VOUT at VIN = 15V, and utilizing Eqn. (6.1), [ J R1 Select NBVDZR and Rm. Measure the 810pe of IQ vs VIN for the quiescent current measurement. Then from Eqn. (6.11), = 3’11. (6.27) Ala From the ripple rejection measurement, determine RR”. Then determine the small signal resistance of D211» rum. This is determined from a trial macromodel run with PSpice. Then from Eqn. (6.6), . new From the ripple rejection measurement, determine P1,“, then from Eqn. (6.7). 8) 9) 10) 11.) 12.) 13.) 226 1- ‘ R” (6.29 r'm- ) Based on the line transient response measurement, select CR, RC3, and RR2 empirically. From the power up and down square wave measurement, measuring the response time and from Eqn. (6.22), V +1.4 - V g” = cc 0‘” W. (6.30) At V,,, This will produce a close value. This value should then be iterated to produce a value based on both the power up and down triangle and square waves. From the quiescent current vs input voltage measurement, determine the value of the quiescent current at the point where a steady value is achieved. The total quiescent current is the sum of the currents from GQ1 and G02: using this fact and Eqn. (6.10), 6‘ I 3." (6.31) Vast Set C3, = CB2 and R,,, = R,,2 and determine values for both of them. Select R,,, and R32. From the load regulation measurement, determine the value of ROUT. Then, from Eqn. (6.17) 227 _ Roar hm“ (6.32) 3e 1+— 3, 14) From the short circuit current measurement, find IMAX. Select ISQL. Then, from Eqn. (6.19) Iersc N170, = 1411,,(M) (so: (6.33) 15.) Select IS and BF for Qp, and Q92. From the dropout voltage measurement and from Eqn. (6.23) m NF = . "m" ,2 (6.34) VT In Law 1820 16) Select the parameters for the diode Dms. This concludes the design procedure. All of the parameters for the macromodel have been selected. 6.4 DESIGN EXAMPLE FOR A UA7 23 The design example is based on laboratory measurements is presented. The data, unless otherwise specified, is taken directly off from the plots which were shown previously in the document. The nominal 1509 load resistor was measured at 150.949. R, was measured at 2.41849, R, at 5.7375k9 and R,, at 16169. The compensation capacitor had a measured value of 153.98pF and a negligible series resistance. Finally RSC was 228 measured at 5.20629. 1) Set E, = 600. 2) Let the diodes D+ and D_ be the Pspice default diodes. Set V+ = -1.6V, 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) V' = IV. Set the gain of E, = 1 and let V(8,1) be the controlling voltage. If the diode voltage drops are approximated at 0.8V, the maximum voltage at node 17, for node 5 grounded, is approximately V,,,. The minimum voltage for the amplifier is 0.2V. Based on the vow vs VIN measurement, set BVDZ, = 1V. Set NBVDZ, = 0.001. From the measured value of VOUT at VIN = 15V, set BVDZR = 6.904V. Set NBVDZR = 0.001 and RZR = 1MEG9. From the IQ vs VIN measurement, R,, = 237.273k9. From the ripple rejection measurement, RR“. = 63.694db = 0.6536m. run, was determined to be 8.99, as was rpm. This gives R,, = 100.19369. P1,“, was determined to be 14kHz, then Ln = 1.1390mH. Based on the line transient response measurements, the following components were selected: R0, = 109, R,,2 = 150009, and CR = 3pF. Base on the power up and down square wave measurement, At as 4.4us. This gave a value of 0.0224m for ng, however the value 0.08m worked much better for the power up and down responses. IQ was measured at 2.5244mA, then a, = 0.28325m. Set CB, = CI32 = lpF. Set R,,c, = R,,C2 = 109. Set R,,, = 109 and R,,, = 109. From the load regulation measurements, Rom. = 50m9. Then hLDR = 229 35.2m. 14) IMAX at 15V was determined to be 258.3mA. Set ISQL = 1e-20A. Then NFQL = 1.3466. 15) Set 13021,qu = 1e-20. Set BFQP1,QP2 = 50. VDC = 2.08V, then N091, 022 = 1.0188. 16) Let the diode DDIS be the Pspice default diode. 17) Set R,N = 100k9. This concludes the design example. All of the parameters for the macromodel have been selected. 6.5 MODELING THE UA723 AT -55 AND 125 DEGREES 6.5.1 Strategy in Modeling the UA723 Temperature Variations The room temperature model is developed first. The steps which need modifications are steps 3, 4, 5, 6, 7, 10, 11, 13, and 14. These will give rise to new values for BV,)“, BVDZR, R,,, R3,, and L,,. This will also be used to find the coeflicients of the polynomials which describe hum, EL, and gm. For further ease, the parameters XTI = 0 and EG = OeV have been set for QL. This makes the value of IS for QL relatively constant over the temperature range of interest. To solve for the value of EL, Eqn. (6.20) is modified for temperatures other than the nominal temperature as 801 Van [rm-Rx + ya 3 NF yr In (73;). (6.35) 6.5.2 Design Example to Include Temperature Dependance In this section the parameters for the model for -55°C and 125°C are developed. 230 The temperature coefficients are determined and then inserted into the room temperature model. This will represent the fully developed, macromodel for the UA723. Following the example in section 4 for -55 degrees: 3) 4) 5) 6) 7) 10) 13) 14) Based on the VOUT vs VIN measurement, set BVZ, = 1V. From the measured value of VOUT at VIN = 9.823V, set BVZR = 6.9103V. From the IQ vs VIN measurement, R,, = 196.569k9. From the ripple rejection measurement, RR”. = 68.7 967db = 0.3632m. rDZR was determined to be 5.249. This gives R,, = 44.98409. P1,“, was determined to be 14khz, then LR = .5507mH. IQ was measured at 2.6283mA, then gq,(-55°C) = 0.3003m. From the load regulation measurements, Rom = 137.6m9. Then hLDR = 0.0968. Im at 15V was determined to be 152.4mA. Solving Eqn. (6.35) for EL yields EL(-55°C) = -.1825V. Following the example in section 4 for 125 degrees: 3) 4) 5) 6) 7) 10) 13) Based on the VOUT vs Vm, set BV,,Z, = 1V. From the measured value of VOUT at V,N = 9.92V, set BV,,ZR = 6.97 85V. From the IQ vs VIN measurement, RQ = 318.543k9. From the ripple rejection measurement, RR”. = 62.11db = 0.7843m. rDZR was determined to be 15.79. This gives R,, = 160.05339 P1,“, was determined to be 11kHz, then LR = 2.3158mH. IQ was measured at 2.3625mA, then gq,(125°C) = 0.2585m. From the load regulation measurements, Rom = 171.9m9. Then hLDR 14) = 0.1209. 231 ISC at 15V was determined to be 169mA. Solving Eqn. (6.35) for EL yields EL(125°C) = -.9012V. A final summary of the temperature dependent parameters and elements follows. element or value at value at value at parameter 25 degrees -55 degrees 125 degrees BVDZ, 1 1 1 BV,,ZR 6.9504 6.9103 6.9785 R, 237.273k 196.569k 318.543k Rm 100.1936 44.9840 160.0533 LR 1.1390m .5507m 2.3158m gQ, .2832m .3003m .2585m hum 35.2m 0.0968 .1209 L 0 -.1825 -.9012 Table 6.1 Temperature dependent components and parameters Solving for the linear and quadratic coefficients for each of these components and parameters to the following results for Table 6.2 232 merit or T0] or TBVl TC2 or TBV2 parameter (linear coefi'.) (quadratic coefi‘.) BVDZ, 0 0 BV,,ZR 5.8034e-05 -1.7605e-07 R,, 2.7 132e—03 6.8655e-06 R,,, 6.4819e-03 -5.0748e-06 LR 8.1788e-03 2.1531e—05 gQ, -2.2853e-07 -1.8472e-10 hLDR -4.6889e-05 9.0389e-06 EL -2.7380e-3 -6.2740e-5 Table 6.2 Temperature coeflicients The final macromodel is shown in follows. The macromodel includes the effects of temperature. .SUBCKT UA723 1 2 3 4 5 6 7 8 9 10 * I I l l I I I I l l * CS I I l I I l I | | * IN- I I I | | | I I * IN- I l I I I l I * VREF I l I I I l * V- | I I I I * VOUT I I l I * VC I I | * V+ I I * FC I * CL *- DZ1 13 8 DZ1 .MODEL DZ1 D (BV=1 NBV=0.001) RQ 40 13 237.273K TC=2.7132E-3, 6.8655E-6 DZR 11 40 DZR .MODEL DZR D (BV=6.9504 TBV1=5.8034E-5 TBV2=-l.7605E-7 NBV=0.01 CJO=1P) RZR 11 40 1MEG RRl 11 500 100.1936 TC=6.4819E-3,-5.0748E-6 LR 500 5 LR 1.1390M .MODEL LR IND (TC1=8.1788E-3 TC2=2.1531E-5) 233 332 500 5 15000 CR 11 1000 3P RCR 1000 5 10 001 8 4 POLY (2) (4,5) (100000) 0 .2832M 0 0 -2.2853E-7 0 0 0 -1.8472E-1O ER 4 5 40 5 1 RIN 2 3000 100K HLDR 3 3000 POLY (2) VLDR VT 0 35.2M 0 0 -4.6889E-5 0 0 0 9.03892E-6 002 8 17 4 5 .08M DB 17 19 DB .MODEL DB D R0 19 14 500 EA 14 5 3000 2 600 D- 22 19 DC V- 22 5 DC 1 E+ 23 5 8 5 1 D+ 19 20 DC V+ 20 23 DC -1.6 .MODEL DC D RT1 10000 10001 100.00001 TC=0.01 RT2 10001 0 -100 IT 0 10000 DC 1 0T 0 30000 10000 0 1 VT 30000 30001 DC 0 RT3 30001 0 1 331 17 9 10 332 9 21 10 QPl 8 21 16 QPASSl QP2 7 16 15 QPASSZ .MODEL QPASSl NPN (BF=50 VAF=5O NF=1.0188 IS: 1320) .MODEL QPAssz NPN (BF=50 VAF=50 NF=1.0188 IS=1E-20) 0301 21 800 1P RCBCl 800 8 10 0302 7 160 IF 30302 160 16 10 VLDR 15 6 DC 0 QL 9 125 1 QLIMIT .MODEL QLIMIT NPN (IS: 1E-20 EG=0 XTI=0 NF=1.3466) ESC 10 125 POLY (1) (100000) 0 -0.002738 -6.274E-5 DDISl 15 8 DDIS .MODEL DDIS D .ENDs UA723 234 6.5.3 Comparison of Macromodel Predictions with Lab Results A comparison of macromodel predictions with lab results are presented in this section. Ripple Rejection vs Fre UA723 -20loa(voutlv1n) (db) quency 80 U 1 I IIIIIII I I IIIIIII I I IIIIIII I I IIIIIII I I IIIIIII I I I IIIIII I I IIIIII 1 10 100 1000 10000 100000 10000001000000 Frequency [HZ) temp - -55 —t— temp - 25 + temp = 125 noloed Figure 6.10 Ripple rejection vs frequency, measured RR.CIR BO 1., _ temp I -33 degrees C 50- f F. f ‘- temp I 25 deareee C I temp - 125 deoreee C 40- 20- t1.011 15R, 10'011 1.131(1) 101:1: 1001(1) 1.01111 10M!) a . e -db( (231vr11) Frequency Figure 6.11 Ripple rejection vs frequency, macromodel 15V 1.5V "div .1113 . 259(112)5°.1221Ltt§3155. M i I I 1 trtg’d 235 :2 £35332‘103'3018IX63'3’ . I I-AA‘A‘M‘A‘AAAA v-rw tans/010 79.2g5 Figure 6.12 Power up and down, square wave, measured 236 PU.CIR 15V 3 c c 1 1) 4) 10V"" -°:'°':' : 1) 1 SV" ' ' I 0 II II 0 DV 3 r 1 J— 1 ¢ 08 2005 4005 6005 0005 10000 ev(2] .v(1) Time Figure 6.13 Power up and down, square wave, macromodel 237 5:22: 359525255°t922zL5955965~ ':€:35252‘Y63'3618r143'3’ M , ‘ Figure 6.14 Power up and down, triangle wave, measured 238 PU_TR I .0”? 15V 10v- 5v~ UV'JH I l l I 05 2005 4005 6005 0005 10005 oV(‘|] 0V(2) Time Figure 6.15 Power up and down, triangle wave, macromodel SE39 11501 GITIZ date: ;1—wqr-éget?§5iLig§§8?§o i::€:35959‘963-3618YZ63-3’ 169mV "\W ‘ ‘ " i ‘1, .fi ‘ ~ -—/9y i Li I Z A; ' 1 ; T“ V’ ‘W 35mV§ ”div. Mn" - q «>th f fbM¢W‘ . ‘ T inn-A, i fllnv § ”flow .r ' ' l'. puny I i ? ......... ’IBImV ‘ i -4.16us Ens/div 15.3§E§ Figure 6.16 Line transient response, measured 240 LTR.C|R 10.1V 10.0V- 9.9V‘ ' ' u 1 9.8V- 9.7V 05 505 1005 1505 2005 nV(2) Tlme Figure 6.17 Line transient response, macromodel 241 11‘001 T 5.... BEAJQE‘GSSEF’ISSEB?w : in i:;¥:Ea§a€‘?6i'36181163-3’ I'U .3V: Bflflmv dlU A 1 e— d ‘ : 13y “I NEW R— :35C3'O-165’Ah - . -:..¢ 24" fluid 4' ' ' i I: .....- .. I K..- I i ‘- my I . Y i 0“ -4.16us Bus/div 15.84ns Figure 6.18 Load transient response, measured 242 LDTR.C|R 10.1V 10.DV~ 9.9V~ 9.8V‘ 9.7Vq 9.5V f 1 1 505 1005 1505 2005 05 ”(2) Tlme Figure 6.19 Load transient response, macromodel 243 Qwescent Current vs VIN UA723 0 IO (to-4 amps) 0 10 20 30 40 50 VIN [volts) -*- temp = ~55 —*— temp = 25 + temp =125 Figure 6.20 Quiescent current vs input voltage, measured IG.CIR 3.0m ov 16v 26v 36v 46v sov o o AICRQJIES) VIN Figure 6.21 Quiescent current vs input voltage, macromodel 244 Comparison of Macromodel parameters and Measured Parameters QUANTITY -55°C 25°C 125°C RR”. lab 68.767db 63.694db 62.110db model 68.744db 63.687db 62.069db P1RR lab 14kHz 14kHz 11kHz model 13.55kHz 14.16kHz 11.38kz IQ lab 2.628mA 2.524mA 2.363mA model 2.628mA 2.526mA 2.360mA AIQ/AVin lab 5.087u 4.215u 3.139u model 5.195u 4.381u 3.331u max load current lab 152.4mA 252.9mA 169mA model 157.8mA 258.3mA 154.3mA dropout voltage lab 2.68V 2.08V 2.36V model 2.20V 2.37V 2.56V AVOU.,./AILOAD lab .1389 .050 .172mQ model .1469 .0590 .182!) Table 6.3 Macromodel comparisons with lab data 245 6.6 TEST CIRCUITS 6.6.1 Basic Pspice Test Circuits a} L V+ VCC VIN VREF VDUT 2 ' UA723 R3 R50 CL 0 + ‘N I CS INV R, v am V- CDMP RLOAD R _ _____JEC '8 2 Figure 6.22 Basic pspice test circuit RR.CIR a: *RIPPLE REJECTION CHARACTERISTICS FOR THE UA723, HIGH VOLTAGE *APPLICATION VIN 8 0 DC 15 VAC 1 8 AC 1 R1 2 3 2.4184K R2 3 O 5.7375K R3 4 5 1616 CC 6 3 153.98P *pins 12345678910 XREG 2354021162UA723 .OPTIONS ITL1=300 ITL2=300 TNOM=25 .TEMP -55 25 125 DP .LIB UA723.LIB .PROBE .AC DEC 20 10 1MEG .END PU.CIR * 246 *POWER UP, SQUARE WAVE, FOR THE UA7 23, HIGH VOLTAGE APPLICATION * VP 1 0 PULSE (O 15 20U O 0 50U) R1 2 3 2.4184K R2 3 O 5.7375K R3 4 5 1616 CC 6 3 153.98P RLOAD 2 0 150.94 *pins 12345678910 XREG 2354021162UA723 .OPTIONS ITL1=300 ITL2=300 TNOM = 25 .OP .TEMP 25 .LIB UA723.LIB .PROBE .TRAN .1U 100U 0 .1U .END LTR.CIR * *LINE TRANSIENT RESPONSE FOR THE UA723, HIGH VOLTAGE APPLICATION * VIN 8 0 DC 15 VP 18PUISE(O44U0010U) R1 2 3 2.4184K R2 3 O 5.7375K R3 4 5 1616 CC 6 3 153.98? RLOAD 2 0 150.94 *pin 12345678910 XREG 2354021162UA723 .OPTIONS ITL1=300 ITL2=300 TNOM=25 .OP .TEMP 25 .LIB UA723.LIB .PROBE .TRAN .1U 20U 0 .1U .END 247 LDTR. CIR * *LOAD TRANSIENT RESPONSE FOR THE UA723, HIGH VOLTAGE APPLICATION * VIN 1 0 DC 15 R1 2 3 2.4184K R2 3 0 5.7375K R3 4 5 1616 CC 6 3 153.98P RLOAD 2 10 150.94 VP 10 0 PULSE (9.9 0 4U O 0 10U) *pin 12345678910 XREG 2354021162UA723 .OPTIONS ITL1=300 ITL2=300 TNOM=25 .OP .LIB UA723.LIB .TEMP = 25 .PROBE .TRAN .1U 20U O .1U .END IQ.CIR a: *QUIESCENT CURRENT CHARACTERISTICS FOR THE UA723, HIGH VOLTAGE APPLICATION it VIN 1 0 DC 15 R1 2 3 2.4184K R2 3 0 5.7375K R3 4 5 1616 CC 6 3 153.98? RQUIES 7 0 100.072 *pin 12345678910 XREG 2354721162UA723 .OPTIONS ITL1=300 ITL2=300 TNOM=25 .TEMP -55 25 125 .OP .LIB UA723.LIB .PROBE .DC VIN O 40 0.25 .END 248 DROPOUT.CIR a: *DROPOUT CHARACTERISTICS FOR THE UA723, HIGH VOLTAGE APPLICATION * VIN 1 0 DC 15 R1 2 3 2.4184K R2 3 O 5.7375K R3 4 5 1616 CC 6 3 153.98P RLOAD 2 0 150.94 *pins 12345678910 XREG 2354021162UA723 .OPTIONS ITL1=300 ITL2=300 TNOM=25 .TEMP -55 25 125 .OP .LIB UA723.LIB .PROBE .DC VIN 0 20 0.1 .END CL.CIR * *CURRENT LIMITING CHARACTERISTICS FOR THE UA7 23, HIGH VOLTAGE APPLICATION * VIN 1 0 DC 15 R1 2 3 2.4184K R2 3 O 5.7375K R3 4 5 1616 CC 6 3 153.98P RSC 8 2 5.2062 RLOAD 2 0 5.5762 *pin 12345678910 XREG 23540 81168UA723 .OPTIONS ITL1=300 ITL2=300 TNOM=25 .OP .LIB UA723.LIB .PROBE .TEMP -55 25 125 .DC VIN O 40 0.25 .END 249 6.6.2 Measurement Test Circuits 8 . j. “ V+ vcc VV 1» R V R3 " i 5 1" VREF vn UT .1_L 3 R3 UA723 Rm - CL A'A'A' A ‘0 4. ML cs b INV R, VtIIJT v- chP J Rm _ R _ .__7Ec a 2 Figure 5.23 Test circuit No. 1 The conditions of test circuit No. l are stated. R1 measured 2.4184kfl. R.z measured 5.7375162. R3 measured 1.616kfl RSC measured 5.206252. RLOAD measured 150.940. CC measured 153.98pF at 100kHz and had a negligible series resistance. R,, R,, R,, R,, and R5 have nominal values of 1k9. V+ is a positive 50V dc power supply. V- is a negative 10V dc power supply. OA is a Burr-Brown OPA541 Op-Amp. The UA723 resides inside a temperature chamber. Wires are connected at the terminals of the UA723 to allow it to be connected outside the chamber to the test circuit. 250 '— V+ VCC R2 EL 5 j /l: + ‘p R V Rafi " 5 I" VREF vnur _ ‘t g :33 UA783 Rsc - CL ‘v‘v‘v {J + NJ. 9 INV 1:12, V,,,JT V- CDMP ‘L ::R I b a ' Rm... 6° i 2 Figure 6.24 Test circuit No. 2 The conditions of test circuit N o. 2 are stated. R, measured 2.4184kfl. R2 measured 5.7375kQ. R, measured 1.616kfl RSC measured 5.20620. Rooms measured 100.0729. CC measured 153.98pF at 100kHz and had a negligible series resistance. R,, R,, R,, R,, and R5 have nominal values of 1kfl. V+ is a positive 50V dc power supply. V- is a negative 10V dc power supply. OA is a Burr-Brown OPA541 Op-Amp. The UA7 23 resides inside a temperature chamber. Wires are connected at the terminals of the UA723 to allow it to be connected outside the chamber to the test circuit. 251 Re DA F ... V- V+ VCC AA AAA ‘p Re 1* VREF VUUT UA723 Ill-O I AAA '7 Z) 0 NJ. CS Figure 6.25 Test circuit No. 3 The conditions of test circuit N o. 3 are stated. R, measured 2.4184162. R, measured 5.7375k9. R3 measured 1.616kfl RSC measured 5.2062Q. RLOAD measured 150.949. CC measured 150.94pF at 100kHz and had a negligible series resistance. R,, R2, R,, R,, and R5 have nominal values of 11:9. V+ is a positive 50V dc power supply. V- is a negative 10V dc power supply. 0A is a Burr-Brown OPA541 Op-Amp. The UA7 23 resides inside a temperature chamber. Wires are connected at the terminals of the UA7 23 to allow it to be connected outside the chamber to the test circuit. Q, is a 2N4401 npn transistor. R,,, has a nominal value of 10m. R32 has a nominal value of 1k9.. 1) 2) 3) 4) 5) 6) 7) 8) 252 Ripple Rejection was done using test circuit 1. VA was connected to an ac function generator. V,, was connected to a positive dc power supply. These were set to produce a 15V dc voltage at VIN with a sine wave superimposed for both. Voltages and phases were measured with a Tektronix 11401 scope. The V,,, vs VOUT and VOUT at VIN = 15V for the UA723 was done using test circuit 1. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. VB was grounded. These were set to produce the necessary voltage at VIN. Voltages were measured with a Tektronix 11401 scope. The power up and down square wave measurements were done using test circuit 1. VA was connected to an pulse generator. VB was grounded. Voltages were measured with a Tektronix 11401 scope. The power up and down triangle measurements was done using test circuit 1. VA was connected to an ac function generator, generating a triangle wave. VB was connected to a positive dc power supply. These were set to produce a triangle wave at VIN which has a maximum value of 15V and a minimum value of 0V. Voltages were measured with a Tektronix 11401 scope. The quiescent current measurements were done using test circuit 2. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. VB was grounded. These were set to produce the necessary voltage at Vm. Rooms measured 100.0720. Voltages were measured with a Tektronix 11401 scope. The voltage was measured across Rooms and divided by Rooms to give the quiescent current. The load transient response measurements was done with test circuit 3. VA was grounded. VB was connected to a positive power supply to produce a dc voltage of 15V at Vm- VI. was pulsed to allow Q1 to function as a switch, connecting Rm“, on and off to ground to simulate the switching on and ofl' of a load. The maximum output current vs VIN measurements were done using test circuit 1. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. VB was grounded. These were set to produce the necessary voltage at V,,,. Rum: measured 5.20. Voltages were measured with a Tektronix 11401 scope. The voltage was measured at RLOAD was then converted to a current. The line transient response measurements was done with test circuit 1. VA was connected to a pulse generator. VB was connected to a positive dc power supply. These were set to produce a 15 volt dc voltage at VIN with a pulse superimposed. Voltages were measured with a Tektronix 11401 scope. CHAPTER 7 SG137 MACROMODEL DEVELOPMENT 7.1 INTRODUCTION This chapter describes the development of the SG137 voltage regulator macromodel. The SG137 is a three terminal, adjustable, negative, voltage regulator. 7.2 DEVELOPMENT OF THE SG137 MACROMODEL The functional block diagram for the SG137 macromodel is shown in Fig. (7.1). The macromodel for the SG137 is shown in Fig. (7.2). The voltage reference is been replaced by Dzn» R23, D2,, R,,, L,, CR, and Rex. The bias current source is been replaced by R,,. The error amplifier is replaced by E,, E2, Rom, CP, R,,, Rm: D“ D_, V,, V,, and E,. The pass transistors are replaced by QP and some base resistance is provided for by RB, and R32. Some additional circuitry has been added to the SG137 functional block diagram. Fq, Em, Vm, and R,,, provide for quiescent current characteristics. RDO, Em“, and D902 provide dropout characteristics for the SG137. DL, EL, DFB, and EPB provide the model with short circuit current and foldback current limiting. DDIS provides for capacitive load discharge through the device. Finally, Ro provides for output resistance. This gives an overview of the macromodel. Finally, the SG137 needs external resistors to provide for the variable output voltage. The basic application circuit for the SG137 is shown in Fig. (7.3). The 253 254 ADJ —'1 as ‘n Y 4 O VDUT at},1 ' 17 iv IBIAS + O VIN Figure 7.1 Functional block diagram for the SG137 regulated output voltage is then R, V,,”, = V,,, [1 1’ (7.1) assuming the current out of the third terminal is 0A. 7.2.1 The Voltage Reference The reference voltage generator consists of Dzm RZR D2,, R,,, R,,, LR, CR, and RC“. When a suficient voltage is applied across pins 1 and 3, the diode DZR operates in the breakdown region. When set with a breakdown voltage of 1.25V, this provides the macromodel with the basic 1.25V reference which is seen in the actual chip. RR and R,, help to provide some dc changes for VREF with changes in input voltage. These Changes are the main contribution to line regulation and low frequency ripple 255 Figure 7.2 Macromodel for the SG137 256 R2 + ADJ VREF R, 36137 - O VIN VOUT + “Lt. VOUT +1 .5. 3 Figure 7.3 Basic application circuit for the SG137 rejection. The inductor LR, the capacitor CR and the resistor RCR provide for the reference to have some frequency response. This provides the reference voltage with two poles and two zeros in it’s ac response. This contributes significantly to the ripple rejection response. R,, is set to be much larger than the combination of the differential resistance of Dza and R,, so that under dc conditions, changes in input voltage which occur across the reference structure are dropped mainly across it. This contributes to quiescent current variations with input voltage. The usual "on" voltage for the device. This is modeled by the diode Dz,. Before the reference voltage can begin to turn on, the voltage between pins 1 and 3 must overcome BV,)”. This gives 257 BVM = V,,, (7.2) 7 .2.2 The Error Amplifier The error amplifier is modeled as a one pole amplifier to model the effects of a frequency compensated amplifier which exists in the SG137. This efl'ect is modeled by R,N which represents the input resistance for the amplifier, E, which provides all of the dc gain, R,, and CP which provide the pole, and E2 which has a gain of one and senses the voltage across CF. E2 is used as a buffer. The amplifier senses the I difference between a sample of the output and the reference voltage. R,,, D,, D_, V,, V,, and E, provide for maximum and minimum clamping for the amplifier. 7.2.3 Ripple Rejection Modeling Rrpple Retecuon vs Frequency SG137 -20lo voutlvm db 70 0| )1 ) 50L. .............................................................. 501- """""""""""""""""""""""""""""""""""""""" 40L ......................................................................... 301— ------------------------------------------------------------------------ 20? """"""""""""""""""""""""""""""""""""""""" 10*— """""""""""""""""""""""""""""""""""""""""" 1 10 100 1000 10000 10000010000001000000 trethz) -- rload = 75 +00“ = 750 + rload = 1500 Temp : 25 0501005 calms Figure 7.4 Ripple rejection vs frequency, measured Fig. (7 .4) gives an example of ripple rejection vs frequency for the SG137. In 258 modeling ripple rejection vs frequency, the following approximations are made. The first approximation is that the low frequency ripple rejection for all the loads are the same. The second approximation is that the first pole in ripple rejection is the same for all loads. As seen in Fig. (7.4), the approximations are reasonable. In order to evaluate the ripple rejection for the macromodel, the program Sspice is used to get an approximate symbolic solution. The symbolic solution for the macromodel is quite complicated, and using this symbolic solution in designing the macromodel is quite involved. The useful formulas which can be used are given here without proof or derivation. These formulas provide the necessary information to correctly choose the low frequency ripple rejection and the first pole. These two parameters dominate the ripple rejection response as seen in Fig. (7 .4). The formula for low frequency ripple rejection is RRU= R: +R1*R2Rx+'pn’ (7.3) Reflux R1 Ro+rnz1 where rm, and rum are the small signal resistances of the diodes Dz, and Dzn- The formula for the first pole in ripple rejection, which is the first zero in the transfer function is ___ RIIRZ +RR+rDZR. (7.4) L, The capacitor CR, RC3, Cp, R,,, the load capacitor and it’s series resistance P1,, contribute to the frequency response as well. The load capacitor and series resistance are fixed, but the other capacitors and resistors mentioned can be varied to produce the desired ripple rejection. 259 7 .2.4 Output Impedance Modeling Output impedance vs frequency is not modeled, however output resistance is modeled. The formula for output resistance has been determined from Sspice and is ROUT'[£.L:R_.;+RO)£ (7.5) where ADC is taken to be the product of the dc gains of EA and E3. The output resistance of the SG137 is taken from either the load transient response or load regulation measurement. For a given load, the Thevenin output resistance can be deduced from the change in output voltage when the load is connected from the output voltage under no load conditions. 7.2.5 Quiescent Current Modeling Quiescent current vs input voltage is shown in Fig. (7.5). The elements which contribute to quiescent current are R,,, Fq, Eqn Vq,, and Rev Eq, is a voltage controlled voltage source which depends upon the reference voltage. FQ is a current controlled current source which senses the current through VQl and has a gain of 1. From the transistion from V = 0V to the point where VREF achieves its reference voltage, it is FQ which contributes most of the quiescent current to the third terminal. At this point v I = 1 = Hf (7.6) Q ’0 R0, 0' or f0 = 10%. (7.7) up Then, R,,, can be varied with temperature to produce a change in quiescent current with temperature. fl 260 IQ vs WIN: SG137 IGtE-S 0m 5 20 t p) -5 LL L _1 L J L I 0 s 10 15 20 25 30 35 40 WIN: (volts] ‘4‘ temp 2 25 Figure 7.5 Quiescent current vs [VIN I, measured After the reference voltage has achieved it’s nominal value, the current through FQ no longer changes. The variations in quiescent current now come fi'om R,,. Thus = MIMI, (7.8) Ala In the quiescent current measurement, the lab data plot shows that a severe change in quiescent current occurs at approximately V1N = 16V . This slope is not modeled. It is felt that this slope is a function of the test circuit, and does not occur under normal operation. If it did, quiescent current on the order of .2mA, which occurs at IVINI = 35V, would have a significant effect on the output voltage, as it flows through R2. This was checked in lab, and no effect on output voltage was noted. Therefore, it probably does not exist, and is not modeled. 261 7.2.6 Short Circuit Current and Foldback Current Limiting A plot of measured short circuit current and foldback current limiting is shown Max Output Current SG137 3 IMAX (amps) 10 15 20 25 VDIFF (volts) -'- temp = 25 degrees C Figure 7.6 Maximum output current vs err: measured in Fig. (7 .6). The short circuit current circuitry consists of DL and EL and the foldback current circuitry consists of D”, and EFB. These additional circuitry work in the following way. The load current flows through the collector of Q. Then, a current, approximately equal to IC/BF must flow through the base of Q, as well. If the base current is limited, the collector current is limited, and hence the output current is limited. The base current of Q? is limited by limiting the voltage across R32. The voltage drop across the series combination of DL and EL is equal to the voltage drop 262 across R,,2 + Vamp. If V,,,32 + Vamp becomes larger than V0,”), + V3,, then the diode DL will turn on. If the voltage drop across the diode is taken to be nearly equal to Vamp: then V,,B2 = VEL. VEL depends upon the differential voltage, V(2,3), so under short circuit current conditions, and for a given V(2,3) it is constant and constrained, meaning that V,,B2 cannot become larger than V3,, The voltage R132 then becomes clamped at this maximum voltage, and hence the load current becomes clamped at some maximum value. The equation, then relating maximum output current to the model parameters is .. m (7.9) where the voltage VEL is a function of the differential voltage V(2,3). This formula does not take into account the current necessary to bias R, and R,, which is small in comparison to the maximum allowable output current. To select the coeficients of the polynomial which describes the voltage across EL, two points are picked in the current limiting region, which are not in the foldback current region. These points are the point in Fig. (7 .6) where the maximum output current is achieved afier device turn on, and the edge of the foldback region. In practice, EL is modeled with a constant term and one first order term. The constant slope of the maximum output current in this region should strongly suggest this relationship. The foldback current works identically to the short circuit current limiting circuitry. In the foldback region, the voltage drop across E33 is selected so that it is less than the voltage drop across E, in the foldback region. This means that the voltage Era is the main controller of the maximum output current. Then 263 1,“, = BFQZE’gL—Efl (7.10) and EPB also depends on the differential voltage. The behavior of the maximum output current in this region, suggests a higher order relationship between Em, and V(2,3). In practice, a fourth order relationship is used. 7.2.7 Power Up and Down, Square Wave Fig. (7.7) gives the power up and power down for a square wave input. The peaking which occurs in power up is a result of the natural frequencies of the circuit. These are mainly determined by ripple rejection, but it is advised to use ripple rejection to get a feel for the approximate placement of the poles and zeros, and to tweak components to get the correct power up transient response. The delay seen just before the peaking occurs results from the output capacitor slewing, which occurs because the regulator can only supply a maximum amount of current due to current limiting. This, of course, is set by the current limiting itself. Upon power down, the capacitor must discharge itself through the regulator. DDIS is used to model these effects. 7.2.8 Power Up and Down, Triangle Wave Fig. (7.8) gives the measured power up and down with triangle wave. The main component of power up and down which is modeled, and controlled by the user, is the peaking which occurs just prior to the regulation of the chip. This occurs primarily as a result of the time required to charge up Cp. Presently, there is no formula for this, it is done with an empirical fit. 7.2.9 Dropout Characteristics The dropout characteristics are contributed by R90, D001: D902 and Q9. This is 264 333.22% l?{913.1315};,9§E§L&9§EQB§. 332.13.52.12‘703'30181263'3’ av unnu---., ,1 z .1 ? EV l t I ) 'dtU: 1 l tngd: -.2'0v'L -99.7Fus Sans/div _,hwfiBB.ZS#s Figure 7.7 Power up and down, square wave, measured 265 .1122: ”5951311252 ANS 9530183835.. 5318352003 361811443 3’ 12K 8V ' 7 A ..... I .' - ‘76 3m- -.umv I I '0. ~11“: _ 1 . . / \ h~ , t \ ) “ i T pl \ 4 ' r 1. . ., ~- ~ . '. 1 ‘7’114 ‘l . D \ I ' v e—~ om 1" / t, .1 { ~ ., . .. ..3.?!K._m \ _-m.. _ f . . kl ’ l' , / I 1*— *— 7 1)“qu 9%..“ \ Y7 “79615 _ Beans/div, , ____l__.2__8_40_1$ -'—‘.0v L.— " V Figure 7.8 Power up and down, triangle wave, measured 266 approximately the voltage required to put QP at the edge of saturation. Then [LOAD VDO = Imme+2NVTln[lsml]+Vumr(1m), (7.11) if the diodes D90, and D002 are taken to be equivalent. Eqn. (7.11) does takes into account the fact that the saturation voltage of QP is a function of load current. 7.2.10 Other Modeled Characteristics The prior characteristics are used in determining component selection. As a result of correct choice of parameters and topology the macromodel predicts other responses. These are: line and load regulation, line transient response and load transient response. 7 .3 DESIGN PROCEDURE FOR A SG137 Based on the equations and procedures shown in the last section, a design procedure will be developed in this section. Basic to the design procedure is a list of measurements required to base the design on. The following measurements should be taken in the basic regulator circuit: 1) Measure Vou'r vs Vm with no load. 2) Measure IQ vs V,N with no load. 3) Measure VOUT for VIN = -15V, with no load. 4) Measure ripple rejection vs frequency with a 1000 load. 5) Take a load transient response measurement with a 1000 load, and from this determine Row» 6) Measure maximum output current vs voltage difi‘erential. 7) Measure dropout voltage with RLOAD = 1000. 267 8) Take a power up and down with both triangle wave input and square wave input with RLOAD = 1000. 9) Measure Rum), and the external resistors R, and RZ. These measured values get used in all of the equations. Measure as well the capacitances of all capacitors and the series resistance of all capacitors at some representative fiequency. The component selection procedure is: rd, 1) Select E, and E2. ' l 2) Select the amplifier clamping circuitry, these are the values for: ,2; V,, V,, E“ E_, and the diode parameters for D+ and D,. l 3) Based on the Vow vs VIN measurement, determine the input voltage required to begin to turn the circuit on, VON, then BVM = lel. (7.12) Select NBVDZP 4) From the measured value of VOUT at VIN = -15V, and utilizing Eqn. (7 . 1), "m = Vm = IVOZI ' (7.13) 1 + _ t a.) Select NBVM, and RZR. 5) Measure the slope of IQ vs VIN for the quiescent current measurement. 6) Then from Eqn. (7.8), “Q (7.14) - -_ IAle' From the ripple rejection measurement, determine RRLF. Then 7) 8) 9) 10) 11) 12) 13) 14) 15) 268 determine the small signal resistance of DZR, rDZR and of D2,, run. This is determined from a trial macromodel run with PSpice. Then from Eqn. (7 .3), RR = (RRU- Rafip‘IIIRITRzyko-rmrrm (7.15) From the ripple rejection measurement, determine P1“, then from Eqn. (7.4), ' L,, = R‘lkzgz‘ui'm. (7.16) Select RCR From the ripple rejection vs frequency measurement, determine 0,, empirically. Select R0 and R,, From the power up and down triangle measurement, as well as ripple rejection vs frequency, determine 0,; empirically. From the power up and down square wave measurement, measuring the difference in the input and output voltage waveforms directly after power down, select an appropriate value for NDmS. Select Rqr Then from the IQ vs VIN measurements and from Eqn. (7 .7), R01 (7 17) f = I —. . Q 0 VREF Select the parameters for the output transistor QP. These are BF and IS. Select R,,, and R52. 16) 17) 18) 269 Select the parameters for the diodes DL and D93. From the maximum output current vs difi‘erential voltage measurement, in the short circuit current region, select 11 and V1, the point where maximum output current is achieved. Select 12 and V2 as the point where the device enters into the foldback region. Then the coefficients of EL need to be solved for. EL is described as E1. = “0+“le (7.18) ["1 Then from Eqn. (7.9), let u a,, = —R.,. (7.19) are, Then a, can be determined and is run —BFop ' (7.20) 0,: V2 Select a maximum of 4 points in the foldback limiting region, (Il,V1) (I2,V2) (I3,V3) and (I4,V4). The first point should be the point on the curve where the device enters into the foldback region, the last should be the last point in the measurement, and the other two placed where the rate of change in the curve is greatest. The coefficients of EFB need to be solved for and these are b0, b,, b2, and b3. EFB can now be described as En = bo+b,Vm+b2V;,,+bsl’3W (7°21) The coefficients can be solved for by solving the system of equations 19) 270 ( II 1 ( , BF“, (1 v1 V12 V1" be 12 R 1 V2 ”2 V23 b‘ ”Q" n (7.22) 1 V3 V32 V33 b2 - A ' (1 V4 V41 1,431,151 ”(I _14_ (”or i i From a trial run with the macromodel, determine the value for stmpo Select T" 1301101111102- Determine the value of the load current. From the measured ' i . dropout voltage, VDO, and Eqn. (7 .11), i I Nnno = VDO-V,,“.‘QP-Imwkc I ' 7.23 2171,, [£94] ( ) [saw 20) 21) 22) From the load regulation measurement, measure the change in output voltage when the 1000 load is connected from no load conditions. Then from Eqn. (7.5) AV Roar = V._0_w_'_gm, (7.24) OUT. 11.-1000 From Eqn. (7.5) R «1- R0 = “007%:- -]flfi§3. (7.25) Select R,,... At times, a capacitive load may need to partially discharge through this resistance, so it should be selected large, but finite. Several diodes will have very small values selected for their series resistance, RS, and junction capacitance, CJO. This helps the 271 macromodel converge, especially at the temperatures of -55 degrees and 125 degrees. This concludes the design procedure. All of the parameters for the macromodel have been selected. 7.4 DESIGN EXAMPLE FOR A SG137 The design example is based on laboratory measurements is presented. The data, unless otherwise specified, is taken directly ofi' from the plots which were shown previously in the document. The nominal 1000 load resistor was measured at 100.2140. R, was measured at 119.930 and R2 was measured at 820.130. An output capacitor was used with a series capacitance value of .9396uF and a series resistance of 1.09530 at 100kHz. The output capacitor was necessary. An adjustment capacitor was also necessary. This is a capacitor which is connected between the adjustment pin and ground. This had a series capacitance of 158.04pF and a negligible series resistance at 100kHz. 1) Set E, = 600 and E2 = 1. 2) Let the diodes D+ and D, be the Pspice default diodes. Set V+ = -1V, V' = 1V. Set the gain of E+ = 1 and let V(3,1) be the controlling voltage. This means the maximum voltage for the amplifier is (V(3) + 0.3)V and the minimum voltage for the amplifier is (0.3 + V(1))V which falls between the rail voltages of the chip. 3) Based on the Vow vs VIN measurement, set BVz, = 1V. Set NBVZ, = 0.001. 4) From the measured value of VOUT at V,,q = -15V, set BVDZR = 1.25V. Set _Il 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17) 18) 19) 272 From the IQ vs V,N measurement, R,, = 1.7546Meg0 From the ripple rejection measurement, RR“. = 60.8db = 0.9120m Then rDZR was determined to be 1.30, as was run. This gives R,, = 98.29940. P1,“, was determined to be 120Hz, then L, = .2709H. Set Ra, = 150k0. By iteration, CR = 3pF. Set R0 = 100 and R,, = 1510. By empirical methods, CP = 0.01uF. From the power up and down square wave measurement, set NDDIS = 1. IQ was measured at 78.09uA. Set R0, = 10. Then fq = 0.0625m. Set BFQP = 500 and ISQP = 1e-14A. Set R,,, = 100 and R,,2 = 5000. Let the diode parameters for DL and D00 be the Pspice default diodes. From the maximum output current vs differential voltage measurement, 11 = 2.447A, then a0 = 2.447. Then 12 = 2.29A and V2 = 15.724V gives a, = -0.01. 4 points were selected in the foldback limiting region, (2.29A, 15.724V) (1.8233A, 18.188V) (1.5878A, 19.922V) and (1.2880A, 23.7 2V). Solving (7 .22) yields the following values for the coefficients a,,, a,, a,, and a3, 12.5955, 4.2275, 0.0457, -5.9169e-4. Set 150001.0002 = 1e-14A From a trial run with the macromodel, V3,,” 273 20) From the load regulation measurement, AVG,” = 1.9mV for the 1000 load, then Rom. = 0.01930 and R0 = 1.1556m0. 21) Set R,,, = 100k0. This concludes the design example. All of the parameters for the room temperature macromodel have been selected. 7.5 MODELING THE SG137 AT -55 AND 125 DEGREES 7 .5.1 Strategy in Modeling the SG137 Temperature Variations The room temperature model is developed. The steps which need modifications are steps 3, 4, 5, 6, 7, 8, 11, 13, and 15. These will give rise to new values for BV,)”, BV,,ZR, R,,, R,,, L,,, Reg, 0?, and R82. Lab data will be taken and the above parameters will be selected. In step number 13, R,,, was set, then the determination of 1}, followed. For simplicity, fQ remains constant throughout temperature, and R,,, is varied to produce variation in quiescent current with temperature. For the temperature dependence of the maximum current and foldback current limiting, R,,2 is varied. This results in shifting the maximum output current curve up or down, depending on the temperature. This does not give exact results, but gives good results. 7.5.2 Design Example to Include Temperature Dependance In this section the parameters for the model for 55°C and 125°C are developed. The temperature coefficients are determined and then inserted into the room temperature model. This represents the fully developed, macromodel for the SG137 . Following the format of the first example and applying it to the -55°C model: 3) 4) 5) 6) 7) 8) 9) 11) 13) 15) 20) model: 3) 4) 5) 6) 7) 8) 274 Based on the vou'r vs V,,." set BVDz, = 1.25V. From the measured value of VOUT at VIN -15V, set BVDZR = 1.2503 V. From the IQ vs VIN measurement, RQ = 1.7 546Meg0. From the ripple rejection measurement, RR”. = 57.6db = 1.9120m. Then rDZR was determined to be .8510 as was rum. This will then give R,, = 189.60. P1RR was determined to be 17 0H2, then LR = .2755H. By iteration, CR = 3pF. By empirical methods, CP = 0.01uF. 1Q was measured to be 81.6uA. Then R,,, = .95740. 1m = 2.36A From Eqn. (7.19), R,,2 = 518.430. From the load transient response measurement, AVOUT = 4mV for the 10011 load, then ROUT = 00410:) and R0 = 4.2674m0. Following the format of the first example for the and applying it to the 125°C Based on the VOUT vs V,,,, set BVDZ, = .75V. From the measured value of VOUT at V = -15V, set BVDZR = 1.2511V. From the IQ vs V,,, measurement, R,, = 1.9331Meg0. From the ripple rejection measurement, RR“ = 61.8db = .81283m Then rDZR was determined to be 1.510 as was run. This will then give R,, = 94.31970. P1,,“ was determined to be 110Hz, then LR = .29H. 275 9) By iteration, CR = 3pF. 11) By empirical methods, CP = 0.01uF. 13) IQ was measured to be 81.6uA. Then R,,, = .84450. 15) IMAX = 2.413A. From Eqn. (7 .19), R32 = 507.05360. 20) From the load regulation measurement, AVOUT = 1mV for the 1000 load, then ROUT = 0.01020 and R0 = -.2m0, therefore let it be approximately 1e-80. A final summary of the temperature dependent parameters and elements follows in Table 7.1. element or value at value at value at parameter 25 degrees -55 degrees 125 degrees BV,,Z, 1 1.25 .75 BVDZR 1.25 1.2503 1.2511 R,, 1.7 546Meg 1.7546Meg 1.9331Meg RR 98.2994 189.6 94.3197 LR .27 09m .2755 .29 R,,, 1 .9574 .8445 R32 500 5 18.43 507 .0536 R0 1.1556m 4.267 4m _ 1e—8 Table 7.1 Temperature dependent components and parameters Solving for the linear and quadratic coefficients for each of these components and 276 parameters leads to the following results in Table 7.2 ‘__ I element or TCl or TBVl T02 or TBV2 parameter (linear coefi‘.) (quadratic coefi'.) BV,,Z, -0.002847 3.4722e-6 BVom 2.2444e-6 6.5556e-8 RQ 4.5212e—4 5.6515e-6 R,, -0.00663 6.2251e-5 LR 1.9544e-4 5.0962e-6 R,,, -3.9528e-4 -1.1597e-5 R,32 -1.9327e-4 3.3434e-6 RO -.007894e-4 0.001136 Table 7.2 Temperature coefiicients The macromodel for the SG137 follows. The macromodel includes the effects of temperature. .SUBCKT SG137 1 2 3 *pin out adj I I * out | LR 1 4 IND1 .2709 .MODEL IND1 IND (TCl=7.8864E-4 TC2=-2.8391E-5) RR 4 5 98.2994 TC=-0.0063,6.2251E-5 CR 1 6 3p RCR 6 7 150k DZR 7 5 DZR .MODEL DZR D (BV=1.25 TBV1=2.2444E-6 TBV2=6.5556E-8 NBV=0.0001 CJO=.1P) RZR 7 5 1MEG DZ1 8 7 DZ1 .MODEL DZ1 D (BV=1 TBV1=-0.002847 TBV2=3.4722E-6 NBV=0.0001 CJO=1P RS=1) RQ s 3 1.7546MEG TC=4.5212E-4,5.6515E-6 FQ 1 3 VQ1 0.0625m EQ1 24 0 1 7 1 VQ1 24 25 dc 0 RQ1 25 0 1 TC=-3.9528E-4,-1.1597E-5 277 RIN 7 23 100k E1 11 3 23 7 600 ROEl 9 11 10 D+ 9 13 dc V+ 14 3 -1 E+ 13 14 1 3 1 D- 12 9 DC V- 12 3 DC 1 .MODEL DC D (CJO=10P) RP 9 10 151 CP 10 3 .01U E2 15 3 10 3 1 R31 15 16 50 R32 16 19 500 TC=-1.9327E-4,3.3434E-6 DSC 16 17 DMOD ESC 17 3 POLY (1) (2,3) 2.447 -.01 DFB 16 18 DMOD EFB 18 3 POLY( 1) (2,3) 12.5955 -1.227 5 0.0457 -5.9169E-4 QP 20 19 3 QMOD .MODEL QMOD NPN (BF=500 IS=1E-14) RDO 23 22 0.1 DDOl 22 21 DDO DD02 21 20 DDO .MODEL DDO D (N =.9687 IS=1E-14) R0 23 2 0.0017 TC=-0.07894,0.001136 DDIS 3 23 DDIS .MODEL DDIS D (CJO = 1P) .MODEL DMOD D (IS=1E-14) .ENDS SG137 27 8 7.5.3 Comparison of Macromodel Predictions with Lab Results A comparison of macromodel predictions with lab results is presented in this section. Ripple RejectIOn vs Frequency SG137 0 -20log(voutlvm) (db) 0 l 1 1111111 1 1 1111111 1 1 1 111111 1 1 L111111 1 1 1 1111 1 1111111 1 1 111111 1 10 100 1000 10000 100000 10000001000000 freq (Hz) —— temp - -55 -+- temp . 25 + temp . 125 Figure 7.9 Ripple rejection vs frequency, measured 125 Degree- C 60« -55 Degrees C 40« .25-Door... c. ... 20~ U - _fi . . . . 1.0h 10h 1oon 1.0Kh 10Kh 100Kh 1.0Mh 1OMh - 9 o—db(V(Z)IV(1JJ Frequency Figure 7.10 Ripple rejection vs frequency, macromodel 279 11901 DIGIIIZING OSCIL SC P date: ~ .h-‘? trmo: Egzwgzgs 15553352691953'3518I163'3) 'lhk 8V av r d ‘ ‘J . ll ' A‘ ' - Mr A:"—* u- 7 f 4'" ‘1 it: i ’P -1 .1 trlq'd : ’f—fi -r-— S J: I g u 1 ,. - M001 1 -20v 11 Figure 7.11 Power up and down, square wave, T = -55, measured 280 111213.212 1113211311213 - 3> m "5"”; m I“ i I 1;:m==:=: EII-—- '— 1 L Ev ) ’dlU: t of‘ L ’14" lb . .lrzfl“ iwfiw i trmhz r -1?8V 9 l— '0 -99.75H3 . _ ___ sans/div _ 488.5523 Figure 7.12 Power up and down, square wave, T = 25, measured 281 ll'wil DISI’IZING OSCILLOSCOPE -Cexo:3.8.drq:3.91.dsv:3.3) date: ~ T time: .__--:'.o Instrument 100 8010199 8V W F“ “2m:- l 2 1 ’ (1 IV : f ‘40 L 1‘ ...” - ___:m: . .4 ~ r ‘ _fl? #— ‘vtfr‘ 1I 11'” d! R’ A:—— n :_ _ '7 ‘ “T! l 1 DEV L-— -- Egg 75MB saflsrdiv 433.25#s Figure 7.13 Power up and down, square wave, T = 125, measured 282 UV- d - -55 degrees C 4) 4 . ' ) -sv. . . . . i . . . . . . . . . . . . %. 1 ) 1 25 depress C 1) I ) h—‘C—f -10V~ : -. ~15V ._ 111.7: :, 41~¢*:. , 443—: , 05 10005 20005 30005 40005 50005 a o 2V[1) v o +V(2) Tlme Figure 7.14 Power up and down, square wave, macromodel - ZED—'1 283 51291 °§951£$§$3619253L18fit9§§4 13:8:35352‘903'36181263'3’ 8V , ’ — '76 3...... A) I ‘ 2 "div! El " -~").!Lan ' ’1 \x 7 1 (l M7M.p%_ trthi ) l \ l K g \_ 1 g ...... l 1 ”EN L— . -:Bbus EBaus/dlv 1.284ms Figure 7.15 Power up and down, triangle wave, measured 284: p0-trl.cir 0V -SVd ~55 degrees C \j 25 degrees C ~10V« 125 degrees C -1SV« -20V . . r 05 0.5m5 1.0m5 1.5m5 2.0ms u o AV(1) v o +V(2) Time Figure 7.16 Power up and down, triangle wave, macromodel 'Lw‘ 1")le 285 i 13" 1.1% 11:” t 1 5:513:212*113-3518rx43-3’ )JL— I fi — — In Figure 7.17 Line transient response, measured 286 ltr.c1r -9.0V - -SS and 25-degrees C -g,5v. . . . . . . . . . I . . . . -1g,ov. . . . . , I ii 125 degrees C -10.SV- . . . . . . -1l.0V‘ -11.5V« -1 . V . . . . 2 0 Us 10005 20005 30005 10005 50005 a e AV(2) T1me Figure 7.18 Line transient response, macromodel 287 11401 115 r 2 ~ ‘ 5.... 2.390193%31-399313. 1:: #35959‘903'361812163'3’ . ' v ,0. I t 1 .. . m . . «w . | . 1 - l l 68mV§ ”(1101 ”in" I! 5 ‘ 1. l +— iiiii ' I (J; . l t:— H" M f 1'.?~"’v tri’gd! l.‘0~\v .3101" ‘ H: 1 U .__¢_~_ ; 2.2"" ' HUI-Comm“ —- IV ‘2 1 1 , sf ‘ . 1 , —*——-1 '98m‘v’ “ I I + - r f ;- oIOV “19.603 EBHSKdtu 188.438 Figure 7.19 Load transient response, measured ”"3 .80V .84V- 288 ldtr.cir .BZV‘ ' 25 depreés c' - '55 CWTOOS C ‘ A A — v V .BBV‘ . 1’. 1 4 'F I I .98V« .90V‘ 125 degrees C I, .92V 5005 10005 15005 20005 4V2 ( ) Time Figure 7.20 Load transient response, macromodel 289 I0 vs (VIN) 86137 D IG IE-5 lamps] o S 10 15 20 25 30 35 40 |VIN| (volts) —‘— temp = -55 —+— temp = 25 + temp = l25 Figure 7.21 Quiescent current vs IVm I, measured 1q.c1r 2000A 1souA-1 ooooooooooooooooooooooooooooooooooooooo 125 Door or C - ' _ .; _ . '-‘ ; 1000M -------- -_---- "":‘::t:"-'w . }ss Degriebs c o: I c , , , $00M . .............. 2.5. 91“.“. ................. OA- ...................................... -SOUA ' '—v —“r “r T fi 3 0V 5V 10V 15V 20V 25V 30V 35V 40V a o Altrquros) vrn Figure 7.22 Quiescent Current vs WIN (, macromodel .OA 3 IMAX [amps] 290 Max Output Current SG137 .1 .DA- 5 ID 15 20 25 3D VDIFF (volts) -‘- temp = ~55 —+— temp = 25 + temp :125 Figure 7.23 Maximum load current vs IVmI: measured Cl .cur . 25 degrees C 125 degrees C J £55 degrees 0 EV 16v 15v 273v 251v 30x7 9 o A l(rload) vm Figure 7.24 Maximum load current vs [VIN], macromodel 291 Comparison of Macromodel parameters and Measured Parametersfi—1 QUANTITY -55°C 25°C 125°C RR”. lab 57 .6db 60.8db 6 1.8db model 57.5db 60.8b 61.6db P1RR lab 17 OHz 120Hz 110Hz model 170.5Hz 120.4Hz 110.0Hz IQ lab 81.6uA 79.1uA 92.5uA model 82.2uA 78.5uA 92.6uA AIQ/AVIN lab .5699u .5699u .5173u model .5765u .5740u .5225u maximum load current lab 2.36A 2.45A 2.41A model 2.24A 2.3OA 2.25A dropout voltage lab 1.83V 1.16V 1.35V model 1.86V 1.64V 1.20V Rm}.r lab 0.04100 0.01930 0.01029 model 0.05459 0.03169 0.02550 Table 7.3 Macromodel comparisons with lab data This concludes the comparison of the macromodel with lab results as well as the report for the development of the 86137 macromodel. 292 7 .5 TEST CIRCUITS 7.5.1 Pspice Test Circuits CAnufii R2 ‘ + ADJ VREF R1 1 _ 3 $6137 8 0 V 6+) BUT ’ CDUT + VDUT IN LOAD RDUT Figure 7.25 Basic PSpice test circuit 293 RR.CIR * *RIPPLE REJECTION FOR THE SG137 * VIN 4 0 DC -15 VAC 1 4 AC 1 RLOAD 2 0 100.214 COUT 2 10 .9396u ROUT 10 0 1.0953 R1 2 3 119.93 R2 3 0 820.13 CADJ 3 0 158.04p XREG 3 2 1 sg137 .OP .LIB SG137.LIB .AC DEC 20 10 1MEG .PROBE .TEMP -55 25 125 .END PU.CIR * *POWER UP AND DOWN, SQUARE WAVE FOR THE SG137 * RLOAD 2 0 100.214 CLOAD 2 10 .9396u RCLOAD 10 0 1.0953 R1 2 3 119.93 R2 3 0 820.13 CADJ 3 0 158.04p X1 3 2 1 SG137 VP 100 0 PULSE (O -15 100u 0 0 250u) RVP 100 1 .1 .LIB SG137.LIB .TRAN 1u 500u 0 1n .TEMP -55 25 125 .PROBE .END 294 PU_TRI.CIR * *POWER UP AND DOWN, TRIANGLE WAVE FOR THE SG137 * ROUT 2 0 100.214 COUT 2 20 .9396u RCOUT 20 0 1.0953 X1 3 2 1 SG137 R1 2 3 119.93 R2 3 0 320.13 CADJ 3 o 158.04p VP 1 o PULSE (0 -20 On 700u 700u lu 1410u) .LIB SG137.LIB .TRAN 2.5u 2000u o 2.5u .TEMP -55 25 125 .PROBE .END LTRCIR 2: *LINE TRANSIENT RESPONSE FOR THE SG137 * ROUT 2 0 100.214 COUT 2 10 .9396u RCOUT 10 0 1.0953 X1 3 2 1 sg137 R1 2 3 119.93 R2 3 0 820.13 CADJ 3 0 158.04p VIN 11 0 dc -15 VP 1 11 PULSE (0 -4 100u On On 250u) .LIB SG137.LIB .TRAN 1u 500u 0 1n .TEMP -55 25 125 .PROBE .END 295 LDTRCIR * *LOAD TRANSIENT RESPONSE FOR THE SG137 * VP 10 0 pulse (-9.8 0 20u 0 0 10011) RLOAD 2 10 100.214 *RLOAD NOT GROUNDED, ONE PIN CONNECTED TO OUTPUT, THE OTHER TO *VP COUT 2 100 .9396u RCOUT 100 0 1.0953 R1 2 3 119.93 R2 3 0 820.13 CADJ 3 0 158.04p X1 3 2 1 sg137 VIN 1 0 dc -15 .TRAN .1u 200u 0 .1u .TEMP -55 .LIB SG137.LIB .PROBE .END IQ.CIR a: *QUIESCENT CURRENT CHARACTERISTICS FOR THE SG137 It VIN 0 1 DC 10 RQUIES 0 3 0.00001 RLOAD 0 2 100MEG X1 3 2 1 SG137 .LIB SG137.LIB .TEMP -55 25 125 .PROBE .END 296 CL.CIR * *CURRENT LIMITING FOR THE SG137 * VIN o 1 DC -15 RLOAD o 2 .9938 R1 2 3 119.93 R2 3 0 820.13 CADJ 3 o 158.04p COUT 3 10 .9396u RCOUT 10 0 1.0953 XREG 3 2 1 sg137 .DC VIN o 25 0.1 .PROBE .LIB SG137.LIB .TEMP -55 25 125 .END VDO.CIR :1: DROPOUT VOLTAGE FOR THE SG137 * VIN 0 1 DC -15 RLOAD 2 10 100.214 R1 2 3 119.93 R2 3 0 820.13 CADJ 3 0 158.04p COUT 3 10 .9396u RCOUT 10 0 1.0953 XREG 3 2 1 sg137 .DC VIN 0 25 0.1 .LIB SG137.LIB .PROBE .TEMP -55 25 125 .END 297 7.6.2 Measurement Test Circuits C”: ADJ 1 1 3 86137 2 F + g I vIN 2 Figure 7.26 Test circuit No. 1 The conditions of test circuit N O. 1 are stated. R1 measured 119.939. R.z measured 820.139. Cour measured .9396uF at 100kHz. Room represents the series resistance of COUT and measured 1.09539. CADJ measured 158.04pF at 100kHz. R3, R4, R5, and R5 have nominal values of 1k9. V+ is a positive 10V dc power supply. V- is a negative 50V dc power supply. OA is a Burr-Brown OPA541 Op-Amp. The SG137, R1, R2 reside inside a temperature chamber. Wires are connected at the terminals of the SG137 to allow it to be connected outside the chamber to the test circuit. 298 F"QUIES ADJ 1 g 3 86137 8—0 + VUUT VIN 2 Figure 7.27 Test circuit No. 2 The conditions of test circuit N O. 2 are stated. R3, R4, R5, and R3 have nominal values of 1k9. V+ is a positive 10V dc power supply. V- is a negative 50V dc power supply. 0A is a Burr-Brown OPA541 Op-Amp. The SG137 resides inside a temperature chamber. Wires are connected at the terminals of the SG137 to allow it to be connected outside the chamber to the test circuit. RQUIES has a nominal value of 1009. 299 ADJ 1 _ 8 3 86137 3 4‘3 + __i.‘__ Figure 7.28 Test circuit No. 3 The conditions of test circuit N o. 3 are stated. Rl measured 119.939. R2 measured 820.139. Cour measured .9396uF at 100kHz. Room represents the series resistance of COUT and measured 1.09539. CADJ measured 158.04pF at 100kHz. R3, R,, R,, and R, have nominal values of 1k9. V+ is a positive 10V supply. V- is a negative 50V supply. 0A is a Burr-Brown OPA541 Op-Amp. The SG137, R,, R.z reside inside a temperature chamber. Wires are connected at the terminals of the SG137 to allow it to be connected outside the chamber to the test circuit. Q1 is a 2N4403 pnp transistor. R31 has a nominal value of mm. R82 has a nominal value of 1k9. 1) 2) 3) 4) 5) 6) 7) 8) 300 Ripple rejection was done using test circuit 1. VA was connected to an ac function generator. VB was connected to a negative dc power supply. These were set to produce a -15V dc voltage at VIN, with a sine wave superimposed. RLOAD measured 100.2149. Voltages and phases were measured with a Tektronix 11401 scope. The VIN vs Vow and VOUT at V = -15V measurements were done using test circuit 1. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. VB was grounded. These were set to produce the necessary voltage at Vm- Room: when used, measured 100.2149. Voltages were measured with a Tektronix 11401 scope. The power up and down square wave measurements were done using test circuit 1. VA was connected to an pulse generator. VB was grounded. RLOAD measured 100.2149. Voltages were measured with a Tektronix 11401 scope. The power up and down triangle measurement was done using test circuit 1. VA was connected to an ac function generator, generating a triangle wave. VB was connected to a negative dc power supply. These were set to produce a triangle wave at VIN which has a maximum value of 0V, and a minimum value of -20V. RLOAD measured 100.2149. Voltages were measured with a Tektronix 11401 scope. The quiescent current measurements were done using test circuit 2. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. VB was grounded. These were set to produce the necessary voltage at VIN. unms measured 99.8769. Voltages were measured with a Tektronix 11401 scope. The voltage was measured across RQUIES and divided by Remus to give the quiescent current. The load transient response measurement was done with test circuit 3. VA was grounded. VB was connected to a negative power supply to produce a dc voltage of -15V at VIN. VP was pulsed to allow Q1 to function as a switch, connecting me on and off to ground to simulate the switching on and ofl‘ of a load. The maximum output current vs VIN measurements were done using test circuit 1. VA was connected to an pulse generator and pulsed at 100Hz, with a duty cycle of 5%. V,, was grounded. These were set to produce the necessary voltage at Vm- RWAD .99389. Voltages were measured with a Tektronix 11401 scope. The voltage measured at RLOAD was then converted to a current. The line transient response measurement was done with test circuit 1. VA was connected to a pulse generator. VB was connected to a negative dc power supply. These were set to produce a -15V dc voltage at VIN, with a sine wave superimposed. RLOAD measured 100.2149. Voltages were measured with a Tektronix 11401 scope. CHAPTER 3 DESIGN ISSUES 8.1 INTRODUCTION In this chapter, some of the issues which go into the macromodeling of voltage regulators are discussed. The issues are general issues of macromodeling, and can be applied macromodels of other IC’s as well. 8.2 DESIGN ISSUES The macromodeling problem can be broken up into three parts. They are: 1) starting point 2) modeled specifications 3) development to meet specifications Although I and 2 seem simple, they are not. Many current macromodels violate good choices for 1 and 2. Part 3 is where the problem becomes most open ended, with numerous solutions. 8.2.1 Starting Point The thesis shows that good macromodels are developed from a good choice of a starting point. The most reasonable choice is the functional block diagram [13]. It makes sense that if a model is functionally the same as the actual chip, that it behaves like the real chip. If the model is not functionally the same, it is unreasonable to assume that the model will perform like the actual chip. This is only common sense. An example of a chip which violates this idea is the MicroSim’s 301 m‘vmmw. .~.' 7 LM78XX macromodel. The chip assumes a grounded voltage reference, instead of the voltage reference existing between two internal nodes in the chip. 8.2.2 Modeled Specifications This is another seemingly easy, but dificult task. Obviously, when a correct starting point has been chosen, a goal must be set. The goal is the choice of parameters to be modeled. In the case of the op-amp, a well known chip and widely used chip, it is easy. There are enough designers with enough op-amp experience so that it is relatively clear which parameters need to be modeled. An example of a chip in which it is not clear what to model is the voltage reference. The chosen parameters should be suitable to define the chip. This helps guarantee that the model will work even when implemented in a topology which may be difi‘erent from any topology that the model underwent during development. It is not clear how many parameters or characteristics can completely define the chip being modeled. It would be ideal, that if given a number of parameters, one could completely characterize the chip. Consider the linear 1-port network. Fundamental theory states that two measurements are necessary to completely characterize the linear one-port. These measurements are open circuit voltage measurement and short circuit current measurement. The equivalent circuit which results can be used in place of the linear l-port. With a linear 2—port, four measurements are necessary, etc. Unfortunately IC’s are non-linear devices with non-linear phenomenon, a problem that cannot be solved as easily as the linear networks, if at all. It is easy to choose 1 or 2 characteristics and have the macromodel mimic these characteristics with great accuracy. It is difficult to choose many parameters and have the model reflect all of them accurately. 302 I f |",‘ "h..‘."'.'-E fl] 303 Most importantly, the most critical characteristics of the devices should be modeled. For the voltage regulator, power up and down, and output resistance are the important parameters which must be modeled. In general, the modeled characteristics can come from several sources. These are data sheets, customer applications, personal experience, and personal curiosity. It was curiosity which lead to the measurement of the frequency response of the voltage reference inside the UA723. This lead to a great deal of insight. The other chosen characteristics came from the first three sources. When a decision has been made on what characteristics are to be modeled, the characteristics should be measured. The model is then based on measurement. Relying on data sheets is not good practice - as data sheets may be incorrect. Finally, the user must select some tolerance for the characteristics. Even maturely developed macromodels can not completely meet specifications. There is a trade-off to be made on how much tolerance is realistic for the model to be useful and time invested in the model. Trade-offs will also occur between characteristics. Low frequency ripple rejection in the SG78XX was favored over line regulation, for example. Any of the macromodels presented here can model almost any parameter with almost zero percent tolerance, but at the cost of reducing the accuracy of other modeled characteristics. At some point, the user must decide when all of the parameters are modeled with reasonable accuracy. 8.2.3 Developing the Macromodel Once the starting point and ending goal have been defined, the starting point is developed to meet the desired specifications. Ideally, it is desirable to replace each functional block with an equivalent circuit for that actual functional block which W" c._...- ___3 304 behaves like that functional block for all linear and non-linear behavior. The voltage reference in the CA3085 is an example of this. Because we were able to measure the reference, the reference which replaced it had almost identical ac and dc response to the actual reference. Instead of a differential amplifier, or some other type of error amplifier, a voltage controlled voltage source with some gain and clamping is seen to work well with all of the macromodels. Darlington output pair transistors can frequently be replaced by one pass transistor. Most of the maximum output current structures are also identical to what may be found in the actual chip. Optimally, the functional blocks are replaced with circuits which are less complicated, easier to understand, and have fewer components. At times, it may be necessary to model phenomenon by adding in components which have actually no physical meaning inside the chip. The maximum output current Of the SG137 is an example of this. Perhaps, to a degree, adding an output resistor to model output resistance is also an example of this. Caution must be exercised when using this technique. This technique deviates the model from a functional block approach. It works well in the SG137 because the short circuit current circuitry is normally ofi‘ and does not affect the circuit under normal operating conditions. Once the structure has been developed, choosing component values presents yet another problem. Techniques in choosing component values range from empirical to symbolic. The symbolic techniques are beyond the scope of this dissertation. Ideally, each component would be chosen by formula. These formulas would be derived from the measured characteristics. The guidelines presented are some fundamental guidelines which can bring a 305 macromodeling problem to a manageable technique. CHAPTER 9 CONLUSIONS This dissertation presents the development of five voltage regulator macromodels. The macromodels are developed for use in the circuit simulator PSpice. The models developed are for five representitive topologies in the voltage regulator family. Chapter 3 gives the development the macromodels for the SG7 805 and SG7 812 voltage regulators. This represents a model for a fixed, three terminal, positive voltage regulator. Chapter 4 gives the development of the SG7915 voltage regulator macromodel. This represents a model for a fixed, three terminal, negative voltage regulator. Chapter 5 and 6 gives the development of the UA723 and CA3085 voltage regulators. These are programmable, positive, 8 and 10 terminal devices. Finally, Chapter 7 gives an example of an adjustable, three terminal, negative voltage regulator. These regulators can easily be adapted to other models of voltage regulators sharing the same functional blocks. For each model, the room temperature model is developed, as well as models for -55°C and 125°C. This represents the range of military temperature specifications. For a much stronger temperature dependent model, data would be gathered for more temperatures. The parameters of the macromodels would then be fitted to this set of temperature data. The temperature set used in this dissertation represented a set of three data points. Three points were chosen because of many of the PSpice defined temperature variable parameters had a built in quadratic dependence. Also, the three 306 points represented a complete range of temperatures. However, in many circumstances the temperature dependent phenomenon is well behaved, and not much more than a "three-point" curve fit is required. The temperature work presented lays the basis for much stronger temperature modeling. Chapter 8 provides some useful ideas and guidelines that were used in designing the macromodels. The future of macromodelling lies in the ability to systematically generate accurate macromodels which reflect ambient as well as self-heating effects. The macromodels must be conceptually easy to understand as well. Macromodeling needs for its advancement the following. Continued advancement in the area of computer-aided design of electronic circuits. It is stated in the first chapter, that computer Simulations are not a replacement for breadboarding. DeveIOpment must proceed along the path of bridging the gap between breadboarding and computer simulation. This is an enormous task, however the path is clear. When this happens, more circuit designers can use a macromodel for an IC or a number of IC’s in a computer simulation and make confident decisions based on the simulation results. Computer simulators, in particular, PSpice needs more development. In macromodeling, more flexibilty is desirable. Consider for example the limitation of the quadratic temperature dependence of the passive components. If an unlimited order were available, more accurate temperature models could be generated. Complex user defined devices should also be available, although this is somewhat available with the device equations options in PSpice. 307 BIBLIOGRAPHY BIBLIOGRAPHY [1] Nagel, L.W., "SPICE 2: A Computer Program to Simulate Semiconductor Circuits," Univ. of California, Berkeley, ERL-M520, May 1977. [2] Boyle, G. R., Barry M. Cohn, Donald 0. Pederson, and James E. Solomon, "Macromodeling Of Integrated Circuit Operational Amplifiers," IEEE Journal of Solid-State Circuits, Vol. SC-9, no. 6, Dec 1974, pp.353-364. [3] Krajewska, Grazyna, and Frank E. Holmes, "Macromodeling of FET/Bipolar Operational Amplifiers," IEEE Journal ofSolid-State Circuits, Vol. 80-14, no. 6, Dec 1979, pp. 1083-1087. [4] Turchetti, Claudio, and Guido Masetti, "A Macromodel for Integrated All-MOS Operational Amplifiers," IEEE Journal of Solid-State Circuits, Vol. SC-18, no. 4, Aug 1983, pp. 389-394. [5] Alexander, Mark and Derek F. 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