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This is to certify that the

thesis entitled

0P AMP MACROMODELS

presented by

RAOUDHA HAMZA

has been accepted towards fulﬁllment
of the requirements for

Master's Electrical

degree in

 

 

Engineering

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OP AMP MACROMODELS
By

Raoudha Hamza

A THESIS
Submitted to
Michigan State University
in partial fulﬁllment of the requirements
for the degree of

MASTER OF SCIENCE

Department of Electrical Engineering

1992

ABSTRACT
OP AMP MACROMODELS
BY

Raoudha Hamza

In this thesis, the circuit analysis and basic operations of two different op amp
macromodels are described. One is called microsim model and the other one is called
linear technology model. Some macromodel design procedures are presented, that enables
the macromodel parameters to be found from typical data sheet or easily measured
characteristics. Numerical examples are included using the M741, LM124, LF411,
LF355 and LTClOSO. Some inaccuracies of the two models are explained followed by
the device level performance. Finally some improvements of these models are proposed.
The improvements include supply current, power supply rejection ratio, clipping voltage

and common mode rejection ratio.

To my parents and my dear husband.

ACKNOWLEDGMENTS

My. gratitude to professor G.M. Wierzba for his guidance and assistance in
completing this thesis.

My appreciation to Shoba Krishnan for her help in drawing the diagrams.

iv

I.

II.

111.

TABLE OF CONTENTS

LIST OF FIGURES
LIST OF TABLES
Introduction
1.1 Introduction
1.2 Boyle model
1.3 Thesis summary
Microsim model
2.1 Introduction
2.2 Circuit Component and Operation
2.2.1 Input stage
2.2.2 Intermediate stage
2.2.3 Output stage
2.3 Preview
2.4 The NPN Bipolar Input Stage Macromodel
2.4.1 SPICE test circuits
2.4.2 Model formulas
2.4.3 Design procedure
2.4.4 Numerical example
2.5 PNP Bipolar Input Stage Macromodel
2.5.1 SPICE test circuits
2.5.2 Model formulas
2.5.3 Design procedure
2.5.4 Numerical example
2.6 IFET Input Stage Macromodel
2.6.1 SPICE test circuits
2.6.2 Model formulas
2.6.3 Design procedure
2.6.4 Numerical example
Linear Technology Model (LTC)
3.1 Introduction
3.2 Circuit Component and Operation
3.2.1 Input stage
3.2.2 Intermediate stage

<
:2

N .

\qu Ch mum eh
.__caoo8‘....u.e§2}.".o“ooo~n

3.3
3.4

3.5

3.2.3 Output stage

Preview

JFET Input Stage Macomodel
3.4.1 SPICE test circuits
3.4.2 Model formulas

3.4.3 Design procedure
3.4.4 Numerical example
MOSFET Input Stage Macromodel
3.5.1 SPICE test circuit
3.5.2 Model formulas

3.5.3 Design procedure
3.5.4 Numerical example

. Inaccuracies and Improvements of the Model

4. l
4.2

4.3
4.4

4.5

4.6

4.7

5.1
5.2

Introduction

Supply Current Test

4.2.1 Microsim model

4.2.2 LTC model

The Effect of BOND in the Microsim Model
Power Supply Rejection Ratio (PSRR)
4.4.1 Microsim model

4.4.2 LTC model

Clipping Voltage

Common Mode Rejection Ratio (CMRR)
4.6.1 Microsim model

4.6.2 LTC model

Numerical Example

. Conclusion and Future Research

Conclusion
Future Research

APPENDIX A: List of SPICE files

vi

71
72
72
74
75
91
95
98
100
101
107
110
114
114
114
115
117
118
119
119
122
124
126
126
129
130
131
131
131
134

1.1

2.1

2.2

2.3a
2.3b
2.4a
2.4b
2.5a
2.5b
2.6a
2.6b
2.7a
2.7b
2.8a
2.8b
2.9a
2.9b
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
3.1

3.2

3.3

LIST OF FIGURES

Boyle macromodel

Microsim macromodel of the uA741
uA74l full device

Test circuit for do transfer curve ’
dc transfer curve

Input bias current (macromodel)
Input bias current (full device)

Open loop test circuit

Open loop gain and phase margin
Output impedance test circuit

Output impedance versus frequencies
Common mode test circuit

Common mode gaim of the uA741
Short current test circuit

Short current of the uA741 macromodel
Slew rate test circuit

Slew rate of the uA741

Collector currents of Q1 and Q2
Voltages at node 6 and 7

Input stage differential mode

More simpliﬁed input stage DM
Currents in F. and v,

The resistance seen by c2

A simpliﬁed common mode input stage
Currents through c2 and r02

Currents through F., g,, v", and VI,
Currents through F.” g, and dc
Microsim macromodel of the LM124
Microsim macromodel of the LF411
Drain current of jl and j2

LTC macromodel of the LF355
LF355 full device

Drain current of jl and j2

vii

10
11
12
13
13
14
15
16
16
17
17
18
18
19
19
20
20
23
24
26
28
32
35
36

47
55
56
69
73
77

3.4
3.5
3.6
3.7
3.8
4.1a
4.1b
4.2a
4.2b
4.3
4.4
4.4a
4.4b
4.4c
4.5a
4.5b
4.6a
4.6b
4.7
4.8a
4.8b
4.9a
4.9b

Voltages at node 8 and node 1

Intermediate stage at UM input

Resistance seen by c2 '

The current flowing through g, and g.

LTC macromodel of the LTClOSO

The supply current of the uA74l (full device)
The supply current of the uA74l macromodel
The new output stage circuit

The supply current of the modiﬁed macromodel
Supply current of the modiﬁed LF355 macromodel
PSRR test circuit

PSRR of the uA741 full device

PSRR of the uA741 macromodel

PSRR of the modiﬁed uA741 macromodel

PSRR of the LF355 full device

PSRR of the modiﬁed LF355 macromodel
Clipping voltage of the uA74l full device
Clipping voltage of the modiﬁed macromodel (uA74l)
Additional components used for CM response
CM response of the modiﬁed macromodel

A more improved CM response

CM response of the modiﬁed LF355 macromodel
A more improved CM response

viii

78
79
81
88
99
115
116
119
117
118
119
120
121
122
123
123
125
125
128
129
129
130
130

2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3.1
3.2
3.3
3.4
3.5
4.1
4.2
4.3
4.4
A.l
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A. 10
A.11
A. 12
A. 13
A. 14
A. 15
A. 16

LIST OF TABLES

SPICE ﬁle of the uA741 macromodel
SPICE ﬁle of the uA741 full device
Parameters of the uA74l

SPICE ﬁle of the LM124 macromodel
Parameters of the LM124

SPICE ﬁle of the LF411 macromodel
Parameters of the LF411

Revised parameters of the LF411
SPICE ﬁle of the LF355 macromodel
SPICE ﬁle of the LF355 full device
Parameters of the LF355

SPICE ﬁle of the LTC1050 macromodel
Parameters of the LTC1050

Values of the additional offset (uA741)
Values of the additional offset (LF355)
Values of the clipping voltage (uA74l)
Parameters of the original and modiﬁed uA74l macromodel
SPICE ﬁle of Fig. 2.3a

SPICE ﬁle of Fig. 2.5a

SPICE ﬁle of Fig. 2.6a

SPICE ﬁle of Fig. 2.7a

SPICE ﬁle of Fig. 2.8a

SPICE ﬁle of Fig. 2.9a

SPICE ﬁle of Fig. 2.14

SPICE ﬁle of Fig. 2.19

SPICE ﬁle of Fig. 2.22

SPICE ﬁle of Fig. 3.3 & 3.4

SPICE ﬁle of Fig. 3.7

SPICE ﬁle of Fig. 4.1a

SPICE ﬁle of Fig. 4.1b

SPICE ﬁle of Fig. 4.2b

SPICE ﬁle of Fig. 4.4a

SPICE ﬁle of Fig. 4.4b

10

47
53
54
66
67
70
74
98
100
1 13
122
124
126
131
134
134
135
135
135
136
136
136
136
136
137
137
137
137
137
138

A.17 SPICE file of Fig. 4.4c 138
A.18 SPICE ﬁle of Fig. 4.6a 138
A.19 SPICE file of Fig. 4.6b 138

CHAPTER 1

Introduction

1.1 Introduction

Electronic circuit simulators have certain limitations, such as the maximum number
of nodes, devices, elements, etc. These limitations are established either by memory
limitations or convergence problems. Even if adequate simulaters and computers are
available, nowadays the required simulation time makes the analysis impractical for the
design engineer. Therefore, the idea and use of macromodels in electronic design arose
since 1970’s. The purpose of the op amp macromodel is to provide an adequate pin for
pin representation of op amp and to represent the electrical characteristics of the
operational ampliﬁer. Since the macromodel components are selected based on data sheet
speciﬁcations, this allows the designer to accurately model a speciﬁc IC based on
laboratory measurements.

A macromodel for all bipolar operational ampliﬁer was developed by GR Boyle,
B.M cohn, D.O. Pederson and LE Solomon [1]. This macromodel is referred to it as the
Boyle model. Since this paper was published, the area of op amp macromodeling has

been of interest to many SPICE users [6], [9], [2]. Later on the MOS bipolar and JFET

1

2

bipolar op amps were presented based on the original Boyle model [3] and others have
worked on improving the Boyle model such as in [l 1], [9], [4], [2]. In all the work, the
design procedures were not developed and sometimes even the design formulas were not
derived such as in [9], [2]. The main focus of this thesis is to present a complete analysis
of two macromodels one called the microsim model [9] and the other one is called the
linear technology model [2]. These two models were published with no design formulas
or design procedure. This thesis includes all the necessary design formulas of these two
macromodels. A design procedure is established so that given the op amp speciﬁcations

one can determine its macromodel parameters in a systematic way.

1.2 Boyle Model

The circuit diagram of the op amp Boyle macromodel is shown in Fig. 1.1. This
model is divided into three stages. The input stage consists of two ideal transistors,
sources and some passive elements. This stage produces the necessary linear and non-
linear differential mode (DM) and common mode (CM) input characteristics. In addition,
this stage is designed to have a unity voltage gain to reduce the complexity of the design
equations. The intermediate stage produces the DM and CM voltage gain. Also a
capacitance c2 is used at this stage to control the frequency and slew rate performances.
The output stage provides a do and ac output resistance for the op amp, the desired output
voltage swing limits and is responsible for limiting short circuit output cunent. Since

then, this strategy has been adapted by most of the op amp macromodels with of course

some improvements.

 

     
   
 

 

 

r L
-' vc
2 dc
c
Vb [’0‘
0' ‘ L I! ‘L “ ‘ “ out
I\
r02
r01 r02 ,2 do
at , d.
can vcm on v. ab vb
C. $ _' v.
roe
v V vout

 

(a;

Figure 1.1 Boyle macromodel
1.3 Thesis Summry

This thesis concentrates on the analysis of two different designs of op amp
macromodel: one called the microsim model, in chapter 2 and the other one called the
linear technology model, in chapter 3.

Chapter 2 itself includes three different types of op amp macromodels: npn input
stage macromodel (nA74l), pnp input stage macromodel (LM124), n-channel JFET input
stage marcomodel (LF411).

Chapter 3 also includes two different types of op amp macromodels: p-channel

4

JFET input stage macromodel (LF355), PMOS bipolar input .stage macromodel
(LTC1050).

In each of these chapters, the schematic diagram and its corresponding SPICE ﬁle
of each op amp macromodel are provided followed by a set of SPICE test circuits to
measure some of the typical op amp macromodel characteristics. Then, the design
equations of each macromodel are derived with details which allows us to develop a
systematic general design procedure for each type. Finally, a numerical example is used
to verify the accuracy of the derived design equations by comparing the calculated
measurements with the simulated ones.

Chapter 4 includes some models inaccuracies and some improvements to the two
models.

Chapter 5 includes the conclusion and further research.

CHAPTER 2

Microsim Model

2.1 Introduction

In this chapter, the structure and basic operations of an op amp macromodel called
the microsim model are described. The schematic diagram of an npn bipolar input stage
macromodel (uA74l) is shown in Fig. 2.1 as well as its SPICE ﬁle in Table. 2.1 [9]. The
choice of the macromodel parameters are determined and explained later in other sections.
This macromodel is designed by using elements inherent to SPICE such as ideal
controlled source stages instead of transistors, and generally minimizes the number of pn
junctions [1]. Two basic controlled sources dominate the microsim model: the voltage
controlled voltage source (VCVS) and the voltage controlled current source (VCCS).
This macromodel should represent the circuit behavior of an IC op amp for nonlinear dc,
ac, and large signal transient responses.

The microsim model is fundamentally similar to the Boyle model [1] but with further
adaptation such as the intermediate stage and the short circuit current limiter. However,

the input stage and the voltage limiting circuit remain almost the same.

 

 

 

 

 

 

 

 

 

 

Figure 2.1 Microsim macromodel of the uA741

Table 2.1 SPICE ﬁle of the uA74l macromodel

*CONNECTIONS: + - VP+ VP- VOUT
.SUBCKT UA741 1 2 3 4 5

Cl 11 12 8.661E-12

C2 6 7 30.00E-12

DC 5 53 DX

DE 54 5 DX

DLP 9O 91 DX

DLN 92 90 DX

DP 4 3 DX

EGND 99 O POLY(2) (3,0) (4,0) 0 .5 .5
FB799POLY(5)VBVCVEVLP

+ VLN

+ O 10.61E6 -lOE6 10E6 10E6 -10E6
GA 6 O 11 12 188.5E-6

GCM O 6 10 99 5.96lE-9

IEE 10 4 DC 15.16E-6

HLIM 90 O VLIM 1K

Q1 11 2 13 OK

Q2 12 1 l4 QX

R2 6 9 100.0E3

RC1 3 11 5.305E3

RC2 3 l2 5.305E3

REl 13 10 1.836E3

RE2 14 10 1.836153

REE 10 99 13.19E6

ROI 8 5 50

R02 7 99 100

RP 3 4 18.16E3

VB 9 0 DC 0

VC 3 53 DC 1

VB 54 4 DC 1

VLIM 7 8 DC 0

VLP 91 0 DC 40

VLN 0 92 DC 40

.MODEL DX D(IS=800.0E-18 RS=1)
.MODEL QX NPN(IS=800.0E-l8
BF=93.75)

.ENDS

2.2 Circuit Component and Operation

The microsim model can be divided into three basic building blocks: input stage,
intermediate stage and output stage which includes the short circuit cunent and voltage

limiting. Each stage provides a certain characteristic.

2.2.1 Input stage

The input stage consists of two ideal transistors Q1, Q2, resistances, a capacitance
c1 and a current source noted I” or I”. This stage produces the necessary linear and
nonlinear differential mode (DM) and common-mode (CM) input characteristics and it is
isolated from the rest of the stages to simplify the modeling of the slew rate and
frequency response [3]. For simplicity and design ﬂexibility, the input stage gain was
chosen to be unity [1]. This normalization step increases the utility of the model by
simplifying design expressions for gain bandwidth product as shown in the model
formulas section. In addition, this unity gain enables other structures to be implemented
such as pnp and JFET input stages without changing the basic design equations [2]. Also
the two transistors are modeled in the SPICE with their simplest models which does not

include internal capacitances or resistances.

2.2.2 Intermediate stage

The elements g,, gm, Pb, r2, r02 and c2 provide the DM and CM op amp gain and
vary the frequency response characteristics. The capacitance c2 is used to provide the

necessary ac output resistance change with frequency [1].

2.2.3 Output stage

The output stage provides a dc and ac output resistance of the op amp by the two
resistances r02 and r01.
The short circuit current limiting which provides the desired maximum short

circuit current, 1”, consists of two diodes d db, two dc voltage souces v.9, vb and a

lp’
controlled voltage source hlilll which is controlled by the current flowing through r01. The

elements (1 v", provide the positive short circuit current 1,0,, while db, vIn provide the

lp’
negative short circuit current I».
The elements dc, vc and d,, v° provide voltage clamp circuits where the pair dc, vc

is for the positive voltage clamp and d,, V0 is for the negative voltage clamp.

2.3 Preview

The focus of the rest of the chapter is on developing expressions for the values
of the elements in the macromodel. This is done because the design formulas for this

model have not been published. The starting point is to use SPICE simulations of a given

9

macromodel to establish the basic design equations. Then, a general procedure is
developed for the prarneter and element values in the macromodel. Finally, the last step
is to check the design procedure by using a numerical example. This analysis is done for
a three different input stage macromodels: npn input stage macromodel (uA741), pnp

input stage macromodel (LM324) and n-channel JFET input stage macromodel (LF411).

2.4 The NPN Bipolar Input Stage Macromodel

One of the npn bipolar input stage macromodels is the uA74l. The schematic '

diagram is shown in Fig. 2.1 and the corresponding SPICE ﬁle is shown in Table 2.1.
Also, the schematic diagram shown in Fig. 2.2 is of the pA741 full device op amp and

its corresponding SPICE ﬁle is in Table 2.2.

2.4.1 SPICE test circuits

The SPICE test circuits are established using the uA74l macromodel. Since, the
uA74l full device is available, then there are additional SPICE test circuits to compare
the full device with its macromodel. The SPICE test circuits include transfer
characteristics, input bias and offset currents, open loop gain, output impedance, common

mode gain, short circuit current and slew rate.

!I

 

 

. o
3.2 99—;
9 16's;

9

 

 

 

 

 

Figure 2.2 11A741 full device

Table 2.2 SPICE ﬁle of the 11A741 full device

.SUBCKT UA7414 5 1 13 25
* + - Vp+ Vp- Vout

Q1 2 4 6 13 M1
Q2 2 5 7 13 Ml

Q3 8 3 6 13 M2

Q4 9 3 7 13 M2

Q5 8 10 11 13 Ml

Q6 9 10 12 13 Ml

Q7 1 8 10 13 M1

Q8 2 2 1 13 M2

Q9 3 2 1 13 M2

Q10 3 15 1413 M1
Q11 15151313 M1
Q12 16 16 1 13 M2
Q13A 21 16 1 13 M2 .25
Q13B 17 16 1 13 M2 .75
Q141212413M13
Q15 21 24 25 13 M1
Q16 19 18 13 Ml
Q17 17 18 19 13 M1
Q18 21 22 23 13 M1
Q19 21212213 M1
Q20 13 23 26 13 M2 3
Q21 20 26 25 13 M2
Q22 9 20 13 13 M1

Q23A 13 17 23 13 M2

Q23B 13 17 9 13 M2

Q24 20 20 13 13 M2

R1 11 13 1K

R2 12 13 1K

R3 10 13 50K

R4 14 13 SK

R5 16 15 39K

R6 24 25 27

R7 25 26 22

R8 19 13 100

R9 l8 13 50K

R10 22 23 40K

R11 0 13 50K

CC 17 9 30F

.MODEL M1 NPN (BF=200 IS=1E- 14
+ VAF=125 VIS=.75 RB=185 RC=15
+ CJE=.65P CJC=.36P TF=1.15N

+ TR=405N CJS=3.2P MJS=.5)
.MODEL M2 LPNP (BF=50 IS=lE-l4
+ VAF=50 VJS=.75 RB=500 RC=150
+ CJE=.1P CIC=1.05P TF=27.4N

+ TR=2540N CJS=5.1P MJS=.5)

. ENDS

 

1hr

wh

the

offs:

 

1 1
2.4.1.1 Tramfer characteristics

The circuit used for the transfer characteristics test is shown in Fig. 2.3a. Using
the cursor in SPICE, one can determine the input offset voltage, vi0 by reading the input
when the output is zero. Fig. 2.3b shows the transfer curve for the macromodel where
the input offset is measured to be -l9. 17 11V and the saturation voltages are v”, = 14.45
V and v”, = ~14.46 V. Also Fig. 2.3b shows the full device response where the input

offset voltage is measured to be 327 11V, v.m = 14.3 V and vow = -12.77 V.

 

 

Figure 2.3a Test circuit for dc transfer curve

 

0

mg.

 

svi

  
 

1
full device :
i
macromodel E
+

 

-sonuv -400uv -3anuv .2oouv -1iitv -33v 1000;—

Figure 2.3b dc transfer curve

2.4.1.2 Input bias and offset currents

Consider the circuit test of Fig. 2.3a. The input offset current, I“, is the difference
between the current at the positive and negative input of the op amp. In other words, it
is the difference between the base currents of the two bipolar transistors Q1, Q2 at the
input stage [7]. The bias current, IB is the average of the two input currents [7]. Fig.
2.4a shows the base currents for the macromodel where 18,, = 79.66 nA, ID, = 79.82 nA.
13+ is the current at the positive input and IE is the one at the negative input of the op
amp. Then, 1.0 = 0.16 nA. Fig. 2.4b shows the full device response where I1,, = 33.89

nA and 13, = 34.12 nA, then, L0 = 0.23 M and ID = 34.005 nA.

 

24.1,

”"5 tam

l3

 

 

 

 

 

 

 

 

 

 

100M? ¢ + +— 45 _T 4'
90am}- .3.
arm ; i .r 4. _ - _ L t - : ::
70nA+ ‘1
-snouv «cow . 311an 4011111: 4001111 -0uV wow
neuron . 18mm)
10

Figure 2.4a Input bias cunent (macromodel)
4011A? ¢ ¢ 4= ¢ #— —+
at“; 1.
IBM-@- 4:.
3m _ - _ :ﬁ ; k , Ar - - 2 4;
320A+ 4:.
30“; ¢ 4+ # 4; ¢ - =1;
-3uouv -2onuv -1now -DuV wow

40an «now
cleaner) - 131111.02) VD

Figure 2.4b Input bias current (full device)
2.4.1.3 Open loop gain

The circuit used for the open loop gain test is shown in Fig. 2.5a. Fig. 2.5b shows
the gain versus frequency and the phase versus frequency for both cases macromodel and

full device. The dc gain Am is equal to 105.9 dB, the 3dB frequency f0 is found to be

14
5.012 Hz. Therefore, the gain bandwidth product GBP which is deﬁned as the product

of Adm and f0 and is approximately equal to 988.57 KI-Iz [7]. Also, the unity gain
frequency, f”, is located at 891.3 KHz and the phase margin, (ppm, is 63.l°. For the full
device response Am, = 107.2 dB, the 3dB frequency fo is 3.286 H2 and the unity gain
frequency f1: = 825.4 KHz. Therefore, the GBP = 752.77 KHz. Also, the unity frequency

11 = 825.4 KHz and the phase margin q)” = 64,40,

 

 

Figure 2.5a Open loop test circuit

15

 

+
11'
11
it
1

---_¢.
I
I

10111 +
macromodel i

01 1

1 full device :

L _._.A._ 4. ..|__
.1 T_

e e vdbﬂ)
i'

\ I-

 

 

 

400$;-

 

I
4006+ -------- + ------- -o--- =e # =~r ¢ ¢
mm 1.011 1011 1000 1.0Kh 10th 10001 LM 1"!
e e vp(4) '
Frequency '

Figure 2.5b Open loop gain and phase margin

2.4.1.4 Output impedance

The output impedance is measured by using the circuit shown in Fig. 2.6a where
the input is grounded and a test current IT is applied at the output. The variation of the
output impedance versus frequency is shown in Fig. 2:6b for both macromodel and full
device of the 11A74l.

At low frequencies, the output impedance for the macromodel is measured to be
151.7 0 and is called the dc output resistance rm. At high frequencies it becomes
constant and is called ac output resistance, rm and is equal to 50.4 0. For the full device

case, PM: = 98.32 9 and rm = 87.17 (2.

 

 

 

Figure 2.6a Output impedance test circuit

1601- --------- -+ --------- -+ --------- +-- 4 4 4
I

  
 

macromodel

 

frﬁl devae - ‘11

 

100m: Con
o .vmnur)

_.I..

10h 1311» 1.3111 131:» 11131111 1.1»:
Frequency

Figure 2.6b Output impedance versus frequencies

2.4.1.5 Common mode gain

The common mode gain test circuit is shown in Fig. 2.7a. The corresponding
simulation curves for both macromodel and full device are shown in Fig. 2.7b ( gain
versus frequency and phase versus frequency ). Obviously, the dc common mode gain
is not modelled at frequecies higher than 10 Khz. The common mode gain is measured

to be 15.89 dB = 6.23 for the macromodel and is 2.059 dB = 1.267 for the full device.

l7

 

\ICIH

 

Figure 2.7a Common mode test circuit

 

V— V' T _‘T— ‘7— _"
I I
I

a : full device 1,
-wmr macromodel T

-200
4006

 

L
_.'_

e eVDBU)

 

it it
it i
it 11

full

amrh-——..“-_‘* ’A—’/,//'/’ﬂ—_ﬁ\\\\device 1

macromodel -
"‘1 r

-2oo¢ i e
- -wuu

 

 

1.8% worth 1“ 1.0611
Frequency

ﬁgure 2.7b Common mode gain of the 11A741

2.4.1.6 Short circuit current

The short circuit current test is shown in Fig. 2.8a. A very small resistance (1 Q)
is connected to the output so the output is almost shorted. Fig. 2.8b shows the SPICE
response of the macromodel where the positive short circuit current is measured to be I,”

= 40.61 mA and the negative short circuit current is 1,, = -40.61 mA.

l8

 

r131

 

 

SM‘L .4— JL _.L_ 4_ 4 .L L
T 1— ‘7— 'T ’Y— V’ w 1—
I

 

 

 

 

 

 

 

 

 

 

 

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Figure 2.8b Short current of the 11A741 macromodel

2.4.1.7 Slew rate

The slew rate is an important large signal characteristic of the operational
ampliﬁer and it is usually measured for the unity gain buﬁ‘er ampliﬁer as shown in Fig.
2.9a. The corresponding response is shown in Fig. 2.9b for both devices. As we can see
the full device has a jump at the rising edge, which is not modeled correctly by the

macromodel.

l9

 

 

 

 

5.0V? ..... A: ¢ A¢= 4—
1

 

  
 
  
   

T T

movi i
5 full 1
device
2.0V? .1
o.ov+ .1
: model i
4.0% macro +
-4.0V'Ir +

 

 

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Figure 2.91) Slew rate of the 11A741

2.4.2 Model formulas

2.4.2.1 Slew rate

Consider the unity gain buffer ampliﬁer conﬁguration as shown in Fig. 2.9a, the

op amp input stage passes through several states. Fig. 2.10 shows the collector currents

of the two transistors Q1, Q2. From these SPICE simulations, we see that at the rising

20
edge of the input, Ql is cutoff and Q2 is active, while at the falling edge of the input Ql

is active and Q2 is cutoff. Also, Fig. 2.11 shows that the voltage at the node 6, v‘5 is

almost equal to zero and the voltage at node 7, v7 is almost equal to the output voltage,

vow

 

 

 

 

S.0V+- # --+— ------------- + ------------- -r
: :

5 s

5 a

5 E
------- +-—------------+----- +~ .

(t)
20 A --------------------------- + ------------- -+- ------------- + ------------- -f-

 

 

 

 

l

1

L‘D
41-

il‘ it
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Figure 2.10 Collector currents of Q1 and Q2

 

 

 

 

 

 

 

 

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Figure 2.11 Voltages at node 6 and 7

a) Positive slew rate, SR”

21

At the rising edge of the input when Ql is cutoff anf Q2 is active, the current
through the resistance rel, IW2 is almost equal to I“ and I,cl =- 0.
Also v, = v11 - v,2 = r,2 x I“. To simplify the design, the VCCS g, is chosen to be equal

to
1 1
ga:_:_
1.c2 1.c1
then, the current ﬂowing in the VCCS g, is equal to I“, that is

gave =Iee

Since v6 is a very small voltage and r2 is a large resistance, then most of the current 1,,

ﬂows through c2. The voltage across c2, vc2 is equal to

ch=v6 'V7 " “V7 ' -vout

 

then
Ieet
v =-__ =-v
c2 C2 out
and
Av I 2.1
SR ‘= ”=3; ( )
At c2

b) Negative slew rate, SR‘

At the falling edge of the input when Ql is active and Q2 is cutoff, Q1 is Operating
as a source follower tracking the variation of the output voltage. r.Bl is a small resistance,
therefore the output is across ree which is a very large resistance. Then the current

ﬂowing through rM is almost equal to 1,, and

 

22
Incl-Ice.In:l

hence

Va=vrr -v12=Ieercl

Since v6 is a very small voltage. then most of Iee ﬂows out of c2, thus

I
- CC --
vc2-_t- vout
C2
and
SR'=- °°
C

2.4.2.2 Transistor parameters

(2.2)

The two transistors used at the input stage, Q, and Q2 are identical, therefore L0

is zero and IB is equal to the base current

In =Iar =IBZ

The saturation current 18,, IS2 of the transistors Q1, Q2 are also the same. The value of

[3, and B, for the two ideal transistors is obtained from the values of the base currents IBi

and I132 and the collector current ICl and IC2 where

1”
Ic1 =Ic2 3‘2"

Hence

 

23

I
= =__°°_ 2.3
131 [32 213 ( )

2.4.2.3 Input stage: rd, rd

The circuit of the input stage differential mode is shown in Fig. 2.12. The dc
voltage sources are grounded while the dc current source are open circuit. Using Bartlett’s
Bisection theorem [8], the common nodes are left grounded. Then, the circuit of Fig 2.12

becomes that shown in Fig. 2.13.

 

vdm/2

 

 

Figure 2.12 Input stage differential mode

 

 

24

 

Figure 2.13 More simpliﬁed input stage DM

At low frequencies, cl is an open circuit then, the voltage vl2 is equal to

vdrn
+re2(B 2 +1»

 

v12=-BzcmIBz=-Bzrcz 20,”

where r,,2 is the small signal input resistance between base and emitter, looking into the
base [7]. Since v12 = “’11 then v. = —2 V”. The input stage gain Ad is chosen to be one

as was explained previously, then

A,1=_ﬂ’°*__=1 (2.4)
(’e*’ea(P-.+1))

Through all the analysis, the subscript i could be 1 or 2 because the input stage is

perfectly symmetric. Using the above equation 1'ei is equal to

r -r (2.5)

ei“ e1

_1
gm

where

25

. Bi+l
l3.

and guni is the transconductance deﬁned as follows

-1

 

VT =1'
C'

.=_ _’“ (2.6)
gun I‘ 131

la: lee/2 is the collector current, vT = K T/q = .02583 V at T = 300K [7].
The current controlled current source F, is a polynominal set of currents ﬂowing
through 111 do voltages vb, vc, ve, v,p and vIn with at, a,, a3, a4 and as are respectively the

real coefﬁcients.

Fb=allvb+a21vc +a31ve+a4lvlp+a51vln (2'7)
When the op amp macromodel is operating in the linear region, the current ﬂowing

through Fb becomes equal to

Fb =alIvh (23)

Equation 2.8 is also veriﬁed by using SPICE. The test circuit used is the same as in Fig.
2.9a where the input does not exceed the saturation voltage (vin = 1 V). Fig. 2.14 shows

that the current in Fb is almost equal to equation 2.8.

 

and

"Sing CQU;

81““ the j

 

Hen” the

 

 

 

I
42”;- + #

 

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I.

Figure 2.14 Currents in Fl, and v,,

At dc, c2 is an open circuit, then v6 becomes equal to
v6=-gever2=-lvbr2
and
v.,----Fbroz--vom (2.9)
using equation 2.8, v7 becomes
v7 =alIWroz=alguv‘r02 (2.10)
Since the input stage gain A,l = 1 then v, = van, and from equation 2.9 and 2.10

vom=algerozvdln

Hence, the dc gain Am is

Adrnogalgeroz (2'1 1)

The previous analysis holds for very low freqeuncies where c2 is an open circuit, but at

 

higher
0116 C3]

applied

From et

a, is usu

and thee

because a

“he”: {0 is

frequcncy,

 

27

higher frequencies 02 becomes short and a pole occurs. The pole is found by using the
one capacitor method [8]. To solve for the resistance seen by c2, a test current source is
applied in parallel with the capacitance c2 creating a voltage drop called vx (see Fig. 2.15).

Also, Va... is set to zero, then v1 = 0,

vx=l r +r (Pu-Ix)

x2 02

From equation 2.8

vx =Ixr 2 +r02(aIIx +Ix) ~

al is usually much larger than 1, then

Vin-Ix“ 2 +311. 02)

and the above equation could be also approximated

vx .1xalr02

because a, x r02 is much larger than r2, hence the resistance seen by c2 is al x r02, then

1

g (2.14)
0 (zuczarroz)

where f0 is the frequency at which the dominant pole occurs and it is also the 3dB cutoff

frequency. Thus, the gain bandwidth product is

GBP=i (2.15)
211:c2

28

pd

r02

 

Figure 2.15 The resistance seen by c2

2.4.2.4 Input offset voltage: vi0

Even though the input offset is meant to be zero in this type of 0p amp
macromodel the value is measured to be -19.17 11V. This offset is due to the voltage
across re, which is fedback to the VCCS gm at the intermediate stage. In order to ﬁnd
an expression of the input offset, the positive and negative inputs of the macromodel are

grounded, then an expression of vom is established where

v. :- °"‘ (2.16)

 

Since the input stage is perfectly symmetric, then the voltage at the node 10, v10, is equal

to

vb,i is the base emitter voltage of the forward bias transistors Ql or Q2 and is deﬁned as

follows

29

”gvm— 21S)

IS is the saturation current of the transistor Q1 and Q1. Since vin = 0 V then v, = 0 V and

the output voltage is found to be

=gcmvcrnrozal +V99

v99 is the voltage at the node 99 and if the power supply are equal in magnitude then
v99 = 0 V because EGND is averaging the power supplies. vcm is the voltage drop across
rec, thus it is the difference between v10 and v99, using equation 2.16, the expression of vi0

is as follows,

 

g... 1..
v‘.=— 2 .. NAM-513- Ishvel-rv

ge l.02a919ge

2.4.2.5 Input stage: I, and r,

The value of the dc current source at the input stage for equal collector current is

 

+1
I”=2( BB )IC--21C

The resistance r,, is added to previde a ﬁnite CM input resistance. Because the current
source I” is often realized with an npn transistor, the resistance rea is taken as its output

resistance,

30

. V
r =_‘
I”

where VA is the early voltage of the device [1]. VA for a small npn is typically 200 V.
2.4.2.6 Input stage: cl

From Fig. 2.5b and Fig. 2.12, a second pole occurs at f,. Using the one capacitor

method

1

(2.17).
41trczcl

f:

2

 

cl is added at the input stage to introduce the excess phase effects in the DM ampliﬁer
response [1]. The excess at f2 due to the non-dominant second pole is A41 deﬁned as

follows

A¢=90°-¢m

where on, is the phase margin of the DM open-loop response.

f
manna;

2

Substituting equation 2.17 into the above equation [8]

tan|A¢|=41tr cf

c2111

Then, the necessary value of C1 to produce the second pole is

 

2.4.2.

dc cun

Where

Slncc rec

The mum

31

_tan|90°-¢Pm|

1
41tfnrc2

 

2.4.2.7 Interstage: g,

(2.18)

For CM response and after using the Bartlett’s theorem, becomes that shown in

Fig. 2.16 where the common nodes are left open, the dc voltage sources are grounded and

dc current source becomes open circuit.

At low frequencies 02 is an open circuit and

vm=2r°e([3i+l)ibi

where

Vern

1”: r,“ +(Bi+1)(r°i+2ru)

 

Since tee is a very large resistance, then ibi could be approximated to

V
- cm

"" (15195211.;

Substituting equation 2.20 into 2.19

V‘V

10 cm

The current ﬂowing through r2 is equal to

Ivb = -gcmvcm

Substituting the above equation into equation 2.9

(2.19)

(2.20)

32

voutgalgcmrozvcm

Hence, the common mode gain, Ann is

Acm=alg r (2.21)

cm 02
The common mode rejection ratio (CMMR) is deﬁned as the ratio of the DM gain to the

CM gain [7], that is

CMMR= (2.22)

 

 

Figure 2.16 A simpliﬁed common mode input stage

2.4.2.8 DC power drain

To model the actual dc power dissipation of an op amp, a resistance r, is added

into the macromodel [l]. The power dissipation is

33
The necessary value of r, to produce this dissipation is

_ 2
r = We V1») (2.23)
P Pa‘(Vp.'Vp.)Iee

 

The diode dp is used across rP for modeling the case of possible conduction. This can
occur with incorrect power supply polarities. Also the diode d, has an ohmic resitance

noted as r, and chosen to be 1 Q to avoid the convergence problem.

2.42.9 Output Stage: re, and r02

The output stage provides the do and ac output resistances. From Fig. 2.6b, the

output resistance at low frequencies (dc output impedance) is

ro-dc =rol +1.02 (224)
At high frequencies, 02 is short and the ac output impedance is
rHc=r01 “Tani-1152) (2.25)

Since al is very large, then

‘1'

o-ec ol

34
2.4.2.10 Output stage: current limiting

a) Sourcing current: I,”
The positive short circuit current, I”, is a sourcing current that occurs for positive
output voltages. When the input and output do not exceed the saturation voltage of the

op amp, the expression of the CCCS F. becomes as follows

F =a I aI (2.26)

b 1 via... 4 vlp
The current I", is used to absorbs the current ﬂowing in Fb. The current ﬂowing in r0,
is I,” and from the SPICE simulation (see Fig 2.17) the current ﬂowing through c2 is

almost zero, that is

(2.27)
gave=-Ivb =1ee
and
I' I
Fb=-(1+_°_)Ix. (2.28)
1' 02

Since I” and I,” are positive currents, then the two above equations show that, I“, and F,
are negative currents. From equation 2.11, the coefficient al is found to be a very large
positive number. Thus the product of al and L. is a large negative current. Also I“, is
deﬁned to be a positive cunent In order to make F. a small internal current, the product
of a. and 1,“, has to be positive. Thus a has to be positive coefficient and close to but

smaller than al so that F" is still negative current and satisﬁes equation 2.28.

I
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e 1(X1.C2

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1

 

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Figure 2.17 Currents through c, and r02

The CCVS h“In is deﬁned as

hm=alvm=alx.
a is a constant coefﬁcient and usually selected to be equal to l K. On the other hand,

h“In is the summation of the voltage drop v4.1, across the diode 11., and the dc voltage

source vw. Therefore

“Perv-v“, (2.29)

The voltage v", could be solved once Va, is determined and I”, is speciﬁed. The voltage

van, is related to the current ﬂowing through the diode (1,, which is equal to 1“,, that is

v =v (IV'P)
dip TlnIS

41?

 

where 184,, is the diode saturation current of the diode, (1,, speciﬁed in SPICE program
as IS and is arbitrarily chosen to be 8E—l6 A. The value of L", is determined by equating

equation 2.26 and 2.28, that is

36

I.
rug-.141 +_?.‘.)1m+3‘.1u
a4 1.02 4

Since a. is usually a large coefﬁcient, then the above equation is approximated as follows,

Hence

a’llee

vdlp =len( ) (2.30)

 

a4ISmP

Finally, by substituting equation 2.30 into 2.29, the expression of v“, is established

 

a I
=(xI .-v n 1 °° (2-31)

All this analysis is checked by using SPICE (see Fig. 2.18).

 

 

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11
i
1

 

 

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it it
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L
T
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T
v
w i

L

 

 

 

A_

Figure 2.18 Currents through F,, g... v“, and V,
b) Sinking current: I»

The negative short circuit I» is a sinking current that occurs at negative output

37

voltages. When the input and output do not exceed the saturation voltage of the op-amp.

the expression of the CCCS Fb becomes as follows

Fh-—-allw+aslv (232)
Now, the current ﬂowing through rol is I”, and from the SPICE simulation (see Fig. 2.17),

the current ﬂowing through c2 is almost zero, that is

g‘v‘=-I =—I (2.33)

and

1'
[she-(1 + °' )1“, (2.34)

1‘02

 

Since I“, is a negative current then, the two above equation show that, In, and F, are
positive currents. The product of al and Lb is a large positive current. Also the current
L1,, is deﬁned to be a negative current. In order to make Fl, a small positive internal
current, the product of as and I,“ has to be negative. Thus a5 is a negative coefﬁcient and
close to but smaller than a. If the negative short circuit current is equal in magnitude
to the positive short circuit current, the 214 is equal to the absolute value of a,.

The CCVS hat. is now deﬁned as

Also

lirn = -vln -vdln

then

v =-al _-v (2.35)

The voltage vIII could be solved once len is determined and I“, is speciﬁed. Following
the same methodology done previously for the case of I”, the expression of vIn is found

tobe

a I
vm=—alx,-len(- is”) _ (2.37)

anIn

 

where [Sam is the saturation current of the diode db. It should be noted that I“, is a

negative quantity.

2.4.2.11 Output stage: voltage limiting

a) Positive voltage limiting
The positive output voltage is limited by the voltage by the voltage source diode
clamp combinations vc, dc. When the output clamps positively such as to forward bias

dc, a current ﬂows in the diode dc, Idc to absorbs the current ﬂowing in CCCs Fb, thus

FbgalIVb-a'zldc (2°38)
where It = - Ivc because in SPICE the current is deﬁned to ﬂow from the positive node

to the negative node. Also from the SPICE simulation (see Fig. 2.19), the current ﬂowing

in the VCCS g, is

gv=I

and the current Lb is approximately equal to 4”, then equation 2.38 becomes now

39
Fiﬁ-311” -a21dc

Since Idc is a positive quantity, then a2 must be a negative coefﬁcient to make F, a small
internal current and is close to but smaller than al in magnitude so that F, is still negative
small current as seen in Fig. 2.19. Therefore 1,, is approximately equal to

a
I --_‘.I”
‘° 3.
Since positive output voltage islimited by the voltage source diode clamp combinations

v,, d,, the clipping voltage is equal to

vm,=vp,-vc+v¢ (239)
where v,, is the voltage drop across diode dc. Since vW is speciﬁed (for the 11A741 is
measured to be 1:14.61 V), then the value of v, could be determined once v,, is

determined. This voltage is related to the current 1,, as follows

v -v (- all°")
dc" Tln azlsae .

 

[St is the diode saturation current of the diode d, and is set arbitrarily equal to 8E-16 A.

Finally using equation 2.39 and the above equation, the value of vc'is deﬁned as below

 

aIIee
Vc =VP+ -vset+ +len( - a213,, ) (2.40)

b) Negative voltage limiting
The negative output voltage is limited by the voltage source diode clamp
combination v,, d,. When the output clamps negatively such as to forward bias d,, v“,

is deﬁned as follows

 

 

Folio

found

when:

40
vm-=vp-+ve-vdc

Following the same methodology done in the case of the positive output clamp, v, is

found to be

V.=“’p -+vm-+v1.1n(

 

311» ) (2.41)
21.18..

where IS“ = IS,, and a3 is a positive coefﬁcient close to but smaller than a,.

2001M?

 

«more; +
n 1(XI .FB)
2111111; i

1I L—Lf’r L151“

 

 

 

 

~20uA 4 L *
. 0.51m
el(X1.DC) e 1.061.1(X1JEE)

Figure 2.19 The current through F,, g, and d,

2.4.3 Design promdure

A summary of the design equations for the macromodel parameters is developed
in this section. The following design procedure could be used for any op amp microsim
model with npn bipolar transistor at the input stage. The starting point of the design is

to have values of the typical response characteristics of the corresponding op amp, that

41
is, the following speciﬁcations are assumed available : SR”, SR‘, 1,, A...» f,, 63?, 111,“,

CMRR9 l-o-ee9 l.o-rlc’ Ive» Ise-r vat-w veer-9 and pd‘

Step 1: Choose 02 = c, where cc is used in the chip as a compensation capacitance.

Stev 2: , 1,3238. *
Step 3' [3- I”
21—

Step 4: Choose the saturation current 18 for the two transistors Q, and Q2 to be equal to

8E-16 A.
Step 5: rct=r.2=—-l——
271:GBPc2
Step 6 - I”
8..., .2;
Step 7: l-el=Te2='-rci_'—l'
81111

Step 8: Choose VA = 200 V, then 1- av;
. lee

c =m|90°’¢,..|
‘ 41tfr

ucl

Sup 9:

 

42

Step 10: g =_l_
‘ rc2
Step 11: g =__1_
°"' CMMRrcl

Step 12: Choose r2 = 100 k9.

Step 13' r -r r

02- o-dc - o-ac

Step 14: a = drno Cl

 

Step 15: Pick -a2 = a3 = a, = -a5 = a,, and then round them off.
Step 16: Choose the diode saturation cunent for all the diodes used in the model to be
equal to 8E-16 A and the diode ohmic resistance r, to be 1 (2.

Step 17: Choose or = l K.

 

 

a I
SICP 133 v =01 —v ‘ °°
1p sco Tln 34184.,
SICP 19' v --aI v1ln all”
'“ "’ aSISm
a I
Step 20: v = -v +v 1n— 1 9°

 

c 134» seto T

Step 21:

Step 22:

Step 23:

43

aIIee
a31S

 

ve =vp_ +vm_ +len
de

_ 2
.. (VP+ VIP)

9. p d -(vP,-vp_)lee

 

 

2.4.4 Numerical example

A numerical example is used to illustrate the development of the parameters of the
op amp macromodel and to verify the design formulas and procedure. This veriﬁcation
is done by ﬁnding the speciﬁcations of the model using the model formulas derived in
the previous section and the macromodel parameter’s values given in Table 2.1. Table
2.3 includes the calculated and the SPICE simulated measurements using the 11A74l

microsim macromodel as an example. A list of the equations used to ﬁnd the calculated

measurements are listed below.

1)

2)

1
SR :=_°:
c2
1
SR -=-_°:.

3)

 

 

I”
4) v.---ig°':—°°r-v.1n<—>+v..1-

 

 

 

 

 

l
5 f= -_
) ° 211:c2a1r02
6) Admo=alger02
7) GBP= g:
21cc2
8) = -f22+\/f2‘+4Amzf,2f22
" 2
l
where f2
4nr,,cl
9) -90' tan f“
- -arc _
0,. f2
10) e 1

   

 

reigcrn

11)

12)

13)

14)

15)

16)

17)

 

 

 

o-ec 0l
romits-1.01 1'02
I .--1—(Vt +Vr1n 1111,, )
5° (1 P 3418‘“?
1 ( r1“ all“
..___ v +V ——
sc- "' 3515111.
alIee
vsat+=vlﬁ 'Vc +V ..
321$,lc
+ 1.111 aIIee
v =v V ‘V
w- 9' ° a318,,
pd=(vP+-vp-)Iee+( P. P.)

45

45

Table 2.3 Parameters of the M741

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter Calculated Simulated
SR” 0.5053 v/us 0.5074 v/us
SR‘ -0.5053 v/us -0.4957 v/tts
vi0 -l9.24 11V —19.17 11V
1, 80.853 nA 79.742 11A
to 5.000 Hz 5.012 Hz
Ah, 106.02 dB 105.9 dB 11
GBP 1 MHz 988.57 KHz
f, 889.53 [(112 891.3 KHz
4),“ 62.81° 63.1°
CMRR 90 dB 90.01 dB
r“, 50 (2 50.4 (2
r,,,, 150 Q 151.7 Q
Let 40.614 mA 40.61 mA
1,, -40.614 mA -40.61 mA
vm 14.614 V 14.61 V
v“, -14.6l4 V 14.61 V
p, e 50 mW 50 mW I

 

2.5 PNP Bipolar Input Stage Macromodel

The pnp input stage microsim macromodel schematic is the same as the npn input

stage macromodel with of course pnp transistors replacing the npn transistors. This

causes the input stage to be ﬂipped over as it is seen in Fig. 2.20. This type of

macromodel has been adapted to many op amps such as: LT1013, LM324, LM124,

 

L1

1--

-Schk1
0

‘fort[

15.1 sp‘

maCIOmod

”amp is

47

LM158, LM224. LM258, LM358 ......

III—

VC

dc

out

 

do

I
I

 

 

 

 

 

 

 

 

 

 

 

v

-51.... 27.:
.1

Figure 2.20 Microsim macromodel of the LM124

Table 2.4 SPICE ﬁle of the LM124 macromodel

.subckt LM124 l 2 3 4 5
* + - vp+ vp- vout
* for the rest of the ﬁle see SPICE library version 4.02 July 1989

2.5.1 SPICE test circuits

The same SPICE test circuits established previously using the npn input stage

macromodel, now will be deﬁned using the pnp input stage macromodel. The LM124

op amp is used as the example. The summarized data of the SPICE test circuit

 

stag

the b
since

voltag

48

measurements are included in Table 2.5.

2.5.2 Model formulas

The only difference between the npn and pnp input stage macromodel is the input
stage. Even though all the previous analysis was done for the npn input stage, including
the design equations, the same formulas hold exactly for the pnp macromodel except for
the bias current and input offset voltage. The bias current is deﬁned as a negative cunent
since it is ﬂowing out of the base. The input stage is also symmetric, but due to the

voltage across ree the input offset is not zero and is deﬁned as follows

 

gem Iee ( Ice ) v99
v- =— —r o +v — _V -
IO ' 2 8| Tln 218 99] [.0231 g‘

2.5.3 Design procedure

A summary of the design equations for the macromodel parameters is developed
in this section. The following design procedure could be used for any op amp microsim
model with pnp bipolar transistor at the input stage. The Starting point of the design is
_ to have the following speciﬁcations of the corresponding op amp: SR”, SR‘, 1,, Am,
GBP, f,, q)”, CMRR, r,” r,,,, 1,”, 1”,, Va”, v”, and p,.

Step 1: Choose c2 = cc where cc is used in the chip as a compensation capacitance.

Step 2: 1,3288 :

 

'ﬁ

S1

8E

Ste;

Step

$th 7:

Step 9:

Step 10;

 

Ste1311:

 

5[5912: C

49

Step 3: 13... ..

 

Step 4: Choose the saturation current for the two transistors Q1 and Q, to be equal to

8E-16 A.
$181) 5: rcl=rc2=__i_
21tGBPc2
Step 6: .=_:
gm 2vT
Step 7: r =r =r .-_1_

Step 8: Choose VA = 200 V, then ,- =_V_A_
Ice

 

Step 9: c .m'90 -¢,..|
‘ 41tf r
[.1 cl
. 1
Step 10. g =—
. l.c2
Step 11' g =___l_
°° CMMltrcl

Step 12: Choose r, = 100 kg.

 

 

51

Su:
Ste;
equa

Step

518p ,

Step 11

Step 20

Step 21:

Step 22:

 

50

Step 13: l.02:ro--clr: -ro-ec
rol=To-ec
Step 14: a = Aho’cl

 

Step 15: Pick -a, = a, = a4 = -a5 = a,, and then round them off.
Step 16: Choose the diode saturation current for all the diodes used in the model to be
equal to 8E-l6 A and the diode ohmic resistance r, to be 1 9.

Step 17: Choose a = 1 K.

 

 

 

 

a I
Step 18: v mew-van ‘ °°
"’ a418,"?
Step 19' v --otr len 3‘1”
l“ “' a515,“
Step 20’ v -v +len all”
e - —v .-
c p+ sat+ 3218‘,
Step 21‘ v -v + + all“
. — v v
e 9" set- Tln 3318a
_ 2
Step 22.1- 2 (VPI VP.)

 

P pd-(vP,-vp_)lee

51

Step 23: E = p... 9'

 

2.5.4 Numerical example

This veriﬁcation is done by ﬁnding the speciﬁcations of the model using the
model formulas derived in the previous section and the macromodel parameter’s values
given in Table ‘ 2.4. Table 2.5 includes the calculated and the SPICE Simulated
measurements using the LM124 microsim macromodel as an example. A list of the

equations used to ﬁnd the calculated measurements are listed below.

 

1
1) 5112.:
oz
1
2) SR-=-_:°.
C2
3) I :_Iar+laz=__lee_
B 2 2

 

4) v. =§°_“.[_I°_°.r .+v.,ln .135.) -v,,]- V”
8

'° . 2 °‘ 21S roza1 g.
5) ff;
21tc a r

6)

7)

8)

where

9)

10)

11)

12)

13)

14)

52

A r

«no: lga 02

GBP=_;
21cc

 

 

dmoOZ

-f22+‘/f2“+4A 2f 2f 2

 

 

2
411trc2c1

, f
¢m=90 -arctan_"

CMMR

 

r cigcrn

l.o-Irc- 01

-. +
o-dc.rol I.02

 

SC.

I
I =i(v +vln ale‘)
a a1

allee )

1
I =-_(v +v -
9" ct '“ Tm 351311..

 

 

 

a1

15) v =v -v+v - 1”
8.19 p0 C Tln 3.218“

a1

16) v =v +v -v 1”
1 88‘- p' e Tlnajlsa
_ 2
17) p d =(vp, -vp_)lee +_(._"‘__i

53

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SR“ 0.503 V/us 0.4942 Was 11
SR‘ 0503 V/us -0.506 was 1'
I, -45.26 M -44.83 nA
fo 10.00 Hz 10.00 Hz
A“, 100 dB 99.91 dB
GBP 1 MHz 989.691 KHz
f, 982.577 KHz 962.4 KHz
(1),, 79.29° 79.5°
CMRR 85.43 dB 84.97 dB
r,_,, 50 £2 50 Q
r“, 75 (2 75.92 9
1,, 40.613 mA 40.61 mA
1,, -40.613 mA -40.6l mA
vm 14.113 V 14.11 V
11 v“, -15.6l3 v -15.61 v
99.55 mW 99.5 mW

 

54
2.6 JFET Input Stage

An other op amp macromodel designed by microsim is the n-channel JFET input
stage macromodel (see Fig. 2.21 ). Its schematic is very similar to the bipolar transistor
input Stage macromodel with of course JFETS j,, j, replacing the transistors Q,, Q,. This
macromodel has been adapted to several op amps such as: LF411, LF412, TLO82 and
TL084 ....... The only difference between these two macromodels is the input stage. The
intermediate and output Stages remain exactly the same as was described previously. The
input stage now has a two n-channel JFETS j,, j, instead of the two transistors Q,. Q,.
A capacitance cs, is added to produce the asymmetric slew rate. Since the input stage has

a unity dc gain, then the basic design equations remain the same.

Table 2.6 SPICE ﬁle of the LF411 macromodel
.subckt LF411 1 2 3 4 5

* + - vp+ vp- vout
* (for the rest of the SPICE ﬁle see SPICE library version 4.02 July 1989)

2.6.1 SPICE test circuits

The same SPICE test cicuits established using bipolar input stage macromodel,

now will be established using the n-channel JFET input Stage macromodel such as the

LF411. Table 2.7 provides the summarized data of the SPICE test circuits for the LF411.

55

 

POI

'2 E {if T 7 III
1?

 

 

 

 

 

Figure 2.21 Microsim model of the LF411

2.6.2 Model formulas

|1P

 

VC

dc

out

6.

V.

The basic operations and design formulas of a n-channel JFET input Stage

macromodel are described in this section.

2.6.2.1 Slew rate

Consider the op amp (LF411) in a closed loop circuit as in Fig. 2.9a with a pulse

at the input, the op amp passes through several states. Fig. 2.22 shows the input voltage,

and the drain current of jl and j,.

a) Positive slew rate: SR”

56
The SPICE simulation (Fig. 2.22), shows that on the rising edge of the input, j,

is active and jl is cutoff. The current ﬂowing in the VCCS g, is equal to I, . Then, the
current 1,, ﬂows out of c, because r, is usually a large resistance. The voltage across c,

is almost equal to the output voltage. Thus, the positive slew rate is found to be

 

 

 

 

 

 

SR 9. ss
c2
6.0V+ --------- -1- --------- -+ --------- ~0- --------- -+ --------- -+ --------- -+ --------- 1-
+ ------------------ -+ --------- -1- --------- 4» --------- -1- --------- -+ --------- -+
V(1)
200 A+ ------------------ -+ --------- -+ --------- -+ --------- -1- --------- -1- --------- -9-
I 1
l
u ------------------ -+ --------- -1- --------- -+ --------- -1- --------- -+ --------- -1-
e 10(X1 .J 1)
4000A+ --------- -+ --------- -+ --------- -+- --------- -+ ------ 4 --+ ---+
H 11
0uA+ --------- -1- ------------------ -1---- A —+ --+ --------- +
or 1000 20111 30w 4011a 5000 6011a 70110
e lD(X1.J2)
Tune

Figure 2.22 Drain current of jl and j,
b) Negative slew rate: SR’
At the falling edge of the input, the SPICE simulation (Fig. 2.22) shows that jl is

active and j, is cutoff. At this case jl is operating as a source follower tracking the

variation of the output voltage. The output voltage is all across the capacitor c”, then

D
<
D
<
H

SR-= 011- “-08

 

 

57

where 1,. is the current ﬂowing in 03,. Since the Slope is negative, then I,“ is negative
quantity and it is pumped out of c“. The current ﬂowing in r,,, 1“,, is equal to the

summation of 1,, and 1,“, then

Irdl=Iss +SR ’css (2.43)
From equation 2.42
1
SR ‘=_L"2_
CZ
but in this case
va=-rdllc2
Therefore
SR 2.121.
c

Then, using equation 2.43

-c2$R “=1“ +SR 'c“

that is

 

The capacitance c, makes the slew rate asymmetric. That is SR“ is larger than SR‘ in

magnitude.

58
2.6.2.2 JFET parameters

The JFET used at the input Stage are presented in SPICE program by the simplest
models which does not include internal capacitance and resistances.

The input currents ﬂowing in the gate ofj1, j, are due to the saturation currents
of both pn junctions. The required value of the saturation current speciﬁed in SPICE
program as IS could be established once the input offset and bias current are given. The
SPICE JFET model has two diodes connected to the gate. Thus the gate current, 13,, is

twice the saturation current,IS.,, of the corresponding JFET, that is

135-218, ‘

The input offset current, L, is the difference between the two base currents,

I.=I I

to 82.. BI

The bias current, IB is deﬁned as follows

I

131+1

3'2

82

 

then, the saturation current IS, for each IFET is found to be

1 I.
IS=_-I:_'°.
i2( 3 2)

In the case of the microsim model, the JFETs at the input stage are identical, therefore
Ii0 = 0, and ISl = IS, = IS.

As it was mentioned previously, the input stage gain has a unity dc gain, that is

 

Vt

59
A” =gmra= 1 (2.44)

where g,, is the transconductance deﬁned as follows
1
=2 .1
8... 113 2

gm= 1 (2.50)

using equation 2.44,

So obviously, the value of B could be established once the value of r,Ii is determined,

where

0: 1 (2.45)
2151' ,2

 

The input offset voltage, V, could be modelled as the difference in the threshold voltages
of the two JFETS used at the input. This threshold voltage in noted in SPICE program

as VTO, that is vi0 is equal to

vio=VTO1 -VTO2
where VTOl and VTO, are respectively the threshold voltage of j,, j,. Since jl and j,
have the same VTO, then v,, =' 0 V. So the microsim did not model the input offset
current and the input offset voltage fot this type of op amp macromodel. However from
SPICE measurement, it shows that vio is different from zero and that is because of the

voltage drop across r”. vi0 is found to be equal to

60

 

g Is: V99
vi0=- "n [ _-VTO +v -_
2131 21’ r,,ttl‘/2131ss

2.6.2.3 Input stage gain: r,

The intermediate and output stage design equations of the JFET input stage
macromodel are the same as the bipolar input stage macromodel except for some minor

changes due to the notation.
2.6.2.4 Input stage: r“

The resistance r“ is added for the same purpose as r“ in case of bipolar input stage

macromodel and is deﬁned as

VA

r-

“'7:

where VA is the early voltage of the device.
2.6.2.5 Intermediate and output stage

Since, the intermediate stage and output stage are exactly the same as the bipolar
op amp macromodel, the previous analysis holds for this op amp macromodel. Therefore,

the other design equation are the same as the bipolar input stage.

61
2.6.3 Design procedure

A summary of the design equations for the macromodel parameters is developed
in this section. The following design procedure could be used for any op amp microsim
model with a n-channel JFETS at the input stage. Given the following speciﬁcations:
SR‘, SR’, 1,, Am, GBP, f,, (ppm, CMRR, r,,,, r,_,,, 1,“, 1w vs“, v“, and p,, then the
design procedure is

Step 1: Choose c, = cc where cc is used in the chip as a compensation capacitance.

 

Step 21 Iss=c28R *
Step 3: c“: SIR _ 'Cz Assuming SR+ > -SR'.

Step 4: Choose the saturation current of the two JFETS to be equal to 12.5 pA and

 

vro = -1 v.
Swp5: .e 1
" chzGBP
. 1
Step 6. B:
21,34,2

Step 7: Choose vA = 200 v, then ,5;

c =tan|90°—¢pm|
1 41tfr

udi

Step 8:

 

62

Step 9: g =_1_
a rdi
“n —_-CMMeri

Step 11: Choose r2 = 100 k9.

Step 12: l.02.:ro-dr;“to-at:
rol=l.o-ac
Step 13: a = Amordi

 

Step 14: Pick -a2 = a3 = a4 = -a, = a1, and then round them off.
Step 15: Choose the diode saturation current for all the diodes used in the model to be
equal to 8E-16 A and the diode ohmic resistance r, to be 1 52.

Step 16: Choose on = l K

 

 

Step 17. v zalsu-len l °°
'9 a4ISdlp
Step 18' v --ot1 v1ln 3‘1“
" ”' 35154:.
. all“
Step 19. vc=vP+-vm.+len-

 

63

a1

Ice

21.13..

 

Step 20: v°=vp_+v -+len

sat

_ 2
Step 21: r = (VP V?)
P p d-(vw-vpﬁee

 

Step 22: E -.- P: P-

 

2.6.4 Numerical example

This veriﬁcation is done by ﬁnding the speciﬁcations of the model using the
model formulas derived in the previous section and the macromodel parameter’s values
given in Table 2.6. Table 2.7 includes the calculated and the SPICE simulated
measurements using the LF411 microsim macromodel as an example. A list of the

equations used to ﬁnd the calculated measurements are listed below.

 

I
1) SR ".=_.
CZ
I
2) SR -=- “
02w.

3) IB=-ZIS

64

4) gm [ I I” VTO vgg] v99
V.o="_.___ _' + "———
281 2" real/261..

5) f’:_______
0 21tczalro2

6) Admo =31 garoz
7) GBP=_g;
21tc2

 

 

f = 4; «I f 4 «Amiga;

 

 

 

2
8) p 2
l
where f2
41trdicl
9) -90' tanf"
¢pn' are E
10) CMMR= l
rdigcm
11) r =r

o-ac ol

12)

l3)

14)

15)

l6)

l7)

 

ro-ck.:=r01 ['02
1 [Ice
I“. a(vlpa-len )
4 clip

a1 ee

sc-= -_(vln +len --a-I—S_
5 din

 

 

v -v -v +len all”
3‘" a2IS‘lc
v -v +v len all”
sat- p- e 3313“

(v -vp_)2

pd =(vp* "VP )1” +_p_*__

65

66

Table 2.7 Parameters of the LF411

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter Calculated Simulated
SR” 17 was 19.6 V/us
SR‘ -11.975 V/us -15.07V/us
v.0 -6.69l pV -3.25 “V
IE -25 pA -40.32 pA
fo 20.000 Hz 19.95 Hz
Am. 106.02 dB 112 dB
GBP 4 MHz 7.942 MHz
fll 3.292 MHz 5.412 MHz
4% 55.37° 41.4°
CMRR 100 dB 106.07 dB 1
two 50 a so a I
PM. 75 0 76.38 9
1”, 25.675 mA 25.68 mA
Isc -25.675 mA -25.68 mA I
v.“ 14.175 V 14.17 V
v“, -14.175 V -14.17 V
pd r 65: mW 65.1 mW

 

 

 

Lots of the simulated measurements obtained in the above table do not match the

calculated measurements such as Adm, GBP, f", ow amd CMRR due to the wrong

deﬁnition of [3 used by the microsim in Table 2.6. While using the [3 deﬁnition given in

equation 2.45 and the same values of 1,, and rdi given in Table 2.6, the value of B reduces

by a factor of 4.

Also the bias current is off because SPICE program models the open circuit by

67

a large resistance of 1E12 Q value between the gate and the channels this causes a
leakage current ﬂowing out of the gate. Therefore the base cuurent calculated in the
above table does not match the simulated one. In order to avoid the effect of these
resistances we connect other resistances between the gate and the channels with a -1512
Q value. Table 2.8 shows the simulated measurements of the revised model. Thus, the

two measurements are comparable.

Table 2.8 Revised parameters of the LF411

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

r- Parameter Calculamd Simulated
511+ 17 V/ps 19.6 V/us
SR‘ -11.975 V/us 44.9 V/us
vi0 -3.237 11V -3.2 uV I
1,, -25 pA -25 pA I
f0 20.000 Hz 19.95 Hz I
Adm 106.02 dB 106 dB I
GBP 4 MHz 3.98 MHz I
f" 3.292 MHz 3.286 MHz I
a,“ 55.37° 554° I
CMRR 100 dB 100 dB I
r“. 50 n 50 n I
rod: 75 a 76.38 a
I,“ 25.675 mA 25.68 mA I
1,, -25.675 mA -25.68 mA
vm 14.175 v 14.17 v f I
v“, -14.175 v -14.17 v '
pd 65.1 mW 65.1mW

 

 

 

CHAPTER 3

Linear Technology Model (LTC)
3.1 Introduction

In this chapter, the structure and basic operations of another op amp macromodel
called linear technology model (LTC), are described [2]. Fig. 3.1 shows a schematic
circuit of a JFET p-channel input stage macromodel. The LTC macromodel is designed
by using elements inherent to SPICE such as using ideal controlled source stages instead
of transistors, and generally minimizes the number of pn junctions [2]. Like the microsim
model, two basic controlled sources dominate this op amp macromodel: the VCVS and
the VCCS.

As mentioned in the ﬁrst chapter a good macromodel design is one that shows a
useful reduction in simulation time and memory usage. If improving a macromodel
results in a very complex circuit, then we maybe better off to model the op amp at the
electronic device level.

The LTC model is called a modiﬁed Boyle model [2], and can model virtually any

input differential transconductance stage [2]. Therefore, it can be adapted to any op amp

68

69
with an npn, pnp, JFET or MOSFET input stage [2]. Obviously the LTC model is a more

complex macromodel.

vi’

«if MM

- § -

V

 

 

 

 

F,

 

 

  

r61

IP—WV'v

 

 

Figure 3.1 LTC macromodel of the LF355

Table 3.1 SPICE ﬁle of the LF355 macromodel

* Linear Technology LF355

* Connections: + - V+ V- O
.SUBCKT LF355 3 2 7 4 6
* INPUT

VCM2 40 4 2.0000E+00

RDl 40 80 2.1221E+03

RD2 40 90 2.1221E+03

J 1 80 102 12 MI

12 90 103 12 JM2

CIN 2 3 4.0000E-12

ROI 2 102 2.0000E+00

RG2 3 103 2.0000E+00

C1 80 90 1.5000E-11

[SS 7 12 2.4000E-04

GOSIT 7 12 90 80 1.2000E-04
* INTERMEDIATE

GCM 0 8 12 0 4.7124E-09
GA 8 0 80 90 4.7124E-04
.R2 8 0 1.0000E+05

C2 1 8 3.0000E-11

GB 1 0 8 0 4.2768E+01

R02 1 0 9.9000E+01

* OUTPUT

R80 1 6 1.0000E+00

ECL 18 0 1 6 1.9963E+01
GCL 0 8 20 0 1.0000E+00
RCL 20 0 l.OOOOE+03

D1 18 20 DMl

3.2 Circuit Component and Operation

D2 20 18 DMl

D3A 131 70 DM3

D38 13 131 DM3

GPL 0 8 70 7 1.0000E+00

VC 13 6 3.136OE+00

RPLA 7 7O 1.0000E+04

RPLB 7 131 l.OOOOE+OS

D4A 60 141 DM3

D4B 141 14 DM3

GNL 0 8 6O 4 1.0000E-1-00

VB 6 l4 3.13GOE+OO

RNLA 6O 4 1.0000E+04

RNLB 141 4 1.0000E+05

at:

[P 7 4 1.7600E-03

DSUB 4 7 DM2

* MODELS

.MODEL IMl PJF (IS=3.lSOOE-ll
+ BET A=4.6264E-O4 VTO=-l)
.MODEL JM2 PJF (IS=2.8500E-11
+ BETA=4.6264E-4 VTO=-9.97E-l)
.MODEL DMl D (IS=1.0000E-15)
.MODEL DM2 D (IS=8.0000E-16
+ BV=4.3200E+01)

.MODEL DM3 D (IS=1.0000E-l6)
.MODEL DM4 D (IS=1.0000E-O9)
.ENDS LF355

The LTC op amp macromodel can be divided into three basic building blocks:

input stage, intermediate stage and output stage which includes the short circuit current

and voltage limiting.

7 1
3.2.1 Input stage

The input stage is very similar to the microsim model input stage and is, also
isolated from the rest of the stages to simplify the modeling of the slew rate and
frequency response. The two transistors used at the input are represented in the SPICE
program by the simplest models which does not include internal capacitances or
resistances. They are at the input to model the linear andinonlinear differential mode and
common mode input characteristics and provide the desired input offsets [2]. The input

stage gain is chosen to be unity for the same reasons mentioned in chapter 2.
3.2.2 Intermediate stage

The element g., g, r2, r02 and c2 provide the op amp gain and vary the frequency
response characteristics. For a more simpliﬁed LTC model, the basic modeling equations
follow exactly the original Boyle model [2]. The capacitance c2, c1 are used for the same

reasons used in the microsim model.
3.2.3 Output stage
The output stage provides a dc and ac output resistance of the op amp by the two

resistance r02 and r”.

The short current limiting which provides the desired maximum short circuit

72

current 1,, consists of two back to back diodes d,, d2, a resistance rcl and a VCVS ed,
where vac, is the voltage across rso. The diode dl provides current limiting for positive
short circuit 1,0,, while (12 is for negative short circuit current I”,

The voltage limiting circuit is more complex than the microsim model voltage
limiting circuit. The diodes d,,, d” and VCCS g9, form a positive voltage limiter, while

d“, d“, and VCCS gm form the negative voltage limiter.

3.3 Preview

The focus of the rest of the chapter is to develop expressions for the values of the
elements of the macromodel. The starting point is to use SPICE simulations of a given
macromodel to establish the basic design equations. Then, a general procedure will be
developed for the parameter and element values of the linear technology macromodel.
Finally, the last step is to check the design procedure by using a numerical example. This
analysis will be done for a three different input stage macromodels: JFET p-channel input

stage macromodel (LF355) and PMOS input stage macomodel (LTC1050).

3.4 J FET Input Stage Macromodel

One of the JFET p-channel input stage macromodel is the LF355. Its schematic

diagram is shown in F1g. 3.1 and its corresponding SPICE ﬁle is shown in Table. 3.1.

Also, a schematic diagram of the LF355 full device is shown in Fig. 3.2 and its

73
corresponding SPICE ﬁle in Table 3.2 [3].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3.2 LF355 full device

Table 3.2 SPICE ﬁle of the LF355 full device [3]

*OP AMP LF355 DEVICE LEVEL
*CONNECTIONS + - V+ V- 0
.SUBCKT LF355D 3 2 7 4 6
QD4 20 20 4 6 MOD3

QD5 21 21 4 6 MOD3

QlC 10 10 7 6 MOD2 1

14A 21 10 10 MOD4 4

MB 20 10 10 MOD4 4

R2 16 15 30

R3 15 17 30

R4 14 4 1K

R5 18 4 5K

R6 19 4 5K

Cl 11 4 10E-12

C2 13 12 10E-12

QlA 810 7 6 MOD21

QlB 910 7 6 MOD21

Q5 41312 6 MOD21

Q6 7 ll 18 6 MOD3

Q7 7 18 16 6 MOD3

Q8 13 19 17 6 MOD3

Q9 7 12 19 6 MOD3

Q12 8 15 14 6 MOD3 2

Q13 15 20 4 6 MOD3 4

J3 13 10 9 MOD4 10

J10 41212 MOD4 3
J1141111MOD4 3

3.4.1 SPICE test circuits

R7 26 4 3K

R8 27 4 50

QDl 23 23 22 6 MOD3 3

QD6 24 24 4 6 MOD3

Q2 713 23 6 MOD3 3

Q3 7 23 28 6 MOD3 3

Q10 7 25 26 6 MOD3

Q1128 26 27 6 MOD3 3

Q15 25 24 4 6 MOD3 2

J5 25 22 28 MOD4 2

J9 24 23 23 MOD4 1

R1 28 6 25 .

Q14 22 21 4 6 MOD3 4

J1 12 3 8 MOD4 5

J2 11 2 8 MOD4 5

.MODEL MOD2 PNP (BF=40 BR=.1
+ RB=500 RC=500 CJS=.2lE-l2

+ TF=25N TR=2.5U CJE=.5E-12

+ CJC=.21E-12 IS=3.5E-15 VAF=SO)
.MODEL MOD3 NPN (BF=1OO BR=.1
+ RB=500 RC=500 CJS=.2lE-12

+ TF=1N TR=.5U CJE=.5E-12

+ CJC=.21E-12 IS=1E-15 VAF=250)
.MODEL MOD4 PJF (VTO=-l.0

+ BETA=.25E-4 LAMBDA=.01 RD=90
+ RS=9O CGS=ZE-12 CGD=2E-12

+ PB=.6 IS = 1E-15)

.ENDS LF355D

The same test circuits established using the npn input stage microsim macromodel,

now will be established using the p-channel JFET input stage LTC macmmodel such as

the LF355. Table 3.3 provides the summarized data of the SPICE test circuits for the

LF355 macromodel and full device.

75
3.4.2 Model formulas

3.4.2.1 Slew rate

The LTC models asymmetric slew rate for some chips by adding a VCCS
designated go“ (instead of using css or c) which has no effect on the frequency response
[2]. This VCCS modiﬁes the total current available to jl and j,. This source is driven
by the differential output of j,. j2 and produces a current which adds to or substracts from
the ﬁxed current I”. Then, the current ﬂowing to charge or discharge the compensation
capacitance c2 increases for one slewing slope and decreases for the opposite. Consider
the unity gain buffer ampliﬁer conﬁguration, the op amp input stage passes through
several states. Fig. 3.3 shows the drain current of the two JFET j,. j,.

a) Negative slew rate: SR‘
Fig. 3.3 shows that at the falling edge of the input j2 is active and jl is cutoff. The

current ﬂowing in r42, lm2 is equal to

11112 :1” “ga-‘V.

and I,“ = 0, therefore

V: = .09 -gocitva)rd2

then

76

v5-1"; (3.1)
l-gositrdz

Since g. is chosen to be equal to l/rdi, then the current ﬂowing in the VCCS g. is

l -gositrd2
Since the voltage at node 8 noted. vsb, is very small voltage and r2 is a large resistance

then most of the current (g. v,) ﬂows out of c2 then,

1” 1t

l-gatra 9.

where vc2 is the voltage across c2 (see Fig.3.4).

c2-

 

ch- -vout

Hence

I“ 1
SR '=-_____
c2 l'gotitrdz

(3.2)
b) Positive slew rate: SR+

Fig.3.3 shows that at the rising edge of the input jl is active and jz is cutoff. At this case

jl is operating as a source follower tracking the variation of the output voltage. The

current ﬂowing in r“, I,“ is equal to

I=I v

tar u-gotu a

and now I“,2 = 0. Also

77

Va gas: -goeitva)rd1

then

I

88

1' +gositrdl

Since V3,, is very small voltage and r2 is a very large resistance, then most of the current

V

00

g, v, ﬂows through c2, then

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I
SR .__. e 1 (3.3)
CZ l+gocitrd2
--------- 4--- 4 4 4 4
6 0V 4 --------- 4 --------- -o---- 4 4
on,“ 4 --------- 4- 4 4 4
a, L
a U
5 5
‘ :
«one» --------- -+ --------- 4 --------- 4 --------- 4n" 4 4 4
u 10(X1.J1)
u 4 4 4 ---+---- 4 4 4
I
51 L
f U
«ones; 4 4 4 4 4 4 4
tour 200: 300! 4011: $011: 6003 10110

0110
0 10011.42)

Figure 3.3 The drain current of jl and j2

 

 

a... .;

 

 

 

ll

1
-41 11.---------

iOVf

 

--—.+--------

 

.1nv; ......... .q. ......... .9 ......... .+- :4; ¢ ¢ 4
Due 1011! 2011: 3011: 4011s $011: 500: 70"
0V(X1.1) . vu)

Tl”

 

Figure 3.4 The voltage v8, and vc2

3.4.2.2 JFETs parameters

The JFETs parameters can be derived the same way done in chapter 2. These two
J FETs used at the input stage have different threshold voltages and saturation currents so

that the input offset current and the input offset voltage are different from zero.

3.4.2.3 Input stage: rdl

When the op amp macromodel is operating in the linear region, the current
ﬂowing through the VCCS g“, g” and 8.1 are zero. For the diﬂ‘erential mode and using
Barlett’s theorem [8], vcm is shorted, therefore the current ﬂowing in the VCCS g, is

zero. Thus, the schematic circuit of the intermediate stage for the differential mode Case

79

is shown in Fig.3.5. The resistance r“, is usually very small, thus the output voltage vom

is approximately equal to that at node voltage 1, v1.

:2
- I 1e 4 -
9. r2 9b '02
'?' ?

 

Figure 3.5 lnterrnediate stage at DM input

Since at dc, c2 is an open circuit, then vt'is equal to

v1=-gbvg.r02«-vout '(3-9)
and
v8b=--g.v.r2 (3.10)
Substituting equation 3.10 into 3.9 then
va-gtsJM. (3-11)
Since v. = vd, then the dc gain Am is
Amggbgir oz (3°12)

The previous analysis holds for very low frequencies where c, is an open circuit, but at

higher frequencies c2 becomes short and

8O

1
vom- -g.v‘(rozll_ llrz) (3.13)
8.
Mg, << r02 << r2 thus,
_l_llrozllrz-_l_
b b
and from equation 3.13
glvl
V om- ‘—
gt)

which is very small, therefore a system pole must occur at low frequencies. The pole is
found by using the one capacitor method [8]. To solve for the resistance seen by c,, a
test current source L is applied in parallel with the capacitance c2 creating a voltage drop

called vx. vdull is set to zero, thus v3 = 0, (see Fig. 3.6)

vx =Ixr2+roz(gbvsb+1x) (3.14)
then
V
ferrous”... (3.15)

The above equation can be approximated as

V!

T ozgsr 2
X

Hence. the resistance seen by c2 is rozxgptr2 and the frequency fo at which the pole occurs

is

81

l

 

 
 
 

 

 

f =_— (3.16)
o Zurozrngcz
Using equation 3.12 and 3.16
GBP: 1 (3.17)
2W.
. Ob ir O 2
Figure 3.6 Resistance seen by c2
3.4.2.4 Input stage: c,
The second pole occurs at f2 which is found to be equal to
f 1
2’ (3.18)
41¢er

Following the same analysis done in chapter 2, the necessary value of c! to produce the
second pole is

tan|90°-¢,.l

cl (3.19)
47rfnr‘i

 

82
3.4.2.5 Interstage: 8...

At low frequencies c2 is an open circuit and

V31, =gcmr2 (3.20)

and

(3.21)

vout - -gbvgbr02

Substituting equation 3.20 into equation 3.21

vout--gcmgbr ozvcn (322)

then, the common mode gain Am is

IA...| =gms.r .2 (333)

Using equation 3.12 and 3.23, the common mode rejection ratio is found to be

1

gourd

CMMR= (3.24)

 

3.4.2.6 DC power drain

To model the actual dc power dissipation of an op amp, a current source i, is

added into the macromodel. The power dissipation is

83

p d=(vp .-VP )1“ +(vp .-vp .)ip
Then, the necessary value of ip to produce this dissipation is
1P=__'3:'__-1“ ' (3.25)
(vp.-vp-)
A diode d", is used across i1, for the same reason as microsim model and it has a
breakdown voltage which is equal to the maximum ‘total supply voltage of the

corresponding op amp.
3.4.2.7 Output stage: r” and r,,2

The output stage provides the dc and ac output resistances. The output resistance
usually depends on rso and r02 as was described in chapter 2. But for this type of
macromodel this assumption is not valid anymore due to the short circuit cunent design.
The test circuit used to ﬁnd the output impedance is shown in Fig. 2.6a. At low
frequencies, 02 is open. When the current IT ﬂows through r”, it creates a voltage drop
which is fedback through a VCVS, ed. Thus the resistance rcl also has a very small
voltage drop across it. In SPICE program, when the diode is in the cutoff mode it is

represented by a large resistance r = 1E12 0. Thus the voltage across rd, vc, is

1‘ I' e
_ so c1 cl
[cl+_l'

2

This voltage is fedback through the VCCS, gcl and creates a voltage drop across r1, noted

84

Vs- Since the current through c2 is almost zero, then the current through VCCS g, is

_[ l.sorclrzgclgbccl
bat)- 1

 

+ l
rcl _r

The output voltage, vom is found to be

1set 21' clgc Igbccl
l

llad-""1.

vout: so +I’T( 1 + ”02

 

Hence the dc output impedance is

(1 + 1'21- sorclgclgbccl

l.el

V
_ out
I'D-(k -— =rso +1.02

)

 

+_I'

At higher frequencies, c2 is shorted and the ac output impedance is

”0...”... +(rzll_l-lr°2) ~rw (3.27)
8

[9

3.4.2.8 Output stage: current limiting

When the output is shorted and current limiting occurs, a predetermined voltage
appears across re, which controls the current in VCCS 8.1 to absorb the current from the
main signal path through the VCCS g. [2]. The voltage across the diode is used to adjust
the desired sinking and sourcing current limits.

a) Sourcing current: I”,

The short circuit, 1”,, ﬂows through rm creating a voltage drop, v“, across r”, so

85

v -r I (3.28)

eel sosc°

The voltage veel controls the VCVS ed, where

VC

V +V
ecl

c1= dl gcl
Va, is the diode voltage drop across (11 and vac, is the voltage across the resistance rel.

Substituting equation 3.28 into the above equation, ecl is found to be,

 

c=a+w an)

The current ﬂowing in the VCCS g, is equal to the current (I, - g“ VJ, as well as the

VCCS 8.1- This is veriﬁed by using SPICE program (see Fig. 3.7), that is

gava =gClvgcl=Iss -gos-“V‘ (3.30)

For a simpler design procedure, gcl is usually picked to be 1 Q", then the value of v.“ is

determined by using equation 3.30

l2133:) 0M)

V
F gel go +goeit

 

The current ﬂowing in the diode d,, I“, is the same current ﬂowing in rd, thus

V

Idl=_?::_l (3.32)
Substituting equation 3.31 into 3.32 then
I g
I = ” ( ' ) (3.-33)

 

 

d1

getter 333.“

86

So now, the current I“ is determined once the value of re, is determined. For the p-
channel JFET op amp macromodel. rd is chosen to have the value of 1 kn . The voltage

across the diode d,, v“, is established from the diode equation,

I
vdl=vT1n_Is“_‘_ (3.34)

The diode saturation current IS“. speciﬁed in SPICE program as IS, is chosen to have the

value 1E-15 A. Then, substituting equation 3.33 into 3.34

v d1 =vl In 1‘3' (3.35)
gelrelISdIIga +goa'a) I

So now, the value of cc, could be established by substituting equation 3.35 and 3.31 into

3.29

ed=_.l_.[v11n(

 

1.8. ). Inge ] (3.36)
I'soIseo gelrcllsdl (gt +goc't) gcl(ga gosh)

b) Sinking current: 1,,
The negative short circuit current, 1,, ﬂows through r,0 creating a voltage drop,

v”, across r,o

v 'r I (337)

ad none-

The voltage veel controls the VCVS ed, where

Veetectgvgtt'va
v‘,2 is the diode voltage drop across d2. Substituting equation 3.37 into the above

equation, ecl is found to be

 

Clr1

SO 56"

The current ﬂowing in VCCS g, is now equal to the -(I,, - gosit v) as well as the VCCS

 

 

 

gd. That is
-gava = -gclggcl =13: -gositva
Then
Is‘s ga
V 8" - -—( )
gel gt .goe'n
Therefore
v
1 = ~l‘
d2
l.cl
Hence
1.. g.
va=v1ln( ( ))

gelrcllsdz gt -goli

So the value of e“I in terms of I”, is found to be

 

1 1.. g. 1.3.
c,=-—1v (—__< +———1
l rsolac- Tm gcircllsrlz ga -goeit gel(ga .803!)

88

1+
1
1|»
1
1r
1

 

K 1
1
.4

 

 

 

E
M
1
I
"1 114mm---"

 

 

 

 

 

 

 

4onu»--~----4— --------+- ------------------------------ +- 4
n.1(x1GA) “(111.551.11x1.m11').1(x1.cn)
zoouae _ ............ f f v if.
I a
)
UIIA 1b
5 1) .1
ennui-'7 - 4 = ._
1 l
: - D g _ L
«can» -------- S4-u ------- 3;"- L"4" 4 4

ﬂu “is 30611. 35E:- «In
.1011 511M) . 0001.155) ”(111331.11)”. 111112.111)

Figure 3.7 The current ﬂowing through g, and 8.1

3.4.2.9 Output stage: voltage limiting

a) Positive output voltage
When the output is clamped positive, a predetermined voltage drop occurs across

rpla WhiCh controls the VCCS g” to absorb the main current ﬂowing in g., then
g.V.=ngpl= Ig-gog‘v ‘ (3.37)

For a simpler design procedure, g,, is chosen to have the value 1 9". From equation 3.37

) (3.38)

 

v =_(
‘" g" are...

The voltage vc is equal to

89

vc ~vP.-vm. ”43.1%” (3.39)

where v43. and vm are respectively the voltage drop across d,, and d3”. These two diodes
are identical and have the same saturation current speciﬁed in SPICE as 1S and is chosen
to be equal to 1E-l6 A. The current in the diode d,,, 143, is the same current ﬂowing in

’va thus

1 = 31" (3.40)

Therefore, by selecting the value of rph one can determine the value of Va. by substituting

equation 3.38 and 3.40 into the diode equation,

I g I
v .=v (_‘_‘._(_'_)) (3.41)
d3 Tln gplrplaISrB gt +goe'u

 

The voltage across rpm is the summation of v43, and V911 then, the cunent ﬂowing through
rplb’ [11111) is
I = V131 ”up! (3.42)
rplb 1'
pl!)

In order to determine the voltage v43,” one needs to ﬁnd the current 143., ﬂowing through

it which is deﬁned by the following equation,

I I I (3.43)

= 4-
43b rplb «13.

Substituting equation 3.40 and 3.42 into 3.43

9O

__ v 3. 1 1
[m -_r‘_ +vm(.r_ +__) (3.44)
plb pla plb

Since the voltage V”, is much smaller than v43” then equation 3.44 becomes as follows,

1 -_"3_‘ (3.45)

I
1 =im(__3_(_g1_» (3.46)

Hence

vd3b=len[_l_-v_Tln(__I”__( g- )1] (3.47)

181131) rp111 gpl‘rplalsdh ga+goch

Finally, the expression for vc is established after selecting a value for rim, and substituting

equations 3.41 and 3.47 into 3.39

1.1 g ) v I,( f
8. gosh )+ll'l( T In g! goon

gplrplaISdBa 1' [11111 81136 gpl‘rplalsoa

)

 

 

)1

vc -vp,-vow +vT[ln(

b) Negative output voltage
When the output is clamped negative, a predetermined voltage drop occurs across

r,m which will control the VCCS g,” to absorbs the main current ﬂowing through g.

‘W'Vmgpﬁk-saa. , (3.48)

For a simpler design procedure, g“, is chosen to have the value 1 (2". Using equation

3.48

91

I
= -_1( g'
gal ga .3063

)

 

Van:
The voltage v, is equal to

ve--vp_+vm_+vm+vm (3-43)
where v“, and v“. are respectively the voltage drop across the diodes d“ and d... These
two diodes are identical to d,, and d» and have the same saturation current. The
expression of ve can be established by following the same procedure done previously.

Also rm = ‘11- and rm, = r,,.,, then

 

 

1,1 g ) v 1.1 3' )
8! gosh )+ln( T '1‘ 3.1“ )1

gnlrnllISd“ rnlbISde gull-“IS“.

V.“ —vp_ +vm_ +VT[ln(

 

3.4.3 Design procedure

A summary of the design equations for the p channel JFET linear technology
macromodel is developed in this section. The starting point of the design is to have the
corresponding op amp characteristics such as SR‘, SR‘, 13, 1,, vb, A... GBP, f... 91m
CMRR, rm rm 1.», I”, v”, v“, and p...

Step 1: Choose c2 = c., where cc is used in the chip as a compensation capacitance.

. I
Step 2. [dis szPC—z

92

 

 

SICP 3: g =_l_
8 rd.‘
Step 4: 1 = 2C2
" l _ 1
SR’ SR'
Step 5' - ( I“ 1)
go“, g‘ SR ‘cz
g2
Step 6: =_'_
B 21”
s 7. 1 1..
ICp . [5145a], +7)

IS 1( I“
.31.?

where 18,, IS1 are respectively the saturation currents of j,, j,.
Step 8: Choose VTOl = -1 V, and VTO2 = -l - V1... where VTO,, VTO, are respectively

the threshold voltages of jl, j,.

=tan|90°-¢P__|

Step 92 c1 41“. r
a di

 

93

Step 10: g = 1
m rdiCMRR
Step 11: Choose r2 = 100 k!)

A
garzroz

dlno

 

Step 12. gb

Step 13: Choose 8.1: 1 Q", rcl = 1 k9

Step 14: Choose the saturation current of the diode cll and (12 to be equal to lE-lS A.
I ( 8. ) I ( 8. )

Step 15: ctr: l [VTIM gl+gosit )+ ga+goci ]
rsolar; + gclrellsdl gel

 

 

 

Step 16: Choose r1,“ = rm = 10 kﬂ
rpm = run, = 100 kﬂ
g... = g... = 1 0"

Step 17.1' -r

80 0'“

(to-c -ro-ac)(rcl 42%”

r02 3

 

1.1:14.';’r +r1rsorclgclgbccl

Step 18: Choose the saturation currents of the diodes d,” d“, d“ and d“ to be equal

94

 

 

1E-16 A.
Step 19:
1,,( f‘ ) v 1“( f‘ )
v.=V..-v...+vTIIn<—&—§£i‘—)+1n(_L.m(__ng4“L))1
gplrplalsdh rplblsab gpll' 91.1543.
Step 20:
Is,( g' 1,,( g' )

 

 

- . V -
V.=‘Vp- +vm_+vT[ln(_§‘_g°l) +ln(_L_ln( g‘ g". D]
gur [Sat fuels.» gﬂrmIS“.

nla

 

Step 21: Choose the saturation current of the diode d", to be equal to 8E-l6 A.
Step 22: Set the breakdown voltage of the diode d“, to be equal to the maximum supply

voltage of the op amp.

Pa

Step 23: i, (Vr‘Vr) a

Step 24: Choose ch = input capacitance of the op amp.

Step 25: The voltage source vein is picked such that it will simulates the negative
common mode characteristics of some JFET ampliﬁers. In most of the cases is set to
2 V.

Step 26: Choose r81 = r!32 = 2 Q.

95
3.4.4 Numerical example

A numerical example is used to illustrate the deveIOpment of the parameters of the
op amp macromodel and to verify the design formulas and procedure. This veriﬁcation
is done by ﬁnding the speciﬁcations of the model using the model formulas derived in
the previous section and the macromodel parameter’s values given in Table 3.1. Table
3.3 includes the calculated and the SPICE simulated measurements using the LF355
macromodel as an example. A list of the equations used to ﬁnd the calculated

measurements are given below.

1
21cc; a

1) GBP=

 

1
2) sn:- “ 1

c2 1 +goeirdz

3) sank—1—
c2 l-gmnl2

4) v“,-V"1'Ol--VTO2

5) 1,431.13,

6) 1.5203. -IS)

7) r = 1

0 zmozr 281102

96

 

 

 

 

 

 

 

 

8) Admo =gogar2roz
l
f =
9) 2 41tc1rdi
f _ 422 +\/f2“ +4Adm°2fozf22
10) F.- 2
. fn
11) ¢m=90 -arctan.?2.
CMRR: 1
12) gcmrdi
13) ro-at:=rso
r r C C cc
ro¢=rw+roz(l+ so It lg lg!) I)
Ileft-'2'r
3.
1,1 g' ) I..(g +g )
ga+g ' a ocit
14) I...= 1 [van( °" )+ 1

 

 

l.socta gctl’cllsrll gel

97

 

 

 

 

 

 

 

 

 

 

 

1 Us: ) I“(g-gs: )
15) Isc_=_ [V ( a osit )+ a osit ]
l.soccl Tln gclrcllsdz gel
16)
1.1g f ) 1.1g fg )
vsat+=vp ‘VC+VT[ID(A)+111(V ln( ' “a ))]
gplrplaISdiia l.plblsdiil) gplrplaISdSa
17)
at: > “g: >
_ + _ 1n 3 081! +111 —ln . an
vat-WP- V’ VI": ( nlrulaISdh ) (rnlbISMb ( gulrnlalsd‘a ))l
18)

pd =(ip +133) (VP. ”Vp.)

98

Table 3.3 Parameters of the LF355

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter Calculated Simula
SR‘ -10.733 V/us -10.70 V/us
SR+ 6.376 V/us 6.364 Was I
V1. -3 mV -3.005 mV
Ii0 6 pA 6.01 pA
IB 60 pA 73.47 pA II
fo 12.5298 Hz 12.59 Hz II
Am, 105.99 dB 105.9 dB
GBP 2.5 MHz 2.5 MHz
f“ 1.965 MHz 1.979 MHz
on 51.82° 51.4°
CMRR 100 dB 100 dB
r(He 1 9 1.023 (2
rue 116.9 52 117.4 9
I,“ 24.70 mA 24.72 mA
I“, ~25.383 mA -25.40 mA
vm 12.99 V 12.99 V
vs“, -l3.01 V -13.01 V

 

 

 

3.5 MOSFET Input Stage Macromodel

 

 

Some of the LTC macromodels have a PMOS input stage such as the LTC1050.

Its design is very similar to the JFET input stage macromodel with of course a PMOS Ml,

99
M2 replacing the JFETs jl, j,. This macromodel has been adapted to several op amps

such as: LTC 1051, LTC1049, LTC1052.... The schematic circuit of the LTC1050 is
shown in Fig. 3.8 and its corresponding SPICE ﬁle in Table 3.4. The only differences
between these two macromodels are the input stage and the short circuit current. The
intermediate stage, the output stage including the voltage limiting remain exactly the same

as was described for the JFET input stage LTC macromodel.-

A

 

 

rpll rplh

' .1

v 0

 

 

 

 

 

 

Figure 3.8 LTC macromodel of the LTC1050

100
Table 3.4 SPICE ﬁle of the LTC1050 macromodel

* Linear Technology LTC1050 VODl 19 20 0.0000E+00
* Connections: + - V+ V- 0 D2 20 21 DMl
.SUBCKT LTC1050 3 2 7 4 6 VOD2 21 18 2.6932E+00

=1 INPUT
RD14 80 2.12215+03
RD2 4 9o 2.12215+03
M180 2 12 12 PMl

M2 90 3 12 12 PM2

CIN 2 3 5.0000512

DGl 2 7 DMGl

DG2 3 7 DMG2

C1 80 90 1.50005-11

188 7 12 120005-04

cs 12 o 1.2857E-11

* INTERMEDIATE

GCM 0 8 12 0 149025-10
GA 8 0 8o 90 471245-04
122 8 0 1.00005+05

c2 1 8 3.00005-11

GB 1 0 8 o 1.0664E+04
R02 1 0 19900sz

* OUTPUT

R80 1 6 1.00005+oo
ECL 18 o 1 6 1.79555+02
GCL 0 8 20 0 1.00005+oo
RCL 20 0 1.00005+01

131 18 19 DMI

3.5.1 SPICE test circuits

D3A 131 70 DM3

D38 13 131 DM3

GPL 0 8 70 7 1.0000E-1-00

VC l3 6 1.4332E+00

RPLA 7 70 1.0000E-1-01

RPLB 7 131 1.0000E+03

D4A 60 141 DM3

D4B 141 14 DM3

GNL 0 8 60 4 l.00005+00

VB 6 14 1.4332E+00

RNLA 60 4 1.0000E+01

RNLB 141 4 1.0000E+03

IP 7 4 8.8000E-04

DSUB 4 7 DM2 -
.MODEL PMl PMOS (KP=1.8506E-3
+ VTO=-l.10000001'£+00)

.MODEL PM2 PMOS (KP=1.8506E-3
+ VTO=~1.1000005E+00)

.MODEL DMl D (IS=1.00005-20)
.MODEL DM2 D (IS=8.0000E-16

+ BV=1.9800E+01)

.MODEL DM3 D (IS=1.0000E-l6)
.MODEL DMGl D (IS=2.0010E-ll)
.MODEL DMG2 D (IS=9.9998E-15)
.ENDS LTC1050

The same SPICE test circuits used for the JFET input stage macromodel, now may

be used for the PMOS input stage macromodel such as the LTC1050. Table 3.5 provides

the summarized measurements of the SPICE test circuits for the LTC1050. For this type

of op amp, the maximum total supply voltage has to be less than or equal to 18 V.

101
3.5.2 Model formulas

The basic operation and design formulas of the PMOS input stage macromodel are

described in this section.

3.5.2.1 Slew rate

This version of the macromodel, models the asymmetric slew rate by adding a
capacitance c, at the input stage. Consider the unity gain buffer ampliﬁer conﬁguration,
the op amp input stage passes through several states. the two PMOS M1, M2.

a) Negative slew rate: SR‘

Using a SPICE simulation, we conclude that on the falling edge of the input M2
is active and Ml is cutoff. The current ﬂowing in the VCCS g, is equal to I, which ﬂows
out of c2, since r2 is usually a large resistance, the voltage across 02 is almost equal to the

output voltage. Then SR' is found to be

1
SR '41 (3.49)

b) Positive slew rate: SR“
Also on the rising edge of the input, M2 is cutoff and M1 is active. For this case
M, is operating as a source follower tracking the variation of the output. The output

voltage is all across the capacitor cs. Then SR+ is equal to

 

SR *= dv” =22}: (3.50)
dt dt c

where v“ is the voltage across cs and 1c, is the current ﬂowing through it. Since the slope
is positive then I“ is positive and it is pumped through c,.

The current ﬂowing through 1'81 is the difference between 1,, and I“ that is

 

IrdI=Iss—Ics - (3.51)
substituting equation 3.52 into 3.53
[m =1” -SR ‘c' (3.52)
Since on the rising edge of the input
va=Ircllrdl
then
I
SR 41 (3.53)
CZ
Using equation 3.53 in 3.52, then
SR ‘c2=1” -SR ’c, (354)
Finally, equation 3.54 gives,
1
SR ’= " (3.55)
c +c

103
3.5.2.2 MOSFET parameters

The input offset voltage vi0 is modeled as a difference in the threshold voltages

of the input MOSFETS speciﬁed in SPICE program as VTO, so

V16=VT01 -VTO2
where VTOl and VTO2 are respectively the threshold voltages of M1, M2. The value of

Kp can determined from the following equation

IS!
gm= 2KP7

where g, is the transconductance of the MOSFET and its value can be determined from

the unity input stage gain A“, that is

Avl=g r l

rudi-

Hence

gm=_ (3.56)

3.5.2.3 Intermediate stage

All the design equations developed for the intermediate stage of the JFET input

LTC macromodel remain the same for the MOSFET input stage LTC macromodel.

104
3.5.2.4 Output stage: current limiting

Two voltage sources v0“, V082 have been added to the short circuit current used in
the case of JFET input stage LTC macromodel as shown in Fig. 3.8a. These two souces
are added because the positive and negative short circuit current are not equal in
magnitude. This is one of the typical specs for the PMOS input stage LTC macromodel.
While for the JFET input stage case I”, and I”, are almost equal in magnitude.

a) Sourcing current: I“,

The short circuit 1w ﬂows through r$0 creating a voltage drop v.61 across r”, so

v 'r I (3.57)

ecl sosc‘

The voltage vecl controlls the vcvs ed, where

vec1cc1=vdr +vgcl+vod1 (3'58)

substituting equation 3.57 into 3.58, ecl is found to be

V+V +V

C :3 41 31:1 0111 (3.59)

cl
real-u

The current ﬂowing in the VCCS g, is equal to the current 1,, as well as the VCCS g“.

This is veriﬁed using SPICE program, then

g‘v.=g v =1 (3.60)

cl gel as

The value of gcl is usually selected to be 1 52". Then using equation 3.60

105

_ Is:

V-__

8“ gcl

(3.61)

The current ﬂowing in the diode (1‘, Im is the same current ﬂowing in rel, thus

1 3'9“
.11 '1:
Substituting equation 3.61 into 3.62,
I - I“
1-
d gclrcl

 

(3.62)

(3.63)

So now, the current 1.", is determined once the value of rcl is determined. For this type

of op amp (PMOS input stage macromodel) rcl is chosen to have the value of 10 Q. The

voltage across the diode d,, vdl is established from the diode equation once the saturation

current of the diode (1,, IS“ speciﬁed in SPICE as IS, is selected. Usually, for the PMOS

input stage macromodel, 18‘“ is equal to 1E-20 A. Then substituting equation 3.63 into

the diode equation

I

 

 

v =v (364)
M Tln gelrcllsdl
Finally substituting equations 3.64 and 3.61 into 3.59
l
.. =—1v 1n< “ )+_“.+v 1 (165)
| rsoIaco T gell-c1181“ gel 0‘“

The value of ecl could be determined once the value of vodl is solved.

b) Sinking current: 1,,

Following the same procedure done for the positive short circuit, the expression

106

of ecl could be established also from the following equation

I
=- [v ( “ _+v ] (3.66)
I.soI sc- 1-lngclrctISd2)+4gcl 0d:

where ISI12 is the saturation current of (12 and is selected to be equal to IS“. So, we obtain

 

 

two equations 3.65 and 3.66 but with three unknows. There are two cases to discuss.
Case 1: If I I”, l < l I”, I then set v0,“ = 0. Using equation 3.65, ec| can be determined
and then substituting its value into equation 3.66, then V0.12 can be solved using the
following equation

I“
)+_

gclrcllsdz gel

Case 2: If I I” l > | I,c_ I then set V0.12 to zero. Using equation 3.66, ecl can be

vo‘12 -e=Ir+ +vln(

cl sc- so

 

determined. Substituting its value into equation 3.65 v04, can be solved using the

following equation

. I“
) -_

cl‘r cl Sdl gel

V6.1 l=eIr -vln(

cl see so

 

3.5.2.5 Intermediate stage and output stage

The PMOS input stage macromodel has the same intermediate and output stage
including the voltage limiting as the JFET input stage macromodel. Therefore the design
equations for this part remain the same as was done in the previous section for the JFET

input stage macromodel.

107
3.5.3 Design procedure

The following design procedure could be used for any op amp linear technology
macromodel with PMOS at the input stage. The starting point of the design are the
corresponding op amp measurements such as: SR“, SR‘, V16. Adm, GBP, f", 11)”, CMRR,

I.o-arw 1Io-drv In»? Iced vsatv vsat- and pd

Step 1: Choose c2 = cc where cc is used in the chip as a compensation capacitance.

 

Step 2: 135-SR 'c2
I
Step 3: Cs: 3’ .02
SR ’
. 1
Step 4. f .=
" 271:GBPc2
. 1
Step 5. g =—
! rdi
2
Step 6: K =g_'
P I

Step 7: Choose VTOl = -1 V, and VTO2 = -l - V18. where VTO,, VTO2 are respectively

the threshold voltages of MI, M2.

Step 81 c‘=tan|90 wwl
471:f“r‘Ii

 

108

l

SICP 9: g :
°"' rdiCMRR

Step 10: Choose r2 = 100 k!)

Admo

Step I 1: gb:
garzroz

 

Step 12: Choose gc| = 1 Q", rcl = 10 (2

Step 13: Choose the saturation current of the diode d, and (12 to be equal to 1E-20 A.

Step 14: If I I,“ | < l I“, I then, set v0“ = 0 V.

1 1 ( I“ )1“)
v __+_
rlx+ lJng,rlS

ccl=
so c cl d1 gcl

 

and

)+;

gclrclISdZ gel

 

V0112 = -eclrsolsc- +len(

Step15:IfII,“|>|lw,|then,setvoa=0V.

1 1.. 1..
c..=-—I——1v.1n(__—)+_1

rso ae- gclrcllsdl gcl

and

votll =chrwIsco-len( g It :8 ).E:
c c (11 cl

 

109

Step 16: r =r

SO 0 "QC

(to-dc -ro—ac)(rcl 4.?)

 

r02 1
1‘cl +31. +r2rsorc Igclgbccl

Step 17: Choose 1?“ = rm = 10 Q
tp111 = 1.1111) = 1 m

8..=8..=19"

Step 18: Choose the saturation currents of the diodes d,” d», d“ and (14., to be equal

15-16 A.
Step 19:
um 1“ )1n( VT 1111 I“ ))1
V =V "V +V _ + —_ —_
" “ T gPerhISa. rmISm 81.151.13.13.
Step 20:

Is: vT In
v.=-v,-+v...-+v,11n(___)+1n(_—1n(—))1

5.1.13... 51.18... 85.83...

Step 21: Choose the saturation current of the diode d“, to be equal to 8E-l6 A.
Step 22: Set the breakdown voltage of the diode d“, to be equal to the maximum supply

voltage of the op amp.

110

Step 23: 1 =___.p" -1

Step) 24: Choose cill = input capacitance of the op amp.

3.5.4 Numerical example

A numerical example is used to illustrate the development of the parameters of the
op amp macromodel and to verify the design formulas and procedure. This veriﬁcation
is done by ﬁnding the speciﬁcations of the model using the model formulas derived in
the previous section and the macromodel parameter’s values given in Table 3.4. Table 3.5
includes the calculated and the SPICE simulated measurme’nts using the LTC1050 as an

example. A list of the equations used to ﬁnd the calculated measurements are listed

 

 

below.
I
1) SR '=-_2
c2
I
2) SR ’= n
024.0:
3) GBP= 1
w.

4) V1. =VTO2 -VTOI

111

 

 

 

 

 

 

5) fo=___l.__
21n.oZ‘r 2gb02
6) Assesses
7) 12= 1
471c1r .11
8) f = -122~./f;-4Ahﬁozr;
1* 2
9 ° f
) ¢pm =90 -arctan._".
f2
10) CMRR= 1
gcmrdi
1 1 ) I‘D-E =r80
ro-t =1.” +r°2( l + reorzrclgdgbccl)
rcl+—r
2
12) 1 1.. ..
I”, = [VTIM ) +— +vodI]

 

 

l.soccl gcl’rcllsdl gel

 

13)

14)

15)

16)

112

I
[win “+v...)

braced gclrcllsdz) gel

 

 

Is: VT In
Vs...=V,.-V. +Vrlln(——) +ln(——1n(———))]

gplrtmlscna 1' plbISd36 gplrplalsdh
[ln( 1” ) ln(—— ln(——I ))1
Vs _=V _'l'Ve "V __ +
" " T .8513... r518... 8.51.1

p d=(ip +1“)(vp.-vp_)

 

113

Table 3.5 Parameters of the LTC1050

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter Calculated Simulated
SR" 2.8 V/us 2.8 V/ps
SR‘ -4 V/ps -4.12 les

.0 0.5 uV 0.0087 1.1V
f0 25 mHz 27 mHz
Am, 160 dB 159.2 dB
GBP 2.5 MHz 2.46 MHz
f,I 1.965 MHz 1.995 MHz
(ppm 51.82° 51.5°
CMRR 130 dB 130 dB
r“. 1 Q 1 Q
r.ch 962.05 (2 961.30
I”, 4.995 mA 5.002 mA
I”, -20 mA -20 mA
vs,” 4.989 V 4.991 V
vs“, -4.989 V 4991 V
p.l 10 mW 10 mW

 

 

 

 

 

CHAPTER 4

Inaccuracies and Improvements of the Model

4.1 Introduction

In this chapter, some of the additional SPICE test circuits that were not performed
in the previous chapters are introduced here. These tests do not contribute in determining
the macromodel parameters, but they show some of the model inaccuracies and its failure
to mimic the actual behavior of the corresponding full device. These consist of the
supply current, asymmetric power supplies and ﬁnally the power supply rejection ratio
(PSRR). In order to fix some of these failures, some elements are added to the
macromodel as will be described in this chapter. These changes do not effect any of the

original macromodel formulas.
4.2 Supply Current Test

The supply current SPICE test circuit consist of the op amp connected as a

noninverting ampliﬁer with a 10 [(9 load resistance. Then measure the curent

114

115

flowing through the positive and negative power supply pins.
4.2.1 Microsim model

The following test was performed on the uA74l macromodel and the full device.
Fig. 4.1a shows the SPICE response of the uA74l full device. The current ﬂowing in the
positive power supply is coming into the chip, while the current ﬂowing in the negative
power supply is pumped out of the chip. Also as the output voltage increases, the load
current increases, therefore the supply current increases through the positive and negative
power supplies. If the output decreases, then the load current also decreases, thus the
supply current decreases. In the case where the output is constant (clamped), the supply

current is also constant (clamped). So the load current ﬂows from the power supplies.

BJM‘ #
T
0

1r
4
«all

 
   

mun-li-

 

 

tmu- 0.5. 1.0 L¢ .
u-I(VP9) I -I(VP-) “ s" 2 M

Figure 4.1a The supply current of the uA74l (full device)

Fig. 4.1b shows the supply current test response of the M741 macromodel. The supply

116

current has the same direction as in the case of full device, but it remains constant as the
output voltage increases or decreases. Thus the load current is not modeled as ﬂowing
from the power supplies. In order to ﬁx such a porblem, the output current is fedback
into the power supplies through a CCCS [8]. Hence the current ﬂowing through the
power supplies have the same variation as the load current. The diode d,Kl and theCCCS
f“ are used for the positive load current while (1,2 and f1L2 are used for the negative load
current. Fig. 4.2a shows the new output stage circuit, and Fig. 4.2b shows the

corresponding response of the supply current test.

 

 

:
av

 

 

 

I
-2ov+ +—

fl'(4)

i
hit it

it it

i

0.0»? 1r

A A A- L
v v v '

 

 

 

0.!" 0.5“
O-|('Do) . -l(VD-)

Figure 4.1b The supply current of the uA741 (macromodel)

VC

2

mg
a i
a.

,

2

<

3

C

0"
nt—

dc

0'

m I

 

 

 

 

 

 

 

 

 

 

the 0.3.0 1.0a 1.5.. the
n-I(VP-) I -I(VPo) o um) Tm

Figure 4.21) The supply current of the modiﬁed macromodel

4.2.2 LTC model

The following tests are performed on the LF355. The supply current test response

of the LF355 full device looks the same as the M741 full device. Also, for the

 

118

macromodel the load current is still not modeled as ﬂowing from the power supplies.
This problem can be ﬁxed in the same way. Fig. 4.3 shows the supply current test

response of the improved LF355 macromodel where the load current is modeled correctly.

 

 

 

 

 

4.0»;- ----------------- -+--- #— ¢
a.” 0.5m
o-l(VP-) I -I(WO) 0 NHL)

Figure 4.3 Supply current of the modiﬁed LF355 macromodel

4.3 The effect of E6ND in the microsim model

The EGND is added in the microsim model to average the power supplies, but in
[8] it was shown that this VCVS has no effect on improving the macromodel behavior
in case of asymmetric supplies. However the input offset of the macromodel depends on
EGND, thus in the case of asymmetric supplies this input offset voltage becomes large.
Therefore as was suggested in [8], it is better to remove this VCVS, Bow to eliminate

further error.

119
4.4 Power Supply Rejection Ratio (PSRR)

The power supply rejection ratio SPICE test circuit is shown in Fig. 4.4. The test
consist of sweeping the dc input voltage for different values of positive and negative
power supplies. The PSRR is the ratio of the change in the voltage input offset over the

change in the power supplies

Av.
PSRR=__‘°.

rp

 

vd

 

Figure 4.4 PSRR test circuit

4.4.1 Microsim model

Fig. 4.4a shows the SPICE response of the M741 full device, where the input

offset varies as the power supplies changes. Fig. 4.4b shows the SPICE response of the

120

uA74l macromodel. The input offset remains the same as the power supplies vary. So,

the microsim model does not model the PSRR.

 

 

15v? 4= ------------ + ------------- -+- ------- +— 1
I I

Figure 4.4a PSRR of the M741 full device

 

 

 

 

 

 

 

The PSRR problem can be ﬁxed by adding two controlled voltage sources at the
input stage of the macromodel. These two controlled sources are described by a look-up
tables. One table is for the positive power supply case and the other one is for the
negative power supply. Each table consists of pairs of values. The ﬁrst value in each
pair is the value of the power supply and the second is the corresponding additional input
offset voltage. The table’s input values must be in order from lowest to highest.

For the positive power supply case the table’s values are found by using the following

formula

y=PSRR(vP,-15)

where y is the additional input offset voltage added to the positive input for the

corresponding value of VP+. The PSRR is about -7.104 uVN for VP, 5 6 V and is about

121
-6.85 uV/V for v” 2 6 V. Table 4.1 includes the values used in the look-up table for the

case of the positive power supply. For the negative power supply, the following formula

is used to find the additional input offset voltage, y, added to the negative input

y=PSRR( |vp_| ~15)

where PSRR is about -7.85 uV/V for | v? I S 6 V and is about -6.66 uVN for l v? I
2 6 V. Table 4.1 also includes the values used in the table look-up for the case of the

negative power supply.

 

it

 

 

/
: F
w r f 1r

-sv-JL _/ 4
J
-1uv+ J
J

_L

 

 

 

 

 

 

' “V 4+— 4 T 4% #4 ¢ +—
°3UOIIV( ) - ISOUV '1000V '50IIV OIIV 500V ‘IOOIIV ISOUV QOUUV
I v
W

Figure 4.41) PSRR of the uA74l macromodel

The PSRR test SPICE response of the modiﬁed microsim model is shown in Fig.

4.4c where now the PSRR is modeled correctly.

122

 

 

 

 

 

 

 

 

 

 

 

15V? 4: —+ -- +2 +............;?.
/f
/ / A j

a / / j s
/J
.............. - ..... . s - . .5
- 200.0:(41 -1UOUV UUV VD 1000V 2000V 3OUIIV

Figure 4.4c PSRR of the modiﬁed uA74l macromodel

Table 4.1 Values of the additional offset (uA741)

 

 

 

 

 

vp— (V) vp+ (V) y (W)

-3 3 85.25

-6 6 61.7

- 15 15 0

-20 20 -34.27 \

 

 

 

 

 

4.4.2 LTC model

The LTC model does not also model the PSRR. Fig. 4.5a shows the SPICE
response of the LF355 full device to the PSRR test circuit. Then Fig. 4.5b shows the
SPICE response of the modiﬁed LF355 macromodel where the same method used for

the M741 now is used for the LF355. Table 4.2 includes the values of the additional

123

input offset voltage for both negative and positive power supplies.

 

 

 

15Vf ------- 4- ------ 4 ------- + ------ 4— ------ + ------ -+- ------ + ------- 4- ------ 1-
10%!» l
:
: E
SV+ +

 

 

 

I
-1SV-.+ ------- +— ------ 4 ------- + ------ 4- ------ + ------ -+- ------ + ------- +- ------ 4-
-20uV 0W 20W 40w 50W BOW 100W 120W 140W 160W
VD

Figure 4.5a PSRR of the LF355 full device

tSVf --------- -+ --------- 4 --------- -+- 4 4 4
I

 

«all

 

mt gr

/ é
f r;

///

""i J 3'

j *

 

 

 

 

I
or“; 4 4 4 4 4 4 4'
'3.IV(4) '3.0~V ~3.0m '3.0W -2.9m '2.'M '2.IH-2..m
.
VD

Figure 4.5b PSRR of the modiﬁed LF355 macromodel

124
Table 4.2 Values of the additional offset (LF355)

 

 

 

 

 

 

 

 

 

vp- (V) vp+ (V) y (uV)

-3 3 46.61

-6 6 9.745

-15 15 0

-20 20 -5.414
4.5 Clipping Voltage

For some op amps the clipping voltage changes linearly as the positive power
supply changes even around the 0 V such as the LF355. But some other op amps like
the uA74l, the clipping voltage changes linearly as the positive power supply except at
the value of 0 V for the positive power supply (see Fig. 4.6a). For both macromodels
(LTC and microsim), the clipping voltage changes linearly even around the 0 V power
supply because of the voltage source used at the output stage usually noted as vc. The
nonlinearity of the clipping voltage around the 0 V power supply such as the uA741 can
be easily solved by introducing a controlled voltage source instead of vc [8]. This
controlled voltage source is described by a look-up table which consists of pair of values.
The ﬁrst value in the pair is the value of the power supply and the second is the
corresponding value of the controlled voltage source at the output. The values used in the
look-up table are determined by using equation 2.40 and are included in Table 4.3. Fig.
4.6b shows the modiﬁed macromodel response where the clipping voltage does not

change linearly around 0 V.

 

J...“

 

1—4

-+. --

 

/// ‘

'15V‘I- """"""" ' ¢ T #
«new ~300u 410an 400w (luv talluv

a!“
V0

-- -—+

 

Figure 4.6a Clipping voltage of the uA741 full device

 

 

 

 

 

 

 

 

tSV-y- -------- + ------- —+— ------- + -------- +—-- 4 4 4
row? 4;.
E
5W} +
OH»
3
sv+ 4L
10V‘l- 4+
mi 4 4— + L 4
mini“) 4.7-w 4.7-v 03w 0.2m 0.4m am am 1.0m
.'
V!)

Figure 4.6b Clipping voltage of the modiﬁed macromodel (M741)

126

Table 4.3 Values of the clipping voltage (M741)

 

 

 

 

 

VP+ V6 1|
0 V 0.6128 V

5 V 1.253 V

20 V 1.253 V

 

4.6 Common Mode Rejection Ratio (CMRR)

Since the CMRR is the ratio of the differential mode gain and the common mode
gain, then the CMRR SPICE test circuit could be done in two steps: differential mode
gain test and a common mode gain test. These two tests were already described

previously in Fig. 2.5a and 2.7a.

4.6.1 Microsim model

The microsim model fails to model correctly the common mode gain even for a
range of frequency lower than 10 MHz, while it succeeds to mimic the differentail mode
behavior of the full device up to 10 MHz. Thus, the CMRR versus frequency is not
modeled correctly even for a range of frequency less than 10 MHz. So, the CMRR is
improved by improving the common mode gain. The common mode SPICE response of
the full device uA741 (see Fig. 2.7b) shows that a pole occurs at a frequency less than

10 Hz, a zero occurs at approximately 10 KHz and another one at 100 KHz. While the

127

macromodel SPICE response ﬂ-iig. 2.7b) shows that only a pole occurs at f0 - 5 Hz. In
order to ﬁx the common mode response, a circuit of two zeros needs to be added to the
common mode response, one at 10 KHz and the other one at 100 KHz. These zeros are
added by using inductors in series with resistances, where at low frequencies these
inductors are short circuits [8]. The additional components needed to add these zeros are
shown in Fig. 4.7. The two CCCS are used to feed back the signal into the intermediate
stage. At low frequencies 02 is open and the two inductors added lam, 1“,; are shorted,

therefore Acm is now found to be equal to

IA...|~a18..r.zr...r...g...g.m
Comparing the above equation to equation 2.21, the low frequency common mode gain
is not the same, but by selecting the product rcml rm2 gcull gm,2 to be equal to one, the
above equation becomes the same as equation 2.21.
At higher frequencies, 02 is not open anymore and the common mode transfer

function has the following form

(1+i)(1+i)
v =A 21
v... (1+1)
p.

 

where 2,, z2 are the two zeros added to the common mode response, and

l’

|zl|=_°“i

curl

and

128

l.crnZ

I22 I =—
lemZ

pl is the existing pole that occurs at f0 deﬁned by equation 2.14 due to c2.

rcm‘l rcm2

 

 

 

 

 

Figure 4.7 Additional components used for CM response

Fig. 4.8a shows the SPICE response of the modified microsim macromodel
(uA741) and its full device response. So clearly with these additional components the
common mode gain now modeled correctly for frequencies lower than 10 MHz. However
for frequencies higher than 10 MHz, the macromodel common mode gain keeps
increasing while the full device common mode levels off and then starts to deacrease.
In order, to level off the common mode gain at frequencies higher than 10 MHz a
resistance, r, is added in parallel with 1“,. Fig. 4.8b shows the ﬁnal modiﬁed
macromodel response where: g“In = gen, = lE-2 (2" rcml = rm, = 100 Q, 1“,, =' 1.592 mH,

1....2 = 0.1592 mH , r, =1m.

41'

-----.+------

  

 

 

 

   
 
 
      

 

 

~o+ +
5 full device -
o-L ------ 4= - --b ------- =4: 4: =4

e IVDBU)
4006+ -------------- +- ------------- + ------- =4 4 4
macromo e1 5
zone {-
5 full g
“T device T
-200d‘;- ------- 4 -+ ------- 4 4 4'
man. 10h 1.0m mourn 1am Lwh

e IVPU)

Frequency

Figure 4.8a CM response of the modiﬁed macromodel

 

 

 

   

 

 

 

 

 

40 4+ ------ 4 + ------- —4 4 4
0 +
«o+ +
' full device 5
-e0 4» ------ 4 4 4 4 4
o o V08“)
d J
2m 4 macromo epl
5 full
u+ device?
an“; 4 4 4 4
loﬂlh 10h 1.0Kh 100th 1uun 1.06h
- -wun

Frequency

Figure 4.8b A more improved CM response

4.6.2 LTC model

Also the LTC model fails to model correctly the common mode gain for the same

range of frequencies as the microsim model, while it succeeds to mimic the differential

130

mode behavior of the full device. Thus adding the same additional components
described in the above section to the LF355, the common mode gain is now modeled
correctly except that the phase versus frequency is off by 180° (see Fig. 4.9a). To ﬁx this
phenomena we just need to reverse the direction of the current in the CCVS gm (see Fig.

4.9b).

‘It
41.

 
 

full device

r t
4 4
i

l
v 4

: macromode

   
 
 

full device

é4+------+---""4 4+4

-4llOd4 4

an 1 In ruin: am
e IVP(4)

‘
9

Frequency

Figure 4.9a CM response of the modiﬁed LF355 macromodel

 

-100
2004

 

e eVDO(4)

it it

it it
T
it i

 

ocJ

    
 

 

-2uoe1r
5 full device
«nocé 4 4 4
1 one ton 1.0km more 1m 1.0m
e IVP(4)

Frequency

 

Figure 4.9b More improved CM response

131

4.7 Numerical example

A numerical example is used to verify that the changes added to the original
macromodel do not affect any of the original macromodel formulas. This veriﬁcation is
done by comparing the SPICE simulated measurements of the original “A741 microsim

macromodel and the modiﬁed uA74l macromodel.

Table 4.4 Parameters of the original and modiﬁed uA741 macromodel

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter Original macromodel Modiﬁed macomodel
SR’ 04957 was -O.4957 V/us
SR” 0.5074 was 0.5074 V/rrs
vi0 -l9.l7 pV -l9.17 av
13 79.742 nA 79.742 nA
f0 5.012 H2 5.012 Hz
Adm 105.9 dB 105.9 dB
GBP 988.57 KHz 988.57KHz
f” 891.3 KHz 891.3 KHz
om 63.l° 63.l°
CMRR 90.01 dB 90.01 dB
r,Hc 50.4 (2 50.1 (2
rm 151.7 9 151.7 9
I... 40.61 mA 40.61 mA
I”, -40.6l mA -40.61 mA
vs... 14.61 V 14.36 V
vs“, -14.61 V -l4.61 V
p, 50.0 mW 50.4 mW

 

 

 

 

CHAPTER 5

Conclusion and Future Research

5.1 Conclusion

The design procedures developed in this thesis allows the designer to determine
the corresponding op amp characteristics. Also these equations shows how the different
components effect the op amp characteristics. Most of the macromodels mimic some of
the behaviors of the real device while it fails to mimic some other behaviors. Therefore,
the designer has to select the most suitable macromodel that provides a close

approximation to the certain response of interest.

5.2 Future Research

Since a large number of macromodels are published without design procedure, one
may continue on testing some other macromodels and develop their model formulas. In
this way the designer will have more macromodels to choose from. Two macromodels

published in [14] and [15] could be an area of future research using the same ideas

132

133

presented in this thesis.

1.) One of these macromodel is called the advanced linear devices (ALD) in [13].
The ALD op amp macromodel is built based on the microsim model but it has MOSFET
input stage. This kind of macromodel is very useful for CMOS IC’s since the microsim
don’t have a MOSFET input stage macromodel in their library.

2.) The other macromodel is called the PMI model (Precision Monolithics
Incorporation) in [14]. This model is built trying to improve on the Boyle model so that
it operates better versus frequency. This macromodel mimics the behavior of op amps
with multiple poles and zeros. Also this model has no ground reference while all the
previous macromodels have a ground reference. This is more complex than the other

macromodels and thus requires more time for simulation but it has improved accuracy.

APPENDIX

APPENDIX A

List of SPICE ﬁles

Table A.l SPICE file of Fig. 2.33
Table A.2 SPICE ﬁle of Fig. 2.53
DC TRANSFER FUNCTION

* MACROMODEL UA741
VD 1 0

VP+ 2 0 15

VP- 3 0 -15

RL 4 0 10K
X110234UA741

.DC VD ~500U 100U 2.5U
.LIB MICROSIMLIB
.PROBE

.END

DEVICE LEVEL

VD l 0

VP+ 2 0 15

VP- 3 0 -15

RL 4 0 10K

X110 2 3 4 UA741A
.DC VD -500U 100U 2.5U
.LIB UA741D.LIB
.PROBE

.END

134

OPEN LOOP GAIN MACROMODEL
VD 1 0 AC 1

VP+ 2 0 15

VP- 3 O -15

RL 4 0 10K

V10 1 5 .01923m
X150234UA741
.AC DEC 30 .1 lOMEG
.LIB 741M.LIB
.PROBE

.END

DEVICE LEVEL

VD l 0 AC 1

VP+ 2 O 15

VP- 3 O -15

RL 4 0 10K

V10 1 5 .327m

X15 0 2 3 4 UA741A
.AC DEC 30 .1 lOMEG
.LIB UA741D.LIB
.PROBE

.END

Table A.3 SPICE ﬁle of Fig. 2.6a

OUTPUT IMPEDANCE
* MACROMODEL
VP+ 2 O 15

VP- 3 0 —15

IT 0 4 AC 1

V10 0 5 19.17U
X150234UA741
.AC DEC 30 .l lMEG
.LIB 741M.LIB
.PROBE

.END

DEVICE LEVEL

VP+ 2 0 15

VP- 3 O -15

IT 0 4 AC 1

V10 0 5 327U

X15 0 2 3 4 UA741A
.AC DEC 30 .l lMEG
.LIB UA741D.LIB
.PROBE

.END

135

Table A.4 SPICE ﬁle of Fig. 2.7a

COMMON-MODE GAIN
* MACROMODEL
VCM 1 0 AC 1

VP+ 2 O 15

VP- 3 0 -15

RL 4 0 10K

V10 1 5 .01923m
X151234UA741
.AC DEC 30 .l lOOMEG
.LIB 741M.LIB

.PROBE

.END '

DEVICE LEVEL

VCM 1 0 AC 1

VP+ 2 0 15

VP- 3 0 -15

RL 4 0 10K

V10 1 5 .327m

X1512 3 4 UA741A
.AC DEC 30 .1 lOOMEG
.LIB UA741D.LIB
.PROBE

.END

Table A5 SPICE ﬁle of Fig. 2.8a

SHORT CIRCUIT CURRENT
* MACROMODEL
VIN 10 SIN (0 .011K)
VP+ 2 0 15

VP- 3 0 -15

RL 4 0 10k
X110234UA741
.TRAN 10U 2m 0 10U
.LIB 741M.LIB
.PROBE

.END

Table A.6 SPICE ﬁle of Fig. 2.9a

SLEW RATE MACROMODEL
VIN l O PULSE (-5 5 lOU .5U .5U
+ 45U)

VP+ 2 0 15

VP- 3 0 -15

RL 4 0 10K
X114234UA741

.TRAN .5U IOOU 0U .5U

.LIB 741M.LIB

.PROBE

.END

DEVICE LEVEL

VIN 1 0 PULSE (-5 5 10U .5U .5U
+ 45U)

VP+ 2 0 15

VP- 3 0 -15

RL 4 0 10K

X114 2 3 4 UA741A

.TRAN .5U IOOU 0U .5U

.LIB UA741D.LIB

.PROBE

.END

Table A.7 SPICE ﬁle of Fig. 2.14

CURRENT IN FB AND VB
VIN 1 0 SIN(O 1 5K)

VP+ 2 0 15

VP- 3 0 -15

RL 4 0 10K
X114234UA741
.TRAN 5U 400U 0U 5U
.LIB 741M.LIB

.PROBE

.END

136

Table A.8 SPICE ﬁle of Fig. 2.19

OUTPUT VOLTAGE CLAMP
VCM l 0 SIN(O 2 1K)
VP+ 2 O 15

VP- 3 O -15

RL 4 0 10k

R1 5 0 1K

R2 5 4 9K
X115234UA741
.TRAN lOU 2m 0 IOU
.LIB 741m.LIB
.PROBE

.END

Table A.9 SPICE ﬁle of Fig. 2.22

SLEW RATE MACROMODEL LF411
VIN 1 O PULSE (-5 5 IOU .5U .5U
+ 35U)

VP+ 2 O 15

VP- 3 O -15

RL 4 0 10K

X114234LF411

.TRAN .5U 70U 0U .5U

.LIB LF411.LIB

.PROBE

.END

Table A.10 SPICE ﬁle of Fig. 3.3 & 3.4

SLEW RATE MACROMODEL LF355
VIN l O PULSE (-5 5 lOU .5U .5U
+ 35U)

VP+ 2 O 15

VP- 3 O -15

RL 4 0 10K

X1 1 4 2 3 4 LF355

.TRAN 5U 70U 0U 5U UIC

.LIB LF355.LIB

.PROBE

.END

Table A.11 SPICE ﬁle of Fig. 3.7

SCHORT CIRCUIT CURRENT
* MACROMODEL LF355
VIN 10 SIN (O 10 SK)
VP+ 2 0 15

VP- 3 O -15

RL 4 O 1
X114234LF355
.TRAN lOOU .4m 0 IOOU
.LIB LF355.LIB

.PROBE

.END

Table A.12 SPICE ﬁle of Fig. 4.1a

NONINVERTING AMPLIFIER
* DEVICE LEVEL UA741
VIN 1 OSIN(02 1K)
VP+ 2 0 15

VP- 3 0 -15

RL 4 0 10K

R2 5 4 9K

R1 5 0 1K

X115 2 3 4 UA741A
.TRAN IOU 2M 0 10U
.LIB UA741D.LIB
.PROBE

.END

Table A.13 SPICE ﬁle of Fig. 4.1b

MACROMODEL UA741
VIN 1 OSIN(02 1K)
VP+ 2 O 15

VP- 3 O -15

RL 4 0 10K

R2 5 4 9K

R1 5 0 1K
X115234UA741
.TRAN lOU 2M 0 IOU
.LIB 741M.LIB
.PROBE

.END

137

Table A.14 SPICE ﬁle of Fig. 4.2b

NONINVERTING AMPLIFIER
* MODIFIED MACROMODEL UA741
VIN l O SIN (O 2 1K)

VP+ 2 O 15

VP- 3 O -15

RL 4 0 10K

R2 5 4 9K

R1 5 0 1K
X115234UA741

.TRAN lOU 2M 0 lOU

.LIB MICROSIMLIB

.PROBE

.END

Table A.15 SPICE ﬁle of Fig. 4.4a

DC PSRR DEVICE LEVEL UA741
VD 1 0 -
EP+ 2 0 6 0 1

EP— 0 3 6 0 1

VP 6 0

RP 6 0 1K

RL 4 0 10K

X110 2 3 4 UA741A

.DC VD -400U 100U 2.5U VP 3 15 3
.LIB UA741D.LIB

.PROBE

.END

Table A.16 SPICE ﬁle of Fig. 4.4b

DC PSRR OF UA741 MACROMODEL
VD l O

EP+ 2 O 6 O 1

EP- 0 3 6 O 1

VP 6 0

RP 6 0 1K .

RL 4 O IOK

X110 2 3 4 UA741A

.DC VD -200U ZOOU 2U VP 3 15 3
.LIB 741M.LIB

.PROBE

.END

Table A.17 SPICE ﬁle of Fig. 4.40

DC PSRR OF MODIFIED UA741
* MACROMODEL

VD 1 0

EP+ 2 0 6 0 1

EP— 0 3 6 0 1

VP 6 0

RP 6 0 1K

RL 4 0 10K

X110 2 3 4 UA741A

.DC VD -200U 200U 2U VP 3 15 3
.LIB MICROSIMLI'B

.PROBE

.END

138

Table A.18 SPICE ﬁle of Fig. 4.6a

CLIPPING VOLTAGE DEVICE LEVEL
VD l O

VP+ 2 0

VP- 3 O -15

RL 4 0 10K '

X110 2 3 4 UA741A

.DC VD -4OOU IOOU 2.5U VP+ O 15 5
.LIB UA741D.L[B

.PROBE

.END

Table A.19 SPICE ﬁle of Fig. 4.6b

CLIPPING VOLTAGE OF THE

* MODIFIED MACROMODEL UA741
VD l O

VP+ 2 0

VP- 3 0 --15

RL 4 0 10K

X110 2 3 4 UA741A

.DC VD -0.4m 1m SU VP+ O 15 5
.LIB UA741D.LIB

.PROBE

.END

Table A.20 SPICE ﬁle of the modiﬁed microsim macromodel

*CONNECTIONS: + - VP+ VP- VOUT
.SUBCKT UA741 301 302 3 4 5
Cl 11 12 8.661E-12

C2 6 7 30.00E-12

DC 5 53 DX

DE 54 5 DX

DLP 90 91 DX

DLN 92 90 DX

DP 4 3 DX

EVP+ 301 1 TABLE {V(3)} =
+ (3,85.25E-6) (6,6l.7E-6) (15.0)
+ (20,-34.27E-6)

EVP- 2 302 TABLE {-V(4)} =
+ (3,85.25E-6) (6.61.7E-6) (15,0)
+ (20,-34.27E-6)

FB 7 O POLY(S) VB VC VE VLP VLN
+ O 10.61E6 -10E6 10E6 10E6 -lOE6
GA 6 O 11 12 188.5E-6

[BE 10 4 DC 15.16E-6

HLIM 90 O VLIM 1K

Q1 11 2 l3 QX

Q2 12 l 14 QX

R2 6 9 100.0E3

RC1 3 11 5.30553

RC2 3 12 5.305E3

REl 13 10 1.836E3

RE2 14 10 1.836E3

REE 10 O 13.19E6

ROI 8 201 50

R02 7 O 100

*CMRR FIX

GCM O 6 85 O 5.961E-9

GCMl O 83 10 O le-2

RCMl 83 84 100

LCMl 84 O 1.592mH

GCM2 O 85 83 0 le-2

RCM2 85 86 100

LCM2 86 O .1592mH

Rx 86 O 1000

* IVP FIX

VIOUT 201 5 0

D5 3 207 DX

R5 207 0 lMEG
F5 207 0 VIOUT 1
D6 204 4 DX

R6 204 0 lMEG
F6 204 0 VIOUT 1
RP 3 4 18.16E3
VB 9 0 DC 0

a

* CLIPPING FIX

*

EVC 3 530 TABLE {V(3)} = (0.0.6128)
+ (5, 1.253) (20,1.253)

*

VC 530 53 DC 0

VB 54 4 DC 1

VLIM 7 8 DC 0

VLP 91 0 DC 40

VLN O 92 DC 40

.MODEL DX D(IS=800.0E-18 RS=1)
.MODEL QX NPN(IS=800.0E-18

+ BF=93.75)

.ENDS

LIST OF REFERENCES

[1]

[2]

[3]

[4]

[5]

[6]

[71

[8]

[9]

LIST OF REFERENCES

G.R Boyle, B.M. Cohn, D.O. Pederson, and J.E. Solomon, "Macromodeling of
Integrated Circuit Operational Ampliﬁers," IEEE J. Solid-State Circuits, vol. sc-9,
pp. 353-363. Dec .1974.

Walt Jung, "Models can mimic behavior of reallop-amps," Electronic Design, pp.
71-79, Oct. 25, 1990. ’

G. Krajewska, "Characterization and modeling of FET-bipolar operational
ampliﬁers," M.A.Sc thesis, Univ. Toronto, Toronto, Ont., Canada 1979.

B.M. Cohn, D.O. Pederson, and J.E. Solomon, "Macromodeling of operational
ampliﬁers," in ISSCC Dig. Tech. Papers, Feb. 1974, pp. 42-43.

D.O. Pederson and J.E. Solomon, "The need and use of macromodels in IC
subsystem design," in Proc. 1974 IEEE Symp. Circuits and Systems.

G. Krajewska, and RE. Holmes, "Macromodeling of FET/bipolar operational
ampliﬁers," IEEE J. Solid-State Circuits, vol. sc-.14, pp. 1083-1087, Dec. 1979.

AS. Sedra, and KC. Smith, Microelectronic Circuits, CBS College Publishing,
1987.

GM. Wierzba,Short course: "SPICE Macromodeling of Analog IC’s," Willow
Electronics Inc, Okemos MI, 1992.

Linear Circuits: Operational Ampliﬁer, Comparator, and Building Block
Macromodels Level 1, Level [1, Data Manual, Texas Instruments, Inc., Dallas TX,
1992.

[10] C. Turchetti, and G. Massetti, "A macromodel for integrated all MOS operational

ampliﬁer," IEEE J. Solid-State Circuits, vol. sc-18, no. 4, pp. 389-395, Aug. 1983.

140

 

141

[11] G. Casinovi and A. Sangiovanni Vincentelli, "A Macromodeling Algorithm for
Analog Circuits," IEEE Trans. Computer-Aided Design, vol. 10, pp. 150-160, Feb
1991.

[12] G.K.C. Chen and J. Whalen, "Macromodel Predictions for EMI in Bipolar
Operational Ampliﬁers," IEEE Trans. Electromagnetic Compatibility, vol. EMC-22,
pp.262-265, Nov 1980.

[13] F. Goodenough, "Mixed-Sidnal Library Used Breadboard and Simulation,"
Electronic Design, pp. 159-163, July 25, 1991.

[14] M. Alexander and DE Bowers, "Op-amp macromodel provides superior in high-
frequency regions," Electronic Design, pp. 155-164, Mar. 1, 1990.

[15] M. Alexander and DP Bowers, "New Spice Compatible op-amp model boosts ac
simiulation accuracy," Electronic Design, pp. 143-154, Feb. 15, 1990.

"I1111111111111111"