fur?! {Sf-r...

Influlr...£n .. pt.

              

 

.._....n. .1"; .
5“,... .
. in?
wmhvnafimwfififli
_ .14 .
.knmuufigmxnafln: .
fixwmw»? «gang

       

         
                

i : I355}... v
:finulflulflukh‘. ‘—

navy-.3 .-
I‘ I

  

 

. 9 ‘l't I‘O. :l.|\.' .vs..l‘l

I .! c (I. v I .‘lpl... Illc'l.h.‘lfir'.

. '1). 5,... Eh. I! ;t‘lirl I:
..I\.L.01:¢.Il'ubl| .ulll .10 o‘1

-: .1: It b’lll.31\l.ll..¢lo¢99.ll
1.1-! .1;»5-...u¢'.'(l8|41uo‘t
..._.. ..lv.| till.) !|‘.l
Y . . . 1'3... - '3.
.90... I-y-l1.\ 1.1 .I-I% al“...
I .. I40. . \ .2|l..t:£|0. lit-‘11-
3 I I. 01')». {Kalli 31.11! ‘1
13...: .. I- I {0-1019 ilellilu
. .. .0 It. I. . 11.-.!v'lvbll
0.12! t lIII.n’s‘i.v0 1-514) ¢l
A ((3.!!! v 3 .151". c :1!
. I x. hurl... "IQI‘I‘ !
- .I. . A I- lilo: ....on.lo|;.l:llfll)1 A
z A -u.‘ .n 0013.15 i0-
. .Y. -.l!.|bz.ll {‘3‘ . 1

 

D» . life-0.": |..\!it§ ‘1
av: v1-5 ..alvl.'lln .lAII-‘C O
A 2*; ’50 in .. Ivalnvtfk‘l‘l
‘‘‘‘‘‘‘‘‘‘ § II. I. n'illll: :« -t’“ ‘10.
n v. . . t \..v \‘; l ."|""
| (IMF E (‘1‘!
' w I Iult. .l‘ll‘l l
{‘l. tK’krl n.|||| '4.‘
. ‘ r U .Sval'lv .0. [\IIIII‘I .-
‘j {tic y"¢‘.0". " I'll.
«L .llu.7. {31”}. (In! l..-
11141] IN gil}.ll}|
.r v ..-1I.II‘III £121:
l.l It“ ltt.nlll.llvllll.b|‘u
.. I \{|(udlr kl.‘ .‘.ii-
I 73'2v. \ Ic| lv till‘IOI'x»! u'l'
A‘f ill.)l|'b 1.}lln
c l to -.'.'ll|'rnl|¥ ‘ol...’

   

  

$37.

    
      

 

. . . . ..a|.......r:|yx Iilviiu I'll
1| 3. . .Illll . {Olivifvtoll
I. . I‘luL .Iav ‘1.t..>' \ li‘. ~A. . ‘r’n "uni." {rilli‘
.- ,bln‘f . I 4'? \I.4v .01 hilt," illl I. I.‘ r! »
- o I .1»
.I....o . I I . .i A v I .ur . .. . 6.1... l... . . . J . .I l . . .6. . .. .’I. 1 . I \I
. .A.\.l.rt.a..fl..ou|.hl. 2 Vs...“ hulk 17.1.2.1... :3! 0‘ z . . 21.. ' I: ..u....!..... . 5, .u :40 I .0193“: I. .nrA o. -. -- o .- . u “1..-- laws 3 9.1.11! - 1 01%.: .D
. . . 4 . i. . V . . . . . u. . . . , . - -
III‘ I " lll' ' ‘l ' l I! ullll'

'HESIS

////////////////////////////////////////////I

This is to certify that the

dissertation entitled

Design and Test of Current-mode Signal
Processing Circuits

presented by

Shoba Krishnan

has been accepted towards fulfillment
of the requirements for

Ph.D. Electrical

 

 

degree in
Engineering

ZQLQM f.)

Wrofzéor

Date ’ ¢

MS U is an Affirmative Action/Equal Opportunity Institution 0-12771

 

 

v

LIBRARY
Michigan State
University

 

 

 

PLACE IN RETURN BOX to remove this checkout from your record.
TO AVOID FINES return on or bdore date due.

ll DATE DUE DATE DUE DATE DUE ll

 

 

 

 

 

 

 

 

 

 

it

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

e JI

MSU Is An Affirmative Action/Equal Opportunity Institution
czbimmpma-pd

 

 

 

Design and Test of Current-mode Signal Processing Circuits

BY
S haba Krishnan

A DISSERTATION

submitted to
Michigan State University
in partial fulfillment of the requirements

for the degree of
DOCTOR OF PHILOSOPHY
Department of Electrical Engineering

1993

ABSTRACT

Design and Test of Current-mode Signal Processing Circuits

By
Shoba Krishnan

The shrinking feature sizes of devices and their increasing density make it
necessary that a reduced supply of 3.3V and lower operating voltages be used in order to
enhance performance and reliability. The effects of this reduction are especially
impressive for battery-operated systems, as this reduces power drain, which extends
battery life and allows for smaller and lighter portable equipment. As pressures increase
on VLSI designers to use lower power, voltage-mode techniques will deteriorate in
performance due to reduced dynamic range and operating speeds. Analog design has
historically been viewed as a voltage-dominated form of signal processing and, all too
often, the electronics engineer will think in voltage terms rather than current simply
because of the unavailability of current-mode signal processing circuits. Current-mode
circuits, circuits in which signals are processed mainly in the current domain, will become
increasingly important and attractive as they improve dynamic range and operating speed
and have simpler circuin and lower power consumption. In this study, these inherent
advantages of current-mode techniques are applied to the design of data-acquisition and
conversion circuits.

To decrease costs and increase performance of electronic circuits, it has become

increasingly necessary to integrate both analog and digital circuits on-chip, thus making the

fabrication process very complicated. Current-mode circuits generally do not require high
precision resistors or capacitors and can be designed almost exclusively with transistors
making them fully compatible with most standard digital CMOS processes. Matched
currents are typically generated using current mirrors which depend on good component
device matching. Although the use of laser-trimming technology may result in good
component device matching, the fabrication process is costly. This work develops and
analyzes current-mode signal processing circuits in MOS technology that achieve their
functionality without the need for well-matched components.

In real-time applications, it is important to achieve validation of the data generated
from data-acquisition and conversion elements. Even though analog MOS circuits are
becoming increasingly sophisticated in terms of checking and correcting themselves, the
techniques used may not be appropriate when a fatal fault occurs during real-time
operation. It would be preferable for the circuits to be designed such that they will indicate
malfunction during normal operation and will not produce an erroneous result without an
error indication. This dissertation implements time redundancy techniques in analog circuit
design for reliability enhancement. In addition, current-mode Built-In Self—Test (BIST)
structures are developed to increase the number of test points in a circuit, while still keeping
low pin overhead.

Sensor arrays, in which signal processing is integrated with the sensor, are being
employed in many applications. The requirement on speed of the data-acquisition and
conversion circuits in such implementations is not very high, but the reduction of the size
and power consumption is the most important. Thus, the developed current-mode signal
processing circuits and diagnosable design methodologies are well suited for the design of

reliable integrated sensor arrays.

To my parents

Alamelu and K alyana K rishnan

iv

ACKNOWLEDGEMENTS

I would like to thank my advisor, Dr. Chin-Long Wey, for his guidance and encour-
agement throughout my graduate studies and this research. I would also like to thank my
committee members, Dr. J. Resh, Dr. G. Wierzba, and Dr. J. B. Eulenberg for sharing their
time and advice through the course of this dissertation. I am very grateful to my parents,
Alamelu and Kalyana Krishnan, and my husband, Venkatesh, for their constant concern
and encouragement and direct assistance in the preparation of this manuscript. I would es-

pecially like to thank my friend, Sondes, for her continual support and help.

 

TABLE OF CONTENTS

LIST OF TABLES ........................................................................................
LIST OF FIGURES ........................................................................................

Chapter 1: Introduction ............................................................................
1.1 Potential of Current-mode Signal Processing Circuits ............
1.2 Importance of Reliability .........................................................

1.3 Dissertation Organization .................................................................

Chapter 2: Background ..............................................................................
2.1 Data-acquisition and Conversion Techniques ........................
2.1.1 Sample-and-hold (S/H) Circuits ...................................
2.1.2 Analog-to-Digital (A/D) Converters .............................

2.2 Current-mode Circuits ...............................................................
2.2.1 Current Minors ...........................................................
2.2.2 Current Copiers ...........................................................
2.2.3 Dynamic Current-mode Signal Processing Circuits ......
2.2.3.1 Current-mode Multiplier ............................................
2.2.3.2 Current-mode Divider ................................................
2.2.3.3 Current-mode A/D Converter ...................................

2.3 Fault-tolerant and Testable Circuit Design ...................
2.3.1 Fault Tolerance .......................... . ..................................

2.3.2 Testability Techniques ................................................

vi

Chapter 3: Current-mode Data-acquisition and Data-conversion
Circuits ' ....................................................................................
3.1 Bipolar Current Copier ............................................................
3.1.1 Circuit Design and Operation ........................................
3.1.2 Analysis .........................................................................
3.1.3 Experimental Results ....................................................
3.2 Current-mode Shift Register .................................................
3.2.1 Operation Principle ........................................................
3.2.2 Design Considerations .................................................
3.2.3 Simulation Results ........................................................
3.3 Current-mode Divider Circuit .................................................
3.3.1 Method of Operation ...................................... '. ...............
3.3.2 Performance Estimation .................................................
3.3.3 Experimental Verification .............................................
3.4 Successive-approximation AfD Converter ............................
3.4.1 Circuit Description ..........................................................
3.4.2 Analysis .........................................................................
3.4.3 Design Evaluation ..........................................................
3.4.4 Array Structures ..............................................................
3.4.5 Hardware Reduction .........................................................
3.4.6 Implementation ................................................................

3.5 Summary ................................................................................

Chapter 4: Testable Current-mode Circuits .........................................
4.1 Testable Current-mode A/D Converter .................................

4.1.1 Concurrent Error Detection ............................................

4.1.1.1 Fault Models .......................... ‘ ..................................

4.1.1.2 Fault Coverage .........................................................

4.1.2 Test Generation ............................................... '. .............

vii

4.1.2.1 Fault Model and Fault Effects ................................. 101

4.1.2.2 Test Generation and Fault Coverage ..................... 104

4.2 Testable Data-acquisition Circuits ......................................... 105

4.2.1 Built-In Self-Test Structures ......................................... 106

4.2.2 Experimental Results ................................................... 1 10

4.3 Summary ................................................................................. 1 12
Chapter 5: Conclusions ............................................................................ 115
5.1 Summary .................................................................................. 1 15

5.2 Contributions .......................................................................... 118

5.3 FutureResearch ...................................................................... 119
APPENDIX A: A CMOS Opamp ................................................................. 124
APPENDIX B: PSpice Files .......................................................................... 126
LIST OF REFERENCES ................................................................................ 130

viii

LIST OF TABLES -

Table 2.1 Comparison of Current Mirror Structures .............................. 22

Table 3.1 Relationship among 7, k and the Corresponding Error Terms .. 65

Table 3.2 Error Terms Obtained from Simulations ................. i ............... 71
Table 3.3 Relationship among 7, k and N .............................................. 80
Table 4.1 Type 1 Errors .......................................................................... 96
Table 4.2 Type 2 Errors .......................................................................... 97
Table 4.3 Type 3 Errors .......................................................................... 98
Table 4.4 Type 4 Errors .......................................................................... 100
Table 4.5 Error Detection ....................................................................... 100

Table A.1 Simulated Characteristics of Opamp ...................................... 125

Figure 1.1
Figure 1.2
Figure 2.1
Figure 2.2
Figure 2.3

Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8

Figure 2.9

Figure 2.10

Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3.8

LIST OF FIGURES

A Sensor Array Implementation

000000000000000000000000000000000000000000000

Testing of the A/D Converter

000000000000000000000000000000000000000000000000000

A Sample-and-hold Circuit

000000000000000000000000000000000000000000000000000000

Block Diagram of a Time Interleaved A/D Converter ............
Successive-approximation A/D Converter:

(a) Block Diagram; and (b)Voltage Waveform ...................
A Simple N-Channel Current Mirror
Simple Current Copier: (a) NMOS Copier; and (b) PMOS Copier

Active NMOS Copier

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

00000000000000000000000000000000000000000000000000000000

Current-mode Multiplier
A Highly Accurate Current Divider: (a) Schematic Diagram;

and (b) Switching Sequence ...................................................
Current-mode A/D Converter: (a) Schematic Diagram; and
(b) Switching Sequence

000000000000000000000000000000000000000000000000000000000

The Concept of Time Redundancy .............................................
Bipolar Current Copier: (a) Simple Copier; and (b) Active COpier
Experimental Results of a Bipolar Current Copier

Unidirectional Limitation of NMOS and PMOS Copiers

PSpice Simulation of a Bipolar Current Copier

OOOOOOOOOOOOOOOOOOOOOOO

PSpice Simulation of a Bipolar Active Copier

Current-mode Shift Register Using Simple Current Copiers ......
Switching Sequence for Load/Shift Operation ........................

Operation Sequence during Load/Shift:(a) Parallel Loading; and
(b) & (0) Serial Shifting

000000000000000000000000000000000000000000000000000000

10
14

16
19
24
27
29

29

32 '
38
42
45
46
48
49
51
5 1

52

Figure 3.9 A Current-mode Shift Register Using Active Current Copiers

Figure 3.10

Figure 3.11
Figure 3.12
Figure 3.13
Figure 3.14
Figure 3.15
Figure 3.16
Figure 3.17
Figure 3.18
Figure 3.19
Figure 3.20
Figure 3.21

Figure 3.22

Figure 3.23
Figure 3.24

Figure 3.25

Figure 4.1
Figure 4.2

Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6

ND Converter

(b) Combined CV (CCV) Circuits: CCV0 and CCVe

Simulation of the Current-mode Shift Register: (a) Varied

Inputs; and (b) Output of the PMOS Copier Load

Simulation of the Shift Register with Active Copiers

Error Effects of the Sample-and-hold Procedure

Improvements to the Acquisition Procedure

The Alternative Current-mode Divider ................................

Operational Sequence of Divider

PSpice Simulations of the Current-mode Divider
Divider Operation with 5% Mismatch ....................................
Divider Operation with 10% Mismatch

Experimental ErrOr Terms

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

Comparison of Error Terms

Block Diagram of a Current-mode Successive-approximation
Proposed Current-mode A/D Converter: (a) Schematic Diagram;
(b) Current Copying Sequence; and (c) Switching Sequence

A Converter Array with two CV Circuits
Converter Arrays (a) RG(l) Circuit; (b) RG(I) Circuit with
2-by-3 CV Array; and (c) RG(2) with 4-by-4 CV Array
Hardware Reduction (a) An Array with 4 CV Circuits; and

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

00000000000000

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

CED Structure with AL Implementation

Proposed Current-mode A/D converter with CED Design:

(a) Schematic Diagram; and (b) Switching Sequence ....................

Modified Current-mode A/D Converter

0000000000000000000000000000000

An BIST Structure Using Simple Current Copiers ...............

An Improved BIST Structure with Active Current Copiers
BIST Tests for Various Faults

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

xi

53

56
57
59
60
62

67
68
70
72
72

74

76
82

84

86
91

Figure 5.1
Figure 5.2
Figure A1

A Sensor Array Implementation

oooooooooooooooooooooooooooooooooooooooooooo

Temperature Dependence of Bipolar Copier Operation .........

A Two-stage CMOS Opamp

xii

ooooooooooooooooooooooooooooooooooooooooooooooooo

Chapter 1

Introduction

 

The present trend in digital integrated circuits (ICs) towards submicron
technologies with 3.3 V power supplies is increasing. The shrinking feature sizes of
devices and their increasing density makes it necessary to have reduced supply and
operating voltages to help enhance their performance and reliability [1]. The widespread
use of MOS technology, with its unique ability to accurately store and transfer voltages or
charge packets, led to the development of analog IC techniques in which voltage was used
as the signal. These techniques, though quite successful in many applications, have
deteriorated in performance due to reductions in the available supply voltage and the
move to ever smaller geometries [2]. Thus, there is difficulty in designing high-linearity,
wide-dynamic-range and high-speed voltage-mode analog circuits.

Analog circuit design has historically been viewed as a voltage-dominated form of
signal processing. This has been apparent in analog IC design where generally current
signals are readily transferred into the voltage domain before any analog signal processing
takes place. All too often, transistors are assembled into voltage-oriented circuits and
systems, and this form of processing is assumed to be most appropriate for the task,
although BJTs and FETS are both current-output devices. The electronics engineer will
think in voltage terms rather than current simply because of the unavailability of current—
mode signal processing circuits such as data-acquisition and data-conversion systems [3].

Sample-and—hold circuits (S/H), analog-to-digital (A/D) converters and digital-to-

analog (D/A) converters form an integral part of real-time systems. Validation of the data

generated from these elements for real-time applications is very important. Analog MOS
circuits are becoming increasingly sophisticated in terms of checking and correcting
themselves [4]. They use self-correcting, self-compensating, or self-calibrating techniques
to eliminate errors traditionally associated with analog circuits such as offset, low
frequency noise, and non-linearities [5,6,7]. However, these techniques may not be
appropriate when a fatal fault occurs during real-time operation. It would be preferable for
the circuits to be designed such that they will indicate malfunction during normal operation
and will not produce an erroneous result without an error indication. _

This study addresses the potential of current-mode circuits for signal processing.

and presents their applications and reliability issues for real-time systems.
1.1 Potential of Current-mode Signal Processing Circuits

A current-mode circuit may be taken to mean any circuit in which current is used
as the active variable in preference to voltage. Current-mode circuits have emerged over
the last decade as an important class of analog circuits with properties that enable them to
rival their voltage-mode counterparts in a wide range of applications [8]. Recently, a
number of novel circuit functions and topologies have been explored on the broader front
of current-mode analog circuits, opening up wider areas of interest. Current conveyors and
related current-mode circuits such as current converters, amplifiers and current rectifiers‘
are only a few of the circuits that have been successfully constructed using Bipolar, MOS,
BiCMOS, GaAs, and optical technologies [8].

There are many advantages to be gained by signal processing embracing current-
mode techniques. Due to the nonlinear I-V relationship exhibited by most transistor
structures, a small change in input voltage results in a much larger change in the output
current [9]. Consequently, for a process with a fixed voltage supply, the usable dynamic
range of current-mode signals is significantly larger than that of their voltage-mode
counterparts. It has long been recognized that current manipulation is inherently faster

than voltage manipulation, since the effects of stray inductances are less severe than those

of stray capacitances [10]. Thus, there is potential for higher operating frequencies in
current-mode circuits.

To decrease the costs and increase the performance of electronic circuits, it has
become increasingly necessary to integrate both analog and digital circuits on the same 1C
[11]. The problem is that the most commonly available process, the standard digital CMOS
process, does not offer the linear components with which analog design is usually
implemented. Until recently the only solution to this problem was to develop more
complicated processes that can provide such linear components. Thus, there is a need for
circuitry that is compatible with the standard digital CMOS process. Current-mode signal
processing circuits generally do not require high precision resistors or capacitors. When
capacitors are used to store the signal, they need not display good ratio matching or good
linearity. Consequently, these circuits can be designed almost exclusively with transistors
making them fully compatible with most digital processes. Generally, current-mode
circuits do not require amplifiers with high voltage gains thereby reducing the need for high
performance amplifiers [12].

When current is used as the active parameter, the need for matched signals implies
a need for matched currents [13]. Matched currents are generally generated using current
mirrors which depend on good component device matching. Although the use of laser-
trirnming technology may result in good component device matching, the fabrication
process is costly. Therefore, it is necessary to develop current-mede circuits which achieve
their functionality without the need of well-matched components.

The continued growth of mixed analog/digital VLSI systems will ensure the need
for small size, high speed analog-to-digital and digital-to-analog converters fabricated
using commonly available digital processes. Mixed signal VLSI design is essential to
analog and digital interfacing, and the immunity of current-mode circuits to supply noise
is an important property in a mixed-mode environment. Also, in large data-acquisition
systems there is a preference for the use of current to represent the measurand as it is fairly
interference-resistant [14]. This is because of the low probability that DC currents would

be induced in data-transmission lines.

The complexity of current-mode circuits is generally less than their voltage-mode
counterparts for the same function, as currents may be manipulated to yield more effective
and efficient circuit realizations. They have also been found to be a cheaper alternative to
voltage-mode circuits for many applications. Another significant advantage rests in the
immunity of current signals to deleterious influences such as ground and power strpply
noise, debiasing, and signal line impedance [15]. These technological reasons form the
basis of many commonly used current-mode circuits.

One of the important applications of current-mode signal processing circuits is in
the design of integrated sensors. Integrated sensors have the inherent advantages of small
size, light weight, high performance, low cost, and high reliability. They provide a better
signal-to-noise ratio, improved sensitivity, and a digital output which is less prone to
noise. Smart sensor arrays improve overall system performance by changing the system
architecture to take advantage of signal processing that is integrated with the sensor [16].
A sensor array chip must include data-acquisition and conversion circuits as well as an
array of sensing elements, as shown in the block diagram of Figure 1.1. Each sensing
element may include a signal conditioning circuit and/or a simple analog signal processor.
When a scan has been completed, each cell in the array will be holding the raw sensing
data as either voltages or currents which are read out and converted by either a high-speed
current-mode A/D converter, or an array of medium-speed converters. The requirement on
speed of the acquisition and conversion circuits is not very high in many such
implementations, but the reduction of the size and power consumption is of utmost
importance [17].

This dissertation develops a current-mode shift register that can be wound through
the array and simultaneously load the data which can then be serially read out to be
converted. This dissertation also presents the design of current-mode A/D converter arrays
in which each subconverter does not rely on high gain amplifiers or well-matched
components to achieve high resolution. Incorporating parallel signal processors into an IC

sensor array will increase the overall computation rate significantly.

 

Sensors

   

Current-mode Digital
AID Converter Latches

I

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

Current-m o I e
Analog Shift Register

Figure 1.1 A Sensor Array Implementation

One of the primary motivations of this work. therefore, is to apply the inherent
advantages of current-mode techniques to the design of data-acquisition and conversion
circuits. The goal of this dissertation is to develop, analyze and construct these current-
mode signal processing circuits in MOS technology and to explore the limits of their

applications.

1.2 Importance of Reliability

For real-time applications, in general, the validation of data from A/D converters is
accomplished by using an extra D/A converter and an analog window comparator [18], as
shown in Figure 1.2, where a high-resolution and high-accuracy D/A converter is needed
and the comparison is performed in an analog manner. Therefore, the validation must
highly depend upon the reliability of both the D/A converter and the window comparator.
Although their reliability may be improved by using sophisticated testing schemes to weed
out faulty components [19], such off-line or static tests cannot identify the transient faults
that occur during on-line operation. Therefore, it is obvious that a mechanism for
concurrent error detection (CED) [20-22] must be installed to detect such faults before
they cause undesirable results.

One of the objectives of this dissertation is to implement time-redundancy
techniques in analog circuit design for reliability enhancement of real-time systems. In this
study, an alternative current-mode A/D converter with CED capability is presented in
which the Alternating Logic technique [22] is implemented. The fault model considered
here is the single stuck-at fault at the switching elements. The A/D converter is capable of
detecting all transient faults and most permanent faults.

For more than two decades, the subjects of automatic testing and fault diagnosis of
electronic circuits have been of interest to researchers in the area of circuits and systems
[23-28]. Recently, with rapidly increasing complexity :and size of modern electronic
systems, these subjects have become more important and critical. Due to the difficulty of

current measurement in an analog circuit, most of the fault diagnosis algorithms have been

 

 

 

 

 

 

 

 

 

 

 

 

 

Analog Current Samgle A/D ‘ Digital
Input 132m Converter ’ output
Error _
Window Indication
—>

i__!, Comparator

 

 

 

 

D/A
Converter

 

 

 

 

 

 

 

Figure 1.2 Testing of the A/D Converter

developed requiring only node voltage measurement [23-26]. However, it has been shown
that the use of both current and voltage measurement can simplify the diagnosis process
significantly [27,28]. This dissertation presents alternative Built-In Self-Test (BIST)
structures in order to allow the voltage and current test data measured at various test points

to be shifted out for fault diagnosis.
1.3 Dissertation Organization

This dissertation is organized as follows. Chapter 2 presents background
knowledge of data-acquisition and conversion circuits in general and existing current-
mode signal processing methods specifically. The concepts of reliability and fault testing
applied in diagnosable design are also touched upon.

Chapter 3 describes in detail several basic elements developed, followed by
descriptions of data-acquisition and conversion systems in which they are used. A bipolar
current copier that forms a sample-and-hold building block is first presented. A current-
mode shift register used as a data-acquisition system is also discussed. An accurate
current-mode divider circuit which does not rely on well-matched components is later
described. A successive-approximation A/D converter that can be adapted into a parallel
array structure with a common reference unit is finally illustrated. Several design issues
are addressed, and simulation results give a thorough understanding of the functioning and
performance of these current-mode signal processing circuits. 9

Chapter 4 describes the incorporation of reliability into these circuits and presents
the diagnosable current-mode circuit design methodology. Finally, Chapter 5 summarizes

this dissertation and contributions of this study as well as future research topics.

 

Chapter 2

Background

 

This chapter briefly reviews the background knowledge of data-acquisition and
conversion circuits in general and existing current-mode signal processing methods. In

addition, the concepts of reliability and testability are also discussed.

2.1 Data-acquisition and Conversion Techniques

Sample-and-hold circuits are the essential elements in data-acquisition systems
and contribute significantly to their performance. Analog-to-digital (A/D) and Digital-to-
analog (D/A) converters are the primary components of data-conversion, and they have
been implemented using several techniques. The operation principles and characteristics

of different sample-and-hold elements and A/D converters are described in this section.

2.1.1 Sample-and-hold (S/H) Circuits

A sample-and-hold (S/H) circuit is an essential building block of sampled data
systems and its operation and properties are described in this section. The function of a S/
H circuit in its simplest configuration is to take sampleS‘from an input signal during the
sample mode and then to hold the last value of the input signal for a certain time interval,

called the hold mode [29]. An elementary S/H circuit is shown in Figure 2.1. The switch

 

10

 

 

 

Figure 2.1 A Sample-and-hold Circuit

11

M1 is implemented by a single or complementary MOS transistor. During the sample
mode the input voltage source vi(t), which has an internal resistance R, is connected to the
hold capacitor Ch via the MOS switch M1. The capacitor voltage follows (tracks) the input
voltage assuming that the time constant RC“ is small enough. When the ‘hold’ mode is
selected and the switch is opened, the capacitor voltage remains fixed at the input signal
level. To avoid the discharging of the hold capacitor Ch by an output circuit, a buffer
amplifier (voltage follower) is usually used. If necessary, a second voltage follower is used
at the input of the S/H stage to avoid loading the input signal source.

In the ideal S/H circuit, tracking is error-free; i.e. the capacitor is immediately
charged and the change from the sampling to the hold mode and vice-versa occurs
instantaneously. However, there are several factors that determine the performance of
practical S/H elements. For example, in the switched capacitor implementation of the
elementary S/H circuit, noise and unbalanced charge injection are the major sources of
error of the sampled voltage.

The most important S/H circuit parameters are defined as follows [29]:

(1) Acquisition Time: The time required after receipt of the sample command for
the hold capacitor to charge to a specified voltage change and remain within a specified
error band.

(2) Slew-Rate: The maximum rate of change of the output voltage after receipt of
the sample command and for a voltagestep applied to the input.

(3) Aperture Uncertainty Time: The time variation or jitter in the opening of the
sampling switch.

(4) Hold-Mode Droop Rate: The output voltage change per unit 'of time during the
hold mode.

(5) Offset: The extent to which the output deviates from zero for zero input.

(6) Feedthrough Offset: The step error occurring at the initiation of the hold mode
caused by the clock voltage feedthrough through the gate-source or gate-drain overlap

capacitances and the unbalanced channel charge stored in the MOS switch.

12

2.1.2 Analog-to-Digital (A/D) Converters

A/D converters are used to transform continuous-time or discrete-time analog
signals (typically voltages) to digital data which can then be easily processed, stored, and/
or transmitted digitally. An A/D converter connected between some analog sensors and a
digital computer, must be able to accept the outputs from these sensors as its inputs. It
should provide its digital outputs to the computer and its complete operation and
performance must be tailored to that of the overall system. For example, there is no need
for a converter to have 12-bit accuracy if the signals from the sensor are accurate only to
8-bits.

When the input signals to the converter change as a function of time, which is most.
often the case, it is important to consider all the factors that determine the dynamic
behavior of a converter [29]. A/D conversion is ideally considered to take place instantly
but in real converters this process takes a finite amount of time for completion during
which the output cannot be updated. The dynamic parameters of the converter primarily
characterize the speed of converter operation. The most important of these parameters are
conversion time, conversion rate (often called throughput rate) and aperture effects (delay,
jitter). Conversion time is the amount of time required for an A/D converter to perform
one complete conversion under the least favorable conditions. Alternatively, to determine
the conversion speed one uses the conversion rate (throughput rate) defined as the
maximal number of repetitive analog-to-digital conversions per second. It is calculated as
the reciprocal of the total time required for one successful conversion.

Depending upon the structure and the principle of operation, A/D converters can
be [divided into several different categories such as parallel (direct), serial (or sequential),
and serial/parallel. Based on the speed of conversion, A/D converters can be divided into
three groups: high-speed, medium-speed, and slow-speed [29]. This categorization is
based on the conversion time which is 50nsec for a high-speed converter while the

medium-speed and low-speed types convert at 50nsec and 100msec, respectively.

13,

W

High-speed A/D converters find application in the encoding of composite video
signals. Parallel or flash converters are the fastest and largest of this group. Both pipelined
and time-interleaved array converters offer a fast conversion rate and a smaller circuit.

In a parallel or flash A/D converter, the reference is divided into 2N nominally
equal segments, thus generating all possible signal quantization levels. It employs the
most straightforward approach to achieve high-speed analog-to-digital conversion by

performing 213“ simultaneous voltage comparisons with the ZN'l

equally spaced reference
sources, where N is the number of bits. If the input signal is higher than the quantization
level under consideration, an output bit of 1 is generated; otherwise an output bit of 0 is
produced. This digital code is then converted to the desired binary code by an encoder
circuit. The main advantage of flash A/D converters is their high conversion rate.
However the exponential increase in the number of comparators as a function of
resolution limits the practicality of such converters.

In time interleaved array A/D converters, n identical N—bit A/D converters with S/
H stages are connected in n parallel channels as shown in Figure 2.2. In each channel, the
input signal is sampled and held and then converted at a rate of 1/nT. By staggering the S/
H stages in time such that the sampling in the second channel is'T seconds behind that in
the first channel and so on, the input signal can be sampled and held each T seconds by a
different A/D converter in the structure. Hence, the overall system achieves a conversion
rate n times higher than that of the building A/D subconverter. A buffer and a digital
multiplexer stage is used at the output to service the conversion channels one at a time. For
high-speed input signals very stable and regular sampling intervals are required. Even a
small, deviation from the nominal sampling frequency of l/nT may cause considerable
error since it leads to overlapping the input signals. A high-speed analog demultiplexer can
be used to relax the sampling accuracy requirement by converting the analog input signal
into n lower-speed sampled and held data signals which are fed into the appropriate sample-

and-hold stage.

I4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S/H A/Dl 2
_. S/H A/D2 :3 Buffer Di ital
Analog and . g
In ut digital '
p . Output
multiplexer
-S/H W n 2)

 

 

 

 

 

 

 

 

Figure 2.2 Block Diagram of a Time Interleaved A/D Converter

15

The pipelined A/D converter architecture is such that the pipe consists of m basic
stages, each stage consisting of a S/H circuit and a low-resolution low-speed A/D
converter. The input signal flows sequentially through successive stages, so the converter
produces an N-bit digital word over several sampling periods rather than one period. The
main idea of a pipelined A/D converter is to insert S/I-I structures between the subconverter
stages in order to operate all the stages concurrently thus achieving a high conversion rate
which is almost independent of the number of stages. The principal disadvantage of

pipelining is the requirement of high-speed and high-precision S/H structures.

M I. -S I 3 [D f |

This classof A/D converters commonly employ successive-approximation and
cyclic or algorithmic conversion techniques. Both techniques offer a relatively good
speed-size performance.

Successive-approximation A/D converters require the use of a S/H stage, a signal
comparator, a D/A converter and a successive-approximation register (SAR) as shown in
Figure 2.3 (a). The input S/H stage is used to hold the analog input signal constant during
the conversion process. The converter operates on the following principle: after the reset
in the first conversion step, the SAR sets the D/A output to X,/2. Hence, the most
significant bit or MSB, (11, is assumed to be one whereas all other bits are set to zero. If the
input is higher than X,/2, the MSB is left at one; otherwise, it is reset to zero. In the next
step, the D/A converter output is set to X r/ 2 i X r/ 4 where the plus sign is taken if (11
= l and the minus sign if (11 = 0. This signal is again compared with the input and the
second most significant bit is detemrined depending on the result of comparison as seen in
Figure 2.3(b). In the following step, the output of the D/A is to be incremented or
decremented by X r/ 8 and a third comparison is performed leading to d3. The process
continues until all bits of the output word have been determined. Such a converter requires
pnly N clock cycles to complete an N-bit conversion. Mathematically, the algorithm which
describes the operation of the successive-approximation A/D can be represented as

follows:

16

 

 

 

Reset
Analog l
Input ’ + Clock
m

 

 

 

 

 

 

 

 

 

 

 

\/

Digital Output

 

 

(a)

 

 

 

 

 

 

 

 

 

 

4 mo
xr/Z‘I / xin
/ “—1
Xr/4..
L
d1=0 (12:1 d3=l (14:0 d5=l

Figure 2.3 Successive- Approximation A/D Converter :
(a) Block Diagram; and (b) Voltage Waveform

17

a
X(k) =X(k-l)-———X (2.1)
2" r
with dk = 1 if Xin >X(k) and dk = 0 otherwise

for k = 1, 2,...,N where X(0) = Xr'

A bipolar A/D conversion can be achieved by introducing a sign bit do to select
either +X, or -X,.

The cyclic or algorithmic A/D converter involves the .basic operations of
comparison, subtraction and multiplication by two. Conversion is based on holding the
reference signal constant and multiplying the signal to be converted by two during each
conversion cycle. Conversion begins with sampling the input signal, Xi", doubling it, then
comparing it with X, in order to generate the MSB d1. If 2X-ln _>. X, then d1 is set to l, X, is
subtracted from 2X,n and the difference is multiplied by two. Otherwise, (1, is set to 0 and
X,n is multiplied by two. This procedure continues according to the algorithm described by

the next set of equations until the desired resolution is achieved.
ak-l
X(k) 2 2X (k— l) + (—1) Xr (2.2)
with dk = 1 if X(k) 20 and dk = 0 otherwise

for k = l, 2,...,N where X(O) = Xi , d0 = l.

n

Wm

High resolution converters can be obtained using one of the described conversion
techniques at the expense of costly fabrication technology and/or complicated circuitry.
Two alternative techniques achieve high resolution without these burdens but their
conversion speed is negatively affected.

The integrating type A/D converter operates with a conversion cycle consisting of
two separate integration intervals. In the first interval thetanalog input signal is integrated
up for a fixed and known period of time. In the second interval the negative reference signal

is integrated down until the output voltage of the integrator returns to zero. This time period

18.

is then proportional to the input signal. At the start of conversion, the integrator and the
counter are both zeroed to guarantee stable timing. The important feature of this result is
that the digital output is independent of the integration time constant and of the clock
frequency since these parameters affect both the first and the second interval in the same
ratio. 3

In oversampling A/D converters, the input signal is sampled at a rate much higher
than the Nyquist rate, then converted to a digital stream in an interpolative modulator. The
quantized approximation of the input signal is subtracted from it and the difference is
integrated. The integrator in the loop tends to minimize the average difference of the
sampled analog input and the quantized approximation. The output of the estimator goes to
a digital-low-pass filter which averages and decimates this coarse estimate to get a finer

approximation at a lower sampling rate.
2.2 Current-mode Circuits

This section reviews some traditional concepts of current-mode circuits. Current-
mode signal processing circuits using dynamic techniques and challenges in their design

are also described.
2.2.1 Current Mirrors

The current mirror is a very useful and familiar building block in CMOS analog
circuit design. Current mirrors use the principle of matched devices such that if the gate-
to-source potential of two identical MOSFETS are equal, their currents are equal [30].
Figure 2.4 shows the implementation of a simple n-channel current mirror. The current i1
is assumed to be defined by a current source or some other means and i0 is the output or
“mirrored” current. M1 is in saturation because VDSI=Vdsr In the most general case, the

ratio of i0 to i; , is then

l9

 

 

 

+ M1 M2 +
VDSI + VDSZ
_ VGS -
- V53

Figure 2.4 A Simple N-Channel Current Mirror

2
‘__o_ _ [L1W2)[VGS_VT2) (1+AVDS2)(u02Cox2) (2 3)
i _ — _—___ —— — '
I W1L2 Vos Vrr l'HU/osr “orcoxr

where (W/L), are the aspect ratios, VT: is the threshold voltage of the MOSFETS.
Normally, the components of a current mirror are processed on the same integrated circuit
and thus all of the physical parameters such as VT, [10, Cox, etc., are identical for both
devices. As a result, (2.3) simplifies to

€9_ £1312. Lives; (24)
i, wle 1+Av '

051

If VDSZ = VDSl (not always a good assumption ) then the ratio of iO/il becomes

i L W '
__0 = (33) (2,5,
‘1 W1L2

Consequently, io/il is a function of the aspect ratios that are under the control of
the designer. However, there are three main factors that cause the current mirror to be
different than the ideal situation of (2.5). These factors are: (1) channel-length modulation,
(2) threshold offset between the two transistors, and (3) imperfect geometrical matching.

Consider the channel-length modulation effect Assuming all other aspects of the
transistor are ideal and the aspect ratios of the two transistors are both unity, then (2.4)

simplifies to

i l + XV
.—0 = {—312} (2.6)

t
1 1+AVDSI

with the assumption that the modulation parameter k is the same for both transistors. This
equation shows that differences in drain-source voltages of the two transistors can cause a

deviation for the ideal unity current gain or current mirroring.

21

Consider two transistors in a mirror configuration where both have the same drain-

source voltage and all other aspects of the transistors are identical except VT. In this case,

(2.3) simplifies to
- v v 2
‘0 GS— T2
T = (7:77) (27)
’ as T1

It is also possible that the transconductance gain K' of the current mirror is also
mismatched. Assume that the W/L ratios of the two mirror devices are exactly equal but
that K' and V1- may be mismatched. (2.3) is then written as

io K 2 (V05 - VT2)

I ..
K1 (V05 V11)

 

The third nonideal effect of current mirrors is the error in the aspect ratio of the
two devices. These are due to mask, photolithographic, etch, and out-diffusion variations.
These variations can be different even for two transistors placed side by side. One way to
avoid the effects of these variations is to make the dimensions of the transistors much
larger than the typical variation one might see. For transistors of identical size with W and
L large in value, the errors due to geometrical mismatch will generally be insignificant
compared to offset-voltage and VDS induced errors.

In most current mirror realizations, ideal mirroring is true only for a range of
voltages, and there is a minimum voltage, VMIN’ below which the realization will not be a
good approximation of the input current. This is because the MOS transistor in the
nonsaturation region is not a good current source. Even in the region where it is a good
approximation, it deviates due to the resistance r0“, which is ideally infinite. Thus, the
small signal output resistance of a current mirror is important in determining its
performance. Therefore, VMIN and rout are the two major aspects by which these mirrors
can be characterized. I

The advantage of this current mirror is its simple structure. Higher performance

current mirrors will attempt to increase the value of rout and reduce VMIN further. Several

22

improvements such as bootstrapped structures or cascode structures have also been
implemented. Table 2.1 summarizes the performance of the different types of MOS
current mirrors having unity gain from the viewpoint of accuracy (linearity), output
resistance, and VMIN [31]. Additional considerations include the size of devices where

ratio accuracy will be obtained for larger size devices.

Table 2.1 Comparison of Current Mirror Structures

 

 

 

 

 

 

 

 

 

 

 

. Accurac '
MOS Current MIITOI' (i0 = i1)y rout VMIN
: :_J
Simple Poor r0=1/(Ai0) VDS(sat)
Cascode Good gmro2 2VD3(sat)
Wilson Good gmr02/2 VGS + VDS(sat)
Regulated Cascode Good gm2r03 VDS(sat)

 

2.2.2 Current Copiers

The current mirror uses the principle that if the gate-source potential of two
identical MOS transistors are equal, the channel currents should be equal. However, the
most important limits of conventional current mirror techniques with respect to their use
in high-precision analog circuits are the current errors due to mismatch and the low-
frequency 1/f flicker noise. Both of these can be reduced by increasing the gate area WL
and the saturation voltage VDsat’ but this classical approach cannot eliminate flicker noise
or reduce the error much bClow 1% [1].

' Unlike bipolar transistors, MOSFETS do not need any gate current to control their
drain current. This property has been recently used to build current copiers or dynamic
current mirrors that do not require well-matched components [32-34]. The analog storage
capability is exploited to sequentially use the same transistor for copying and read-out

Thus, the very notion of mismatch disappears since there is only one transistor. These

23.

current copiers make practically identical copies of a given current without the need for
accurately matched componentsand are implemented as sampled-current circuits [1].

Figure 2.5(a) shows a simple current copier that consists of switches, a non-critical
enhancement-mode MOS transistor, and a non-critical capacitor. [in is copied into the
current storage cell by turning on the switches SW, ST and SQ, the capacitor will charge
up to the gate voltage needed by the transistor to achieve a drain current equal to lin- The
switches SW and SQ are then turned off to disconnect the cell from the current source;
thereafter, the cell is capable of sinking a current [in when connected to a load. Note that
the input current to the NMOS copier cell must be positive. Figure 2.5(b) illustrates a
simple PMOS copier which memorizes negative input current.

Many current-mode circuits that utilize dynamic techniques are constructed using
current copiers. The error effects of the current copiers will also affect these current-mode
circuits. Inevitable circuit non-idealities will cause the current retrieved from a cell to differ
from its original copied current. Some of the mechanisms of original-to-copy error include
clock feedthrough, leakage and channel length modulation [33,34].

The first important limitation to the precision of the above scheme is charge
injection or switch charge feedthrough. The various switches are realized by means of
transistors. To close the switch, the switching transistor is made conductive by mobile
carriers that are attracted into the channel by the gate voltage. When the switch is opened,
these carriers are released from the channel in order to block the transistor, and most of
them flow to the source or to the drain [32]. Thus, when the switch opens, a fraction Aq of

. . A . .
q flows onto the capacrtor C1, which causes an error AV = C—q 1n the stored voltage. This
I A I g AV
voltage error in turn creates a relative error in the output current equal to 7— = ",1 .
0

0
An estimate of the magnitude of this effect for the basic cell of Figure 2.5(a) can be

 

derived as follows. Assume a single n-channel transistor acting as switch SQ. If half of the

charge QsQ on the switch inversion layer is dumped onto C1, then

Q (was c (sz—sz)
AV: 1(32) : 1[ Q 0xC SQ)
l

(2.9)
l 2

 

NI

24

l

. C1
E—i P1
SW SQ

SM
m

30
ST ST
80
SQ SW
i‘l ”‘ '-
C1 m S
(a) (b)

Figure 2.5 Simple Current Copier: (a) NMOS Copier; and (b) PMOS Copier

25

where the assumption that the switch is operated in the linear region and N1 in the
_ saturation region is taken. WSQ and LsQ represent the width and length of switch SQ. C0,,
is the gate oxide capacitance per unit area (VGS'VTISQ is the ‘on voltage’ of the switch
and [1, Wm and LN, represent the electron mobility, width and length of N1, respectively.

The resulting relative change in the copier current is

I
I W i I
Al RmAV l’lCox ( 2:) N1 (WL) SQCox (VGS _ VT) 5Q ,
I— : = (2.I())
o

C
210 1

 

 

 

Simple alternations to the basic current copier'cell can help reduce some of the
errors. The use of CMOS switches may eliminate the error caused by switch charge
feedthrough. AV can also be decreased by increasing C1, with one limit given by the area
of the capacitor. It can also be decreased by reducing the total charge q in the channel in
order to reduce the fraction Aq that flows onto C1. This can be achieved by minimizing the
gate area WL and/or by controlling the gate control voltage of the switch in order to adjust
its on-conductance to the minimum required value. External gate capacitors can be used to
reduce the effects of the charge injection from switches and to allow the transistor and
capacitor geometries to be determined independently.

The various approaches to reduce the effect of charge injection on the precision of
the dynamic mirror may be combined. It may be pointed out that most of them tend to
increase the time needed to achieve equilibrium in the circuit and therefore decrease the
maximum frequency of switching. Since the input current is sampled, the bandwidth of
the mirror is in turn reduced. Thus, there exists a trade-off between speed and precision.

Another contribution to the error is due to channel length modulation which is
represented by the drain-to-source conductance gds. As shown in Figure 2.5(a), the drain
of N1 is connected to its gate during the storage phase, thus the two nodes are at the same
voltage potential. During the read-out phase, the drain potential will be different and be
equal to a value imposed by the load of the mirror. This difference in drain voltage during

the two phases produces important additional contributions to the inaccuracy of the mirror.

Because of the change in the effective channel length as VDS of N1 changes, the basic
current copying circuit of Figure 2.5(a) will supply a slightly different current during
retrieval.

These considerations show that an accurate implementation must include some
means to keep the drain voltage of N1 as constant as possible in spite of the difference. An
operational amplifier could be used for this purpose, in which case the circuit becomes an
active current copier shown in Figure 2.6. Another solution which is more compact is
obtained by adding a common gate transistor in series with the main transistor to build a
cascode structure, a technique commonly used in current mirrors.

Junction leakage is another error effect to be considered. Even with the switch SQ
turned off, a small current will flow through the reversed biased source-substrate junction.
drawing charge from C1. Over a time interval At this leakage current I leak will create a

change in voltage AV = across C1 with a resulting change in current

At
Ileak-(,7
AI = gmAV . However, as is also true for switched capacitor circuits, with usual junction
leakage currents and reasonable clock rates, this does not create a severe constraint on
circuit operation.

Since both the transconductance element and the switches consist of MOS
transistors, the copier inherently contains both thermal and I/f internal noise sources. As
with other sampled data circuits, the resulting output noise current can be separated into
two types. Sampled noise, occurring during the period when the current is sampled,
resulting in an error in the voltage held across the capacitor C1 and nonsampled or direct
noise, occurring when the copier is sinking current from a load.

Junction leakage and noise can be limited by a careful choice of switch dimensions.
capacitor sizes, and loop bandwidth. Note that larger capacitors may reduce the effects of
the thermal noises and charge injection from the switches, thus increasing the resolution.

However, larger capacitors result in slower settling time. This leads to a significant area/

resolution/speed trade-off.

27

 
  

Ksr

SQ SO Read out

0—/
KI N1
C1

Figure 2.6 Active NMOS Copier

 

 

28,

2.2.3 Dynamic Current-mode Signal Processing Circuits

Several circuits that use dynamic current-mode techniques are reviewed in this
section. These circuits form an essential part of current-mode data converters and utilize

current copiers.

2.2.3.1 Current-mode Multiplier

One obvious application of current copiers is the integer current multiplier where if the
input current [in is constant, then an output current equal to an integer multiple of I,“ can
be obtained. Figure 2.7 shows a current-mode multiply-by-two circuit which achieves
accurate signal multiplication without the need for well-matched components [9].

Initially, switches SI, 82 and 83 are turned on. After the amplifier has settled, [1 will
equal Ii". When switch S3 is turned off, the gate capacitance will cause transistor N to
“memorize” the current level. The procedure is then repeated for transistor N2 by turning
on S], S4 and S5. Once N2 has been “programmed”, an output current of 21,n is produced
by turning on 82, S4 and S6 and providing an appropriate Vout such that [out is equal to
(11+12) or ”in Ideally, the sum of the outputs of the cells is therefore an integer multiple

of [in achieved without relying on element matching.

2.2.3.2 Current-mode Divider

Current dividers are usually implemented by using resistor networks or weighted
transistors. The division accuracy of such solutions is limited by device mismatch. An
algorithmic method for dividing a given current [in by an integer factor without depending
on device matching or even linearity is depicted in Figure 2.8, for the specific case of
division by a factor of 2. The circuit does not require laser trimming, external adjustment,

or matched components [35].

29

 

 

 

 

 

 

First .
Iteration
Other
Iterations

 

 

 

 

 

 

' (b)

Figure 2.8 A Highly Accurate Current DiVider: (a) Schematic Diagram;
and (b) Switching Sequence

30

The basic operation of the current divider is described as follows. (For simplicity of
the discussion, 1,, i=1, 2, or 3. is the memorized current in transistor N, and I4 is the current
held in P4.) First, the current difference (lin-I 1) is fed to both transistors N2 and N3 by
turning on switches SO, 81, S3, S4, SS, and S6, and turning off the others. The currents
copied into N2 and N3 are determined by the mismatch between them. In order to obtain
the difference in their currents, N3 sources its copied current to P4, during the second cycle.
by turning on S7, Sg, and 35, and turning off the others. Once the current held in P4 is set.
turning on S3, S7, 81, and $2, and turning off the others, during the third cycle, will copy
the current difference (14-12) into N1, i.e., I 1: 4—12. Thus, N1 holds the current difference
between 12 and I 3. This completes an iteration of the division process and thus each iteration
takes three clock cycles. During the next iteration, this current difference is removed from
[in and is sourced to N2 and N3. Therefore, through subsequent iterations, the error reduces
to a minimal value and the current in N3 converges to [in/2. Note that, in order to zero the
current remaining in N1, only the input current [in is copied into N2 and N3 during the first
iteration. The number of iterations necessary to obtain half of the current with certain
accuracy depends on the mismatch in N2 and N3. Figure 2.8(b) illustrates the switching
sequence of the divider circuit. Let a2 and (13 be the mismatch factors of the transistors N2
and N3, respectively, then 12=0t21im l3=a31im where

2
k V —V
(I = 2( GS T2) (2.”)

2 2 2
k2(VGs‘V12) + k3 Was-VB)

 

2
k (V -V )
a3 = 3 GS 73 (2.12)

2 2
k2 (VGS‘Vrz) + k3 (VGS—VT3)

 

Note thath and VT3 are the threshold voltages of the transistors N2 and N3, respectively,

and the device transconductance k, = k', (%) where (W/L)i. i=1 or 2, is the aspect ratio
t

of the transistor Ni. Since the sensitivity of a2 and (13 to VGS is small, the values of a2 and

(13 are considered constant [35].

31

2.2.3.3 Current-mode A/D Converter

As discussed in (2.2), algorithmic (cyclic) current-mode A/D converters convert an
input current to an N-bit digital data word D using a multiply-by-two scheme . The
accuracy of these converters is often limited by the mismatching of passive components of
the circuits. An algorithmic A/D converter that combines current-mode and dynamic
techniques achieves high resolution without the need for high gain amplifiers or well-
matched components [13]. The converter, shown in Figure 2.9, starts converting for the
most significant bit (MSB) of an input current [in by turning on switches 81, $2, and S3 to
cause the current in N1 to be set to (in. Once N1 is set, S; and S3 are switched off while S4
and 85 are on to set NZ to be (in: Once the input signal has been stored on N1 and N2, twice
the input, signal is loaded into P, by turning off 81 and 85 while switching on 82, S6, and
S7. After P1 is set, 82, S4, and 87 are turned off while Sg is turned on, thus allowing the
comparator to sense the current imbalance, and hence, determine if the signal, 21,", is

‘61,,

greater than 1,69 If the signal exceeds the reference, the MSB will be a otherwise it will

be a “.”0 This completes the conversion for the MSB.

2.3 Fault-tolerant and Testable Circuit Design

During the last few years the theory and practice of testing electronic products have
changed considerably. The continuing revolution in electronic circuitry in terms of size and
speed has increased the problems of testing. The philosophy of testing has evolved from
merely measuring electrical parameters at many points in the device under test to
integrating testing in every step of the device design and development. A whole field of
testing has emerged. The following section presents a brief introduction to some important

testing concepts.

 

I

%

 

tr
I

it:

|—>
t9

 

Comparato
+
Amplifie

D.

—o Comparator
Output
(to latch)

 

35

 

 

 

(a)

 

MSB

previous bit = 1

previous bit = 0

 

Latch

[Reset

 

 

 

 

 

m
I—L___

 

__l_|

 

 

 

 

 

 

 

(b)

Figure 2.9 Current-mode A/D Converter: (a) Schematic Diagram: and

(b) Switching Sequence

33

2.3.1 Fault Tolerance

There are two fundamentally different approaches that can be taken to increase the
reliability of computing systems [36]. The first approach is called fault prevention (also
known as fault intolerance) and the second fault tolerance. In the traditional fault
prevention approach the objective is to increase the reliability by a priori elimination of
all faults. Since this is almost impossible to achieve in practice, the goal of fault
prevention is to reduce the probability of system failure to an acceptably low value. Fault
tolerance is an attribute that is designed into a system to achieve some design goal. A
design must meet many functional and performance goals, it must satisfy numerous other
requirements as well. The most prominent of the additional requirements are reliability,
availability, safety, performability, dependability, maintainability, and testability. Fault
tolerance is one system attribute capable of fulfilling such requirements. Fault tolerance is
not a replacement but rather a supplement to the most important principles of reliable
system design: (a) use the most reliable components; and (b) keep the system as simple as
possible, consistent with achieving the design objectives.

Three fundamental terms in fault-tolerant design are fault, error, and failure [20].
There is a cause-and-effect relationship between faults, errors, and failures. Specifically,
faults are the cause of error, and errors are the cause of failures. A fault is a physical
defect, imperfection, or flaw that occurs within some hardware or software component. An
error is the manifestation of a fault, and it is a deviation from accuracy or correctness.
Finally, if the error results in the system performing one of its functions incorrectly, a
system failure has occurred. Essentially, a failure or malfunction is the non-performance
of some action that is due or expected.

Fault duration specifies the length of time for which a fault is active. A permanent
fault remains in existence indefinitely if no corrective action is taken, while a temporary
fault occurs for short period of time. Temporary faults have been referred to as
“intermittent” or “transient” faults with the same meaning. Transient faults are non-

recurring temporary faults. Intermittent faults are recurring faults that reappear on a

34

regular basis. A major portion of digital system malfunctions are caused by temporary
faults. Such faults can occur due to loose connections, partially defective components or
poor designs.

In the fault tolerance approach, faults are expected to occur during computation.
but their effects are automatically counteracted by incorporating redundancy, i.e.
additional facilities, into a system, so that valid computation can continue even in the
presence of faults. They are redundant in the sense that they could be omitted from a fault
-free system without affecting its operation. Redundancy is achieved simply by the
addition of information, resources, or time beyond what is needed for normal system
operation [20]. The redundancy can take one of several forms: hardware redundancy.
software redundancy, information redundancy and time redundancy. Note that time
redundancy uses additional time to perform the functions of a system such that fault

detection and often fault tolerance can be achieved.

2.3.2 Testability Techniques

The testing of an integrated circuit is extremely vital to the ultimate goal of
achieving high reliability, availability, safety, maintainability, fault tolerance or other
design requirements [20]. Integrated systems, even when designed with highly reliable
components, do not operate forever without developing some faults. When a system
ultimately does develop a fault it has to be detected and located so that its effect can be
removed. Fault detection means the discovery of something erroneous in a system or
circuit. Fault location means the identification of the faults with components, functional
modules or subsystems, depending on the requirements. Fault diagnosis includes both
fault detection and fault location.

Fault detection in a logic circuit is carried out by applying a sequence of test inputs
and observing the resulting outputs. Therefore, the cost of testing includes the generation
of test sequences and their application. The test generation process includes fault

modeling, test pattern generation, fault simulation and fault coverage evaluation. The first

35

step consists of developing a fault dictionary for the circuit, i.e. modeling the faults that
. are assumed. Next, test vectors and/or test patterns are generated to test for the set of faults
being considered. One of the main objectives in testing is to minimize the length of the test
sequence. The test patterns are then simulated against the faulted circuit, and the fault
coverage is evaluated. If the fault coverage is inadequate, the process of test pattern
generation and fault simulation is repeated. To be practical and cost effective for large
scale integrated circuits, the test generation process should be automated. A test is a means
by which the existence and quality of certain attributes within a system are determined.
The testing process attempts to detemrine if the unit under test (UUT) works and if
it possesses its complete capability [20]. There are two key concepts in having a testable
design: controllability and observability. Controllability refers to the ability to apply test
patterns to the inputs of a sub-circuit via the primary inputs of the 'circuit. Observability
refers to the ability to observe the response of a sub-circuit via the primary outputs of the
circuit or at some other output point. In general, the easiest way to increase controllability/
Observability is to add some control gates and control terminals (controllability) or to add

some output terminals (Observability) for testing purposes.

EauILMmIQI

Fault modeling is very important in developing cost effective test strategies for
electronic circuits. In general the effect of a fault is represented by means of a model.
which represents the change the fault produces in circuit signals. The selection of adequate
fault models is crucial to achieving high quality testing because the efficiency of a test
scheme is limited by the accuracy of the chosen fault model. If the model fails to capture
the important characteristics of the actual fault, the test based on this model will fail to
detect the actual fault [36].

The fault models in use today are Stuck-at faults, Bridging faults and Stuck-open
faults. The most common model used for logical faults.is the “single-stuck-at fault”. It
assumes that a fault in a logic gate results in one of its inputs or the output being fixed to

either a logic 0 (Stuck-at-O) or a logic 1 (stuck-at-l). Stuck-at-O and stuck-at-l faults are

36

often abbreviated to s-a-O and s-a- 1, respectively. The stuck-at fault model, often referred
to as the “classical” fault model. offers good representation for the most common types of
failures, e. g. short-circuits (“shorts”) and open-circuits (“open”) in many technologies.

For circuits containing switching elements. the logical stuck-at model is
appropriate. effective and simple to work with. This model is based on the assumption that
the basic functionality of the circuit is not affected by the fault. This implies that the circuit
continues to behave as expected of it given the existence of the fault.

There exist various testing techniques that can be used to achieve this goal. In
general testing techniques use two major approaches: built-in test and external test [20].
External test techniques are typically performed with the UUT removed from its operating
environment and various tests applied to it using external equipment. Built-in test
techniques usually incorporate testing as part of the design of the device; thus no external

testing e®ipment is needed.

W

As digital circuits grow more complex and difficult to test, it becomes increasingly
attractive to build some self-testing ability into the circuits under test. Built-in test may be
conveniently used to detect and isolate a faulty component in a circuit and thus facilitate
its replacement. An important added feature of properly designed built-in test is the ability
to simplify off-line testing by taking advantage of the increased controllability and
observability made possible by the incorporation of the self-testing capability.

The built-in test strategy can be used to enhance testability .of VLSI chips. It is
based on the following principles: (1) Test patterns are generated on-chip; (2) Responses
to the test patterns are also evaluated on-chip; (3) External operations are required only to
initialize the built-in tests and to check the go/no-go tests results from a chip; and (4)
Additional pins and silicon area are kept to a minimum.

As the internal complexity of the integrated cirCuit chip increases, the idea of built-
in test becomes more and more attractive as it has many advantages: (1) Test patterns are

generated automatically inside chips; (2) Responses to test patterns need not be stored;

37

and (3) Use of expensive test equipment is not necessary. Built-in techniques can follow
either a conc‘urrent (on-line) or a nonconcurrent (off-line) approach. Nonconcurrent test
techniques require that the operation of the UUT be halted before beginning the test.
Concurrent test techniques allow a device to be tested while in normal operating mode.
The off-line test techniques suffer from the disadvantage of not being able to detect

temporary faults, which are likely to be more important in VLSI systems.

WWW) .
Although reliability of circuits may be improved by using sophisticated testing .
schemes to weed out faulty components, off-line or static tests cannot identify the transient
faults that occur during on-line operation. Therefore, a mechanism for concurrent error
detection must be installed to detect such faults before they cause undesirable results [22].
All CED schemes detect errors through conflicting results generated from operations on the
same operands. CED can be achieved through space or time redundancy, or space/time
. hybrid redundancy. Time redundancy employs only one single set of hardware to carry out
the repeated operations and can be effectively used in the detection and correction or errors ,
caused by temporary faults. Since the same hardware is used, the repeated operation, in the
presence of faults, is liable to produce the same erroneous result as that of the first step. To
avoid this problem, the operand must be coded in the repeated cycle, and the result thus
obtained must be decoded back to the appropriate form for meaningful comparison.
Consider a time redundancy technique shown in Figure 2.10 [21,22]. Let'x be the
input of the computation unit f, and let fp(x) and f(x) be the outputs with and without
encoding-decoding operations, respectively. Two fundamental requirements must be
satisfied in these operations. First, the coding function c must not interfere with the original
function f. In other words, for a selected coding function c, there must exist a decoding
function C'1 such that fp(x) = c'1(f(c(x))) = f(x) in the absence of faults. This is the concept
of mappable correct output [37]. Secondly, for the purpose of fault detection, the coding
operation c must transform the input operand(s) x in such a way that when subjected to the

same faulty conditions, the output in the repeated step, though still erroneous will be

38

 

 

. inputx _ f(x)
Trmeto f l—u Register .

Timer, inputx.( :) I» f . a

 

 

 

 

 

  

 

 

 

 

 

 

Figure 2.10 The Concept of Time Redundancy

39

different from the first step. This is the concept of disjoint error sets. Two simple time
redundancy techniques have been reported: RESO (REcomputing with Shifted Operands)
[21,37] and AL (Alternating Logic) [22,38]. Among existing CED techniques, both RESO
and AL have unique features of transient fault detection and require only a moderate
increase in hardware. AL implementation uses the complementation operator as the
encoding function while RESO uses the arithmetic shift.

The “alternating logic design” technique achieves its fault detection capability by
utilizing a redundancy in time based on the successive execution of a required function
and its self-dual [22]. A function for which the normal output is the complement of the
output, when complemented inputs are applied, is known as a self-dual function, e.g. a
function f(x), where x=(x1, x2, ...... , X“), is a self-dual if for all x, nil, i2, ...... ,_xn) = f(xl,
x2, ..... , xn). Thus, the principal characteristic of alternating logic is that it provides a true
output in one time period and the complementary output in the next time period. The main
disadvantage of the technique is that it requires twice as much time to obtain the verified

output.

Chapter 3

Current-mode Data-acquisition and
Data-conversion Circuits

 

All too often the electronics engineer will think in voltage terms rather than current
simply due to the unavailability of current-mode signal processing circuits, thus not taking
advantage of the many gains. of current-mode techniques [3]. The goal is thus to develop,
analyze and construct current-mode data-acquisition and conversion circuits in MOS
technology for signal processing and to explore the limits of their applications.

This chapter presents several current-mode circuits and their design and operation.
Section 3.1 describes the bipolar current copier, which is a fundamental building block for
several current-mode signal processing circuits. A data-acquisition system in the form of a
current-mode shift register is discussed in Section 3.2. In Section 3.3 a current-mode
divider is described that will form an integral part of a current-mode A/D converter as its
reference-generating unit. And, finally, Section 3.4 presents a successive-approximation

A/D converter that operates in the current domain.

3.1 Bipolar Current Copier

A simple NMOS current copier, consisting of three non-critical components: a
switch, an enhancement-mode NMOS transistor, and a capacitor, is generally used to copy
a positive current into its cell [39]. It has also been implemented to memorize the current

difference 13:11-12, where the current difference I3 must be positive, i.e., I] is greater than

40

41

[2. However, the copier cannot precisely memorize a negative current difference.
Moreover, the problem of memorizing negative currents can be resolved simply by either
switching the polarities of the current sources 11 and 12, or using a simple PMOS current
copier with a PMOS transistor. In instances when the polarity of the current may be either
positive or negative neither PMOS nor NMOS copier can be implemented. Thus, in
anticipation of a time varying bidirectional input current (can be either positive or
negative), as would be encountered in a general purpose multiplier or divider. a
bidirectional copier is necessary. This section presents a current copier which can precisely

memorize bipolar input currents.
3.1.1 Circuit Design and Operation

Figure 3.1(a) shows a bipolar current copier that employs a CMOS structure CMI
and one gate capacitance C, for both the NMOS and PMOS transistors. During the
copying, the switches SW, ST and SQ are turned on and the capacitor will charge up to the
gate voltage needed by both NMOS and PMOS transistors to achieve a current equal to the
input current lin=ldnl‘ldp19 where Id,“ and ’de are the drain currents of the NMOS and
PMOS transistors, respectively. If the polarity of the current I in is positive, then ’de < 1d,, 1’
otherwise ’de > Ian- Note that [dpl=ldnl if lin=0. After the copying, switches SW and SQ
are turned off to disconnect the cell from the input current source, and then the cell is ready
to source or sink current when connected to a load with ST turned on.

The bipolar copier suffers from the same limitations of switch charge feedthrough,
channel length modulation, noise and junction leakage similar to those of a simple copier.
The appropriate circuit techniques discussed earlier can also be applied to the bipolar copier
to reduce the error effects. For example, the effects of channel length modulation can be
'reduced by implementing an active copier with the addition of an opamp to fix the drain
Voltage as shown in Figure 3.1 (b). The opamp forces the drain voltages of both transistors
to a bias voltage so that they operate in the saturation region during copy. The correct

current can then be extracted by ensuring the same drain voltage at the time of retrieval.

42

 

 

VDD
CMl
P1 11.1
Idpl
S ST SW
HEAL/J
ildnr

 

 

(a)

 

 

 

 

(b)
Figure 3.1 Bipolar Current Copier: (a) Simple Copier; and (b) Active Copier

43

3.1.2 Analysis

The performance of the bipolar copier for a range of currents has to be analyzed.
For reliable operation of the copier it is necessary that the PMOS and NMOS transistors
either both be operating in the saturation region or at most one in cutoff. Thus, there is a
finite range over which the copier will perform accurately.

For dual power supplies of +VDD and -V55 for the PMOS and NMOS transistors
and a bias voltage, Vbias» of zero, one can obtain an approximate estimate of the input
current range available for the active bipolar copier. One end of the range is when the
NMOS transistor is operating in the saturation region while the PMOS is at pinch-off. The
drain voltage being at zero and the PMOS being in pinch-off implies that the gate voltage
is equal to its threshold voltage. Thus, the minimum negative current is the sum of the

saturation currents of the two transistors and is given by

I ,W 2 IW
I... = {M -,—)va0- (k figures-val] (3.1)

£21 ) are the device transconductance parameters of the PMOS and
n

NMOS transistors, respectively and V,” and V,p are their‘threshold voltages. The second

where (k'%) and (k’

term of (3.1) is zero when the NMOS transistor is in the cutoff region. Similarly, for the
PMOS and NMOS transistors operating in the saturation region and pinch-off, respectively,

the maximum positive current is determined by

W

l ,W 2 I
Imax = El:(k Z)nVSS— (k f)p(vm_ VDD_th) 2] (3.2)

and the second term vanishes when the PMOS transistor is in cutoff.

3.1.3 Experimental Results

In order to verify the performance and analysis of the bipolar copier design. both
simulations and experimental tests were carried out.

A prototype active bipolar copier, which is comprised of a CD4007 dual
complementary pair chip and a uA74l opamp, has been implemented where the dual power
supplies of i2.5V were employed [40]. The experimental results are plotted in Figure 3.2.
where the capacitance C1=46.035pF and the applied input currents range from —2.2mA and
+2.2mA. Both drain currents 1an and Idpl are measured by two ammeters. Since both
PMOS and NMOS transistors in the CD4007 chip have virtually the same device
transconductance parameters k = k' (%l ) the plot is nearly symmetrical. Results show that
ldp1=2.0mA and ldn1=0mA if Iin=-2.0mA; Idp1=1.l8mA and ldn1=0.08mA ifl,,,=- 1.10mA;
Idp1=ldn1=0.49mA if lin=0mA; Idp1=0.06mA and ldn1=l.15mA if lin=+1.09mA; and
ldp1=0mA and Idn1=2.0mA if lin=+2.0mA. The experimental results show that 1min: -
1.4350mA and [max=+l.4370mA, i.e., the prototype bipolar current copier can reliably
memorize the input currents within this range.

PSpice, a circuit simulator of the SPICE (Simulation Program with Integrated
Circuit Emphasis) family, was used to verify the bipolar copier operation. The simulations
assume the transistor parameters of the M0815 2pm CMOS technology, i.e., kln=56.06uA/
V2 and k'p=22.3ttA/V2, Vm=0.771327V, and V,p=-0.78821V. The simulations were
carried out to further verify the operation of the copier circuit. The switches were modeled
as ideal switches and were operated at a cycle time of lusec. In order to keep the symmetry
of the drain currents for both NMOS and PMOS, the aspect ratios of the NMOS and PMOS
transistors were chosen as 2pm/2um and Sunr/Zum, respectively. This implies that
(16%)" = 56.06u% and (16%)!) = 55.73%}. The power supplies were a V,» of 5
volts and VS S at ground. Note that PSpice represents the drain current in a MOSFET ml as
Id(ml). Also, PSpice shows the opposite polarity of current in the PMOSFETs. Thus, all
graphs and plots from PSpice have a negative sign for Id(mp), the drain current in the

PMOSFET mp.

 

45

 

 

 

 

 

 

 

2.5 v f . , , , fl A j
00
0°
2 " 00° -1
0°00
1 5 ' . . 0°00
. "' - 0° ‘1
'. I I on"
dpl dnl °°°°o°
id (mA) 1 — / \ coo -
o°°
. °o°°°
O 5 _ . _. -.cP°° 4
' 00090 I. ' ' .
00°° H
O mooowowcoow . . . .

M A“- . oooooooooooooooooo i
PMOS line NMOS saturation _, NMOS linear
NMOS CUIO PMOS saturation PMOS CUIOff

_05 1 r 1 L r r L 4 4
"2 -I .5 -l -0.5 0 0.5 I 1.5 2

Iin (mA)

Figure 3.2 Experimental Results of a Bipolar Current Copier

 

46

NMOS current copier copying negative current

 

 

 

 

 

 

 

 

 

 

0A
.OuA 4
.OuA~
OUA1 (1003011,-60307711)
OUA I T T T
Os 0.5us l.Ous l.5us 2.0us 2.5us
OIDUTIII) .
Time
PMOS current copier copying positive current
.OuA
.OuA~
(l.OOOOu,4.9622u)
//
.OuA~
.OuA4
0A r . . . .
Os 0.5us 1.0us 1.5us 2.0us 2.5us
uID(mp) Time

Figure 3.3 Unidirectional Limitation of NMOS and PMOS Copiers

47

Figure 3.3 illustrates that an NMOS copier cannot copy negative current while a
PMOS copier cannot copy positive ones. When a negative current of ~50uA is copied into
an NMOS copier the NMOS device is forced to copy -6.3109|.LA as it cannot source current.
Similarly as the PMOSFET in a PMOS copier cannot sink current, a positive current of
SOuA is copied as 4.9679uA. However, the bipolar current copier is capable of copying
both positive and negative polarity currents as seen in the simulations of Figure 3.4. For
Ii": 50.039uA, the current copied to the NMOS was Id(mnl) = 98.606uA and to the
PMOS, Id(mpl) =-48.553uA. The positive input current then read outto a PMOS copier as
load was equal to 49.900i1A thus having a percentage error of 0.277%. On the other hand.
a negative input current of [in = -50.023|.rA resulted in Id(mpl) =-98.198uA and Id(mnl)
= 48.155uA. This current on retrieval to an NMOS copier, as illustrated in Figure 3.4,
produced an error of 0.527%.

It should be mentioned that, based on the PSpice parameters and (3.1) and (3.2), the
range that can be accurately obtained from this copier results in 1min: -0.298mA and
ImaX=0.3mA. In practice. the range of the input currents can be improved by increasing the
aspect ratios (W/L)n and (W/L)p but at the cost of larger chip area. In order to study the
effects of channel length modulation, the functioning of the active copier of Figure 3.1(a),
was also simulated, where a two-stage CMOS opamp and a Vbias of 2.5 volts were
employed. Figure 3.5 illustrates the performance of this active copier. The percentage error
in copying +50ttA was 0.091% and the accuracy for -50uA was 0.039%. The results show

that the active copiers significantly reduce the effects caused by channel length modulation.
3.2 Current-mode Shift Register

A current-mode shift register can sample the data in parallel and then serially read
it out to be converted by either a high-speed current-mode A/D converter, or an array of
medium-speed converters [41]. Thus, the shift registers can be used where the data is

transmitted serially over a single pair of wires, instead of as parallel bits over many wires.

48

Iin : +50.039uA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

lZOuAe
98.606u
¢/ ¢ :E~¥ 4 c
I
80uA4 A
50.039u o
A / .-.
40uA~ '
it
0
0A ‘5 3 3 5
l
_ -48.553u r —49.900u
4 OUA'i { ; rk ‘ fi/ A v A
4)
Os 0 Sue l.0us 1 Bus 2.0us
oI(IinJ oID(mnl) oID(mp1) vID(mpout)
Time
Iin = -50.023uA
lOOuA
ti
48.155u 49.759u
SOuA« ..// .. " - {’- - -
0
C
OuA e =1 e e
-S0.023u H
-SOuA e = ,/ 1
I
-98.198u ,
.. lOOuA /; Afi 0 .‘r
./'/i
ll
~150uA .
l O s = l.Sus 2.0us

0? , ofSus . u
oI Iin) .ID(mnl) eID(mpl) vID(mnout)

Time

Figure 3.4 PSpice Simulation of a Bipolar Current Copier

49

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3.5 PSpice Simulation of a Bipolar Active Copier

Iin : 50.037uA
lZOuA
98.642u
is // g i or
8OuA4
50.037u 0
4; / 3 —
40uA«
I
0A : e d :fi = a
0
—48.604u -49.99lu
—40uA~
W 1/ ; J L 7/ - l
0
-80uA . .
Os _ . us l.0us 1.5us 2.0us
oI(Iin) oID(mnl) AID(mpl) vID(mpout)
Time
Iin : - 50.039UA
lOOuA
47.440u 50 Ol9u
50uA« I: g; e e
0A t 1* 3
. -50.039u
—50uA4 —~ 1/ -
l
-97.505u
—lOOuA« ’/ : e - =
A
—150uA r7 . .
Os . 0.5us l.0us 1.5us 2.0us
aI(Iin)°ID(mnl) «Io(mp1) 'ID(mnout) '
Time

50

In this section, current-mode shift register structures for sampling and holding current data

are discussed.
3.2.1 Operation Principle

Figure 3.6 shows a shift register using simple current copiers, where four sampling
nodes, mi, i= 1 to 4, are assumed from the sensors and a 4-stage current-mode shift register
is considered. Each current copier is defined as a Current Storage Cell, C SC#i . The timing
diagram, as shown in Figure 3.7, shows the switching sequence of the current-mode shift
register for its operation which proceeds in two stages: load and shift.

Figure 3.8 illustrates a part of the load/shift operation. First, the switches SWi, ST,,
and SQ, are all turned ON, as shown in Figure 3.8 (a), loading data into the current storage
cells. Once the data is held in the CSC#i, the switches SW3, ST,, and SQ, are turned off.
This cycle is referred to as the load pracess. The shift process proceeds in a last stage first
out fashion. More specifically, the datum held in the last stage (or the fourth stage in Figure
3.6) is first shifted out by turning on the switches SP4 and 8T4, where the switches ST].
8T2, and ST3 remain OFF, as shown in Figure 3.8(b); thereafter, the load will source a
current 14 which is the same as the stored current in CSC#4. This is followed by switching
on SP3, and ST3 and turning off 8T4, as shown in Figure 3.8(c), and the load will copy a
current 13 that is stored in CSC#3. Thesubsequent data are processed in a similar manner
and the operation is carried out continually until the current held ,in CSC#I' is finally
processed. It should be noted that switches ST, help disconnect those storage cells which
are not being processed. For instance, when data held in CSC#3 is being processed, the load
may source current to both CSC#3 and CSC#4 in the absence of ST4 and copy an incorrect
datum. The accuracy of the current-mode shift register suffers due to the same non-ideal
effects that limit the performance of the basic current copier. For example, during readout
the drain voltage varies due to the load, a PMOS copier, and the channel length modulation
parameter causes an original-to-copy error. This limitation can be overcome with the use of

active current copiers as illustrated in the alternative structure in Figure 3.9.

 

  

 

SP3

Vss

"""""""""

 

.Scf/

ST3

 

m3

 

51

’0', 'O'I'DOUD' '

 

Sensors
SP2
SQs

sr2

 

m2

/

 

f""""""
‘4

 

SP1
srl
302

m1

 

 

"""""""""

FFFFFFFFFFFFFFFFFF

I
'oooooooooooooooo

v
0

'0000'0000000'00

 

I

O'COOO'O'OOODO"

 

 

It

O'OOO'OOOODOOOO

r
'0

I.

 

 

Shifting

 

 

CSC#4

 

 

 

Lmflmg

 

 

 

CSC#3

 

 

 

SMfimg

 

 

 

CSC#Z

 

 

memg

 

 

 

__J
_J

CSC#I
sw,
SP4
s11.
ST3
SP2

Figure 3.6 Current-mode Shift Register Using Simple Current Copiers
5T2
SP1

on

 

 

 

__l

 

 

I_I
j—l.

 

 

 

' __r
-—‘—.—'

Figure 3.7 Switching Sequence for Load/Shift Operation

sr,
so,

 

 
  

 

 
 
 
 

52

   

 

 

 

 

 

   

 

   

 

 

 

 

 

 

v
m1 m2 m3 m4 DD
9 O O 0
iii, iir. iii, iii, W“
sw, sw2 sw3 sw,
.__/ __..__/ _.._/ __.._/
SPl SP2 SP3 SP4
srI srI ‘ sr3 sr4
SQr 302 303
. l i l l
l I 0
5 M1: : 2: r i : M4:
: r : : : : : :
a I a I c I p a
a I o 0 I I o C :
‘T ‘ ‘1' ‘ ‘T ‘ ‘T ‘ =
5 1 L 1 1 -1 1 -‘ VSS
CSC# l CSC#Z CSC#3 CSC#4
' (a) v
m, m4 oo
jg)”; yj:8%}:3:13 [‘ Load
sw,
sr4
8"?st Q3 l
I I
a a M. 5 Mr 2 r
I I ' I 0 a I
I a l I I a 0
g : i 1 C3 5 l 3
; ETC 2 5T i E i vSS
CSC# l C SC#2 CSC#3 CSC#4
(b)
m3
SP: WJS‘W‘S P4
/s ; sr3 sr4
1 SQ‘
:r o r! I
i W: E M: 5 /M3; 5 M4;
t :1 1 g g a. E 3
I r' o r I
: cl :5 : c2 if t c, g; t c, :
gt [331' if ;T 2' 3T v55

 

CSC#I

Figure 3.8 Operation Sequence during Load/Shift: (a) Parallel Loading;

 

CSC#Z

 

CSC#3

(C)

and (b) & (c) Serial Shifting

CSC#4

 

 

 

 

 

 

 

 

Figure 3.9 A Current-mode Shift Register Using Active Current Copiers

54

3.2.2 Design Considerations

The current-mode shift register being a set of sample-and-hold elements suffers
from problems faced by many data-acquisition systems. The various practical issues that
must be investigated are (1) determination of the acceptable change and the effect of the
change in the gate voltage held in the capacitor during the read-out stage; (2) the
relationship between the clock rate and the highest allowed signal frequency; and (3)
accumulation of errors due to charge injection from the series switches.

The acceptable change in the sampled voltages during the shifting process is limited
due to charge leakage from the holding capacitor through the switch wherein there is a
constant drift of the gate voltage. The effect of the leakage current is given by

CA}: (3.3)

I leakage = A t
where C is the net capacitance of the holding capacitor and the gate to source capacitance
of the MOS transistor. The effect of the change in the gate voltage brings about a relative

change in the copier current given by

 

(3.4)

where gm is the transconductance and 10 is the drain current.

The accuracy of the gate voltage can be improved by either increasing the
capacitance or decreasing the leakage current Though holding accuracy can be improved
by capacitors of larger size, this is at the cost of acquisition time. A better methodology
would be to carefully allocate the test points so that smaller voltage values sampled at the
register cell are closer to the output terminal while larger values that can be held longer are
further down. Thus, given a percentage accuracy or allowable original-to-copy error, (3.3)

and (3.4) can be used to attain the acceptable change in gate voltage.

 

55

In general, the maximum sample rate of the BIST structure is determined by the
time intervals spent in the sample and hold mode. The minimum time in the sample mode
is established by the sample-and-hold acquisition time, i.e., the time for which the SW,
switches are on. The time interval in the hold mode is determined by the sequence in which
the data stored in register cells is read out. According to the structure, the further the register
cell is from the output terminal, the longer the holding time. Wide BIST structures are thus
not encouraged, and, if more test points are to be sampled, more output terminals may be

used.

3.2.3 Simulation Results

The operation of a four-stage current-mode shift register has been verified using
PSpice where the transistor parameters of the M0818 2pm CMOS technology and ideal
switches were assumed. During the load cycle, the currents loaded into the current storage
cells were such that 1d(m4)=100|.tA, Id(m3)=50.002uA,Id(m2)=25.0lOuA and Id(ml)=
125.048ttA as seen in Figure 3.10(a). During the first shift at the time step of Susec, the
PMOS copier load reads out 99.83luA from CSC#4 with an error of 0.169%, and the
second shift yields an output current of 50.088uA at -4.l71% error. The shift Operation
proceeds as seen in the plot with the data in CSC#2, 27.455uA and CSC#l, 122.148uA
shifting out during the third and fourth cycle at -9.776%-and 2.319% errors, respectively.

As seen from Figure 3.10 (b) the circuit performance when the varied currents of
125uA, 25uA, SOuA and lOOuA are sampled into the shift register is not adequate. The
read-out to a PMOS copier load causes changes in the drain voltage during every cycle of
the shift stage giving rise to considerable errors. For a similar sampling operation the shift
register with active copiers provides a more accurate output, as shown in Figure 3.11, since
the opamp fixes the drain. lOOuA is read out as 99.908uA with 0.092% error while 50ttA
is obtained within -0.129% error. 2511A and 125itA can be shifted out with percentage
accuracy of 0.006% and 0.012%, respectively. The improved current-mode shift registers

provide more accurate data than those using the simple copier, but they require more chip

56

Load Operation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

lSOUA 100.000u
//
0A
a IDIITI4)
lSOuA
50.002u
//
0A 1
a ID(m3)
,lSOuA
25.010u
//
CA I I
a ID(m2)
lSOuA
\\
125.048u
0A . .
3 Bus lOus lSus 20us 25us
a ID<mlI .
Time
(a)
Shift operation
lSOuA -
122.148u
F, /
99.83lu
lOOuA- /
i 52.088u
530qu /
27.455u
L /
0A +7 -
Sus lOus lbus 20us 25us
o- ID(mpout) .
Time
(b)

Figure 3.10 Simulation of the Current-mode Shift Register: (a) Varied
Inputs; and (b) Output of the PMOS Copier Load

57‘

Current—mode Shift register with active current copiers

 

 

 

 

 

 

 

 

 

 

 

 

125.063u
//
99.908u
lOOuA« //
50.067u
SOuAe L //
25.026u
/
0A . .
Os Sus lOus lSus 20us 25us
o— ID(mpout) .
Time

Figure 3.11 Simulation of the Shift Register with Active Copiers

 

58

area to implement them. The improved structure may be used in cases where the original
and copied currents must be matched precisely.

Other error effects that have to be analyzed are those of the sample-and-hold
procedure. According to (3.3) and (3.4), the performance of the copier deteriorates due to
the drop in holding voltage and, as observed in Figure 3.6, the further the register cell is
from the output terminal, the longer the holding time and thereby the greatest error.
Consider the case when an input of 125.057pA is copied into all the four cells. The read-
out current from each stage is plotted in Figure 3.12. The error in current read out from the
last stage, CSC#I. due to junction leakage can be seen from Figure 3.12 where the leakage
current in the holding capacitor C1, I(c1), is approximately -30.483nA. Thus, for a gate
capacitance of 40pF and a hold time of 15 usec, i.e. from the instant the switches are shut
off after load to the time the data in the cell are shifted out, the change in voltage from (3.3)
is approximately -11.43mV and a value of -l 1.35mV is read off the plot. A few methods
by which the holding accuracy can be improved are by capacitors of larger size or by
employing faster clock rates. Figure 3.13 shows simulations in which both these
alternatives were tried out to verify these design options. With the same leakage current and
hold time as before and a hold capacitance two times larger of 80pF, an error of 6.1mV was
obtained while the theoretical prediction from (3.3) was 5.715mV. Thus, the accuracy was
improved, but at the cost of acquisition time, as seen in the plot. With the hold capacitance
of 40pF, data was acquired in 2.075ttsec, while double the capacitance took almost twice
as long, i.e., 3.95usec.

Figure 3.13 shows simulations run at a faster sampling rate of 1 MHz. Sampling
faster implies that the capacitor discharges for a shorter time and so the accuracy does not
deteriorate too much. With At of only 3|.tsec, (3.3) predicts a fifth of the previous error, and

the plot indicates an error of only 2.4mV.

59

Read-out currents of the four stages

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

lSOuA
122.624u 122.238u 121.957u 121.60lu
FT’ 115 j/ 1/ //
lOOuAl
Iin = 125.057uA
SOuA«
0A . . .
3 Bus lOus lSus 20us 25us
o— ID(mpout) .
Time
The leakage effects on the last stage (CSC#l)
lSOuA
\\
(5.0000u,125.057u) (20.000u,121.4l7u)
0A
a ID(ml)
400uA
\\‘ -30.483n
/
r
-400uA
a I (Cl)
3.1V
<5~0990ut3-0525> (20.000u,3.04lO)
3.0V ( I" I T; T
Os Sus lOus lSus 20us 25us
DVICl) .
Time

Figure 3.12 Error Effects of the Sample-and-hold Procedure

 

Larger hold capacitors

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

l30uA
(5.0000u,125.056u) 8
125uA- /’
(20.000u,i22.019u)
t) ; f
120uA. . (20.000u, 1.584u)
ti
llSuA
a oID(ml)
3.lOV
(5.0000u,3.0525)
3.05V~ 1:: :T_‘_~_‘_i‘_~__:20;000u;3.0464)
1/’////7 (20.000u,3.04l01
3.00V . . . .
Os Sus lOus lSus 20us 25us
a °V(Cl) .
Time
Higher sampling rate of lMHz
lSOuA
(l.0000u,125.057u) (4.0000u,122.324u)
0A
aID(ml)
lOnA
-30.507n
/
-40nA
aI(Cl)
3.1V
1.0000 ,3.0525
( r, u ) (4.ooogp,3.0501>
3.0V . . '. .
s l.0us 2.0us 3.0us 4.0us 5.0us
oV(cl) .
Time

Figure 3.13 Improvements to the Acquisition Procedure

 

61

3.3 Current-mode Divider Circuit

Current division has traditionally been carried out using resistive networks or
weighted transistors. However the precision of such schemes are limited by device
mismatch. The highly accurate current divider in Section 2.2. overcomes this limitation by
using dynamic techniques. and the system converges to give an accurately divided current
[35]. Note that an NMOS current copier is generally used to store the positive input
currents. Results have shown that the copier cannot precisely memorize any negative input
currents. Since the NMOS transistor N, is used to hold the current difference between [2
and 13 in the circuit of Figure 2.8, where 11:13-12, the current difference must be positive,
i.e.. [3 must be greater than or equal to [2.

When the mismatch factor or is such that 0 < or < 0.5, then the system response is.
overdamped and all copier currents are unidirectional [1]. But if or is in the range such that
0.5 < or < 1, then the system will become underdamped, and some currents may change
sign while the system is converging. In this case the roles of N3 and N2 would have to be
reversed, which is possible only if switch programming can be implemented. In practice,
the mismatch of transistors is unknown in advance and thus the divider circuit functions
properly only when the mismatch between the transistors N3 and N2 makes ldn3 > ldnz.
Another solution to the problem which would be less complex is the use of a bidirectional
copier. Therefore, an alternative current-mode divide-by-two circuit which allows any
mismatch in N3 and N2, utilizing a bipolar copier is discussed in this section. This circuit
can then be used if I,n is allowed to be bidirectional thus becoming an important general

purpose analog current-mode divider.

3.3.1 Method of Operation

Figure 3.14 illustrates the schematic diagram of the alternative current-mode
divide-by-two circuit. The divider operation and its switching sequence are exactly the

same as those described in Figure 2.8 and are illustrated in Figure 3.15. However, the

 

62

 

 

 

>r
Ampltfie

 

 

 

 

Figure 3.14 The Alternative Current-mode Divider

 

Clock Copying Sequence

 

Iin —) N2& N3
N3-9 P4

P4- N2 -)N1
Iin-CM] -9N2& N3
N3-) P4

P4- N2 -)N1
[in—CMI —)N2& N3

 

 

 

\IONUI-BOJNv-r

 

Figure 3.15 Operational Sequence of Divider

 

63

NMOS current copier with N, used to store the current difference in Figure 2.8 is replaced
by a bipolar CMOS copier CM, [42]. Since the bipolar copier can memorize both positive
and negative input currents, where the memorized current = ldn,-Idp,, this divider circuit
will function properly for any mismatch between N2 and N3. With the mismatch factor a2
greater than (13, less current is copied to N3. Thus, ldn3 < Idnz and the bipolar copier stores _
the negative current difference (ldn3-ldn2), where ldp, > ldn,. On the other hand, a2 < (13
implies the positive current difference (ldn3-Idn2) of the division is stored in the bipolar
copier structure, with Idp,< ldn,. The error due to channel length modulation can be
reduced by the use of an opamp to fix the drain to source voltage. The gate capacitors, C, ,
are used to reduce the effects of the charge injection from switches and to allow the
transistor and capacitor geometries to be determined independently. The circuit accurately
divides the input current I,n by two, irrespective of the mismatch between the two
transistors, and stores the result in N3. Note that the divider circuit does not rely on any

well-matched components or a high gain opamp.
3.3.2 Performance Estimation

The structure of the divider indicates that current division can be carried out
effectively. However, the number of iterations necessary to obtain l,,,/2 with a certain
accuracy depends on the mismatch of the transistors N2 and N3 in the divide—by-two circuit.
The performance and accuracy of the divider considering its dependence on several
parameters is analyzed. Let y be defined as the mismatch ratio of the transistors N2 and N3,
where y=(0t3/ov2)-l. Therefore, 7 is positive if the mismatch factor (13 is greater than (12.
otherwise 7 is negative.The relationship between the number of iterations required for the
division process and the desired accuracy for a given mismatch has now to be addressed.

According to the current copying sequence listed in Figure 3.15, at the end of the
first cycle of the first iteration, N2 copies [2 = 01/21,", and N3 obtains the current 13 = (131,".

Thus, the currents copied to these transistors in terms of y are

 

1 _ 1+Y
—2+Y) and I3 — l- (-—) (3.5)

[2:11'n( m 2+7

The current difference, 13-12, held in CM, at the end of the third cycle is approximately

7

As a result, at the end of the first cycle of the second iteration, I,n - I, is now sourced and

so the current held in N3 becomes

Y 1+)!

2+Y)(2+Y) ’ (3.7)

 

1+7
13 =(ltn’11)(f2_+—Y)‘= 1in(1_

Similarly, at the end of the first cycle of the kth iteration, the current held in N3 can be

expressedas
2 k-l
_ .._7_ L _ _ k-1_Y_ +7
I3—lin|:l 2+7+(2+y) ...+(1) (2+7) ](2—Y+Y) (3.8)

Let [3,, denote the current held in N3 at the end of the first cycle of the kth iteration.
Y

The term in brackets rs a geometric progression, and since 1 +— 2——— + Y: 2(— :7) (3. 8) can
now be re-written as
1 —I—”3 1+(-1)"‘1 (— k (39)
3" — 2 2? + y ' '

For a reasonably uniform technology, the mismatch ratio 7 generally lies between 0

It
and 50%. The error term (2—Iy) diminishes rapidly as k increases, i.e., [3,, == l,,,/2.
Therefore, the error term can be used to determine the number of iterations necessary to

obtain [,n/2 with certain accuracy [43]. Table 3.1 illustrates the relationship among the

 

65

Table 3.1 Relationship among 7, k and the Corresponding Error Terms

 

 

 

 

 

 

 

4.03e-07

 

 

L

 

k y=20% y=10% y=5% y=2% y=l%
l 9.09e-02 4.76e-02 2.44e-02 9.90e-03 4.97e-03
2 8.26e-03 2.26e-03 5.95e-04 9.80e-05 2.47e-05
3 7.51e-04 l.07e-04 1.45e-05 9.70e-07 1.23e-07
4 6.83e-05 5.14e-06 3.53e-07 9.60e-09 6.12e-10
5 6.21e-06 2.45e-07 8.63e-09 9.51e-1 1 3.04e- 12

k y =-20% y =-10% y =-5% y =-2% y =-1%

l 1.1 le-Ol 5.26e-02 2.56e-02 1.0 1e-02 5.02e-03

2 1.23e-02 2.77e-03 6.57 e-04 l.02e-04 2.52e-05
3 1.37e-03 1.45e-04 1.68e-05 l.03e-06 1.26e-07
4 1.52e—04 7 .67 e-06 4.32e-07 l.04e-08 6. 37 e- 10
5 1.69e-05 1.1 1e-08 1.05e-10 3.20e- 12

 

 

 

66

mismatch ratio, 7, and the iteration index, k, and tabulates the corresponding error terms.
Results show that the divider circuit can achieve an accuracy within 6.21e-06 by taking 5
iterations for y=20%. On the other hand, for a practical 1% transistor mismatching, the
circuit takes only 2 iterations to achieve an accuracy within 2,47e-05 and 5 iterations for an

accuracy within 3.04e-12.
3.3.3 Experimental Verification

PSpice simulations were run to test the operation of the divider assuming
parameters of the M0818 2pm CMOS technology. The aspect ratios of the NMOS and
PMOS transistors were chosen as 2|.rm/2um and Sum/2|.tm, respectively. This preserved
the symmetry of the drain currents in the bipolar copier and kept a minimal area for the
divider structure. The circuit had VDD at 5 Volts, V35 at ground and a Vbias of 2.5 Volts
was picked to keep the devices in saturation. The ideal switches were operated at a cycle
time of 3usec. Figure 3.16 shows one iteration of the division process for an input current
of approximately lOOuA through switch SO, I(sw0), with no mismatch between transistors
N2 and N3. The current difference between ldn3 and Mn is very low and the divider settles
down in one iteration within a duration of 9usec. The value of the divided current in N3 is
equal to 50.018uA, and thus an error of only 0.045% exists.

The operation of the divider for several mismatch ratios between the transistors is
then tested. This was established by considering all the mismatch between the two copiers
to be in the aspect ratios of the transistors N2 and N3. For example, for a y of 5%, (W/L)3
was equal to 2.1ttm/2um while (W/L)2 was Zuni/2pm. Figure 3.17 shows the currents as
the iterations of the divider are carried out when a mismatch factor 7 of 5% exists between
Nziand N3. The current in N3 is initially at 51.263uA, thus starting the division process with
an error of -2.535%. The bipolar copier stores the positive error difference between N2 and
N3 of 2.425ttA and sources it for the next cycle. After two iterations, the current in N3
settles to 50.041uA with only —0.09 l % error. For 7': —5%, ldn3 is a lower value of 48.755uA

with the initial error of 2.487%. The negative current difference of -2.5828uA stored in

 

67

Current-mode Divider

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

lSOuA
99.99lu ,
1 s/ ‘ e
50.008u 50.016dt 50.018u
E/- ,/ u .. ,/ -
D. v t" f - v _
0A . : c m .—
oI(st) oID(m2) .ID1m3)
75uA
49.9l6u 49.895u
/ f /
OA 1
a- ID(m4)
lOuA
-25.062n -47.754n
! V 1 ff
—lOuA . .. .7 .
Os 2us 4us 6us 8us lOus 12us
oID(mnl)+ ID(mpl) ,
Time

Figure 3.16 PSpice Simulations of the Current-mode Divider

 

 

68

(W/L)3 > (W/L)2: 5% mismatch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

lSOuA ,
99.99lu 0 v 4
. 4 :
51.263u ‘1 50.0: 2u 50.0.4111
,N—é - .¢ w - / i v/ ;
, 0
0A 48.72/31} 0 :r a a 4.. c :
oI(sw0)oID(m2)aID(m3)
75uA
51.150u 19.916u
- r / /
1
0A 1
a- ID(m4)
lOuA
I 2.4248u 2.3883u
. xi; . /G
P l L______ l
-lOuA . . . . .
Os 4us 8 s 12us l6us 20us 24us
oID(mnl)+ ID(mpfl _
Time
(W/L)2 > (W/L)3: 5% mismatch
lSOuA ,
99.997u t p f
; ' II
1 51.436611 50.0},031 ‘ 50.03/63,
, _ -
48. "5 u t) 0
0A : : e 0: : e :
oI(st).ID(m2) .ID(m3)
75uA
48.643u I 49.894u
. j /
CA I
a- ID(m4)
lOuA
l l +_____
A' ‘\ A ‘\
-2.5828u -2.6317u
-lOuA . . . . . .
Os 4us 8us 12us l6us 20us 24us
oID(mnl)+ ID(mpl) ,
Time

Figure 3.17 Divider Operation with 5% Mismatch

 

69

CM, is sourced in subsequent iterations to make the divided current be 50.036uA. Thus.
the resultant error is only -0.075%.

The relationship between accuracy of the divided current and the number of
iterations has been theoretically derived and is then to be verified through simulations.
Figure 3.18 shows how with a mismatch 7 =10% more iterations are necessary to get a
required accuracy. The error begins with the value of 4.925% and reduces to 0.121%.
0.097% and 0.087% at the start of the second, third and fourth iterations, respectively. The
current in N3 varies at every iteration as CM, holds more of the error current to allow N3
to obtain a more accurate value. For 7 =—10%, the error starts at 4.881% and settles, at the
beginning of the fourth iteration to -0.077% . To study the convergence of the error several
simulations were run on the divider for an input current of approximately lOOuA for
various mismatch ratios. The results of these runs are tabulated in Table 3.2 in the same
fashion as Table 3.1. As seen in the graph of Figure 3.19, the error converges to a finite
value of approximately 0.0026, unlike the theoretical prediction of close to zero error, and
the error term remains at this value for subsequent iterations. This finite error even when
there is a mismatch of zero is due to the limitations in the performance of the active copiers
and the functioning of the switches. A comparison run between the error for 20% mismatch
and its theoretical prediction is plotted in Figure 3.20, and the finite difference in their

converged values can be clearly observed.
3.4 Successive-approximation A/D Converter

The continuous progress of VLSI technology has provided the possibility of
integrating a large sensor array and parallel digital processors on a single chip. The
requirement on speed of the A/D converter array is not necessarily very high. However, the
reduction of the size and power consumption is more important. Cyclic (algorithmic) and
successive-approximation current-mode A/D converters convert an input current to an N-
bit digital data word D using a multiply-by-two scheme and a divide-by-two scheme.

respectively. The former scheme converts for the MSB of an input current by comparing

 

70

(W/L)3 > (W/L)2: 10% mismatch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

lOOuA
52-é6lu 49.938u) 50.047u) 50.042u
5011A < 11—4 - [I t. /' _ /
0A
0 ID (m3)
lOuA
4.8065U 4.6007u 4.6102u
. AVA Z A'_ / Av. z
—25.040n I I
DA / '
-iOuA . . . . .
s §us lOus lSus 20us 25us 30us
oID(mnl + ID(mpl) .
Time
(W/L)2 > (W/L)3: - 10% mismatch
lOOuA \
47.558u 49 927u 50 032u 50.037u
1’ /’

50uA~\, .4 . r /

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A
uID(m3)
lOuA
0A -
l ,-4;9767u -5. 973u -S.2084u
I ' " "
—lOuA . . _ , ,i
0 us lOus laus ‘ 20us 25us 30us

s
oID(mnl + ID(mpl) .
Time

Figure 3.18 Divider Operation with 10% Mismatch

 

71

Table 3.2 Error Terms Obtained from Simulations

 

 

 

 

 

k y=20% y=10% y=5% y=2% y=l%
l 9.37e-02 4.93e-02 2.54e-02 1.04e-02 5.39e-03
2 4.47e-03 1.68e-03 2.32e-03 2.66e-03 2.72e-03
3 4.47e-03 3.51e-03 2.68e-03 2.36e-03 2.44e-03
4 3.95e-03 3.43e-03 2.69e-03 2.44e-03 2.42e-03
5 3.51e-03 3.33e-03 2.79e-03 2.48e-03 2.38e-03

k y =-20% y =-10% y =-5% y =-2% y =- 1%
1 9.32e-02 4.87e-02 2.49e-02 9.96e-03 4.91e-03
2 6.29e-03 7 .99e-05 1.74e-03 2.42e-03 2.59e-03
3 1.66e-03 2.06e-03 2.29e-03 2.32e-03 2. 12e-03
4 2.04e-03 2.29e-03 2.04e-03 2.34e-03 2.42e-03
5 2.14e-03 2.18e-O3 2.19e-03 2. 18e-03 2.28e-03

 

 

 

 

 

 

 

 

Error

Error

72

Simulation results

 

0 .0045

. r r r r r
20% mismatch +—
1113. mismatch —+—
5%. misrnafu‘li G—
. ".14 ..‘9, mismatch -x— "
1’1 mismatch £—
1" misnoat-‘l‘. *—
II (3‘71“? _4
I-
t
0.003 _,

 

 

 

 

 

 

(
l

l
17

 

 

 

 

 

 

 

0 330,5 1 , l l l l l I

3 3.5 3 3.5 4 4.5 5 5.9 e
Number of Iterations
Figure 3.19 Experimental Error Terms
Absolute Error at 20% mismatch
O "L I I 7 T I I I
Theoretical Error 4—

0 Experimental Error -+— q
0. q
0 . .1
O . q
0 _,
0 . i
o. 3
0 . .4
0 . T

1 7; 1
3.5 4 4.5 s

 

Number of Iterations

Figure 3.20 Comparison of Error Terms

 

73

twice the input current to the reference current, while the latter scheme compares the input
current to half the reference current.

The multiplier approach requires simpler cells, but errors are progressively
accumulated from cell to cell, and the largest current (MSB) has the worst relative
precision [29]. A more severe limitation is due to noise. The accumulation of noise
culminates at the MSB and can by no means be compensated. Consequently, the first cells
of the multiplying cascade generate large values of noise and error, which are propagated
to the MSB current. These limitations can be avoided by using the dividing scheme, which
confines the larger error and noise to the least significant bits. This advantage is probably
worth the increased complexity of the cells.

Since the reference current in the divide-by-two scheme is reduced constantly by
half during each bit conversion, the division can be done in parallel with the bit conversion
process. In the multiply-by-two scheme, however, the multiplication cannot be performed
until the end of each bit conversion. Thus, A/D converters implemented with the divide-by-
two scheme achieve higher conversion rates than those with the multiply-by-two scheme.

This section describes the conversion principle of a successive-approximation
current-mode A/D converter implemented with the divide-by-two scheme and its detailed
design and operation. The converter is comprised of a reference-generating (RG) circuit
and a converting (CV) circuit as seen in Figure 3.21. The RC circuit generates the reference
levels 1/2, 1/4, 1/8,..., 1/2N of the reference current, while the CV circuit along with a
comparator determines the converted digital bit value and the current to be converted for
the next bit.

This section also describes a converter array which employs a common RG circuit
that is shared by many CV circuits that process many input signals simultaneously. Due to
the small number of components needed and simplicity of the current-mode circuit
realization, the converter array is well suited for sensor array implementation. Results of
this study will show that the converter array achieves high resolution and high conversion

rate at low hardware cost

 

¢lref

 

Reference-
generating
(RG) Circuits

 

74

Analog
Current
Input

 

__~

 

 

 

Converting
(CV) Circuit

 

 

 

 

 

Control
Logic

 

 

Latch

Serial
Out

 

 

 

 

<

 

 

 

 

Figure 3.21 Block Diagram of a Current-mode Successive-approximation
A/D Converter

 

75.

3.4.1 Circuit Description

The successive-approximation current-mode A/D converter implemented with the
divide-by-two scheme converts an input current [in to an N-bit digital data word D, where
D = (dldz..dN) and d1 and dN are the most significant bit (MSB) and the least significant bit
(LSB), respectively. The converter starts converting for the MSB by comparing the input
current [in to the reference current [ref/2. If [in exceeds [ref/2, the MSB will be a "l", i.e..
d1=l, otherwise it will be a "0". The current to be converted for the bit d2 depends on the
preceding bit value. If d1=0, then the current remains unchanged, otherwise it equals the
current difference (lin‘ ref/2). Bit d2 is determined by comparing this current to the
reference current [ref/4. The remaining (N-2) bits are obtained using the same principle.

Figure 3.22(a) shows the schematic circuit diagram of the current-mode A/D
converter, where latches and control logic circuitry are not shown. The CV circuit consists
of a PMOS current copier, an NMOS current copier, and an opamp. It receives the input
current [in and the current reference levels via switches SI and SR, respectively. Figure
3.22(b) illustrates the sequence of Operations of the circuit. For the MSB conversion. the
input current Iin is first copied into Na, denoted by "Iin-9N3". Then, the current held in Na
is compared to [rep/2 to determine the bit value of the MSB, or d1, denoted by "C(NaJref/
2)". A comparator outputs a " 1" if the current difference between the current held in Na and
a reference current level is positive or zero, otherwise an output‘of "O" is obtained. Once
the bit value is determined, either the current difference (Iin‘ re9’2), for d1=l, or the current
Iin, for d1=0, is copied into Pa, denoted by "Na&dl(Il-ef/2)—)Pa". Finally, Pa sinks its copied
current to Na which holds the current to be converted for the next bit, or d2. The remaining
bits are converted in the same manner. Figure 3.22(c) shows the timing sequence for the
switches necessary to implement the copying sequence listed in Figure 3.22(b). Results
show that the circuit takes three clock cycles for each bit conversion. Note that the switch
81, the NMOS copier, and the opamp form a S/H circuit. Thus, the input current is sampled

and held in Na during the first cycle of operation.

 

 

 

"""""""""""""""""""""""""""""""""""""""

I"

 

 

0"0'000'0OOOOOODOO'O'D'OOOI00".

The Converting (CV) Circuit

 

 

76

 

 

 

 

 

 

 

 

The Reference-generating (RG) Circuit
(a)
Figure 3.22 Proposed Current-mode A/D Converter: (a) Schematic Diagram;
(b) Current Copying Sequence, and (c) Sw1tch1ng Sequence

D'0'0"...OO'OOIOOOO'C'O'OOOOOOOOOOOOOOOO0'00....00000'000'0'00000’

 

 

 

77

 

Clock RG Circuit CV Circuit P5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

l I ref _) pO
2 P0 —) N2&N3
3 N3 —) P4
4 N2&P4 —) CM]
5 P0&CM1 —) N2&N3 ,
6 N3 —) P5 [in —) Na
7 N3 —> Po C(NaJmf/z) x
8 PO —) N2&N3 Na&dl(lref/2) —) Pa X
9 N3 -) P4 X
10 N2&P4 -) CM] X
1 1 P0&CM1 —) N2&N3 X
12 N3 —> P5 . Pa —> Na
13 N3 —) P0 C(Na’Iref/4) X
14 P0 —) N2&N3 Na&d1(lref/4) —) Pa X
15 N3 -) P4 . X
16 N2&P4 —) CM] X
17 P0&CM1 —) N2&N3 X
18 N3 —) P5 Pa —) Na
(13)
[reg/2 § [ref/4’ d1 .5 [ref/8’ d2
50 F7 ‘ g
81 _1—1 4—1 = r—1_
S2 __J | 3 fl 3 j
83 W
84,86 _I_L_l'7 3 I7 I"! i l_L__|"|_
S5 _J U 5 LJ 3 LT
S7 _l—l 5 J l i J_l__
S9 W
S10 l_| J J‘l
311,812 . N j
I l_l_..-....-.-_'__ ............
Sa I 3 5 ........... l____' ............
Sb |'_1._ ........... l_|_ ............
Sc __-_l—= ............ |_I_J'_: ............
Sd _3_J_l .......... _._f._l_| ............
SR m .......... m ............

 

 

(c) :2: =0 lfdi=0;=1 lfdi=1

Figure 3.22 (Continued)

 

 

78

The RC circuit implements the current-mode divide-by-two circuit using the
improved version of the current divider described in Section 3.3 [43]. The PMOS copiers
with P0 and P5 are used to store each reference current level [ref/2t. P0 is used as a current
source for the next reference level generation, while P5 provides the CV circuit with the
current reference. The reference current is first applied to the circuit for generating [ref/2.
Then, the generated reference [ref/2 is applied to the circuit again for generating [ref/4, and
the process is repeated to obtain the remaining reference levels.

The basic operation of the RG circuit is described as follow. First, the reference
current [ref is copied into P0. The divide-by-two circuit divides it by two, where the number
of iterations required for this circuit depends on the desired accuracy. At the end of the first
cycle of the kth iteration, the current level [rep/2 is generated and held in N3. The next
current level [ref/4 is generated by copying the current held in N3, i.e., [ref/2, into P0 and
applying. the same division process. The resultant current level is also held in N3. The
remaining current levels [ref/2t are generated in the same manner.

Figure 3.22(b) illustrates the operation of the RG circuit which is as follows. First,
the current reference [ref is copied into P0. The divide-by-two circuit divides the current
held in P0 by two. During the first iteration, the circuit is operated as follows:
"PO—)N2&N3", "N3—>P4", and "N2&P4—)CM1". Then, at the end of the first cycle of the
second iteration, the currents held in P0 and the bipolar copier CMl are copied into N2 and
N3, where N3 holds the desired reference current level [ref/2. Once the current in N3 is set.
it is copied into P5 so that the reference current level is available for the CV circuit. This
completes the generation of [ref/2. The generation of [ref/4 is achieved by first copying the
current held in N3, i.e., [ref/2, into P0 and dividing the current held in dey two, where the
division process is the same as described above. Then, the resultant reference current level
[ref/4 held in N3 is copied into P5. The remaining reference current levels are generated in
the same manner. Figure 3.22(b) shows that the RG circuit takes 6 cycles for generating
each reference current level. Results show that the RG circuit implemented with such a
divider requires two iterations for achieving an N=10 bit resolution, with a practical 1%

mismatch between transistors N2 and N3 being assumed.

 

 

 

79

3.4.2 Analysis

Since the same circuit and its divided current are used repeatedly, the errors
resulting from the reference generations may add up. The. accumulated error has been
formulated and used to develop the relationship among the mismatch ratio 7, the resolution
bits N, and the number of iterations k [43]. The relationship of the accumulated error in
terms of k is now examined . As shown in (3.9), the current held in N3 at the end of the first

cycle of the kth iteration is

I '_ k _ k
1R1: 12‘1[1+(-1)‘ 19%) ] = {1+ (-1)" 1(§:_y) My (110)

When the current 1R1 is applied to the divider circuit again, the current held in N3 becomes

1 _ k 1 _ k 2
IRZ = —§—1[1+(-1)k 1(2_:Y) ] = ?[1+ (-1)k [(7:7) :1 [ref (3’11)

Therefore, for generating the current level [ref/2'“, m=l, 2,.., N, the current held in N3 can

be generally expressed as follows,

I - - k - k m
[Rm = a; 1[1+(_1)k 1(2—I—y) ] = 2%[1+ (_1)k 1(2_:7y):| [re/(3.12)

 

The accumulated error is estimated by considering the worst case where a suing of
1’s results. The input current to be converted as a string of 1’s should be the sum of all
reference currents [ref/2t and it is expressed as

[3 1y 2 [y N
(3)1,44- (7) Iref+...+ (-2—) lmf (3.13)

I}:

where

1 Y

I =1+(—1)"‘ (—) (3.14)

 

.' l..-

80

and the accumulated error is

1,-1 13-1 I
E2 zlref ‘—-—+-’——+...+ '

 

_ l )
, (3.15)
2 2* 2”

For an N-bit converter, the accumulated error term E2 must be less than l/ZNH.

Accordingto (3.15), Table 3.3 lists the relationship among 7, N, and k.

Table 3.3 Relationship among 7,.k and N

 

 

k Resolution (bits)

’ Y 4 6 8 10 l2 l4 l6
1% l 2 2 2 2 3 3
2% l 2 2 2 3 3 3
5% 2 2 2 3 3 3 3
10% 2 2 3 3 4 4 5
20% 2 3 3 4 5 5 6

 

 

 

 

For example, with 20% mismatching of transistors N2 and N3, the divide-by-two
circuit can be used to achieve a 10-bit resolution by taking 4 iterations for generating each
reference level. For the practical 1% mismatching, the circuit takes only two iterations to
achieve a lO-bit resolution. Note that the operation with k iterations in this implementation
includes 1 clock cycle of loading input data and 3(k-l)+l cycles of generating half of the
input currents, i.e., the operation requires (3k-1) clock cycles. Thus, the RG circuit of
Figure 3.22(a) requires 5 cycles for generating the reference levels for a lO—bit conversion

with 1% mismatch in N2 and N3.

3.4.3 Design Evaluation

The CV circuit in Figure 3.22 requires 3 clock cycles while the RG circuit requires
6 cycles for each bit conversion, and both are operated in parallel. Thus, for repetitive
conversions of continuously changing inputs, the converter requires 6N clock cycles for an

N- bit conversion. However, for a single conversion, the converter may need (6N+1) cycles.

 

81

In practice, however, the conversion rate can be improved by sharing the slower RG
circuit. More specifically, each reference current level is available in P5 for 5 cycles, as
indicated by the "x" in Figure 3.22(b). Since the CV circuit uses the [ref for only two cycles.
the RG circuit is capable of driving one more CV circuit to improve the conversion rate as
shown in Figure 3.23. Thus. a converter with a common RG circuit and two CV circuits
requires 6N cycles to convert two input currents. Thus, for the repetitive conversions of
continuously changing inputs, the average conversion time is 3N cycles.

For the general case where the divide-by-two circuit requires k iterations to achieve
an N-bit resolution, the RG circuit needs 3k cycles to generate each reference current level.
Since the current held on P5 is available for (3k-l) cycles, it can provide V: [#J CV
circuits, where L J stands for the floor function. Thus, such a converter array requires 3kN
cycles for converting v consecutive input currents, i.e., the average conversion time is 3kN/
v cycles. Each conversion is done every two consecutive cycles when [ref/2t is made
available to the corresponding CVi circuit. Therefore, for the 10% mismatch, the divide-by-
two circuit requires 3 iterations for N=10. The converter achieves an average conversion
time of 2.25N cycles. On the other hand, for a mismatch of 20%, the divide-by-two circuit
requires 4 iterations for N=10. The average conversion time is 2.4N, or 24 cycles. This
demonstrates that the mismatch of transistors N2 and N3 will not affect the average
conversion time. 3

Note that current divider achieves a more accurate result if more iterations are
taken. A larger transistor mismatch may require more cycles to achieve the desired
accuracy. As a result, P5 will hold the reference current level for more cycles and connect
more CV circuits. The conversion time can be improved, but the improvement is limited by
the CV circuit operation. In the next section, a parallel array structure is presented to

achieve higher conversion rate.

 

82

Referencegenerating (RG) Circuit

 

 

 

 

 

 

 

'OIOIOOO'COOOOOODODD'O'OOOOOIOOO0'...'0'.O'OCOIOOOOOOO'OOOOO'OOOOOOOOOOOO'0...
o a
I | u
1 V00 5 : CV Array :
u
. 5 : :
I l
s \
3 1C4 C5 5 ~ ~
‘ ' :0 :
I
I S s \ CV1 \
' SB 12 I : SI ‘
l 1 ‘ \
' ' t :
I I
' CM! ' 3 nmxr ‘
5 / z - :
I ’ \ \
a \ u
I 89 S7 SI] 1 = :
a
' I 5 : :
a a
I '" T + a ‘ ‘
i 32 " i CV :
0 SO ‘- s \ 2 t
' ' ‘ 5x2 ‘
' - ' ‘ ~
I _ 1 ‘ \
: C S ' i i
a
' 1 In! S1 5 ' ‘ ‘
I p ‘ \
‘ ' .“‘\\““““\\\“““\\‘\“
a a
I I
a a
: l
a
: N2 N3 :
a S S a
o ‘ 6 a
a a
I I
z ' :
I C2 C3 '
' VS I
a I
I a
5 t
’O'O‘ll'l'tili0"0”Cof'O'OIOOOC’OIIOIOO'CI'ICOIOIOCIO'C'l'Ofl'Cl'vfl'O'O'IIOIO:

 

 

 

Figure 3.23 A Converter Array with two CV Circuits

 

 

83

3.4.4 Array Structures

In general, the CV circuit of a successive-approximation A/D converter may require
only two or three cycles. Thus, the slower RG circuit may degrade the conversion rate. In
practice. however, a common RG may be shared by several CVs to simultaneously convert
several analog data. The implementation of the R0 in an A/D converter array to achieve a
higher conversion rate is discussed.

High conversion rate can be achieved by using a parallel array structure with a
common RG circuit. Figure 3.24 shows an alternative RG circuit which is comprised of a
current-mode divide-by-two circuit and two PMOS copiers with PI-Ii, i=1 and 2. Similar to
P5 in Figure 3.22, Pm are used to hold the generated reference current levels for the use of
the CV circuits. For the case of 1% mismatch, the divide-by-two circuit takes 5 cycles to
generate the reference current level which is held in N3. Together with two cycles for
copying the current in N3 into PHI and Pm, the RG circuit requires 7 cycles for each
reference current generation. Since each Pm holds the current for 6 cycles, it can provide 3
CV circuits, as shown in Figure 3.24(b). Thus, the RG circuit connects to 6 CV circuits via
the two analog demultiplexers (each has three switches).

Consider a general RG(m) circuit which is comprised of a current-mode divide-by-
two circuit and m pairs of PMOS copiers, i.e., 2m PMOS copiers with Pm, i=1,2,..,2m.
Thus, the RG circuit in Figure 3.24(a) is a RG(l) circuit. In general, a RG(m) circuit
requires 5 cycles for generating each reference current level and 2m cycles for copying it
to all Pm, i.e., (2m+5) cycles in total. Each Pm holds the reference current level for (2m+4)
cycles and connects to (m+2) CV circuits via an analog demultiplexer. Thus, a converter
consisting of a RG(m) circuit, 2m(m+2) CV circuits, and 2m demultiplexers, requires
(2m+5)N cycles to convert (2m2+4m) input currents. Figure 3.24(c) illustrates a converter
array with a RG(2) circuit.

Since a RG(m) circuit is comprised of a divide-by-two circuit and 2m PMOS
copiers, its hardware includes a bipolar copier, an opamp, two NMOS copiers, and (2m+2)

PMOS copiers in total. Thus, the converter array with a RG(m) requires (2m2+4m+1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.... N...
M fl
C 2

—S

 

 

CV Array

‘OCCJIOOOU‘OI'O'OI

(a)

I
O
I
0
I
O
I
O
0

CV Array

"""""""""""""""""""""""""""""""""""""

 

 

 

OOOOOODOOO'OOOOOOCJ

 

 

 

 

 

 

I.

"D'O'IOOOOOOODU

" " ""

(C)

Figure 3.24 Converter Arrays (a) RG(l) Circuit; (b) RG(l) Circuit with

2-by-3 CV Array; and (c) RG(2) with 4-by-4 CV Array

 

85

opamps, (2m2+4m+2) NMOS copiers, (2m2+6m+2) PMOS copiers, (2m2+4m)
comparators, (2m2+4m) switches (for demultiplexer circuits), and one bipolar copier. As.
a result, the number of each type of components, except the bipolar copier, is quadratically

increased with m.
3.4.5 Hardware Reduction

Since the CV circuits are dominant in the hardware of the converter circuit with a
RG(m) circuit, the hardware cost can be reduced considerably if some components in those
CV circuits can be shared. Figure 3.25(a) shows a structure with four CV circuits, CVi,
i=1,2,3,4, which are connected to the PHI of the RG(2) circuit via the switches Si of the
demultiplexer. The PHI holds the reference current level for eight cycles, and it sinks its
current to the CV1 circuit during the first and second cycles, to the CV2 during the third and
forth cycles, to the CV3 circuit during the fifth and sixth cycles, and to the CV4 during the
seventh and eighth cycles. Note that each CV requires only three cycles to complete its
operation. This means that the CV1 circuit completes its operation and becomes idle when
the CV3 circuit starts off its operation. Thus, the opamp and comparator in the CV1 circuit
can be shared by the CV3 circuit. In addition, since the PMOS copier in each CV circuit is
used as temporary storage while the NMOS copier stores the current to be converted, the
PMOS transistor in the CV1 circuit can also be shared by the CV3 circuits. As a result, a
circuit that combines the CV1 and CV3 circuits, referred to as the combined CV circuit, or
denoted as CCVO, is shown in Figure 3.25(b). Similarly, a circuit combining the CV2 and
CV4 circuits, referred to as CCVe, has the same structure.

For a converter array with a RG(m) circuit, each PHi connects to a CCVO circuit and
a CCVe circuit, where the CCV0 circuit combines [(m+2)/2] CV circuits and the CCVc
circuit includes the remaining L(m+2)/2_I circuits, where I' I stands for the ceiling function
and L J stands for the floor function. The CCV0 (CCVe) circuit is comprised of [(m+2)/2"
(I_(m+2)/2J) NMOS copiers, one PMOS copier, one opamp, and one comparator. In

addition, the CCV0 and CCVe circuits are connected to the RG(m) circuit via switches S0

 

86

8‘ CVl
32 CV2
S3 CV3
S CV4

(a)

CCVe or CCV0

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

 

CCVO Comparator

 

 

ccve

 

 

“\““““““““““‘ ““““““““\“““‘
v ‘
‘\\“ “““““““\‘““““‘“‘\\\“‘.“““\

(b)

Figure 3.25 Hardware Reduction (a) An Array with 4'CV Circuits; and
(b) Combined CV (CCV) Circuits: CCVO and CCVe

 

 

87

and Se, respectively. Thus, the array structure requires a RG(m) circuit, 2m CCVo circuits.
2m CCVe circuits, and 4m switches, i.e., it requires (4m+1) opamps, (6m+2) PMOS
copiers, 4m comparators, 4m switches. (2m2+4m+2) NMOS copiers, and one bipolar
copier in total. Consequently, the numbers of opamps, PMOS copiers, comparators, and
switches are linearly proportional to m, instead of m2. Thus, the chip area is reduced

considerably.

3.4.6 Implementation

Since the basic circuit components of the converter array structures and their
operations are similar to the successive-approximation current-mode A/D converter
reported in [13] in which its prototype circuit has been fabricated using 3um CMOS
technology. The circuit achieves a resolution of 10 bits with a maximal sample rate of 25
KHz, or 40 psec conversion time. Since the converter requires 4N clock cycles for an N-bit
data word, this implies that a cycle of 1 usec is sufficient to stabilize the circuit operation.
The fabrication data reported in [13] may be used to assess the performance of the converter
array structures. Based on the experimental data in [13], the converter with RG(m), where
m=10, for example, requires (2m+5)N, or 250 cycles, or 250 usec, or 4 Kframes/sec. for a
12-by-20 sensor array with a 10-bit resolution. Its hardware includes 41 opamps, 62 PMOS
copiers, 40 comparators, 4O switches, one bipolar copier, and 242 NMOS copiers. Note that
the converter in [13], consisting of 3 MOS copiers, an opamp, two switches, and a
comparator, takes only 0.6x0.2mm, or 0.18mm2. Thus, it is predictable that the converter
requires a reasonably small chip area which is well suited for use in smart sensor array
designs.

It is obvious that the sample rate of the converter array can be increased as m is
increased. However, it should be mentioned that the reference current in each Pm of the
RG(m) circuit must be held for (2m+4) cycles. As m increases, larger capacitors may be
needed so that the copier can accurately hold the reference current level. Although larger
capacitors may reduce the effects of the thermal noise and charge injection from the

switches, they lead to slower settling time. The dilemma is that, as m increases. the

 

88

conversion rate increases, but the settling time may decrease. Thus, a point will eventually

be reached where an optimal conversion rate, i.e., an optimal value of m, is obtained.
3.5 Summary

In this chapter, several new current-mode signal processing circuits have been
presented. A bipolar copier with its bidirectional copying capability is an essential element
in general purpose multipliers and dividers. In analog fault diagnosis with current data. a
malfunction in a circuit may cause currents to be of any polarity. The CMOS bipolar copier
can be an important part of fault diagnosis systems and can be used to load current test data.

The current-mode shift register can be used to load sensory information for signal
processing of sensor arrays and arranged to exploit the parallelism of an array structure.
The study of the shift-register structure also indicates that it can be easily adapted to obtain
an analog BIST design for current test data. A highly accurate current divider that does not
require matched components or external adjustments has also been devel0ped and
successfully implemented as a reference-generating unit of a successive-approximation A/
D converter. Section 3.4 presents a successive-approximation A/D converter that uses a
divide-by-two scheme, thus avoiding the accumulation of error and noise that can be
associated with the multiply-by-two methods. In order to improve the conversion rate that
can be degraded due to a slow reference generation, array structures have been described.
These current-mode A/D converter arrays contain subconverters that do not rely on high
gain amplifiers or well-matched components to achieve high resolution and are inherently
insensitive to the amplifier's offset voltage. These arrays utilize the inherent idleness of
several operational blocks to execute the conversions in parallel at very low hardware cost.

Even though these structures are successful in function, during real-time operations
it is difficult to achieve data validation of these circuits. Thus, the reliability of the current-
mode signal processing circuits and their data has to. be‘ ensured and so the diagnosable

design of current-mode data-acquisition and data-conversion circuits has to be addressed.

 

Chapter 4 '

Testable Current-mode Circuits

 

A/D and D/A converters are the main link between the analog world of signals and
digital systems that control and monitor electronic applications. The properties of the
converters used for such systems are important and reliability is one of the crucial
elements in their make-up. During real-time operations, a system failure could have fatal
results. Consequences of such failures stress the importance of converter reliability and
reliability of electronic circuits in general.

The objective of this chapter is to present schemes to improve the testability and
reliability of current-mode data-acquisition and conversion circuits. In order to enhance
the reliability of A/D converters for real-time operations, an alternative current-mode A/D
converter with CED capability is described in Section 4.1 to detect transient and
permanent faults [44-46]. Further, the fault effects and test generation of the current-mode
A/D converter proposed in [13] is presented. Based on the single stuck-at fault model for
the switching elements, the converter can achieve full testability with the application of
two test currents. In the past, analog circuit fault diagnosis algorithms that have been
developed are restricted for use only on small-scale networks due to the limited number of
available test points. Section 4.2 presents analog BIST structures using voltage test data
and current test data which can be used to make fault diagnosis and testing of analog

circuits much simpler.

89

 

90

4.1 Testable Current-mode A/D Converter

In this section, a diagnosable current-mode A/D converter with CED capability is
presented and thus it can achieve data validation for real-time applications [44]. Due to the
continuum nature of analog circuits, it is extremely difficult to generate a finite and
complete set of test vectors. Exhaustive tests are impossible even though the number of
inputs of an analog circuit may be reasonably small, and so analog circuits become very
difficult to test. This section addresses the fault effects and test generation of an algorithmic
current-mode A/D converter, and the design achieves full testability with the application of
only two test currents [44]. Thus, a test set of only two vectors is all that is necessary for

100% fault detection.

4.1.1 Concurrent Error Detection

Figure 4.1 illustrates a CED scheme with the AL implementation. First, the input
current I”: in is converted during the first time step (or, normal operation phase) and the
resulting digital data word is stored in a digital shift register. Then, the complemented
current Ia=lref - in is converted during the second time step (or, recomputing phase). The
digital data words resulting from both phases are compared to identify an error, if it exists.
If the converter is fault-free, the converted data resulting from both phases must be bitwise
complements of each other. For example, with the reference current of IreFIOOuA, the
input current 27uA and its complement 73uA are converted to the lO-bit data word
D1=(0100010100) and D2=(1011101011), respectively, where both D1 and D2 are bitwise
complements- Since the comparison is in a digital manner, a totally self-checking (TSC)
checker can be used to identify the error and also to ensure the correctness of the checker
circuit. Therefore, a reliably converted data word can be attained.

Figure 4.2 shows the current-mode A/D converter with the CED capability. The
input current [in is sampled only once and the current is stored in P1. In order to store the

current (Imp/in), an additional PMOS current copier is needed to hold the current at the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

91
l Iref
[in (In) . .
__._ A/D Convener - , Dlgltal OUtpUt
Shift Register
Time t1 -
.......................................................................... b-.---.—.--..---~---~.---.-.-.--...
l—out-of—2
Time t2 1 [ref checker
Totally
-> . . —>
Iref‘ 11" (la) Self-Checckrng
(TS )
-—Di A/D Converter Comparator —>

 

 

 

 

 

 

Figure 4.1 CED Structure with AL Implementation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 C4 1 C3
|——L/ bl? Comparator
P2 89 (Enugrgth)
Comparato —o
38 36
MI 9 l +
Amplifier
S4 f '
|__I_/S3 N2 35
I14 :
TC] :- C2
(a)
CurrentI NORMAL OPERATION PHASE RECOMPUTATION PHASE
S/H MSB Previous bit = 1 Previous bit = 0 MSB Previous bit = 1 Previous bit: 0
s1 |"l
52 _I—U—L m1 I‘LJ_I_ l—l_l_|_ I—Ll—L I_l_l_l_
83 .n n_. ri— m— H_ H—
84 _LJ_L_ _I'_L_ _l—'I_ _F—L. n _I—_l_
ser F I
s—; |_L_§_J—I_ _m_ __J—L
38 _I—I I I I
s. It __ _rL __l_L_ __J—L
Srolj I II __II___II I__I __II
(b)

Figure 4.2 Proposed Current-mode A/D converter with CED Design:
(a) Schematic Diagram; and (b) Switching Sequence

 

93

beginning of the data-conversion. The input current Iin is copied and stored in P1 by turning
on Switches 31, 36, and S7, while the current difference (Iret‘lin) is loaded to P2 by turning
off S1 and S7 and turning on S8, Sg, and S 10. Once both currents are stored. the current held
in P1 and the current held in P2 are converted. The results from both conversions are
compared to identify an error, if it exists. The data-conversion process is exactly the same

as presented previously. Figure 4.2 (b) illustrates the switching sequence.

4.1.1.1 Fault Models

Since the current-mode A/D converter implements a ratio-independent algorithm
for conversion, any mismatched components do not affect the converted data. However,
any faulty switching element may result in incorrect operation and thereby erroneously
converted data. The single stuck-at fault model has been commonly employed for digital
test generation. In this implementation, it is assumed that only one faulty switch occurs at
a time and the faulty switch is permanently or temporarily stuck-at ON state (S/ON) or OFF
state (S/OF F). In general, the faults may be caused by either an erroneous clock generator
where the tinting control signal may be permanently stuck-at-l (or 0) causing the controlled
switch to be S/ON (or S/OFF). These faults can also be the result of malfunctioning
transistor switches.

Temporary faults, or transient faults are such that the duration of fault behavior is
sufficiently short. Transient faults have been very common in today’s digital VLSI design.
Since all switches in the A/D converter are controlled by the digital clock signals, a signal
may temporarily change its value from 0 to 1 or from 1 to 0 and cause the switching
elements to temporarily malfunction. For permanent faults, the duration of the fault
behavior is sufficiently long. In general, the permanent faults may be caused by either an
erroneous clock generator where the timing control signal may be permanently stuck-at-l
(or 0) causing the controlled switch to be S/ON (or S/OFF), or by malfunctioning transistor

switches. For a reliable circuit design, the permanently faulty switches can be tested by an

 

94

off-line test process. The chance that permanent faults occur during the normal operation

is rare. However. the design can still detect most of the permanently faulty switches.

4.1.1.2 Fault Coverage

In general, the duration of a transient fault is sufficiently short. It is most likely
shorter than the conversion time for the converter, i.e., 4N clock cycles. Here, a fault may
occur during the first time step, or during the second time step, or overlap in both time steps
(but the duration is shorter than 4N). If the fault occurs only during the first time step, i.e..
the fault disappears during the second time step, then the converted data word D2 is reliable
and can be used to check D1 for identifying an error, if it exists. Thus, the fault is detectable.
Similarly, the fault that occurs only during the second time step is also detectable. Now, if
the fault occurs after the rth bit of D1 is being converted and disappears after the (r-1)th of
the D2, for any integer r, then at least the first (r- 1) bits of D1 are reliable and can be'used
to identify the fault. Thus, the fault is detectable and the design can detect all transient
faults.

If the duration of fault behavior is longer than the time required to complete the first
time step and the second time step, all time redundancy CED schemes will no longer
possess the property of disjoint error sets, and the errors, thus, cannot be detected. This
implies that not all permanent faults are detectable. It would be preferable for the circuits
to be designed so that they will indicate malfunction during normal operation and will not
produce an erroneous result without an error indication. In these circuits, any failures will
cause a detectable erroneous output during normal operation, and each fault must not cause
an erroneous output without also producing an error signal. The circuits that possess this
property are referred to as fault secure circuits.

The errors resulting from these faulty switches can be categorized into four types.
The errors that can be definitely detected by the CED scheme are referred to as Type 1
errors, i.e., a Type 1 error causes Dl¢fiz for all possible input currents. The errors that
cannot be detected are referred to as Type 2 errors, i.e., a Type 2 error causes D1=Dz for

all possible input currents. In some cases D1152 for all possible input currents except a

 

95

few. For these few where D1=D'2, if the resulting data word D1 is reliable even in the
presence of fault(s), then the circuit is fault secure and such an error is referred to as Type
3 error. On the other hand, if the resulting data word D1 is not reliable in the presence of
fault(s), then the fault cannot be detected for the application of such input currents and this

error is referred to as Type 4 error.

A. Type 1 Errors

Type 1 error causes DlatDz for all possible input currents. These errors are
definitely detected by the CED scheme. Such errors are the results of S/ON faults at 82, S3,
S4, and S5 and S/OFF faults at $2 and S4. Table 4.1 lists the faults and fault effects of Type
1 errors.

Consider a S/OFF faulty switch 82. During the first time step, for the fault-free
circuit, the input current [in held in P1 is copied to both N1 and N2, and then the sum current
Zlin is copied back to P1. However, because of the faulty switch N1 cannot sink any current
held in P1. This is equivalent to a zero current being held in N1. Thus, only the [in held in
N2 is copied back to P1, i.e., P1 holds Iin in each bit conversion. This results in D1=(00..O)
regardless of converting any input current. During the second time step, the conversion of
the complemented current IreFIm, the resulting data word D2=(00..0), i.e., DlatDz for all
possible input currents. Thus, this is a Type 1 error. Since the S/OFF fault of switch S4 and
the S/ON faults of switches 32 and S4 have the same fault effect, thus these faults are all
detectable, i.e., the errors are all Type 1 errors. I

For the S/ON faulty switch S3, during the first time step, the currents [in and (Imp
Iin) are respectively held in P1 and P2. When the current held in P1 is converted, the current
is first copied to N1 and then to N2. Now, when the current is copied to N2, the fault causes
the gate-source voltages of both N1 and N2 to be the same. If both N1 and N2 are well-
matched, the currents held in both N1 and N2 will be the same. However, if both N 1 and N2
are mismatched, the current held in N1 is overwritten. When the currents held in N1 and N2
are copied back to P1, due to the S/ON faulty switch S3, the operation is equivalent to

copying the current held in N2 to a CMOS current copier consisting of PMOS P1 and

 

 

96

NMOS N. The experimental results have shown that D1=(00..0) and D2=(10..0) for a
sufficiently low input Iin; D1=(10..0) and D2=(00..0) for a sufficiently high input Iin; and
D1=(00..010..0) and D2=(00..010..0) for the others. Obviously, the error can be detected for

either case. Thus, it is a Type 1 errors. Similarly, the S/ON fault of S5 has the same fault

 

 

 

effect as that of S3.
Table 4.1: Type 1 Errors
Fault ' Analysis Fault Effects
32 (s4) S/OFF Zero current held in N1 (N2). ol=oz=(00...00)
Current not doubled.

 

82 (S4) S/ON N1 (N2) cancels current from P1 or P2. D1=D2=(00...00)
N2 (N1) holds zero current.
Current not doubled.

S3 (S5) S/ON Output depends on the CMOS structure One bit of D1 equals
Pl/N 1 (Pl/N2). the respective of D2.

 

 

 

 

 

 

B. Type 2 Errors

Type 2 errors cause D1=Dz for all possible input currents. These errors are caused
by either not reading the input current (S/OFF fault at 81), or not reading the reference
current (S/OFF fault at 810), or the equivalent fault effects (S/OFF fault at S6 and S/ON
fault at 810), as shown in Table 4.2. In general, these errors are not detectable by the CED
scheme.

For example, a S/OFF fault at 81 implies that a zero current is copied to P1 and thus
[ref is copied to P2. Thus, D1=(00..0) and D2=(11..1), i.e., D1=Dz for all possible input
currents. Such a Type 2 error is definitely undetectable. Similarly, the S/OFF faults of
switch S6 has the same fault effect as above and the errors are also of Type 2.

Consider a S/OFF fault at S 10. The fault is equivalent to the A/D converter using a
zero reference current. First, the input current [in is copied to P1. Then, P2 was expected to
source a current equal to (Implin). However, the zero reference current results in a negative

current, “Iin: being copied to P2 and causes a breakdown in transistor P2. Since, during the

 

 

97

first time step, P1 holds the current [in and the reference current 1,650. the resultant data
word D1=(l 1..1). On the other hand, the breakdown of transistor P2 may result in
D2=(00..O). Thus, D1=52 for all possible input currents and it is a Type 2 error. Similarly.

a S/ON fault at 810 has the same fault effect. Thus. it is also a Type 2 error.

Table 4.2: Type 2 Errors

 

 

 

 

 

 

 

Fault Analysis Fault Effects

31 S/OFF EquivaTent to lin=0. DI=DZ=(00...00)
P1 holds zero and P2 holds [rep

S6 S/OFF P1 never copies current. D1=Dz=(00...00)
P2 holds (ref.

S 10 S/OFF Equivalent to Iref=0. D1=Dz=( l l...l l.)
'[in forced into P2

S 10 S/ON [ref always added to the current copied D1=Dz=( l 1...] 1.)
into P1.

 

 

 

 

'lin forced into P2

 

C. Type 3 Errors

In some cases D1¢DZ for all possible input currents except a few. For these few
where D1=D-2, if the resulting data word D1 is reliable even in the presence of fault(s), then
the circuit is fault secure and such an error is referred to as Type 3 error. Table 4.3
illustrates the fault effects of Type 3 errors. The faults include S/ON faults at 86, S7, Sg,
and 89: S/OFF faults at 88 and Sg.

Consider a S/ON fault at S6. According to the switching sequence shown in Figure
6(b), S6 is on for the entire conversion cycle during the first time step. Thus, the resultant
data word is still correct even in the presence of such a fault. On the other hand, at the end
of the first time step, the current held in P1 is Ix, where Ix is less than 1 LSB if the last bit
of D1 is 1; otherwise I7‘ is greater than I LSB. Due to the=faulty switch 86, the current, Ix.
held in P1 is always available during the second time step. This is equivalent to converting

the sum of Ix and the current held in P2 for each bit conversion. If Dye-132, then the checker

 

98

will indicate an error. On the other hand, if D5132, the converted data word D1 is reliable.
Thus. the circuit is fault secure and the error is of Type 3.

Similarly, a S/OFF fault that occurs at SS or 89 and a S/ON fault at 89 does not affect
the conversion in the first time step, i.e., D1 is reliable. However, the S/OFF faulty switches
83 and S9 results in D2=(00..0), while the S/ON faulty switches Sg may cause P2 to source
a random current. Thus, the circuit is fault secure in the presence of such fault(s) and the
error is of Type 3. In the same manner, a S/ON faulty switch 88 results in D1=(l 1.. l) for
all possible input currents, but provides a reliable data word D2. If there exists, at least, one
l-bit in D2, the comparison will identify an error. On the other hand, if D2=(00..0), then D1

provides a reliable result. Thus, the circuit is also fault secure in the presence of such a fault.

Table 4.3: Type 3 Errors

 

 

 

 

 

 

 

 

 

 

 

Fault Analysis Fault Effects

S6 S/ON Normal operation phase not altered. D1: correct
Residual current in P1 always sourced dur- D2: random
ing recomputation phase.

S7 S/ON During comparison P1 initially copies [ref D1=(11...11)
and then gets compared. D2: approximately
Recomputation phase always converts the digital output
approximately [ref/2. of [rep/2

Sg S/ON Residual current in P2 always sourced dur- D1: random
ing normal operation phase. D2: correct
Recomputation phase not altered.

89 S/ON Normal operation phase not altered. D1: correct
During comparison P2 initially copies [ref D2=(11...ll)
and then gets compared.

S8 S/OFF Normal operation phase not altered. D1: correct
P2 never copies current. D2=(00...00)

Sg S/OFF Normal operation phase not altered. D1: correct
Residual current in P2 always compared D2: random
with lmf.

 

 

 

 

 

   

99

Consider the S/ON faulty switch S7. The fault causes the current held in P1 to be
changed whenever the opamp is in use. For example, after the input current I in is loaded to
P1, the current (Iret‘lin) is copied to P2. The faulty switch S7 will cause the gate-source
voltage of P1 to be changed as the same as that of P2 and. thus, changing the current held
in P1. In addition, when the current held in P l is compared to the reference current [ref to
determine the converted bit value, the faulty switch S7 causes the current held in P1 to be
[ref and, thus, a " l " results. This implies that D1=(l 1..] 1). Since the fault does not affect the
conversion of the current held in P2, hence, the converted data word _D2 is reliable. Similar

to the above discussion, this is a Type 3 error.

D. Type 4 Errors .

If the resulting data word D1 is not reliable in the presence of fault(s). then the fault
cannot be detected for the application of such input currents and this error is referred to as
Type 4 error. The fault effects of such error types are listed in Table 4.4. The faults include
S/ON fault at SI; S/OFF faults at S3, 85, and S7.

Consider the S/ON faulty switch 81. It is assumed that the input current will be
varying for real-time applications. The fault implies that the data is converted in the
environment where the noise is equivalent to the varied input currents. Thus, D1 and D2 can
be any random results. Statistically speaking, the probability of having two random data
words D1 and D2 as complements to each other is very low. Thus, this is a Type 4 error. _

Due to the S/OFF faulty switch 87, the current copier with P1 cannot copy any
current. Thus, the current, Ix, held in P1 is the one remaining from the previous operation.
This results in D1=(00..0) if Ix < Inf, or D1=(11..1) otherwise. Since P1 can still source the
current Ix, the current held in P2 is (’ret‘lx) and the resultant data word D2 is reliable.
Therefore, D1=D'2 only if either Ix or (Iret‘lx) is less than 1 LSB, D1¢D_2 otherwise. This is
a Type 4 error. Similarly, the S/OFF faulty switch S3 causes the current copier with N I not
to copy any current. Assume that the current held in N1 ‘is Ix. Experimental results. have
shown that D1=Dz only if Ix is very close to [ref/2, and D1552, otherwise. For a reliable

design, the chance that the fault occurs when the current held in N1 is [ref/2 is rare. Due to

 

100

the analog nature, this error is of Type 4. Since the fault of S/OFF switch 85 has the same

fault effect as S3, the error is also a Type 4.

Table 4.4: Type 4 Errors

 

Fault Analysis Fault Effects

 

 

Sl S/ON Varying [in always sourced to the circuit. D1 & D2: random

 

S3 (SS) S/OFF N1 (N2) do not copy any current but its D1 & D2: random
residual current is sourced. ‘

 

S7 S/OFF Residual current in P1 always compared D1 & D2: random
with Inf. Recomputation phase converts
the complement of this residual current.

 

 

 

 

 

Based on the above discussion, Table 4.5 summarizes the status of error detection
of the A/D converter with CED capability. There exist eight Type 1 errors, four Type 2
errors, five Type 3 errors, and three Type 4 errors. If the fault coverage is defined as the
total number of Types 1, 3, and 4 errors over all possible errors, the fault coverage of

permanent faults is 80%.

Table 4.5: Error Detection

 

 

Switches S/ON S/OFF
Type Type
S1 4 2
32 1 1
S3 1 4
S4 1 1
55 1 4
S6 3 2
37 3 4
S8 3 3 .
S9 3 3
310 2 2

 

 

 

 

 

 

101

4.1.2 Test Generation

For the A/D converter in [13], the input current is needed during the first two clock
periods of the conversion cycle, a sample-and-hold (S/H) circuit is, thus, required for the
input current. In practice however, the S/H circuit may be omitted by holding the input Iin '
in P1, where the polarity of the input current is changed as shown in Figure 4.3. The
sampled current is held in P1 by turning on switches SI, S6, and S7 to cause the current in
P1 to be set to [in- Once P1 is set, the remaining switching sequences are the same as those
in Figure 2.9. In other words, the converter needs 5 cycles to determine the MSB.
Therefore, there exists a trade-off between hardware (a sample-and-hold circuit) and speed

(an additional cycle).
4.1.2.1 Fault Model and Fault Effects

Although mismatched components are allowed in the converter of Figure 2.9, the
converter is still susceptible to faulty switching elements which cause incorrect operation
of the converter. A single stuck-at fault model is assumed where only one switch is faulty
at a time and it is permanently stuck-at ON state (S/ON) or OFF state (S/OFF). The cause
of these faults could be malfunctioning clock generators or transistor switches.

The analysis of the faulty switches in the converter of Figure 4.3 revealed that the
fault effects can be classified into three types: Type 1 fault effect occurs when the faulty
switch results in the same conversion output regardless of the values of the input current.
Switches SI, 82, S4, S7, and 810 being S/ON and S], 82, S4, S6, and Sm being S/OFF
illustrate this fault behavior; Type 2 occurs when the faulty switch renders the conversion
output dependent on the initial condition of the active capacitors. Switches S3, 35. S7 lead
to this condition when S/OF F ; and Type 3 faults make the result of the conversion process
dependent on the CMOS structure PI/N 1 (or P1/N2) when S3 (or 35) is being S/ON.

Throughout the next analysis, [Pl (1N1, or 1N2) will denote the current held in P1 (N1, or N2).

 

‘—
r..-

102

 

 

 

P1
Comparato
86 l
+
r { Amplifie
SI S 10 32 S4 f '
Iin Iref N1 53 N2 55

#

 

 

 

Figure 4.3 Modified Current-mode A/D Converter

Comparator
Output
(to latch)

_o

 

 

 

103

A. Type 1 Fault Effect

Consider the case when 81 or S6 is S/OF F , the input current will not be copied into
P1; this is effectively equivalent to an input current of zero. Consequently, the conversion
process results in a string of zeros. When 82 (S4) is S/OF F , the input current in P1 will never
be doubled. In fact, S2 (S4) being open circuited results in N1 (N2) contributing zero current
to P1 during the copying of the sum current [Ms-11.12. Hence the comparison of current in
P1, i.e., Iin, and [ref always results in a zero bit. Sm being S/OF F leads to the current in P1
being compared to zero instead of Iref. Hence conversion results in a string of ones. When
$1 is S/ON, P1 gets the input current; however when P1 is being copied into N1 (N2), N1
(N2) gets the difference current (Ipl-lin)=0. The comparison of [p1 (=IN1+IN2+’in) and I ref
produces a zero MSB. Next, instead of P1 being copied into N1, the zero current difference
UPI-I'm) is copied into N]. Hence conversion results in a string of zeros.

At the end of every conversion, the capacitors are left charged. This charge
represents the last current that has been copied into the corresponding transistor. Since N1
and N2 copy either the current [p1, when [131 < Iref, or the current difference (lpl'lrcf), when
[P] > (ref, the current in the corresponding NMOS, at any instant, is bounded between zero
and (ref. If 82 is S/ON, both the initial current [N1 and the input current [in will be copied to
P1, i.e., P1 gets Iin‘I'lNl- Then P1 is successfully copied into N1. However, when P1 is being
copied into N2, the current in N1 is subtracted from it resulting in copying zero current into
N2. Hence the current in P1, will not be doubled. During the comparison phase, the
comparator senses the current imbalance, - ref, from P1, N1, and Inf. Thus, a zero bit always
results. Similarly, when S4 is S/ON, a string of zeros is resulted.

While comparing P1 and Iref with 87 being S/ON, P1 will first copy Iref due to 37
being ON. At the end of the comparison cycle, the difference between [p1= ref and [ref will
be compared leading to a conversion bit of 1. This scenario is repeated for all conversion

bits. Thus, a string of ones results.

B. Type 2 Fault Effect
When S3 is S/OFF, the transistor N1 cannot copy any current because the capacitor

C, has no charging path. Thus, N1 will retain the current it has copied prior to the

104

occurrence of the fault. This current will be held constant since the capacitor can only leak
its charge through the gate to source impedance. In the presence of such a fault, conversion
proceeds as follows: [in is copied into P1; P1 copy to N1, but N1 still holds the constant
current Ix; P1 is copied to N2; P1 gets INI'I'INZ’ or Ix+lin; finally, the current held in P1 is
compared to [ref and the proper conversion bit results. Similarly, the S/OF F faulty switch
85 has the same fault effect When S7 is S/OFF, the transistor P1 cannot copy any current.

Thus, the constant current in P1 is compared to [ref for the output.

C. Type 3 Fault Effect

In the presence of S/ON faulty switch S3, conversion starts off with successfully
copying [in into P1; P1 into N1, and P1 into N2. Then, instead of copying [N 1+IN2 into P1,
N2 will source its current [in to the CMOS structure, comprised of P1 and N1, due to S3
being S/ON. Similarly, the S/ON faulty switch 85 has the same fault effect.

4.1.2.2 Test Generation and Fault Coverage

According to the fault effects discussed previously, in the presence of a Type I
fault, i.e., S/ON faulty switch S1, 82, or S4, or S/OFF faulty switch SI, 82, S4, or S6,
conversion results in a string of zeros. Thus, any nonzero input current can detect such a
fault. Similarly, in the presence of S/ON faulty switch 810 or S/OFF faulty switches S7 or
S 10, conversion results in a string of ones. Thus, a zero test current can detect the fault.

For Type 2 fault effect, in the presence of S/OF F faulty switch 83, the current held
in P1 is equal to Iin+lx’ where IR is a constant current held in N1. Thus, two test currents,
[in=0 and Inf, can detect such a fault. More specifically, for [in=0, during the MSB
conversion, the comparison of 11:1 (=Iin+1x=1x) and [ref generates a zero MSB except when
lx=lref. During the kth bit conversion, Ipl=klx generates a zero bit except for IX 2 [ref/k.
Hence the conversion of lin=0 generates at least one nonzero bit in the kth bit position. The
result of conversion follows the general patterns of 0...lxxx, and the first nonzero bit

detects the fault. On the other hand, for Iin: ref, the comparison of [p] (=Iin+]x= Iret‘I’IX)

F _ .. .ft'A‘n-n‘

105

and [ref leads to an MSB of l. The kth comparison involving lpl=klx and [ref produces a
one bit except 1x 5 [ref/k. Hence the result of conversion follows the patterns 1..0xxx and
the first occurrence of a zero bit detects the fault. This concludes that these two test currents
can detect the fault regardless of the value of Ix. Similarly, these two test currents can detect
the S/OF F fault on switch SS. Consider the presence of S/OFF faulty switch S7, the fault
effect shows that the constant currently held in P1 is bounded between 0 and 2 Iref. Thus.
the above two test currents can also detect the fault. More specifically, lin=0 and Iin: Im-
detect the fault in cases I), < [ref and 1y 2 Iref, respectively.

For Type 3 fault effect, in the presence of S/ON faulty switch S3, the transistor N2
will source its current Iin to the (Pl/N1) CMOS structure. This results in [pl-IN1=IN2=Iin,
where the values of [P1 and [N1 depend on the characteristics of the CMOS structure. For
example, based on the parameters given in the M0813 2um CMOS technology, when the
aspect ratios of P1 and N1 are lOum/Zttm and 4um/2ttm, respectively, PSpice simulation
results show that, for lin=0, the currents lpl=lNl=O. l483mA, and the current [p1 increases
as the positive current [in increases. Thus, the converted data will definitely include at least
a 1 in the presence of such a fault and the test current [in=0 detects the fault. Similarly. the
test current also detects the S/ON fault on switch S 5.

In summary, two test current Iin=0 and Iin= [ref can detect all S/ON and S/OF F

switches in the converter of Figure 4.3. Thus, the converter achieves full testability.

4.2 Testable Data-acquisition Circuits

Recently, with rapidly increasing complexity and size of modern electronic
systems, automatic testing and fault diagnosis of electronic circuits have become more
important and critical. Historically, analog circuits have been tested with the aid of a bed of
nails tester that allows one to make use of test data which is not accessible via the input and
output terminals of the circuit board, or chip. Howeverrthis is only pertinent to printed
circuit boards with discrete circuit design including some replaceable units, and it does not

apply to analog integrated circuits because only primary inputs and primary outputs are

'J.
7‘

 

 

106

accessible. Modern electronic systems are often multi—layered and/or coated, thereby
limiting the applicability of the bed of nails concept. As the number of components in a unit
increases, it is impractical to provide proportionately more I/O terminals. As a result.
various existing analog circuit test algorithms have suffered from the restriction of the
number and location of test points that must be externally accessible.

One approach to increasing the number of accessible nodes and thereby test points.
while still keeping low pin overhead, is to incorporate Built-In Self-Test (BIST) circuitry
into the unit under. test (UUT) during the initial design. The BIST design has been
successfully applied to the test of digital sequential circuits. With the BIST structure.
circuits that generate test patterns and analyze the output responses of the functional
circuitry are included on the same chip or elsewhere on the same board. In order to ensure
the reliability of the copied test data, it is necessary to check whether or not the BIST
structure is functioning properly before the structure is used. Thus, full testability of the
BIST structure is one of the most important issues in the BIST design. Due to the difficulty
of current measurement in an analog circuit, most of the fault diagnosis algorithms have
been developed requiring only node voltage measurement. However, it has been shown that
the use of both current and voltage measurement can simplify the diagnosis process
significantly. In order to allow the current test data measured at various test points to be

shifted out for fault diagnosis, a BIST structure has been implemented [41]. '

4.2.1 Built-In Self-Test Structures

The current-mode shift register described earlier can be used to sample and hold
current test data. Results show that the shift register circuit is self-testable and allows the
measured test data to be simultaneously loaded into the register cells and serially read out.
The study of the structure initially attempts to simplify the fault analysis process and
provides a possible BIST analog circuit design. :

Scan-in and scan-out terminals are added to the current-mode shift register to form

the BIST structure and make it testable as seen in Figure 4.4. Four test points, mi, are

107

 

UUT
m3

m2

m1

 

SP2

3%

Iin
Scan-In

 

ST3

sr2

 

srl

 

  

".---.....--....

...................

l

0----..ooonoooool

v

IIIIIIIIIIIIIIIIII

...‘O'...’..'...‘

V

llllllllllllllllll

.
o
o
o
.
.
o
o
.
.
.
.
.
f

l

.................

v

 

CSC#2 CSC#3 CSC#4

CSC#l

Figure 4.4 An BIST Structure Using Simple Current Copiers

108

assumed in the UUT and a 4-stage BIST structure is considered. The structure is operated
in two modes: the normal operation mode and the test mode. During the normal operation
mode, all switches SWi are OFF, disconnecting the current storage cells from the test
points. Thus, the BIST does not effect the functioning of the UUT. However, during the test
mode, the BIST comes into play and is utilized to carry out fault diagnosis. In this mode,
two operations can be identified. They are: the load/shift operation and the scan test
operation. The scan test operation is to ensure the reliability of the BIST structure while the
load/shift operation samples the current test data from the UUT. Since the BIST structure
is non—redundant, any fault is considered fatal and no further testing of the UUT is needed.

In order to ensure the reliability of the copied test data, it is necessary to check
whether or not the BIST structure is functioning properly before the structure is used for
the load/shift operation. The BIST structure is tested by the scan test operation which
includes the testing of switches SWi, SPi, STi, and SQi, and the storage cells.

The fault models considered in the BIST structure are the stuck-at fault for switches
and the functional fault for the storage cells. The stuck-at fault model assume that a switch
is either stuck-at-ON state or stuck-at-OF F state. The former, referred to as stuck-at-ON
fault, implies that a switch is always ON regardless of the application of controlled clock
signals, while the latter, referred to as stuck-at-OF F fault, indicates a switch is always OFF.
The ability of storing correct test data in the storage cell determines whether the cell is
functioning properly.

In order to ensure full testability of the BIST structure, the scan test operation
proceeds by first checking the switches SPi, STi, and SWi, and then testing the storage cells
and switches SQi. First, the switches SWi and STi are all OFF, and SPi are all ON,
expecting a current copied at the load to be exactly the same as the current sunk into the
scan-in portion if the switches are all fault-free. If any of the SWi are stuck-at-ON, the
corresponding input current, Ii, will also be sourced and the output current will be the
summation of this current and the scanned in current, [in-1 SPi being open or stuck-at-OFF
implies an open circuit in the scan path and lo“t will be zero. With any STi stuck-at-ON, the

respective NMOS copier will sink some current thus causing [out to be the difference of Iin

109

and the sunk current. Thus, passing this test implies that neither stuck-at-ON faults occur
in switches SWi and STi, nor stuck-at-OFF faults in SPi.

The storage cells, in general, can be tested by first loading test data from the scan-
in portion to each storage cell and comparing the copied and stored currents. More
specifically, turning on ST4 and switching off SP4 will load the test datum from the scan-
in portion into the storage cell CSC#4. Then, with SP3 and SQ4 OFF and SP4 ON, the
copied current is expected to be identical to the stored current. Passing this test implies that
the storage cell C SC#4 and switch SQ4 are functioning properly. Also, neither ST4 nor SP4
has a stuck-at-OFF fault implying that both the switches ST4 and SP4 are also functioning
properly. Once the components in the fourth stage are tested to be all reliable, they can be
used to test the third stage. The same test procedure can be carried out for the remaining
stages. In summary, passing the above tests will ensure that all components, except
switches SWi, are fault-free. However, it has been checked that no stuck-at-ON fault occurs
in SWi. So, there is only the need to test whether or not the switches have stuck-at-OFF
faults.

If a switch SWi has a stuck-at-OFF fault, no current will flow through the switch
and the current stored in CSC#i will be zero. On the other hand, if the current stored in
CSC#i is zero, three cases can be identified: (1) the current Ii is actually zero (or nearly
zero); (2) A faulty UUT induces [1:03 and (3) the switch SWi is stuck-at-OFF. Since cases
2 and 3 have already indicated the existence of fault, the remaining task is to distinguish
case 1 from others. This can be done by applying appropriate inputs to the UUT during the
test mode, (where the appropriate inputs are the ones which should generate a sufficiently
large current Ii if the UUT is fault-free). Since the current Ii will not be zero with the
appropriate inputs to the UUT, a zero current stored in C SC#i will indicate the existence of
a fault in case 2 or case 3.

Thus, the BIST structure is concluded to be fully testable. The load-shift operation
can then be carried out with this assurance. The sequence of steps for this mode is similar

to the current-mode shift register and is carried out in the same manner.

 

 

110.

As mentioned previously, there are several error effects that limit the accuracy of
the simple current-copiers and thereby that of the current retrieved. In order to avoid the
accumulation of offset errors and charge injection from the series switches SPi in Figure
4.4, an improved version of BIST structure is shown in Figure 4.5, where switches SPi are
the scan switches which form a demultiplexer circuit, while switches STi form a
multiplexer circuit for reading out the current test data. Both opamp and cascode current
copiers can reduce the errors due to the channel length modulation. The improved BIST
structures using such copiers may provide more accurate test data than that using the simple
copier, but they require more chip area to implement them. The improved copiers may be
used in cases where the original and copied currents must be matched precisely. In analog
circuit fault diagnosis, however, a “good” component value may deviate from its nominal
value within a predefined component tolerance. Thus, the test data obtained at various test
points may also deviate from the expected "nominal" values within a certain tolerance even
though the components are all good. Due to the inherent tolerance in analog circuits, precise
matching of the original and copied current is desirable, but not necessary. The trade-off
lies between precision and chip area. In principle, in cases where chip area is insignificant.
such as board testing, the improved BIST structures may be employed. However, for chip
testing, the BIST structure using the simple copier may be sufficient for fault diagnosis if

the copied current deviates from the. original current within 5 to 10 percent.
4.2.2 Experimental Results

Simulated verification of the design and operation of the BIST structure was done
using PSpice. Various switching faults were induced in a 4-stage BIST made up of active
copiers. Constant currents, Ii, were applied at the different test points as data from the UUT.
A scan-in current of 75uA was used and the tests were run at a cycle time of 4usec.

As the effect of a fault could cause bidirectional currents at the scan-out terminal, a

bipolar copier was implemented as the load. The scanned out current IO“t is thus given by

ll

1

 

 

 

 

 

 

Scan-out

 

Figure 4.5 An Improved BIST Structure with Active Current Copiers

ll2

Id(mnout)-Id(mpout). The current through SP0 is the current scanned in, I,n and through
SW, flow the currents, 1,.
I Figure 4.6 shows the results of some of the tests performed on this BIST structure.
Initially, a check is to be done for switches SP,, ST,, and SW,. With SW, and ST, open and
only SP, on, the output current must equal the current scanned in. This step is verified in
the first cycle of Figure 4.6, where there were no faults in the BIST and thus [0,,t is
approximately 75uA. For a second test run, SP, have to be verified to be not stuck-at-OFF.
For example, when one of the pass switches SP2 is stuck-at-OFF. it causes an open circuit
and so 10,,t = 0 at I,n and the BIST output during the second cycle of Figure 4.6 indicates
that a fault has occurred. The next check is to verify that all the SW, are open. SW3 stuck-
at-ON implies that [3 will also combine with the scan-in current As seen in the third cycle
Figure 4.6, the current through switch SW3 which is equal to SOuA‘ adds with l,n =75ttA
and results in output of lZStrA. Again the BIST successfully detected the fault. To check
the stuck-at-ON faults on the ST,, a charge of approximately 2.75Volts on the capacitor C4
will cause the NMOS transistor in CSC#4 to sink lOOuA of current. Consequently with ST4
stuck-at-ON, 10,,t = I,n - I(st4) and a negative current of -25uA is read out as seen in the last
cycle of Figure 4.6. The bipolar copier load thus helps check the reliability of the BIST

SU’UCIUI‘C.
4.3 Summary

This chapter has presented a novel current-mode A/D converter design with time
redundant CED capability. A slight addition in hardware of a PMOS copier is all that is
required to make the validation of the converted data more reliable. The design can detect
all transient faults that occur at the switching elements and most of the permanent faults.
Some permanent faults cannot be detected due to the unavailability of test patterns for real-
time applications. However, the same structure can be tested off-line with only two test

patterns and this is described in the test generation process of the current-mode A/D

 

 

 

lSOuA

OA
lOOuA

0A
lSOuA

OA
lSOuA

-50uA

H3

BIST structure with active current copiers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

74.952u 74.936u 74.972u I
1’ A: h /’
203.ll3n[ H
7 /
DIISpOI
50.033u
(V J
DI<SW3I
100.338u 1
I / I
eI(st4)
7 .1 2 <\
5135 u 125.119u
l75;§56n -25.l42u
s 4us 8h l2us 16us 20us
cID(mnout)+ ID(mpout ,
. Tlme

Figure 4.6 BIST Tests for Various Faults

ll4

converter. With the application of only two test signals, the converter achieves full
testability of single stuck-at faults at the switching elements.

In the past, analog circuit fault diagnosis algorithms that have been developed were
restricted for use only on small-scale networks due to the limited number of available test
points and have strictly used voltage test samples. The analog BIST structure presented in
this chapter increases the accessible nodes through scan terminals and utilizes current test
data thus making fault diagnosis and testing much simpler. The BIST structure can be
perfectly employed for testing mixed analog/digital circuits and can be incorporated into an

analog function or module design.

Chapter 5

Conclusions

 

As pressure increases on VLSI designers to use a lower supply voltage, analog
circuits operating in the voltage domain will suffer and circuits designed to exploit current-
mode techniques will surely become increasingly important and attractive [8]. All too often
the electronics engineer will think in voltage terms rather than current simply because of
the unavailability of current-mode signal processing circuits [3]. The primary goal of this
dissertation has been to develop a gamut of current-mode data-acquisition and conversion
circuits. This chapter describes the major contributions of this research and addresses some

potential problems for further investigation.
5.1 Summary

In this research, a set of new circuits, such as bipolar copiers, current-mode shift
registers and current-mode dividers have been presented for the design of current-mode A/
D converters and their array structures.

The bipolar copier which is a very useful building block in the design of current-
mode data-acquisition and conversion circuits has been presented. This copier can
precisely memorize input current which is either positive or negative. Its bidirectional
capability makes it an important element in general purpose multipliers and dividers. It
forms an integral part of a current divider that generates reference current levels for a

successive-approximation A/D converter. In analog fault diagnosis with current data, a

ll6

malfunction in a circuit may cause currents to be of any polarity. Thus, the need for a circuit
that can sense bidirectional current arises. This necessity can be satisfied by the bipolar
copier which can then be used as a load to sense the current test data. The use of this copier
in these applications has also been demonstrated.

A current-mode shift register has been developed to copy currents. This shift
register can be used to load sensory information for signal processing and can be arranged
to exploit the parallelism of array structures. Although the shift-register is similar to an
analog multiplexer circuit, its structure indicates that it can be easily adapted to obtain a
possible analog BIST circuit design for current test data. This was possible by the use of an
additional scan-in terminal for self-testability which allows the structure to detect any
faults, either stuck-at faults at switching elements, or functional faults in the storage cells.
Both the shift register and its BIST implementation have been simulated to verify their
operation principle.

According to the switching operation of the current-mode shift register circuit the
data held at the first stage will be read out last For this reason, the criterion to determine
the optimal number of stages for the shift register structure given the precision of the
measurement has been developed. The reduction in the number of stages can be achieved
by increasing the number of scan paths and forming a parallel structure in which several
shift registers can be arranged in rows. Thus, instead of having a long sequential chain,
several short serial segments can be operated in parallel.

Current dividers are important signal processing elements but have been limited in
their accuracy by device mismatch. This dissertation has presented a highly accurate
current-mode divide-by-two circuit that does not require well-matched components or a
high gain opamp. The circuit allows any mismatch factors between the divider transistors
through its use of the bipolar copier. The current-mode divider circuit has been
implemented as the reference-generating (RG) circuit of the current-mode A/D converter.
The number of iterations required for the divide-by-tWo circuit to obtain the desired

accuracy has been formulated and its performance has been assessed through simulations.

117

This dissertation has also presented a successive-approximation current-mode A/D
converter that functions through a divide-by-two scheme. The circuit does not rely on high
gain amplifiers or well-matched components to achieve high resolution and is inherently
insensitive to the amplifier's offset voltage. For the practical 1% mismatch between the
divider transistors of the RG circuit, 5 clock cycles are required to generate each reference
level. In general, the converting (CV) circuit of the A/D converter may require only two or
three cycles. Thus, the slower RG circuit may degrade the conversion rate. In practice.
however, a common RG unit may be shared by several CVs to simultaneously convert
several analog data. Based on this idea, the converter deSign has been modified to obtain a
parallel A/D converter with a common RG circuit to achieve a higher conversion rate. The
array structure has been designed such that several functional units are time shared thus
utilizing minimum hardware. Results show that the array structure achieves high resolution
and high conversion rate at a very low hardware cost.

In order to improve the reliability of data validation for real-time operations, this
paper presents a novel current-mode A/D converter design with CED capability, where a
time redundant scheme is implemented. The original A/D converter with the addition of
only a PMOS current copier provides CED capability improving its reliability. The design
can detect all transient faults that occur at the switching elements and most of the
permanent faults. Some pernianent faults cannot be detected due to the unavailability of test
patterns for real-time applications. To satisfy this need and to enable off-line testing, test
generation of the current-mode A/D converter has also been demonstrated. With the
application of only two test signals, the converter achieves full testability of single faults at
the switching elements. Therefore, as permanent faults can be fully testable by these two
test patterns it is suggested to randomly apply the two test signals to the A/D converter
detecting the permanent faults during real-time operation.

The drawback of this design with CED capability is approximately 100% overhead
in time which is inherent in all time redundancy schemes. Judging from the VLSI
performance measure of ATk (where A is the chip area, T is the operation cycle time, and

k is a parameter determined by the applications), this is rather a high price to pay

118

particularly when k is increased. However, the performance penalty associated with time
redundancy can be absorbed by the inherent idleness of the processing element This design
can be effectively applied to those systems or subsystems in which the time to process the
converted data is as much as twice of the conversion time. The other salient feature is that
the design allows users to easily switch between an A/D converter with and one without
CED capability without causing any performance degradation.

To alleviate the problem of limited number of available test points for fault
diagnosis of analog circuits, analog Built-In Self-Test (BIST) structures have been
implemented in this dissertation. These structures provide more test points, while still
keeping low pin overhead, for analog fault diagnosis with current test data and voltage test
data. With both BIST structures, fault diagnosis and testing of analog circuits will become
simpler. In addition, these structures also provide an innovative feature that allows
designers to use one channel of an oscilloscope to simultaneously monitor multiple output
waveforms of analog circuits or systems. The BIST structures are perfectly employed for
fault diagnosis and testing of mixed analog/digital circuits and can be incorporated into an
analog function or module design. In addition, it is better off to include an A/D converter
into the analog module so that the test outputs of the analog module are in digital form. The
digital data obtained from the digital modules and the analog modules are then processed

by a simple microprocessor for fault diagnosis and testing.

5.2 Contributions

The major contributions of this research are described as follows.

(1) This dissertation has successfully developed, analyzed and constructed current-
mode signal processing circuits that include bipolar copiers, current-mode shift registers,
current-mode dividers, A/D converters and converter arrays.

(2) In this study, diagnosable circuit design methodologies have been applied to

current-mode data-acquisition and conversion circuits in order to enhance their reliability.

119.

(3) The investigation of some practical design issues through simulations. to assess
the performance of the architectures presented has also been carried out.

(4) This research has also investigated the design trade-offs and developed a design
strategy to provide an optimal solution for the integration of the current-mode circuits with

IC sensor arrays.
5.3 Future Research

For the design of these analog signal processing circuits, it is essential to apply
MOS technology to the single chip implementation of analog and digital circuits. As both
the digital control units and the analog interface systems such as the A/D converters.
sample-and-hold elements have to be implemented on the same chip, there has to be an
automated design tool to cope with the complexity of building such large scale mixed mode
circuits. The performance specifications for the analog building blocks are more
complicated that the digital ones. Thus, a topology and layout for the A/D converter for the
given specifications has to be chosen. The device sizes and currents have to be adjusted to
satisfy performance criteria such as power dissipation, bandwidth, sampling rate, settling
time, area, etc. It is the future intent of this research, to develop a methodology for a design
and layout tool that optimizes the design and performance of these current-mode signal
processing circuits.

Current copier cells are controlled by digital clock signals. The potential crosstalk
problem of digital noise finds its way into sensitive analog circuitry [47]. Although the
problem can be handled effectively by judicious use of multiple power bussing and
desensitized analog circuitry, the noise problem will worsen in the future as digital speeds
will increase, additional analog circuitry will be included, chips will become more densely
packed, interconnect layers will be added, and analog resolution will be increased. A
number of possible sources of performance degradation in mixed analog/digital ICs have
been identified: signal coupling through the substrate, coupling through parasitic wiring

capacitance, and coupling the IR drops in the power distribution network [47]. However,

l 20

quantitatively modeling and simulating these effects is extremely difficult. Therefore, these
dominant error sources and the limitations they impose on the performance of the various
current-mode signal processing circuits have to be assessed. Therefore, it is also necessary
to develop in the automated tool a method for designing such mixed analog/digital current-
mode circuits so that alternative circuit structures for various design variations can be
investigated.

Integration of sensing and processing on chip yields a qualitative improvement in
performance. Thus, the shift registers and the converter array can be integrated along with
an array of sensors. Recently, a smart sensor array has been implemented for a light-stripe
rangefinding system, where each pixel contains a photodiode to detect the light stripe and
an analog signal processor to determine and store the time at which the light stripe crosses
that photodiode [48]. For the current-mode data-acquisition and conversion circuits
developed and analyzed, the demonstration of integrating these circuits with an IC sensor
array can be conducted. Figure 5.1 illustrates a possible implementation of the current-
mode A/D converter array in a sensor array [49]. The architecture is comprised of a sensor
array, current-mode analog shift registers, a current-mode A/D converter array with a
common RG circuit, and a set of high speed digital shift registers. The sensory
information is sampled row-wise into a set of current-mode shift registers and is then
shifted out serially to a channel _of the current-mode A/D converter array. These
independent signals sources are processed through the same converter or communications
channel and so a multiplexer is usually introduced to couple the. input signals into A/ D
converter in some sequence. Additional switching logic can keep track of which data
source is coupled to the converter at any instant. After the conversion, multiplexers can
then output, one at a time, the converted data from the array, to common digital shift
registers. The current-mode shift registers can be arranged more efficiently to exploit the
parallelism in the array structure and to have more accurate sampling. To reduce the
hardware cost, the array structure shares resources and alternately processes data in the
CCVo and CCVe circuits. Apparently, the hardware reduction is achieved at the cost of

performance of the sensory structure. Future study can explore the advantages and

121

c-cocoooovvocvOOODOOOODUOOOOOO

 

Shift Register

 

Digital

 

 

 

 

 

 

3532524

 

 

 

5.83222

 

 

 

tartar ..........................

 

 

  

 

 

353252

 

 

 

 

RG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CCV .

---CO-----.C.-.‘........-.O.....OOOJ

9‘F'Il""""""'I”"""'-' ""-""""""""“ """"""""""""""""""""""""

Sensors

 

 

Analog Shift Register

Current-Mode

 

 

Figure 5.1 A Sensor Array Implementation

122

disadvantage of implementing such structures and identify their best applications. An
arbitrary IC sensor array may be used to demonstrate the practicality and resulting
improvement in using these current-mode circuits.

As the copiers may be used as sample-and-hold elements to read data from sensors.
their operation under changing sensory conditions should be investigated. As temperature
sensing is an important application, PSpice simulations were run at different temperatures
on the simple bipolar copier copying positive current of 50uA. Results show that the copier
functions correctly, but its accuracy varies with temperature as shown in Figure 5.2. This
variation is mainly due to the dependence of certain parameters, such as transconductance
( k' ), bulk p-n saturation current (IS), junction capacitances, and several others on
temperature. One primary error source of the copier, leakage current, thus varies with
temperature. Other sources of error and factors that come into play at different temperatures
are also to be investigated.

For the diagnosable design of the current-mode circuits, the fault model considered
in this study was the single-stuck at fault in the switching elements. Although this fault was
focussed on, the faults that occur in other elements can be modeled as the equivalent faults
of the switching elements. This leads to an interesting area for future study. Also the
concurrent error detection time redundancy scheme was Alternating Logic. Some
interesting prospects of better fault coverage may be obtained by the use of the RESO
(REcomputing with Shifted Operands) scheme. Shifting in the analog world would mean
multiply or divide the signal by two. As both the multiplier and the divider circuits are

available in current-mode, this method could also be implemented in the future.

Percentage Error

123

Bipolar Copier Operation at Different Temperatures

 

 

 

 

4 , , T r —7 r
3- .
2- 4
1- -
0- _
-1_ e
-2? _.
_3_ 4
-4 1 1 l l L 1
-SS -25 O ‘27 75 125
Temperature

Figure 5.2 Temperature Dependence of Bipolar Copier Operation

APPENDICES

Appendix A
A CMOS Opamp

 

The operational amplifier used for the simulations is a two-stage, N-channel input,
unbuffered CMOS opamp, as shown in Figure A.l, where compensation is achieved
through resistor, rz, and capacitor, cc. The simulated characteristics of the operational
amplifier are given in Table A. 1.

Von

M3
E rbias
M1

'—| .
in a M7
1,

Figure A.l A Two-stage CMOS Opamp

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SS

124

125

Table A.l Simulated Characteristics of Opamp

Design Specification I Simulation Result

Supply Voltage l 5 V olts
Open Loop Gain I 44.18 dB
94°

 

     

 

 

Phase Margin
(Load Capacitance=lOpF)

Gain Bandwidth Product | 3.58 MHz

 

 

(Load Capacitance=lOpF)

 

Output Resistance I 5.77KQ
Input Resistance I leQ

Slew Rate 1 9.556 (+) V/ttsec
(Load Capacitance=lOpF) 7.567 (-) V/ 1186C

Input Offset Voltage I 1.46mV
Input CMR I +4.47v, -5v
Output Voltage Range | +4.924v, -5v

 

 

 

 

 

 

 

Power Dissipation I 1.91 mW

Appendix B

PSpice Files

 

 

mos.|ib

* parameters: MOSIS 2 micron CMOS process on Oct.3. 1990

.model nmos nmoslevel=21d=0.25u vto=.771327 kp=56.06u gamma=.53 phi=.6
+ lambda=.030894 rsh=29.6 cj=113.65u cjsw=531.87p mj=.6862 mjsw=.2651

+ cgso=322.9249p cgdo=322.9249p cgbo=672.6429p nsub=6.257042e+15

+ nss=l0.0e+9 nfs=4.834708e+12 tox=40.ln xj=0.25u uo=650.996

+ ucrit=41.9315e+3 uexp=.153507 vmax=67.6608e+3 delta=.472546

.model pmos pmos level=2 tpg=-1 ld=0.20961u vto=-.78821 kp=22.3u gamma=.5486
+ phi=.6 lambda=.049817 rsh=90.7 cj=251.36u cjsw=294.47p m j=.5471

+ mjsw=.3 188 cgso=270.7532p cgdo=270.7532p cgbo=583.9625p

+ nsub=6.722092e+15 nss=10.0e+9 nfs=0.le+12 tox=40. 1n xj=0.25u uo=259

+ ucrit=l2.5945e+3 uexp=.l82346 vmax=41.2226e+3 neff=l.001 delta=.844423

CMOS opamp with lead compensation
.subckt opamp 1 2 6 100 101

* + - o +p -p

ml 4 2 3 3 nmos w=10u 1: 2n

m2 513 3 nmos w=10u 1= 2u

m3 4 4 100 100 pmos w=20u 1= 2n
m4 5 4 100 100 pmos w=20u 1: 2n
m5 3 7 101 101 nmos w=2u 1: 2n-
m6 6 5 100 100 pmos w=76u 1: 2n
m7 6 7 101 101 nmos w=4u 1: 2n
m8 8 7 101 101 nmos w=2u 1: 2n
rz 5 9 7.28K

cc 9 6 5p

rbias 100 8 158K

rsc 7 8 l

.LIB mos.|ib

.ends

A CMOS switch

.subckt msw 210 212 213

* In Out Ctrl

vdd 25 0 5

vss 24 0 0

ml 210 211212 25 pmos w=5u l=2u
m2 210 213 212 24 nmos w=2u l=2u
m3 211 213 25 25 pmos w=2u l=2u
m4 211 213 24 24 nmos w=2u1=2u
.LIB mos.|ib

.ends

 

 

 

126

I27

 

Bipolar current copier
* Copying positive current

* The power supplies

vdd 10 0 5

vss 9 0 0

*The input

mll 101 101 1010pmos w=5u l=2u
m12 102 101 10 10 pmos w=5u l=2u
i1 101 0 50o

xsw 102 ll 1w msw

vsc 11 l O

* The bipolar copier

mp1 3 4 10 10 pmos w=5u l=2u
mnl 3 4 9 9 nmos w=2u l=2u

cpl 4 9 10p

st 1 3 1t 0 sw

sq 3 4 lq 0 sw

* The output stage

mpout 7 8 10 10 pmos w=5u l=2u
cpout 8 10 4p

stout l 7 2t 0 sw

sqout 7 8 2q 0 sw

*Digital waveforms for switching

U1 STIM(3. 111) $G_DPWR $G_DGND 1w 1t lq
+ IO_STM TIMESTEP = 0.2us

+Label = startl

+ 0c 111

+ 4c 110

+ SC 010

+ 10c 000

+ +5c GOTO startl 5 times

Uout STIM(Z, 11) $G_DPWR $G_DGND 2t 2q
+ IO_STM TIMESTEP = 0.2us

+Labe1= startl

+ 0c 00

+ 5c 11

+ 9c 10

+ 10c 00

+ +5c GOTO startl 5 times

.model sw vswitch(ron=10 roff=100e+6 von=5
voff=0)

.LIB mos.|ib

.LIB sw.lib

.LIB digital.lib

.tran 0.01u 2n Ou 0.01u UIC

.IC v(4)=0.0 v(8)=0.0

.probe

.end

 

 

Bipolar current copier
* Copying negative current

* The power supplies

vdd 10 0 5

vss 9 0 0

*The input

mll 101 1019 9 nmos w=5u l=2u
m12 102 101 9 9 nmos w=5u l=2u
i1 10 101 50u

xsw 10211 1w msw

vsc 11 1 0

* The bipolar copier

mp1 3 4 10 10 pmos w=5u l=2u
mnl 3 4 9 9 nmos w=2u l=2u

cpl 4 9 10p

st 1 3 1t 0 sw

sq 3 4 1q 0 sw

* The output stage

mnout 7 8 9 9 nmos w=5u l=2u
cnout 8 9 4p

stout 1 7 2t 0 sw

sqout 7 8 2q 0 sw

*Digital waveforms for switching

U1 STIM(3. 111) $G_DPWR $G_DGND 1w 1t lq
+ IO_STM TIMESTEP = 0.2us

+I..abel = startl

+ DC 111

+ 4c 110

+ SC 010

+ ICC 000

+ +5c GOTO startl 5 times

Uout STIM(2, 11) $G_DPWR $G_DGND 2t 2q
+ IO_STM TIMESTEP = 0.2us

+I..abel = startl

+ 0c 00

+ 5c 11

+ 9c 10

+ 10c 00

+ +5c GOTO startl 5 times

.model sw vswitch(ron=10 roff=100e+6 von= 5
voff=0)

.LIB mos.lib

.LIB sw.lib

.LIB digital.lib

.tran 0.01u 2u Ou 0.01u UIC

.IC v(4)=0.0 v(8)=0.0

.probe

 

.end

 

 

 

 

Current-mode Shift register
* Four stages with active current copiers

* The power supplies
vp+ 110 0 5

vp- 90 0 -5

vdd 100 0 5

vss 9 0 0

vbias 108 0 2.5

*The firstcell

il.010150u

r1010100K

swl 1011 1w05w

ml 12 l399nmos w=2u l=2u
cl 139100p

stl ll 121t03w

sql 1413 lquw

spl 1121 lpOsw
x11110814110900pamp

*The second cell

i2 0 20 50u

r2 0 20 100K

sw2 20 21 2w 0 sw

m2 22 23 9 9 nmos w=2u l=2u
c2 23 9 100p

st2 21 22 2t 0 sw

sq2 24 23 2q 0 sw

sp2 21 31 2p 0 sw

x2 21 108 24110 90 opamp

* The third cell

i3 0 30 75a

r3 0 30 100K

sw3 30 31 3w0sw .
m3 32 33 9 9 nmos w=2u l=2u
c3 33 9 100p

st3 3132 3t05w

sq3 34 33 3q 0 sw

sp3 31413p05w

x3 31 108 34110 90 opamp

* The fourth cell

i4040125u

r4040100K

SW4 40414WOSW

m4 42 43 9 9 nmos w=2u l=2u '
c4 43 9100p

st4 41 42 4t05w

sq44443 4q05w

sp441514p Osw

x441 10844 110 90 opamp

128

 

 

 

* The output stage

mpout 51 53 100 100 pmos w=5u l=2u
com 53 100 10p

sqout 54 53 Sq 0 sw

x5 51108 54110 90 opamp

*Digital waveforms for switching

U1 STIM(4. 1111) $G_DPWR $G_DGND 1w 1t lq 1p
+ IO_STM TIMESTEP = lus

+Label = startl

+0c 1110

+4c 1100

+ 5c 0000

+ 20c 0101

+ 25c 0001

+ +5c GOTO startl 5 times

U2 STIM(4, llll) $G_DPWR $G_DGND 2w 2t 2q 2p '
+ IO_STM TIMESTEP = lus
+Label = start2

+ 0c 1110

+ 4c 1100

+ 5c 0000

+ 15c 0101

+ 20c 0001

+ +10c GOTO start2 5 times

U3 STIM(4, 1111) $G_DPWR $G_DGND 3w 3t 3q 3p
+ IO_STM TIMESTEP = lus

+Label = start3

+ 0c 1110

+ 4c 1100

+ 5c 0000

+ 10c 0101

+ 15c 0001

+ +15c GOTO start3 5 times

U4 STIM(4, 1111) $G_DPWR $G_DGND 4w 4t 4q 4p
+ IO_STM TIMESTEP = lus

+Label = start4

+ 0c 1110

+ 4c 1100

+ 5c 0101

+ 10c 0001

+ +20c GOTO start4 5 times

U5 STIM(l, 1) $G_DPWR $G_DGND Sq
+ IO_STM TIMESTEP = lus

+Label = starts

+ 0c 0

+ 5c 1

+ 9c 0

 

 

 

 

129’

 

+14c0
+15c1
+19c0
+20c1
+24c0
+ +6c GOTO start5 5 times

.model sw vswitch(ron=10 roff=100e+6
+von=5 voff:0)

.LIB mos.lib

.LIB opamp.lib

.LIB digital.lib

.tran 0.005u 25u Ou 0.005u UIC

.IC v(13)=0 v(23)=0 v(33)=0 v(43)=0
.probe

.end

Current-mode Divider
*(W/L)2 > (W/L)3 : 5% mismatch

* The power supplies
vp+ 100 0 5

vp- 90 0 -5

vdd 110 0 5

vss 109 0 0

* The input stage
iin 0 101 125u

rin 0 101 100K
st 101 10 1v 0 sw

* The error corrector stage - mp1 and mnl

swl 101 110 sw

sw2 107 2 12 0 sw

mnl 1 2 109 109 nmos w=2u l=2u
mp1 1 2 110 110 pmos w=5u l=2u
c12 109 40p

* The divider stage

* The nmos stage - m2

sw3 10 3 13 0 sw

sw4 107 4 14 0 sw

m2 3 4 109 109 nmos w=2.2u l=2u
c2 4 109 40p

* The nmos stage - m3

sw5 10 5 15 0 sw

sw6 107 6 l6 0 sw

m3 5 6 109 109 nmos w=2u l=2u
c3 6 109 40p

 

 

* The pmos stage - m4

sw7 10 7 17 0 sw

sw8107 818 0 sw

m4 7 8 110 110 pmos w=5u l=5u
c4 8 110 40p

* The opamp stage

x100 10 108 107 100 90 opamp
vbias 108 0 2.5

* Digital waveforms for switching

Uin STIM(l, l) $G_DPWR $G_DGND 1v
+ IO_STM TIMESTEP = 0.6us

+Label = instart

+ 0c 1

+ 5c 0

+ +10c GOTO instart 5 times

Ucmos STIM(2, 11) $G_DPWR $G_DGND 11 12
+ IO_STM TIMESTEP = 0.6us

+ 0c 00

+Label = cstart

+ 10c 11

+ 14c 10

+ 20c 00

+ +5c GOTO cstart 5 times

Unmos STIM(4. 1111) $G_DPWR $G_DGND 13 14 15 16
+ IO_STM TIMESTEP = 0.6us

+Label = nstart

+ 0c 1111

+ 4c 1010

+ 5c 0010

+ 10c 1000

+ +5c GOTO nstart 5 times

Upmos STIM(2, ll) $G_DPWR $G_DGND 17 18
+ IO_STM TIMESTEP = 0.6us

+ 0c 00

+Label = refstart

+ 5c 11

+ 9c 10

+ 15c 00

+ +5c GOTO refstart 5 times

.model sw vswitch(ron=10 rofl'=100e+6 von=5 voff=0)
LIB mos.|ib

LIB opamp.lib

.LIB digital.lib

.tran 0.01u 72u Ou 0.01u UIC

.IC v(2)=0.0 v(4)=0.0 v(6)=0.0 v(8)=0.0

.probe

.end

 

 

LIST OF REFERENCES

[1]

[2]

[3]

[41

[5]

[6]

[7]

[8]

[9]

[10]

[11]

LIST OF REFERENCES

Toumazou, C., F. J. Lidgey. and D. G. Haigh, Analogue IC design: the current-mode
approach, Peter Peregrinus Ltd., London, United Kingdom, June 1990.

Hughes, J. B., N. C. Bird, and I. C. Macbeth, “Switched Currents - A New Technique
for Analog Sampled-Data Signal Processing,” Proceedings of the International
Symposium on Circuits and Systems, pp. 1584-1587, 1989.

Toumazou, C., J. Lidgey, and B. \Vrlson, "Current-mode Analog Signal Processing,"
IEE Proceedings, Vol. 137, Part G, pp. 61—62, April 1990.

Tisividis, Y. P., "Analog MOS Integrated Circuits - Certain New Ideas, Trends, and
Obstacles," IEEE Journal of Solid-State Circuits, Vol. SC-22, pp. 317-321, June
1987. '

Poujois, R., B. Baylac, D. Barbier, and J. M. Ittel, "Low-level MOS Transistor
Amplifier Using Storage Elements," IEEE ISSCC Dig. Tech. papers, pp. 152-153,
1973.

Tisvidis, Y. P., M. Banu, and J. F. Khoury, "Continuous-time MOSFET-C Filters in
VLSI," IEEE Journal of Solid-State Circuits, Vol. SC-21, pp. 15-30, February 1986.

Yung, H. T., and K. S. Chao, "An Error-Compensation A/D Conversion Technique,"
IEEE Transactions on Circuits and Systems, Vol. 38, pp. 187-195, February 1991.

Wilson., B., "Recent Developments in Current Conveyors and Current-Mode
Circuits," IEE Proceedings, Vol. 137, Part G., No. 2, pp. 63-77, April 1990.

Naim, D. G., and C. A. T. Salama, "Current Mode Analog-to-digital Converters."
Proceedings of the International Symposium on Circuits and Systems, pp. 1588- l 59 l ,
1989.

Lee, S.-S., R. H. Zele, D. J. Allsot, and G. Liang, “A CMOS Continuous-Time
Current-Mode Filter Technique”, Proceedings of the International Symposium on
Circuits and Systems, pp. 2021-2024, 1992.

Crawley, P. J., and G. W. Roberts, “Predicting Harmonic Distortion in Switched—

Current Memory Circuits”, Proceedings of the International Symposium on Circuits
and Systems, pp. 1243-1246, 1993.

130

 

[12]

[13]

[141

[15]

[16]

[17]

[18]

[19]

[20]

[21]

[22]

[23]

[24]

131

Gilbert, B., “A New “ride-Band Amplifier Technique,” IEEE Journal of Solid State
Circuits, Vol. 803, pp. 353-365, 1968.

Nairn, D. G., and C. A. T. Salama, "A Ratio-Independent Algorithmic Analog-to
digital Converter Combining Current Mode and Dynamic Techniques," IEEE
Transactions on Circuits and Systems, Vol. 37, pp. 319-325, March 1990.

Middelhoek, S., and S. A. Audet, Silicon Sensors, Academic Press, 1989.

Krenik, W. R., R. K. Hester, and R. D. DeGroat, “Current-Mode A/D Conversion
Based on Current Splitting Techniques”, Proceedings of the International Symposium
on Circuits and Systems, pp. 585-588. 1992.

Carley, L. R., and T. Kanade, "A Three Dimension Imaging System Integrating
Parallel Analog Signal Processing and IC Sensors," Technical Report, Department of
Electrical and Computer Engineering, Carnegie Mellon University, 1991.

Chen, K., and C. Svensson, "A Parallel A/D Converter Array Structure with Common

Reference Processing Units," IEEE Transactions on Circuits and Systems, Vol. 36.
pp. 1116-1119, August 1989.

Analog Devices, Analog -Digital Conversion Handbook, Prentice Hall, Englewood
Cliffs, N.J., 1986.

Abraham, J. A., and V. K. Agarwal, "Test generation for digital systems," in Fault-
tolerant C omputing, Theory and Techniques, edited by D.K. Pradhan, Prentice-Hall,
Englewood Cliffs, N.J., 1986.

Johnson, B. W., Design and Analysis of Fault Tolerant Digital Systems, Addison
Wesley, 1989.

Patel, J. H., and L. Y. Fung, "Concurrent error detection in ALUs by recomputing
with shifted operands," IEEE Transactions on Computers, Vol. C-31, pp. 589-595,
July 1982.

Wey, C. L., "Concurrent Error Detection in Array Dividers by Alternating Input
Data," Proceedings of the International Conference on Computer Design: VLSI in
Computers & Processors, pp. 114-117, October 1991.

Bandler, J. W., and A. E. Salama, "Fault Diagnosis of Analog Circuits," IEEE
Proceedings, pp. 1279-1325, August 1985.

Liu, R.-W., Analog Fault Diagnosis, IEEE PRESS, 1988.

 

[25]

[26]

[27]

[28]

[29]
[30]
[31]
[32]
[33]

[34]

[35]
I361

[37]

132

Liu, R.-W., Testing and Diagnosis of Analog Circuits and Systems, Van Nostrand
Reinhold, 1991.

Jiang, B. L., and C. L. Wey, "Fault Prediction Process for Large Analog Circuit
Networks," International Journal of Circuit Theory and Application, Vol. 17. pp.
141-149, April 1989.

Wey, C. L., and R. Saeks, "On the Implementation of an Analog ATPG: The Linear
Case", IEEE Transactions on Instrumentation and Measurement, Vol. IM- 34, pp.
277-284, September 1985.

Wey, C. L., and R. Saeks, "On the Implementation of an Analog ATPG: The
Nonlinear Case", IEEE Transactions on Instrumentation and Measurement, Vol. IM-
37, No. 2, pp. 252-258, June 1988.

Unbehauen, R., and A. Cichocki, MOS Switched-Capacitor and Continuous-Time.
integrated Circuits and Systems, Springer-Verlag Berlin Heidelberg, 1989

Allen, P. E., and D. R. Holberg, CMOS Analog Circuit Design, Holt, Rinehart and
Winston, Inc., 1987.

Geiger, R. L., P. E. Allen, and N. R. Strader, VLSI Design Techniques For Analog and
Digital Circuits, McGraw-Hill Publishing Company, 1990

Daubert, S. J., and D. Vallancourt, "Operation and Analysis of Current Copier
Circuits," IEE Proceedings, Vol. 137, Part G., pp. 109-115, April 1990.

Daubert, S. J ., D. Vallancourt, and Y. P. Tsividis, "Current Copier Cells," Electronics
Letters, Vol. 24, No. 25, pp. 1560-1562, December 1988.

Vallancourt, D., Y. P. Tsividis, and S. J. Daubert, "Sampled-Current Circuits,"
Proceedings of the International Symposium on Circuits and Systems, pp. 1592- 1595,
1989.

Robert, J ., P. Deval, and G. Wegmann, "Very Accurate Current Divider," Electronics
Letters, Vol. 25, No. 14, pp. 912-913, July 1989.

Lala, P. K., Fault Tolerant and Fault Testable Hardware Design, Prentice-Hall
International, 1985.

Chan, S.-W., and C. L. Wey, "The Design of Concurrent Error Diagnosable Systolic
Arrays for Band-Matrix Multiplication," IEEE Transactions on CAD of Integrated
Circuits and Systems, Vol. CAD-7, No. 1, pp. 21-37, January 1988.

[38]

[39]

[40]

[41]

[42]

[43]

[44]

[451

[461

[47]

[48]

[49]

133

Reynolds, D. A., and G. Metze, "Fault Detection Capabilities of Alternating Logics,"
IEEE Transactions on Computers, Vol. C-27, pp. 1093-1098, December 1978.

Wegmann, G., and E. A. Vittoz, "Very Accurate Dynamic Current Mirrors."
Electronics Letters, Vol. 25, No. 10, pp. 644-646, May 1989.

Sahli, S., Test Generation and Concurrent Error Detection in Current-Mode A/D
Converters, MS. Thesis, Michigan State University, December 1992.

Wey, C. L., and S. Krishnan, "Built-In Self-Test (BIST) Structures for Analog Circuit
Fault Diagnosis with Current Test Data," IEEE Transactions onlntrumentation and
Measurement, Vol. 41, No. 4, pp. 535-539, August 1992.

Wey, C. L., and S. Krishnan, "A Current-mode Divide-by-two Circuit," Electronics
Letters, Vol. 28, No. 9, pp. 820-822, May 1992.

Krishnan, S., and C. L. Wey, "An Accurate Reference-generating Circuit for
Successive-approximation Current-mode A/D Converters " accepted to appear in the
International Journal of Circuit Theory and Applications.

Krishnan, S., S. Sahli, and C. L. Wey, "Test Generation and Concurrent Error
Detection in Current-Mode A/D converters," Proceedings of the IEEE International
Test Conference, pp. 312- 320, September 1992.

Sahli, S., S. Krishnan, and C. L. Wey, "Design of Concurrent Error Detectable
Current-Mode A/D converters," Proceedings of the International Conference on
Microelectronics, Tunisia, December 1992.

Wey, C. L., S. Krishnan, and S. Sahli, "Design of Concurrent Error Detectable
Current-Mode A/D converters for Real-time Applications," accepted to appear in
Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers.

Olmstead, J. A., and S. Vulih, "Noise Problems in Mixed Analog-Digital Integrated
Circuits," IEEE Custom Integrated Circuits Conference, pp. 659- 662, May 1987.

Gruss, A., Carley, L. R., and T. Kanade, "Integrated Sensor and Range-Finding
Analog Signal Processor," IEEE Journal of Solid-State Circuits, Vol. 26, pp. 184-192,
March 1991.

Wey, C. L., and S. Krishnan, "A Current-Mode A/D Converter Array with a Common
Current Reference-Generating Circuit," submitted to IEEE Transactions on
Instrumentation and Measurement.