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MICHIGM STATE

III (II III II III III IIII IIIIIIIIIIIIII

 

 

 

 

 

 

 

 

 

 

This is to certify that the

dissertation entitled

A Noise Study of Bipolar Junction Transistor
Reliability

presented by
Chih-Chieh Jack Sun

has been accepted towards fulfillment
of the requirements for

Ph.D. degree inElectrical Engineering

 

 

Dr K. KM; at

Major professor

 

Dam/”limit @1993

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MSU Is An Affirmative Action/Equal Opportunity Institution
emmnt

A NOISE STUDY
OF BIPOLAR JUNCTION TRANSISTOR RELIABILITY

BY

Chih-Chieh Jack Sun

A DISSERTATION

Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

DOCTOR OF PHILOSOPHY

Department of Electrical Engineering

1993

ABSTRACT

A NOISE STUDY OF BIPOLAR JUNCTION TRANSISTOR RELIABILITY

BY

Chih-Chieh Jack Sun

Reliability issues, including hot-electron effects and electromigration effects, are
investigated for bipolar junction transistors. The low-frequency l/f noise power spectral
density and the common-emitter current gain (hFE) are the principal physical observables
for this study. Bipolar n-p-n transistors manufactured with three different technologies are
electrically stressed by reverse biasing or forward biasing the emitter-base junction at
various temperatures (-75 C to 240 C) and times up to 2500 hours.

After reverse-bias stress, an increase of the noise and a decrease of the gain were
observed. The decrease of gain was caused by the increase of the base current with the
collector current remaining unchanged. A linear relation between the noise increase and
the base current increase is predicted theoretically and observed experimentally. The
observed degradation is attributed to the hot-electron induced increase of interface states
and oxide trapped electrons. Forward-bias induced post-stress recovery allows partial
reversal of degradation and is believed to be due primarily to a reduction of the number of
oxide trapped electrons. Thermal annealing, which is capable of removing interface states
as well, produces a larger recovery of both gain and noise performance measures. With the
final merit of the transistor being its lifetime, the forward-bias induced recovery results
show that the lifetime of a transistor depends not only on the time over which a reverse

bias is applied, but also on the history of biases applied between the reverse bias periods.

For forward-bias stress, a combination of high currents and high temperatures
produced gain degradations or failures of transistors for all three technologies as well as
changes in transistor noise characteristics. Specifically, in all transistors stressed, the low-
frequency noise initially decreased without a change in gain. For longer stress times, it was
observed in two technologies that the noise eventually increased again concurrent with a
gradual decrease in gain. Electromigration induced compressive stress is believed to play
an important role in these phenomena. The third technology eventually showed failures of
the transistors due to electromigration produced open circuits. A degradation model which
explains the electromigration induced noise and gain changes on forward-bias stressed

transistors is presented.

Copyright © by
CHIH-CHIEH JACK SUN
1993

To my parents
and

my wife

ACKNOWLEDGMENTS

The author wishes to express his appreciation to his academic advisor, Professor
Donnie K. Reinhard, for his guidance and continuous encouragement during the course of
this work.

Appreciation is also extended to Dr. Timothy A. Grotjohn and his former Ph.D.
student, Dr. Chi-Jung Huang, for their generous assistance and valuable suggestions
during this research.

This work was partially supported by IBM Corporation, Fishkill, NY. The author
wishes to thank Dr. C.-C. W. Yu (IBM Cooperation, Kingston, NY) for his suggestions
and comments.

The author also thanks R. S. Hemmert for providing some of the devices, and Dr.

Mohammad Aslam for packaging selected devices used in this investigation.

vi

TABLE OF CONTENTS

LIST OF TABLES ......................................................................................................... ix
LIST OF FIGURES ........................................................................................................ x
Chapter 1 Introduction ................................................................................................... l
1.1 Motivation ..................................................................................................... 1

1.2 Objectives ...................................................................................................... 3

1.3 Preview of Thesis .......................................................................................... 4
Chapter 2 Background ................................................................................................... 6
2.1 Low-Frequency Noise Sources in BJT's ......................................................... 6

2.1.1 Physical Origins ............................................................................... 6

2.1.2 Identification of l/f Noise Sources in BJT's ................................... 10

2.2 A Review of BJT Degradation due to Electrical and Thermal Stress ............. 16

2.2.1 Hot-Carrier Induced Degradation .................................................. 16

2.2.2 Eiectromigration Induced Degradation .......................................... 22

Chapter 3 Reverse-Bias Stress Results ......................................................................... 27
3.1 Device Description ...................................................................................... 27

3.2 Device Characterization ............................................................................... 32

3.2.1 Low-Frequency Noise Measurement Method ................................ 32

3.2.2 I-V Characterization ...................................................................... 38

3.3 DC Reverse-Bias Stress and Post-Stress Recovery ....................................... 43

3.3.1 DC Reverse-Bias Degradation and Thermal Annealing .................. 46

vii

viii

3.3.2 F orward-Bias Induced Recovery ................................................... 51
3.3.3 AC Stress ...................................................................................... 59
3.4 Voltage Dependence of Reverse-Bias Stress ................................................ 64
3.4.1 Experimental Methods ................................................................... 64
3.4.2 Results .......................................................................................... 66
3.4.3 Discussion ..................................................................................... 79
Chapter 4 Forward-Bias Stress Results ........................................................................ 84
4.1 Device Description ...................................................................................... 84
4.2 Experimental Methods ................................................................................. 90
4.3 Stress Effects on Gain .................................................................................. 92
4.4 Stress and Thermal Annealing Effects on Noise ............................................ 98
4.5 Discussion ................................................................................................. 114
Chapter 5 A Forward-Bias Stress Induced Degradation Model ................................... 116
5.1 Background ............................................................................................... 116

5.1.1 Effects of Emitter-Edge Dislocations on BJT Low-Frequency

Noise ........................................................................................ 116

5.1.2 Dislocation Motion Under Forces ................................................ 120

5.1.3 Piezojunction Effect .................................................................... 123

5.2 Degradation Model .................................................................................... 128
Chapter 6 Summary and Conclusions ......................................................................... 142

BIBLIOGRAPHY ....................................................................................................... 146

LIST OF TABLES

Table Page
3.1 The values of A13 and ASIbe used in Figure 3.36 and the corresponding

stress history. ....................................................................................................... 83
4.1 The magnitudes of the current gain vs. stress time at VBE = 0.6 V for all

seven transistors of the Hemmert test structure. ................................................. 100
5.1 The normalized hFE for transistor #2, #3 and #4 of the Hemmert's test

structure. ........................................................................................................... 135
5.2 The normalized hFE decrease for transistor #2, #3 and #4 of the Hemmert's

test structure. ..................................................................................................... 136
5.3 The electromigration-induced compressive stress gradient along the

distance from transistor #1. ................................................................................ 139

ix

LIST OF FIGURES

Figure Page
2.1 Possible l/f noise sources inside a n-p-n transistor biased in forward-

active mode. ........................................................................................................ 11
2.2 A circuit model for the rrns 1/f noise sources measured in a BJT. ......................... 13
2.3 The transistor bias circuits for low-frequency noise measurements. ...................... 14
2.4 An electromigraion—induced metal accumulation, with a passivation layer

enclosing the metal, can result in compressive stress on the emitter. ..................... 24
3.1 Top view of the TIN3 device layout. .................................................................... 28
3.2 Top view of the TOUT device layout. .................................................................. 29
3.3 Doping profile for TIN 3 and TOUT devices. ........................................................ 30
3 .4 Pin out configuration of the transistors. ................................................................ 31
3.5 A set of three measurements of the emitter noise power spectral density

on a TIN3 device under different bias conditions. ................................................. 35
3 .6 Two measurements of the emitter noise power spectral density on the

same TIN3 device with its noise levels as shown in Figure 3.5. ............................. 36
3 .7 The quadratic current dependence of the noise power for a TIN3 device. ............. 37
3 .8 A set of three measurements of the emitter noise power spectral density

on a TOUT device under different bias conditions. ............................................... 39
3.9 Two measurements of the emitter noise power spectral density on the

same TOUT device with its noise levels as shown in Figure 3.8. ........................... 40
3.10 The quadratic current dependence of the noise power for a TOUT device. ........... 41

X

3.11
3.12
3.13
3.14

3.15

3.16

3.17

3.18

3.19

3.20
3.21

3.22

3.23

3.24
3.25

3.26

xi

The noise measurement flow of the emitter-voltage power spectral density. .......... 42
Circuit configuration for the I-V measurements. ................................................... 44
Diagram for the I-V measurement setup. .............................................................. 45

Average Gummel plot for a population of 12 devices at various stress

times (0 to 500 hours) for devices reverse stressed with VBE = -4 V and
VBC=OVat23 C. .............................................................................................. 48
hp]; vs. VBE for the data shown in Figure 3.14. .................................................... 49
km; recovery of degraded transistors shown in Figure 3.14 as a result of

post-stress thermal annealing at temperatures of 150, 175, and 240 C. .................. 50
The noise power spectral density measured at various stress times ( O to

100 hours) for a TIN 3 device reverse bias stressed with VBE = -4 V and
V3c=0Vat23 C. .............................................................................................. 52
The noise was reduced almost to the pre-stress level after 240 C

annealing for 60 hours. ......................................................................................... 53
DC reverse stress and post-stress thermal annealing effects on the

normalized hp}; and normalized low-frequency noise levels 511,9. ........................... 54
F orward-bias induced hp}; recovery under various recovery conditions. ................ 56
The test sequence for an investigation of 1/f noise recovery due to post-

stress forward bias. .............................................................................................. 58
Low-frequency noise reduction at various recovery time (0 to 60

minutes) due to forward bias applied to the emitter-base junction. ........................ 6O
Forward-bias induced recovery effects on normalized by; and

normalized low-frequency noise levels S1,”. .......................................................... 61
AC stress results with and without forward-bias (1.0V) cycles. ............................ 63
The voltage divider circuit used to perform reverse-bias stress under

various stress voltages. ......................................................................................... 65

The experimental flow for the reverse-bias stress under various voltages. ............. 67

xii

3.27 Normalized hFE at VBE = 0.6 V for TOUT devices stressed under -3.5,

4.0 and -4.5 V. ..................................................................................................... 68
3.28 The emitter noise power spectral densities afier different times of -3.5 V

stress. The noise measurements are performed under the common-

collector configuration with the bias conditions of VBE = 0.78 V and

VBC = -1.5 V. ...................................................................................................... 70
3.29 The emitter noise power spectral densities afier different times of -3.5 V

stress. The noise measurements are performed under the common-

collector configuration with the bias conditions of VBE = 0.76 V and

VBC = -1.5 V. ...................................................................................................... 71
3.30 The emitter noise power spectral densities after different times of -3.5 V

stress. The noise measurements are performed under the common-

collector configuration with the bias conditions of VBE = 0.74 V and

VBC = -1.5 V. ...................................................................................................... 72
3.31 The emitter noise power spectral densities afier different times of -4.0 V

stress. The noise measurements are performed under the common-

collector configuration with the bias conditions of VBE = 0.78 V and

VBC = -1.5 V. ...................................................................................................... 73
3.32 The emitter noise power spectral densities after different times of -4.0 V

stress. The noise measurements are performed under the common-

collector configuration with the bias conditions of VBE = 0.76 V and

VBC = -1.5 V. ...................................................................................................... 74
3.33 The emitter noise power spectral densities after different times of -4.0 V

stress. The noise measurements are performed under the common-

collector configuration with the bias conditions of VBE = 0.74 V and

VBC = -1.5 V. ...................................................................................................... 75

3.34 The emitter noise power spectral densities afier different times of -4.5 V

xiii

stress. The noise measurements are performed under the common-

collector configuration with the bias conditions of VBE = 0.78 V and

VBC = -1.5 V. ...................................................................................................... 76
3.35 The emitter noise power spectral densities after different times of -4.5 V

stress. The noise measurements are performed under the common-

collector configuration with the bias conditions of VBE = 0.76 V and

VBC = -1.5 V. ...................................................................................................... 77
3.36 The emitter noise power spectral densities after different times of -4.5 V

stress. The noise measurements are performed under the common-

collector configuration with the bias conditions of VBE = 0.74 V and

VBC = -1.5 V. ...................................................................................................... 78
3.37 ASIbe versus A13 for TOUT devices stressed under -4.0 and -4.5 V. ..................... 82
4.1 A schematic of the Hemmert test structure. .......................................................... 85

4.2 A set of three measurements of the emitter noise power spectral density

on a TSEO3I device under different bias conditions. ............................................. 87
4.3 The quadratic current dependence of the noise power for a TSE03I

device. ................................................................................................................. 88
4.4 Two measurements of the emitter noise power spectral density on the

same TSE03I device with its noise levels as shown in Figure 4.2. ......................... 89
4.5 Current gain vs. VBE for TIN3 transistors at stress times of O, l, 4, 24,

100, 200, 500 hours. The forward stress was done at 240 C with a

current density of 2 mA/umz. ............................................................................... 93
4.6 Normalized current gain of TIN3 transistors vs. stress time at various

current levels and ambient temperatures. .............................................................. 94
4.7 Current gain of individual TSE03I transistors vs. stress time for a stress

condition of 225 C and IE = 5 mA/umz. ............................................................... 96

4.8 Gummel plots for a TSE03I device showing the onset of high resistance

xiv

and eventually an open circuit during stress with an emitter current

density of 5 mA/um2 at 225 C. ............................................................................. 97
4.9 Normalized current gain for transistors #1, 2, 3, and 6 of the Hemmert

test structure vs. stress time. ................................................................................ 99
4.10 The noise power spectral density for transistor #1 of the Hemmert test

structure. ........................................................................................................... 101
4.11 The noise power spectral density for transistor #2 of the Hemmert test

structure. ........................................................................................................... 102
4.12 The noise power spectral density for transistor #3 of the Hemmert test

structure. ........................................................................................................... 103
4.13 The noise power spectral density for transistor #4 of the Hemmert test

structure. ........................................................................................................... 104
4.14 The noise power spectral density for transistor #5 of the Hemmert test

structure. ........................................................................................................... 105
4.15 The noise power spectral density for transistor #6 of the Hemmert test

structure. ........................................................................................................... 106
4.16 The noise power spectral density for transistor #7 of the Hemmert test

structure. ........................................................................................................... 107
4.17 Normalized base current noise power at 1 Hz vs. stress time for the

seven transistors of the Hemmert test structure. ................................................. 109
4.18 The noise power spectral density of a TIN3 transistor decreases afier a

forward-bias stress, reaches a minimum and subsequently increases

again. ................................................................................................................. l 10
4.19 The noise power spectral density of a TIN3 device decreases afier

stressing with IE = 2 mA/um2 at 240 C for 66 hours. Also shown is the

post-stress thermal annealing increase of the noise levels toward its

original values. The annealing was done at 240 C for 66 hours. .......................... 111

XV

4.20 The noise power spectral density of a TIN3 device decreases afier

stressing with JE = 2 mA/p.m2 at two different temperatures: first, 23 C

for 100 hours, then, 240 C for 66 hours. ............................................................. 112
4.21 The noise power spectral density of a TSEO3I device decreases afier

stressing at 225 C with IE = 5 mA/um2 for 90 hours. The noise level

increases after a post-stress annealing at 225 C for 90 hours. .............................. 113
5.1 Forward-bias stress degradation model. .............................................................. 130
5.2 Normalized base-current noise power spectral density at 1 Hz vs. stress

time for the seven transistors of Hemmert's test structure designed for

investigating the electromigration-induced compressive stress. ........................... 133
5.3 The forward-bias degradation model for Hemmert's pressure sensors

designed for testing the electromigration effect. .................................................. 137

CHAPTER 1
INTRODUCTION

1.1 Motivation

Degradation of bipolar junction transistor (BJT) parameters, such as the current
gain (km) and noise, is an important reliability consideration. Modern scaled-down
bipolar junction transistors are widely used in integrated circuits, such as in BiCMOS
gates, because of the advantages of high speed and low noise levels compared to
MOSFET's. However, long-term degradation of BJT parameters may counter these
advantages. The decrease of hpE in degraded BJT's can have a number of deleterious
effects including bias level shifiing and degradation of speed performance of integrated
circuits. The increase of the low fiequency noise levels in degraded BJT's may reduce the
signal to noise ratio and may cause an increase of the sofi error rate. In order to determine
proper corrective actions for the degradation effects, a detailed analysis and thorough
understanding of the phenomena which affect reliability is required.

The physical causes of device degradation can be introduced either during the
manufacturing process or by externally applied electrical and thermal stress. An example
of manufacturing induced degradation is the ionic contamination which can cause hFE
degradation in BJT's. However, improvements in the quality of the passivation layers
currently used in integrated circuit manufacturing produce transistors which are not
expected to degrade by ionic contamination. This study is specifically concerned with BJT

degradation due to externally applied electrical and thermal stress which includes hot

1

carrier effects and electromigration effects. In order to have a better understanding of
these two different degradation phenomena, the low frequency noise level which is well
known as a sensitive indicator is used as a physical observable in this study. In addition to
noise measurements, device I-V characteristics are also measured.

Hot carrier induced degradation of both hp}; and low frequency noise levels as a
result of avalanching the emitter-base junction of a silicon transistor was observed by
McDonald [2,14] in 1970. It was believed that the observation of an hFE decrease and l/f
noise level increase came from the same physical phenomenon, which was an increase in
the number of surface recombination states within the surface depletion region. Such an
increase may be a result, for example, of broken Si-H bonds caused by hot carriers. In
recent scaled-down BJT's, hot carrier induced hFE degradation has been also observed
during reverse-bias stress with the bias below the avalanche voltage [4-9] and possibly
during forward bias stress with very high current densities [1,12,13]. A below-avalanche
reverse bias can cause hFE degradation if energetic carriers are created by a sufficiently
high electric field obtained by reverse bias in the scaled transistors. As a result of reverse-
bias stress, an increase in the effective number of surface recombination states will result in
an hFE decrease and a noise level increase [14-16].

For the forward-bias stress, hot carriers in the base-emitter region are not likely to
be generated by an electric field because the base-emitter region electric fields in the
devices are much smaller during forward bias stress then during reverse bias stress.
Watchnik et. a1. [1] proposed, however, that hot carriers created by the Auger
recombination process during forward bias stress can also cause an increase of surface
recombination states. Consequently, an hFE decrease during forward-bias stress would be
observed. There is no report yet to describe the behavior of noise levels during the
forward-bias stress although according to the above rationale the noise would be expected

to increase because of the increase of surface recombination states.

High forward-active current stress may also lead to BIT degradation as a result of
electromigration induced compressive stress built-up above the emitter region as described
by Hemmert et. al. [18,77]. It is noted that both hot carrier and electromigration effects
can produce similar degradation effects, although the two effects are quite different
physically. For example, both may cause hFE to decrease, both may cause an increase in
the leakage current and in the emitter-base junction current in the low forward-bias
voltage region, and both show annealing of degradation effects. Consequently, it is not
sufficient to distinguish between these two phenomena only by monitoring hp}; changes.
Since the two phenomena relate to different device design features, it is important to
distinguish between them. Noise measurements are helpful in this regard. It is shown in
this dissertation that after forward-bias stress on a BIT the noise levels actually decrease,
which is opposite to the expectation of a noise increase caused by an increase of surface
recombination states. This indicates that noise measurements can indeed provide

information which enables one to distinguish between these two degradation phenomena.
1.2 Objectives

The objective of this study is to provide an increased understanding of the
degradation mechanisms, with particular emphasis on hot electron effects and
electromigration effects, when a BJT is subjected to externally applied bias and
temperature stress. Toward this objective, noise measurements are performed in addition
to the traditional hp]; measurements in order to help obtain a more extensive view of the
degradation phenomena. The measurements are designed to identify which physical noise
sources are the principal contributors for any observed noise changes. Noise degradation
models then can be built up, based on the experimental results, to correlate noise changes

with the observation of has degradation.

There are two main tasks addressed in this study. First, the low frequency noise
measurement is used as a vehicle to distinguish the different physical causes of
degradation, either hot-carrier induced degradation or electromigration effects, when
BJT's are subject to forward bias stress. Explanations of the origins of the noise changes
are evaluated. Second, for reverse-bias stress, a comprehensive study of device
degradation and post-stress recovery on both gain and noise behavior is presented. A
model which correlates the stress induced noise changes with the stress induced base
current changes is presented. This model allows one to predict the noise changes, which
requires a more complicated characterization process, by knowing the changes in base

current.
1.3 Preview of Thesis

Chapter 2 reviews previous studies of hot electron effects and electromigration
effects on bipolar junction transistors.

Chapter 3 presents the reverse-bias stress results of the present study. Various DC
stress voltages and various AC stress signals are applied to stressed devices. Post-stress
recovery mechanisms, including thermal annealing and forward-bias induced recovery, are
also investigated. A model which correlates the stress induced noise changes with the
stress induced base current changes is presented. Also included in Chapter 3 is the noise
measurement method used in this study for identifying the dominant noise source within a
given bipolar junction transistor.

Chapter 4 presents the experimental results of the forward-bias stress on three
kinds of bipolar junction transistors manufactured with different technologies, including a
test structure design specially intended for investigating the effects of electromigration

induced compressive stress. For all three different BJT technologies, a general trend in the

noise analysis emerged: the low-frequency noise levels initially decreased after application
of forward bias stress at high temperature.

A model for interpreting the experimental data shown in Chapter 4 is given in
Chapter 5. The background needed to build-up this model is first reviewed. Then, the
model is presented which utilizes the concepts of both dislocation motion and band gap
narrowing caused by electromigration induced compressive stress. This model presents
qualitative explanations of both gain and noise changes on all three different BJT
technologies.

Finally, conclusions and results are summarized in Chapter 6.

CHAPTER 2
BACKGROUND

2.1 Low-Frequency Noise Sources in BJT's

2.1.1 Physical Origins

There are in general four kinds of low-frequency noise sources that may be
observed when noise measurements are performed on bipolar junction transistors at room
temperature, namely, (1) the surface recombination noise source, (2) the diffusion noise
source, (3) the internal series resistance noise source, and (4) the burst noise source. In
principle, there is additionally a fifih low-frequency noise source due to bulk
recombination in the base region, but it has been shown [24] that the bulk recombination
noise source is generally negligible compared with other low-frequency noise sources. The
noise power spectra of the first three low-frequency noise sources are almost inversely
proportional to the fi'equency; in other words, they have the frequency dependence of M“
, where a is around unity. Consequently they are ofien referred to as l/f noise sources.
However, for burst noise, the noise power spectrum typically has a 1/f2 shape for
frequencies lower than 104 Hz [25]. The physical origin of each of these noise sources is
described as follows.

The surface recombination l/f noise is associated with the fluctuation of the carrier

density due to the recombination-generation process around the device surface [26-28].

The recombination at the surface proceeds via fast surface recombination states, but these
surface recombination states are modulated by the trapping or detrapping of carriers at
and near the surface. Consequently, the fluctuation in the surface recombination should be
proportional to the fluctuation in the density of trapped centers, and hence to the density
of surface recombination states. This recombination type of l/f noise source is sometimes
also regarded as a "non-firndamental noise" because the magnitude of its spectrum can be
strongly reduced by eliminating most of the surface recombination states. The
recombination current may be only a small part of the total current in BJT's, but the
recombination 1/f noise can be significant since the recombination is a quite noisy process.
It is believed that the surface 1/f noise of a bipolar junction transistor comes from the
recombination at the base surface or at the emitter-base space charge region [29]. Jantsch
[30] obtained a expression for this surface noise current power spectral density as

_ 0.1 (is)2
l - _ 9
rec f AN”

 

(2.1)

where f is the frequency, A is the surface area where the surface recombination takes
place (e. g. the base surface area or the emitter-base junction surface area), Nit is the
interface state density, and 73 is the surface recombination current. With an applied
voltage V, is is given by [64]

is =1—sO exp(qV/ZkT) (2.2)
with

isO cc AN“. (2.3).
Since (792 is proportional to (ANi¢)2, Equation 2.1 predicts that the noise power
spectrum increases linearly with Na. Since the total base current is

18 =180 exp(eV/ka) (2.4)
where

Ismsz, (2.5)

by using Equations 2.1, 2.2 and 2.4, the noise intensity can also be expressed as

, = _ [3.
rec fA N it 130m

 

(2.6)

Consequently, the surface 1/f noise power spectrum can have a non-linear current
dependence.
It is noted that Equation 2.1 allows one to calculate the rrns noise current within a

given frequency range as

1/2
fH
(Irec)rms =|:fJ: Slmdf] « (2.7)

1.
Note that since S1,“ goes as l/f, the noise power contained in a bandwidth between fL and
f H is proportional to log( f” / f L)- Consequently, each decade of frequency contains the
same noise power. For example, the noise power contained between 10 Hz and 100 Hz is
the same as that contained between 0.1 Hz and 1 Hz.

The diffusion 1/f noise [24,31,32] is caused by the mobility (u) fluctuation of
charged carriers when current is flowing in the devices. Physically this fluctuation is due to
the scattering of carriers. Because of the Einstein relation eD=kTu, the mobility
fluctuation will lead to a fluctuation of the diffusion constant D. It has been shown both
experimentally [33-36] and theoretically [24,37] that the diffusion 1/f noise can be one
important noise source for solid-state devices governed by diffusion process, such as
BJT's. The diffusion 1/f noise is also regarded as a "fundamental noise" because it should
have the identical value from device to device for the same device structure. For a n-p-n
bipolar junction transistor biased in the forward active mode, there are two diffusion
current sources which can result in the diffusion l/f noise. One, S15", is due to the injection
of electrons from the emitter to the base, diffusion in the base, and subsequent collection
from the base by the collector. This noise current power spectral density can be expressed

as [38]

 

I D 0: N(0)
S = ‘1 En n Hnl , 2.8

where f is the frequency, Dn is the diffusion constant for the electrons, W3 is the width of
the base region, N(0) and N( W3) are the base-injected electron concentration at the
emitter side and at the collector side, respectively, and 05”,, is the Hooge parameter [34]
for electrons. A mobility fluctuation induced noise, SIB,” is also associated with the base
current which results from the injection of holes from the base to the emitter and
subsequent diffusion in the emitter. This noise current power spectral density can be

expressed as [38]

 

_ €113th O‘Hp P(0)
SIB}, (f) _ WE2 f ln[P(WE)]a (29)

where f is the frequency, DP is the diffusion constant for the holes, W5 is the width of the
emitter region, P(0) and P(WE) are the electron concentration at the base side and at the
emitter side, respectively, and 0:11,, is the Hooge parameter [34] for holes. Similar diffusion
noise expressions can also be applied to a p-n-p transistor, however, with the opposite
types of diffiision carriers.

' The diffiision 1/f noise sources can be distinguished from the surface
recombination l/f noise source with the help of their current dependence. The power
spectrum of diffusion 1/f noise is proportional to the magnitude of current (I). On the
other hand, the power spectrum of surface recombination l/f noise is not linearly
dependent on I and usually has a quadratic dependence on the current [29,3 5].

The l/f noise which originates from the internal series resistance in a BJT's was
first proposed in 1980 [39] although there was a controversy [40] on the accuracy of the
qualitative elaboration of this proposed idea. Recently a more definitive investigation of
this noise source [41] was presented. In this study, the low-frequency noise measured in

high bias current region (15 > IOOuA) was attributed to the base series resistance

10

fluctuation. Although the base series resistance (rb) consists of two parts: contact
resistance (rbc) and bulk resistance (rbb), the results indicated that the observed l/f noise
was mostly from fbb. According to the Hooge relation [33]

Srbb(f) = “(2"be /be , (2.10)
where f is the frequency, 05;, is the Hooge parameter for the base, and Nb is the effective
number of charge carriers. Physically this noise is also due to mobility fluctuation caused
by the carrier scattering. In general, the emitter series resistance re and the collector series
resistance rc can also contribute to the l/f noise as Sr, and Src respectively. However, re is
generally small, and in the common emitter configuration rc is in the output stage which
will have less effect on device noise properties than rb, which is in the input stage.
Consequently, Sr, and 5,, usually are neglected in comparison with Sn,-

The mechanism that causes the burst noise in bipolar transistors is not well
understood so far. However, it is generally accepted that the burst noise is a particular
type of generation-recombination noise which is caused by the defects located near and
inside the bulk emitter-base junction area. Nevertheless, opinions on the nature of the
defects are divided. Hsu et al. [25] indicated metallic precipitates, Blasquez et al. [42]
favored crystallographic defects, and in supporting this Mihaila et al. [43] presented
results indicating that burst noise is due to the clusters of dislocations inside the emitter

area.
2.1.2 Identification of l/f' Noise Sources in BJT's

As mentioned in the previous sub—section, the possible low-frequency 1/f noise
sources in an given n-p-n bipolar junction transistor are S1,“, S15", S13," and 5,1,, which are
shown in Figure 2.1. The goal of this sub-section is to review some noise measurement

techniques used for finding the location of 1/f noise generator(s) inside a BJT, and,

ll

      

 

h+

.."'.'fl"'-""‘O-""--"““"

 

 

F /too;-nooa-cocoon-ov—cooooaooaoao
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O

O

a
................................................................

 

Slm, = suface recombination l/f noise source

S,“ = electron diffusion l/f noise source

S,“ = hole diffusion l/f noise source
5'1, = base series resistance l/f noise source

Figure 2.1 Possible 1/f noise sources inside a n-p-n transistor biased in forward-active
mode. The arrows show the direction of charged carrier flow (not the current

flow).

12

furthermore, deciding which of four above-mentioned l/f noise sources may be dominant
in each generator(s).

It is generally accepted that a circuit model for the l/f noise power spectra
measured in bipolar junction transistors should include two independent noise current
generators: Slbe located between the base and the emitter, and S1ce located between the
collector and the emitter. There should, in principle, be a third noise current generator Slbc
located between the base and the collector. However, the base-collector junction is usually
reverse biased so that the base-collector current is slight and its noise can be neglected
[35]. SIbe can be attributed to the combined effect of diffusion 1/f noise source (i.e., 813,,
for a n-p-n transistor) and surface recombination 1/f noise source (81,“); however, usually
one type of 1/f noise sources will be dominant. By checking the current (13) dependence,
as described in Section 2.1. 1, one can determine the dominant contributor. On the other
hand, Slce comes from the diffusion 1/f noise source (i.e., S15" for a n-p-n transistor) and
should be proportional to the current 1c. Besides those two noise current generators, there
is also a noise generator attributed from the base series resistance noise sources, Srb. Since
there is a current 13 flowing through rb, S", can contribute to the low frequency noise in a
transistor. Figure 2.2 shows the circuit model for the low-frequency l/f noise sources.
Here ibe and ice are the rms noise currents of SIbe and SI“, respectively. It is noted that
there also exits a rrns noise voltage of [32 Sn, across rb since 13 flows through rb. The rrns
noise value of either a current power spectral density or a voltage power spectral density
has a similar definition as shown in Equation 2.7.

Kleinpenning [41] demonstrated a method to identify the 1/f noise sources by
analyzing the results measured under both the common-emitter and common-collector
configurations with different values of the external resistances. Figure 2.3 showed the
circuits used for his noise measurement method. It is noted that the transistors have the
noise circuit model shown in Figure 2.2. Both the collector-noise voltage spectral density

(Sr/C) and the base-noise voltage spectral density (S V3) were

l3

 

 

 

 

 

 

 

 

 

 

b rb b' C, ’c
w r T W-—*
lbe El gr“ CngVb’e, [3 ice
e'
re
e

Figure 2.2 A circuit model for the rms l/f noise sources measured in a BJT.

l4

 

: VCC

 

 

 

 

 

 

 

 

VCCTT_
_: VEE

 

 

 

 

Figure 2.3 The transistor bias circuits under (a) common-emitter configuration and (b)
common-collector configm'ation for low-frequency noise measurements. (After

Kleinpenning [41])

15

measured under the common-emitter configuration, and the emitter-noise voltage spectral

density (S V5) was measured under the common-collector configurations. It may be shown

 

 

 

that
r- +R S +r+ +R 2S + +12128
SVE=[7: a”) 3)}2 [be [75 if B] Ice ([3 ) B’bXRlzf’ (2.11)
' Z
[329), +RB +r +R ]2S +[r +0, +R +r +R ]25 “#32125
S = e E Ibe n B e E Ice 8 I'b X 2
VC 2 RC’
Z
(2.12)
r+ r+R 2S +r+R 2S +12S
SVB=[7r me 175)] 1be22[9 E] [Le 13'be13, (2.13)
with
Z=RB+rb +rn+(l3+1)(RE +re)- (2'14)

It is noted that a white noise term could be added to each of above noise equations.
However for low frequencies, the white nose is dominated by l/f noise. By measuring SVE,
SVC and S VB for known values of 11;, 1C, 113, RE, RC and RB, these three equations enable
one to solve the three unknown noise generators, (1) S1ce, (2) Sibe, and (3) 54' Also, by
modifying the bias point by varying the resistor values, it is also possible to check the
current dependence of S1ce and Sjbe, and thus determine the physical origin for these l/f
noise sources, as will be described in Chapter 3.

An alternative noise measurement method has been developed by van der Ziel et al.
[29]. The bias circuit for this method uses only the common-emitter configuration,
however, with or without a R}; in the emitter lead. In this approach, basically four
measurements are needed for a given bias point: (1) the collector noise spectrum with R5,
(2) the collector noise spectrum without RE, (3) the base noise spectrum with R5, and (4)
the base noise spectrum without RE. RE serves as a feedback resistor which allows the

observation of the amplification or attenuation of noise generators, thus facilitating the

l6

determination of noise generator. Also, in this approach, the 1/f noise caused by internal

series resistance fluctuations was not considered.

2.2 A Review of BJT Degradation due to Electrical and Thermal Stress

The physical causes of BJT degradation can be introduced either during the
manufacturing process or by externally applied electrical and thermal stress. An example
of manufacturing induced degradation is ionic contamination which can cause hFE
degradation in BJT's. However, improvements in the quality of the passivation layers
currently used in integrated circuit manufacturing produce transistors which are not
expected to degrade as a result of ionic contamination. This section is specifically
concerned with BJT degradation due to externally applied electrical and thermal stress,

which includes hot-carrier induced degradation and electromigration induced degradation.

2.2.1 Hot-Carrier Induced Degradation

It is believed that the physical cause of hot-carrier induced degradation is generally
due to one of two mechanisms. The Si-Si02 interface may be damaged, resulting in an
increase in the number of interface states. Secondly, carriers may be trapped in the oxide,
either by surrnounting the Si-Si02 barrier, or by tunneling through the barrier to trap
states in the energy gap of the oxide. In either case, the resulting change in trap density
and band bending cause changes in BJT performance parameters.

There are two distinctly different mechanisms by which hot-carriers may be created
in a BJT. Hot-carriers are produced either by a large electric field or by Auger
recombination [1]. The first mechanism certainly plays a dominant role in reverse-bias
degradation of BJT's, and both mechanisms may play a role in forward-bias degradation of
BJT's.

17

For reverse-bias degradation studies, McDonald [2] in 1970 showed that ha;
degradation results when the emitter-base junction is reverse biased to the point of
avalanche. He was able to explain the degradation induced leakage current by an increase
in the number of surface recombination centers as a result of avalanche-induced surface-
state formation within the surface depletion region. By using a gate-controlled transistor
structure, he also determined that there was localized charge trapping within the oxide
over the emitter-base junction as a result of avalanching.

In the past twenty years, several improvements have bee; trade to avoid operating
BJT's at avalanching biases. An example is the termination of wt lines by clamping
diodes in integrated circuits. However, recent trends in bipolar transrstor scaling [3] have
resulted in highly energetic carriers at the reverse biased emitter-base jL tion for below-
avalanche voltages [4]. Hot carriers were reported to cause degradation ir. ivanced
technology transistors not operated under avalanche bias conditions in sever:~ .;udies [4-
9].

Petersen et al. [5] described a hot-electron .iuced hFE degradation study in
advanced self-aligned sidewall spacer n-p-n bipolar transistors. The transistors were
operated with their emitter-base junctions reverse biased below the avalanche voltage and
collectors opened. The carriers were injected by illuminating near the edge of emitter-base
depletion region with a 5 mW He-Ne source. The measured characteristics taken before
and after stress showed that the increase of the low level base current afier stress was
accompanied by a shift in the ideality factor from near 1 to 2. This indicated that the
probable cause for the higher base leakage current is an increase of interface state density
in the sidewall oxide between the emitter and base.

The work done by Joshi [6] showed hot-carrier induced degradation in a poly-
emitter bipolar transistor fabricated by a BiCMOS process. Transistor hpg degradation
was studied by reverse biasing the emitter-base junction under DC, pulse, and AC

conditions. For the ceramic packaged devices, extended temperature (-55 to 175 C) tests

18

were performed. For a constant current stress, it was shown that hFE degradation
depended on the total injected charge, which was equal to the stress current multiplied the
stress duration, through the reverse biased emitter-base junction.

A study of hot-carrier efi‘ects in self-aligned polysilicon emitter bipolar transistors
was also presented by Burnett et al. [7] in 1988. The 17175 degradation under DC reverse-
bias stress was described by a empirical model with fitting parameters. The model was able
to predict the device lifetime over a wide range of reverse-bias stress currents for a given
technology.

Momose et al.'s paper [8] showed a study of temperature dependence of emitter-
base reverse-bias stress degradation. It was found that the largest degradation occurred
around 50 C. Their simulation work confirmed that both electron trapping in the oxide and
interface state generation occurred during stress. However, the generation of interface
states in the oxide near the emitter-base junction was the main cause for the degradation.

In Burnett et al.'s later work [9], BJT's fabricated by BiCMOS technology were
reverse biased at 110 K and 300 K respectively. Although the reverse current is smaller at
110 K than at 300 K for the same reverse voltage, the rate of degradation was observed to
be four times larger at 110 K than at 300 K for the same reverse voltage and ten times
larger for the same stress current. The increased degradation at low temperature is
consistent with the increase severity of hot-carrier damage in MOSFET's [10]. In both
cases, the carrier mean-free-path increases with decreasing temperature, allowing the
carriers to achieve higher energy prior to scattering.

Recently an investigation of process dependence of reverse-bias hot-carrier
reliability in BiCMOS n-p-n transistors was performed [76]. As shown in the experimental
results, the base doping concentration as well as the thermal history affect the hot-carrier
induced hFE degradation. Rapid thermal annealing (RTA) was used in this study. The
band-to-band tunneling current was identified as the dominant reverse-bias stress source.

Consequently, any means which can reduce the band-to-band tunneling current should

l9

improve the hot-carrier reliability. It was found that hot-carrier induced degradation was
improved by reducing the base dopant concentration and by increasing the RTA time.

For forward-bias induced hot-carrier degradation studies, Chen et al. [11] in 1986
reported the effects of forward active current stress on the electrical characteristics of self-
align transistors. The transistors were mounted on high temperature ceramic packages and
stressed in an ambient temperature ranging from 25 C to 280 C. During stress, the
transistors were biased in the forward active mode by forcing a constant current density of
1 mA/um2 through the emitter. It was found that the transistors with higher initial non-
ideality factor were more susceptible to degradation induced by high-current stress. The
dominant changes in the electrical characteristics after stress were found to occur at the
base-emitter junction with the collector current remaining unchanged. In the low current
region, an increase of the non-ideality factor of the base current, and thus a decrease of
hp}; was observed after stress, and was attributed to interface state generation underneath
the sidewall oxide between the base and the emitter polysilicon. In the high current region,
for transistors initially with nearly ideal base and collector current characteristics, hpg was
found to increase afier stress. It was suggested that this was caused by an increase in the
total Gummel number resulting fiom either electromigration of the dopant to the interface
between the 11+ polysilicon and crystalline silicon, or the breaking of the interfacial oxide
barrier between n+ polysilicon and crystalline silicon. However, no physical evidence was
given to confirm these mechanisms.

Auger recombination was identified by Wachnik et al. as a main source of forward-
bias induced hot-electrons which produced BJT damage [1]. At room temperature, the
forward bias was applied across the emitter-base junction with the base-collector junction
shorted. Under this condition, electric fields in the BJT are relatively low since the base-
emitter junction was forward biased, which reduced the electric field at that junction, and
the collector-base junction had a zero bias applied. Also, the stress time and temperature

ruled out the possibility of electromigration such as that reported by Hemmert et al. [18]

20

(see Section 2.2.2). They reported an observation of a fluctuating increase in the base
current with the collector current remaining unchanged. Wachnik et al. proposed that the
degradation was due to generation and diffusion of hot Auger electrons to the Si-SiOz
interface at the sidewall oxide between the emitter polysilicon and base polysilicon. This
was followed by a bond breaking event creating a dangling silicon bond, presumably a
broken Si-H bond. The work also presented evidence for repassivation of that bond with
continued stressing since fluctuation of the base current was observed.

In 1990, Joshi [12] reported a study on degradation for self-aligned bipolar
transistors operated under various forward-bias current densities (0.23 mA/um2 to 2.86
mA/umz) at various ambient temperatures (0 to 150 C). The most pronounced change in
BJT characteristics was the base current and the hpg. The collector current remained
unchanged during stress. hpE in the low current region (Ic < IOuA) was found to increase
initially with stress time and then degrade very rapidly with subsequent stress, whereas
by; in the high current region was found to increase monotonically with stress time. He
also found the transistors with perimeter-to-area ratio larger than 1.5 were more
susceptible to larger hFE changes. It was suggested that the major cause of [1,75 change
was an increase of interface traps and/or positive charges due to Auger hot-electrons. A
predictive model for the device degradation rate depending on the effective emitter stress
current destiny and stress temperature was also developed.

A investigation of very-high-current (up to 12.5 mA/umz) degradation on Si n-p-n
transistors was done by Tang et al. [13]. The stressed devices were double-poly self-
aligned n-p-n bipolar transistors with a emitter area of 0.8x2.0 umz. The emitter-base
junction showed negligible degradation when the transistor was stressed in the normal
mode such that the emitter-base junction was forward biased and the collector-base
junction was reverse biased, so that electrons were injected fiom the emitter, diffused
through the base and collected by the collector. However, the emitter-base junction

showed degradation when stressed in the forward bias with the collector open. Also, the

21

emitter-base junction showed degradation when the transistor was stressed in the inverse
mode such that the emitter-base junction was reverse biased and the collector-base
junction was forward biased, so that electrons were injected from the collector and
collected by the emitter. They observed a significant stress-induced leakage component in
the base current in the later two stress modes. The cause of the junction degradation was
believed to result from the degradation of the sidewall oxide damaged by the hot-carriers
injected from the base-collector junction.

Besides the above-mentioned reports, in which transistor DC current
characteristics and hpE were primarily used as the physical observables, some other studies
have also indicated that the low-frequency noise will be changed during reverse-bias hot-
carrier degradation. McDonald [14] reported that I/f noise was increased significantly
after avalanching the emitter-base junction of a bipolar junction transistor. By using the
gate-controlled transistor structure, he showed that the mechanism that caused a l/f noise
increase was identical to that responsible for hp}; degradation, which was attributed to an
increase in surface recombination centers within the emitter-base space-charge region.

Koolen et al. [15] also showed that an increase of low-fi'equency noise was
correlated with the decrease of hFE of a bipolar transistor afier reverse-bias stress. The
decrease of 11175 was identified as resulting from an increase of the non-ideal base current
component with the collector current remaining unchanged. A modified SPICE noise
model which described the noise behavior during the reverse-bias stress by relating the
magnitude of the non-ideal base current component to the increase of the low-frequency
noise was presented.

Another model correlating the l/f noise magnitude with the hFE degradation of a
polysilicon emitter n-p-n transistor fabricated by BiCMOS technology was proposed by
Dreyer et al. [16]. At room temperature, a below-avalanche 5.2 V reverse bias was applied

to the emitter-base junction. Consequently the noise voltage power spectral density was

22

related to by; degradation in the following form:

720,0...) = a x exp(—b - hFE" ), (2.15)
where a and b were the fitting parameters, and km“ the normalized hFE defined as hp);
after stress divided by original hFE. By checking the current dependence of the noise
magnitude, they confirmed that surface recombination was the source of observed
increased l/f noise. Furthermore, it was found that the slope of the noise spectrum was
very sensitive to hpE degradation, with an increase in spectral slope from 1/f to l/f‘2 at the
onset of degradation. However, the slope of the noise spectrum slowly dropped toward its
initial value as the stress continued.

There is no report found yet to describe the behavior of low-frequency noise levels
as a result of the forward-biased induced hot-carrier degradation. However, one would
expect to observe the same low-frequency noise increase as that in reverse-bias stress
because the same physical degradation phenomenon, which is the increase of surface
recombination centers, can be applied to both reverse-bias and forward—bias induced hot-

carrier degradation cases.
2.2.2 Electromigration Induced Degradation

Forward-bias stress with a very high current density can also cause
electronrigration induced degradation in a BJT in several ways. Previous reports include
the observation of an open circuit for the collector, a short circuit or a resistive shunt
between the base and the emitter, a short circuit between the multiple-layer metalization, a
change of contact resistance, the penetration of contact metal into Si substrate, and a
change of Irma.

Electromigration induced failure for silicon devices and integrated circuits utilizing

Al metalization was presented by Black [17] in 1969. He described two kinds of failure

23

modes: (1) the formation of an electrically open circuit due to the occurrence of the metal
voids, and (2) the penetration of aluminum into the Si emitter of a n-p-n bipolar transistor,
by which the shorting of the underlying junction could occur. A theory which described
the failure rate (open circuit) of metal conductor stripes was also presented. The theory
expressed that the failure phenomena proceeded as the current density square multiplied
by exp(-¢/kT), where d) is the activation energy, k is the Boltzmann's constant, and T is the
absolute temperature.

A study of electromigration induced hpg degradation attributed to
electromigration induced compressive stress was proposed by Hemmert et al. [18] in
1982. Under forward-bias stress, electromigration will tend to cause an accumulation of
metal above the emitter region. However, as shown in Figure 2.4, with a passivation layer
enclosing the metal line the thickening of the metal will not be able to readily occur.
Instead, there will be a build up of compressive stress normal to the substrate. The devices
used for stress in their study were n-p-n transistors fabricated in a conventional manner on
<100> p-type wafers. Aluminum penetration into the emitter was prevented by a chrome
diffusion barrier. A Si02/Si3N4 passivation layer with different thicknesses was deposited
above the devices. The experimental results showed that increasing the passivation
thickness aggravated beta degradation. This phenomenon was explained by the thick wall
pressure vessel problem [19], where equal volume of fluid accumulation(metal) resulted in
higher pressure(stress) as the vessel wall(passivation layer) became thicker. According to
the theory proposed by Kanda [20], when a n-p-n BJT built on a <100> wafer is subjected
to a compressive stress, a net decrease in has should be observed for a long stress time.
However, on a shorter time scale, a double minimum in hFE is predicted during the stress
period. This double minimum in hFE is attributed to the stress dependence of the hole
effective mass. Hemmert et al. did observe a slight double minimum in 111:]; degradation
process. A post-stress annealing was also performed at various temperatures, and a

complete recovery of 171:}; was achieved at 400 C in less than 15 minutes. The annealing

 

PAS SIVATION

(COMPRESSIVE STRESS)

OXIDE
L EMITI‘ ER j

BASE

k J

 

 

 

OXIDE

 

 

W

 

 

 

 

 

COLLECTOR

Figure 2.4 An electromigraion-induced metal accumulation, with a passivation layer
enclosing the metal. can result in compressive stress on the emitter. (After
Hemmert et al. [18])

25

effect indicated that electromigration induced compressive stress is relieved by creep in the
aluminum metalization.

Wada et al. [21] performed electromigration tests on n-p-n bipolar transistors with
three different metal layouts. Both transistor configuration 1 (Tr-1) and transistor
configuration 2 (Tr-2) had a single emitter. However, Tr-l had single base and single
collector contacts, but Tr-2 had double base and double collector contacts. Transistor
configuration 3 (Tr-3) had a double emitter and triple base and collector contacts. Also,
Tr-3 was the only transistor using double layer metalization. The stress condition was with
Ic varying from 4 mA to 60 mA and with temperature varying from 150 C to 250 C. They
observed that in all cases degradation was accelerated by higher temperature and higher
current density. Also, the failure mode depended on the metal layout of the transistor.
When the configurations of the emitter metalization and collector metalization were
almost the same, the open circuit of the collector was the main failure mode. However,
when the configurations of the collector metalization was larger than that of the emitter
metalization, the resistive shunt of the emitter-base junction occurred. For Tr-l a gradual
decrease of [mg was also observed before the open circuit of the collector was finally
observed. For Tr-3, which had a collector metalization on top of the emitter metalization,
emitter-collector short circuits were caused by hillocks breaking through the intermediate
dielectric layer.

Tang et al. [75] showed a metal migration into the polysilicon emitter afier
stressing at an emitter current density of 1.63 mA/um2 for 47 hours at 90 C. According to
post-stress TEM analysis, a metal filament was observed at the edge of the emitter
polysilicon. However, it did not penetrate through the polysilicon. It is noted that the edge
of the emitter polysilicon has the highest current density because of the emitter crowding
effect. The metal filament lowered the emitter contact resistance. Also they suggested that

a nrinute amount of metal, undetectable to the TEM analysis, could penetrate through the

26

polysilicon and reach the polysilicon/silicon interface. Under that circumstance, a lower
hFE may be expected.

Noise measurements have been used to predict the failure rate of metal film
interconnectors for VLSI [22-23]. However, no report has been found using noise as an
observable for the electromigration induced compressive stress effect on BJT's. In this
dissertation, a noise study for such compressive stress on a BJT will be presented. Chapter
5 presents the experimental portion of this noise investigation, and a model for. interpreting

the data is given in Chapter 6.

CHAPTER 3
REVERSE-BIAS STRESS

3.1 Device Description

There were two kinds of silicon n-p-n transistors which were manufactured by
IBM used in this reverse-bias stress study, namely TIN3 and TOUT. These transistors
were contained in silicon chips, which were bonded in 28 pin ceramic packages. Each chip
had one TIN3 and one TOUT. The chips were traceable as to location on the wafer, wafer
number and job number. Conventional oxide isolation methods [81] were used for
fabricating TIN3 and TOUT. These devices did not include polysilicon emitter or
polysilicon base structures. Instead, a first layer metal was used for device contacts.
Figures 3.1 and 3.2 show the layouts for TIN3 and TOUT devices respectively. TIN3 and
TOUT had the same emitter region layout with an area of 2.5x4.3 umz. The emitter
contact cut is also the emitter ion-implant region. However, TOUT had a Schottky diode
clamp and TIN3 did not. Both devices had the same doping profile as shown in Figure 3.3.
The donor concentration on the emitter surfaces of both devices was 3.2x1020/cm3, and
the acceptor concentration on the extrinsic base surface was 6.3x 1013/cm3. The intrinsic
base width was 0.35 pm. Both devices were provided with double collector contacts,
double emitter contacts, and a single base contact as shown in Fig 3.4. For TIN3, the pin-
to-pin resistance between the two collector contacts were approximately 21 Q whereas for

TOUT the resistance was approximately 5.2 (2. For the common emitter contacts shared

27

 

. V a
M
H—f—H

\\ \'
\\

 

 

 

 

Fgur31TpvrwthIN3dvrcely t.eTh dienm nisare units ofum.Metal
region sear shownassolidbla ckareaso ontactc ansdascro sts-ha ched
regions elsewhere. Actual metal regions exceed the plotted metal regions.

 

\\\\\\\\\\\\\\\\\\\

\ \\ \

Base t \\

 

\\

\\\\\\\\\

\\\\\

 

 

 

 

 

:0a

A JJALAAA

10'

A AAAAAA‘

A

xo|O

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doping concentration

A A A AAAAA.

(917

A A ALAAA.

 

 

 

 

 

10" T r ,
0.00 .230 .WOO .600 .000 1.00 1.20 1.W0

Figure 3.3: Doping profile for TINB and TOUT devices [81]. The impurity concentrations

are in units of cm'3.

31

ll 12 13 17 I9 20
10: TOUT 141:1 TD4 18 TINS

15 16

 

 

Figure 3.4: Pin out configuration of the transistors. The three transistors have two

common emitter pits.

32

by TIN3 and TOUT, the pin-to-pin resistance was approximately 8.5 Q. Both collector
contacts and both emitter contacts were used during the stress conditions and during

measurements to reduce parasitic resistance effects.

3.2 Device Characterization

3.2.1 Low-Frequency Noise Measurement Method

As described in Section 2.1.2, the low-frequency noise sources inside a bipolar
junction transistor can be identified by simple biasing techniques [41,29]. In this section,
the noise measurement method used in this study is presented. This method used the noise
equations obtained in [41]. As described in this section, it is found by this method that the
dominant l/f noise source in both TIN3 and TOUT is the surface recombination type, and
is located between the emitter and the base. By the same method, it will be shown later in
Chapter 4 that the low-frequency noise source of transistors used for the forward-bias-
stress study is also dominated by the surface recombination 1/f noise.

The noise power spectral density was measured at room temperature by using a
Hewlett-Packard 3561A Dynamic Signal Analyzer and averaging 200 sampling results.
The frequency region measured was from 1 Hz to 100 KHz. The Hanning filter shape
(window) of the HP 3561A was chosen in processing the data. The bandwidth was 375
ner when the noise measurement was performed from 1 Hz to 100 Hz, 37.5 Hz when the
noise measurement was performed from 100 Hz to 10 K Hz, and 375 Hz when the noise
measurement was performed from 250 Hz to 100 KHz. In order to reduce the effect of
noise sources other than the test transistors, wire-wound resistors and battery power
supplies were used in the noise measurement circuit.

By using the common-collector bias circuit as described in Figure 2.3 (b), the

emitter voltage-noise power spectral density (S V5) has the following form

33

S _ [6: 43(4) +RB)]251b, +16: “b +RB]ZSIce +(l3+l)21§Sq,
V5 ' 2
Z

 

x1233, (3.1)
with
Z=RB+rg +r,,+([3+1)(RE +re). (3.2)
If a large RE is chosen in the bias circuit for this noise measurement, such that (B+1)RE >>
R3 + r], + r), +re and RE >> re, , then
SVE =1rn/13-(n, +RB)12S1,, urn/(3+0), +RB)/m251,, +4235... (3.3)
Here, we assume [3 >> 1.

For a given n-p-n transistor, SIbe can be attributed to the combined effect of base
diffusion l/f noise and surface recombination 1/f noise. However, usually one type of 1/f
noise sources will be dominant. By checking the current (13) dependence, one can
determine the dominant contributor. Slbe has a dominant diffusion noise if SIbe cc [3. The
surface recombination noise is dominant if SIbe oc (IB)7, with y z 2. On the other hand, S1“,
comes from the emitter diffusion 1/f noise and should be proportional to the current IC.
S", is attributed to the base series resistance noise and has a fixed magnitude. However, as
shown in Equation 3.3, the third term in SVE which includes S", will show its current
dependence as 132. The steps for checking the dominant noise source in SVE are presented
as the following.

By fixing the base resistance (RB) and changing the emitter resistance (RE), the
bias conditions of the common-collector circuit as shown in Figure 2.3 (b) can be changed,
and the current dependence of SVE thus can be checked. There are three bias conditions
checked for a given device in our study. For example, the base-emitter bias (VBE) can
vary as 0.78, 0.8 and 0.82V with a constant base-collector bias (VBC) of -1.5V. For both
TIN3 and TOUT devices, these bias conditions correspond respectively to R5 = 510 KO,
200 K52, and 100 K!) with a constant R3 = 100 K!) used in the common-collector bias

circuit with VEE = 36 V and VCC = 1.5 V. If SVE happens to have a current dependence of

34

132 (or 132), this means the base surface recombination noise, the base series resistance
noise, or the combination of these two noise sources is dominant in SVE. In this case,
further analysis has to be made. By examing Equation 3.3, one will find that for a fixed 13
value, the contribution of Sn, to S VE is a constant, but that of Slbe to 5V3 will depend on
the value of R3. If R3 >> (I), —r,r/[3), SVE is approximately proportional to R32.
Consequently a fourth noise measurement must be performed with one of the three bias
conditions used before for checking the current dependence, however, with a different
combination of R3 and R3. For example, for a TIN3 device the fourth measurement can be
made with VBE = 0.82 V and VBC = -1.5 V by biasing with a smaller R3 (= 51 K0) but a
higher R3 (z 100.5 KQ). It is noted that this R3 value (= 51 K52) should be much larger
than (I), -r,,/fl). If S V5 from the fourth measurement is the same as that from the third
measurement, then we know that S,,, has a dominant effect on SVE. If S VE from the fourth
measurement is deceased and proportional to R32, then the surface recombination Sjbe is
dominant. Otherwise, one would conclude that both Sn, and the surface recombination
Slbe have appreciable effects on SVE, and their respective effect can be further decided by
comparing the results from the third measurement with that from the fourth measurement.

Figure 3.5 shows a set of measurements of the noise power spectral density on a
TIN3 device under different bias conditions: VBE = 0.78, 0.80 and 0.82 V with a constant
VBC = -1.5 V. Under the same bias conditions as the third measurement, VBE = 0.82 V
and VBC = -1.5 V, Figure 3.6 also shows that the noise power spectral density is
decreased to a quarter of the magnitude obtained in the third measurement when R3 is
decrease to half of the value used in the third measurement. Figure 3.7 shows the
quadratic current dependence of the noise power at 1 Hz. The results confirm that the
surface recombination Slbe is the dominant noise source in TIN 3 devices.

Figure 3.8 shows three measurements of the noise power spectral density on a
TOUT device under the same bias conditions as Figure 3.5: VBE = 0.78, 0.80 and 0.82 V

with a constant VBC = -1.5 V. Under the same bias conditions as the third measurement,

Sve

35

TIN3 (80)

10-11

10‘12

10-13

10‘1Li

 

 

 

10-15 ' I T Y Y i r r l r v T v r l
100 101 10a 103 10‘+ 105

FREQUENCY

Figure 3 .5: A set of three measurements of the emitter noise power spectral density on a
TIN3 device under different bias conditions: VBE = 0.78, 0.80 and 0.82 V with

aconstant VBC = -1.5 v.

Sve

10-10

10-11
\

10-12

10-13

10-1%

10‘15

36

TIN3<EO> Ube=0 BEU

 

 

 

r1*‘1*'1*fffir1
100 101 10a 103 10‘+ 105

FREQUENCY

Figure 3.6: Two measurements of the emitter noise power spectral density on the same

TIN3 device with its noise levels as shown in Figure 3.5. These two
measurements are made under the same bias conditions, VBE = 0.82, and VBC

= -l .5 V with a difi‘erent combination of R3 and R3.

37

 

 

 

10%0 TIN3<80>
@
> 10”14
U)
10”? . *fi , 1
10‘5 10‘* 10‘3

Figure 3.7: The quadratic current dependence of the noise power at 1 Hz for a TIN3

device.

38

VBE = 0.82 V and VBC = -1.5 V, Figure 3.9 shows the noise power spectral density is
decreased to a quarter of the magnitude obtained in the third measurement when R3 is
decrease to half of the value used in the third measurement. Figure 3.10 shows the
quadratic current dependence of the noise power at 1 Hz. The results also confirm that the
surface recombination Slbe is the dominant noise source in TOUT devices.

Although it does not apply to TIN3 or TOUT devices, it is noted for the sake of
generality that if SVE happens to have a linear current dependence with [3 (or 13), this
means the base diffusion 1/f noise of SIbe: the emitter diffusion 1/f noise (51cc), or the
combination of these two noise sources is dominant in SVE. According to Equation 3.3, the
contribution of SIbe to SVE can be minimized if R3 is equal to r" - rb. Consequently, a
fourth measurement could be performed with the same bias conditions as the third
measurement used before for checking the current dependence, but with R3 chosen to be
equal to r” - rb. If the noise power measured in the fourth measurement is decreased
dramatically, then the base diffusion l/f noise is dominant. If the noise power measured in
the fourth measurement is almost unchanged, then the emitter diffusion l/f noise is
dominant. However, as noted, the transistors used in this study did not have a dominant
diffusion noise source. Instead, the quadratic current dependence indicates surface
recombination noise.

The noise measurement flow of the emitter-voltage power spectral density (S V5)
used for identifying the noise sources inside a given n-p-n BJT is summarized in Figure

3.11.

3.2.2 I-V Characterization

The I-V characteristics of the transistors being stressed were measured before any

stressing began and at cumulative stress times of 1, 4, 24, 100, 200, 500, and 1000 hours

Sve

39

TOUT (05)

10'101

 

 

10-15 1 T T v , I 1 w i v r I

FREQUENCY

Figure 3.8: A set of three measurements of the emitter noise power spectral density on a
TOUT device under difl‘erent bias conditions: VBE = 0.78, 0.80 and 0.82 V

with a constant VBC = -1.5 V.

Sve

TQUT<OS> Ube=0 BEU

10-11

10-12

10-13

 

10'1“+

 

 

10-15 ' ' I ' ' r * 1 w 1 T ' 1
10° 101 102 103 10"+ 105

FREQUENCY

Figure 3.9: Two measurements of the emitter noise power spectral density on the same
TOUT device with its noise levels as shown in Figure 3.8. These two
measurements are made under the same bias conditions, VBE = 0.82, and VBC

= -1.5 V with a different combination of RB and RE-

41

 

 

 

 

fie TOUTCOS)
10 —
,
01
m
1
!
10‘13 l T
10‘5 10‘“ 3 4
19

Figure 3.10: The quadratic current dependence of the noise power at 1 Hz for a TOUT

device.

42

 

Check 3v]; at three different bias conditions
BI, 82 and B3 to determine the current
dependence of SVE. (choose a large RE)

st oer; / \ 5.,E 0:13

Repeat SvE at B3 with

 

 

 

 

 

 

Repeat SvE at B3 with a .
different combination of R3 R33?“ and a drfferent
and RE. (R3 >> rb - r,,/ [3) RE.

SvE changed ? SvI3 decrease dramatically?

 

 

   

(unchanged)

’ Surface noise
51

be

 

Figure 3.11: The noise measurement flow of the emitter-voltage power spectral density

(SVE)~

43

during the stress. The I-V characteristics measured consisted of the following set of six I-
V measurements:

(1)1EBO forward, 0.0 V s V33 3 0.8 V and I < 1 mA,

(2) IEBO reverse, -2.0 V s V33 3 0.0 V,

(3) ICBO forward, 0.0 Vs V30 3. 0.8 V and I < 1 mA,

(4) 10130 reverse, -5.0V 3 V33 .<_ 0.0 V,

(5) 13, 1C with VBC = 0.0 V and 0 S V33 5 0.8, and I < 1 mA (Gummel plot),

(6) Family of curves, IC versus VC3 and 13.
Figure 3.12 shows the circuit configuration for each of the tests. Double contacts were
used for the emitter and the collector during device testing.

Measurements were performed with a Hewlett-Packard 4145B Semiconductor
Parameter Analyzer in the long integration time mode, except for the family of curves, for
which the medium integration time was used. The measurements were performed at T =
23 i 1 C in a temperature-controlled environmental chamber as shown in Figure 3.13. The
data collected was then transferred to a workstation where a database was created. The
characteristics studied most extensively were the common-emitter current gain and

Gummel plot curves.
3.3 DC Reverse-Bias Stress and Post-Stress Recovery

Previous work has shown that two critical bipolar junction transistors performance
characteristics, current gain (1133) and low-frequency noise level, can be degraded by
reverse biasing the base-emitter junction as described in Chapter 2. It has also been
previously reported that the degradation in gain can be recovered at least in part by post-
stress thermal annealing, and more recently, by application of a post-stress forward bias as
well [6,8,78]. In this section, a similar recovery for transistor low-frequency noise is

presented.

 

 

0 [lcso
[ 11:30
(a) I 11:30 (h) 1 cao
IC
4.
Von

 

 

 

 

(:1) Family of Curves

Figure 3.12: Circuit configuration for the I-V measurements: (a) I530 forward and
reverse, (b) ICBO forward and reverse, (c) Gummel plot, and (d) family of

CUIVCS.

45

 

‘I'hermon'on
Environmental

 

Chamber

 

HP 41453
Semiconductor -
Parameter
Analyzer

 

 

 

 

 

 

 

 

 

 

Test Device
in Low Noise - IEEE 488
Fixture Bus

 

 

 

 

 

Ethernet

 

 

MSU
Work Stations

 

 

 

Figure 3.13: Diagram for the I-V measurement setup.

TIN3 devices are used for this study. The reverse-bias-induced hot-carrier
degradation on gain and noise and the post-stress thermal annealing will be shown in
Section 3.3. 1. The forward-bias-induced post-stress recovery on both gain and noise levels
on TIN3 devices will be shown in Section 3.3.2. By comparing the thermal annealing
recovery of 1133 and noise with forward-bias-induced recovery of h33 and noise, estimates
are provided for the relative role of interface state generation and trapped electrons in the
degradation/annealing process. Finally, the gain degradation behaviors under AC stress
will be provided in Section 3.3.3 which shows that the AC stress including forward-bias

cycles produced less degradation than the AC stress without forward-bias cycles.

3.3.1 DC Reverse-Bias Degradation and Thermal Annealing

TIN 3 transistors were divided into two groups for this study. In the first group,
transistors were subjected to a reverse-bias stress for a longer stress time (up to 500
hours), and the post-stress thermal annealing was performed at various temperatures (fiom
150 C to 240 C). Only I233 changes were monitored for the devices in the first group. In
the second group, transistors were subjected to the reverse-bias stress for a shorter stress
time (up to 100 hours), and the post-stress thermal annealing was performed only at 240
C. Both h33 and low-frequency were observed for the devices in the second group. For
both groups, the reverse-bias stress was applied to the base-emitter junction with the
collector-base junction shorted. The stress voltage is -4 V which is below the breakdown
voltage of approximately -5 V. The stress was interrupted for measurements at 1, 4, 24
and 100 hours for both groups and also at 200 and 500 hours for the first group.

The Gummel plots and the h33 degradation of the transistors in the first group, as
illustrated in Figure 3.14, 3.15 respectively, indicated that h33 degradation was due to an
increase in base current with the collector current remaining unchanged. The increase in

base current due to stress is particularly apparent at low values of V33. At low values of

47

junction voltage, the junction current due to diffusion and drifi is small compared to the
stress-induced leakage current. At V33 = 0.6 V, 500 hours of stress causes a reduction in
1133 to 36% of its original value and at V33 = 0.8 V, a reduction in h33 to 82% to its
original value.

The post stress thermal annealing was performed at ambient temperatures of 150,
175, and 240 C after 500 hours of reverse-bias stress. The annealing experiments were
interrupted at pre-selected times so that the I-V characteristics could be measured to
determine the recovery rate of the current gain. The recovery of the normalized current
gain (gain post-annealing / gain pre-annealing) at V33 = 0.6 V is shown in Figure 3.16.
The recovery is due entirely to a reduction in base current since the collector current is
unchanged by the annealing procedure. The thermal activation energy for this annealing
process is in the range of 1.2 to 1.5 eV, which is comparable to the value of 1.6 eV
reported in earlier work by McDonald [2]. For each annealing temperature, the largest
recovery occurred during the earlier portion of the annealing process. Complete recovery
of the gain was not observed at any of the time/temperature annealing combinations
investigated here. An 85% recovery was achieved after annealing for 700 hours at 240 C.
However, saturation of current gain recovery is not observed over the time scale of the
study.

For the second group, both the gain and the noise level were investigated. The
collector-voltage noise power spectral density (S VC in Equation 2.12) was measured. The
measurement circuit is under the common-emitter configuration, as shown in Figure 2.3
(a), with zero R3 and a large R3. Because the dominant noise source in a TIN3 device is
the surface recombination type located between the base and the emitter (Slbe), according

to Equation 2.12 the magnitude of S VC can be written approximately as

R 2 2
VC =EZ—Lkg2—XSIb . [3.4]
(RB +r1r) e

48

 

 

 

 

10'2
10" —
’01:
(Amp)
10-10 _
10‘14 —1 -' '\
o 1.2

 

Figure 3.14: Average Gummel plot for a population of 12 devices at various stress times
(0 to 500 hours) for devices reverse stressed with V33 = -4 V and V3c = 0 V
at 23 C.

49

 

80

hFE

 

 

 

 

0 0.2 0.4 0.6 0.8 l
VBE(V0“)

Figure 3.15: h33 vs. V33 for the data shown in Figure 3.14.

1.2

50

 

 

2.5
2 _
Normalized 24°C
hrs
v,£=o.6v 175 C
1.5 .—
150 c
1 ...
l l

 

 

1 1
10° 101 102 103 10‘ 10’
Armani; Time (min)

Figure 3.16: 1133 recovery of degraded transistors shown in Figure 3.14 as a result of post-
stress thermal annealing at temperatures of 150, 175, and 240 C. Complete

recovery would correspond to a normalized 1133 equal to 2.75.

51

Consequently, the magnitude of Sjbe can be carried out by measuring 51/0 In agreement
with previous studies described in Chapter 2, a significant increase in l/f noise power
spectral density after reverse-bias stress was observed, as shown in Figure 3.17. Figure
3.18 showed the noise was reduced almost to the pre-stress level after 240 C annealing for
60 hours. The stress/annealing results for both gain and noise level of the devices in the
second group are summarized in Figure 3.19. The 1133 reduced monotonically with time to
60% of its initial value afier 100 hours of stress, and then, recovered to 89% of its original
value after 60 hours of thermal annealing. Under the same conditions, the noise level
increased to 4.6 times the original level after 100 hours of stress, and after 60 hours of
thermal annealing, noise reduced to 1.63 times the original level.

It is generally hypothesized that the physical cause of reverse bias stress induced
degradation in modern BJT's can be due to two mechanisms. The Si-Si02 interface may be
damaged, resulting in an increase in the number of interface states. Secondly, carriers may
be trapped in the oxide, either by surmounting the Si-Si02 barrier, or by tunneling through
the barrier to trap states in the energy gap of the oxide. From this view, the source of
post-stress recovery may be due to (1) annihilation of interface states, (2) change in
occupancy of interface states, and (3) detrapping of electrons from oxide traps. However,
the thermal annealing results alone do not distinguish among these possibilities. In order to
add fiirther insight into the degradation and recovery mechanisms, a means of recovery
which does not involve thermal activation was investigated, as described in the next

subsection.

3.3.2 Forward-Bias Induced Recovery

Two groups of TIN3 devices were used in this study. For the first group, TIN3

devices were degraded by a -4 V base-emitter bias for 300 hours at 23 C without

interruption. As for previous cases, the collector-base junction was short-circuited. Then

52

 

 

 

10'"
. + : Ohours
: . e- : 1hours
‘ ’ -v- : 4 hours
_ 4..- : 24hours
10.20 REE“ . + :100hours
515: 21 i r
10' — ‘N.
Wm) = .
K.
10‘22 2
10‘23 1
10° 10‘
Frequemy (Hz)

Figure 3.17: The noise power spectral density measured at various stress times ( o to 100

hours) for a TIN3 device reverse bias stressed with V33 = -4 V and V33 = 0

Vat 23 C.

 

53

 

 

 

 

 

10‘l9 —
A
10’20
s
012711sz ‘
10‘22 —
10‘23 I
10° 101 102
Beam (Hz)

Figure 3.18: The noise was reduced almost to the pre-stress level afier 240 C annealing

for 60 hours.

 

 

 

 

 

 

1 101
10 Stress Annealing
<—-————>
3“ -
Normalized SI“ Normalized hp;
8130112 1 q-a—l VBB=0°6V
(Plotted as I) .............. (Plotted as U)
B .......
—r —1
10 1 1 1 1 1°
0 20 40 60 80 100 160
Tune (hours)

Figure 3.19: DC reverse stress and post-stress thermal annealing effects on the normalized
1133 and normalized low-frequency noise levels 51,, (normalized to the PRE-
STRESS values). The ratio of the post-annealing 1133 (noise) to post-stress
1133 (noise) is 1.48 (0.35).

55

three post-stress recovery experiments induced by a 0.8 V forward bias were performed.
Only 1133 was monitored for the devices in this group. For the second group, both the gain
and the noise level were investigated. The stress was again made by a -4 V bias on the
base-emitter junction for 100 hours at 23 C without interruption. Then the post-stress
recovery by a 0.8 V forward bias on both gain and noise levels was investigated. Again,
the collector-voltage noise power spectral density (Sr/C) was measured.

In the first group of TIN3 devices, three forward-bias-induced recovery
experiments were performed at 23 C. In the first, degraded devices had sequential
Gummel plots measured with intervals between measurements of five minutes for a total
of ten measurements. During the measurements, the base-emitter junction experienced a
forward-bias increasing from 0 V to 0.8 V over a time period of 50 seconds. During the 5
minute time period between measurements the device was not biased. It is noted that the
current at 0.8 V is sufficiently small to avoid appreciable self heating of the device since
the power dissipated in the device at 0.8 V bias is 0.1 mW. For the emitter dimension for
TIN3 devices, the thermal resistance can be calculated as 1.2 C/mW [80]. The second
experiment was identical to the first except that the time interval between measurements
was 8 hours. In the third experiment, a steady bias of 0.8 V was applied to the base-
ernitter junction with the base-collector junction short circuited. In this experiment the bias
was interrupted every 5 nrinutes and a Gummel plot was measured for a total of 10
measurements and 50 minutes of forward-bias time.

The results of the three experiments are shown in Fig. 3.20. Significant recovery is
observed in all 3 cases with no gain change in the control device which had received no
previous reverse-bias stressing. Compared to the originally degraded value, the normalized
1133 at V33 = 0.6 V increases by approximately 15% after 10 measurements with a 5
minute interval between measurements. When the time interval is increased to 8 hours,
essentially the same result is observed. This indicates that there is not appreciable

spontaneous recovery between measurements on these time scales, but that the observed

56

1 .25

 

At = 5 minutes, bias = 0.8 V

Normalized

hrs
VBE=O.6V

 

 

 

 

 

Figure 3.20: Forward-bias induced 1133 recovery under various recovery conditions. The

measured 1133 of a control device is also shown for comparison.

57

recovery in gain is due to the measurement process. In the third experiment, a larger gain
recovery is observed with a 22% recovery. This may be interpreted as being a result of a
longer exposure to forward-bias than in the first two experiments. It is also noted that, in
contrast to the thermal annealing results, the gain recovery saturates with increasing time.
The forward-bias gain recovery does not seem to involve interface states. If the
gain recovery is due to a change in population of fast interface states as a result of simply
shifting the Fermi level during forward-bias, then it should also be possible to return the
states to their original post-stress populations by applying a reverse bias to shift the Fermi
level in the opposite direction. Such a repopulation would be expected to occur on a
similar time frame as that required for forward-bias gain recovery. However, this was not
observed experimentally. Reversing the band bending by a subsequent reverse biasing of a
device for 5 minutes does not undo the current gain increase achieved by forward bias gain
recovery. Also, the forward-bias induced gain recovery is maintained over a long time
period. For example, the 15% gain recovery shown in Fig. 3.20 drops to about 11% after
4 weeks of storage at room temperature. Therefore the forward-bias induced gain
recovery is robust with regard to subsequent bias and changes in band-bending, as well as
with time. This indicates that the recovery is more likely due to detrapping of oxide
trapped carriers. Such detrapping could be caused by field assisted tunneling aided by the
oxide electric fields present during forward-bias [79]. However, since only a partial gain
recovery (approximately 20%) is achieved and because the gain recovery saturates, oxide
trap states would appear to be the cause of only a fi'action of the current gain degradation.
In order to investigate the effect of forward-bias on l/f noise recovery, a sequential
two-step experiment was performed on TIN3 devices in the second group. In the first
step, the 1/f noise of the transistor was measured with the transistor biased at 0.72 V. In
the second step, the device is forward biased at 0.8 V for 20 minutes and the 1/f noise is
re-measured. Gummel plots are also measured after each noise measurement as illustrated

in the test sequence shown in Fig. 3.21. This two-step process was repeated several times

58

G=Gummelmeasurernent(v =OtoO.73Vforlrninute)
N = Noise measurement ( V = 0.72 V for 20 minutes )
F = Forward-bias recovery ( VBE=0.8 V for 20 minutes )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V
BE
G N G F G N G F G N G F G N G
Time
[1 [2 l3 14 15 [6 1.7 18

Figure 3.21: The test sequence for an investigation of 1/f noise recovery due to post-stress

forward bias.

59

for a given device. Ideally, the noise measurements would be made at as low a bias value
as possible, so that bias induced recovery does not occur during the noise measurement
itself. The value of 0.72 V represents a compromise between this concern and noise
measurement sensitivity considerations. The value of forward-bias during the recovery
part of the measurement should be higher than the one during the noise measurement, but
not so high as to introduce thermal effects. Again, the value of 0.8 V was arrived at as a
compromise between these two considerations.

Figure 3.22 shows that there is in fact recovery of 1/f noise caused by the forward-
bias. The l/f noise for an unstressed device when measured at V33 = 0.72 V is less than
our measurement resolution 1023 AZ/Hz. Consequently, as was the case for current gain
recovery, forward-bias alone produces only a partial recovery of noise degradation. The
experiment illustrated in Fig. 3.21 produces information both on current gain recovery and
noise reduction, and the effect of forward bias on both of these quantities is shown in
Figure 3.23. It is noted that forward bias alone produces a much smaller gain recovery
than thermal annealing. Also as shown in Figure 3.23, a saturated h33 recovery was
observed. However, saturation of noise recovery is not observed over the time scale of
this study. This indicates that a portion of the recoverable states affects noise properties
but not gain. For control devices, which were not stressed, no change in h33 or noise was

observed.

3.3.3 AC Stress

Based on the forward-bias induced gain recovery observation, it would be
expected that AC stress that includes forward-bias cycles should produced different results
than AC stress without forward-bias cycles. To investigate the effect of non-DC stressing,
transistors were stressed under two conditions. In the first group of six transistors, a 1

KHz alternating reverse-bias to forward-bias (-4 to +1 V) pulse train was applied to the

 

 

 

 

 

10'21
-I- : 0min
€- : 20mm
a. -- : 40min
4 a + : 60mm
1 .
S». _22 . 5‘
(A2/Hz)10 -
10-23 I
10° 101 102

Frequency (Hz)

Figure 3.22: Low-frequency noise reduction at various recovery time (0 to 60 minutes)

due to forward bias applied to the emitter-base junction.

61

 

 

 

 

7.5 45
6.5 .—
5,“ 5.5 —
at 10 Hz h”
CKIAJ-zallz/IIZ) 3-4“) I/gg’==(1(5‘/
(Plotted as I) 4.5 —( (Plotted as CD
3.5 .4
2'5 1 1 1 1 1 1 1 1 35

I] (2 13 l4 (5 ‘6 l7 (3

Figure 3.23: F orward-bias induced recovery effects on normalized 1133 and normalized
low-frequency noise levels 51,, (normalized to the POST-STRESS values).
The ratio of the post-recovery h33 (noise) to post-stress 1133 (noise) is 1.24
(0.66).

62

base-emitter junction with the collector-base junction shorted. The duty cycle was 50% so
that the devices were in forward-bias for half the time and reverse bias for half the time. In
the second group, an alternating reverse-bias to zero (-4 to 0 V) pulse train was applied so
that the devices were unbiased for half the time and reverse biased for half the time. Self
heating of the device is in both cases not sufficient to cause thermal annealing effects.
With 1 V forward bias on the base-emitter junction, the device power dissipation is 10
mW. The thermal resistance is 1.2 C/mW so the resulting temperature rise of 12 C is well
below the temperature required for thermal annealing effects as reported in Section 3.2.1.

Previous reports on AC stressing have indicated variable results. In one report, a
significant difference in degradation between stress cycles which included forward-bias
cycles and stress cycles without forward-bias was reported [6]. However, a second study
did not observe any difference between the two stressing modes within the time of study,
which was about one hour of reverse—bias-on time [78]. Our results for AC stressing for
up to 2000 hours are shown in Fig. 3.24. For the first 100 hours, no apparent distinction is
observed between the two stressing conditions. However, with longer stress times, a
decrease in degradation rate is observed for the devices receiving forward-bias pulses.
After 2000 hours, h33 has degraded to 26% of the original value for reverse bias only
stressing, and has degraded to 45% of the original value for stressing which included
forward-bias pulses.

When comparing these results with those of Section 3.3.2, this would indicate that
the difference is due to a lower trapped electron effect in those samples receiving forward-
bias pulses. The degradation to 26% of the original value is interpreted as being due to the
combined effect of an increase in interface states and an increase in trapped-electrons. The
degradation to 45% of the original value is interpreted as being due to an increase in
interface states, and fewer trapped electrons. The data also suggests that degradation due
to interface states may accumulate more rapidly than does degradation due to trapped

electrons. For short stress time, our results show that there is negligible difference

63

 

1_1

0.8 -2
Normalized

hrs
v” = 0.6 v 0.6 _

0.4 —

 

0.2

 

 

 

l l l l
0 400 800 1200 1600 2000
Stressing Time (hours)

Figure 3.24: AC stress results with and without forward-bias (1.0V) cycles. The AC signal
was applied to the E-B junction with the B-C junction shorted. The fiequency
of the AC signal is l KHz and the duty cycle is 50%. The power dissipation is
10 mW during the forward-bias cycles which will not cause thermal annealing

since the device thermal resistance is 1.2 C/mW.

between the two stress conditions, which is consistent with [78].

3.4 Voltage Dependence of Reverse-Bias Stress

In previous sections, the reverse-bias experiments were performed under the
conditions of V33 = -4 V and V3c = 0 V. In this section, the results of reverse-bias stress
under various stress voltages are presented. The stress devices used for this study are

TOUT devices.

3.4.1 Experimental Methods

The emitter-base junction of TOUT devices was reverse-bias stressed with the
collector-base junction shorted at room temperature. A voltage divider circuit designed by
[87] and shown in Figure 3.25 was used to perform stress under -3.5 V, -4.0 V and -4.5
V. For -3.5 V and -4 V stress, the total stress time was 200 hours, and for -4.5 V stress,
the total stress time wais 24 hours. The stress was interrupted for both noise and I-V
measurements at l, 4 and 24 hours for all three stress conditions, and also at 100 and 200
hours for -3.5 V and -4 V stress.

A set of three emitter low-frequency noise power spectral densities from 1 Hz to
100 Hz was measured before and after stress. The noise was measured under the
common-collector configuration as described in Section 3.2.1. This set of three noise
measurements performed under three different bias points allows one to check the current
dependence of the noise power (and consequently, the noise source inside the device). It is
noted that the forward bias can induce post-stress recovery as described in Section 3.3.2.
Consequently, the forward bias on the emitter-base junction during noise measurements
should be kept as low as possible to minimize the forward-bias induced effect. However,

the forward bias can not be arbitrarily low, or the 1/f noise will be too small to measure.

65

 

 

 

 

 

 

 

 

 

VCC=5V
0
3R1
4.5V
1R2
4.0V 2 = i-
< R3
?
35V _— _ _

 

 

 

 

fiN‘

 

 

 

 

 

 

Figure 3.25: The voltage divider circuit designed by [87] used to perform reverse-bias
stress under various stress voltages. The values of resistors are : R1 = R2 = R3

= 47 Q, R4 = 317 Q, allothers are 100 K52.

Under these concerns, the three measurement bias points were chosen as VBE = 0.74, 0.76
and 0.78 V with a constant VBC = -1.5 V. These bias conditions correspond respectively
to varying RE = 2 MO, IMO and 510 K!) with a constant RB = 100 K!) used in the
common-collector bias circuit with VEE = 36 V and VCC = -1.5 V, as shown in Figure 2.3
(b). The pre-stress noise measurements on TOUT devices under these three bias points
show that the noise power has a quadratic current dependence. This indicates that the
dominant noise source is the surface recombination type, which is consistent with the
results described earlier in Section 3.2.1. Afier each noise measurements, a Gummel plot
with VBE s 0.6 V was measured.

A set of device I-V characteristics were also measured after the above-mentioned
set of noise measurements. The device I-V characteristics are monitored by the following
set of three measurements:

(1) Gummel plot, [3 and 1C with VBC = 0.0 V and 0 _<_ VBE s 0.6 V,

(2) 11380 reverse, stress voltage 3 VBE s 0.0 V,

(3) 11580 forward, 0.0 V s VBE .<_ 0.6 V.

It is noted that the forward bias on the emitter-base junction during I-V characterization is
only 0.6 V, which is expected to cause a negligible effect on post-stress recovery. The

experimental flow for this study is summarized in Figure 3.26.
3.4.2 Results

The normalized hFE for devices under various stress voltages is shown in Figure
3.27, which indicates the hFE degradation caused by reverse bias stress and also the effects
of by; recovery induced by the forward bias used for performing the post-stress noise
measurements. It is clear to see that the forward-bias induced recovery plays an important
role in this degradation study. For example, the hFE dropped to 83.9% of its initial value

after 1 hour of -4 V stress, and recovered to 88.9% of its initial value after 15 minutes of

67

 

Initial noise measurements under three
bias points and initial I-V characterization
including a set of three measurements:
Gummel plot, 1530 reverse and forward.

4

Reverse-bias stress on TOUT devices with
stress voltages of -3.5, -4.0 and -4.5 V for
pre-selected stress time interval.

 

 

 

 

 

 

 

 

.1

i

Gummel plot measurement
Repcat (V35 5 0.6 V)

 

till

three
noise
measurements -

are
done.

 

 

 

 

The noise measurement under one of the
three bias points.

 

 

 

 

 

 

Y

I-V characterization including a set of three
measurements: Gummel plot, 1530 reverse
and forward.

 

 

 

 

 

 

 

Figure 3.26: The experimental flow for the reverse-bias stress under various voltages.

0 SU

NQRMQLIZED HFE at UBE

850

700

550

L+00

850

100

Figure 3.27: Normalized hFE at VBE = 0.6 V for TOUT devices stressed under -3.5, 4.0

 

 

REUERSE STRESS ON TOUT'S
4:99 :5 u _ 3 5 U
0
0
~ i—% 00
$—% EU
1 1 1 * 1
10‘ 10° 101 108 103
TIME

and -4.5 V.

69

0.78 V forward bias introduced by the first noise measurement, to 89.1% of its initial
value after 15 minutes of 0.76 V forward bias introduced by the second noise
measurement, and finally to 89.4% of it initial value afier 15 minutes of 0.74 V forward
bias introduced by the third noise measurement. It is noted that the data presented in
Figure 3.27 is measured at VBE = 0.6 V, which is different from the bias conditions of
VBE = 0.74, 0.76 or 0.78 V used for the set of noise measurements. However, a similar
hFE behavior will be expected to be observed for those bias conditions.

The noise measurements of -3.5 V stressed TOUT device are shown in Figures
3.28 to 3.30. Figure 3.28 shows the noise results measured under the bias conditions of
VBE = 0.78 V and VBC = -1.5 V. Figure 3.29 shows the noise results measured under the
bias conditions of VBE = 0.76 V and VBC = -1.5 V. Figure 3.30 shows the noise results
measured under the bias conditions of VBE = 0.74 V and VBC = -1.5 V. A fluctuation of
the noise data is observed under -3.5 V stress. The noise magnitude initially decreases,
then increases, then decreases again as stress time increases. The reasons for this behavior
are unknown. However, because the degradation rate is much slower in -3.5 V stress than
that in either of the other two stress voltages, the forward bias may have a more significant
effect on these noise results.

The noise measurements of a -4.0 V stressed TOUT device are shown in Figures
3.31, 3.32 and 3.33, which represent respectively the results measured under the bias
conditions of VBE = 0.78, 0.76 and 0.74 V with VBC = -1.5 V. Also, the noise
measurements of -4.5 V stressed TOUT device are shown in Figures 3.34, 3.35 and 3.36,
which represent respectively the results measured under the bias conditions of VBE = 0.78,
0.76 and 0.74 V with VBC = -1.5 V. It is noted, as expected, that a larger noise increase
will be observed if a device is stressed under a higher reverse bias. For example, under the
measurement bias conditions of VBE = 0.74 and VBC = -1.5 V (Figures 3.32 and 3.35),
the noise power at 1 Hz increases to 9.4 times the initial value after 24 hours of -4 V

stressed, but to 124.2 times the initial value after 24 hours of -4.5 stress.

Sve

7O

TQUT(-3 5U STRESS),UBE=O 78U

 

lnrtral

 

 

10‘13— 0 1 hr
A L1 hrs
4 Y 8L1 hrs
X 100 hrs
1 o 200 hrs Y
10‘“+ . . 1 . , 1
10° 101 10a

FREQUENCY

Figure 3.28: The emitter noise power spectral densities afier different times of -3.5 V

stress. The noise measurements are performed under the common-collector

configuration with the bias conditions of VBE = 0.78 V and VBC = -1.5 V.

71

1041_ TOUT(—3 50 STRESS),UBE=0 76U

Sve

 

D lh1t1a1

 

 

10_“+‘ 0 1 TWV
A R hrs
Y 2% hrs
X 100 hrs
0 800 hrs
10‘1'5 . es 1 .
m° 1m m3

FREQUENCY

Figure 3 .29: The emitter noise power spectral densities after different times of -3.5 V
stress. The noise measurements are performed under the common-collector

configuration with the bias conditions of VBE = 0.76 V and VBC = -1.5 V.

Sve

w'“—

72

TQUTC-B 5U STRESS>,UBE=O 7%U

     

D lhrtral

 

 

10”“h 0 1 hr
A R hrs
Y 8% hrs
X 100 hrs
0 800 hrs
10-15 fl 1 fl 1
m° 1w m3

FREQUENCY

Figure 3.30: The emitter noise power spectral densities after different times of -3.5 V

stress. The noise measurements are performed under the common-collector

configuration with the bias conditions of VBE = 0.74 V and VBC = -1.5 V.

Sve

73

TQUT(-% 0U STRESS).UBE=O 78U

     
 

 

 

10'9 —
10‘10)
A - ‘ e
10'114 ‘ "V \s;
a , ‘ \.
6
10-18 _, I...\¢\
D lhltlal
10‘134 O 1 hr
A R hrs
Y 8% hrs
X 100 hrs
0 800 hrs
10-1% ' ' 1 1 w 1
100 101 102
FREQUENCY

Figure 3 .3 1: The emitter noise power spectral densities after different times of -4.0 V
stress. The noise measurements are performed under the common-collector

configuration with the bias conditions of VBE = 0.78 V and VBC = -1.5 V.

74

TQUT(-% 0U STRESS).UBE=O 76U

-10
10 7
Q
) 9 ;\
10-11 ‘1 '9 -‘.
A “
j T\ 9
\,

‘\

Sve

 

 

 

10.“+ ' ' 1 ' ' l

FREQUENCY

Figure 3 .32: The emitter noise power spectral densities afier different times of -4.0 V
stress. The noise measurements are performed under the common-collector

configuration with the bias conditions of VBE = 0.76 V and VBC = -1.5 V.

Sve

10‘11

10-12

10-13

10'1'4

10‘15

75

TQUT(-% 0U STRESS),UBE=O 7%U

‘h

‘0

l 1

    

D Ihltlal
0 1 hr
A R hrs
Y 2% hrs
X 100 hrs
0 800 hrs

 

 

r r l ‘

FREQUENCY

Figure 3 .33: The emitter noise power spectral densities afier different times of -4.0 V

stress. The noise measurements are performed under the common-collector

configuration with the bias conditions of VBE = 0.74 V and VBC = -1.5 V.

Sve

10-10

10’11

10‘12

10‘13

lo'lLf

l
-<l>GE-l

76

TQUTC-R 5U STRESS),UBE=O 78U

    
 

1h1tlal
1 hr

L1 hrs
2L1 hrs

 

 

l I ”‘1

FREQUENCY

Figure 3.34: The emitter noise power spectral densities after different times of -4.5 V

stress. The noise measurements are performed under the common-collector

configuration with the bias conditions of VBE = 0.7 8 V and VBC = -1.5 V.

809

77

TQUT(—L+ 5U STRESS>,UBE=O 76k)

 

m‘m—

C

4

6 7‘

é &
a 3

10-11“ .9 I.)

1

1* e
-12 ‘ \‘3‘

10 E —‘ .'\ .5. 4‘5

    
 

 

 

m-m- D lhltral
0 1 hr
1 A L1 hrs
Y 8% hrs
l ._.1
10'H . . 1 - A A
m° m1 m3

FREQUENCY

Figure 3.35: The emitter noise power spectral densities after different times of -4.5 V
stress. The noise measurements are performed under the common-collector

configuration with the bias conditions of VBE = 0.76 V and VBC = -1.5 V.

Sve

78

TQUT(-% 5U STRESS),UBE=O 7%U

 

   
 

 

 

10-101
:
10_11.2. -"- g
C. e T 7
‘s‘
's‘
e
m‘m—
‘ _. 3" e e
0
10‘13— ‘ ~‘
3 lhltlal
10‘1”“ 0 l tar
A R hrs
Y 8% hrs
10-15 .T I l r Y 1
m° 1w m3

FREQUENCY

Figure 3.36: The emitter noise power spectral densities after different times of -4.5 V
stress. The noise measurements are performed under the common-collector

configuration with the bias conditions of VBE = 0.74 V and VBC = -1.5 V.

79
3.4.3 Discussion

When the bipolar junction transistors in this study are subjected to a sufficient
reverse-bias stress, hot-carrier induced degradation is clearly observed. It is generally
believed that the physical cause for such degradation is due to one of two mechanisms.
The Si-SiOz interface may be damaged, resulting in an increase in the number of interface
states. Secondly, carriers may be trapped in the oxide, either by surrnounting the Si-Si02
barrier, or by tunneling through the barrier to trap states in the energy gap of the oxide. In
the second case, the occupancy of previous existing interface states can be modulated by
band bending and a shifted Fermi energy. In either case, the resulting change in the
effective number of interface states causes a change of the surface recombination velocity,
and consequently changes of the BJT characteristics. For example, both the base surface
recombination current Ts and the surface recombination type 1/f noise S1,.“ can be
increased after a hot-carrier stress, as shown in Section 3.3 for TIN3 devices and 3.4.2 for
the TOUT devices.

The surface recombination current is proportional to the surface recombination
velocity and to the carrier concentration at the surface. The surface recombination velocity
[64] is equal to ov,,,N,-,, where o is the carrier capture cross-section with a value around
10‘16 cm2 depending on the type of carriers [90], v”, is the thermal velocity which is equal
to 107 cm/s at room temperature, and Ni, is the surface state density which can be
increased by the hot-carrier stress as described earlier. Consequently, we can write the
surface recombination current as the following fiom [89]

7. =qvm(a..An.+opAp.)AN.-.. (3.5)
where Ans and Aps are the electron and hole concentrations at the surface respectively
whose magnitude will depend on the bias condition, and 0,, and 0,, are the carrier capture

cross-sections for electrons and holes respectively. It is noted that the surface

80

recombination current is linearly proportional to the surface state density N”. As described

in Section 2.1.1, the surface recombination l/f noise has the following form

=.01(1s)2
rec _f AN“

 

1 (3.6)

By substituting Equation 3. 5 into Equation 3. 6 and also by assuming 0,, ~ op= o, the

surface recombination 1/f noise can be rewritten as

0.1
51,,- -—f-xq v,,,ol(An. Mp.) AN... (3.71

which also will be linearly proportional to Nit. Consequently, for a device subjected to a
reverse-bias stress, the resulting increase of the surface recombination current (211;) and
the resulting increase of the surface recombination 1/f noise (ASIrec) are both linearly
proportional to the resulting increase of the surface state density (ANH). In the other

words, the ratio between AS396 and ATS will have the following form

 

ASI 0.1
AIS f xqvthop ( )
with
2
=(AnS1 +Aps1) (3 9)
(A1132 +Aps2)

and is independent of AN“. By plotting ATS versus AS1rec, a straight line with a slope
equal to the right hand side of Equation 3.8 is expected. In general, the bias condition used
for performing the noise measurement to obtain ASI,“ can be different from that used for
performing the current measurement to obtain ATS. Consequently, in Equation 3.9 Ans 1
and Aps, correspond to the surface carrier concentrations under the bias condition used
for the noise measurement, and Ans, and Ap52 correspond to the surface carrier

concentrations under the bias condition used for the current measurement.

81

The above argument, which claims that the ratio between AS1rec and ATS is
independent of AN,-,, can be verified by plotting the results of TOUT devices subjected to
a reverse stress under various voltages as described in the previous section. Figure 3.37
plots the increased l/f noise at 1 Hz under the bias conditions of VBE = 0.74 V and VBC =
-1.5 V, versus the increased 13 measured under the bias conditions of VBE = 0.6 V and
VBC = 0 V (Gummel plot measurement) which is known as the surface recombination
current (A75). The l/f noise shown here is the surface recombination 1/f noise located
between the emitter and the base, SIbe, which is calculated by using Equation 3.3 from the
measured results of the emitter noise power spectral density under the common-collector
configuration (Figures 3.33 and 3.36). The stress conditions for obtaining these data are
with VBE = -4 or -4.5 V and with VBC = 0 V. It is noted that, as shown in Figure 3.37,
the increased base current (A13) and the increase surface recombination current (AS Ibe)
can be expressed by a linear relation as

LXI—1;" =a , (3.10)

where a is obtained as 2.14x10"14 A/Hz by using the least-squares fitting the experimental
data. If we substitute some numerical values into the left hand side of Equation 3.8, i.e. f =
1 Hz, q = 1.6x10'19 coul, v”, = 107 cm/s, o z 10'16cm2, and assume p is unknown, by
using a = 2.14x10'14 A/Hz the magnitude ofp can be estimated as 1.34x1015 cm3. It is
also worth noting that the above linear relation between A13 and ASIbe does not depend

on the stress voltages. The values of A] B and AS139 and the corresponding stress voltages

and times are shown in Table 3.1.

delta<SIbe> (X10T81)

82

 

 

TOUT
8 00‘
0
1 71'4
/
/
/
1a3~ //
/
/
/
/
/

114— //

/

/

/o
/
857 — //
m,’
/
X o
5713 //
/
/
l/ O -% 5U Stress
em6~ m , m
/
/
/
/ U
/
000 E3 1 1 1 T r fi
000 l 33 8 67 S 00 5 33 6 67 8 00

delta<lB> <><10‘8>

Figure 3.37: 4511).; versus A13 for TOUT devices stressed under -4.0 and -4.5 V. The base

current and the noise power are both measured under the bias conditions of

‘VBE=WIWIV2md‘&Kf=-L5\L

83

 

 

 

 

 

 

 

 

 

 

AIB (nA) Asa. (Io-23A2/Hz) Stress History
2.4 2.41 -4 V for 1 hr
6.2 25.33 -4 V for 4 hrs
13.0 11.02 -4Vfor 24 hrs
25.8 24.55 -4 V for 100 hrs
32.9 76.50 -4 V for 200 hrs
34.5 64.18 -4.5 Vfor 1 hr
47.5 96.78 -4.5 V for 4 hrs
73.6 175.38 -4.5 V for 24 hrs

 

 

 

 

Table 3.1: The values of A13 and “Mg used in Figure 3.36 and the corresponding stress

history.

CHAPTER 4
FORWARD-BIAS STRESS RESULTS

4.1 Device Description

Three kinds of silicon n-p-n transistors fabricated with different technologies by
IBM were used in this forward stress study, namely TIN3, TSEO3I and the Hemmert test
structure. TINB's were fabricated by conventional oxide isolation technology [81], as
described in Section 3.1, with emitter dimensions of 2.5x4.3 umz. TSEO3I's were
advanced technology devices, fabricated with polysilicon base contacts and side-wall
oxides, which had emitter dimension of 1.5x2.0 umz. Metal contacts to these devices
were not by first level metallization, but rather by means of metal studs through oxide vias.
Such studs serve to reduce electromigration induced stress directly over the transistor
contacts. The Hemmert test structure is a test structure reported by Hemmert [77] which
was designed particularly to investigate the electromigration induced compressive stress
efl‘ects. As shown schematically in Figure 4.1, seven identical transistors with emitter
dimensions of 2.5x4.0 umz have their emitter centered under and connected to a long
conductor which is 4 pm wide and 2 mm long. Only one transistor on the end of the series
of seven is electrically forward-bias stressed. As described in Chapter 2, a metal
accumulation can occur above the emitter region of this electrically stressed transistor
because of electromigration, and consequently a compressive stress can be built-up around
the metal accumulation region. Since the forward-bias-stressing current does not flow

through the conductor that contact the other six emitters, any change in the characteristics
84

85

 

 

BASE METAL
6 5 4 3 1
ENH 1 ”ER METAL EMITI'ER‘ CONT ACT

 

 

 

4...: 4.1. 1 - ELECTRON
:f FLUX

 

 

Figure 4.1: A schematic of the Hemmert test structure. Transistor #1 to #6 are separated
equally by a distance of 10 um. Transistor #7 which is 100 um away from

transistor #1 is not shown here.

86

of the other six transistors is attributed to electromigration induced compressive stress
effects in the common conducting line over the emitters. These seven transistors
essentially act as pressure sensors which sense the compressive stress along the long
conductor at 0 (region of metal accumulation), 10, 20, 30, 40, 50, and 100 um from the
region of the metal accumulation. All test dies from three kind of transistors, TIN3,
TSE03I and the Hemmert test structure, were mounted on ceramic DIP packages.

As described in Section 3.2. 1, the dominant l/f noise source of TIN3 devices was
verified to be the surface recombination type located between the base and the emitter.
The verification was done by checking the current dependence of the noise power spectral
density measured under the common collector configuration. The same verification
method was also performed on the new technology device TSEO3I. Figure 4.2 shows a set
of three measurements of the noise power spectral density on a TSE03I device under
different bias conditions: VBE = 0.77, 0.80 and 0.82 V with a constant VBC = -1.5 V.
These bias conditions correspond respectively to R5 = 510 KO, 200 KS), and 100 K!)
with a constant R3 = 100 K!) used in the common-collector bias circuit, referring to
Figure 2.3 (b), with VEE = 36 V and VCC = 1.5 V. Figure 4.3 shows the quadratic current
dependence of the noise power at 1 Hz. However, as described in Section 3.2.1, both the
surface recombination 1/f noise (Slbe) and the base resistance fluctuation 1/f noise (Srb)
have the quadratic current dependence. Consequently, in order to distinguish these two
noise sources inside a TSE03I device, a fourth noise measurement has to be made, which
will has the same bias conditions as the third noise measurement (i.e., VBE = 0.82 V and
VBC = -1.5 V), however, with a different combination of RE and RB. If the result fi'om the
fourth noise measurement is the same as that from the third noise measurement, then the
base resistance fluctuation l/f noise (Srb) is dominant. However, if the result from the
fourth measurement is changed and proportional to R32, then the surface recombination
l/f noise (S1,,e) is dominant. Figure 4.4 shows that the noise power spectral density of the

fourth noise measurement is decreased to a quarter of the magnitude obtained in the third

87

TSE031<#79)

m‘m—

A: Ube=0.82U
10*1— 0: Ube=0.80U
m: Ube=0.77U

Sve

10-13

10-1%

 

 

 

'15
10 "T‘frl ‘1"V"1

Figure 4.2: A set of three measurements of the emitter noise power spectral density on a
TSEOBI device under different bias conditions: VBE = 0.77, 0.80 and 0.82 V

with a constant VBC = -1.5 V.

TSEOBI<fi79>

 

 

 

 

10-11l
10'”31
m
>
on
J
10‘V31
10.“+ ll 1 1
10‘5 10‘” *0‘3

Figure 4.3: The quadratic current dependence of the noise power at 1 Hz for a TSEO3I

device.

TSEO3I<fi79> Ube=0,880

H II
t—AO
KO

E70
UU

10‘”- Y:

Sve

 

 

 

100 101 103 :33 10‘+ 105

FREQUENCY

Figure 4.4: Two measurements of the emitter noise power spectral density on the same
TSEOBI device with its noise levels as shown in Figure 4.2. These two
measurements are made under the same bias conditions, VBE = 0.82, and VBC

= -l.5 V with a different combination of R3 and RE.

9O

measurement when R3 is decrease to half of the value used in the third measurement. The
results confirm that the surface recombination S Ibe is the dominant noise source in TSEO3I

devices.
4.2 Experimental Methods

Transistors from the above-mentioned three technologies were stressed with the base-
collector junction short-circuited and the base-emitter junction forward biased. The stress
was interrupted at the pre-selected times to measure the I-V characteristics and, for some
devices, to measure the noise characteristics additionally. Device measurements were
performed at a temperature of 23 C i 1 C in an environmental chamber. The method for I-
V characterization was described earlier in Section 3.3.2. However, in this forward-bias
stress study the I-V measurements with reverse-biased junctions (Icao reverse and 1530
reverse) were not performed in order to eliminate the possibility of degradation due to
reverse-bias produced hot electrons. Consequently, the only potential source of hot
electrons are those produced by Auger recombination during forward-bias stress as
proposed in [1]. The noise measurements were performed under the common-emitter
configuration or under the common-collector configuration to obtain the collector noise
power spectral density (SVC) or the emitter noise power spectral density (S VE),
respectively. Since the dominant noise source has been verified as the surface
recombination type located between the emitter and the base (SIbe), the magnitude of Slbe

can be carried out fi'om either SVE or SVC by using the equations described below

3V, =[rn/fl-(rb mars]... (4.1)

2 2 2
R
VC =-———B B RC2 XSIb . (4.2)
(R8 +r1t) e

The above equations are also shown as Equations 3.3 and 3.4 in Chapter 3.

91

The stress conditions used for this forward-bias stress study varied a number of
parameters including stress time, stress temperature and stress current. All devices were
stressed with the base-collector junction short-circuited and the base-emitter junction
forward biased. Post-stress thermal annealing was also performed on selected devices.
These stress conditions and post-stress annealing conditions are listed separately below for
the three technologies. It is noted that the symbol 15 represents the stress emitter current

density.

(I) TIN3
(A) Current gain degradation study:
(1) IE = 105 A/cm2 at -75 C for 500 hours;
(2) 15 = 105 A/cm2 at 175 C for 500 hours;
(3) JE = 105 A/cm2 at 240 C for 750 hours;
(4) JE = 2 x r05 A/cm2 at 240 C for 500 hours.
(B) Noise characteristics study:
(1) JE = 2 x 105 A/cm2 at 240 C for 100 hours;
(2) JE = 2 x 105 A/cm2 at 23 C for 100 hours, and then IE = 2 x 105 A/cm2
at 240C for 66 hours;
(3) JE = 2 x 105 A/cm2 at 240 C for 66 hours, followed by annealing at 240
C for 60 hours.
(11) TSE03I
(A) Current gain degradation study:
(1) 15 = 2 x 105 A/cm2 at 225 C for 2400 hours;
(2) 15 = 5 x 105 A/cm2 at 225 C for 500 hours;
(3) 15 = 5 x 105 A/cm2 at 175 C for 2500 hours.
(B) Noise characteristics study:

(1) JE = 5 x 105 A/cm2 at 225 C for 250 hours;

92

(2) JE = 5 x 105 A/cm2 at 225 C for 90 hours, followed by annealing at 225
C for 90 hours.
(111) The Hemmert test structure
(A) Current gain degradation study:
(1) JE = 5 x 105 A/cm2 at 200 C for 500 hours.
(B) Noise characteristics study:

( 1) JE = S x 105 A/cm2 at 200 C for 500 hours.

Control devices were also used which received temperature stress, but not
electrical stress. In addition, desk control devices were used which received neither
electrical or temperature stress, and were used to monitor the repeatability of the test
procedures. The results of stress effects and post-stress thermal annealing effects on both

gain and noise are shown in the following sections.

4.3 Stress Effects on Gain

TIN3 devices showed a pronounced and systematic gradual degradation of gain
with increasing stress time when subjected to a combination of high forward-bias current
and temperature. Fig. 4.5 shows the ratio IC/IB, or hFE, versus VBE and stress time as
obtained from the Gummel plots. The data represents an average of 12 devices which
were stressed simultaneously. However the gradual decrease with stress time is
representative of the degradation of the individual devices in the population as well. This
degradation is a result of an increase in base current and not a change in collector current.
For VBE = 0.6 volts, as shown in Fig. 4.6, the resulting gain degradation after 500 hours
of stress at 240 C is approximately 20% when the stress current is 2 mA/um2 and
approximately 10% after 750 hours when the stress current is 1 mA/umz. Stress was also

performed at the latter current with ambient temperatures of -75 C and 175 C; however,

93

80

 

hrs 40-

  

20—

iiififiil.
a
5

   

 

 

 

0 0.2 0.4 0.6 0.8 l 1.2
VBE(V0”)

Figure 4.5: Current gain vs. V33 for TIN3 transistors at stress times of 0, 1, 4, 24, 100,
200, 500 hours. The forward stress was done at 240 C with a current density
of 2 mA/umz.

1.1

 

 

 

 

+ l mA/tlm§ at -75 C
G- : l mwz at 175 C
-v- 2 1 "TA/«UN: at 7A0 C
+ :2m um at240C
1
Normalized «
hrs
VBE=O.6V
0.9 -—
0.8 l 1
10° 101 102 103

Stress Time (hours)

Figure 4.6: Normalized current gain (average current gain after stress/average current gain

before stress) of TIN3 transistors vs. stress time at various current levels and

ambient temperatures.

95

no degradation in gain was observed during the 500 hour time period of the test. The
gradual degradation and the temperature dependence is consistent both with
electromigration induced compressive stress and with Auger hot electron induced damage.
However, as discussed later, comparison with the Hemmert test structure indicates that
electromigration is present and at least partially is responsible for the behavior shown in
Figures 4.5 and 4.6.

For TSEO3I devices, the degradation was quite different than for TIN3 devices.
Figure 4.7 shows the result of forward-bias stress with 5 mA/um2 at a temperature of 225
C. No systematic change was observed up to 100 hours, but thereafter degradation in the
population of 10 devices was observed. In contrast to the results for TSEO3I technology,
the degradation for a given device was precipitous rather than gradual. Gummel plots of
devices which had begun to degrade showed a increased series resistance such that more
voltage was required to maintain a given current. Once degradation had begun, in about
30 to 40 hours the process culminated in an open-circuited transistor. This phenomenon is
shown in Figure 4.8. The time required for a 50% drop out of the population was
approximately 400 hours. The nature of the failure is indicative of electromigration, with
openings in the line initially producing an increase in series resistance until a line is
completely opened, finally producing an open circuit. Scanning electron microscopy
(SEM) confirmed this conclusion.

Further evidence of electromigration failure in TSE03I devices is found by
considering the results when the devices were stressed at 225 C with a lower current
density of 2 mA/umz. For this stress condition, the time required for 50% drop out was
approximately 2400 hours. This indicates a degradation phenomena which proceeds as the
current density squared, consistent with electromigration [17]. However for TSEO3I
devices there is no evidence for gradual gain degradation due either to electromigration

induced stress or to hot electrons.

 

 

 

 

 

 

 

200 L
150 ‘
hrs
vggzoov ‘00 “
so _
'0 r r
10° 101 102 103
Stress Time (hours)

Figure 4.7: Current gain of individual T813031 transistors vs. stress time for a stress
condition of 225 C and 15 = 5 MW.

97

END STRESS on TSEOBI (T=885>

 

 

 

10-8 1
10'3 j
10“+ :
10‘S —
i
10'6 j
10'? 9
m i
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‘ [I]: 800 hr S
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. 43,21.“ , . A: 39Ht hr S
rose. W5 hrs
~ ,, i .«0' ' «257’ X: L+13 hrs
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10 131‘”, or. Ioootlltmmmnflali; lib." "I”, I?“ i
illlimiimwwmr flilli ......
-. ........ T l
00 0 800 400 600 1 00 1 20
UBE

Figure 4.8: Gummel plots for a T813031 device (module #88) showing the onset of high

resistance and eventually an open circuit during stress with an emitter current

density of 5 mA/ltrn2 at 225 C.

98

Our gain degradation studies on the Hemmert test structure, as shown in Figure
4.9, confirm the results of Hemmert [77]. The first transistor which received the direct
electrical stress shows the largest degradation in hFE after 500 hours of stressing with 5
mA/um2 at 200 C. For the other six transistors, the gain degradation decreases with
increasing distance from the first transistor, consistent with expectations for
electromigration induced compressive stress. It is noted that since these six transistors
received no electrical stress, the possibility of hot electrons is ruled out. For all the
transistors in the Hemmert test structure, the decrease in gain is due to an increase in base
current. The magnitudes of the current gain vs. stress time at VBE = 0.6 V for all seven

transistors of the Hemmert test structure are listed in Table 4.1.

4.4 Stress and Thermal Annealing Effects on Noise

The low frequency noise characteristics were also measured for the three different
bipolar transistor technologies. The stress condition for the Hemmert test structure was
with a current density of S mA/um2 at T=200 C for up to 500 hours, and the noise levels
were measured using the common emitter configuration. Transistor #1, through which the
current flowed, showed a low frequency noise characteristic as shown in Figure 4.10. The
noise initially dropped for the measurement taken after one hour of stress. Subsequent
noise measurements taken at 4, 24, 100, 200 and 500 hours of cumulative stress showed a
noise level that increased with stress time. The noise characteristics of transistor #2 which
experiences a mechanical stress change only, i.e., no current flows through this transistor,
showed a similar behavior with the noise decreasing during the first 24 hours of stress, as
shown in Figure 4.11. The noise measurements at 100 and 500 hours of cumulative stress
showed the noise level to be increasing with stress time. Transistor #3 showed the lowest
noise level after 100 hours of stress, as shown in Figure 4.12. Figures 4.13 to 4.16 shows

the noise behavior of transistors #4 to #7, respectively. The overall noise behavior of the

 

 

 

 

1 9

2

Normalized
hrs
v35=0.ov 0'5 "
1
'0 I I
100 101 102 103

Stress Time (hours)

Figure 4.9: Normalized current gain (current gain after stress/current gain before stress)

for transistors #1, 2, 3, and 6 of the Hemmert test structure vs. stress time. The
stress was done at 200 C with 15 = 5 mA/umz.

100

 

 

 

 

 

Transistor Number
#1 #2 #3 #4 #5 #6 #7
Initial 77.1 78.3 78.2 84.0 80.70 76.0 80.9
1 hr 77.9 81.5 81.5 83.8 82.4 78.6 82.5
4 hr's 67.4 83.2 81.1 84.2 81.6 80.2 83.1

 

24 hr's 61.2 80.9 81.5 83.8 81.5 81.3 81.1

 

 

 

 

100 hr's 53.9 78.3 77.3 81.8 82.0 80.8 83.6
200 hr's 57.6 76.8 76.9 80.3 82.2 80.0 84.3
500 hr's 4.88 69.8 75.0 76.4 79.4 77.1 83.4

 

 

 

 

 

 

 

 

 

Table 4.1: The magnitudes of the current gain vs. stress time at VBE = 0.6 V for all seven

transistors of the Hemmert test structure.

101

Hemmert's device (#1)

10-18

w‘” D3 1h1t1al
01 1 hr
A: S hrs

10_20 Y1 ELi ru's
X= 100 hrs
°= 800 hrs
+3 500 hrs

   

 

 

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e;f'
. st~
‘ .151!
10‘85 r 3
10-26 1 ' I T I r I r I
100 101 108 103 10% 105
FREQUENCY

Figure 4.10: The noise power spectral density for transistor #1 of the Hemmert test

structure.

10”8—
1040;
10—21 I

10'22 —

Slbe

1083—

10-29 _

 

10-86

   

Hemmert's devlce (#8)

1h1t1a1
1 hr

H hrs
8% hrs
100 hrs
200 hrs
500 hrs

-9<>X<l>OEl

 

Y ' l ' ' l ' ' l ‘ ' l ‘ l
101 103 103 10‘+ :05

FREQUENCY

Figure 4.11: The noise power spectral density for transistor #2 of the Hemmert test

structure.

103

Hemmert's dev1ce (#3)

 

m‘ms
10493 D: 1h1tlal
0: 1 hr
A: % hrs
_p_0 Y: 8% hrs
10 A X: 100 hrs
l. 0: 800 hrs
" i: 500 hrs
10-21

10-22

Slbe

10‘23

10-2'4

 

10-85

 

10‘26

 

I‘FII’I"I"1
100 101 108 103 1.0“+ 10S

FREQUENCY

Figure 4.12: The noise power spectral density for transistor #3 of the Hemmert test

SENKnuflL

104

Hemmert's devrce (#H)

 

 

 

 

 

10*8—
10493 B: Ihltlal
. 0= 1 hr
J A: S hrs
Y: 8% hrs
10720—4 .
x. 100 hrs
0: 800 hrs
4‘ 500 hrs
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0—23 _
i
i
0’394
i
J
0'35 l
13-86 ' ' I . * I I . I I ' I ' s I
100 101 103 103 10‘+ 105

FREQUENCY

Figure 4.13: The noise power spectral density for transistor #4 of the Hemmert test

structure.

10-18

10-19

10-80

10-81

10-88

Slbe

10-23

10‘29

10'85

10‘86

105

Hemmert's devlce (#5)

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1 hr

% hrs
8% hrs
100 hrs
800 hrs
500 hrs

 

m0

Figure 4.14: The noise power spectral density for transistor #5 of the Hemmert test

structure.

106

(#6)

Hemmert's device

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The noise power spectral density for transistor #6 of the Hemmert test

Figure 4.15

SUUCIUI‘C.

10~18

10'19

10-20

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10-88

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10'23

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10-85

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107

Hemmert s

device (#7)

Initial
1 hr

% hrs
8% hrs
100 hrs
800 hrs
500 hrs

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Figure 4.16: The noise power spectral density for transistor #7 of the Hemmert test

structure.

108

Hemmert test structure, as shown in Figure 4.17, is an initial noise decrease and a
subsequent noise increase as the transistor starts to show substantial gain degradation.
These noise changes are produced in the case of transistors #2 and #3 exclusively by
changes in the mechanical stress in the transistor structure since no electrical current
flowed through either of these transistors.

Experiments performed on both TIN3 and TSEO3I transistors also showed similar noise
characteristic changes due to forward bias stress. TIN3 transistors showed an initial
decrease in their low frequency noise characteristics when stressed at 240 C with a current
density of 2 mA/umz. Figure 4.18 shows the noise power spectral density for pre-stress,
66 and 100 hours of cumulative stress time. It is significant that the observed noise
decrease during the first portion of the stress (66 hours) required both the high
temperature and the high current density conditions. This was confirmed by stressing the
transistors with no current and just high temperature. This experiment did not reduce the
noise significantly. In fact, if transistors with the noise previously reduced by applying both
high current densities and high temperatures are subjected to just a high temperature of T
= 240C (post-stress thermal annealing) the noise is seen to increase as seen in Fig. 4.19.
Fig. 4.20 shows that the application of a current density of 2 mA/pm2 at 23 C also does
not produce a significant noise decrease. Hence, it is the combination of both the high
current density and high temperature that produces the noise reduction.

For TIN3 devices the noise reduction occurs for the initial portion (66 hours) of
the forward bias stress. As shown in Fig. 4.18, the noise increases after longer stress
times, i.e. 100 hours cumulative stress. This same behavior was observed as presented
above for the transistors of the Hemmert test structure. For both TIN3 devices and the
transistors of the Hemmert test structure, the noise starts to increase, afier its initial
decrease, at about the same time the gain begins to drop substantially. TSEO3I transistors
also showed a drop in the low frequency noise characteristics as seen in Fig. 4.21. This

technology did not show the later increase in the low fiequency noise as the other

Normallzed N01se Power

109

   

 

 

m3 _
i
m1 e
/
IN
E Tr#1
O Tr#8
4 A Tr#3
10 Y Tr#%
X Tr#5
0 Tr#6
e Tr#7
I
109 . . I . . I , . I . ..j

(a)

10‘1 100 101 103

C)

Stress Time

Figure 4.17: Normalized base current noise power at 1 Hz vs. stress time for the seven
transistors of the Hemmert test structure. Transistor #1 is the only transistor

subjected to a electrical stress.

110

 

    

 

 

 

10-20
+ : original
-9- : 66hours
1041 7 + : 100 hours
c
5": -22
(AZ/Hz)10 ‘
10-23 _
10‘“ I
10° 101 102
Frequency (Hz)

Figure 4.18: The noise power spectral density of a TIN3 transistor decreases after a
forward-bias stress, reaches a minimum and subsequently increases again. The

stress was done at 240 C with IE = 2 mA/umz.

111

 

 

 

 

10-20_
+:original
«948113811158ng
-9-:afterannealing
U : ‘
104‘- . a
A r 3
Slb - _ = ‘ _,
(AZ/HZ) - - ’ _ _
. _ E ‘-
10‘22— ’ - - . _ _‘=\_‘
10-23 I 1
10° 101 102
Frequency (Hz)

Figure 4.19: The noise power spectral density of a TIN3 device decreases after stressing
with .15 = 2 mil/um2 at 240 C for 66 hours. Also shown is the post-stress
thermal annealing increase of the noise levels toward its original values. The
annealingwasdoneat240Cfor66hours.

112

 

 

10-20 _
a- :original
9 :23 C, 100 hours
-.- : 240 C, 1 hour
...- : 240 C, 65 hours
10-21 I

 

 

 

22
(A 2am ‘0’ ‘
10-23 _
10'“ I
10° 101 102
Frequency (Hz)

Figure 4.20: The noise power spectral density of a TIN3 device decreases after stressing
with 13 = 2 mA/trm2 at two difl’erent temperatures: first, 23 C for 100 hours,
then, 240 C for 66 hours.

113

 

  
 
   

 

 

 

10'24
+: original
+: after stressing
~94 after annealing

10-25 ‘

Slb
(A 2IHZ)
10-26 __
10'” I
10° 101 102
Frequency (Hz)

Figure 4.21: The noise power spectral density of a TSEO3I device decreases after stressing
at 225 C with JE = 5 mA/um2 for 90 hours. The noise level increases after a

post-stress annealing at 225 C for 90 hours.

114

technologies. It is worth noting that TSEO3I devices did not show a gradual gain
degradation as did the devices of the other two technologies, rather TSEO3I devices failed
due to open circuits caused by electromigration. As also shown in Figure 4.21, a post-
stress thermal annealing (225 C) caused the noise levels to increase toward the pre-stress

levels, which is consistent with the annealing results obtained on TIN3 devices.

4.5 Discussion

Gradual gain degradation due to base current increases was observed to occur as a
result of forward bias stressing in two of the three technologies tested. T SEO3I devices did
not show a gradual gain degradation, rather, a relatively abrupt failure occurred due to an
open circuit produced by electromigration. The failures of TSEO3I transistors were
verified as electromigration open-circuits using SEM examination. The TIN3 devices
which had a gradual gain degradation were cross-sectioned for SEM examination. Any
electromigration occurring in this technology was not large enough to be observed under
SEM examination. As described in Chapter 2, previous studies of gain degradation due to
base current increases under forward bias stress have attributed the effects to
electromigration[18,77] or to Auger-recombination produced hot electrons [1]. Both of
these phenomenon would show a gradual drop in the gain as the degradation proceeds.
Also, both of these phenomenon would be expected to increase as the ambient
temperature increases. The recent study of Hemmert [7 7] demonstrates that the gain
degradation can occur due to electromigration as evidenced by the gain changes induced
in devices receiving no electrical current but with forward bias current flowing through a
neighboring device. The results of the present study on the Hemmert test structure, as
shown in Section 4.4, indicate that electromigration also produces low frequency noise
changes that can initially decrease the noise followed in some technologies by noise

increases. This noise decrease is distinct from hot electron noise changes since hot

115

electrons produce noise increases[88]. The decrease in noise phenomenon was observed in
all three technologies studied.

This unique feature of the low frequency noise decreasing, at least initially, due to
electromigration, provides an additional indicator as to whether the cause of gain
degradation under forward bias stress in a particular technology is due to electromigration
or hot electrons. A forward-bias degradation model which uses the concepts of dislocation
movement and energy band narrowing both caused by electromigration induced
compressive stress is presented in next chapter. This model gives a good explanation of

the observed noise and gain changes after a forward-bias stress.

CHAPTER 5

A FORWARD-BIAS STRESS INDUCED DEGRADATION MODEL

As shown by the experimental results in Chapter 4, the forward bias combined with
a high temperature can produce gradual changes on BJT's gain and noise characteristics.
Namely, the low-fiequency noise initially decreases with the gain remaining unchanged;
however, when the gain begins to decrease as the stress is continued, the low-fi'equency
noise starts to increase. It is concluded that electromigration induced compressive stress
plays an important role in these observed phenomena. The goal for this chapter is to
propose a physical model, which can explain how such a compressive stress can cause the
observed changes of the noise and gain characteristics. In Section 5.1, the background
material to be used in developing the model is reviewed. There are two classes of physical
phenomena which affect device performance that may result fi'om the application of
compressive stress to a p-n junction. The stress may cause dislocations present in the
crystal to move. Secondly, the application of mechanical stress can modify the energy
band and change effective mass, lifetime, and mobility of carriers. Then, the model is

presented in Section 5.2.

5.1 Background

5.1.1 Effects of Emitter-Edge Dislocations on BJT Low-Frequency Noise

Dislocations in crystals refer to the line defects. For example, one kind of
116

117

dislocation can be considered as an extra plane of atoms partially crowded into the crystal.
Another example of dislocations can be thought of as produced by cutting the crystal
partway through and shearing it parallel to the edge of the cut by one atom spacing. The
different kinds of dislocations can appear in the same crystal simultaneously. The
dislocations can be easily observed by the etch pitting method. The etch pitting method
requires a special ”dislocation" etchant, e. g. the Sirtl etchant [82], to reveal the locations
of the dislocation lines. After a sample have been etched in such etchant, washed and
dried, small pits can be observed on the surface of the sample by a microscope. These
small pits indicate the points where dislocation lines cut the surface. Other methods are
also used to observe dislocations, such as X-ray topography, scanning electron
microscopy (SEM), or transmission electron microscopy (TEM).

It is well known that dislocations can affect the electrical properties of
semiconductors. For example, the low-frequency noise is one of the sensitive parameters
to the effects of dislocations. In 1969, Green et al. [44] investigated the noise of planar p-
n junctions affected by dislocations. In this study, dislocations were introduced by a
bending procedure which caused mechanical stress, and the densities and the orientations
of dislocations were monitored by both SEM and TEM. The investigated devices were
divided into two groups. In the first group, the bending procedure was designed such that
the dislocations emerged at the device surface near the junction. On the other hand, in the
second group the bending procedure was altered such that the dislocations emerged at the
device surface away fiom the junction. The densities of dislocations in both groups were
varied. The low-frequency l/f noise spectra were then measured on both groups. The
results from the second group showed that the 1/f noise did not change although the
dislocation densities in the device were changed. However, the l/f noise of the first group
was increased with the increase of dislocation densities. There is a very important
conclusion drawn in this study: the low-fi'equency l/f noise increases with the increasing

of the dislocation density ONLY when the dislocations emerge at the surface of the device

118

near the junction. In other words, only those dislocations at the surface of the device near
the junction will affect the low-frequency 1/f noise properties.

For a given silicon wafer, it was shown in another study by the etch-pit evaluation
technique that phosphorus diffusion was also able to create dislocations [45]. It is believed
that in this case an internal stress is induced by the high concentration of dopants, and that
this internal stress is partially relieved by the generation of dislocations. For a n—p—n
transistor, generally two kinds of dislocations can be generated during the emitter
diffusion process. The first kind is the diffusion-induced dislocations [47], which appear
inside the diffusion emitter area. The second kind is the emitter-edge dislocations [48],
which appear around the edge of diffusion emitter area, usually after the emitter oxidation
step. The density of each kind of dislocations depends on the emitter phosphorus-diffirsion
conditions [49,54]. However, the densities of both kinds of dislocations will increase as
the phosphorus doping concentration increases. These two kinds of dislocations can be
observed by one of the above-mentioned methods, such as etching pitting, X-ray
topography, SEM or TEM.

Nishida [46] studied the effects of dislocations induced by impurity diffusion on
gate-controlled n-p-n transistors, and he found that the low-frequency noise increased
when more dislocations were created by a higher concentration of dopants. The
dislocation density was counted by the etch-pit technique. However, Nishida did not
identify whether the contribution to the 1/f noise changes came from the diffusion-induced
dislocations or fi'om the emitter-edge dislocations.

However, it was shown later that only emitter-edge dislocations affect the low-
frequency l/f noise properties. Stojadinovic [49] investigated the low-frequency noise of
silicon n-p-n transistors with different densities of emitter-edge dislocations and diffusion-
induced dislocations. The etch pit was the observable of the dislocation density in this
study. It was found that a transistor with a large number of diflirsion-induced dislocations

had an almost equal low-frequency noise level as one without diffusion-induced

119

dislocations as long as the two transistors had a similar amount of emitter-edge
dislocations. From Stojadinovic's observation and the conclusion [44] made by Green
mentioned early, the indication is that only the emitter-edge dislocations emerging at the
device surface will contribute to the low-frequency l/f noise. These emitter-edge
dislocations are believed to induce surface states near the EB junction area of n-p-n
transistors. Since the surface states accept and emit electrons, the l/f noise will be of the
surface recombination type. It is noted that the low-fi'equency noise characteristics of the
devices used in our study are in fact characteristic of surface l/f noise, as described in
Chapter 3.

The emitter-edge dislocations can also induce bulk generation-recombination
centers in the base region of n-p-n transistors [43,46]. These generation-recombination
centers give rise to generation-recombination noise which, however, is usually lower than
the 1/f noise and the shot noise at room temperature [52]. Moreover, the surface states
and bulk centers induced by emitter-edge dislocations have fluctuating charges, which can
produce enhanced scattering fluctuations, and therefore can also give rise to mobility
fluctuation 1/f noise. However, this mobility fluctuation type of l/f noise does not appear
in our transistors.

Mihaila et al. [43] also investigated the effect of emitter-edge dislocations on the
low-frequency noise of bipolar transistors in relationship to the phosphorus surface
concentration. An abrupt increase in both noise magnitude and dislocation density was
observed for surface concentration greater than 4.3 x1020 cm'3. In their following work
[53], an appearance of burst noise was sometimes observed, and they associated the
existence of dislocation clusters inside the emitter area with the burst noise generation. It
is noted that in some devices used for our forward-bias—stress study, the burst noise also

appeared and disappeared in a random fashion.

120

5.1.2 Dislocation Motion Under Forces

When an external stress is applied on dislocations, some reaction of the
dislocations can be observed, such as the motion of dislocations and the change of
dislocation shapes. The applied stress (a) required to cause a motion of the dislocations is
called the critical stress (ac). The magnitude of critical stress depends on the strength of
the lattice resistance. For example, dislocations in the heavily doped silicon crystals require
a very high critical stress to start moving. This phenomenon is called dislocation locking.
It is believed that an interaction between the impurities and the dislocations is the cause of
the locking, and the locking strength will depend on the type and the concentration of the
impurities. For example, a phosphorus doped silicon crystal has a dc value around 8.0x 107
dyn/cm2 with a doping concentration of 1.0x1014 cm'3 [86], but a larger cc of 1.1x108
dyn/cm2 is observed with a doping concentration of 1.5x 1019 cm'3 [55]. Some impurities
have smaller ac values in silicon, e. g. a dc value less than 1.2x 107 dyn/cm2 is observed for
a boron doped silicon crystal with a d0ping concentration of 2.0x1012 cm'3, and a
similarly small 0c is found for an oxygen concentration of 1.5x10l7 cm'3 in silicon. Higher
ac values are also found with values as high as 2.0x 108 dyn/cm2 for Sb doped silicon at a
doping concentration of 8x 1018 cm'3 [50].

The basic hypothesis on dislocation motion was proposed long ago [56-58] in
1937. However, it was not until the late 1950's that experimental evidence for dislocation
motion was obtained. The pioneering experimental study which demonstrated dislocation
motion was performed by Johnson et al. [59] on LiF. They utilized etch pits to detect the
positions of dislocations, and dislocation movements were traced by repeated etching. In
this manner, the distance that a dislocation moved after an application of external force
could be measured. Consequently, the average velocity of the dislocation versus the
applied force was computed by knowing the duration of the external force. The results

showed that the velocity was extremely sensitive to applied stress at low velocities: the

121

larger the stress was, the higher the velocity was obtained. However, a saturation of
velocity increase was observed at high velocities. The maximum velocity is essentially the
velocity of sound in the crystal.

Following Johnson et al.'s work, Chaudhuri et al. [60] performed a similar study on
four semiconductor crystals: silicon, germanium, gallium antimonide, and indium
antimonide. The impurity concentration of Si was less than 1015 cm'3. The test conditions
were with temperatures varying fiom 560 C to 940 C and with the applied stress varying
from 1.1x103 dyn/cm2 to 3.5x1011 dyn/cmz. It is worth noting that the doping
concentration is lower than the intrinsic carrier concentration under these test
temperatures. The range of velocities measured was found to be between 10'6 and 2x 10'1
cm/sec. A relation between stress (a) and the dislocation velocity (v) was obtained in the
following form

v = v0(o/O'0)’" exp(-AH/kT), (5.1)
with a stress exponent m = 1.4 :t 0.1, and an activation energy AH = 2.2 i: 0.1 eV. A
constant stress value 00 is used for normalization, and v0 is a fitting parameter. For
example, ”0(0/00) = 2x10‘2 cm/sec for an applied stress a = 6x108 dyn/cm2 at T = 560
C. As we can see in Equation 5.1, dislocations can move faster under conditions of higher
temperatures and higher stress.

It was also shown later [50,51,55,6l,62] by various methods that the dislocation
velocity and its temperature dependence (activation energy) in semiconductors can be
influenced by the impurity concentrations. However, the stress exponent m is not affected
by the impurity carrier concentrations. Depending on their types, impurities can either
decrease or increase the fitting parameter v0. For n-type silicon with doping
concentrations larger than the intrinsic carrier concentration at the test temperatures, the
velocity of the dislocation will increase with increasing doping. For example, in n-type

silicon at 600 C, the dislocation velocity starts to increase with increasing doping when the

122

doping concentration is 1018 cm'3 or higher [61]. The intrinsic carrier concentration at
600 C is 3.4x10l7 cm'3.

Kulkarni et al. [50] observed the dislocation velocity on n-type silicon by using
Lang X—ray topography. They reported that the dislocation velocity varied linearly with
the majority carrier concentration in a heavily doped silicon crystal. The activation energy
AH is 1.4 eV for Sb doped silicon with a doping concentration of 8x1018 cm'3. Similar
values of the activation energy were reported by other researchers. Patel [61] obtained 1.6
i 0.1 eV for a 5.5x1019 cm'3 As doped silicon. George [51] observed the activation
energy as 1.41 eV to 1.5 eV for a P doped silicon with a concentration of 1.4x10l9 cm‘3.
Imai [55] observed activation energy between 1.57 eV and 1.58 eV for a 1.5x1019 cm'3 P
doped silicon.

It has been shown [84,85] that the dislocation movement induced by an applied
force in a silicon crystal is a reversible effect. In these studies, a line defect (dislocation)
which has a half-loop shape with its two ends cutting the surface is subjected to a
mechanical stress. The locations of the two ends of the half-loop can be revealed by the
etch pitting method as described earlier. It has been shown that at a high temperature the
size of the dislocation half-loop will expand under an applied force. This phenomenon can
be observed by monitoring the movement of the two ends of the half loop on the surface
represented by the etch pits, which move away from the original positions after the force is
applied. However, if the sign of the applied force is reversed, at the same high temperature
the etch pits can move back towards their original positions. Also, it is found that the
dislocation velocity of backward movement is higher than that of forward movement. The
physics behind this phenomenon of the observed velocity difference is not well
understood. It is also indicated by another research group [83] that such a dislocation half-
loop will also contract, i.e. the dislocation line moves backward towards its original
position, if the sample is just put in a high temperature in absence of applied stress.

Unfortunately, no detailed experimental data was given in [83]. One would expect that the

123

thermal-activated backward movement would be slower than that with a reverse applied

force .
5.1.3 Piezojunction Effect

When a piece of n- or p-type semiconductor is subjected to a mechanical strain, a
change of its resistance can be observed. This is called the piezoresistive eflect, which can
be explained by the mobility change caused by the strain-dependent effective mass of the
semiconductor. However, when p-n junction devices are subjected to a large compressive
stress, 109 dyn/cm2 or larger, the I-V characteristics can also be changed. This
phenomenon is called the piezojunction eflect, which can be correlated to the
piezoresistive effect, but can not be adequately explained only by the mobility change. It is
noted that the electromigration-induced compressive stress is evaluated to be as high as
1010 dyn/cm2 [7 7]. Consequently, the piezojunction effect should be considered in our
forward-bias-induced degradation model.

The piezojunction effect is manifested in various ways depending on the junction
configuration, and the stressing technique. In this sub-section, the experimental results
performed by other researchers and the proposed models are reviewed, with special focus
on the change of the forward-bias current and the mag.

The total forward-bias current (11:) of a p-n junction can be divided into two parts:
the ideal current (Id) and the recombination current (1,). The ideal current is attributed to
the minority carrier diffusion and has the following form:

Id =WAInpmn/rnm +pnmp/rp)“21xlexp(qV/kr) -11, (5.2)
where 71,, and pn are the minority carrier concentrations of electrons in the p side and the
minority carrier concentration of holes in the 11 side respectively, 1.1,, and up are the

electron and hole mobilities respectively, In and IP are electron and hole lifetimes

 

124

respectively, A is the junction area, and V is the applied voltage. Assuming that the stress
has a negligible effect on A, then the stress-dependent parameters which need to be
considered in Id will be the minority carrier concentrations, the mobilities, and the
lifetimes. The recombination current sometimes is dominant in the low voltage range and
can be expressed as [64]

Ir = (qW/ZM ovrthnr exp(qV/ZK T ) ~ Nr no (53)
where o is the carrier capture cross section, v”, is the carrier thermal velocity, N, is the
trap density, and n,- is the intrinsic carrier concentration. Again, if we assume that the
stress has a negligible effect on W and A, then the dominant changes in I, can come from
N, and ni. It is also noted that the minority carrier concentrations and intrinsic carrier
concentration can be related to the energy gap (Eg) and the effective mass (m‘) as [64]

nppp =p,,n,, ="i2 “(may2 Hug/2 )l/2(m;m:2 )l/4 exp(—Eg/kT), (5.4)
where n" and pp are the electron concentration in the n side and hole concentration in the
p side respectively, "’1; .is the light-hole effective mass, mzh is the heavy-hole effective

* . . . . .
mass, m, rs the longrtudrnal electron effective mass, and m: transverse electron effective

mass. As described below, research has correlated the observed changes of IF and 1,. with
the stress related behavior of the parameters like the mobilities, the lifetimes, the effective
masses, and the energy gap.

Early work in the piezojunction effect investigated the effect of hydrostatic
pressure upon diodes [65]. A small change in the electrical properties was observed which
could mainly be attributed to the change of energy gap. It has been shown [66] that under
hydrostatic pressure (P) the energy gap change (8Eg) could be described as

6Eg =axP, (5.5)

where a = -2x10'12 eV-cm2/dyn for silicon.
In 1962, Rinder reported an anisotropic stress effect (ASE) on the characteristics

of p-n junctions [67]. The stress was applied perpendicularly to the device surface, by

125

means of a diamond stylus with a radius of curvature of 17 um. It is worth noting that in
the ASE study the junction area is much larger than the contact area of the stressing
element. A large stress, in the range of 1010 dyn/cm2 or larger, could be easily obtained. A
significant increase of both forward-bias and reverse-bias current was observed, and these
effects increased with increasing temperature. It was noted by the author that these effects
could not be interpreted as being simply due to the piezoresistive effect, which would
show an opposite temperature dependence. In his later work [68], the ASE was found to
increase strongly with decreasing junction depth. In the same study a tentative model was
also proposed to explain qualitatively the observed piezojunction effect caused by the
ASE. This model assumes that dislocations can be created during stress, and these
dislocations can be elastically "indented" by the stress to a depth which was comparable to
that of very shallow junctions. Under this circumstance, new generation-recombination
centers which are induced by dislocations become electrically effective in or above the
space charge region and result in the increase of the recombination current. When the
stress is removed, it is hypothesized that dislocations are able to move back elastically.
Consequently a reversible effect can be observed in the ASE. On the other hand, if the
stress is large enough to produce permanent dislocations with electrical consequences as
previously described, the partially irreversible effects of the ASE can be observed. This
model gives a good explanation on the irreversible effects observed in the ASE. However,
this model is not adequate to explain some other observations. For example, the current of
a device under the ASE test sometimes increases at first and then decreases.
Consequently, other models were also proposed later to explain the ASE piezojunction
effect [20,69-74].

As indicated earlier in Equation 5.2, the minority carrier lifetime is one of the
parameters that should be considered when the device current is changed by a mechanical
stress. Sloan et al. [72] investigated experimentally the compressive stress effect on the

minority carrier lifetimes on doped silicon wafers. The lifetime was determined by the

126

method of photoconductive decay. The excess minority carriers were created in a piece of
semiconductor by optical excitement. The rate of decrease of minority carriers was
monitored by the change in conductivity with time measured immediately after ceasing
optical generation. Consequently the minority carrier lifetime could be determined. In this
study, the hydrostatic pressure was used as the means to apply mechanical stress. It was
found that the minority carrier lifetime of electrons (tn) decreased and the minority carrier
lifetime of holes (tp) increased after applying compressive stress. The physical cause of
these lifetime changes was not fully understood. This lifetime data was taken into account
by Kanda [73,74] who also developed a piezojunction model, but he showed that the
effect of the lifetime is negligible compared with other variables.

Using BJT's, Edwards [71] observed both collector current and base current
increases afier a local stress was applied. He also investigated the influence of the strain
distribution on the changes of 11175. It was found that when the stress was applied over a
relatively large area using a blunt stressing element, the hp]; increased for the low values
of current; however, when the stress was applied by a sharper stressing element, a
decrease of has is observed over a wide current range. The changes of the emitter
efficiency caused by the changes of the energy gap (Eg) alone under compressive stress
were used to interpret the experimental results.

A more sophisticated model was developed by Wortman et al. to explain the
increase of the ideal part [69] and the recombination part [70] of the forward-bias current
under a compressive stress. This model was based on the stress-induced variations in
energy band structure and, consequently, their effect on minority carrier concentrations.
From Equation (5.4), the minority carrier concentration changes, np/npo and pn/pno, with 0
denoting zero applied stress, is equal to the square of intrinsic carrier concentration
change, (ni/n;0)2. Instead of only considering the energy gap change as proposed by
Edwards [71], the stress-induced changes in all conduction band minima (AEcl, AECZ, ---)

as well as two valance band maxima (AEVI, AEVZ) for both heavy and light holes were

 

 

127

taken into account. For example, the piezojunction model for silicon devices, given that

silicon has six conduction band minima, could be presented as
1
(n,- /n,.O )2 = gleXPMEvr /kT) +exp(AEv2 /kT)] x[exp(—AEcl /kT) + +exp(-AECG /kT)]

2 w. (5.6)
In this model, the effective mass was assumed to be constant during the stressing. The
changes of mobilities and lifetimes were also neglected. Since there was only a part (A S) of
total junction area (A ,) that was subjected to stress, Equations 5.2 and 5.3 are modified to
include the stress effect on Id and 1, resulting from the stress-induced changes of np, p",

and (In-)2. These modified equations are

’_d tags

= . 5.7
[do A, ’4th ( )
I A -A A 2
—'—=———! S+—Syf,’ . (5.8)
1’0 Al At

Following the band structure model proposed by Wortman et al., Kanda
[20,73,74] also investigated the stress dependence of the ideal forward-bias current under
ASE. However, Kanda included the stress-induced effects on mobilities, lifetimes, and
hole effective masses. It was concluded that the changes of mobility and lifetimes were
small in comparison with the changes in minority carrier concentrations. On the other
hand, because of the stress-induced effect on the hole effective mass, it was predicted that
for the <100> orientation of silicon the diode current had a double peak at a stress around
109 dyn/cmz. Also, the hp}; would go through a minimum at around a similar stress
magnitude. In the work done in 1978, the noise behavior of a Si piezo-transistor was
studied. It was found experimentally that the noise behavior did strongly depend on the
exact location on the emitter where the mechanical stress was applied. If the stress was

applied close to, or right over, the emitter-base junction edge, the noise increased with

128

stress. Otherwise, the noise decreased with stress. No further explanation for this
observation was given.

Hemmert et al. [77] used bipolar junction transistors as pressure sensors to
monitor the electromigration-induced compressive stress in conductors of integrated
circuits. The common emitter current gain (hFE) of the transistors subjected to such
compressive stress decreased because of the increase of the base recombination current
with the collector current unchanged. From Equation 5.3, the increase of the
recombination current can be described as due to the increase of intrinsic carrier
concentration, which was caused primarily by compressive stress induced band gap (Eg)
narrowing as described in Equation 5.4. If hFEn represents the ratio of hp}; before stress to
hFE after stress, then

hFEn = exp(—AEg / 2kT). (5.9)
Also from Equation 5.5, the magnitude of the compressive stress can be evaluated by
knowing the amount that Eg changes, thus

2kT1fl(hFE,,) = -AEg = -axP. (5.10)
From Hemmert's results, a large compressive stress (up to 1010 dyn/cmz) was deduced to
be present on the stressed transistors. It is noted that the gradual degradation of hp);
observed in our forward-bias stress devices has the same qualitative degradation behavior,
namely only the base recombination current increases with the collector current remaining

unchanged.

5.2 Degradation Model

As shown in Figure 2.3 in Chapter 2, under forward-bias stress, electromigration
will tend to cause an accumulation of metal above the emitter region. However, with a
passivation layer enclosing the metal line the thickening of the metal will not be able to

occur. Instead, there will be a build up of compressive stress normal to the substrate. In

 

129

our forward-bias stress study, the electromigration-induced compressive stress is claimed
as the main origin of the observed changes of gain and the noise characteristics.

It is worth noting that there are some distinct properties of the electromigration-
induced compressive stress which are different than the anisotropic stress used in the ASE
studies or a hydrostatic pressure. The electromigration-induced compressive stress offers a
non-uniform stress over the device surface around the emitter region and the emitter-base
junction beneath the field oxide. The magnitude of the compressive stress will depend on
the device configurations. For example, it has been shown that a higher compressive stress
can be achieved with a thicker passivation layer [18]. Also, the stud contacts used in
TSEO3I devices will reduce the electromigration-induced compressive stress on
transistors. Besides the dependence of device configurations, the magnitude of the
compressive stress will also depend on the forward-bias stress conditions. The devices will
be subjected to a larger compressive stress with higher stress current densities, higher
stress temperatures and longer stress times.

As shown in our experimental results, the low-frequency noise initially decreases
with the gain remaining unchanged; however, when the gain is ready to decrease as the
stress is continued, the low-frequency noise starts to increase. The decrease of the gain is
caused by the increase of the base recombination current with the collector current
remaining unchanged. Also as described in Chapter 4, the low-fi'equency noise is identified
as the surface l/f noise located between the base and the emitter.

Figure 5.1 shows a specific degradation model for these forward-bias stress
research. The stressed devices are scaled-down transistors, which have very high emitter
doping concentrations (usually larger than 1020 cm'3). Because of the high doping
concentration, emitter-edge dislocations are presented which can contribute to a part of
the surface l/f noise as described in Section 5.1.1. When the forward-bias stress starts, a
small compressive stress is initially built-up upon the emitter edge. It is proposed that

when the compressive stress becomes large enough (>1. 1x108 dyn/cmz) to move the

 

COMPRESSIVE STRESS

 

 

 

 

 

 

A : EMITI'ER-EDGE DISLOCATIONS

131

locked dislocations in heavily doped n-type silicon, the emitter-edge dislocations will move
in the direction of the force away from the surface, as described in Section 5.1.2.
Therefore, the surface recombination center induced by the dislocations will decrease, and
a drop of 1/f noise power spectra thus can be observed. Equation 5.1 enables us to
estimate the dislocation velocities in our devices under the forward-bias stress conditions.
It is also noted that the dislocation velocity is linearly proportional to the doping

concentration [50]. Consequently, one can use the following relation

m
l’rzfl 91 exp A”. 1.-.]- (5.11)
V2 "2 02 k 71 T2

to calculate the dislocation velocity v 1 of the device with a doping concentration of n,
under compressive stress of a, at temperature T 1 if the values of v2, 112, 02, T 2 and the
activation energy AH are known. Kulkarni et al. [50] measured a dislocation velocity of
3.6x 10'5 cm/sec at 650 C with the compressive stress of 2.2x 108 dyn/cmz. In their study,
the doping concentration was 8x1018 cm’3. Also a activation energy of 1.4 eV was
obtained. Our devices have the doping concentration about 20 times larger then the
samples used in Kulkarni et al.'s study. The stress temperatures in our forward-bias stress
experiments are in the range of 200 C to 240 C. With the activation energy of 1.4 eV, the
dislocation velocities in our devices will be 3.85x10'll cm/sec at 200 C or 5.74x10'10
cm/sec at 240 C under the same compressive stress of 2.2x108 dyn/cmz. This means that
the dislocations can move away from the surface to a distance of 13 A at 200 C or of 206
A at 240 C after an hour of compressive stress of 2.2x108 dyn/cmz. It is worthy noting
that under the same compressive stress condition, the dislocation velocity at room
temperature is only 3.7x 10'3 A/hour, which is too small to affect the dislocation density at
the device surface. This explains why the noise drop is not observed during a room-
temperature forward-bias stress. If we also consider the force dependence for the

dislocation velocity, i.e. (01/02)“ term in Equation 5.11 with m = 1.4, a higher velocity

132

can be obtained under a larger compressive stress. For example, under the compressive
stress of 7.0x 108 dyrI/cm2 the dislocation can move a distance of 66 A per hour at 200 C.
It is noted that the compressive stress can also act on the field oxide and can possibly
affect the base-emitter junction beneath the oxide. However, according to Equation 5.10
the hFE change at room temperature is less than one percent under the stress magnitude of
2.2x108 dyn/cmz, and is 2.7 % under 7.0x108 dyn/cmz.

A movement of dislocations which would result in a decrease of surface state
density would in principle cause the base surface recombination current to decrease. In
fact, in this study an initial slight increase in gain due to a reduction in base current was
observed on TIN3 and Hemmert devices. However, this effect cannot be unambiguously
attributed to a movement of dislocations. Other possible explanations exist, such as
temperature induced relief of pre-existing stress [18]. In some cases, control devices that
received only the temperature stress also showed this slight gain increase.

As the forward-bias stress continues, a larger compressive stress will be established
over the stress transistor resulting in a non-negligible band gap narrowing. Hence an
increase of the base recombination current can be observed. Assume a substantial decrease
of 11175, for example, is 4%. By Equation 5.11, a compressive stress larger than 1.1x109
dyn/cm2 is required to achieve a 4% hFE decrease. Also, as shown in Equation 2.1, the
surface l/f noise is proportional to the recombination current squared. Under this
condition, the surface l/f noise will start to increase because of the increase of the base
recombination current. It is noted that the movement of dislocations is still in action at this
stage, but its effect is compensated by the effect of the base recombination current
increase.

The experimental results performed on TIN 3 devices can be well explained by the
above model. For TSEO3I devices, only the initial decrease of 1/f noise was observed, and

a subsequent increase of the noise was not shown. The l/f noise reached a minimum value,

133

  

 

 

102 l
.l
L 101 — .
(b .
3 ,1
o
0.
cu
Ul .
O
U
OJ .
N
E: 13 Tr#l
g 0 11138
5 A Tr#3
Z: 10-17 '5 Y Tr#L+
>< Tr#5
Ii 0 “”116
4‘ Tr#7
.
10‘8 4 . l . . r . . I s
10"L 100 101 10a 10‘

Stress Time

Figure 5.2 Normalized base-current noise power spectral density at 1 Hz vs. stress time
for the seven transistors of Hemmert's test structure designed for investigating
the electromigration-induced compressive stress. Transistor #1 is the only
transistor subjected to a electrical stress. The stress was done under the

conditions of J = 5 mA/pm2 at 200 C.

 

 

134

and then stayed in that low value. The gain remained approximately at a constant during
the forward-bias stress till the fatal failure of the devices finally occurred. In this case, the
l/f noise decrease can be explained by the motion of emitter-edge dislocations cause by
the compressive stress (~ 108 dyn/cmz) built-up on the emitter edge, as described earlier.
Because the dislocations contribute to only a part of the surface l/f noise, the continuous
decrease of the 1/f noise will not occur. However, because TSEO3I devices have the stud
contacts, which is used to minimize the effect of electromigration-induced compressive
stress, a large compressive stress (> 109 dyn/cmz) which can cause the increase of the base
recombination current will not be obtained. Under this condition, a later noise increase and
gradual gain decrease will not be observed.

For Hemmert's BJT pressure sensors designed for investigating the
electromigration-induced compressive stress, as described in Chapter 4, only the first
transistor was subjected to the electrical stress. Therefore, any observed changes on the
rest of the transistors will be attributed to electromigration effects. As shown in the
experimental data of Chapter 4 and repeated here in Figure 5.2, the overall noise behavior
is still that of an initial noise decrease and a subsequent noise increase as the transistor
starts to show substantial gain degradation. However, the noise minimum occurs at a later
time with the increasing distance from the transistor subjected to the electrical stress. For
example, the noise levels of transistor #2 reached a minimum after 24 hours of stress. The
noise levels of transistor #3 varied less but seemed to reach a slight minimum after 100
hours of stress. Aspects of the observation of the gain and the noise changes can also be
qualitatively explained by the above-mentioned degradation model by considering the
varying magnitude of compressive stress acting over each transistor.

Table 5.1 shows the normalized 11175 for transistor #2, #3 and #4. The normalized
by; is defined as the hp]; after stress divided by the initial has. It is noted that there is a
small increase in the by: before the hat; decrease occurs. Hemmert et al. attributed this

increase to the hypothesis that the electromigration produced compressive stress

 

 

 

135

 

 

 

 

 

 

 

 

 

 

 

stress time hFEn of hFEn of hFE" of
(hours) transistor #2 transistor #3 transistor #4
0 1.000 1.000 1.000
1 1.041 1.042 0.998
4 1.062 1.037 1.003
24 1.033 1.042 0.999
100 1.000 0.989 0.975
200 0.981 0.984 0.957

 

Table 5.1 The normalized hpg (hFE before stress / hp]; after stress) for transistor #2, #3

and #4 of the Hemmert's test structure.

 

 

 

 

136

 

 

 

 

 

stress time h'FEn of h'FE, of h'FEn of
(hours) transistor #2 transistor #3 transistor #4
24 0.972 1.000 0.996
100 0.942 0.949 0.972
200 0.923 0.944 0.954

 

 

 

 

#3 and #4 of the Hemmert's test structure.

Table 5.2 The normalized hp}; decrease (hFE / the highest value of hp];) for transistor #2,

 

137

COMPRESSIVE STRESS

 

 

 

 

OXIDE

---------------------------

 

 

 

 

 

 

BASE 2
EB JUNCTIONS
8 10 18 20 (um)

A :EMITER-EDGE DISLOCATIONS

Figure 5.3. The forward-bias degradation model for Hemmert's pressure sensors designed
for testing the electromigration efl‘ect. Only the second and the third transistors
are shown. The electrical stress is applied only on the first transistor.
Transistors are separated equally by 10 um measured from the center of each
transistor. The emitters have a length of 4 um, as shown in the cross section,

and a width of 2.5m.

 

138

compensated some initial built-in stress from the fabrication process [18]. Additional
compressive stress builds as the degradation process is continued and will result in hpg
decrease. It is then convenient to define another quantity to monitor hFE decrease. The
normalized hp]; decrease (h'FEn) is defined as the hp]; divided by the highest has, and the
values of h'FEn is shown in Table 5.2.

A schematic of the second and the third transistors in Hemmert's test structure are
shown in Figure 5.3. The center of transistor #1 is located at x = 0 urn which is not shown
in Figure 5.3. The center of transistor #2 is located at x = 10 um, and that of transistor #3
is located at x = 20 pm. For each transistor, the largest compressive stress is obtained on
the E-B junction located on the left side of the emitter contact. The emitter size is 4 um
long (as shown in Figure 5.3) and 2.5 pm wide. Consequently the EB junction subjected
to the largest compressive stress for transistor #2 is located at x= 8 pm, and that for
transistor #3 is located at x = 18 um. The compressive stress at the location of the E-B
junction can then be calculated by monitoring the gain decrease of the respective
transistor.

Table 5.3 shows that calculated pressure by using the data provided in Table 5.2.
With the help of Equation 5.10, the pressure at x = 8 um and that at x = 18 um can be
calculated by using the data of the normalized by; decrease (h'FEn) for transistor #2 and
#3.. It has been also shown [77] that the electromigration-induced compressive stress has
an exponential decay form of exp(- 0), where L0 is called the characteristic length. It has
also been shown [77] that L0 will be increased as the stress time increases. The values of
L0 versus the stress times in our study was evaluated as 10.25 pm after 24 hours, 26.2 um
after 100 hours and 38 um after 200 hours of forward-bias stress. It is noted that the
pressure at x = 18 um after 24 hours of stress is carried out by interpolating with the help
of the data fi'om transistor #4.

As described earlier, the compressive stress acting on the emitter edge will cause

the dislocation to move if the compressive stress is large enough to overcome the locking

 

 

 

139

 

 

 

 

 

Pressure (dyn/cmz)
stress time x = 8 pm = 18 um
(hours)
24 7.30x108 2.75x108
100 1.56x109 1.07x109
200 2.06x109 1.59x109

 

 

 

 

 

Table 5.3 The electromigration-induced compressive stress gradient along the distance (x)

from transistor #1.

140

strength on dislocations. This usually requires a compressive stress larger than 103
dyn/cmz. The stress temperature for these devices is at 200 C. It has been estimated in
Section 5.1.2 that the dislocation can move 13 A per hour at 200 C under a pressure of
2.2x108 dyn/cm2 or 66 A per hour at 200 C under a pressure of 7.0x108 dyn/cmz. On the
other hand, the compressive stress acting on the E-B junction will cause the narrowing of
the energy gap and consequently will result in a decrease of the gain. We also estimated
that it requires 1.1x 109 dyn/cm2 to observe a substantial 4% gain decrease. From the data
in Table 5.3, after 24 hours the compressive stress built-up on the emitter edge of
transistor #2 (x z 8 pm) is around 7 .30x 103 dyn/cmz, which enables dislocations to move
at a velocity of around 66 A/hour at 200 C. Also the compressive stress on the E-B
junction (x = 8pm) is 7.3x103 dyn/cmz, which is too small to cause an appreciable
increase of the recombination current. Consequently we will observe a noise decrease with
the gain remaining almost unchanged at this stage. However, after 100 hours of forward-
bias stress the compressive stress built-up on the E-B junction of transistor #2 is large than
1.1x109 dyn/cm2 which can result in an appreciable increase of the base recombination
current. That is why the decrease of the gain and the increase of the noise level will be
observed after 100 hours on transistor #2. In between 0 hours and 100 hours, there is a
noise minimum. On the resolution of the time scale used here, the minimum noise was
measured at 24 hours. However, the actual minimum may be somewhat earlier or latter
than this. Consequently the true minimum may be deeper than shown. Additionally it is
noted that for transistor #1 , the stress covers the entire perimeter with relatively equal
magnitude because the current flows vertically down into the device. However, for
transistor #2, the edge of the perimeter close to transistor #1 is subjected to a larger stress
prior to the far edge. Consequently, the minimum would be reduced and spread out with
time relative to transistor #1. For transistor #3, after 24 hours of forward-bias stress at
200 C the compressive stress built-up on the emitter edge (x z 18 um) is around 2.75x108

dyn/cmz, which is less than that on transistor #2. Under this compressive stress, the

141
o

dislocation is just about to move and moves slowly in a velocity of around 13 A/hour at
200 C. Consequently a smaller noise drop will be observed on transistor #3 afier 24 hours.
Also at this moment the compressive stress on the EB junction of transistor #3 is not
large enough to produce the gain changes. After 100 hours, a larger compressive stress is
built on the emitter edge. However, the compressive stress on the EB junction at this time
is also large enough (1.07x109 dyn/cmz) to produce the increase of the base
recombination current, so the noise decrease caused by the dislocation movement was
compensated by the noise increase caused by the base recombination current increase.
Since there was no measurement between 24 hours and 100 hours, any noise minimum
that occurred was not well measured in this experiment. Also, the initial noise for
transistor #3 was different (smaller) than transistors #1 and #2, so some differences in
noise variation may be expected.

It is also noted that as shown by the results in Chapter 4, the post-stress noise
levels will return towards the initial higher values after thermal annealing. However, total
recovery is not observed on the devices after around 60 hours of annealing at T = 225 to
240 C. It is known that the application of high temperature annealing afier the
electromigration-induced compressive stress has built-up due to forward-bias stress would
allow the metal to creep reducing the pressure. Hemmert et al. [18] showed that such
compressive stress could be totally removed after 15 minutes of annealing at 400 C. Also,
as described in Section 5.1.2, the dislocation movement induced by an external
compressive stress can be reversed by thermal annealing. The post-annealing noise
behavior suggests that a part of the dislocations which initially moved away fi'om the
surface due to the compressive stress can move back to the surface after annealing. The
thermal annealing is believed both to remove the electromigration-induced compressive
stress and to activate the backward movement of dislocations. Consequently, a increase of

noise levels can be observed after annealing.

 

 

 

CHAPTER 6
SUMMARY AND CONCLUSIONS

In this study, reliability issues resulting from hot-carrier effects and
electromigration effects in bipolar junction transistor structures were investigated. The
physical observables for this study included device I-V characteristics and low-fi'equency
noise properties. Four kinds of bipolar junction transistors with different manufacturing
technologies were used: namely, TIN3, TOUT, TSE031 and the Hemmert test structure.
TIN3 and TOUT devices were manufactured by conventional oxide isolation methods.
However, TOUT had a Schottky diode clamp but TIN3 did not. TSE031 devices were
advanced technology transistors, fabricated with polysilicon base contacts and side-wall
oxides. The Hemmert test structure, which contained a set of seven transistors, was a test
structure designed particularly to investigate the electromigration induced compressive
stress effects. A detailed description of these devices is presented in Section 3.1 and
Section 4.1.

The noise measurements for this study were performed by biasing the transistor in
a forward active bias condition under both the common-collector and common-emitter
configurations. The dominant low frequency l/f noise source of transistors was identified
by determining the current dependence of their noise power spectral densities. A quadratic
current dependence of the noise power was observed; consequently, it was concluded that
the dominant pre-stress and post-stress low frequency 1/f noise source for the transistors
under study is due to surface recombination states located between the base and the

emitter.
142

143

Reverse-Bias Stress

For the reverse-bias stress study, both TIN3 and TOUT devices were investigated.
Transistors were electrically stressed at 23 C by applying three reverse DC bias voltages (-
3.5 V, -4.0 V, and -4.5 V) to the base-emitter junction and by applying two AC conditions
(0 to -4 V and 1 to -4 V) to the base-emitter junction. The base-collector junction was
short-circuited. Stress times varied up to 2000 hours. Two post-stress recovery
mechanisms, namely thermal annealing and forward-bias induced recovery, were also
studied. Observed degradation phenomena included a decrease of hFE and an increase of
low-frequency noise levels after reverse bias stressing of the base-emitter junction of
bipolar junction transistors. The observed gain and noise changes are attributed to both
interface states and oxide trap states produced by hot electrons. Forward-bias induced
recovery allows a partial reversal of degradation and is believed to be due primarily to a
reduction in the number of electrons trapped in the oxide. Thermal annealing, which is
capable of removing of interface states as well, produces a larger recovery. Furthermore,
because of the effect of forward-bias induced recovery, AC stress that included forward-
bias cycles produced less degradation than AC stress without forward-bias cycles.
Consequently, the degradation of the transistor not only depends on the time over which a
reverse bias is applied, but also on the history of biases applied between the reverse-bias
periods. Also, it was found experimentally and theoretically that after DC reverse-bias
stress the increased base current was linearly proportional to the increase surface
recombination surface noise power. The slope of this linear relation did not depend on the
stress voltages. This linear relation allows one to predict the noise changes, whose
characterization requires a more complicated experimental process, by knowing the base
current changes after stress.
Forward-Bias Stress

For the forward-bias stress study, TIN3, TSE031 and the Hemmert test structure

were the devices under investigation. The devices were electrically stressed at various

144

temperatures (from -75 C to 240 C) with large stressing emitter current densities (fiom 1
mA/um2 to 5 mA/umz). Stress times varied up to 2500 hours. It was shown that the
combination of high currents and high temperatures produced gradual gain degradations
on both TIN 3 transistors and the transistors on the Hemmert test structure, and produced
precipitous failures of TSE031 transistors. Similarly the application of high currents and
high temperatures produced changes in transistor noise characteristics for all three
technologies. Specifically, in all transistors stressed, the low-frequency noise initially
decreased. It was also observed in TIN3 transistors and in the transistors on the Hemmert
test structure that the noise eventually started to increase again at the point in time when
an appreciable gain decrease was observed as the stress continued. For TSE031
transistors, the initially decreased noise stayed in the decreased levels till the precipitously
failures finally occurred. The failures were due to electromigration produced open circuits.
Degradation Mechanisms

Reverse-bias degradation of gain and noise attributes is consistent with hot
electron degradation. However, for the forward-bias induced changes in gain and noise, it
is believed that electromigration induced compressive Stress played an important role in
the phenomena of noise decrease followed by noise increase observed during forward-bias
stress. As mentioned earlier, the dominant l/f noise source inside the stressed transistors is
due to surface phenomena. Consequently, the result of forward-bias stress induced
reduction of 1/f noise indicates that the stress reduces noise producing states at the
surfaces. Such surface states may be due, for example, to crystal dislocations, which have
been reported to be caused, for example, by high doping or by process induced stress and
have previously been shown to be related to l/f noise. As described in Chapter 5, the
magnitudes of electromigration-induced compressive stress in this study are sufficient (>
108 dyn/cmz) to cause appreciable dislocation motion, and the direction of the force is
away from the device surface. Consequently, from this viewpoint, electromigration

induced compressive stress tends to drive surface dislocations beneath the surface where

145

they are no longer contribute to surface 1/f noise. However, as the forward bias stress
continues to long stress times, the compressive stress eventually increases to a point (z
109 dyn/cmz) sufficient to cause appreciable band-gap narrowing. At this point, there is a
resulting increase in base recombination current causing gain degradation. Also, since 1/f
noise is proportional to the recombination current squared, the l/f noise at a given base-
emitter voltage increases accordingly with the gain decrease.

The forward bias induced noise decrease, at least initially, is opposite to
expectations for hot electron effects, by which a monotonic noise increase with stress
times will be observed. Consequently, the low-frequency noise behavior provides an
indication as to whether the cause of gain degradation under forward bias stress in a
particular technology is due to electromigration or hot electrons.

Future Studies

There are three suggestions for the future studies related to the current work.
First, a simulation of hot electron induced noise changes after a reverse-bias stress would
be useful in order to compare the simulation results with the experimental results
presented in this dissertation. Secondly, the forward-bias stress effect should be further
studied on advanced poly-emitter devices, and the results should be compared with the
current results performed on conventional and advanced poly-base transistors.
Consequently, the physical causes, either hot electron effects or the electromigration
effects, of forward-bias induced degradation on advanced poly-emitter transistors also can
be identified. Finally, the direct experimental evidence of electromigration effects on near-
surface dislocations is necessary to confirm the hypothesis developed in Chapter 5. For
example, methods of producing etch pits may be used to observe the movement of

dislocations after an electromigration induced compressive stress is built up.

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