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This is to certify that the
dissertation entitled
VLSI Smart Logic Modeling and Design For
Optimum Chip Feature Characterization

presented by

Hsien-Hui Tseng

has been accepted towards fulfillment
of the requirements for

Ph.D. degree in Electrical
Engineering

 

 

  

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MSU Is An Affirmative Action/Equal Opportunity Institution

 

 

 

 

 

 

 

VLSI SMART LOGIC MODELING AND DESIGN FOR
OPTIMUM CHIP FEATURE CHARACTERIZATION

By

Hsien-Hui Tseng

A DISSERTATION

Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

DOCTOR OF PHILOSOPHY

Department of Electrical Engineering

1993

ABSTRACT
VLSI SMART LOGIC MODELING AND DESIGN FOR
OPTIMUM CHIP FEATURE CHARACTERIZATION
By
Hsien-Hui Tseng

Because the transportation and handling of agricultural products can result in various
degrees of damage due to impacts, a 38 mm (1.5 in.) diameter self-contained Instrumented
Sphere (IS) was designed to record the impacts it experiences while being handled with
like-sized commodities (plums, tomatoes, peaches, strawberries). Compared with the 89
mm (3.5 in.) diameter sphere previously reported by Zapp et a1., 1990, this miniaturized
unit contains a composite smart logic chip with the same 32K of memory, approximately
1/ 12 the volume, smaller batteries, and a smaller triaxial accelerometer.

Spatial optimization was performed by computer to investigate the practical minimum
volume configuration that can be realized using commercially available components. The
saving in power consumption for the smart logic configuration was also investigated. The
combination of reduced power, small circuit elements and optimum packaging produce a
feasible sphere of 38 mm (1.5 in.) diameter.

The overall objectives accomplished in this research report are: 1) development of a
general design rule for a n-Dimensional (n-D) data acquisition system with m restrictions
(m or more of the input signals from each of the n independent sources are above some
threshold for signal acceptance); 2) design of a 3-D smart logic data acquisition system
with one restriction (This latter system replaces a u-P circuit and other supporting logic of
an operational data acquisition system. Essentially a single chip data acquisition system
replaces a circuit board system of 5 chips); 3) demonstration of a VTI smart logic simula-
tion to verify the single chip performance, and; 4) assessment of the size, power con-

sumption, and cost compared to the operational u-P based system.

Copyright by
Hsien—Hui Tseng

1993

To my family

iv

ACKNOWLEDGMENTS

I would like to express my greatful appreciation and gratitude to the members of my
Dissertation Committee: Dr. H. Roland Zapp, Dr. Mohammad Aslam, Dr. Galen K.
Brown, Dr. Bong Ho, and Dr. David Yen. Their constructive comments and guidance
were invaluable to the completion of this thesis.

A special appreciation goes to Dr. H. Roland Zapp and Dr. Mohammad Aslam, my
advisors, for serving as chairs of my dissertation committee. Their encouragement,
advice, support and friendship helped each step along the way and their excellent dedica-
tion provided continuous inspiration.

I wish to acknowledge Dr. Galen K. Brown for providing an assistantship during the
course of this project.

I also wish to express my gratitude to Dr. Paul R. Armstrong for his assistance.

At last I wish to express my love and gratitude to my family for their support.

TABLE OF CONTENTS

 

 

 

 

 

 

LIST OF TABLES - ...... - - ix
LIST OF FIGURES x
1. INTRODUCTION - 1
2. BACKGROUND 4
2.1 Historical Perspective ............................................................................................. 4
2.2 Previous u-P Based Data Acquisition Units .......................................... 8
2.3 Criteria for 3-D Data Acquisition ........................................................................ 10
2.4 VTI and CMOS VLSI Design Considerations ..................................................... 11
3. SYSTEM DESIGN STRATEGIES 13
3.1 A Review of the u—P Based IS .............................................................................. 13
3.2 Smaller Size and Reduced Power Consumption by Smart Logic ......................... 14

3.2.1 General Design Rules for n—D Data Acquisition with m

Restrictions .................................................................................................. 14

3.2.1.1 Clock Design ....................................................................................... 15
3.2.1.2 Binary Code Development .................................................................. 18

3.2.1.3 Signal Latching ......................................................................... 18
3.2.1.4 Comparison of Input Signal with a Threshold .................................... 18

3.2.1.5 Memory Address Counting ................................................................. 18

3.2.2 Flow Chart for System Operation ................................................................ 25

3.3 The Algorithm ....................................................................................................... 26
3.4 Special Case (Clock Count Per Burst Less Than Data Dimension) ...................... 28

vi

3.5 Application (Design of a Smart Logic 3-D Data Acquisition System

 

 

 

 

 

 

with One Restriction) ............................................................................................ 28
3.5.1 CSC Design .................................................................................................. 28
3.5.2 CTB Design ................................................................................................. 30
3.5.3 LATCH Design ............................................................................................ 30
3.5.4 COMP Design .............................................................................................. 44
3.5.5 COUNTER Design ...................................................................................... 44
3.6 Software Program ................................................................................................. 51
4. VARIATION IN SIZE, POWER AND HEAT DISSIPATION WITH
SPECIFICATION REQUIREMENTS 53
4.1 Estimation of Size, Power and Heat Dissipation for a u-P Based IS .................... 53
4.1.1 Estimation of Power Dissipation in a 3.5 Inch u-P Based IS - 53
4.1.2 Estimation of Power Dissipation in a 2.5 Inch u-P Based IS. ....................... 54
4.1.3 Estimation of Power Dissipation in a 2.0 Inch u-P Based IS

Multichip Housing - -- - - ....... 55

4.2 Estimation of Size, Power and Heat Dissipation for a Smart Logic Chip
Based IS ...... - ........ - - ...... 55
4.2.1 Estimation of the Size ................................................................................... 56
4.2.2 Estimation of the Power and Heat Dissipation ............................................. 57
4.3 Ultimate Size, Power and Heat Sink Consideration .............................................. 58
4.4 Variation of Power and Size vs Specification Changes ........................................ 60
5. SIMULATION RESULTS 79
5.1 Architecture for IS Smart Logic Chip ................................................................... 80
5.2 Simulation Results ................................................................................................ 80
5.3 Discussion ............................................................................................................. 83
6. CONCLUSIONS AND DIRECTIONS FOR FUTURE WORK 95
6.1 Conclusions ........................................................................................................... 95

6.2 Directions for Future Work .................................................................................... 96
APPENDICES , 97
BIBLIOGRAPHY _ __ - - _ - -- 125

 

 

LIST OF TABLES

Table 1 - Software program for synthesizing the n-D with m restrictions data
acquisition system. ........................................................................................... 52
Table 2 - Maximun u-P current consumption for different models from two
manufacturers ................................................................................................... 62

Table 3 - Current and power consumption for the conventional u-P circuit

(89 mm or 3.5 in. IS) and the composite smart logic chip ............................... 63
Table 4 - IS dimensions for different geometrical configurations ..................................... 64

Table 5 - CMOS currentconsumption values for various quad gates at T =25 °C for

different manufacturers .................................................................................... 65
Table 6 - Minimum 18 dimensions for different geometrical configurations .................... 66

Table 7.a - Gate count variation vs different specifications relative to tA/D =1 16

usec and maintaining t1=0.125 usec, f=0.003 MHz, and n=3 conditions ....67
Table 7 .b - Gate count variation vs different specifications relative to tA/D =1 16

usec keeping t1=0.125 usec, f=0.0025 MHz, and n=3 fixed ....................... 68

Table 8 - Power variation vs different specifications relative to t AID =1 16 usec

maintaining t1=0.125 usec, f=0.003 MHz, and n=3 fixed ............................ 69

LIST OF TABLES

Table 1 - Software program for synthesizing the n-D with m restrictions data

acquisition system. ______ _ - - 52

 

Table 2 - Maximun u—P current consumption for different models from two
manufacturers ................................................................................................... 62
Table 3 - Current and power consumption for the conventional u—P circuit

(89 mm or 3.5 in. IS) and the composite smart logic chip ............................... 63

 

Table 4 - 18 dimensions for different geometrical configurations ............. 64
Table 5 - CMOS current'consumption values for various quad gates at TA=25 °C for

different manufacturers - ........... - - - -65

 

Table 6 - Minimum IS dimensions for different geometrical configurations .................... 66
Table 7.3 - Gate count variation vs different specifications relative to t AID =116
usec and maintaining t1=0.125 usec, f=0.003 MHz, and n=3 conditions ....67
Table 7.b - Gate count variation vs different specifications relative to tA/D =116
% usec keeping r1=o.125 usec, r=o.oozs MHz, and n=3 fixed 68

 

Table 8 - Power variation vs different specifications relative to t AID =116 usec

maintaining t1=0.125 usec, f=0.003 MHz, and n=3 fixed ............................ 69

LIST OF FIGURES

Figure 1 - A t usec clock with f MHz frequency forms the waveform SWC ............. 20
Figure 2 - Block diagram for the n-D data acquisition system with m restrictions ..... 21

Figure 3 - The detailed circuit diagram for the CSC (counter & switch clock)

generator for n=3 ....................................................................................... 22
Figure 4 - The waveform SWC, with 3 pulses of 2 usec at a 0.003 MHz

repetition frequency ................................................................................... 23
Figure 5 - The detailed circuit diagram for the CTB (clock-to-binary) generator

for n=3 ........................................................................................................ 24
Figure 6 - A t usec clock with f MHz frequency forms the waveform SWC

(for the special case n=4) . ........ .............. -32

 

Figure 7 - The schematic circuit diagram for the CSC (counter & switch clock)
generator for the special case n=3 .............................................................. 33

Figure 8 - The detailed circuit diagram for the CSC (counter & switch clock)

 

generator for the special case n=3- -- .......... 34
Figure 9 - The simulation results of the CSC (counter & switch clock)

generator circuit for the special case n=3 .................................................. 35
Figure 10 - The waveform SWC, with 3 pulses of 128 usec at a 0.002604 MHz

repetition frequency for the specific smart logic case ............................... 37
Figure 11 - The simulation results of the CTB (clock-to-binary) generator

circuit for n=3 ............................................................................................ 38

Figure 12 - The simulation results for the latch circuit for the special case n=3,

m=1, t’=125 nsec, tA/D =116 nsec, f=0.003 MHz .................................. 39
Figure 13 - The detailed circuit diagram for a two stage latch with n=3, m=l ........... 42
Figure 14 - One impact force which contains five sampled data ................................. 43
Figure 15 - The simulation results for an 8 bit comparator with predetermined
thresholds ................................................................................................... 45
Figure 16 - The detailed circuit diagram for an 8 bit comparator with

 

predetermined thresholds - - . . - -- ..... 46
Figure 17 - The simulation results for a 16 hit counter which is divided into

four parts .................................................................................................... 47
Figure 18 - The detailed circuit diagram for a 16 bit counter ...................................... 49
Figure 19 - Block diagram for the smart logic chip ..................................................... 50

Figure 20 - Patterned silicon substrate to support the SLIC, RAM, AID

and Op Amp dice in order to form the composite smart logic chip ........... 70
Figure 21 - The front view of the typical configuration for the sphere of 30 mm

(1.18 in.) diameter. Not included: rigid foam, beeswax, and epoxy .......... 71
Figure 22 - The side view of the typical configuration for the sphere of 31.62 mm

(1.25 in.) diameter. Not included: rigid foam, beeswax, and epoxy .......... 72
Figure 23 - The front view of the typical configuration for the sphere of 30.24 mm

(1.19 in.) diameter. Not included: rigid foam, beeswax, and epoxy .......... 73
Figure 24 - The front view of the typical configuration for the sphere of 28.72 mm

(1.13 in.) diameter. Not included: rigid foam, beeswax, and epoxy .......... 74
Figure 25 - The front view of the typical configuration for the sphere of 24.58 mm

(0.97 in.) diameter. Not included: rigid foam, beeswax, and epoxy .......... 75
Figure 26 - The front View of the typical configuration for the sphere of 28.28 mm

(1.12 in.) diameter. Not included: rigid foam, beeswax, and epoxy .......... 76
Figure 27 - f' vs different specifications as given in Table 7.a ................................... 77
Figure 28 - Gate count variation vs different specifications as given in Table 7.b ..... 78

Figure 29.a - The detailed circuit diagram for the data acquisition system

with n=3, m=l ............................................................................................ 85
Figure 29.b - The detailed circuit diagram for the smart logic chip

(special case of n=3, m=1) ......................................................................... 86
Figure 30 - The simulation results of the CSC (counter & switch clock)

generator circuit for n=3. - - -- - - - -- - - ........ 87
Figure 31 - The simulation results of the data acquisition system with n=3,

m=1, t’=125 nsec, t=2 nsec, f=0.003 MHz ................................................ 88
Figure 32 - The typical simulation results of the smart logic chip

(special case of n=3, m=1) ......................................................................... 91
Figure 33 - Two impact forces which contain ten sampled data. ................................. 94

CHAPTER 1

INTRODUCTION

Agricultural products, sensitive electronic equipment, glass and bottled goods are
among the many items which can be damaged by impact or shock. To identify the sources
of damage, instrumentation mounted to the item or substitution of the item by an electronic
clone have been proposed. For example, an Insu'umented Sphere (IS) accompanying
apples during mechanical handling operations has provided the monitoring required to
identify locations and magnitudes of significant impacts which cause bruise damage to
apples [1],[2]. This IS [3] had a diameter of 89 mm (3.5 in.), which was adequate for mea-
surements with apples, potatoes, cucumbers and other medium sized produce.

The 89 mm (3.5 in.) 18 has been very useful for identifying damage causes; impact loca-
tions and impact magnitudes. A smaller IS is essential to accomplish similar results in
smaller size produce such as strawberries, plums, mushrooms, peaches, eggs, etc.. One
method to achieve a size reduction was to re-package the electronics in a 63.5 mm (2.5 in.)
diameter IS [4], probably the smallest size possible without the use of very large scale inte-
gration (VLSI). A second approach is to develop a multich housing [5] which replaces
four standard integrated circuit (IC) chip with four dice mounted on a single substrate with
pinouts compatible to those of the microprocessor (tr-P). A piggyback sandwich type con-
figuration results which has dimensions of just the u-P. Operational power reduction is nec-
essary to accommodate smaller batteries for the much smaller size IS. Heat sinking must

be considered because of the high circuit density in the reduced size. These conflicting

requirements suggest a CMOS smart logic VLSI design [6],[7] to achieve the simultaneous
objectives of small size and low power consumption.

A CMOS smart logic chip approach should produce the smallest size IS. The approach
to chip miniaturization is to eliminate the u—P and replace it with a “smart logic” low power
consuming chip. The motivation here is to simplify the electronics by using a smart logic
integrated circuit (SLIC) for performing the system operation instead of the u-P since the
u-P is highly underutilized in the presently available IS. Thus, by developing dedicated
logic, which should be compatible with VLSI technology, the size [8],[9], power consump- V
tion [9]~[12] and cost [13] of the miniaturized 18 is substantially reduced. In the previous
18 designs, the u-P was the major power consumer. A factor of two in power reduction is
realized using smart logic without a u—P.

A A smaller IS which consumes less power than the previous 89 mm (3.5 in.) diameter
IS and present 63.5 mm (2.5 in.) diameter is a design objective. A final size of less than 38
mm (1.5 in.) diameter, or about ll 12 the volume of the earlier 89 mm (3.5 in.) model,
results. The miniature IS uses a smaller triaxial accelerometer, a SLIC, operational ampli-
fier (Op Amp), analog-to-digital conversion (AID) and the same 32K of external random
access memory (RAM). The final design eliminates the circuit board by incorporating the
circuit in a single IC package which contains four IC dice. These dice are mounted on a
patterned silicon substrate that fits in the package. After bonding the dice [14]~[17], the
package is sealed using standard IC package processing. The completed electronic package
is encased in rigid foam and cast in beeswax to provide structural hardness for the IS. After
adequate testing, an epoxy casing will be utilized. An optimization routine shows that a 38
mm (1.5 in.) diameter is feasible using commercially available elements. A number of ele-
ment packaging arrangements were configured with the optimization routine. The results
of these optimization configurations are presented. The power and heat dissipation analysis
for the smart logic configuration is included.

Chapter 2 gives a review of some researchers’ efforts in detecting and explaining

bruising in fruit during harvesting and handling. Criteria for 3-Dimension (3-D) data
acquisition, VTI and CMOS VLSI design considerations and previous u—P based data
acquisition units are also addressed in that Chapter. Chapter 3 presents system design
strategies which include system operation, general design rules and algorithms for n-D
data acquisition with m restrictions, special cases and applications and the software list-
ing. Chapter 4 provides the analysis of size, power and heat dissipation for the u—P based
IS, the composite smart logic chip based IS and the absolute size limit for an IS. Power
and size are substantially reduced from the commercially available unit and heat dissipa-
tion represents no problem for size reduction related to multich housing. The variation
of power and size vs specification changes is also provided. Chapter 5 presents simulation
results and discussion. Chapter 6 discusses the general results and conclusions and pro-

vides some ideas for future studies.

CHAPTER 2

BACKGROUND

2.1 Historical Perspective

During the past two decades many researchers tried to detect and explain bruising in
fruit during harvesting and handling. Rider [18], developed a pseudo-fruit to measure the
forces involved in the collisions and to relate these forces to the generation of bruises. In
this pseudo-fruit, three separate accelerometers were mounted in a 57-mm diameter steel
shell covered with 9.5 mm of Ensolite material. This pseudo-fruit was capable of record-
ing the maximum acceleration and the time duration of an impact by using cables to trans-
fer acceleration signals to a chart recorder. Rider showed that acceleration can be used to
predict internal shear stress, if the modulus of elasticity and the radius of the surface
impacted by the pseudo-fruit were known. Although physical properties of the Rider
pseudo-fruit were similar to those of a peach, the duration of impact did not agree with the
values obtained from the Hertz theory. He attributed this to the ”bottoming out" of the
covering material at relatively high impact values. Rider et a1. [19] also studied the
pseudo-fruit’s calibration and how it would correlate to bruise damage in fnrit. The previ-
ous other researchers had showed that the probability that a peach will be bruised by
impact can be related to the internal shear stress developed in the fruit, based upon the
assumption that the fruit behaves elastically. So Rider calibrated the accelerometer out-

puts to the shear stress experienced by the pseudo-fruit. Thus the shear stresses experi-

enced by the pseudo-fruit were supposed to correlate directly to bruise damage. All of
Rider’s formulas assumed perfectly elastic impacts. In order to test the mathematical rela-
tionships, a 76.2 mm (3.0 in.) diameter, 204 gm (0.45 lb) pseudo-fruit which contained a
piezoelectric triaxial accelerometer was constructed. The small flexible coaxial cables
were connected between this encased sensor and a tape recorder. The shell of the pseudo-
fruit was a 1.52 mm (0.06 in.) thick 57.15 mm (2.25 in.) diameter steel sphere covered
with a layer of 9.53 mm (3/3 in.) thick type AH EnsoliteR over which three layers of 3M’
Fastbond-10R contact cement were applied. The accelerometer was rigidly mounted inside
the shell. The unit had a coefficient of restitution of 0.42 when dropped 152.4 mm (6 in.)
onto concrete. The modulus of elasticity of the pseudo-fruit, 489 kPa (71 psi), was deter-
mined both by measuring the area of contact during impact and by using a quasi-static
compression test. In Rider’s calibration procedure the only externally supplied variable,
was the modulus of elasticity of the impacted surface. From the data, he only made use of
the peak acceleration and impact duration. In order to make the theoretical calibration
procedure correspond to experimental data however, the impact duration time had to be
multiplied by an unexplained factor of 2 before being used in the calibration procedure.

Pullen and Diener [20] developed a low cost FET triaxial accelerometer. The advan-
tages of this system were the vector summing capabilities, using long cables without cable
noise or cross talk, high power gain and low impedance output. Three cables were
required to transmit the impact data to a recorder. This accelerometer approach was sub-
sequently duplicated by others in recent telemetry systems. Another approach was to use
telemetry in a pseudo-fruit to transmit the variation in accelerations via a FM transmitter.
The objective was to remove any sensing cables from the pseudo-fruit in order to enable
.the pseudo-fruit to simulate the free movement of a fruit.

O’Brien et a1. [21] developed a telemetry system which contained three miniature and
separate FM transmitters with antennas, one for each axis and a triaxial accelerometer.

The accelerometer and electronics were enclosed in a 50.8 mm (2 in.) hollow fiber glass

sphere covered by 10.2 mm (0.4 in.) thick layer of resilient material. A standard FM
receiver was used to pick up the pseudo-fruit signal and store this signal on a multi-chan—
nel analog tape recorder. Because of low transmitter power, the receiver’s antenna had to
be placed very close to the pseudo-fruit. The calibration accuracy was estimated to be
:l:5%. The pseudo-fruit was not sensitive to accelerations below 0.5 g (gravitational
force), or to frequency response down to 2 Hz, because these were believed unimportant
for bnrise formation.

Aldred and Burch [22] developed an electronic shock-sensing device for detecting
amplitudes and frequencies of acceleration of peaches during harvesting and handling. A
microcomputer and an analog vector summing circuit were added to this impact detection
system. This impact detection system still consisted of a sensing unit and receiving sta-
tion. Instead of transmitting 3 channels of data, only one transmitter (for the resultant
acceleration) was placed inside a 67 mm (2.64 in.) sphere for transmitting one channel of
data. Data from the sensor were telemetered to a microcomputer, then processed, stored
and retrieved later as a direct readout of maximum impact or as a curve on a strip chart
recorder. Approximately 2 sec of data at a 1 kHz sampling rate were stored and processed
for each impact. It was stated that additional experimentation was necessary to insure that
the pseuso-fruit resembles a real fruit and to correlate output of the pseudo-fruit with the
actual bruise. No attempts were made to calibrate the output of this system.

Jenkins and Humphries [23] developed a new technique to assess impact damage.
They used a fluid filled bladder with slit valves to meter fluid flow during impact. This
bladder was a hollow vinyl sphere (toy ball) approximately 76 mm (3 in.) in diameter with
a 3 mm (0.12 in.) wall fitted with six equally spaced one-way slit valves. According to the
relationship between water loss and impact velocity, this system resulted in good correla-
tion between drop height on a hard surface and water loss. The only drawback was the
lack of an automated recording system.

Halderson et a1. [24] developed their first generation impact detection telemetry sys-

tem to predict impact bruises to potatoes. They used a triaxial accelerometer configuration
with three miniature transmitters which operated in the commercial FM band and a three
channel FM receiver. The unit operated up 30 m (100 ft.)from the receiver but was too
directional. This research, however, lacked both a true calibration procedure and a field
test performance analysis. Their second generation impact detection device had a single
transmitter system with three subcarriers. The most efficient and non-directional antenna
for the unit were two wire loops of approximately 6 cm (2.4 in.) diameter which oriented
90 degrees to each other. A special three channel FM telemetry receiver was used to
receive the transmitted signal. During impact tests, the correlation of the enclosed accel-
erometer voltage with decorder voltage was slightly better than 80%. By 1986 Halderson
et al. [25] had built and tested a third generation impact detection device. The main
changes from his previous device were in the packaging. The new unit enclosed all of the
electronics in a 40 mm x 40 mm x 57mm aluminum box. Three small LC antenna were
mounted on the outside of the three perpendicular planes of the box. The aluminum box
was molded in silicone (Dow Corning RTV-3110) to form a cylindrical package that was
100 mm (4 in.) in length and 84 mm (3.3 in.) in diameter, weighed 654 gm (1.44 lb), and
had an overall specific gravity of 1.18. The device was tested under impact conditions by
dropping a 1054 mm (41.5 in.) in length, 286.7 gm (0.63 lb) in weight metal rod, with a
spherical hard rubber tip (36.5 mm (1.44 in.) in diameter), onto the device which was sup-
ported by a 75 mm (3 in.) thick foam pad with a force-deflection rate of 275 (gm/cm2)lcm
(9.93 (lb/in.2)lin.). Ten replications of 0.2 I (1.9 x 10'4 BTU) of energy were used for each
axial direction. Coefficients of variation were 8.3%, 8.4% and 5.2% respectively for the
X, Y and Z axes. The transmission distance was evaluated around a potato harvester, but
no range distances were reported.

Anderson and Parks [26] developed two impact detection devices (two physical units)
using a pressure sensor transducer in one and a single axis accelerometer in the other. The

pressure version was packaged by mounting the electronic assembly inside a hollow rub-

her ball which was then sealed, thus containing air at atmosphere pressure. The acceler-
ometer version is built up by surrounding the electronic assembly with cushioning foam
and an outer shell. Both devices used telemetry to transmit data to a receiver with an
attached tape recorder. A two channel tape recorder was used so that data could be
recorded on one channel and voice commentary on the other. Both devices used the same
FM transmitter design and battery configuration which could operate for eight hours.
The pressure version was calibrated by compressing it between two plates with a known
force, while the accelerometer version was calibrated by dropping it from known heights.
The acceleration data was used to generate an ”equivalent drop height number”. These
devices were used to test potato handling equipment.

Kerr and Wilkie [27] described a uiaxial accelerometer and telemeu'y system, as an
automated data collection system, for use on a potato harvester to provide an immediate
indication of damage. This unit included a computer on-board the harvester which stored
the acceleration, temperature and other critical data for further analysis. No calibration,
accuracy or performance results were discussed, however.

More recent work was performed by Siyami [28], Zapp and Armstrong [3], Sober [2]
and Brown [1]. The strong continuing interest is due to the recent developments in VLSI
design and implementation techniques and the continuing development of miniaturized
accelerometers and batteries. The recent technical advances have also reduced the power

consumption of most components.

2.2 Previous u-P Based Data Acquisition Units

The application of the u-P based system to data acquisition systems has been common.
Lowther et al. [29] designed a general purpose dual-microprocessor data acquisition
system. The hardware allowed data capture at speeds of up to 600 kHz and the software
provided the user with a simple but powerful interface for setting up test requirements.

These requirements included a certain amount of real time control for retrieving and

examining the data. This system has been used to investigate the penetration of magnetic
fields into nonlinear laminated media under transient and steady state conditions and also
to study an electromagnetic suspension system and linear motor drive for advanced
ground transportation research.

Hill et a1. [30] developed a u-P based digital wattrneter which can measure power in
the frequency range dc to 1 kHz with a full scale accuracy of better than 0.5%. First, the
u-P measured the voltage waveform period and then computed the sampling interval and
number of samples. The measurement of average power must be taken over an integer
number of cycles. Second, it is necessary to multiply together the samples of the voltage
and current waveforms, accumulate the products over the measurement period, and then
divided by the number of samples. Finally, we can read out as a 4-digit display of the
scaled average power.

Wallingford [31] designed a simple data acquisition scheme which was implemented
on a 16-bit microcomputer. This system can simultaneously acquire and store the output
of two independent 8-bit AID at a 115 kHz rate with a 3 MHz clock. This high speed data
acquisition is made possible by configuring the interface to respond to two separate non-
flicting parallel processes. The simultaneous conversion of two AID’s made this data
acquisition scheme well suited for FFI‘ signal processing systems.

Sridharan [32] developed a synchronous multichannel (8-channel) data acquisition
system by using a separate AID converter for each channel. The synchronous sampling
became very desirable when the data was required for system identification studies, or
when fast data conversion of a large number of analog channels was involved. For a
microcomputer clock period of 330 nsec, the program took only 93 usec of CPU time to
convert and store the results of 8 channels in RAM.

Adam [33] made a telemetric seismic data acquisition system which sampled trans-
ducers continuously but stored data only when a threshold was exceeded. This system

consisted of remote encoding stations and data acquisition stations. Each remote station

10

consisted of up to three seismic sensors operating at sampling rates of 60 samples/sec.
The highest single sensor sampling rate was 240 samples/sec. If any of 24 possible
encoder stations registered above the threshold for a predetermined time, all of the
encoder stations were recorded. If all of the signals were below. the threshold for a short
period of time, recording was terminated. In order to make the threshold process immune
to nonseismic disturbance such as rain and eliminate the need for threshold adjustments, it
is necessary to divide the short term average by the long term average.

Ahrens et a1. [34] developed a multi-channel microcontroller-based data acquisition
unit for logging the activity of cattle on the range which was small enough to be carried by
cattle without bothering them. The chewing and walking habits of the cattle were of pri-
mary interest to the researchers. Significant motion from these habits produced 5 volt
pulses out of the sensor and conditioning circuits which could be sent to the microcontrol-
ler.

Negro [35] designed a low power u-P controlled data acquisition system which used
nonvolatile bubble memory cartridges for mass data storage. The system was battery
powered. By chosing magnetic bubble memory, the period of unattented operation in the
field can increase from 2 weeks to about 2 months and improve reliability. The input volt-
age to the data acquisition system is derived from the output of a gamma-ray ionization
chamber that uses a temperature-compensated electrometer, or other moderately high out-
put transducer. CMOS technology and power switching techniques were used in this sys-

tem achieving very low power consumption (less than 10 mW).

2.3 Criteria for 3-D Data Acquisition

The need for data acquisition is very common in industrial applications. Some exam-
ples of user needs have already been introduced in Section 2.2. For a n-D data acquisition
system, in order to save memory by recording only useful data, some restrictions or

thresholds for data acceptance are predetermined. For example, in a 3-D data acquisition

11

system for measuring and storing impact accelerations along 3 orthogonal axis, a vector
threshold or a single axis threshold can be set in order to efficiently utilize the available
memory. The single axis restriction is more easily implemented than a vector restriction.
The n-D and m restrictions on a data acquisition system means discarding n data compo-
nents if less than m of these components are above some threshold where ann. For exam-
ple, if n=4, and m=2, with each threshold=5, any 2 or more of the 4 dimensions which
have absolute values above 5 results in storing all four components. If less than 2 compo-
nents are above 5, all four components are discarded. The criteria for the 3-D and I
restriction data acquisition system include the capability of recording and saving 3 data
components if any 1 or more of these components are greater than some threshold, for
instance :t10 g acceleration. This algorithm can be realized as follows: if |x(n)l210 or
ly(n)l210 or lz(n)|210, then output=x, y, z, otherwise, output=0, 0, 0. This provides a trans-
fer function given by H(z)=1 when lx(n)l210 or ly(n)1210 or lz(n)l210, otherwise H(z)=0.

2.4 VTI & CMOS VLSI Design Considerations

VTI is a comprehensive VLSI design technique [36]~[48] from VLSI Technology,
Inc. It covers a broad range of chip design tasks, including behavioral modeling, sche-
matic entry, simulation, symbolic layout, hand-crafted layout, analysis, and test descrip-
tion.

Complementary Metal Oxide Silicon (CMOS) technology has played an increasingly
important role recently because of the very low power consumption by this design config-
uration. Two types of MOS field effect transistors (FET) are produced by this technology,
an n-channel MOSFET (NMOS) and a p-channel MOSFET (PMOS). The NMOS transis-
tor consists of n diffusion, polysilicon, metal and insulating layers, while the PMOS tran-
sistor consists of p diffusion and the remaining similar materials.

The CMOS inverter, which uses an NMOS transistor as the driver and a PMOS tran-

sistor as the load, is characterized by low power consumption in the quiescent state, since

12

one of the two series transistors is always off except during a switching u'ansition from
one logic level to the other. Since power dissipation is a concern for VLSI NMOS chips,
CMOS is an attractive alternative for VLSI application. For this reason we use VTI tools,

which include CMOS standard cells, to design the smart logic chip.

CHAPTER 3

SYSTEM DESIGN STRATEGIES

3.1 A Review of the u—P Based IS

The existing tr-P based IS consists of one circuit board. The main electronic compo-
nents consist of an 8-bit CMOS Motorola u-P (XC68HC11) which has an integral 8-chan-
nel AID converter, 8K byte ROM (which stores the monitor program), and a R8232 serial
communication port. The other electronic components include 32 K RAM, latch, multi-
plexer and Op Amp.

The analog signal flow originates from a triaxial piezoelectric accelerometer (Colum-
bia model 512TX) and adjacent conditioning circuits. The conditioning circuits provide
impedance matching, voltage range scaling and noise filtering before input to the 0-5 Vdc
AID on-board the u—P. The u—P provides a multiplexed 8-channel 8-bit AID converter
with sample and hold.

The IS power supply consists of a rechargable, 7.2 V NiCad battery (Eveready CH22)
chosen because of its availability, reliability, cost and size. The charge capacity is about
80 mA-h. Voltage regulation to 5 Vdc is accomplished with a high efficiency low differ-
ential regulator from National Semiconductor (LM2931AZS). When the IS is in operation
the current drain is less than 14 mA, which corresponds to approximately 6 h of battery
power. At lower sampling rates or in a "sleep" mode the current can be reduced substan-

tially (down to 2 mA in the sleep mode).

13

14

The entire design is enclosed in a 89 mm (3.5 in.) diameter sphere cast in wax to

reduce the construction interface problem.

3.2 Smaller Size and Reduced Power Consumption by

Smart Logic

The application of digital electronics to data acquisition systems is common. A
sophisticated u-P based data acquisition system for agricultural damage monitoring has
been proposed and demonstrated. But the u-P occupies a relatively large volume and
demands the most system power. Thus, a new design idea using smart logic without a u-P
and other auxiliary components such as a latch and a multiplexer would be desirable. The
new design concept should accomodate a number of desired features, such as small size
and long Operation time. The design incorporates a suitable clock, a selection algorithm to
choose the correct analog signals, and a threshold filter. A memory address counting
scheme to store desired digital data is also required. The absence of the u-P assures a
reduction in power consumption by a factor of 2. However, without the u-P, the system
will suffer some flexibility; for example, the sampling rates will not be changable, the data
dimensions and thresholds can not be altered and the prograrnability is lost. These fea-
tures are not critical for a dedicated data acquisition device. Each new application will

require custom designed acquisition features.

3.2.1 General Design Rules for n-D Data Acquisition with m

Restrictions
A general data acquisition unit allowing 11 data lines and m restrictions is developed.
This general design can be reduced to the specific case to be realized in hardware. The n-
D and m restrictions means saving it data components if any m or more of these compo-

nents are greater than some threshold where ann. For example, n=4, m=2, threshold=5, if

15

any 2 or more of the 4 components have absolute values greater than 5 all 4 data compo-
nents are recorded otherwise these components are ignored. The design concept requires
developing a suitable clock, latch and other auxiliary circuits to realize a low cost, low
power consumption single chip data acquisition system. In order to get a suitable clock, as
the specification requires, it is necessary to develop a clock design. After obtaining the
desired clock, it is still necessary to choose the correct analog input signals for the AID, so
that the appropriate binary code development is necessary to multiplex the correct input
signal. It is also necessary to threshold the signals from the AID, to provide signal latch-
ing and to generate a comparison circuit with a threshold, to identify the desirable signals.
Finally, we need a 16-bit counter for address counting of the memory. The design specifi-

cation is divided into the following five main parts:

3.2.1.1 Clock Design

A CSC (Counter & Switch Clock generator) circuit can generate a t usec clock burst (t
represents the usec duration of the clock pulses in the burst) with f MHz frequency (f rep-
resents the frequency of the burst), see Figure l, for input to the CI'B (clock-to-binary
generator), as shown in Figure 2. In addition, the CSC generates a similar signal, when
latch enable (LE_) is low, for input to a 16-bit counter, identified as counter16.

Assuming that the crystal provides a clock period of t’, and considering the AID speci-
fications, we can choose t such that

t] t’ = p =2q
where q is an integer. Thus we need a q hit counter, identified as counter], which converts
an input clock period t’ from the crystal into an output period t, see Figure 3. Every f MHz
cycle, we will keep n (data dimension) clock pulses of t usec duration each and ignore the
(lid) - 11 remaining clock pulses. We will call this waveform SWC (switch clock), as
shown in Figures 1 and 2. The waveform SWC is generated as follows:

Express lItf (clock pulses count per sampling frequency) as a binary code d15d14

l6

...d2d1d0 If lItf is not an integer, it should be rounded off to form an integer. Define
f'=(1/t)-(1I(d15d14 ...d1 d,.1d1_2...d1do)), so that if lItf is an integer then f=f, otherwise
f’~f.

In our circuit design, we need the lower 1 bits of the sequence d15d14 ...d[dl.ldl.2
...d1do equal to n in order to get n clock pulses of t usec duration per f MHz cycle as
shown in Figure 1, where n is the data dimension and l=round-off of logzn +1.

Define s“. . .30: n where n, the data dimension, equals the decimal equivalent to the
binary sequence. If d,.1d,.2...d1do equals sumso, let f', the real frequency in the SWC
waveform, be equal to (llt) -(1I(d15d14.. .d2d1d0)) or f'=f'. In the general case where d“
(11.2.. .dldo does not equal 51.1.. .so, we can replace dud” . ..d1do by $1.1. . .so according to
the following round off nrles:

If dud”. . .dldo > s1.1...so,

or s,.1...s0 - d,,1d,.2...d1d0 s 2“, then f'=(lIt)-(ll(d15d14 ...d, s,.1...so)) ; '

whereas, if s,_1...so - d,.1d,.2...d1do > 2“, then f'=(1/t)-(1I(d15d14 ...d,s1.1...so-2')).
The above rules will result in a minirnun error of f-f" where f' is the real frequency in the
SWC waveform and f' is approximately equal to f. If f'=f and f-f' gives zero, the actual
frequency will be the ideal specified frequency.

In order to generate the SWC signal a second counter, identified as counter2, is neces-
sary to accept clock t and output Q15Q14...Q1Q0, see Figure 3. From the Q15Q14...Q1
sequence choose those which have a value of 1 when the corresponding modified values
(consistent with previously discussed requirements) of d15d14 ...d, has a 1 and connect
these Q values to an AND gate. After (llf') - tn usec the output of the AND gate, Tl, will
go high to enable the SWC. Similarly, from the Q15Q14...Q1Qo sequence choose those
which have a value of 1 when the corresponding modified values of d15d14. . .dzdldo has a
l and connect these lines to a NAND gate. For this latter case, we need to add an extra t’ to
the NAND gate input to avoid a transient spike. After l/f' usec the output of the NAND

gate, T2, goes low, which sends a low reset, RS1, to counter2 to reset Q15Q14...Q1Q0.

17

This allows T1 to go low, so that the total high time is tn. The resulting T1 and I generate
the SWC used in the CTB. From SWC and LE_, we can get CNTC (counter clock) for
counter addressing. See Figure 3 for the sequence described above.

Example:

Assume n=3, m=1, t=2 user and t’=125 nsec. Then t/t’=16=24. As seen in Figure 3.
counterl receives input from the clock with t’ =125 nsec and sends out a clock with t=2
nsec. In the design considered here, n=3, f=0.003, so every 0.003 MHz we keep 3 clock
pulses and ignore the remaining 164 clock pulses in order to obtain 3 clock pulses per 0.003
MHz, each of 2 usec duration. This waveform is shown in Figure 4, and is called SWC.

The waveform SWC is generated as follows:

The number of pulses per cycle is expressed by its binary representation:

1Itf=1I(2 nsec x 0.003 MHz)-167=10100111=d7d6. ..d2d1do

Since n=3, or s1s0=11, and dldo is the same as slso, the sequence d7d6...d2d1do
=10100111 remains unchanged.

The counter2, shown in Figure 3 receives 2 nsec clock pulses and outputs Qng
. . .QlQo. from which Q7Q5Q2 can be choosen for input to an AND gate. After 328 usec (2
user x (27+25+22)), T1 (the output of the AND gate) will go high to enable the swc. Sim-
ilarly, from the Q7Q5...QIQ0 sequence choose Q7Q5Q2Q1Qo and connect to a NAND
gate. For this latter case, we need to add an extra 125 nsec clock pulse to the NAND gate
in order to avoid a transient spike. Without this delay clock pulse, the output from the
NAND gate will induce a 4.1 nsec spike due to a timing conflict with countea. This spike
will produce a 3.0 V signal at RSI, which will incorrectly enable counter2 and will generate
an ambiguous output Q7Q6...Q1Qo. Assuming correct timing, after 334 nsec (2 nsec x
(27+25+22+21+2°)), T2, the output from the NAND gate, will go low and send this low,
R81, to reset all output Q7Q6. ..Q1Qo of counter2, so that T1 goes low giving a total high I
time of 6 nsec. Using T1 and a 2 nsec clock, we can generate SWC to be used in the CTB.
From SWC and LE_, we can get CNTC for counter addressing.

18

3.2.l.2 Binary Code Development

The AID has n channels (for example, the National Semiconductor ADC0808 data
sheet shows 8 channels), which are multiplexed by analog switches to choose the appro-
priate analog input. It is necessary to develop the binary code for correct AID addressing.
This is accomplished by the CTB circuit, as shown in Figure 5, which accepts the pulse
sequence SWC from the output of the CSC, and generates the binary code $1.1. . .so, where

l=round-off of log2n +land n is the data dimension for AID addressing.

3.2.1.3 Signal Latching

Because we need to threshold filter the signals from the AID, a latch is necessary to
store these signals in a buffer memory. The latch operates in two stages; First, we need to
store n parallel input signals from the AID into a pre-latch every f MHz cycle in order to
investigate m constraints. Second, if m or more constraints are satisfied, a low LE_ is sent
to the CSC to control the clock for the counterl6 and pass the n signals into the post-latch.
The data is stored in memory during the next f Nle cycle. If the constraints are not satis-

fied, the LE_ will remain high and the post-latch will block the signal.

3.2.1.4 Comparison of Input Signal with a Threshold

The signal from the AID is threshold filtered in order to save memory. Thus, we
require an 8 bit comparator circuit to compare the signals from the AID with predeter-
mined thresholds (both positive and negative thresholds). If a signal satisfies the thresh-
old, a low LE;_ (lSiSn) is sent to the latch. If the thresholds are not satisfied, the LE; will

remain high. Thus only interesting data will be latched into memory.

3.2.1.5 Memory Address Counting
The memory has a 16-bit address bus, so a l6-bit counter is necessary to receive the

clock pulses from the CSC and send the 16 hit count signal to memory for address count-

l9

ing.
The block diagram for this n-D data acquisition with m restrictions circuit is shown in

Figure 2.

20

tusec
.uu.

I‘— fMHz —>|

Figure 1 ' A t nsec clock with f MHz frequency forms the waveform SWC.
(n=4, l=round-off of log2n +1=3, $1.1...so=szslso=100=n)

21

 

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Figure 4 - The waveform SWC, with 3 pulses of 2 usec at a 0.003 MHz repetition

frequency.

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25

3.2.2 Flow Chart for System Operation

An overall flow chart for system operation is shown as follows:

 

input n dimensions
m restrictions
threshold value for m restrictions
crystal clock signal
sampling period
AID max. conversion time

I

I System Initialization

l

I Generate AID Sampling Signal

 

 

 

 

 

 

 

 

Binary code development
Signal latching

Comparison of input signal with a threshold
Memory address counting

I

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26

3.3 The Algorithm

Develop a new design methodology [49]~[53] to synthesize a n-dimension with m
restrictions data acquisition system which includes the previously defined CSC, CTB,
latch, comparator and counter16 for optimum power and size features.

The development of the overall data acquisition signals will precede as outlined
below. The design methodology follows the flow graph attached below to develop the

actual sampling frequency f', with minirnun error in the difference f- f'.

27

Flow graph for developing the actual sampling frequency f' with minirnun error in the

difference f- f'.

 

input 1’, f, n, tAID

i

q= round-up of log2(tA/D lt’)

t= t’ ~29

d15d14. ..d2d1do= round CH of l/tf
f=(1/t)°(1/(d15d14...d1d1.1d1-2...d1d0))
l= round-off of logzn +1

 

 

 

 

 

 

 

 

 

 

81.1. . .80=1‘1
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=0

 

 

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T
f'=(l/t)-(1/(d15d14...d, $1.1...So»

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28

3.4 Special Case (Clock Count Per Burst Less Than Data

Dimension)

When lItf <n where t, f, and n were previously defined, and t/ t’ = p =2q (with q an
integer and t’ as previously defined), we still need a q+l bit counter, counterl, which
receives an input clock period t’ from the crystal and generates the waveform SWC, see
Figure 6. For f'=1/tn, the actual frequency from the SWC is generated as follows:

From the Qq+1.1Qq+1.2...Qq sequence choose those which have a value of 1 when the
corresponding values of dq+,_1dq+1.2...dq has a 1, where dq+1.1dq+1.2...dq is the binary
code of ll, and connect these lines to a NAND gate. Again, we need to add an extra t’ to
the NAND gate input to avoid a transient spike. After 1If usec the output of the NAND
gate, T2, goes low, which sends a low reset, RSI, to counterl to reset Qq+,.1Qq+,.
2...Qqu-1 ...Q1Q0. The Qq-1 (t’x2q=t) is the SWC used in the CTB. From SWC and

LE_, we can get CNTC for counter16 addressing, see Figure 7 for this sequence.

3.5 Application (Design of a Smart Logic 3-D Data

Acquisition System with One Restriction)

According to the general design rules, with n=3, and m=1, we can achieve the design
of a smart logic circuit to replace an Operational u-P based system. The design will contain
the following five main blocks: CSC, CTB, LATCH, COMP, COUNTER. The design pro-
cedure follows the techniques outlined for the n-D data acquisition with m restrictions. The

five required blocks are as follows:

3.5.1 CSC Design

The counter and switch clock generator generates the desired signals for the CTB and
for the counter16. In our case, the input clock t’ from the crystal is 125 nsec. According to

the AID specification the maximum conversion time is 116 nsec (National Semiconductor

29

ADC0808). In the design considered here, n=3, f=0.003, so that l/tf=1I(ll6x0.003)
~2.87<3=n, which indicates that these conditions belong to the special case design consid-
ered in Section 3.4 above. If we choose t=128 nsec, then tIt’=128I0.125 =1024=21°, or
q=10, and with l=round-off of log23 +l=2, we need a 12-bit counter (q+l), counterl, which
can be the cascade of a first stage 4-bit counter, counterA, and a second stage 8-bit counter,
counterB. CounterA receives its input from the clock with period 125 nsec (from the crys-
tal) and generates an output Q3 of period 2 usec. CounterB receives the 2 usec clock signal
from Q3 of CounterA and generates the waveform SWC, see Figure 8. If we define f'=1I
tn=1/(128x3) ~0.002604 as the real frequency for the SWC, the waveform for SWC is gen-
erated as follows:

From the Q7Q6...Q1Qo sequence of counterB choose Q7Q6 (2 usec x (27+26)=384
usec= 128 usec x3) and connect these lines to a NAND gate along with an extra 125 nsec
clock pulse in order to avoid a transient spike. After 384 usec the output of the NAND gate,
T‘2, goes low, which sends a low reset, R81, to counterB to reset Q7Qg. . .QlQo. The Q5 (2
nsec x 26:128 usec) of counterB is the SWC used in the CPR. From SWC and LE_, we
can get CNTC for counter16 addressing, see Figure 8 for this sequence.

The simulation results of the CSC generator circuit for the special case n=3, m=1,
t’ =125 nsec, tM) =116 nsec, f=0.003 MHz are shown in Figure 9. Each of the monitoring
nodes can refer to the circuit diagram shown in Figure 8. The SWC and CNTC are expected
signals. CLK8MH ( t’) and LE_ are input signals. At first LE_=0, RS is set to low to clear
counterA and forces R81 to 0 which clears Q7Q6. . .Q1Q0 of counterB. Then RS is set to
high and forces R81 to 1, counterA and Q7Q6...Q1Qo of counterB counts step by step
according to the clock sequence of CLK8MH and the output of counterA, respectively. T2
is an important signal, which is initially high and after 384 pace (2 usec x (27+25)=384
nsec: 128 nsec x3) goes low and sets RSl=0 in order to reset Q7Q5 ...Q1Qo of counterB.
The Q5 (cycle time of one pulse=2 usec x 26:128 usec) of counterB is the SWC (contains
3 pulses of Q5) used in the CTB. From SWC and LE_, we can get CNTC for counterl6

30

addressing. Then T2 goes high and sets RSl=l to continue a new cycle of SWC.

3.5.2 CTB Design

The AID has 8 channels (National Semiconductor ADC0808) for multiplexing differ-
ent analog inputs. The clock-to-binary circuit accepts 3 pulses of 128 usec signals at
0.002604 MHz repetition frequency, see Figure 10, converts these to binary codes $130 and
sends these codes to the AID for choosing x, y, z axis analog inputs.

The simulation results of the CTB generator circuit for n=3 are shown in Figure 11.
Each of the monitoring nodes can be referred to the circuit diagram shown in Figure 5. The
81 and SO are CTB output control signals for choosing respectively the x, y, z axis analog
AID input signals. The SWC is an input signal representing a series of bursts from the CSC.
The system initialization is as follows: the K of the IK Flip F10p is always set high, the CLR
(clear) is set low in order to set 81 and 80 to 00, after which CLR is set high. The 81 and
80 change from 00, 01, 10 to correctly select the x, y, z axis analog inputs respectively and
return to 00 according to the clock count of the SWC. The cycle continues in order to
choose the desired signal. Each cycle needs three pulses from the SWC. Sl_ and 80_ are
the complements of SI and SO, respectively, and these four signals are used in the latch for

selecting digital signals from three different axes.

3.5.3 LATCH Design

The latch circuit accepts three signals from the AID at a 0.002604 MHz rate, and gen-
erates a LE_ (latch enable low true) signal which is sent to the CSC to control the CNTC.
For each 0.002604 MHz cycle, if one or more of the received signals are above the thresh-
old, the low enable latch will strobe the signals into memory. For signals below the thresh-
old, the LE_ will remain high and the latch will block these signals from memory.

The simulation results for the latch circuit for the special case n=3, m=1, t’ =125 nsec,

tA/D =1 16 nsec, f=0.003 MHz are shown in Figure 12. Each of the monitoring nodes are

31

shown in the circuit diagram of Figure 13. The 07,06, ...... ,00 and LE_ are output signals.
The former is sent to memory as input data and the latter is send to the CSC to control the
CNTC. The LE,-_ (i=x,y,z, referred to as 18 in the simulation), I7,I6,.....10 are input signals
representing the latch enable signal of a single axis and digitalized impact force, respec-
tively. The signals shown on Figure 12, namely, SWC, RSI, SI and SO are control sig-
nals. The input signal used to run a simulation is an impact force similar to that shown in
Figure 14. The output signals are delayed one time unit (384 its) and the first two data
values are replaced by a heading and time of occurrence for any significant impact pulse.
The output signals are updated only when SWC is high. 81 and 80 are used to choose the
input signals from the x, y, z axis, where Sl,SO=00 chooses the x axis, Sl,SO=01 chooses
the y axis, and Sl,S0=10 chooses the z axis. The 81,80 control signals continue to cycle
in order to select the desired signal from the data sequence.

In Appendix 1 and Figure 14, the first input data to the latch for the three axes is 84H,
84H, 84H, which is below the threshold. The relative output data which is delayed one
time unit is undefined, and in particular resulted in the sequence: 80H, 80H, 84H for our
simulation. The second input data is 84H, 84H, COH, which is above the threshold. The
relative output data, which is delayed one time unit, is 80H, 80H, 80H, which represents
heading. The third input data is EOH, EOH, EOH, which is also above the threshold. The
relative output data, which is delayed one time unit, is 00H, 00H, OCH, which represents
the real time clock count. The fourth input data is EOH, EOH, 84H, which is above the
threshold. The relative output data, which is delayed one time unit, is EOH, EOH, 84H, the
same as input data The fifth input data is 84H, 84H, 84H, which is below the threshold.
The relative output data, which is delayed one time unit, is arbitrary for example EOH,
84H, 84H in the simulation performed in this thesis.

32

tusec
4h-

J'IIUTJ‘U'UULI'U'LFLI'L
amal-

Figure 6 - A t nsec clock with f MHz frequency forms the waveform SW C.
(for the special case and n=4)

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 7 - The schematic circuit diagram for the CSC (counter & switch clock) generator

for the special case n=3.

34

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 8 - The detailed circuit diagram for the CSC (counter & switch clock) generator

for the special case n=3.

35

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102400 204800 307200
Figure 9.b - The simulation results of the CSC (counter & switch clock) generator circuit

for the special case n=3, continued.

37

128usec
+| l.—

IU‘LI'LI'LHILI'IIU’LFLFL
—>| |<—

0.002604 MHz
Figure 10 - The waveform SWC, with 3 pulses of 128 nsec at a 0.002604 MHz repetition

frequency for the specific smart logic case.

38

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 11 - The simulation results of the CTB (clock-to-binary) generator circuit for n=3

39

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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204800 409500 614400 819200

Figure 12.a - The simulation results for the latch circuit for the special case n=3, m=1,

(=125 nsec, tA/D =116 usec, f=0.003 MHz.

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Figure l2.b - The simulation results for the latch circuit for the special case n=3, m=1,

t’ =125 nsec, tA/D =116 11sec, f=0.003 MHz, continue.

41

 

  

 

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427 . . 1 1 . 1 . 1 . . 1 1 . . 1 1
1433600 1638400 1843200 2048000 2252800

Figure 12.c - The simulation results for the latch circuit for the special case n=3, m=1,

t’=125 nsec, ‘A/D =116 nsec, f=0.003 MHz, continue.

42

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43

(EOH, EOH, EOH)

 
   
 
 

(EOH, EOH, 84H)

(84H, 84H, COH)

(841-1, 841-1, 84H) (84H, 84H, 84H)

Figure 14 - One impact force which contains five sampled data.

3.5.4 COMP Design

The 8-bit comparator circuit compares the output signal from the AID with prepro-
grammed thresholds (8AH and 76H, for +10 g and - 10 g, respectively) and generates a latch
enable signal, LE,-_ (latch enable LE,- low true, i=x,y,z). If the signal magnitude is above
the threshold, LE;_ will go low, otherwise, LE; will remain high.

The simulation results of the comparator circuit are shown in Figure 15. Each of the
monitoring nodes can be referred to the circuit diagram shown in Figure 16. The input sig-
nals are placed on the lines A7,A6, ....,A0 (data lines) and the output signal appears as LE;_.
The first set of input data is the sequence 00H, 10H, 20H, 30H, 40H, 50H, 60H, 70H which
is above the threshold, so that LE;_ goes low. The second set of input data is chosen as
90H, AOH, BOH, COH, DOH, EOH, FOH, FFH which again is above the threshold so that
LE,-_ again goes low. Finally the set of input data 76H, 78H, 7AH, 7CH, 7EH, 7FH, 80H,
81H, 82H, 84H, 86H, 88H, 8AH is applied which is below or at the threshold so that LE;_
goes high.

3.5.5 COUNTER Design

The 16-bit counter circuit receives the clock signal from the CSC and sends a l6-bit
word to memory for address pointing. The simulation results for the counterl6 circuit are
shown in Figure 17. Each of the monitoring nodes can be referred to the circuit diagram
shown in Figure 18. The output signals appear on the Q15Q14...Q1Qo lines. The input sig-
nal is CP (CNTC). We divide the counterl6 into four parts to simulate the individual cir-
cuits since simulating the whole counterl6 requires 65536 clock counts which would
expend to much time and paper. For each individual part the 16 clock counts are sufficient
to verify counter simulation performance. Initially, RS=0 in order to clear Q15Q14...Q1Q0.
When RS=1, Q15Ql4. . .QlQo will count each pulse from the clock which generates the sig-
nal CP (CNTC). This process is repeated for the other 3 four bit parts of the counter.

The block diagram for this SLIC is shown in Figure 19.

45

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Figure 16 - The detailed circuit diagram for an 8-bit comparator with predetermined

thresholds.

47

 

 

 

 

 

 

 

0.0 2ND 400.0 600.0 800.0 1000.0 1200.0 1400.0 [m0 18111.0 2000.0
Time (nsec)

 

 

 

 

 

 

 

 

0.0 200.0 400.0 6m.0 0WD 1WD 1200.0 [4010 1603.0 1300.0 2WD

Tune (nsec)

Figure l7.a - The simulation results for a 16-bit counter which is divided into four parts.

48

 

 

 

 

 

 

 

 

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51

3.6 Software Program

A software program based on the flow graph shown in Section 3.3 has been developed
for synthesizing the n—D with m restrictions data acquisition system according to the
design methodology developed in Section 3.2. The flow chart for the software to accom-
plish this objective is shown in Section 3.3. This program develops the actual sampling
frequency f', with minirnun error in the difference f- f'. The detailed software listing is

included in Table l.

52

#include <math.h>

#include <stdio.h>

mainO

{ /* The program for synthesizing the n-dimension with m restrictions data acquisition
system */

float tl,t,f,tad,ql,fl.f2;

int n,q,d,l,s,dl;
printf("enter the t1 value with nsec:");/*interna1 clock period generated from the crystal*/
t1=getnum()/1000.;

printf(”enter the f value with Hz:"); 1* sampling frequency *1

f=getnum0/ 1000000.;

printf("enter the tad value with usecz"); I* AID maximum conversion time */
tad=getnum();

printf("enter the n value:"); I“ data dimension */

n=getnum0;

ql=log10(tadlt1)/log10(2.0); /* q=round-up of log2(tad/tl) */

if (ql-(int) q1=0)

q=ql:

else q=++ql;

t=tl*pow(2.0,(float) q); l“ usec duration of the clock pulses in the burst */

if ((1/(t*f))-(int)(ll(t"'t))<0.5) I“ d=round off of lItf */

d= l/(t*f);

else d=l+ll(t*f);

f l=( llt)*(ll(float) d);

l=log10((float) n)/log10(2.0)+l; /* l=round-off of log2(n) +1 *I

dl=d&((int) pow(2.0,(float) I) -l); /* d1 = the least I bit of d *I

if (ll(t*f)<n /* special case: clock count per burst less than data dimension */

f2=( l/(t*n)); /* 12 represents actual frequency of the SWC waveform *l
else if (dl==n)
t2=(llt)*(ll(float) d); 1* f1=f2 *l
else if (dl>n) l* minimize f1-f2 */

=(llt)*(l/(float) (d-dl+n));
else if ((n-dl)<=(int) pow(2.0, (float) l-l.0))
f2=( llt)*( l/(float) (d-dl+n));
else f2=( l/t)"‘(1/(float) (d-dl+n-(int) pow(2.0, (float) l)));
printf(" =%d t=%f d=%d f1=%f l=%d dl=%d f2=%f", q,t,d,fl,l,dl.f2);
}
getnumO
{
char s[80];
868(8);
return(atoi(s));
}
Table l - Software program for synthesizing the n-D with rn restrictions data acquisition
system.

CHAPTER 4

Variation in Size, Power and Heat Dissi-
pation with Specification Requirements

It is important to estimate the size, power and heat dissipation of the u-P based IS, of
the composite smart logic chip based IS and of the absolute limit for an optimum design in
order to compare the improvement for each step of the smart logic implementation. A
general analysis of power versus size for multich housing configurations and high den-

sity VLSI will aid in the design of compact data acquisition devices.

4.1 Estimation of Size, Power and Heat Dissipation for a
u-P Based IS

The size, power and heat dissipation of the u—P based 18 are analyzed in order to com-

pare the power and size saving achievable with a composite smart logic chip based 18.

4.1.1 Estimation of Power Dissipation in a 89 mm (3.5 in.) u-P

Based IS
A 89 mm (3.5 in.) 18 previously reported by Zapp. et al. (1990) has a 13.804 mA total
current consumption from a 7.2 V battery which includes 9 mA for the u-P (the power

consumption data of some typical single chip u—P are listed in Table 2 for reference), 1.2

53

54

mA for the 32 K RAM, 0.004 mA for the latch and multiplexer, 0.6 mA for the Op Amp,
and 3 mA for the regulator biased at 7 .2 V. Thus the total power consumption is
P=IV=13.804 mA x 7.2 V = 99.39 mW. The current and power consumption for the con-
ventional u—P circuit in the 89 mm (3.5 in.) IS are shown in Table 3.

According to the data sheets for the MC68HC11A8 u-P (Motorola Semiconductor
Products, Inc.), the average chip-junction temperature, T}, in °C can be obtained from:

TJ=TA+(PD X 91A) (4.1)

where TA: Ambient Temperature, °C

em = Junction-to-Ambient Package Thermal Resistance, °CIW
Pa = PM + Puo
PM = Chip internal power Icc x Vcc, W
Pm = Power dissipation on input and output pins
For most applications Pug < < PM and can be neglected.

For the 89 mm (3.5 in.) IS, the estimated u-P current consumption based on total sys-
tem current requirements gives Icc=9 mA, at Vcc=5 V, so that PD: Icc x Vcc= 9 mA x 5
V = 45 mW if Pm is neglected. Thus TJ'TA= 45 mW x 50 °CIW (The u-P
MC68HC1 1A8, Plastic 52-pin Quad Pack, Thermal Resistance is given as OJA=50 °CIW)

= 2.25 °C. Such a small temperature increase is allowable in the 89 mm (3.5 in.) IS.

4.1.2 Estimation of Power Dissipation in a 63.5 mm (2.5 in.) u-P

Based IS
A 63.5 mm (2.5 in.) IS previously reported by Techrnark, 1991, has a 10.244 mA total
current consumption which includes 9 mA for the u-P, 1.2 mA for the 32 K RAM, 0.004
mA for the latch and multiplexer and 0.04 mA for the Op Amp at Vcc=5 V. This gives a
total power consumption of P=IV=10.244 mA x 5 V = 51.22 mW.
For the 63.5 mm (2.5 in.) IS, using Eq. 4.1, and the estimated u-P current consumption

(based on total system current requirements) of Icc=9 mA, at Vcc=5 V, gives PD: Icc x

55

Vcc= 9 mA x 5 V = 45 mW if Pm is neglected. This results in TJ'TA= 45 mW x 50 °Cl
W = 2.25 °C. This temperature increase is allowable in the 63.5 mm (2.5 in.) IS.

4.1.3 Estimation of Power Dissipation in a 50.8 mm (2.0 in.) u-P

Based IS Multichip Housing

A 50.8 mm (2.0 in.)‘multichip housing IS, has a 10.804 mA total current consumption
which include 9 mA for the u-P, 1.2 mA for the 32 K RAM, 0.004 mA for the latch and
multiplexer and 0.6 mA for the Op Amp at Vcc=5 V, giving a total power consumption of
P=IV=10.804mA x 5 V = 54.02 mW.

For the 50.8 mm (2.0 in.) 18, using Eq. 4.1, and a u-P current consumption of Icc=9
mA, at Vcc=5 V, gives PD: Icc x Vcc= 9 mA 1: 5 V = 45 mW if Pyo is neglected. Thus
TrTA= 45 mW x 50 °CIW = 2.25 °C which is allowable in the 50.8 mm (2.0 in.) IS.

Comparing section 4.1.1, 4.1.2 and 4.1.3 for the three different sizes of u-P based IS,
the TrTA (the temperature difference between chip-junction and ambient) is the same

because we use the same u—P and the u-P dominates the power consumption.

4.2 Estimation of Size, Power and Heat Dissipation for a

Composite Smart Logic Chip Based IS

The SLIC, AID, Op Amp and RAM dice are housed together on a single substrate
without circuit board and connected to form what we call the composite smart logic chip.
Figure 20 depicts the smart logic substrate layout, showing the 4 subsets, RAM, Op Amp,
SLIC and AID. The dimensions of the single housing unit are 20 x 20 mm (0.787 x 0.787
in.). The composite smart logic chip will save power compared to the previous 89 mm
(3.5 in.) IS since SLIC replaces the u—P which dominates the total power consumption. It
is necessary to estimate the size and power for a composite smart logic chip based 18 to

verify the specification requirements of smaller size and lower power consumption than

56

for the previous 89 mm (3.5 in.) IS.

4.2.1 Estimation of the Size

Three different configurations for the smart logic chip based 18 are considered:

For a one substrate composite smart logic chip configuration, the volume of the sub-
strate is 20 mm x 20 mm x 5 mm (0.787 in. x 0.787 in. x 0.197 in.), the volume of the tri-
axial piezoelectric accelerometer (Vibrametrics model 3130HT) is 7 mm x 7 mm x 15.2
mm ( 0.275 in. x 0.275 in. x 0.6 in.), and the volume of the smallest battery (Panasonic
model P22330) of which 3 are needed has a 23.2 mm diameter and a 3.0 mm height (0.91
in. diameter, 0.12 in. height). Using Autocad an optimal volume configuration has been
developed as shown in Figure 21. The components are contained in a spherical volume
which has a sphere diameter of 30 mm (1.18 in.). If a utilization rate (minimum element
volume divided by minimum sphere space) of 46.33% is assumed and the remainder of the
sphere is filled with heat sink, rigid foam, beeswax, and epoxy walls of 3.81 mm (0.15 in.)
thickness, the IS diameter becomes 37.62 mm (1.48 in.). The disadvantage of this config-
uration is that the accelerometer is not located in the center of the sphere.

For two half-substrate configurations, the volume of each substrate is 20 mm x 10 mm x
5 mm (0.787 in. x 0.394 in. x 0. 197 in.). Using the same accelerometer and battery as pre-
viously, the Autocad software provides two possible configurations. The sphere diameter
for one is 31.62 mm (1.25 in.) which for a utilization rate of 39.57% gives an IS diameter
of 39.24 mm (1.55 in.) as shown in Figure 22. The advantage of this configuration is that
the accelerometer is located near the center of the sphere.

The sphere diameter for the third configuration is 30.24 mm (1.19 in.) which using a uti-
lization rate of 45.24% gives an 18 diameter of 37.86 mm (1.49 in) as shown in Figure 23.
The advantage of this configuration is that the accelerometer is located in the sphere cen-
ter. The disadvantage is that the separating distance between the two half-substrates is

larger than that of the previous configuration, so that longer wire connections are neces-

57

sary.
The detailed 18 dimensions for the three different configurations are shown in Table 4.

4.2.2 Estimation of the Power and Heat Dissipation
Replacement of the u-P with a composite smart logic chip results in a substantial
power reduction. The expected power reduction can be calculated using the known power
consumption of individual gates comprising the composite smart logic chip. Specifically,
the gate count for the SLIC is approximately 1500 gates. According to the National Semi-
conductor CMOS Logic Databook, Application Note 303, Kenneth Karakotsios [54], the
CMOS Logic Databook [55], the Texas Instruments CMOS Logic Databook [56], and the
Samsung CMOS Logic Databook [57], as summarized in Table 5, the average HCMOS
current consumption for one gate is 0.5 uA at TA=25 °C, at a bias voltage of Vcc= 6 V.
Thus the current consumption of the smart logic circuit is less than 1 mA at Vcc= 5 V.
The current consumption of the 32 K RAM (IDT 71256, Integrated Device Technology,
Inc., Santa Clara, CA) is approximately 1.2 mA at Vcc= 5 V. The current consumption of
the AID (ADC 0808IADC 0809, National Semiconductor) is approximately 3 mA at Vcc=
5 V. The current consumption of the Op Amp (TLC 271.4, Texas Instruments Inc., Dallas,
TX) is approximately 0.04 mA at Vcc= 5 V (A recent modification incorporated in the IS
by Techmark Inc. of Lansing uses this type of Op Amp to provide a reduced current con-
sumption of 0.04 mA and achieve a smaller size for the IS of 63.5 mm (2.5 in.) diameter),
so that the total current consumption of the composite smart logic device during operation
is about 5.24 mA at Vcc= 5 V. This is less than half the current consumption of the con-
ventional u-P based circuit. The better than 2.0 reduction in power consumption allows
the use of smaller volume batteries to achieve the same results as for the existing larger 18.
The current and power consumption for the composite smart logic IS chip are shown in
Table 3. .
According to R. C. Eden [58], the maximum temperature rise, Tm, above the heat sink

S8

temperature is given by:

Tm'To=(P/2nkz)[lfl(Ro/Ri)+1/2] (4.2)

where k is the substrate thermal conductivity, z its thickness, T0 is the heat sink tem-
perature, P is the power which is unifome distributed over the chip area, and R, is the
radius of a chip centered on a substrate of radius R0.

For the composite smart logic chip (38 mm or 1.5 in. IS), with a silicon substrate of
thickness z=0.5 mm, thermal conductivity of k = 149 WIm°C [58], substrate of diameter
2R0=28.4 mm (1.12 in.) (actual chip is 19 x 19 mm (0.75 x 0.75 in.) square) and four dice
distributed in a diameter of 2Ri=l4.2 mm (0.56 in.) gives a power consumption of P: 5.24
mA x 5 V =26.2 mW. Using Eq. 4.2,

Tm-To=[26.2 mW/(21r x 149 WIm°C x 0.5 mm)]x[ln(28.4 mm/ 14.2 mm)+ 1I2]=0.067 °C
which is smaller than the temperature increase for the 89 mm (3.5 in.) IS. Thus power dis-

sipation represents no problem for size reduction related to multich housing.

4.3 Ultimate Size, Power and Heat Sink Limitations

Assuming the availability of smaller accelerometers and batteries, three different size
limitations are considered:

For a one full-substrate configuration, using a smaller battery with dimensions of
16.64 mm diameter and 3.0 mm height (0.655 in. diameter, 0.12 in. height), or approxi-
mately 51% of the original battery, we can get the lowest bound on the sphere diameter of
28.72 mm (1.13 in.) as shown in Figure 24. With the addition of rigid foam, beeswax, and
epoxy shell, the 18 diameter becomes 36.34 mm (1.43 in.).

For a two half-substrate configuration, using a battery with dimensions of 13.4 mm
diameter and 2.5 mm height (0.528 in. diameter, 0.1 in. height), or 18 % the volume of the
original battery and a smaller accelerometer of dimensions 5 mm x 5mm x 12.43 mm
(0.197 in. x 0.197 in. x 0.49 in.), we get the lowest bound on the sphere diameter of 24.58
mm (0.97 in.) as shown in Figure 25. Adding the rigid foam, beeswax, and epoxy shell

59

increases the IS diameter to 33.1 mm (1.27 in.). For this configuration, the accelerometer
would not be located exactly in the sphere center. To locate the accelerometer in the
sphere center requires two substrates and longer wire connections thus increasing the
dimensions slightly to 28.28 mm (1.12 in.) for the basic unit as shown in Figure 26 and to
35.9 mm (1.42 in.) for the rigid foam, beeswax and epoxy shell encased unit. For the min-
imum size in this latter configuration, the battery dimensions were chosen to be 19.66 mm
diameter and 2.5 mm height (0.744 in. diameter, 0.1 in. height).

The detailed limited IS dimensions for the three different configurations are shown in
Table 6.

To achieve an even smaller size IS (< 33 mm or 1.3 in.), only the size of the acceler-
ometer and batteries must decrease. The power consumption and substrate size will
remain the same as for the 38 mm (1.5 in.) smart logic based IS. The temperature increase
is thus the same as for the 38 mm (1.5 in.) IS if the same silicon substrate be used. This
certainly will cause no thermal concern. However, if it is desirable to prevent even such a
small temperature increase, a high thermal conductivity substrate could be chosen. Dia-
mond’s physical attributes make it a very good substrate material choice [58]~[61]. Dia-
mond provides a combination of good heat conduction and excellent electrical insulation
with a low dielectric constant. For example, the thermal conductivity of CVD diamond =
1000 ~ 1300 WIm°C (Lateral, in-plane), 1250-1600 WIm°C (Normal, Top-bottom) for
ET-lOO quoted by Norton Company; and > 1300 WIm°C (Lateral), > 1600 WIm°C (Nor-
mal) for FIT-200 again from Norton Company. These values are 2 to 4 times superior to
that of copper. Of course, the structural strength of diamond is also highly desirable in
impact measuring devices such as the IS.

The freestanding ”white" diamond wafer, the purest form of diamond manufactured by
the chemical vapor deposition (CVD) process, is now available from Norton Company’s
diamond film division with dimensions of 100 mm (4 in.) diameter and 1 mm (0.04 in.)

thickness. This achievement represents an important breakthrough in the commercializa-

60

tion of diamond produced by the CVD process, which can be utilized directly in the IS. If
a diamond substrate replaces the silicon substrate in the minimum sized 18, according to
Eq. 4—2, with k=1000 WIm°C, and the other parameters the same as in Section 4-2, the 38
mm (1.5 in.) smart logic based 18 gives a temperature rise of :

Tm-To=[26.2 mW/(21t x 1000 WIm°C x 0.5 mm)]x[ln(28.4 mm! 14.2 mm)+ll2]=0.01 °C
which is one sixth the temperature increase of the silicon substrate. This small tempera-
ture increase is clearly acceptable for the minimum sized IS.

Many IC now operate from 3 V power supplies [62],[63]. Embedded controller, mem-
ories, and a variety of logic chips are widely available in this form. Choice of the low
voltage ICs will allow the battery requirements to decrease (the three cells may be reduced
to two cells) and the battery to last longer between recharges. Other benefits include

smaller size and lower heat dissipation than for 5 V systems.

4.4 Variation of Power and Size vs Specification Change

The estimation of power and size has been accomplished in section 4.2 for the speci-
fied parameter values for the IS, namely, t’=0. 125 11sec, tAID=116 nsec, f=0.003 MHz and
n=3. If the same size and power algorithm is applied to other systems, the parameter val-
ues may be different, but the variation in power and size will be small. The gate count for
the smart logic circuit dominates the power and size constraint if the remaining circuit ele-
ments are maintained. An analysis of the variation of gate count vs specification change is
provided. A gate count corresponds to 2.5 11W in power and approximately 0.003 mm2 '
(4.65 x 10*5 in.2) in area.

Assuming fixed values for t’, f, and n as specified above and allowing for a variation in
1ND of 2 11sec, 4 nsec, 8 nsec, 16 nsec, 32 nsec, 64 nsec and 116 psec, we obtain different
lItf and f' which produce the gate count variation shown in Table 7.a and Figures 27 8t
28. From this table, the gate count variation vs different specifications relative to the HUD

=116 nsec is one gate count, or 2.5 11W in power change (referred to Table 8) and no

61

change in area (referred to Appendix 2 & 3).

In similar fashion, if we alter f from 0.003 MHz to 0.0025 MHz keeping the remaind—
ing variables fixed and following the same procedure as above, the result are as shown in
Table 7 .b and Figures 27 & 28. From this table, the gate count variation vs different spec-
ifications relative to tND=l 16 nsec is at most one gate count, or 2.5 11W in power

(referred to Table 8) and no change in area (referred to Appendix.2 & 3).

62

Manufacturer Model No. Max supply current ROM RAM EEPROM

Motorola MC68HC11A8 20 mA 8 K bytes 256 bytes 512 bytes
Intel 8050AH 80 mA 4 K bytes 256 bytes

8049AH 70 mA 2 K bytes 128 bytes

8048AH 65 mA 1 K bytes 64 bytes

8052AH 175 mA 8 K bytes 256 bytes

8051AH 125 mA 4 K bytes 128 bytes

Table 2 - Maximun u-P current consumption for different models from two

manufacturers.

63

conventional u-P circuit composite smart logic chip
(89 mm or 3.5 in. IS) (38 mm or 1.5 in. IS)

u-P 9.0 mA

Memory (32 K) 1.2 mA 1.2mA
MUX 0.002 mA

Latch 0.002 mA

Op Amp 0.6 mA 0.04 mA
Regulator 3.0 mA

Smart Logic Circuit 1.0 mA
ND 3.0 mA
Total current consumption 13.804 mA 5.24 mA
Total power consumption 99.39 mW 26.2 mW

Table 3 - Current and power consumption for the conventional u-P circuit (89 mm or 3.5

in. IS) and the composite smart logic chip.

 

sut

mix

ele:

COI

uti

substrate type one full-substrate
minimum diameter 30.00 mm
(1.18 in.)
element volume 6.55 cm3
(0.4 111.3)

complete sphere space 14.14 cm3
(0.86 in.3)

utilization rate 46.33%

two half-substrates

31.62 mm
(1.25 in.)
6.55 cm3
(0.4 in.3)
16.55 cm3
(1.01 in.3)

39.57%

two half-substrates

. 30.24 mm

(1.19 in.)
6.55 cm3
(0.4 in.3)
14.48 cm3
(0.88 111.3)

45.24%

Table 4 - IS dimensions for different geometrical configurations.

65

Manufacturer Gate Type T A Icc Vcc
National Semiconductor Quad Gates 25 °C 2.0 11A 6 V
Quad Nand Gate 25 °C 2.0 11A 6 V
Quad Nor Gate 25 °C 2.0 11A 6 V
Texas Instruments Quad Nand Gate 25 °C 2.0 11A 6 V
Quad Nor Gate 25 °C 2.0 11A 6 V
Samsung Quad Nand Gate 25 °C 2.0 11A 5 V

Quad Nor Gate 25 °C 2.0 11A 5 V

Table 5 - CMOS current consumption values for various quad gates at TA=25 °C for

different manufacturers.

66

substrate type one full-substrate two half-substrates two half-substrates
minimum diameter 28.72 mm 24.58 mm 28.28 mm

(1.13 in.) (0.97 in.) (1.12 in.)
element volume 4.70 cm3 3.02 cm3 4.20 cm3

(0.29 in.3) (0.18 in.3) (0.26 in.3)
complete sphere space 12.40 cm3 7.78 cm3 11.84 cm3

(0.76 111.3) (0.47 in.3) (0.72 111.3)
utilization rate 37.91% 38.78% 35.50%

Table 6 - Minimum IS dimensions for different geometrical configurations.

t ND t’ f

nsec nsec MHz
2 0.125 0.003
4 0.125 0.003
8 0.125 0.003
16 0.125 0.003
32 0.125 0.003
64 0.125 0.003
116 0.125 0.003

Table 7 .a - Gate count variation vs different specifications relative to tM) =116 usec and

lItf

167
83
42
21

10

67

decimal binary

10100111
01010011
00101010
00010101
00001010
00000101

00000011

lltf'

binary

10100111
01010011
00101011
00010111
00001011
00000111

00000011

f' gate count variation

MHz

0.002994
0.003012
0.002907
0.0027 17
0.002841
0.002232

0.002604

maintaining t’ =0. 125 11sec, f=0.003 MHz, and n=3 conditions.

tAID

t!

f

usecusecMHz

2

4

8

16

32

64

116

Table 7.b - Gate count variation vs different specifications relative to tM) =116 nsec

0.125
0.125
0.125
0.125
0.125
0.125

0.125

0.0025
0.0025
0.0025
0.0025
0.0025
0.0025

0.0025

lItf

68

decimal binary

200

100

50

25

13

11001000
01100100
00110010
00011001
00001101
00000110
00000011

l/tf'

binary

11000111
01100011
00110011
00011011
00001111
00000111

00000011

1' gate count variation

MHz
0.0025 13
0.002525
0.002451
0.002315
0.002083
0.002232

0.002604

keeping t’ =0.125 nsec, f=0.0025 MHz, and n=3 fixed.

1ND t’ f
nsec nsec MHz
2 0.125 0.003
4 0.125 0.003
8 0.125 0.003
16 0.125 0.003
32 0.125 0.003
64 0.125 0.003
116 0.125 0.003
2 0.125 0.0025
4 ' 0.125 0.0025
8 0.125 0.0025
16 0.125 0.0025
32 0.125 0.0025
64 0.125 0.0025
116 0.125 0.0025

Table 8 - Power variation vs different specifications relative to t AID =1l6 nsec

69

lItf

decimal binary

167
83
42
21

10

200
100
50
25

13

10100111
01010011
00101010
00010101
00001010
00000101
00000011
11001000
01100100
00110010
00011001
00001101
00000110
00000011

l/tf'

- binary

10100111
01010011
00101011
00010111
00001011
00000111
00000011
11000111
01100011
00110011
00011011
00001111
00000111

00000011

f'
MHz
0.002994
0.003012
0.002907
0.0027 17
0.002841
0.002232
0.002604
0.0025 13
0.002525
0.00245 1
0.0023 15
0.002083
0.002232

0.002604

maintaining t’=0.125 nsec, f=0.003 MHz, and n=3 fixed.

power variation

ILA 11W
0.5 2.5
0.5 2.5
0.5 2.5
0.5 2.5
0.5 2.5
0.5 2.5
O 0
0.5 2.5
0.5 2.5
0.5 2.5
0.5 2.5
0.5 2.5
0.5 2.5
0 0

70

 

5432128

 

7654321
menu
(OP/WP)

191011121314

 

 

 

 

 

 

1 65432132725324?! 2!

109I765431|

SMART
mic

NTEG
CIRCUIT
(SLIC)

 

 

 

 

 

Figure 20 - Patterned silicon substrate to support the SLIC, RAM, AID and Op Amp dice

in order to form the composite smart logic chip.

71

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

\\ M... //
\i\ ‘\ ‘1 / / /é/
\ \ \ ““"°’°'“°“°‘ / /. //

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 21 - The front view of the typical configuration for the sphere of 30 mm (1.18 in.)

diameter. Not included: rigid foam, beeswax, and epoxy.

72

Substrate

Accelerometer

 

Figure 22 - The side view of the typical configuration for the sphere of 31.62 mm (1.25

in.) diameter. Not included: rigid foam, beeswax, and epoxy.

73

Substrate Substrate

Accelerometer

 

Figure 23 - The front view of the typical configuration for the sphere of 30.24 mm (1.19

in.) diameter. Not included: rigid foam, beeswax, and epoxy.

74

Substrate

Accelerometer

 

Figure 24 - The front view of the typical configuration for the sphere of 28.72mm (1.13

in.) diameter. Not included: rigid foam, beeswax, and epoxy.

75

      
    
 

Substrate

Substrate

Accelerometer

Figure 25 - The front view of the typical configuration for the sphere of 24.58 mm (0.97

in.) diameter. Not included: rigid foam, beeswax, and epoxy.

76

Substrate Accelerometer Substrate

1

Batteries

 

Figure 26 - The front view of the typical configuration for the sphere of 28.28 mm (1.12

in.) diameter. Not included: rigid foam, beeswax, and epoxy.

1" (MHz)

77

 

 

 

 

-3
3,2“0 . . .5.... . . - .....
0 represents n=3, f=0.003
3 - o 0 . represents n=3, f=0.0025-
O
O
2.8 - -
O
2.6 - e -
2.4 — -
O
2.2 - -
2 4 L a41 1 a
10° 10‘ 102 10
1M, (usec)

Figure 27 - 1' vs different specifications as given in Table 7.a.

Gate count variation

78

 

 

 

 

1 e -4...e., e. 3553..., 4 . 55....
0 represents n=3, f=0.003

0.8 - . represents n=3, f=0.0025-
O.6 » 1
0.4 b -
0.2 - -

0 1 1 1 1 1 1 1 1 1 1 ' 1 1 1 1 14 Ag

10° 101 102 10

We (usec)

Figure 28 - Gate count variation vs different specifications as given in Table 7.b.

CHAPTER 5

Simulation Results

The development of a smaller IS design takes into consideration the experiences gained
from the previous designs, specifically with respect the parameters of acceleration thresh-
old, signal bandwidth and digital sampling rates. It has become clear that the units must be
designed for specific applications in order to avoid dominance of data outside the realm of
interest. For example, in transportation studies, the damaging vibrations and impacts occur
at lower frequencies (less than 100 Hz, typically 5 to 25 Hz) than for packing line studies
(more than 100 Hz). Thus, units designed to accept data to 4 kHz are saturated with useless
data. For transportation studies, a 100 Hz or less low pass filter is mandatory, and a lower
sampling rate consistent with this filter is required. Also, since the impacts experienced in
transportation have lower peak acceleration levels, the sensitivity of the accelerometer
must be increased and can be achieved by eliminating the shunt capacitor across each accel-
erometer. Based on the above conflicting constraints, no single electronics design will ful-
fill all application objectives. Thus, multiple electronics designs will be implemented to
tailor the IS to the particular desired application. Each smart logic design will maintain
fixed data acceptance thresholds and sampling rates. This is a major change from the u-P
based system where thresholds and sampling rates could be changed in software. The per-
formance of new application designs can be studied using simulation techniques developed

to investigate the properties and operation of the smart logic chip. Thus the simulation pro-

79

80

vides a powerful tool by which to evaluate the performance of new IS designs.

5.1 Architecture for IS Smart Logic Chip

It is desirable to view the operation of the entire smart logic device based on a realistic
simulation. The overall system architecture for the smart logic composite chip is display
in Figure19. The simulation is chosen to examine all facets of the operating system. Thus
the data generated is extensive, so that only a small fraction can be shown and discussed.
The detailed block diagram for the n-D data acquisition system with m restrictions is
shown in Figure 2. The detailed circuit diagram for the data acquisition system with n=3,
m=1 is shown in Figure 29.a. The detailed circuit diagram for the special case of 3-D and
one restriction smart logic design is shown in Figure 29.b. It is this configuration for
which extensive simulations have been carried out. The detailed architectural subsets for

the components included in the simulation are shown in Figures 5, 8, 13, 16, and 18.

5.2 Simulation Results

We have used the VTI tools [64]~[69] for the circuit diagram layouts presented in this
thesis. Some standard cells are normally stored in the VTI library, and we have used these
to build larger and more complicated circuits, which are then connected together as shown
in Figures 3, 5, 8, 13, 16, 18, 29.a and 29.b. After all the circuits were connected a simu—
lation was developed, initially for the individual circuits and then for the global circuit in
order to verify that both the system and subsystem performance is as expected.

For the simulation of the CSC generator circuit for n=3, m=1, t’ =125 nsec, t=2 nsec,
and f=0.003 MHz, each of the monitoring nodes are referenced in Figure 3. The SWC and
CNTC are the output signals. The former is sent to the CTB as an input signal to generate
SO, 81 and the latter is sent to COUNTER16 as an input signal to generate the address bus
A15 to A0. The CLK8MH (t’) and LE_ are input signals representing the clock from the
crystal and latch enable signal, respectively. At first LE_=0, CLR (clear) is set to low in

 

81

order to clear counterl and R8 is set to low in order to force RSl=0 which clears
Q15Q14...Q1Qo of counter2. Then CLR is set high and RS is set high which forces
RSl=1, so that counterl and Q15Q14 . . .QlQo of counter2 count pulses from CLK8MH (t’)
and CLK500KH (t), respectively. T1 and T2 are signals obtained from the output of the
AND gate and NAND gate, respectively and are important because they control the timing
of the swc. At first T1 is low and '12 is high, but after 328 11sec (2 11sec x (27+25+22)),
Tl will go high to enable the SWC. After another 6 nsec (or 334 11sec from the origin
given by 2 11sec x (27+25+22+21+2°)), 12 will go low and force RS1=0 which will reset
all outputs Q15Q14...Q1Q0 of counter2, and force T1 low resulting in a total high time of
6 11sec. Using T1 and CLK500KH, we can generate SWC to be used in the CTB. From
SWC and LE_, we can get CNTC for counter addressing. The simulation results are
shown in Figure 30.

For the simulation of the data acquisition system with n=3, m=1, t’ =125 nsec, t=2
11sec, and f=0.003 MHz, each of the monitoring nodes are referenced in Figure 29.a. The
O7,06,....,OO and A15,Al4,...,A0 are the response signals. The former is sent to memory
as input data and the latter is sent to memory as an input signal (address). The I7,I6,...,IO
and CLK8MH are input signals representing digitalized impact force and clock signal
from the crystal, respectively. The important signals are SO, 81, LE_, RSI, SWC and
CNTC because SO and SI choose the input signals from the x, y, z axis, LE_ controls
CNTC, RS1 controls the SWC cycle, SWC generates SO and 81, and CNTC generates
address bus A15 to A0. The output signals are active only when SWC is high. 81 and SO
choose the input signals from the x, y, z axis according to the following assignments:
Sl,SO=00 chooses the x axis, Sl,SO=01 chooses the y axis, and Sl,SO=10 chooses the z
axis. They continuously cycle to select the desired axial signal. Starting with I7=I6=1,
15=I4= ...=10=0 or COH which is an input signal above the threshold of 8AH, the output,
delayed one time unit, gives O7=O6=1, 05=O4=....=OO=0 or COH and the address lines

A15,A14,...,A0 give a count of 3 to store the 8-bit x, y and z axis data into sequential

82

memory. If 16 changes to 0 while the other data values stay fixed, the input signal takes a
value of 80H which is be10w the threshold of 8AH so the output, delayed by one time unit
(384 11sec), keeps the previous value of COH and A15,Al4, ...,AO also keep their previous
values (no data is written into memory). The simulation results for this operation are
shown in Figure 31.

In Figure 9, the simulation results for the CSC generator circuit, for the special case
n=3, m=1, t’ =125 nsec, tA/D =1 16 nsec, and f=0.003 MHz, are shown. The detailed
description of the operation is contained in Section 3.5.1. Figure 11 provides the simula-
tion results of the CTB generator circuit for which the operation is outlined in Section
3.5.2. Figure 12 shows the simulation results for the latch circuit which is described in
Section 3.5.3. Figure 15 provides the simulation results for the 8 bit comparator with pre-
determined thresholds. The detailed description of the comparator simulation is contained
in Section 3.5.4. Finally, Figure 17 shows the simulation results for the 16-bit counter
which is divided into four parts due to the amount of data displayed. The detailed descrip-
tion of the counter simulation is contained in Section 3.5.5.

For the typical simulation of the smart logic integrated circuit, for the special case n=3,
m=1, t’=125 nsec, tA/D=116 nsec, and f=0.003 MHz, each of the monitoring nodes are
identified in Figure 29.b. The O7 to 00 and A15 to A0 are output signals. The former is
sent to memory as an input data signal and the latter is sent to memory as an input address
signal. The 17 to 10 and CLK8MH are input signals representing digitalized impact force
data and clock signals from the crystal, respectively. The important signals are SO, 81,
LE_, RS1, SWC and CNTC because SO and 8] choose the input signals from the x, y, z
axis, LE_ controls the CNTC, RSl controls the SWC cycle, SWC generates SO and SI,
and CNTC generates the address bus A15 to A0. The detailed descriptions of these sig-

nals are contained in Section 5.3. The simulation results are shown in Figure 32.

83

5.3 Discussion

The relative input and output data are listed in Appendix 4. The corresponding signal
plots are shown in Figure 32. The simulation trace data file of the SLIC are listed in the
Appendix 5. The input signals are two impact forces shown in Figure 33. The output sig-
nals are delayed one time unit (384 11s) and the first two data values are replaced by a
heading and time of occurrence for each significant impact pulse. Because the sampling
time is very small compared to each impact period, generally, each impact pulse has many
samples, so that the first two data points can easily be sacrified. Because simulation times
are very long for each data sample, we only choose 4 data samples for the first impact
force and 6 data samples for the second impact.

The first input data for the first impact is 84H, 84H, 84H which is below the threshold.
The relative output data which is delayed one time unit is arbitrary. The second input data
is 84H, 84H, COH which is over the threshold. The relative output data which is delayed
one time unit is 80H, 80H, 80H which represents heading. The third input data is EOH,
EOH, EOH which is also over the threshold. The relative output data which is delayed one
time unit is 00H, 00H, OCH which represents the real time clock count. The fourth input
data is EOH, EOH, 84H which is over the threshold. The relative output data which is
delayed one time unit is EOH, EOH, 84H, the same as the input data.

‘ The first input data for the second input pulse is 84H, 84H, 84H'which is below the
threshold. The relative output data which is delayed one time unit is arbitrary. The sec-
ond input data is 84H, COH, COH which is over the threshold. The relative output data,
delayed one time unit, is 80H, 80H, 80H which represents heading. The third input data is
AOH, AOH, AOH which is over the threshold. The relative output data, delayed one time
unit, is 00H, OOH, 18H which represents the real time clock count. The fourth input data is
EOH, EOH, EOH, which is over the threshold, gives an output, delayed one time unit, of
EOH, EOH, EOH which is the same as the input data. The fifth input data above threshold,
COH, COH, COH gives a unit delayed output of COH, COH, COH again the same as the

84

input data. The sixth input data is 84H, 84H, 84H which is below the threshold, and thus
gives a unit delayed output which is arbitrary.

Thus the system processes all the input signals which are above the threshold and dis-
plays them as output signals, except for the first two data points above threshold which are
used to generate a heading and time before each group of output signals relative to one
impact. Thus we can identify each group of output signals for each impact pulse and save
memory by ignoring all input signals below the threshold. We can recognize the time of

occurrance for each impact.

 

85

 

Figure 29.a - The detailed circuit diagram for the data acquisition system with n=3, m=l.

86

 

Figure 29.b - The detailed circuit diagram for the smart logic circuit (special case of n=3.

m=1).

 

87

LKBMH

 

 

 

 

 

 

ccccc

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NTC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I f

. 1 1 . 1 1 1 . L 1 1
331200 332800 334400

 

 

 

 

 

 

Figure 30 - The simulation results of the CSC (counter & switch clock) generator circuit

for n=3.

88

CLK8MH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK500KH

 

07

 

06

05

 

I7

 

IS

 

 

 

 

 

SO

 

 

 

 

$1

 

 

LE.

 

'RSi

 

 

 

l-‘W

 

 

 

 

 

 

 

 

 

SVC

 

Err—Tc

 

 

 

1
L

8280005

L

1 l 1 1 1 l 1 1 1 1 1 1 .1 L
329600 331200 332800 334400

Figure 31.8 - The simulation results of the data acquisition system with n=3, m=1, t’=125

nsec, t=2 nsec, f=0.003 MHz.

89

CLK8MH

 

 

 

 

 

 

 

 

 

 

 

CLK500KH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I7

16

 

IS

 

 

 

 

80

 

 

 

 

51

 

 

 

LE.

 

 

 

 

 

 

SVC

 

 

 

 

 

 

 

 

 

CNTC

 

 

 

 

 

 

 

 

 

r1
2
IA 14 1 1 1 1

_1 1 1 1 1 1 1 1
662400 664000 665600

1 l 1 1 1 1
667200 668600

Figure 31.6 - The simulation results of the data acquisition system with n=3, m=1, t’ =125

nsec, t=2 nsec, f=0.003 MHz, continued.

 

9O

WMWJUWUWM

£LK8MH

 

 

 

 

 

 

 

 

 

 

 

CLK600KH
b7

06

 

 

 

 

05

 

 

 

 

 

 

 

 

 

 

SO

 

 

 

 

$1

 

 

 

LE.

 

'RSl

 

 

 

 

 

 

 

 

 

 

 

 

SVC

 

CNTC

 

A0

I“

P2

 

J1 % A

1 1 1 1 1 1 1 4 I
996800 998400 1003

m l 1 1 l 1
1000000 1001600
Figure 31.c - The simulation results of the data acquisition system with n=3, m=1, t’ =125

nsec, t=2 nsec, f=0.003 MHz, continued.

91

F 1 IF I
1 j‘ I I
L J 1 I
9 L_ 1 l
1 I
Z I In
I
t: : m .
_ 1.1
L
. k
1 I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LIZ.

 

 

 

 

LEFF

 

 

 

1 1 1 l 1 1 1

1 1 14 1 1 1 1 | .
204800 409600 614400 019200 204800 409600 614400 019200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LE2.

 

 

 

 

 

.gmwgfifimfm

r:

C __ ......1
1: PFjj ___

 

‘01

11_1i111_L11¥
. . . . . . . 1 . . . 1 1 1 1 1 .
°° °‘92°° ‘°2‘°°° ‘22°'°° “335°° 00 019200 1024000 1220000 1435600

 

 

Figure 32.a - The typical simulation results of the smart logic integrated circuit (Special

case of n=3, m=1).

92

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00 1
I—L I
.M '
. 1 1 1 +_1l_._... 1111111111

._L1 1 1 4 1 1 1 1 1
M7
1433600 1638400 1843200 2040000 2252800 1433500 1630400 “‘32“ 2“.”0 #2252800

 

 

 

— .

 

 

 

L.

 

 

 

 

 

 

 

!l
"l

LI LT
b 11

NY

12x.
EYE:
WM “gm LI

 

 

 

 

 

 

 

 

 

 

WC “2.
W 1 I l
—_L___f_—_l___l t ‘
J01 . I
W -
WWW
2252000 2457500 2552400 2057200 3072 2252000 2457500 2552400 2557200 3072

Figure 32.b - The typical simulation results of the smart logic integrated circuit (special

case of n=3, m=1), continued.

93

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I'_—_ W I

 

 

 

 

 

 

I" .1. U u
1- ' Lu 1] L]

W 111- 7.! 7_J
W .1 I l . 4
1m W

I I I I _1_1 1 I 1 1 1 | . .
0 3072000 3276000 3401500 3505400 3 0 3072000 3276800 3401600

 

 

 

35064 00 3

 

Figure 32.c - The typical simulation results of the smart logic integrated circuit (special

case of n=3, m=1), continued.

94

(EOH, EOH, EOH)

(FDH, EOH, FDH)

   
   
   
  

(AOH. AOH. AOH)
(EOH, EOH, 84H)
(84H, 84H, COH)

(84H, 84H, 84H) (84H, 841-1, 841-1) (841-1, 84H, 84H)

Figure 33 - TWO impact forces which contain ten sampled data.

 

CHAPTER 6

Conclusions and Directions for Future
Work

6.1 Conclusions

The major motivation for the deve10pment of smart logic is to replace the existing u-P
circuit in order to achieve a total data acquisition sphere of dimension less than 50.8 mm
(2 in.). Other objectives in the research are to reduce power and cost. An extensive indus-
trial demand for such a device exists.

As discussed in Chapter 4, the size of the composite smart logic chip based 18 is about
38 mm (1.5 in.), or ll 12 the volume of the first commercial unit. The power consumption
for the composite smart logic chip based IS is about 5.24 mA per hour at Vcc=5 V, which
is less than half the current consumption of the conventional u-P based circuit. Thus the
smart logic configuration can accomodate all of the desired features - smaller size, longer
Operation time and ultimately lower cost.

If specifications were to change, for example tA/D changed from 2 usec to 116 11sec,
with the other parameters fixed, the power consumption and size remain approximately
the same. This is true even if the other parameters are varied, as shown and discussed in
Chapter 4. Thus the variation in power and size vs specification change is very small indi-

eating a very robost system.

95

 

96

Based on the simulation results discussed in Chapter 5, the smart logic system can
accept all the input signals above an assigned threshold, store these in memory, along with
a data header, and output the data when requested. Thus every impact is recorded and
identified if it surpasses its assigned threshold but ignored if it falls below the threshold.

A 3-D smart logic data acquisition system design with one restriction is developed.

6.2 Directions for Future Work
A composite smart logic chip based IS is a good choice for reducing the size of the IS

and thus allowing the measurement of impacts to smaller produce. This process can be
expanded to include low voltage ICs for example, 3 V as proposed by Prince and Salters
[62] and Williams [63], or to pursue the Fujitsu proposal to operate a 32 K byte full
CMOS static RAM down to 1 V. These approaches will allow the battery requirements to
decrease, the three cells may be reduced to two cells or one cell, and the battery will last
longer between recharges. Other benefits include substantially smaller size and lower heat
dissipation than for 5 V systems. An early approach would be to fabricate a SLIC as a die
and bond four dice - Op Amp, AID, RAM, SLIC onto a substrate as shown in Figure 20.
A diamond film substrate would provide an ideal heat sink for such a high density circuit
configuration. The accelerometer and battery could be connected in a configuration such

as shown in Figure 23.

 

APPENDICES

Appendix 1 Simulation Results for the Latch

The input signals used to run the simulation consist of 2 hexadecimal characters which
represent an impact force similar to that shown in Figure 14. The output signals are delayed
one time unit (384 11s) and the first two data values are replaced by a heading and time of
occurrence for any significant impact pulse (impact data samples above the threshold).
High/Low threshold is set at 8AH/76H (equivalent to +10 gl-lO g). “0” represents
acknowledgment of a signal above the 'threshold and “X” represents a signal below the
threshold.

Input signal: placed on the I7~IO binary data lines
84H, 84H, 84H (100001003, 100001003, 100001003) X
84H, 84H, COH (100001003, 100001003, 110000003) 0
301-1, EOH, EOH (111000003, 111000003, 111000003) 0
EOH, EOH, 84H (111000003, 111000003, 100001003) 0
841-1, 84H, 84H (100001003, 100001003, 100001003) X
Output signal: received on the O7~OO binary data lines
80H, 80H, 84H (100000003, 100000003, 100001003) Arbitrary
80H, 80H, 80H (100000003, 100000003, 100000003) Heading
OCH, OCH, OCH (000000003, 000000003, 000011003) Time
EOH, EOH, 84H (111000003, 111000003, 100001003) 0
EOH, 84H, 84H (111000003, 100001003, 100001003) Arbitrary

97

Appendix 2 The Die Size Variation of the SLIC vs

Specification Change

The tA/D represents the maximum AID conversion time, t’ represents the internal clock
period generated from the crystal, f represents the sampling frequency, n represents the
data dimension, t represents the duration of the clock pulses in the burst, 1/tf represents the
round off of clock count per sampling frequency, 1/tf' represents the clock count per
actual sampling frequency and f' represents the actual sampling frequency. The specifica-

tion changes are made to tA/D and f. No change in die size occurs as a result of specifica-

tion changes.

1ND t’ f
nsec nsec MHz
2 0.125 0.003
4 0.125 0.003
8 0.125 0.003
16 0.125 0.003
32 0.125 0.003
64 0.125 0.003 .
116 0.125 0.003
2 0.125 0.0025
4 0.125 0.0025
8 0.125 0.0025
16 0.125 0.0025
32 0.125 0.0025
64 0.125 0.0025
116 0.125 0.0025

wmwuuuwwuwwwmm

lItf

167
83
42
21
10

5
3

200

100
50
25
13

6
3

decimal binary

10100111
01010011
00101010
00010101
00001010
00000101
00000011
11001000
01100100
00110010
00011001
00001101
00000110
00000011

98

1103
bhuuy
10100111
01010011
00101011
00010111
00001011
00000111
00000011
11000111
01100011
00110011
00011011
00001111
00000111
00000011

f' die size variation

MHz -
0.002994
0.003012
0.002907
0. 0027 17
0.002841
0.002232
0.002604
0.0025 13

0.002525 '

0.00245 1
0.0023 15
0.002083
0.002232
0.002604

OCOOOCOCOOOOOO

mm

2

 

Appendix 3 The Chip Size Variation of the Composite
Smart Logic Chip vs Specification Change

The tA/D represents the maximum AID conversion time, t’ represents the internal clock
period generated from the crystal, f represents the sampling frequency, 11 represents the
data dimension, t represents the duration of the clock pulses in the burst, lItf represents the
round off of clock count per sampling frequency, 1Itf' represents the clock count per
actual sampling frequency and f' represents the actual sampling frequency. The specifica-

tion changes are made to tND and f. No change in chip size occurs as a result of specifica-

tionchanges.

t AID t’ f n lItf 1Itf' f' chip size variation
nsec 11sec MHz decimal binary binary MHz mm2
2 0.125 0.003 3 167 10100111 10100111 0.002994 0

4 0.125 0.003 3 83 01010011 01010011 0.003012 0

8 0.125 0.003 3 42 00101010 00101011 0.002907 0

16 0.125 0.003 3 21 00010101 00010111 0.002717 0

32 0.125 0.003 3 10 00001010 00001011 0.002841 0

64 0.125 0.003 3 5 00000101 00000111 0.002232 0

116 0.125 0.003 3 3 00000011 00000011 0.002604 0

2 0.125 0.0025 3 200 11001000 11000111 0.002513 0

4 0.125 0.0025 3 100 01100100 01100011 0.002525 0

8 0.125 0.0025 3 50 00110010 00110011 0.002451 0

16 0.125 0.0025 3 25 00011001 00011011 0.002315 0

32 0.125 0.0025 3 13 00001101 00001111 0.002083 0

64 0.125 0.0025 3 6 00000110 00000111 0.002232 0

116 0.125 0.0025 3 3 00000011 00000011 0.002604 0

99

Appendix 4 Simulation Results of the SLIC

The input signals used to run the simulation consist of 2 hexadecimal characters which
represent two impact forces similar to that shown in Figure 33. The output signals are
delayed one time unit (384 ps) and the first two data values are replaced by a heading and
time of occurrence for any significant impact pulse (impact data samples above the thresh-
old). High/Low threshold is set at 8AH/76H (equivalent to +10 gI-10 g). “0” represents
acknowledgment of a signal above the threshold and “X” represents a signal below the
threshold.

Input signal: placed on the I7~IO binary data lines
84H, 84H, 84H (100001003, 100001003, 100001003) X
84H, 84H, COH (100001003, 100001003, 110000003) 0
EOH, EOH, EOH (111000003, 111000003, 111000003) 0
EOH, EOH, 84H (111000003, 111000003, 100001003) 0
84H, 84H, 84H (100001003, 100001003, 100001003) X
84H, COH, COH (100001003, 110000003, 110000003) 0
AOH, AOH, AOH (101000003, 101000003, 101000003) 0
EOH, EOH, 30H (111000003, 111000003, 111000003) 0
COH, COH, COH (110000003, 110000003, 110000003) 0
84H, 84H, 84H (100001003, 100001003, 100001003) X
Output signal: received on the O7~OO binary data lines
80H, 80H, 84H (100000003, 100000003, 100001003) Arbiu'ary
80H, 80H, 80H (100000003, 100000003, 100000003) Heading
00H, 00H, OCH (000000003, 000000003, 000011003) Time
EOH, EOH, 84H (111000003, 111000003, 100001003) 0
EOH, 84H, 84H (111000003, 100001003, 100001003) Arbitrary

100

101

80H, 80H, 80H (100000003, 100000003, 100000003) Heading

OOH, OOH, 18H (000000003, 000000003, 000110003) Trme

EOH, EOH, 30H (111000003, 111000003, 111000003) 0

COH, COH, COH (110000003, 110000003, 110000003) 0
Address for memory: A14~AO binary data address lines

The simulation monitoring nodes shown in Figure 32 are:

1. O7, O6, 05, O4, O3, 02, 01, 00: Output data bit 7, 6, 5, 4, 3, 2, 1, 0 from latch.
2. ENX_, ENY_, ENZ_: Post latch enable control for X, Y, Z axis.

3. R81: Reset signal in CSC (counter & switch clock) generator.

4. SWC: Switch clock generated from CSC.

5. I7, 16, 15, 12: Input data bit 7, 6, 5, 2 to pre-latch.

6. SO, 81: Selective address for AID analog switch.

7. LEX_, LEY_, LEZ_: Latch enable control from comparator for X, Y, Z axis.
8. LE_: Post latch enable control.

9. CNTC: Counter clock generated from CSC.

10. A0, A1: Address bus for memory.

 

Appendix 5 Simulation Trace Data File of the SLIC

The input signals used to run the simulation consist of 2 hexadecimal characters which
represent two impact forces similar to that shown in Figure 33. The output signals are
delayed one time unit (384 us) and the first two data values are replaced by a heading and
time of occurrence for any significant impact pulse (impact data samples above the thresh-

old). HighILow threshold is set at 8AH/7 6H (equivalent to +10 gl-lO g).
Time - 1:1 [0 ns].

I7 - 1 [O] (input)(display)
I6 - O [0] (input)(disp1ay)
I5 - O [0] (input)(disp1ay)
12 - 1 [0] (input)(display)
SO - u [0] (output)(disp1ay)
$1 - u [0] (output)(display)
LEX_ - u [0] (output)(disp1ay)
LEY_. - u [0] (output)(disp1ay)
LEZ - u [0] (output)(display)
LE - u [0] (output)(display)
CNTC - u [0] (output)(display)
A0 - u [0] (output)(display)
A1 - u [0] (output)(display)
A2 - u [0] (output)(disp1ay)
A3 - u [0] (output)(display)
A4 - u [0] (output)(disp1ay)
I4 - 0 [O] (input)(disp1ay)
I3 - O [O] (inputltdisplay)
Il - 0 [0] (input)(display)
IO - O [0] (input)(display)
T2 - u [0] (output)(display)
QO - u [0] (output)(disp1ay)
Ql - u [0] (output)(disp1ay)
QZ - u [0] (output)(display)
CLR - 0 [0] (input)(disp1ay)
RS - O [O] (input)(display)
OX7 - u [0] (output)(display)
0Y7 - u [0] (output)(display)
027 - u [0] (output)(disp1ay)
CLK8MH - u [0] (clock)(disp1ay)
O7 - u [0] (output)(display)
06 - u [0] (output)(display)
05 - u [0] (output)(disp1ay)
04 - u [0] (output)(display)
03 - u [0] (output)(display)
02 - u [0] (output)(disp1ay)
01 - u [0] (output)(disp1ay)
00 - u [0] (output)(disp1ay)
ENX_ - u [0] (output)(disp1ay)
ENX_ - u [0] (output)(disp1ay)
ENz_ - u [0] (output)(disp1ay)
RSI - u [0] (output)(display)
SWC - u [0] (output)(disp1ay)

102

Time - 1:1
CLK8MH --> 0
L82_ --> 1
LE¥_ --> 1
LEX_ --> 1
R31 --> 0
ENY_ --> 1
BNZ_ --> 1
A2
A3

I
I
V
O

I
I
V
IHOOOOOOO

Time
CLK8MH
Time - 2:
RS --> 1
CLR --> 1
CLK8MH -—> 0
R81 --> 1
LE_ --> 1
07 --> 0
Time - 2:
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH

1:

l
l
v
when:

l
I
V
HNOHHNOHHNOHHN

103

[0 ns]
[+0/0]
[+4.1/O]
[+4.1/0]
[+4.1/O]
[+7/0]
[+13.3/0]
[+13.3/0]
[+15/0]
[+15/0]
[+15/0]
[+15/0]
[+15/O]
[+17.6/O]
[+17.7/0]
[+17.7/0]
[+17.7/0]
[+19.5/Ol
[+20.4/0] °
[+20.6/01
[+22.1/0]
[+24.4/O]
[+26.8/0]
[+29.4/0]
[+33.7/0]
[+35.3/01
[+36.6/O]
[+36.6/O]
[+36.6/Ol
[+36.6/01
I+36.6/01
[+36.6/O]
[+36.6/0]
[+45.2/0]
[62.5 ns]
[+0/01
[125 ns]
[+0/01
[+0/01
[+0/01
[+6.4/6.4]
[+24.7/5.1]
[+32/.41
[187.5 ns]
[+0/01
[250 ns]
[+0/0]
[312.5 ns]
[+0/O]
[375 ns]
[+0/Ol
[437.5 ns]
[+0/01
[500 ns]
[+O/0]
[562.5 ns]
[+O/0]

Time - 5121:1 [640000

104

ns]
17
I6
IS
12
SO
81
Lex_
Ler_
LEZ_

Q2
CLR
RS
OX7
0Y7
OZ7

CLK8MH

Time - 5121:1 [640000

CLK8MH --> 0

[+0/0]

Time - 5121:2 [640062.

CLK8MH --> 1

02 --> o
01 --> o
00 --> o
SWC --> 0
$1 --> 1

[+0/01
[+25.5/7.9]
[+26.7/9.1]
[+28.2/10.6]

[+33/15.4]
[+59.7/17.4]

O7
06
05
O4
O3
02
01
OO
ENX_
ENY_
ENZ_
R81
SWC
ns]

5 ns]

HHHHHOOOOOOOHHHHHHHHHHHOOOOOOOOOOHHHHOHHOOH

[O] (input)(display)
[0] (input)(display)
[0] (input)(disp1ay)
[0] (input)(disp1ay)

[512131.
[384128.
(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)

[4.1]
[4.1]
[4.1]
[149.7]
[29.4]

1] (output)(display)
1] (output)(display)

(output)(display)
(output)(disp1ay)

[15] (output)(disp1ay)
[15] (output)(display)
[15] (output)(display)
[15] (output)(display)
[15] (output)(display)
[0] (input)(disp1ay)
[O] (input)(display)
[0] (input)(display)
[0] (input)(disp1ay)

[384145.
[638092.
[636091]
[632089.
(input)(disp1ay)
(input)(disp1ay)

[125]
[125]
[17.7]
[17.7]
[17.7]
[639937

[256150
[256150

[35.3]
[13.3]
[13.3]

[384151.
[5760981

1] (output)(display)
6] (output)(disp1ay)
(output)(display)
7] (output)(display)

(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)

.5] (clock)(disp1ay)
[384176.
.2] (outputltdisplay)
.2] [output)(display)
[256150.
[256150.
[256150.
[384140.
[384140.

6] (output)(display)

2] (output)(disp1ay)
2] (output)(disp1ay)
2] (output)(display)
3] (output)(display)
3] (output)(display)
(output)(display)

(output)(display)

(output)(disp1ay)

5] (output)(display)

(output)(disp1ay)

Time
CLK8MH

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
, Time
I6 -->
12 -->
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH

- 5122:1
..-) 0
[+8

[+8
[+8

OOOOOOOHOflflCCCGCC

- 5122:2

I
U"
H
N
U
h) 0a n: be

- 5125'1

1 [+0/01

[640125
[+0/0]

.7/0]
[+8.
[+8.
[+8.

7/0]
7/0]
7/0]

.7/0]
.7/0]
[+8.
[+9.
[+13/29.2]
[+24.5/0]
[+25.2/0]
[+25.2/0]
[+25.2/0]
[+25.2/0]
[+25.2/0]
[+25.2/0]
[+25.2/0]

7/0]
4/0]

[640187
[+0/0]
[640250
[+0/0]
[640312
[+0/0]
[640375
[+0/0]
[640437
[+0/O]
[640500

0 [+0/O]

-—> 0
- 5125:2
--> 1
- 5126:1
--> 0
- 5126:2
--> 1

[+0/0]
[640562
[+0/0]
[640625
[+0/0]
[640687
[+0/0]

105

ns]

.5 ns]
ns]
.5 ns]
ns]
.5 ns]

ns]

.5 ns]
ns]

.5 ns]

 

Time - 6138:1

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH

- 6138:
--> 0
- 6138:
--> 1
- 6139:
--> 0
- 6139:
--> 1
- 6140:
....) 0
- 6140:
--> 1

NHNHNH

106

[767125 ns]
17

02
CLR

RS

OX7
CY?
027
CLK8MH
O7

00
EN&_
ENY_
ENZ_
R81
SWC
[767125 ns]
[+0/0]
[767187.5 ns]
[+0/0]
[767250
[+0/0]
[767312.5 ns]
[+0/0]
[767375 ns]
[+0/0)
[767437.5 ns]
[+010]

ns]

IdOJ<DFJPJC>C>HHD<DC>C>HHJFJFJPJF‘HHJFJF4F‘CHD¢D<>C>C>CHD<DFJC>C>HHHFJCDCDCHHFJ

[0]
[0]

[4.1]
[4.1]

[15]
[15]
[15]
[15]
[15]
[0]
[0]
[0]
[0]

[125]
[125]
[17.7]
[17.7]
[17.7]
[767062

[640150

[640150

[35.3]
[13.3]

[704133.
[384151.
[704098]

(input)(disp1ay)
[640500]
(input)(disp1ay)
[[640500]
[640138]
[640122.
[output)(disp1ay)
(output)(disp1ay)
[704113.
[704125.61
[704128.
(output)(display)
(output)(disp1ay)
(output)(display)
(output)(display)
(output)(disp1ay)
(input)(display)
(input)(display)
(input)(disp1ay)
(input)(display)
[384145.
[766092.
[764091]
[760089.
(input)(disp1ay)
(input)(display)

[input)(disp1ay)

(input)(disp1ay)
(output)(display)
2] (output)(display)

3] (output)(disp1ay)
(output)(disp1ay)
2] (output)(display)

1] (output)(disp1ay)
6] (output)(disp1ay)
(output)(disp1ay)
7] (output)(disp1ay)

(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)

.5] (clock)(disp1ay)
[640149.
[640150.
.2] (output)(disp1ay)
[640150.
[640150.
[704149.
.2] (output)(display)
[640150.

5] (output)(display)
2] (output)(disp1ay)

2] (output)(display)
2] (output)(disp1ay)
1] (output)(disp1ay)

2] (output)(display)

(output)(disp1ay)

(output)(disp1ay)

9] (output)[display)

5] (output)(disp1ay)
(output)(disp1ay)

107

Time - 6141:1 [767500 ns]
CLK8MH --> 0 [+0/0]

Time - 6141:2 [767562.5 ns]
CLK8MH --> 1 [+0/0]

Time - 6142:1 [767625 ns]
CLK8MH --> 0 [+0/0]

Time - 6142:2 [767687.5 ns]
CLK8MH --> 1 [+0/0]

Time - 6143:1 [767750 ns]
CLK8MH --> 0 [+0/0]

Time - 6143:2 [767812.5 ns]
CLK8MH --> 1 [+0/0]

Time - 6144:1 [767875 ns]
CLK8MH --> 0 [+0/0]

Time - 6144:2 [767937.5 ns]
CLK8MH --> 1 [+0/0]

Time - 6145:1 [768000 ns]
CLK8MH --> 0 [+0/O]

Time - 6145:2 [768062.5 ns]
CLK8MH --> 1 [+0/0]
02 --> 0 [+25.5/7.9]
01 --> 0 [+26.7/9.1]
00 --> 0 [+28.2/10.6]
SWC --> 0 [+33/15.4]
CNTC --> 0 [+35.6/2.6]
zuz_ --> 1 [+41.5/7.7]
A0 --> 1 [+49.4/.S]

Time - 6146:1 [768125 ns]
CLK8MH --> 0 [+0/0]
T2 --> 0 [+2.5/1.9]
81 --> 0 [+3.1/19.3]
R81 --> 0 [+9.5/7]
02 -—> 0 [+15.3/.4]
T2 --> 1 [+20.1/2.1]
R81 --> 1 [+26.5/6.4]

Time - 6146:2 [768187.5 ns]
CLK8MH --> 1 [+0/0]

Time - 6147:1 [768250 ns]
CLK8MH --> 0 [+0/0]

Time - 6147:2 [768312.5 ns]
CLK8MH --> 1 [+0/O]

Time - 6148:1 [768375 ns]
CLK8MH --> 0 [+0/0]

Time - 6148:2 [768437.5 ns]
CLK8MH --> 1 [+0/0]

Time - 6149:1 [768500 ns]
15 --> 1 [+0/0]
CLK8MH --> 0 [+0/0]

Time - 6149:2 [768562.5 ns]
CLK8MH --> 1 [+0/0]

Time - 11257:1

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH

- 11257:

--> 0

- 11257:

--> 1

- 11258:

--> 0

- 11258:

--> 1

- 11259:

-~> 0

H

HNHN

108

[1407000 ns]

02

CLR

RS

OX7
CY?
027
CLK8MH

00
ENX_
ENY_
ENZ_
R81
SWC
[1407000 ns]
[+0/0]
[1407062.5 ns]
[+0/0]
[1407125 ns]
(+0/0]
[1407187.5 ns]
[+0/0]
[1407250 ns]
[+0/0]

O
O
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

HHHOHOOOOOOOOHHHHHHHHHHOOOOOOHOHHOOOOOHOHHH

[0] (input)(display)

[640500] (input)(display)
[768500] (input)(display)
[640500] (input)(disp1ay)
[1280131.1] (output)(disp1ay)
[1152128.1] (output)(disp1ay)
[832113.31 (output)(disp1ay)
[960113.31 (output)(display)
[704113.31 (output)(display)
[704125.61 (output)(display)
[1344100] (output)(display)
[1280111.9] (output)(disp1ay)
[1152115.7] (output)(display)
[1152111.9] (output)(display)
[15] (output)(disp1ay)

[15] (output)(display)

[O] (input)(display)

[O] (input)(disp1ay)

[0] (input)(disp1ay)

[0] (input)(display)
[1152145.1] (output)(disp1ay)
[1406092.6] (output)(disp1ay)
[1404091] (output)(display)
[1400089.7] (output)(display)
[125] (input)(disp1ay)

[125] (input)(display)

[17.7] (output)[disp1ay1
[17.7] (output)(display)
[17.7] (output)(disp1ay)
[1406937.5] (clock)(display)
[1152177.11 (output)(display)
[1024150.2] (output)(display)
[1024150.2] (output)(display)
[1024150.2] (output)(disp1ay)
[1024150.2] (output)(disp1ay)
[1024150.2] (output)(disp1ay)
[1024150.2] (output)(disp1ay)
[1024150.2] (output)(display)
[1280104] (output)(display)
[1344107.1] (output)(disp1ay1
[1152104] (output)(display)
[1152151.5] (output)(disp1ay)
[1344098] (output)(display)

Time - 11259:2 [1407312

CLK8MH --> 1 [+0/0]
Time = 11260:1 [1407375

CLK8MH --> 0 [+0/0]
Time - 11260:2 [1407437

CLK8MH --> 1 [+0/0]
Time - 11261:1 [1407500

CLK8MH --> 0 [+0/0]
Time - 11261:2 [1407562

CLK8MH --> 1 [+0/0]
Time - 11262:1 [1407625

CLK8MH --> 0 [+0/0]
Time - 11262:2 [1407687

CLK8MH --> 1 [+0/01
Time - 11263:1 [1407750

CLK8MH --> 0 [+0/0]
Time - 11263:2 [1407812

CLK8MH --> 1 [+0/0]
Time - 11264:1 [1407875

CLK8MH --> 0 [+0/0]
Time - 11264:2 [1407937

CLK8MH --> 1 [+0/O]
Time - 11265:1 [1408000

CLK8MH --> 0 [+0/0]
Time - 11265:2 [1408062

CLKBME --> 1 [+0/0]

02 --> 0 [+25.5/7.9]

01 --> 0 [+26.7/9.1]

00 --> 0 [+28.2/10.6]

SWC --> O [+33/15.4]

CNTC --> o [+35.6/2.6]

anx_ --> 1 [+41.5/7.7)

A1 --> 1 [+49.4/.5]

A0 --> 0 [+53.2/.7]

$1 --> 1 [+59,7/17.4]w
Time - 11266:1 [1408125

CLK8MH --> 0 [+0/0]

07 --> u [+8.7/0]

03 --> u [+8.7/0]

02 --> u [+8.7/0]

01 -—> u [+8.7/0]

00 --> u [+8.7/0]

04 --> u [+8.7/0]

05 --> u [+8.7/0]

06 --> u [+8.7/0]

80 --> 0 [+13/29.21

00 --> 1 [+24.5/0]

03 --> 1 [+24.5/O]

01 --> 1 [+24.5/0]

07 --> 0 [+25.2/0]

02 --> 0 [+25.2/0]

04 --> 0 [+25.2/0]

05 —-> 0 [+25.2/0]

06 --> 0 [+25.2/O]

109

.5 ns]
ns]
.5 ns]
ns]
.5 ns]
ns]
.5 ns]
ns]
.5 ns]
ns]
.5 ns]
ns]

.5 ns]

ns]

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
I6 -->
I5 -->
12 -->
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH

- 11266:

--> 1

- 11267:

--> 0

= 11267:

--> 1

- 11268:

--> 0

- 11268:

-—> 1

- 11269:

--> 0

= 11269:

--> 1

- 11270:

--> 0

- 11270:

--> 1

- 11271:
0 [+0/O]

N

2
1

[1408187.

[+0/0]
[1408250
[+0/O]
[1408312
[+0/0]
[1408375
[+0/0)
[1408437
[+0/0]
[1408500
[+0/0]
[1408562
[+0/o]
[1408625
[+0/O]
[1408687
[+0/0]
[1408750

0 [+0/0]
1 [+0/0]

--> 0

- 11271:

--> 1

- 11272:

--> O

2
1

- 11272:2

--> 1

[+0/01

[1408812.

[+0/0]
[1408875
[+0/01

[1408937.

[+0/Ol

110

5 ns]

ns]

.5 ns]

ns]

.5 ns]

ns]

.5 ns]

ns]

.5 ns]

ns]

5 ns]
ns]

5 ns]

Time

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
QZ -->
01 -->
00 -->

SWC --> 0

111

- 12288:1 [1535875 ns]

02
CLR
RS
0x7
CY?
027
CLK8MH
O7
06
05
O4
03
O2
01
00
Eux_
ENY_
ENZ_
R81
SWC
[1535875 ns]
[+0/0]
[1535937.5 ns]
[+O/01
[1536000 ns]
[+0/0]
- 12289:2 [1536062.5 ns]
--> 1 [+0/0]
0 [+25.5/7.9]
0 [+26.7/9.1]
0 [+28.2/10.61
[+33/15.4]

O
O
IllIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

- 12288:1
--> 0
- 12288:2
—-> 1
- 12289:1
--> 0

HHOHHOOHHOOOOHHHHHHHHHHOOOOOOHHOHOHOOHOHOOH

[0] (input)(disp1ay)

[1408750] (input)(display)
[1408750] (input)(display)
[1408750] (input)(disp1ay)
[1408138] (output)(display)
[1408122.2] (output)(display)
[832113.31 (output)(disp1ay)
[960113.3] (output)(display)
[1472112.1] (output)(disp1ay)
[704125.61 (output)(disp1ay)
[1472100] (output)(disp1ay)
[1408115.7] (output)(disp1ay)
[1408111.9] [output)(disp1ay)
[1152111.9] (output)(disp1ay)
[15] (output](disp1ay)

[15] (output)(disp1ay)

[O] [input)[display)

[0] (input)(disp1ay)

[0] (input)(disp1ay)

[0] (input)(disp1ay)
[1152145.1] (output)(disp1ay)
[1534092.6] [output)(display)
[1532091] (output)(disp1ay1
[1528089.7] (output)(disp1ay)
[125] (input)(disp1ay)

[125] (input)(disp1ay)

[17.7] (output)(display)
[17.7] (output)(disp1ay)
[17.71 (output)(disp1ay)
[1535812.5] (clock)(disp1ay)
[1408150.2] (output)(disp1ay)
[1408150.2] (output)(disp1ay)
[1408150.2] [output)(disp1ay)
[1408150.2] (output)(disp1ay)
[1408149.5] (output)(display)

[1472126] (output)(display]
[1472125.5] (output)(disp1ay)
[1472127] (output)(disp1ay]
[1280104] (output)(disp1ay1
[1408104] (output)(disp1ay)

[1472107.11
[1152151.51
[1472098]

(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)

112

CNTC --> 0 [+35.6/2.6]
ENZ_ --> 1 [+41.5/7.7]
A0 --> 1 [+49.4/.5]

Time - 12290:1 [1536125 ns]
CLK8MH --> 0 [+0/0]
T2 ——> 0 [+2.5/1.9]
81 --> 0 [+3.1/19.3]

R81 --> O [+9.5/7]
02 --> 0 [+15.3/.4]
03 --> 0 [+15.3/.4]
T2 --> 1 [+20.1/2.1]
R81 --> 1 [+26.5/6.41
07 --> 1 [+51.6/.5]
06 --> 1 [+51.6/.51
05 --> 1 [+51.6/.5]

Time - 12290:2 [1536187.5 ns]
CLK8MH --> 1 [+0/0]

Time - 12291:1 [1536250 ns]
CLK8MH --> 0 [+0/0]

Time - 12291:2 [1536312.5 ns]
CLK8MH -—> 1 [+0/0]

Time - 12292:1 [1536375 ns]
CLKBMR ——> 0 [+0/0]

Time - 12292:2 [1536437.5 ns]
CLK8MH --> 1 [+O/0]

Time - 16379:1

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Tbme
CLK8MH

- 16379:
--> 0
a 16379:
--> 1
- 16380:
-—> O
- 16380:
--> 1
- 16381:
--> 0

1

NHN

113

[2047250 ns]

02
CLR
RS
0x7
0!?
OZ?
CLK8MH
07
06
05
04
03
02
01
00
ENX_
ENY_
ENZ_
R81
swc
[2047250 ns]
[+0/01
(2047312.5 ns]
[+0/0]
[2047375 ns]
[+0/0]
[2047437.5 ns]
[+0/0]
[2047500 ns]
[+0/0]

O
O
IIIIIIIIIIIIIIIIIIIIIlllllllllllllllllllllllllllll

1dDdFJFJPJC>C>C>C>CHH[JFJFJF‘F‘HHHFJPJFJF4F‘C>C>CHD<DFJ<DFJC>C>F‘HHHFHCDCDFJC>CHH

[0] (input)(disp1ay)

[1408750] (input)(display)
[1408750] (input)(disp1ay)
[1408750] (input)(display)
[1792138] (output)(display)

[1920128.1]
[1600112.1]
[1728112.11
[1472112.11
[1920169.8]
[1920098.1]
[1920115.7]
[1920111.9]

(output)(disp1ay)
(output)(display)
(output)(display)
(output)(display)
(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
[1664115.7] (output)(display)
[1664111.9] (output)(disp1ay)
[15] (output)(display)

[0] (input](display)

[0] (input)(disp1ay)

[0] (input)(display)

[0] (input)(display)
[1920145.1] (output)(display)
[2046092.6] (output1(disp1ay)
[2044091] (output)(disp1ay)
[2040089.7] (output)(disp1ay)
[125] (input)(display)

[125] (input)(disp1ay)

[17.7] (output)(display)
[17.7] (output)(disp1ay)
[17.7] (output)(display)
[2047187.51 (clock)(disp1ay)
[1792149.5] (output)(disp1ay)
[1920139.6] (output)(disp1ay]
[1920139.6] (output)(disp1ay)
[1792150.2] (output)(disp1ay)
[1792150.2] (output)(display)
[1920140.3] (output)(display)
[1792150.2] (output)(disp1ay)
[1792150.2] (output)(display)

[1664104] (output)(display)
[1792104] (output)(disp1ay)
[1920104] (output)(display)
[1920151.5] (output)(disp1ay)
[1984098] (output)(disp1ay)

114

Time = 16381:2 [2047562.5 ns]
CLK8MH --> 1 [+0/0]

Time = 16382:1 [2047625 ns]
CLK8MH --> 0 [+0/0]

Time = 16382:2 [2047687.5 ns]
CLK8MH --> 1 [+0/01

Time - 16383:1 [2047750 ns]
CLK8MH --> 0 [+0/0]

Time = 16383:2 [2047812.5 ns]
CLK8MH --> 1 [+0/0]

Time - 16384:1 [2047875 ns]
CLK8MH --> o [+0/01

Time - 16384:2 [2047937.5 ns]
CLK8MH --> 1 [+0/0]

Time - 16385:1 [2048000 ns]
CLK8MH --> 0 [+0/0]

Time - 16385:2 [2048062.5 ns]
CLK8MH --> 1 [+0/0]
Q2 --> 0 [+25.5/7.91
Ql --> 0 [+26.7/9.1]
00 --> 0 [+28.2/10.6]
SWC --> 0 [+33/15.4]

Time - 16386:1 [2048125 ns]
CLK8MH -—> 0 [+0/0]
80 --> 1 [+6.1/26.3]

Time - 16386:2 [2048187.5 ns]
CLK8MH --> 1 [+0/0]

Time - 16387:1 [2048250 ns]
16 --> 1 [+0/0]
12 --> 0 [+0/O]
CLK8MH --> 0 [+0/0]

Time - 16387:2 [2048312.5 ns]
CLK8MH --> 1 [+0/0]

Time - 16388:1 [2048375 ns]
CLK8MH --> 0 [+0/0]

Time - 16388:2 [2048437.5 ns]
CLK8MH --> 1 [+0/0]

115

Time - 18429:1 [2303500 ns]

I7 - 1 [0] (input)(display)
16 - 1 [2048250] (input)(disp1ay)
15 - 0 [1408750] (input)(display)
12 - 0 [2048250] (input)(display)
SO - 0 [2176138] (output)(display)
81 - 1 [2176122.2] (output1(display)
LEX_ - 1 [1600112.1] (output)(disp1ay)
LEY” - 0 [2112113.3] (output)(display)
LEZ_ - 0 [2240113.3] (output)(disp1ay)
LE_ - 0 [2112125.6] (output)(disp1ay)
CNTC - 1 [2240100] (output)(disp1ay)
A0 - 1 [2176111.9] (output)(disp1ay)
A1 - 1 [1920111.9] (output)(disp1ay)
A2 - 0 [1664115.7] (output)(disp1ay)
A3 - 1 [1664111.9] (output)(disp1ay)
A4 - 0 [15] (output)(disp1ay)
I4 - 0 [0] (input)(display)
13 - 0 [0] (input)(display)
11 - 0 [0] (input)(disp1ay)
10 - 0 [0] (input)(display)
T2 - 1 [1920145.1] (output)(display)
QO - 1 [2302092.6] (output)(disp1ay)
Ql - 1 [2300091] (output)(disp1ay)
QZ - 1 [2296089.7] (output)(disp1ay)
CLR - 1 [1251 (input)(disp1ay)
R8 - 1 [125] (input)(disp1ay)
0x7 - 1 [17.7] (output)(disp1ay)
0Y7 - 1 [17.7] (output)(disp1ay)
027 - 1 [17.71 (output)(disp1ay)
CLK8MH - 1 [2303437.5] (clock)(disp1ay)
O7 - 1 [2176149.5] (output)(disp1ay1
O6 - 0 [2176150.2] (output)(disp1ay)
05 - 0 [2176150.2] (output)(display)
O4 - 0 [2176150.2] (output)(disp1ay)
O3 - 0 [2176150.2] (output)(disp1ay)
02 - 1 [2176149.5] (output)(disp1ay)
01 - 0 [2176150.2] (output)(disp1ay)
00 - 0 [2176150.2] (output)(disp1ay)
BNX_ - 1 [1664104] (output](disp1ay)
ENY_ - 1 [21761041 (output)(disp1ay)
ENz_ - 0 [2240107.1] (output)(display)
R81 - 1 [1920151.51 (output)(disp1ay)
- SWC - 1 [2240098] (output)(disp1ay)
Time - 18429:1 [2303500 ns]
CLK8MH --> 0 [+0/0]
Time - 18429:2 [2303562.5 ns]
CLK8MH --> 1 [+0/0]
Time - 18430:1 [2303625 ns]
CLK8MH --> 0 [+0/0]
Time - 18430:2 [2303687.5 ns]
CLK8MH --> 1 [+0/0]
Time - 18431:1 [2303750 ns]
CLK8MH --> 0 [+0/0]

Time - 18431:2 [2303812.5 ns]
CLK8MH --> 1 [+0/0]

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
QZ -->
Q1 -->
00 -->

SWC --> 0
CNTC —-> 0
suz_ --> 1

A2 -->
A1 -->
A0 -—>

Time
CLK8MH
T2 -—>
81 -->

R81 --> O

06 -->
05 -->
02 -->
T2 -->

RSl --> 1

06 -->
05 -->
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
16 -->
15 -->
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH

116

- 18432:1
--> 0
= 18432:2
--> 1
= 18433:1
--> 0

[2303875 ns]
[+0/0]

[2303937.5 ns]
[+0/0]

[2304000 ns]
1+0/01
- 18433:2 [2304062.5 ns]
--> 1 [+0/0]

0 [+25.5/7.9]

0 [+26.7/9.1]

0 [+28.2/10.6]

[+33/15.4]
[+35.6/2.6]
[+41.5/7.7]

1 [+49.4/.5]

0 [+53.2/.7]

0 [+53.2/.7]

- 18434:1 [2304125 ns]
--> 0 [+0/0]

0 [+2.5/1.9]

0 [+3.1/19.3]

[+9.5/7]

1 [+14.6/.5]

1 [+14.6/.5]

0 [+15.3/.4]

1 [+20.1/2.1]

[+26.5/6.4]

0 [+57.9/.4]

0 [+57.9/.4]

- 18434:2 [2304187.
--> 1 [+0/0]

- 18435:1 [2304250
--> 0 [+0/0]

- 18435:2 [2304312.
--> 1 [+0/0]

- 18436:1 [2304375
0 [+0/0]

1 [+0/0]

--> 0 [+0/0]

- 18436:2 [2304437.
--> 1 [+0/01

- 1843731 [2304500
--> 0 [+0/0]

a 18437:2 [2304562.
--> 1 [+0/01

5 ns]
ns]
5 ns]

ns]

5 ns]
ns]

5 ns]

Time = 21507:1 [2688250 ns]

17 - 1 [0] (input)(disp1ay)
16 - 0 [2688125] (input)(display)
15 - 1 [2304375] (input)(display)
12 - 0 [2048250] (input)(display)
SO - 0 [25601381 (output)(disp1ay)
81 - 0 [2688128.1] '(output)(disp1ay)
LEX_ - 0 [2368113.3] (output)(disp1ay)
LEY_ - 0 [2112113.3] (output)(disp1ay)
LEZ_ - 0 [2240113.3] (output)(disp1ay)
LE_ - O [2112125.61 (output)(disp1ay)
CNTC - 0 [2688098.1] (output)(disp1ay)
A0 - 1 [2688111.9] (output)(display)
A1 - 1 [2560111.9] (output)(display)
A2 = 1 [2304111.9] (output)(display)
A3 - 1 [1664111.9] (output)(display)
A4 - 0 [15] (output)(display)
14 - O [01 (input)(display)
I3 - 0 [0] (input)(display)
11 - O [0] (input)(disp1ay)
IO - 0 [0] (input)(disp1ay)
T2 - 1 [2688145.1] (output)(disp1ay)
QO - O [2688090.7] (output)(display)
Q1 - 0 [2688089.2] (output)(disp1ay)
02 - 0 [2688088] (output)(display)
CLR - 1 [125] (input)(display)
RS - 1 [125] (input)(disp1ay)
OX7 - 1 [17.7] (output)(disp1ay)
017 - 1 [17.7] (output)(disp1ay)
027 - 1 [17.7] (output)(disp1ay)
CLK8MH - 1 [2688187.51 (clock)(disp1ay)
07 - 0 [2688177.1] (output)(display)
06 - 0 [2560150.21 (output)(disp1ay)
05 - 0 [2560150.21 (output)(display)
04 - O [2560150.21 (output)(display)
03 - 0 [2560150.21 (output)(disp1ay)
02 = 0 [2560150.21 (output)(disp1ay)
01 a 0 [2560150.21 (output)(disp1ay)
00 - 0 [2560150.21 (output)(display)
ENX_ - 1 [2432104] (output)(display)
ENY_ - 1 [2560104] (output)(display)
ENz_ - 1 [2688104] (output)(disp1ay)
R81 - 1 [2688151.5] (output)(disp1ay)
SWC - 0 [2688095.5] (output)(disp1ay)
Time - 21507:1 [2688250 ns]
CLK8MH --> 0 [+0/O]
Time a 21507:2 [2688312.5 ns]
CLK8MH --> 1 [+0/0]
Time - 21508:1 [2688375 ns]
16 --> 1 [+0/0]
CLK8MH --> 0 [+0/0]
Time - 21508:2 [2688437.5 ns]
CLK8MH --> 1 [+0/0]

Time - 21509:1 [2688500 ns]
CLK8MH --> 0 [+0/0]

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH

- 21509:

--> 1

- 21510:

-—> 0

- 21510:

--> 1

- 21511:

--> 0
- 21511

--> 1

2
1
2
1

:2

[2688562.
[+0/0]
[2688625
[+0/0]
[2688687.
[+0/o]
[2688750
[+0/0]
[2688812.

[+0/0]

118

5 ns]
ns]
5 ns]
ns]

5 ns]

Time - 24573:1

= 24573:

-—> 0

- 24573:

--> 1

- 24574:

--> O

- 24574:

--> 1

--> 0

e - 24575:

--> 1

H

NHN

e - 24575:1

119

[3071500 ns]
17

02
CLR
RS
0X7
0Y7
027
CLK8MH
O7
06
05
O4
03
02
01
00
ENX_
ENY
ENZ_
R81
SWC
[3071500 ns]
[+0/0]
[3071562.5 ns]
[+0/0]
[3071625 ns]
[+0/0]
[3071687.5 ns]
[+0/O]
[3071750 ns]
[+0/0]
[3071812.5 ns]
[+0/0]

O
...:
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIllllllllllllllllllllllllll

HHOHHOOOHHOOOHHHHHHHHHHOOOOHOOOHHOOOOHOOHHH

[0] (input)(display)

[2688375] (input)(display)
[2304375] (input)(display)
[2048250] (input)(display)
[2944138] (output)(display)

[2944122.21
[2368113.31
[2112113.31
[2240113.31
[2112125.61
[3008100]

[2944111.9]
[2816115.7]
[2816115.7]

(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
(output)(display)
(output)(disp1ay)
(output)(display)
(output)(display)
[2816115.7] (output)(disp1ay)
[2816111.9] (output)(display)
[0] (input)(disp1ay)
[0] (input)(display)
[01 (input)(display)
[0] (input)(display)
[2688145.1] [output)(display)
[3070092.6] (output)(display)
[3068091] (output)(disp1ay)
[3064089.7] (output)(display)
[125] (input)(disp1ay)
[125] (input)(disp1ay)
[17.7] (output)(display)
[17.7] (output)(display)
[17.7] (output)(disp1ay)
[3071437.5] (clock)(disp1ay)
[2944150.2] (output)(disp1ay)
[2944150.2] (output)(display)
[2944150.2] (output)(disp1ay)
[2944149.5] (output)(disp1ay)
[3008124.9] (output)(disp1ay)
[3008124.4] (output)(display)
[3008125.5] (output)(disp1ay1
[3008127] (output)(display)
[2816104] (output)(disp1ay)
[2944104] (output)(disp1ay)
[3008107.1] (output)[display)
[2688151.5] (output)(disp1ay)
[3008098] (output)(disp1ay)

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
QZ -->
01 —->
co -->

- 24576:1
--> 0
= 24576:2
--> 1
- 24577:1
—-> 0
= 24577:2
--> 1

0
0
0

SWC —-> 0
CNTC --> 0
EN2_ --> 1

A1 -->
A0 -->

Time
CLK8MH
T2 -->
81 -->

1
0

- 24578:1

--> 0
0
0

R81 --> 0

04 -->
03 -->
T2 —->

0
0
1

R81 --> 1

07 -->
05 -->

Time - 24578:2

CLK8MH

Time - 24579:1
--> 0
Time - 24579:2

CLK8MH

CLK8MH

Time - 24580:1

15 -->
CLK8MH

CLK8MH
CLK8MH

CLK8MH

1
1

-—> 1

--> 1

O

--> 0
Time - 24580:2
--> 1
Time - 24581:1
--> 0
Time - 24581:2
--> 1

[3071875
[+0/o]

[+0/0]
[3072000
[+0/0]
[3072062
[+0/0]
[+25.5/7.9]
[+26.7/9.11
[+28.2/10.6]
[+33/15.4]
[+35.6/2.6]
[+41.5/7.7]
[+49.4/.5]
[+53.2/.7]
[3072125
[+0/o]
[+2.5/1.9]
[+3.1/19.31
[+9.5/7]
[+15.3/.4]
[+15.3/.4]
[+20.1/2.1]
[+26.5/6.4]
[+51.6/.5]
[+51.6/.5]

[+0/0]
[3072250
[+0/0]

[+0/0]
[3072375

[+0/0]

[+0/0]
[3072437

[+0/0]
[3072500

[+0/0]
[3072562

[+0/0]

[3071937.

[3072187.

[3072312.

120

ns]
5 ns]

ns]

.5 ns]

ns]

5 ns]
ns]
5 ns]

ns]

.5 ns]

ns]

5 ns]

Time - 27645:1

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH

- 27645:

--> 0

- 27645:

--> 1

- 27646:

-—> 0

- 27646:

--> 1

- 27647:

--> 0

- 27647:

--> 1

n) be n: ta

[.1

121

[3455500 ns]
17
16

02
CLR

RS

OX7
CY?
027
CLK8MH
O7

00
ENX_
ENY
EN2_
R81
SWC
[3455500 ns]
[+0/0]
[3455562.5 ns]
[+0/0]
[3455625 ns]
[+0/O]
[3455687.5 ns]
[+0/01
[3455750 ns]
[+0/0]
[3455812.5 ns]
[+O/0]

0
O
lIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

H+4c>H+acwo<3c>cnaraH+AhIH+JhlwwahIHracwo<3c>H<3haowaracnac>owac>ow3haH

[01

[2688375]
[3072375]
[2048250]
[33281381
[3328122.21
[2368113.31
[2112113.31
[2240113.31
[2112125.61
[3392100]
[3328115.7]
[3328115.7]
[3328111.9]
[2816115.7]
[2816111.9]

[01
(0]
[0]
[0]

[3072145.11
[3454092.61
[3452091]
[3448089.7]

[125]
[125]
[17.7]
[17.7]

'[17.7]

13328150

(input)(disp1ay)
(input)(display)
(input1(disp1ay)
(input)(disp1ay)
(output)(disp1ay)

(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
[output)(display)
(output)(display)

(output)(disp1ay)

(output)(disp1ay)
(output)(display)
(output)(disp1ay)
(output)(display)
(output)(display)

(input)(disp1ay)
(input)(display)
(input)(display)
(input)(display)

(output)(disp1ay)
(output)(disp1ay)

(output)(disp1ay)

(output)(disp1ay1

(input)(display)
(input)(disp1ay)

(output)(display)
(output)(display)
(output)(display)
[3455437.
[3328149.
[3392122.
[3328149.
[3328150.
[3328150.
[3328150.
[3328150.

[3200104]
[3328104]
[3392107.1]
[3072151.5]
[3392098]

(clock)(disp1ay)

(output)[disp1ay)
(output1(display)
(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay1
(output)(display)
(output)(disp1ay)

(output)(disp1ay)
(output)(disp1ay)

(output)(disp1ay)
(output)(disp1ay)

(output)(disp1ay)

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
02 -->
01 -—>
co —->

SWC --> 0
CNTC --> 0
_ --> 1
A0 --> 1
Time = 27650:1

ENZ

CLK8MH
T2 —->
81 -->

R81 --> 0

T2 -->

RSI --> 1

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
16 -->
12 -->
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH

27648:1
--> 0
- 2764822
--> 1
a 27649:1
--> 0
- 27649:2
--> 1
0
0
0

[3455875
[+0/0]
[3455937
[+0/0]
[3456000
[+0/01 ‘
[3456062
[+0/0]
[+25.5/7.9]
[+26.7/9.1]
[+28.2/10.6]
[+33/15.4]
[+35.6/2.6]
[+41.5/7.7]
[+49.4/.5]
[3456125
[+0/01
[+2.5/1.91
[+3.1/19.31
[+9.5/71
[+20.1/2.1]
[+26.5/6.41
[3456187
[+O/01
[3456250
[+0/0]
[3456312
[+0/0]
[3456375

—-> 0
0
0

1

- 27650:2
--> 1

- 27651:1
-—> 0

- 27651:2
--> 1

- 27652:1
0 [+0/01

1 [+0/0]

--> 0 [+0/0]

- 27652:2 [3456437
--> 1 [+0/0]

- 27653:1 [3456500
—-> 0 1+0/O]

- 27653:2 [3456562
--> 1 [+0/O]

122

ns]
.5 ns]
ns]

.5 ns]

ns]

.5 ns]
ns]
.5 ns]

ns]

.5 ns]
ns]

.5 ns]

Time - 30717:1

Tbme
CLK8MH
Tinua
CLK8MH
Tin“:
CLK8MH
Tinue
CLK8MH
Time
CLK8MH
Tinme
CLK8MH

- 30717:

--> 0

- 30717:

--> 1

- 30718:

--> 0

- 30718:

--> 1

- 30719:

--> 0

- 30719:2

—-> 1

[3839500

L
L
L

C

CLK8MH

E
E
E

[3839500
[+0/0]
[3839562
[+0/0]
[3839625
[+0/01
[3839687
[+0/01
[3839750
[+0/0]
[3839812
[+0/O]

123

ns]
17
16
15
12
SO
81
EX_
EY_
EZ_
LE_
NTC
A0
A1
A2
A3
A4
14
13
11
10
T2
00
01
02
CLR
R8
OX7
0Y7
027

O7
06
05
O4
03
02
01
00
NX_
NY_
NZ_
R81
SWC
ns]

.5 ns]
ns]
.5 ns]
ns]

.5 ns]

HHOHHOOOOOOHHHHHHHHHHHHOOOOHOHHHHOHHHHOHOOH

[01

[3456375]
[3072375]
[3456375]
[3712138]
[3712122.
[3520112.
[3648112.
[3776112.
[2112125.
[3776100]
[3712111.
[3584111.
[3328111.
[2816115.
[2816111.

[0]
[01
[0]
[0]

[3456145.
[3838092.
[3836091]
[3832089.
(input)(disp1ay)
(input)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
[3839437.
[3712149.
[3712149.
[3776123.
[3712150.
[3712150.
[3712150.
[3712150.
[3712150.
[3584104]
[3712104]
[3776107.
[3456151.
[37760981

[125]
[125]
[17.7]
[17.7]
[17.7]

2]
1]
11
11
51

91
9]
91
71
9]

1]
61

71

11
5]

(input)(disp1ay)
(input)(display)
(input)(disp1ay)
(input)(display)
(output)(disp1ay)

(output)(display)
(output)(display)
(output)(display)
(output)(display)
(output)(disp1ay)

(output)(disp1ay)

(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
(output)(display1
(output)(disp1ay)

(input)(display)
(input)(display)
(input)(disp1ay)
(input)(disp1ay)

(output)(display)
(output)(display)

(output)(disp1ay)

(output)(disp1ay)

(clock)(disp1ay)

(output)(display)
(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
(output)(disp1ay)
(output)(display)
(output)[disp1ay)
(output)(disp1ay)

(output)(display)
(output)(disp1ay)

(output)(disp1ay)
(output)(disp1ay)

(output)(disp1ay)

Time
,CLKBMH

Time
CLK8MH

Time
CLK8MH

Time
CLK8MH
02 -->
01 -->
Q0 -->

SWC --> 0
CNTC --> 0
EN2_ --> 1

A3 -->
A1 -->
A2 -->
A0 -->

Time
CLK8MH
T2 -->
81 -->

R81 --> 0

T2 -->

R81 --> 1
LE_ --> 1

Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH
Time
CLK8MH

124

- 30720:1
--> 0
= 30720:2
--> 1
a 30721:1
--> 0

[3839875 ns]
[+0/0]
[3839937.5 ns]
[+0/0]
[3840000 ns]
[+0/0]
= 30721:2 [3840062.5 ns]
--> 1 [+0/0]
0 [+25.5/7.9]
0 [+26.7/9.1]
0 [+28.2/10.6]
[+33/15.4]
[+35.6/2.61
[+41.5/7.7]
1 [+49.4/.5]
0 [+53.2/.7]
0 [+53.2/.7]
0 [+53.2/.7]
- 30722:1 [3840125
--> 0 [+0/0]
0 [+2.5/1.9]
0 [+3.1/19.3]
[+9.5/7]
1 [+20.1/2.1]
[+26.5/6.4]
[+44.8/5.1]
[3840187.
[+0/0]
[3840250
[+0/0]
'[3840312.
[+0/0]
[3840375
(+0/0]
[3840437.
[+0/0]
[3840500
[+0/0]
[3840562.
(+0/0]

ns]

= 30722:2
--> 1
- 30723:1
--> 0
- 30723:2
--> 1
- 30724:1
--> 0
- 30724:2
--> 1
- 30725:1
--> 0
- 30725:2
--> 1

5 ns]
ns]
5 ns]
ns]
5 ns]
ns]

5 ns]

BIBLIOGRAPHY

BIBLIOGRAPHY

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128

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