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MICHIGAN STATE U IVERSITY LIBRARIES

ll Ill/l ll lllllllll/lllllllllllllll

3 1293 00908 5568

ll

 

 

 

 

 

 

 

 

This is to certify that the

thesis entitled

AN UPGRADED INTERFACE FOR
AN ICP-DIRECT READING SPECTROMEI'ER

presented by

Julie Anne Horner

has been accepted towards fulfillment
of the requirements for

W degree in _'Ss:ience_

W ./M

Major professor

Date 1991. 04 10

0-7639 MS U is an Afﬁrmative Action/Equal Opportunity Institution

 

 

l

 

lc

w—rv

LIBRARY

Michigan State

University

"'N

 

J

PLACE IN RETURN BOX to remove this checkout from your record.

TO AVOID FINES return on or before date due.

 

 

DATE DUE DATE DUE DATE DUE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSU Is An Afﬁrmative Action/Equal Opportunity Institution

cMVcMMS-o.‘

 

AN UPGRADED INTERFACE FOR
AN ICP-DIRECT READING SPECTROMETER

BY

Julie Anne Homer

A THESIS

Submitted to
Michigan State University
in partial fulﬁllment of the requirements
for the degree of

MASTER OF SCIENCE

Department of Chemistry

1991

ABSTRACT

The computer interface for a Jarrell Ash AtomComp 750 direct reading
spectrometer has been upgraded. The original interface involved integration of the
photocurrent followed by an analog to digital conversion of the resulting voltage.
This system was controlled by 21 DEC PDP8/M minicomputer. The upgraded
interface involves amplification of the photocurrent using a current to voltage
converter and conversion of this voltage to a frequency. The frequency is then
counted by a counter/timer board mounted in an IBM PC/AT clone. Four
channels of data can be collected simultaneously by the upgraded system. Results

obtained with the new instrument are presented.

ACKNOWLEDGEMENTS

This thesis cannot be said to be the accomplishment of a single person.
Thanks go ﬁrst to Stan for giving me the opportunity (and the funds) to realize this
goal; to LEB for help with every aspect of the project itself and about 137 late night
coffees; to Pete for inspiring and uplifting telephone conversations on Saturday
evenings; to JR, BQ, Kris and Steve for sharing many lunch hours; to Tree-sir for
more moral suuport than I deserved; to my family (mon Pere, the Lizard, Lolly Pop,
Wes, Kiwi and Rye) for keeping me sane during my eighteen months at MSU; and
ﬁnally my thanks go to Dr. Adrian Wade and his clan for generously allowing me to

complete this thesis in their lab at UBC.

II

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TABLE or CONTENTS
LIST OF FIGURES ......................................................................................................................... v
LIsr OF TABLES ........................................................................... - -- - VII
Chapter 1.
INrRooucrION.
1.1 Deve10pment of the ICP ............... - - _- -- - - - - --1
1.2 History of ICP Measurement systems ...................... - -- -- 3
1.3 Objectives ............................ . .................................................................................. 7
Chapter 2.
ORIGINAL SYSTEM.
2.1 ICP-Direct Reader ............. - -- - _ - . _ 9
2.21CP Unit__-__-. ___________ _ - _- -_ - -- - - -_ 11
2.2.1 Inductively Coupled Plasma__--_ -_ - 11
2.2.2 Sample Introduction ...... _ 11
2.3 Detection System and Optics ..... 13
2.3.1 Imaging optics ........................ - ....... 13
2.3.2 Polychromator _- ..................................................... 13
2.3.3 Slit Assemblies .................................................................................... 15
2.3.4 Photomultiplier Tubes"; .................................................................... 15
2.3.5 PMT Housings ........................... __ - - - 17
2.4 Data Processing System... - - - - -- - - - - 17
2.4.1 Channel Module Boards ....... - - - 17
2.4.2 PDP/8m Minicomputer ...... - - 21
2.4.3 Additional Features....................... _ _ _-24

 

2.5 Summary ......................................................... _ - - _- -_ - ..... 26

 

III

Chapter 3.

UPGRADED SYSTEM.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.1 Desired Features - -_ 28
3.2 Design Approaches ....... 29
3.2.1 Evaluation of Options __ ..... - 29
3.2.2 Comparison Of Options................- ...... 31
3.2.3 Conclusions ........ - - _ 34
3.3 Previous Approaches- - - - - - _- 35
3.4 Description of Upgraded System -- - _ _ - - 36
3.4.1 Current to voltage Conversion- -- - 36
3.4.2 Voltage to Frequency Conversion -- - _ _- 37
3.4.3 Channel Module Boards--- __ -- - 42
3.4.4 Channel Module Motherboard ___________ - - - ..... 43
3.4.5 Metrabyte Counter/Timer Module _______ -- -- - - 43
3.4.6 Software ............................................. - -- -- - - 59
Chapter 4.
RESULTS AND DISCUSSION.
4.1 Experimental .......... - __ -_ 69
4.1.1 Instrumentation .................................................................................. 69
4.1.2 Parameters . - - -- -70
4.1.3 Solutions .............................................................................................. 70
4.2 Results ................. -- -71
4.3 Discussion ........................................................................................................... 78
4.3.1 Analytical Figures of Merit ............. 78

 

4.3.2 SMEA .................................................................................................. 79

IV

Chapter 5.

CONCLUSIONS AND FUTURE WORK.

 

 

 

 

 

 

 

5.1 Conclusrons - - - -81

5.2 Future Work - ..... . ............... 31

5.2.1 Switchable Gain ................................................................................. 81

5.2.2 Expansion to More Channels ..... - 82

5.2.3 Independent Gating ....................... 82

5.2.4 Channel Resolution ..................... - - - - 86

5.2.5 Software Improvements.......-. ........ - -- 86
APPENDIXI - 92

 

IV

Chapter 5.

CONCLUSIONS AND FUTURE WORK.

 

 

 

 

 

5.1 Conclusions ......................................................................................................... 81
5.2 Future Work - - __ - -- - - - 81
5.2.1 Switchable Gain ................................................................................. 81
5.2.2 Expansion to More Channels.......- - 82
5.2.3 Independent Gating 82
5.2.4 Channel Resolution ..................... -- - 86
5.2.5 Software Improvements.. - ...... 86

 

APPENDIX I ................................ - - 92

V

 

LIST OF FIGURES
Page Caption

Fig. 1 4 Block diagram Of a typical ICP emission system.

Fig.2 6 Optical configuration of a Paschen-Runge direct reading
spectrometer.

Fig.3 10 Diagram Of the ICP Direct Reader as received from the
N ational Aeronautics and Space Association.

Fig. 4 12 Diagram of the ICP sample introduction system.

Fig. 5 14 Plasma imaging optics.

Fig. 6 16 Ray trace through refractor plate and slit assembly.

Fig. 7 18 Cross section of a direct mount slit assembly with
photomultiplier tube.

Fig. 8 19 Cross section of an overhead mount Slit assembly with
photomultiplier tube.

Fig.9 20 Circuit diagram of the channel module board as recieved from
the National Aeronautics and Space Association.

Fig. 10 26 Diagram of the wobulator: Method of background correction
use with the J arrell Ash Atomcomp 750.

Fig. 11 30 Outline of Options for the photomultiplier tube interface.

Fig. 12 37 Circuit diagram of the current-tO-voltage converter

Fig. 13 39 Schematic diagram Of the Analog Devices 65230 Synchronous
voltage-to-frequency converter

Fig. 14 45 General block diagram of the Advanced Microdevices 9513
Counter Timer.

Fig. 15 46 Pin out of the Advanced Microdevices 9513 Counter Timer.

Fig. 16 47 Communication within the Advanced Microdevices 9513
Counter Timer.

Fig. 17 51 a) Counter logic groups 1 and 2.
b) Counter logic groups 3, 4 and 5.

Fig. 18 55 Master Mode Register bit assignments.

 

Page; Caption
Fig. 19 77 a) Calcium Calibration Curve
b) Cadmium Calibration Curve
c) Nickel Calibration Curve
(1) Magnesium Calibration Curve
Fig. 20 83 Diagram Of a switchable gain Current to Voltage converter.
Fig. 21 84 Diagram of a four-fold expansion Of the direct reader interface
using 4 to 1 multiplexers.
Fig. 22 85 Expansion of the direct reader interface using four Advanced
Microdevices 9513 Counter Timers.
Fig. 23 87 Independently gated, Five channel interface for the direct

reader using two Advanced Microdevices 9513 Counter
Timers.

VII

 

LIST OF TABLES
Page Title

Table 1 2 Characteristics Of the Inductively Coupled Plasma.
Table 2 22 Functions Of Integrator-Controlling Field Effect Transistors.
Table 3 26 Functions of Power Relays.
Table 4 48 Counter Group and Element Fields.
Table 5 49 Element Fieldsfor Control Group.
Table 6 52 Counter Mode Options.
Table 7 60 Master Mode Register Bit Assignments.
Table 8 63 Counter 1 Mode Register Bit Assignments.
Table 9 64 Counters 2-5 Mode Register Bit Assignments.
Table 10 7O Instrument Parameters.
Table 11 71 Experimental Conditions for Determinations of Various

Sources of Noise and Background.
Table 12 71 Typical Values of Various Sources of Noise and Background.
Table 13 72 Typical Counts for Initial Four Elements.
Table 14 74 Background Intensities.

Chapter 1

INTRODUCTION
1.1 Development of the ICP

The introduction of the inductively coupled plasma (ICP) as an excitation
source for spectrochemical analysis revolutionized Optical emission spectroscopy.
Following the description of an ICP by Reed12 in 1961, two independent groups of
spectroscopists began research in the area. Their Objective was to modify the ICP
such that it would be suitable for optical emission spectroscopy (OES). Greenﬁeld3
et al in 1964 and Fassel and Wendt“ in 1965 published results Obtained with the ﬁrst
ICP-OES systems. Although their instruments were quite different and neither was
Optimized, their results were competitive with those Obtained using the more
established ﬂame methods. In a critical paper, Fassel er al’ describe an ICP-OBS
system incorporating impedance matching Of the plasma and power supply. They
found that this improved detection limits over those previously Obtained with ICPS
and. over those Obtained using flame atomic emission (ABS) or ﬂame atomic
absorption (AAS). This particular work gave credence to predictions that the ICP

would become a primary source for atomic emission spectroscopy.

Up until this time, the most widely used methods for spectroscopic analysis of
solutions were ﬂame ABS and AAS. In their favour, ﬂame ABS and AAS are
instrumentally relatively simple techniques which can be implemented at low cost.
The ﬂame, however, has several inherent disadvantages with respect to its use as an
excitation source for AES. Flames typically display high background levels, poor
sensitivity, narrow linear dynamic range and high susceptibility to chemical and

spectral interferences. Flame ABS in particular has a limited number of elements

1

to which it may be applied because the ﬂame does not provide enough
thermal energy to excite many elements. Flame AAS compensates for some of
these disadvantages since an external excitation source is used, but a hollow cathode

lamp for the element of interest must be available.

The ICP suffers to a much lesser extent from these inherent disadvantages
and is nearer to an ideal atomization and excitation source. Table 1 lists some of
the ICP’s characteristicsé. The higher temperature of the plasma alleviates many of
the disadvantages typical Of ﬂames. The plasma’s higher temperatures and near
inert environment make it relatively free of chemical interferences resulting from
the formation of molecular species or refractory compounds. A higher temperature
also increases the number Of elements that can be successfully determined using

ICP-OBS and improves detection limits since more Of the analyte is atomized.

Table I: Characteristics of the Inductively
Coupled Plasma

High temperature

Long residence times

High electron number densities

Free atoms formed in nearly inert environment
Molecular species absent or present at very low levels
Optically thin

NO electrodes

NO explosive gases

P3999959!“

Low background emission in the analytical Observation zone and the optical
thinness Of the plasma give it a wide linear dynamic range. Freedom from many
chemical interferences and its ability to excite most samples make the ICP well
suited to simultaneous multielement analysis (SMEA). SMEA would be feasible for

ﬂame ABS if more elements could be excited at ﬂame temperatures, but it is not

feasible for ﬂame AAS in part because of geometric restrictions and the loss of
sensitivity accompanying the use of multielement hollow cathode lamps. In an
overall comparison of analytical ﬁgures of merit, the plasma is certainly superior to

ﬂames for atomic spectroscopy.

The ICP also offers some advantages over other plasma sources. As
discussed in an extensive review by Greenﬁeld er aﬂv3'9, the ICP, in the majority of
cases, gives better detection limits and has higher sensitivity than both dc plasma
jets and microwave plasma torches. For many analytes, the limit of detection is
some two to three orders Of magnitude lower with the ICP than with other plasma
sources examined. To a lesser extent, the ICP also gives higher precision than the
other plasma sources. Boumansw'11 evaluated the ICP, high temperature ﬂames,
current free and current carrying DC plasmas and microvvave plasmas for their
applicability to simultaneous multielement analysis. Boumans concluded, based on
his criteria, that the ICP gave the best analytical performance of the excitation.

sources examined.
1.2 History of ICP Measurement Systems

When the ﬁrst ICP-OBS systems were developed, they were generally
applied to single element or sequential multielement analyses. The typical
detection system consisted of a monochromator, spectrometer or spectrograph,
phototransducer, ampliﬁer and readout device. Certainly one of the more popular
early systems incorporates a scanning monochromator and a photomultiplier tube
(PMT). This provides the high resolution spectral information obtainable from
monochrOmators with the high sensitivity of a PMT. A block diagram of such a
system is given in Fig. 1. One disadvantage is that the time required for acquisition

of a single spectrum is Often on the order of tens of minutes.

 

 

 

 

ICP

PHOTO

 

TRANSDUCER

 

 

 

 

 

 

 

 

Figure 1: Block diagram of a typical ICP emission system.

 

‘--—-MONOCHROMATOR --

'READOUT

 

 

 

The approach described above was taken by Barnett er al12 for ICP-AAS,
Scott et (1113,1445 and Kirkbright et (11164743 for ICP-OBS analysis of real samples
including rock, soil and plants. Boumans et all”)21 describe an interesting dual
channel-dual monochromator system. A commercial ICP-OBS system based on an
instrument developed by Boumans and de Boer employs a 1.5 m concave grating
spectrometer and a roving slit assembly that enables measurement of any spectral
line within the wavelength range of the instrument. As indicated above, a large
number of early detection systems for ICPs have involved a scanning
monochromator and single photomultiplier tube. This approach has the advantage
Of providing spectral information and ﬂexibility of line choice, but, because it
involves some means of scanning, it is also time intensive and consumes much

sample.

It was quickly recognised that ICP-OBS was fundamentally well suited to
simultaneous multielement analysis. An initial study by Boumans and de Boer22
revealed that conditions for SMEA favoring few interferences were the same
conditions that gave relatively good detection limits for most analytes. By the mid
19705 many researchers were taking advantage of this capability of the ICP by using
polychromators or spectrometers with multiple ﬁxed exit slits and detectors. An
Optical diagram of a polychromator is shown in Fig. 2. These systems in most cases
could accommodate more than twenty channels. Greenﬁeld et at”, since the early
19705, have used a thirty channel polychromator. Watson et a!“ used a 3.4 m Ebert
spectrograph and 24 channel spectrometer. The popularity of multichannel systems
extended to instrument manufacturers and by the late 19705 several companies
offered ICP detectors capable of determining as many as 64 elements
simultaneously. Among these is the 50 channel Jarrell Ash AtomComp 750. In

contrast to monochromator based systems, the polychromator or direct reading

Concave Grating

\V

 

Exit
Slit
Entrance Photomultiplier
sm 0 tube

 

 

 

 

To detection electronics

Figure 2: Optical configuration of a Paschen-Runge type direct reading
Spectrometer.

instrument gives only intensity information at a ﬁxed set of wavelengths within a
speciﬁed range. This range, however, is typically greater than 300 nm.
Furthermore, polychromator systems take less time than monochromator systems
for analysis Of a ﬁxed number of analytes (greater than one) and, hence, generally

consume less sample.

A compromise between the two detection systems discussed above is the
photodiode array (PDA). A number of researchers have chosen this detector in the
recent past for a variety of applications of the ICP753637. The FDA in conjunction
with a mono- or polychromator can provide spectral information in a very small
amount of time. The disadvantages associated with the PDA may, however, make it
inappropriate for some applications. The wavelength range available at one time is
reduced relative to the polychromator/ﬁxed detector system. Furthermore, the
PDA is less sensitive than a PMT. The problem of sensitivity has been somewhat
alleviated by the development of intensiﬁed diode arrays, but the restricted
wavelength range remains an inconvenience if the ICP system is to be used for

SMEA.

In the very recent past, the ICP has been introduced to a new detection
system - charge coupled and charge injection devicesm". As yet, this innovative and
promising measurement technique is used primarily in the research environment.
Charge coupled and charge injection devices are more sensitive than diode arrays

and have higher resolution but are still relatively expensive.

Evaluation of all options for detection systems for ICPs indicates that some
are fundamentally better suited to SMEA than others. The photodiode array has
many desirable features but lacks the breadth of wavelength range necessary for

SMEA. The CCD and CID may in time become more popular for this type of work

but at present are out of the price range of many potential users. Thus, for many

analytical applications the direct reader remains the most viable option.
1.3 Objective

The goal of this work was to modernize the computer interface for the
ICP/polychromator system. The ICP unit is the PlasmaTherm ICP 2500 with a
radio frequency generator and AMNS Automatic Matching Network. The direct
reader is an automated Fisher Jarrell Ash AtomComp 750 (equipped with up to 50
PMTs) interfaced to a Digital Equipment Corporation PDP8/M minicomputer.
This original system is described in Chapter 2. The intent is to re-interface the
polychromator to a IBM PC, XT, or AT clone. Various approaches will be
proposed and evaluated. The upgraded system is detailed in Chapter 3. Results
that have been obtained with the revised system are presented and discussed in
Chapter 4. Conclusions and possible methods for improving the revised system are

given in Chapter 5.

Chapter 2

ORIGINAL SYSTEM

This chapter gives a description of the ICP/Direct reader system as it was
received from NASA. A brief description of the instrument as a whole is given in
the ﬁrst section. The Jarrell Ash Direct Reader can be divided into three
subsystems, each performing a unique function. The second section of this chapter
describes the excitation source; the inductively coupled plasma. Section three deals
with the detection system and Optics; the PMTs and polychromator. The ﬁnal
section is devoted to the data acquisition and control system consisting of the

channel modules and PDP8/ M minicomputer.
2.1 The ICP Direct Reader

The ICP direct reader system as received from NASA consisted of the
following components: the PlasmaTherm 2500 ICP unit (PlasmaTherm, Kresson
NJ) with 27.12 MHz radio frequency generator (PlasmaTherm, Kresson NJ) and
AMNS automatic matching network (PlasmaTherm, Kresson NJ); imaging optics,
AtomComp 750 polychromator (Fisher Jarrell Ash, Waltham, MA) with PMTs and
sockets (Hamamatsu, Bridgewater, NJ), Model 1307A High Voltage. power supply
(Bertan, Syosset, NY) channel module boards and module motherboard (Fisher
Jarrell Ash, Waltham, MA), PDP8/ M minicomputer (Digital Equipment
Corporation), background correcter (wobulator) and controller. A diagram of the
instrument is given in Fig. 3. Each component is described in further detail in the

proceeding sections”.

10

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11

2.2 ICP unit
2.2.1 Inductively Coupled Plasma.

The plasma unit itself is composed of a sample introduction system
(consisting Of a concentric glass nebulizer and spray chamber), the torch assembly,
Tesla coil and load coil. A diagram of the sample introduction system and torch

assembly is given in Fig. 4.

The plasma is ignited by a quick discharge of the Tesla coil across a gap at
the base of the torch. The discharge provides the seed Argon ions and electrons
required for generating the plasma. The seeded plasma is maintained by supply of
alternating current (27.12 MHz) through the load coil at roughly 1 kW of power.
RF power is coupled to the plasma via argon ions and electrons. Two features of
modern instruments give rise to a stable plasma. The ﬁrst is an automatic matching
network which continually matches the output impedance of the RF generator to
the impedance of the plasma and load coil. The second stabilizing feature is a
continuous ﬂow of coolant gas introduced tangentially between the plasma tube and
the outer barrel of the torch. The torch is thus kept at a much lower temperature

than the plasma.
2.2.2 Sample Introduction.

Samples are introduced into the plasma in solution form through a
concentric nebulizer (Precision Glassblowing, Denver, CO) at a rate between 2 and
3 mL/min. The sample is aspirated from the spray chamber up through the
innermost tube of the torch (Precision Glassblowing, Denver, C0). As the
nebulizer gas ﬂow rate is increased, a hole is formed in the centre of the plasma so

that the plasma takes on a torroidal shape. The formation of this hole allows

12

 

 

 

 

 

 

 

 

 

 

 

 

RF
TORCH
ASSEMBLY
L—
ZR A
r
\ F_K
H
CONCENTRIC 2
NEBUUSER
Sample .
SPRAY CHAMBER 1

Ar

Figure 4: Diagram of the ICP sample introduction system

13

sample to reach the core of the discharge. This increases both the atomization

efﬁciency and the residence time of atoms and ions in the plasma.
2.3 Detection System and Optics
2.3.1 Imaging Optics.

Two optical elements are used to focus a 1:1 image of the plasma onto the
entrance slit of the polychromator. This is shown diagrammatically in Fig. 5. Focal
lengths and relevant distances are given in the diagram. The Optical elements are

mounted in a cabinet which formerly housed a spark source.
2.3.2 Polychromator.

The image of the plasma is centred on a 25 um x 2 cm bayonet type entrance
slit. The entrance can be accurately translated using a micrometer so that Optimal
alignment of the spectrum onto the exit slits can be obtained. Radiation passing
through the slit travels down a light pipe onto a 0.75 m focal length concave
holographic grating (1509 grooves / mm). The grating is mounted on a rigid cast iron
stand but can be adjusted in both vertical and horizontal directions and can be
rotated with respect to the focal curve of the polychromator if necessary. The

position of the grating is optimized at the factory”.

Dispersed radiation is passed through a mask before reaching the exit slits on
the focal curve. The focal curve has positions for 70 exit slit assemblies, up to ﬁfty
of which can be occupied at any one time. Each assembly is composed of a slit body
that serves as a mount for the exit slit and refractor plate, as well as alignment pins,

hold down screw and clamp, the refractor plate, the exit slit, PMT socket and PMT.

14

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2.3.3 Slit Assemblies.

Exit slits are available in three widths: 10, 35 and 50pm. The 50 um slit is
used for typical applications. The slit can be mounted in a right hand or left hand
fashion and will have one of four radii of curvature depending on its position along

the focal curve.

A refractor plate, mounted in front of each exit slit, allows ﬁne adjustment of
the wavelength passing through the exit slit. This procedure30 is diagrammed in
Fig. 6. The refractor plate is constructed either of quartz, corex or glass which is 1
or 3 mm thick. Plates that are one millimetre thick allow a 0.2 nm variation of ﬁrst
order radiation on either side Of the centre wavelength of the exit slit. Three
millimetre plates allow a 1.0 nm sweep on either side of thecentre wavelength. The
refractor plate also reduces other order stray radiation for a given region of the

spectrum.
2.3.4 Photomultiplier Tubes.

Three types of PMTs are available for use in various regions of the spectrum.
All are side on mount Hamamatsu (Bridgewater, NJ) photomultiplier tubes which
are most sensitive either to red, visible or ultraviolet radiation. The R427 has a
useful wavelength range between 160 and 320 nm with a maximum response at 200
nm; its window is quartz and the photocathode material is Cs-Te. The R300 has a
useful wavelength range between 185 and 650 nm and has its maximum response at
340 nm. The photocathode for this PMT is Sb-Cs and its window is constructed of
UV glass. The R889 is used between 185 and 850 nm with a maximum response at
530 nm. Its photocathode is a multialkali material; its window is also UV glass. All

are low dark current models which can produce photocurrents of up to 10 pA.

16

 

 

 

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i 5")

 

 

 

Focal Refractor Exit

PMT
Curve Plate Slit

 

is, selected by the refractor plate

Figure 6: Ray trace through refractor plate and slit assembly.

l7

PMT sockets are constructed with a total dynode chain resistance of about 10
Mn , (about 1 Mn between each pair of dynodes). The sockets and PMTs are
mounted by the manufacturer. Each socket is connected to a power distribution or
’mother’ board which supplies a maximum of 950 V. All channels are tested at this
voltage. If the count rate is too high, resistors are inserted in the J board for the

individual channel to reduce the total PMT gain.

2.3.5 PMT Housings.

The photomultiplier tubes and sockets can be mounted in one of two types of
housings. The ﬁrst holds the PMT in an upright position about 5 cm directly behind
the exit slit. A diagram of this housing is shown in Fig. 730. When space constraints
prevent this for a particular channel, an overhead mount is used. In this case the
PMT is held perpendicular to the plane of the exit slit as shown in Fig. 83°. A mirror
mounted at a 45° angle with respect to the PMT and exit slit is used to direct
radiation to the photocathode. In both cases a reﬂective sleeve ﬁts around the PMT
which extends to the exit slit. This increases the amount of radiation at the centre

wavelength and reduces the amount of stray radiation reaching the photocathode.
2.4 Data Processing System
2.4.1 Channel Module Boards.

The channel module board performs integration of the photocurrent and
decodes I/O instructions from the CPU. Each channel module is speciﬁc for a
single element. The PMT is connected to its channel module board by a removable
anode clip attached to an insulated solid wire ﬁxed to the board. The photocurrent
from the PMT passes along the lead directly to an operational ampliﬁer conﬁgured
as an integrating charge to voltage converter. A simpliﬁed circuit diagram is shown

in Fig. 930. The capacitance in the feedback loop is selected for the channel

PMT Anode
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Figure 7: Cross section of a direct mount slit assembly with photomultiplier

19

 

 

 

 

 

 

 

 

 

 

 
    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Figure 8: Cross section of an overhead photomultiplier tube holder

20

Cint zero

 

Cint = (9.1 ITIF

@ \ ADC connect
/——> ADC

 

 

 

 

 

 

Figure 9: Simplified circuit diagram of the channel module
as supplied by NASA.

21

(element) based on the relative intensity of its spectral line. This is typically 0.1 uF,

but, for unusually weak lines, is 0.01 p F.

The operational ampliﬁer is switched between integrate and zero modes by a
ﬁeld effect transistor (FET 2). In the Zero Mode, the capacitor is shorted and the
operational ampliﬁer output is converted to the input (summing point). When the
FET switch opens, the capacitor is allowed to charge and the integrator is in

Integrate Mode.
2.4.2 The PDP8/M Minicomputer.

Each channel module occupies one edge connector on the channel control
board. The minicomputer communicates with the channel via this edge connector.
Both control functions, (e.g. switch the capacitor from integrate mode to zero
mode); and data acquisition functions, (e.g. send the output voltage from the
integrator to the analog to digital converter (ADC)); are carried out through this

edge connector. These functions are described in more detail below.

The central processing unit of the PDP8 / M performs four main functions for

the channel modules through the channel control board. These are listed below.

1. The CPU addresses and instructs any one of the 50 channel modules with one of
the following commands:
a.) Connect the integrating capacitor to the ADC.
b.) Disconnect the capacitor from the ADC.

c.) Zero the integrating ca acitor by shortin it, which connects the
operational ampliﬁer tot e inverting input summing point).

(1.) Clear the capacitor’s ground connection for integrate mode.

22

‘ 2. Requests the analog to digital conversion and transfer the count to the

accumulator.
3. Transfer the contents of the accumulator to memory.

4. Select low or high gain mode for the analog to digital conversion. This allows
two modes of acquisition:
a.) Integrate using the integrating capacitor or

b.) Proﬁle by reading instantaneous intensities.

All user [/0 is expressed in octal numbers and all operations of the

computer can be synchronized to a real timeclock.
Control of the Integrator:

The PMT is physically connected at all times to the integrating capacitor.
Two ﬁeld effect transistors control the status of the integrator and connection of the
operational ampliﬁer output to the analog to digital converter. The speciﬁc

functions of each FET are given in Table 2 along with the octal codes which request

 

 

the function.
Table II: Functions of Integrator-Controlling
Field Effect Transistors
Octal
FET 1 Code Stamgﬂmegrator
open 2023 Clear mode: A 100 la) resistor is placed across the ter-
minals of the integratin capacitor. Ci... will build up
a voltage as a result of t e photocurrent.
closed 2013 Zero mode: Ci... is shorted through a few hundred

05 to the summing point of the Operational ampliﬁer.

 

~ Octal

FET 2 Code ADC Status

open 0023 Disconnect: The ADC is not connected to the output
of the integrator.

closed 0013 Connect: Integrator output is connected to the ADC.

Control commands can be issued by the current program or typed directly
into the teletype. These are three or four digit octal codes. Instructions are
transferred to the decoders by 1/0 instruction 61643. The capacitor is connected to
the ADC directly if 4013 is speciﬁed or through a 300 fold ampliﬁer if 4023 is
speciﬁed. The analog to digital conversion is initiated by I/O instruction 61613.

The count is loaded into memory when the CPU receives I/O instruction 61623.
Integration Mode.

An example of the interrogation of channel one is given below. The
procedure includes connecting channel one to the ADC, performing a conversion,
transferring the count to the accumulator, and determining whether or not to zero

the integrator. This cycle repeats every 16.67 ms.

1. A 61643 I/O instruction followed by the channel select code 0013 are sent to

connect channel one to the ADC. This closes FET 2.

2. A 61613 [/0 instruction is sent which requests that an analog to digital

conversion be performed.

3. The count is compared to 37773.
a.) If the count is less than 37773, a 0023 is sent to disconnect channel one
from the ADC. This opens FET 2, allowing the capacitor to continue

integrating.

24

b.) If the count is greater than 37773, the CPU transfers the count to the
accumulator and then to memory with a 616231/0 instruction. A 0023
signal is sent disconnecting channel one from the ADC. The
integrating capacitor is then zeroed by sending 2013 and cleared for

integration by sending 2023 to FET 1.

Once the counts for all channels of interest have been stored in memory, they
are available for readout as absolute intensities, relative intensities with or without

background correction and can be converted into concentrations.

This implies that computer data acquisition is not initiated simultaneously for

all channels; but all channels can be acquiring data within 16.67 ms.
Proﬁling Mode.

A channel that is being proﬁled can be monitored on a real time basis at a
current meter mounted on the front left side of the cabinet below the
polychromator. The analog voltage at the output of the operational ampliﬁer is
converted to a digital signal and then sent to a digital-to-analog converter (DAC)

and ﬁnally displayed on the microammeter.
2.4.3 Additional Features.
Background Correction.

Background correction can be achieved by a computer controlled rotatable
refractor plate system, called a wobulator mounted in the bottom left corner of the
cabinet below the polychromator . A quartz refractor plate is mounted on a
rotatable stage between the entrance slit and the grating. When the angle between

the plate and the entrance slit is varied, the spectrum is shifted with respect to the

25

exit slits such that the spectral lines are not centred on the slits. The intensity
measured by the PMT is then background intensity. This automated background

correction procedure is shown in Fig. 10.
Slave Relays.

Also mounted behind the ammeter in the top left comer Of the cabinet below
the polychromator is a slave relay board. This houses a set of six power relays
whose functions are described in Table 3. The power relays are operated by reed
relays on the G board. All relays in the system were intended for the control and
actuation of a spark source which was mounted in the space now occupied by the
collection optics. A +12 V power supply is included to power the relays. This is

intended for use with the spark source originally accompanying the polychromator.

Table III: Functions of Power Relays

 

REEL Function
1 Fatigue lamp relay: Turns fatigue lamp on at the end of the exposure,
turns lamp Off on request.
2 Unused: Turns on an optional accessory with 1133, off with 1143.
3 Exposure relay: Turns on power to the source unit and to the EXP

par.:l light during the eprsure and preburn cycles. Computer
software determines the duration of the preburn cycle.

4 Blank relay socket: Turns on a second Optional accessory with 1113,
off with 1123.
5 Standby rela : Turns on the SB panel light when the source is turned

Off. Turns S off when source is on.

6 Flush relay: Opens the solenoid of the gas system mounted beside the
microammeter in the upper left corner of the cabinet on user request.
This relay is actuated by the controlling computer after relay 3.

 

Grating

Rotation
angle

To grating

 

To focal
curve

Rotation by
anglefI (l\
\l \

Refractor Entrance
Plate Slit

 

 

 

 

 

 

~. 1 liefractor plate

 

 

 

2
ight from

entrance slit

Figure 10: Diagram of the wobulator: method of background correction
used with the Jarrell Ash Atomcomp 750.

27

2.5 Summary

The original data acquisition and control system, including the integrators
and the DEC PDP8/ M, has several advantages. Most importantly, it was
constructed to accommodate up to 50 channels. Furthermore, the system provides
options such as automated background correction, some data manipulation, and
control of the excitation procedure if the spark source is used. The original system

has virtually full automation of control of the instrument and data acquisition.

The data acquisition and control system also has some disadvantages. Most
obviously it is outdated. The advances made in both digital and analog electronics
over the past ﬁfteen years warrant updating the instrument. For example, the
operational ampliﬁers used as integrators could be replaced with the more stable,
lower bias current models available today. The PDP8/M minicomputer could be
replaced by a faster, higher capability IBM compatible (or Maclntosh type)
microcomputer. The DEC PDP8/ M has only 64K of random access memory and
uses paper tape drives for long term storage. The user interface consists of a
teletype or paper tape reader. Instructions must be given in the form of octal
number sequences or primitive basic code. Data presentation facilities are minimal.
Today’s computers are faster, smaller and have more capabilities than the PDP8/ M.
Thus, an upgraded interface would greatly enhance the viability of the ICP/direct

reader system as a research quality instrument.

Chapter 3

UPGRADED SYSTEM

As discussed in the introduction, it was the goal of this work to design and
construct an interface for the ICP polychromator system described in chapter 2. In
the ﬁrst section of this chapter the desired features of the upgraded system are
outlined. Two design approaches are evaluated in the second section. The third
section discusses the modifications made to the original instrument. A detailed

description Of the upgraded system is presented in the ﬁnal section of this chapter.
3.1 Desired Features

The most obvious requirement for the upgraded system is replacement of the
PDP8/ M minicomputer by an IBM compatible microcomputer. This will increase

the speed and performance of the system and also improve its user interface.

Another important feature of the upgraded system is the capability for
simultaneous multielement analysis. The original system allows simultaneous
measurement of up to 50 channels. These are gated independently, however, so that
a channel begins and ends integration in a sequential fashion. This allows unique
integration times (i.e. variable gain) for all channels. It might be more convenient
to have all channels gated by the same signal and provide some other means of gain
selection. Finally, the upgraded interface should give detection limits, signal to

noise ratios and sensitivities competitive with state-of-the-art systems.

3.2 Design Approaches
There are two unique options for the design of a system with the

characteristics discussed above. These are techniques involving integration of

29

analog signals or those involving integration of digital signals. In this section these

two options will be presented and compared.
3.2.1 Evaluation of Options
Analog Integration.

A block diagram of an interface based on analog integration is given in
Fig. 11a. Like the present system, this Option involves integrating the current from
the photomultiplier tube using an operational ampliﬁer with a capacitor as its
feedback element. Inherent in this option is the necessity to address each channel
module individually (for integrator SET and RESET) which requires decoding logic.
For this option, the simplest approach would be to replace the outdated components
on the existing boards with new ones and to use a PC/XT or PC/AT clone equipped
with an ADC board for data acquisition. This would provide four or ﬁve

independent channels.
Digital Integration.

A block diagram of an interface based on digital integration is given in
Fig. 11b. In this option, the photocurrent is ﬁrst converted to a voltage using an
operational ampliﬁer equipped with an appropriate feedback resistor. The voltage
is then converted to a frequency using a single, commercially available voltage to
frequency converter (VFC). This performs an analog to time domain conversion.
The ﬁnal step would be to count the frequency using a counter/timer chip which
completes the analog to digital conversion process. This option involves essentially
reconstructing the majority of the existing system rather than replacing key

components.

 

 

PMT

 

 

 

 

 

INTEGRATOR

 

 

 

 

ATOD

 

 

 

0) Option 1: Integration of charge

 

 

PMT

 

 

 

 

 

 

 

I TO v L—{ v T0 r |—— COUNTER

 

 

 

 

 

b) Option 2: Integration of frequency

Figure 11: Outline of options for PMT interface

31

3.2.2 Comparison of Options.

In order to determine which of the two methods is the more appropriate,
they were compared based on construction time, cost, and analytical ﬁgures of

merit.
Time.

The ﬁrst option maintains much of the existing system as it is. The integrator
boards would be modiﬁed and the computer replaced. The second option requires
full reconstruction of the channel modules as well as replacement of the computer
system. Furthermore, software already exists for data acquisition with two ADC
boards; the Analog Devices RT'I/850 and the IBM data acquisition and control
adapter. A counter/ timer chip has been used in the laboratory but for applications
other than the one of interest. On the basis of time required for construction, then,

the ﬁrst option seems more attractive.
Cost.

Again, the ﬁrst option requires only the purchase of replacement
components for the channel module integrator boards, whereas the second option
would require supplies for their complete reconstruction. However, the cost of an
ADC board when compared to the cost of a counter/ timer greatly favors the second
option. This has become true only in the recent past with the lack of availability of
the IBM data acquisition and control adapter. A second option, Analog Devices’
RT'I/850, is priced at 11003 versus 325$ for the Metrabyte Counter/Timer Module.

When considering cost, the second option appears to be more favorable.

32
Analytical Figures of Merit.

This is perhaps the most important basis for comparison of the two methods.
Several analytical ﬁgures of merit will be discussed which are relevant to the choice

of the better method for modernizing the polychromator interface.
Resolution

Since both results would be 16 bits, technically neither method gives an
advantage over the other with respect to resolution. The second option, however,

could accomodate a 32 bit result.

The ﬁrst Option has a variable integration time in the sense that the
integrator can be set and cleared as many times as the user wishes up to a total time
of 10 seconds. For uninterrupted integration, the time is ﬁxed by the capacitance
value and the magnitude of the signal. One advantage of this method is that each
channel’s integrator can be set and cleared an independent number of times so that

the total integration time could be different for each channel.

The second option allows the integration time to be any value from lus to
3276.7 5, a span of roughly nine orders of magnitude. Clearly the useful range of
integration times is dictated by the frequency values produced by the voltage to
frequency conversion, but still the capability exists to use any integration time within
the given range. In a truly simultaneous application, however, it must be noted that
all channels would have the same integration time unless an independent source

gated each of the counters.

33

The second option could easily incorporate a switchable current
ampliﬁcation factor so that any board could be used for any element. The ﬁrst

option dedicates each channel module board to a speciﬁc element.
Lin mi n

It is somewhat difficult to compare the linear dynamic ranges Of the two
methods. According to the AtomComp 750 manual”, the maximum number of
counts per second obtainable with the present system is about 250 000. This value
for the second Option will vary depending on the clock frequency used to drive the
VFC. Assuming a 1 MHz oscillator is used, the maximum frequency output would
be 500 kHz, and thus the maximum obtainable number of counts per second is

500 000. These values are comparable.

5i"

In both cases the real sensitivity depends on the input bias current of the
operational ampliﬁer used either for integration or for current to voltage
conversion. In both cases the bias current results in a small voltage output. For
option one, however, the magnitude of the output voltage due to the bias current
varies with time since Vout is charge and time dependent. The voltage output of a
current to voltage converter does not vary inherently with time and can be

calculated by:
Vout = 'ibe
D . ,I . .

The susceptibility of a signal to variation or loss as it is passed between

various elements of a system is an important consideration if the signal is small.

34

Analog signals are more susceptible to electrical noise manifested as amplitude
ﬂuctuations. Time domain signals or digital signals are much less sinsitive to these
amplitude ﬂuctuations since only HI and LO logic levels need to be distinguished;
this type of noise does not change the frequency which encodes the signal. It is
therefore likely that the frequency passed from the VFC to the counter will be
better maintained than will be the voltage passed from the integrator to the ADC.
Since the detection limit is three times the signal to noise ratio (expressed as the
concentration of the analyte) it is possible that, all other things being equal, the
second option will have associated with it a lower limit of detection than does the

ﬁrst.

Although this is somewhat an esoteric factor, the simplicity of a system‘often
contributes to its user friendliness as well as to its functional lifetime. The second
system proposed is probably simpler to construct and use because it involves no
communication between the computer’s CPU and individual channel module
boards. The counter timer used with the second option serves as the integrator and
the analog to digital converter and provides the gate signal for the integration
process. The integrators of the ﬁrst Option are set and cleared by mechanical

switches which must be controlled by a remote CPU.
3.2.3 Conclusions.

Based on the criteria discussed above the second option was chosen for the
modernization of the polychromator interface. Speciﬁcally, reduced cost, wide
linear dynamic range, good sensitivity, ﬂexibility and simplicity make the second
option the more attractive overall. The system which was constructed is described

in detail in the next section.

35

3.3 Previous Approaches

The VFC and counter approach to data acquisition from photomultiplier
tubes has been used by several workers. Blades and Horlick reported in 198131 a
wide dynamic range data acquisition system for a single PMT using a VFC and an
8080 based single board computer. The key subsystem of the computer was an

onboard 8253 counter/ timer chip.

The 8253 counter timer has three 16 bit counters that can be programmed by
the user. Both the frequency measurement and the integration time carried 32 bit
resolution by cascading two counters on two separate 8253 counter timers. This
afforded the wide dynamic range deemed necessary for spectrochemical

measurements.

In the same publication by Blades and Horlick, a second wide dynamic range,
microprocessor controlled data acquisition scheme was described. A current to
voltage conversion is carried out as well, but in this case the voltage was
immediately applied to a 10 bit successive approximation ADC which was interfaced
to the single board computer. In a comparison of the two methods, the authors
suggest that the VFC/counter approach may be better suited to multichannel

measurements.

Horlick and Karannassios propose a method for interfacing the direct reader
involving a current to frequency conversion followed by counting. They suggest that

the system could be controlled by a single board computer”.

Judith Auping’s PhD thesis” describes a 48 channel upgraded interface for
the Jarrell Ash direct reader. In this system each channel module was equipped

with a current to voltage converter, a voltage to frequency converter, cascaded 4 and

36

12 bit counters, a 16 bit latch and chip select logic. This method allowed all 48
channels to be easily interfaced but requires communication between the central
processing unit and individual channel modules. In this system all channels cannot
be addressed simultaneously; as with the original system each integrator is

independently gated.
3.4 Description of Upgraded System

In two of the systems described above a VFC and counter approach is used
to interface a PMT to a computer. In both cases, however, the resulting instrument
lacks one of the two features desired of this system; multiple channels in the ﬁrst
case and simultaneity in the second case. These shortcomings are addressed in the

discussion of this system. Each aspect of the signal processing is described below.
3.4.1 Current to Voltage Conversion.

The current-to-voltage conversion is carried out by an operational ampliﬁer
(OA) equipped with a resistor in the feedback loop; that is a resistor between the
output and inverting input of the operational ampliﬁer. The choice of which
operational ampliﬁer to use involved a compromise between the relative
magnitudes of the input bias current and the offset voltage. Operational ampliﬁers
are typically constructed with either a low bias current or a low offset voltage. For a
current to voltage converter, the bias current is ampliﬁed by the same factor as the
signal. The offset voltage, however, remains constant regardless of the ampliﬁcation
factor. Furthermore, it is possible, with some operational ampliﬁers, to trim the
offset voltage with a potentiometer. For these reasons, an operational ampliﬁer
with a very low input bias current was chosen. The Analog Devices 549LH satisﬁed
the requirements with an ultra low input bias current and a fairly low offset voltage.

A diagram of the AD549LH based current to voltage converter34 is given in Fig. 12.

10 MO

) \
_.l_ PMT / O v
_ . 4. out

AD549LH
V

 

 

 

 

 

 

 

 

Q

Figure 12: Circuit diagram of the current to voltage converter.

38

The feedback element for the current to voltage converter was chosen based
on the expected magnitude of the photocurrent. The largest expected current
should be ampliﬁed such that it produces a voltage no larger than the maximum
voltage input of the voltage-to-frequency converter. The Hamamatsu
photomultiplier tubes generally give no higher than 10 pA signals”; typical values
of photocurrents listed in the literature are between 1 nA and 1 uA. The largest
voltage for which the voltage-to-frequency converter will give a linear response is 10

V. A 10 MD feedback resistor gives 10 V for an input current of MA

Two decoupling capacitors are used to ﬁlter the power supply; a 0.01 uF
ceramic capacitor for low frequencies and a 1 uF Tantalum capacitor for high
frequencies. These are placed between the supply voltage input pins and digital
ground. The offset voltage was left untrimmed since its maximum value (0.4 mV) is
small compared to the expected signals. Furthermore, the output voltage due to the
dark current of the photomultiplier tube is an order of magnitude larger than the

offset voltage (5 mV).
3.4.2 Voltage to Frequency Conversion.

The voltage-to-frequency conversion is performed by a single integrated
circuit. The particular package was selected because it had low gain and linearity
errors, a wide range of oscillator frequencies and high sensitivity. The AD6SZBQ
speciﬁes a 0.25 % gain error, a 0.002% linearity error, and a clock input of up to 5
MHz”. Finally the frequency output of the AD652BQ is synchronized to its clock
input. A circuit diagram of the AD652BQ synchronous voltage-to-frequency
converter '(SVFC) is given in Fig. 13.

A synchronous voltage-to-frequency converter, like other VFCs, uses an

integrator to carry out a charge balance of the input signal with an internal

39

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40

reference current. However, for the SVFC, the primary timing element is an
external clock rather than a one shot monostable multivibrator. This method
removes the requirement for a high quality low drift capacitor and allows the user to
determine the system stability and drift based on the performance of the external

clock or oscillator.

The voltage-to-frequency conversion involves several key steps. Assuming
the input signal is DC, the charge balancing integrator produces an up and down
ramp output. After the integrator output has crossed below the comparator
threshold the output of the AND gate goes H1. The next negative edge of the clock
transfers the information to the output of the ﬂip-ﬂop. At this point, the clock level
is LO so the latch does not change state. When the clock returns HI, the latch
output goes HI. This simultaneously drives the switch to reset the integrator and
returns the AND gate to a LO output state. On the next negative edge of the clock,
the LO AND output is transferred to the output of the D-ﬂop. When the clock goes
HI the latch output goes LO, driving the switch back into integrate mode. At the
same time, since not Q of the latch is HI, the AND gate is put into a state where its

output will truthfully represent the output of the comparator.

An external oscillator frequency of 1 MHz was chosen for the system. This
value gives reasOnable frequency outputs seven at low output voltages and
corresponds to a useful range of integration times between 1 and 1000 1115. A 0.022
uF mylar integrating capacitor was chosen. This was the component recommended
in the data sheets for use with the device operated at frequencies greater that 500
kHz. A 1 kn resistor is inserted between the frequency out pin of the package and 5
V. This sinks any excess current from the VFC. Two decoupling capacitors of the
same values and composition as those used for the operational ampliﬁer are

mounted near the supply voltage pin of the device to reduce AC noise from the

41

power supply. A 39 pF ceramic capacitor is chosen for the one shot giving a pulse
width of about 200 us. The one shot is actuated by connecting the capacitor to 15 V
(+V.). The voltage to frequency converter is conﬁgured for positive input voltages
in the O to 10 V range. An input greater than or equal to 10 V gives an output
frequency of one half of the clock frequency (500 kHz).

The synchronous VFC can be used in a number of creative applications. If
the output frequency is gated by a signal derived from its clock, the clock stability is
not important. In this conﬁguration, the SVFC acts as a voltage controlled
frequency divider giving a high resolution analog to digital converter. Also, if the
clock signal for a SVFC is supplied by a VFC, the output frequency of the SVFC is
related to the product of the two input frequencies. In this situation, multiplication

and analog to digital conversion of two signals can be performed simultaneously.

Note also that the Q output of the latch goes HI for exactly one clock cycle.
As long as the external clock is stable, the reset pulses applied to the integrator are
always of the same duration. This reduces the linearity error and produces a very

linear voltage to frequency transfer relationship.

One slight disadvantage of using a synchronous VFC is that the output is
constrained to be an exact fraction of the clock frequency. For example, if the input
current is exactly one quarter of the reference current then the output frequency will
be one quarter of fdock. This corresponds to one clock cycle for reset and three
cycles for integration. Increasing the input current very slightly should produce an
instantaneous, slight increase in the output frequency. This, however, is not what
occurs. Initially, no change in the output frequency is observed. The output
frequency remains at one quarter of few. so that an average of 250 pA is delivered

to the summing point of the integrator. Because the input current is slightly greater

42

that 250 uA (corresponding to an input voltage of Vm > {250 pA }{20 In} > 5 V)
the integrator accumulates charge. This causes the sawtooth signal that is the
integrator output to drift downward, and the comparator threshold is crossed earlier
with each integrator/ reset cycle. Finally, a full clock cycle is lost and the integration
time period lasts two clock cycles rather than three. Thus, the average output
frequency of the SVFC is proportional (linearly related) to the input voltage but the

instantaneous may not be.
3.4.3 Channel Module Boards.

The current-to-voltage converter, voltage to frequency converter, crystal
oscillator, anode clip and BNC f0... jack are mounted on a 3” x 5" dual inline pin type
vector board. Each board is equipped with two busses and two 30 position IC
mount lanes. Each position is a 3 hole per pad strip on either side of a bus. The
edge of the vector board has 30 copper strips with the same spacing as the edge

connectors mounted on the channel module motherboard.

The vector boards were modiﬁed slightly for use with the system. The boards
were ﬁrst cut to ﬁt the guides on the motherboard edge connectors. The
connections between solder strip busses and copper ﬁngers were severed. The
centre arm of the outer bus was isolated. These modiﬁcations generated three
ﬂoating busses which could be dedicated to +V., -V5 and ground by connection to
the appropriate copper ﬁngers as dictated by the conﬁguration of the motherboard.
The three busses were then connected to the appropriate positions along the edge
corresponding to those used in the original system. Positions 1 and 15 are at ground
potential, position 2 is at +Vs and position 3 is at -V,. Position 12 is used for a 5 V

supply voltage but is not connected to a bus on the vector board.

43

The ICs are mounted in 3MFM teﬂon crimp sockets. Wire wrap (22 gauge)
wire is used to make connections between two sockets and to passive components.
Photocurrent is passed from the PMT to the current to voltage converter via the
anode clip which is connected to a 12" piece of stranded, ﬂexible wire soldered to
the vector board. The output of the SVFC is removed from the channel module

board via a PC mount female BNC jack.
3.4.4 Channel Module Motherboard.

A motherboard for the five channel modules was constructed from existing
components; a printed circuit board manufactured at NASA and edge connectors
from a spare motherboard supplied by Jarrell Ash. The printed circuit board has
positions for 50 edge connectors with busses connecting pins 1, 2, 3, and 15. Five of
the edge connectors were removed from the original motherboard and mounted
onto the printed circuit board. The +5 V bus at pin 12 was constructed by
connecting jumper wires between adjacent edge connectors at that position. A four
terminal barrier strip was mounted on the motherboard for connection of the power
supply. The power supply for the channel module boards provides +15 V, -15 V,

and 5 V regulated outputs and was constructed in house.

The output frequencies from the channel modules are sent to a BUDTM box
via coaxial cable. Here the frequencies are transferred from the coaxial cable to the

SOURCE input pins of the MetrabyteTM board (via 37 conductor ribbon cable).
3.4.5 Metrabyte Counter Timer Module.

The ﬁnal step in signal processing is counting of the frequencies from each of
the four channel module boards. This is achieved by the software control of a

MetraByte counter/timer module, the C'I'MOS. The key subsystem of the board is

44

the Advanced Microdevices AMD9513 counter/timer. Other components on the
board include the system oscillator, base address selector and address decoding

logic, and an interrupt line”.
ADVANCED MICRODEVICES AMD9513 SYSTEM TIMING CONTROLLER.

This subsection gives a description of the AMD9513 system timing controller.
Some of the general details of its operation are given” along with its speciﬁc uses in
this system. A general block diagram of the AMD9513 is given in Fig. 14; a pinout

is shown in Fig. 15.

The AMD9513 can be addressed through two [/0 ports. The control port,
which directly accesses the command and status registers and the data port which
communicates with all remaining registers including the mode, load and. hold

registers for all ﬁve counter groups. The communication processes that occur within

the AMD9513 are shown in Fig. 16.
Control Port Registers

The control port addresses the command register when writing and the status
register when reading the hexadecimal (base 16) address 301. Both registers are 8
bits wide.

.Cammamdﬁcgistsr.
Several groups of functions can be performed by writing 8 bit command
codes to the command register. These are: Data Pointer Register updating,

Counter control, single bit Counter functions, and single bit Master Mode Register

functions. Each group of functions is described below.

Source 1-5

45

 

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requency sealer I _,. Logic Group
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register pointer Register , __, Logic Group
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and MUX 11 made register - Logic Group
, I l
m l"_—
: Bus Power ON _, Counter 1
; Interface Reset .___, Logic Group
; Control VCC V55

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Figure 14: General block diagram of the Advanced MicroDevices 9513

Counter Timer.

 

 

(+5V) VCC
OUT 2 <—C.‘
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Figure 15: Pin out of the Advanced MicroDevices 9513 Counter Timer.

47

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‘1. Data Pointer Register Updating.

All data pointer register (DPR) updates are requested by command codes
having the three most signiﬁcant bits set to 000. The location to which the DPR will
point is speciﬁed by a three bit group pointer and a two bit element pointer. The
group pointer selects either the control group or one of the counter groups. The
element pointer specifies one of the available registers in the given group. The
contents of the DPR specify the location for the next word sent through the data

port. The bit sequences for accessible registers are given below.

The three bit sequence for each of the counter groups and the two bit

element sequences available with each of the counter groups are listed in Table 4.

Table IV: Counter Group and Element Fields

 

Sequenee Green Segnenee Element
000 illegal
001 counter group 1 00 Mode register
010 counter group 2 01 Load register
011 counter group 3 10 Hold register
100 counter group 4 11 Hold register/hold
101 counter group 5 cycle increment
110 illegal

To select the control group, a three bit group ﬁeld of 111 must be speciﬁed.

The elements of the control group are given in Table 5.

49

Table V: Element Fields for Control Group

 

Sequence Element
00 Alarm register 1
01 Alarm register 2
10 Master mode register
11 Status register/ no increment.

The data pointer register itself is 6 bits wide. Five of the six are the element
and group ﬁelds; E2 E1/G4 G2 G1. The least signiﬁcant bit of the data pointer
register is the byte pointer which indicates whether the least or most signiﬁcant byte

of the data word is to be transferred on the next access through the data port.
2. Counter Control Functions.

All counter control function command codes begin with 001 through 110 and
end with a ﬁve bit counter select ﬁeld. Thus the function indicated by the ﬁrst three

bits is performed on the counter N if bit (N-l) of the command register is set.
3. Single Bit Counter Functions.

Single bit counter functions begin with 111 and end with 001 to 101

corresponding to the binary equivalent of counter 1 to 5.
4. Master Mode Register Single Bit Switching Codes.

These codes also begin with 111 but end with either 000, 110, or 111. Master
mode bits 12, 13 and 14 can be set or cleared by selecting the appropriate command

code. This is an alternative to using the data pointer register and the data port.

50
W
The status register is an 8 bit read only register typically accessed by reading

the control port, but can also be accessed via the data port as part of the control

group.

The least signiﬁcant bit of the status register (SRO) is a byte pointer which
indicates which byte of a 16 bit word is to be transferred next (0=LSB, 1=MSB).
This is functional only if an 8 bit external bus is speciﬁed since the Metrabyte board
has a 16 bit internal bus. For a 16 bit external bus, this bit is always 0. Bits SR1
through SR5 reﬂect the internal outputs of counters 1 through 5 after the polarity
select logic and just before the interface buffer circuit. The two most signiﬁcant bits

may be 0 or 1 and have no apparent purpose.
Data Port Registers.

Once the DPR has been loaded with the desired location, the next data
transfer through the data port delivers its contents. Each of the registers described

below is loaded through the data port in this fashion.
W25.

Each of the ﬁve counter logic groups includes a 16 bit general counter with
associated control and output logic, a 16 bit mode register, a 16 bit load register and
a 16 bit hold register. Counter groups 1 and 2 also have a 16 bit alarm register and
a 16 bit comparator. All registers are read/writeable through the data port, but the
counter itself is never directly accessed. Comparator and alarm functions for

counters 1 and 2 are controlled by the master mode register. A block diagram of

the control of counter logic groups is shown in Fig. 17.

51

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GATE I Slnput 16 bit load register
FREQ . elect 3
TCN—1 —. Logic 1
Counter Control . Out
Logic 16 but counter Control
16 bit mode register 16 bit hold register

 

 

 

 

 

 

 

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16 bit comparator r——-—‘

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16 bit alarm register]

 

 

 

 

 

 

Figure 17a: Counter Logic Groups 1 and 2

 

 

 

 

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Counter Control . . ‘ Out 1
Logic "_’| 16 bit counter H Control ‘—*

I16 bit mode register 16 bit hold registerl

 

 

 

 

 

 

 

 

 

 

 

Figure 17b: Counter Logic Groups 3,4 and 5

52

The general counter is reloaded from either the load or hold register on each
occurrence of a terminal count. The value in the load register is transferred to the
counter after each terminal count. The terminal count is the point in time when the
contents of the counter would have been zero if an external value had not been
transferred into the counter. Regardless of the mode selected, the contents of either
the load or the hold register are transferred to the counter on terminal count.
Issuing a LOAD command or combinations of commands including the LOAD

command is considered equivalent to a terminal count occurring.
1. Counter Mode Register.

The 16 bit counter mode register allows the user to specify the counting,
gating, source select and output functions for its respective counter. A wide variety

of mode options are available. A list is given in Table 6.
Table VI: Counter Mode Options

Mode Description

Software triggered strobe with no hardware gating

Software triggered strobe with level gating

Hardware triggered strobe

Rate generator with no hardware gating

Rate generator with level gating

Non retriggerable one shot

Software triggered delayed pulse one shot

Software triggered delayed pulse one shot with hardware gating
Hardware triggered delayed pulse strobe

Variable duty cycle rate generator with no hardware gating
Variable duty cycle rate generator with level gating

Hardware triggered delayed pulse one shot

RESERVED

Software triggered strobe with level gating and hardware retriggering

zgrn-mowmonw>

53

Table VI Continued: Counter Mode Options

 

Mode Description
0 Software triggered strobe with edge gating and hardware retriggering
P RESERVED
0 Rate generator with synchronization
R Retriggerable one shot
S Gate controllable delay/pulse width delayed pulse one shot
T RESERVED
U RESERVED
V Gate controlled variable duty cycle rate generator
W RESERVED
X Hardware save

2. Load Register.

The 16 bit read/write load register can be used to specify the contents of its
corresponding counter. The conditions for driving a counter to terminal count can
be selected when the mode is speciﬁed, but issuing a LOAD command always drives
the counter to terminal count. The action of the load register can be disabled by

giving it a value of hexadecimal 0000.
3. Hold register.

The 16 bit read/write hold register can be used for two purposes. The ﬁrst, as
mentioned above, is the same as the load register; that is its contents can be
transferred to the counter on terminal count. The bold register can also be used to
store the instantaneous count value accumulated in the corresponding counter.
Sampling. the counter by transferring its contents to the hold register does not
disturb the counting process. The STORE function can be executed by sending the

appropriate command code to the command register at any time during the

counting process.
4. Alarm Registers and Comparators.

These elements and their functions are available only for counters 1 and 2.
The comparator’s output will be TRUE when the counters contents are the same as
those of the alarm register. When the comparators are activated, the outputs of
counters 1 and 2 will follow the state of the comparator; out = TRUE when the
comparison is TRUE. The active level is speciﬁed in the counter mode register
output control ﬁeld. The comparators are activated individually by enabling the
appropriate bits of the master mode register. The alarm registers can be loaded by
issuing the appropriate command code through the control port such that the data
pointer register points to the register, and then sending the desired value through

the data port.

W

The master mode register controls internal functions which pertain to the
system as a whole or which are not controlled by the individual counter mode
registers. Setting the master mode register requires sending two commands. A hex
17 command code is sent through the control port, which sets the data pointer to
point to the MMR. The 2 byte master mode word is then sent through the data
port. Master mode bits 12, 13, and 14 can be set individually by issuing master
mode register single bit switching command codes to the command register through

the control port.

Fig. 18 gives assignments for the 16 bits of the master mode word. The
following is a brief description of system options that are controlled by the master

mode register.

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1. Time of Day Mode.

This function is controlled by master mode bits 0 and 1. Bit assignments and
their operations are given below.

00 - disabled

01 - enabled; 5 input

10 - enabled; 6 input

11 - enabled; 10 input

If MMO or MMl is 1 additional counter decoding and control logic is

enabled for counters 1 and 2 which causes their decades to turn over at counts which

generate 24 hour accumulations.
2. Comparator Enable.

The comparator functions for counters 1 and 2 are controlled by master mode bits 2
and 3.

MMZ = 1: Counter 1 comparator is enabled
MM3 = 1: Counter 2 comparator is enabled
If MM2/MM3 is 0, the corresponding comparator is disabled.

3. f0... Source.

The fl’CCll." ncy input for the f0... divider is speciﬁed by the next 4 bits of the
master mode word, MM4-MM7. The options include BCD or binary scaled

oscillator frequencies, source inputs, and gate inputs.
4. font dIVIdeI'.

Master mode bits 8-11 specify the four bit value by which the fa... source is

divided before being presented to the fa... pin.

57

5. font Gate.

Master mode bit 12 toggles the gate for f0... on (MM12=0) and off
(MM12=1). When fout off is chosen, the output is sent through a low impedance to

ground.
6. Data Bus Width.

Master mode bit 13 toggles the data bus width between 8 (MM13=0) and 16
bits (MM 13 = 1) wide. When an 8 bit external bus width is chosen the 8 lowest order

bits of the internal bus contents are used for input/ output.
7. Data Pointer Sequencing.

Master mode bit enables (MM14=O) or disables (MM14=1) the automatic
data, pointer sequencing functions. These are sequences through which the location
speciﬁed by the DPR will progress on request. When MM14=0, any of the data
pointer sequences can be speciﬁed or the data pointer register can be set manually
using the appropriate command codes. When MM14=,1 the data pointer register
can only be set manually. The automatic data pointer sequences that are available

are described below.
Element Cycle

This cycle is selected by setting either bit in the element ﬁeld (E1 or E2) to 0
and the group ﬁeld (G4 G2 G1) to counter group N. In this conﬁguration, the DPR
points ﬁrst to the mode register then to the load register and ﬁnally to the hold
register of counter N. The completion of the ﬁrst element cycle causes the group
pointer to be incremented by 1; the element cycle is then repeated for group (N+ 1)

and so on.

58

Hold Cycle

The hold cycle is enabled by setting the element ﬁeld (E2 E1) to 11 and the
group ﬁeld (G4 G2 Gl) to some counter group N. This selection cycles the data
pointer register through the group ﬁelds N, (N+1), (N+2) and so on with the

element ﬁxed at the hold register.
Control che

This sequence is activated by setting the element ﬁeld (E2 E1) to anything
but 11 and the group ﬁeld (G4 G2 61) to 111. In this conﬁguration, the data

pointer cycles through the elements of the control group only.
Status Cycle

This sequence is selected by setting the element ﬁeld to 11 and the group
ﬁeld to 111 and involves no incrementing of the data pointer register. The DPR

points to the status register all of the time.
8. Scaler Ratios.

Master mode bit 15 speciﬁes the base by which scaled oscillator frequencies
F2-F5 are derived. If MM15 is set to 0, the oscillator frequency is divided in binary
fashion, by successive powers of 16; if MM15 is set to 1 the oscillator is divided in

binary coded decimal fashion; by successive powers often.
3.4.6 Software.

An elementary program was written for simple data acquisition from the
Metrabyte CTMOS board. The original program was written in Microsoft

QuickBasic 4.00B. This was then translated into assembly code by Eric Hemenway

59

Of the C. G. Enke research group. The assembler routines were written in the
Turbo Assembler (TASM) environment. This was intended to increase the speed of
execution. The ﬁnal program uses a library of assembler routines callable from the
main QuickBasic program. The library, CTMLIB, includes subroutines for setting
the AMD9513 master mode register, conﬁguring counters 1-5, starting the gate
signal, checking the status of the gate signal, and storing the counts in counters 2-5
in an array. Each of the subroutines is described in detail in the following sections.
The QuickBasic calling code and library of assembler routines is listed in Appendix

1.
CTMLIB.

This is the calling code for the library of routines described below. The
system is ﬁrst initialized by CTMLIB, relevant constants are deﬁned, and then each

routine is called in succession.
Setting the Master Mode Register: SE‘I'MMR.

This subroutine is called ﬁrst from the QuickBasic program and serves to
conﬁgure the master mode register of the 9513 for the desired system functions.
This is typically if not always the ﬁrst task to be performed when programming the
AMD9513 counter timer. The data pointer register is loaded with the address of the
MMR by writing the appropriate command code to the command register through
the control port (17 Hex). Two bytes are then sent through the data port, DlDO
Hex, corresponding to the MMR bit assignments given in Table 7.

60

Table VII: Master Mode Register Bit Assignments

 

Bits Function Value Result
0,1 Time of Day Mode 00 TOD disabled
2 Compare 1 enable 0 Disabled
3 Compare 2 enable 0 Disabled
4-7 F0... source 1 101 F1
811 Foot divider 0001 Divide by 1
12 F0... gate 1 F0... off
13 Data bus width 0 8 bit bus
14 Data pointer control 1 Disable increment
15 Scaler control 1 BCD division

The time of day mode and comparator functions are disabled since they are
not used. The f0... source, divider and sealer control were assigned arbitrary values
since bit 12 turns off the fa... gate. The data pointer control bit is set to 1 to disable
automatic data pointer sequencing functions. This restricts the programmer to
changing the contents of the data pointer only by loading the command register with
the appropriate byte. An 8 bit bus width is speciﬁed to allow ﬂexibility in the choice

of the controlling microprocessor.

Generating the Gate Signal.
Cheesing the Gate Siggal,

The next subroutine will set up a gate signal for the data counters. As
mentioned in the section describing the capabilities of the AMD9513, there are
many gating options available to the user. Thus, it is advantageous for the user to
deﬁne a set of requirements for the gate signal that form a basis for choice of a
speciﬁc option. Three points seemed essential in this particular application. First,

the frequency of the gate signal must be sufficiently adjustable to generate a wide

 

61

range of integration times. Second, the level of the gate signal must be readable so
that the status of the data acquiring counters (integrating or ready for reading) can
be quickly determined without disruption of the integration cycle. Third, the gate
signal must be available as output on the 37 pin D connector so that it can be

connected to the external gate inputs of the integrating counters.

These constraints leave two more obvious options for generating the gate
signal. Both methods involve hardware triggering of the data counters; only the

source of the gate signal differs.
1. Gate = fout

The frequency output available to the user at the fa... pin is derived from the
internal frequency source of the AMD9513. Two software speciﬁed parameters
determine the magnitude of the frequency at the fa... pin. Any one of 15 internal
sources can be divided by up to 16, in unit increments, providing a reasonably large
number of gate periods. Sources which can be sent to the divider are chosen from
the following options; any one of the ﬁve counter sources (SRCl-SRCS) or gate
inputs (GATEl-GATES), or one of ﬁve frequencies derived from the on board
oscillator (Fl-F5). The base frequency, F1, is the external oscillator frequency
(1 MHz). The maining four frequencies, F2-F5, are integral fractions of the
oscillator frequency. If the scale for division is binary coded decimal (BCD), then
F2-F5 are, respectively; 100 kHz, 10 kHz, 1 kHz, and 100 Hz. If the scale for
division is binary, then F2-F5 are F1/16...F1/164.

The f0... pin is accessible at the D connector and can thus be used as input for
the gate pins of the ﬁve counters but its output level cannot be determined directly
by software inquiry. It could, however, be read through the digital input port

available at the D connector.

62

All possible sources available to be sent to the fa... divider cannot be used
with this application. The sources for the ﬁve counters (SRCl-SRCS) must be the
frequencies produced by the VFCs; the gate signals GATEl-GATES also must be
used, leaving only F1-F5. This is still a reasonable selection of frequencies since
each element of the two sets of Fl-FS can be divided by any integer between 1 and
16. This gives a total of 136 unique output frequencies that can be used for gate
signals. The calculation of periods for each frequency (and hence integration times)
depends on the duty cycle of f0.... This is not, in general, 50% and varies depending
on which of the ﬁve frequencies is used and what f0... divider ratio is chosen. Thus,
f0... may not be the ideal source for a gate signal. Furthermore, in order to adjust
the value of f0... and the state of the fa... gate, the master mode register must be

reconﬁgured.
2. Gate = Counter 1.

As an alternative, one of the counter outputs could be used as a gate input
for the remaining four counters. This counter can be conﬁgured to use an internal
or external time base as its source. Given that the time base is chosen, the counter
can be set to count (down) from any value between 1 and 216-1 (65535). The output
of each of the ﬁve counters available on the D connector and is software accessible.
Finally, the counter’s output can be set to give a short pulse or to toggle its output

state on each occurrence of a terminal count source pulse.

This option unfortunately requires the sacriﬁce of one of the data channels
since one counter serves as a gate for the others. Thus only four channels of data
may be acquired simultaneously as opposed to the ﬁve available with the ﬁrst
option. However, using one of the counters as a gate signal for the others produces

a set of integration times spanning nine orders of magnitude in unit increments of

63

the smallest period (1 us). Also, all functions of the gate counter can be controlled
by issuing commands to the appropriate counter mode register or to the command

register.

Based on ﬂexibility and predictability of integration times, and simplicity of
implementation, the second gating option was chosen for this system. The details of

conﬁguring counter 1 as the gate signal are given below.
Conﬁguring Counter 1 as Gate: SETCNTR 1.

In this subroutine, counter 1 is conﬁgured as the gate signal for the remaining
counters. Before implementing this routine, the output pin of counter 1 (pin 35 on

the D connector) is connected to the gate input pins of counters 2-5.

The counter mode register of counter 1 is loaded with the 2 byte word that
corresponds to the desired actions; OEOZ Hexadecimal. The individual bit

assignments are listed in Table 8.

Table VIII: Counter 1 Mode Register Bit Assignments

 

m Value Function
0-2 010 Counter 1 output TC toggled
3 0 Count down
4 0 Binary count
5 0 Count once
6 0 Reload from load
7 0 Disable special gate
8-11 1110 Source = F4; 1 kHz
12 0 Count on rising edge

13-15 000 No gating

64

This selection enables single point data acquisition on user request. The integration

is speciﬁed in ms since 1 kHz is selected for a time base.

Counters 2-5 will begin counting when their gate inputs are LO (this is
deﬁned in the CNTSEUP routine). To ensure that the gate is not opened before the

user requests acquisition of data, the output of counter l is set HI.
Setting up the data counters: CNTSETUP.

This subroutine sets up the data acquiring counters. The mode register for
each counter is Set with the desired options. All other registers are loaded with zero
to start. At the end of the subroutine, the counters are LOADed, ARMed and are

waiting for the gate to open; that is for the output of counter l to go LO.

Each counter mode register is loaded individually in a loop. The number of
counters being used is obtained as input from the user. The mode register for the’
current counter is loaded by sending the appropriate word through the data port.

The bit sequence for the necessary functions is detailed in Table 9.

Table IX: Counters 2-5 Mode Register Bit

 

Assignments
CMR Bits Value Function
0-2 000 Counter N output is inactive
3 1 Count up
4 0 Binary count
5 0 Count once
6 0 Reload from load
7 0 Disable special gate
8-11 N Count source = SRC N
12 0 Count on rising edge

13-15 101 Gate = Active LO level GATE N

65

After the counter mode register has been set up, the load register of counter
N is sent a value of zero. When the loop is terminated, counters 2-5 are LOADed
and ARMed at the same time by sending a single command code (7E Hex) to the

command register.
Starting the Gate Signal: STRTCNTI.

This subroutine loads counter 1 with the integration time, opens the gate by
setting counter 1 output L0, and starts counter 1 counting down from the

integration time.

The integration time is sent to the load register of the gate counter. The
output of counter 1 is then cleared (set LO). Immediately after this command, the

counter is issued a LOAD and ARM command, which begins its counting period.

Because loading and arming counter 1 does not toggle its output, the output
of counter 1 following this command is still HI. Thus a LOAD and ARM command
is not sufﬁcient to provide the gate signal for counters 2-5. In order for counters 2-5
to begin counting, a DO must be presented to their gate inputs. This is achieved by
CLEARing the output of counter 1 (setting it LO) immediately before this counter
is given a LOAD and ARM command. Using this sequence of commands, the gate

counter’s output is L0 and will stay LO for the duration of the integration time.

The disadvantage to this approach is that as soon as the gate inputs for
counters 2-5 go LO, the counters are counting. This occurs before the gate counter
starts counting through the integration period. The integration time then must be
calculated to include the time delay for execution of the LOAD and ARM
command. Since the software is written in assembly language, this delay is relatively

short compared to typical integration times; perhaps a few microseconds added to at

least one millisecond.
Integration Cycle Status Check: CHKSTAT.

This subroutine determines whether or not integration is completed. This
task is not trivial since operations which may interrupt the integration process must
not be executed during the integration cycle. Thus, a non-invasive method for
determining whether or not the cycle is complete is essential. Several conditions

would indicate that the integration period had concluded. These are listed below.

1. The values in counters 2-5 are constant.
2. The output of counter 1 and the gate inputs of counters 2-5 are LO.
3. The gate counter has reached its terminal count (TC) value.

The ﬁrst option requires making successive comparisons over time of the
counts in each data counter. Since the source frequency could be any value between
0 and 500 kHz, this method is not feasible. Furthermore, whether or not a signal is
being collected, the data counters are recording background and thus their values

are always increasing.

The second choice requires reading the least signiﬁcant bit of the status
register (OUTl) 9:111] it goes HI. The options for determining the contents of the

status register were discussed earlier in this chapter.

The ﬁnal possibility involves reading the contents of counter 1 until they are
equal to TC. Either of the latter two options is acceptable; the third was chosen.
The conditions for driving to TC a counter operating as a software triggered strobe

are described below.

67

When any software triggered down counter receives an ARM command, it
begins counting down from some value N (the integration time) until it reaches a
value of one. The count remains one for one cycle of the source at which point the
counter is reloaded with the contents of a preselected register. The mode register
was conﬁgured such that counter 1 is reloaded from the load register, so that the
contents of the counter are again N. Counter 1 continues counting down to (N-l),
the terminal count value. Thus, the TC condition is met for counter 1 when a source

edge drives its count to (N-l) for the second time.

As mentioned above, the integration period is complete when the contents of
counter 1 are (N-l) where N is the integration time. This event, however, will occur
twice; once during the integration period, and again at TC. The ﬁrst occurrence
clearly must be ignored so two check status routines were written. CSTATl
determines whether or not the gate counter has reached a count of (N-l) for the
ﬁrst time. This is accomplished by repeatedly comparing the contents of counter 1
to (N-l). The comparison is false while the count is greater than or equal to (N-l);
true if the count is less than (N-l). When the comparison is true, the second check
status routine is called. CSTAT‘Z also compares the contents of counter 1 to (ND.
The comparison is false in this case while count 1 is not equal to (N-l). When the

count is (N-l), the comparison is true and the subroutine is exited.

Both check status routines perform the same function; that is to compare the
contents of counter 1 with (N-l) without disturbing the counting process. The
contents of the counter are sent to the hold register by issuing a SAVE command.
By pointing to the hold register of counter 1, its contents can be taken through the
data port as input. The value in the hold register is thus read into one of the
microprocessor’s internal registers, and the comparison is made. The process is

repeated until the individual conditions for termination given above are met.

Save the data: STORECNT.

This ﬁnal library routine stores the contents of the integrating counters in an
array called CNTR. Each counter’s contents are transferred to its hold register.
The data pointer is set to point to appropriate location, the data word is read as

input and ﬁnally stored in the array.
Calling Code: CTMOSB

The main program, CTMOSBBAS, serves to obtain various pieces of

information from the user and to call the library of assembler routines.

A ﬁlename and key data collection parameters are obtained from the user.
The number of channels of data being examined and the integration time are then
requested. With this information, the quicklibrary CTMLIB is called. When data
have been acquired, the user is prompted to either save or reject the points. He/she

may then collect another data point or exit the program.

Chapter 4

RESULTS AND DISCUSSION

In this chapter the results obtained with the revised system are presented and
discussed. The experimental section gives the details of instrumental parameters
used for data acquisition. The results section deals with the two goals of this work;
the ﬁrst being selection of four appropriate elements for simultaneous multielement
analysis; the second being construction of calibration curves. Analytical ﬁgures of
merit and SMEA capabilities of the ICP/direct reader are evaluated in the

discussion.
4.1 Experimental
4.1.1 Instrumentation

The ICP-OBS system used for this work is a PlasmaTherm 2500 inductively
coupled plasma. This consists of an RF Plasma quartz torch and a Meinhard
concentric glass nebulizer. The ICP is powered by a PlasmaTherm 27.12 MHz RF
generator equipped with a PlasmaTherm AMNS automatic matching network.
Radiation from the ICP is focussed onto the entrance of the polychromator with two
optical elements; both are fused silica biconvex lenses with focal lengths of 60 mm
and 90 mm. Focussed radiation is passed to a 0.75 m holographic concave grating
(1509 grooves/mm). Dispersed radiation is passed through 25 um exit slits onto 1%
inch diameter side-on mount Hamamatsu photomultiplier tubes. Photocurrent from
the PMTs is ampliﬁed, and then converted to a frequency. This frequency is then
counted using a Metrabyte CTM-OS Counter Timer Module mounted in a Zenith
IBM PC/AT compatible computer. The computer is equipped with a Zenith

ﬂatscreen color monitor, VGA card and Keytronix keyboard.

69

70

4.1.2 Parameters

For most experiments, the instrumental parameters used are listed in

Table 10.

Table X: Instrument Parameters

 

 

 

 

 

 

 

N ebulizer OFF.
Plasma gas ﬂow rate .......................... 12.01/min
Auxiliary gas flow rate--- - - 1.01/min
Nebulizer gas flow rate - ........... 0.0 l/min
RF power ............................................ 1.0 kW
PMT voltage.---- - - -- 950 V
Integration time..-..- "-1000 ms

Nebulizer ON.
Plasma gas ﬂow rate .......................... 14.0 1/ min
Auxiliary gas ﬂow rate ...................... 0.85 l/min
Nebulizer gas flow rate ..................... 0.65 l/ min
RF power- - . - - ..... 1.50 kW
PMT voltage - - 950 V
Integration time-- - - - - -------- 1000 ms

4.1.3 Solutions

Stock solutions were prepared by diluting the appropriate mass of a chloride
or nitrate salt of the metal in 1 litre of distilled-deionized water (Millipore).
Standard solutions of 0, 5, 10, 15, 20, 25, 40, 60, 80, and 100 ppm were prepared by

dilution of the appropriate stock solution.

71

4.2 Results

Four calibration curves were obtained for Ca, Cd, Mg, and Ni. For all but
calcium, concentrations of 0, 20, 40, 60, 80, and 100 ppm were used. Standards of 5,
10, 15, and 25 ppm were added for the Ca calibration. In addition to the single
element calibration curves, data were collected from two, three and all four

channels simultaneously for various concentrations of each element.

Initial experiments were carried out for measurement of the background.
Electronic, thermal, stray light, and dark current contributions to this were
determined independently. The conditions for each experiment are summarized in
Table 11.

Table XI: Experimental Conditions for Determinations
of Various Sources of Noise and Background.

 

Digital PMT Anode Ent.

Power Power Connect Slit
Electronic Noise on off no block
Thermal Noise on off yes block
Dark Current on on yes block
Stray light on on yes open

Average values of each type of noise are given in Table 12. These results

indicate that the largest contribution to the background is stray light.

Table XII: T ical Counts for Various Sources of
oise and Background

 

Electronic Thermal Dark Stray
Channel Noise Noise Current Light
1 25 29 30 330
2 6 7 14 153
3 21 21 28 687
4 33 33 66 574

72

Photomultiplier tubes and sockets were installed only at positions along the
focal curve corresponding to elements of interest. All PMTs were aged for about 48
hours to allow stabilization of the dark current before being used for data collection.
Optical alignment of the exit slits was veriﬁed in the following fashion. With the
plasma off, hollow cathode lamps were mounted behind the ICP enclosure such that
their radiation passed through the housing and was focussed onto the entrance slit
of the polychromator by the collection optics. The position of the HCL was
optimized to obtain maximum throughput of light through the polychromator.
HCLs were powered with nominal currents of 5-10 mA and in most cases were
single element lamps. Once the position of the lamp was optimized, the refractor

plate for the relevant element was rotated to maximize the signal.

Four elements were chosen for initial studies. These were Na, Fe, K, and Ca.
Typical count values (obtained from hollow cathode lamps) for each element are

listed in Table 13.

Table XIII: Typical Counts for Initial Four Elements

h n n W v 1 n

1 Fe 259.9 nm 30
2 Ca 393.7 nm 27750
3 K 799.4 nm 1388
4 Na 589.5 nm 59300

Although the intensity observed for iron at channel 1 was small, spectral
interferences of much higher magnitude were seen at every other channel. For
these reasons the PMT at channel 1 was moved from the Fe line at 259.9 nm to a Co
line at 345.3 nm. Alignment of the Co slit was ensured. The plasma background

intensity at all channels was then evaluated at the minimum PMT voltage.

73

With no solution being nebulized, three of the four channels gave the
maximum number of counts. Since the PMT voltage was at its minimum value, the
only means of further reducing the gain of the system was to reduce the

ampliﬁcation factor of the currentoto-voltage converter.

The amount by which the ampliﬁcation should be reduced was determined as
follows. Neutral density ﬁlters were placed back to back in front of the entrance slit
until the counts obtained at all four counters were on scale. Four 10% ND ﬁlters
were required, implying that a reduction Of three to four orders of magnitude of the

I/ V ampliﬁcation factor would be sufﬁcient.

The feedback element for a single bOard, the calcium at channel three, was
switched to a 10 kn resistor from 10 Mn. The plasma background was remeasured
and found to be an acceptable value of about 2000 countss‘. A 5 ppm Ca2+
solution was then aspirated into the plasma to estimate the sensitivity of the lower

gain system. Approximately 52000 countS'S'1 were collected.

At the same time a second method was employed to reduce the measured
background intenSity of the plasma. The entrance slit to the polychromator was
blocked such that only radiation at more than 12 mm above the load coil (ALC)
passed through the slit. The plasma is hottest below about 10 mm ADC where most
ion-electron recombinations and brehmsstralung (free electron continuum) occur.
This results in extremely intense UV radiation. Masking the slit proved very
effective in reducing observed background intensity. Average background counts

are given in Table 14.

 

74

Table XIV: Background Intensities

 

Integration Background Relative
Channel Time (ms) Counts Std. Devh
Ca 100 14400 1.3%
Ni 1000 615 1.0%
Cd 1000 700 1.0%
Mg 1000 185 1.0%

With the slit masked below 10 mm ALC and the gain of the channel at
10 V/mA, a 10 ppm Ca2+ solution was aspirated into the plasma. This gave a signal
of approximately 2000 counts 5'1 with a background of 500 counts 5". Solutions of 10
ppm Nat, Kt, and Co2+ were then aspirated, again with the slit masked below 10
mm ALC but with a gain of 10 kV/mA The signals for all elements were

indistinguishable from the background.

Feedback resistances for the remaining three channels (Nat, K”, and Co“).
were changed to 10 kn so that all channels have a gain of 10 V/mA. At the same
time new elements were selected for these channels. Channel one collects Ni
emission at 231.6 nm, channel two collects Cr emission at 425.4 nm and channel four
collects Mg emission at 285.2 nm. The photomultiplier tubes at channels one and
four were replaced with UV sensitive PMTs (Hamamatsu R4275). The electronic
noise level was remeasured and the new PMTs were aged again for 48 hours prior to
redetermination of dark current. The dark current was determined at both the
highest and the lowest possible values of the PMT voltage. These values are given
in Table 15. '

75

Table XV: Dark Current at Various PMT Voltages

Electronic Dark Current (cnts

 

Chm Noise tents) 580 V 950

1 9 2 10
2 35 1 10
3 27 900 32200
4 23 0 1

Aspirating 100 ppm solutions of each of the three new elements into the plasma and
collecting emissions above 7 mm ALC gave the representative signals shown in

Table 16.

Table XVI: Signals Obtained Above a 7 mm
Height Above the Load Coil

 

n l B Ni ML CI—
1 30 160 30 33
2 510 510 510 515
3 2150 2170 2150 2150
4 25 25 35 35

The combination of masking the entrance slit and reducing the ampliﬁcation
factor of the current to voltage converter by three orders of magnitude gave a
sensitivity far below that which could be expected. In order to increase sensitivity,
the ampliﬁcation factor was raised to 100 V/mA using a 100 kn feedback resistor

for all four channels.

With the revised channel module boards in place, the entrance slit masked
below approximately 12 mm ALC and the PMT voltage raised to 950 V, the

following representative signal intensities were obtained:

 

76

Table XVII: Representative Signal Intensities Obtained
at Reduced Gain

10 ppm 100 ppm

 

Channel Blank Ca

1 (Ni) 70 90 90
2 (Cr) 1250 1750 1750
3 (Ca) 3000 24000 4500
4 (Mg) 40 4O 70

Following various unsuccessful attempts to improve the sensitivity of the
chromium channel, and in light of its susceptibility to spectral interferences, again a
new set of elements was chosen. The ﬁnal positions of the PMTs are as follows:
Channel one collects second order Ni emission at 231.6 nm, channel two collects
second order Cd emission at 228.8 nm, channel three measures Ca emission at 393.7

nm and channel four measures Mg emission at 285.2 nm.

After selecting four elements for which simultaneous multielement analysis
gives minimum spectral interference and acceptable sensitivity on all channels, the
data acquisition software was improved so that runs could be made quickly in
succession. Data for each element alone were collected on all four channels such
that single element calibration curves could be constructed. These are shown in
Fig. 19. Finally, emission studies of two, three and all four elements were conducted
simultaneously. These results are given in Table 18.

Table XVIII: Simultaneous Multielement Analysis
with Upgraded ICP-OBS System

Concentration
l n M r i

Ca 6.45 :1: 0.07 6.0 9
Ni 9.81 0.1 10.0 2

Calcium Calibration

 

 

 

 

 

Curve
40000 1 1 1 1
O
3. 30000 — —
.(7) O
E a
E 20000 _ -
(D O
.2
:6 a
§ 10000 — -
O
O
O 1 1 1 1 r
0 10 20 30 40 50
[Calcium] ppm
Nickel Calibration
Curve
1000 1 r 1 1
800 — a
3
'(71
8 600 — —
E
Q)
.3 400 — ~
0
E)
200 — —
O 1 1 1 .1 —

 

 

 

O 20 40 60 80

[Nickel] ppm

Relative Intensity

Relative Intensity

Cadmium Calibration

 

 

 

 

Curve
2500 1 1 1 1
2000 — a
1500 e -
1000 — a
500 — ~
0C 1 1 1 1 T
0 20 40 60 80
[Cadwmnn]ppa1
Magneshnn Cahbraﬁon
Curve
300 1 1 1 1

 

250

200

150

100

50

 

 

l l l

l

 

 

20 40 60

[Magnesium] ppm

80

78

Table XVIII continued: Simultaneous Multielement Analysis
with Upgraded ICP-OES System

 

Concentration

Element Me r A
Ca 6.36: 0.06 A 7.0 6
Ni 15.8: 0.2 15.0 5
Cd 9.8: 0.1 10.0 2
Ca 3.97:1: 0.04 4.0 1
Ni 11.8: 0.1 10.0 18
Cd 14.71 0.2 15.0 2
Mg 16.1 :1: 0.2 20.0 20

4.3 Discussion

The four channel, voltage-to-frequency conversion based data acquisition
system was shown to be effective for simultaneous multielement analysis. The
results presented above prove the feasibility of the system, but by no means reﬂect
its full potential since data were collected under less than optimal conditions. In
this section, analytical ﬁgures of merit of the ICP polychromator detection system
are evaluated and discussed. Methods for improvement of these features are

proposed with a focus on optimization of instrumental parameters.
4.3.1 Analytical Figures of Merit.
Sensitivity.

The revised system is capable of distinguishing between two photocurrents
differing by a minimum of only 0.2 nA out of a total possible 100 AA. This is a
function of the hardware based on the sensitivity of the voltage-to-frequency
converter and the ampliﬁcation factor of the current to voltage converter. With

switchable gain, this value could be reduced.

 

79

Detection Limit.

Experimental (30) detection limits for the four elements studied are between
0.5 and 1 ppm. The values given fora are standard deviations in the 0 ppm signal on
the line of interest. Speciﬁc detection limits for each element are as follows:
Ca: 0.7 13an Cd: 0.7 ppm. Ni: 1.1 ppm, Mg: 0.9 ppm. The Cd and Ni channels
collect second order radiation, so their detection limits might be expected to be

slightly higher than those collecting ﬁrst order radiation (Ca and Mg).
Linear Dynamic Range.

The theoretical linear dynamic range is six orders of magnitude. This
corresponds to the linear range of the voltage to frequency converter. The plasma
can be expected to give a linear range of ﬁve orders of magnitude. The observed

LDR is roughly three orders of magnitude.
Precision

Typical relative standard deviation values are on the order of 1%. This

ﬁgure is inherently highly dependent on the stability of the plasma.
4.3.2 Simultaneous Multielement Analysis.

In order for a system to be amenable to simultaneous multielement analysis,
instrumental parameters must be similar for a large number of analytes. Excitation
sources should be free of chemical and other types of interelement interferences,
and matrix effects for a wide selection of analyteslot". Spectroscopic tools in
particular-should be free from spectral interferences over a large wavelength range.
The ICP itself satisfies all of these requirements to a very reasonable extent. The

detection system, however, is less ideal. Several parameters including appropriate

 

80

individual channel gain, background intensity in the analytical window, spectral line
intensity, etc. vary quite a bit depending on the element being studied. These

problems could be removed with further optimization of the instrument.

When choosing a set of elements to be determined simultaneously, it was
necessary, then, to select four whose signals are all on scale and roughly the same
for a single integration time. This was somewhat difﬁcult since individual channels
are not all fully optimized. The single most important parameter to be optimized is
the position of the refractor plates in front of each exit slit. If each spectral line
were aligned, individual channel sensitivities would improve and perhaps be more

similar.

Chapter 5
CONCLUSIONS AND FUTURE WORK
5.1 Conclusions

The upgraded instrument maintains all of the capabilities of the original ICP
direct reader system, and makes it competitive with state-of-the-art systems. The
sensitivity and linear dynamic range are not reduced by the new interface; values for
detection limits do not increase. The system’s performance could be improved by
optimization of optical alignment as discussed in chapter 4. Some modiﬁcations to

the interface, however, might also enhance the instrument’s overall performance.
5.2 Future Work

In the remaining paragraphs of this chapter, possible improvements of the
direct reader interface are discussed. These are switchable gain, expansion to more
channels, independent channel gating, larger number of counters per channel, and

ﬁnally aesthetic improvements to the software.

5.2.1 Switchable Gain.

The addition of switchable gain for individual current to voltage converters (I/V)
might aid in optimizing the sensitivity of .each channel. As it stands, all PMTs
receive the same dynode voltage (since all PMT sockets have the same total dynode
resistance) and all signals are integrated for the same amount of time. With
switchable gain I/Vs, one source of ampliﬁcation is selectable by the user. The
disadvantage of including switchable gain is that the system is somewhat more
complicated with respect to the user. The beneﬁts afforded by such a modiﬁcation,
however, outweigh this disadvantage. A simpliﬁed circuit diagram of a four option

switchable gain current to voltage converter is given in Fig. 20.

81

 

82

5.2.2 Expansion to More Channels.

The expansion to more channels increases overall sample throughput since
more analytes can be determined at one time. The likelihood of chemical and
spectral interferences in such a system increases, but in many cases these can be
corrected for. There are two methods by which more channels could be included.
The ﬁrst is to multiplex the inputs of each counter; the second is to use more

counters.

Multiplexing of data channels is perhaps the more inexpensive method of
expanding the system. Four counters could be used to count as many as sixty four
frequencies. A block diagram of a 16 channel (multiplexed) interface for the direct
reader is given in Fig. 21. The multiplex approach, however, inherently involves
sequential analysis. Thus, the capability for simultaneous multielement analysis of

all channels is lost.

A second option would be to use more counters. In this case there is one
counter for each frequency (channel module board). A 50 channel system would
then require eleven AMD9513 counter timers (assuming all channels use the same
gate signal). A block diagram of a 19 channel interface using this approach for the
direct reader is shown in Fig. 22. This approach retains the simultaneous

multielement analysis capability of an ICP.
5.2.3 Independent Gating.

Independently gating each channel provides an alternative means of gain

selection since each channel would have a unique integration time. Addition of this

83

 

 

 

 

 

Figure 20: Diagram of a switchable gain current to voltage converter.

 

 

 

[1rov1-fvror]————
[ITOV Hvror }-—1
[HM Hvror }—J
[ITOV Hvrorj————

 

 

 

 

 

 

4MT8X1 —.@UNIER 1|

 

 

 

Ll

 

 

 

 

 

 

[110v J—urvror }—

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[1rov}—~.{vror}——-l , “01
vux ouerz]
[ITOVH vror ]——J
[trovHvror }-———
Llrov Hvror }——
[nov ]-—>| vror l—‘1
‘MTSX' OUNTER 3
[ITOVH vror l—J
[110v Hvror ]——
L1rov l-~l vror
[trov1—.[vror1—1 4701 oumrm}
uux
[110v ]—>[ vroﬂ—-—J

 

 

 

 

 

[110v Hvror

Figure 21: Diagram of a four-fold expansion of the Direct Reader interface
using 4 to 1 multiplexers.

 

85

 

 

r Channel 1 lﬁ

[ ChannelZ }——l J Counter2

é" Counter 3 Counter 1
:1 Counter 4 Gate
I Channel 3 |————J r] CounterS

r Channel 4 If Am9513 Counter Timer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

r Channel 5 }—

1
Channel 6 |-———-| ’
r q] ounter }

 

 

 

 

 

 

ounter
Chonnel7 1 *“ Counter3
I

:1
Counter 4
g] Counter 5
r Channel 8

Am9513 Counter Timer
rChonnel 9

 

 

 

 

 

 

 

 

 

 

 

[ ChanneliO

[Channel11
Counter

rChannel 12 Counter 3

I
F
f
l
I Counter 4
Counter 5
I Channel 13 I
1
I
l
J

 

 

 

 

 

l 1

Counter 1

 

 

 

JUUUUL

 

 

 

 

 

Am9513 Counter Timer
ﬂhannel 14

 

 

 

 

 

 

 

Counter 1
Counter

L Channel 17$ Counter 3

Counter 4
* Counter 5
I Channel 18 I ~

 

 

 

 

 

JJUU

 

Am9513 Counter Timer

 

 

I Channel 19 [F

 

Figure 22: Expansion to 19 channel using four Analog MicroDevices 9513
Counter/Timers

 

 

86

feature, however, necessitates the use of at least two counters for each channel in
the system. This is shown in a block diagram (Fig. 23). Expansion to many channels
using this approach may be more difﬁcult and would be more costly than using one
gate for all channels; however, independent gating of channels results in a much

more ﬂexible system.
5.2.4 Channel Resolution.

The use of two cascaded counters for each data channel would double the
present resolution and (logarithmic) linear dynamic range of the system. Currently,
each channel has 16 bit resolution. The useful linear dynamic range (LDR) of the
system is roughly 5 orders of magnitude. With two cascaded counters per channel, a
32 bit resolution and, hence, a linear dynamic range of 10 orders of magnitude are
theoretically possible. The limitation to the LDR, in this case, would be the
inductively coupled plasma itself which operates linearly over about 6 orders of
magnitude. Thus, increasing the resolution to 32 bits may not afford much of an

advantage.
5.2.5 Software Improvements.

Two modifications could be made to the existing software which would

improve both its user interface and capabilities.

First, the option to collect ﬂowing stream data at a ﬁxed rate should be
incorporated. Flow injection (FIA) is now widely used for sample introduction into
a plasma and offers many advantages over conventional methods. Less sample is
consumed and larger sample throughput can be achieved with an FIA-ICP-OES
system”. Furthermore, combining SMEA with PIA-ICP would result in a highly

modernized system.

87

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Counter 1 GATE 1 t CH AthtIéL 1 J Counter 1
Counter 2 GATE 2 t CHErirIéL 2 I Counter 2
Counter 3 GATE 3 >I CH 331$ 3 7 Counter 3
Counter 4 GATE 4 > CH 3mg ‘ Counter 4
Counter 5 GATE 5 Ar CH ADNAFIEL 5 I Counter 5
Am9513 Counter Timer Am9513 Counter Timer

Figure 23: Independently Gated, Five Channel Interface for the Direct Reader
using two AM09513 Counter/Timers

 

88

Second, the package could be menu driven to increase ease and speed of its
use. Potential options for the user might be choice of mode, time base, integration
time, and number of data channels for data acquisition. This could be considered a
somewhat esoteric improvement to the system, but would broaden its scope of

potential users.

The upgraded system may well be improved by the modiﬁcations mentioned
above, but is presently a research quality instrument capable of computer assisted

simultaneous multielement analysis.

10.

11.

12.

13.

14.

14.

16

17.

18.

19.

89

REFERENCES

TB Reed,J. Appl. Phys, 32, 821 (1961).

TB Reed,J. AppL Phys, 32, 2534 (1961).

S Greenﬁeld, Analyst, 89, 713 (1964).

VA Fassel and RH Wendt, Anal. Chem, 37, 920 (1965).

VA Fassel and SW Dickinson, Anal. Chem, 40, 1021 (1969).

SR Crouch and JD Ingle, S pectrochemical Analysis, Prentice Hall, Englewood
Cliffs, NJ 07632, 1988.

S Greenﬁeld, H MCD. MCGeachin and PD Smith, Talanta, 22, 1 (1975).

S Greenﬁeld, H MCD. MCGeachin and PD Smith, Talanta, 22, 553 (1975).
S Greenfield, H MD. MCGeachin and PD Smith, Talanta, 23, 1, (1976)
PWJ M Boumans, Phillips Tech. Rev., 34, 305 (1974).

PWJ M Boumans, Z. Anal. Chem, 279, 1 (1976).

WB Barnett, VA Fassel, RN Knisely, Spectrochim Acta, 825, 139 (1970).
RH Scott and ML Kokot, Anal. Chim. Acta, 75, 257 (1975).

RH Scott and A Strasheim, Anal. Chim. Acta, 76, 71 (1975).

RH Scott, A Strashiem, and ML Kokot, Anal. Chim. Acta, 82, 67 (1976).
IF Alder, AM Gunn, and GF Kirkbright, Anal. Chim. Acta, 92, (1977).
AM Gunn, GF Kirkbright, and LN Opheim, Anal. Chem, 49, 1492 (1977).
JP Alder, RM Bombelka, and GF Kirkbright, J. Phys. B, 11, 235 (1978).

PWJ M Boumans and FJ de Boer, Spectrochim Acta, 827, 391 (1972).

 

20.

21.

22.

24.

25.

26.

27.

28.

29.

30.

31.

32.

33.

34.

35.

36.

90

PWJM Boumans, FJ de Boer, and JW de Ruiter, Phillips Techn. Rev., 33, 50
(1973).

PWJ M Boumans and F] de Boer, Spectrochim. Acta, B32, 365 (1977).
PWJ M Boumans and FJ de Boer, Spectrochim Acta B, 27, (1972), 391.

S Greenﬁeld , ILW Jones, H MCD M‘Geachin, and PB Smith, Anal. Chim
Acta, 74, 225 (1975).

AE Watson, GM Russel, and G Balaes, ICP Inf. NewsL, 2, 205 (1976).
ED Salin and S M‘George, Spectrochim. Acta, 408, 435 (1985).
MW Blades and G Horlick, Appl. Spec., 34, 696 (1980).

KR Brushwyler, N Futura, and GM Hieftje, Spectrochim. Acta, 468, 85
(1991).

JV Sweedler, RD Jalkian, RS Pomeroy and M Bonner Denton, Spectrochim
Acta, 448, 683 (1989).

RB Bilhorn and M Bonner Denton, Appl. Spec., 44, 1538 (1990).
Fisher J arrell Ash Mark H AtomComp 750 Manual, Waltham, MA.
MW Blades and G Horlick, T alanta, , 574 (1981).

G Horlick and V Karanassios, Appl. Spec., 42, 961 (1988).

J Auping, Ph.D. dissertation, Cleveland State University, March 1983.

Analog Devices AD549 Monolithic Electrometer Operational Ampliﬁer Data
Sheet; Analog Devices, One Technology Way, PO. Box 9106, Norwood, MA
02062-9106.

Hamamatsu Catalogue, Side-0n Type Photomultiplier Tubes, Hamamatsu,
p. 24.

Analog Devices AD652 Monolithic Synchronous Voltage to Frequency
Converter Data Sheet; Analog Devices, One Technology Way, PO. Box 9106,

 

37.

38.

39.

91

Norwood, MA 02062-9106.

MetraByte CTM-OS Manual, MetraByte C TM-05 Counter Timer Module, 440
Myles Standish Blvd., Taunton, MA 02780.

Analog Devices RTI/850 Manual, Chapter 1: "The Am9513", Analog
Devices, One Technology Way, PO. Box 9106, Norwood, MA, 02062-9106

J Ruzicka and E Hansen, Flow Injection Analysis, Second Ed., 1988, Wiley,
New York, NY

APPENDIX I

Basic and Assembler Source Code Listings

 

; Name: CTMLIB
3 Function: To initialize and control the ch-os board.
3 Caller: MS-QuickBasic

' Declaration:

DECLARE SUB C'I'MLIB( BYVAL CNTR%, BYVAL IN'ITIM%,
BYVAL SEGADDR%, BYVAL ADDRPTR% )

CALL CTMLIB(CNTR%, INTI'IM%, VARGSEG(CNT&(1)),
VARPTR(CNT&(1)))

where CNTR% is number of used counters and INTTIM% is
the integration time (ms). The array must be a long
integer array.

0. .

‘C..'I.0.0.0.0'0.0.0.0.

.MODEL MEDIUM
.DATA

datptr EQU word ptr [bp+ 06]l ; Array offset.
datseg EQU word ptr [bp 4» 08 ; Array segment.
inttim EQU word ptr [bp +10] ; Integration time.
cntr EQU word ptr [bp +12] ; Counter used.

dat EQU 300h ; Deﬁne address of data register
cmd EQU 301h ; Deﬁne address of command register
.CODE
PUBLIC CTMLIB
CTMLIB PROC
push bp ; Store base pointer
mov bp,sp ; Setup own pointer
push es ; Store extended seg. reg.
push di ; Store data index.

call far ptr ;setmmr]

call far ptr tsetcntrl]
call far ptr_cntsetu ]
call far ptr strtcntl

 

call far ptr :chkstat]

call far ptr _storecnt]

pop di ; Restore data index.

pop es ; Restore extended segment.
mov sp,bp ; Restore stack pointer.

pop bp ; Restore base pointer.

retf 8 ; Return with 8 byte offset.

93

CTMLIB ENDP

; Routine: SETMMR

i Function: To set the Master Mode Register (MMR).
;SETMMR PROC

é Call routine to set the Master Mode Register (MMR).

9

3 Point to the Master Mode Register (MMR) through the
; command register (at &h301).

mov dx, cmd
mov ax,17h ; Set ptr to MMR

jm 3+2
olir dx, a1
2 Set the MMR.

’ mov dx, dat
mov al,0d0h ; Send 10 byte ﬁrst

jm S + 2
OUT dx, al
mov al,0d1h ; then send hi byte.
ijTS + 2
0 dx, a1
retf
’SETMMR ENDP

o
9

; Routine: SETCNTRI
3 Function: To set counter 1.
SETCNTRI PROC

; Point to counter 1 mode register throu h command register.
; Set the command mode register (CMR .

94

mov dx, cmd

mov al,1h

jmp 3+2

out dx,al ; Set ptr to counter 1.

mov dx, dat

mov ax,2h

jmp 3+2

out dx,al ; Send 10 byte.

mov al,0eh
jmp 3+2
out dx,al ;Send hi byte.

mov dx, cmd

mov al,0e9h

jmp 3+2

out dx,al ;To start, SET cntr 1 out (HI)

retf
SETCNTRI ENDP

; Routine: CNTSETUP
3 Function: To setup the used counters.
CNTSETUP PROC

3 Get the counting counters ready to go with the input
; parameters. On completion of the loop, counters are ready
; to go and are awaiting the gate signal. Also, load and
; arm counters 2~5.
’ mov bx,cntr ; Move counters into bx.
inc bl ; Offset due to counter 1.
’ mov cx,2 ; First counter used.
81:
mov dx, cmd
mov al, C]
jmp 3+2
out dx,al ; Point to mode register of counter.

mov dx, dat

mov al,8h

jmp 3+2

out dx,al ; Conﬁg. mode reg. of counter.

mov al, cl
or al,0a0h
jmp 3+2
out dx,al

mov dx, cmd
mov a1, cl
or al,8h
jmp 3+2
out dx,al

mov dx, dat
mov al, 0
jmp 3+2
out dx,al

inc cl
cmp cl, bl

jng SHORT 51

mov dx, cmd
mov al,7eh
jmp 3+2
out dx,al

retf

95

; Set for active LO gate level.

; Point to load reg. of counter.

; Load with zero.
; Next counter.

; Test if done.

; Load and arm counters.

 

CNTSETUP ENDP

; Routine: STRTCNTI
E Function: To start counter 1 counting.

STRTCNTI PROC

mov dx, cmd

mov al,9h

jmp 3+2

out dx,al ; Point to load reg. of cntr 1

mov ax, inttim

mov dx,dat ; Load with integration time.
jmp 3 + 2

out dx,al ;Lo byte.

xchg ah, a1

jmp 3 + 2

out dx,al ; Hi byte.

mov dx, cmd
mov al,0e1h

jmp 3+2
out dx,al ; Now clear cntr 1 out (LO)

mov al,61h
jmp 3+2
out dx,al ; Begin read gate signal

retf
STRTCNTI ENDP

; Routine: CHKSTAT
2 Function: To check if counter 1 is ﬁnished counting.
CHKSTAT PROC

3 Check to see if we have passed the looped count.
; For a full explanation, see Julie Horner.

mov bx,inttim ; Move integration time to bx.
dec bx ; Offset for counter overcount.

CSTATI:
mov dx, cmd
mov al,0a1h
jmp 3+2
out dx,al ; Hold counter 1.
mov al,11h
jmp 3+2

out dx,al ; Point to hold reg. of counter 1.

mov dx, dat

jmp 3+2

m 21de ; Read 10 byte.

xchg al, ah

jmp 3+2

in ade ; Read hi byte.

xchg ah,al ; Put bytes in right order.

cmp ax, bx
jge SHORT CSTATl ; Check if counter now lower.

; Now, we check to see if ﬁnished counting.

9

97

CSTA’I‘Z:
mov dx, cmd
mov al,0a1h
jmp 3+2
out dx,a1 ; Hold counter 1.
mov al,11h
jmp 3+2
out dx,al ; Point to hold reg. of counter 1.

mov dx, dat

jmp 3 + 2

in al,dx ; Read 10 byte.

xchg al, ah

jmp 3 + 2

1n al,dx ; Read hi byte.

xchg ah,al ; Put bytes 1n right order.

cmp ax, bx
jne SHORT CSTATZ ; Check if ﬁnished counting.

retf
CHKSTAT ENDP

; Routine: STORECNT
2 Function: To store the counter values in an array.
STORECNT PROC

9
; Save contents of counters 2-5 in hold registers. Return
; contents to caller v1a passed array.

cld ; Clear direction ﬂag.
mov ax,datseg ; Set ES to array segment.
mov es, ax
mov di,datptr ; Set D1 to array offset.

’ mov cx,1 ; First counter + 1.

32:
mov dx,cmd ; Command reg.

’ mov al, 1
sh] al,c1 ; Mask for selected counter.
or al,0a0h
jmp 3+2

out dx,al ; Move count to hold.

 

98

mov al,cl ; Reload counter number.
inc al ; Increase by one for counter 1 offset.
or al,10h
jmp 3+2
out dx,al ; Point to indiv. counter hold.
’ mov dx, dat
jmp 3+2
1n al,dx ; low byte
mov ah, a1
jmp 3+2
1n al,dx ; high byte
xchg ah,al ; Put them in the right order.
’ stosw ; Store the value.
mov ax, 0
stosw . ; Clear out high 16 bits just to be safe.
’ inc cl ; Next counter.
cmp cx, cntr ‘
jng SHORT 82 ; Check if done.
’ retf
STORECNT ENDP

END

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