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This is to certify that the

thesis entitled

UTILIZING AN FPGA IN CONJUCTION WITH A DSP PROCESSOR
TO FACILITATE THE IMPLEMENTATION OF
INDUCTION MOTOR CONTROL

presented by
John William Kelly

has been accepted towards fulfillment
of the requirements for

M. S. degree in Electrical Eng

66’;wa

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UTILIZING AN FPGA IN CONJUNCTION WITH A DSP PROCESSOR TO

FACILITATE THE IMPLEMENTATION OF INDUCTION MOTOR CONTROL

By

John William Kelly

A THESIS
Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

MASTER OF SCIENCE

Department of Electrical Engineering

1 997

 

 

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ABSTRACT

UTILIZING AN FPGA IN CONJUNCTION WITH A DSP PROCESSOR TO

FACILITATE THE IMPLEMENTATION OF INDUCTION MOTOR CONTROL

By

John William Kelly

The digital control program of an induction motor can be separated into two distinct
components, the actual control program and the pulse width modulation (PWM) program.
The control program is feedback dependent and sequential in nature, while the PWM
program does not depend on feedback and is memoryless. This thesis explores the
feasibility of implementing the PWM program on dedicated hardware, functioning in
parallel to the control processor. The intention is decreasing the overall computation time.
However, it was determined that only a partial PWM dedicated program was needed to
improve overall processing time. The other part of the PWM program was implemented
on a DSP processor. The DSP processor was also responsible for an indirect rotor flux
field orientation control program, which regulated the speed of a 1/12 horsepower
induction motor. Experimental results show this type of hardware parallelism decreases

computation time, resulting in greater inverter switching frequency.

Copyright by
JOHN W. KELLY
1997

To Katherine B. Torpey and Annie Kelly

ACKNOWLEDGEMENTS

I would like to thank professor Elias Strangas for his encouragement, support and
guidance. I would also like to thank professor Khalil and professor Shanblatt for their
time and effort in being on my committee.

Finally, I owe a special thanks to my parents, William and Patricia Kelly, and to my

wife Amy for their support, encouragement and love.

TABLE OF CONTENTS

LIST OF TABLES ....................................................................................................... viii
LIST OF FIGURES ....................................................................................................... ix
CHAPTER 1
INTRODUCTION ........................................................................................................... 1
The DSP Overview .................................................................................................... 2
The FPGA Overview .................................................................................................. 3
Program Allocation between FPGA and DSP .......................................................... 5
CHAPTER 2
SPACE VECTOR PULSE WIDTH MODULATION ................................................... 9
The Inverter .............................................................................................................. 9
SPWM Timing Calculation ..................................................................................... 11
CHAPTER 3
DSP IMPLEMENTATION OF SPWM ........................................................................ 15
Space Vector Calculations ...................................................................................... 15
SPWM Timing Calculations ................................................................................... 17
Execution Time ...................................................................................................... 18
Total Program Timing ............................................................................................ 19
CHAPTER 4
FPGA IMPLEMENTATION OF SPWM ..................................................................... 2O
FPGA-DSP Signals ................................................................................................. 2O
FPGA Program Overview ....................................................................................... 22
FPGA Program Components ................................................................................... 22
Pulse “on/oft” Constraints ....................................................................................... 26
CHAPTER 5
INDIRECT ROTOR FLUX FIELD ORIENTATION ................................................... 31
Mathematical Description of Induction Motor ........................................................ 32
Simplification of torque equation ............................................................................ 32
CHAPTER 6
CONTROL SCHEME .................................................................................................. 36
Transformation into Rotor Field Coordinates .......................................................... 36
Second Order Flux Observer .................................................................................. 38
Transformation into Stator Coordinates ................................................................. 40

Vi

CHAPTER 7

RESULTS ..................................................................................................................... 42
Induction Motor Parameters .................................................................................. 42
Simulation of Control Scheme ................................................................................ 43
Experimental Setup ................................................................................................ 44
Speed Tracking with Disturbance ........................................................................... 45
Step Input, Speed Command .................................................................................. 46
Free Acceleration ................................................................................................... 47
Program Timing ..................................................................................................... 48

CHAPTER 8

SUMMARY AND CONCLUSION ............................................................................ 50
Control and PWM Program Hardware Allocation .................................................. 51
Indirect Rotor Flux Field Orientation Control ........................................................ 52

Simulation vs. Actual Results ........................................................................... 53
Experimental Results ........................................................................................ 53
SPWM Pulse Time Constraints .............................................................................. 54
Future Directions .................................................................................................... 54

APPENDDC A .............................................................................................................. 56

APPENDIX B .............................................................................................................. 76

BIBLIOGRAPHY ........................................................................................................ 79

vii

LIST OF TABLES

Table 7.1 - Motor Parameters ........................................................................................... 42
Table 7.2 - DSP Control and SPWM program timing specifications .............................. 48
Table 7.3 - FPGA SPWM program timing specifications ............................................... 49

viii

LIST OF FIGURES

Figure 1.1 - Routing paths between CLBS ........................................................................ 3
Figure 1.2 - Combinational Logic Blocks of the Xilinx XC4005 FPGA .......................... 4
Figure 1.3 - CORDIC Processor ........................................................................................ 8
Figure 2.1 - Terminal and phase voltages of an inverter ................................................. 10
Figure 2.2 - Three phase inverter with resistive load ....................................................... 10
Figure 2.3 - Inverter switching states in the complex plane ............................................ 11
Figure 2.4 - SPWM pulse ................................................................................................ 13
Figure 3.1 - Determing switching state from sine and cosine ......................................... 16
Figure 3.2 - SPWM pulse ................................................................................................ 18
Figure 3.3 - DSP Timing ................................................................................................. 19
Figure 4.1 - The schematic of the FPGA program .......................................................... 21
Figure 4.2 - TCTIMER component ................................................................................. 24
Figure 4.3 - PULGEN component ................................................................................... 25
Figure 4.4 - SPWM pulse ................................................................................................ 26
Figure 4.5 - The elimination of pulses with small “on” times ........................................ 27
Figure 4.6 - The elimination of pulses with small “oft” times ........................................ 27

Figure 4.7 - Motor Phase Current and PWM Signal with 8 us time Pulse Constraint.... 28
Figure 4.8 - Motor Phase Current and PWM Signal with 9 us time Pulse Constraint.... 29
Figure 4.9 - Motor Phase Current and PWM Signal with 10 us time Pulse Constraint.. 29

Figure 5.1 - Equivalent Circuit of induction motor ......................................................... 33
Figure 5.2 - Stator, Rotor and Rotor Flux Coordinates .................................................. 34
Figure 6.1 - Schematic of the Control Scheme ............................................................... 37
Figure 6.2 - usd, isd relationship ....................................................................................... 40
Figure 6.3 - usq, isq relationship ....................................................................................... 40
Figure 7.1 — Reference (dashed) and actual speed (solid) with wref =18O rads/sec ........ 43
Figure 7.2 - Experimental Setup .................................................................................... 44
Figure 7.3 - Wref = 180 rads/s with load applied and removed ..................................... 45
Figure 7.4 - Without load (dashed) and without load (solid) .......................................... 46
Figure 7.5 - Free Acceleration, wref 20-220 rads/sec ..................................................... 47

Chapter 1

INTRODUCTION

A typical digital control program of an induction motor can be separated into two
parts, the actual control program and the pulse width modulation (PWM) program.
Sensing the stator currents and rotor speed, the control program determines a reference
voltage space vector required to achieve the desired response. The implementation of this
voltage is the task of the voltage-fed inverter, via a Pulse Width Modulation scheme.
From the angle and magnitude of the desired control voltage space vector, the PWM
program produces timing pulses for the inverter switches.

The digital implementation of the control and PWM programs is computationally
time consuming. The long processing time is at the expense of the inverter voltage
resolution. A lower resolution means a lower inverter switching frequency which results
in slower response and greater harmonic effects. Therefore, the overall goal in designing
a program structure is to attain the highest switching frequency possible. The purpose of
this thesis is to explore the idea of utilizing a field programmable gate array (FPGA) in
parallel with a digital signal processor (DSP) to decrease the processing time of the total

control program of an induction motor.

Before expanding on the decided optimal roles of the FPGA and DSP in the overall

program design, overviews on both devices will be discussed.

1.] THE DSP OVERVIEW

The digital signal processor was chosen for its inherent speed advantage, which is
due to its parallel processing architecture. The DSP processor used was the 50MHz,
AT&T DSP32C. Two major components of the processor are the control arithmetic unit
(CAU) and the data arithmetic unit (DAU). The CAU is responsible for arithmetic
calculations required for logic and control functions. Functioning in parallel with the
CAU, the DAU is responsible for all 32-bit floating-point operations.

The computational speed advantage of the DSP processer is realized in the DAU.
The DAU consists of a dedicated floating-point multiplier and adder, which work in

parallel to perform the DAU’s basic operation, the inner product step:

a=b+c*d (1-1)

The DAU performs this operation in a four-stage pipelined instruction sequence,
fetch-multiply-accumulate-write. First c and d are fetched from memory and multiplied
together. Next the product of c and dis added to b. Finally, the sum is written to memory

or an I/O port. The instruction cycle time is 80 ns. [1]

1.2 THE FPGA OVERVIEW

A Field Programmable Gate Array consists of three general components; logic
blocks, routing resources and I/O blocks. Each one of the components is reprogrammable,
which is why FPGAs are a popular prototype tool. The U0 block connects the external
package pins to internal logic blocks. Routing resources connect the I/O blocks to Logic
Blocks and Logic Blocks to each other. The programmable switching matrices allow

Logic Blocks to be connected in an array type architecture on the chip, Figure 1.1. [2]

 

Figure 1.1 - Routing paths between CLBS

The logic block implements the desired function. There are two methods which a
combinational function is realized in a FPGA. The function is either implemented by a
multiplexer scheme or with a look-up table (LUT). The LUT is the predominant
architecture used today. Often called a function generator, the LUT along with the U0
block and switching matrix is configured by static random-access memory (SRAM) cells
on the chip. The program written by the user is downloaded from a PC or EPROM to the
SRAM cells. Figure 1.2 shows the components of the Combinational Logic Block (CLB)

of the Xilinx XC4000 FPGA.

Control Inputs

(31

Logic
CZ Funcfion
G of
G4 c1—c4

Logic
Funcfion

of
F1 —F4 FF

'71-” "'1'“

 

Figure 1.2 - Combinational Logic Block of the Xlinx XC4000 FPGA

From Figure 1.2 it can be seen that the Combinational Function generator has eight
variable inputs, G1-G4 and Fl-F4. Therefore this CLB can implement the combinational
function f(Gl-G4,Fl-F4). The programmer may design this network either by using a
CAD program or writing the Boolean equations. However, in the LUT architecture, the
function is implemented by its truth table. The combinational function generator, or
lookup table, of the CLB contains the truth table of the function. The output part of the
truth table is stored in the SRAM cell and can be reconfigured for different functions. The
process of going from a cad program or Boolean expression of a network to a truth table

is called Combinational Logic Synthesis.

1.3 PROGRAM ALLOCATION BETWEEN THE FPGA AND DSP

The ideal scheme would utilize the FPGA to implement the total PWM program
while the DSP handled the control program. Because the single-input, single-output
PWM program is memoryless and feedback independent, it seemed practical to
implement the PWM program as a combinational logic circuit on a FPGA. The DSP
would determine the magnitude and angle of the voltage space vector and pass these
values to the FPGA.

With this information, the first step of the FPGA program would be to perform

several trigonometric operations, similar to:

Asin(a) (1'1)

Asin(a +- nil/3) (1-2)

In order to digitally evaluate these functions, a coordinate rotation digital computer
(CORDIC) processor [3] was developed for FPGA implementation, Figure 1.3. However,
the cordic processor was complex and CLB expensive. A finite-state—machine had to be
designed to control the cordic algorithm. Due to a limited number of CLBS, the resolution
of the processor was only 8 bits. Therefore resolution of the PWM signal would be at
maximum 255 pulses per period of the fundmental signal. Implementing a cordic
processor along with additional PWM arithmetic operations was determined too
expensive in terms of CLBS.

Therefore, instead of the total PWM program being implemented on the FPGA, it
was more practical to have the trigonometric calculations resolved on the DSP. With
the inverse magnitude of the voltage space vector, the DSP determines the cosine and
sine of the voltage space vector angle in two multiplication operations. This program
topology makes it unnecessary to determine the actual angle on the DSP via a lengthy
arctangent algorithm and unnecessary to implement a CLB, costly cordic processor on
the FPGA. Due to hardware and time constraints a further simplification was make to the
FPGA’s PWM responsibility. Half of the PWM timing information is calculated by the

DSP. The extra twenty six lines of code, approximately 2.1us, could be straightforwardly

implemented in a combinational logic fashion on a bigger FPGA, if the DSP required

more time for the control program. However, the need for more DSP control processing

time was not necessary. Implementing an indirect rotor flux orientation control scheme, a
inverter switching frequency of 12.4kHz was obtained.

The following chapter examines the PWM algorithm in terms of the space vector.
This is followed by detailing the DSP and FPGA responsibilities in implementing the
PWM algorithm. In order to test the PWM program, an indirect rotor flux orientation
control scheme was developed for implementation, which is also described in detail.
Using this control scheme and the PWM program , a 1/12 hp induction motor was run at
different set speeds, 2O - 230 rad/sec. The motor was run with a load and without a load,
in order to test the response of the motor. Plots of the speed are presented and discussed.
Finally, an evaluation of utilization of a FPGA in conjunction with the DSP is made,

along with future recommendations.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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8&1

Chapter 2

SPACE VECTOR PULSE WIDTH MODULATION

The three-phase stator voltages of an induction motor can be represented by a space

VCCIOT as
2
u. =-3- (um + anew + use em) (2-1)

At synchronous speed the voltage space vector rotates around the complex plane at
synchronous speed and with a constant magnitude. The basic idea of the PWM scheme
implemented, is that by controlling the magnitude and angle of the voltage space vector it
is possible to control the motor. Space Vector Pulse Width Modulation (SPWM) is a

technique for implementing a desired voltage space vector from a d.c. source.
2.1 THE INVERTER

The SPWM technique produces a switching sequence, pulses of varying duration, for
turning on and off the IGBTs of an inverter. Therefore, understanding SPWM requires a
basic understanding a voltage-fed inverter.

Figure 2.1 is the schematic for a six step inverter. The combination of the “on/off”
states of the three pairs of IGBTs results in eight possible switching states. The terminal

voltage of each leg of the inverter is U”, U3 and U13.

lO

 

 

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.

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.

 

 

 

 

 

 

Figure 2.1 -Terminal and phase voltages of an inverter

For a purely resistive load, the combination of terminal voltages produces the “stair-

step” like phase voltages: U”, U,» and U“ , Figure 2.2. [4]

I II III IV VVI

 

Figure 2.2 -Three-phase inverter with resistive load

11

The Roman numerals of Figure 2.2 are the switching states. The “+” indicates that
the top IGBT is closed or on.
Figure 2.3 shows the space vector representation of the switching states. States VII

and VIII are zero voltage output states.

  

 

     
 

IV

-<—++> - _

‘ E+++§VII | 1231—?
___ |
I
|

' VI
(——+): (+-+)

Figure 2.3 -Inverter switching states in the complex plane

Thus, each switching state represents a different voltage space vector value.
Additional voltage values can be achieved if the space vector is averaged between two
adjacent fundamental states and a zero state. The resulting voltage space voltage u"; in
Figure 2.3 is the average of the voltage of the three adjacent inverter switching states.

Over a re period, the switching state is (+ - -) for a duration of t], for a time of t; the

12
switching state is (+ + -), for a time of tO/Z the switching state is (+ + +) and for to/Z the

switching state is (- - -).

to to
Ic=§+tl+t2+-2" (2-2)

The time tc is half the switching period. In order to reduce inverter current harmonics,
tc should be chosen to be as small as possible. The constraints on the relative length of tc
are the speed of the control and pulse width modulation programs and the physical
switching ability of the inverter. The DSP SPWM program has the ability to change re, the
switching frequency, for each pulse. The time to is detennined from t1, t2 and re from
equation (2-2).

From Figure 2.3, the equation of the voltage space vector u”, is
l unfl IC = u] I] + “2 12 (2-3)

In terms of rectangular coordinates

t 2 1 +t 2 cos60 -t 2 cosa (24)
l3ud0 23W sin60-c3udmsina

The modulation index m is defined as:

 

m = 31' (2-5)
“4

13

Therefore, for a voltage space vector between states I and II, the times are:

* sin(6O - a)

 

t = tc * m 2'6

’ sin60 ( )

:2 = [C at m * Sl_n(a) (2-7)
sm6O

Figure 2—4 shows the inverter input pulses. Every pulse begins with the switching

state VII, (- - -), and ends with the switching state VII, (+ + +).

 

U1-++

 

 

 

 

UZ"+

 

|

L_
|
L_

 

 

U3"

 

 

 

 

 

 

Figure 2.4 -SPWM pulse

14

The procedure is the same for space vectors in the other five sectors, with angles

adjusted accordingly.[5]

Chapter 3

DSP IMPLEMENTATION OF SPWM

The control program determines the required voltage space vector in the stator
coordinates. This space vector is represented in its stator complex quaduature components

u“ and up. The quaduture voltage components are the inputs to the DSP part of the SPWM

program. With these two components, the DSP computes the sine and cosine of the angle

and the magnitude of the voltage space vector.
3.1 SPACE VECTOR CALCULATIONS

From the stator voltages , the complex quadature voltages “a and “a are defined as

“a I O 0 use
[ l: ___1_:_1_ a»
up 0J3 3 (3-1)

The magnitude of the voltage space vector is found by

 

l unfl = \l(ua* ua + up* up) (3-2)

However, first the inverse of '11an is calculated. The algorithm used is a Chebychev
approximation. The execution time of this computation is approximately 2.93 us with 21

significant bit accuracy. [6]

15

16

The angle of the space vector is not found directly, rather the sine and cosine of the

angle are determined.

 

 

cos(a)=—l:—:- (3-3)
sin(a)=-l-ffil- (3-4)

By comparing the values of sine and cosine, the switching sector which the voltage
space vector resides can be determined. This avoids the need to calculate the arctangent,
which is computationally expensive. The algorithm for determining the switching state

requires approximately 1.1 us.

IIIIIIIVVIV

 

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cccccc

 

 

 

 

 

 

 

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Figure 3.1 Determining switching state from sine and cosine

17

3.2 SPWM TIMING CALCULATIONS

Once the voltage space vector switching sector is determined, the SPWM pulse timing

information can be resolved. Using the trigonometric identity

sin(¢ - 5) = sin(¢)cos(§) — cos(¢)* sin(.’,‘) (3-5)

there is no need to use a lengthy sine algorithm to determine timing information. For the
DSP, determining the timing routine requires a series of floating-point multiplication and

addition operations. For example, the timing information of sector I is:

(sin(60)* cos(a) — cos(60)* sin(a))

 

 

t1 = t * * 3-6
C m sin(60) ( )
t2 = tc *m * SIM“) (3-7)

s1n(60)

The value of the inverse of sin(60) is a constant and is stored as a fixed variable in
the DSP SPWM program.
From to, t, and t2, the DSP program determines the off times of the SPWM pulses

according to which switching sector the voltage space vector resides.

l8

 

 

 

 

 

 

 

 

 

 

 

 

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Figure 3.2 -SPWM pulse

From Figure 3.2, tu, tv and tw are the times until the next switching state for the three

phases, respectively.

3.3 EXECUTION TIME

Starting with the acquistion of the stator quaduture voltage components, um and up
until the transfer of the SPWM timing information to the FPGA, the execution time of
the DSP SPWM program is approximately 9.71.1.8. Part of this time is used to determine

2tc, the SPWM period. Therefore, not only the magnitude of the space vector can be

varied but the its frequency can be varied as well, without sacrificing resolution.

19

3.4 TOTAL PROGRAM TIMING

After the SPEW timing information is determined, it is serially transferred as a 32-
bit word at a rate of 6.25 MHz to the FPGA. Once this word is latched into the serial
output buffer of the DSP, the control loop begins again. The actual data transfer to the

FPGA requires 5.3 Its. However, the data transfer and control program occur concurrently

 

l—l

I COMM. COMM.
M W? CONTROL 1 PWM | CONTROL [PWMJ
1 W

 

 

 

 

 

 

 

 

 

Figure 3.3 ~DSP Timing

Chapter 4

F PGA IMPLEMENTATION OF SPWM

Half of the timing information, t“, tv, t... and tc is passed from the DSP to the FPGA.
From these values, the FPGA calculates the other half of the timing information and
produces the PWM pulse. The design of the FPGA PWM program consists of several key
components, each of which will be described in detail.

An additional task assigned to the FPGA PWM program is to apply a time constraint
on the PWM pulse’s “on” and “off” times. These constraints are meant to meet inverter

switching specifications.

4.1 FPGA - DSP COMMUNICATION

At the end of the control program the DSP initiates the communication with the
FPGA by sending a load signal. Along with the load signal (OLD), four other signals are
connected to the FPGA: the DSP communication clock (OCK) the serial output line
(DO), the end load signal (OSE) and the serial input signal (DI). In Figure 4.1 the

schematic Of the FPGA program , the signals are seen as input pads.

20

21

“mmmwmhwm

 

 

 

 

>Ji_mx .3 21D) rm

mmumuZmuum
Han

a
m
D

m
7.

»

mDH<uHD2H Dmmnm FHm mm Lunx

gnu-ofikg
oma mmauva,
wva amnma_
mam use-ma
DODmMm ch m

(Nfis<zHa
s<aooma 13a

 

 

Figure 4.1 -The schematic of the FPGA program

22

4.2 FPGA PROGRAM OVERVIEW

From half of the SPWM pulse timing information tc, tu, tv, and tw, the FPGA
calculates the other half Of the timing information. First, tumW is substracted from tc.
Next, tc and (tc-tuym ) are doubled, simultaneously with the execution of the pulse. Due to
the symmetry of the SPWM pulse, 2(tc-tu,v,w) is the total “on” time of the pulse and 2tc is
the period of the pulse. After the time t”,w the SPWM pulse goes high and stays high for

a time of 2(tc-tu,v,w). After a time of 2tc new timing information is loaded.

4.3 FPGA PROGRAM COMPONENTS

The 3ZSTOP component of the FPGA program is a passive thirty-two bit serial to
parallel register. After the completion Of the serial download, the thirty-two bit timing
word is latched into a storage register, FD32RE. When the timing information is latched,
the DSP post-processing of the timing data begins, allowing the DSP to restart the control
program. First, t“, t, and tw are subtracted from tc by an eight bit high speed ripple-carry
subtracter. This difference along with the original timing information is again latched and
stored until needed by the PULGEN and TCTIMER components.

The TCTIMER component multiplies tc by two, resulting in the SPWM pulse
period. At the end of the pulse period, TCTIMER resets the counters of the PULGEN
components. During the next clock pulse TCTIMER receives the new tc and initiates the

loading Of the timing information to the three PULGEN components. Figure 4.2 shows

23

the schematic of the TCTIMER. The signal CLRILD is an initialization signal. The signal
LD2 resets the counters of the TCTIMER and the PULGENs and triggers timing data
latches. The TCTIMER has the capability to producing a pulse frequency of 100 kHz.

The PULGEN components produce the actual SPWM pulse. At the end of a pulse,
the PULGEN components loads new timing information, I“... and (tc-t...,,,,,,). A sixteen hit
counter immediate begins counting to tum. During the count of tum the signal (re-rmw)
is doubled, resulting in the total “on” time Of each SPWM pulse. When the count reaches
I”... the output Of a sixteen bit magnitude comparator goes high. This signal enables a
second counter that begins counting to 2(tc-tu,,,,,,,). When the count reaches 2(tc-tu_.,,,.,) the
output of a second sixteen bit magnitude compartor goes high. Therefore, the SPWM

pulse is an ‘exclusive or’ of the two magnitude comparators.

24

 

 

 

 

fio_mfi:no

 

 

mmhpmlozm A

 

 

 

 

 

 

 

 

 

 

OIL
Nah

 

mo.mfiwuHXUF

 

_ mmnnatazm Nan .muaabao
_ LQ.NLUH Qn\¢nu xnu mu .WODQCH
.

mmzHHuH

 

 

 

 

Nxx

moéuu:

 

 

 

IQLlll

 

 

Q4\m4u
xhu

Ii

mu

 

 

Figure 4.2 -TC77MER component

25

 

 

 

fl m.muupxup

 

 

 

 

 

 

 

 

 

 

fl o.mfi TquU»

 

 

 

Nab

 

,Qs\¢nu

 

 

 

 

 

 

 

 

 

 

 

mmhjm

 

 

 

 

 

 

 

 

mznmzou

 

 

 

 

ucfimcumcou med» umca+mo com: mo_muy_xu

mmnaa .ujauao

Non Dn\¢nu xnu mu fio.KLUL flo.mm<c fio_amx1u .mODQCH
zmo.L:a

 

 

 

 

fl 0.xgx1u

 

 

 

 

Figure 4.3 -PULGEN component

26

4.4 PULSE “ON/OFF” CONSTRAINTS

Figure 4.3 is the schematic Of the PULGEN component. The load signal, LD2,
generated by TCTIMER resets the counters. The signal PULSE is the SPWM pulse signal
sent to the output pads of the FPGA. The PULGEN is capable Of producing a pulse with

“on” or “off” time of 2/,Is. However, the inverter may not be able to switch at this speed.
The IGBTs of the actual inverter used were rated at a minimum of Sus. Switching faster

than the inverter specified rate may damage the IGBTs. Therefore, a constraint is placed
on the minimal time of the “on” and “off” of the SPWM pulse, Figure 4.4. This constraint
is implemented in PULGEN by evaluating the timing information. In Figure 4-3 there are
two eight bit magnitude comparators that compares the times 2(tc-tu,v,w) and tum, to user
defined times. If the “on” time is smaller than the user defined time, the SPWM pulse
will remain low for the entire period. Likewise, if the “Off” time of the SPWM pulse is
smaller than the user defined time, the pulse will remain high for the entire period,

meaning the inverter never switches states.

 

 

 

 

 

 

 

'Off" H
U1 1 ! I
| I I
tll It]
lilil12l_o|
I2I 1It I 2.
I -§— I

Figure 4.4 -SPWM pulse

27

Figures 4.5 and 4.6 show the actual PWM signal with pulse time constraints. In each
of the plots the top signal ( which is the same PWM phase signal) has an imposed time

contraint, while the bottom signal is free of a time constraint.

-.t"'-c

 

 

 

"n'.-"4 . n

"
'0'. .
III. .
II. 9
ll 4
7' I-
". a
I'- IL
"
ll .
F'- T-“
a" e
0
III" .II.
.-
II TL
.
r" U’.
_
j'.’A‘.T' .T'.
B
.‘l'.-. .-.'. .

III
III

l! N H!
ii iii

III II
III II

II II III
III II II II III

III II

!! ii!
i! U!

° III II
III II

'.‘.'.'."

 

 

Figure 4.5 - The elimination of pulses with small “on” times

"oTT't' .

 

F'.¥j '.'.1v

. .IIIA

r..-u'A

AR

1.”...

I A

run

.‘.'.'.1‘

.1I.l.:

 

H
ll

IJIII II

II i II
M l 1!

'1

l!
U

 

 

 

 

Figure 4.6 - The elimination Of pulses with small “off” times

28

In order to determine the effects of placing “on” and “off” timing constraints on the
SPWM pulse, the motor was run with no load at rated voltage and current. The switching

frequency Of the SPWM signal was 24.8 kHz. Figures 4.7,8,9 demonstrate the effects of

placing time constraints on the pulse.

 

 

 

 

 

 

 

 

a 2 T r
O.
E 1
0
- 0
2
4
-2 l A l A
0 0.01 0.02 0.03 0.04 0.05
g seconds
0 10
>
2 5
3
m
o' : L '
0 0.01 0.02 0.03 0.04 0.05

seconds

Figure 4.7 -Motor Phase Current and PWM Signal with 8 us time Pulse Constraint

In Figure 4.7 the timing constraint was set at 8,5. However, the times tn and 2(tc-tu)
of the PWM signal were not less than 81.13. The phase current appears relatively sinusoidal

with an amplitude of 0.7 amps.

Next, the pulse time constraint was increased to 9 us. As seen in Figure 4.8, the pulse

“on” and “off” constraints had an effect on the PWM signal. The modified PWM signal

29

introduces harmonics on the phase current. As the result Of the harmonics, the motor

draws more current.

 

 

 

 

 

 

 

 

 

 

 

‘9 2 v v . .
Q C
E
a. 0 ,
9.- .
.2 J l A; A
0 0.01 0.02 0.03 0.04 0.05
g seconds
0 10 v v v v
> e o e
5 C O
3
Q
0 0.01 0.02 0.03 i 0.04 0.05
seconds

Figure 4.8 -Motor Phase Current and PWM Signal with 91.1.: Time Pulse Constraint

 

 

 

 

 

“ 2 U U V U
a O
E 1
a
. 0
2

d

.2 A A A A

0 0.01 0 02 0 03 0 04 O 05

seconds

 

PWIM.VOHI

  

__‘_-

O 001 002 003 004 005
seconds

 

 

 

Figure 4.9 -Motor Phase Current and PWM Signal with 10115 Time Pulse Constraint

30

For implementing the control program, the speed Of the motor was needed. From
Figure 4.1, a counter is used to count the number of clock pulses between encoder pulses.
This sixteen bit time is serially uploaded to the DSP simultaneous as timing information
is downloaded.

The clock used to count out timing pulses is supplied by the DSP. The FPGA clock
is fraction of the serial output clock, 3.25 MHz.

The total FPGA program requires 379 combinational logic block function generators,
15 HO blocks and 297 combinational logic block flip-flops . The program was able to fit

onto the Xilinx 4005 chip, which contains 5000 gates.

Chapter 5

INDIRECT ROTOR FLUX FIELD ORIENTATION

Due to the nonlinearity and mathematical complexity of an induction motor, the d.c.
motor has been favored over the induction motor in terms of control response. However,
it has been shown that by transforming the mathematical equations from the stator
coordinates to rotor flux coordinates the equation of the induction motor become
uncoupled. This simplification allows for an input-output relationship similar to the d.c.

motor.

5.1 MATHEMATICAL DESCRIPTION OF INDUCTION MOTOR

The nonlinear differential equations which describe the behavior of an induction
motor are:

. dir d . .
err + L; + b.2703 exp(— 1P8» = 0

(5'1)
Rsis + Ag:— + 5&0} exp( 1P8» = u: (5-2)
I 51—01 = "Id — nu. = 3 PL». IIu[is(ir exp(j£) )] — m1. (5'3)
dt 3
513:0, (54)
(I!
Where:

8 is the rotor position
0), is the rotor speed

32

to, is the rotor speed

mt], driving torque

mL load torque

J total inertia of drive

Lm mutual inductance

Ls stator inductance per phase

I.r rotor inductance per phase

Rs stator winding resistance per phase
Rr rotor winding resistance per phase
P pole pair

i, space vector of stator current

i,(t) = i,,(t) + i,2(t)e‘2"’3 + i83(t)ei4"3 (5-5)
i, space vector Of rotor current
i,(t) = i,1(t) + i,,(t)eiz*’3 + i,3(t)ej4“’3 (5-6)
as space vector of stator voltage

u.(t) =u..(t> +u.2(t)e‘2"3 +u.3(t>e“"3 (54)

As seen in equations (5-1)-(5-3), there exists a complex relationship between the
voltage input a, and m], and uh, electrically developed torque and rotor flux respectively.

Because Of this coupled and complex relationship between inputs and outputs of an

induction motor, d.c. motors have been favored over induction motor in terms of output
response. The relationship between input and output, 1., and m‘L, of a separately excited

d.c. motor is

meL= k if ia (5-8)

33

5.2 SIMPLIFICATION OF TORQUE EQUATION

In 1971 Blaschke [7] showed that by a coordinate transformation to rotor field
orientation, the input-output relationship Of a induction can be made to emulate the input-
output relationship of a separately excited d.c. motor. The rotor flux field is characterized

by the space vector In, a sinusoidal flux wave rotating in the airgap. The rotor flux vector,

uh, can be represented by i,,.,(t), the magnetizing current.

(5-9)

 

imr(t) = \V

Lr

 

 

Figure 5.1 -Equivalent Circuit of induction motor

The i..,(t) vector rotates at angular speed of (om, relative to the stator reference

frame.

£2 = (D'nr(t) (5-10)
dt

In the rotor flux field coordinates, both the stator current and voltage space vectors,

i,(t) and u,(t), can be decomposed into two orthongal parts: isd, isq and usd, usq.

is(t)e'j' = isd + jisq (5-11)

us(t)e'j" = usd + jusq (5-12)

As shown in Figure 5.2, the current isd is proportional to im. In the rotor flux field
orientation the developed torque is

5-13
mcL = k imr isq 214a ( )

= 3(1+ Or)

 

 

\
// \
/ is \
/ \ rotor axis
/ \
/ \
/ \ car ‘1,
i \ mr
sq \ .
00 rotor flux ans
3 mr
isd
/ 8 p
stator OXIS a

 

Fig 5.2 -Stator, Rotor and Rotor Flux Coordinates

35

The uncoupled dynamic equations of the induction motor in the rotor field

orientation are:

 

 

 

 

 

 

 

L. d(i.d) _ um , L. d(i....)
’E d: +'“_E+mofil’q_(l—°)7 ,1, (5-14)
035th” +1.“! = us"! -makisd —(1—O’)£im
R: dt R: R; R: (5-15)
—L4 do") +13... = in (5-16)
R, dt
—d(p) + w = LI” + or» (5-17)
dt Lrlmr
d 0” 2L» 5-18
I Elt)="leL—m1=kimrisq—Inl k=3(l+O-r) ( )

From equation (5-13), the expression for the developed toque, appears similar to the
torque expression of a separately excited d.c. motor, equation (5-8). Analogous to the d.c

motor field current, im, is maintained at maximum level. Thus, the torque is controlled by

rsq.

Chapter 6

CONTROL SCHEME

Emulating the torque control scheme of separately excited d.c. motor, the rotor flux
of the induction motor is maintained at maximum level, while isq is varied accordingly.
Therefore, two feedback loops are maintained, the isd loop, which tracks a constant
reference flux and the isq loop, which tracks torque and speed inputs. The output of the
control loops are usd and usq. However, the first step of the control scheme is the

transformation to rotor flux field coordinates.
6.1 TRANSFORMATION INTO ROTOR FIELD COORDINATES

As Shown in Figure 6.1, the motor stator currents are transformed from the three phase

reference frame to the complex quadature reference frame.

isc = 'isa ' isb (6'1)

[ta] 1 ‘1) 01 'f“
= _ lsb
. —— 6-2
as O {—3 {—3 i“ ( )

The complex quadature currents, in and in, along with the rotor speed to, are the inputs

into a second order rotor flux observer.

36

37

 

cove:

9w

 

 

 

AI
gmwsm>c all
Al

 

:39

 

 

 

 

 

\V ‘7

 

 

 

 

37'

w \r xiv

 

 

 

X
3
LL

 

 

 

‘V

 

 

 

 

 

 

 

 

Figure 6.1 -Schematic of the Control Scheme [8]

38

6.2 SECOND ORDER FLUX OBSERVER

The key to the rotor field orientation control is knowledge of the position of the space
vector uh. With direct rotor field orientation control, Hall Effect probes measure the

actual flux in the airgap of an induction motor. However, for indirect rotor field
orientation control, the position of the rotor flux space vector is indirectly measured.
One way to determine, indirectly, the rotor flux space vector is by implementing a rotor
flux Observer in the stator coordinates.

The rotor flux observer is described in the stator coordinates as

 

 

d(\v'a) R, R, ,
=-— 'a- ' +—Ln a
d: aw paw " L. ' (6-3)
d—(‘V-i)"-& 'b-i- (Dr ' + r Lnib
d: L)" 9 W ° L, (64)

where w‘. and ‘V‘b are estimates of rotor flux in the stator reference frame. The magnitude

and angle of the rotor flux space vector are

 

w" = J01“ *w'a+\y'b*\y'b) (6’5)

p’: aICtan(\l"b/\v'a) (6'6)

39

Defining the estimate error as e s = w} - M, the error estimation is exponentially

stable for a constant rotor resistance and has an upper ultimate bound for a nominal
resistance [9].
With the estimated position of 01,, the complex quaduature stator currents can be

transformed into isd and isq.
isd = cos(p) sin(p) isa (6-3)
isq - sin( p) cos( p) in,

The decoupled equation (5-13) and (5-14) are rewritten with the outputs in terms of

 

 

 

usd = Rsisd + 03L: (“I“) — moms, + (1 - a)L. do”) (6“)
dt dt
“:4 = Rsisq +osls (12:1) +(I}OLsisd +(l-O')L.imr (55)

From equation (64), usd is denominated by isd Therefore, with a isd error as the input,

a proportional and integral (PI) controller produces a reference usq.

40

 

id , d ref
ref PI | 5
)O 9 Controller
T ia

 

Figure 6.2 -usd, isd relationship

Similarly, the output usq is dominated by isq term.

 

i O u
q ref Pl q ref
)0 9 Controller
T,

 

Figure 6.3 -usq, isq relationship

6.3 Transformation into Stator Coordinates

The voltage components usq and usd are transformed back into the stator reference

frame by the inverse coordinate transformation.

ua _ cos(p)-sin(p) an
up _ sin(p) cos(p) um (6-6)

Finally the complex quadauture stator voltage are transformed into three phase form.

30 1 _
“ -1 J3 In] (6-7)
usb -' — ‘—

0
2
2

H

—_£b

 

 

2
“3c —
2

h d

Chapter 7

RESULTS

The purposed control scheme was simulated in Matlab in order to determine gain
values for the PI controllers. Experimentally, a 1/ 12 hp induction motor was used to test
the PWM and control program. A dc motor supplied the load to the induction motor to

test speed control response.

7.1 INDUCTION MOTOR PARAMETERS

A small 1/12 horsepower induction motor was chosen in order to protect the
inverter’s IGBTs. If there was a problem with the program that caused a short across an
IGBT leg, the lower current would be less likely to damage the IGBTs. The motor
parameters were determined by measuring the power during a no-load test and a blocked

rotor test.

Table 7.1 -Motor Parameters

 

42

43

7.2 SIMULATION OF CONTROL SCHEME

Simulations were done using Matlab. The motor, the control scheme and the flux
Observer were modeled in a continuous fashion. Therefore the model had a total of

thirteen continuous states, see Appendix B for simulation program.

 

200--------

a

radians per second
8

 

 

 

 

0 5 10 15 20 25 30
seconds

Figure 7.1 -Reference (dashed) and actual (solid) speeds with wref=l80 rads/sec

7.3 EXPERIMENTAL SETUP

 

Figure 7.2 -Experimental Setup

A 40 volt separately excited d.c. motor acted (though a belt and pulley) as a load on
the induction motor. Two current sensors measured the phase currents of the motor. The

voltage-fed inverter was supplied by a 3-phase 208 V”, source

45

7.4 SPEED REGULATION WITH DISTURBAN CE

With switching frequency of 24kHz, the speed command for this experiment was 180
radians per second. Once the motor reached steady state a load was applied by the d.c

motor. After retaining the command speed, the load was removed.

 

 

 

ooooooooooooooooooooooooooooooooooooo

fig
.-—;
l
I.
|

 

radIans per second
8
3%
< 0.0

 

 

 

150................. ---:' --------------------------

m, .................... .................... .. .
50 .................... é. ........................
00 1.0 20 30 4:0 50 60 7‘0 80

Figure 7.3 -W,,f = 180 rad/s with load applied and removed

46

7.5 STEP INPUT, SPEED COMMAND

In this experiment, the initial speed command was 180 radians per second. After
reaching steady state the speed command (step input) became 4O radians per second. For
the first run, no load was applied to the motor. In the second run, an initial load was
applied to the motor. Again the switching frequency was 24kHz. The d.c. motor was

supplied 40 volts. See Appendix A for program.

 

 

g

 

 

 

 

 

8150.. .
8 .
a) e
2 I
a, .
a I
8100’ """"""""""""""""""""""""" "'
.s -
'o I -
8 ;.
. II .
0?""o'"°°l'""o'""o'.' “o """"""""" "'
m, —-:---:--—.—-.+ 3.7“,
: : : :ll ..
. . . . I.
0 i i i i L i 1 i
0 10 20 30 40 50 so 70 30

seconds

Figure 7.4 -Without load (dashed) and without load (solid)

47

7.6 FREE ACCELERATION

The gain values Of the PI controller were adjusted to provide a fast response to a
speed command, over a range of speeds from 20 to 220 radians/second. N0 load was

applied.

 

 

 

 

 

 

 

 

 

250 ........ ....... 5 ........ 5 ........ f ........ 3 ....... ,
° ' ' 220 I s
200""' '3'" "°‘. °°°°°° 3° ------- E -------- I ....... d
.2 . o o z 11 f?!
8 . : : : :
8150 ....... :. ....... :...l40rad/.s ...... ..
8 . A vv-v w: .. waTv‘V "ié‘v‘v VT‘V V‘VW‘
a, . . . e
g E
"""""""" ; 111:.“1;;‘8Iast1'
50" "
. 20rad/SI
o L._A n n L a n
0 5 10 15 20 25 30

seconds

Figure 7.5 -Free Acceleration, w“; 20-220 rads/sec

48

7.7 PROGRAM TIMING

Table 7.2 is an estimation of the total time of the DSP program. The total time is
broken down between program parts. For example, the time of the DSP SPWM program

is 9.7118, which is 26.7 % of the total program time.

Table 7.2 -DSP Control and SPWM program timing specifications

 

The actual program time was 40.1 us, because the IGBTs were rated at 25kHz

switching frequency .

49

Table 7.3 is an estimation of the total time of the FPGA program. All timing

simulations were conducted using Xilinx’s ViewSim program. However, once the data is

latched by

Table 7.3 -FPGA SPWM program timing specifications

 

’ ‘5‘ Time Approximation ]
L 14.5ns |

 
 

the FD32RE latch (Figure 3.1) the most significant delay in the critical path delay is from
the Adder/Subtracter component which perform the Operation team... All other
mathematical operations occur simultaneously with the outputting of the PWM pulse.

Thus, relative to the DSP, the FPGA’s time delays are insignificant.

Chapter 8

SUMMARY AND CONCLUSIONS

The main goal of this thesis was to explore the feasibility Of implementing an
induction motor control program and the Pulse Width Modulation program on separate
dedicated hardware. The benefits of this hardware partitioning would be the
computational alleviation of the control processor. Once freed of the responsibly of the
PWM program, the control processor could implement more sophisticated control
schemes or increase inverter switching frequency, for improved response.

Due to the memoryless and feedback independent characteristics of the PWM
program, a field programmable gate array was chosen as the target hardware for PWM
implementation. Although total program separation was found to be impractical, partial
separation between the control program and PWM program significantly decreased
processor computational time allowing for higher frequency inverter switching.

An indirect rotor flux field orientation control scheme was chosen to test the idea Of
program partitioning. Experimental results of Chapter 7 are discussed in this chapter.

An additional benefit of the PWM partitioning is the placement of time constraints
on the PWM pulse without a computational time penalty. The time constraints on the
PWM pulse ensures operation within inverter specification. However it was found that
the modification to the PWM signal, from pulse time constraints, resulted in increased

harmonic effect on stator currents.

50

51

8.1 CONTROL AND PWM PROGRAM HARDWARE ALLOCATION

Total implementation of the Space Vector Pulse Width Modulation algorithm on an
FPGA was found to be impractical. Although the SPWM algorithm appears more
comparable to a combinational logic circuit as Opposed to the sequential circuit nature of
the control program, the SPWM consists of several arithmetic Operations which if
implemented in a combinational fashion would not be cost effective. A FPGA CORDIC
processor was developed to handle the trigonometric operations of the SPWM algorithm.
However, the CORDIC algorithm and its controller consumed over eighty-five percent of
the CLBS of the targeted FPGA with only eight bits of resolution. A trigonometric look-
up table was not considered because handling an addressable matrix look-up table is more
applicable to a microprocessor; thus creating a complex, two—microprocessor system.
Therefore, the responsibility Of the SPWM trigonometric operation was shifted back to
the control processor. This shift eliminates the inherent redundancy in performing
trigonometric calculations in a system with total hardware separation between control
and PWM programs.

In a total hardware separated system the control processor must perform an
arctangent operation to find the voltage space vector angle. The angle is passed to the
FPGA, where the cosine of the angle is calculated. With the partially separated system the
actual angle of the voltage space vector is never calculated, rather the cosine and sine Of
the angle is calculated with a simple multiplication Operation, eliminating the timing

consuming task of performing the arctangent Operation.

52

With the partial PWM hardware implemented system, an inverter switching
frequency of 24 kHz was achieved, while the applying an indirect rotor flux field

orientation control scheme.

8.2 INDIRECT ROTOR FLUX FIELD ORIENTATION CONTROL

The proven indirect rotor flux field orientation control scheme was chosen to test the
partial PWM hardware implemented system. The control scheme was first simulated in a
continuous fashion, varying PI controller gain values for desired response. The actual
control was written using AT&T DSP32C assembly code. The control program required
three hundred lines of codes. In conducting experimental runs of Chapter 7, the focus was
less on the actual control response but more on the feasibility Of the overall system
structure. However, the fact that the system delivered desired control response is a

validation to the actual feasibility of the system.

8.2.1 SIMULATION VS. EXPERIMENTAL RESULTS

Simulation of the control scheme was conducted using MATLAB. Figure 7.1
shows the comparison between the actual response and simulated response Of the system.
The response profile of reaching the desired speed Of 180 rad/s differs slightly between
the actual and simulated results. This difference may be due to the variation in the

measured motor parameters, implying the need for a more robust control scheme. Also,

53

the simulation did not take into account the inertia Of the encoder, whose effect may not

be insignificant for such a small motor.

8.2.2 EXPERIMENTAL RESULTS

Figure 7.3 shows the control program correcting for an applied load. The settling time
is approximately seven seconds. After ten seconds the load is removed and again the
controller performs a correction.

Figure 7.2 shows the controller responding to a speed change command. The set
speed was changed from 180 to 40 rad/s. The first run was without a load. The settling
time is approximately twelve seconds with an overshoot of 10 rad/s. For the second run
an initial load was applied to the induction motor. As expected, the settling time of the
speed change increased, approximately 23 seconds. There is increased noise on the speed
signal of the second run. This is probably caused by the increased current which created
increase noise on the speed sensor.

Figure 7.5 shows the speed range capability of the controller. The speed PI Controller
gains k, and kp were increased for faster response. No load was applied. The minimum

speed Obtained was 20 rad/s.

54

8.3 SPWM PULSE TIME CONSTRAINTS

Imposing time constraints on the PWM pulse results in a distorted PWM signal
which, in turn, results in distorted sinusoidal voltage waveforms. However, for increased
switching frequencies, pulse constraints are especially necessary. Faster switching results
in greater occurrences of smaller pulse “on/off" times, putting the inverters IGBTs more
at risk. Decreasing modulation can also act as a pulse time constraint. However,
maximum voltage utilization from the inverter is usually desired. Due to the lack of a
computational time penalty, imposing time constraints via the FPGA SPWM program is

desirable.

8.4 FUTURE DIRECTION

Assuming increasing computational speeds and decreasing cost of processors, full
implementation of a PWM algorithm on a FPGA should not be pursued even with the
introduction of FPGA dsp tools.

The idea of varying the switching frequency should be explored. The primary
disadvantage of increased switching frequency is increased switching power loss. An
optimal scheme would have switching frequency increase for transient response and have
the switching frequency decrease for steady state operation. The DSP SPWM developed

for this thesis has the ability to change tc, the switching period, from pulse to pulse.

APPENDIX A

APPENDIX A

The DSP Code

The DSP Code is written in AT&T’s DSP32C Assembly language. The program is

composed of the indirect rotor flux orientation control program and the partial SPWM

program.

55

56

I*****************************************************************************/

/* INDIRECT ROTOR FLUX FIELD ORIENTATION CONTROL PROGRAM

/* WITH PARTIAL SPWM PROGRAM (cc18.s )
/* by
/* John W. Kelly

/* Copyright 1997

*/
*l
*l
*l
*/

l*****************************************************************************/

#define ivtpe

.global _start

r22e

.global _control

.global _end
. global _intr

.rsect ".start"
goto _start
nop

.rsect ".prog"
.align 4

start: ivtpe = itable
ioc = 0x020fd3

r1 =Ox4432
pcw = r1

r2e = Ox200008

r1 = Oxfe66
*r2 = r1
nop

r13e = Ox60000

/* Disable any Serial DMAs */
/* 32 bit word output */
/* output rate 6.25 Mhz */
/* OLD out */
/* ILD in *l
/* OCK out *I

/* interupt time 41us*/

 

 

 

/* Start Loop = */
/* *l
l* *I
_control: r2e = _gg l* */
r3e = _posl /* */
*r2 = a1 = *r3 /* */
nop
nop

It

 

*/

 

57

 

 

 

 

 

 

 

 

 

 

 

 

/* *l
/* m Stator Current Measurments r *l
/* ---*l
/* measurment of stator current of phases A and B */
/* calculation of stator current in phase C */
/* *l
/* fast LEM current sensors */
/* *l
/* cur_a = float(channel A)*f_in*f_cur + offset */
/* cur_b = float(channel B)*f_in*f_cur + Offset */
/* cur_c = - cur_a - cur_b */
/* */
rle = Ox200000 /* analog channel A */
r2e = 0x200004 /* analog channel B */
r3e = f_in /* 1V * f_in = 1.0 */
r4e = cur_a l* current phase A */
r5e = cur_b l* current phase B */
r6e = cur_c /* current phase C */
a0 = fioat(*r1) /* read analog channel A */
a1 = float(*12) /* read analog channel B */
r7e = f_ino

a0 = *r7 + a0 * *r3

a1= *r7 + a1* *r3

r9e = offs_2

r8e = f_cur2

*r4 = 30 = *r9 + a0 * *r8 /* store cur_a */
*r5 = a1 = *r9 + a1 * *r8 /* store cur_b */
r7e = loops

nop

*r4 = a0 = a0 * *r7

*r5 = a1 = a1 * *r7

nop

*r6 = a2 = -a1 - a0 /* store cur_c */
nop

nop

/* 23 *l

/* ------—-——-—- -———---- *l

/* *l

/* -----—--— Speed Measurement = */

/"' *l

/* The number of clock ties between speed encoder pulses is */

/* continuously uploaded to the DSP. The resolution of the encoder */

/* is 1024 pulses per rev. The Speed Equation: */

/* wr = (2*pi/1024)*(clk freq] clk tics) */

/* *l

33 = f10at(ibuf) /* read serial buffer */

rle = _wr_new

58

r2e = _wr_oldh /* Upper speed limit
r4e = _wr_old /*

r3e= _zero

a2 = *r3

if (ale) goto _SdeerO /* count = zero
al = a2 /* speed = zero
r2e = _2n /* dummy varible

*r2 = a2 = seed(a3) /* -- Inversion Routine: _invf --
r3e = _invfa I * Source: AT&T Appl. Soft. Lib.
nop /* replace nop of _invf
a0=*r3++-a3 *a2 /*_invf

a1 = *r2 * *r3-I-I- /* _invf

a2=*r3++-a3* *r2 /*_invf

a0 = *r3-H- + a0 * a0 /* _invf

a1 = a0 * a1 /* _invf
a2 = a2 * a1 /* _invf
nop /* replace retum(r14) of _invf

a0=a2+a0*a1 /*_invf

r2e = _wr_oldh /* (nop) Upper speed limit
r4e = _wr_old /* (nop)

r6e = _2pi_fclk /* (nop) (2*pi/1024)*6.25e6
I"r1 = a1 = a0 * *r6 /* (2xpi/1024)x6.25e6/_epulse_new
nop

_Sdeero:
a2 = *r4 /* <-I
r3e = _wr_oldl /* I Lower speed limit
a0 = *r2 - a1 /* |<-I Upper limit - speed
a3 = *r3 - a1 /* I I<-l Lower limit - speed
if (aeq) goto _LL /* <-l I l WrOld = O
r6e = _spd_tol /* l | Speed tolerance

LL:

if (alt) goto _OldSpd l*<—l I Upper limit-speed<0
nop /* a2=a0+a1 */

nop /* I

nop

if (agt) goto _OldSpd /* <-I Lower limit-speed>0
nop /* a2=a3+a1*/

nop

nop

nop

a2 = *r1

nop

_OldSpd: nop

nop
nop
*r1 = al= a2
nop

*/
*l

*l
*l

*l
*l
*l

*l

*l

*l

*/

*/

*I

*l

*/

*l

*l
*/

*/
*/

*/
*/
*l
*l

*l
*l
*l

*l

*/

59

nop
*r2 = a3 = a1 + *r6 * a1 /* Upper speed limit
*r3 = a0 = a1 - *r6 * a1 /* Lower speed limit

 

 

 

 

*/
*l

*/

*l
*l
*l
*l
*l
*/
*l
*/
*l
*/
*l
*/
*/

nop
nop
*r4 = a1 = a2 /* WrOld = WrNew
nop
/* 56 *l
/* —————————-——-—.————————————————-—————————————— III,
III
/* ---- 3=>2 Transformation -
[It
/* 3-phase to 2-phase transformation
[11!
/* ia = 2/3*cur_a - cur_b/3 - cur_c/3
/* ib = l/sqr(3)*(cur_c - cur_b)
/*
rle = _isa_new /* stator current q_axis
r2e = _isb_new /* stator current d_axis
r3e = _ _fac /* 2/3 1/3 1/sqr(3)
r4e = cur_a /* current phase A
r5e == cur_b /* current phase B
r6e = cur_c /* current phase C

a0 = *r3-H- * *r4

a0 = a0 - *r3 * *r5

*r1 = 30 = a0 - *r3++ * *r6 /* ia=2/3*a - b/3 - c/3
a1 = *r3 "‘ *r6

*r2 = a1 = a1 - *r3 * *r5 /* ib=llsqr(3)*(c-b)

*/

*l

*/

*/

 

 

 

nop

nop
/* 13 */
[It __._..
/* ISD LOOP
[It
/* = Flux Observer

 

*/

*/

 

/* psiathew = -ITr*psiahNew - p*WrNew*psithew + ITr*Lm*IsaNew
/* psibthew = -ITr*psithew + p*WrNew*psiahNew + ITr*Lm*IsbNew

r3e = _pole
r7e = _wr_new

a1 = *r7 * *r3 /* pole*WrNew

r4e = _th_new
r5e = _Yah_new

a2 = -a1 * *r4 /* pole*WrNew*thNew

*/
*l

*l

*l

60

a3 = a1 * *rS
r3e = _I'Tr

/* pole*WrNew*YahNew

a1 = a2 - *r3 * *r5 /* ~pole*WrNew*thNew - I'Tr*YahNew
a2 = a3 - *r3 * *r4 l* +pole*WrNew*YahNew - IT r*thNew

r3e = _c1 /* IT r*Lm
r5e = _isa_new
a3 = *r5 * *r3 /* (ITr*Lm)*Isanew

r4e = _isb_new

 

*/

*l

*l

*l

*/

 

 

 

 

 

a0 = a3 + a1
/* -pole*WrNew*thNew-I'Tr*YahNew+(ITr*Lm)*Isanew */
a1 = *r4 * *r3 /* (ITr*Lm)*Isbnew */
nop
a3 = a1 + a2
/* +pole*WrNew*YahNew-I'Tr*thNew+(ITr*Lm)*Isbnew */
r3e = _time
a1 = *r3 * a0 /* HT*(Yathew) */
a2 = *r3 * a3 /* HT *(Y bthew) */
r4e = _Yah_new
*r4 = a3 = a1 + *r4 /* Yahold+HT*(Yathew) */
r5e = _th_new
*r5 = a1 = a2 + *r5 /* thold+HT*(thdNew) */
nop
nop
/* 25 *l
l* *l
/* *l
/* Coordinate Transformation AB => DQ */
/* *l
/* */
a2 = a3 * a3 /* Yahnew"2 */
a0 = a1 * a1 /* thnew"2 */
nop
rle = _invsqr_in /* */
*r1 = a1 = a0 + a2 /* Yd"2 = Yah"2 + th"2 */
call _invsqr (r21) /* Call Inverse of Square Root */
nop
r9e = _invsqr_out /* 1/(Yd)".5 */

nop

61

a3 = *r9

r2e = _2n I* dummy varible

*r2 = a2 = seed(a3) /* -- Inversion Routine: _invf --
r3e = _invfa /* Source: AT&T Appl. Soft. Lib.
nop /* replace nop of _invf

a0=*r3++-a3 *a2 /*_invf
a1 = *r2 * *r3-H- /* _invf

a2 = *r3++ - a3 * *r2 /* _invf
a0 = *r3+—I~ + a0 * a0 /* _invf

a1 = a0 * a1 /* _invf
a2 = a2 * al /* _invf
r7e = _Yd_new /* replace retum(r14) of _invf

a0=a2+a0*a1 /*_invf

r2e = _Yah_new

r3e = _th_new

r4e = _cos_pr

r5e = _sin_pr

*r7 = a3 = a0 /* Store Yd

*r4 = a1 = *r2 * *r9 /* cosPr = Yahnew / Yd
*r5 = a2 = *r3 * *r9 /* sinPr = thnew / Yd

r2e = _isa_new
r3e = _isb_new

a0 = *r2 * a1 /* IsaNew * cosPr
a3 = *r3 * a2 /* IsbNew * sinPr
nop

r6e = _isd_new

*r6 = a0 = a3 + a0 /* Isquw=IsaNew*cosPr+IsbNew*sinPr
nop

a3 = a2 * *r2 /* -IsaNew * sinPr
a0 = a1 * *r3 /* IsbNew * cosiPr

r7e = _isq_new
*r7 = a2 = a0 - a3 /* Istew=—IsaNew*sinPr+IsbNew*cosPr

*/
*l
*I

*/

*l

*l

*l

*/

*l

*/
*/

*/

*l

*l
*/

*l
*l

*l

*l

*l

*/

_*/

 

 

*l
*/

 

 

nop
nop
/* 45 + 34*/
[It ———————— __._
[It
/* = Flux Controller
[It
[it

 

*/
*/

62

r2e = _Yd_new
r3e = _Yd_ref_new

a0 = *r3 - *r2 /* YdError = YdRefNew - YdNew
nop

r5e = _time
a2 = a0 * *rS /* H*YdError
nop

r6e = _Yd_int_old
*r6 = a1 = a2 + *r6 /*YdIntOld = YdIntOld+H*YdError

r2e = _isd_kp

a2 = *r2 * a0 /* YdError * Kp
r3e = _isd_ki

a3 = a1 * *r3 /* YdIntNew * Ki
nop

a0 = a3 + a2

r4e = _ILm /* 1/Lrn

r5e = _isd_ref_new
*r5 = a1= a0 * *r4 /* Yd/Lm = Imr

 

 

 

 

nop
nop
nop
/* 21 *I
[it
/* Isd Current Controller
It
/*
r2e = _isd_new
r3e = _isd_ref_new
a0 = *r3 - *r2 /* IsdError = IstefNew - Istew
nop
r5e = _time
a2 = a0 * *r5 /* H*IsdError

r6e = _isd_int_old
*r6 = a1 = a2 + *r6 /*IsdIntOld = IsdIntOld+H*IsdError

r2e = _usd_kp
a2 = *r2 * a0 /* IsdError * Kp

*/

*/

*l

*/

*I

*l

*/

*/
*l
*l
*/

*l

*l

*l

*l

 

 

63

 

 

 

 

 

 

 

 

 

 

 

r3e = _usd_ki
a3 = a1 * *r3 /* IsdIntNew * Ki */
r4e = _usd_ref
*r4 = a0 = a3 + a2
nop
l* 15 *l
/* -- *l
/* *l
/* ISQ LOOP = *l
/* *I
/* Speed Controller */
/* --*l
/* */
r2e = _wr_new
r3e = _wr_ref
30 = *r3 - *r2 /* WrError = WrRef-WrNew */
nop
r5e = _time
a2 = a0 * *r5
r6e = _wr_int_old
*r6 = a1 = a2 + *r6 /*WrIntOld=WrIntNew=WrIntOld+H*WrErrorNew */
r2e = _te_kp
a2 = *r2 * a0 /* WrError * Kp */
r3e = _te_ki
a3 = a1 * *r3 /* WrIntNew * Ki */
r4e = _te_ref_new
*r4 = a0 = a3 + a2 l*TeRefNew=WrErrorNew*Kp+WrIntNew*Ki */
nop
nop
/*l6 */
l* */
I* = Torque Controller */
/* *l
/* te = 1.5*p*Lm*Yd*Isq/Lr */
/* */
r2e = _isq_new
r3e = _Yd_new
a0 = *r2 * *r3
nop
r4e = _k /* 1.5*Pole*Lm */
a1 = a0 * *r4 /* TeNew = 1.5*p*Lm*Yd*Isq/Lr */

/*
[It
[33
/*

nop

r3e = _te_ref_new

a0 = *r3 + a1 /* TeError = TeRef-TeNew
nop

r5e = _time

a2 = a0 * *r5

nop

r6e = _te_int_old

*r6 = a1 = a2 + *r6 /*TeIntOld=TeIntNew=TeIntOld+H*TeErrorNew
r2e = _isq_kp

a2 = *r2 * a0 /* TeE'rror * Kp

r3e = _isq_ki

a3 = a1 * *r3 /* TeIntNew * Ki

r4e = _isq_ref_new

*r4 = a0 = a3 + a2 /*IquefNew=TeErrorNew*Kp+TeIntNew*Ki

nop
nop
nop

Isq Current Controller

 

 

r2e = _isq_new

r3e = _isq_ref_new

r7e = _isq_error

*r7 = a0 = *r3 - *r2 /* Iqurror = IquefNew - Isquw
nop

r5e = _time
a2 = a0 * *r5 /* H*Iqurror

r6e = _isq_int_old

*r6 = a1 = a2 + *r6 /* IsqIntOld=IsqIntOld+H*Iqurror

r28 = _usq.kp

a2 = *r2 * a0 /* Iqurror "‘ Kp
r3e = _usq_ki

a3 = a1 * *r3 /* IsqIntNew * Ki
r4e = _usq_ref

*r4 = a0 = a3 + a2

nop

*/

*l

*l

*l

*I

*l
*l
*l
*l

*l

*/

*/

*l

*l

65

 

 

 

 

 

 

 

 

 

 

nop
nop
/* 18 *l
/* — .. *I
[an *I
/* m = *I
/* *l
/* - Voltage Coordinate Transformation */
/* *l
/* Vsa = UsteP'cos_pr-UqueP"sin_pr */
/* Vsb = Uquet‘cos_pr+Ustet"‘sin_pr */
/* */
r2e = _usq_ref
r3e = _sin_pr
a0 = *r2 * *r3 /* Uquef * sin_pr */
r4e = _usd_ref
r5e = _cos_pr
a1 = *r4 * *r5 /* Ustef * cos _pr */
a2 = *r3 * *r4 /* Ustef * sin _pr */
a3 = *r5 * *r2 /* Uquef * cos _pr *l
r7e = _Vsa
*r7 = a0 = a1 - aO /*Vsa = Ustet‘cos_pr-Uquef*sin_pr */
r6e = _Vsb
*r6 = a2 = a3 + a2 /*Vsb = Uquet‘tcos_pr+Ustef*sin_pr */
nop
nop /* ? *l
/* 14 *l
/* *l
/* *l
/* — Store Speed & Current */
r3e = _done
a1 = *r3
r7e = _wr_new
r4e = _count
r5e = _posl /* initial = 1 then =0 */
*r4 = a2 = *r4 + *r5
r2e = _event
if (agt) goto _ok
nop
a3 = *r2 - a2
nop
r6e = _storcnt
r3e = _zero

if (agt) goto _ok
nop

66

*r6 = a2 = *r6 + *r5
*r13++ = a1 = *r7

 

 

 

 

 

 

 

nop
r9e = _stor
a3 = *r9 - a2
nop
*r4 = a0 = *r3
r6e = _done
if (agt) goto _ok
nop
*r6 = a1 = *r5 /* _stposl = O *l

_ . nop

/* 28 *l

/* Start PWM Program *I

/* */

/"‘ */
r6e = _Vsa
a0 = *r6
r7e = _Vsb
a2 = *r7
nop
a3 = a0 * a0 /* Va"2 */
a1 = a2 * a2 /* Vb"2 */
nop
rle = _invsqr_in /* Vd */
*r1 = a2 = a3 + a1 /* _Vd"2 = Va"2 + Vb"2 */
call _invsqr (r21) /* */
nop /* */
rle = _invsqr_out /* */
r2e = _Vsa /* */
r3e = _cosV /* */
*r3++ = a1 = *r1 * *r2 l* cos(a) = Vsa/Vd pt to _sinV */
r2e = _Vsb /* */
*r3 = a2 = *r1 * *r2 /* sin(a) = VsbNd */
nop

/* 12434 = 45 *l

I* —-—= Calculate to and factor which includes voltage modulation */

[It II!

I. .;
rle = _fout /* */
r3e = _2n_fclk /* samples/folk */
a3 = *r1 * *r3 /* fout*samples/fclk */
rle = _invsqr_out /* */
r5e = _cosV /* for "Determine Sector" was nop */
a3 = a3 * *rl /* fout*sampleslfclk/Ud */
r2e = _2n /* */

 

67

 

 

 

 

 

 

*r2 = a2 = seed(a3) /* INVERSION OF PREV. LINE */
r3e = _invfa /* */
r6e = _sinV /* for "Determine Sector" was nop */
a0=*r3++-a3*a2 /* */
a1 = *r2 * *r3-H- /* */
a2=*r3++-a3**r2 /* */
a0 = *r3++ + a0 * a0 /* */
a1 = a0 * a1 /* */
a2 = a2 * a1 /* */
r4e = _tc /* point to _tc */
r3e = _factor /* r3 point to _factor */
a0 =a2+a0*a1 /* store _tc */
rle = _invsqr_out l* rle points to l/Ud */
r8e = _pwm /* r8 points tp _pwm */
*r4 = a3 = a0 * *rl /* a2 = tc*fclk*Ud/Ud */
r1 1e = _m /* r5 pts to l/(Uret‘I‘sin(pi/3)/.86 */
*r3 = a0 = a0 * *rll /* tc*fclk/(Uret"‘sin(pil3)/.866 */
*r8 = a3 = int24(a3) /* store tc a0 = int(tc*fclk) */
/* —- 35 lines - *l
/* *l
/* Determine Sector */
/* *l
/* _cosV resides in a1 & _sinV resides in a2; last operation *I
/* */
a1 = *r5 /* "‘/
a2 = *r6 /* <-| */
r3e = _cos_pi_3 l"‘ l */
r2e = _sin_pi_3 /* I */
a3 = *r2 + a2 /* l <-l */
if (ale) goto _xx /* <-I I <-l */
a3 = a1 /* l<-I I l */
a3=*r2-a2 /*<-I II | */
nop /* I I l l */
a3 = a1 /* |<-| I I I */
a3 = a1 * *r2 /* sin(pi/3)*cos(a) l */
if (alt) goto _sec2 /* <-I I I I I */
a0 = a2 * *r3 /* cos(pi/3)*sin(a) I */
if (alt) goto _sec3 /* <-I l I I */
nop /* I l l */
goto _secl /* l I l */
_xx: a3 = a1 * *r2 /* sin(pi/3)*cos(a)<-l */
if (ale) goto _sec5 /* <-I I */
a0 = a2 * *r3 /* cos(pi/3)*sin(a) */
if (ale) goto _sec4 /* <-l */
nop /* */
goto _sec6 /* */
nop /* */
/*——-- max lines: 14 */
_secl: a0 = -a0 + a3 /*-cos(pi/3)*sin(a)+sin(pil3)*cos(a) */
r3e = _factor /* r3 points _factor */

a3=a2**r3
a0=*r3*a0
r2e=_half
al=a0+a3
r3e=_tc
a2=-al+*r3
r7e=_tu
r15=0x0001
a3=a2 **r2
r6e=_tw
r5e=_tv
a2=a3+a1
a0=a3+a0

*r7 = a3 = int24(a3)
*r6 = a2 = int24(a2)
*r5 = a0 = int24(a0)
r8e = _pwm + 1

r7 = *r7

r6 = *r6

r5 = *r5
*r8++r15 = r61
*r8++rlS = r51
pchtO _end
*r8 = r71

 

l*:

_sec2:

al=a0+a3
32=a0-a3
r3e=_factor
r2e=_half
a0=*r3*a1
a3= a2**r3
r5e=_tv
al=a3+a0
r3e=_tc
a2=-al+*r3
r6e=_tw
r7e=_tu
a0=a2 **r2
r15=0x0001
a2=a0+al
al=a0+a3

*r5 = a0 = int24(aO)
*r6 = a2 = int24(a2)
*r7 = a1 = int24(a1)

r8e = _pwm +1
r5 = *r5
r6 = *r6
r7 = *r7
*r8++r15 = r61

*r8+-I-r15 = r51

26 lines test w/ .5 O615232a

68

/* load _t2 with _factor*sin(_vang)
/* load _tl w/_factor*sin(pi/3-a)
/* r2 points _half
/* a1= _tl+ (_t2)
/* r3 points _tc
/* _tc -(_t1 + _t2) = _t0*2
[It
/* for address _pwm increment
/* _tu = a3 = _t0*2 ( *.5)
/*
Iii!
/* _tw = a2 = _t0 + _t1+_t2
/* _tv = a0 = _t0 +_tl
/* int24(tu)
/* int24(tw)
/* int24(tv)
/*
[It
/*
[It
I* tw to _pwm+l
/* tv to _pwm-+2
la]:
/* tu to _pwm+3

*/
*l
*l
*/
*/
*/
*/
*l
*/
*/
*l
*/
*l
*l
*l
*l
*/
*I
*/
*l
*l
*l
*l
*l
*/

 

/*cos(pi/3)*sin(a)+sin(pi/3)*cos(a)
/*cos(pi/3)*sin(a)-sin(pi/3)*cos(a)
/* r3 points _factor
/* r2 points _half

/* load _tl w/_factor*sin(pil3-a)

/* load _t2 with _factor*sin(_vang)
[Ill
/* al = _tl-I- (_t2)

/* r3 points _tc
/* _tc -(_tl + _t2) = _t0*2
/*

/*

/* _tv = a3 = _tO*2 ( *.5)

/* for address _pwm increment
/* _tw = a2 = _t0 +_t1+_t2
/* _tu = a0 = _t0 +_t2

/* int24(tv)

/* int24(tw)

/* int24(tu)

[’13
[III
/*

[III

/* tw to _pwm-+1

l* tv to _pwm-+2

*/
*l
*l
*l
*l
*l
*/
*l
*/
*l
*l
*/
*l
*l
*l
*I
*l
*l
*l
*l
*/
*l
*l
*/
*/

/*-——-

 

pcgoto end

*r8 = r71

27 lines test w/ 1.32745 01072323

 

sec3:

I*-—-—

sec4:

aO=-aO-I-a3

a0=aO-I-a3
r3e=_factor
a3 = a2 * *r3
a0 = -*r3 * a0
r2e=_half
a1= a0 + a3
r3e=_tc

a2 = -a1+ *r3
r5e=_tv

r15 =0x0001
a0 = a2 * *r2
r6e=_tw

a3 =aO+a3
a2= aO+a1
r7e= tu

*r5 = a0 = int24(aO)
*r6 = a3 = int24(a3)
*r7 = a2 = int24(a2)
r8e = _pwm +1

r5 = *r5
r6 = *r6
r7 = *r7

*r8++r15 = r61
*r8++r15 = r51

pcgoto _end
*r8 = r71

 

r3e = _factor
r2e = _half
a3 = -a2 * *r3
a0 = -*r3 * a0
r7e = _tw

a1 = a0 + a3
r3e = _tc

a2 = -a1 + *r3
r5e = _tu

r6e = _tw

a0 = a2 * *r2
r15 = OxOOOl
a2 = a0 + a1

al=a0+a3

*r7 = a0 = int(aO)
*r5 = a2 = int(a2)
*r6 = a1 = int(al)
r8e = _pwm +1

r7 = *r7

69

[Hit
/* tu to _pwm+3

*/
*/
*/

 

/*cos(pi/3)*sin(a)+sin(pil3)*cos(a)
/* r3 points _factor

/* load _tl with _fact0r*sin(_vang)
/* load _t2 w/_factor*sin(pi/3-a)
/* r2 points _half
/* a1 = _t1+ (_t2)

/* r3 points _tc

/* _tc -(__t1 + _t2) = _tO*2

[Ill

/* for address _pwm increment
/* _tv = a3 = _t0*2 ( *.5)

[all
/* _tw = a0 = _t0 +_tl
/* _tu = a2 = _t0 + _t1+_t2

[31!

l* int24(tv)

/* int24(tw)

/* int24(tu)

/*
[III
/*
[It

/* tw to _pwm+1

l* tv to _pwm+2

[It
/* tu to _pwm+3

26 lines test w/ 2.1745 21071f2a

/*-cos(pi/3)*sin(a)+sin(pil3)*cos(a)
/* r3 points _factor

/* 12 points _half

/* load _t2 with _factor*sin(_vang)
/* load _tl w/_factor*sin(pil3-a)

[It

/* a1 = _t1+ (_t2)

/* r3 points _tc

/* _tc -(_t1 + _t2) = _t0*2

/*

[It

/* _tw = a0 = _t0*2 ( *.5)

/* for address _pwm increment

l* _tu = a2 = _t0 +_tl+_t2

/* _tv = a1 = _t0 +_t2

/* int24(tw)

/* int24(tu)

/* int24(tv)

[11!
la]:

*/
*l
*l
*l
*l
*l
*/
*l
*/
*/
*l
*/
*l
*l
*l
*l
*/
*l
*l
*l
*/
*l
*l
*l
*l
*l
*l
*l
*l
*l
*l
*/
*l
*l
*l
*/
*l
*l
*l
*l
*/
*l
*l
*l
*l
*/
*l

[*m
sec5:

r5 = *r5

r6 = *r6
*r8-H-rlS = r71
*r8++r15 = r6l
pcgoto _end
*r8 = r51

26 lines test 3.2745 220b082a

 

a1= a0 + a3
a2 = a0 - a3
r3e =_factor
1'26 =_half
a0 = -*r3 * a1
a3 = -a2 * *r3
r7e =_tw
a1= a3 + a0
r3e =_tc

a2 = -a1 + *r3
r5e =_tv

r6e =_tu

a3 = a2 * *r2
r15 = OxOOOl
a2 = a3 + a1
a0 = a3 + a0

*r7 = a3 = int24(a3)
*r5 = a2 = int24(a2)
*r6 = a0 = int(aO)

r8e = _pwm +1
r7 = *r7

r5 = *r5

r6 = *r6
*r8++r15 = r7]
*r8-H-r15 = r51
pcgoto _end
*r8 = r61

a0=a0+ a3
r3e=_factor
r2e=_half
a3 = -a2 * *r3
a0= *r3 * a0
r7e=_tu
a1= a0+ a3
r3e=_tc
a2=-a1 + *r3
r5e=_tv
r15=0x0001
a3 = a2 * *r2
r6e=_tw
a0=a3 + a0
a2 =a3 + a1

27 lines test 4.32745 1d22072a =

70

/*

[it

/* tw to _pwm+l
/* tv to _pwm+2
[It

/* tu to _pwm+3

*/

*l
*l
*/
*/
*l

*/

 

/*cos(pi/3)*sin(a)+sin(pil3)*cos(a)
/*cos(pi/3)*sin(a)-sin(pi/3)*cos(a)
/* r3 points _factor

/* 12 points _half

/* load _tl w/_factor*sin(pi/3-a)
/* load _t2 with _factor*sin(_vang)
/*
/* a1 = _tl+ (_t2)

/* r3 points _tc
/* _tc -(_tl + _t2) = _t0*2

/*
/*

/* a3 = _t0*2 ( *.5)

/* for address _pwm increment

/* _tv = a2 = _t0 +_t1+_t2

/* _tu = a0 = _t0 +_t1

/* int24(tw)

l* int24(tv)

/* int24(tu)

[It

/*

/*
[It

I* tw to _pwm+l

/* tv to _pwm+2

[ill

/* to to _pwm+3

*/
*l
*/
*l
*l
*/
*l
*l
*l
*l
*l
*I
*l
*l
*l
*/
*l
*/
*l
*l
*l
*/
*l
*/
*/
*l
*/

 

/*cos(pi/3)*sin(a)+sin(pil3)*cos(a)
/* r3 points _factor

/* r2 points _half

/* load _t2 with _factor*sin(_vang)
/* load _tl w/_factor*sin(pil3-a)
[Ill
/* a1 = _t1+ (_t2)

/* r3 points _tc

/* _tc -(_tl + _t2) = _t0*2

[all

/* for address _pwm increment

/* a3 = _t0*2 ( *.5)

[ill

/* _tw = a0 = _t0 +_tl

/* _tv = a2 = _t0 +_t1+_t2

*/
*l
*/
*l
*I
*/
*l
*l
*/
*/
*l
*/
*/
*l
*I
*/

[*M

[II
It
/*
/*

[it
/*
I?

71

*r7 = a3 = int24(a3) /* int24(tu)

*r6 = a0 = int24(a0) /* int24(tw)

*r5 = a2 = int24(a2) /* int24(tv)

r8e = _pwm +1 /*

r7 = *r7 /*

r6 = *r6 /*

r5 = *r5 /*

*r8++r15 = r6] /* tw to _pwm-+1

*r8++r15 = r51 /* tv to _pwm+2

pcgoto _end /*

*r8 = r71 /* tu to _pwm+3

26 lines test 5.32745 07 22 Ob 2a

*/

m: Wait Loop

*/
*l
*l

*l

*/

*/

*l
*l
*l
*l
*/

 

*/

 

*/
*/

 

*/

 

end:

r26 = _gg

a1 = *r2

3*nop

if (ale) goto _control
nop

goto _end

nop

*/

 

 

_invsqr:

*/
*/

 

Inverse Square
r2e = _x1 /* dummy varible
rle = _invsqu
*r2++ = a0 = *rl-H-
*r2-- = a0 = *r1

rle = _invsqr_in
r3e = _invsqu
r41: *rl

nop

r4 = -r4

*r2 = r41

a2 = *r1 * *r2

r4 = r4 >> 1

if (cc) pcgoto _invsqrA
a1 = a2 * a2

r2e = r2 + 4

_invsqrA:

a0 = a2 * *r3++

a0 = a0 + *r3++

a0 = a0 +al * *r3++
a1 = a2 * *r3++

a1 = a1 + *r3++

a0 = a1 + a1 * a0

a2 = a2 * *r3-H-

r4 = r4 - 64

*l

I?

72

a1 = a0 * a0

*r2 = r4]

a0 = a0 * *r2

a1 = *r3 - al *a2
rle = _invsqr_out
nop
*r1=a0=a0*a1
nop

return (r21)

nop

*/

 

34 lines --

 

1*:

/*

Interupt Routine

*/

 

 

 

It
_intr:

[It

itable:

_pwm:
_2pi:
_2n:
_n:

r2e = _pwm

obufe = *r2

nop

r26 = _gg

r3e = _negl

*r2 = a1 = *r3

nop /"‘ required */
nop /* required */
ireturn

nop

*/
*l

*/

 

.rsect ".table"

2*nop

goto 0x8004d4
nop

2*nop

2*nop

2*nop

goto _intr
nop

.rsect ".data"

float
float 6.2831853

float 8.26e2
float 4.13e2

_2n_fclk: float 2.6432e-4

_cos_pi_3: float 0.50000000

/*

_sin_pi_3: float 0.866025404

*/

 

—-== Inversion

73

_invfa: float 1.4074074347, 0.8l,2.27424702,-0.263374728

 

 

/*———-- = = -- */
_cosV: float 0.0 /* */
_sinV: float 0.0

_tc: float 0.0

_tu: float 0.0

_tw: float 0.0

_tv: float 0.0

_vang: float 0.0

_m: float 6.04e-3 /* pi/(2*Vdc)*sin(pil3)) */
_factor: float 0.0

_half: float 0.5

_negl: float -1.0
_posl: float 1.0
_zero: float 0.0
_Yd_new: float 0.0
/* ---—- INVSQR fl___. */
_invsqu: float 042990081, 1.2869825, 0057866799, -2.0122938
float 2.0972557, 0.5, 1.5000001
_invsqu: float 1.0, 1.4142136

 

 

 

 

_x0: float 0.0
_xl: float 0.0
_x2: float 0.0

_invsqr_in: float 0.0
_invsqr_out: float 0.0

 

/* -----—._.__.._._._ ----- =—-——-—- = */
_gg: float 0.0

_ang: float 0.0

_fclk: float 3.125e6 /* clock of pulse generaters */
_fout: float 3.0e1

/* ___...—--—-—-——-—...._.__...__ CURRENT MEASUREMENT PARAMETERS m */

cur_a: float 0.0
cur_b: float 0.0
cur_c: float 0.0

 

f_in: float -0.000081197 /* analog channel: - 0.00009184 */
offset: float 132.5 /* offset of current measurement */
f_cura: float 99.0 /* 125 Amp/ 1.25 V */
f_curb: float 99.0 /* 125 Amp / 1.25 V */
f_ino: float -0.036539

offs_2: float 00482 I* offset of current measurement */
f_cur2: float -20.086 /* 1 Amp] 17.7 mV */
loops: float 0.142857 /* 1/wire loops XXOXOXOXOX */
/* m SPEED MEASUREMENT PARAMETERS —— */
_2pi_felk: float 3.83495e4 /* (2*pi/1024)*6.25e6 */

_wr_new: float 0.0

_wr_old: float 0.0

_Wr_oldh: float 0.0

_wr_oldl: float 0.0

_spd_tol: float 0.05 /* Speed to]. +/- XXOXOXOXOX */

It

_isa_new: float 0.0
_isb_new: float 0.0
[It

 

_p_fac: float 0.66667, 0.33333, 0.57735 /* 2/3 1/3 1/sqr(3)

74

 

=>2 Coord. Transformation

__..___.=====:—..=== */

*/

FLUX OBSERVER PARAMETER

 

_pole: float 2.0
_ITr: float 3.24e2
_cl: float 6.1
_time: float 82.0e-6

_Yahd_new: float 0.0
_thd_new: float 0.0

_Yahd_old: float 0.0
_thd_old: float 0.0

_Yah_old: float 0.0
_Yah_new: float 0.0
_th_old: float 0.0
_th_new: float 0.0

_Yd_ref_new: float 0.02
_1_Yd: float 0.0

_cos_pr: float 0.0
_sin_pr: float 0.0
_isq_new: float 0.0
_isd_new: float 0.0

*/
*l
*/
*l
*/

 

/* XXOXOXOXOX

/* XXOXOXOXOX

/* ITr*Lm XXOXOXOXOX
/* XOXOXOXOX

/* XXOXOXOXOXOX */

 

[it
_count: float 0.0
_event: float 1230.0
_testc: float 0.0
_storcnt: float 0.0
_stor: float 3.20e4
_done: float -1.0

It

 

_eventspd: float 2.0e4
_speedl: float 0.0
_speed2: float 140.0
_donespd: float -1.0
/* _—

 

_countspd: float 0.0

STORAGE PARANIET */

/* XXOXOXOXOXOX I"I

CHANGE SPEED

FLUX CONTROLLER

 

_Yd_int_old: float 0.0
_isd_kp: float 0.35
_isd_ki: float 0.001
_ILm: float 53.0
_isd_ref_new: float 0.0
[It

_isd_int_old: float 0.0
_usd_kp: float 0.25

— Isd CURRENT CONTROLLER

_....-._ *I

[It
/*
III!

XXOXOXOXOXOX
XXOXOXOXOXOX
XXOXOXOXOXOX

*/

*l

*/
.._. */
[it

XXOXOXOXOXOX */

_usd_ki: float 0.0
_usd_ref: float 0.0

75

 

/* ==
_wr_ref: float 210.0
_wr_int_old: float 0.0
_te_kp]: float 0.7
_te_kp2: float 0.7
_te_kp: float 1.17
_te_ki: float 0.15
_te_ref_new: float 0.0
/*

 

 

_k: float 3.9
_te_int_old: float 0.0
_isq_kp: float 1.05
_isq_ki: float 0.15
_isq_ref_new: float 0.0

/*

 

_isq_int_old: float 0.0
_isq_error: float 0.0
_usq_kp: float 0.25
_usq_ki: float 0.0
_usq_ref: float 0.0

_Vsa: float 0.0
_Vsb: float 0.0

 

 

/* XXOXOXOXOXOX */
SPEED CONTROLLER */
/* XXOXOXOXOXOX */
/* XXOXOXOXOXOX */
/* XXOXOXOXOXOX */

TORQUE CONTROLLER */
/* 3*p*Lm/2*Lr XXOXOXOXOXOX */
/* XXOXOXOXOXOX */
/* XXOXOXOXOXOX */
Isq CURRENT CONTROLLER ======-—-—-—— */
/* XXOXOXOXOXOX */
/* XXOXOXOXOXOX */

APPENDIX B

76

%*****************************************************

% Simulation program of Indirect Rotor Flux Field Orientation
% by John W. Kelly
% Copyright 1997

%*****************************************************

0L

global YahNew YahOld thNew thOld Yathld thdOld 2 TE;
global Vsa Vsb;
YahNew = 0.00;
YahOld = 0.00;
thNew = 0;
thOld = 0;
Yathld = 0.0;
thdOld =0.00;
Vsa = 0;
Vsb =0;
2 =0;

[Ly]=ode23('mtrr12',0,40,[0.02 0.0 0.0 0.0 0.0 0.0 0.02 0.0 0 0 0 0 0]');
01.

IV

 

function [xdot] = mtrr12 (t,x,Vsa,Vsb)
global YahNew YahOld thNew thOld Yathld thdOld 2 TE;
global Vsa Vsb;
%z=1+z

Wrref = 180;

p=2:

j=.0006;

Rs=8;

Rr=4.1668;

Lr= .0128875;

Ls: .0128875;

Lm = .018833;

segr = Ls/Lm - 1/Lm;
%segr = -52.414;

seg = l - l/(1+segr)"2;
%seg = .999622;

ITs = Rs/Ls;

%ITs = 620.76;

ITr = Rr/Lr;

%ITr = 323.32;
beta=Lm/(seg*Ls*Lr);
%beta=1 13.43;
eta=llseg;

%eta=l .00;
gamma=1/(seg*Ls);
%gamma = 77.594;

77

 

 

mu=p*Lm/(j*Lr);

%mu=29.292;

k=3.9;

TL=0.00;

% --- Induction Motor Model in Stator Coordinates
xdot(l)=-ITr*x(1)-p*x(5)*x(2)+ITr*Lm*x(3); %dYra/dt
xdot(2)=- r*x(2)+p*x(5)*x(1)+ITr*Lm*x(4); %dYrb/dt

xdot(3)=beta*ITr*x(l)+beta*p*x(5)*x(2)-(ITs*eta+ITr*beta*Lm)*x(3)+gamma*Vsa;%dIsa/dt
xdot(4)==beta*ITr*x(2).beta*p*x(5)*x(1)-(ITs"‘eta+ITr*beta*Lm)*x(4)+gamma*Vsb;%dIsb/dt
xdot(5)=mu*(x(2)*x(3)-x(1)*x(4));
xdot(6)=x(5);

% Second Order Flux Observer
xdot(7) = -ITr*x(7)-p*x(5)*x(8)+ITr*Lm*x(3);
xdot(8) = -ITr*x(8)+p*x(5)*x(7)+ITr*Lm*x(4);

 

 

WrNew = x(5) ;
%W = [ WrNew t];
IsaNew = x(3);
IsbNew = x(4);

% Control Scheme

 

 

Yd = sqrt(x(7)."2 +x(8)."2);
cosPr=x(7) JY d;
sinPr=x(8)./Y d;

 

% Coord. Transformation

 

Istew = IsaNew*cosPr+IsbNew*sinPr;
Isquw = -IsaNew*sinPr+IsbNew*cosPr;

%++++++++++++++ Usdref ++++++++++1~++++++++++++++++++++

 

 

% Flux Controller
Kp = .35;

Ki = .001;

Yrref = .02;

YrrefENew = (Yrref - Yd)JLm;

xdot(9)= YrrefENew;

IsdrefNew = Kp.*YrrefENew + Ki.*x(9);

% Mag. Cunent Controller Isd

 

 

Kp = 0.25;
Ki = 0;

78

IsdrefENew = Isdmmew - Istew;
xdot(10) = IsdrefENew;
UsdrefNew = Ki.*x(10) + Kp.*IsdrefENew;

07..
II;

%++++-H-++++++++++++++ Usqref +++++++++++++++++++++++++++++

 

 

% Speed Controller
Kp = 1.170;
Ki = 0.15;

WrrefENew = Wrref - WrNew ;
%WE(z, 1)=WrrefENew;

xdot( 1 1) = WrrefENew;

%WE(z,2)=x(1 l);

TrefNew =Kp.*WrrefENew+Ki.*x(11) ;
%WE(z,3)=TrefNew ;
%po=[WrrefENew x(l l) TrefNew x(5)];

 

 

 

0]..

% Torque Controller
Kp = 1.05;

Ki = 0.05;

TrefENew = TrefNew - Isquw.*Yd.*k;
%TE(z, 1)=TrefENew;

xdot( 12) = TrefENew;

%TE(z,2)=x(12);

IsqrefNew = Kp.*TrefENew + Ki.*x(12);
%TE(z,3)=IsqrefNew ;

%
% Current Controller Isq
Kp =.25;

Ki: 0;

IsqrefENew = Isqmmew -Isquw;

xdot(l3) = IsqrefENew;

UsqrefNew = Kp.*IsqrefENew + Ki.*x(l3);
%TE(z,4)=UsqrefNew ;

%
UsqrefENew = UsqrefNew;
UsdrefENew = UsdrefNew;

 

 

 

 

% Condinate Transformatiom DQ=>AB
Vsa = UsdrefENew.*cosPr- UsqrefENew.*sinPr;
Vsb = UsdrefENew.*sinPr + UsqrefENew.*cosPr;

 

 

BIBLIOGRAPHY
[1] DSP32C Digital Signal Processor Information Manual, AT&T documentation,
1990
[2] The Programmable Logic Data Book, Xilinix, 1994

[3] J. Volder, “The CORDIC Trigonometric Computing Technique,” IRE Transactions
on Electronic Computers, pp 330-333, September 1959

[4] Muhammad H. Rashid, “Power Electronics Circuits, Devices, and Applications,”
Englewood Cliffs, NJ. Prentice Hall, 1993.

[5] H. W. Van der Broeck, H. Skudelny, G. Stanke, “Analysis and Realization of a

Pulse Width Modulator Based on Voltage Space Vector,” IEEE Transaction on Power
Electronics, 1986

[6] DSP32C Application Software Library Reference Manual, AT&T 1990

[7] F. Blaschke, “ Das prinzip der fieldorientierung, die grundlage futr dir transvector-
regelung von asynchronmaschinen,” Siemens Zeitschrift, p. 757, 1971

[8] W. Leonhard, “Control of Electrical Drives,” Springer Verlag, 1985

[9] B- AlOIiWi, H- Khalil. E-G. Strangas, “Robust Speed Control of Induction Motor,”
Michigan State University, 1996

79

"Illllllfllllllillllllll“