1| : V. . . . . ‘ I<V
H.‘ «w ‘0. . . , . . . . , . .. V {tr

5-3.. .V:

 

 

.q 6:34...- .

 

KATA... ~33. ... [I 1.0 5 . .a, 3i ..

 
 

THEsiB

 

 

 

 

x I
“q? ///////////77m7/‘787??7,fl7“~£s ’
LIBRARY avlé/Q/li/lylga/MWI ‘
Michigan State 7
University
This is to certify that the

dissertation entitled

DESIGN OF HIGH PERFORMANCE AND LOW POWER
CMOS SNITCHED-CURRENT DATA CONVERTERS

presented by
Jin-Sheng Wang

has been accepted towards fulfillment
of the requirements for

Ph.D. degree in Elec‘trica] Eng

flog/QM M7

ajor profo§sor

/
Date (ng [i ?g

MS U is an Affirmative Action/Equal Opportunity Institution 0-12771

 

PLACE IN RETURN Box to remove this checkout from your record.
To AVOID FINE return on or before date due.
MAY BE RECALLED with earlier due date if requested.

 

DATE DUE DATE DUE DATE DUE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1M COW“

 

DESIGN OF HIGH PERFORMANCE AND LOW POWER
CMOS SWITCHED-CURRENT DATA CONVERTERS

By

J in-Sheng Wang

A DISSERTATION

Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

DOCTOR OF PHILOSOPHY
Department of Electrical Engineering

1998

ABSTRACT

DESIGN OF HIGH PERFORMANCE AND LOW POWER
CMOS SWITCHED-CURRENT DATA CONVERTERS

By
J in-Sheng Wang

The advent of portable communication and computing service has stirred a great
deal of interests in both commercial and research areas. The circuit technology used in
portable equipment has been changed from the conventional analog circuit technology to
mixed-signal circuit technology. Low power and high performance are strongly needed for
both analog and digital circuits to increase operation time of the portable equipment. The
design of low power and high performance mixed-signal CMOS IC’s is hindered by pro-
cessing techniques that are optimized for digital applications. Moreover, scaling/reliability
consideration are driving CMOS process towards submicrometer feature size and lower
power supply voltages.

Switched-current (SI) technique has received considerable attention as an altema-
tive for analog data acquisition and conversion circuit design. However, existing SI cir-
cuits cannot make the theoretically expected performance due in part to the use of non-
optimal current copiers, its basic building blocks. Based on our development of design
methodologies and synthesis process for optimally generating low power and high perfor-
mance CMOS current copiers, SI technique becomes feasible.

This thesis develops high performance and low power CMOS SI data converters,

ADCs (analog-to-digital converters) and DACs (digital-to-analog) converters. A 12-bit

CMOS cyclic ADC circuit which consumes 1.9mW in power and takes 2.13 mm2 in chip
area, has designed and fabricated. A 11-bit CMOS DAC circuit which consumes 4.4mW
in power and achieves lOO MSamples per second in conversion rate, has been designed
and simulated, where 3.3 V power supply voltage and MOSIS SCN20 2 mm CMOS pro-
cess with 2-level transistor parameters are employed. This thesis also presents the design
methodologies and performance analysis process. The developed design methodologies
guide the designers to properly select the transistor sizes and capacitances based on a
given set of design specifications including input dynamic range, full-scale current, SNR,
power consumption, etc., and the performance analysis process estimates the calibration
time, holding time, and accuracy of the data converter circuits.

This study also develops a built-in tester to enhance the testability of SI circuits,
The tester possesses the features of autozeroing and self-testability. The autozeroing prop-
erty increases the accuracy, while the self-testability ensures the correctness of the tester
before it is used to test SI circuits.

“6th the successful development in this thesis study, we believe that SI technique

will soon become an alternative industrial standard for designing analog components in

mixed-signal circuits for low-voltage/low-power signal processing applications.

To my parents, wife, daughter and brothers

iv

ACKNOWLEDGEMENTS

I sincerely thank Professor Chin-Long Wey, my thesis advisor, for his support and
valuable suggestions throughout this research. It has been a pleasure to work under his
supervision and I have certainly learn a lot from him. I would also like to express my grat-
itude to the members of my guidance committee, Dr. James A. Resh, Dr, Gregory M.
Wierzba and Dr. Chester Tsai, for taking time to serve in the committe. This research is
sponsored in part by National Science Foundation under grant number MIP-9321255.

I have to thank my fellow graduate students, Dr. Chen-ng Wang and Wei-hsing
Huang. I got much inspiration from the discussion with them.

A special thanks goes to my parents, Fu-tseng Wang and A-chin Lin, my wife,
Huie-fang Tsao, and my brothers, Jin-hsiang and Jin-tao, for their long-term support and
encouragement they have given me during the critical stage of my life.

I also need to thanks Brain Dazsi, Mohammad Athar Khalil, Malinda Funk and
Jim Ganong for reading and editing this work.

A final note of appreciation must be sent to all the nice people who have ever

enriched my campus life while I stayed in Michigan State University.

TABLE OF CONTENTS

LIST OF TABLES .......................................................... xi
LIST OF FIGURES ......................................................... x
1. INTRODUCTION ....................................................... 1
1.1 Switched-Current (SI) Circuits ...................................... 2
1.2 Objectives and Research Tasks ...................................... 3
1.3 Thesis Organization ................................................. 5
2. CMOS SI CIRCUITS .................................................... 7
2.1 Current Copiers ...................................................... 7
2.2 Multiplier and Divider Circuits ........................... ' ........... 9
2.3 Data Converter Circuits .............................................. 12
2.3.1 Conversion Algorithms ...................................... 14
2.3.2 Design Specification of Data Converters ..................... 16
2.3.3 CMOS SI ADC Circuits ...................................... 17
2.3.3.14-cycle Conversion .................................... 21
2.3.3.2 2-cycle Conversion .................................... 22
2.3.4 CMOS SI DAC Circuits ...................................... 23
2.4 Test Generation ...................................................... 26
2.4.1 Fault Models ................................................. 26

vi

2.4.2 Test Generation of Current Copie ........................... 28

2.4.3 Test Generation of ADC Circuits ............................ 30

2.5 Discussion ........................................................... 32

3. CMOS SI ADC CIRCUIT DESIGN .................................... 36
3.1 Design and Consideration ........................................... 36
3.1.1 2—Cycle Residual Amplifier .................................. 37

3.1.2 2-Cycle Conversion with Modified RSD Algorithm ........ 37

3.2 Design Consideration .............................................. 44

3.3 Simulation Results and Measurements ............................. 46

3.4 Conclusion ........................................................... 53

4. CMOS SI DAC CIRCUIT DESIGN .................................... 56
4.1 Current-Mode DAC Circuits ......................................... 56
4.1.1 CRG_DC Circuits ............................................ 57

4.1.1.1 Divide-by-Two (DB2) Circuit ........................ 59

4.1.1.2 m-bit CRG_DC Circuit ............................... 63

4.1.2 CRG_MC Circuits ............................................ 64

4.1.3 Design Methodology ......................................... 66

4.1.4 Performance Analysis ...................................... 69

4.2 Design Examples ................................................... 72

vii

4.2.1 A 6-bit CRG_DC Circuits .................................. 72

4.2.2 A 7-bit CRG_MC Circuits .................................. 78
4.2.3 Simulation Results .......................................... 78
4.3 DAC Circuit Design ................................................ 78
4.3.1 Low Power SI DAC Circuit ................................. 82
4.3.2 Design Examples -- an ll-bit DAC Circuit .................. 82
4.3.3 Alternative Designs ........................................... 83
4.4 Conclusion ........................................................... 87
5. BUILT-IN TESTERS FOR SI CIRCUITS .............................. 89
5.1 Built-in Testers ....................................................... 89
5.2 CMOS Current Comparator ......................................... 97
5.2.1 Autozeroing .................................................. 97
5.2.2 Self-Testability ............................................... 99
5.3 Conclusion .......................................................... 105
6. CONCLUSION ........................................................... 107
6.1 Summary and Contribution .......................................... 108
6.2 Future Work ......................................................... 110

viii

LIST OF TABLES

2.1 Relationship amomg k, r, and accuracy ................................. 13
2.2 Summary of defects and circuit fault ................................... 27
2.3 Fault types ........................................................... 30
3.1 The summarized performance od ADC ................................. 55
4.1 Parameter values for CRG_DC in Figure 4.5(a) ........................ 75
4.2 Performance analysis for various bit sizes of CRG_DC ................ 75
4.3 Parameter values for CRG_DC in Figure 4.5(b) ........................ 77
4.4 Performance analysis for various bit sizes of CRG_DC ............... 77
4.5 Parameter values for CRG_MC in Figure 4.3(c) ....................... 79

ix

LIST OF FIGURES

1.1 Schematic diagram of a typical DSP-based mixed-signal IC .......... 2

2.] Various current copier structures ........................................ 8

2.2 SI circuits ............................................................... 11
2.3 Cyclic conversion algorithms ........................................... 19
2.4 Cyclic ADC circuits .................................................... 20
2.5 Current-Mode DAC circuits ............................................ 24
2.6 Fault behavior and switching sequence ................................. 31

2.7 Simplified schematic diagram of SI algorithmic ADC with additional

comparator .............................................................. 3 1
2.8 Test sequence A ......................................................... 33
2.9 Test sequence B ......................................................... 34
3.1 Proposed 2-cycle residual amplifier .................................... 38
3.2 Proposed switched-current CMOS cyclic ADC ........................ 39
3.3 Bit conversion ........................................................... 41
3.4 Modified RSD conversion algorithm ................................... 42
3.5 Simulation results ....................................................... 48
3.6 Implementation ......................................................... 49

3.7 Schematic circuit of voltage-to-current converter ...................... 51

3.8 Analysis of nonlinearity ................................................. 52
3.9 FFI‘ analysis of designed ADC ......................................... 54
4.1 CRG_DC circuit ........................................................ 58
4.2 DB2 circuits analysis ................................................... 61
4.3 CRG_MC ............................................................... 65
4.4 Small signal analysis of negative feedback current copier ............. 70
4.5 6-bit CRG_DC circuit ................................................... 73
4.6 Simulation results ....................................................... 80
4.7 Proposed DAC circuit structure .................................. . ...... 81
4.8 Nonlinearity analysis of M7D4 DAC ................................... 84
4.9 Nonlinearity analysis of M5D6 DAC ................................... 86
5.1 Tester .................................................................... 90
5.2 SI Tester ................................................................. 92
5.3 Schematic and configuration of built-in tester ......................... 93
5.4 Test confidence vs. resolution .......................................... 96
5.5 Autozero current comparator ........................................... 98
5.6 Analysis of current comparator ......................................... 100
5.7 The configuration of circuit under testing .............................. 101

xi

5.8 Operation phase of built-in tester ....................................... 102

5.9 Fault simulation results ................................................. 104

xii

Chapter 1

INTRODUCTION

High speed and low power data converters, analog-to-digital converters (ADCs)
and digital-to-analog converters (DACs), have been highly demanded in portable systems,
such as personal communication systems, astronomy research equipments, and multime-
dia. The analog circuit technology conventionally employed for such applications has
been gradually switched to analog/digital mixed-signal circuits technology [1]. Integrating
both digital and analog on a single chip has improved performance and reduced board size
and cost. Figure 1.1 shows the schematic diagram of a typical DSP (digital signal process-
ing)-based mixed—signal IC. The current trend shows that data converters’ interfaces are
incorporated as a cell in a complex mixed-signal IC containing mostly digital blocks for
DSP and control. Even though very complicated DSP circuits have been widely used, ana-
log circuits will remain for processing or interfacing analog signals to/from I/O devices.

The silicon area in a typical mixed-signal integrated circuit (IC) contains 10% ana-
log circuits and 90% digital circuits. The overall system cost can be reduced significantly
if both analog and digital portions can use the same supply-voltage and the analog por-
tions can be fabricated using the low cost digital CMOS process. If both analog and digital
portions use the same supply-voltage, then the system does not need dc-dc converters to

generate multiple supply voltages.

 

 

 

Analog Analo
__> g __, __>
Input Interface ADC

 

 

 

 

 

 

DSP
Core

 

 

Analog Analog
0' utput Interface «— DAC

 

 

 

 

 

 

 

 

 

 

T We

 

 

 

 

 

 

 

 

 

 

PLL& , Digital
Timing CKT Interface
Timing . . .
Digital Signals

Figure 1.1 Schematic diagram of a typical DSP-based mixed-signal IC.

Since most of analog components in a mixed-signal ICs are used for processing
and interfacing analog signals, their accessibility becomes drastically reduced [2,3].
Recently, manufacturers have found the costs associated with high-volume production of
mixed-signal ICs are strongly affected by the cost of testing. Testing effort is just the
opposite of the silicon areas in mixed analog and digital circuits; i.e., 90% for analog test-
ing and 10% for digital testing. Therefore, enhancing testability can reduce test cost and

thus further decrease system cost.

1.1 Switched-Current Circuits

Traditionally, the analog interface portion of a mixed-signal circuit employs the
switched-capacitor (SC) technique which requires high quality linear capacitors [4]. The
high quality linear capacitors are usually implemented using two layers of polysilicon.
However, the second layer of polysilicon used by SCs is not needed by purely digital cir-
cuits and may become unavailable as process dimensions shrink to the deep submicron
range. On the other hand, to be compatible with low-voltage systems, analog circuits must
be operated at a supply voltage of 2 V or below. However, with lower supply voltages the
realization of high-speed, high-gain operation amplifiers in the SC technique becomes
more difficult [5,6].

Recently, a class of analog circuits wherein current, rather than voltage, is the pri-
mary signal medium has received considerable attention. The use of current-mode creates
a potential for speed improvement because stray-inductance effects in such low-imped-
ance switched-current (SI) circuits are much less severe than those in high-impedance SC

circuits [5-18]. High accuracy can be obtained by using dynamic calibration to alleviate

the error due to element mismatch. The SI technique couples itself well with the down-
scaled CMOS technology, where the transistors with a high cut—off frequency are avail-
able, leading to a higher calibration. In addition, highly linear capacitance is not needed
for high accuracy analog signal processing. Alternatively, accuracy has been traded with
speed in LA modulations using oversampling techniques to achieve performance several
orders of magnitude higher than traditionally associated with analog limitations [9]. The
challenge and the gains are clear for the designer who can manage the extra demands on
analog performance with diminishing resource of digitally-motivated VLSI process devel-
opment [18].

Even though the SI technique possesses the salient features mentioned above, one
frequently asked question is: why hasn’t the SI technique become an industrial standard
yet? A simple answer is that the accuracy, linearity, and noise problems are still not
resolved completely and satisfactorily [18]. It is necessary to develop sound design meth-
odology and synthesis processes for generating high performance analog circuits [18].
Since current copier is the basic building block of SI circuits, the performance of a SI cir-
cuit is determined by the performance of the current copiers it employs. Therefore, devel-
oping a sound design methodology and synthesis process for generating high performance

current copiers becomes a very important task.

1.2 Objectives and Research Tasks
Based on the recently developed current copiers [5-7,14], our research goal is to

develop high performance CMOS SI circuits for low-power/low-voltage signal applica-

tions and the objective of this thesis study is to develop high performance and low power
CMOS SI data converters.

In the past years, a number of high-speed ADC and DAC circuits have been
designed for portable systems [1946]. For such applications, a sample rate above 5 MS/s
(Mega Samples per second) and 8-12 bit resolutions is required. Most of such converter
designs use the switched-capacitor (SC) technique. The power consumption is typically
ranged from 100 mW to 500 mW. Apparently, for battery-powered portable applications,
this level of power consumption is not suitable. Therefore, power reduction is essential for
power-optimized ADC and DAC circuits.

To accomplish our research objective, the research tasks include the development
of design methodologies and performance analysis processes for the optimized data con-
verters. The design methodologies provide the designers to select appropriate structures
and parameter values to meet the design specifications such as accuracy, speed, power
consumption, signal-to-noise ratio (SNR), supply voltage, and etc., while the performance
analysis processes allow the designers to evaluate the performance of the designed cir-
cuits. In this study, the developed data converter circuits will be designed and fabricated
using the low-cost digital CMOS process and the same low supply voltage for both digital

and analog parts. In addition, the developed data converters must be easily testable.

1.3 Thesis Organization
The thesis is organized as follows: Chapter 2 reviews the background which relates
to this research. The basic current copier is introduced first. Several different structures

and circuit cells are also presented to endorse the feasibility of SI technique. Two current-

mode ADC circuits in [8,16] and a current-mode DAC in [47] are discussed. Finally, the
test generation and fault coverage of SI CMOS ADC developed in [48-52] are briefly
described.

Chapter 3 describes the design and operation of the developed high performance
and low power cyclic ADC circuit using modified redundant-signed-digit (RSD) algo-
rithm. A 12-bit CMOS SI circuit has been designed, simulated, and fabricated. Both simu-
lation results and measurements will be discussed.

Chapter 4 presents the design and operation of the developed DAC circuits. The
weighted current references are generated using current reference generator (CRG) cir-
cuits. Two types of CRG circuits are introduced with their simulation results. The design
methodology and performance analysis of DAC circuits for low power applications are
also presented.

Chapter 5 introduces a built-in tester to enhance the testability of SI circuits. The
tester is comprised of a current comparator, a voltage window comparator, and a digital
latch. The current comparator is required to have high-accuracy, low-power consumption,
simple structure with small chip area, and moderate speed. A comparator adopting an
autozeroing technique is developed to achieve high accuracy, and it possesses the self-test-
ing capability for detecting both catastrophic and parametric faults of all its components.

Finally, Chapter 6 summarizes the thesis study and gives concluding remarks and

future research directions.

Chapter 2

BACKGROUND

This chapter reviews the background knowledges related to the thesis research.
Current copier is the basic building block of SI circuits. Section 2.1 reviews the existing
current copiers. Section 2.2 introduces the current-mode multiplier and divider circuits.
Section 2.3 presents the design and operation of data converter circuits. Finally, test gener-

ation of both current copiers and ADCs are discussed in Section 2.4.

2.1 CMOS Current Copiers

A simple current copier, as shown in Figure 2.1(a) [7], is comprised of two
switches S, and 82, a current-storage transistor MI, and a holding capacitor C,. To copy
the current Ii“, S, and 82 are turned on, therefore feeding Iin to M1 and C1. The capacitor
charges up to whatever gate voltage is needed by M1 to support a current equal to Ii“.
When 8, and 82 are off, the copier cell is disconnected from the current source. Thereafter,
the copier cell is capable of sinking a current Iin when connected to a load. No well-
matched components are needed in the current copier. However, the copier is suffered
from two major error effects due to (1) the nonzero conductance of M1 and (2) charge-
feedthrough of 82 [7]. The non-zero output conductance results from the channel length-

modulation effect and the drain-gate capacitive coupling of M1. The charge-feedthrough

 

 

 

 

 

 

 

 

Ibias

(a) (b) (C)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2.1 Various current copier structures: (a) simple copier; (b) negative feedback

(inverter) structure; (c) negative feedback (follower) structure; (d) differential-
pair; and (e) differential-pair with feedback amplifier.

error is caused as follows: when the gate voltage of 82 goes down during the tum-off tran-
sient, the charge held in the transistor realized by 82 will be forced to leave. Since one end
of 52 is connected to the gate node of M1, some charges of 82 will be dumped to the gate of
M1, which changes the voltage across C1. As a result, the current held in M, will deviate
from Ii“, and the charge-feedthrough error results.

The effect of error due to nonzero conductance of M1 can be alleviated by using
cascode structures [6,9] and negative feedback structures [7,14,18]. The current-storage
transistor M1 together with the input current source constitutes a voltage inverter in Figure
2.1(b) [7], but forms a source follower in Figure 2.1(c) [14,18]. In order to keep the
feedback negative, the former implements an amplifier with a positive gain, while the latter
employs a negative-gain amplifier. On the other hand, the charge-feedthrough error effect
can be reduced by either increasing the capacitance C1, or using appropriate switches.
Recently, a fully differential-pair current copier, as shown in Figure 2.1(d) [17], was
developed in which the distortion is reduced by cancelling even-order harmonics and
crosstalk from neighboring digital circuits. The current copier in Figure 2.1(c) [17] can

reduce both error effects mentioned above.

2.2 Multiplier and Divider Circuits

Current multipliers and dividers are usually implemented by using resistor
networks or weighted transistors. However, the accuracy of such solutions is limited by
resistor or transistor mismatch. To obtain accurate signal multiplication/division without
the need for well-matched components, switched-current multiply-by-two (MX2) circuits

[8] and divide-by-two (D82) circuits [53,54] are introduced.

Figure 2.2(a) illustrates a 3-cycle MX2 circuit [8] which generates an output current
equal to 21,n without the need of well-matched devices. Initially, Switches SO, S], and 82
are turned on. After the op-arnp is settled, 11 will equal Ii“. When 32 is turned off, the gate
capacitance will cause transistor N1 to "memorize" the input current level. This procedure
is then repeated for transistor N2 by turning on So, 83, and S4. Once N2 has been set, an
output current of 2Iiu is produced by turning on S1, S3, S5 and S6, which will cause Iout to
be equal to 11+12 (or 21in)-

Figure 2.2(b) shows an accurate current divider [53] which divides an input current
by two. The number of iterations necessary to obtain half the current with certain accuracy

depends on the mismatch of transistors N2 and N3. Each iteration takes three clock cycles.

The current copying sequences for the first iteration and the remaining iterations are listed

in (a1)-(cl), and in (A1)-(C1), respectively [53].

(31) [in—)N28LN3 (A1) Iin&Nl —) N2&N3
(b1) N2—9P4 (Bl) N2—)P4
(C1) P4&N3—)N1 (C1) P4&N3-—)N1

where “Iin—)N2&N3“ in (a1) means that the input current Iin is stored to both copiers with
N2 and N3. By (b1) and (c1), 11:12-13 which is stored to the copier with N1. Since the
NMOS copier stores only a positive current, hence the divider functions properly only
when 12 > 13.

Let a2 and (13 be the mismatch factors of the transistors N2 and N3, respectively,
where 12=0t21im I3=a3lim and
a2 = [k2(ng-VT2)2] / [k2(Vgs-VT2)2 + k3(ng-VT3)2] (2.1)

(13 = [k3(ng-VT3)2] / [k2(VgS-VT2)2 + k3(ng-VT3)2] (2.2)

10

 

 

_1,
1r—-
tn‘T” ]
U
I
I +
L-----------;------------

 

 

Von
Iin P4
38
S
1 ° 187

51I 53“ 12 51 $13
52 s4 86
V33

(19)

 

Figure 2.2 SI circuits: (a) MX2 [8]; and (b) DB2 [53].

H

where V12 and V13 are the threshold voltages of transistors N2 and N 3, respectively, and
the device transconductance ki=ki’(W/L)i, i=1 or 2, is the aspect ratio of transistor Ni.
Thus, (12 > a3 if 12 > [3. Because the transistor mismatch is generally unknown in advance,
the current divider functions properly only when the mismatch factor a2 > a3. Thus, an

alternative current divider is presented in [53], in which the division works for any mis-
match factors. The relationship among the number of iterations required for the division
process, the mismatch factor, and the desired accuracy, was derived as follows. Let 7

denote the mismatch ratio, i.e., y=(0t3/0t2)-1. According to the current copying sequence,
the current held in N 3 at the end of the first cycle of the k-th iteration, denoted as 13k, is

expressed as [54]

I3k=(I.../2){1+(-1)“"n/<2+v)ik} (2.3)

Table 2.1 lists the relationship among the number of iterations k, the mismatch
factor 7, and the accuracy, i.e., |I3k-Iin/2V(Iin/2), or l[y/(2+'y)]kl. Apparently, the error term
[‘y/(2-I-iy)]k diminishes rapidly as k increases, i.e., I3kz1in/2. Thus, the error term is used to
determine the number of iterations necessary to obtain lift/2 with certain accuracy. Results
show that the divider can achieve an accuracy of 6.21x10'6 by taking five iterations for
20%. On the other hand, for a practical 1% transistor mismatching, the circuit takes only

two iterations to achieve an accuracy of 2.47x10’5.
2.3 Data Converter Circuits

This section reviews the basic data converter algorithms and data converter cir-

cuits.

12

a

 

Table 2.1 W.

(k: number of iterations, 'y: mismatch factor)

 

 

 

 

 

k y=20% y=lO% y=5% 1:22;; y=l%

1 9.09e-O2 4.76e-02 2.44e-02 9.90e-03 4.97e-03
2 8.26e-03 2.26e-03 5.95e-04 9.80e-05 2.47e-05
3 7.51e-O4 1.07e-04 1.45e-05 9.70e-07 1.23e-07
4 6.83e-05 5.14e-06 3.53e-O7 9.60e-09 6.12e-10
5 6.21e-06 2.45e-O7 8.63e-09 9.51e-11 3.04e-12
k y=-20% y=—10% y=-5% y=-2% y=-1%

1 1.11e-01 5.26e-02 2.56e-02 1.01e-02 5.02e-03

2 1.23e-O2 2.77e-03 6.57e-04 1.02e-O4 2.52e-05

3 1.37e-03 1.45e-04 1.68e-05 1.03e-06 1.26e-O7
4 1.52e-O4 7.67e-06 4.32e-07 1.04e-08 6.37e-10
5 1.69e-05 4.03e-07 1.1 le-08 1.05e- 10 3.20e- 12

 

 

 

 

 

 

13

 

2.3.1 Conversion Algorithms

A DAC converts binary numbers, represented by patterns of 1’s and 0’s, into
discrete analog data represented by, either voltage or current. To simplify the discussion in
the later chapters, current data conversion is referred to. Depending on how the DAC is
configured, the transfer function of a DAC can be unipolar (outputs having only positive or
negative values, but not both) or bipolar (outputs can be either positive or negative). There
is a simple linear correspondence between the input codes and the output current levels. For
an N-bit DAC, the output current is represented by

1out =11=s (bl/2 + 132/4 + .. + 131,140“:1 + bN/ZN) (2.4)
where the coefficients, b1, b2, .., bN, represent the logic levels of the input bits, which can
be 1 or 0, b1 is the most significant bit (MSB) while bN is the least significant bit (LSB),
and IFS is the full-scale (FS) current. Eqn (2.4) can be achieved from the following
recursive algorithm,

1k = Ik-l / 2; (2.5)

Bk = B“ + bN_k+1 x I“; k=1,2,..,N (2.6)
where 1k is the reference current for the k-th bit conversion and Bk is the current that is
accumulated at the end of the k-th bit conversion. The initial conditions for (2.5) and (2.6)
are B0=0, and IO=IFS- For simplicity, this approach is referred to as the dividing conversion
(DC) approach.

On the other hand, IFS=2N ILSB’ or ILSB=IFSI2N, where ILSB is the current for
converting the LSB. Eqn (2.4) can be rewritten as

1out = (13,211"1 + 1322""2 + .. + bN,]2 + bN)ILSB (2.7)

and can be achieved by the following recursive algorithm,

14

Bk = BH + bN_k+1 x J“; k=1,2,..,N (2.8)

Jk = 2 x Jk_1; (2.9)
where Jk is the reference current for the (N-k)-th bit conversion and Bk is the current that
is accumulated at the end of the (N-k)-th bit conversion. The initial conditions for (2.8) and
(2.9) are Bo=0, and JO=ILSB. This approach is referred to as multiplying conversion (MC)
approach.

The objective of an ADC is to determine the output digital word corresponding to
an analog input signal. The ADC usually requires a sample-and-hold (S/H) circuit at the
input because it is not possible to convert a changing input signal. The characterization of
the ADC is almost identical to that of the DAC if the input and output definitions are
interchanged. Cyclic (or algorithmic) and successive-approximation (SA) ADCs convert
an input signal (either current or voltage) into an N-bit digital data word using the MC or
the DC approach, respectively.

More specifically, a cyclic ADC first samples and holds an input current/voltage,
and converts the MSB of the input current/voltage by comparing twice the input current]
voltage to the reference current/voltage. If the signal exceeds the reference, the MSB will
be a “1” and a residual current/voltage is the difference of twice the input signal and the
reference. Otherwise, the MSB will be a “0” and the residual current/voltage is just the
twice the input signal. The residual current/voltage is then converted to find the next bit.
This sequence is repeated until the desired resolution has been achieved. Thus, a cyclic
ADC requires a multiply-by-two (MX2) circuit to generate the double residual current!
voltage value.

On the other hand, the SA ADC requires a divide-by-two (DB2) circuit to generate

15

the weighted references, as in Eqn. (2.4). The SA ADC converts the MSB of the input
current/voltage by comparing it to the generated weight which is half of the reference at
this step. If the input signal exceeds the weight, the MSB will be a “1” and the residual
current/voltage is the difference of the input signal and the weight. Otherwise, the MSB
will be a “0” and the residual is just the input signal. The residual is then converted to

calculate the next bit. This sequence is repeated until the desired resolution is achieved.

2.3.2 Design Specifications of Data Converters

One of th basic problems in specifying the transfer function of an A/D convert is
that the characteristics of the transfer function are dependent on the application and test
circuit, the type of input signal, and the sampling rate of the converter [55]. This section
reviews the important parameters and terminology used in the data converters developed
in this thesis.

Dynamic range is the ratio of the largest input that can be converted to the smallest

step size of the converter. For example, a 10-bit current-mode ADC with an input range

from 100p.A to 600p.A has a quantization step size of (600p.-100].t)/210==0.5uA. Therefore,
the dynamic ratio is 1024 and can be also expressed in decibnels as 20 log1024 = 60 dB.
Resolution refers to the number of quantization levels an input signal can be deter-
mined to. This number is usually given in bits. For example, if which of 1024 levels an
input signal lies within can be identified, then the converter is said to have an 10-bit reso-
lution.
Effective number of bits (EN OB) is a measure of overall A/D performance under

dynamic conditions. Cumulative effects of many error sources such as quantization noise,

l6

1d:

1101

'1.

din

mt

dynamic diffemtial nonlinearity error, missing codes, integral nonlinearity, jitter, and

noise, all contribute to a lower effective number of bits. In general, EN OB can be calcu-

lated from the SNR obtained from dynamic FFT testing, i.e., ENOB=(SNR-1.76)/6.02.
Differential nonlinearity (DNL) error is a measure of how uniform the transfer

function step sizes are. Each step size is compared to the ideal step size, i.e., (Imax-Iminy

(2b-l). An difference in magnitude is DNL error. If the DNL error is less than one LSB,
the converter will not have any missing codes. If the DNL error is less than 0.5 LSB, the
converter will be monotonic.

Integral Nonlinearity (INL) error is the deviation of code midpoints from their
ideal locations. A differential error is the error in a particular step size at any specific loca-
tion in the converter transfer function. Integral error is equivalent to the integration (sum-
mation) of these errors along the converter’s transfer function.

Signal-to-Noise ratio (SNR) is characterixed by sampling a pure sinusoidal input
and performing an FFI‘ on the collected data. SNR is the ratio of the magnitude of the fun-
damental frequency to the root mean square (ms) of all other frequencies including har-

monies.

2.3.3 CMOS SI ADC Circuits

The ADC circuits can be generally classified into three categories according to
their conversion speed: Flash/Folding techniques [29,32], Algorithmic/Successive
approaches [34,56], and Oversampling techniques [35,36]. Flash/folding techniques have
the fastest conversion speed but the lowest resolution, while the oversampling ones have

the slowest speed but the highest resolution. Cyclic or algorithmic conversion is well

17

[101
C01
D1;

501

of

1h

51'

th-

51

1h

known for its ability to achieve medium resolution within small silicon area [58].

Figure 2.3 illustrates the cyclic conversion algorithms: (1) based on the conven-
tional restoring numerical division principle [59], as shown in Figure 2.3(a), referred to as
conventional cyclic conversion algorithm; (2) based on the RSD (Redundant Signed-
Digit) cyclic conversion with the SRT division principle developed by Sweeney, Robert-
son, and Tocher [59], as shown in Figure 2.3(b); and (3) based on the RSD cyclic conver-
sion with the modified SRT division principle [24], as shown in Figure 2.3(c), referred to
as modified RSD cyclic conversion algorithm.

The conventional cyclic conversion algorithm, consists of the multiplication of two
of the signal to be converted followed by a comparison of the result with a reference volt-
age (current): If the signal is larger than the reference, the MSB (most significant bit) of
the output code is set to 1, and the reference is subtracted from the signal; else, the MSB is
set to 0, and no arithmetical operation is carried out. The remaining part of the signal, the
so-called “residue voltage (current)” corresponding to the partial remainder of the divi-
sion, undergoes the same operation for the next bit decision, and the loop is run until the
LSB (least significant bit) is obtained. The ADC in [8], as shown in Figure 2.4(a), adopts
this conversion algorithm. For the modified RSD cyclic conversion algorithm, two conver-
sion levels P and Q are used, where P is positive and Q is negative. If the input signal,
twice of the residue voltage (current) is larger than 2P, the output code bits is set to a 1 and
the reference is subtracted; if it is smaller than 2Q, the output code is set to -l and the ref-
erence is added; else, then the bit is set to 0 and no arithmetical operation is carried out.
The ADCs with switched-capacitor [58] and switched-current [10] techniques adopt this

algorithm. The modified RSD conversion algorithm provides a large tolerance for the

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2.3 Cyclic conversion algorithms: (a) conventional restoring numerical
division; (b) RSD approach on the SRT division; and (c) RSD approach
on the modified SRT division (referred to as modified RSD approach)

19

 

Comparato —o

 

Iref

+
Amplifie

 

 

#—

 

 

Comparator
Output
(to latch)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)
“—Cl -— C2 -"—' C3 H— C4 1
+’; Zia-c; (ii/(a zrma ‘4”;(
é'i/e §?/° 89/9 33/9 ”mp1 .,
t. e“ i. e“ t. e" t. e"
e a; 6 «>7 6 oi e «X 13}: _’
S S+d1(¢1+¢3)l s+d2(o1+<i>3)l Vrefl swap-<1)4
+d2(‘1’24’4’U +d1(¢2+¢ 4)
Ii“ Vma—f-D‘latchj;
11,2 ‘1‘
1““ comp S+¢2+¢4
(b)

Figure 2.4: Cyclic ADC Circuits: (a) in [8]; and (b) in [16,18].

20

comparator’s inaccuracy, thus high levels of noise, error effect, and even hysteresis are
allowed [58]. The detail design and operation of the ADCs with the above both conversion
approaches will be discussed in the next section.

The ADC in [8] employs a residual amplifier which takes three cycles to double a
current, and it requires 4 cycles to complete one bit conversion. The residual amplifier in
[10,58] also requires 3 cycles to double a current, but the ADC’s needs only 3 cycles to
complete one bit conversion. A dynamic calibration technique was employed to alleviate
the error due to component mismatch. However, the accuracy of the residual amplifier is
limited by two major error effects, charge-feedthrough and non-zero output conductance
of a copier. The errors are introduced and accumulated at each cycle. To reduce such
errors, a two-cycle residual amplifier for a SI cyclic ADC, as shown in Figure 2.4(b),

which takes only 2 cycles to complete one bit conversion was presented in [16,18].

2.3.3.1 4-cycle Conversion

Figure 2.4(a) illustrates the schematic diagram of the ADC circuit [8], where a 3-
cycle residual amplifier, as shown in Figure 2.2(a), is employed. The converter is com-
prised of two N MOS current copiers, one PMOS copier, an op-amp, and a current compar-
ator. The converter starts converting for the most significant bit (MSB) of an input current

Iin by generating twice the input signal and holding into P1. After doubling the current, the
current held in P1 compares with the reference current Iref in the 4th cycle. If the signal

exceeds the reference, the MSB will be a “1”, otherwise it will be a “0”. This completes
the conversion for the MSB.

The remaining (N- 1) bits are then converted in the same manner. The signal held in

21

P1 is loaded into N 1. If the preceding bit was a “1”, the reference is substracted from the
signal in P1. On the other hand, if it was a “0”, the signal remains unchanged. Once N1 is
set, N2 is followed by the same procedure of N1. The signal is then doubled and stored on
the gate of P1. Finally, it is compared with the reference. This sequence is repeated until

the desired resolution has been achieved. An end of conversion pulse is then generated to
signal the end of conversion. The converter achieves a 10-bit resolution and a sample rate
of 250 kbits/s.

This ADC adopts the conventional restoring numerical division principle. Taking
the comparator error into consideration, the residual current may fall off the convergence
region and provides incorrect decision [10]. Therefore, such an ADC design needs a com-

parator with high accuracy and an operation amplifier with low offsets.

2.3.3.2 2-cycle Conversion

The number of cycles in conversion can be reduced to two by using four current
copiers and comparing the residual current in the amplification phase [16,18]. Figure
2.4(b) shows the structure of the 2-cycle AID converter. During the conversion state,

where the start signal S is low, the four copiers are grouped as two copier pairs, gm” and
gm3_4. At each bit conversion, the residue current, the sum of the currents stored in a
copier pair, is copied during (b1 and (D2 (or (1)3 and (D4) to two current copiers to gm] dur-
ing (D1, while this sum is copied to gmz during (D2. The sum of the current stored in the lat-
ter pair (gml and gmz) becomes the new residue current and is copied back to the former

pair (gm3 and gm4), respectively. Since it takes one cycle to copy the residue current in the

22

former pair to a current copier in the latter pair, the residue amplifier takes only two cycles
to double a current. Two comparators are used to monitor the transconductance current
indirectly. The relationship between the input voltage and the current in the transconduc-

tance is Ii=gmchi, where Ii is the current of transconductance gmi and Vci is the voltage
on the capacitance Ci. Therefore, the voltages Vci can be compared with the reference
voltages Vrefl and Vrefz in the circuit. Since large comparator errors are permitted by a

RSD algorithm, neither exact transconductance nor accurate comparators are needed. The

comparison results are latched at the ends of (1)2 and (b4, where the conversion for one bit
is completed. The single-bit binary outputs d1 and d2 of the latches control the two refer-
ence currents Irefl and Irefz to implement a RSD algorithm. There exists a large tolerance
of Iran/4 for the comparison levels. Results show that the 2-cycle ADC can achieve 12-bit

resolution, 50ns/b conversion rate, and 5mW power consumption.

2.3.4 CMOS SI DAC Circuits

Figure 2.5(a) illustrates a design of current-mode DAC, where the current refer-
ence generator (CRG) generates the current references, or binary weights, for the con-
verter. Figure 2.5(b) shows a typical CRG circuit, where the current references are
realized by ratioed currents. To obtain accurate signal multiplication/division without the
need for well-matched components, a switched-current CMOS CRG circuit using MC
approach, referred to as CRG_MC circuit, was developed in [60] which generates the cur-
rent references in (2.8) and (2.9). Recently, a switched-current CRG circuit using DC

approach, referred to as CRG_DC circuit, was presented in [47] which generates the cur-

23

 

 

 

 

 

 

 

 

 

 

:3 1
Data E Clontrol Iout

a: 0ng .
Input .

53’ Ga“: 1°“ Swrtch Array

 

 

 

 

 

 

 

 

 

 

 

e H

IT,
2.21 at h

 

 

 

 

 

 

Current Reference

Generator (CRG)

 

 

 

3
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
F v
I

 

 

m
C

 

v

5‘

--u------ p--------
1)
——0
m
w
II
'4-
U)
W].
.5.”

 

 

 

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I.

A
O
v

Figure 2.5 Current-Mode DAC circuits: (a) a typical design;
(b) a typical current reference generator (CRG);
and (c) a 81 DAC with CRG_MC [47].

24

 

L".

fl.

 

i

r\
0!.»

rent reference in (2.5) and (2.6). Thus, both CRG_DC and CRG_MC can be used as the
current reference generator of the DAC in Figure 2.5(a).
Figure 2.5(c) shows the algorithmic current-mode DAC in [47]. The converter con-

sists of a current Reference-Generating Unit (RGU), a switch SI, and a current ACcumula-

tion Unit (ACU). The RGU is used to generate the double current reference [60] which is

exactly the same as the CRG_MC circuit; The switch SI is controlled by the digital input
code, where the switch is turned on when bi=1 and off when bi=0, for i=N, N-1,.., 1; The

ACU is employed to conduct the current accumulation in (2.8). The RGU, realized by the

multiply-by-two circuit (MX2), is shown in Figure 2.2(a). The double current reference Ik
generated by the RGU is stored in P1. The ACU is comprised of an NMOS copier and a

PMOS copier with an op-amp. Whether or not a current reference generated by the RGU

is accumulated is determined by each input bit bk. If bk=l, i.e., SI is on, then the current
reference is accumulated and finally stored in Pa; otherwise, the current held in Pa is

unchanged. The RGU needs four cycles to generate a current reference for each bit con-
version, while the ACU requires two cycles for the current accumulation. Therefore, for
repetitive conversions of continuously changing inputs, the converter requires (4N-2)
clock cycles for simultaneously converting three N-bit digital data signal. For a single con-
version, the converter may need (4N-1) cycles. Conversion rate can be improved by using
a parallel DAC presented in [47] in which the converter can simultaneously convert seven
digital data signals in a demultiplexing fashion. The PMOS copier in the ACU is used to
store the accumulated current while the NMOS copier acts as a temporary storage ele-

ment. Conversely, the reference current is stored in the NMOS copiers of the RGU. Thus,

25

 

Ci

the NMOS copier in the ACU holds the accumulated current while the PMOS copier is

used only as a temporary storage element.

2.4 Test Generation of SI Circuits

Although mismatched components are allowed in SI circuits, the SI circuits are
still susceptible to faulty switching elements. Any faulty switching elements may result in
an incorrect converted data. Based on single stuck-at fault model on the switching ele-
ments, the fault behaviors of the ADC in Figure 2.4(a) have been reported [51], in which a
faulty switch can be either permanently stuck-at ON state (S/ON) or OFF state (S/OFF).
The failure of other components can be modeled as the fault of the associated switch.
Thus, the converter can be fully testable. Due to the simplicity of the test generation pro-
cess, a built-in self-test (BIST) design of the ADC is developed in [62]. However, the sim-
ulation results reported in [48] show that stuck-at faults, or catastrophic faults, are
approximately 70% of the total faults. This implies that 30% of the total faults are still
undetectable. These faults are referred to as parametric faults. Therefore, an efficient and
effective fault macromodeling process was developed to enhance the testability of SI cir-

cuits [48].

2.4.1 Fault Models

Based on circuit layout, technology data, and defect statistics, a set of fault types
was developed [50]. According to the functionality of switches in a SI circuit, two types of
switches can be identified: voltage switch and current switch. Based on the circuit layout,

Table 2.2 shows five examples of process defects which are significant and cause the cir-

26

Table 2.2. Summary of defects and circuit ffllié.

 

 

 

 

 

 

 

 

 

Defect Circuit fault defect type
a floating drain/source Type f1
Break of metal , . , -
disconnects the swrtch’s input/output Type f2
a floating ate may tra some
amount ofgcharges on Rte gate Type f3
Break of gate isolates the gate of PMOS transistor I34)
poly silicon isolates thegate of NMOS transistor f3'N
shortens the channel width. Type f4
Digg‘: 12381. on increases the channel impedance Type f5

 

27

 

 

cuit to malfunction, and summarizes the faults due to these defects. Based on the defects,
four fault types of the voltage switch and three fault types of the current switch are con-
cluded and summarized in Table 2.3 [48-51]. Based on the fault types, test generation pro-
cesses for current copiers [50] and SI ADC [49] were reported and they are discussed

below.

2.4.2 Test Generation of Current Copiers

Consider the basic current copier cell in Figure 2.1(a). The switch faults are sum-
marized in Table 2.2, and the faults on current-storage transistors and holding capacitors
can be modeled as the equivalent faults of the associated switch(es) [48,61]. In addition,
the following defects may occur in a current-storage transistor. Breaks on gate polysilicon,
a Type f3 defect, is equivalent to an S/OFF fault on the associated voltage switch, a Type
VSl fault. Shorten channel width, a Type f4 defect, is equivalent to a Type CSl fault.
Break on metal, either drain or source, a Type f1 defect, is equivalent to an S/OFF fault on
the associated current switch, a Type CSl fault. A short between drain and gate implies an
S/ON fault on the associated voltage switch, a Type VS2 fault; A short between source
and gate, or between drain and source, is equivalent to a S/OFF fault on the associated
voltage switch, a Type VSl fault. Any defects in active region, a Type f5 defect, is equiva-
lent to a Type CSl fault. Any process deviation causing an increase of on-resistance
implies the presence of a Type CSl fault. The following defects may occur in the holding
capacitors. Any defects causing a decrease of capacitance, or an open circuit in the capac-

itor, is equivalent to a Type VS4 fault on the associated voltage switch. Any defects caus-

28

Table 2.3. Fault gyms.

 

 

 

 

 

 

 

(a) Voltage Switch
Fault Time Leakage
Types Constant Current
V81 Intolerable Tolerable
V82 Tolerable Intolerable
V83 Intolerable Intolerable
V84 Excess charge flows out

 

switch when switch is off

 

 

 

 

 

 

 

(b) Current Switch
Fault Error Current Leakage Current
Types (switch is on) (switch is off)
CS 1 Intolerable Tolerable
C82 Tolerable Intolerable
C83 Intolerable Intolerable

 

 

 

 

29

ing an increase of capacitance, or a short circuit in the capacitor is equivalent to a Type
V81 fault

The above equivalent faults include both catastrophic and parametric faults for
both current-storage transistors and the holding capacitors in a copier. Based on the fault
types in Table 2.3, the fault behaviors, as illustrated in Figure 2.6 [50], can be distin-
guished from the fault-free behavior by the test sequence. Thus, all fault types in Table 2.3

can be tested.

2.4.3 Test Generation of ADC Circuits
Consider the ADC from Figure 2.4(a) with a comparator, as shown in Figure 2.7.

In the comparator, a current copier consisting of N3, C4 and switches 8x and 8),, is used as
a load to copy the difference current Ix. Since the difference current may be positive or
negative, a bias current source Ibl is used to keep a positive current to be copied to N3. A
current which is slightly higher than Iref is chosen for Ibl- The copier memorizes the cur-
rent Ix and produces a voltage deviation to compare to a zero-voltage in the comparator.
Since the resolution of an ADC is 0.5 LSB, or 0.5 Iref, here a simple comparator instead of
window comparator, can be used. It should be noted that an additional bias current Ib2=Iref
and the switch 82 are used only for testing purpose. During the normal operation, 82 is off

and the bias current is isolated from the converter circuit. Thus, the extra circuitry does not
affect the performance of the converter.

In Figures 2.4(a) and 2.8, 81, 82, 84, 86, 88, 8x, and 82 are current switches, while

83, 85, 87, and 8y are voltage switches. The ADC consists of four copiers. One may apply

30

_ Tm V84 fault

Fault-free
“h; ; PType V83 fault

............ \
I
I

\ Type V82 fault

Type V81 fault

 

 

 

 

 

 

’—
0'
fl
r—
G"
N

 

 

 

 

 

S
~<
Kc

..2

Figure 2.7 Simplified schematic diagram of SI algorithmic ADC
with additional comparator

31

the test sequence developed in the previous section for all copiers in the ADC. However, in
the ADC, we can only observe the result from the output of the comparator, i.e., the con-
verted digital data. Thus, the test sequence should be generated to maximize the accumu-
lated errors so that the error effect can be reflected to the converted digital data [49].
Figure 2.8 illustrates the fault behaviors and switching sequences of a test
sequence, referred to as Test Sequence A, which detects Types V81, V83, and V84 faults

for 83, 85, and 87, Types C81 -C84 faults for 81, 82, 84, 86, and 810, and Types C82 and
CS3 faults for 8x. Figure 2.9 shows the fault behaviors and switching sequence of another

test sequence, referred to as Test Sequence B, which detects Types V82 and VS3 faults for

S3, 86, 87, Types CSI and CS3 faults for 8,, Types C81 -C83 faults for Sz, and Types V81-

V84 faults for 8? This implies that both test sequence will detect all switching faults.

2.5 Discussion

Current copier is the basic building block of a 81 circuit. The performance of a 81
circuit is determined by the performance of the current copiers it employs. Thus, synthe-
sizing optimum current copiers for SI circuits beomes very important task in the SI circuit
design [63].

The objective of this study is to develop high performance and low power data
converters. For the design of CMOS 81 DAC circuits, as discussed in Section 2.3.4, the

CRG circuit can be either realized by using the CRG_DC circuit or CRG_MC circuit.

However, for an N-bit CRG_DC circuit, its LSB current, ILSB=IFSI2N, cannot be lower
than its SNR. This implies that its bit size is limited by the given full-scale current IFS. It

also implies that, for a given 8N R of an N-bit CRG_DC circuit, the only way to increase

32

 

'a

I

'I
--.--J — d
o.

 
 

Fault-free

\

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vcr ‘.
—' i
- — —1 — — — J:- — - _ _
Oi I V1012 ‘~\ >t
MW: ”HM
MSB (n-2.).-brts LSB MSB (n-2)-bits LSB MSB (n-2.)-.brts LSB
Iin=Iref Iin=0 Iin=lref
(a)
51 l l .
32 M M M
S3 __l'__l___ _l'_|___ ___J'__l—
S4 ___J——l_ __l——-1_ ___l'—l_
85 ___i_i__ ___J—i__ __i_‘l_
56 I r 1
S7 l—l_l_l__ —_l'—l._ l 1
S10 1 l | —L_I_'1 1—]
8y J—l 1—1 1“]
SI
MSB Previous Bit=1 Previous Bit=0

(b)

Figure 2.8 Test sequence A: (a) Fault behaviors; (b) Switching sequence.

33

 

, . """"" VC2
r oooooooooooo I.
- k ...................

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Error of Vgsz Error of Vgsz
w w a
I I I I I I I I I I I I r
41 2 3 4 5 6“] 2 3 4.5 6:: __
MSB 2nd bit
(21)
SI
S2 __I——fi_ —I—‘—1_ _I——I__
83 J;_ ____I——I j
84 —_r—1_ E It
SS .____i—i_ 1—1 J—i
6 _l_L_.I'__l__ _J_|_l_l I"-—__l__
57 _l—1 I—I ' |————
Sror—fi l_fi i l—1 L—
x m F—lfi r1 l——l____l_l_
Sy l—L___i'—l_ r—1 m I—1____I—I_
Sz I-—I___ fl r—L__
forS
for S3 (b) 5 for S7

Figure 2.9 Test Sequence B: (a) Fault Behavior; and (b) Type V82 fault.

34

the bit size is the use of larger IFS, but it will be penalized by the increase of power con-

sumption. This concludes that the bit size of both CRG_DC and CRG_MC circuits cannot
be arbitrarily large for low-power applications. Therefore, to increase the resolution of a
81 CMOS DAC circuit for low-power application, Chapter 4 will present alternative struc-
tures of DAC circuit combining CRG_DC and CRG_MC circuits.

As discussed in Section 2.4, test signals for testing current copiers and ADC cir-
cuits with the catastrophic faults can be easily generated and applied. However, test gener-
ation for those circuits with the parametric faults will become much complex [48]. This is
partially due to the lack of accessibility. As suggested in [48], a built-in tester can be used
to simplify the test generation and application. In practice, however, the built-in tester
must be able to test itself to increase the reliability of the tester and also autozero the com-
parator to increase the accuracy of the tester. Chapter 6 presents a built-in tester which

includes a current comparator with autozero and self-test capabilities.

35

Chapter 3

CMOS SI ADC CIRCUIT DESIGN

This chapter presents a high-speed, high-resolution, and low-power CMOS SI
ADC circuit [64]. High performance is attributed to the use of the following components:
(1) a high-perforrnance residual amplifier which takes two clock cycles to double a cur-
rent; and (2) an efficient cyclic RSD algorithm which provides 1.5b resolution without
using two matched reference currents. Section 3.1 describes the design and operation of
the developed ADC using a 2—cycle residual amplifire and 2-cycle conversion algorithm.
Section 3.2. discusses the design consideration for achieving high performance and lower
power. Section 3.3 presents the design, simulation, layout, and measurement of the fabri-

cated chip. Finally, a concluding remark is given in Section 3.4.

3.1 Design and Operation

This section presents the developed 2-cycle residual amplifier and 2-cycle conver-
sion algorithm. The special features in the residual amplifier are: (1) the amplifier has a
negative gain; and (2) the use of two reference currents which do not need to be well-
matched. Based on the special features, the modified RSD algorithm is used for the devel-

oped CMOS SI ADC.

36

3.1.1 2-cycle Residual Amplifier

To reduce the number of cycles, a 2-cycle residual amplifier is developed as shown
in Figure 3.1(a), where four copiers are used. First, the input current is copied to copiers l
and 2 in two consecutive cycles, where 11(1)=12(1)=Iin. Then, the sum current,
11(1)-I-12(1)=21in are stored to copier 3 and then to copier 4. Both copiers 3 and 4 hold the
same doubled current, i.e., 13(2)=I4(2)=Ix=21in. Similarly, the sum currents, 13(2)+I4(2)=
21x, are then stored to copier l and then to copier 2. Thus both copiers 3 and 4 have the same
doubled current, i.e., 11(1)=12(1)=2Ix.

Let 11(2m-l) and 12(2m-1) be the currents held in copiers 1 and 2, respectively, and
determine the (m-1)-th bit Dm_1. The sum current I 1(2m—1)+12(2m-1) is stored to copier 3
and then copier 4, as shown in Figures 3.1(b) and 3.1(e), where 13(2m)=I4(2m)=Il(2m-1)+
12(2m-1). The sum current determines the m-th bit. Similarly, as shown in Figures 3.1(d)
and 3.1(e), the sum current 13(2m)+14(2m) is copied to copier 1 and then to copier 2 to de-
termine the (m+1)-th bit. The process is repeated and it takes 2 cycles to double a current.

When the sum current 11(2m-1)+12(2m-1) is stored to copier 3, once the copier is
settled, the voltage at node X, as denoted in Figure 3.1(a), is compared to determine the m-
th bit. Similarly, the (m+1)-th bit is determined when the sum current is copied to copier 1,
as shown in Figure 3.1(d). Thus, the ADC design using the developed residual amplifier

takes only 2 cycles for one bit conversion.

3.1.2 2-cycle Conversion with Modified RSD Algorithm
Figure 3.2 shows the schematic circuit diagram and block diagram of the developed

SI cyclic ADC design, where copiers 1 and 2 are implemented with NMOS copiers, and

37

 

 

v .8300

 

 

 

 

m ..oEOU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

v 830 , BRO
o / 2.9% N u
m BEoU g BEoU
@5va 2-88:.
X
v 8390 II/ 0.1 m 530
m 6&8 l/ 9| Cameo

 

 

 

 

 

 

(b)

(a)

 

 

v “£30 ,

 

 

 

 

m Baou

 

 

 

 

v e380

 

 

 

 

m 8300

 

 

and:

25s

2:53

 

 

N 33.5

 

 

 

 

fl ..oEoU

 

 

 

 

 

m “cameo

 

 

 

(e)

((1)

Figure 3.1 Proposed 2-cyc1e residual amplifier: (a) block diagram with 4 copiers;
(b)&(c) operations for m-bit; and (d)&(e) operations for (m+1)-bit.

38

 

 

 

291%—

v 2 comm

 

 

 

 

 

 

 

COMP3

 

 

 

my“

Digital Circuit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)
v—I —-I V V
.3 a Q 3 .__p1 ,
a b: 'a g. if 1'
O 4:
I + U U 11:: al
3 Vac 2+ 3 :—
i
Iiv : ii
V 2 ' 4i
T T T I cn" a2
2 ‘2 E e i b2
o. a. I2
0 o
u U I l

 

 

 

 

 

 

 

 

 

 

 

 

 

(b)

Figure 3.2 Proposed switched-current CMOS cyclic ADC:
(a) schematic diagram; and (b) block diagram.

39

 

copiers 3 and 4 are implemented with PMOS copiers. In addition, two bias current sources,
Ibiasl and Ibiasz, and two reference current sources, Ire“ and 1,612, are employed. Two pairs
of comparators are used: the upper pair compares the voltage at node X when the residue
current is copied to copier 3, as illustrated in Figure 3.3(a), while the lower pair compares
the voltage when the residue current is copied to copier 1, as shown in Figure 3.3(c). The
ADC design adopts a modified RSD conversion algorithm described below.

Consider the modified RSD conversion algorithm, as illustrated in Figure 2.3(c).
At each bit decision, two comparison levels P and Q are used, with P positive and Q nega-
tive. If the input signal I" is larger than P, the output code bit is set to l and the reference is
subtracted; if Ix is smaller than Q, the output code bit is set to -1 and the reference is added;
else, then the bit is set to 0 and no arithmetic operation is carried out. If the comparison
takes place before the multiplication by 2, the only requirement on the comparison levels
is 2P6 [0,Iref] and 2Qe [-I,ef,0], as shown in Figure 3.4(a), i.e., PE [0,1,65/2] and Q6 [4,6,4
2,0]. Setting P and Q, respectively, at about +Iref/4 and -I,efl4, as shown in Figure 3.4(b),
provides a large tolerance of 1'1th for the comparator’s inaccuracy, thus high levels of
noise effect, and even hysteresis are allowed. However, the probability of having b=0 be-
comes only 25%, where both b=1 and b=-1 take 75%. Note that the converter circuit takes
no operation when b=0. Therefore, this implementation chose P=+Irepl3 and Q=-Iref/3 to in-
crease the probability of b=0 as 33%. Note that the tolerance of the comparator’s inaccura-
cy is firef/6 which is sufficiently large for us to comfortably design the comparator, where
Iref=250uA is used in this implementation.

Let Ires(m-l) be the residue current that determines the m-th digit, where

Ires(m-1)=Il(2m-1)+12(2m-1)

40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VBEOU .lvlool m 1 and IV
35: w.
m ..oEOU III of) Cl Nag: 17
m, 2.8%.
so: .v I m N 5&8
m.
-8 _
SEE Iv lvloéloi: NV H "BERG
l 2
v._ a
veoaou Ll m 1 Eu: Iv
m.
35:
m 3&8 riot/oi use .v
a 2-83:
Co: .v m Io.cI|Io.Y N $300
m...
-8 _
333 .v Ivloelloivic NV H 20:50

 

 

 

 

 

 

(b) 114-12 -) 14

(a) 114-12 -) I3 and comparison

 

mac:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a. snow , m... up: I
a
m 5&8 use +
Co: .v N 5300
use .v _ eoaou
m m
v V
AENVJ m
whoaou IVIOAI In Go: Iv
8
35:
m 3&8. Name +
Co: .v W IOaI/oi N 8:50
3:: .v Cage

 

 

 

 

 

 

(d) I3+I4—) 12

(c) I3+I4 —-> I] and comparison

Figure 3.3 Bit conversion: (a)&(b) Operations for m-bit;

and (c)&(d) operations for (m+1)-bit.

4l

Residue Ix“

Current ,

  

 

 

     
    

  
      
 

vlvlvlvl'vl‘
A ‘ A
L - - 0....

  

 

I/I/ .

$v.v‘vAvAv

’21:,zyfl’llll

Region 3 Q ; Regionl

Region 2

— : Comparator’s inaccuracy range

0))

 

 

 

Figure 3.4 Modified RSD conversion algorithm: (a) Robertson diagram;
and (b) Conversion ranges and comparison levels.

42

By Figures 3.3(a) and 3.3(b), the currents stored in copiers 3 and 4 are

 

i Ires(m'1) ' Ibiasl' Irefl 3 Region 1
13(2m)=I4(2m)= t Ires(m-l) - Ibiasl : Region 2 (3.1)
t Ires(m-1) - Ibiasl + Iref2 I Region 3

where the convergency regions are defined as
' 1 if Ires(m-1) > Ibias1+1mfll3 : RegiOn 1

Dm_1 = i 0 if Ibiasl'lref1/3 51ms(m'1)51bias1+1ref1/3 : Region 2 (3.2)

 

. -1 if Ibiasl‘lref1/3 > Ires(m-l) : Region 3

Similarly, for the (m+1)-th bit, by Figures 3.3(c) and 3.3(d) the residue current is

Ires(m)=l3(2m)+ 14(2m), and the currents held in Copiers 1 and 2 are

r

 

Ires(m) " IbiasZ' Iref2 I Region 1
11(2m+1)=12(2m+1)=* Ires(m) - IbiasZ : Region 2 (3.3)
Ims(m) - IbiasZ + 1an : Region 3

where the convergency regions are defined as
1 1 if 1mm) > Ibias2+1mle3 : Region 1

Dm,1 = t 0 if Ibiasz-Imsz S Ims(m) _<. Ibia52+Iref2/3 :Region 2 (3.4)

 

. -1 if Ibias2'Iref2/3 > Ires(m) : Region 3
The m-th converted digit Dm is encoded as <1, l>, <0,1>, <0,0> for Dm=1 (region 1), 0 (re-
gion 2), -1 (region 3), respectively. Let b2(m) be the bit complement of a2(m), i.e.,

1 if a2(m)=0
b2(m) = (3.5)
0 if a2(m)=1

Therefore, (3.1) and (3.3) can be respectively written as the following general form

13(2m)=I4(2m)=Ires(m-1)-Ibiasl-a](m-1)Iref1+b2(m-1)I,ef2 (3.6)

43

11(2m+l)=12(2m+1)=Ims(m)-Ibia32-a1(m)Iref2+b2(m)Iref1 (3.7)
where the residue currents are
Ires(m-l)=Il(2m-1)+12(2m- 1)=21,es(m-2)-21bia32-2a1(m-2)I,ef2+2b2(m-2)Irefl (3 .8)
1,65(m)=I3(2m)+I4(2m)=2I,es(m- 1 )'21biasl'231(m‘ 1)I,ef1+2b2(m- 1 )Irefz (3 .9)
It should be noted that, by (3. 1) and (3.3), the stored current is with Ire“, Iran, or neither.
Thus, both reference currents Ire“ and Irefz are not necessary to be well matched. However,
the use of well-matched reference current sources guarantees the quality of the stored cur-
rents, i.e., 11:12 and 13:14, and also reduces the possible current variation in those copies.

Let Imf1=Iref2=Iref2 Also, let Ibias1=1bias2=1b- Therefore, (3.l)-(3.4) can be summarized as

 

 

 

 

 

 

 

 

 

 

 

follows.
Region Dm a1 a2 b2 Ires(m+1) Convergent Range
1 1 1 I 0 21135011) - Ibias - Inf Im(m) > Ibias+Ime 3
2 0 0 l 0 2Ims(m) - Ibias Ibias‘Irell3 S 11.68011) S Ibias‘i'lrelB
3 -l 0 0 1 21m3(m) - Ibias + Inf Ibias-Imfi > Ims(m)
3.2 Design Consideration

The goal of the developed ADC is to achieve low-power with low supply voltage
and moderate conversion speed. There exist design tradeoffs among speed, power con-
sumption, SNR (signal-to-noise ratio), and etc. The speed can be improved, i.e., the de-
crease of the settling time, by increasing the bias current at the cost of increasing power
consumption. The SNR can be reduced by also increasing the bias current while keeping
the same input dynamic range. On the other hand, the SNR can be increased by using a

large storage capacitance.

44

Current copier is the basic building block of a 81 circuit. The performance of the SI
circuit is generally determined by the performance of the copiers it employs. The calibra-
tion speed of the copier is determined by the time constant ‘tzC/gM, where C is the capac-
itance of the storage capacitor and gM is the transconductance of the storage transistor M.
Apparently, increasing the gate capacitance results in a slow calibration speed. The ques-
tions are: Can a copier with a large gate capacitance still be operated at a high calibration
speed? how does gM, aflect the accuracy? and what are the design constraints on selecting
C for keeping the time constant 1 small? The issues on selecting appropriate capacitance
has been addressed and can be found in [13-16].

For low-power application, the storage capacitance should be limited by its SNR re-
quirement and determined as follows [65-68],

SNR = 10 log[Vcn2(rms) / (RT/CH (3.10)
where Vcn(rms) is the tolerable noise variation across the capacitor, T is the operation ab-
solute temperature, the Boltzmann constant k=1.23"‘10'23 JK'l, and C is the storage capac-
itance. Thus, for 12-bit resolution, i.e., SNR=74 dB, if Vcn(rms)=1 V, by (3.10), we obtain
the storage capacitance C=0.093 pF, where T=300° K. Note that this implementation,
Vcn(rms)=0.85 V. With a 74 dB SNR for the 12-bit ADC, the storage capacitance is ap-
proximately 0.11 pF. As mentioned, the larger capacitance can decrease noises and errors,
and thus decreasing the DNL and INL.

The transistor sizes are determined by the input dynamic range and the bias current.
The transistor size should be sufficiently large to operate in the saturation region so that the
current can be held correctly. Note that VgS-VT < Vds when the transistor is operated in the

saturation region. Taking the process variation into account, for purpose of safety, this im-

45

plementation sets the maximum voltage of (Vgs-VT) to be 85% of Vds, i.e., Vgs(max)'
VT=O.85Vds. For a power supply of 3.3V, VdS=1.65V. This implies that the maximum volt-
age Vgs(max)-V1=0.85Vdszl.4V. In general, to keep the transistor inside the strong inver-
sion region, we need Vgs(min)‘VT=0-2V- If the input currents are ranged from Ibias-(Imax/Z)
to Ibias+(lmax/2), then

[1b,,3+(1m,,/2)] / [rm-(Im/zn = [0.85vd5/o2]2

Therefore, the transistor sizes are selected based on the selected Ibias and Imax.

3.3 Simulation Results and Measurements

The developed ADC circuit, as shown in Figure 3.2(a), employs four copiers with
the current-storage transistors Ml-M4. Both In,“ and Ibaisl are implemented with two
PMOS transistors, Mn,“ and Mbaisl’ and Item and IbaisZ are with two NMOS transistors,
Mrefz and Mbaisz- Switches 82“, 82p, 84“, and 84p are realized by CMOS switches with
dummy switches to alleviate the charge-feedthrough errors, while the remaining switches
are implemented with simple CMOS switches. The copiers with negative feedback struc-
ture are used to reduce the error due to channel-modulation. The digital logic circuits, real-
ized by CMOS transistors, are used to produce the digital codes and the control signals.

The circuit has been designed and simulated by pspice, where the SCAN20 211m
CMOS process with level-2 transistor parameters and a supply voltage of 3.3 V are
employed. The transistor sizes for both M1 and M2 are 36 uni/2 um, and for both M3 and

M4 are 80 urn/2 um, where the transconductances of both NMOS and PMOS transistors

are 780 [IA/V and 730 uA/V, respectively. All capacitances are 0.2 pF. The reference and

biased current are chosen as Iref=Iref1 =Iref2=250 11A and Ibias=Ibiasl=Ibia52=350 11A. The

46

bias voltage for the feedback amplifier is Vbias=l.65 V. In the comparators, ch1=l.813 V,
ch2=1.6 V, Vcn1=1.46V, and Vcn2=1.689 V were chosen. The chip layout has been gener-

ated by L-edit and simulated by pspice. Simulation results show that the current storage
transistor can be converged within 30 us. However, a clock rate of 50 us is chosen for this
ADC simulation.

Figure 3.5(a) shows a typical current waveform in a current-storage transistor,

where Figure 3.5(b) plots the partial output of Ire“ to demonstrate the three states in the

RSD approach. Since the clock rate for calibration is 50 us, one state is obtained in every
100 ns. Figure 3.5(c) summarizes the accuracy of the proposed ADC which achieves a 12-
bit resolution for the input currents ranged between 100 ILA and 600 11A. The power dissi-
pation is approximately 1.9 mW.

It should be mentioned that the effects on mismatched reference currents, i.e.,

Iref1¢1ref2, and loop offsets errors, have been studied. The proposed ADC will keep the

same accuracy and the lower limit of the dynamic range. However, the upper limit of

dynamic range decreases as the error effects. More specifically, if both currents 1an and
Irefz are off r% from Iref, or the loop offset error increases r%, the upper limit of the

dynamic range will be reduced approximately (r/2)%.

Figures 3.6(a) and 3.6(b) show the layout of the designed chip and the die photo of
the fabricated chip, respectively. The ADC is fabricated by MOSIS with the SCNA20 211m
N-well CMOS process, where the threshold voltages for the NMOS and PMOS are 0.83V
and 0.99V, respectively. The test chip does not use the double-poly linear capacitor, i.e., it
is fabricated by a digital CMOS process. The 40-pin test chip is comprised of three major

parts: analog portion, digital portion, and clock/pulse generator portion. The analog por-

47

 

 

0A1.---__--.l ........ i____

Os 0.2us 0.4us 0.6us

 

...........................

 

 

 

 

 

 

1.0us

 

...................

 

 

........ miss JAE-
0.6us 0.8us
(b)

 

 

 

 

 

.........

 

.........

Figure 3.5 Simulation results: (a) typical current in a current-storage transistor;
(b) partial outputs of Iref 1; and (c) 12-bit resolution.

48

0.08

0.06

o
8

0

error current (in nicro ampere)

ii
28

—0.06

-0.08

-O.1

 

 

upper limit for 12 bit resolution

 

 

lower limit for 12 bit resolution

I l 1

 

 

1
1 00 200 300 400 500 600
Input current In micro ampere

(C)

Figure 3.5 (cont’d)

49

700

Clock Control Part

 

l .

l. ‘.
I .
i; E
l .
I- -

I , - f i
W...—_..___._____.._ _..—~-----IA— ..

I

 

Figure 3.6 Implementation: (a) The layout of the designed ADC; (b) the die
photo of the fabricated AD

50

tion is approximately (0.967*0.42)=0.41 mmz, the digital portion is about
(0.967*0.52)=0.50 m2, and the clock/pulse generator is nearly (0.6*O.3l)=0.186 mmz.

The total active area of the fabricated chip is (1.628*1.311)=2.13 mmz.

To measure the test chip, a voltage-to-current (V-I) converter, as shown in Figure
3.7 [30], and voltage sources are used to generate the input current signals, where the volt-
age source for the V-I converter is 5 V. A 24.4 kHz sine wave is applied to the test chip at
a 0.8 Msamples per second conversion rate with a 3.3 V supply voltage to measure the lin-
earity of the test chip. The total of 102,400 test data are collected to process the DNL and
INL measurements. Figures 3.8(a) and 3.8(b) show the resultant DNL and INL, respec-
tively, where the maximum DNL and INL are 0.6 LSB and 0.5 LSB, respectively. The lin-
earity plots for 12-bit resolution show that the converter may potentially achieve 12-bit or
more resolution.

More specifically, as discussed in Section 3.2, for 12-bit converter, the required

SNR is set to 74 dB. For Vcn(rms)=0.85 V, the theoretical value of the storage capacitance

is 0.11 pF to keep both DNL and INL within 0.5 LSB. In this implementation, the capaci-
tances are all 0.2 pF for conservative design which will have about 77 dB theoretically.
Note that the use of larger storage capacitance can decrease both DNL and INL. In addi-
tion, since the converter adopts the RSD correction scheme, the use of smaller capacitance
can still achieve the desired DNL and INL. Therefore, with the RSD scheme and the use of
larger storage capacitor, the converter achieves very small DNL and INL. If the design
limits both DNL and INL to be within 1 LSB, the converter can have the potential to
achieve a 13-bit resolution. However, since the clock generator in the test chip was

designed for 12—bit resolution, the converter resolution is set to 12 bits.

51

 

 

 

 

 

Vref Q Iout
Ib2

Figure 3.7 Schematic circuit of voltage-to-current converter

 

52

 

 

II

II
III

I

‘l.

I

llllrl IIIII

llllllllllll‘l

 

Figure 3.8 Analysis of nolinean'ty: (a) The INL of designed ADC;
and (b) The DNL of designed ADC

53

 

 

Figure 3.9 FFI‘ analysis of designed ADC

54

Figure 3.9 shows the measured fast Fourier transform (FFT) spectrum of the test
chip. The input signal 24.4 kHz was applied and 24,576 test data were collected to ana-
lyze. The total harmonic distortion (THD) is -66.7 dB and the signal-to-noise/distortion
ratio (SNDR) is 65 dB which is about 9 dB less than the ideal value. Table 4.1 summarizes

the performance parameters.

3.4 Conclusion

This chapter presents a high-performance CMOS switched-current cyclic ADC,

where the ADC takes 2.13 mm2 in chip area, achieves a resolution of 12-bits, and con-
sumes only 1.9 mW in power. High-speed performance is achieved by reducing the arnpli-
fier stages in the feedback loop of the current copier, where only one stage is used in this
implementation. In addition, with the carefully designed switches, the effect of their para-
sitic capacitances on the settling behavior of the copier has been alleviated considerably.
Finally, the residue amplifier requires only two clock cycles and does not require the well-
matched reference currents. The converter has been designed, simulated, fabricated, and
tested. Experimental results endorse that the developed converter can be used for low-
power/low-voltage mixed-signal circuits.

With the successful development of the high performance and low power CMOS
SI ADC circuits, the next logical step is to develop high performance and low power

CMOS SI ADC circuits which will be discussed in the next chapter.

55

Table 3.1 WW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter Values
Technology 2 pm N-well CMOS
Resolution 12 bits
Conversion Rate 800 KSample/s
Full Scale Current 500 11A
DNL -0.6 ~ 0.6 LSB
INL -0.45 ~ 0.45 LSB
SNDR 65 dB
THD -66.7 dB
Power Supply Single 3.3 V
Active Area 2.13 m2
Power Consumption 1.9 mW

 

 

56

 

Chapter 4

CMOS SI DAC CIRCUIT DESIGN

This chapter presents the design methodology and performance analysis of a high
performance and low power 81 CMOS DAC circuit [69,70]. As discussed in Section 2.2,
the current reference generator (CRG) circuit is realized by ratioed currents as illustrated
in Figure 2.5(b). This study presents the CRG circuit design using 81 technique without
the need of well-matched components. The CRG circuit can be designed using the MC
approach, referred to as a CRG_MC circuit, or using the DC approach, referred to as a
CRG_DC circuit. Section 4.1 presents the design and operation of both CRG_MC and
CRG_DC circuits and the developed design methodology and performance analysis pro-
cess. In order to demonstrate the design methodology, Section 4.2 shows some design
examples. Section 4.3 disucsses the design limitations of the DAC circuit design using
both approaches for low power applications, and presents the developed DAC circuits.

Finally, a concluding remark for SI DAC circuit design is given in Section 4.4.

4.1 Current Reference Generator (CRG) Circuits
This section presents the design and operation of CRG_DC and CRG_MC circuits.
For high performance and low power design, a design methodology is developed and the

performance analysis process is also developed. The design methodology provides the se-

57

lection of the sizes for storage transistors and capacitors based on a given set of design spec-
ifications including input dynamic range, full-scale current, SNR, power consumption, etc.,
and the performance analysis estimates the calibration time, holding time, and accuracy of
the CRG circuits.

A CRG circuit generates multiple current references for data conversion. Its cali-
bration time is defined as the time required to generate all current references. Since the gen-
erated current references are held in current copiers, the held currents will leak out as time
progresses. The holding time is defined as the time for the circuit leaks a current which is
0.01% of the originally generated current. Finally, due to the charge injection error of the
current copiers, error currents are accumulated when all current references are generated,

and the accumulated error currents determine the accuracy of the CRG circuit.

4.1.1 CRG_DC Circuits

Figure 4.1(a) shows the block diagram of an m-bit CRG_DC circuit which is
generalized from a basic divide-by-two (DB2) circuit in Figure 4.1(b) [71]. The DB2 circuit
is comprised of three NMOS current copiers with N1, N2, and N3, two PMOS current
copiers with P1 and P2, and an op-amp. Basically, the DB2 circuit takes three clock cycles
to obtain half the input current if both transistors N2 and N3 are perfectly matched. As
mentioned in Chapter 2, a number of iterations, three clock cycles per iteration, may be
needed if there exists a mismatch between N2 and N3. This subsection discusses the
development of DB2 circuit and then presents the design and operation of CRG_DC

circuits.

58

 

 

 

 

 

N m E

a. a.
Q 8 :3 III 2
§ '§- 'é a

U U 8 p4|l\ S&____..
1"] Ib2 Ib3 Ibm
L I I IX 13>-
l l SOISS S7I S9I =

I- N - N I-

z 2” 86||188||2510||3

H I-

D 0

.§ E" C31 C4; C5; VSS

 

 

 

 

 

 

(a)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Copying Sequence (Iterations 1 to k-l)
D1 [Es/2:1MSB . ‘ ‘
D2 [EL—I N2& N3 Im& N34 N1 N1& N2—) P2
D3 Pz—mzsna Pzaug-m, mare—spa Vb3 M
Dml Pm.1->N2&N3 Pm_1&N3 ->N1 N, a N2 —> P ”’1'
I II

Copying Sequence (k-th iteration) [bi

l’->

-) &
&

-)P

 

MN II/an [ILMN [11.

 

 

1%

(d)

 

 

 

 

ICNI
Vss

 

Figure 4.1 CRG_DC circuit: (a) block diagram; (b) diVide-by-two (DB2) Circuit;
(c) current copying sequence; and (d) a 3-bit CRG_DC circuit.

59

 

   

 

 

 

   

 

 

 

 

 

 

 

 

 

 

 

 

 

a? a? v
% 3 ,§ ... DD Icl Icz
"" "g“ 8‘ S s
U U P4 p5 8___.I.
Ibl
Ib2 1b3 1i SI 53
I I I so i I ' l :
I I 85 S7 89 =
2m [SEII N1 [W N2 [310 N3
is c c c
g- 3; - 41 SI Vss
_ . U
0))

(a)

 

Copying Sequence (Iterations 1 to k- 1)
D1 [3,2451%

D2 Ibl-QN2&N3 Ib1&N3—)N1 N1&N2—)P2 VDD L J
D3 P->N &N P am ->N1 N1&N —>P Vb3
L 2 3 2 § 2 3 __{ MIMI—I] Iii-g:

om] Pm,1—+N2&N3 Pm.1&N3 —>N1 N1 8. N2 -9 In"1| I

Copying Sequence (k-th iteration) 1m
I —. ->P MN iI-AMIE/
—> &
. & ICNI

(d)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4.1 CRG_DC circuit: (a) block diagram; (b) divide-by-two (DB2) Circuit;
(c) current copying sequence; and (d) a 3-bit CRG_DC circuit.

59

4.1.1.1 Divide-by-Two (DB2) Circuit

Consider the DB2 in Figure 2.2(b). Based on the copying sequence in (al-cl) and
(A 1 -C l ), the circuit requires that 12 > 13 in order for the current copier to properly memorize
the current difference. In this study, an alternative DB2 circuit with an altemaitve copy
sequence is developed. Mor especifically, in the copying sequence (Al), the sum current of
Iin and I] is stored into the copiers with N2 and N3, where, by (b1) and (c1), 11:12-13.
Therefore, the sum current can be expressed as Iin+11=1in+(12'13)- It can also be expressed
as 1in+11=(IIn-I3)+12- Since Iin is always greater than N3, the difference current (Iin-I3) can
be stored in the NMOS copier with N1. The divider circuit functions properly regardless of
the mismatch. Note that the resultant current is held in the copier with N 3.

The following copying sequences can be used for the DB2 circuit in Figure 2.2(b)

(a2) _ Iin —) N2 & N3 (A2) P4 —) N2 & N3
(b2) Iin & N3 -> N] (B2) Iin & N3 -> N1
(C2) N1 & N2 —) P4 (C2) N1 & N2 —") P4

However, the input current needs to be available for many cycles, i.e., (a2), (b2), and (B2).
Figure 4.1(b) illustrates the developed DB2 circuit, where an additional current copier with
P5 is employed to store the input current. Thus, the input current is sampled and held only

once. The circuit implements the following switching sequence

(a3) Iin —9 N1 (A3) P4 —) N2 & N3
(b3) N1 —> P4 (B3) P5 & N3 —> N1
(03) N1 —) P5 (C3) N1 & N2 '—) P4

where (a3)-(c3) are for the preparation cycles, while (A3)-(B3) are for the conversion

cycles.

60

Figure 4.2(a) shows the pspice simulation results of theDBZ circuit with an input
current ZOOuA, where MOSIS SCNA20 2pm process technology and 3.3V supply voltage
were assumed, C1=C2=C3=C4=C5=8pF, (W/L)4=(W/L)5=152/2, (W/L)1=(W/L)3=71/2,
and (W/L)2=85.2/2 are simualted. Note that the mismatch ratio between N2 and M3 is 20%.
The figure shows the 3 cycles of the resultant currents 12 and 13. Results show that the DB2
circuit can reach 12-bit accuracy after 3 iterations.

Theoretically speaking, for a given mismatch ratio, the accuracy can be improved
as the number of iterations increases. In practice however, errors may be accumulated in
every cycle of the division process. As mentioned, a basic current copier suffers from two
major error effects: due to non-zero output conductance and clock feedthrough. Consider
the current copier with N1 in Figure 5.1(b), a clock feedthrough error occurs when switch
S6 is opened. Additional charges will be dumped into the holding capacitor C3. The
dumped charges from a CMOS switch can be expressed as

AQ = IQOLN -Q0Lpl = Cox*lLDN-LDPI*W*(VH-VL) (4.1)
where QOLN (QOLP) is the overlap capacitance charge in N- (P-) transistor, LDN (LDP) is
the lateral diffusion, C0" is the gate oxide capacitance, W is the channel width of the
transistor for S3, and VH and VL are the high- and low-level of the clock for the switch.

Figure 4.2(b) plots the voltage errors on the holding capacitor for various
capacitances. It shows that the voltage error decreases significantly as the capacitance
increases. (Note that the speed performance degrades as the capacitance increases.) The
resultant error current can be expressed as AI=gm*AQ/C, where gm is the transconductance
of the storage transistor. For an input current IOOuA, the error current is 0.12uA, where

C=1pF and gm=600uA/V. This means that the maximum accuracy of the copier is 9-bit,

61

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

120“ - . - . 2nd iteration 3rd iteration
. lst iteration - 1r r
i l
0A I l
2%» + ;_ , . - - . . '
0A . ;
ous 4us 8us 12us 16us 20us 24us
(a)
0.4 I l T r
0.35 *- -
E 0.3 ..
‘5
@025 “
'8
z 0.2 ..
O
t:
m 0.15 -4
0.1 .1
0.05 .
o l L l l l l
o 4 Capacitance (P19) 12 14 16
(b)

Figure 4.2 DBZ circuit analysis: (a) Simulation of DB2 circuit; (b) charge-injection
errors on the holding capacitor; (c) accumulated errors for various iterations

62

mismatch 20% with input current 100uA

 

10, I I T f I I I

1 st Iteration

 

 

 

 

E 10 2 ,- 1
E 2nd Iteration ‘
: 4th 'on
10‘3 r .
E 3rd Iteration
10 4 l 1 1 4 L r l
0 2 4 6 8 10 12 14
Holding Capacitor
(C)
Figure 4.2 (cont’d)

63

and thus limiting the number of iterations required for the divider circuit.

Taking the clock-feedthrough error effects into consideration, Figure 4.2(c) plots
the simulation results for the percentages of the accumulated error current in each iteration
for various capacitances, where the input current is IOOuA and a 20% mismatch was
assumed. Results show that the best accuracy is reached at the third iteration. The accuracy
is getting worse in the 4th iteration because the accumulated errors dominate. Results also
show that, in the 3rd iteration, the accuracy is no longer improved as the capacitance is up

to 4 pF.

4.1.1.2 m-bit CRG_DC Circuit

Based on the DB2 circuit, an m—bit CRG_DC circuit is comprised of 3 NMOS
current copiers with N1, N2, and N3, one current source with IFS/2, and (m—l) PMOS
current copiers with P2, .., Pm. The copying sequence for the m—bit RG circuit is listed in
Figure 4.1(c), where the sequence (Di) is for the first (k-l) iteration of the i-th bit division,
while the sequence (Di’) is for the k-th iteration. Figure 4.1(d) shows a 3-bit CRG_DC
circuit. For an m—bit RG circuit with k iterations, generating the first bit takes 2 cycles, the
last bit needs 3(k-1)+2 cycles, and the remaining bit requires 3k cycles. Therefore, the total

number of cycles is
KDC = 2 + (3k)(m-2) + 3(k-1)+2 = 3k(m-1) + l (4.2)

The generated current references are held in the current copiers with Pi’s, i=1,2,..,m.
It should be mentioned that the PMOS copiers in the CRG_DC circuit are realized
in slightly different way as those in the DB2 circuit. More specifically, the DB2 circuit em-

ploys the PMOS and NMOS switches for the PMOS and NMOS copiers, respectively,

whi‘:

IOU

int!

:‘—.
t )

4.1

33

while the CRG_DC circuit employs all CMOS switches to alleviate the charge injection er-
ror effect. In order to further reduce the charge injection error effect, the storage capacitors
in the PMOS copiers of the CRG_DC circuit are connected to VSS instead of VDD in Figure

4.2(b). The same PMOS copiers will be also used for the CRG_MC circuits.

4.1.2 CRG_MC Circuit

Figure 4.3(a) shows an III-bit CRG_MC circuit that produces ka=2k'11LSB,
k=1,2,..,m. The circuit is generalized from a basic multiply-by-two (MX2) circuit, as
shown in Figure 2.2(a). Given a current ILSB, the MX2 circuit accurately generates the
doubled current ZILSB. The circuit may take the generated current ZILSB as its input and
again generate the doubled current of 21153, i.e., 221133. The process can be repeatedly
applied to generate the current references ka=2k'IILSB, k=1,2,..,m. The m-bit CRG_MC in
Figure 4.3(a) is realized by 2 NMOS current copiers, one current source with ILSB’ and (m-
1) PMOS current copiers. Figure 4.3(b) shows the copying sequence. Therefore, the total

number of cycles required for an m-bit CRG_MC circuit is
KMC = 3(m-1) (4.3)

The generated current references are held in the PMOS current copiers.

For low power applications, the LSB current is generally very small and thus a bias
current is needed for the copiers to function properly [14,15]. Figure 4.3(c) illustrates the
realization of a 7-bit CRG_MC circuit. Instead of using Ix1=ILSB, we set Ix1=ILSB+Ibias_2-

The current reference 1x2 is generated by the following copying sequence

Ix] —> Mm; Ix] —> MN2; MN1+MN2‘Ibias_2 —> W2-

65

 

 

 

 

 

11.513

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XH
r-Copier N 2 —/——\_<: Copier P2 '-
>1
N
—\1- Copier P3 -
X
-\.<:
X
B

 

~Copier N] —/——

 

(a)

 

Copying Sequence

 

M1
M2 1X14 N1 111-) N2 N1& N2 —’ Pa
M3 '32—) N1 P2 —) N2 N1 & N2 -) P

 

 

 

 

 

 

 

 

 

 

Mm Pm_1—)N1 Pm.1—)N2 N1 & N2 —) PW

 

 

 

 

 

 

 

 

 

Figure 4.3 CRG_MC: (a) Block Diagram; (b) Copying Sequence;
and (c) 7-bit CRG_MC.

66

At the end of the multiplying cycle, the current copier with MX2 holds a current of
(ZILSB+Ibias_2): i.e., Ix2+1bias_2- When the current reference 1x2 is read, the current held in
the copier with MX2 and the bias current Ibias_2 are sunk simultaneously, i.e.,
Iout=(Ix2+Ibias_2)'Ibias_2=Ix2' Similarly, the current references Ixi‘s, i=3,..,7, are generated

by the following copying sequences,
Ix,i-1—>MN1; Ix,i-1—>MN2; MN1+MN2'Ibias_i -> Mx,i-l-

where the copier with Mxi holds the current (Ixi+1bias_i)’ Ixi=21x,i-l’ Ibias_i is the bias current
associated with the Ixi, and the clock signals (Dxi’s are shown in Figure 4.3(c). This results
that each pair (Mxi,MRi) together with Ibias_i produces the current reference Ixi° The use of
the 7 bias currents allows the generated current references to be used simultaneously. For
design simplicity, the bias currents Ibias_i are generated by the transistors MRi with the same
biased voltage Vbz- Since the bias currents will be canoelled out during the operation, there
exist no transistor mismatch problem in such an implementation. Additional transistor MR1

is needed for Ix1=ILSB+Ibias_2 to produce the bias current Ibias_2'

4.1.3. Design Methodology

In an m-bit CRG_DC, the current references Ibk=IFS/2k, k=1,2,..,m, are stored in the
storage transistor Mpk. As the copy sequence (D1 ’) in Figure 4.1(c), the current Ib1=IFS/2,
the largest current references, is copied to N1, and thus the transistor size of N1 must be suf-
ficiently large to operate in the saturation region so that 1b] can be held correctly. Taking
the process variation into account, for purpose of safety, this implementation sets the max-

imum voltage (Vgs-VT)max=O.85Vds. Therefore, the transistor size of N1 is chosen as

Ib1=(kn/2)(W/L)N1(O.85Vds)2 .._. (O.98k,,)(W/L)N1, or

67

(W/L)N1=Ib1/O.98kn (4.4)

where kn is the transconductance parameter of the NMOS transistor. Similarly, from the

copy sequence (D2), both N2 and N3 must be able to hold the current Ib1/2. Thus, we need

(W/L>N2= (W/L)N3=(1/2)(W/L)N1 (4.5)

The size in the PMOS transistors are selected in the same way. The size (W/L)p1 of Mp1 is
chosen to generate the current Ibl, and (W/L)p2= (W/L)p1 because the transistor Mp2
should be sufficient enough to hold Ibl in (D1’). Since Mp3 needs to store the current
Ib2=lbll2 at the end of (D2’), (W/L)p3z(1/2) (W/L)p2. Thus, the transistor sizes are chosen

as

(W/L)p,k+1'-(l/2) (W/L)pk, k=2,3,..,m—1 (4.6)

In an m—bit CRG_MC circuit, the current references ka=2k'IILSB, k=1,2,..,m, are
stored in Mxk. As the sequence M2 shown in Figure 4.3(c), Ix, is the minimum current
stored in the copier with N 1. A typical value of (Vgs‘VT)min is 0.2V which keeps the tran-
sistor in the strong inversion region. Therefore, similar to (5.6), the transistor size for both

N1 and N2 are chosen with

(W/L)N1= (W/L)N2=Ix1/(0.02kn) (4.7)

At the end of k’s cycles, the PMOS transistor Mxk holds a current Ibias+21x,k-1’ while the
NMOS transistor MN] holds a current Ibias+Ix,k-l' If we ignore the channel modulation ef-
fect, the currents held in Mxk and Mm can be respectively expressed as (kp/2)(W/L)xk
(VDD-Vgp-VTP)2 and (kn/2)(W/L)N1(vgn-vSS-VT,,)2, where vgn (vgp), VT“ (VTp), kn (kp),
and (W/L)N1 [(W/L)xk] are the gate voltage, threshold voltage, transconductance, and as-

pect ratio of the transistor Mm (Mxk), respectively. Thus, the size (W/L)xk can be estimated

68

as follows

(“l/L)“ = kanpnONII-JNI [(Ibias+21x,k-1)/(Ibias+lx,k-l )] (4'8)

where kpn=knlkp and Vpn=[(Vgn'VSS'VTn)/(VDD'Vgp'VTp)]2' It is reasonable to assume
that the charges dumped into the storage capacitors of both NMOS and PMOS copiers are
the same if both copiers have the same gate voltage. The error current due to the charge in-
jection effect must be considered. The current variation can be expressed as
AI=gm*AV=gm*AQ/C, where AV is the voltage variation across the holding capacitor, gm
is the transconductance of the storage transistor, and AQ is additional charge dumped into
the holding capacitor [71]. Therefore, the total charge injection error current for both cur-
rent copiers with N1 and N2 is approximately 2gmN1*AQ/CN1, where CN1=CN2 and
gmN1=gmN2. If we make both gate voltages for both N M08 and PMOS copiers to be equal,
i.e., Vgn=Vgp=Vg and 2gmN1*AQ/CN1=gmx2*AQ/Cx2, or Cx2=(gmx2/2gmN1)CN1, then
the charge injection errors may be compensated and thus reducing the error currents. Since
the currents held in both copiers with N1 and N2 are copied to the PMOS copier with Mxk,

similar to the above derivation, the capacitance ka is set to
ka = (gmxk/ 28mN1)CN1 (49)

Since the dividing approach requires more cycles to obtain the current references
with the desired accuracy, the charge injection errors are generally higher than that with
multiplying approach. Our goal is to develop a CRG_DC which achieves about ll-bit res-
olution. Therefore, large capacitors are employed to alleviate the charge injection errors. A

typical capacitance is 1 pF.

69

4.1.4. Performance Analysis

Calibration Time: Based on the transfer function of the small-signal equivalent cir-
cuit of a current copier in Figure 4.4. The following estimation of calibration time and hold-
ing time can be applied for both CRG_DC and CRG_MC circuits. As the input current
decreases, the capacitance ng becomes very important because the gain for MOS increases
and the Miller effect may affect the whole system. The characteristic function can be ex-

pressed as

(1.32 + BS +11 = 0 (4.10)
where

1 1
a = [(ng+Cgs)Cd+ngCgs](;-+r—) (4.11)

S 0

 

C +C C C
B = cgd(i+gm)(1+_1-)+ M M 8‘ .. gdgma (4.12)
rds rs o 1‘er rsrds r

 

n = 1 +lgmgma (4.13)

rsrords rs

Since all three structures have the second order characteristic equation
82 + 2Ccons + 0),,2 =0 (4.14)

where the natural frequency (on: Jn/ 0t and the damping ratio §=B/( 2 Jan ). Considering
the second order characteristic equation in (4.14), the settling time can be estimated. If the
ratio C ranges between 0 and 1 and 8 is the steady state error, then the settling time tS can

be determined by

70

 

 

gs

J l

 

 

 

Figure 4.4 Small signal analysis of negative feedback current copier

7|

 

ts:

£0: 1n(e./1—§2) (4.15)

While C is larger than or equal to l, the settling time can be decided by the roots, a and b,
of the characteristic equation, where lal 2 lbl decides the dominant pole of the characteristic
equation with 0.01 % accuracy. The settling time can be approximated by

ts = ilne (4.16)
Therefore, the settling time can be found and the comparison for different structures can
be done.

Holding lime: Due to the leakage current, Ileak’ of the holding capacitor, the cur-
rents held in the capacitor decreases. The leakage current is determined by that of the re-
verse-biased diode of a CMOS switch, and the time-dependent drain current due to the
diode leakage can be expressed as [72]: Ids,leak(t)=1,ergm*Ileak/Cgs*t. For a minimum
CMOS switch, it consists of two transistors with the size of 3 urn/2 pm for 2 urn technol-
ogy. A typical value is Ileak=10 mA/m2 for each transistor [72]. Therefore, the current Ileak
=0.12 pA for the CMOS switch. If we define the holding time as the time required for the
holding capacitor to lose 0.01% of the generated current, then the holding time, th, for an

m—bit CRG circuit can be expressed as follows, where Cpm and gmp are the capacitance and

the transconductance of transistor in the m-th PMOS copier Pm, respectively

1,, = 10'4='=1bm *Cpm/(gmpflleak) (4.17)

Accuracy: In the m-bit CRG_DC, the generated current reference is held in N3, the

current variation due to the charge injection error can be expressed as
Albk = gmk AV z [2kn(W/L)N3Ibk]1’2 AV (4.18)

where gmk is the transconductance of N3 when the current Ibk is held. Therefore, the accu-

72

mulated error of the m-bit CRG_DC circuit is the sum of Albk’s, i.e.,
eacc(m)=AIbl+AIb2-I-..+Albm.

For the CRG_MC circuit, if we properly design the circuit so that Vgn=Vgp=Vg in
(4.8) and CN1=CN2, then the charge injection errors can be cancelled out because
AQN1=Aka. However, due to the process variation, there might have a mismatch between
Cm and Cm. Without loss of generality, let CN2=CN1+ACN1, the error current can be ex-
pressed as AI=gmn(AQ/CN1)+gmn[AQ/(CN1+ACN1)]‘gmxk(AQ/ka) = gmn(AQ/
CN1)(ACN1/CN1). Since the CMOS process can control ACNIICNI to be below 0.1%, the

error current may be of insignificance.

4.2 Design Examples
Based on the developed design methodology and performance analysis, a 6-bit

CRG_DC circuit and a 7-bit CRG_MC circuit are demonstrated.

4.2.1 A 6-bit CRG_DC Circuit

Figure 4.5(a) shows a 6-bit CRG_DC circuit which is comprised of 3 NMOS cur-
rent copiers with N1, N2, and N 3, one current source with IFS/2 realized by a PMOS with a
bias voltage Vb3, and 6 PMOS current copiers with Mpk, k=2,3,.., 6. Consider the full scale
current IFS=1 146.88 uA, i.e., IMSB=IFSI2=573.44 11A. The 6-bit CRG_DC circuit generates
4 current references Ib1=573-44 uA, Ib2=286.72 [1A, Ib3=143.36 11A, Ib4=71.68 11A,
Ib5=35.84 11A, and Ib6=l7.92 11A. Note that kn=48.92 uA/V2 and kp=19. l6 ttA/V2 are con-
sidered in this design. By (4.4), the theoretically maximum values of (W/L)N1=Ib1/

(0.98kn’)=11.96, (W/L)N2 =(W/L)N3=5.98. In this implementation, the transistors are cho-

73

 

Kiwi/iii iii/iv
1”}ch 1 £{>_

iii)? ii? iii

 

 

 

 

 

 

iii?“ ii: ii
iii? ii? iii WW

 

 

 

Figure 4.5 6-bit CRG_DC circuits: (a) structure #1 and (b) structure #2.

sen as their sizes shown in Figure Table 4.1. In order to alleviate the charge injection errors,
the capacitances are chosen as listed in Table 4.1 for achieving the accuracy better than 11
bits, i.e., the accumulated error currents must not exceed the limit (1 146.88*2'l 1), i.e., 0.56
uA.

The 6-bit CRG_DC in this implementation takes 2 cycles for each iteration [71],
and thus, by (4.2), the total number of cycles required for generating the 6 current referenc-
es is KDC=31. The cycle time is determined by the time required for generating Ib6- The set-
tling time for Ib6=17.92 11A is estimated as follows: (1),,2=3.7342"‘1017 and
2Ccon=1.3107*1017. By (3.29), the settling time ts=1.45 us. This implies that the calibration
time of the 6-bit CRG_DC circuit is 1.45 us*31= 44.95 [.15. By (5.10), the holding time of
the 6—bit CRG circuit is th=403 us, where Leak: 0.12 pA for the CMOS switch, lb6=17-92
uA, gmpg=37 uA/V, and Cp6=1 pF.

For sake of comparison, Table 4.2 lists the performance analysis for the CRG_DC
circuit with 2 to 6 bits, including gm, settling time, error current, and accumulated error cur-
rents. For example, a 4-bit CRG_DC circuit uses only 4 bits of the 6-bit CRG_DC circuit
in Figure 4.5(a) and the corresponding parameters. For the accumulated error, by (4.8), the
current deviation is AIb2= 0.23 uA for Ib2=286.72 uA, where the transconductance
gm2=574.26 uA/V. Note that the voltage deviation due to the charge injection error is as-
sumed to be AV=0.4 mV. (In practice, the deviation AV is not always constant). Similarly,
the error currents are calculated and listed in Table 4.1, where the accumulated error of the
6-bit CRG is 0.452 uA which is much smaller than 0.56 uA for 1 1-bit resolution. This con-
cludes that, for a given full scale current IFS=1 146.88 uA, the 6-bit CRG circuit takes 44.95

us to generate 6 current references with an accuracy better than ll-bits, where a supply

75

Table 4.1 Parameter Values for CRG_DC in Figure 4.5(a).

 

 

 

 

 

 

 

TfflflSiStOl’ M p1 Mp2 Mp3 Mp4 Mp5 MP6 Capac Cm,” CP4-P6
size itance
WA. 0"“) 120/4 120/4 65/4 32/4 16/4 8/4 (pF) 1 . 14 1 .0
Transistor Mm Mm MN; Capac Cm.
size itance N3
“”1- ( m) ( F)
11 42/4 29/4 28/4 p l .2

 

 

 

 

 

 

 

 

 

 

Table 4.2 Perfomance Analysis for Vag'gus Bit Sizes of QRQ IX;-

 

 

 

 

 

 

 

 

 

 

 

g settling error :3;
characteristic equation m time current
(uA/V) (118) (M) current
(11A)
1.,2 s2+3.3979*103s+2.8414*1017=0 574.26 0.055 0.230f 0.230
Ib3 824.1 _4501 :1: 1088+23142$1017=0 298.86 0.127 0.119 0.349
Ib4 82+5.2398*107S+l.6209*1017=0 148.27 0.352 0.059 0.408
lbs s2+1.9837*107s+6.7551*1016=0 74-1 0-928 0-029 0-437
Ib6 32+].3107*107s+3.7343*1016=0 37-0 1-450 0-015 0452

 

 

 

76

 

 

voltage of 3.3 V and 2 pm CMOS process are employed. The resultant currents can be held
for 403115 before they need to be refreshed.

The calibration time of the CRG_DC may be improved by using smaller holding ca-
pacitances and transistors. More specifically, the decrease of calibration time can be accom-
plished by using the smaller holding capacitances at the cost of increasing the error current.
However, one may use a smaller N MOS transistor to bring the error current down. Figure
4.5(b) presents an alternative structure of a cascode 6-bit CRG_DC circuit and Table 4.3
lists the parameter values, where the parameter values of the first 4 bits are exactly the same
as those in Figure 4.5(a), and three additional NMOS copiers with N A, N3, and NC are em-
ployed. Note that the additional copiers function exactly the same as the copiers with N1,
N2, and N3. The PMOS copiers with P5 and P6 are used to generate and store the 5-th and
6-th current references. The parameter values for NMOS copiers with N A, N3, and NC are
selected for holding the maximum current Ib5=Ibll 16 to speed-up the settling times for lbs
and Ib6- Similarly, Table 4.4 lists the calculated gm, settling time, error current, and accu-
mulated error current for both 5-th and 6-th bits. Results show that the 6-bit CRG_DC cir-
cuit takes 0.977 113*3 1:30.29 its to generate 6 current references with an accumulated error
current of 0.472 11A which is better than ll-bit accuracy, and its holding time is 268 us.

Comparing both 6-bit CRG circuits in Figures 4.5(a) and 4.5(b), the latter circuit
improves the calibration time from 44.95 us to 30.29 us, i.e., 1.48 speed-up ratio, but the
holding time drops from 403 us to 268 us and the accumulated error current increases from

0.452 11A to 0.472 uA. In addition, 3 extra NMOS copiers are needed in the latter circuit.

77

Table 4.3 Parameter Values far CRG DC in Figm 4.5(b),

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transistor Mp1 Mp2 Mp3 Mp4 Mp5 MP6 Capac sz_ Cp4_
size itance P3 P6
W/L
(um) 120/4 120/4 65/4 32/4 32/4 18/4 (pF) 1.14 1.0
Transistor MN, Mm MN; MNA MNB MNC Capac Cm- CNA-
size itance N3 NC
W/L
(“I") 42/4 29/4 28/4 10/5 16/10 15/10 (pp) 1.2 0.6
Table 4.4 Egfi'gmaaice Analysis f9; Vag'gus Bit Sizes at cm DC
gm settling error :2}
characteristic equation (uA/V) tans: c213? current
(11A)
lbs s2+2.5278*107s+1.1453*10”=0 104-85 0728 0-042 0-450
Ib6 52-1-1.8843*107s+2.5387*1017=0 55.6 0.977 0.025 0.472

 

 

 

 

 

 

78

 

4.2.2 7-bit CRG_MC Circuit

Consider the 7-bit CRG_MC in Figure 4.3(c). With ILSB=0.56 uA, the 7-bit
CRG_MC circuit generates Ix1=0.56 uA, Ix2=1. 12 uA, Ix3=2.24 ilA, Ix4=4.48 11A, Ix5=8.96
11A, Ix6=l7.92 uA, and Ix7=35.84 iiA. Theoretically, by (4.7), the minimum size of the tran-
sistor N1 must be exceed 0.56 uA/(0.02kn)=0.572. Here, we chose (W/L)N1=(W/L)N2=5
um/7 um. Table 4.5 lists the parameter values. The holding time is determined by the copier

with Mpland it is approximately 509 us.

4.2.3 Simulation Results
Figure 4.6(a) shows the simulation results of the 6-bit CRG_DC circuit in Figure
4.5(b), where the parameter values in Table 4.3 are used, and 3.3 V supply voltage and M0-
SIS SCN20 2 um CMOS process with 2—level transistor parameters are simulated. Results
show that the circuit takes 31 cycles with a clock rate of 1 us, i.e., its calibration is 31 us.
Figure 4.6(b) shows the simulation results of the 7-bit CRG_MC circuit in Figure
4.3(c) with the parameter values in Table 5.5. The circuit takes 18 cycles to generate the 7

current references, where the clock rate is also set to 1 us, i.e., its calibration time is 18 its.

43 DAC Circuit Design

This section presents high-speed DAC circuits for low-power applications. As
shown in Figure 4.7, the developed (0t+B)-bit DAC circuit, i.e., MaDB DAC circuit, is
comprised of a 01-bit CRG_MC to generate Jk’s, k=1,2,..,m, from the LSB, and a B-bit
CRG_DC to generate Ik’s, k=1,2,..,B, from the MSB. Based on the design and simulation
results of the 6-bit CRG_DC and 7-bit CRG_MC circuits presented in the previous section,

we may construct the following hybrid 11-bit DAC circuits: M7D4, M6D5, and M5D6.

79

Table 45 WW

 

 

 

 

 

Transistor size Mxl MX2 Mx3 Mx4 st Mm Mx7 MN MN Mm
W/L (um) 1 2
5/16 9/11 8/4 7/3 10/3 11/3 18/3 5/7 5/7 6/5
Capacitance sz Cx3 Cx4 st CX6 Cx7 Cm CNZ
(PF) 0.69 0.72 0.85 1.1 1.1 2 0.35

 

 

 

 

 

 

 

 

 

 

 

80

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 4us 8us 12us 16us 20us 24us 28us

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

e
A ‘1 J— A L

 

 

 

 

 

 

 

 

ol

 

 

(b)
Figure 4.6 Simulation results: (a) 6-bit CRG_DC Circuit;
and 7-bit CRG_MC Circuit.

81

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ot-bit CRG_MC
3 Load
:9: Control
Data ff Logic
Input g Gate Iout
Q

 

 

 

 

 

 

 

 

B-bit CRG_DC

 

Figure 4.7 Proposed DAC circuit structure

82

4.3.1 Low Power SI DAC Design

In an N-bit CRG_DC circuit, its LSB current, ILSB=IF3/2N, cannot be lower than its
signal-to-noise ratio (SNR). This implies that its bit size is limited by the given full-scale
current IFS. It also implies that, for a given SNR of an N -bit CRG_DC circuit, the only way
to increase the bit size is the use of larger IFS, but it will be penalized by the increase of
power consumption. This concludes that the bit size of both CRG_DC and CRG_MC cir-
cuits cannot be arbitrarily large for low-power applications. To increase the resolution of a
SI CMOS DAC circuit for low-power application, the block diagram of a high-speed SI
DAC circuit, as shown in Figure 5.8, is developed in this study. The developed (oc+B)-bit
DAC employs a 01-bit CRG_MC to generate Jk’s, k=1,2,.,a, from the LSB, and a B-bit
CRG_DC to generate Ik’s, k=1,2,..,B, from the MSB. For simplicity, the DAC is referred
to as a MOLDB DAC circuit. For example, a M7D4 DAC circuit is a hybrid ll-bit DAC cir-
cuit with a 7-bit CRG_MC and a 4-bit CRG_DC. It should be mentioned that an alternative
high-resolution hybrid current-mode DAC was reported in [40], but it employs well-

matched components similar to Figure 2.5(b) to generate the current references.

4.3.2 Design Example -- an ll-bit DAC Circuit

Consider the 7-bit CRG_MC circuit in Figure 4.3(c) and the 4-bit CRG_DC circuit
in Figure 4.5(a). (Note that the simulation results for the 4-bit CRG_DC in Figure 4.5(b)
should be the same as those in Figure 4.5(a).) Results in Figure 4.6(b) show that the cali-
bration time of the 7-bit CRG_MC circuit is 18115 and the holding time is 509 us. For the
4-bit CRG_DC circuit, the first 19 cycles in Figure 4.6(a) shows that the calibration time is

191.13 and the holding time is 402 us. This concludes that the M7D4 DAC circuit takes 19us

83

to generate the 11 current references which can be used for 402 its before refreshing. The
power consumption is approximately 4.4 mW, including 3.8 mW for loading the current
references and 0.6 mW for the op-arnp.

Figures 4.8(a) and 4.8(b) plots the integral nonlinearity (INL) and the differential
nonlinearity (DNL) of the hybrid M7D4 DAC circuit, while Figure 4.8(c) shows the floor
noise spectrum of the 1024-FFT. The output is the fill scale swing sinusoidal wave with 25
kHz. The difference between the signal to the floor noise is approximately 73 dB. Simula-
tion results show that the M7D4 DAC circuit has ll-bit resolution, 100 MSample per sec-
ond for conversion rate, and the power consumption is approximately 4.4 mW with 3.3 V
power supply voltage and MOSIS SCN20 2 pm CMOS process with 2-level transistor pa-

1' 311161613 .

4.3.3 Alternative Designs

Consider the design of a hybrid M5D6 DAC circuit, where the 6-bit CRG_DC cir-
cuit in Figure 4.5(b) and the 5-bit of the CRG_MC in Figure 4.3(c) are employed. As shown
in Figure 4.6(a), the calibration time of the 6-bit CRG_DC circuit is 31 us and the holding
time is 268 [.13. On the other hand, as shown in Figure 4.6(b), the calibration of the 5-bit
CRG_MC is 12 us and the holding time is 509 us. This concludes that the M5D6 DAC cir-
cuit takes 31 its to generate the 11 references and needs to be refreshed at 268 us. Similarly,
Figures 4.9(a) and 4.9(b) plots the INL and DNL of the hybrid M5D6 DAC circuit. Both
M5D6 and M7D4 DAC circuits have the same SNR of 62 dB which is a 11-bit resolution.

It should be mentioned that the CRG_DC circuit generates its current references

from IMSB’ while the CRG_MC circuit does it from ILSB. Therefore, the accumulated error

84

 

 

 

 

 

Figure 4.8 Nonlinearity analysis of M7D4 DAC: (a) INL; (b) DNL;
and (c) Noise Floor.

85

 

 

Figure 4.8 (cont’d)

 

 

 

 

 

(b)

Figure 4.9 Nonlinearity analysis of M5D6 DAC: (a) INL; and (b) DNL.

87

currents resulted from the CRG_DC circuit are generally smaller than those from the
CRG_MC circuit. This can be seen from both INL and DNL plots in Figures 4.8 and 4.9,
i.e., the M5D6 DAC circuit has better nonlinearities than the M7D4 DAC circuit, but both
achieve a 11—bit resolution. Since the M7D4 DAC circuit is better than M5D6 circuit in the
calibration time of 19 us vs. 31 us and the holding time 402 its vs. 268 us, as far as the
speed performance and low-power are concerned, the hybrid M7D4 DAC circuit is recom-

mended.

4.4 Conclusion

This chapter presents a high performance SI CMOS DAC circuit for low—power
applications, where the DAC circuit achieves 11-bit resolution, 100 MSample per second
for conversion rate, and the power consumption is approximately 4.4 mW with 3.3 V
power supply voltage and MOSIS SCN20 2 mm CMOS process with 2-leve1 transistor
parameters. The 11-bit DAC circuit is comprised of a 7—bit CRG_MC circuit and a 4-bit
CRG_DC circuit. The DAC takes 19 its to generate the 11 current references for data con-
version, and the generated currents can be held for 402 us before refreshing.

For the hybrid ll-bit DAC circuits, three different structures may be constructed,
i.e., M7D4, M6D5, and M5D6. For high speed performance, the M7D4 DAC circuit is
recommended. The next logical question is whether it is feasible for developing the high
speed hybrid DAC circuit with higher bit size for low power applications. The cascode
structure for CRG_DC presented in Figure 4.5(b) can be potentially extended for higher
bit size. For low-power applications, however, there exist some design trade-offs among

accuracy and speed performance. This leads to a very important research topic that devel-

88

ops a synthesis process for generating high speed hybrid DAC circuits for low power

applications.

89

Chapter 5

BUILT-IN TESTERS FOR SI CIRCUITS

Built-in self-test (BIST) has been accepted as a tool for digital verification and pro-
duction test. A tester is built inside the circuit to monitor the circuit performance. Thus,
the tester will reduce the tester complexity, eliminate the need for off-chip interfacing, and
allow the device to be tested many times during the manufacturing cycle of the product.
The BIST approach has also been introduced for analog circuits [73]. However, the BIST
approach may require additional hardware and degrade performance of the designed cir-
cuits. Section 5.1 reviews the structure of a built-in tester for SI circuits developed in [48].
The built-in tester is comprised of a high-accuracy CMOS current comparator, a voltage
window comparator, and a latch [7 3-75]. Section 5.2 introduces a high performance cur-
rent comparator which is capable of autozeroing and self-testability. Finally, Section 5 .3

gives a concluding remark.

5.1 Built-in Testers

In order to enhance the reliability of SI circuits, a built-in tester was introduced in
[48-50]. Consider the ADC circuit in Figure 2.4(a) with its output stage shown in Figure
5.1(a), and its simplified version in Figure 5.1(b), where the circuit is comprised of 3

current copiers. The current copier has an S/H function and can be implemented as an

90

 

 

 

 

 

 

l-i—l V01]!
37
1m P1 w D Q ‘Ijj >vo
Sl { S6 TX
L 8 l x + plifi » I
l s _
S8 S2 4 :
iii 7C2

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5 1 Tester: (a)Proposed test SI circuit; (b) Simplified of proposed test

91

 

 

11th

3??

ClIC

DUE

1101

 

cirt

se\

CU

in

analog scan structure for fault diagnosis and testing [73,76]. Test generation [47] and BIST
design [61] of such a converter have been developed for single stuck-at fault models.
Furthermore, the test generation of the ADC circuits for both stuck-at and parametiic fault
models were reported in [49] which shows that the N-bit resolution ADC circuit takes
approximately 24N clock cycles to detect all switching element faults [50]. The ADC
circuit can achieve 11-bit resolution and thus requires 264 cycles to detect the faults. The
number of clock cycles for detecting the faults can be reduced significantly if a high-

accuracy built-in tester can be used [50].

Figure 5.2(a) illustrates a typical SI circuit with a built-in tester which is currently
not available in its counterpart SC circuits. Figures 5.2(b) shows an example of the ADC
circuit in Figure 5.1(b) with the tester. With the self-testing capability, the tester can be first
self-tested. The fault-free tester is then used to test each component in SI circuits, such as
current copiers, current sources, amplifiers, etc. Finally, the tester will verify the

interconnections. Here, both catastrophic and parametric faults are included.

Consider the block diagram of a built-in tester in Figure 5.3(a) [48]. The current
comparator checks if the difference of two input currents In and In is sufficiently small. A
corresponding voltage level Vy with respect to the current difference Ix=Ii1-Ii2 is generated.
Thus, the current comparator is effectively a current-to-voltage (I-V) converter. The
generated voltage level is then applied to a regenerative latch to determine the digital

output.

If the comparator is designed in such a way that a corresponding voltage level Vy,
-VWSVySVw, is generated for any input Ix, 101ng Ito}, then a simple voltage window

comparator with a pair of symmetric the threshold voltages, VW and -Vw, can be used. An

92

Built-In
Tester

 

    

SI Circuits

 

 

 

(a)

 

  

m

 

 

>-

Opamp

161'

C0-

 

3?
i

 

(b)

Figure 5.2 SI tester: (a) SI circuit with tester; (b) SI AID converter

93

Window
Comparator

 

 

Current

 

 

Ii2
Comparator

 

 

 

 

 

  

 

 

 

 

 

 

 

Ix \ {— Vw
X Current Voutwo)
'— Comparato D Q
:>—____II CLK
= Y

Vss

(b)

Figure 5.3 Schematic and configuration of built-in tester: (a) schematic; (b) configuration

94

 

ideal current comparator has a linear relationship between 1x and V), as
Vy = 1,, I]; (5.1)
where rk is a constant transresistance.

Figure 5.3(b) shows the schematic diagram of the built-in tester which is applied to
the AID converter in Figure 5.1(a), where nodes X and Y are the same locations as those in
Figure 5.1(b). Two multiplexers X1 and X2 are used in the voltage window comparator
(W CP). During the normal operation, X1 and X2 are switched to Ground and Vss,
respectively. The output of WCP is set to “1” if Vy > 0, and to “0” otherwise. They are set

to Vw and -VW during the test mode.

The threshold voltage VW is determined by the predetermined tolerable current Ito]
[48]. It should be noted that an ideal current comparator may have a’ linear relationship
between I1‘ and Vy, as shown in (5.1). However, the voltage Vy may deviate because of the
offset current due to mismatched components in the current comparator and the
nonlinearity of rk. The offset current may cause an offset voltage, Vofs, in the output of the
current comparator, while the nonlinearity of rk leads to a nonlinearity quality an(Ix) which

is a function of Ix. Thus, Vy in (5.1) can be re-written as

Vy = IX 1" + Vofs + anax) (5.2)

Hence, the accuracy can be improved by reducing the terms Vofs and an(Ix). Let Vymm)
and Vy(min) be the maximum and minimum values of Vy in (5.2) due to the above
deviations. Since designing a window comparator with symmetric threshold voltages, i.e.,
V1=-V2, seems to be easier than with non-symmetric ones, we choose V1=-V2=Vw.

However, the window comparator may produce incorrect comparison results in the ranges

95

[szvy(max)] and ['szvy(min)]° This becomes an important issue for the quality of the

tester.

The quality of the tester is determined by its testing confidence with respect to the
selected tolerant current Ix, where the testing confidence of a tester is defined as the
probability that the comparison results are reliably determined. Based on the test
confidence discussed in [48], Figure 5.4 plots the relationship between the testing
confidence and the testing resolution. The testing resolution is defined as the number of bits
that represent the ratio Iml/Imax, where Imax is the maximum different current applied to the

tester, i.e., Imax=lx(max). Mathematically, the number of bits, b, is
b =[ Iogzamax/lefl (5.3)

For example, suppose that Imax=100 HA and Itol=40 nA; by (5.3), the testing resolution is
b=l2 bits. Similarly for Imax=100 11A and 1101:20 nA, the testing resolution is 13 bits.
Therefore, given a tolerance current 1.01, the threshold voltage VW of the window

comparator is chosen as

vW = 1,0er = (Imam/(2b) (5.4)

Since the converter circuit implements a multiply-by-two circuit that doubles the

residual current at each cycle of conversion, the tolerant current is also doubled. More
specifically, at the first bit conversion, the tolerant current is (1/2)ILSB; It01=lILSB for the
second bit conversion; and ItolzzMJILSB at the M-th bit conversion. Suppose a tester with
b-bit resolution is used, we have

1,0,:21‘4'11L_.,B=2'I’Imax (5.5)

where Imax=lref=2NILSB for an N-bit A/D converter. This implies that b=(N+l)-M. For the

96

g

Testing confidence (16)
8

K1

 

 

 

 

 

1 3.5

Figure 5.4 Test confidence vs. resolution

97

ADC circuit in Figure 5.1(a), the comparator requires Itol=(1/2)Iref, i.e., M=N, or b=l, i.e.,
this implies that the comparator used in the converter is equivalent to a tester with a testing

resolution b=1.

By (5.5), if we use the developed tester with 12-bit resolution, i.e., with a threshold
voltage Vw= l 30 mV, for the ADC circuit in Figure 5.1(a), any faults can be detected during
the conversion with a testing confidence of 99.5% and no test sequence is needed. On the
other hand, if we use a tester with ll-bit resolution, with Vw=260 mV, for the ADC circuit,
any faults can be detected with a testing confidence of 99.9% and 24 test cycles are needed.
Similarly, for 10-bit resolution tester with Vw=521 mV, it has almost 100% testing
confidence and takes 48 test cycles. This example concludes that the number of test cycles

decreases as the accuracy of the tester increases.

5.2. CMOS Current Comparator

One of the most critical parameters which limit current comparator performance is
the offset voltage of the comparators [16]. This study develops a high accuracy CMOS
current comparator which is capable of autozeroing and self-testability. The autozeroing
property is to reduce the offset voltage and to increase the accuracy of the tester, while the

self-testability is to enhance the reliability of the tester.

5.2.1. Autozeroing

Figure 5.5(a) shows an autozeroed current comparator which is operated in two

phases: autozeroing phase and comparing phase. During the autozeroing phase, the circuit

98

 

 

Window
Comparator

 

 

 

 

 

F D

(C)

Figure 5.5. Autozeroed current comparator: (a) schematic;
(b) autozeroing phase; and (c) comparing phase.

99

is reconfigurated as shown in Figure 5.5(b), where switches S,“ and 8x2 are ON. As a result,
the offset voltage of the comparator is memorized by the capacitor C A, and the voltage at
node X is memorized in the capacitor CH. During the comparing phase, the comparator is
reconfigured as shown in Figure 5.5(c), where both le and 8x2 are OFF. The capacitor C A

is connected in such a manner as to cancel the offset voltage.

The current comparator in Figure 5.5(a) has been designed and simulated by pspice,
where the SCNA20 2pm CMOS process with level-2 transistor parameters are assumed.
The switches are realized by CMOS transistors with dummy switches to alleviate the
charge-injection error effects. Figure 5.6(a) shows the simulation results of the autozeroed
comparator. The first stage is the autozeroing, the second stage is with an input current, or
the current difference, of -50nA, while the third stage is with 50nA. From the transfer
function of the comparator, as shown in Figure 5.6(b), one can determine the threshold
voltages needed for the window comparator. Simulation results show that, for an input
current IOOuA, the comparator can achieves a resolution of lnA. This is equivalent that the

comparator can reach a l6-bit resolution.

5.2.2 Self-Testability

The self-testability of the tester is verified through fault simulation. Consider the
ADC circuit in Figure 5.7, where the comparator and output latch circuit in Figure 5.1(a)
are replaced by the tester in Figure 5.5(a). In this fault simulation, only one fault is injected
at a time and the fault is assumed to be S/ON or S/OFF fault. The S/ON fault is simulated
by connecting two node of the switch, while the switch is removed for S/OFF fault. To

simplify the discussion, we only consider the equivalent circuit, as shown in Figure 5.8(a),

100

50nA

Output Voltage

<1)
.0
t:
o
5
TE
.Q
.e-I
:
o
1:
:3
U

5011A

 

 

 

comparators output voltage (V)

 

 

 

 

_2 i i i L L A J_ I i
—1 0 —8 —6 —4 —2 0 6 8 10
error current (nA)

Figure 5.6 Analysis of current comparator: (a) simulation result for comparator;
(b) transfer function of comparator

101

Output Voltage

4.)
o
It:
a)
33
E
O
H
r:
o
1:
:5
U

-5()nA

 

 

 

comparators output voltage (V)

 

 

 

I i 1 i_ l l 1 i i

1‘1 o —e —s —4 —2

 

0 2
error ounent (M)

(b)

Figure 5.6 Analysis of current comparator: (a) simulation result for comparator;
(b) transfer function of comparator

101

Vdd

51

_L

3
P1
S

7

S

 

 

 

 

1 1

38 S2
S
N‘ a”
IREF C1

V88

6
S4

8
”2 0”
7C2

 

V

if?”
>1...-

 

11
F Sx2
j
le
..CH

 

 

Figure 5.7 The configuration of circuit under testing

102

for fault simulation, where the current copiers with N 2 and P1 are switched away during the

simulation by turning off S4, SS, Sg, S7, and SS.

A test sequence is applied to detect the S/ON and S/OFF faults for both 8,, and 8,2.
The test sequence is comprised of three cycles. In the first cycle, as shown in Figure 5.8(b),
the current copier with N 1 is calibrated with Im=IREF and the comparator is in the
autozeroing phase. Switches S], S; and S3 in the copier are ON and switches 8,, and 8,2 in
the comparator are also ON. Since the comparator is performing autozeroing, the output of
the comparator is zero. In the second cycle, as shown in Figure 5.8(c), switch S3 in the
copier and S,“ and 8,2 in the comparator are all OFF. The offset voltage of the op-amp is
stored in C A and V’comp =V+comp. Thus, the output of the comparator is also zero. This
concludes that, for fault-free tester, the output voltages of the comparator are all zeros with

these two cycles.

Consider the S/OFF fault on 8x2. In the first cycle, the comparator fails to perform
autozeroing. Since the comparator has a differential gain about 80 dB, the difference
(V+comp-Vcomp) forces the output of comparator to become very close to Vdd, as shown in
Figure 5.9. The same output voltage is carried into the second cycle. Thus, the fault can be
detected. For the S/OFF fault on le , since the comparator performs autozeroing in the first
cycle, the output voltage of the comparator is zero and thus the fault cannot be distin-
guished in the first cycle. However, in the second cycle, Vcomp =VX+VCA, and the fault
causes a negative V+comp. As a result, a negative output is obtained, and a “1” is detected
from the window comparator which distinguishes the faulty circuit from the fault-free one.

When a S/ON fault occurs at S“, the comparator performs autozeroing in the first

cycle regardless of the fault. In the second cycle, the fault causes V+comp =VX=V‘comp and

104

 

8x2 stuck—at-off fault {W fault free

le and 8x2 sluck-at-on fault

 

 

le $ch

 

us

Figure 5.9 Fault simulation results

105

thus the output of the comparator is zero. In other words, the first two cycles of the test se-
quence cannot detect such a fault. In order to detect such a fault, the third cycle is applied
with the same setting as in Figure 5.8(c), except that IIN=IREF/2- For the fault-free circuit,
the capacitor CH memorizes the voltage Vx when IIN=IREF. Now, when the input current
decreases, the voltage Vx also decreases. As a result, Vcomp < V"comp and a negative output
in the comparator is obtained, or a 1 is expected. However, in the presence of such a fault,
V"comp =V'comp and a zero output is resulted. Therefore, the fault can be detected. Similar-
ly, for a S/ON fault on 8x2, a 1 is expected for the fault-free circuit. With such a fault, the
circuit is equivalent to performing the autozeroing for the third cycle, i.e., a zero output is
resulted. Thus, the fault can be detected.

In these fault simulations, the on-resistance and off-resistance of the switches are
assumed to be 5.7 k!) and 1.2 GD, respectively. The parametric faults in switch assume
that both on-resistance and off-resistance are moved away from the defined values. Simu-
lation results show that both catastrophic and parametric faults for the components in the

tester can be detected. Thus, the tester circuit is fully testable.

5.3 Conclusion

This chapter presents the design and operation of built-in tester for high
performance and low power CMOS switched-current circuits. The tester is comprised of a
high accuracy current comparator, a voltage window comparator, and a digital latch. In this
study, a simple, yet high accurate current comparator which is capable of autozeroing and
self-testing is developed. The autozeroing property increases the accuracy of the tester.

Simulation results show that the comparator can achieve a resolution of 1 nA which is

106

equivalent to a l6-bit resolution. This chapter also demonstrates the self-testability of the
tester through a fault simulation. Since the current comparator possesses self-testing
capability, the fault-free comparator can test all components in the SI circuit and thus
simplifying the testing process. This study has evidently shown that the use of tester in SI
circuit has made more attraction of using SI technique for the analog portion of the mixed-

signal circuit design.

107

Chapter 6

CONCLUSION

The advent of portable communication and computing service has stirred a great
deal of interests in both commercial and research areas. The circuit technology used in
portable equipment has been changed from the conventional analog circuit technology to
mixed-signal circuit technology. Low power and high performance are strongly needed for
both analog and digital circuits to increase operation time of the portable equipment. The
design of low power and high performance mixed-signal CMOS IC’s is hindered by pro—
cessing techniques that are optimized for digital applications. Moreover, Scaling/reliability
consideration are driving CMOS process towards submicrometer feature size and lower
power supply voltages.

SI technique has received considerable attention as an alternative for analog data
acquisition and conversion circuit design. However, existing SI circuits cannot make the
theoretically expected performance due in part to the use of non-optimal current copiers,
its basic building blocks. Based on our development of design methodologies and synthe-
sis process for optimally generating low power and high performance CMOS current copi-
ers [18,63], SI technique becomes feasible.

With the successful development in this thesis study, we believe that SI technique
will soon become an alternative industrial standard for designing analog components in

mixed-signal circuits for low-voltage/low-power signal processing applications.

108

6.1 Summary and Contribution

Chapter 1 introduces the advantages of using SI technique for designing analog
portion of mixed-signal ICs. The objective of the thesis study is to develop high perfor-
mance and low power data converters, ADC and DAC circuits. Chapter 2 reviews existing
current copiers, current-mode multiplier and divider circuits, ADCs and DACs, and test
generation for SI circuits.

Chapter 3 presents a high performance and low power CMOS cyclic ADC circuit.

The ADC circuit has been designed, simulated, and fabricated. The designed ADC circuits

takes 2.13 mm2 in chip area, achieves a resolution of l2-bits, and consumes only 1.9 mW
in power. High performance is attributed to the use of the following components: (1) a
high performance residual amplifier which takes two clock cycles to double a current; and
(2) an efficient cyclic RSD algorithm which provides 1.5b resolution without using two
matched reference currents.

Based on efficient current-mode divider and multiplier circuits, Chapter 4 develops
the design methodologies and performance analysis process for current reference current
generator (CRG) circuits which generates the weighted reference currents for DAC cir-
cuits. The developed design methodologies guide the designers to properly select the tran-
sistor sizes and capacitances based on a given set of design specifications including input
dynamic range, full-scale current, SNR, power consumption, etc., and the performance
analysis process estimates the calibration time, holding time, and accuracy of the CRG cir-
cuits. For low power applications, a hybrid (a+B)-bit DAC circuit design is introduced,
where a a-bit CRG_MC circuit and a B-bit CRG_DC circuit are employed. This chapter

demonstrates the detailed design of a DAC circuit which achieves 11-bit resolution, 100

109

 

MSample per second for conversion rate, and the power consumption is approximately 4.4
mW with 3.3 V power supply voltage and MOSIS SCN20 2 pm CMOS process with 2-
level transistor parameters. The 11—bit DAC circuit is comprised of a 7-bit CRG_MC cir-
cuit and a 4-bit CRG_DC circuit. The DAC takes 31 its to generate the 11 current refer-
ences for data conversion, and the generated currents can be held for 402 us before
refreshing. The trade-offs among the different structures are discussed such as M7D4,
M6D5, and M5D6. The designer can choose the most feasible structure to reach the speci-
fication of the product and speed up the design period.

In order to enhance the testability of SI circuits, Chapter 7 presents a built-in tester
design. A high performance current comparator was developed. The comparator possesses
the features of autozeroing and self-testability. The autozeroing property reduces the offset
voltage of the comparator and thus increasing the accuracy of the comparator, while the
self-testability of the comparator enhances the self-testability of the tester.

The major contributions in this thesis study can be categorized as follows:

(a) Developing high performance and low power SI CM OS cyclic ADC circuit

(b) Developing design methodologies and performance analysis process for high per-
formance and low power SI CM OS hybrid DAC circuits.

(c) Developing a built-in tester for high performance and low power SI circuits.

The simulation results and measures of the fabricated ADC chip demonstrate the
feasibility of the SI technique. The considerably low power consumption will soon make
the SI technique to become an alternative industrial standard for designing analog compo-
nents in mixed-signal circuits. In addition, the salient feature of the self-testability of the

built-in tester makes the SI circuits to be easily testable.

110

 

6.2 Future Work

Based on design trends that the complexity of analog/mixed-signal ICs will contin-
uous to increase. Portable systems will become more and more popular as the size contin-
ues to shrink. Thus, further decreasing the power consumption to prolong the life of
portable systems becomes more and more important. Also, enhancing the testability
becomes necessary for quality improvement.

The quality of the developed data converter circuits can be further improved by
using better process technologies and low supply voltages. In this study, the MOSIS 211m
digital CMOS process and 3.3 V supply voltage were assumed. The power consumption
can be further reduced with the decrease of supply voltage. However, there exist design
trade-offs between power reduction and speed performance. Therefore, it is worthwhile to
examine the performance degradation of the developed data converters due to the decrease
of supply voltages such as 2.5V or 1.5V, and to develop design methodologies for data
converter to improve the performance while keeping low power consumption.

One solution to increase the conversion speed of the developed ADC circuit is the
use of pipeline structures. The developed ADC circuits can be easily modified as pipeline
structures. It is believed that the pipeline structure can achieve the same resolution and its
data conversion rate can reach to 8 MSamples per second. However, the offset current for
each stage must be carefully managed to keep the same accuracy.

The developed hybrid DAC circuits whose weighted currents are generated by
both CRG_DC and CRG_MC circuits. The accuracy of both CRG circuits does not
require well-matched components. However, due to the leakage currents, the generated

current references need to be refreshed. Note that the data conversion will not be available

111

 

when the CRG circuits are being refreshed. Therefore, the DAC circuits will be perfectly
applied to some applications which allow the DAC circuits have a period of idle time.
Finally, the developed built-in tester can significantly simplify the testing process
of SI circuits. It is believed that the autozeroing scheme for current comparator can be
modified for voltage comparators. Thus, the same concept of the tester design should be to
apply for switched-capacitor circuits. This leads to a very interesting and important

research topic for future study.

112

References

113

References

A. Mastsuzawa, "Low-Voltage and Low-Power Circuit Design for Mixed
Analog/Digital Systems in Portable Equipment," IEEE Journal of Solid-State
Circuits, vol. 29, no. 4, pp. 470-480, April 1994.

C. L. Wey, "Mixed-Signal Testing -- a Review," (invited) Proc. of IEEE Inter-
national Conference on Electronics, Circuits, and Systems, Rodos, Greece,
pp. 1064-1067, 1996.

C. L. Wey, "Mixed-Signal Fault Models and Design for Test", (Tutorial
Course) Proc. of IEEE Asian Test Symposium, Hsinchu, Taiwan, 1996.

R. Castello, F. Montecchi, F. Rezzi, and A. Baschirotto, "Low-voltage Ana-
log Filters," IEEE Trans. on Circuits and Systems, Part I: Fundamental The-
ory and Applications, vol. 42, no. 11, pp. 827-840, November 1995.

C. Toumazou, F. J. Lidgey, and D. G. Haigh, Analogue IC design: the cur-
rent-mode approach, London, Peter Peregrinus Ltd., 1990.

C. Tomouzou, J. B. Hughes, and N. C. Battersby, Switched-Currents: an
Analogue Technique for Digital Technology, London, Peter Peregrinus Ltd.,
1993.

S. J. Daubert, D. Vallancourt, and Y. P. Tsivids, "Current Copier Cells," Elec-
tronics Letters, vol. 24, no. 25, pp. 1560-1562, December 1988.

D. G. Naim and C. A. T. Salama, "A Ratio-Independent Algorithmic Analog-
to digital Converter Combining Current Mode and Dynamic Techniques,"
IEEE Trans. on Circuits and Systems, vol. 37, no. 3, pp. 319-325, March
1990.

R. H. Zele and D. Allstot, "Low-voltage Fully-Differential CMOS Switched-
Current Filters," Proc. of IEEE Custom Integrated Circuits Conference, pp.
6.2.1-6.2.4, 1993.

114

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

D. Macq and P. G. A. Jaspers, "A lO-bit Pipelined Switched Current AID
Converter," IEEE Journal of Solid-State Circuits, vol. 29, no. 8, pp. 967-971,
August 1994.

L. Zhang, T. Sculley, and T. S. Fiez, "A 12 Bits, 2V Current-mode Pipelined
AID Converter Using a Digital CMOS Process," Proc. of IEEE International
Symposium on Circuits and Systems, vol. 5, pp. 369-372, London, England,
1994.

H. Hasegawa, M. Yotsuyanagi, and K. Sone, "A 1.5Video-Speed Current-
Mode Current-Tree AID Converter," Proc. of Symposiums on VLSI Circuits,
Honolulu, pp. 17-18, 1994.

R. Huang and C. L. Wey, "Simple Low-Voltage, High-speed, High-Linearity
V-I Converter with S/H for Analog Signal Processing Applicatiosn," IEEE
Trans. on Circuits and Systems. Part II. Analog and Digital Signal Process-
ing. vol. 43, no. 1, pp. 52-55, January 1996.

R. Huang and C. L. Wey, "Design of High-speed, High-accuracy Current
Copiers for Low-Voltage Analog Signal Processing Applications," IEEE
Trans. on Circuits and Sys., Part II. Analog and Signal Processing, vol. 43,
no. 12, pp. 836-839, December 1996.

R. Huang and C. L. Wey, "A High-Accuracy CMOS Oversampling Current
Sample/Hold (SIH) Circuit Using Feedforward Approach," IEEE Trans. on
Circuits and Systems. Part II. Analog and Digital Signal Processing. vol. 46,
no. 3, pp. 395-399, March 1998.

R. Huang and C. L. Wey, "A 5mW, 12-b, 50ns/b Switched-current Cyclic AI
D Converter," Proc. of IEEE International Symposium on Circuits and Sys-
tems, Atlanta, GA, pp. 207-210, 1996.

R. Huang, J. S. Wang, C. L. Wey, “A Fully Differential Switched-Current
ADC with Improved Performance,” Proc. of IEEE Midwest Symposium on
Circuits and Systems, Davis, CA, pp. 177-180, 1997.

R. Hunag, “Design of High-Performance CMOS Switched-Current Circuits,”
Ph.D. Dissertation, Department of Electrical Engineering, Michigan State
University, 1998.

S. H. Lewis and P. R. Gray, “A pipelined 5-Msamples/s 9 bit analog-to-digi-

115

 

20.

21.

22.

23.

24.

25.

26.

27.

28.

29.

tal converter,” IEEE Journal Solid-State Circuits, vol. 22, no. 12, pp. 954-
961, December 1987.

S. H. Lewis, et al., “10b 20 Msamples/s analog-to-digital converter,” IEEE
Journal Solid-State Circuits, vol. 27, no. 3, pp. 351-358, March 1992.

Y. M. Lin, B. Kim, and P. R. Gray, “A 13b 2.5MHz self-calibrated pipelined
AID converrter in 3-um CMOS,” IEEE Journal Solid-State Circuits, vol. 26,
no. 4. pp. 628-636, April 1991.

T. Matsuura, eta1., “ A 95 mW, 10b, 15Mhz lower-power CMOS ADC using
analog double-sampled piplining scheme,” Symposium on VLSI Circuits,
Digests Technology Papers, pp. 98-99, 1992.

B. S. Song, M. F. Tompsett, and K. R. Lakshmikumar, “A l2-bit l-Msample/
s capacitor error-averaging pipelined AID converter,” IEEE Journal Solid-
State Circuits, vol. 23, no. 6, pp. 1324-1333, December 1988.

M. Yotsuyanagi, E. Etoh, and K. Hirata, “A 10-b SO-Mhz pipelined CMOS
AID converter with S/H,” IEEE Journal Solid-State Circuits, vol. 28, no. 3,
pp. 292-300, March 1993.

B. Razavi and B. A. Wooley, “A 12b SMSampleIs two-step CMOS AID con-
verter,” IEEE Journal Solid-State Circuits, vol. 27, no. 12, pp. 1967-1978,
December 1992.

S. Hosotani, et al., “An 8 bit 20 MS/s CMOS AID converter with 50 mW
power consumption,” IEEE Journal Solid-State Circuits, vol. 25, no. 1, pp.
167-172, Feburary 1990.

T. Matsuura, et al., “An 8b 50Mhz 225mW submicron CMOS ADC using
saturationelirninated comparator,” Proc. of IEEE Custom Integrated Circuits
Conference, pp 6.4.1-6.4.4, 1990.

M. Ishikawa and T. Tsukahara, “ An 8 -bit 50-MI-Iz CMOS subranging AID
converter with pipelined wide-band S/I-I,” IEEE Journal Solid-State Circuits,
vol. 24, no. 6, pp. 1485-1491, December 1989.

A. G. W. Venes and R. J. van de Plassche, “ An 80-Mhz, 80mW, 8-b CMOS
Foldinf AID Converter with Distributed Track-and-Hold Preprocessing,”

116

 

30.

31.

32.

33.

34.

35.

36.

37.

38.

IEEE Journal Solid-State Circuits, vol. 31, no. 12, pp. 1846-1853, December
1996.

C. C. Chen and C. Y. Wu, “Design Techniques for 1.5-V Low-Power CMOS
Current-Mode Cyclic Analog-to-Digital Converters”, IEEE Trans. on Cir-
cuits and Systems-II: Analog and Digital Signal Processing, vol. 45, no. 1,
pp. 28-40, January, 1998.

M. Bracey, W. Redman-White, J. Richardson, and J. B. Hughes, “A Full
Nyquist 15 MSIs 8-b Differential Switched-Current AID Converter”, IEEE
Journal Solid-State Circuits, vol. 31, no. 7, pp. 945-951, July 1996.

M. P. Flynn and D. J. Allstot, “CMOS Folding AID Converters with Current-
Mode Interpolation”, IEEE Journal Solid-State Circuits, vol. 31, no. 9, pp.
1248-1257, September 1996.

I. Galton and H. T. Jensen, “Oversampling Parallel Delta-Sigma Modulator
AID Conversion”, IEEE Trans. on Circuits and Systems-II: Analog and Digi-
tal Signal Processing, vol. 43, no. 12, pp. 801-810, December, 1996.

P. c. Yu and H. s. Lee, “A 2.5V, 12-b, 5-MSamples/s Pipelined CMOS
ADC”, IEEE Journal Solid-State Circuits, vol. 31, no. 12, pp. 1854-1861,
December 1996.

M. Mayes and S. W. Chin, “A 200mW, 1 Msample/s, l6-b Pipelined AID
Converter with On-Chip 32-b Microcontroller”, IEEE Journal Solid-State
Circuits, vol. 31, no. 12, pp. 1861-1872, December 1996.

T. Kwan, R. Adams, R. Libert, “A Stereo Mutibit 2A DAC with Asynchro-
nous Master-Clock Interface,” IEEE Journal Solid-State Circuits, vol. 31, no.
12, pp. 1881-1887, December 1996.

T. Hamasaki, et al., “A 3-V, 22-mW Multibit Current-Mode 2A DAC with
lOOdB Dynamic Range,” IEEE Journal Solid-State Circuits, vol. 31, no. 12,
pp. 1888-1894, December 1996.

R. Romanczyk and B. H. Leung, “BiCMOS Circuits for High Speed Current
Mode D/A Converters,” IEEE Journal Solid-State Circuits, vol. 30, no. 8, pp.
923-934, August 1995.

117

39.

40.

41.

42.

43.

45.

46.

47.

48.

P. Ju, K. Suyama, P. F. ferguson, W. Lee, “A 22-kHz Multibit Switched-
Capacitor Sigma-Dalta D/A Converter with 92 dB Dynamic Range,” IEEE
Journal Solid-State Circuits, vol. 30, no. 12, pp. 1316-1324, December 1995.

H. J. Schouwenaars, D. W. J. Groeneveld and H. A. H. Termeer, “A Low-
Power Stereo 16-bit CMOS DIA Converter for Digital Audio”, IEEE Journal
Solid-State Circuits, vol. 23, no. 6, pp. 1290-1297, December 1988.

L. Weyten and S. Audenaert, “TWO-Capacitor DAC with Compensative
Switching”, IEE Electronics Letters, vol. 31, no. 17, pp. 1435-1437, August
1995.

P. Rombouts and L. Weyten, “Linearity Improvement for Switched-Capaci-
tor DAC”, IEE Electronics Letters, vol. 32, no. 4, pp. 293-295, Feburary
1996.

T. Miki, Y. Nakamura, Y. Akasaka, and Y. Horiba, “An 80-Mhz 8-bit CMOS
DIA converter,” IEEE Journal Solid-State Circuits, vol. 21, no. 6, pp. 983-
998, December 1986.

Y. Nakamura, T. Miki, A. Maeda, H. Kondoh and N. Yazawa “A lO-bit
70MSIs CMOS DAC,” IEEE Journal Solid-State Circuits, vol. 26, no. 4, pp.
637-642, April 1991.

T. Wu, C. Jih, J. Chen, and C. Wu, “A low glitch 10-bit 75Mhz CMOS Video
DIA converter.” IEEE Journal Solid-State Circuits, vol. 30, no. 1, pp. 68-72,
January 1995.

N. Tan, E. Cijvat, and H. Tenhuen, “Design and Implementation of High-Per-
formance CMOS DIA Converter,” Proc. of IEEE International Symposium
on Circuits and Systems, pp. 421-424, HongKong, 1997.

S. Krishnan, "Design and Test of Current-Mode Signal Processing Circuits,"
Ph.D. Dissertation, Department of Electrical Engineering, Michigan State
University, August 1993.

C. P. Wang, ”Efficient Testability Design Methodologies for Analog/mixed-
signal Circuits,” Ph.D. Dissertation, Department of Electrical Engineering,
Michigan State University, December 1997.

118

 

49.

50.

51.

52.

53.

54.

55.

56.

57.

58.

59.

C. P. Wang and C. L. Wey, "Test Generation of Switched-current AID Con-
verters," Proc. of IEEE International Mixed Signal Testing Workshop, Que-
bec City, Canada, pp. 98-103, 1996.

C. P. Wang and C. L. Wey, "Test Generation of Analog Switched-Current
Circuits," Proc. of IEEE Asian Test Symposiums, Hsinchu, Taiwan, pp. 376-
381, 1996.

C. P. Wang, and C. L. Wey, "Fault Macromodel for Switches in Switched-
Current Circuits," International Journal of Circuit Theory and Applications.
vol. 26, no. 1, pp. 93-102, January 1998.

C. L. Wey, "Test techniques for CMOS Switched-Current Circuits," Analog
and Mixed-Signal Test, Edited by B. Vinnakota, Prentice-Hall, Inc., 1998.

J. Robert, P. Deval, and G. Wegmann, “Very Accurate Current Divider,”
Electronics Letters, vol. 25, no. 14, pp. 912-913, 1989.

C. L. Wey, and S. Krishnan, “An Accurate Current-Mode Divide-by-Two
Circuit,” Electronics Letters, vol. 28, No. 9, pp. 820-822, 1992.

D. F. Hoeschele, Analog-to-Digital and Digital-to-Analog Conversion Tech-
niques, John Wiley & Sons, Inc, 1994.

D. Kim, J. Park, S. Kim, D. Jeong, and W. Kim, “A Single Chip D-S ADC
with Built-In Variable Gain Stage and DAC with a Charge Integrating Sub-
converter for 5V 9600-b/s Modem,” IEEE Journal of Solid-State Circuits,
Vol. 30, No. 8, pp. 940-943, August 1995.

R. Khoini-Poorfard, L. B. Lim, and D. A. Johns, “Time-Interleaved Over-
sampling AID Converters: Theory and Practice,” IEEE Trans. on Circuits and
Systems, Part H: Analog and Digital Signal Processing, Vol. 44, No. 8, pp.
634-644, August 1997.

B. Ginetti, P. G. A. Jespers, and A. Vandemeulebroecke,” A CMOS 13-b
Cyclic RSD AID Converter,” IEEE Journal of Solid-State Circuits, vol. 27,
no. 7, pp. 957-965, July 1992.

K. Huang, Computer Arithmetic -- Principles, Architecture and Design, John
Wiley & Sons, Inc, 1979.

119

60.

61.

62.

63.

65.

66.

67.

68.

69.

70.

S. Krishnan and CL. Wey, "A Parallel Current-mode AID Converter Array
with a Common Current Reference-Generating Circuit," Proc. of IEEE Mid-
west Symposium on Circuits and Systems, Lafayette, LA, pp. 1168-1171,
1994.

C. L. Wey, S. Krishnan, and S. Sahli,” Test generation and Concurrent Error
Dection in Current-Mode AID converters,” IEEE Trans. on CAD of Inter-
grated Circuits and Systems, vol. 14, no. 10, pp. 1191-1198, October 1995.

C. L. Wey, "Built-in Self-Test (BIST) Design of Current-mode Algorithmic
AID Converter," IEEE Trans. on Instrumentation and Measurement. Vol. 46,
No. 3, pp. 667-671, June 1997.

J. S. Wang, and C. L. Wey, ”Synthesis of Optimal Current Copiers for Low-
Power/Low-Voltage Switched-Current Circuits”, Proc. of IEEE Midwest
Symposium on Circuits and Systems, Notre Dame, IN, 1998.

J. S. Wang, and C. L. Wey, “A 12-bit, lOOns/b, 1.9mW CMOS Switched-Cur-
rent Cyclic AID Converter,” Proc. of IEEE International Symposium on Cir-

cuits and Systems, Monterey, CA, 1998.

P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Oxford Uni-
versity Press,Inc, 1987.

D. A. Johns and K. Martin, Analog Intergrated Circuit Design, John Wiley &
Sons, Inc, 1997.

P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Cir-
cuits, John Wiley & Sons, Inc, 1993.

J. E. Franca and Y. Tsividis, Design of Analog-Digital VLSI Circuits for Tele-
communications and Signal Processing, Prentice Hall, Inc, 1994.

J. S. Wang, and C. L. Wey, “A lO-b lOOMS/s, 2.8mW CMOS Switched-Cur-
rent DAC for Low-Power/Low-Voltage Signal Processing Applications,”
Proc. of IEEE Midwest Symposium on Circuits and Systems, Notre Dame,
Indiana, 1998.

J. S. Wang, and C. L. Wey, “High-Performance CMOS Switched-Current D/
A Converters for Low—Power/Low-Voltage Signal Processing Applications,”

120

 

71.

72.

73.

74.

75.

76.

Proc. of IEEE International Conference on Electronics, Circuits, and Sys-
tems, pp. 19-22, Lisboa, Portugal, 1998.

J. S. Wang, and C. L. Wey, "An Accurate CMOS Current Divider Circuit,"
Proc. of IEEE International Symposium on Circuits and Systems, Monterey,
CA, 1998.

D. W. J. Groeneveld, H.J. Schouwenaars, H.A.H. Termeer, and C.A.A.
Bastiaansen, “A Self-Calibration Technique for Monolithic High-Resolution
DIA Converters,” IEEE Journal of Solid-State Circuits, vol. 24, no.6, pp.
1517-1522, December 1989.

C. L. Wey and S. Krishnan, “Built-In Self-Test(BIST) Structures for Analog
Circuit Fault Diagnosis with Current Test Data,” IEEE Trans. on
Instrumentation and Measurement, vol. 41, No. 4, pp. 535-539, August 1992.

J. S. Wang, W. H. Huang and C. L. Wey, “Built—In Testers for Analog/Mixed-
Signal Circuits with CMOS Switched-Current Technique," Proc. of IEEE
International Mixed-Signal Workshop, Hague, Netherlands, 1998.

J. S. Wang, W. H. Huang and C. L. Wey, “Fault Simulation of CMOS
Switched-Current Circuits with Built-In Tester," Proc. of IEEE Midwest
Symposium on Circuits and Systems, Notre Dame, Indiana, 1998.

M. Soma, “Structure and Concepts for Current based Analog Scan,” Proc. of
IEEE Custom Integrated Circuit Conference, pp. 517-520, 1995.

121

MICHIGAN STATE UNIV. LIBRQRIES
IIHIWIIWIIIIIIINIIUIUHIIII‘IIIIIIIIWIIIIHIIIIIHI
31293017668041