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HIGH PERFORMANCE CMOS SNITCHED-CURRENT CIRCUITS
FOR LON-VOLTAGE SIGNAL PROCESSING APPLICATIONS

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Renyuan Huang
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use COMM“

HIGH PERFORMANCE CMOS SWITCHED-CURRENT CIRCUITS
FOR LOW-VOLTAGE SIGNAL PROCEESSING APPLICATIONS

By

Renyuan Huang

A DISSERTATION

submitted to
Michigan State University
in partial fulﬁllment of the requirements
for the degree of

DOCTOR OF PHILOSOPHY

Department of Electrical Engineering

1998

ABSTRACT

HIGH PERFORMANCE CMOS SWITCHED-CURRENT CIRCUITS
FOR LOW-VOLTAGE SIGNAL PROCEESING APPLICATIONS

By

Renyuan Huang

Portable televisions, camcoders, and compact disk players have been made avail-
able by consumer electronics companies. Cellular phones provide virtually unlimited
access for voice communications; and laptops, notebooks and palmtops are the fastest
growing types of computers. Portable multimedia terminal will come into being, which will
be capable of providing speech communication, data transfer, handwriting recognition, and
high-quality, full motion video. Each of these technologies relies on VLSI for cost and
power-consumption effective implementation. Given sufﬁcient complexity, even CMOS
dissipation levels become excessive especially where high frequency is involved. It is nec-
essary to optimize the VLSI-technology for low-power operation of digital/analog circuits.

CMOS switched-current (SI) technique has received considerable attention as an
alternative for analog circuit design. However, existing SI circuits cannot make the theoret-
ically expected performance due in part to the use of non-optimal current copiers, its basic
building blocks. With the developed design methodologies and synthesis process for Opti-
mally generating low power and high performance CMOS current copiers, SI technique

becomes feasible.

The objective of the thesis research is to develop new generation of high-perfor-
mance, low-power/low-voltage current-mode circuits. The emphasis is placed on the devel-
opment of sample/hold circuits, and analog-to-digital circuits for mixed-signal IC’s in
future portable equipment. In this study, a simple yet high performance SI V-I converter
with the S/H function and an oversampled high linear S/H circuit are developed. Result
shows that, with the small resistor in the V-I converter, 3 large dynamic range of the con-
verted current can be obtained with a small swing of input voltages. Thus, the circuit is via-
ble for low-voltage operation. The developed oversampled SI S/H circuit adopts a simple
forward approach to reduce the output current of the integrator. With a simple structure and
a small oversampling ratio, the circuit achieves high accuracy. This study also develops a
high performance cyclic AID converter circuit design. The high performance is attributed
to: (1) the use of high performance current copiers; (2) the use of a residual ampliﬁer which
takes two clock cycles to double a current; (3) the use of an efficient Cyclic RSD algorithm
which provides 1.5b resolution without using two matched reference currents.

The developed circuits meet the design requirement not only for portable equip-
ments, but also for video signal processing, such as HDTV, high-frequency digital commu-
nications, and waveform acquisition/instrumentation. This research has demonstrated that
this development is not merely an academic curiosity, but an important practical technology

for the future.

ACKNOWLEDGMENTS

The author wishes express his sincere gratitude to his advisor Dr. Chin-Long Wey
for his guidance, advices and numerous help, not only academically but also personally.
The author would like to acknowledge Dr. James A. Resh, Dr. Gregory M. Wierzba, and
Dr. “William Pratt for their work in the guidance committee and for the helpful questioning
and discussions during committee meetings. This research was sponsored in part by
National Science Foundation under grant number MIP-9321225.

Finally, the author is especially grateful to his beloved wife Ming for her tolerance,

patience and support.

iv

TABLES OF CONTENTS

LIST OF FIGURES .............................................................................................. viii
Chapter 1: Introduction ..................................................................................... 1
1.1 Problem Statement .......................................................................... 3

1.2 Previous Works ................................................................................ 4

1.3 Research Tasks ............................................................................... 5

1.4 Thesis Organization .......................................................................... 7
Chapter 2: Background ..................................................................................... 8
2.1 Current Mirrors ................................................................................. 8

2.2 Current Copiers ................................................................................ 10

2.2.1 Cascode Current Copiers ...................................................... 14

2.2.2 Negative Feedback Current Copiers .................................... 16

2.3 Switched-Current Circuits .................................................................. 19

2.3.1 Switched-Current Converters ............................................. 19

2.3.2 Switched-Current S/H Circuits ........................................... 21

2.4 Discussion ........................................................................................ 23
Chapter 3: High Performance Current Copiers ................................................... 25
3.1 Performance Analysis ........................................................................ 25

3.1.1 Charge-Feedthrough Error Effects ..................................... 26

3.1.2 Stray Effects ..................................................................... 30

3.1.3 Signal-to-Noise Ratio (SNR) .............................................. 36

3.1.4 Discussion ........................................................................ 48

3.2

3.3

3.4
Chapter 4:
4. 1

4.2

4.3
Chapter 5:
5.1
5.2

5.3

Alternative Negative Feedback Current Copiers .............................. 50
3.2.1 Structure and Operation ...................................................... 50
3.2.2 Stray Effects ...................................................................... 53

Simulation Results ............................................................................ 56
3.3.1 Speed Limitation ................................................................ 58
3.3.2 Error Currents .................................................................... 63

Discussion ........................................................................................ 65

Sample and Hold (S/H) Circuits ...................................................... 66

A V-I Converter with S/H Function .................................................. 67
4.1.1 Structure and Operation ..................................................... 69
4.1.2 Speed Limitations ............................................................... 72
4.1.3 Simulation Results ............................................................... 75

An Oversampled S/H Circuit ............................................................. 79
4.2.1 The Feedforward Approach ................................................ 79
4.2.2 Structure and Operation ...................................................... 83
4.2.3 Simulation Results .............................................................. 85

Discussion ........................................................................................ 86

Analog-to-Digital Converter Circuits ............................................... 89

Cyclic Conversion Algorithms ......................................................... 90

Cyclic AID Converter Circuit Designs ............................................... 93
5.2.1 A 4—cyc1e Cyclic Converter .............................................. 93
5.2.2 A 3-cycle RSD Cyclic Converter ..................................... 95

Proposed 2-Cycle RSD Cyclic Converter ...................................... 97
5.3.1 Structure and Operation ................................................... 97
5.3.2 Convergency Range ........................................................ 102
5.3.3 Comparator Levels .............................................................. 104
5.3.4 Decoding ........................................................................ 105

vi

5.4 Circuit Description ............................................................................ 107

5.4.1 Circuit Structure ............................................................... 107

5.4.2 Control Circuitry ............................................................. 113

5.4.3 Simulation Results ........................................................... 113

5.5 Discussion ...................................................................................... 1 17
Chapter 6: Conclusion ..................................................................................... 118
6.1 Summary and Contribution ................................................................ 119

6.2 Future Research ............................................................................. 121

LIST OF REFERENCES .................................................................................... 123

vii

Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6

Figure 2.7

Figure 2.8

Figure 3.1
Figure 3.2

Figure 3.3

Figure 3.4

Figure 3.5

Figure 3.6
Figure 3.7

LIST OF FIGURES

Simple Current Mirrors: (a) NMOS; and (b) PMOS. ........................
Basic Structure of a Current Copier. .................................................
Output Conductance Resulting From CGD ........................................
Charge Dumped Onto C1 Through Switch 82. ..................................
Cascoded Copiers: (a) Simple; and (b) Regulated. ............................
INFCC: (a) Circuit Structure; (b) Feedback Ampliﬁer with a High
Input Impedance; and (c) with a Low Input Impedance ....................
Cyclic Converter: (a) Block Diagram; (b) SI x2 Unit; and (c) State
Table. .................................................................................................
An Oversampling S/H Circuit with an Integrating Feedback Struc-
ture: (a) Basic Structure; and (b) Signal-ﬂow Graph .........................
Equivalent Circuit of the Copier for VDD-VX< V31 ...........................
Performance Analysis: (a) Effect of Power Supply Voltage on the
Stray Capacitance cs; (b) on the Resistance r52; and (c) Small Signal
Linearized Model. ..............................................................................
Simple Cascode Copiers: (a) Improved Version; and (b) Equivalent
Circuit. ...............................................................................................
Regulated Cascode Copiers: (a) Improved Version; and (b) Equiva-
lent Circuit. ........................................................................................
INFCC: (a) Ampliﬁer Model & (b) Calibration Model of INFCCI;
and (c) Ampliﬁer Model & ((1) Calibration Model of INFCCII. .......
A Pair of Basic Copiers with Noise Current Sources. ......................
Basic Copier: (a) Noise as a Function of Modulation Index; and (b)

Modulation Index for Maximum Noise as a Function of 1). ..............

viii

11

13

13

15

17

20

22

29

31

34

34

37
39

41

Figure 3.8

Figure 3.9
Figure 3.10

Figure 3.11
Figure 3.12

Figure 3.13
Figure 3.14
Figure 3.15
Figure 3.16

Figure 3.17

Figure 3.18

Figure 4.1
Figure 4.2

Figure 4.3
Figure 4.4
Figure 4.5

Figure 4.6
Figure 4.7

Figure 4.8

Figure 4.9

Structure Functions for Basic Copiers: (a) nB(m,-,u); and (b) Opti-
mum Device Parameter Values uo. ....................................................
Cascode Copier: (a) Schematic; (b) nc(m,~,t)); and (c) Optimum no.

Negative-Feedback Copier: (a) Schematic; (b) nN(m,—,u); and (c)
Optimum no. ......................................................................................
Performance Comparisons: (a) Power; and (b) Capacitance. ............
FNFCCs: (a) Schematic; (b) CMOS Ampliﬁer; (c) BiCMOS
Ampliﬁer; (d) Equivalent Circuit for FNFCCI; and (e) for FNCCIL
Equivalent Circuits: (a) FNFCCI; and (b) FMFCCH. .......................
Stray Effect Reduction. ......................................................................
Simulated Circuits: (a) Block Diagram; and (b) Schematic. .............
Effects of Sample Switch: (a) Settling Time; (b) Equivalent Circuit;
and (c) Optimal Capacitance. ............................................................
Current-Storage Switch Effects: (a) Equivalent Circuit; (b) Settling
time; and (c) Current Cell Pair. ..........................................................
(a) Settling Time; and (b) Error Currents. .........................................
Proposed Current-Copier—Based V-I Converter with S/H Function. .
Schematic Circuit Diagram of the Propose V-I Converter. ...............
Linearized Small-signal Equivalent Circuits: (a) Switch Transistor
[21]; and (b) Proposed V-I Converter. ...............................................
Transconductance vs. Input Frequency. ............................................
Total Harmonic Distortion (THD) vs. Relative Input Currents. ........
Total Harmonic Distortion (THD) Vs. Input Frequency. ..................
Proposed S/H Circuit with Feedforward Approach: (a) Basic Struc-
ture; (b) Current Copying Operation; and (c)-(e) Equivalent Cir-
cuits for the Three Clock Cycles in a Loop Operation. ....................
Transistor-level Implementation of Proposed S/I-I Circuit: (a) Sche-
matic Diagram; (b) Ampliﬁer; and (c) Input Stage. ..........................
Simulation Results: (a) Signal-to-Distortion (SDR) Ratio; and (b)

Simulation Noise Floor. .....................................................................

ix

45

47
49

51

55

55

57

59

62

68
70

73

77

77

78

80

84

87

Figure 5.1

Figure 5.2

Figure 5.3

Figure 5.4

Figure 5.5

Figure 5.6

Figure 5.7
Figure 5.8
Figure 5.9

Figure 5.10

Figure 5.11
Figure 5.12

Figure 5.13

Cyclic Analog-to-Digital Conversion Algorithms: (a) RC Algo-
rithm; and (b) RSD Algorithm. ..........................................................
Transfer Characteristics of RC Algorithm: (a) Ideal Case; (b) with
Comparator Error; and (c) with Loop Offset Error. ........................
Transfer Characteristics of RSD Algorithm: (a) Ideal Case; (b) with
Comparator Error; and (c) with Loop Offset Error. .........................
A 4-cycle Cyclic AID Converter: (a) Schematic; and (b) Switching
sequence. .........................................................................................
A 3-cycle Cyclic AID Converter: (a) Schematic; and (b) Switching
sequence. .........................................................................................
A 2-cycle Cyclic AID Converter: (a) Schematic; and (b) Switching
sequence. .........................................................................................
Residual Current Transition. .............................................................
The Comparison Levels with Respect to the Convergence Regions.
The Decoder. .....................................................................................
Proposed AID Converter Circuit: (a) Schematic; (b) Modiﬁed
FNFCC; (c) Input Stage with Switch 81; (d) Feedback Ampliﬁer;
and Equivalent Circuits of the Level Shifter for (e) (D1 & (D3; and
(f) (1)2 and (1)4. ...................................................................................
Current Copier with the Input Stage. ................................................
Control Circuitry: (a) Reference-Current Generating Circuit; (b)
State-Transition Diagram; and (c) Logic Implementation. ................
Simulation Results: (a) Typical Current Waveform; (b) Partial Out-
puts for Inf]; and (c) 12-bit Resolution. ...........................................

91

92

92

94

96

98

103

106
108

109
112

114

116

Chapter 1

Introduction

 

 

 

There is always the desirability of portable operation for all types of electronic sys-
tems. A signiﬁcant market advantage can be obtained for virtually any electronic function
by merely providing the same functionality of a wired system in a wireless implementation
[1]. Portable televisions, camcoders, and compact disk players have been made available
by consumer electronics companies. Cellular phones are going to provide virtually unlim-
ited access for voice communications; and laptops, notebooks and palmtops are the fastest
growing types of computers. In the next few years, portable multimedia terminal will come
into being, which will be capable of providing speech communication, data transfer, hand-
writing recognition, and high-quality, full motion video. Through the multimedia terminal,
individual users will have portable access to ﬁxed computing facilities [2].

Each of these technologies relies on VLSI for cost and power-consumption effec-
tive implementation [3]. Complicated digital processing, such as audio/video compression
and decompression will be used. Since the signals to and from I/O devices, such as mag-
netic recordings, microphones, speakers, CCD’s, LCD’s, and wireless modulators and
demodulators, are analog, the use of analog processing will continue, however, to be con-

ﬁned mainly to the digital-analog interfaces [4]. Most of the chip area will be dedicated to

digital applications. The chip power consumption will originate mainly from the digital cir-
cuits. Given sufﬁcient complexity, even CMOS dissipation levels become excessive espe-
cially where high frequency is involved. It is necessary to optimize the VLSI-technology
for low-power operation of the digital circuits [5]. This situation creates a great challenge
for analog circuit designers.

The power of a CMOS digital circuit can be optimized by minimizing the expres-
sion Power: CVddzf. The capacitance C can be reduced by sealing down the MOS device,
but not without a boundary. A limitation on the reduction of C is set by the interconnection
capacitance that ceases to scale below IIIm due to photolithographic considerations.
Reducing V“ is the most strongly suggested way to achieve the power minimization. The
power should go down quickly with Vdd because it is proportional to the square of the sup-
ply voltage. On the other hand, the reduction of Vdd will cause speed loss. The reason is that
a gate has a longer delay for a lower supply voltage. Moreover, the speed loss can be com-
pensated for by using parallelism. Suppose that the gate delay is doubled because of the
supply voltage reduction, two paralleled gates can then be used to keep the throughput the
same as that before the supply voltage is reduced. Although C will be doubled due to the
double of the hardware, f will be halved as only half the throughput is provided by every
device. Therefore, Cf is kept constant. This principle shows that parallelism can be used as
much as possible for supply voltage reduction without reducing the throughput. Unfortu-
nately, some overhead hardware is needed to realize the parallelism, which makes If
increase with the degree of parallelism. As a result, there is an optimum supply voltage for
achieving lowest power consumption. This voltage is found to be about equal to 1.5 and 1

volts for a 2pm and a 0.6].Lm process, respectively [2]. Mth such supply voltages, a high-

gain high-speed operation ampliﬁer is unobtainable.

To keep the static power consumption low and the digital noise margin high, the
threshold voltage will not be scaled down with the supply voltage [5]. The combination of
low supply and high threshold voltages diminishes the allowed voltage swings in analog
circuits which results in worsened dynamic range. The analog switch characteristics are
also degraded [6].

Adequate yield and low cost with higher digital complexity will be achieved by
process simpliﬁcation. This again adds to the burden of analog design since special options
included in today’s processes to assist analog design (e. g. second polysilicon layer for
implementing linear ﬂoating capacitors) may soon become a historic luxury. Still worse,
the increasingly high performance of the digital signal processor must be matched by its
analog interface (e. g. speed, dynamic range, linearity etc.) and this enhanced performance
must be achieved in the noisy environment of digital circuits [5].

In summary, future analog circuits will need to perform better in nosier conditions

and with less optimum, digitally-oriented, CMOS process.

1.1 Problem Statement

Some recent innovative work to lower the power supply to 3.3V or lower are indi-
cating possible solutions to this dilemma. The insufﬁcient-dynamic-range problem due to
down-scaled supply voltage is avoided by using current, instead of voltage, to represent the
signal [7]. This change from voltage to current mode creates also the potential for speed
improvement because stray-inductance effects are less severe in low-impedance circuits

than stray-capacitance effects in high-impedance circuits. High accuracy is obtained by so

called switched-current (SI) technique, using dynamic calibration to alleviate the error due
to elements mismatch [8].

The SI technique couples itself well with the down-scaled CMOS technology,
where transistors with a high cut-off frequency are available, meaning a high calibration
speed. Another advantage of this technology is that highly-linear capacitance is not needed
for high accuracy analog signal processing. Alternatively, accuracy has been traded with
speed in Z-A modulators using oversampled techniques to achieve performance orders of
magnitude higher than traditionally associated with analog limitations [9]. The challenge
and the gains are clear for the designer who can manage the extra demands on analog per-
formance with diminishing resource of digitally-motivated VLSI process development.
This thesis study addresses this challenge by making full use of the salient pr0perties of
switched-current circuits to improve the speed of the circuit with power supply voltage of
3.3V, or lower. New structures for hi gh-performance, low-voltage/low-power current-
mode data acquisition and conditioning circuits, such as, analog-to—digital converters
(ADC’s, or AID converters) and sample and hold (SIH) circuits will be developed for

mixed-signal IC’s for future portable equipments.

1.2 Previous Works

A number of outstanding low-power pipelined CMOS ADC’s have been reported
recently, such as a lO—b, 20MS/s, 35mW ADC [10] in 3.3V supply voltage and 1.2um pro-
cess; a lO—b, 20MS/s, 50mW ADC [11] in SV supply voltage and 1.2um process, and a 10-
b, 4OMS/s, 85mW ADC [12] in 2.7V supply voltage and 0.8um process. They are imple-

mented with switched-capacitor techniques in which the accuracy and speed are limited by

(1) the accuracy of the capacitance matching; and (2) the use of high-gain ampliﬁers which
have two or more stages for error reduction. It would be very difﬁcult for them to increase
the accuracy above 10 bits without having a substantial increase in area and power con-
sumption. On the other hand, further reduction of the supply voltage is virtually impossible.
Some reported current-mode Adds achieve low supply voltage, including a 12-b, 2V Cur-
rent-Mode Pipelined AID Converter Using a Digital CMOS Process [13], and a 1.5V
Video-Speed Current-Mode Current-Tree AID converter [6]. The design in [13] achieves
only a sample rate of IMS/s, but its power consumption is 60 mW. The design in [6] has a
sample rate 20MS/s, but it uses current mirrors to create equal current sources. Its accuracy
depends on element match and is limited to about 8-b.

For some applications, a sample rate higher than 50 MS/s may be needed. An effec-
tive bipolar solution using the bridge-diode S/H circuit has been provided [14]. In CMOS
technology, an open-loop S/H using switched-capacitor has been demonstrated in a 8 b
ADC with a sample rate of 85 MS/s [15], while closed-loop S/H circuits for 10 b at 50 MS/
5 [l6] and 100 MS/s [17] have also presented. However, they have either high power con-

sumption or low accuracy.

1.3 Research Tasks

The objective of the thesis research is to develop new generation of high-perfor-
mance, low-power/low-voltage current-mode circuits. The emphasis is placed on the devel-
opment of S/H circuits and ADC circuits for mixed-signal IC’s in future portable

equipment.

A simple, yet high-speed, high-linearity current copier with a compensator can be
used as a S/H circuits. The compensator can reduce the errors due to the capacitive current
and the increase of high-frequency linearity of the current copiers. Thus, the current c0pier
can process rapidly varying continuous-time signal and acts as a high-performance S/H cir-
cuit. In this task, two types of SIP] circuits are developed: a V-1 converter with S/H function,
and an oversampled S/H circuits.

Low speed of the switched-current ADC is not due to physical limitations, but non-
optimized circuit structure and the use of switches with large stray capacitance in the signal
path. In this task, new designs for high speed current copier and current switches with much
smaller stray capacitance are presented. Based on the developed high-performance current
copiers, the initial target performance of the proposed parallel ADC is set at an accuracy of
12 bits and 0.1mW/bit/Ml-Iz power consumption in 2-3V supply voltage with orbit standard
SCDN2O 2um digital CMOS process. The performance can be further improved with better
technology, such as 1.2um or 0.8um process. The major concern is higher accuracy, higher
speed, and lower power. In addition, the approach must be compatible with modern digital
CMOS process.

The circuits developed in this study will meet the design requirement not only for
portable equipments, but also for video signal processing, such as HDTV, high-frequency
digital communications, and waveform acquisition/instrumentation. This research will
demonstrate that this development is not merely an academic curiosity, but an important

practical technology for the future.

1.4 Thesis Organization

This thesis is organized as follows: Chapter 2 reviews the previous work in the
design of current mirrors, current copiers, and some existing current-mode circuits. Chapter
3 presents the developed high-performance current copiers. Based on the developed high-
perforrnance current copiers, the designs of both SIH circuits and ADC circuits are dis-
cussed in Chapters 4 and 5, respectively. Finally, conclusions and future research are given

in Chapter 6.

Chapter 2

Background

 

Current copier is the basic building block of Switched-Current (SI) circuits. It is
developed to alleviate the errors of conventional current mirrors caused by fabrication tol-
erance. Section 2.1 reviews the current mirrors and their error effects, while Section 2.2
outlines the existing current copiers and the difﬁculties for achieving high speed and high

accuracy. Finally, Section 2.3 discusses the existing SI circuits related to this study.

2.1 Current Mirrors

A current mirror, as shown in Figure 2.1, is a circuit that reproduces its input cur-
rent. The output current 10 equals the input current Ii if its two transistors are identical and
their output impedances are very high. In practice however, it is virtually impossible to ob-
tain identical transistors due to the following error effects: (1) Channel length modulation
(r0); (2) Aspect ratio mismatch (W/L); (3) Threshold voltage mismatch (VT), and (4) mo-
bility mismatch (11). Note that the error due to the channel-length modulation can be re-
duced by using some circuit technologies presented in [18], while errors (3) and (4) can be

alleviated when large-size transistors are used. On the other hand, the error due to the aspect

 

 

 

 

 

 

 

 

 

 

(b)

Figure. 2.1: Simple Current Mirrors: (a) NMOS; and (b) PMOS.

ratio mismatch can be reduced by using long-channel transistors [19], but it is penalized by
limiting the speed performance particularly when high accuracy is required. As a result, the
ADC design using current-mirrors have been limited up to 8 bits when power and area opti-

mizations are considered [19,20], and up to 20MHz for the operating speed [6].

2.2 Current Copiers

Current copiers perform the same functions as current mirrors, but they alleviate the
error effects in current mirrors [8]. Figure 2.2 illustrates the basic structure of a current
copier. The input current [in is reproduced by turning on switches 81 and 82. The circuit will
settle to the state referred to as calibration state, where the capacitance Cl has a voltage nec-
essary to support the drain current ID] that is equal to Ii“, plus the bias current. Once the
required settling accuracy is reached, the circuit can be turned into the operation state by
opening 81 and 82, and closing S3. Thus the input current source I," is free for other uses, and
a load current Iout which is equal to Iin can be sunk by transistor M1. The transistor M1 is
called a current-storage transistor. The current Iout can be reproduced from the input cur-
rent Iin without the need of well-matched elements. However, the current copier is not free of
errors. It suffers from two errors due to (1) the nonzero output conductance go] of M1; and
(2) the clock feedthrough of 82 [8].

The nonzero output conductance g0, results from the channel length-modulation
effect [18] and the drain-gate capacitive coupling of transistor M1 [8]. The former effect
reﬂects the fact that the depletion region in the channel of a MOS transistor stretches itself
toward the source when the drain-source voltage VDS increases. This means that the distance

that a carrier from the source must pass to reach the drain is shorter for a higher drain-source

10

 

 

 

 

 

 

Ibras I gb
lin \ / Load
+ S‘ 53 T
00
F X
ID! V
32 D
Igo]
I M1
G Sol
—— S
._.._ Cl
'GND

Figure. 2.2: Basic Structure of a Current Copier.

11

voltage difference than for a lower one, resulting in an increase of the drain current with
VDS. On the other hand, the drain-gate capacitive coupling may also cause the nonzero con-
ductance when the gate of a MOS transistor is ﬂoating, as it is the case when a current-stor-
age transistor is in the operation state. As the small-signal equivalent circuit shown in
Figure 2.3, any variation on the drain voltage AVD will couple to the gate and cause a gate
voltage variation AVG As a result, a change of the drain current incurs through the
transconductance gm 1. The output conductance can be expressed as goc=CDG(CDG+C1)‘l
gmlzCDG't'l, where ‘l:=C1gm1'1 is the time constant of the current copier. This relation
reveals that for high-speed operation, i.e. small 1:, the current copier will have a large output
conductance.

The clock feedthrough error effect [21] is caused by the charge stored in the con-
ducting channel of a MOS transistor. As shown in Figure 2.4, one end of the switch is con-
nected to the gate node G of the transistor M1. During the tum-off transient, the gate voltage
Vg of the switch goes down, forcing the charge in the switch channel to leave. Some
charges, in the channel of the switch will dump onto the gate G The dumped charge
changes the voltage across the capacitance, causing the current Io“, sunk by M1 in the oper-
ation state to be different from 1,". Note that the charge stored in the switch-transistor chan-
nel and the sharing of the charge by the both ends depend on the voltage VG which changes
with the input current, thus, the error current will depend on the input current. In other
words, the error current is not just an offset [22-24], but also causes gain error and distortion
of the current copier.

A number of current copiers have been proposed recently to alleviate the error due

to the output conductance go], including cascode approach [8] and negative feedback ap-

12

 

Figure. 2.3: Output Conductance Resulting From CGD

l

Vq

 

transistor used to
realize $2

GandDaretheGatcandDrain
': nodesofthe transistorMI

Figure 2.4: Charge Dumped Onto C1 Through Switch 82.

13

proach [25,26]. A cascode current source has an output impedance much higher than a sim-
ple one. This technique has been widely used to design high-speed and high-gain operation
ampliﬁers [18], and to separate the drain of a current—storage transistor M1 from the output!
input node X to alleviate the effect of the input current on the drain potential. On the other
hand, the latter approach separates the gate of the current-storage transistor from node X.

This structural difference results in important performance difference of the copiers.

2.2.1 Cascade Current Copiers

Figure 2.5(a) illustrates a basic cascode current copier [8], where the current-stor-
age transistor M1 in Figure 2.2 is replaced by a cascode structure with M1 and M2. Due to
the cascode structure, the input current has a much smaller impact on the drain voltage of
M1 in this c0pier than that in the basic current copier shown in Figure 2.2. The drain voltage
of transistor M1 in Figure 2.2 is equal to the gate voltage during calibration and the varia-
tion of the error current I 80 due to the output conductance is related to the input current vari-
ation and can be expressed as

AIgo “ [(goi+gb)/gm1] AIin (2-1)
where gb is the output conductance of the bias current source. In addition, due to the eas-
code structure, the drain voltage variation of transistor M1 can be reduced by a factor of A2,
where A2=AVDZIAVSZzgm2/(g02+gb) is the voltage ampliﬁcation of the common gate
ampliﬁer consisting of transistor M2 and the bias current Ibias' Thus, the variation of the
error current 180 can be written as

Algo = Igor/(gmrAz) + gb/gml] Min (22)

This implies that the error can be reduced by a factor A2, if gb is kept small. Therefore, to

14

 

 

 

 

 

 

 

Figure 2.5: Cascoded Copiers: (a) Simple; and (b) Regulated.

15

keep a small gb, a cascode current source is needed for the bias current source.

The main disadvantage of the cascode copier is the use of the headroom transistor
M2, which reduces the gate available voltage swing of transistor M1 and increases the
requirement on the supply voltage. As can be seen in the later discussion.

The accuracy of the simple cascode copier and its need of high supply voltage can
be improved by a regulated cascode copier, as shown in Figure 2.5(b) [27], where the gate
bias voltage of M2 in Figure 2.5(a) is replaced by an ampliﬁer consisting of M3 and the bias
current source on its drain Idb3- The input of the ampliﬁer is connected to the drain of the
current-storage transistor Ml . Thus, its drain voltage variation with respect to the input cur-
rent is further attenuated by the voltage gain of the ampliﬁer. If the voltage gain of the
ampliﬁer is A 3, the error current due to the output conductance can be expressed as

AIgo z [801/(gm1A2A3) + gb/gml] AIin (2-3)
In addition, the drain voltage of M2 changes with its gate voltage. In other words, the tran-
sistor can work at the just-saturated bias point for all input currents. This will reduce the
power supply voltage. This point is made clear in the later discussion. In fact, as a large
error attenuation is provided by ampliﬁcation A3 and the main error is due to charge injec-
tion effect, M1 can be designed to work in the linear region to further reduce the power sup-

ply voltage, without loss of its accuracy [27].

2.2.2 Negative Feedback Current Copier

Figure 2.6(a) illustrates a negative feedback current copier. The structure provides
not only a constant drain voltage for the storage transistor, but also for the bias current

source at the same time. Thus, the bias can be implemented as a simple current source. As

16

 

 

 

 

 

S G V5832
D
10!!!
0——>
:01 lo
8 Vbias!
X G 5
‘41
D
vs
(13)
(8!)
V00
5 Vbiasz
80A In“ .
V - D
g"— bias]
Km 3"

(C)

Figure. 2.6: INFCC: (a) Circuit Structure; (b) Feedback Ampliﬁer with a
High Input Impedance; and (c) with a Low Input Impedance.

17

no headrooms are used, the copier can be operated using low supply voltage. In fact, unlike
the basic copier of Figure 2.2, where, in the operation state, the transistor M1 has the lowest
drain voltage for the largest drain current, the current-storage transistor in a negative feed-
back copier has always the same drain voltage for all drain current. This feature provides a
negative feedback copier the ability to be operated with the lowest power supply. Since the
current-storage transistor, together with the input current source, constitutes an inverter, the
copier is referred to as an Inverter Negative Feedback Current Copier, or INFCC. The per-
formance of an INFCC highly depends upon the type of feedback ampliﬁer it implements.
For simplicity, the INFCC with the ampliﬁer in Figure 2.6(b) is referred to as INFCCI [25],
while the INFCC with the one in Figure 2.6(c) is called INFCCII [9].

During calibration the switch 82 is on. The variation of the drain voltage of M1 is
related to the variation of its gate voltage and the voltage gain of the ampliﬁer as
AVD1=AVGI/A. Thus, the error currents for INFCCI and INFCCII can be represented as

AIgo z [(801+gb)/gm1A] Alin (2.4a)

AIgo z [(goi+gb)/gm1A + goA/gmil AIin (ZAP)
(2.4) conﬁrms that the error due to the output conductance of the bias-current source is
reduced at the same time with that of the current-storage transistor. The second term in (2.4
II) stands for a new error of INFCC II, because the ampliﬁer has an input current changing
with 1;". For high accuracy, the output conductance of the ampliﬁer 80A must be small, and
a cascode current source has to be used to generate the bias for the ampliﬁer. For the case

shown in Figure 2.6(c), the error of the copier can be quite large.

18

2.3 Switched-Current Circuits

Current copiers are the basic building blocks in SI circuits. This sub-section pre-

sents the designs of some SI circuits, such as, data converters and sample/hold circuits.

2.3.1 Switched-Current Converters

Recently, SI technique has been applied to design high-resolution analog-to-digital
converters [3,25,27]. An accuracy beyond what is possible using matched capacitor or
resistor networks can be reached by a simple inexpensive digital fabrication process. Figure
2.7(a) shows the functional diagram of a bit cell in a cyclic analog—to-digital converter. The
bit cell produces one bit digit word D(i) and the output residue current IR(i+1) from the
input residue current IR(i). The core unit of the bit cell that determines the accuracy is the
x 2 unit, called a residue ampliﬁer, which doubles the residue current. In SI technology,
the unit is implemented using current copiers as shown in Figure 2.7(b). It consists of 3 cur-
rent copiers and the switching states for the copier’s operation are shown in Figure 2.7(c).
Recall that the copier in the operation state outputs the current, while receiving the current
in the calibration state. The current stored in Copier 3 is copied to Copier 1 in the ﬁrst cycle,
i.e., 11:13, and to Copier 2 in the second cycle, i.e., 12:13, then the currents stored in both
Copiers I and 2 are copied back to Copier 3 in the third cycle, where Imm=ll+12=213mr
This concludes the operation for the computation of the residual current for the next bits.
In the above simpliﬁed explanation, the operation of a possible subtraction of a reference
current from the ampliﬁed residue is omitted. The subtraction can be done separately [25]
or at the same time as the residual ampliﬁcation [27]. For the former case one more clock

phase will be needed.

19

D(i)
<—

IREF

 

 

comparator

 

 

i

Oar-1“,.-

 

 

 

 

 

 

 

 

 

 

 

Copier 3

 

 

 

 

.5.”
U0
Copier I W
H

 

 

 

 

I—d
N
Copier2 ~>~ 0—.

 

 

 

(1))

U)
N
w

 

 

 

 

 

 

 

 

 

 

 

 

 

_> X 2 -> 1R(i+ 1)
T 1R0)
(at)
1 2 3
Copier 1 Calib. Idle Oper.
Copier2 Idle Calib. Oper.
Copier 3 Oper. Oper. Calib.
813 ON OFF ON
$23 OFF ON ON
S33 ON ON ON
(C)

Figure 2.7: Cyclic Converter: (a) Block Diagram; (b) SI x2 Unit; and
(c) State Table. (Calib - calibration, Oper. - operation.)

20

 

2.3.2 Switched-Current SIH Circuits

For current-mode data acquisition systems, current sample/hold (SIH) circuits are
frequently required to freeze fast moving signals before processing by the system. A num-
ber of current SIH circuits have been reported [28]. The main problem with the current-
mode SIH circuits is that high precision is difﬁcult to achieve due to the signal-dependent
clock feedthrough errors. Over-sample techniques have been proposed as an effective
method to reduce the errors.

Recently, a design methodology for highly accurate oversampling current SIH cir-
cuits with an integrating feedback structure, as shown in Figure 2.8(a), has been proposed
in [29]. The circuit consists of a gain stage (with DC gain of A1), a switched-current inte-
grator, and a current copier (CC). The same clock is applied to both the integrator and the
current copier. Consequently, the varying input current is sampled in the integrator while a
constant output is held by the current copier. The structure has the similar feature of a E—A
modulator, which achieves a very high linearity by limiting the signal bandwidth. Also, it
reduces both thermal noise and systematic errors simultaneously, thus the circuit provides
a superb linearity and a very large dynamic range even for continuous-time input currents.

Figure 2.8(b) illustrates an equivalent z-domain signal-ﬂow graph of the integrating
feedback structure in Figure 2.8(a), where two potential errors may result from the struc-
ture: one is from the integrator while the other from the copier CC. Let E1(z) and Ec(z)
denote the errors resulting from the integrator and the copier, respectively. The output cur-

rent can be expressed as
1

"7412-1 ( +Eﬁl)_ (l—z-l)z.i
1+(A1—1)z_l "' Ar 1+(Al—l)z_

 

 

Iout(z) = 1Ec(z) - (2'5)

21

Clock

1 Clock

 

 

 

 

P I>

(a)

EI(Z) Ec(Z)

 

—>
Iout

l z-1/2
Iin(z) AI .0 1 _z-l ’L 2' lI2 Iout(z)’

Cb)

Figure 2.8: An Oversampling SIH Circuit with an Integrating Feedback
Structure: (a) Basic Structure; and (b) Signal-ﬂow Graph.

22

By (2.5), the term ll-z'll decreases as the oversampling ratio increases and thus reducing
the error effect due to EC(z) from the copier. On the other hand, the increase of the over-
sampling ratio does not affect the ﬁrst term of (2.5). Apparently, by (2.5), the term (E1(z)/
AI) can be reduced signiﬁcantly if a large gain AI is used. However, to maintain the stability
of the system, the pole has to be located inside of the unit circle. Therefore, IAI-ll < l, or
O< A1 < 2, is required. Consequently, there are the needs for a large oversampling ratio to
compensate the low gain of the direct path [29] and high-order structures have been sug-
gested to reduce the error E1(z). Thus, a higher circuit complexity may be needed for such

an implementation.

2.4 Discussion

It is believed that switched-current circuits can be operated with low power supply
voltage because of small voltage swings associated with low-impedance nodes. Low-cost
standard digital processes can be used for manufacturing since precision linear capacitors
are not required. Thus, switched-current is ideally suited to mixed-signal IC’s in future low-
power/low-voltage analog signal processing applications. Since the current copiers are the
major building blocks of switched-current circuits, it is desirable to develop high-perfor-
mance current copiers. Different structures provide a current copier with different perfor-
mances, including speed, power, capacitance and supply voltage requirement. Reducing
the supply voltage is greatly desired to reduce the power consumption and cost of mixed-
signal chips. However, there is not enough study dedicated to low- voltage performance of
current copier circuits. No clear answer for the important question, such as, what sets the

limit for supply voltage of different designs can be readily found in the literatures.

23

In practice, with the realistic switches where the stray effects are not negligible for
low supply voltage, the speed performance may be degraded signiﬁcantly. Thus a thor-
oughly study of the effects and structures which minimizes the effects will be handled in
the next chapter. Several design issues on high accuracy and high speed current copiers are

investigated.

24

Chapter 3

High Performance Current Copiers

 

The performance of SI circuits is mainly determined by the current copiers they
employ. Therefore, high-performance current copiers are desired. The developed current
copiers should be simple yet high-speed and high-accuracy, and can be used for low-power/
low-voltage analog signal processing applications. This chapter addresses the design issues

and presents the developed current copiers and their performance analysis.

3.1 Performance Analysis

Current copiers suffer from two major effects which are due to the non-zero output
conductance and charge feedthrough. Several circuits have been presented in the previous
chapter to reduce the error due to the non-zero output conductance. The error effect due to
charge feedthrough can be alleviated by increasing the gate capacitance C1 [21]. An open
question is: how to make a copier with a larger gate capacitance to be operated at high cal-
ibration speed? More speciﬁcally, the calibration speed of the copier in Figure 2.2 is deter-
mined by the time constant

t=C1/gm, (3.1)

25

where gm] is the transconductance of the transistor M]. In fact, by (3.1), a slow calibration
speed will result if a large capacitance C, is employed. On the other hand, the time constant
can be kept small with the use of a large C1 if a relatively large 8m1 is chosen. The following
important issues will be addressed: what is the effect of gm, on the accuracy? and what is
the limitation on the choice of C], if a small I is allowed by charge feedthrough effect? Is
the charge injection error effect the main obstacle for high performance? and Does the

stray eﬁfects limit the calibration speed?

3.1.1 Charge-Feedthrough Error Effects

Consider the gain-error of a current copier deﬁned as

= M!)

e
dIin

(3.2)

where AI=Iom-Iin is the error current of the copier. The error current due to charge Aq

dumped by switch 82 onto the gate capacitance C1 can be written as

A
A] = Egg,“ (33)
1

By (3.2) and (3.3), the gain-error 8 can be re-written as

 

 

 

d(AI)
dlout
8 - Tim (3'4)
+
dIout
with
d(AI) Ag 1 d( Aq)
= + —— (3.5)
dIout C1(VG - V10) C1 dVG
When (3.5) was derived, the following relation

26

has been used, where B is the transconductance constant and V70 the threshold voltage of
the current-storage transistor M1. From (3.4) and (3.5), lel can be kept small if we chose C 1
and VG- V10 to be sufﬁciently large. As a result, by (3.6), gm] must be kept large. As men-
tioned, for relatively large C1 and gm] , by (3.1), the time constant 1: can be kept small. Thus,
there is no direct impact on speed 1: and accuracy 8 with the error eﬁ’ect due to the charge
feedthrough. However, as far as the power consumption is concerned, the choice of C I is

critical. More speciﬁcally, by (3.1) and (3.6), we have

_ C1(VG ‘ Vro)
210a!

 

(3.7)

As the minimal value of C ,(VG- V70) will be limited by the required accuracy given by (3.5)
or the signal-to-noise ratio (SNR) of the copier cell [30], the time constant I can be made
small only by choosing a large current 10“,, resulting in a large power consumption.
Assume that C1=2pf, VG'VT0=0-5 V, and t=2ns, by (3.7), we have IouFZSOuA. For
a supply voltage of 3.3V, the power consumption for a current copier is 0.825mW. There-
fore, the total power consumption of a 10-bit ADC which contains 20 current copiers is
approximately 16.5mW. Assume that the settling time of the copier is 71: and the residual
ampliﬁer of the ADC requires at least two calibration cycles. Thus, the sample rate of the
ADC is 1/141, or 35.7 MSamples per second (MS/s). The above assumptions are all achiev-
able. Unfortunately, existing pipelined ADC’s have not yet reached the estimated power
consumption level with this sample rate, mainly due to the effect of other time constants
which make the calibration slower than that predicted. This result reveals that charge injec-
tion is not the main obstacle for high performance, but the stray effects that limit the cali-

bration speed. The limitation on the choice of C1 from SNR requirement will be discussed

27

later.

The choice of C I is also limited by the on-resistance of the switch 82 and the supply
voltage. To make the clock-feedthrough error small, a small transistor should be used for
the switch 82. The on-resistance r32 of the switch 82 is usually larger than 101(5) due to the
small size of the switch and the low bias voltage for low supply voltage applications. This
low conductance together with the low power supply will limit the maximum current that
is available to charge the capacitance C], as the shown by equivalent circuit Figure 3.1. The
equivalent circuit is obtained from Figure 2.3 for the case VDD'VX < VST, where VX is the
voltage of node X and VST is the saturation voltage of the bias current source in Figure 2.3.
During the transient, the voltage Vx approaches VDD, forcing the transistor which imple-
ments the bias current source to operate in the triode region and resulting in a low output
impedance. The transient state occurs when [in-1014b,“ > (VDD‘VGI'VSTl/rs2- As the time
moves on, the current I D I will approach I in, making the current (Iin'IDI'Ibias) ﬂowing
through r32 to become smaller. At the end of the transient state, the circuit will go back to
the state shown in Figure 2.2. When I D I approaches Ii", in Figure 3.1, the time constant is
132=r32C1. Note that, for low supply voltage and small switch, the resistance r52 is gener-
ally large. Thus, choosing large C] will deﬁnitely cause a large time constant 1:32. It will
also take much longer transient time from the state in Figure 3.1 to that in Figure 2.2. For
example, if r52=10KQ and C I =2pf, then the time constant 1:32:20ns. This large time con-
stant may cause a longer transient response when the copier is driven into the state shown
in Figure 3.1 with a large pulse input current. The amplitude of the pulse input current

should be limited to keep the transient short.

28

charging current VDD
for capacitance C1

 

go]

 

Figure 3.1 Equivalent Circuit of the Copier for VDD-Vx< V37;

29

3.1.2 Stray Effects

When an ideal switch is employed in the basic copier, the settling time of the copier
is determined solely by the time constant 1:. However, this may not be valid when low sup-
ply voltage and non-ideal switches with relative high threshold voltages are employed.
Three switches are includes in the basic copier in Figure 2.2: S, and S3 are current-steering
switches and 82 is a sampling switch. When S, must carry out a current equals to the input
current, its area cannot be too small, and its stray capacitance cannot be ignored. On the
other hand, 82 must be kept small in order to minimize the charge injection error, and it may
have large stray resistance. As a result, both stray capacitance and resistance generates a
large time constant which will deﬁnitely affect the speed performance. The stray effects in

various copiers are analyzed as follows.

E . C | C .

Figure 3.2 plots the stray capacitances, cs, of both S, and S3 and the stray resistance,
r82, of $2 for various supply voltages. The switches are implemented with CMOS switches,
where the width of the PMOS transistor is twice that of the NMOS transistor. The width of
switches S, and S3 is chosen in such a way that the voltage drop across them is about 0.2V
when a current 300uA ﬂows through them. The widths of both NMOS and PMOS transis-
tors are 6pm. The stray capacitance can be expressed as cs: 0x(W,+W3), where Cox is the
oxide capacitance, and W, and W; are the total widths of S, and S3, respectively. (The total
width of a switch is the sum of the widths of the NMOS and the PMOS transistors.) In Fig-
ure 3.2(a), the stray capacitance increases as the supply voltage decreases, because the

switch width has to be increased to keep the capacity of the switch to carry a current

30

resistance in kg

 

 

 

 

I l T T I
X

1 02 P a
‘1‘ i
Q I d
.E- .
8 l Cs .
C
Q
3:: x
8
8'
o it
>5
(6
.‘::
U)

it
3!
l
10' r e
l l 1 l l ‘
2.2 2.4 2.6 2.3 3 32
supply voltage vdd V

(a)

 

 

 

r32

 

 

 

101 =8m1VGr

 

 

I l l l l
24 26 28 3 32

(C)

supply voltage vdd V
(b)

Figure 3.2: Performance Analysis: (a) Effect of Power Supply Voltage
on the Stray Capacitance cs; (b) on the Resistance r52; and
(c) Small Signal Linearized Model.

31

unchanged with a lower bias voltage. In Figure 3.2(b), the stray resistance r82 of the switch
82 as a function of the supply voltage, where the input voltage of the switch is assumed to
be 1.6V. The resistance r32 goes up as the supply voltage goes down, which reduces the bias
voltage of the switch. Therefore, a large time constant may result for low-voltage supply
applications.

To simplify the performance analysis, a small-signal linearized model, as shown in
Figure 3.2(c), is employed. It should be noted that large change of the transistor currents
may occur during the transient period. However, it occurs only during a very small fraction
of the entire transient period. The currents are in near steady state in most of the period.
Thus, the impact of the stray effects on the settling time can be studied from the small-sig-
nal linearized model. Solving the nodal voltage equations, one obtains a characteristics
equation

s2+(1+c,/c,)r,'1s+rs"r"=o (3.8)
where ts=csr32 is the time constant introduced by the stray effects. Since the settling speed
of system (3.8) is determined by the maximum absolute value of the real parts of the roots,
the system can have a speed equivalently equal to the one determined by the time constant
21:5/(1+cs/C1). Compared to the speed with ideal switches, the speed degradation can be
represented as
Ds=2rszgm1/( 1+C1/cs) (3.9)

where Ds is speed ratio between using ideal and CMOS switches. From Figures 3.2(a) and
3.2(b), cs may be in the same range as C, and rszgm, may be much larger than one, thus,

great speed degradation may result.

32

W

The speed performance can be improved by decreasing Ds in (3.9). This can be
achieved by reducing either r,2 or c,. Note that, for a given supply voltage, the only way to
reduce rd is to increase its width which will cause the increase of channel feedthrough error.
Therefore, it would be better to reduce c,. The stray capacitance of a switch which is in the
saturation region is much smaller than that in the linear region. More speciﬁcally, in the sat-
uration region, the stray capacitance on the drain side includes the gate-drain overlap capac-
itance and the drain-body capacitance. The capacitance is much smaller than the on-state
gate-channel capacitance of a switch driven into the linear region. However, a large drain-
source voltage drop may occur when the switch is working in the saturation region.

The speed performance for both the simple and self-regulated cascode copiers, as
shown in Figures 2.5(a) and 2.5(b), respectively, can be improved by reducing the stray
capacitance c,. Consider the simple cascode copier in Figure 2.5(a). Switch S3 is removed
and substituted by the transistor Mb, as shown in Figure 3.3(a). Two additional pairs of
switches are added to control the gates of M2 and Mb. During the calibration, M2 is turned
on and M3 is off, where both 8,, and sz are opened, and 8,2 and Sb, are closed, i.e., the
gate of M2 is connected to Vbias, while the gate of M3 is grounded. In other words, during
the calibration, both structures in Figure 3.3(a) and Figure 2.5(a) are exactly the same. The
copier cell outputs its current Iout through the transistor Mb. More speciﬁcally, during copy-
ing, M2 is turned off and Mb is switched on, i.e., both S,2 and Sb, are opened, and S,, is
grounded and sz is connected to Vbias. Similarly, S, can be also substituted by a transistor
Ma similar to Mb with its associated switches. As a result, the stray capacitance at node X,

denoted as cx, is reduced signiﬁcantly due to the substitution of both switches S, and S3.

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[in ngVSZ
<15 Vsz :L: c Clgh
C2 0
salvo: T

Figure 3.3: Simple Cascode Copiers: (a) Improved Version;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and (b) Equivalent Circuit.
Von
X
”'25 “2 b7 “3’3 b7
8
Sal l ‘2 L SM LS”
32: Sn
/ 82 l M,
H M.
vSS C11—
((1)
(C)

Figure 3.4: Regulated Cascode Copiers: (a) Improved Version;
and (b) Equivalent Circuit.

34

The ratio C,/cx is much larger than C,/cs in (3.9), and thus the speed performance can be
improved even with a large gm,rsz. Similarly, the regulated cascode copier in Figure 2.5(b)
can be modiﬁed as shown in Figure 3.4(a) with its equivalent circuit in Figure 3.4(b).
The use of the headroom transistor M2 introduces a new time constant 12. Figure
3.3(b) shows the small-signal linearized model of the circuit in Figure 3.3(a). One derives
the following characteristic equation,
3 1 2 l 1

S' +6.15 +ES+E=O (3.10)

with
a=i<1+c./C.>+r."i.’]"r.’; b=[(1+Co/Cr)+’€2'lT.’](1+C0/Cr)'112 .-
and c=(1+co/C,)T (3.11)

where T,’=cor,2. It should be noted that the two copiers have the same characteristics equa-

tion. Based on (3. 10), the speed performance can be optimized.

N |° E II I C | C .

An INFCC has its current-storage transistor working as an inverter during calibra-
tion. As shown in Figure 2.6(a), the inverter consists of the transistor M, and the bias cur-
rent source Ibia5° If the ampliﬁer of Figure 2.6(b) is used for high accuracy, the node X will
be a high impedance node. On the other hand, the gate node G of M, is also a high imped-
ance node. This means that INFCCI has two high-impedance nodes in the signal path of its
feedback loop. The capacitive loads associated with these high impedance nodes cause
large delays of the feedback signal, effecting the stability of the copier. Using the ampliﬁer
in Figure 2.6(c), the number of the high impedance nodes can be reduced to one, where
node X now becomes a low impedance node due to the low input impedance of the ampli-

ﬁer. Thus, a much better stability can be obtained by INFCCII. A small-signal equivalent

35

circuit shown in Figure 3.5 is used to analyze the stability property. Using the equivalent
circuits, where the stray effects of the switches are ignored, the following characteristic
equations are obtained

52 + mp" =0 (3.121)

52 +‘tA'ls + (11.1)" =0 (3.1211)
where tA=CAlgmA is the time constant of the ampliﬁer. The ﬁrst equation is for INFCCI
and the second for INFCCII. This implies that IFNCCI has a stability problem, while IFNC-
CII has a settling speed determined by the time constant 1A’=21Awhich is twice the time
constant of the ampliﬁer. With the use of short-channel transistors where TA’ is in the nano-
or sub-nano-second range, IFNCCII may have a settling time in the nano-second range.
However, as pointed out in Section 2.2.2, an IFNCCII suffers from a accuracy problem due
the input current of the ampliﬁer. Thus, neither INFCCI nor INFCCII can achieve the

desired speed performance.

3.1.3. Signal-to-Noise Ratio (SNR)

A SI circuit samples and holds an input current signal. Any noise currents intro-
duced with the signal or by the storage transistors undergo the same sampling process.
Noise with frequency components above the Nyquist frequency are undersampled and
therefore create replicas at base-band frequencies [31]. The major noise current sources in
the storage transistors of current copiers are thermal noise and ﬂicker noise. The analysis
and model of such noise sources in current copiers have been studied extensively in [32].
It is well understood that the input current source has also a signiﬁcant contribution to the

total noise. However, the noise caused by the input current source was not included.

36

 

 

 

 

 

 

 

 

 

 

 

 

 

+
C, i 8m(V+-V.) 1‘" 1' C4 C1"
lor=8m1VGI 3MVX
(a)
(b)
SMVX
Vx V01
@—
+ —®— I -L __
in — CA CH—
CA I: gmA(V+'V-) 1
IDI=8m1VGI
(C)
((1)

Figure 3.5. INFCC: (a) Ampliﬁer Model & (b) Calibration Model of INFCCI;
and (c) Ampliﬁer Model & ((1) Calibration Model of INFCCII.

37

In this study, the input current source is considered in the noise analysis. A pair of
current copiers with a noise current sources in, and inz, as shown in Figure 3.6, is employed.
The copier consists of two storage transistors M, and M2, and the common bias transistor
M,, with a noise current inb‘ During the hold time of the copier, while the sample and hold
noise is being output from the storage transistor, the noise source ﬂows directly to the out-
put. Since the sampled noise and the direct noise have opposite signs, the low-frequency
ﬂicker noise can be ignored, and the thermal noise dominates [32]. The variances of the

noise currents are respectively expressed as

.2 2

1 M = gmrrijgmiAf

.2 2

1 n2 = 3mkaJ-8m24f (3-13)

, 2
r... = gmrrijgmiAf

where mm is a process-dependent constant which in practice ranges from 1 to 2.5, k is the
Boltzmann constant, T- is the absolute temperature, Af=gm,/(4C) is the noise bandwidth,
and gm,, gmz, and gmb are the transconductance of M, , M2, and M,,, respectively. Note that
the transconductances are

gm, = 2mg", = 2m,and gm, = 2 (3,1,, (3.14)
where [3,, [32, and [3,, are the transconductance constants of M,, M2, and M,,. Since these

noise currents are uncorrelated, the variance of the total noise is the sum of the variances in

(3.13), i.e.,
3’ 2 2 2
l n = gmrhijle +8m2+8mblAf= 3m,h(ij/C)§gmb (3-15)
where
2
8
g = (1 + £12 ., Mjﬂg
8m] gm] gmb

38

 

 

 

 

1b
I x rm
AVG] D1 VG, \
_| Q
l 2
c:: 'M" ::C
Vss

Figure 3.6: A Pair of Basic Copiers with Noise Current Sources.

39

Apparently, the maximum noise variance occurs when the ﬁ-value is maximum. Let
m,=ZID,/I,,-1 be the modulation index and u=B,/[3,, be the normalized transconductance
constant. If we assume that B,=B2 and Ib=I D ,+I Dz, both drain currents are

ID, = (1+m,-)I,,/2, and IDZ=(1-m,-)Ib/2 (3.16)

Therefore, by (3.14)-(3.16), we have

§=t;(m,,u)=[u(1+m,)+ ,/u(1— m3) + /2u(1+ m,)] / 2 (3.17)

Figure 3.7(a) plots the values of E for m,- ranged from 0 to l and 0:0.25, 2, and 4.
Results show that, for small m,, the noise increases as m,- increase, due to the increase of
I D ,, causing a larger noise bandwidth. Let mm,“ denote the modulation index such that
§(mim,n,u) is the maximum value of §(m,-,u). The noise decreases when m,- > mm“, due
to the reduction of I 02- Figure 3.7(b) shows that the maximum values §(mimu,u) for all
u’s ranged from 0 to 4 are located between 0.785 and 0.9. It should be noted that, in Figure
3.7(a), the ﬁ-value decreases as 1) decreases. However, it does not imply that the total noise
level is low for a small 1), but the noise generated from the bias transistor dominates.

For a sinusoidal with peak amplitude m,I,,/2, the RMS value is milb/ J8 , and the
variance of the signal is

i 2 =m,.21,,2/8 (3.18)

S

Therefore, with Ib/Bb=(IVGSbl-IVT,,I)2, the SNR can be expressed as

2 2
mi (IVGSbI " IVTbI)

 

SNR = 10 logwiif/izn] = 10 log“, 64 (3.19)
ﬁmghﬂjﬂmpv)
where the worst-case SNR can be obtained by substituting m,=mm,,. With the time con-

stant “WC/gm, and gm,= , I2u(l + m,) Ib/(IVGSbl-IVTbI), the SNR in (3.19) can be expressed

40

 

 

 

 

 

 

 

6 0:4
s~ .
4.
72— =1
l nr 3. ..
2- -(
,. u=.25 ,
o l l l I 1 l l l l
o 0.1 02 0,3 0.4 0.5 0.6 0.7 03 as 1
mi
(a)
0.9
one»
036-
mim

084*

0.82

0.8 -

 

0.78

 

 

 

(b)

3.5

Figure 3.7: Basic Copier: (a) Noise as a Function of Modulation Index; and
(b) Modulation Index for Maximum Noise as a Function of t).

41

 

 

 

tVDDIb
SNR = 10 log,0 i1(m,, 1)) (3.20)
16J2
IVGSbI - IVTbI
where n(m,, 1)) = V f(m,, 1)) and (3.21)
DD
2
«mi: D) =

mi
J21)+b,/l+m,+u./1—m,

The function n(m,-,1)) is referred to as a structure function. Note that different c0pi-

ers have different structure functions. The structure functions are derived as follows.

B O C I C 0
Consider the basic current copier in Figure 3.6, the bias transistor M,, works in sat-
uration if VDD-VX > VDD-Vb-IVTbI. To make both transistors M, and M2 to operate in sat-

uration, it requires

VXmin > VXmax ' VTia and VXmin > VXmax ' VT]

where VT, is the threshold voltage of M, , and the maximum and minimum values of VX are

1 + m-
VXmax = J 21) I(ll/ass] "IVTbI)+ V71 (3-22)

1 — m,
VXmin = TQVGSbl " IVTbI) + VT] (3.23)

Note that VXmax and VXm,n are the voltages when the calibrated storage transistor has the

 

and

maximum and minimum drain currents, respectively. Since VDD=Vb+lVGSbL we obtain
VGSbI'IVTbI S VDD I fB(m,-,1))

where

42

 

 

fB(m,-,1))=l+2 j(1+m,)/2u - J(l—m,)/20 (3.24)

Thus, the structure function is expressed as

nB(m,-,1)) = f(m,-,1))/fB(m,-,1)). (3.25)
Figure 3.8(a) plots the structure function of the basic current copier in Figure 3.6,
where the u-value is varied from 0 to 4 for m,=0.4, 0.6, and 0.8. Figure 3.8(b) shows the
optimum device parameter values 1) for maximum nB(m,-,1)) with m,- ranged between 0.4

and 0.8.

Cascodeﬁurrenmnnier,
Figure 3.9(a) shows the cascode copiers which are used for noise analysis. Simi-
larly, both M11 and M21 are operated in saturation when
Vbl ‘ VGSlZmax > VXmax ' VTll
and the condition for both M12 and M22 operated in saturation is
VXmin ' (Vbi ' VGS12min)> VGSlZmin ' VT12
Similarly, the conditions for both bias transistor in saturation are
”0332' + Vb3 ‘ VXmax > IVGs32' ' IV'r32|
VDD ' 'Vos32l ' Vb3 > I"(3831' ' IVT31I
If we assume that both M,, nd M,2 have the same size, then VGSlZmax=VGSIImax=VXmaX9

and VGS,2min=VGS, lmin=VXmin' Therefore, we obtain,

IVGSbI'IVTbI = IVGs3ll-IVT3II S VDD / fC(m,~,1))

where

 

 

fC(m,-,u) = 2 + 3 J0 + m,)/21) - J0 — m,)/21) (3.26)

Thus, the structure function for the cascode current copier,

43

 

nB(mi2‘D)

 

 

 

 

 

0.025 -
0m _ =0.4 ,
0.01s - N
0010 015 1 115 2 2 5 3 35 4
1)
(a)
12s . .
1.2 - .1
1.15 )-
1.1
'00 1.05 - 4
1 .
035 ~ «
0.9 '- .
085 I‘ J

 

 

 

(b)

Figure 3.8: Structure Functions for Basic Copiers: (a) nB(m,-,1)); and
(b) Optimum Device Parameter Values 00.

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3.9: Cascode Copier: (a) Schematic; (b) 11C(m,-,1)); and (c) Optimum no.

45

nC(m,-,1)) = f(m,-,1))/fC(m,-,1)). (3.27)
Figure 3.9(b) plots the structure functions of the cascode copier, and Figure 3.9(c) shows
the optimum device parameter values 1).
Note that, by (3.21), for a given design constraint on both speed and power, the cur-
rent copier who has higher structure function value will achieves larger SNR. This implies
that, for a given design constraint on both SNR and speed, the current copier which has the

higher structure function value will require less power.

N l' E II I C l C .

Figure 3.10(a) shows the copiers for noise analysis. In this structure, a new noise
source is introduced by the additional feedback ampliﬁer, where the noise source is mod-
eled by adding an input current source in,- and an input voltage source vm, as shown. How-
ever, the new noise source is not of signiﬁcance to the total noise. More speciﬁcally, the
noise voltage source causes the voltage on X to be deviated from the expected value me

by vni. Thus, the variance of the noise current caused by this voltage source is go2 um.2 , where
g0 is the equivalent conductance between X and ground. Since g0 is usually very small, the
noise can then be ignored. On the other hand, it has been shown that the noise caused by
the input noise current is also very small compared to the total noise [32]. Thus, the noise
caused by the ampliﬁer is ignored in this discussion. Similarly, the conditions for M,, M2,
and M,, in saturation are
mex - VT, < VX, VGZmax - VT, < Vx, and VDD-Vx > VDD-Vb-IVTbI

where V5, and V02 are the gate voltage of both M, and M2, respectively. Therefore, we

obtain,

46

TIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A
im
Ib Vni
ID! X 102 V
,_/ V61 52
C . |_0‘
C I: 1'" '"2 :C
Vss
(a)
003
0.74)
Q07-
mi=0.8 W
om.
07»
0“. -1 Do
-_-0.6 Oﬂr
“I’M on
m- 054.
=0.4
mrN 0w
”'0051152253354 abmogofssosojs
i
(b) (C)

Figure 3.10: Negative-Feedback Copier: (a) Schematic; (b) nN(m,-,1));

and (0) Optimum no.

47

 

 

IVGSbI'IVTbI S VDD I fN(m,-,1))

where

 

fN(m,-,1)) = l + J(1 + m,)/ 21) (3.28)
Thus, the structure function for the negative-feedback current copier,
nN(m,-,u = f(m,-,u)/fN(m,-,u). (3.29)
Figure 3.10(b) plots the structure functions of INFCC, Figure 3.10(c) shows the optimum

device parameter values 1).

3.1.4. Discussion

According to the simulation results for the structure functions plotted in Figure
3.8(a), 3.9(b) and 3.10(a), we have nN(m,~,1)) > nB(m,,1)) > 11C(m,-,1)), for the same m,- and 1).
This implies that the negative-feedback current copier has the largest SNR. This also
implies that, for a given design constraint on both SNR and speed, the current copier which
has the higher structure function value will require less power. In other words, the negative-
feedback current copier requires the least power to achieve the same SNR and speed com-
paring with the other two copiers.

Figure 3.11(a) plots the power consumptions for the three copiers, where 1:=lns
m,=0.8 were simulated, and Pb, PC, and Pf denote the power of the basic, cascode, and the
negative-feedback copiers, respectively. Since the cascode copier has the least structure
function value, it requires the largest power. Figure 3.11(b) plots the capacitances required
for the three copiers to achieve a SNR of 65dB, where t=1ns m,~=0.8 were simulated, and
Cb, CC, and Cfdenote the capacitance required for the basic, cascode, and the negative-feed-

back copiers, respectively. Results show that the negative-feedback copier requires the least

48

 

Power (Watt)

 

 

 

 

 

 

 

 

 

 

(I5 2 2.5 3 3.5 4 4.5 5

VDD (V011)
(b)

Figure 3.11: Performance Comparisons: (a) Power; and (b) Capacitance.

49

capacitance. For the same supply voltage, the capacitance required by the negative-feed-
back copier is nearly 5.6 times less than that by the cascode copier. The use of large capac-
itance also implies the need of more chip area. In other words, the negative-feedback copier
takes much less chip area. In addition, designing sample switches to drive such large capac-
itance will be a problem. Thus, the use of small capacitance in the negative-feedback copier

reveals the best candidate for low-voltage/high-performance operation.

3.2 Alternative Negative Feedback Current Copiers

As discussed in Section 2.2.2, in an INFCC, Inverter Negative Feedback Current
Copier, the current-storage transistor, together with the input current source, constitutes an
inverter, the copier takes a positive-gain ampliﬁer to form a negative feedback loop. To fur-
ther simplify the structure while improving speed performance, this section presents an al-
ternative negative feedback structure which is comprised of a source follower and a simple
negative-gain ampliﬁer [24]. Such current copiers are referred to as Follower Negative

Feedback Current Copiers, or FNFCCs.

3.2.1 Structure and Operation

Figure 3.12(a) shows the schematic circuit diagram of the FNFCC. The current-
storage transistor M, works as a source follower and its source node connected to the I/O
node X. Note that node X has a low impedance, during calibration, even if an ampliﬁer with
a high input impedance is used. Thus, high speed and high accuracy can be obtained simul-
taneously. Since the body effect of M, may increase the transconductance g0,, the body of

M, is connected to its source. Two negative-gain ampliﬁers, as shown in Figure 3.12(b) and

50

 

 

 

 

 

 

 

 

 

GND
(2!)
lollies p_vbias
x V”
—l v... X
(b) (c)
VX _ S1 G] V C1 VG I
[or]- H ID! ‘6
I Iin '
In I CA The TC“ Blb
i SnXVGer) gmAVX igrrIVEI’VX') -
(d) (C)

Figure 3.12: FNFCCs: (a) Schematic; (b) CMOS Ampliﬁer; (c) BiCMOS Ampliﬁer;
(d) Equivalent Circuit for FNFCCI; and (e) for FNCCII.

51

Figure 3.12(c), are employed in this implementation. The BiCMOS ampliﬁer is attractive
for its large bandwidth and high voltage-gain. For simplicity of this discussion, the FNFCC
using the CMOS ampliﬁer is referred to as FNFCCI, while the one with BiCMOS ampliﬁer

as FNFCCII.

Similar to (2.2), the variation of the error current AIg0 can be expressed as

 

 

 

g0, + g, 7 (3.301)
A + 1
A180 z — gm“ ) AI,"
801 + gb + 80/4
_g,,.1(A + 1) 1338",, (3.3011)

where [3,, is the current gain of the bipolar transistor in Figure 3.12(c). From (2.41) and
(3.301), both FNFCCI and INFCCI have the same accuracy. In (3.3011) for the NFCCII, the
ﬁrst term can be ignored due to the large voltage ampliﬁcation of a bipolar inverter. The
second term reﬂects the fact that the base current of the bipolar transistor in Figure 3.12(c)
depends on the input current. Typically, we have gm,/goA=50 and 03:100. Thus, as in
(3.3011), the accuracy can be 115000, i.e. 2x104, which is nearly a 12-bit accuracy if the
copier is used to design an ADC.

The characteristic equations, without considering the stray effects of the switches
for both FNFCCI and FNFCCII, are derived as follows, where the small-signal equivalent

circuits shown in Figures 3.12(d) and 3.12(e) are employed

—1
‘s+ (1,1,) _ o (3.311)

_ -l -1
s2+(1+BB l)1, s+ (r113) (3-3111)

2 ._
s +1,

where 1:B=(r,,e/C,,e)/BB is the time constant of the bipolar ampliﬁer. (3.31) shows that both

52

FNFCCI and FNFCCII have short settling time.

As the speed predicted by (3.31) is quite high, the limitations determined by the
stray effects of the switches may be approached. Thus, it is necessary to include the effects
of the switches. To obtain a model which is simple, can accurately predict the settling
behavior and give guidance on the choices of the parameters for the ampliﬁer, the storage-

transistor and the switches, we need to select appropriate time constants.

3.2.2 Stray Effects

For the FNFCC, the effect of the stray capacitance cs is alleviated due to the fact
that they are in parallel with the input capacitance of the feedback ampliﬁer. The time con-
stant associated with the input capacitance can be written as

(3.321)
(CA + CslghlA

1,," =
(Cbe + cs)(rbe/BB)

(3.3211)
This express shows that the increase of IA’ due to cs can be alleviated by an increase of the
transconductance gmA. The stray resistance r32 of the switch 82 effects the settling time
through the time constant
15' = ’szCo (3.33)

where C0 is the stray capacitance at the output of the ampliﬁer. For the CMOS ampliﬁer,
this capacitance includes the drain-to-gate, and drain-to body capacitances of the transistors
at the output of the ampliﬁer. The gate capacitance of the switch 82 makes also a contribu-
tion to the capacitance. For the BiCMOS ampliﬁer, the capacitance will be mainly deter-

mined by the collector-base and collector-body capacitances of the bipolar transistor.

53

Taking the time constant of the current-storage transistor 1 into consideration, the
small-signal linearized equivalent circuit for both FNFCCI and FNFCCII are illustrated in
Figure 3.13. From the equivalent circuits, both have the same characteristics equation as
given in (3. 10), but the coefﬁcients for the FNFCCI are expressed as
a=[1+cOIC+co/(CA+CS)]"r,’
b=[1+cO/C+co/(CA+CS)][l+gm,co/(gmAC)]'ITA” (3.341)
c=[l+gm,col(gmAC)]T

and for the FNFCCH
a=11+co/C+co/(cbe+c,)]"r,’
b=[1+c0/C+c0/(Cbe+Cs)][1+colC+rbegm,co/C]"T A” (3.3411)
c=[l+co/C+rbegm,co/C]‘C

Due to the stray effects of the current-steering switches, the stray capacitance at the
input of the feedback ampliﬁer is increased, from C A to C A+cs for the FNFCCI and from
Cbe to C,,¢+cs for the FNFCCH. To keep the time constant 1: A” unchanged, the transconduc-
tance gm, or rbe'l has to be increased accordingly. This asks for an increase of the device
current. The increase of the device current will be accompanied by a number of side effects,
including higher power consumption, larger noise and lower ampliﬁcation of the ampliﬁer.
Thus, some other possibility to reduce the stray effects will be desired.

One way to achieve this is to move the switch from node X to the drain side of the
current-storage transistors, as shown in Figure 3.14, where switches S,,, with 1 S i S N,
control the current. This method can be useful when a number of current-storage transistors
share the same feedback ampliﬁer, as it is often the case for a switched current integrator

and residue ampliﬁer. The current can be transferred from one transistor to the others by

54

 

 

 

 

 

 

 

 

 

 

v" 1C1 VOTIE—l v0
1 l ;_I
gm1(vG'Vx) ——- 1A=gmAVx ——
—_CA +cs ——C-o
#
(a)
Vx C vs r52 vo
. 1 1—1:
gMKVGWX) __ 'be ic1=l3iiih ——
Chg-c, CO
L
(b)

Figure 3.13: Equivalent Circuits: (a) FNFCCI; and (b) FMFCCII.

V01)

1
511 /82, SN!
S2
312} D 522) 32 D Sm) S2 D
B I B I B
OIEI‘M, G "sz .0000. G *MN

1m X
+§~

) $3
Ibias GEE] Sb

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3.14: Stray Effect Reduction.

55

control the state 8,, and 8,2, to implement different functions. As the switches Si, is sepa-
rated from node x by the current storage transistors, their stray capacitance will have no
effect on the stability of the feedback loop. The settling behavior can be analyzed using
model (3.34) with cs set to zero. An input switch 8,, is needed to control the input current
1,“. The design of the switch and the way how to output current from the current-storage

transistors will be discussed in Chapter 4.

3.3 Simulation Results

The accuracy and settling performance of a FNFCCII and the effects of the current-
sample and current-steering switches on the settling behavior are studied by simulations.
The simulations verify the high accuracy and high speed of a FNFCCII. They show also
large effects of the switches on the settling time and ampliﬁer design.

The simulation is conducted using two identical copiers, as shown in Figure 3.15(a),
where one is used as the operational copier (o-copier), and the other as the calibration
copier (c-copier). The I0 and Ic are the output currents of the o-copier and the input current
of the c-copier, respectively. This conﬁguration implies that the current held in one copier
is transferred to the other one. Therefore, the impact of the stray effects of both, the c-copier
and the o-copier, are included in the simulation. The input current I,n is introduced to gen-
erate a pulse current for settling time simulation. The circuit of Figure 3.15(b) is used to
implement the conﬁguration of Figure 3.15(a). It contains two current-storage transistors
M, and M2, a feedback ampliﬁer with transistors Q, and M3 and some level shifters.
Diodes D, and D2 consists of a level shifter. It generates a proper potential for the node x.

The level shifter at the output of the ampliﬁer ensures that the output voltage of the ampli-

56

 

 

 

 

O-copier

 

 

 

 

 

 

 

C-copier

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Level
Shifter

 

 

 

 

 

 

 

 

 

 

(b)

Figure 3.15: Simulated Circuits: (a) Block Diagram; and (b) Schematic.

57

ﬁer be in the range, such that the ampliﬁer works properly. This shifter can be implemented
using MOS capacitors and switches [34], where the detailed implementation will be
described in Chapter 5. The supply voltage is chosen as 3.3V due to the high threshold volt-
ages, about 0.8673V for NMOS and -0.9506V for PMOS. In the simulations, transistor M2

is assumed to be the operation, while M, the calibration transistor.

3.3.1 Speed Limitation

In order to study the speed limitation, the setup is simulated by assuming all with
ideal switches. The closed switches, including S,,, 8,2 and 82,, are replaced by a wire and
the opened switches 822 are simply removed. The impulse amplitude of the input current
source I,n is set to 1011A. The capacitance C and the bias current of the transistor Q, are
chosen so that the best speed can be reached. The simulated results is represented by the
‘o’-cover shown in Figure 3.16(a). The settling time is deﬁned as the time space from the
onset of the impulse input current to the time for the drain current of the calibration tran-
sistor M, to settle within 0.1% of the impulse amplitude. As discussed in Section 2.2.2, the
speed will be limited by the feedback ampliﬁer. The settling time is expressed as a function
of the current in the calibration transistor M,, because the current affects the transconduc-
tance.

The settling time of a current c0pier may be affected by the sample switch, current-
steering switches, and power supply voltage employed by the copier. The following discus-
sion describes their effects on the settling behavior.

W To evaluate the effect of the sample switch, the switches S ,2

and 822 are replaced by MOS transistors in this simulation, where the channel length of the

58

 

 

 

 

 

 

 

 

 

 

 

 

50- "E -
X
45- " it ~
its 3" WIL==3|l/2].l.
40- a“ a,
* )1! X x T * )K * * x X
a; 35: -
5
0 30" x —1
3° .. 2"."
u-q .- ¥ * * * * _
a 20 3‘ it x 3,, 3‘ ’6 x a“ a“ x a, an N‘ 3‘
I}; 15" x .1
”‘ r a 10111211
10-x): a"matters”‘mmmmmmmmmm’(m.251-112
_ " at "‘ ’1‘ at )K x in *‘ _ 11
5 °°666i8§saz§§sst§i§aua 3511/21:
foo réo 260 aéo as. aéo 460 réo 500 550
Input current (11A) ‘o’:ideal sample switch; ‘*’:MOS switches
(a)
V01 rs2 V0 4 4 4 ﬂ
o—E ‘2
3'5” " *: with ideal S11 and 8,2
:: C0 —— OUtpUt LL 3» X2 With MOS S“ and 812
current Dr +: with ideal 5,, and 5,2
.1. of the 5 ’5 but M08 82, and 822
:- ampliﬁer U 2. '
1.5» x
(b) 1» I X
05* . +
°o 5 1‘0 I5 20 2‘5 3‘0 3‘5 40
Winum
(C)
Figure 3.16: Effects of Sample Switch: (a) Settling Time; (b) Equivalent Circuit;
and (c) Optimal Capacitance.

59

switch transistor is chosen as 211m, i.e., the minimum length allowed by the technology, and
various channel widths are chosen. The gate capacitances are varied to reach the best speed
for a given switch width. The results for the settling times are represented by the ‘*’-curves
in Figure 3.16(a). Two changes of the settling behavior can be seen: a rapid increase of the
settling time and an increase of the dependence of the settling time on the transistor current
as the switch size goes down.

Recall that a large switch has a large gate capacitance and a small on resistance, and
a small switch has a small gate capacitance and a large on—state resistance. The settling time
becomes worse for a small switch reveals simply that the stray resistance has a severer
impact than the stray capacitance. As shown in Figure 3.16(b), the stray resistance r52 and
the stray output capacitance C0 of the ampliﬁer generates a R-C link between the output
node Vo of the ampliﬁer and the gate node V6, of the calibrating current-storage transistor.
The time constant rszCo becomes large as the switch size goes down, leading to a large
delay through the link. The settling time increases.

For the circuit of Figure 3.15, the stray capacitance C0 is mainly the collector-to-
substrate and the collector-to-base capacitances of the bipolar transistor Q, . A small tran-
sistor should be used to keep these capacitances small. On the other hand, NMOS transistor
should be chosen for the switch to reduce the stray resistance r52. This is the reason for
choosing PMOS current-storage transistors in Figure 3.15. It allows low operating gate
potentials VG] and V62, so that the stray-resistance of the NMOS switches 82, and 822 can
be reduced as much as possible.

The optimal gate capacitance for the best speed under a given switch width is shown

in Figure 3.16(c). From the illustration, the capacitance decreases with the increase of the

60

switch width. Since a large gate capacitance and a small switch stands for a small charge-
injection error, with the decrease of the switch width, the accuracy of the copiers will
increase. On the other side, the speed of the copier decreases. Therefore, there is a trade-off
between speed and accuracy. However, for the circuit of Figure 3.15, the switch should not
go down below 511, to avoid strong dependence of the settling time on the transistor current.

Wins To control the current of the storage-transistors,
switches S,, and 82, have to be used. Their introduction will cause another degradation of
the settling time due to their stray resistances r,,, and 5,2, and stray capacitances C3,, and
Cs”. Since they have to carry a current equal to that of the current-storage transistor, their
size cannot be small. As shown in Figure 3.17(a), a R—C link, consisting of rs,, and
(C,,,+C,,2)/2 between node S, and x is introduced. The effect of the stray capacitance
(C,,,+C,,2)/2 can be reduced by increasing the bias current of the bipolar transistor, which
increases the equivalent capacitance Cbe and reduces the equivalent resistance rbe. How-
ever, the effect cannot be removed completely because of the stray base resistance rb of the
transistor Q, , the stray resistance rd of the level-shifting diodes and the stray resistance r,,,
of the switch itself. Therefore, there is still some degradation of the settling time even if the
transistor current is increased. The simulated settling times, with switches S,, and S22 also
replaced by NMOS transistors and the bias current for Q, increased to 1.4mA, are shown
in Figure 3.17(b). The optimal capacitance for the best speed is represented by the ‘x’-curve
in Figure 3.16(c). Compared with the results of Figure 3.16(a), where the bias current for
Q, is only 3500A, some degradation can still be seen.

The increase of the bias current of Q, will introduce side effects, including increase

of the power consumption, reduction of the ampliﬁcation and enhancement of the noise of

61

Settling time (ns)

 

 

 

 

 

 

    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S2
'SCSII .5C312:_ __ Cb¢:: Tb:
'5(Cs +C1112) CGM3+CGM4
(a)
50 x t Y
45» x x -1
40" X .4
35., X WII4=4W2p _
301- X
x x x x x x x x 1
x x X
25" X x x X X x -4
20b : x x x x x 811/211, -
's *.::a::xxxx::x:xXxxx-
10~++++ xx§§§ xX§xﬁﬁ§§§_25ul2u
5% 1' + + + + + + + + + + +_ + + + + + - 3511/2“.
906 $0 200 aéo ar‘ro eée 400 ace 5a. 560
Input current (11A) ‘+’:ideal sample switch; ‘x’:MOS switches
(b)
V131)
1b
Vb I M M3
b vo
X
S12 V 1131 I132
O G] M1 M2 LCVCI
.1... Shifter
C —'- S11 S21
v55 _.._ C0
. :l—
(C)

Figure 3.17: Current-Storage Switch Effects: (a) Equivalent Circuit;
(b) Settling time; and (c) Current Cell Pair.

62

the ampliﬁer. Thus, the bias current should be kept as small as possible. This forces us to
look for other approaches for implementing the switches S,, and 8,2, or to ﬁnd other ways
to switch the current in the storage transistors. A very effective method to achieve this is to
move the switches S,, and S2, from the source side to the drain side of the current-storage
transistors, as shown in Figure 3.17(c). This replacement can completely remove the effect
of the switch. Simulation results, with all the switches implemented using MOS transistors
and a bias current of 35011A for Q,, show no noticeable deviation of the settling time from
the one given in Figure 3.16(a). A MOS switch working in the saturation region can be used
to supply the input and take the output current.

mm Figure 3.18(a) shows the Pspice simulation results of the
settling time of the circuit of Figure 3.17(c) for various supply voltages. The width of the
sample switch is 611m. The simulation result shows that the settling time increases signiﬁ-
cantly as the supply voltage goes down. This is due the increase of r82, which causes 1:52

becoming large.

3.3.2 Error Currents

Figure 3.18(b) illustrates the accuracy of the copier. The accuracy is calculated with
the following process: (1) set the input current I,n to zero, (2) simulate the copier in the ﬁg-
uration of Figure 3.17(c) with one copier in operation and the other in saturation; and (3)
exchange the copier states. The difference of the currents obtained in the steady-state at
Steps (2) and (3) is deﬁned as the error current. The error current exists because of the
effects due to charge-feedthrough and non-zero output conductance. The copier current is

varied by changing the initial on the gate capacitance of the operation copier in the step (2).

63

Settling Time in Nanosecond

Error Current 11A)

32 T l I T

 

 

 

 

 

 

 

H I
it
30 -
26 -
26 -
24 - x
22 '-
R
20 -
I
10 -
it at
16 - in
at )It
iii
14 - X x
J; l l J l l
2.2 2.4 2.6 2.8 3 3.2
Supply Voltage in Volt
(a)
0.2 I I I I I I T I
I
0.15 - * .
R
at
0-1 ' 9 “' Vdd=2-5V “ ‘
:1: --- Vdd=3.3V at
X
0.05 - 4
it
o
" o
o
x o
in o .
0 It 0 O o
K
it o 0 o
O“ O
O O 0*
_005 L l I L l I l l
1 00 1 50 200 250 300 350 400 450
Copier ﬁgment (11A)

Figure 3.18: (a) Settling Time; and (b) Error Currents.

 

The copier has a smaller error current for Vdd=2.5V because the charge injection error is

reduced.

3.4. Discussion

Based on the analysis of the charge-injection error, this chapter outlines the design
trade-offs among accuracy, speed performance, and power consumption and addresses the
stray effect of the switches which may degrade the speed performance of the copiers. It has
been shown that the stray effects can be alleviated by reducing the stray capacitance of the
current-steering switches, or by separating the large current-steering switches from the
small current-sample switches, for the copier to achieve high speed operation.

The proposed FNFCC structure enhances the speed performance of INFCCI and
resolves the accuracy problem in INFCCH. The proposed FNFCC can achieve a very high
accuracy and speed by using BiCMOS technology. The simulation results have veriﬁed the
operation of the proposed copiers and demonstrated that a very high accuracy and speed of
FNFCCII can be attained even with a low supply voltage. Since the supply voltage is
mainly determined by the switch performance to keep a short setting time, the supply volt-
age in the proposed copier can be reduced to 1.5V without affecting its speed performance
if the threshold voltage is reduced to nearly 0.5V.

The results of this study have demonstrated that, with the proposed high-perfor-
mance current copiers, the switched-current circuit techniques become promising. The de-
velopment of the next-generation data acquisition and conversion circuits using these

copiers will be discussed in Chapters 4 and 5.

65

Chapter 4

Sample and Hold (SIH) Circuits

 

This chapter presents the design of a simple high-performance SI V-I converter
with the sample/hold (SIH) function [35,36] and an oversampled high-linear SI sample
and hold (SIH) circuit using current copiers [37-39]. A V-I converter is often needed at the
"front end" of some current-mode circuits to provide interface with a voltage-mode sys-
tem. The proposed V-I converter combines both V-I conversion and SIH function to sim-
plify the circuit. Concerns are paid to high-speed operation and to reducing distortion due
to nonlinear properties of MOS devices.

The oversampled SIH circuit achieves a very high linearity. Using a digital technol-
ogy, where no linear capacitor is available, the linearity of a SIH circuit will be degraded
since a nonlinear capacitance has to be used for signal storage. This is true for both the tra-
ditional voltage-mode and the current-mode SIH circuits. Using the SI technique, integra-
tors having a simple structure can be designed, which helps to reduce the overall
complexity of an oversampled SIH circuit. This study adopts a feed-forward approach to
further simplify the operation to reduce the order of integrations needed to meet a linearity

speciﬁcation.

66

4.1. A V-I Converter with SIH Function

A number of transconductor designs have been proposed and implemented [40].
However, a simple high-linear V—I converter can be realized using a resistor and a current
copier, as shown in Figure 4.1, where the circuit has the advantage that it incorporates the
S/H function. The circuit is operated in two modes: sampling/conversion mode and holding
mode. During the sampling period, S, is closed and $5 is opened, the copier is in its
calibration state. Note that if the copier has a very small input impedance during calibration,
its input/output node "G", serving as a virtual ground, has a potential that is virtually not
affected by the input current 1,. Therefore, the relationship between the variations of I, and
V,- will be solely determined by the resistor R and thus the circuit achieves high-linear
conversion. On the other hand, during the holding period, switches 85 and S, are
respectively turned on and off to deliver the held current to the load. The choice of the
current copier is important for high-performance V-I converter.

Numerous current copiers have been presented and discussed in Chapters 2 and 3.
However, in addition to simple structure and high-speed operation, the current copiers must
have a very low input impedance during calibration and can be operated under low power
supply. Therefore, this section presents an alternative copier, differential current-storage
unit, using negative feedback to boost its transconductance. To demonstrate the high-speed
operation, the settling behavior of the V-I converter is analyzed, where the non-ideality of
the switches are taken into consideration and the switches are modeled by the small-signal
linearized circuit model [21]. The analysis provides a guideline for selecting appropriate

device parameters.

67

 

 

 

 

 

 

Figure 4.1: Proposed Current-Copier—Based V-I Converter with SIH Function.

68

4.1.1 Structure and Operation

Figure 4.2 illustrates the proposed current—copier-based V-I converter. The current
copier is comprised of a diﬂerential current-storage unit and a feedback ampliﬁer. PMOS
transistors M, , M2, and M5 constitute the differential current-storage unit, where the
capacitance C memorizes the voltage needed by M2 to support the input current ﬂowing
through M,. The capacitor C is connected between the gate and source nodes of M2, while
the drain node of M2 is grounded. The circuit is operated as follows. When switches S,, 82,
and 83 are closed, and S4 and 85 are opened, referred to as the sampling period, the output
tracks the input. When S,, S2, and 8;, are opened, referred to as the holding period, the
converted current is sampled and held by the current copier. During the holding period, the
sampled current is read by turning on switch 85. The ampliﬁer is used to accurately transfer
the sampled current to a current copier load by turning on switch S4.

During the sampling period, the input node, X, serves as a virtual ground. The input

current variation A],- can be expressed in term of the input voltage variation AV,- as

A1 AV,
i- R-I-r

 

(4.1)

where the small signal input impedance, r, of the copier is

l
r =
AnggMZ/(ng "' 8M2)

 

(4.2)

gM, (8M2) is the transconductance of M, (M2), and A is the voltage gain of the feedback
ampliﬁer. Since the sum of both drain currents, ID, and 1m, of the transistors M, and M2,
is constant, increasing 1D,, equivalent to the input current, results in decreasing 1,32. Thus,
by (4.1) and (4.2), the ﬁrst-order dependence of the transconductance on the input current

can be cancelled off. Equation (4.1) also implies that the linearity of the V-I conversion is

69

 

! VDD=3 .3V
M5

e—l _1 A -'-
| 33
FE:

/ S]

x Ii 32

.. 1, >1 ‘1 C.
Vi Q LOAD (a Current Copier)

Figure 4.2: Schematic Circuit Diagram of the Propose V-I Converter.

 

 

 

 

 

 

 

 

 

70

increased with a larger resistance. In practice however, a larger resistance causes an
increase of the feedback loop gain and the time constant associated with node X which
decrease the loop stability and result in a longer settling time. A larger resistance also needs
a larger input voltage swing to achieve the same range of dynamic output currents. This
leads to a signiﬁcant design trade-off among linearity, dynamic range, and conversion
speed.

For high-frequency applications, large distortion may occur due to the modulation
of the sample time through the input signal. To keep the distortion small it is essential that
the potential at both ends of the sampling switch 82 be only little effected by the input. Note
that the potential of 82 is determined by the gate voltage of M2 and the variation Ang can

be expressed as a function of the input voltage variation AV,:

AV-

AV = ‘ 43
82 R8M18M2/(8M1+8M2) ( ' )

 

Apparently, choosing large transconductances, gM, and gm, can reduce the variation
Ang. Since the variation, AV,/R, is determined by the dynamic range given in a design
speciﬁcation, sufﬁciently large transconductances are then selected for both M, and M2 to
reduce the variation AVgZ. Note that the use of large transconductance gM2 does not imply
the increase in the charge injection error, due to 82, because the error depends on the time
constant gMz‘lC [21], not on gM2 only. Thus, the charge injection error can still be kept

reasonably small even though large gm is chosen.

71

4.1.2 Speed Limitations

For high—speed applications, fast settling time of the converter is needed. Settling
time depends on the bandwidth of the CMOS inverter and the time constant gMZ'lC, and it
may also be affected by the use of practical switches which have non-zero on-resistances
and gate capacitances. The following subsection discusses the settling behavior of the
proposed V-I converter and describes the design principles of choosing the device
parameters for achieving fast settling time.

To study the settling behavior of the proposed converter, the non-ideal switches are
modeled by the small-signal linearized equivalent circuit, as shown in Figure 4.3(a) [21],
where rsk and Csk are respectively the on-resistance and the half of the on—gate—capacitance
of the switch S,,. Based on the switch model, Figure 4.3(b) illustrates the equivalent circuit
of the proposed V-I converter during the sampling period. Based on the node-voltage
equations of the equivalent circuit, we obtain a second order open-loop transfer function

that can be used to estimate the main poles of the V-I converter,

INS) _ (1 +1112, g2S)(1 “711344.134”
If(S) 0105(1 + 01,5)

 

H(S) = (4.4)

where 1:3,, denotes the time constant generated by ra (or ga) and Ch; gM34=gM3+gM4 and
ng34=ng3+ng4. If we assume that
183g >> I”, for all x at 53 and y at g2. (4.5)
then both (10 and or, can be approximated as
a0=TM2,g2/RSM34 and 0‘1 = TR, X”, + Ts1,s1' + Tr213 + Ts3,s3' + TMigi (4-6)
where me , contributing to the time constant TR, X...’ is the total capacitance on node X

when both rs, and r52 are shorted, and CG is the total capacitance on node G. In the

72

 

cskZZ 2: C81:

 

 

 

(a)

 

 

V‘B“ igneV£2—_,_

 

 

 

 

 

 

 

 

 

v rs2 v
x 53—9] }
C C 2_ jz—‘L‘l
Ii If 1'31 8934 g _ V Buivcu
<4) (4 :: Co: G :ng ::C,3
R C
X C 1, Suave (TD—,—
T S schrz
CX = Csl""Cs2 ng34=ng3+ng4 CG=Cg3+cg4+cs2
Csl’ = Cs1""ngl Ii=vilR Cs3’=Cs3+ng2

1F18M1/(1+rs1Cs1*S)le

(b)

Figure 4.3: Linearized Small-signal Equivalent Circuits: (a) Switch
Transistor [21]; and (b) Proposed V-I Converter.

73

calculation of Cg, the capacitance ng34 must be multiplied by a factor B (=gM34rs3) to take
the Miller effect into account.

The assumption in (4.5) suggests that a small switch S3 be employed to reduce the
charge injection error. On the other hand, based on (4.6), the width of 82 should be chosen
appropriately so that the value of or, is minimum. More speciﬁcally, the increase of the
width of 82 results in decreasing the corresponding on-resistance r82 and increasing the gate
capacitance C X...’ Note that the time constant 132,6 decreases as r82 decreases, while the
time constant 1: R, X... increases as C X... increase. In other words, in (4.6), the term 152,0
decreases and IR, X... increases as the width of 82 increases. Otherwise, the term 1825
increases and 1R, X... decreases. Therefore, there exists an optimum width of 82 such that
the value of or, is minimum.

In order for the copier to achieve the shortest settling time, the optimum resistance

R is chosen as follows. Consider the poles given by (4.4). The poles can be approximated as

 

131.2 s — o :1: jar (4.7)
where
1 + R
o = 3M and» = -—l——O’2 (4.8)
201, a001,

For a large R, where RgM34 >> 1, the ﬁrst term in (4.6) dominates. Thus, 0' can be

represented as

o== 81434
" ZCX

tot

 

(4.9)

and the settling time is limited by the time constant of the ampliﬁer. On the other hand, as

R decreases, 0' becomes a constant

C = l/[2(Tsl,sl’ + TSZ’G '1' 183,83, + TMl,gl)] (4.10)

74

The time constants associated with the device M, dominates and thus limits the
settling time. Due to the Miller effect and the parasitic capacitances at the input, the
ampliﬁer may have a smaller bandwidth than the device M,. Thus, the use of small R is
preferred. However, as R decreases, the value of 010, in (4.6), increases. This may cause (u
to become an imaginary number even though a sufﬁciently small time constant TMl,gl may
be chosen. Note that the settling time is determined by the smaller absolute value of the two
main poles. By (4.8), the lower bound of the resistance R should be limited by the condition
that a) is a real number. In other words, fast settling time can be achieved by choosing a

small R that keeps to as a real number.

4.1.3 Simulation Results

The proposed transconductor for V-I conversion has been simulated by PSpice,
where the process parameters of MOSIS 211m CMOS technology are assumed, and the fol-
lowing parameters are chosen: R=2KQ Vb,=2. 1V, and Vb2= 1.5V. To determine its viability
for low-voltage operation, the circuit uses a single 3.3 V power supply. The transistor M,
has a bias current, Ibias1=270 11A, and a constant voltage, 1.43V, the bias voltage of the
ampliﬁer, is used as the load. The above choice is, in fact, appropriate for the use of a cur-
rent copier load whose output voltage is stabilized by the ampliﬁer while 8,, is closed. The
dimensions of each transistors were chosen as follows: (W/L),=500|.1m/2]1m; (WIL)2=
50011n1/2um; (W/L)5=500um/2um; (W/L)3=30um/2p.m; and (W/L)4=20|.1m/2um. The
switches are realized by CMOS transistors. Since the circuit settles within 0.1% at 15ns, a
sampling frequency 25MI-Iz is used in this simulation, where the control pulses for the

switches have a rise and fall time of lns. For a case that an input sine-wave voltage ranged

75

between 0.55V and 1.25V is applied with an input frequency 200KHz, the simulation
results show that the output currents swing between 9611A to 440]).A, and the total power
consumption is less than 2.5mW.

Figure 4.4 shows the transconductance vs. the input frequency, where the
transconductance is deﬁned as the ratio of the amplitude of AV, over that component of the
held output current A10, where both have the same frequency. In this simulation, the sample
frequency is 25MHz and the sine-wave input current has a peak-to-peak value of 0.4 Ibias1°
Results show that the input impedance is about 50 Q for the input frequency of 2MI-lz,
while it is approximately 57 Q for lOMI-Iz. Since the feedback loop has a large bandwidth,
a very flat frequency response is obtained, where a roll-off of about 0.05 dB results when
the Nyquist frequency is reached.

Figure 4.5 illustrates the THD (total harmonic distortion) vs. the amplitude of the
relative input currents, where the relative input current is deﬁned as the peak-to-peak input
current divided by 2 Q,,-M,, the sampling frequency is 25MHz, and the input frequency is
25/ 128 MHz (or, ~200KHz). Results show that a small THD (< -65dB) is obtained for input
currents which swing a range of 300uA. As the amplitude of the relative input currents is
larger than 0.8, the corresponding THD increases rapidly because the small drain currents
of M, or M2 cause a signiﬁcant settling error for the current copier.

Figure 4.6 describes the THD vs. the input frequency, where the sampling
frequency is 25MHz, and the amplitude of the relative input current is 0.2 (or 0.4 lbw”). As
input frequency increases, the current ﬂowing through the gate capacitance C of M2 causes
a voltage drop at VDS of 82. The nonlinear relationship between the voltage drop and the

capacitive current variation increases the THD. This concludes that the THD increases with

76

 

488

487.5

487

486.5

486

Transconductance (10'6 mho)

485.5 _

 

 

 

485
Frequency (106 Hz)

Figure 4.4: Transconductance vs. Input Frequency. (Sampling frequency,
fs=25 MHz, Ib,m,=270|.1A, and I,,p_p)=0.4 Q,,-asp)

 

THD (dB)
r

I

l

 

 

-70 1 1 L 1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Relative Input Current

 

Figure 4.5: Total Harmonic Distortion (THD) vs. Relative Input Currents.
(Sampling frequency fs=25MHz, Input frequency = fs/128, or 2200 KHz)

77

 

 

 

 

'40 l I l I l

-45 1-— 4
a -50 — -
E" ‘55 F— -—1

~60 _. ..

~65 _ _

_ 1 1 1 1 1

700 2 4 6 8 10 12

Frequency (106 Hz)

Figure 4.6: Total Harmonic Distortion (THD) Vs. Input Frequency.
(Sampling frequency fs=25MI-Iz, and
Relative Input Current, 1,0,1, , I 2 Ib,a_,,=0.2)

78

the input frequency.
In summary, the simulation results show that the circuit achieves a high sampling
rate, 25MHz, large dynamic range of the converted currents, and low power consumption

with a low power supply (3.3V).

4.2 An Oversampled SIH Circuit

As discussed in Section 2.3.2, a high accuracy current-mode SIH circuit can be
achieved by current copier with a compensator. Figure 2.11 illustrates a method of building
a highly accurate oversampling current S/H circuit with an integrating feedback structure.
However, the structure may result two major errors: one is from the integrator and the other
from the copier CC. The use of a high-order structure may reduce the errors [29]. However,
it would be penalized by the circuit complexity and the instability problem. Therefore, this
task is to develop an alternative high-accuracy S/I-I circuit using a feedforward approach.
The feedforward approach alleviates the error E,(z) due to the integrator, while the high-
performance copier developed in the preliminary study is used to reduce the error resulting

from the second term of (2.10).

4.2.1 The Feedforward Approach

Figure 4.7(a) illustrates the basic structure of the developed SIH circuit, where the
input current Iin is connected to the inputs of both the gain stage and the copier CC via
switches in different clock cycles. In this structure, the integrator needs only to output the
error current of the copier CC and its output swing can be as much as several ten times

lower than that in the structure shown in Figure 2.11(a). Thus, the error lE,(z)l is reduced

79

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H /. Copier 1

 

 

 

 

 

 

 

 

 

 

 

1
J
(b)
163 102 lb]
Integrator CC
V156 V156
m N "‘ m '—
'2 .2 g I- .53; .§ Inn
in
8 8 8 s 8
<wa 111
i (C) (C)
Vss Vss

Figure 4.7: Proposed SIH Circuit with Feedforward Approach: (a) Basic Structure;

(b) Current Copying Operation; and (c)—(e) Equivalent Circuits for the
Three Clock Cycles in a Loop Operation.

80

considerably. The operation of the feedforward approach can be described by the block dia-
gram illustrated in Figure 4.7(b), where Copier l is the current copier CC, while Copiers 2
and 3 form an integrator. The integrator requires two clock cycles to complete the integra-
tion, while the copier CC takes an additional clock cycle. Thus, the SIH circuit requires 3
clock cycles to complete a loop operation. The operation of the SIR circuit is summarized
as follows. Let m, m+l/3, and m+2/3 denote the three clock cycles of the m-th loop opera-
tion. Copiers 2, 3, and l are calibrated at the ﬁrst, second, and third clock cycles, respec-
tively. Then, the current obtained by a copier in the m-th loop operation can be represented
as Il(m+2/3), 12(m) and I3(m+l/3). The equivalent circuits of the SIH circuit for different
cycles are given in Figure 4.7(c)-(e), where the operating copiers are represented by current
sources and the calibrating one’s by conductances.

During the ﬁrst clock cycle of the m-th loop operation, switch S, is turned ON.
Copier 2 is in calibration, while Copiers 1 and 3 are in operation. From Figure 4.7(c), we
have,

12(m) =Ib2-I,n(m) - I,(m—1/3) - 13(m-2/3)+A12(m) (4.11)
where A12(m) is the error of the copier 2 and I,(m—l/3) and I3(m-2/3) are the currents held
in Copiers l and 3 at the third and second clock cycles of the (m-l)-th loop operation,
respectively. At the 2nd clock cycle, S, is turned OFF. Copier 2 is in operation, Copier 3 is
in calibration, and Copier l is OFF. From Figure 4.7(d), we have
13(m+1/3) = Ib3-12(m)+AI3(m+1/3) (4.12)

Finally, in the 3rd clock cycle, S, is turned ON again. Copier 1 is in calibration, Copier 3
is in operation, and Copier 2 is OFF. Therefore from Figure 4.7(c), we have

I,(m+2/3) = Ib3-Iin(m+2/3) - I3(m+l/3)+AI,(m+2/3) (4.13)

81

After completing the calibration of Copier l, the m-th loop Operation is completed and the
same process is repeated.

The z-domain solution for the currents, I,(z), are

(1 - 41-5/3”!” 4' Z-2/3Ub2‘1b3)

 

 

’1“) = l—z" (1 +z_2/3-z'l)l,n+(l -z.-l)All +z'2/3A12—z'l/3A13
-I
_ 162-1 ’61 -1/3 -I/3 (4°14)
l2(2) - ——:,—-(z -1)I,-,,—z AI, +1312
l-z
-I/3 —4/3
2 (1,, -I )+2 1,, _ _ _ _
13(1) = 31 ”-1 1+,z 1/3_z 2/3)Im+2 2/3Al,-zl/3A12+Al3
-z

Some important properties for the proposed S/I-I circuit are summarized as below:

(i) The error AI,(z) of the copier CC is attenuated by the transfer function (l-z'l);

(ii) The error of the integrator, A12(z)-AI3(z), determines the accuracy of the SIH cir-
cuit for high oversampling ratio;

(iii) The integrator’s output current, 13(z), is mainly determined by the error current
AI,(z) of the copier CC; and

(iv) The effect of the input current on the integrator current is attenuated by the trans-
fer function (l-z'm), where the oversampling ratio is 3 times of that provided by

the transfer function (l-z").

For a high oversampling ratio, the integrator has a very small output current. If the
bias currents of copiers 2 and 3 are chosen to be the same, then both error currents A12(z)
and AI3(z) are virtually equal, i.e., |A12(z)-AI3(z)l is almost zero. Therefore, by Property (ii),

the SIH circuit can accomplish a very high accuracy.

82

4.2.2 Structure and Operation
Figure 4.8(a) shows the schematic diagram of the oversampled current SIH circuit
using the feedforward approach described in Figure 4.7. The current copier CC is realized

by the current-storage transistor M,, while the integrator is implemented with two current-
storage transistors M2 and M3. The negative-gain feedback ampliﬁer, realized by a simple

inverter circuit shown in Figure 4.8(b), is used to stabilize the voltage on Node X enhanc-
ing the accuracy of both Copier CC and the integrator. For structural simplicity and fast

convergency, we choose the gain A,=l.
All switches, except S,, are implemented with simple CMOS switches. Note that

the simple CMOS switch has large on-state capacitance which is equal to the gate-source

capacitance of its switching transistor. Since S, is connected to Node X, the input of the

feedback ampliﬁer, and its stray capacitance, as the dotted lines shown in Figure 4.8(a), is
in parallel with the input of the ampliﬁer, the on-state capacitance will strongly affect the

settling time. Thus, for fast settling time, the on-state capacitance of S, much he kept as

small as possible. In this implementation, a regulated cascode stage, as shown in Figure

4.8(c), where both M121 and Mm are switching transistors, the drain current of M121 is
connected to Node X, and the drain of Mm is connected to the ground. The pair transis—
tors M,, and MiLl form a feedback ampliﬁer for reducing the input impedance of the

switch so that high-linearity current transfer can be attained even when the input current

source I,n has low output impedance. The pair transistor M,, and M,,L form a level shifter
to maximize the gate-source voltage difference among M,,, Mm, and Min. For a given

current range, the use of the level shifter will reduce the transistor size and the output

83

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(C)

Figure 4.8: Transistor-level Implementation of Proposed SIH Circuit:
(a) Schematic Diagram; (b) Ampliﬁer; and (c) Input Stage.

84

capacitance of the switch, and improve the settling speed. A regulated—cascode output
stage with very high output impedance is also used so that the load will not affect the drain

voltage of M, and thus keeping high accuracy and speed of the SIH circuit.
The bias currents 1b,, 1,,2, and 1,,3 are generated by M,,,, sz, and Mb3, respec-

tively, with a bias voltage, VBLAS. The bias current must be chosen properly so that M,,
M2, and M3 have the correct bias. Assume that the input current has a bias Iinbr while I,,,,
12b, and 13,, denote as the bias currents of M,, M2, and M3, respectively. Using (4.14), the
following relations between the bias currents Ibi and the bias currents lib and Iinb’ of the
input current and that in the devices, can be obtained:

I151 = 1115 +131: + Iinb

Ib2 = 11b +1215 +130 + Iinh

1113 = 120 +130
In this implementation, we choose the bias currents I,b=1mbﬂ00uA and 12b=13b=20011A.
Thus, Ib,=1mA, Ib2=l.2mA, and Ib3=0.4mA. The bias currents are obtained by selecting

an appropriate voltage VBIAS and proper transistor sizes for M,,,, i=1,2,3.

4.2.3 Simulation Results

The SIH circuit has been simulated by Pspice, where the parameters 211m SCNA20
CMOS technology is used and 3.3V supply voltage is assumed. Simulation results show
that the calibration of a current-storage transistor takes only 10118 for settling to 0.1%
accuracy. Thus, in this simulation, we choose 15ns for a clock cycle. This implies that it

takes 45ns, 3 clock cycles, for the loop operation in Figure 4.7(a). In other words, the cir-

85

cuit can accomplish a sample rate of 22MSamples/s. Figure 4.9(a) shows the calculated

signal-to-distortion ratio (SDR) of the output current Iout as a function of the signal fre-

quency, where a sinusoidal input current with a 100|1A peak-to-peak amplitude is applied;
and then a 512-point FFT analysis for the output current is made, where the output current

is taken at the end of the operating state of M,. The SDR is deﬁned as the ratio of the sig-

nal amplitude over the highest amplitude of the harmonic that has a frequency different
from the signal. The input frequency is varied from very low to the Nyquist frequency,
llMHz. Results show that the SDR is higher than 60dB for input frequency lower than
nearly 2MHz, or an oversampling ratio higher than 5.5. It should be mentioned that the
saturation of the SDR at the low frequencies is caused by the limited accuracy provided by
the Pspice simulator. The simulation errors result in a noise ﬂoor, as shown in Figure
4.9(b), which is obtained by applying a DC current to the SIH circuit and taking a lOOuA
peak-to-peak sinusoidal input current as a OdB reference. In general, if no computational
errors exist, no harmonics on the spectrum occurs when a DC input current is applied.
Therefore, the simulation noise ﬂoor indicates the computational errors. In this simulation,
the noise ﬂoor limits the SDR to 70.7dB for a lOOuA peak-to-peak sinusoidal input cur-
rent, and the AC current level is bounded by the distortion of the input switch and the out-

put circuit.

4.3 Discussion

A simple transconductor circuit for V-I conversion is presented. The circuit is com-
prised of a simple yet high-linear current copier and a resistor, where the resistor can be

realized on chip. Results show that a high-linearity of the V-I conversion is achieved even

86

simulator noise ﬂoor in dB

\1
C
I

 

 

 

 

 

-105

105

106
Frequency in HZ

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 5 6
frequency in HZ
(b)

Figure 4.9: Simulation Results: (a) Signal-to-Distortion (SDR) Ratio;

and (b) Simulation Noise Floor.

87

though a small resistor is implemented. With the small resistance, a large dynamic range of
the converted currents is obtained with a small swing of the input voltages. Thus, the circuit
is viable for low-voltage operation. The sampling frequency of the V-I conversion can be
increased if the channel length of the devices is further reduced. Based on the salient fea-
tures described above, the proposed circuit is well suited for high-speed and low-power sig-
nal processing applications.

This study presents also a high-accuracy CMOS oversampling current S/H circuit
using a feedforward approach. In an integrating feedback structure, the error current
resulted from the integrator determines the performance of the SIH circuit. Convention-
ally, the integrator has an output current which is nearly equal to the input current in
amplitude. Thus, the large error current of the integrator degrades the performance of the
SIH circuit. As a result, it needs the used of high-order structure to resolve the accuracy
problem and thus requiring high complex circuitry for implementing the SIH function.
This study proposes a simple feedforward approach to reduce the output current of the
integrator. Consequently, high accuracy is attained with a simple structure and a small
oversampling ratio. The transistor level design of the SIH circuit has been simulated and

simulation results are very promising.

88

Chapter 5

Analog-to-Digital Converter Circuits

 

This chapter presents a new high-speed, high-resolution, and low-power switched-
current cyclic AID converter [40]. Cyclic or algorithmic conversion is well known for its
ability to achieve high resolution within small silicon area; the redundant signed digit
(RSD) approach still reinforces the hardware simplicity. The cyclic conversion algorithm
[24] is based on the conventional restoring numerical division principle [24], while the
RSD cyclic conversion [41] is based on the SRT division principle [42]. The converter cir-
cuits in [24] and [41] takes 4 and 3 cycles to double a current. Both use the dynamic cali-
bration technique to alleviate the errors due to component mismatches. However, the
accuracy of the multiplication is still limited due to two major error effects, charge-
feedthrough and non-zero output conductance of the copier. The errors are introduced and
accumulated at each cycle. Therefore, to achieve high accuracy and high speed, it is neces-
sary to reduce the number of cycles required for doubling a current.

In this chapter, both conversion algorithms and the circuit implementations are
reviewed in Sections 5.1 and 5.2, respectively. Section 5.3 presents a 2-cycle RSD cyclic

converter circuit [34].

89

5.1 Cyclic Conversion Algorithms

Figure 5.1 illustrates two cyclic conversion algorithms presented in [24,41]. The
cyclic conversion algorithm [24] in Figure 5.1(a), referred to as RC algorithm, is based on
the conventional restoring numerical division principle, while the RSD cyclic conversion
[41] in Figure 5.1(b), referred to as RSD algorithm, is based on the SRT division principle.
The RC algorithm uses only one comparator and one reference current, and the RSD algo-
rithm requires two comparators with two reference currents. On the other hand, the com-
parator tolerance in the RC algorithm is equal to the resolution of the AID converter, and
the comparator tolerance in the RSD algorithm is much larger. Due to the larger compara-
tor tolerance, the RSD algorithm has been widely used to simplify the comparator design,
to enhance the speed performance, and to reduce the power consumption.

Figure 5.2 illustrates the transfer characteristics of the RC algorithm. For the ideal
case, as shown in Figure 5.2(a), where no comparator error is considered, the residual cur-

rent is Inf when ix=Ire,12. In other words, the boundary i.e., 1,6,, of the convergency region,
the shaded region, is reached when ix=I,e,:/2. However, when the comparator error is taken

into consideration, the residual current can easily fall outside of the shaded region, as illus-
trated in Figures 5.2(b) and 5.2(c), due to the errors of the comparator and the loop opera-
tion. These errors will cause either divergence or wrong digital output codes. As a result,
implementing the RC algorithm requires a high accuracy comparator and an operational
ampliﬁer with low offsets.

Figure 5.3 illustrates the transfer characteristics of the RSD algorithm and its con-
vergence region. For the ideal case, as shown in Figure 5.3(a), it has a very large margin

between the boundary and the current ranged -I,e,r/2 S ix 5 Inf/2. Therefore, implementing

90

ix

b

 

 

x2

 

 

@N"

Yes

 

 

subtraction of Ire,

 

 

T

(a)

 

 

No

i,T

 

 

x2

 

 

 

 

Yes

 

 

subtraction of - m,

 

 

 

subtraction of In,

 

 

Figure 5.1: Cyclic Analog-to-Digital Conversion Algorithms:
(a) RC Algorithm; and (b) RSD Algorithm.

F

 

(b)

91

l

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

residual out of the residual 9‘" 0f “1°
, convergence convergence
r sidual resrdual region residual region
urrent Current Current 6)
A l
Iref 1'“ Irief
loo / V
. . offset .
#1,, >‘X error -‘x
liter"2 1“,, 1 ﬂ Iref L912 Iref
comparator
(a) (b) "'0' (C)
Figure 5.2: Transfer Characteristics of RC Algorithm: (a) Ideal Case;
(b) with Comparator Error; and (c) with Loop Offset Error.
residual A
Current
lief
I 1’?-
-Imf l'B II'B Iref L
i‘r
tell2 1min )1
'Irer'4 1.814
'Iref
, (a)
A resrdual A .
Comparator urrent Loop Offset resrdual
Error Error Current
Iref lief
1131’: I
_ I r’2
If“ 0 ml 1'“ r 'Iref m \_ / I Let _
i ‘ / - '
ﬂ -1rer’2 x ”7'2 § -1,,,12 1"
- [“14 I Imﬂ‘l / Ital“
- ”f -1 (44 'Iref
14—» re
K C
(b) omparator
Tolerance (c)

Figure 5.3: Transfer Characteristics of RSD Algorithm: (a) Ideal Case;
(b) with Comparator Error; and (c) with Loop Offset Error.

92

the RSD algorithm can tolerate larger inaccuracy in the comparators and offset in the oper-

ation loops, as illustrated in Figures 5.3(b) and 5.3(c).

5.2 Cyclic AID Converter Circuit Designs

TWO cyclic AID converter circuits have been presented in [24,41] and implemented
the RC algorithm and the RSD algorithm, respectively. This section reviews the circuit

design and operation of both converters.

5.2.1 A 4-cycle cyclic converter

Figure 5.4(a) shows the schematic of a cyclic A/D converter [24] implementing
with the RC algorithm. The converter circuit takes 4 clock cycles to generate one bit, as
indicated by the timing scheme of the switch clocks in Figure 5.4(b). At ﬁrst, let us con-
sider the process that generates i-th digital bit with the s-signal having its state law. We

denote the current sampled by the transistor M3 as Id3(i-l) and the digital bit d“ produced
by comparing Id3(i-1) with the reference current. The current Id3(i-1) will be sampled by
transistors M1 and M2 during (D1 and (Dz, respectively. Whether the reference current Iref is
subtracted from the current depends on the state of d at that time, or the value d“. Note
that di,1=sign[Id3(i-1)-I,ef/2] is a two-valued variable with di,1=l, if Id3(i-l)-I,efl2 > O, and
di_1=0 otherwise. Thus, we can write
Id1(i) = Id2(i) = Id3(i-1) — di,11,ef/2. (5.1)
In (D3, the sum of the drain currents Id1(i) and Id2(i) of the transistors M1 and M2

will be sampled by M3. Thus, we have

93

 

C3
_ Ampliﬁer
5/ D—T

 

0 E
’
d(¢l+¢2)+¢4 t0 latCh

__ \ ¢1+¢3 W 4545
4’1

 

 

Iref/2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 'I‘ 2T 3T 4T 5T 6T 7T 8T 9T

0))

Figure 5.4: A 4—cycle Cyclic A/D Converter: (a) Schematic;
and (b) Switching sequence.

94

Id3(i) = 2 [Id3(i-l) - di_,lref/2]. (5.2)
The digital bit di is obtained in (D4 by comparing Id3(i) with Inf/2. The iteration (5.2) per-
formed by Figure 5.4(a) is exactly the same one as deﬁned by Figure 5.1(a), where i" is
replaced by Id3. The s-signal is used to control the beginning of the conversion. Its effect is
to substitute Iin for Id3(0) in (5.1). Another additional comparison is needed to generate the
most-signiﬁcant bit do.
The converter achieves a lO—bit accuracy and a speed 250 kbit/s [24]. The low

speed is mainly due to its use of INFCCI copiers.

5.2.2 A 3-cycle RSD cyclic converter

The number of clock cycles for one bit conversion can be reduced from 4 in [24] to
3 by removing the clock cycle (D4, and making the comparison in parallel with computing
the residual current [41]. More speciﬁcally, the doubled current held in P, is copied to N1 in
the clock cycle (D1. Since N1 is idle during the clock cycle (Dz, the current held in N 1 is
compared with Inf/2 for determining the converters bit. Figure 5.5(a) illustrates the cyclic
AID converter circuit developed in [41], where three copiers are employed as the residual
ampliﬁer which takes 3 cycles to double a current. The self-regulated cascode copiers with
the transconductance gm], gmz, and gm3, are used to achieve high speed, and no feedback
ampliﬁer is needed. The transconductance gm1 is calibrated during the clock cycle (DI.
During (D2, the current held in the copier with gm, is sent to the current mirror consisted of
transistors M4, M5, and M, where the current is ampliﬁed by a factor of 2. The ampliﬁca-

tion is achieved by selecting the aspect ratios of M5 and M6 to be twice that of M4. The out-

95

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

$ Irefl S —‘
A =IretJ
g: \ I: d1 d2 :I
E | d’Z/ compl comp2
f / ¢}+¢3 (D +¢3
% Mam f (ht—E1}— l 31,,f/4 rel/4 .L

 

 

 

 

 

«e
II h-t
gs
<~|

D
.9
<—|

(a)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

o T 2T3T4T5T 6T7T8T9T
(b)

Figure 5.5: A 3-cycle Cyclic A/D Converter: (a) Schematic;
and (b) Switching sequence.

96

put currents Ids and Id6 of the current mirror are compared with (3/4)Imf and (l/4)Imf,
respectively. The comparison results, (1, and d2, are then sampled at the end of (D2. Both bits
d. and d2 are used to control which reference current, In,“ or Item, is used for next compari-

son. The converter achieves a simulated lO-bit resolution and 4.5 MS/s sample rate with

pipeline structure [41].

5.3 Proposed 2-Cycle RSD Cyclic AID Converter

To alleviate the error effects in current copiers for high accuracy and high speed
cyclic AID converter, the number of cycles for a residual ampliﬁer must be reduced. This
section proposes a 2-cycle RSD cyclic AID converter circuit design which achieves a 12-
bit accuracy and 20 Mbit.s speed. This section presents the residual ampliﬁer, the RSD

algorithm, and the decoding scheme for the proposed AID converter.

5.3.1 Structure and Operation

Figure 5.6(a) shows the proposed converter, where four current copiers represented
by gm“ are employed. The circuit requires only two cycles to generate a ternary bit, rep-
resented by the two single-bit binary signal (1, and d2. During the conversion state, where
the start signal s is low, the four copiers are grouped as two copier pairs, gm” and gm3,4.
At each bit conversion, the residual current, the sum of the currents stored in a copier pair,

is copied during (1)1 and (1)2 (or (b3 and (134) to two current copiers in the other copier pair.
Speciﬁcally in Figure 5.6(a), the sum of the currents in gm3 and gm4 is copied to gm] dur-

ing (D1, and then copied to gmz during (D2. The sum of the currents stored in the pair

97

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-C1 -- C2 - C3 - C4
gm 9" gmz 9— Kgmaig Rennie" :
m son: was Wm. '21/ ,
get/ 9 g%/ 9 31/ ° 31/ 9 c°mP d]
_e Ne me ve ‘
e a e m e to“ e :7; E1>‘la§h—*
S S+d1(¢,+¢3)l S+d2(<l>1+d>3)[ an S+d>2+¢4
+d2(¢2+¢4) +d] (¢2+¢4)
[in V platen?
I I I 4
b ref 1 ref2 re comp2 S+¢2+¢4
(a)
b b b b b
S— 1 2 3 4
dz, _
“’2
$23—
“’4
0 T 2T 3T 4T 5T 6T 7T 8T 9T

(1))

Figure 5.6: A 2-cycle Cyclic AID Converter: (a) Schematic;

and (b) Switching sequence.

98

(gm1,gm2) becomes the new residual current which will be copied back to the pair
(gm3,gm4) during (b3 and (D4, respectively. Since it takes one cycle to copy the residual
current in the pair (gmbgmz) to a current copier in the pair (gm3,gm4), the residual ampli-
ﬁer takes only two cycles (1)] and (1)2 (or (D3 and (D4) to double a current.

Two comparators are used to monitor the transconductance currents indirectly. The
relation between the input voltage and the current in the transconductance can be expressed

as Ii=gmchi, where, Ii is the current of transconductance gm; and Vci the voltage on the
capacitance Ci. Therefore, instead of comparing the currents Ii with the reference currents,
we can compare the voltages Vci with the reference voltages Vren and Vrefz. The use of

voltage comparison instead of the current comparison can simplify the circuit and reduce
the power by avoiding using the current mirrors. Since large comparator errors are permit-
ted by a RSD algorithm, neither exact transconductances nor accurate comparators are

needed. The comparison results are latched at the ends of (D2 and (b4, where the conver-
sions for one bit are completed. The single-bit binary outputs (11 and d2 of the latches con-
trol the two reference currents In“ and Iref2 to implement a RSD algorithm. It will be seen
later that the conversion accuracy will not be affected by the mismatch of In“ and Item.
The start signal s is used to sample the input current Ii“. When 3 is high, a transcon-
ductance pair (gm3,gm4) is set to the calibration state and to receive the input current,
while the pair (gm1,ng is turned off. Each reference current is turned on by the s-signal

to produce a suitable bias current for the input current source. At the same time, the input

current is compared with the two reference levels { gmijfl, gmijfz} to produce the most

signiﬁcant bit b0, where j=l,2,3,4. Here, the transconductances are chosen with the same

99

values. At the end of the s-signal, we have the residual current IR(O) in the conductance
pair (gm3,gm4) and the most signiﬁcant digital bit d1(0) and d2(0) in the latches.

Without loss of the generality, we assume that the residual current for the odd bits
are held in the pair (gm1,gm2), while that for the even bits are in the pair (gm3,gm4). Let
Ij(i) denote the current stored at transconductance gmj, j=l,2,3,4, and IR(i) be the residual
current for the i-th bit. During (bl, the switch on the top of reference current In“ is con-
trolled by the single-bit binary signal d1 while the switch on the top of reference current
Irefz is controlled by the single-bit binary signal d2, thus we have for the odd bit i, the cur-
rent in gm] is expressed as

Il(i) = Ib+d1(i-1)I,ef1+d2(i-1)Ima-[I3(i-l)+l4(i-1)]

= Ib+d1(i'l)lrefl+d2(i’l)lref2 4110-1) (531)
During (1)2, the switch on the top of reference current Ire“ is controlled by the single-bit
binary signal d2 while the switch on top of reference current Inn is controlled by the sin-
gle-bit binary signal d1, we have the current in gmz

I2(i) = Ib+d2(i'1)lrefl+dl(i'1)Iret‘2’[l3(i'l)+14(i'1)]

= Ib+d2(i'1)lmf1+dl(i'l)lref2 -IR(i-1) (5.311)

and the new residual current can be expressed as
1R0) = [Il(i)+12<i)1=21b+td1<i-1)+d2(i-aluminum) -2IR(i-1). (5.4)

The current in the transconductances is detected using the voltage on the node X. During
(1)2, the gate switch of the transconductance gmz is closed and its input is connected to node
X. The current in this transconductance will determine the voltage on node X. Thus, the out-

puts of the comparators will determine the range of the current in gmz. In other words, the

100

digital outputs d1 and d2 are determined by the current in gmz, which is half the residual cur-
rent. At the end of (1)2, the comparison results will be sampled by the latches. The digital
signals d1 and d2 will be changed from d1(i-1) and d2(i-1) to d1(i) and d2(i), respectively.
Similar to (5.3), we have the current obtained by gm3 in (D3,

13(i+1) = Ib+dl(i)1ref1+d2(i)lref2'[l1(i)+12(i)] = Ib+d](i)lref1+d2(i)lref2 -IR(i),(5.51)
and the current obtained by gm4 in (1)4,

14(i+1) = Ib+d2(i)1ref1+dl(i)Ircf2'[Il(i)+12(i)] = Ib+d2(i)1refl+d1(i)lref2 -IR(i).(5.511)
The new residual current is

IR(i+1) = [Il(i+1)+12(i+1)]=21b+[d1(i)+d2(i)](lrefl+lrcf2) -21R(i). (5.6)
During (b4, the gate switch of gm4 is closed and its input is connected to node X. The current
in this transconductance is used to determine the digital outputs (11 and d2. At the end of (1)4,
the new digital bit d1(i+1) and d2(i+l) will be sampled by the latches.

Equations (5.4) and (5.6) show that the scheme of implementing the RSD algorithm.
The three output states of the redundant bit is d1d2={00, 01,11}. It should be noted that the
two reference currents are averaged by the two clock cycles for a bit conversion. As a result,
the sum of the two reference currents determines the reference level, and the mismatch
between them will cause no loss of the resolution of the AID converter circuit.

In (5.4) and (5.6), the old residual current is multiplied by a factor of (-2), before it
is added to the new residual current. This is not the same as a conventional scheme, where
a factor of +2 is used. The difference will result in a digital output which is not in a standard
binary code. Thus, a decoder is introduced to change the generated code to a stand binary
code. The negative sign will also change the determination of the comparator levels which

will be discussed later.

101

5.3.2 Convergency Range

The convergency range is the current range of the transconductances, in which the
residual current will not decrease or increase unboundly. The determination of the conver-
gency ranges will permit us to ﬁnd out the input current range for a given 1b and Infl+lren,
in which the converter can work properly. It permits us also to ﬁx the comparator levels
that gives maximum comparator error tolerance.

The residual current IR(i) is divided into three regions by the two comparators.

They can be deﬁned as:
R0: 112.6) 5 IL E9 d2d1=00
R1: IL < IR(i) < IU =i> d2d1=01 (5.7)
R2: IU 5 Ike) => d2dl=ll,

where IL is the residual current level, at which the ﬁrst comparator output (11 changes state,
and IU the residual current level, at which the second comparator output d2 changes state.
In the above deﬁnitions, 1U being larger than IL is assumed. Initially, the residual current

can be in any of the regions. Using (5.4) or (5.6) one can ﬁnd where the new residual cur-
rent will be, when an initial residual current is given.

Figure 5.7 shows some possible transitions of the residual currents between differ-
ent regions, with the initial residual current IR(1) being in R0. Case (a) corresponding to
the situation that the initial residual current has such a value that the new residual current
IR(2) will remain in R0. With the decrease of the initial residual current IR(1), the new
residual current IR(2) will go into region R1, as indicated in Figure 5.7 (b). For a even more

smaller IR(1), the residual current IR(2) will go into the region R2, and R2 can also be large

102

I I
R0 m L R1 |u R2

 

 

 

l IR
a 3' I >
1 2
(a)
I IU
R0 1 IL 2 R1 I R2 15
w ' ,
(b)
I
R0 IIL R1 I” R2 IR
4 I * ’

 

I

Figure 5.7: Residual Current Transition.

103

enough, such that residual current IR(3) goes back to region R0. For convergency, we
require
1R0) >IR<1) (5.8)
Using (5.6) and (5.7), we have
IR(2)=21b-21R(1); IR(3)=21b+21,er21R(2) (5.9)
where ImFIrefl+Imf2. Similarly, if we assume that IR(1) and IR(3) are in R2, and IR(2) in
R0, the convergency condition will be changed to
IR(3) <1R(1) (5.10)
Using (5.6) and (5.7), we have
IR(2)=21b+21rer21R( 1); IR(3)=21b-21R(2) (5.1 1)
Form (5.8)-(5.11), we have
21b/3'21ref/3 < IR < 21bI3+41mtI3 (5. 12)
In the (5.12), the time index of the residual current is dropped off since the inequality must

be meet by all the residual currents for convergency.

5.3.3 Comparator Levels

To determine the comparator levels, we have to find out the convergency regions
for the different residual computation rules. From (5.6), there are three different ways to
compute the new residual current from the initial one. Putting different possible values of
dzdl into (5.6), we have

IR(2) = 21b - 21R(1) rule 0

IR(2) = 21b + Iref - 21R(1) rule 1 (5.13)

104

IR(2) = 21,, + 21M - 21R(1) rule 2
The new residual current IR(2) must be in the range given by (5.12), no matter which rule
is used. Thus, from (5.12) and (5.13), we obtain the convergency regions for different
residual computation rules
2IbI3-21mf/3 < IR < 21b/3+I,ef/3 rule 0
21b/3-0.51,efl3 < IR < 21bl3+2.51,ep’3 rule 1 (5.14)
21bl3+Ire1J3 < IR < 21bl3+41refl3 rule 2
The convergency regions given in (5.14) are plotted in Figure 5.8. There are over-
lap convergency regions for ruleO-l and rule1-2. The middle points of both overlapping
regions, IL=21bI3+ImfI12 and IU=21bI3+7Iref/12, are selected as the comparator levels.

Thus, like a conversional RSD algorithm, the one presented here provides a tolerance of

ﬂmﬂ4 for the comparator’s inaccuracy.

5.3.4 Decoding

As mentioned before, after one bit is generated, the residual current is multiplied
by a factor of (-2). This is different than a conventional converter, where it is multiplied by
a factor of (+2). The generated output digital codes must be transformed to standard binary
codes and a decoder is developed. For a 2N-bit converter, the relation between the input
current Ii“ and two one bit digital codes d2 and (11 can be written as

2N-1

I... = Io+Iref z [claimant-2)"

i=0
N-l . N-l .

= 10+Iref 2 [d2(i)+d1(i)]2'l-Imf 2 [d2(i)+d1(i)]2'(2‘+1) (5.15)
i=0 i=0

105

IL 10
(1mm) (71ml'l12)

-21 3 I 3 41 g3
m! ruleO I :6: rule2 m

 

 

 

; 1,,8(m)-21b/3

 

4L

 

Figure 5.8: The Comparison Levels with Respect to the Convergence Regions.

106

Where I0 is a constant offset. Expressing 10 in the form

N-l .
I0 = 1;,+ Ilref 2, 2'”
i=0

we can rewrite (5.15) as

N-l _ N4 .
Iiflo+1ref3d2(i)+d1(i)]2'2!+ r,3fX( l -d2(i))+( 1-d1(i))]2'(21+1)
H) ”0 (5.16)

N" , N-l _ _ .
=1$+Irefﬂd2(i)+d1(i)]2'2‘+I,ef§[Od2(i)+dl(ing-(21“)
i=0 1

where 211 and dz denote the logical complementary of d1 and d2 respectively. By deﬁning

, d2(i) d1(i) for even i
d§(i) d1(i) ={ __ __ (5.17)
d2(i) d1(i) for odd i

we can express (5.16) as

I,,,=I,’,+1)Iref (5.18)
2N-l , , ,
D=}=:otd2(i)+d1(i)12“ , (519)

Based on (5.17) and (5.19), the decoder can be implemented as shown in Figure 5.9.

5.4 Circuit Description and Simulation Results

This section describes the circuits used to implement the proposed AID converter
circuit, including both the analog circuits and digital circuits for the clock generating and

conversion control. Finally, the simulation results are given to verify the operation.

5.4.1 Circuit Implementation

Figure 5.10(a) shows the proposed cyclic AID converter circuit. The transconduc-

tances gm-, j=l,2,3,4, in Figure 5.6(a) can be implemented using any of the current copiers

107

d2(i) 550)

d1(i) d—l-(i)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

i=even
T i=odd
AND AND AND AND
OR OR
1 , ,,
d2(i) l d1(1)
L ADDER
ADDER
\ I
Latch ‘——
'=2N- 1

 

 

Figure 5.9: The Decoder.

108

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6 3' f 7
III]
M O- M O- M II’ O-‘ '1’ 0'0
9 “'IC' “TC: "’TC’ '1.._C‘
~ . a A 5»
:2. it ”"1” 12“} 1“"1 “— g
1’ .. 1° “>0 .—
ma.
(a)
VDD SI

 

 

i1 "
rig-L
Ix

 

 

 

 

*1

"<1 SH
.5.»
.3
my:
Kg:
<1
,3 8

 

 

 

 

 

MiLl

Vbiaicﬂ VDF VDD
iS i C C
Vbias_e_2_‘ c m JFI IrL
FB DA2 ll DA DA2 IF DA
C Silg DA _‘ Cﬁl — Cﬂsz ‘—
l

 

 

 

- T>_ Mifl
I DA Vbiiii MifL
1 GND

 

 

 

 

 

 

 

 

 

 

 

Hm — 1| I
CFB

V 2 V CF81 V
SmL DF__{ l.— VDD DF___| }__ DD

GND (d) (e) (f)

 

 

Figure 5.10: Proposed AID Converter Circuit: (a) Schematic; (b) Modiﬁed FNFCC;
(c) Input Stage with Switch S]; ((1) Feedback Ampliﬁer; and Equivalent
Circuits of the Level Shifter for (e) (b1 & (D3; and (f) (D2 and CD4.

109

discussed previously in Chapters 2 and 3. For high performance AID converter design, this
implementation employs the current copiers, as shown in Figure 5.10(b), which is modiﬁed
from the FNFCCs in Figure 3.12(a). The copier has the best speed and noise performances
under low supply voltage, and also permits the use of a simple N-well CMOS process that
is preferred for digital circuit design considerations.

Three switches, S], 82, and S3, are used in the current copier. Switches can be gen-
erally implemented with simple CMOS transistors. However, the simple CMOS switch has
large on-state capacitance which may slow the settling time. In this implementation, both 82
and S3 are realized by simple CMOS switches, but not 8,. Since 81 is connected to node X,
an input of the of the ampliﬁer, its on-state capacitance must be kept as small as possible to
reduce the settling time. Therefore, switch 81 in Figure 5.10(a) is employed, where both
Mm and Mm are the switching transistors, and the drain of Mm is connected to node X.
Note that the switching transistors are operated in saturation when they are turned on. Thus,
the stray capacitance is only the overlap capacitance between gate and drain of the switching
transistor, and this capacitance is much smaller than that in a simple CMOS switch.

Figure 5.10(d) shows a high-gain feedback ampliﬁer which is used to reduce the er-
ror due to the increased output conductance. The ampliﬁer is a simple cascode stage with a
capacitive level shifter. With the level shifter, the output of ampliﬁer can be higher than the
power supply VDD. The level shifting maximizes the gate source voltage difference Vgsl of
M1 for low power supply applications. Maximizing Vgsl will reduce both thermal noise and
the error due to charge feedthrough effect.

The level shifter uses a three-capacitance approach to avoid the effect of the stray

resistances on the settling time, thus, small switches can be used. The switches are con-

110

trolled, such that, for one operation cycle of the ampliﬁer, where one of the current copiers
is calibrated, capacitance CF31 is connected between VDD and V012, and CF32 is paralleled
with CF. In the other operation cycle, the positions of CF31 and CF32 are exchanged. The
equivalent circuits of the level shifter for different clock phases are illustrated in Figures
5.10(e) and 5.10(f). Suppose at time k the voltage across the capacitance CF is VCF(k) and
CFBI=CF32=CFB’ then, at time k+l, the capacitance will have a voltage VCF(k+1)=
[CFVCF(K)+CFB(VDD’VDF)]/(CF+CFB)- This expression gives a steady-state solution VCF
= VDD - VDF. The voltage on the output node DA is shifted up by VDD-VDF, relative to that
on the node DA2. This structure of the level shifter has the advantage that a signal path from
DA2 to DA is provided directly by C1; The parasitic resistances of the switches have little
effect on the settling of the copier.

It should be mentioned that the pair transistors Mn and Min form a feedback am-
pliﬁer for reducing the input impedance of the switch so that high-linearity current transfer
can be attained even if the output impedance of the input current source is small. The pair
transistors Mif and Mn form a level shifter to maximize the gate-source voltage difference
among Mil, Mm , and Mm. For a given current range, the use of the level shifter will reduce
the transistor size, improves the settling speed, and reduce the output capacitance of the
switch. Simulation results show that the improved switch achieve a settling time of 8ns.

For time-interleaven parallel ADC structure, the drain current of Mm can be used
as the input of the other ADC cell, as shown in Figure 5.11. The number of channels can be

increased for parallel ADC structure by increasing the switching transistors.

11]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5.11: Current Copier with the Input Stage.

112

5.4.2 Control Circuitry

Figure 5.12(a) shows the control circuitry for managing the reference currents 1an
and 1mm, where the inputs of the control logic include 5, d1(i), d2(i), (bl, (D2, (113, and (D4.

The control signals for the input switches and the switches at the gates and drains
of the current-storage transistors can be generated using a state machine. More speciﬁcally,
the clock cycles presented in Figure 5.6(b) can be described by a state machine shown in
Figure 5.12(b). The converter samples the input current during the state 3:1. The current is
then sampled by the current-storage transistor pair (M1,M2) or (M3,M4), depending on the
state of the mode-4 counter before sampling. In Figure 5.6, we assumed that the current is
sampled by the pair (M3,M4). Because the symmetry of the two pairs, the difference will
make no effect on the conversion results. After the input current is sampled, the residual
current will be transferred from one pair to another during the states (1314 and (133.4. Every

time the residual current changes its location a new digital bit will be generated, increasing
the bit number i by 1. Because the residual current goes back and forth between the two

pairs, the converter goes back to state (1)] after the state (D4. The mode-N counter counts

how many bits is converted. After the last bit is obtained, a carry will be output by the
mode-N counter, as shown in Figure 5.12(c), and the converter goes back to its initial state

to sample a new input current. The whole process repeats itself again.

5.4.3 Simulation Results

Consider the schematic diagram of the proposed switched-current cyclic AID con-

verter in Figure 5.10(a), where four copiers implemented by the current-storage transistors

113

Irefl

 

 

 

 

 

 

 

 

 

 

ORﬁ

 

 

VBIAS

 

 

 

 

 

 

AND

 

 

 

 

 

 

 

 

d1(i)

d2(i)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OR

 

 

 

OR

 

 

 

 

 

 

 

 

 

Clock .

 

 

(C)

 

 

 

(R4 ‘23 (152 4’1
OR
AND AND AND AND 1
r4 iﬁ Clock
1 r4 Mode-N
Q1 01 Q0 Q0 Counter
Mode-4 Counter Carry i s

Figure 5.12: Control Circuitry: (a) Reference-Current Generating Circuit;

114

(b) State-Transition Diagram; and (c) Logic Implementation.

M 1-M4, and the two reference currents, 1an and 1mm, and the bias current, 1., are generated
by the transistors Mm“, Mmfz, and Mb; Switch 81 is implemented by the circuit shown in

Figure 5.10(e), while other switches are realized by simple CMOS switches; The circuit in
Figure 5.10(d) is employed as the feedback ampliﬁer; and the comparators and the digital
logic, implemented by CMOS transistors, are used to produce the digital codes. The circuit
has been simulated by pspice, where the SCDN20 2|.tm CMOS process with level-2 transis-
tor parameters and a supply voltage of 3.3V are employed. The reference and biased cur-

rent are chosen as Iref1=1ref2=170l1A and Ib=lmA. Simulation results show that the total

power consumption is about 7mW, including 2mW for the input current switching unit.
Figure 5.13(a) shows a typical current waveform in a current-storage transistor,

while Figure 5.13(b) plots the partial output of Ire“ to demonstrate the three states in the

RSD approach, where the current pulse widths of 50ns, 25ns, and 0ns, represent the state 2,
1, and 0, respectively. (Since the clock rate for calibration is 25ns, i.e., one bit is obtained
in every 50ns.) Figure 5.13(c) summarizes the accuracy of the proposed ADC which
achieves a 12-bit resolution for the input currents ranged between 350uA and 850u.A.
According to the simulation results in Figure 5.13(b), the time period for the
steady-state can be further reduced and thus increasing the conversion rate. In addition,
since a larger settling error is allowed for those lower signiﬁcant bits, a shorter clock cycle
can be used to perform the calculation. Therefore, the use of multiple clock cycles can also
increase the conversion rate. We believe that the average bit conversion can be moved to

20-25ns in a 12-bit conversion.

115

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3...
G
"005 """""""""" 3 3 , - 81
umeus
(a)
2501" - ---- - -
200.
r
2,...er (W rrrr' r
'5'
'3‘ 100‘
50‘
0 Hi... tccl .21 L 4.1 1 51. LL .... 1-53
-503- ----- - .2 , -- -- - --,'8.-- -- -- ---
timeus '
(b)
0.1 l r I T r
‘5 upper limit for 12 bit resolution
5? 0.05 - -
L. 8. * *
10:, 5 * =1: :1: *
.. g 0 — :1: at: ‘2
5. :1:
E E =1:
3'; -o.os _ * _
lower limit for 12 bit resolution
'0'131 400 35?) 600 760 860 900
input current in micro ampere
(C)

Figure 5.13: Simulation Results: (a) Typical Current Waveform;
(b) Partial Outputs for Ire“; and (c) 12-bit Resolution.

116

5.5 Discussion

This chapter presents a high performance cyclic AID converter circuit design. The
high performance is attributed to: (l) the use of high performance current copiers; (2) the
use of a high performance residual ampliﬁer which takes two clock cycles to double a cur-
rent; (3) the use of an efficient Cyclic RSD algorithm which provides 1.5b resolution with-
out using two matched reference currents.

The performance of AID converter can be improved by further reducing the charge
injection errors [43]. A fully differential switched-current AID converter has been investi-
gated, where high performance fully differential current copiers are implemented. Fully
differential architectures are frequently employed in both continuous-time and switched-
capacitor circuits to achieve the highest level of analog performance [44]. The approach
reduces distortion by cancelling even-order harmonics and reduces cross-talk from neigh-
boring digital circuits through common-mode and power supply rejection of the ampliﬁers.

Thus, a fully differential current copier can further reduce charge injection errors [43].

117

Chapter 6

Conclusion

 

Portable televisions, camcoders, and compact disk players have been made avail-
able by consumer electronics companies. Cellular phones are going to provide virtually
unlimited access for voice communications; and laptops, notebooks and palmtops are the
fastest growing types of computers. Portable multimedia terminal will come into being,
which will be capable of providing speech communication, data transfer, handwriting rec-
ognition, and high-quality, full motion video. Each of these technologies relies on VLSI for
cost and power-consumption effective implementation. Given sufﬁcient complexity, even
CMOS dissipation levels become excessive especially where high frequency is involved. It
is necessary to optimize the VLSI-technology for low-power operation of both digital and
analog circuits.

SI technique has received considerable attention as an alternative for analog circuit
design. However, existing 81 circuits cannot make the theoretically expected performance
due in part to the use of non-optimal current copiers, its basic building blocks. Based on our
development of design methodologies and synthesis process for optimally generating low

power and high performance CMOS current copiers, SI technique becomes feasible.

118

The objective of the thesis research is to develop new generation of high-perfor-
mance, low-power/low-voltage current-mode circuits. The emphasis is placed on the devel-
opment of sample/hold circuits, and analog-to-digital circuits for mixed-signal IC’s in

future portable equipment.

6.1 Summary and Contribution

In Chapter 1, the low power design issues were addressed and the advantages of
using SI technique for designing analog portion of mixed-signal ICs were introduced. A
number of previous works for designing high performance AID converters and SIH cir-
cuits were reviewed. The research tasks were outlined. Chapter 2 reviews existing current
copiers, switched-current data converters, and switched-current SIH circuits

Based on the analysis of the charge-injection error, Chapter 3 outlines the design
trade-offs among accuracy, speed performance, and power consumption and addresses the
stray effect of the switches which may degrade the speed performance of the copiers. It has
been shown that the stray effects can be alleviated by reducing the stray capacitance of the
current-steering switches, or by separating the large current-steering switches from the
small current-sample switches, for the copier to achieve high speed operation. A simple,
yet high performance current copier, FNFCC, was developed. Simulation results verify the
operation and demonstrate high performance accomplished by the developed copier.

Chapter 4 presents the design of a simple high performance SI V-I converter with
the SIH function and an oversampled high linear SI SIH circuit. The developed V-I con-
verter is comprised of a high-linear current copier and a resistor. Result shows that, with the

small resistor, a large dynamic range of the converted current can be obtained with a small

119

swing of input voltages. Thus, the circuit is viable for low-voltage operation. The devel-

oped oversampled SI S/H circuit adopts a simple forward approach to reduce the output

current of the integrator. With a simple structure and a small oversampling ratio, the circuit
achieves high accuracy.

In Chapter 5, a high performance cyclic AID converter circuit design was presented.
The high performance is attributed to: (l) the use of high performance current copiers; (2)
the use of a high performance residual ampliﬁer which takes two clock cycles to double a
current; (3) the use of an efﬁcient Cyclic RSD algorithm which provides 1.5b resolution
without using two matched reference currents.

This work has established guidelines for designing high-speed current copiers and
switched-current circuits, making them more attractive for the next generation low-power,
low-voltage, high-speed high-accuracy analog circuit design. The major contributions can
be categorized as follows:

(a) Developed a performance analysis process for current copiers and a synthesis pro-
cess for developing high-performance current copiers for low-power/low-voltage
signal processing applications.

(b) Developed two types of SIH circuits; and

(c) Developed a novel high-speed and low-power cyclic AID converter design.

The developed circuits meet the design requirement not only for portable equip-
ments, but also for video signal processing, such as HDTV, high-frequency digital commu-
nications, and waveform acquisition/instrumentation. This research has demonstrated that
this development is not merely an academic curiosity, but an important practical technology

for the future.

120

6.2 Future Work

Circuit synthesis is to select the right circuit from among existing alternatives to ful—
fill the intended application. Conventionally, guided from past experiences designers
choose a promising circuit architecture that could meet the given set of performance spec-
iﬁcations. However, because of the large number of variables involved, it is difficult to
accurately predict the circuit behavior. The circuit may partially fulﬁll the performance
speciﬁcations, but it is not optimally designed. As a result, existing SI circuits cannot meet
the expected theoretical performance even though with novel circuit structures. Thus, it is
necessary to develop a design methodology for high-performancellow-voltage CMOS SI
circuits. This can be accomplished by constructing the parameter space of current copiers
for a given set of performance speciﬁcations and providing the optimally designed copiers.
The performance analysis and synthesis process discussed in Chapter 3 can be further
developed for synthesizing optimal current copiers and SI circuit.

In Chapter 5, a l2-b, 20 MS/s, and 7mW AID converter circuit has been designed
and simulated. The simulation results have conﬁrmed the operation of the converter. The
performance can be further improved by the following parallel-pipelined structure with cal-

ibration capability.

 

 

 

 

 

 

121

At any time one AID converter will be calibrated by sending Inf to the converter,
The other converters will be used for conversion. The speed-up ratio of the parallel struc-
ture with n converter is (n-l) with calibration ability, while a speed-up ratio of n is achieved
if no calibration capability is considered. With the calibration ability, the DC offset of dif-
ferent channels can be cancelled off; and the linearity can be made only determined by the
units that controls the calibration of the input current and the reference current. Apparently,
the sample rate increases with the number of converters. However, the increase of convert-
ers will also increase the total power consumption. It is expected that, with 10 converters,
the parallel-pipelined converter achieves more than 12 bits, 40-50MS/s, and 60mW.

The performance of AID converter also can be improved by further reducing the
charge injection errors [43]. A fully differential switched-current AID converter has been
investigated, where high performance fully differential current copiers are implemented.
The fully differential architectures reduce distortion by cancelling even-order harmonics
and reduce cross-talk from neighboring digital circuits through common-mode and power
supply rejection of the ampliﬁers. Based on the fully differential current copier developed
in [43], it is worthwhile to develop a high performance AID converter.

To develop high-performance D/A converters, it is necessary to develop a new cur-
rent copier which is error-free from charge-feedthrough effects. The accuracy of the con-
verter is expected to be the sum of the mismatch of components and the accuracy of the
dynamic calibration. For example, l6-bit accuracy of D/A converter circuit may be realized
by 8-bit accuracy of well-matched components and 8 bit accuracy with dynamic calibra-
tion. Hi gh-speed can be obtained by separating calibration from the output of the converter,

making the speed of the conversion determined only by the output unit.

122

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