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I‘HESIS
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12 0178 86 5977
LIBRARY

Michigan State
University

|\ \l

 

 

 

 

This is to certify that the

dissertation entitled

EFFICIENT TESTABILITY DESIGN METHODOLOGIES
FOR ANALOG/MIXED-SIGNAL INTEGRATED CIRCUITS

presented by

Cheng-Ping Wang

has been accepted towards fulfillment
of the requirements for

Ph. D. degree in Electrical Eng

 

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DATE DUE DATE DUE DATE DUE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1M mu

 

EFFICIENT TESTABILIT Y DESIGN METHODOLOGIES
FOR ANALOG/MIXED-SIGNAL INTEGRATED CIRCUITS

By

Cheng-Ping Wang

A DISSERTATION
Submitted to
Michigan State University
in partial fulfillment of requirements
for the degree of

DOCTOR OF PHILOSOPHY

Department of Electrical Engineering

1 997

ABSTRACT

EFFICIENT TESTABILITY DESIGN METHODOLOGIES
FOR ANALOG/MIXED-SIGNAL INTEGRATED CIRCUITS

By

Cheng-Ping Wang

More and more mixed-signal devices are being designed recently for the
applications of multimedia, wireless communication, and portable data systems. The
analog circuit technology conventionally employed for such applications has been
gradually switched to analog/digital mixed-signal circuit technology. Even though much
more complicated digital circuits have been widely used in the DSP-based mixed-signal IC,
analog circuits will remain for processing or interfacing analog signals. Integrating both
digital and analog on a single chip has improved performance and reduced board size and
cost. However, the increasing complexity of mixed-signal circuits drastically reduces the
controllability and observability of the circuit on the chip. As a result, testing of such
complex circuit becomes very difficult and expensive. Therefore, the goal of the thesis
study is to develop an efficient testability design system for analog/mixed-signal circuits so
that all designed circuits are easily testable.

The thesis study has developed efficient testability design methodologies and test-
ability enhancement methodologies. The developed design methodology defines a set of
fault types from circuit layout, technology data, and process defect distribution, and it gen-
erates a set of test vectors based on the parameter deviation bounds which are derived

from the design specification, discrete input set, and defined fault types. The test vectors

and parameter deviation bounds allow us to evaluate the fault coverage of a designed ana-
log circuit. This methodology was developed using the inductive fault analysis (IFA) tech-
nique. However, the IFA technique requires a tremendous amount of computational time
and thus it has been limited for small circuits. For reasonable large analog circuits, a hier-
archical testability design methodology is developed to reduce the computational com-
plexity. Basically, a designed circuit is decomposed into many components. The
components can be further decomposed until they can be handled comfortably by the [FA
technique. In other words, a circuit is decomposed as primitive cells and/or macros.

Based on the hierarchical fault macromodeling process, a hierarchical testability
design system, namely, PETOMIC (Packages for Enhancing Testability Of Mixed-signal
Integrated Circuit) is also developed. The system generates cell library, macro library, test
set, and evaluates the fault coverage. The system has been developed and implemented in
C language, Spice, and Matlab. The detail system development is discussed with examples
of generating a cell library of an Opamp and a macro library of a current copier.

Some testability enhancement methodologies have also been developed in this
study. Based on the given design specifications, a set of discrete inputs used for design
verification, and the fault types, a set of testability design rules is developed to ensure the
existence of the circuit parameter deviation bounds for these discrete inputs and for all fault
types. These parameter deviation bounds are used to generate test vectors. Thus, the
designed circuit can be easily testable. In addition, a high-accuracy current comparator is
developed as a built-in tester (BITER). The use of BITER not only enhances the testability,

but also simplifies the test generation process and reduces the test sequence length.

To my parents, brother and his wife.

iv

ACKNOWLEDGEMENTS

I sincerely thank Professor Chin-Long Wey, my thesis advisor, for his support and
valuable suggestions throughout this research. It has been a pleasure to work under his
supervision and I have certainly learn a lot from him. I would also like to express my grat-
itude to the members of my guidance committee, Dr. James Resh, Dr. Gregory Wierzba
and Dr. Chien-Peng Yuan, for taking time to serve in the committee.

I have to thank my fellow graduate students, Wei-Hsing Huang and Jin-Sheng
Wang. I got much inspiration from the discussion with them.

A special thanks goes to my parents, my brother and his wife for the support and
encouragement they have given me during the critical stage of my life.

A final note of appreciation must be sent to all the nice people who have ever

enriched my campus life while I stayed in Michigan State University.

TABLE OF CONTENTS

LIST OF TABLES .............................................................................................. viii

LIST OF FIGURES ............................................................................................. ix

Chapter 1 INTRODUCTION ......................................................................... 1
1.1 Objectives and Research Tasks ..........................................

1.2 Thesis Organization .............................................................. 9

Chapter 2 BACKGROUND ........................................................................... 11

2.1 Fault Definition ................................................................... 11

2.2 Test Generation of Switched-Current Circuits ..................... 14

2.2.1 Switched-Current Circuits ......................................... 14

2.2.2 Structures and Operations ......................................... 15

2.2.3 Fault Behaviors and Test Generation of an ADC ........ 20

2.3 Analog/Mixed-Signal Testing Schemes ................................. 23

2.3.1 Desi gn-for-Testability Techniques ............................ 23

2.3.2 BIST Designs ........................................................ 27

Chapter 3 FAULT MACROMODELING .................................................... 30

3.1 Fault Types in Switches .................................................... 31

3.2 Heuristic Fault Macromodeling Process .............................. 35

3.2.1 Example Circuit - Current Copier .............................. 36

3.2.2 Example Circuit - ADC ............................................ 42

3.2.3 Discussion ............................................................... 49

3.3 [FA-Based Fault Macromodeling Process ........................... 50

3.3.1 Fault Classification ................................................. 50

3.3.2 Testability Design Rules ......................................... 56

3.3.3 Test Generation and Fault Coverage ......................... 60

3.3.4 Example .................................................................. 61

3.4 Discussion ......................................................................... 72

Chapter 4 TESTABILIT Y ENHANCEMENT .............................................. 74

4.1 Hierarchical IFA-Based Fault Macromodeling ..................... 74

4.1.1 Macro Library ......................................................... 76

4.1.2 Fault Coverage Estimation ...................................... 82

4.2 Testability Design Rule ................................................... 87

4.2.1 Development ........................................................... 88

4.2.2 Discussion .............................................................. 91

4.3 High-Accuracy Built-In Tester ........................................... 91

4.3.1 Design and Operation ............................................. 94

4.3.2 Simulation Results ................................................. 98

4.3.3 Performance Analysis ............................................. 104

4.3.4 Built-In Tester and Test Sequence ........................... 108

Chapter 5 HIERARCHICAL TESTABILIT Y DESIGN SYSTEM ................. 111
5.1 CLG_Routine ...................................................................... 1 1 1

5.2 MLG_Routine ...................................................................... 128

Chapter 6 CONCLUSION ............................................................................ 137
6.1 Summary ............................................................................ 137

6.2 Future Work ......................................................................... 139
APPENDICES ................................................................................................... 141
REFERENCES ................................................................................................... 166

vii

LIST OF TABLES

Table 2.1 Fault types and expected outputs. .................................................. 21
Table 3.1 Defect and fault count distributions. .............................................. 69

Table 3.2 Defect and fault count distributions. (With inaccurate test instru-
ment) .............................................................................................. 70

viii

Figure 1.1
Figure 1.2
Figure 1.3
Figure 2.1

Figure 2.2

Figure 2.3

Figure 2.4
Figure 2.5
Figure 2.6

Figure 3.1

Figure 3.2

Figure 3.3

Figure 3.4

Figure 3.5

Figure 3.6

LIST OF FIGURES

Schematic diagram of a typical DSP-based mixed-signal IC. ......

Single stuck-at-fault-model-based testing in digital circuit.

0000000

Broad view of this thesis study.

.................................................................

Inductive fault analysis.

Current copier: (a) basic copier; (b) with feedback amplifier; and
(c) CMOS switch with a dummy switch. ........................................

An SI algorithmic ADC: (a) schematic diagram; and (b) simulation
results.

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

DSP-based IC with scan structures.

Test bus.

00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

BIST design of an ADC.

ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

Defects: (a) switch layout; (b) defected layout; and (c) summary of
defects and circuit fault.

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

(a) Simulation results of I-V plot of M1 with load lines for Sz; and
(b) fault behavior and switching sequence.

Built-in tester: (a) schematic; (b) switching sequence; and (c) fault
simulation results.

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

Test structure for SI algorithmic ADC: (a) schematic diagram; and
(b) comparator. ..............................................................................

Test sequence A: (a) fault behaviors; and (b) switching sequence.

Test sequence B: (a) fault behavior; and (b) type V82 fault. ......

13

16

18

24

26

26

32

37

43

45

47

Figure 3.7
Figure 3.8

Figure 3.9

Figure 3.10

Figure 3.11

Figure 3.12

Figure 3.13

Figure 3.14
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6

Figure 4.7

Figure 4.8

Figure 4.9

Figure 4.10

Figure 4.1 1

Step 1 of IPA-based fault macromodeling. .................................
Step 2 & 3 of IPA-based fault macromodeling. ..........................

Switches: (a) schematic; (b) fault model for voltage switch; and (c)
fault model for current switch. .......................................................

Relationship between parameter deviation and performance devia-
tion. .................................................................................................

Example for the definition of parameter deviation bounds. .......

Equivalent circuit of the portion including transistor and current
switch of the current copier, and its I-V characteristic. .................

Simulation results: (a) for f]; and (b) for f2. ..............................

Fault coverages with respect to accuracy of test instrument. .....
Computational complexities of [FA process. .............................
Concept of hierarchical fault modeling. ....................................
Cell library of hierarchical IFA-based fault macromodeling. .....
Macro library of hierarchical [FA-based fault macromodeling.

Fault equivalence. .........................................................................
Macro “current copier”: (a) layout; and (b) routing area. .........

Fault coverage for routing area: (a) due to etching defect; and (b)
due to extra defect. ........................................................................

Examples for the definition of parameter deviation bounds: (a) in 1-
dimension; and (b) & (c) in 2-dimension. .....................................

Current comparators: (a) in [52]; (b) in [60]; and (0) proposed
design. ............................................................................................

Current comparator: (a) schematic diagram; (b) switching
sequence; (c) small signal equivalent circuit when SI is off; and (d)

& (e) offset-compensated amplifier. ..............................................

Proposed current comparator: (a) parameter values of Figure
4.10(a); (b) parameter values for Figure 4.10(e); and (c) physical

51

52
54

57

57

62

67

71
75
77'
78
79
81

83
84
89

92

95

Figure 4.12

Figure 4.13

Figure 4.14

Figure 4.15

Figure 5.1
Figure 5.2
Figure 5.3

Figure 5.4

Figure 5.5

Figure 5.6

Figure 5.7
Figure 5.8
Figure 5.9
Figure 5.10

Figure 5.11

layout. ........................................................................................... 99

Transient responses: (a) during the compensation process; and (b)

during the comparison process. .................................................... 100
Simulation results: (a) Ix-Vy characteristic curve; (b) harmonic dis-
tortion; and (c) nonlinearity element Vn1(Ix) vs Ix & Vy .............. 101

Performance analysis: (a) Gaussian distribution of Vy; (b) statistical

confidence vs. window threshold voltage; and (c) statistical confi-
dence vs. resolution. ..................................................................... 106

ADC with built-in tester: (a) ADC; (b) with built-in tester; and (c)

window comparator. ...................................................................... 109
Structure of PETOMIC. ............................................................. 112
The use of defect generator in cell library establishing. ............ 113
Example of extraction file and K. ............................................... 115

Experiments for extract parameters from cell K, Opamp in this
example. ........................................................................................ 116

Example of prem.cir. .................................................................... 117

The use of fault behavior evaluator and fault type classification

environment in cell library establishing. ...................................... 120
Example of cell library. ................................................................ 121
Fault behavior display window. .................................................... 126
Summary of files used or generated in CLG_routine. ................ 127
Example of macro.cir. .................................................................. 129
Example of macro library. ........................................................... 131

(i

Chapter 1

INTRODUCTION

More and more mixed-signal devices are being designed recently for the
applications of multimedia, wireless communication, and portable data systems. The
analog circuit technology conventionally employed for such applications has been
gradually switched to analog/digital mixed-signal circuit technology. Figure 1.1 shows a
typical digital signal processing (DSP)-based mixed-signal integrated circuit (IC). The
digital area typically takes more than 60% of the total [C area [1]. The main analog and
mixed-signal components tend to be analog-to-digital converter (ADC), digital-to-analog
converter (DAC), phase-locked-loop (PLL), operational amplifier (OP-amp), and filters.
Even though much more complicated digital circuits have been widely used in the DSP-
based mixed-signal 1C, analog circuits will remain for processing or interfacing analog
signals [2]. Integrating both digital and analog on a single chip has improved performance
and reduced board size and cost. However, the increasing complexity of mixed-signal
circuits drastically reduces the controllability and observability of the circuit on the chip.
As a result, testing of such complex circuit becomes very difficult and expensive.

In mixed-signal circuits, the digital and analog components are tested separately.
Procedure and equipment for testing stand-alone digital or analog chips have been well-

established and implemented. However, manufacturers have found the costs associated

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Analog
In ts Analo
pu g
DSP
Analog Core
Outputs Analog DAC
_p.
PLL & Digital
Timing CKT. Interface
. . v
Tmung Digital Signals

Figure 1.1 Schematic diagram of a typical DSP-based mixed-signal IC.

with high-volume production of mixed-signal ICs are strongly affected by the cost of
testing, where the analog circuit testing dominates. Considerable effort has been devoted to
identify the causes of the analog test complexity [3]. Unlike digital circuits, analog circuits
do not have the binary distinction of pass and fail. The time and voltage continuous nature
of their operation make them further susceptible to defects [4-6]. Analog systems are often
nonlinear, thus their performance depends heavily on circuit parameters. Process variations
within allowable limits can also cause unacceptable performance degradation.

In digital circuits, there exists a wide range of fault models [7]. These models or
abstractions form the basis of representing the faulty circuit behavior as well as the test
generation. Given a set of test vectors, if the simulated output (signature) of a fault differs
from that of the good circuit, then this set of test vectors can detect the fault. This testing
process is called fault-model-based testing in which the fault definition and test generation
are the major tasks. Thus, simulation before manufacture can be used to determine a set of
test vectors for post-manufacture testing. Similar analysis can be done to determine the
testability of a design. Figure 1.2 shows an example of the fault-model-based testing
process for an AND gate. For a stuck-at one fault (S/ 1) on input of the AND gate, we can
use test input {0,1} to distinguish the faulty circuit under test (CUT) from good one by
comparing their outputs.

Analog testing is usually a specification-driven process. It tests a circuit for all
specifications both during wafer-probe and final tests. However, given a set of
specifications for a circuit, a basic question is [8]: Are these specifications necessary and
suflicient? In fact, insufficient specifications may result that some faults cannot be detected

properly, while unnecessary specifications cause the increase of the complexity of test

/ "P > Single stuck-at-fault model
’1,

 

 

 

  
 

 

 

 

/
Testset ,___J (__.___‘
L I 311 w I
I 0: fl
Ic1) l
1.. ______
Test output
I' ----- ‘1
l
I
——l"‘

 

I... _____

‘ J
Good circuit

Figure 1.2 Single stuck-at-fault-model-based testing in digital circuit.

generation process. Therefore, analog testing may be simplified if the specification-driven
process can be mapped to a fault-model-based process [9]. However, the effectiveness of
applying digital fault models on analog circuit is questionable.

The similar stuck-at fault model has been applied for testing analog circuits. In
order to enhance the reliability of ADCs for real-time applications, a CMOS switched-
current algorithmic ADC which possesses the concurrent error detection (CED) capability
was developed in [10-15] to detect transient faults and permanent faults. Based on single
stuck-at fault model on the switching elements, the fault behaviors of the A/D converter
(ADC) were reported. It was assumed that faulty switched are either permanently stuck-at-
ON state (S/ON) or stuck-at-OFF state (S/OFF). The failure of other components can be
modeled as the fault of the associated switch. Thus, the converter can be fully testable. Due
to the simplicity of the generated test patterns for the ADC [10-15], a built-in self-test
(BIST) design of the ADC is reported in [16] which demonstrates the self-testability with
a simple BIST structure. The above studies have shown that the failure of non-switch
components can be modeled as the fault of the associated switch. Thus, the converter can
be fully testable, but only for stuck-at faults. As it will be discussed later in this thesis study,
our simulation results will show that the stuck-at faults in a CMOS switch are about 70%
of the total circuit faults. This implies that a 30% of the total faults are not detectable in
those studies, and they are referred to as parametric faults. Therefore, to enhance the
testability, the first major task is to develop an efficient and effective fault model for analog
circuits.

The second major task is to develop test generation and fault coverage evaluation.

Most analog circuits are presently designed without considering the testability. More spe-

cifically, a set of nominal parameter values and the associated tolerances are selected to
meet a given set of design specifications. Therefore, a designed circuit meets the specifi-
cations, if all parameters are selected to be within the tolerances. In many circuit designs,
however, a circuit may still meet the specification even if a parameter deviation is far
beyond the tolerance. Testability design methodologies have been developed successfully
for digital circuits, and its success is attributed to the well-defined fault models and test-
ability design rules. Therefore, based on the fault models defined in the first task, it is nec-
essary to develop certain testability design rules for the designed analog circuits in order
to make it easily testable, i.e., the test vectors can be easily generated.

In summary, the goal of this thesis study is to develop an efficient testability design

system for analog/mixed-signal circuits so that all designed circuits are easily testable.

1.1 Objectives and Research Tasks

The approaches for developing an efficient testability design system for analog/
mixed-signal circuits include: (1) the development of efficient testability design
methodologies; and (2) the development of testability enhancement methodologies. Figure
1.3 illustrates a broad view of the thesis study. The testability design system develops an
analog circuit in two different cycles. In the design cycle, based on design specification, a
set of testability rules is adopted to make the designed circuit easily testable. In the testing
cycle, based on the process data and design circuit layout, the fault models of the design
circuits are defined using an inductive fault analysis (IFA) technique [17]. Based on the
defined fault models, test generation process is invoked to generate a test set and evaluate

the fault coverage of the design circuit using the generated test set.

 
  
 
 

 
    

Desi . .
S I cificgittlions Hierarchical

Fault Macromodeling

  

High—accuracy
Built-in Tester

    

Testability
Desi ; Ru e

IC Design Cycle

 
 

IC Testing Cycle

Figure 1.3 Broad view of this thesis study.

The IFA technique has been used to efficiently generate the layout defects and fault
types. However, its computational complexity is always a major problem, and it is only
applicable to small circuits. For reasonably large analog circuits, a hierarchical fault
macromodeling process should be developed so that a large circuit can be hierarchically
decomposed into smaller macros or primitive cells which can be handled comfortably by
the IFA technique.

As mentioned, analog circuits are designed with a set of testability design rules. The
rules ensure that a test set can be generated to test the designed circuit. However, the rules
do not guarantee that the test set be generated at low cost. Thus, testability enhancement
methodologies should be developed to reduce the number of hard-to-test faults and thus
decrease the test generation cost. ICs are usually tested with expensive ATE (automatic test
equipment). In addition to the instrument cost, the distortion caused by the interface
between internal circuitry and external test equipment is always a severe problem in the IC
testing. Therefore, the use of a built-in tester (BITER) not only prevents the distortion
problem, but also simplify the test generation process.

In summary, the objectives of the thesis study are to develop efficient testability
design methodologies and testability enhancement methodologies for analog/mixed-signal
circuits. The major research tasks include the development of: (a) an [FA-based fault
macromodeling process; (b) a hierarchical fault macromodeling process; (c) test generation
and fault coverage evaluation processes; and (d) built-in testers. The final goal is to develop
an efficient and effective testability design system which produces easily testable analog

circuits.

1.2 Thesis Organization

The dissertation is organized as follows: Chapter 2 reviews the background
required for the thesis study. The [FA technique [17] used for modeling digital circuits is
first discussed. Then, the test generation and fault coverage of the switched-current CMOS
ADCs [IO-15] are briefly described. It will include the salient features of switched—current
circuits [18-22,23], the designs and operations of current copiers and CMOS ADCs, the
fault behaviors, test generation, and fault coverage evaluation. Finally, some design-for-
testability schemes developed for analog/mixed-signal circuits are reviewed.

Chapter 3 presents the developed fault macromodeling process. The process
includes two major tasks: Fault-Type definition and Test Generation. Two macro fault
macromodeling processes have been developed: heuristic process and [FA-based process.
The former process defines the fault types from the circuit layout, technology data, and
possible defects, and generates test set based on the fault types. To systematically generate
practical fault types, the latter process defines the fault types from the circuit layout,
technology data, and the defect distribution from real manufacture process. The fault types
are ranked in terms of their occurrences and the higher ranked fault types are used to
generate test set. To demonstrate the effectiveness of the developed fault macromodeling
process, both current copiers and switched-current ADCs are used as example circuits.

Chapter 4 presents some testability enhancement methodologies. To reduce the
computational complexity of the fault macromodeling process with the IFA technique, a
hierarchical fault modeling process is developed. A circuit is partitioned as primitive cells
and/or macros. The procedures for generating cell library and macro library will be

presented. Based on both cell library and macro library, the test set for the target circuit is

10

generated and the fault coverage of the generated test set is evaluated. To simplify the
testability design process, the refinement of the set of testability design rules presented in
Chapter 3 will be presented. Finally, a high-accuracy CMOS current comparator is
introduced as a built-in tester. The detail design and operation of the tester will be discussed
with the simulation results and performance analysis. In addition, this study also addresses
the design trade-off between the accuracy of the tester and test sequence length.

Based on the hierarchical fault macromodeling process presented in Chapter 4,
Chapter 5 presents a hierarchical testability design system, namely, PETOMIC (Packages
for Enhancing Testability Of Mixed-signal Integrated Circuit). The system generates cell
library, macro library, test set, and evaluates the fault coverage. The detail system develop-
ment is discussed with examples of generating a cell library of an Opamp and a macro
library of a current copier. The system demonstrates the feasibility of the hierarchical fault
macromodeling process.

Finally, Chapter 6 summarizes the thesis study and gives a concluding remark and

some future research directions.

Chapter 2

BACKGROUND

Analog circuit testing process can be simple and effective if the specification-driven
test process can be mapped to a fault-model-based testing process. Fault definition and test
generation are two major tasks in a fault-model-based testing process. Section 2.1 reviews
the fault definition and IFA technique. Section 2.2 discusses a test generation process
developed in [12,14,15] for switched-current (SI) ADCs. This section briefly describes the
importance of SI circuits, the structures and operations of current copiers and an ADC, and
the fault behaviors and test generation of an ADC. Finally, some analog/mixed-signal

testing schemes are presented in Section 2.3.

2.1 Fault Definition

A number of factors contribute to the failure of a fabricated circuit. Process distur-
bance, which is essentially random in nature, result in either global or local defects [24-
27]. Typically, local defects cause structural deformation at the physical level. The defor-
mations that alter the circuit topology (hard shorts, opens) create catastrophic faults, while
that do not alter the circuit topology (component deviation) or the DC circuit connection
(capacitance bridges) appear as non-catastrophic faults. Catastrophic faults result in com-

plete circuit malfunction. Circuit failures are marginal in the presence of non-catastrophic

12

faults. On the other hand, global defects result in either obvious failures (spotted by virtual
inspection) or, subtle parametric faults. The deviation of process parameters beyond toler-
able limits rcsults in parametric faults which cause marginal failures of some design spec-
ifications [24].

Inductive fault analysis (IFA) [17] is a common technique for deriving a graded list
of the most likely faults from a description of circuit layout, process parameters, and
defect statistics of the fabrication process. The IFA procedure is comprised of three steps,
as illustrated in Figure 2.1. The first step includes the defect generation and the defect-to-
fault translation. Based on the defect distribution obtained from an actual manufacture
process, a defect generator generates a collection of defects, and it injects these defects
into the circuit layout. Note that the manufacture process statistics contains the defect den-
sity per area and the distribution of defect size. Once the defective layouts are generated,
and their associated circuit parameters are extracted by a circuit extractor. This step trans-
lates the defects in the layout level to faults in the circuit-level. VLASIC [28] is a software
tool commonly used for both defect generation and fault translation for catastrophic faults.
The second step defines the macro-level fault behaviors of the faulty circuit parameters.
The circuit parameters extracted from the defective layout are simulated by a circuit simu-
lator, SPICE, to generate macro-level fault behaviors such as output impedance, DC bias
voltage on macro output or frequency response, etc.

Step 3 groups the fault behaviors into a collection of fault types, where the fault
types may be ranked according to the number of their occurrences. This generates a list of

fault types.

13

 

 

 

Current Technology Defect
Layout Data Statistics

 

 

 

 

 

 

 

 

 

     

  

Map Physical defects list
to circuit fault list

 

 

Step 1 [ Defect Generation 7 Defect Simulator
6 (e. g. VLASIC)

 

 

Defect-to-fault Translation

 

 

 

 

(Circuit fault extraction)
L List of circuit faults

 

Evaluate effect of faults on circuit— Circuit Simulator
Step 2 level operation ‘ lag. SPICE)

 

L List of fault behaviors

Step 3 Classify the fault behaviors into fault
types and rank the fault types.

1

List of fault types

 

Figure 2.1 Inductive fault analysis.

14

2.2 Test Generation of Switched-Current Circuits

There exists many kinds of fault models in digital circuits. These fault models
form the foundation of representing the faulty circuit behavior as well as the test genera-
tion. For given test vectors, if the simulated output (signature) of a faulty circuit is differ-
ent from that of the good one, these test vectors can detect the fault. Thus, simulation
before manufacture can be used to determine a set of test vectors for post-manufacture
testing. In this section, a switched-current ADC is used as an example to demonstrate the

test generation process.

2.2.1 Switched-Current Circuits

Low-voltage/low-power circuit design is strongly needed for both analog and digi-
tal circuit in portable data systems to increase operation time and to decrease the number
of batteries and the weight, volume, and operating temperature of the equipment. With the
trend that analog-digital interfaces are incorporated as a cell in complex mixed-signal inte-
grated circuits, the use of the same supply-voltage for both analog and digital circuits can
give advantages in reducing the overall system cost by eliminating the need of generating
multiple supply voltages with dc-dc converters. Therefore, to be compatible with low-volt-
age systems, analog signal processing components must be able to operate at supply volt-
age 2-3 V. Reducing power dissipation associated with high-speed sampling and
quantization is another important key factor.

Traditionally, the switched—capacitor (SC) technique has been employed exten-
sively in the analog interface portion of mixed-signal designs. However, SC circuits are

not fully compatible with digital CMOS processing technology and, as the technology

15

advances further, the drawbacks of SC technique are becoming more significant. SC tech-
niques traditionally require high quality linear capacitors, which are usually implemented
using two layers of polysilicon. The second layer of polysilicon used by SCs is not needed
by purely digital circuits and may become unavailable as process dimensions shrink to the
deep submicron range. The trend towards submicron processes is also leading to a reduc-
tion in supply voltages, directly reducing the maximum voltage swing available to SCs
and consequently reducing their maximum achievable dynamic range. With lower supply
voltages, the realization of high-speed high-gain operation amplifier becomes more diffi-
cult.

Recently, a class of analog circuits wherein current rather than voltage is the pri-
mary signal medium has been received considerable attention. The use of current-mode
creates a potential for speed improvement because stray-inductance effects in such low-
impedance switched-current (SI) circuits are much less severe than those in high-imped-
ance SC circuits. The SI technique couples itself well with the down-scaled CMOS tech-
nology, where transistors with a high cut-off frequency are available, meaning a high
calibration speed. In addition, highly-linear capacitance is not needed for high accuracy
analog signal processing circuits using SI technique. Thus, the same low-cost digital
CMOS process for the digital portion of mixed-signal circuits can also be used for the ana-

log portion with SI technique [18-20].

2.2.2 Structures and Operations
Current copier is the basic building block of switched-current circuits. The perfor-

mance of SI circuits is determined by the current copiers they employ. A copier, as shown

l6

/ x '
82 S2 ___
”‘ i7 F b“
b c 53
(b

 
 

 

CI

)

Vgn ir—

dummy
switch

(:3. {uni-"H:
J M1 T :T m 11v.
VF M3. J— EL ‘54} ii

I; LE{%C

 

 

 

 

 

 

 

 

 

 

 

 

 

Vgp I

(C)

Figure 2.2 Current copier: (a) basic copier; (b) with feedback amplifier;
and (c) CMOS switch with a dummy switch.

17

in Figure 2.2(a) [21], is comprised of S1 and 82, the current-storage transistor M1, and the
holding capacitor C. To copy the current Iin, S1 and 82 are turned on for feeding [in to M1
and C. The capacitor is charged up to whatever gate voltage is needed by M1 to support a
current equal to Ii". When 81 and S2 are turned off, the copier cell is disconnected from the
current source; thereafter the copier cell is capable of sinking a current Iin when connected

to a load.

Copier suffers from two major error effects: (1) the nonzero conductance of M1 and
(2) charge-injection of 82 [22]. The non-zero output conductance results from the channel
length-modulation effect and the drain-gate capacitive coupling of M1. The charge-
injection error effect is caused as follows: When the gate voltage of 82 goes down during
the tum-off transient, the charge held in the transistor realizing S2 will be forced to leave.
Since one end of S2 is connected to the gate node of M1, some charge of 82 will be dumped
to the gate of M1 and change the voltage across C. As a result, the current held in M1 will
deviate from Ii“, and charge-injection error results. The error effect due to the nonzero
conductance of M] can be alleviated by using a negative feedback structure, as shown in
Figure 2.2(b), where an amplifier is inserted between the drain and the gate of M1. On the
other hand, the charge-injection error effect can be reduced by either increasing the
capacitance C, or the use of CMOS switch with a dummy switch, as shown in Figure 2.2(c)
[29-30].

Figure 2.3 illustrates an S1 algorithmic ADC that combines current mode and
dynamic techniques [23]. This converter does not rely on high gain amplifiers or well-
matched components to achieve high resolution and it’s inherently insensitive to the

amplifier’s offset voltage. This converter is comprised of two NMOS current copiers, one

1 C3
S61P1——7—_— Comparato

.L
ATmplifi 1
IS

Com arator
_° Outgut

(to latch)

 

 

 

 

 

S 1 510 SZ S4
IIN IREF N1 S
IT’ |
IC' I
(a)
ls; bit bit
200uA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

lOmsec 20msec 30msec 40msec

(b)

Figure 2.3 An SI algorithmic ADC: (a) schematic diagram; and

(b) simulation results.

l9

PMOS copier, an op-amp, and a current comparator. The conversion starts sampling the

input cunent and holding it in P1 by turning on S], 86, and S7, and converting for the most
significant bit (MSB) of an input current IIN by first switching on S6, 82, and S3 to cause
the current in N1 to be set to IIN. Once the current in N1 is held, S2 and S3 are switched off
while S4 and S5 are on to copy IIN to N 2. The currents stored in N1 and N2, twice the input
signal, are then loaded into P, by turning off S] and 85 while switching on 82, S6, and S7.
After P1 is set, S2, S4, and S7 are turned off, and Sm is turned on, it allows the comparator
to sense the current imbalance, and determines if the signal, 21m, is greater than Inf. If the
signal exceeds the reference, the MSB will be a “1” otherwise it will be a “O”. This com-
pletes the conversion for the MSB.

The remaining (N-l) bits are then converted in the same manner. The signal held in
P1 is loaded to N1 by turning on S6, S2, and S3. If the preceding bit was a “1”, S10 is also
turned on to subtract the reference from the signal in P1. On the other hand, if it was a “0”,
310 is off so that the signal remains unchanged. Once N1 is set, N2 is set by the same pro-
cedure. The signal is then doubled and stored in P1. Finally, it is compared with the refer-

ence. The sequence is repeated until the desired resolution is achieved: and the end of
conversion pulse is then generated to signal the end of conversion. The converter needs 4N
clock cycles for and N-bit conversion [29,31].

The circuit has been implemented and simulated using MOSIS 211m CMOS pro-
cess parameters, where supply voltages i2.5V are used [29]. Figure 2.3(b) shows the
pspice simulation results for the currents held in the PMOS copier at each conversion

cycle, where an input currents IIN=100ttA is applied. The results show that the converter

20

achieves a 11-bit resolution. The results also show that the sampling rate and resolution
can be improved. However, the performance improvement is not of primary concern in
this study. The circuit is implemented to demonstrate and endorse the correctness of our

fault simulations.

2.2.3 Fault Behaviors and Test Generation of an ADC

Although mismatched components are allowed in the ADC of Figure 2.3(a), the
converter is still susceptible to faulty switching elements. Any faulty switching element
may result in an incorrect converted data. Based on the single stuck-at fault model com-
monly employed for digital test generation, the implementation [12,14,15] assumes that
only one faulty switch occurs at a time and the faulty switch is permanently stuck-at ON
state (S/ON) or OFF state (S/OF F). That study generates test signals to completely test the
ADC.

The analysis of the faulty switches in the ADC revealed that, due to the fault equiv-
alence, the fault behaviors can be classified into three types: Type I fault behavior occurs
when the faulty switch results in the same conversion output regardless of the values of the
input current. Switches SI, S2, S4, S7, and S10 being S/ON and S], 82, S4, S6, and Sm
being S/OFF illustrate this fault behavior: Type 2 fault occurs when the faulty switch ren-
ders the conversion output dependent on the initial condition of the active capacitors.

Switches S3, 35, and 87 lead to this condition when S/OF F : and Type 3 faults makes the
result of the conversion process dependent on the CMOS structure PllN 1 (or P1/N2) when
S3 (or 55) is being S/ON. Throughout the next analysis, 11)] (1va or 1N2) will denote the

current held in P, (N, or N2).

21

Table 2.1 Fault types and expected outputs.

 

 

 

 

 

F lt T Input Current Expected Output
au ypes To Be Converted Bit Pattern
Type IA xx...xx 00 ...... 00
Type 1B xx...xx 11 ...... 11

00.00 0..01x x
Type 2
11...11 1..10x..x
lxx ...... x
Type 3 xx...xx x xlx x

 

 

 

 

22

More specifically, consider the case when S] or S6 is S/OF F, the input current will
not be copied into P1; this is effectively equivalent to an input current of zero. 310 being S/
OFF leads to the current in P1 being compared to zero instead of Inf. Hence conversion

results in a string of ones. For simplicity of this discussion, Type 1 faulty elements are dis-
tinguished as Type IA if they result in a string of zeros, and as Type 13 if they produce a
string of ones. The detailed fault behaviors for various fault types can be found in
[12,14,15].

Table 2.1 summarizes the expected output bit string for each type of faults. A
string of zeros is expected in the presence of a Type IA fault for applying any input cur-
rent to the converter. Similarly, a string of ones is expected for Type 1B fault. Thus, two

test currents, IT1=0 and IT2=Iref, can detect both types of faults. More specifically, a bit
string of zeros is expected when the test current IT1=0 is applied to a fault-free converter.
Thus, the test current IT1=0 detects Type 1B faults. Similarly, the expected bit string of
ones for 1T2=Iref detects Type 1A faults. For Type2 faults, the application of IIN=O results

in a bit-string pattern of O..01x..x. This implies that the expected bit string of zeros for the

test pattern IT1=0 detects the faults. On the other hand, a bit pattern of 1..10x..x is pro-
duced when IIN=Iref is applied. Thus, the expected bit string of ones for the test current
I'I‘Zzlref, detects such faults. Finally, in the presence of a Type 3 fault, a bit string contain-
ing at least a l is generated and the fault can be detected by the test current 111:0. This
concludes that both test currents, IT1=0 and Isl-film, detect all single stuck-at faults at the

switching elements of the ADC. If fault coverage is defined as the ratio of the number of

faults can be detected over the total number of faults in that circuit, then the converter is

 

C11

C01

23.

Sign
digit
incre
1601's
3.4m
test d;
1W0 3‘
free. I
(ASR,
data. a
Mile ;

Circuit 1“

23

fully testable with respect to single switching element faults using these two test currents.

2.3 Analog/Mixed—Signal Testing Schemes

Design for testability (DFI‘) techniques and methodologies as well as built-in self-
test (BIST) structures have been successfully developed and implemented for digital
circuits [32,7], they are recently extended to mixed-signal circuits to increase both
controllability and observability. This section reviews the development of DPT techniques

and BIST structure.

2.3.1 Design-for-Testability Techniques
Conceptually, testability can be considered as the ability to control and observe
signals at the circuit (internal) nodes. Given the complex chip in Figure 1.1, analog and
digital blocks are generally tested separately. Each block is isolated with a scan path to
increase both controllability and observability [33,34]. A scan chain using digital shift
registers is added to the interface between the ADC/DAC and DSP core, as shown in Figure
2.4(a), where each register is connected to a node to be accessed. The scan chain allows the
test data to be simultaneously loaded to the register and sequentially shifted out, where only
two additional pins required for scan-in and scan-out to ensure the scan chain to be fault-
free. The same scan design concept can be extended for analog block. Analog shift registers
(ASRs), realized by sample/hold (S/H) circuits, can be used to load and shift out the test
data, as shown in Figure 2.4(b) [35]. A switched-capacitor (SC) S/H circuit was used to
realize the shift register for voltage test data measurement, while current copier, as S/H

circuit in switched-current (SI) technique, implements for current test data measurement

24

 

 

  

 

 

 

 

 

ADC DAC I ILJU'I; I
Scan-in Tr , Scan-out
. . l Scan-in Scan-out
Digital I
(b)
(a)

Figure 2.4 DSP-based [C with scan structures.

25

[36,37]. For voltage test data measurement, each unit (corresponding to a test point) of the
scan structure requires a test-point buffer and an ASR. The test-point buffer is used to
isolate the test circuit from the UUT (Unit Under Test) so that it will not affect the voltage
level at the test point during the sampling period. The buffer is implemented by a voltage
follower that has a very high input impedance and a very low output impedance. The scan
structure allows parallel of loading the test data and serially shifting them to the output
buffer for circuit testing and fault diagnosis. The scan chain also ensures the testability of
the analog shift register, i.e., the scan structure is self-testable. Results show that high-
accuracy, high-linearity, and high-speed performance can be achieved by the analog shift
registers. Connecting all shift registers as scan chain works perfectly in digital circuits,
however, the offset voltage in each analog SC S/H circuit may be accumulated to a huge
error. This has motived the development of an alternative structure using analog
multiplexers [36] which alleviate the error effects. The design concept of combining analog
multiplexing and demultiplexing to analog inputs and outputs has been extended to develop
analog test bus, as shown in Figure 2.5 [38]. It has also further extended as the IEEE 1 149.4
standard for boundary scan design. Scan structures are well-suited for those designs which
have insufficient probing pads, and have been applied to board- and system-level design to
offset the hardware overhead. However, it may be applied in circuit-level design if the
hardware overhead can be reduced.

In addition to controllability and observability, fault coverage is also a very important
testability measure in digital testing. Fault coverage is a measure of completeness in testing.
Instead of number of faults detected, the term fault coverage in analog testing should be:

how many parameters should be tested to ensure adequate performance in the intended

TI

PI

 

    
 

Filter

 

 

Pl: Primary Input
PO: Primary Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Tl: Test Input
TO: Test Output

 

 

Digital Output

 

 

 

 

 

 

 

Figure 2.5 Test bus.
Inputs TE (Test Enable)
Multiplexers F— Test
TG Generator
. . Current-Mod
Timing
Circuit Circuitry
—U
ADC
Under Output
Comparator
Test
//
—D
oc > El
Error
”Outputs lndrcator

 

 

Figure 2.6 BIST design of an ADC.

27

application. The concern is which parameters to test. Analog circuits have many parameters
to be tested, but only some parameters, referred to as critical parameters, may significantly
affect the circuit behavior. The error effect due to the variations of such parameters may
cause a system failure. Thus, it is desirable to investigate the relationship between
parameter variation and system failure, and to further identify the critical parameters. The
set of critical parameters should be minimal in order to simplify the testing/diagnosis

process.

2.3.2 BIST Designs

Since most analog components in mixed-signal circuits are used for processing and
interfacing analog signals, pin overhead becomes an important issue. A number of analog
BIST structures have been presented [39-49,31] to enhance the testability and fault
diagnosability of analog circuits. The major design issues include the hardware and pin
overhead, self-testable capability of the added hardware, and performance degradation. A
BIST structure of a digital circuit, as shown in Figure 2.6 [31], is comprised of five major
parts: Test Generator (T G), Input multiplexers (INMUX), U UT, Output Comparator, and
Timing Circuitry. The INMUX selects the input signals either from the normal input signals
during the operation mode, or from the test signal generated from TG during the test mode.
The timing circuitry is used to synchronize the entire operation. Two extra pins, test enable
(TE) and error indicator (El), are needed.

In [31], the single stuck-at fault model was assumed. A fault which occurs at any
components in the BIST structure causes an error and will be indicated by El. By faults, we

mean the stuck-at ON/OFF faults at all switching elements in the converter circuit and the

28

stuck-at 0/1 faults at the D-input and Q-output (denotes as Q0) of the flip-flop, TS, XO,
TE, and E1. The self-testing process starts with checking the latter faults, and then testing
the former faults in the converter circuit.

Checking the latter faults is conducted by turning on the power and resetting the
flip-flop to a 0. The test enable signal TE is changed from a 0 to a l, and it is expected that,
for a fault-free AND gate, the signal E1 is also changed from a 0 to a l, where the signal TS
is set to a 1. Consequently, an unchanged signal EI=1 implies that a stuck-at-l (s-a-l) fault
occurs at E1 or TE. On the other hand, an unchanged signal EI=0 indicates the occurrence
of either a s-a-O fault at TE, EI, TS, or X0, or a s-a—l at QO. Note that the s-a—l fault at QO
also implies that the flip-flop fails to perform the reset function. After passing the above
test, the signal TS is set to a 0 and the signal TE remains as a 1, hence, the signal E1 is
expected to be a 0. Therefore, an unexpected EI=1 implies that a s-a-l fault occurs at TS,
QO, E1, or XO. Therefore, with these two tests, the only undetected stuck-at 0/1 faults
include the s-a-O fault at Q0 and the s-a-O/l fault at the D-input of the flip-flop which will
be tested later.

By Table 2.1, a converted bit string of zeros is the result of Type IA faults and a
string of ones for Type 18 faults; a bit string of 0...01x...x for Type 2 faults with the
application of IIN=0 and a string of 1...10x...x for Type 2 faults with the application of
IIN=Iref; and a bit string having at least one 1 for Type 3 faults. Therefore, to test the
converter circuit, we first apply the zero test current, where TS is set to a 0, the flip-flop is
reset, and TE remains as a 1 for the test mode. In this test, the signals EI=0 and XO=1 are
expected for a fault-free circuit. An unexpected EI=I implies the occurrence of a Type 13,

Type 2, or Type 3 fault, or a s-a—l fault at the D-input of the flip-flop. After passing the test,

29

the test current [ref is applied, where TS is set to a 1, the flip-flop is reset, and TE=1. This
test is also expected to produce EI=O. An unexpected EI=1 implies the occurrence of either
a Type IA fault, or a s-a-O fault at QO or D-input of the flip-flop.

This concludes that the BIST structure is fully testable for all single stuck-at non-

redundant faults [31].

Chapter 3

FAULT MACROMODELING

This chapter presents two fault macromodeling processes that map the
specification-driven analog testing process to a simple fault-model-based process:
Heuristic [29,30,50] and [FA-based [51]. The former process defines the fault types from
the circuit layout, technology data, and possible defects, and generates test set based on the
fault types. To systematically generate practical fault types, the latter process defines the
fault types from the circuit layout, technology data, and the defect distribution from real
manufacture process. The fault types are ranked in terms of their occurrences and the higher
ranked fault types are used to generate test set.

Switches are commonly used in both SI and SC circuits. According to the func-
tionality, two types of switches, voltage switch and current switch, can be identified. Sec-
tion 3.1 describes some defects and circuit faults of both switches and illustrates their fault
behaviors and fault models. Based on the circuit faults, Section 3.2 presents the heuristic
fault macromodeling process. Two example circuits, current copier and ADC, are used to
demonstrate the process. Section 3.3 introduces the developed [FA-based fault macro-
modeling process. Finally, summary and concluding remark for the fault macromodeling

is discussed in Section 3.4.

30

31

3.1 Fault Types in Switches

Current switches have been commonly used in SI circuits, while Voltage switches
are used in both SC and SI circuits. As their names imply, the current switch passes current
signal, while the voltage switch passes voltage signal. For example, as shown in Figure
2.2(b), $2 is used to pass the currents held in copiers, 81 used to pass (IN. Thus, they are all
implemented by current switches. On the other hand, S3, used in copier for calibration, is
implemented with voltage switches.

Figure 3.1(a) shows the physical layout of the switch in Figure 2.2(c), where the
MOSIS 2pm CMOS technology, a two-metal, single polysilicon, and n-well, was assumed.
Figure 3.1(b) gives five examples of process defects which are significant and cause the
circuit to be malfunction. The faults due to these defects are summarized in Figure 3.1(c).
In addition, other process defects may also cause faults, such as variations of channel size,
errors in doping concentration, errors in the thickness of the gate oxide, etc.

Consider a voltage switch. Let Tclk be the clock pulse width applied to the switch.
When a fault-free switch is on, the time constant ton=RonC should be smaller than Tclk for
sampling the input voltage signal. On the other hand, when the switch is off, the maximum
leakage current [leak should be tolerable, i.e., [leak < 1101. The on-resistances of both PMOS
and NMOS transistors in the switch should be connected in parallel when the switch is on.
As shown in Figure 3.1(c). the presence of the Type fl defect causes a floating drain/source
in PMOS/NMOS transistors. This results in an increase of on-resistance, while the off-
resistance remains the same. Therefore, the increase of on-resistance due to this defect will
cause Ton>Tclk- This implies that the capacitor C samples and holds a unsettled, incorrect

input voltage when the switch is on. Note that the fault does not affect the switch when it

32

 

 

 

 

 

 

 

 

 

(b)
Defect Circuit fault defect type
a floating drain/source Type f1
Break of metal _ . .
disconnects the swrtch’s input/output Type 12
a floating ate may tra some
amount of3 charges on e gate Type f3
Break of gate isolates the gate of PMOS transistor f3‘P
polysilicon isolates the gate of NMOS transistor f3-N
shortens the channel width. Type f4
D2232; lite E ion increases the channel impedance Type )5

 

(C)

Figure 3.1 Defects: (a) switch layout; (b) defected layout;
and (c) summary of defects and circuit fault.

 

 

33

is off. A Type f2 defect is equivalent to a S/OFF fault in the switch, in which both the on-
and off-resistances are sufficiently large. In other words, when the switch is on, the increase
of on-resistance due to this defect will cause ton>Tclk, but the off-resistance is not affected.

In the presence of a Type f3 defect, the gate of an NMOS transistor is isolated and
traps some charges, either positive or negative charges. Three cases can be identified for
trapping a positive charge: (1) for larger positive charges, it causes a decrease of off-
resistance, but the on-resistance remains the same; (2) for large negative charges, it causes
an increase of on-resistance, but the off-resistance remains the same; and (3) for a small
amount of positive or negative charge, it causes a decrease of off-resistance and an increase
of on-resistance. Similarly, isolating the gate of PMOS transistor has the same fault
behaviors but exactly opposite to those of NMOS transistors. The first case causes
Ileak>ltob while the second case results in Ton>Tc1k- Case 3 includes both defect effects and
causes a larger time constant ton and an intolerable leakage current. Types f4 and f5 defects
cause an increase of on-resistance. Based on the fault behaviors of the defects, the

following three fault types are concluded,

Type VSI fault: causes an intolerable time constant “:0n and
a tolerable leakage current;

Type V52 fault: causes a tolerable time constant ton and
an intolerable leakage current; and

Type VS3 fault: causes an intolerable time constant ton and

an intolerable leakage current;

34

Note that the charge-injection error occurs at the moment when switch is turned off. Since
the charge held by the capacitor changes when switch state is changed, an additional fault

type should be included.

Type VS4 fault: cause excess charge flows out of switch

at the moment when switch is turned off.

Consider the fault models of a current switch. Let Vmax be the maximum voltage
across the switch. In general, Vmax=VDD (power supply voltage). For a fault-free current
switch, its on-resistance Ron must be sufficiently small so that the maximum switch current
(=Vmax/Ron) is larger than the maximum input current, IIN(maX)’ and its off-resistance Roff
has to be sufficiently large so that the maximum leakage current [leak (=Vmax/Roff) is
smaller than a tolerance, 1,0]. Therefore, an increase of on-resistance, i.e., Vmaleon <
IIN(maX)’ results in an error current, AI=Im-me/R(m when IIN>(Vmax/Ron) is applied. On
the other hand, a decrease of the off-resistance causes the maximum leakage current Vmax/
Roff to be greater than the predetermined current tolerance Ito]. Let Vtol be the equivalent
voltage across the switch, where Vtol=ltolRofla Therefore, it produces an intolerable leakage
current, V/Roff, where Vtol < V < Vmax. Three fault types can be concluded in a current

switch as follows,

Type CS 1 fault: causes an error current when switch is on, and
a tolerable leakage current when switch is off;

Type CSZ fault: causes an intolerable leakage current when switch is off

35

and no error current when switch is on; and
Type CS3 fault: causes an error current when switch is on and

an intolerable leakage current when switch is off.

The deviation of an output current in a current switch is caused only by the channel
resistance, but not influenced by the charge-injection errors. Thus, the charge-injection
should not be considered in the fault model for the current switch.

This study shows that a fault-free switch macro may be used as either a current
switch or a voltage switch. However, the number of fault types in a current switch is less
than those in a voltage switch. In other words, the fault model of current switch is simpler
than that of voltage switch. This concludes that a fault-free macro may be used for different
applications, but the fault models of the same macro may be different depending upon the
applications. Those fault types causing only minor or no effects should be excluded in order

to simplify fault simulation and test generation.

3.2 Heuristic Fault Macromodeling Process

The heuristic fault macromodeling process defines the fault types based on circuit
layout, technology data, and some possible defects on the circuit layout. Based on the
defined fault types, a test set is generated. For simplicity of discussion, two example

circuits, current copiers and ADC, are used to demonstrate the process.

36

3.2.1 Example Circuit - Current Copier

A current copier, as shown in 2.2(c), is comprised of switches and other
components. The faults on current-storage transistors and holding capacitors can be
modeled as the equivalent faults of the associated switch(es) [12,14,15]. It is also valid in
this study based on the defects shown in Figure 3.1(c). More specifically. the following
defects may occur in a current-storage transistor: Breaks on gate polysilicon, i.e., Type f3
defect, is equivalent to a S/OF F fault on the associated voltage switch, i.e., Type VSI fault;
Shorten channel width, i.e., Type f4 defect, is equivalent to a Type CSI fault; Break on
metal, either drain or source, i.e., Type f1 defect, is equivalent to a S/OFF fault on the
associated current switch, i.e., Type CS] fault; Short between drain and gate implies that a
S/ON fault on the associated voltage switch, i.e., Type VS2 fault; Short between source and
gate, or between drain and source, is equivalent to a S/OF F fault on the associated voltage
switch, i.e., Type VS 1 fault. Any defects in active region, i.e., Type f5 defect, is equivalent
to a Type CSI fault. Any process deviation causing an increase of on-resistance implies the
presence of a Type CSI fault. The following defects may occur in the holding capacitors:
Any defects causing a decrease of capacitance, or an open circuit in the capacitor, is
equivalent to a Type VS4 fault on the associated voltage switch. Any defects causing an
increase of capacitance, or a short circuit in the capacitor is equivalent to a Type VS 1 fault.

The above equivalent faults include both catastrophic and parametric faults for both
current-storage transistors and the holding capacitors in a copier. Based on the fault types
for both current switches and voltage switches, the test generation process for the current
copier is described as follows.

Figure 3.2(a) plots the I-V characteristics of M1 and the load 82 with and without

37

 

 

 

 

 

 

 

 

 

 

 

    
 

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Figure 3.2 (a) Simulation results of I-V plot of M, with load lines for 82;
and (b) fault behavior and switching sequence.

38

faults, where the aspect ratio of M1 is (W/L)=6ttm/4ttm. The copier including 82 and M1
can be treated as an amplifier with a switch which acts as a voltage control active load. For
a fault-free current copier, M1 can store a current of 100|1A when the switch is on and
VGS=2.5V. Figure 3.2(b) illustrates the behaviors of faulty and fault-free copiers with the
application of the test sequence. The test sequence is comprised of three steps, or six clock
cycles, and can detect all types of switch faults, i.e., Types CS1 -CS3 and VS] -VS4 faults. It
also shows the test currents with the switching sequences for both switches Sz and S3 at
each clock cycle.

Let VCI be the initial voltage held in the holding capacitor C, and chax be the
maximum voltage across the capacitor. Taking the process variation into account, let Vtou
and Vtolz be the allowable voltage deviations for both chax and 0, respectively. The
corresponding current tolerances are Itoll=B(chax'Vth)*Vtoll and Itolz=0.5B(le-Vth)2,
where Vth is the threshold voltage of M]. In the first cycle of Step 1, the input current Iin=0
is copied and stored in M1, where both 82 and S3 are on, to discharge the capacitor. Thus,
after turning off S3 in the second cycle of Step 1, the current held in M1 is compared with
an expected zero-current. Step 2 consists of three clock cycles. An input current Ii“: ref is
applied and copied to M1 so that the capacitor is charged up to chax within the clock cycle
Tclk- Once the current is copied, both S2 and S3 are turned off and the current Inf is held in
M1 even though the test current is changed in these three clock cycles, as shown in Figure
3.2(b). Thus, at the end of Step 2, the current held in M1 is compared with an expected
current Inf. Finally, in the Step 3, when lin=0 and both 82 and S3 are off, a zero-current is
expected for fault -free circuit.

M1 is expected to hold a zero-current at the end of the 2nd cycle of Step 1,

39

unsuccessful test implies the existence of a Type VSI, VS2, or VS3 fault. More specifically,
the presence of a Type VSI or VS3 fault causes an intolerable time constant to“ which may
be too short to discharge the capacitor so that the voltage across the capacitor exceeds Vtolz.
On the other hand, a Type VS2 or VS3 fault produces an intolerable leakage current and
results in a current held in M1 to exceed 1,012.

If the copier passes the test in Step 1, the test pattern and clock sequence in Step 2
are applied. At the end of the 3rd cycle in Step 2, for fault-free circuit, the current held in
M1 is expected to be Inf, i.e., the voltage across the capacitor is expected to be between
(chax-Vtou) and chax. Unsuccessful test implies the existence of a Type VSI-VS4, CS 1
or CS3 fault. More specifically, an intolerable time constant to“ caused by a Type VSI or
VS3 fault may be too short to charge up the capacitor and result that the voltage across the
capacitor is below (chax-Vmu). On the other hand, during the second cycle of Step 2, for
fault-free circuit, switches 82 is on and S3 is off, the test current is changed from [ref to 0,
where the current held in M1 is still Iref, i.e., the voltage across the capacitor is chax. Since
the output of the amplifier is zero, the voltage across S3 is also chax. However, when S3
is off, an intolerable leakage current caused by a Type V52 or VS3 fault will discharge the
capacitor so that the voltage across it is below (chax-Vto“). Even though the test current
is changed back to Iref, the leakage current may continuously discharge the capacitor, as
shown in Figure 3.2(b). Since a Type VS4 fault causes excess charge flows at the moment
when S3 is off, the fault is identified if the voltage across the capacitor exceeds chax.

Finally, as illustrated in Figure 3.2(a), a Type CS] or CS3 fault causes the maximum
current which can be stored in M1 being reduced. Hence, when Ii“: refis applied, the fault

is identified if the current held in M, is less than (IreFItoll)° Finally, unsuccessful test for

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(c) fault simulation results.

41

Step 3 identifies a Type CS2 or CS3 fault. Since the fault causes an intolerable leakage
current when 82 is off, the fault is identified if a non-zero leakage current is detected. This
concludes that the test sequence in Figure 3.2(b) detects Type VSI-VS4 and CS1 -CS3 faults.

In the above test process, a tester is needed to compare the current held in M1 to 0
in Step 1 and [ref in Step 2. The tester, as shown in Figure 3.3(a), is comprised of a current
copier, a window comparator, and a D-flip-flop, and its switching sequence is illustrated in
Figure 3.3(b). Let 1M1 denote the current held in M1. Turning on S] and 82 causes a
difference current Ix=Iin-IM1. Turning on Sa and Sb will copy a current (heft-Ix) to MT and
virtual ground Vy. A zero current or Inf is applied from the input source through 81 when
[M] is compared to a 0 or a Iref. Applying a zero current is equivalent to turning off S1.
Closing Sa and Sb, then, will lead to a shift of Vy from 0. The voltage Vy is compared with
the threshold voltages V, and V2 of the window comparator. The output is defined as: Vo=0
if V2 < Vy < V1, and Vo=l otherwise. Let Ito] be the tolerance of Ile, then the values v, Vton ,

and Vtolz can be expressed in terms of Ito] as follows,

V = Vi = 'Vz = ltot / [Iref * 01¢}va
Vy=-Ix / [Inef * (twp)
Vtoll = ’10] l erean

Vtol2 = Vth 4' J21 tol/ Br:

If Ix=0, the voltage Vy is equal to 0. On the other hand, if a current equal to or greater than
Ito], by the above equations, 1 Vy I 2 v, and thus VO=1. Thus, the digital data Q=0 means the

comparison is asserted, and Oz], otherwise.

42

Figure 3.3(c) shows the simulation results of the circuit in Figure 3.3(a), where the
transistor size is W/L=6}.tm/4|J.m for both M1 and MT, IreFIOOuA, and V1=-V2=v=0.1V.
The process parameters are 2on=l .991479e-2, hp=4.921086e-2, Vth=0.822163, kp=
4.89376e-5, and Bn=kp*(6/4)=7.3406e-5. Thus, we obtain 1.01:0.69126ttA, Vton=5.7mV,
and Vtolz=0.9594V. Results show that Step 1 takes 1 cycle to initialize the circuit, 2 cycles
to force a zero current to be held in N1, and 1 cycle to compare the result, Step 2 takes 2
cycles to keep [ref and 1 cycle to compare the result, and Step3 takes 2 cycles. Results
conclude that Type VS 1 -VS3 faults can be detected in Steps 1 and 2, Step 2 also detects Type

VS4, CS1 and CS3 faults, and Step 3 detects Type CS2 and CS3 faults.

3.2.2 Example Circuit - ADC

In the test generation process for current copier, the emphasis was placed on
generating a test sequence that maximizes the error effects caused by failure switch(es).
However, for ADC, the emphasis should be on maximizing the accumulated error
generated at each conversion step. Based on the accumulated errors, a test sequence is
generated to excite the fault and the fault effects are observed from the converted digital
data.

Consider the ADC in Figure 3.4(a) [23] with a comparator in Figure 3.4(b). In the
comparator, a current copier consisting of N3, C4 and switches 8x and Sy, is used as a load
to copy the difference current Ix. Since the difference current may be positive or negative,
a bias current source lb] is used to keep a positive current to be copied to N3. A current
which is slightly higher than [ref is chosen for lb]. The copier memorizes the current Ix and

produces a voltage deviation to compare to a zero-voltage in the comparator. Since the

43

 

 

 

 

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Figure 3.4 Test structure for SI algorithmic ADC: (a) schematic diagram;
and (b) comparator.

resolution of an ADC is 0.5LSB, or 0.51,“, here a simple comparator instead of window
comparator, can be used. It should be noted that an additional bias current Ib2=lref and the
switch S2 are used only for testing purpose. During the normal operation, S2 is off and the
bias current is isolated from the converter circuit. Thus, the extra circuitry does not affect
the performance of the converter. The function of this extra circuitry will be explained
shortly. Just like current copier, the current switch and voltage switch are also used in ADC.

In Figure 3.4, S], S2, S4, 86, Sm, SK, and S2 are current switched, while S3, 55. S7,
and Sy are voltage switches. The ADC consists of four copiers. One may apply the test
sequence developed in the previous section for all copiers in the ADC. However, in the
ADC, we can only observe the result from the output of the comparator, i.e., the converted
digital data. Thus, the test sequence should be generated to maximize the accumulated
errors so that the error effect can be reflected to the converted digital data.

As discussed in Section 3.2.1, the current switch faults, Type CSI-CS3 faults, can
be detected by applying a test current Iref. when Ii“: ref is applied, a Type CS] or CS3 fault
at 82 is identified if the current held in N1 is less than (Ira—Ito“). This error will be
accumulated so that the converted digital data with the pattern 1...0xx..x, "x" means "don’t
care", i.e., either 0 or 1, is obtained. On the other hand, with the application of a zero input
current, an intolerable leakage current occurs in the presence of a Type CSZ or CS3 fault at
S2 when the switch is turned off. The accumulated error will cause the converted digital
data pattern to be 0... l xx..x. Thus, both [ref and 0 detects the current switch faults.

Consider a Type VS 1 fault at S3. Figure 3.5(a) illustrates a test sequence, referred to
as Test Sequence A, for detecting such fault. When an input current‘Iin=I,ef is applied in the

first step, the fault causes an intolerable time constant ton which is too short to charge up

45

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(b) switching sequence.

46

the capacitor C1 so that the voltage across the capacitor cannot reach (V max-v.0“) within
the clock period Tclk' In other words, the transistor N1 stores a current less than Imf. As a
result, the converted digital data pattern l...0xx..x identifies such fault. However, this fault
may pass this test if the initial voltage held in C1 is sufficiently high. An input current Iin=0
is applied in the second step to ensure that the voltage across the capacitor is below Vtolz-

In the first cycle of Step 2, the voltage across the capacitor C1 is charged up to
chax. This is simply because the fault may marginally pass the first test, say, VClecmax-
Vm“, and it could discharge C1 to below lez when lin=0 is applied in the next cycle. As
a result, the fault may not be able to be identified. After conversion, if the converted digital
pattern 0... lxx..x is resulted, this implies that Cl fails to be discharged to below lez, and
thus the fault is detected. Finally, if the switch passes the second step, it implies that the
initial voltage across the capacitor is below Vtolz- Thus, applying an input current Ii“: ref
in the third step will detect the fault if the pattern 1..0xx..x is resulted. Similarly, the C1 is
discharged to below Vtolz in the first cycle of Step 3. The similar process can be applied to
test the Type V51 fault for S5 and 8-,. Test Sequence A can also detect a Type VS3 fault in
these switches. Figure 3.5(b) illustrates the switching sequence of all switches. In fact, the
switching sequence is the one for normal conversion process.

Consider a Type V52 fault at S3. The fault causes an intolerable leakage current
which changes the current held in N1, and the voltage across the capacitor. The fault can be
detected by the sequence shown in Figure 3.2(b) for the copier. However, it becomes
difficult to detect the fault by observing the converted digital data pattern. Figure 3.6(a)
illustrates the test sequence, referred to as Test Sequence B, for detecting such faults. There

are six steps for each bit conversion. Figure 3.6(b) shows the switching sequence. In the

 

47

 

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Sz r—l J_l_ r—l_
for S3 for 85 for S7

Figure 3.6 Test sequence B: (a) fault behavior; and (b) type V82 fault.

48

first step, the reference current [ref is copied and stored in N3, where the current store in N3
is (Ibl- ref). In Step 2, the reference current is again copied and stored in P1. Then, the copier
with N1 is calibrated in the third step by turning on Sx, S2,and S3, i.e., to copy the current
Ire,- held in N3 and the bias current source lb, to N. This attempts to raise the voltage across
the capacitor C1 to Van”.

In the next step, the copier with N2 is calibrated by N, and P1. This means that a
zero current is copied and held in N2. This will cause the output voltage of the amplifier,
Node Y in Figure 3.4(b), drops to zero, and thus a maximum voltage across S3, i.e., chax,
is resulted. Note that switch S3 is off in this step. As a result, an intolerable leakage current
in S3 caused by this fault will discharge the capacitor C1 and change the current held in N1.
In Step 5, switches S4, Sx, Sy, Sz are turned on to copy and store the current difference
between lb2=lref and the current held in N2 to the copier with N 3. In Step 6, all switches are
turned off and the current held in N3 is compared and a converted digital data is obtained.
For the fault-free circuit, the current held in N2 is 0 and thus the current held in N3 with lb,
is Inf. A "1" results in the conversion.

As illustrates in Figure 3.5(a), the voltage across C1 is charged up to chax in Step
3, but it drops slightly in Step 4 due to the leakage current caused by this fault. The voltage
drop of C1, decreasing the current held in N1, will result in an increase of the current held
in N2, and increase the voltage across C2. If the error in ch is sufficiently large, then a
digital "0" is resulted in the conversion. Since the S3 is off for 5 clock cycles, the effect due
to the leakage current will be getting severe in the presence of such fault. This will cause
the error of VC2 to be sufficiently large. Thus, repeating the 6-step sequence for converting

n-bit, a converted digital pattern l..0xx.x detects the fault. Similarly, Figure 3.6(b) also

49

illustrates the switching sequences for detecting the faults in S5 and S7. Test Sequence B
can also detect a Type V53 fault in these switches.

Considers a Type V54 fault in S3. The fault causes excess charge flows at the
moment when S3 is off. The charge can be positive or negative. If it is negative, then the
accumulated error will cause Vcl to be less than (chax-an) when the third step of Test
Sequence A is applied. Thus, the fault results in a converted digital data with the pattern
1..0xx..x. On the other hand, if the charge is positive, then the accumulated error will cause
V6] to be more than Vton when the test sequence in Step 2 is applied. Thus, the fault results
in a pattern of 0..lxx..x. This implies that the test sequence for testing Type V51 fault can
also detect Type V54 faults.

The test sequence for the ADC consists of Test Sequence A and Test Sequence B,
where Test Sequence A detects Types V51, V53, and V54 faults for S3, 85, and 8-,, Types
C51-C54 faults for S], 82, S4, 86, and S10, and Types C52 and C53 faults for Sx, and Test
Sequence B detects Types V52 and V53 faults for S3, S6, 8—,, Types C51 and C53 faults for
Sx, Types C51-C53 faults for 82, and Types V51 ~V54 faults for Sy. This implies that both

test sequence will detect all switching faults.

3.2.3 Discussion

This subsection addresses an important issue on simplifying test generation process
using a built-in tester. The range of the threshold voltages, (-V2,V1), in the window
comparator limits the current tolerance, Ito], and the voltage tolerances, Vton and Vtolz- A
better current comparator is needed if a tighter tolerance is required. However, testing with

tighter tolerance may reduce testing time. Moreover, a better comparator is costly.

50

Therefore, developing high-precision yet low-cost current comparators as built-in testers
are of importance for simplifying the test generation process and reducing testing time.
The fault types are defined in a brute-force approach with the possible defects on
the circuit layout. In fact, some fault types may occur with a very low possibility. To
simplify the fault simulation and test generation processes, only those fault types with
higher possibilities are considered. The fault types should be defined based on the defect
distribution generated from the manufacturing process and ranked according to their
occurrences. This motivated the development of a fault macromodeling process using the

IFA technique discussed in the next section.

3.3 [FA-Based Fault Macromodeling Process
This section describes two important steps in the IFA-based fault macromodeling

process: fault classification and test generation.

3.3.1 Fault Classification

The IFA technique, as illustrated in Figure 3.7, contains three steps, where the volt-
age switch with dummy circuit is used as example. In the first step, the input data includes
layout, technology data, and defect statistics, where the Scalable CMOS N-Well (SCN)

technology is employed, and the following density function [17] is used.

2
x/x o,x<x0
f(x)= 2 3 (3.1)

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Note that x0 is the mean of x, and the probability density function, f(x), of the diameter of

defect, x. The defect distribution is based on the real process data collected from clean
room. Based on this distribution, the defect generator program generates defects with dif-
ferent diameter on the layout. All the defects are passed through a decision process and
determined if they have effect on the circuit performance or not. The defects which have
effect on the circuit performance are called significant defects and they can be classified
into several defect types according to what kind of effect they will cause. All the faulty
layouts for the significant defects are then translated into spice program by the Magic
extractor, in this example.

Figure 3.8 shows the operation of step 2 and 3 of the process. The Spice files are
simulated by Spice. Therefore, n times simulations are needed if there are n significant
defects. The purpose of these simulation is to find the fault behavior values of the circuit
parameters in interest for every significant defect. For the voltage switch in this example,

the on-resistance ron and off-resistance roff are the two circuit parameters of interest, thus
the corresponding values of ron and roff of every significant defect are found and listed in
the fault behaviors table.

According to the list of fault behavior values, the significant defects are translated

to a list of fault types. In Figure 3.8, the fault types of voltage switch can be concluded as

below,
Type I fault: On-resistance is too high, off-resistance is unchanged;
Type 2 fault: Off-resistance is too low, on-resistance is unchanged;
Type 3 fault: On-resistance is too high and off-resistance is too low; and

Type 4 fault: Intolerable charge injection error.

54

 

 

£
% LP

 

 

 

 

 

 

2
$3, $3:
C 84

(b) (C)

1 C
Cl _L 1: 31
s. ...... s. 6 fig.
5
| s
C

Figure 3.9 Switches: (a) schematic; (b) fault model for voltage switch; and
(c) fault model for current switch.

55

As mentioned previously, a Type 4 fault occurs only in the voltage switches. We may use
the same macromodel for both current or voltage switches. However, they should use dif-
ferent fault macromodels for both switches. The fault macromodel of voltage switch
includes the above four fault types, while the fault macromodel of current switch excludes
the Type 4 fault.

Based on the fault types obtained from IPA, the fault macromodel can be estab-

lished. Consider a CMOS voltage switch, shown in Figure 3.9(a), where Cg“ and Cgp are
the gate capacitance of NMOS and PMOS transistors, respectively. The voltage switch can
be modeled as shown in Figure 3.9(b), where r"on and r°oflr are nominal on-resistance and
off-resistance, respectively, ron and roff are the on-resistance and off-resistance of a faulty
switch, respectively, and CC is the difference of Cgm and Cgp. The switches in Figure 3.9(b)
are all idea], where Sa and Sb are controlled by the clock signals CK and (if, respectively,
while Si, i=1,...,5, are on and off depending upon the fault types. Based on the fault model,

the switches Si’s are assigned as follows, where “0” means “off” and “1” is “on”.

fault free: (81,82,83,S4,Ss)=(1,0,l,O,O);
Type I fault: (31,52,83,S4,Ss)=(0,1,l,O,O);
Type 2 fault: (81,82,83,S4,85)=(1,O,O,1,0);
Type 3 fault: (S1,82,33,84,SS)=(O,1,O,1,0); and

Type 4 fault: (81,82,83,S4,SS)=(1,O,1,0,1);

Similarly, a current switch is modeled as shown in Figure 3.9(c), where both C6 and 85 are

56

removed from the voltage switch fault model. The use of ideal switches for fault macro-
models makes the fault simulation and test generation easier, and the linear resistors defi-

nitely speeds-up the fault simulation, while keeping the accuracy.

3.3.2 Testability Design Rules

Let Ar and Ay be the parameter deviation and performance deviation, respectively,

and Aylb and Ay“b be the lower and upper bounds of a design specification (Figure 3.10).

An analog circuit can be easily testable if it is designed in such a way that, for any fault

type, there exist the parameter deviation bounds Arlb and Arab such that, for all u,

Ay‘bsAysAyub, if and only if Ar'bSArSArub, for all Ar. (3.2)

In other words, for each fault type, there exist a pair of Arlb and Ar“b such that the circuit
meets the design specification if and only if the parameter deviations are within the bounds
for all 11. In fact, the parameter bounds Arlb and Ar“b can be determined by the design
specification, Aylb and Ayub, the inputs u, and the fault types. Therefore, the test generation
problem is to find a set of inputs u that determine the bounds Arlb and Arub. In other words,
with the application of such inputs, if the parameter deviations are out of the bounds, by
(3.2) the corresponding circuit performance will not meet the specification, and thus the
circuit fails.

Unfortunately, during the design process, most analog circuits are designed to meet
specifications without consideration of the testability, and thus fail to meet the condition in

(3.2). More specifically, a set of nominal parameter values and the associated tolerances are

57

 

b b
Arll I A" | u Parameter Deviation
WM
0
10 Performance Deviation
l
Aylb Ayub Ay

 

 

 

Figure 3.10 Relationship between parameter deviation and performance deviation.

 

 

 

 

 

 

 

 

Figure 3.11 Example for the definition of parameter deviation bounds.

58

selected to meet the design specification. The designed circuit meets the specification, if all
parameters are selected within the tolerances. In many designs, however, the circuit still
meets the specification even if a parameter deviation is much larger than the tolerance. A
simple testability design rule can be developed for the designed analog circuits to satisfy
(3.2) and thus we are able to define the parameter bounds for generating test vectors for all
fault types.
Consider the performance of a designed circuit
y=Y(u,r) (3.3)

where u=(u1,u2,...,un), rr—(r],r2,...rq), and y=(y1,y2,...,ym), are the vectors of the input vari-

ables, circuit parameters, and specifications, respectively. Let r0=(r10,r2°,...,rq0) and
y0=(yl0,y20,..., ymo) be the nominal parameters and nominal performance, respectively,

and Art-_r-ro and Ay=y-y0=(Ayl,Ay2, ...,Aym) are the parameter deviation and performance

deviation, respectively. The i-th specification deviation can be expressed as
Aya=yi-yoi=Yi(u.r°+Ar)-Yi(u.r°)=gi(u.Ar) (3.4)

Note that, a specified behavior of an analog circuit is required for a whole range of input

signals, for example, a frequency range, but an analog circuit can be tested at only a finite

subset of the specifications. Without loss of generality, let U={u1,u2,..,uv} be the collec-
tion of the discrete input vectors that are used to verify the above design. In other words,

the circuit meets the i-th specification for all u e U.

For simplicity, we first consider the case that r=(r]), i.e., q=l. Let Ayilb and Ayi“b

59

be the lower and upper bounds of Ayi, respectively. Thus,

Ayilegi(uj,Ar)SAyi“b for all uJ' eU. (3.5)

Let Arjlb and Arjub be the circuit parameter deviations, for u), that satisfy

AYilb=gi("JaArjlb) and AYiub=gi(“',AfJ-"b) (3-6)

i.e. each function gj=g(ul,Ar) intersects Ayilb and Ayi"b at Arjlb and Arjub, respectively, as
shown in Figure 3.1 1, with the input set U={u1, u2, u3 }. The circuit performance meets the
i-th specification for uj if the parameter deviation lies within the bounds, i.e.,
ArjleArSArJ-“b. Therefore, a circuit is easily testable if it is designed in such a way that the
performance variation falls outside the bounds when the parameter deviation falls outside
the bounds. In other words, a circuit is easily testable if the function gj intersects at most

one point to each of the performance deviation bounds, Ayilb and Ayiub, as shown in Fig-

ure 3.11, each gj intersects Aylb and Ay“b at Arj‘b and Arjub, respectively. This concludes

the following testability design rule,

A designed circuit is easily testable if g intersects at most one point to each

of the performance deviation bounds for all Ayi and for all uie U.

60

Similarly, the testability design rule can be applied for the general case r=(r1, r2, rq).

3.3.3 Test Generation and Fault Coverage

The conditions in (3.2) implies that the performance deviation lies within the
bounds, i.e., Ayileg(u,Ar)SAyi“b, if the parameter deviation Arj, for uj, also lies within
bound [NJ-lb, Arjub]. Note that all bounds [NJ-lb, Arjub] contain the point Ar=0. Therefore,
there exists a bound [Arlb, Arub] that ensures the circuit performance meets the i-th specifi-

cation for all nj 6 U, where

[Ar‘b,Ar“b] = n {[Ar.'b,ArJ-“b] | j=1,2,...,v} (3.7)

For example, as shown in Figure 3.11,

{Aflb,AI'Ub] = [Ar] lb,AI'] ub] n [ArzlerZUb]fl[Ar3lb,Ar3“b]=[Ar1lb,Ar2"b]

i.e. both bounds Ar“) and Ar“b are determined by u1 and uz, respectively. This means that

the i-th specification fails if the parameter deviation Ar] is less than Ar]lb when u1 is

2 is applied. Therefore, both 111 and u2 are taken as

applied, or greater than Arzub when u
the test vectors. This concludes that ujl and uj“ are taken as the test vectors if Arjllb=Arlb

and ArjuubzArub. Note that if more than one input satisfies Arjllb=Arlb or Arjuub=Ar“b, one

of them is selected as a test vector.

61

Let F=(f1, f2, ..., fw) be the collection of the fault types, and Ub(fk), k=1,2,...,w, be
the set of test vectors for testing the fault type fk. Since the test vectors are selected from

the discrete input set U, one test vector may simultaneous determine several bounds for
different fault types. The duplicated test vectors should be eliminated. Thus, the developed
test generation process is comprised of two steps: Test set selection and Test set compac-
tion. The former step selects the test vectors as described above, and the latter step elimi-

nates the duplicated test vectors. The final test set is compacted as follows,

TS = n {Ub(fk) I k=1,2,..,w} (3.8)

Let F=(f1,f2,..., fw) be the collection of the collapsed fault types, and ”H be the
number of defects that cause their circuit behaviors to be with the fault type fi. Thus, the
total number of faults NF is the sum of all NFi’s, i=1,2,...,w. Based on the test set derived
from the test generation process, the test set TS will detect Mp, faults with the fault type fi,
and the total detected faults, Mp, is the sum of all MFi, i=1,2,...,w. Therefore, the fault cov-

erage is defined as MF/NF.

3.3.4 Example
Consider the current copier in Figure 2.2(b). Figure 3.12 is its equivalent circuit

excluding the amplifier, where the current switch 8, is modeled as a linear resistor rs, and
the input current 1,”, OSIinSlref. In the presence of a Type I fault, or a non-catastrophic

Type 2 fault, the transistor M1 works in the linear region, and thus its drain current Id, or

62

1d Vc=Vdd
rs

 

 

 

Figure 3.12 Equivalent circuit of the portion including transistor and
current switch of the current copier, and its I-V characteristic.

63

the current held in the copier, can be expressed as follows,

 

.. _ 1 1 1 2(Vx-Vss)
Id—Fd(rS,VC)— a X [Vx - VC + Vth — rS—B + J(Vdd- Vss- V". 4' EB): — T] (3.9)

where Va, and B are the threshold voltage and gain factor of M1, respectively, and VC is
the voltage across the capacitor. Let ron and lemon) be the on-resistance and output current
when S] is on, respectively, in the presence of a Type 1 fault, and roff and Iout(off) be the
off-resistance and leakage current when S] is off, respectively, in the presence of a Type 2
fault. By (3.9), the output current Iout(on)=Fd(roded) because, in the presence of a Type 1
fault, the largest voltage VC=Vdd is calibrated to make Iout(on) to be as close to Iin as possi-

ble, and Iom(of0=Fd(roff,VC) in the presence of a Type 2 fault, where VC is a function of
Ii". Let Ioout(on) and Ioout(off) be the nominal output currents when the switch is on and off,
respectively, i.e., I°out(on)=I,-,, when the switch is on, and Ioom(om=0 when the switch is off.
Let r0on and rooff be the nominal on-resistance and off-resistance, respectively, where

ron=roon+Arom and roficrOOfl-t-Aroff. Therefore, the output current deviations are

Alout(on)=lout(on)‘Ioout(on)=Fd(ronvvdd)'Iin=gon(Iin’Aron); and (3-10a)

Alout(ofi)=lout(off)'loout(offi=F d(roff ’VC)=goff(Iin’Ar off) (3 ° 10b)

It can be shown that both gon and gofl‘ meet the conditions for the testability design rule.

Suppose that the system specification are given as follows

64

“the error output current is less than Iem, when S1 is on,

and the leakage current must be less than [leak when S 1 is of”

Let fi, i=1,2,3, be the Type i fault of the current switch. For f], the on-resistance is
too high and the off-resistance is unchanged, i.e., ron is critical, but rot; is non-critical, or
At=(Aron,O). From the system specification, Jam, 5 Alowon) S 0, by (3.9) and (3.10), the
bounds of ron can be derived as follows,

ronlb=0; and ronub=F5(Vdd,-Iem,+1in)/(-Iem,+lin)

where

 

F5(Vc,i): (VC— vx— v,,) + Juic— vx— v,,)2 + (vx— V”)(2Vdd— vu- 2v,,,— VI)- [331' (3.11)

As a result, the lower and upper bounds are

lb_ lb 0 _ o .
Aron ‘ron 'ron"'r on,and

AI'onub = I.onub' r0on = FS(Vdd"Ierror+Iin)/('Ierror+1in) " r0on

Since the minimum upper bound is obtained when Iin=Iref, for Type 1 fault, f], we con-

clude

Ar0nlb(f1) = .190“; and Aronub(f1) : Aron(min)ub

= FS(Vddi'Ierror'l'Iref)/('Ierror+lref) ’ r00“, (3°12)

65

Similarly, for Type 2 fault, the off-resistance R05 is too small and the off-resistance is
unchanged when the switch is off. Thus, we only consider the critical parameter rofi'.
Based on the specification, 0 S Alout(ofl) S Ileak, the bounds of rofi‘ can be derived as fol-

lows,

lb_ . b-
roff ‘FS(VC’Ileak)/Ileak’ and I'offu -+°°

Since the maximum lower bound is obtained when VC=VC(max)’ for Type 2 fault, f2, we

conclude

Aroffub(f2) =+°°; and Al'offlb(f2) = l.off(max)[b ‘ r0off

= FS(Vc(max)vIleak)/Ileak ' rooff' (3°13)

Note that vcmx) is derived from the equation, Imt=(B/2)(Vc(max)-VSS-Vth)2. For Type 3

fault, both ron and roff are critical and the bounds are

Aron“b(f3) = monubm) and Aronu’(f3) = 4°C“. (3.14)

mofiubag = +oo and Aroff’b(f3) = Arofi’baz).

The following fault ranges are derived based on the following parameter values:

vdd=2.5v; vss=-2.5v; Vx=OV;Iref=100ttA;Vth=0.822163V; B=7.34e-5;

66

Iemr=0.luA; Ileak=0.1p.A; Ron=5.9k.Q; R0fi=6.3x1012§2

As a result, the voltage Vc(max)=-0.027V. Thus, the bounds are

monubm) = 15.726kfl and Aronlb(f1) = -5914).
mofiubaz) =+.. and Arofi’baz) =-6.299975x1012t2
Ar "hm—15726142 dAl' ’b --

on 3 — . an on (f3)- 5.9m

Arofiubap =+oo and Arofl’bag =-6.299975x10129.

Figure 3.13(a) shows the simulation results of AlouKon) versus various Aron for the input
current (in: 20, 40, 60, 80, lOOuA. Results show that Arubon(f1)=15.726kfl and Ar"
bon(f1)=-r°on=-5.9k9. In other words, when the switch is on, the system fails when
ron>21.626kQ or ron< 09. Similarly, Figure 3.13(b) illustrates the simulation for f2, where
ArUbofi(f2)=oo, Ar'bofl(f2)=-6.299975x10‘2§2

For Type 1 fault, as shown in Figure 3.13(a), Arubon=15.726k9, when
1,": reflOOMA, and Ar‘bon=-5.9lto, for all 1,, Thus, Ub(f1)={ loottA}. Similarly, Ar'bofic-
6.299975x10'20 when Ii": lOOuA, i.e., Ub(f2)={100uA}, and Ub(f3)={100p.A}. By
(3.9), the compacted test set is TS={100uA}, i.e., the input current Iin=100ttA detects all

three fault types.
As mentioned, In this experiment, we have injected 3500 defects to the current
switch layout and the defects are generated using the IFA procedure. Among the defects,

the statistics of the defect counts and fault counts for three fault types are summarized in

67

 

 

Output current deviation “out (x10'7)

 

 

L l l l

I
&

 

 

o 2 4 6 a 4 10
On-resistance deviation Aron (10 £2)

(a)

a
bi
..
.

..

.

12

 

a
N

d
l

.0
O
l

 

.0
G
l

.0
a

uA

Leakage current deviation Mont (x10'7)
S
a

 

 

rJ

 

 

$0

-e.2b95 4.2199 4.2935- —6.298
Off-resistance deviation Aroff (1012 (I)

(b)

Figure 3.13 Simulation results: (a) for f1; and (b) for f2.

-6.2975

68

Table 3.1. It shows that there are 3146 defects that would not cause any major malfunction
of the switch, i.e., they do not change the on-resistance and off-resistance of the switch,
and 354 defects that change on-resistance and/or off-resistance, where the fault counts for
Types 1, 2, and 3 faults are 202, 137, and 15, respectively. As shown in Table 3.1, for Type
1 faults, there are 172 defected circuits whose on-resistances are out of bounds, while the
remaining 30 are kept within the bounds even though the defects cause the parameter devi—

ations. Among the 172 defected circuits, 114 are open circuits, i.e., ton: +oo. Similarly,

among 137 circuits with the Type 2 fault, the off-resistances of 134 circuits are out of
bounds, and 3 remains within the bounds. Among the 134 circuits, 121 are short circuits,

i.e., rofi=0. Finally, for Type 3 faults, 12 are out of bounds, while 3 are within the bounds.

In summary, among 3500 defects, 3182 circuits are fault-free and only 318 circuits are
faulty. Using the test vector Iin=Iref=100uA, we detect all 318 faults. Thus, the fault cover-
age is 100%.

The fault counts in Table 3.1 also show that the total number of catastrophic faults,
i.e., open and short circuits, is 235, while the number of parametric faults is 83. In other
words, the catastrophic faults take 76.1% of the total faults. This concludes that, with the
assumption of catastrophic faults, the fault coverage can achieve at most 76%.

It should be mentioned that the full coverage is achieved based on the assumption
that the measurement is performed by a perfect instrument. There always exist some mea-
surement errors in any test environment. Thus, the test environment should be one of the
major parameters for fault coverage evaluation. When the measurement errors are taken
into consideration, some fault ranges may be changed. In general, the fault ranges may be

shrunk and thus some faults may not be detected due to the measurement errors. Thus, the

69

Table 3.1 Defect and fault count distributions.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type 1 faults Type 2 faults
On-resistance count Off-resistance count
5.91:9 <A r0“ < 15.726 30 -6.299975x1012t2 < Aroff < +.. 3
15.726kQ < A ton < +oo 53 -6.3x10‘2t2 < Aroff < -6.299975x10120 13
Aron=+oo(open circuit) 114 Aroff = -6.3x10120 (short circuit) 121
Type 3 faults
Co
Aroff um Ar” -5.9kQ<A r0n<15.726k9 15,726kQ<A r0n<+oo Ar°n=+oo
-6.299975x 10129 < at,“ < +0. 3 O -_
-6.3x10'2§2 < Arfo < -6.299975x10‘2tz 5 7 --
Arofi = -6.3xlOlZQ (short circuit) -- -- --
Defect Count Distribution
. . . . out-of- within
Clrcult Behavror count bounds bounds
Type 1 faults 202 172 30
Type 2 faults 137 134 3
Type 3 faults 15 12 3
Fault-free 3 146 3 146
Total 3500 318 3182

 

 

 

 

 

 

faulty fault-free

 

 

70

Table 3.2 Defect and fault count distributions.

(With inaccurate test instrument)

 

 

 

 

 

 

 

 

 

 

 

 

 

Type 1 faults Type 2 faults
On-resistance count Off-resistance count

5.9m <A ton < 15.726kfl 3o -6.299975xlo‘2r2 < Aroff < +00 5

15.726142 < A rm < +.. 53 -6.3x1012£2 < Aroff < ~6.299975x10120 11

Aron=+oo(open circuit) 114 Aroff = -6.3x10129 (short circuit) 121

Type 3 faults
Ar off Count Aron '5~9k-Q<A ron<15.726kfl 15.726kfl<A r°n<+oo Aron=+oo

-6.299975x10'2£2 < Atoff < +.. 5 2 --
-6.3xlolzo < Atoff< -6.299975x1012o 3 5 --
Aroff = -6.3x1012§2 (short circuit) -- -- --

 

 

 

 

 

 

Defect Count Distribution

 

Circuit Behavior count out-of- With!"
bounds bounds

Type 1 faults 202 172 30

 

 

 

 

 

 

 

 

 

 

Type 2 faults 137 132 5

Type 3 faults 15 10 5
Fault-free 3 146 3 146
Total 3500 314 3186

 

faulty fault-free

 

Fault Coverage (%)

71

 

“30"“!L I I I I u I I I I

99.5 “’

98.5—
98 -
97.5-
97 -

96.5 -

 

96 1

1

P

 

 

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10

Error Current due to Test Instrument (11A)

Figure 3.14 Fault coverages with respect to accuracy of test instrument.

72

fault coverage may be affected by the inaccurate measurement instrument.

For example, assume that the test instrument has a 10% inaccuracy, i.e., Alom(on)<-
0.11ttA and Alout(om>0.ll 11A. Therefore, the bounds are obtained as Ar'boflc-
6.2999773x1o'2r2 and Arubon=15.729k9. The experimental results, as summarized in

Table 3.2, show that, when Arubon is changed from 15.726kfl to 15.72916), the number of
circuits whose on-resistances are out-of-bounds remains the same. However, the change of
Arlbofi, from -6.299975x10129 to -6.2999773x10129, causes two circuits with a Type 2

fault and two with a Type 3 fault to become undetectable. Thus, with the test vector
Iin=100uA, we detect only a total of 314 faults. The fault coverage is Mp/Np=3l4/
318=98.7%. This concludes that the full fault coverage is not achieved because of the
inaccuracy of the test environment.

Figure 3.14 plots the fault coverages of the current switch with respect to the inac-
curacy of the test instrument ranging from 0 to 100%. It shows that a full coverage can be
achieved when the inaccuracy is within 0.002mA for the output current. It is necessary to

keep within 0.5% for achieving a 99% fault coverage.

3.4 Discussion

This chapter presents an effective IFA-based fault macromodeling process that
maps the specification-driven analog testing process to a simple fault-model-based process.
The [FA-based fault macromodeling process defines practical fault types and generates test
sets. A set of testability design rules was included to guarantee the existence of parameter

deviation bounds and to simplify the test generation process. It also shows that the use of

73

built-in tester can further simplify the test generation process and reduce testing time.
However, the IFA has inherent high computational complexity and limited to small circuit
applications. Therefore, for practical circuit design, the reduction of computational
complexity with the IFA technique is of major concern.

Based on the parameter deviation bounds derived from the design specification, a
set of discrete inputs used for design verification, and the faulty types, one can generate the
test vectors and evaluate the fault coverage. However, the assumption that the parameter
deviation bounds exist may not be always valid for today’s circuit design process. This is
simply because that today’s design process placed its emphasis on the design for
functionality, but not for testability, and thus the bounds may not exist. More specifically, a
set of nominal parameter values and the associated tolerances may be selected to meet the
design specification by the most of commercial design tools. The designed circuit meets the
specification, if all parameters are selected within the tolerances. In many designs, however,
the circuit still meets the specification even if a parameter deviation is far beyond the
tolerance. Therefore, the testability design concept is needed for designing easily testable
analog circuits. This can be accomplished by a set of testability design rules.

Finally, as discussed in Section 3.2.3, a high-precision built—in tester can simplify

test sequence and reduce testing time significantly.

Chapter 4

TESTABILITY ENHANCEMENT

To reduce the computational complexity of the fault macromodeling process with
the IFA technique, Section 4.1 presents a hierarchical fault macromodeling process [17].
Section 4.2 proposes some refinements of the testability design rules [51] which generate
easily testable circuits. Section 4.3 presents high-accuracy built-in tester [61] which not
only increases the observability of ICs, but also simplifies the test generation process and
resultant test sequence. It also discusses the trade-offs between the complexities of the

tester and the test sequence and addresses some design issues.

4.1 Hierarchical [FA-Based Fault Macromodeling

The IFA technique is applicable only for small circuits because it requires a tre-
mendous computational time. The hierarchical structures, as shown in Figure 4.1, illus-
trate the computational complexity of the process with the IFA technique. Note that the
ADC is constructed from two NMOS current copiers and one PMOS current copier
together with other components such as comparator, sources, and digital circuits, while the
current copier includes a current switch. For purpose of comparison, the simulation cost is

modeled as

TCS = TS * N + Tovh (4.1)

75

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76

where TCS is the time required for circuit simulations for entire IFA process, Ts is the time

required for simulating a circuit one time, N is the number of significant defects to be sim-

ulated, and Tovh is the time overhead due to unsuccessful simulations. Note that the value
of N is proportional to the layout area. For simplicity, we assume that Tovh=0, i.e., all sim-
ulations are successful. For the current switch, N=354 and Ts=2 seconds, for the current
copier, N=2242, and TS=20 seconds, and for the ADC, N=5310 and TS=15 minutes. Thus,

by (4.1), the simulation costs for the current switch, current copier, and ADC are 11.8

minutes, 12.45 hours, and 55.3 days, respectively.

The basic concept behind the hierarchical fault macromodeling is to decompose a
large circuit into many smaller subcircuits. For example, the ADC can be decomposed into
three current copiers, one comparator, and two current sources. If we assume that all 6
components have the same computational complexity with the IFA technique, i.e., each
component takes 12.25 hours. Thus, the 6 components take a total of 74.7 hours, or 3 days,

which is much better than 55.3 days for directly applying the IFA technique to the ADC.

Section 4.1.1 describes the decomposing principles and how to build a macro
library for the hierarchical fault macromodeling process. Based on cell and macro librar-

ies, Section 4.1.2 presents the estimation of fault coverage in a hierarchical structure.

4.1.1 Macro Library
For a reasonably large circuit, it is decomposed into smaller subcircuits. The
subcircuits may be further decomposed until they can be handled comfortably by the [FA

technique. For simplicity of discussion, the subcircuits which can be comfortably handled

77

$5388 :58 3938202 no «@0280 N6 95m:—

3580

a---

_r

 

78

 

Defect
Statlstlcs

Circuit
Layout

   
    
 

     
   
 
 

Technology
Data

     
 
 

' 7 Step 1 ------------- ' IFA Operation

Ma h sical defects list
Ifopciicuit fault list

    

Defect Generation

I Defect-to—fault Translation I

Defect Simulator
(e.g. VLASIC)

 

 

(Circuit fault extraction)

 

 

 

 

 

Step 2 List of circuit faults
I
Evaluate fault behavior on : Circuit Simulator
c1rcu1t-level operation 1 (e.g. SPICE)
l

 

List of fault behaviors

 

Step 3

 

 

 

I
I [Classify and rank fault typesl I E

 

. ______________ L_ i§t_qf_r§qk_esi_f§tili types

Cell Library

 

 

CC“ Library Cell Layout Design
Infomafio"

 

 

 

 

 

 

 

 

 

 

 

Cell#l
- #of defects
: Fault Types f1 f2 {W
- 1M9 IOnF .......... 60db
Extracted 100m 0.4nF .......... 100db
. Parameter 730m 50pF .......... 83db
: Values 2 : 1

 

 

 

Cell #n

 

 

 

Figure 4.3 Cell library of hierarchical IFA-based fault macromodeling.

79

Cell Library Testability Design Operation

 

 

Macro circuit Parameters in
Specification fault types

 

 

 

 

 

 

   

 

 

Macro circuit schematic
Macro Spice file
Performance specification
Input sets of macro

 

 
  

  

Derive parameter ‘
deviation bounds ”i

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I. 1 Generate test sets

 

 

 

 

 

 

 

I . Evaluate Fault Coverage :

 

 

----------—-—--.-----

 

 

Macro Library

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)

Macro Library , q ,
Macro #1 ‘ DCSign Specification
Macro #2 - myoxfl’afia; $13:

Design Information
5 ' Test Set nggrlztige
Macro #m
(b)

Figure 4.4 Macro library of hierarchical IFA-based fault macromodeling.

80

by the IFA technique is referred to as primitive cells (PCs), and a macro is a subcircuit
which is comprised of many PCs and/or some smaller macros. Figure 4.2 shows a current
copier macro which is comprised of four PCs: current switch, voltage switch, storage unit,
and an op-amp. It also shows that the ADC is comprised of the current copier macros and
the PCs: comparator and current sources.

A cell library, as illustrated in Figure 4.3, is generated by the IFA-based fault
macromodeling process for each PC. The database for each PC includes the number of
defects has been simulated, cell layout and layout area, the ranked fault types, the extracted
parameter values for each fault types, and some design information. The cell library is used
to construct a macro library, as illustrated in Figure 4.4. The test set of a macro is a
collection of the test sets of all PCs it employs, and the fault coverage of the macro is
estimated from those of the PCs. Given a macro specification, the macro schematic, Spice
file, and input sets for design verification were generated during the design phase. Based on
the macro circuit specification, parameters in fault types, and the input sets for design
verification, parameter deviation bounds for the macro are derived. The database of each
macro includes the macro specification, macro layout and layout area, design information,
test sets, and fault coverage. In our implementation, the hierarchical structure allows a
macro includes many other macros and/or PCs.

Since the test set of a macro is a collection of those of the PCs it employs, the test
set can be reduced by dropping the equivalent faults. For example, the voltage switch,
VSW, in Figure 4.5, has four fault types, as described in Section 3.2, and the op-amp (OP)
is assumed to has two fault types: The open loop gain is too small (fault type fopl), and the

output resistance r0 is too large (fopz). Since the faults on ro and ron have the same fault

lin

81

 

 

 

 

 

 

 

 

IT

Figure 4.5 Fault equivalence.

 

 

op lin l.__9"___|
r————'l V
W .
I I
i I rol
I I
1 I [Ki FE — I
l ' csw - —
\Jcsw 1. 1. .1 I..____...l
vsw
SE I_vsw; SE ,...-.1
. w 1' . Wt-
L _| L.__.l
l.Oll

82

behaviors when the voltage switch is on, as the equivalent circuit shown in Figure 4.5, the
fault type fopz is equivalent to the fault type f, in the VSW. Thus, dropping the equivalent
faults will reduce the number of fault types to be simulated and thus simplify the test

generation and fault simulation processes.

4.1.2 Fault Coverage Estimation

The fault coverage of a macro can be evaluated as follows. Let Api be the layout
area of the i-th primitive cell, Psi be the ratio of the significant defects over all injected

defects, and PC, be its fault coverage. Thus, the fault coverage of a macro is
PC = (ZAP,P,,FC,)/(ZAP,PS,) (4.2)

In practice however, the routing area is still susceptible to defects. The routing area
depends on applications. The fault coverage of the routing area should be also evaluated.
Consider a macro, namely, current copier, in Figure 4.1. It is comprised of four
primitive cells (PCs): current switch (CSW), voltage switch (VSW), storage element (SE),
and Op-amp (OP). The macro layout is shown in Figure 4.6(a). Figure 4.6(b) shows the
primitive cells and the remaining routing area.
The fault coverage for the routing area is evaluated as follows. Two major defects
on interconnects are considered: etching and extra. The etching defects cause the intercon-
nect layer to become narrower or even break, while the extra defects make two adjacent

interconnects to become closer or even short. Let Wt be the etching width caused by etch-

ing defect(s), as shown in Figure 4.7(a). A hard fault (open circuit) occurs if Wt > Wmax; a

parametric fault results if Wmin S Wt S Wmax; and no fault occurs if Wt < Wmin- Empirical

83

 

 

 

 

 

 

 

Figure 4.6 Macro “current copier”: (a) layout; and (b) routing area.

84

Fault ran e

 

1,-

1r
.JL

(a)

Fault range

Hard—fault range

    

lé—Di >1

 

Figure 4.7 Fault coverage for routing area: (a) due to etching defect; and
(b) due to extra defect.

85

results show that Wmax=2Wil3 and Wmin=wil3v where Wi is the width of the interconnect.
On the other hand, let Hx, as indicated in Figure 4.7(b), be the shrinking distance between
two interconnects due to extra defects. If the normal distance between two segment is Hi,

then the faults caused by extra defect(s) can be modeled as follows: a hard fault (short cir-

cuit) occurs if Hx < 0'; a parametric fault results if 0' S Hx S e; and no fault occurs if Hx > e,

where 0' and 8 are determined by the technology employed.
To simplify the estimation of fault coverage of both defects on the interconnects of
the routing area, it is assumed that only hard faults are testable. This implies that the fault

coverage is the worst case estimation. Let FCt be the fault coverage for the total faults
caused by the etching defects, Pm and Pts respectively be the probabilities of having the
hard faults and total faults. Thus, the fault coverage for etching defects is FCt=Pd,/Pts.
Hard faults due to etching defects occur if the etching width Wt > 2Wi/3. Let r be the

radius of the defect. Thus, the hard faults occur when the center of the defect locates

within a range with width of (2r—Wi/3) across the interconnect, as shown in Figure 4.7(a),
where r >Wi/3. Similarly, a fault occurs when the center of defect locates within a range

with width of (2r+Wi/3) across the interconnect, where r>Wi/6. Thus, the probability Pts is

Pts= A-l—ZJ; ,/6L'(2r + —)/(r)dr (43)

5 I

where As is the entire routing area, and the p.d.f. of the defect radius is given in (3.1).

Therefore,

3
Pts=Ai‘ZL.[§xo+!’— 6:: ], 1f(W/6)<x0, orP (5:218:50 ,if(W/6)>xo; (4.4)

 

 

3

0

86

Similarly, the probability of Pd, is

_ 1 W‘-
Pm- ziizfi/3Li(2r-?)/(r)dr , r>Wi/3.
Thus,

w. wf 9L
Pm=izt,[§ro-7ur_2 2],if(W/3)<xo;oer= _2__. _2_i__.‘:2 ,if(Wi/3)>x0; (4.5)

Let th and sz respectively be the probabilities of having the hard faults and total
faults due to extra defects. Thus, the fault coverage for extra defects is FCX=thlsz. Hard

faults due to extra defects occur when the center of the defect locates within the range with

width of (Zr-Hi+20') in the gap between the two adjacent interconnects, as indicated in
Figure 4.7(b), where (Hi-G)/2<r<rM and rM is a specified maximum value of r such that a
defect with radius larger then rM will also caused sever damage on primitive component.

Similarly, a fault occurs when the center of defect locates within the range with width of

(2r-Hi+2c) in the gap between the two adjacent interconnects, where (Hi-e)/2<r<rM. Thus,

 

the probability sz is
X
P’xs =TZflL _2€)D,(2r— Hi+2£)f(r)dr (46)
Therefore,
x2 2 H--—28
Pm: ifZD‘[’E+ 2'er H.- 2 2,] If (H 2£)<2rM (4.7)

Similarly, the probability of th is

87

 

2
Pm: %2fi;i_20)Dl-(2r—Hi+20)f(r)dr (4.8)
S i -—2—_
Thus,
P -"02 2 ”"2" 2 'fH2 <2 49
Xh" z;Di_;-;+ 2rM2 +Hi-2o ’1 ( l- 6) I'M (')

If we assume that the occurrences of both etching and extra defects have the same
probabilities, the fault coverage of the interconnects in the routing area is the average of

both fault coverages, i.e., FCS=(FQ+FCx)/2, or [Pm/Pts+th/szl/2- Therefore, the total

fault coverage of the macro is

PC = (215193ch + 2A .P .FC,)/(A,PS + Zapipsi) (4.10)

pl 51

where As is the area of the routing area, and P5 is the ratio of the significant defects over

the all defects.

4.2 Testability Design Rule

Due to the nonlinearity of their parameter-performance mapping, it is usually hard
to generate test set with high fault coverage for analog/mixed-signal ICs. In order to solve
this problem, the testability design rule has to be considered as early as in the design cycle.

A basic testability design rule has already been discussed in Section 3.3.2. This
section presents a refinement of the testability design rule defined by the given design
specifications, a set of discrete inputs used for design verification, and the fault types. The
mle ensures the existence of the circuit parameter deviation bounds for these discrete inputs

and for all fault types. The intersection of these parameter deviation bounds for each fault

88

type defines a parameter bound which is used to generate test vectors for that fault, to
determine whether or not the corresponding specification fails, and to evaluate the fault

coverage.

4.2.1 Development

Based on the test vector generation, the testability rule previously stated (Section
3.3.2) can be simplified as follows. The original testability rule requires that all gj intersects
at most one point at each of Ayilb and Ayiub, for all uje U. In fact, since only ujl and Ill“ are
taken as the test vectors, it is necessary only for gjl and gj“ to intersect at most one point
at Ayilb and Ayiub, respectively. Consider Figure 4.8(a), for example, g3 intersects Ayi“b at
three points, but 113 does not determine Arub. On the other hand, g2 intersects Ayilb at three
points, and u2 determines Ar“), but not Arub. Therefore, the testability design rule can be

modified as follows.

A designed circuit is easily testable if g’.1 and gi“ intersects at most one

point at Ayilb and Ayiub, respectively, for all Ayi.

The testability rule can be generalized. Consider the case of two-dimensional parameter

deviations, as shown in Figure 4.8(b), where U={u', uz, u3, u4}. The bound for each uj

includes the point AmO. The intersection of the four bounds, as indicated by the shaded
area, is bounded by those for u2 and u4. Thus, they are taken as the test vectors.

Figure 4.8(c) illustrates two cases that may affect the testability, where u2 and u4

89

Ar,‘bAr»1‘bz Jllb A

 

 

 

:LN
3&7".
m
[1:
I
:e
'E.I>
-2:
IL:

 

 

 

 

 

 

 

 

Figure 4.8 Examples for the definition of parameter deviation bounds:
(a) in l-dimension; and (b) & (c) in 2-dimension.

90

determine the parameter deviation bound Arb in the region Z. Suppose that g2 intersects
Ayi at two disjoint regions A and X, where X defines Arzb, and A and Y are also disjoint.
Therefore, when a parameter deviation occurs in region A, it may be tested as fault-free
with the application of the test vector uz, but it will be identified as faulty by 114 because

region A lies outside of the bound Ar4b. This implies that the circuit is still testable. On the

other hand, suppose that g2 intersects Ayi at two disjoint regions B and X, where B is
included by Y, and B and Z are disjoint. As a result, the parameter deviations in region B

are located outside of Ar3b and thus they can be detected as faulty when u3 is applied.

Unfortunately, u3 was not selected as a test vector. Thus, the fault can not be detected, and
u3 should be included as a test vector. This implies that, if g intersects Ayib more than one

regions bounded by all test vectors, then those inputs whose corresponding parameter
deviation bounds covers only the region with Ar=0, but disjoints from others, should also

be selected as the test vectors. This concludes that the circuit is easily testable if the g

functions intersects Ayib at most one region formed by the selected test vectors, and the

following testability rule for the general case r results.

A designed circuit is easily testable if g intersects Ayib in at most one region

bounded by all test vectors, for all Ayi.

Note that the rule allows more than one regions bounded by a vector, or many vectors, but

not all the vectors.

91

4.2.2 Discussion
The developed testability rule enables us to design an easily testable analog circuit.
If a circuit design fails to satisfy the rule, it will be very difficult to define the parameter

deviation bounds for test generation and fault coverage evaluation. For example, as shown

2

in Figure 4.8(a), if g2 intersects Ayi“b in more than one points, then 11 cannot be used as

the test vector. Therefore, we have to re-design the circuit to meet the testability design

2

rule. However, 11 can be still used as the test vector if the design specification can be

modified, i.e., Ayiub can be lowered so that g2 intersects Ayiub at only one point. This

implies that the testability rule may play an important role for the design trade-off of test-

ability and the design specification.

4.3 High-Accuracy Built-In Tester

The distortion caused by the interface between internal circuitry and external test
equipment is always a severe problem in the IC testing. One solution to this problem is
using the built-in tester (BITER). The BITER not only relieves the distortion, but also
simplifies the test generation process. In addition, with a low cost BITER, the expensive
ATE (automatic test equipment) may not be needed.

The BITER can be designed using a high accuracy CMOS current comparator. The
objective of a current comparator, as shown in Figure 4.9(a), is to check if the difference of

two input currents In and 1,2 are sufficiently small [52]. A corresponding voltage level Vy
with respect to the current difference Ix=I“-Ii2 is generated. Thus, the current comparator

is effectively a current-to—voltage (I-V) comparator. The generated voltage level is then

applied to a regenerative latch to determine the digital output [52]. The original CMOS

92

 

 

 

 

 

 

 

 

 

Regenerative
Latch

"-Q

 

 

Compensation Circuit

 

 

 

 

Iil —>‘ Current V
1:2 —’ Comparator
(a)
_XLI/
1. — '
I l Uncompensated '
Current
Ii2 — Comparator
(b)
Iii —* Current
112 —’ Comparator

 

 

 

..........................

...........................

 

 

 

 

 

Figure 4.9 Current comparators: (a) in [52]; (b) in [60]; and (c) proposed design.

93

current comparator was proposed in [53] using current mirrors to construct the input and
output stages. For high-speed current-mode circuits, positive feedback structures [54,55]
and prebiasing techniques [56,57] have been applied to improve speed performance. One
of the most critical parameters which limits current comparator performance is the offset
which affects the accuracy of comparators. The first offset compensated current compara-
tor was presented in [58] and generalized in [59,60] for accuracy improvement. Figure
4.9(b) shows an offset compensated current comparator which is comprised of a uncom-
pensated comparator and a compensation circuit [60]. It uses an amplifier and two holding

capacitors CM and Ch2 for the compensation circuit. Both switches in the compensation
circuit are first closed to form a feedback loop making Vy equal to the offset voltage of the

amplifier. When both switches are opened, both holding capacitors memorize the bias
point. In addition, the use of switches and capacitors alleviates the charge-injection error
effect [60], but both capacitors must be identical. Otherwise, the errors due to mismatched
components may be amplified by the amplifier and result in a large offset voltage. To avoid
the error amplification and still reducing the charge-injection errors, an alternative design
is developed. The comparator is used as a BITER of the SI circuits and thus it is expected
to have high accuracy with a moderate speed and can be operated in a low-voltage/low-
power environment.

Section 4.3.1 describes the design and operation of the developed high-accuracy
current comparator. The simulation results are presented in Section 4.3.2, and the perfor-
mance analysis of the comparator as a BITER is given in Section 4.3.3. Finally, the advan-

tages of using BITER are discussed in Section 4.3.4.

94

4.3.1 Design and Operation

Figure 4.9(c) shows the block diagram of the developed BITER which is comprised
of a current comparator, a voltage window comparator, and a digital latch. Suppose the
comparator is designed in such a way that a corresponding voltage level Vy, -VwSVySVw,
is generated for any input Ix, -Ito]SIx_<_Itol. Then, a simple voltage window comparator with
a pair of symmetric the threshold voltages, VW and -Vw, can be used. An ideal current

comparator, or I-V comparator, has a linear relationship between Ix and Vy as

V), = I,r rk (4.11)

where rk is a constant transresistance. In practice however, the accuracy may be affected
by: (a) the offset current due to mismatched components in the current comparator; and (b)
the nonlinearity of rk. The offset current may cause an offset voltage, Vofs, in the output of
the current comparator, while the nonlinearity of rk leads to a nonlinearity quality an(Ix)

which is a function of Ix. Thus, the output voltage Vy in (4.11) can be re-written as

Vy = Ix I'k + Vofs + anax) (4.12)

As a result, the accuracy of a current comparator can be improved by reducing the terms
Vofs and an(lx). The proposed comparator attempts to achieve very small Vofs and
moderate an(Ix)-

Figure 4.10(a) shows the circuit diagram of the proposed current comparator, where

the uncompensated comparator is constructed by the transistors M1, M3, M4, and M5. The

95

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset-Compensation
Circuit
3
w +
1 [_— _
;M2 I l
81
b C
(a)
A
: : ' ' : Vofs
Ii1 : j——-l—l—.- Iors Vc
: f—l—j—i—
Ii2 . . . . . r
Vy : i L_/——"— 09 1'02 8M2Vcr
. - - - . t.
Co‘mpensaticfil‘ Comparison 2
Cycle CYCIC
(c)
(b)

 

 

 

((1)

Figure 4.10 Current comparator: (a) schematic diagram; (b) switching sequence;
(c) small signal equivalent circuit when S1 is off; and

(d) & (e) offset-compensated amplifier.

96

input stage, comprised of the diode-connected transistors M4 and M5, results in a very small
input resistance and a near zero input bias voltage. To maintain large sensitivity of Vy with
respect to Ix, by (4.11), a large transresistance rk is required. In Figure 4.10(a), the
transresistance rk=rolllro3, where rm and r03 are the output resistances of M1 and M3,
respectively. Note that an output resistance roi is approximately inversely proportional to
the drain current Idi, i.e., roi z 1/(Mdi), where A is channel modulation coefficient. Therefore,
a large transresistance rk can be obtained by keeping small drain currents Id] and Id3, for
M1 and M3. The offset compensation circuit is comprised of a current copier with a
negative-feedback amplifier [IS-20,22] and a bias current source lb. The bias current 1b is
equal to the current difference (Idl-Id3). The current copier includes a transistor M2, an
amplifier A, a holding capacitor C, and a switch 81.

Figure 4.10(b) illustrates the switching sequence of S], the application of input
currents, and the resultant output voltage of the proposed current comparator. The circuit
takes the first two clock cycles for the offset-compensation process, where S] is closed and
Ii1=Ii2=0. At the end of the offset compensation process, the current lb, =Id1-Id3, is held in
M2, 81 is opened, and Vy is biased with the offset voltage Vofs which is the sum of Va, the
offset of the amplifier A, and Vch, the offset voltage caused by the charge-injection errors.
After the offset compensation process is completed, the comparison process takes place,
where two input currents I“ and 1,2 are applied. As illustrated in Figure 4.10(b), two
identical input currents, In=li2 are applied to the comparator in the third cycle, and a zero-
valued Vy results. On the other hand, two inputs currents Ii1> Ii2 are applied in the forth
cycle, a negative Vy is obtained.

To analyze the offset voltage of the comparator, a small signal equivalent circuit is

97

shown in Figure 4.10(c), where S1 is opened, and only those effects caused by the offset
current and charge-injection errors are considered. In Figure 4.10(c), rop=r01llro3, Iofs is the
equivalent offset current caused by the offset voltage of the amplifier A, and ch is the
deviation of the voltage across the holding capacitor C due to the charge-injection error

effect. Therefore, the offset voltage is expressed as

Vofs = Va 4' Vch' (4.13)
where

Va = (ropllfoz)lofs and Vch = (ropllr02)(gM2ch). (4.14)

To reduce both Va and Vch, the current copier should be designed as follows. The negative
feedback amplifier A is implemented by two identical amplifiers, as shown in Figure
4.10(d). The amplifier A2 forms a unit-gain buffer which produces the offset voltage Va to
cancel that produced by the amplifier A1. Both amplifiers are realized by differential pairs,
as shown in Figure 4.10(e). On the other hand, the term Vch can be decreased by reducing
gMZ. Since gMFM, where B and 1:12 are the gain factor and drain current of M2,
respectively, 81m is reduced if a small Id2 is used. In Figure 4.10(a), the drain current Id2 is
determined by the biased current lb. In fact, IdZ is much smaller than both Id] and Id3, and
thus the output resistance r02 is very large. In Figure 4.9(b), a pair of switch/capacitor was
used in [60] to reduce the charge-injection error effect. But, the error due to mismatched
components may be amplified. In this implementation, the switch/capacitor circuit is
moved to the output of the amplifier, and thus the charge-injection error effect will not be

amplified. Since the current copier is used as the compensation circuit, no well-matched

98

components are needed.

Finally, the term an(Ix) in (4.12) may be increased rapidly if both transistors M1
and M3 are operated towards the linear region. Therefore, to keep an(Ix) reasonably small,
both transistors must be operated in the saturation region. This can be achieved by
appropriately choosing the threshold voltage, Vw, of the window comparator. Note that the
threshold voltage VW should be smaller than both the threshold voltages of NMOS and

PMOS transistors.

4.3.2 Simulation Results

The current comparator has been designed and simulated by Pspice with the MOSIS
S CN 2pm CMOS process parameters and 2V supply voltage. The transistor dimensions for
current comparator and the amplifier in Figures 4.10(a) and 4.10(e) are listed in Figures
4.11(a) and 4.11(b), respectively. The drain currents and the bias current in Figure 4.10(a)
are assigned as: Id1=0.9|.tA, Id2=0.1|.tA, Id3=l 11A, and Ib=0.1 [1A. Figure 4.1 1(c) shows the
circuit layout generated by the layout editor, Magic. The layout size is approximately
0.01mm2.

As mentioned, 51 in Figure 4.10(a) is closed during the offset compensation
process. The current copier memorizes the bias current Ib and sets Vy to the offset voltage
Vofs. Figure 4.12(a) plots the transient responses of the comparator. Results show that the
circuit, in the offset compensation process, is settled within 0.1% of accuracy in nearly
1.8115, where the voltage V3, is settled at about Vofs=10uV. Note that the offset voltage Vofs

is contributed only by Va. In other words, the offset voltage of the amplifier is Va=10uV.

Switch 8, is then opened at 2.5115 in this simulation, the voltage Vy is changed due to

99

Parameter values for

Current Comparator Parameter values for

Offset-Compensated Amplifier

m1

IuA
lpA
+1V,-1V

 

Figure 4.11 Proposed current comparator: (a) parameter values of Figure 4.10(a);
(b) parameter values for Figure 4.10(e); and (c) physical layout.

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

   

4 FF fl I I I I T if
3.. ...... . ,. ., ..
2.. ...s..........u . ...-..........a..... ....l: ......................................... _1
S. 3.
g 0 ‘. ... , q
5‘ k
_1” ,.. . ...; ........................................ .1
-2. ..
_3- q
_4 _L I 1 1 1 1 1 1
O 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Tlmo(us)
(a)
0.3 T Y T Y
0'2” ________ ‘SOnA
0.1 ..

      
 

  

 

 

 

.9
E 0 I “ " "‘ o L‘
g. | _.-
I ll
1 ._:<
-o.1 : ‘
I
I
l
' 4
-°-2 ------- —50nA
_o.3 1 1 L
o 05 1 15 2 25 3 35 4 45 s

Time. (us)

(13)

Figure 4.12 Transient responses: (a) during the compensation process;
and (b) during the comparison process.

101

1/0 chamctorlotlc curvo of tho cumnt comparator

 

600 ‘T I Y I' T Y I V I

W ("M

 

 

 

 

 

o- -
-—50- -1
—100L 4

WM!)
é

 

 

 

 

 

 

 

-—2oo - —
I

-250 - , » - ; -

“WM/WW .

..350 L .

 

0 0.06 O. 1 0.1 5 0.2 0.26 0.3 0.35 0.4 0.45
Froquonoo (MHz)

 

anllx) (mV)

 

 

 

L I L L

 

:?OO —80 —60 —40 —20 20 4O 60 BO 1 DO

0
Is: (M)

(C)

Figure 4.13 Simulation results: (a) Ix-Vy characteristic curve; (b) harmonic
distortion; and (c) nonlinearity element Vn.(Ix) vs Ix & Vy.

102

charge-injection errors. As shown in Figure 4.10(a), Vy is about 0.6mV. Figure 4.12(b)
plots the transient responses of the comparator during the comparison process. Since the
circuit, in the offset compensation process, can be settled at 1.81.15, here the input currents
are applied after 21.15 when Switch S, is opened. The plot shows that, as indicated by the
dotted lines, Ix=50nA is applied in the third cycle, and Ix=-50nA is applied in the forth
cycle. Results show that it takes about 600ns for Vy to settle.

Figure 4.13(a) plots Vy with respect to Ix ranged from -100nA to 100nA, and the
transresistance rk=(Vy/Ix)z-5.33x106£2. Consequently, the equivalent offset current
Ids: ofS/rk= (0.6m)/5.33x106, i.e., Iofs=0.1nA. The harmonic distortion has also been
analyzed with the input difference current Ix, a sinusoidal waveform with a 100nA peak-
to-peak amplitude, and the simulation results, as plotted in Figure 4.13(b), show that an
attenuation of 55dB results on second and third harmonics. Figure 4.13(c) plots the
nonlinearity element an(Ix) with respect to Ix ranged from —100nA to 100nA. Results show
that a maximum Vn](Ix)=4mV occurs when Ix=-80nA, or, equivalently, by Figure 4.13(b),
the maximum an(lx)=4mV occurs when Vy=440mV.

In summary, simulation results show that the offset voltage of the amplifier in
Figure 4.10(e) is Va=10uV and the equivalent offset current is Iofs=0. lnA. The maximum
an(Ix)=4mV occurs when Ix=-80nA, or Vy=440mV. The simulation result has shown that
the proposed comparator achieves high accuracy and can be operated in low-voltage (Vdd-
Vss=2V supply voltage) environment. The power dissipation is only 20uW. However, the
circuit takes about 600ns for Vy to settle which is rather slow, but it is sufficient for the
built-in tester application.

For built-in tester application, the threshold voltage VW is determined by the

103

predetermined tolerable current Ito]. For example, if Itol=40nA, by Figure 4.13(a), we
choose Vw=213.2mV. As a result, --VWSVySVw for all Ix, ~1t01SIxSIm]. VY=Vw if Ix=-Itol,
and V),=-Vw if [film]. Let an+=an(-Iml) and an’=an(I,ol). In this case, by Figure 4.13(c),
Vn1'=- 1 .SmV and an+=2.6mV. Since Vofs=-0.6mV, the maximum and minimum values of

Vy are

Vy(max)=Vw+Vofs+an+=2 15.2mV, and Vy(mn)=-Vw+VofS+an'=-215.3mV.

Therefore, the threshold voltages of the window comparator are chosen by V1=215.2mV,
while V2=-215.3mV. Similarly, if Itol=80nA, then we choose V1=Vy(max)= 429.8mV and
V2=Vy(min)=--426.4mV, where Vn1’=0.6mV and an+=4mV. On the other hand, for
1.01:20nA, we choose V1=Vy(max)=104.6mV and V2=Vy(min)=-108.3mV.

In the design of a window comparator, a comparator with symmetric threshold
voltages, i.e., V1=-V2, is much easier than that with non-symmetric ones. Since the terms
(Vofs+an+) and (Vofs+Vn{) are relatively smaller than VW and -Vw, respectively, for design
simplicity, we may choose V1=Vw and V2=-VW as the threshold voltages of the window
comparator. However, with such an implementation, the window comparator may produce
incorrect results in the following ranges [Vw,Vy(max)] and ['Vw’vy(min)]° Since Vw,
(Vofs+an+), and (Vofs+Vn1') are determined by Ito], hence the probability that Vy lies in
those ranges depends upon [to] and the distribution of Vy is similar to that of Ix with a scalar

factor rk. The detail discussion is presented in the next section.

104

4.3.3 Performance Analysis
For design simplicity, the threshold voltages of the window comparator are chosen

as V1=VW and V2=-Vw. For a given [to], the voltage Vw is chosen from the plot in Figure
4.13(a). For the ideal case that the relation between Ix and Vy is linear, then -VWSVySVW
for all Ix, - tolflxs [.01. Therefore, the window comparator with the threshold voltages
V1=VW and V2=-VW determines the result correctly. On the other hand, when the offset
voltage and nonlinearity of the current comparator are taken into consideration, the win-
dow comparator may not always provide correct comparison in the ranges [V W’Vy(maX)]

and [-szvy(min)], where Vy(max)=Vw+Vofs+an+ and Vy(min)=-VW+V0fS+VnI-' More spe-

cifically, given a current Ix, Ix>Iml, its corresponding Vy may be Vy < Vy(min) and Vy _>. -
Vw, i.e., V), lies in ['VWtVy(min)]' Since Vy < Vy(min)t or Ix>ltol, a “fail” comparison should
be resulted. However, because Vy lies in [-Vw,Vy(min)], the window comparator will mis-
judge the result and a “pass” comparison will result. Similarly, given a current Ix, Ix.<_lml,
its corresponding Vy may lie in [Vw,Vy(max)]. A “pass” comparison may be misjudged by
the window comparator and a “fail” comparison results. In other words, some comparison
results are misjudged due to the choice of the threshold voltage of the window comparator.
This section is to analyze the quality of the built-in tester which is constructed by the cir-
cuit shown in Figure 4.9(c). We define a testing confidence of the built-in tester as the
probability that the comparison results are reliably determined. Thus, this section discuss
the testing confidence of the proposed built-in tester with respect to the selected current
tolerance.

Assume that the probability density function (pdf) of Ix is Gaussian with a zero

105

mean, i.e., E(Ix)=0. By (4.12), the pdf of Vy is also a Gaussian if the nonlinearity term
an(Ix) is very small compared with Ixrk. (The statement is true and can be verified from
Figures 4.13(a) and 4.13(c)) Therefore, if the term Vn](Ix) is omitted, the mean of the dis-

tribution for Vy is

E(Vy)=rk E(Ix) +vofs = of, (4.15)

Figure 4.14(a) shows the Gaussian distribution for Vy~N(Vofs, 0‘2), where c is its standard
deviation.
By the definition, the testing confidence of the built-in tester is expressed as

follows,

 

 

2
Vy(min) 1 (V _ Vofs)
Pr = 1 - [ exp y V
C I'Vw J21“). [ 202 y

 

 

2
Vyrnax V _V
+j ‘ ’ 1 exp ( Y 2"") Vy] (4.16)
Vw x/ZTCO' 20'

With the standardization, the testing confidence can be re-written as

PTC = l - FD“-Vw+Vn|-)/O')-q)(('Vw-VofS)/C)]

- [<D((Vw+an+/G)-<D((Vw-Vofs)/o)] (4.17)
where
<l>(x)= f Lexp(—y—2)dy (4.18)
-°° 2n 2

106

 

 

     

 

A
f

 

_vw/ '\ 0

.V
Vy(nfin)='vw+vofs+vnl °fs Vw Vy(imam)=Vw~“’ors+Vm+
(a)

 

 

 

 

 

 

 

 

 

.5 10 10.5 11 11.5 12 12.5 13 13.5
Room

Figure 4.14 Performance analysis: (a) Gaussian distribution of V,;

(b) statistical confidence vs. window threshold voltage;
and (c) statistical confidence vs. resolution.

107

Figure 4.14(b) plots the testing confidences for various standard deviations: (1)
0:0.4264V, (2) 0:0.2132V, (3) O'=0.1066V and (4) 0:0.071V, where Vofs=-O.6mV. From
Figure 4.13(c), Vy=O.4264V is equivalent to Ix=80nA. The simulation results plotted in
Figure 4.14(b) may be interpreted as follows: When sz0, the nonlinearity element is near
zero, i.e., (Vofs+an+)= (Vofs+an')=Vofs. Thus, as 0' increases, the total shaded areas
decrease and the testing confidence increases. As VW increases, the increase of nonlinearity
element an(Ix) causes that the total shaded areas increase and the testing confidence
decreases for each 0. Our empirical results show that the testing confidence keeps
decreasing until sz0, for small 0'. The plots also show that, when VW > 300mV, the
testing confidence increases as 0 decreases. As shown in the curve (4), 0:0.071V, with
Vw=300mV, the testing confidence can reach almost 100%.

Since the choice of VW is determined by the given 1.0., Figure 4.14(c) plots the
relationship between the testing confidence and the testing resolution for the testing
resolution is defined as the number of bits that represent the ratio Itol/Imax, where 1mx be
the maximum difference current applied to the built-in tester, i.e., Imax=lx(max).

Mathematically, the number of bits, b, is

b =f logzamax/Imlfl (4.19)

For example, if Imax=100ttA and 1:01:40DA’ then, by (4.19), the resolution is b=12 bits. For
Itol=20nA, the testing resolution is 13 bits. Therefore, given a tolerance current 1.01, the

threshold voltage VW of the window comparator is chosen as

108

vw = Imlrk = (Imam/(2b) (4.20)

In Figure 4.14(c), 6:0.1066V, Imax=100uA, and rk=5.33x106. If b=11, by (4.20), the
threshold voltage Vw=260.2mV is chosen. By Figures 4.14(b) and 4.14(c), the testing

confidence is over 99.9%.

4.3.4 Built-In Tester and Test Sequence

The hi gh-accuracy current comparator can be used as a built-in current tester. Con-
sider the ADC in Figure 4.15(a) which is a simplified version of the ADC in Figure 3.4,
where the digital part is included. Figure 4.15(b) illustrates the implementation of the cur-
rent tester to the ADC, where the voltage window comparator, WCP, is realized as illus-
trated in Figure 4.15(c). Two multiplexers X1 and X2 are used in WCP. During the normal

Operation, X1 and X2 are switched to Ground and V53, respectively, and the output of
WCP is set to a “1” if Vy > 0, and to a “0” otherwise, while they are set to VW and -Vw

during the test mode.

As illustrated in Figure 2.3, the ADC achieves a ll bits resolution and, without a
built-in tester, the ADC requires a test sequence which is comprised of 11 same test cycles
(Figure 3.5) to detect the faults. In practice however, the test sequence length (number of
test cycles) can be reduced significantly if a better comparator or tester with high accuracy
is used. Because the ADC in Figure 2.3 is implemented by using a multiply-by-two cir-

cuit, the tolerance current 1.01 will be doubled in each test cycle. That is to say, before the
beginning of the test sequence, the original Ito. is 2"LSB; while after one test cycle, le

becomes lLSB, and it would be 2LSB after two test cycles. Thus, Itolz2M'lLSB after M

109

 

 

 

 

 

 

 

V0“!
\ J43.
-F+/CP/ an? 0
ADC _ I Tx
X >Y
.1:-
' Cramp

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(C)

Figure 4.15 ADC with built-in tester: (a) ADC; (b) with built-in tester;
and (c) window comparator.

110

test cycles. Obviously, if we want to decide if the ADC is faulty, i.e. the error current

exceeds Ito], just after M test cycles, then a current tester which is capable of detect 1.01 is
needed. By (4.19), a current tester with resolution b is thus required such that 1.01:2”
lLSB=2‘bImax. For the 11-bit ADC in Figure 2.3, Imax is equal to Iref. Therefore, 2M"

1LSB=2"’Iref=2“'bLSB. This is to say, b=12-M. Because the test sequence of the ADC
has 11 test cycles(M=1 l), a comparator (or tester) with resolution of only 1 bit (b=1) can
be used. If a shorter test sequence, i.e. smaller M, is wanted, then a tester with higher reso-
lution, i.e. larger b, is needed. In the most extreme case, if we want to eliminate all the test
cycles in Figure 3.5 (M=0) and test the building blocks, current copiers, directly, then a
current tester with 12-bit resolution is required. According to the performance analysis in

Section 4.3.3, the proposed high-accuracy current tester can provided 12-bit resolution

(with VW equal to 130mV, by (4.20)) with test confidence over 99.5%. Thus, the ADC

which uses the proposed built-in tester (Figure 4.15(b)) can effectively achieve zero test
sequence length. Although the comparator in Figure 4.10(a) requires a test sequence
length of 11 test cycles, it contains only 16 transistors. The ADC using proposed built-in
current tester in Figure 4.10(b) needs no test sequence, but it contains 36 transistors. Thus,

there exists a design trade-off between comparator circuit complexity and the test length.

Chapter 5

HIERARCHICAL TESTABILITY DESIGN SYSTEM

Based on the hierarchical fault macromodeling process, this chapter presents a
hierarchical testability design system, namely, PETOMIC (Packages for Enhancing Test-
ability Of Mixed-signal Integrated Circuit). The system has been developed and imple-
mented in C language, Pspice, Matlab [62,63,64]. The system includes two routines
(Figure 5.1), CLG_Routine and MLG_Routine. The former generates a cell library, as dis-
cussed in Figure 4.3, while the latter builds a macro library, as illustrated in Figure 4.4.
Given a reasonably large analog/mixed-signal circuit, the user first partitions the circuit
into smaller circuits and employs PETOMIC to generates both cell library and macro
library including all primitive cells and macros contained in that circuit.

Section 5.1 describes the system development for the routine generating the cell
library with a detailed example, while Section 5.2 presents that for the routine for generat-

ing macro library.

5.] CLG_Routine
CLG_Routine, as show in Figure 5.], is a routine that generates the cell library.
The routine contains three major subroutines: DG (Defect Generator), FBE (Fault Behav-

ior Evaluator), and FTCE (Fault Type Classification Environment). The above three

[I]

112

cell Library Generation
(CLG_Routine)

 

Defect Generator
(DG)

 

 

Fault Behavior Evaluator
(FBE)

 

Fault Type Classification
Environment
(FTCE)

Macro Library Generation
(MLG_Routine)

 

Faulty Performance Evaluator
(FPE)

 

 

Figure 5.1 Structure of PETOMIC.

113

 

Cell Layout

 

 

 

 

 

 

 

 

Defect Generator
(DG)

i

 

Defective
Cell Layout

 

 

 

 

l

Layout Extractor of Magic
or Ledit

 

 

Spice Extraction Files

for the Significant
Defects
f_1.spice
f_2.spice
f_3.spice

 

 

 

 

 

 

 

Figure 5.2 The use of defect generator in cell library establishing.

114

subroutines implements the three steps in Figure 4.3 for generating a cell library.

The DG takes a cell layout as its input, as shown in Figure 5.2, produces defective
cell layouts. Either Magic [65] or Ledit [66], layout editors, is used to extract Spice files
from both good and defective layouts. In this discussion, the Opamp in a current copier is
used to demonstrate the procedure. The good and defective Opamp layouts are shown in
Figure 5.2. The DG subroutine generates a Spice file, namely, f_O.spice, for the good cell,
and Spice files, namely, f_i, for the i-th defective cell layout, where i=1,2,...,n. In this
implementation, the file “f_7.spice” indicates the Spice file for the 7-th defective cell lay-
out. Figure 5.3 shows the Spice sub-circuit K, where the middle part is generated from the
DG, and both top and bottom portions are added by the user. A Matlab program “dfect-
gen.m” is used to implement the routine DG and the program must be executed with the
Matlab environment.

To evaluate fault behaviors, a set of parameters to be extracted must be prepared.
For example, for the Opamp, three parameters, offset voltage, DC gain, and output resis-
tance, will be extracted for evaluating the fault behaviors. The test circuits for extracting
parameters are illustrated in Figure 5.4. In Figure 5.4(a), the offset voltage, Vin, is selected

when the absolute value of V0 is minimum, where Vin is swept from -2.5V to 2.5V. In Fig-
ure 5.4(b), the DC gain is obtained by applying an AC signal, Vin, with an amplitude l, and
checking the amplitude response of v0 at very low frequency. Finally, in Figure 5.4(c), the
output resistance is the value of V0 at very low frequency when an AC current source with

an amplitude of 1 is applied to the output of the Opamp with its two inputs grounded. Fig-
ure 5.5 presents the Spice files for the circuits setup in Figure 5.4, and it is called

“prem.cir”.

4F!

 

K

I‘ Extraction file of good or defective cell layout

 

f

115

.subckt K 122 147 100 156 117
*body

 

**
*‘k
**
**
*i'

**

M0

M1

C1

**

C6

**

C7

**

**
**

it

 

SPICE file for circuit ampadc
Technology: scmos

NODE: 156 GND
NODE: 100 = Vdd
NODE: 2 = Error

RLUMPO 100 101 3959.5
RLUMPl 102 103 215.0
RLUMP2 102 104 215.0

101 103 104 100 pfet L=5.0U W=8.0U

RLUMP3 100 105 3959.5
RLUMP4 102 106 215.0
RLUMPS 107 108 373.5

105 106 108 100 pfet L=5.0U W=8.0U

154 156 57F
NODE: 154 = Iref

117 156 168F
NODE: 117 = Vout
115 156 59F
NODE: 115 = V0

NODE: 100

= Vdd
NODE: 156 = GND!
NODE: 100 = Vdd!

 

 

 

*body

Cc 117 115 1p

Iref 100 154 25.5u
.ends

Figure 5.3 Example of extraction file and K.

116

Vdd=2.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vin
+
K V0
b
Time Vss=-2.5V
(a)
Vdd=2.5V
Vin
‘ +
1 K V0
’
f — _:___ VSS-=-2.5V
(b)
Vdd=2.5V .
1x
A
1

 

 

 

(C)

Figure 5.4 Experiments for extract parameters from cell K,
Opamp in this example.

117

 

 

* Retrieve Voff

xarnp 3 O l 2 4 K

Vdd 1 O 2.5

Vss 2 0 -2.5

Wu 3 0 dc -2

.Lib K

.dc Vin -2 2 0.01

.print dc v(4)

.Model sv vswitch Ron=4e5 Roff=1e6

+von=2 voff=-2

*parameters: MOSIS 2 micron CMOS process

.model nfet nmos 1evel=2 Ld=.115u TOX=423e-10 NSUB=1.0125225e16
+VTO=.822163 kp=4.893760e-5 gamma=.47 phi=0.6 UO=599.496
+UEXP=5.324966e-3 UCRIT=12714.2 DELTA=3.39718e-5 VMAX=65466.1
+XJ=0.55u lambda=1.991479e—2 NFS=5.66758e11 Neff=1.0010e-2
+NSS=0.0 TPG=1.00 rsh=28.070 CGSO=0.9388e-10 CGDO=O.9388e-10
+cj=l .4563e-4 MJ=O.6 cjsw=6.617e-10 mjsw=0.31

.model pfet pmos 1evel=2 Ld=.18u TOX=423e-10 NSUB=1.421645e15
+VTO=-.776658 kp=1.916950e-5 gamma=.52 phi=0.6 UO=234.831
+UEXP=O. 142293 UCRIT=20967 DELTA=1e-6 VMAX=34600.2
+XJ=O.4lu lambda=4.921086e-2 NFS=4.744781e1 1 Neff=l .OOlOe-2
+NSS=0.0 TPG=-1.00 rsh=45.92 CGSO=1.1957e-10 CGDO=1.1957e-10
+cj=2.4e-4 MJ=O.5 cjsw=3.62e-10 mjsw=0.29

.OPTIONs RELTOL=1E-6.5 pivtol=le-36 pivrel=le-36

+CHGtol=le-13 Abstol=le-13 VNtol=1e-101t15=01tl4=80
+NUMDGT=8 gmin=1e-18

NOECHO NOMOD NOPAGE

.end

* Retrieve Adc

.xamp 3 0 1 2 4 K

Vdd 1 O 2.5

Vss 2 0 -2.5

vin 3 0 ac 1 dc -0.14

.Lib K

.ac dec 10 1 1k

.print ac v(4)

.Model sv vswitch Ron=4e5 Roff=1e6

+von=2 voff=-2

*parameters: MOSIS 2 micron CMOS process

.model nfet nmos 1evel=2 Ld=.115u TOX=423e-10 NSUB=1.0125225e 16
+VTO=.822163 kp=4.893760e-5 gamma=.47 phi=0.6 UO=599.496

 

Figure 5.5 Example of prem.cir.

 

118

 

 

+UEXP=5.3249666-3 UCRIT=12714.2 DELTA=3.397I 86-5 VMAX=65466.1
+XJ=0.55u lambda=1.99l479e-2 NFS=5.66758e11 Neff=1.0010e-2
+NSS=0.0 TPG=1.00 rsh=28.070 CGSO=O.9388e-10 CGDO=0.9388e-10
+cj=1.4563e-4 MJ=O.6 cjsw=6.617e-10 mjsw=0.3l

.model pfet pmos level=2 Ld=.18u TOX=423e-10 NSUB=1.421645e15
+VTO=-.776658 kp=1.916950e-5 gamma=.52 phi=0.6 UO=234.831
+UEXP=0.142293 UCRIT=20967 DELTA=1e—6 VMAX=34600.2
+XJ=0.4lu lambda=4.921086e-2 NFS=4.744781e11 Neff=1 .0010e-2
+NSS=0.0 TPG=-1.00 rsh=45.92 CGSO=1.1957e-10 CGDO=1.1957e-10
+cj=2.4e-4 MJ=O.5 cjsw=3.62e-10 mjsw=0.29

.OPTIONs RELTOI;1E-6.5 pivtol=1e-36 pivrel=1e-36

+CHGtol=le~13 Abstol=le-13 VNtol=1e-101t15=01tl4=80
+NUMDGT=8 gmin=1e-l8

NOECHO NOMOD NOPAGE

.end

* Retrieve ro

xarnp 3 O 1 2 4 K

Vdd 1 0 2.5

Vss 2 0 -2.5

vin 3 0 -0. l4

ix 0 4 ac l

.Lib K

.ac dec 10 1 10k

.print ac v(4)

.Model sv vswitch Ron=4e5 Roff=1e6

+von=2 voff=-2

*pararneters: MOSIS 2 micron CMOS process

.model nfet nmos 1evel=2 Ld=.115u TOX=423e-10 NSUB=1.0125225e16
+VTO=.822163 kp=4.893760e-5 gamma=.47 phi=0.6 UO=599.496
+UEXP=5.324966e-3 UCRIT=12714.2 DELTA=3.397l8e-S VMAX=65466.1
+XJ=0.55u lambda=1 .991479e-2 NFS=5.66758e1 1 Neff=1.0010e-2
+NSS=0.0 TPG=1.00 rsh=28.070 CGSO=O.9388e-10 CGDO=0.9388e-10
+cj=1.4563e-4 MJ=O.6 cjsw=6.617e-10 mjsw=0.31

.model pfet pmos level=2 Ld=.18u TOX=423e-10 NSUB=1.421645e15
+VTO=-.776658 kp=1.916950e-5 gamma=.52 phi=0.6 UO=234.831
+UEXP=0.142293 UCRIT=20967 DELTA=le-6 VMAX=34600.2
+XJ=0.41u lambda=4.921086e-2 NFS=4.744781e1 1 Neff=1.0010e-2
+NSS=0.0 TPG=-1.00 rsh=45.92 CGSO=1.1957e-10 CGDO=1.1957e-10
+cj=2.4e—4 MJ=0.5 cjsw=3.62e-10 mjsw=0.29

.end

 

Figure 5.5 (continue)

 

119

The FBE takes the Spices files previously generated, as shown in Figure 5.6, as its
inputs and generates a list of fault behavior values. The FBE, executed by the program
“ifa_fbe.exe”, evaluates the fault behaviors from executing the Spice file “prem.cir” with
the sub-circuit K, where K is substituted, in turns, by f_O.spice and f_i.spice, for all i. Note
that the code “.Lib K” in the “prem.cir” (Figure 5.5) indicates that the sub-circuit K
defined above. The resultant fault behaviors are listed in Figure 5.7. Finally, the FTDE,
executed by a Matlab program “ifaftde.m”, is an environment that defines the fault types,
and provides a fault behavior display window, as shown in Figure 5.8, for user to define
the fault types. In Figure 5.8, the offset voltage, DC gain, and output resistance are
denoted as Parameters A, B, and C, respectively, where the parameter values are the nor-
malized deviation values. Results show that a group of fault behavior values result in a
deviation of about -17 on the offset voltage (Parameter A), but almost no deviations on
both DC gain (Parameter B) and output resistance (Parameter C). Thus, the fault behaviors
are concluded as a fault type, Offset voltage is too large, referred to as Type I fault. Simi-
larly, we can identify the other fault type, Large offset voltage, small DC gain, and small
output resistance, referred to as Type 2 fault.

The resultant cell library information for Opamp indicates that the cell layout area

is 21837 (um)2, and 700 defects were injected. Among the 700 defects, there are only 48
significant defects. It also shows that 6 significant defects cause simulation failures during
the process of FBE, thus they will lead to hard faults. Among the remaining 42 significant
defects, 10 are Type 1 faults, while 32 are Type 2 faults.

Figure 5.9 summarizes the program files, input files, and output files used in the

CLG_routine. Two major programs, ifajbeexe and ifafidem, are used and they include

120

 

Spice Extraction Files

 

 

 

 

for the Significant
Defects
_ _ f_l .spice . Prepare Spice 5
Prepare Spice Library f_2.spice :Program for Extracting:
for the 800d cell f_3.spice q Fault Behavior Valuesig‘g

 

 

 

 

 

 

 

 

Fault Behavior Evaluator
(FBE)

1

List of Fault Behavior
Values

Fault Type Classification Environment
(FT CE)

Cell Library

 

:

 

 

 

 

 

 

 

 

 

 

 

List of Fault Behavior
Values

 

 

 

 

Ranked Fault Types

 

 

 

 

Figure 5.6 The use of fault behavior evaluator and fault type classification
environment in cell library establishing.

121

 

 

Cell Library for Primitive Component ‘ampadc’

 

Layout_area(um"2)= 21 837
N_of_injected_defects= 700

Detected Output Variables of Premitive Simulation #1

dc --------- > sigl
v(4) --------- > sig2
Detected Output Variables of Premitive Simulation #2
ac --------- > si g3
v(4) --------- > sig4
Detected Output Variables of Premitive Simulation #3
ac --------- > si g5
v(4) --------- > sig6

Parameter1= sig2(200)
Norminal value of parameter1= -O. 14

Parameter2= sig4(2)
Norminal value of parameter2= 68.093461

Parameter3= sig6(2)
Norminal value of parameter3= 1.573879e+5

List of fault behavior values(normalized deviation):
(lst column: index of defects; last column: norm)

1 -1.8857143e+01 -1.0000000e+00 -1.0000000e+00 l.8910099e+01
2 -1.6572788e+01 1.3068817e-02 8.8352408e-03 1.6572795e+01

3 -l.6572788e+01 1.3068817e-02 8.8352408e-03 1.6572795e+01

 

Figure 5.7 Example of cell library.

 

122

 

 

4

5

6

8

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

27

28

-1.6572788e+01 1.3068817e-02 8.8352408e-03 1.6572795e+01

-1.7586038e+01 -l.0000000e+00 -9.8446606e-01 1.7641936e+01

1.68502 17e+01

-1 .7580645e-1-01

-1.6621526e+01

-1.6539791e+01

1.6833645e+01

1.68328756+01

-6.8232061e+00

-1.66147046+01

-1.5623640e+01

1 .6720809e+01

-1.7959396e+01

-1.7611227e+01

1.6846133e+01

l .6855477e+01

-1.7009515e+01

-1.6500823e+01

-1.6500823e+01

1.68559306+01

1.6857143e+01

-9.9996792e-01 -9.4990723e-01 1.6906569e+01

-1.0000000e+00 -9.8439981e-01 1.7636556e+01

4.6783200e-02 -3.2783969e-02 1.6621624e+01

4.7342431e-02 2.8293090e—02 1.6539883e+01

~9.9994250e-01

-9.9993934e-01

-9.44974406-01

4.6763521e-03

-9.3104522e-01

-9.999969Se-01

-9.4794733e-01 1.688994le+01

-9.47773786-01 1 .688916Be+01

-9.3952527e-01 6.9521094e+00

8.7878420e-03 1 .6614707e+01

-9.3485659e-01 1.5679252e+01

-9.4990989e-01 1.6777597e+01

-l.0000000e+00 -9.86480826-01 1.8014246e+01

-9.9974363e-01

-9.9994609e-01

-9.9999407e-01

-9.8954084e-01

2.2 174097e-02

2.2 l74097e-02

-9.9999787e-01

-9.8412991e-01 l .7667012e+01

-9.4990537e-01 1.6902497e+01

-9.4990906e-01 1 .691 18 l 3e+01

-9.6569965e-01 l .7065619e-I-01

2.7479940e-02 1 .6500861e+01

2.7479940e-02 1 .650086 1 e+01

-9.5637415e-01 1.6912629e+01

-1.0000000C+OO -1.0000000e+00 1.6916361e+01

 

Figure 5.7 (continue)

 

123

 

 

29

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

-1.6558173e+01

1.6857 143e+01

-1.8818706e+01

1.6857143e+01

1.6857143e+01

-9.9963657e+00

-1.6499108e+01

1.6857143e+01

-1.8857143e+01

-1.7112481e+01

1.6833710e+01

-1.7611227e+01

-1.8857143e+01

1.6833710e+01

1.6857143e+01

-l .8818708e+01

-1.7959374e+01

-1.7398881e+01

2.5844376e-02 1.7222544e-02 1.6558202e+01

-1 .0000000e+00 -9.4990993e-01 1 .6913474e+01

-1.00000006+00 5.6125100e+04 5.6125103e+04

-1.0000000e+00 -9.4990997e-01 1.6913474e+01

- l .0000000e+00 -9.4990997e-0 1 1 .69 1 3474e+01

-9.9980209e-01 -9.6785226e-01 1.0092753e-I-01

2.5 146937e-02 6.5279478e-03 1 .6499 128e+01

-9.9745402e-01 6.3298820e+04 6.3298823c+04

-1.0000000e+00 -1.0000000e+00 l.8910099e+01

-9.9389041e-01 -9.7173330e-01 1.7168840e+01

-9.9994276e-01 ~9.4796199e-01 1.6890006e+01

-9.9974363e-01 -9.8412991e-01 1.76670126+01

-l.0000000€+00 -9.8473501e-01 1.89092986+01

-9.9994276e-01 -9.4796l99e-01 1.6890006e+01

-1.0000000e+00 -9.4990993e-01 1 .6913474e-l-01

-1.0000000e+00 5.6124511e+04 5.6124514e+04

-1.0000000e+00 -9.86480826-01 1 .8014224e+01

-1.0000000e+00 -9.8189994e-01 1.7455234e+01

N_of_significant_defects= 48

N_of_sim_fail= 6

 

Figure 5.7 (continue)

 

124

 

 

Typel fault: Offset voltage is too large

N_of_typel fault: 10

2 -1.657279e+01 1.3068826-02 8.835241e-O3 1.657279e+01
3 -1.657279e+01 1.3068826-02 8.8352416—03 1.657279e+01
4 -1.657279e+01 1.306882e-02 8.8352416-03 l.657279e+01

11 -1.662153e+01
12 -1.653979e+01
16 -1.661470e+01
24 -1.650082e+01
25 -l.650082e+01
29 -1.6558l7e+01
36 -1.649911e+01

4.678320e-02 -3.278397e-02 1.662162e+01
4.734243e-02 2.829309e-02 l.653988e+01
4.676352e-03 8.787842e-03 1.661471e+01
2.217410e-02 2.747994e-02 1.650086e+01
2.2174106-02 2.7479946-02 l .650086e+01
2.584438e-02 1.722254e-02 1.655820e+01
2.514694e-02 6.5279486-03 1.649913e+01

 

 

Type2 fault: Large Vofs, small DC gain and small ro

N_of_type2 fault: 32

1 -l.885714e+01 -1.0000006+00 -1.000000e+00 1.891010e+01
5 —1.758604e+01 -l.000000e+00 -9.844661e-01 1.764194e-I-01
6 1685022er -9.999679e-01 -9.499072e-01 1.690657e+01

8 -1.758065e+01 -1.0000006+00 -9.843998e-01 l.763656e+01

13
14
15
17
18
19
20
21
22
23
27
28
31
32
33

1683365er -9.999425e-01 -9.479473e-01 1.688994e+01
1.683288e+01 -9.999393e-01 -9.4777386-01 1.688916e-I-01
—6.823206e+00 -9.449744e-01 -9.395253e-01 6.952109e+00
-1.562364e+01 -9.310452e-01 -9.348566e-01 1.567925e+01
1.67208le+01 -9.999969e-01 -9.499099e—01 1.677760e-t-01
-l.795940e+01 -1.000000€+00 -9.864808e-01 l.801425e+01
-1.761123e+01 -9.997436e-01 -9.841299e-01 1.766701e+01
1.684613e+01 -9.999461e-01 -9.499054e-01 1.690250e+01
1.685548e-I-01 -9.999941e-01 -9.499091e-01 1.691181e+01
-1.700952e+01 -9.895408e-01 -9.656997e-01 1.706562e+01
1.685593e+01 -9.999979e-01 -9.563742e-01 1.691263e+01
1.685714e+01 -1.000000e+00 -1.000000e+00 1.691636e+01
1.685714e+01 -1.0000006+00 -9.499099e-01 1.691347e+01
-1.88187le+01 -1.000000e+00 5.612510e+04 5.612510e+04
1.685714e+01 ~1.000000C+OO ~9.499100e-01 l.691347e+01

 

Figure 5.7 (continue)

 

125

 

 

34
35
37
38
39
40
41
42
43
44
45
46
47

1.685714e+01 -1.0000006+00 -9.499IOOe-01 l.691347e-I-01
-9.996366e+00 -9.998021e-01 -9.678523e-01 1.009275e+01
l.685714e+01 -9.9745406-01 6.329882e-I-04 6.329882e+04
-1.885714e+01 -1.000000e+00 -l.000000e+00 1.891010e+01
-1.711248e+01 -9.938904e-01 -9.717333e-01 l.716884e+01
1.683371e+01 -9.999428e-01 -9.479620e-01 1.689001e+01
-1.761123e+01 -9.997436e-01 -9.841299e-01 1.766701e-I-01
-l.885714e+01 -l.0000006+00 -9.847350e-01 1.890930e+01
1.683371e+01 -9.999428e-01 -9.479620e-01 1.689001e+01
1.685714e+01 -1.000000e+00 -9.499099e-01 1.691347e+01
-1.881871e+01 -1.000000e+00 5.612451e+04 5.612451e+04
-1.795937e+01 -1.000000e+00 -9.864808e-01 1.801422e+01
-1.739888e+01 -1.000000e+00 -9.818999e-01 1.745523e+01

 

N_of_fau1t_type= 2

 

Figure 5.7 (continue)

 

126

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5.8 Fault behavior display window.

127

 

ifal ifa2 ifa3.m ifaBCHl ifa_fbe.ext ifaftde.m ifastepl

(a) Program files
f_O.spice f_16.spice f_23.spice f_30.spice f_38.spice f_45.spice f_9.spice
f_1.spice f_17.spice f_24.spice f_31.spice f_39.spice f_46.spice prem.cir
f_10.spice f_18.spice f_25.spice f_32.spice f_4.spice f_47.spice
f_11.spice f_19.spice f_26.spice f_33.spice f_40.spice f_48.spice
f_12.spice f_2.spice f_27.spice f_34.spice f_4l.spice f_5.spice
f_13.spice f_20.spice f_28.spice f_35.spice f_42.spice f_6.spice
f_14.spice f_21.spice f_29.spice f_36.spice f_43.spice f_7.spice
f_15.spice f_22.spice f_3.spice f_37.spice f_44.spice f_8.spice

(b) Input files
Ce11_1ib f_l 5 f_20.ind f_27 f_32.ind f_39 f_44.ind f_7
f_l f_15.ind f_21 f_27.ind f_33 f_39.ind f_45 f_7.ind
f_l .ind f_16 f_21.ind f_28 f_33.ind f_4 f_45.ind f_8
f_10 f_16.ind f_22 f_28.ind f_34 f_4.ind f_46 f_8.ind
f_10.ind f_17 f_22.ind f_29 f_34.ind f_40 f_46.ind f_9
f_ll f_17.ind f_23 f_29.ind f_35 f_40.ind f_47 f_9.ind
f_l 1 .ind f_18 f_23.ind f_3 f_35.ind f_4] f_47.ind paradegl
f_12 f_18.ind f_24 f_3.ind f_36 f_41.ind f_48 paradeg2
f_12.ind f_19 f_24.ind f_30 f_36.ind f_42 f_48.ind paradevl
f_13 f_19.ind f_25 f_30.ind f_37 f_42.ind f_5 paradev2
f_13.ind f_2 f_25.ind f_3] f_37.ind f_43 f_5.ind paraidxl
f_14 f_2.ind f_26 f_31.ind f_38 f_43.ind f_6 paraidx2
f_14.ind f_20 f_26.ind f_32 f_38.ind f_44 f_6.ind

(c) Output files

Figure 5.9 Summary of files used or generated in CLG_routine.

128

the subroutines, ifaI, ifaZ, ifaBCH], ifastepI, and ifa3.m. The detail function of each sub-
routine can be found in [67]. The input files include f_O.spice, f_i.spice, and prem.cir, as

shown in Figure 5.9(b), while the output files are listed in Figure 5.9(c).

5.2 MLG_Routine

The MLG_Routine establishes the macro library described in Figure 4.4. For sim-
plicity of discussion, consider the target macro “current copier” in Figure 4.6 which is
comprised of four primitive cells (PCs): OP, CSW, VSW, and SE. Based on the
CLG_Rouine, the cell library for these four PCs have been built. In MLG_Routine, the
Faulty Performance Evaluator (FPE) derives the parameter deviation bounds, generates
test set, and evaluates the fault coverage of the macro with only one defective PC. Thus,
for the marco “current copier”, The FPE will be respectively used to generate the macro
data for the defective OP, CSW, VSW, and SE. Here, the detail operation of evaluating the
faulty performance of the macro with the defective OP is presented. The same procedure
can be applied for the remaining 3 PCs and the results are attached in Appendix B.

In MLG_Routine, a Spice file, namely “macro.cir”, is used to simulate the good
and faulty circuit behaviors. Figure 5.10 shows the “macroamp.cir” for the macro with the
defective Opamp, where the code “Xamp 4 O 1 14 10 K” will call the sub-circuit K in Fig-
ure 5.3, where K will be substituted, in turns, by f_O.spice, and f_i.spice in the cell library
of Opamp. Similarly, the files macrostr.cir for SE, macrosz.cir for CSW, macroswx.cir
for VSW can be found in Appendix B.

The FPE evaluates the faulty behaviors by executing the program “ifa_fpe.exe”

for “macro.cir” with various Spice files for good and defective Opamps. The simulation

129

 

 

*** Current copier

*

* This program contains the current copier structure
* used to verify the hierarchical IFA fault modeling.
* Treating it as a macro, the current copier includes
* four premitive components, i.e. amplifier, current

* switch, voltage switch and storage element, and they
* are represented by the ‘K’ files in cell libraries

* ‘ampadc’, ‘switchN’, ‘switchx’ and ‘store’, respec-
* tively. All these ‘K’ files are extracted from the

* corresponding premitive component (cell) layouts.

M2 15 12 1 1 pfet w=27u l=3u
M9 3 2 1 lpfet w=23ul=5u
M10 2 2 1 1 pfet w=23u l=5u

C2 12 l 0.5p
Xamp4011410K
Xstore 7 9 14 storeNz

G] 2 14 (17,0) 1
r1 1701meg

X51 3 4 5 switchCz

X52 24 7 8 switchCz
Xs3 10 9 11 switchxz
X34 4 15 16 switchCz
XsS 10 12 13 switchxz

Vdd 1 0 2.5
Vss l4 0 «25

V51 5 0 pwl(O -2.5 1n 2.5 1.999u 2.5 2u -2.5)
V82 8 0 pwl(0 -2.5 1n 2.5)

V33 11 0 pwl(0 -2.5 In 2.5 1.9u 2.5 1.901u -2.5)
V34 16 0 pwl(0 -2.5 1.999u —2.5 Zn 2.5)

V55 13 O pwl(0 -2.5 1.999u ~2.5 Zn 2.5)

Vt4240

 

Figure 5.10 Example of macro.cir.

 

130

 

 

Vi 17 0 input
.ic v(9)=0 v(12)=0 v(4)=O

.Lib K

.Lib lhome/ub/wangche4/ADT/1ib/switchxz
.Lib lhome/ub/wangche4/ADT/1ib/switchCz
.Lib /home/ub/wangche4/ADT/lib/storeNz
.tran 0.05u 4u

.print tran i(Vt)

*N34O SPICE LEVEL 2 PARAMETERS

.Model sv vswitch Ron=4e5 Roff=1e6

+von=2 voff=-2

*parameters: MOSIS 2 micron CMOS process

.model nfet nmos level=2 Ld=.115u TOX=423e-10 NSUB=1.0125225e16
+VTO=.822163 kp=4.893760e-5 gamma=.47 phi=0.6 UO=599.496
+UEXP=5.324966e-3 UCRIT=12714.2 DELTA=3.39718e-5 VMAX=65466.1
+XJ=0.55u lambda=1 .991479e-2 NFS=5.66758e1 l Neff=1.0010e-2
+NSS=0.0 TPG=1.00 rsh=28.070 CGSO=O.9388e-1O CGDO=0.9388e-1O
+cj=1.4563e-4 MJ=O.6 cjsw=6.617e-10 mjsw=0.31

.model pfet pmos 1evel=2 Ld=.18u TOX=423e-10 NSUB=1.421645e15
+VTO=-.776658 kp=1.916950e-5 gamma=.52 phi=0.6 UO=234.831
+UEXP=O.142293 UCRIT=20967 DELTA=1e-6 VMAX=34600.2
+XJ=0.41u lambda=4.921086e-2 NFS=4.744781e1 1 Neff=l.0010e-2
+NSS=0.0 TPG=-1.00 rsh=45.92 CGSO=1.1957e-10 CGDO=1.1957e-10
+cj=2.4e-4 MJ=O.5 cjsw=3.62e-10 mjsw=0.29

.OPTIONs RELTOL=1E-6 pivtol=1e~36 pivrel=1e-36
+CHGtol=le~13 Abstol=1e-13 VNtol=1e-101t15=OItl4=80
+NUMDGT=8 gmin=1e-18 NOECHO NOMOD N OPAGE

.end

 

Figure 5.10 (continue)

 

131

 

Macro Library for macro ‘Current Copier’

 

 

r

Perforrnancel = sig2(40)-sig2(80)
/ lowerfiound = -le-6

K upper bound = le-6 f G

r A = 1
\Layout_area(um 2) 41280 @

 

 

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

Test Generation for TYPE 1 FAULT of Cell:
/home/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/ampadc

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

 

 

 

 

Macro input Defect
r2.SOOOOOe—05 36\
2.500000e-05 24
2.500000e-05 12 a
7.500000e-05 29
\2500000605 1 1)

 

 

 

(Number of total significant defects: 1
QIumber of faulty significant defects: 6/ o

 

.....................................................................................................................

Test Generation for TYPE 2 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/ampadc

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

 

 

 

Figure 5.11 Example of macro library.

132

 

 

Macro input DeEct

2.500000e-05 15
0.000000e+00 35
2.500000e-05 35
5.000000e-05 35
7.500000e-05 35
1.000000e-04 35
2.500000e-05 l7
2.500000e-05 18
5.000000e-05 18
7.5000006-05 18
1.000000e-04 18
2.500000e-05 23
2.500000e-05 39
2.500000e-05 47
5.000000e-05 47
7.500000e-05 47
1.000000e-04 47
2.500000e-05 8

5.000000e-05 8

7.500000e-05 8

1.000000e-04 8

2.500000e-05 5

5.000000e-05 5

7.500000e-05 5

1.000000e-04 5

2.500000e-05 20
5.000000e-05 20
7.500000e-05 20
1.000000e-04 20
2.500000e-05 46
5.000000e—05 46
7.500000e-05 46
1.000000e-04 46
2.5000006-05 42
5.000000e-05 42
7.500000e-05 42
1.0000006-04 42
2.500000e-05 l

5.000000e-05 l

 

Figure 5.11 (continue)

 

133

 

 

7.500000e-05 l

1 .000000e-04 1

2.500000e-05 45
5.000000e-05 45
7.500000e-05 45
l .000000e-04 45
2.500000e-05 32
5.0000006-05 32
7.5000006-05 32
1 .000000e-04 32
0.000000e+00 37

 

Number of total significant defects: 32
Number of faulty significant defects: 19

 

Figure 5.11 (continue)

 

134

results are listed in Figure 5.1 1. Results first show that the layout area of the current copier

is 41280 umz, and the performance specification is that the stored current is ranged
between -1e-6A and 1e-6A. For Type 1 fault, i.e., Offset voltage is too large, the input cur-
rent 2.5e-5A excites faulty performance when the 11th, 12th, 24th, or 36th significant
defect occurs, while the input current 7.5e-5A excites the 29th significant defects. Thus,
both 2.5e-5A and 7.5e-5A are used as the test signals to defect Type 1 faults. Results also
show that 10 significant defects are classified as the Type I faults, which is exactly the
same as the result shown in Figure 5.7. Computation results conclude that 6 out the 10 sig-
nificant defects lead to faulty performance. The number of total significant defects is not
necessary to be equal to that shown in the list of input-defect combination because the test
generator embedded in FPE automatically eliminates the simulation of some significant
defects which has same fault behavior space degree as that of previously simulated defect
in order to speed up the test generation[67]. These eliminated significant defects will not
be shown in the list of input-defect combination, however will be count for the number of
total significant defects. Similarly, 32 significant defects are classified as Type 2 faults.
both 0A and 2.5e-5A can excite 16 defects listed in Figure 5.11, and they are chosen as the
test set. Combining the test sets for both Type 1 fault and Type 2 fault, the test set of the
Opamp cell employed by the macro “current copier” is {OA,2.5e-5A,7.5e-5A). Because
that the test input 0A detects only 35th and 37th significant defects, between them, the
35th significant defect can also be covered by 2.5e-6A. Thus the input 0A can be elimi-
nated from the test set for simplifying the testing process while still maintaining high fault
coverage. That is to say, by using test set {OA,2.5e—6A,7.5e-6A}, all the 25 significant

defects can be detected; however, 24 out of the 25 significant defects can still be detected

135

if we only use the test set {2.5e-6A,7.5e-6A}. Thus, the final test set could be {2.5e-
5A,7.5e-5A}.

As shown in Appendix B, the three other PCs, CSW, VSW, and SE, can be tested
by 1.0e-4A. Thus, the compacted test set for the current copier is (2.5e-5A,7.5e-5A,1.0e-
4A). Based on the test set, the fault coverage is almost 100% if the tester has a 100% accu-
racy, as discussed in Table 3.1.

Similar to Table 3.2., consider an inaccurate tester is used and the fault coverage is
degraded. The inaccuracy of the tester can be viewed as a deviation on the performance
specifications used in establishing the macro library. For example, let the inaccuracy of the
tester is 25%. Thus, the performance specification bounds are changed from 1e-6A to

1.25e-6A to represent the 25% inaccuracy of the tester. The same procedures are applied
to generate the macro current copier and simulation results are shown in Appendix C.

The fault coverage of a macro can be computed as defined in (4.2), where the ratio

of the significant defects overall injected defects is defined as

Psi = [st + 2 Nfsd] / de (5.1)
where st is the number of failure simulations, i.e., the term N_of_sim_fail in Figure 5.7
for Opamp cell, Nfsd is the number of faulty significant defects (Figure 5.11), and de is
N_of_injected_defects (Figure 5.7). For example, for the Opamp, st=6, Nfsd=6 for Type
1 fault and 19 for Type 2 fault, and de=700. Thus, the ratio Psi=Popamp=[6+(6+l9)]/

700:0.044286.
The fault coverage of the i-th primitive cell is defined as
FC; = [st + Z Nfsd]i / [st + 2 Nfsd] (5.2)

where [st + 2‘. Nfsdh is the total significant defects with the inaccurate tester. For example,

136

As shown in C1 (Appendix C), [st + 2 Nfsd]i=6+(4+18)=28. Thus, by (5.2),
FCOpamp = (6+22) / (6+25) = 0.903226.
Similarly, for current switch (CSW), voltage switch (VSW), and Storage element (SE)

PCSW = [l7+(4+0+3)]/350=0.068571; FCCSW=[17+7]/[ 17+7]=1 .0

PVSW = [14+(2+1+6+3)]/350=0.074286; FCvsw=114+12]/114+12]=1 .0
PSE = [1+23]/350=0.068571; FCSE=[1+23]/[1+23]=l .0
Note that the areas for the four PCs and the macro are
Aopamp=21837; Acsw=l638; Avsw=1666 ASE=1100, and Acopier=41280'
By (4.2),
AOpampPOpampFCOpamp=21 837x0.044286x0.903226=873 .4858
ACSWPCSWFCCSW =1638x0.068571x1.0=1 12.3193
AvswpvstCvsw= 1 666x0.074286x 1= 1 23 .7605
ASEPSEFCSE=1 100*0.06857 l * 1 =75 .428 1
and the sum of the above terms, FCX, is l.l85e+3. Similarly,
Aopminopmp=96707 36; ACSWPCSW=1 12.3 193;
Avswpvsw= 1 23.7 605; ASEPSE=75.4281.
The sum of the above terms, PC), is 1.2786e+3. Thus, with 25% inaccuracy of the tester,

the fault coverage

PC = FCx / FCy = 1.185e+3 / 1.2786e+3 = 0.9268.

 

Chapter 6

CONCLUSION

Mixed-signal ICs gradually becomes the main-stream solutions for the applications
such as portable data systems, wireless communication, and multimedia. Manufacturers
have made every effort to enhance the function and performance an mixed-signal IC can
achieve; but the complexity of the IC is also increased at the same time. Due to the
increasing complexity, manufacturers confront the problem of long testing cycle by using
the conventional external functional test performed on ATE machine. This not only reduces
the testing confidence, but also increases the cost directly. Existing design-for-testability
techniques cannot resolve the testing complexity problem because most of the techniques
need exhaustive test set. Therefore, it is necessary to develop a testability design
methodology that maps the specification-driven testing process to a simpler fault-model-
based process. This thesis presents the methodologies that target the issues on testability

design rule, hierarchical fault macromodeling procedure, and test generation process.

6.1 Summary

Two major tasks in the fault-model-based testing process, fault definition and test

generation, have been reviewed. Inductive Fault Analysis (IFA), a practical fault definition

137

138

technique used as the basis of proposed fault modeling methodology, was introduced. The
structures and operations of switched-current circuits were discussed in order to show the
test generation of algorithmic switched-current ADC based on the single stuck-at-fault
model which is widely used in digital circuit testing. Several commonly used testing

schemes for enhancing the testability of analog/mixed-signal ICs were also reviewed.

The single stuck-at-fault model only represents part of the fault types which may
occur in analog/mixed-signal circuits. The proposed testability design methodology uses
the IFA technique to develop a practical fault model to represent both stuck-at faults and
parametric faults. The IFA-based fault modeling process firstly derives a graded list of the
most likely fault types from a description of circuit layout, process parameters, and defect
statistics of the fabrication process. The fault model is then established using these fault
types. Given the performance specifications and a discrete input set which used for design
verification, the parameter bound is derived for each fault type and is then used for test
generation and fault coverage calculation. To make the test generation process simple and
successful, a circuit should be designed with the testability design rules to ensure the

existence of parameter bounds.

This thesis also presents the testability enhancement methodologies to further
decrease the testing cycle time and increase the testability of analog/mixed-signal ICs. The
hierarchical IFA-based fault macromodeling process is developed to reduce the
computational complexity of IFA-based fault modeling. In this hierarchical testing scheme,
a design is decomposed into primitive cells and/or macros, and their IFA testing data such
as fault behavior values, number of injected defects, test set, and fault coverage are stored

in cell/macro library. A software tool has been developed to establish the testing

139

environment.

High-accuracy built-in tester not only help increase the observability of a design,
but also simplify the test sequence. Thus, it decreases the testing cycle time. The study
shows that there exists a trade-off between the accuracy of the built-in tester and the test
sequence. The test sequence length can be reduced significantly if a high-accuracy tester is

used.

6.2 Future Work

It is believed that the complexity of analog/mixed-signal ICs will continuously
increase. Thus, further enhancing testability is necessary and the developed testability

design methodologies can be improved in many different ways.

The success of a developed fault macromodeling process is determined by the fault
coverage that the generated test set can achieve. The developed fault macro macromodeling
process can precisely evaluate the fault coverage of a primitive cell. The evaluated fault
coverage for each cell can be carried out for a macro. However, a macro not only contains
a number of primitive cells, but also includes the interconnect among these cells. The
routing area is still susceptible to defects. In Section 4.1.2, the evaluation of fault coverage
including the routing area has been developed. However, it was assumed that the defects in
the routing area which causes hard faults are testable. This means that the evaluation
obtains the worst case fault coverage. To obtain more accurate evaluation, the testability of
the defects that cause parametric faults must be further investigated. Since the routing area
and interconnects depend on the applications and design style, the way of precisely

evaluating the fault coverage in the routing area is a challenging research task.

140

A designed analog circuit can be easily testable if the circuit is designed based on
the testability design rules developed in Section 4.2. In addition, the testability can also be
enhanced by using the built-in tester developed in Section 4.3. It is believed that some hard-
to-test faults can be eliminated if the circuit layout is changed. In the IFA-based fault
macromodeling process. the generated test set is determined in part by the circuit layout.
Different layout style may generate different test sets. Thus, developing a set of testability
rules in the layout level can easily eliminate some hard-to-test faults and indirectly simplify

the test generation process.

Finally, as discussed in Section 4.3, the testability can be enhanced by accessing the
internal test points using the built-in tester. There exists a trade-off between the tester’s
circuit complexity and test sequence length. Note that a hi gh-accuracy tester may be needed
to measure the test signals on an insensitive test point. Thus, a higher complexity tester is
required for maintaining the testing speed. This implies that selecting the measurements on
highly sensitive test points can reduce the tester cost, and how to select them becomes an

important research topic for future study.

 

APPENDICES

APPENDIX A

141

APPENDIX A

A.1 Cell Library of Current Switch

 

Cell Library for Primitive Component ‘switchN’

 

Layout__area(um"2)= 1638
N_of_injected_defects= 350

Detected Output Variables of Premitive Simulation #1

tran --------- > sigl
i(vx) --------- > sig2
Detected Output Variables of Premitive Simulation #2
tran --------- > sig3
v( 1) --------- > sig4

Parameter]: O.7/sig2(18)
Norminal value of parameter1= 2.8622e+3

Parameter2= 2.5/sig2(38)
Norminal value of parameter2= 8.4198e+12

List of fault behavior values(normalized deviation):
(lst column: index of defects; last column: norm)

1 -l.4057295e-06 -1.0000000e+00 l.0000000e+00
2 2.8196669e+14 3.1038731e—01 2.8196669e+14
3 2.2785931e-01 -1.8788078e-01 2.95328726-01

4 l.6586275e+13 3.4527163e-01 1.6586275e+l3

5 l.8797779e+l3 1.9368736e-01 1.8797779e+13

 

 

 

 

142

 

 

8 4.7876678e-01 -2.2565036e-01 5.2927849e-01
16 2.6104129e-01 -2.0270987e-01 3.3050544e-01
l7 3.8246059e+00 -1.6004544e+01 1.6455182er
19 -1.4057295e-06 —1.7262414e-01 1.72624146-01
21 — 1 .4057295e-06 -1.00000006+00 1.0000000e+00

27 2.6104129e-01 -2.0270987e-01 3.3050544e-01

N_of_significant_defects= 28

N_of_sim_fail= l7

 

Typel fault: On resistance is too large
N_of__type1 fault: 4

5 1.879778e+13 1.936874e-01 1.879778e+13
8 4.787668e-01 -2.256504e-01 5.292785e-01
16 2.610413e-01 -2.027099e-01 3.305054e-01
27 2.610413e-01 -2.027099e—01 3.305054e-01

 

Type2 fault: Off resistance is too small
N_of_type2 fault: 2

1 -1.405730e—06 -l.000000e+00 l.000000e+00
21 -l.405730e-06 -1.000000e+00 1.000000e+00

 

Type3 fault: Ron is too large and Roff is too small

 

 

 

143

 

N_of_type3 fault: 5

2 2.819667e+14 3.1038736-01 2.819667e+14
3 2.278593e-01 -l.878808e-01 2.953287e—01
4 1.658628e+13 3.452716e-01 1.6586286'l'l3
17 3.824606e+00 -1.600454e+01 1.645518e+01
19 -1.405730e-06 -1.726241e-01 1.726241e-01

 

N_of_fault_type= 3

 

 

144

A.2 Cell Library of Voltage Switch

 

Cell Library for Primitive Component ‘switchx’

 

Layout_area(um"2)= 1666
N_of_injected_defects= 350

Detected Output Variables of Premitive Simulation #1

tran --------- > sigl
i(vx) --------- > sig2
Detected Output Variables of Premitive Simulation #2
tran --------- > sig3
v(l) --------- > sig4

Parameter]: O.7/sig2(18)
Norminal value of parameter]: 3.4345e+3

Parameter2= 2.5/sig2(38)
Norminal value of parameter2= 6.5526e+12

Parameter3= sig4(38)
Norminal value of parameter3= 1.5396328e-2

List of fault behavior values(normalized deviation):
(lst column: index of defects; last column: norm)

1 6.0736083e-06 -2.3245778e-06 0.0000000e+00 6.5032592e-06
2 1.4546818e-02 -6.1743795e-02 -7.505296le-03 6.3876722e-02
3 6.07360836-06 -2.3245778e-06 0.0000000e+00 6.5032592e-O6

4 6.07360836-06 ~2.3245778e-06 0.0000000e+00 6.50325926-06

 

 

 

145

 

 

11

13

15

17

20

24

27

28

29

30

31

33

34

35

36

6.0736083e-06 -2.3245778e-06 0.0000000e+00 6.5032592e-06
6.07360836-06 -2.3245778e-06 0.0000000e+00 6.50325926-06
6.0736083e-06 -2.3245778e-06 000000006400 6.5032592e-06
4.8205323e-02 3.7287928e-02 3.49087l3e-02 7.02336176-02
5.1776463e-01 -5.4653168e—02 -8.5467780e+00 8.5626212e+00
7.10998156+01 -1.0000000e+00 -1.00000006+00 7.1113879e+01
5.5948052e+12 1.7493363e+01 2.1710909e+00 5.5948052e+12
6.1226732e-06 -l.4964461e-01 ~3.1183l30e-01 3.4587898e-01
2.1449866e-01 1.1071757e+00 -l.3940769e+00 1.7931252e+00
3.0505743e-01 2.3733617e-01 -8.149l956e+00 8.1583563e+00
l.7389233e-01 -2.9947582e-01 5.1564574e-1-00 5.1680729e+00
6.0736083e-06 -9.6127504e-02 1.9391124e-01 2.1643028e-01
-l.2626046e-03 -1.6883154e-01 2.1266332e+00 2.1333247e+00
1.2147192e-02 5.02886296-01 -6.2277837e-03 5.03071526-01
6.0736083e-06 -5.5974618e-02 3.9199542e-01 3.9597167e-01
-l.8481847e+00 -l.0000000e+00 l.6l37638e+02 1.6139006e+02
-1.8481847e+00 -1.00000006+00 l.6l37638e+02 1.6139006e+02
~l.8481847e+00 -l.0000000e+00 l.6l37638e+02 1.6139006e+02

—l.8481847e+00 -1.0000000e+00 l.6l37638e+02 1.6139006e+02

N_of_significant_defects= 37

N_of_sim_fail= l4

 

 

146

 

 

 

Typel fault: On resistance is too large
N_of_typel fault: 2

11 5.177646e-01 -5.4653l7e-02 -8.546778e+00 8.562621e+00
24 3.050574e-01 2.373362e-01 -8.l49196e+00 8.158356e+00

 

Type2 fault: Off resistance is too small
N_of_type2 fault: I

27 1.738923e-01 -2.994758e-01 5.156457e+00 5.168073e+00

 

Type3 fault: Charge injection is too large
N_of_type3 fault: 6

15 5.594805e+12 l.749336e+01 2.171091e+00 5.594805e+12

29 -1.2626056-03 -l.688315e-01 2.126633e+00 2.133325e+00
33 ~1.848185e+00 -1.000000e+00 1.613764e+02 l.6l3901e+02
34 -1.848185e+00 -l.000000e+00 1.613764e+02 1.613901e+02
35 -1.848185e+00 -1.000000e+00 1.613764e+02 l.6l3901e+02
36 -l.848185e+00 -1.000000e+00 1.613764e+02 1.6139OIe+02

 

Type4 fault: Ron is too large & Roff is too small
N_of_type4 fault: 14

6.073608e-O6 -2.324578e-06 0.000000e+00 6.503259e-06
1.454682e-02 -6.174379e-02 -7.505296e-03 6.387672e-02
6.073608e-06 -2.324578e-06 0.000000e+00 6.5032596-06
6.073608e-06 —2.324578e-06 0.000000e+00 6.5032596-06
6.0736086-06 -2.324578e-06 0.000000e+00 6.503259e-06
6.073608e-06 -2.324578e-06 0.000000e+00 6.5032596-06
6.073608e-06 -2.324578e-06 0.000000e+00 6.503259e-O6
4.820532e-02 3.728793e-O2 3.49087le-02 7.023362e-02

OOQQUIAUJN-fl

 

 

147

 

 

13 7.109982e+01 -1.000000e+00 -1.0000006+00 7.111388e+01
17 6.122673e-06 -1.496446e-01 -3.l 18313e-01 3.4587906-01
20 2.144987e-01 1.107176e+00 -1.394077e+00 1.793125e-I-00
28 6.073608e-06 -9.612750e-02 1.939112e-01 2.164303e-01
30 1.214719e—02 5.028863e-01 -6.227784e-03 5.0307156-01
31 6.073608e-06 -5.597462e-02 3.919954e-01 3.959717e-01

 

N_of_fault_type= 4

 

 

148

A.3 Cell Library of Storage Element

 

Cell Library for Primitive Component ‘store’

 

l

2

 

-1.0000000e+00

-1.0000000e+00

-l.0000000e+00

-1.0000000e+00

-1.0000000e+00

-l.0000000e+00

-1.0000000€+00

-1.0000000€+OO

Layout_area(um"2)= 1100
N_of_injected_defects= 350
Detected Output Variables of Premitive Simulation #1

tran --------- > si g1
i(vdd) --------- > sig2

Parameter1= -1*sig2(40)
Norminal value of parameterl= 9.44844e-5

List of fault behavior values(normalized deviation):
(lst column: index of defects; last column: norm)

1 .0000000e+00

l .0000000e+00

1.0000000e+00

l.0000000e+00

1.0000000e+00

l.0000000e+00

l .0000000e+00

l .00000006+00

 

 

149

 

 

9

10

ll

12

13

14

15

16

17

18

19

20

21

22

24

1.5369818e-01 1.5369818e-01

-1.0000000e+00

-1.0000000e+00

-1.0000000e+00

-1.0000000e+00

-1.0000000e+00

-l.0000000e+00

-1.0000000e+00

-1.0000000e+00

-l.0000000e+00

-1.0000000e+00

-l.0000000e+00

-l.0000000e+00

1.1083183e+00

-l .9927927e-01

1 .0000000e+00

1.0000000e+00

1.0000000e+00

1.0000000e+00

1.0000000e+00

1.00000006+00

1.0000000e+00

1.0000000e+00

l.0000000e+00

l .0000000e+00

1 .00000006+00

l.0000000e+00

1.1083183e+00

l .9927927e-01

N_of_significant_defects= 24

N_of_sim_fail= l

 

Typel fault: Deviation of memorized current is too large

N_of_typel fault: 23

 

 

150

 

 

-1.000000e+00 1.000000e+00
—l.000000e+00 1.0000006+00
-l.000000e+00 1.000000e+00
-l.000000e+00 1.000000e+00
-1.000000e+00 1.000000e+00
-1.000000e+00 1.000000e-I-00
7 -1.000000e+00 1.0000006+00
8 -1.000000e+00 1.000000e-I-00
9 1.536982e-01 1.536982e-01

10 -1.000000e+00 1.000000e+00
ll -1.000000e+00 1.000000e+00
12 -1.000000e+00 1.000000e+00
l3 -1.000000e+00 1.000000e+00
l4 -1.000000e+00 1.000000e+00
15 -1.000000e+00 1.000000e+00
16 -1.000000e+00 1.000000e+00
l7 -1.000000e+00 1.000000e+00
18 -1.000000e+00 l.000000e+00
l9 -l.000000e+00 1.000000e+00
20 -l.000000e+00 1.000000e+00
21 -1.000000e+00 l.0000006+00
22 1.108318e+00 1.108318e+00
24 -l .992793e-01 1 .992793e-01

GUI-#0010—

 

N _of_fault_type= 1

 

 

 

pm

 

APPENDIX B

151

APPENDIX B

B.l Macro Library of Current Copier With Target Cell, Current Switch,
and Specifications of (+/-)le-6

 

Macro Library for macro ‘Current Copier’

 

Layout_area(um"2)= 4 1280

Performance] = sig2(40)-sig2(80)
lower bound = -le-6
upper bound = le-6

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

Test Generation for TYPE 1 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_1ib/switchN

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect

l .000000e-04 l6
0.000000e+00 8
2.500000e-05 8
5.000000e—05 8
7.500000e-05 8
l .0000006-04 8
0.000000e+00 5
2.500000e-05 5
5.000000e-05 5
7.500000e-05 5
l .000000e-04 5

 

Number of total significant defects: 4
Number of faulty significant defects: 4

 

 

 

152

 

 

OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

Test Generation for TYPE 2 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cel1_lib/switchN

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect

 

Number of total significant defects: 2
Number of faulty significant defects: 0

ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

Test Generation for TYPE 3 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/switchN

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect
0.000000e-1-00 l7
2.500000e-05 l7
5.000000e-05 17
7.500000e-05 17
1 .OOOOOOe-O4 l7
0.000000e+00 4
2.500000e-05 4
5.000000e-OS 4
7.500000e-05 4
l .000000e-04 4

 

Number of total significant defects: 5
Number of faulty significant defects: 3

 

 

153

B.2 Macro Library of Current Copier With Target Cell, Voltage Switch, and
Specifications of (+l-)le-6

 

Macro Library for macro ‘Current Copier’

 

Layout_area(um"2)= 41280
Performance] = sig2(40)-sig2(80)

lower bound = -1e-6
upper bound = 1e-6

Test Generation for TYPE 1 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell__lib/switchx

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect
2.500000e-OS 24
5.000000e-05 24
l .OOOOOOe-O4 24
0.000000e+00 1 l
2.500000e-05 1 1
5.000000e-05 l 1
7.500000e-05 l 1
1.000000e-04 l 1

 

Number of total significant defects: 2
Number of faulty significant defects: 2

#############

 

 

 

 

 

154

 

 

Test Generation for TYPE 2 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/switchx

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect

1 .000000e-04 27

 

Number of total significant defects: 1
Number of faulty significant defects: 1

ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

Test Generation for TYPE 3 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/switchx

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect
l .000000e-04 29
0.000000e+00 33
7.500000e-05 33
1 .000000e-04 33
0.000000e+00 15
2.500000e-05 15
5.000000e-05 15
7.500000e-05 15
l .000000e-04 15

 

Number of total significant defects: 6
Number of faulty significant defects: 6

...............................................................................................................

 

 

155

 

 

Test Generation for TYPE 4 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/switchx

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect
l .OOOOOOe-O4 8

l .OOOOOOe-04 20
5.000000e-05 13
7.500000e-05 1 3

1 .OOOOOOe-04 1 3

 

Number of total significant defects: 14
Number of faulty significant defects: 3

 

 

156

B3 Macro Library of Current C0pier With Target Cell, Storage Element,
and Specifications of (+/-)le-6

 

Macro Library for macro ‘Current Copier’

 

Layout_area(um"2)= 41280
Performance] = sig2(40)-sig2(80)

lower bound = -1e-6
upper bound = 1e-6

ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

Test Generation for TYPE 1 FAULT of Cell:
Ihome/ub/wan gche4/ADT/adc_wey/IFA/fotmodellcel1_lib/store

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect
2.500000e-05 9
2.500000e-05 24

 

Number of total significant defects: 23
Number of faulty significant defects: 23

 

 

 

APPENDIX C

 

157

APPENDIX C

C.1 Macro Library of Current Copier With Target Cell, Opamp, and Speci-
fications of (+/-)1.25e-6

 

Macro Library for macro ‘Current Copier’

 

Layout_area(um"2)= 4 l 280
Perforrnancel = sig2(40)—sig2(80)

lower bound = -1.25e-6
upper bound = 1.25e-6

Test Generation for TYPE 1 FAULT of Cell:
/home/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/ampadc

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect
2.500000e-05 24
2.500000e-05 l 2
7.500000e-05 29

 

Number of total significant defects: 10
Number of faulty significant defects: 4

ooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo

Test Generation for TYPE 2 FAULT of Cell:
/home/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/ampadc

 

 

 

158

 

 

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect
2.500000e-05 15
0.000000e-I-OO 35
2.500000e-05 35
5.000000e-05 35
7.500000e-05 35
1.000000e-04 35
2.500000e-05 17
2.500000e-05 18
5.000000e-05 18
7.500000e-05 18
1.000000e-04 18
2.500000e-05 23
2.500000e-05 47
5.000000e-05 47
7.500000e-05 47
1.000000e-O4 47
2.500000e-05 8
5.000000e-05 8
7.500000e-05 8
1.000000e-04 8
2.500000e-05 5
5.000000e-05 5
7.500000e-05 5
1.000000e-O4 5
2.500000e-05 20
5.000000e-05 20
7.500000e-05 2O
1.000000e-04 20
2.500000e-05 46
5.000000e-05 46
7.500000e-05 46
1.000000e-04 46
2.500000e-05 42
5.000000e-05 42
7.500000e-05 42
1.000000e-O4 42
2.500000e-05 1

5.000000e-05 l

 

 

159

 

 

7.500000e-05 1

1 .000000e-04 l

2.500000e-05 45
5.000000e-05 45
7.500000e-05 45
1 .000000e-04 45
2.500000e-05 32
5.000000e-05 32
7.500000e-05 32
1 .000000e-04 32
0.000000e+00 37

 

Number of total significant defects: 32
Number of faulty significant defects: 18

 

 

160

C.2 Macro Library of Current Copier With Target Cell, Current Switch,
and Specifications of (+/-)1.25e-6

 

Macro Library for macro ‘Current Copier’

 

Layout_area(um"2)= 4 1 280

Performance] = sig2(40)-sig2(80)
lower bound = -1.25e-6
upper bound = 1.25e-6

.....................................................................................................................

Test Generation for TYPE 1 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/switchN

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect

1.000000e-04 16
0.000000e+00 8
2.500000e-05 8
5.000000e-05 8
7.500000e-05 8
l .000000e-04 8
0.000000e+00 5
2.500000e-05 5
5.000000e-05 5
7.500000e-05 5
l .000000e-04 5

 

Number of total significant defects: 4
Number of faulty significant defects: 4

 

 

 

161

 

 

.....................................................................................................................

Test Generation for TYPE 2 FAULT of Cell:
[home/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/switchN

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect

 

Number of total significant defects: 2
Number of faulty significant defects: 0

.....................................................................................................................

Test Generation for TYPE 3 FAULT of Cell:
Ihome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/switchN

The following combinations of defect (in target premitive)
and macro input lead to out-of—spec macro performance:

Macro input Defect
0.000000e+00 17
2.500000e-05 17
5.000000e-05 17
7 .SOOOOOe-OS l7
1 .OOOOOOe-O4 17
0.000000e+00 4
2.500000e-05 4
5.000000e-05 4
7.500000e-05 4

1 .000000e-O4 4

 

Number of total significant defects: 5
Number of faulty significant defects: 3

 

 

162

C.3 Macro Library of Current Copier With Target Cell, Voltage Switch, and
Specifications of (+l-)l.25e-6

 

Macro Library for macro ‘Current Copier’

 

Layout_area(um"2)= 41280
Perforrnancel = sig2(40)-sig2(80)

lower bound = -1.25e-6
upper bound = 1.25e-6

Test Generation for TYPE 1 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/switchx

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect
2.500000e-05 24
5.000000e-05 24
1 .OOOOOOe-O4 24
0.000000e+00 1 1
2.500000e-05 1 1
5.000000e-05 ] l
7.500000e-05 1 l
1.000000e—04 l l

 

Number of total significant defects: 2
Number of faulty significant defects: 2

WW

 

Test Generation for TYPE 2 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_1ib/switchx

 

 

 

163

 

 

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect

l .000000e-04 27

 

Number of total significant defects: 1
Number of faulty significant defects: 1

Test Generation for TYPE 3 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/switchx

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect
l .OOOOOOe-O4 29
0.000000e+00 33
l .OOOOOOe-04 33
0.000000e+00 15
2.500000e-05 15
5.000000e-05 1 5
7.500000e-05 l 5
1 .OOOOOOe-04 15

 

Number of total significant defects: 6
Number of faulty significant defects: 6

...................................................................................................................

Test Generation for TYPE 4 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cell_lib/switchx

The following combinations of defect (in target premitive)

 

 

164

 

 

and macro input lead to out-of-spec macro performance:

Macro input Defect
1 .OOOOOOe-04 8

1 .OOOOOOe-O4 20
5.000000e-05 13
7 .SOOOOOe-OS 13
1.000000e-04 13

 

Number of total significant defects: 14
Number of faulty significant defects: 3

 

 

165

CA Macro Library of Current Copier With Target Cell, Storage Element,
and Specifications of (+l-)l.25e-6

 

Macro Library for macro ‘Current Copier’

 

Layout_area(um"2)= 41280
Performance] = sig2(40)-sig2(80)

lower bound = -1.25e-6
upper bound = 1.25e-6

Test Generation for TYPE 1 FAULT of Cell:
lhome/ub/wangche4/ADT/adc_wey/IFA/fotmodel/cel1_lib/store

The following combinations of defect (in target premitive)
and macro input lead to out-of-spec macro performance:

Macro input Defect
2.500000e-05 9
2.500000e-05 24

 

Number of total significant defects: 23
Number of faulty significant defects: 23

 

 

 

10.

ll.

12.

13.

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31293017865977