I" LIBRARY ’Mlchigan State 3 University PLACE IN RETURN BOX to remove this checkout from your record. TO AVOID FINES return on or before date due. DATE DUE DATE DUE DATE DUE TW [Egg 1 6 gpg m 01 1 6 0 3 ll— _ MSU Is An Affirmative Action/Equal Opportunity Institution cAcRMms-nt SY SYMBOLIC ANALOG CIRCUIT ANALYSIS By Sin-Min Chang A DISSERTATION Submitted to Michigan State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Department of Electrical Engineering 1992 COm‘i sensi CirCL fiiiez ABSTRACT SYMBOLIC ANALOG CIRCUIT ANALYSIS By Sin-Min Chang Studies have shown that the efficiency of symbolic circuit analysis can be im- proved by a composition and decomposition strategy. However, most of the existing strategies are not suitbale for analyzing commercial ICs. This limits the application of symbolic approach for circuit analysis. In this dissertation, a new circuit level decomposition strategy is presented. Taking advantage of the characteristics of the nullors, computing efforts can be further reduced by exploring valid and invalid de- composed sub-circuits. Together with a new numerical approximation, the symbolic sensitivity analysis, and the symbolic Hurwitz test capabilities, Sspice, a symbolic circuit analyzer, is capable of analyzing circuits like commercial op-amps and active filters. Examples are given. Copyright by Sin-Min Chang 1992 This research was supported in part by REF of State of Michigan iii go go wwwbr-y TABLE OF CONTENTS LIST OF TABLES vi LIST OF FIGURES vii 1 MOTIVATION l 1.1 Analog Circuit Design Process ...................... 1.2 Analog Circuit Analysis ......................... 3 SYMBOLIC CIRCUIT ANALYSIS 11 2.1 Introduction ................................ 11 2.2 Circuits with Nullors ........................... 13 2.2.1 Nullator-Norator Nodal Analysis ................ 13 2.2.2 Equivalence relations ....................... 19 2.2.3 Special Case for Network Determinants ............. 19 2.3 Graph Theory Approach ......................... 23 2.3.1 Coates Graph and Tree-Enumeration Method ......... 24 2.3.2 Signal-F low Graph and Mason’s Rule .............. 26 2.4 The Existing Symbolic Circuit Analyzers ................ 30 DECOMPOSITION STRATEGIES FOR SYMBOLIC CIRCUIT ANALYSIS 33 3.1 A Review of Decomposition Methods .................. 33 3.2 Obtaining Network Determinants by Decomposition .......... 35 3.3 The Algorithm .............................. 39 3.3.1 Analysis .............................. 46 ' 3.4 Exploiting Special Decomposition Opportunities ............ 49 3.5 A Circuit Level Decomposition Application ............... 55 NUMERICAL APPROXIMATION STRATEGIES FOR SYM- BOLIC CIRCUIT ANALYSIS 66 4.1 Numerical Approximation After Computation .............. 67 iv A '00 iqa H ’3 “I ‘l " .I] ~11 . b”) .C}! (I) 3 CON( BIBL10< 4.1.1 Numerical Approximation in ISAAC .............. 4.1.2 Numerical Approximation in SCOPE .............. 4.1.3 Numerical Approximation in Sspice ............... 4.2 Numerical Approximation During Computation ............ 4.3 Numerical Substitution Before Computation .............. 5 SYMBOLIC SENSITIVITY ANALYSIS 5.1 The Implementation of Symbolic Sensitivity Analysis ......... 5.2 Applications of Sensitivity Analysis ................... 6 SYMBOLIC STABILITY ANALYSIS 6.1 Hurwitz Test Fundamentals ....................... 6.2 Implementation of Hurwitz Test ..................... 7 INIPLEMENTATION OF SSPICE VERSION 2.0 7.1 Matrix Reduction Method ........................ 7.2 Obtaining Matrix Determinant ..................... 7.3 Implementation of Sspice ......................... 7.4 Second Order Filter Function Identification ............... 7.5 In-Band Error Approximation ...................... 7.6 Special Functions . . . . . ........... I ............. 8 CONCLUSIONS BIBLIOGRAPHY 70 71 7‘2 72 75 77 77 79 93 93 96 101 101 104 107 113 115 118 122 125 1.1 3.1 3.2 4.1 LIST OF TABLES Characteristics of Analog and Digital Circuit Designs .......... 2 Symbolic Network Determinants of Example 4 .............. 54 o and u indexes ............................... 57 With and Without Approximation for P1 and P2 ............ 75 vi 1.1 1.2 1.3 1.4 1.5 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 LIST OF FIGURES Flow chart for circuit design process. .................. Series RLC circuit. ............................ Bandstop filter function at V2 of series RLC circuit ........... (a) CMOS op-amp. (b) Open Loop gain circuit. ............ Transfer function of the CMOS op-amp. ................ (a)Nullator; (b)Norator. ......................... Nullator—norator equivalent circuit of a VCVS ............. A circuit with nullator and norator .................... Numerator of V4 in Example 1. ..................... The equivalent network determinant of Y”. .............. Parallel and Open/ Short equivalence ................... (a)Nullator trees; (b)Norator trees. ................... A network has two parts connecting at a single node. ......... A corresponding Coates graph. ..................... A typical Mason graph .......................... Example 2 ................................. The decomposition and composition of two sub-circuits connected at three nodes; (a) The whole circuit; (b)-(g) six cases ........... Example with Na and Nb ........................ Maximum beneficial cut nodes analysis .................. Example 3. ................................ Example 4. ................................ An Example Circuit with two parts .................... The Equivalent Circuit .......................... Cases expanded with respect to G1. (a) NDla, Network Determinant without G1. (b) ND1, Further Simplification of (a). (c) N02, Network Determinant with 61 ............................ vii «1010110 (74 1 1 13 16 16 20 20 22 26 28 [O (Q 36 40 44 48 59 3.10 Cases expanded with respect to G2 of Figure 16(b). (a) N01 1a, Network Determinant without G2. (b) N011, Further Simplification of (a). (c) N012, Network Determinant with G2. .................. 60 3.11 Cases expanded with respect to G2 of Figure 16(c). (a) ND21, Network Determinant without G2. (b) ND22, Network Determinant with G2. . . 61 3.12 Network Determinant Equation of obtaining transfer function . . . . 62 3.13 a, [3 network representation of the transfer function ........... 63 3.14 Schematic diagram of the transfer function K. ............. 64 3.15 Schematic diagram of the transfer function a. ............. 65 3.16 Schematic diagram of the transfer function 6. ............. 65 4.1 A Example for Approximation ...................... 74 5.1 Tow-Thomas Active Filter ........................ 80 5.2 Bandpass filter function of V2 ....................... 80 5.3 Sensitivity of V2 with respect to R3. .................. 81 5.4 W0 of Tow-Thomas Filter ......................... 85 5.5 Sensitivity of Wo of Tow—Thomas Filter. ................ 85 5.6 Q0 of Tow-Thomas Filter. ........................ 86 5.7 Sensitivity of Q0 of Tow-Thomas Filter. ................ 86 5.8 State Variable Active Filter ....................... 87 5.9 Wo of the State Variable Active Filter. ................. 88 5.10 Q0 of the State Variable Active Filter. ................. 88 5.11 Sensitivity analysis without approximation ............... 90 5.12 Sensitivity analysis with approximation ................. 90 5.13 Bandpass filter function of V6 in Svaf .................. 91 7.1 Series resistor circuit ............................ 102 7.2 Relations between minors. ........................ 105 7.3 Flow Chart of Sspice ............................ 108 7.4 The SPICE file of 741 chip without compensation ............ 110 7.5 Frequency response of uA741 op-amp for gain and phase ........ 111 7.6 Sspice output of open loop transfer function of 741 without compensation. 112 7.7 (a) Low Pass. (b) High Pass. (c) Band Pass. ((1) Band Stop. (e) All Pass filter functions. ........................... 114 7.8 Pspice simulation of State Variable Active Filter using ideal and non- ideal op-amps ................................ 1 19 viii CH CHAPTER 1 MOTIVATION Due to the advances of integrated circuit technologies, computer-aided design has become essential for system development. For years, CAD has played an important roll in designing digital systems. However, the CAD technology for analog circuits is still in its infancy. The major difficulty is the lack of understanding of the diversities of circuits. Therefore, it is very difficult to predict the behavior of a system without in-depth analysis. Directly imposing the design process of digital circuits on analog circuits is impractical. Table 1.1 [1] shows the differences between analogand digital circuit designs. Currently, the design and synthesis of analog circuits depends heavily on circuit level simulation. The ability of each circuit designer to analyze the results from simulation determines the performance and characteristics of his/ her design. CAD tools for circuit analysis become necessary for assisting analog circuit design. 1.1 Analog Circuit Design Process A circuit design process for analog circuits is illustrated in Figure 1.1. ve a range am litude and time is under ponents V8 a precise t to use wi at wo or ttot Circuit times tries necessary est Signals have only two states Standardized Short SUCCCSS ponents wi can simp' Amenab to A at tem times circuits to Table 1.1. Characteristics of Analog and Digital Circuit Designs. Begin Define Analog Functions Does the realized circuit match the requirement? Synthesis of Circuit Level _'lDefined Functions "—5” Simulation _' l Circuit Modification and Resynthesis ‘— Circuit Analysis NO Figure 1.1. Flow chart for circuit design process. Complete 1. Define the s 2. Synth whit 3. Circu izec cor 3. Circ th it: 4. Cir 1. Define Analog Functions : The designer has to define the functions needed for the specific application. 2. Synthesis of Defined Hinctions : Circuit designer has to choose a realization which fits the requirement under a reasonable approximation. 3. Circuit Level Simulation : Circuit simulators are used to verify that the real- ized circuit does reach the defined function. This simulation should accurately . compare with the characteristics of a real product. 3. Circuit Analysis : If the realized circuit does not meet the specification, analyze this circuit to find the main contributor to the deviation from the designed function. 4. Circuit Modification and Resynthesis : Modify and resynthesize the circuit according to the information obtained from circuit analysis. Then repeat the procedure in item 3. ' At present, much effort is being placed in developing circuit simulators. Circuit simulators are now accessible to most designers so that their designs can be verified at a reasonable cost. However, it is difficult to synthesize a circuit correctly the first time, even for an experienced circuit designer. Further modifications are inevitably needed in most cases. How to acquire the information needed for the modifications is still a problem. Many times, it is done by multiple runs of the simulator for a different set of element values. Therefore, experience, intuition, and good luck are still the major factors in this process. They are all ad hoc approaches. 1.2 Analog Circuit Analysis The most common circuit analysis methods incorporated into numerical circuit sim- ulators are DC, AC, and Transient analysis. Bash: doctors s aumnm shah-mg devices. ’Ihe' AC an al small-Si cucuh ofthe transfe Ca Iii Basically, DC analysis determines the dc operating point of the circuit with in- ductors shorted and capacitors opened. Usually, DC analysis is performed prior to a transient analysis to determine the transient initial conditions, and prior to an ac small-signal analysis to determine the linearized small-signal models for nonlinear devices. The results of AC analysis report the ac output variables as a function of frequency. AC analysis computes the dc operating point of the circuit and determines linearized small-signal models for all of the nonlinear devices in the circuit. The resultant linear circuit is then analyzed over the specified range of frequencies. Usually, the input of the linearized circuit is set to one, so that the output of the circuit becomes its transfer function. The Transient analysis computes the output variables as a function of time. In other words, it performs the simulation of the specified circuit with respect to the inputs in time domain. Upon understanding these circuit analysis techniques, the next question would be whether these numeric approaches are sufficient to provide all the informations needed for modifying a circuit. This can be illustrated through the following examples. Example 1 Figure 1.2 shows the schematic diagram of a series RLC circuit, where the transfer function at node 2 is a notch filter. The stopband frequency is about 50K Hz; and the Q0 is about 0.673. Is there any way that a circuit designer can modify this circuit so that the stopband frequency is moved to 100K Hz without aflecting the Q0? Answer: Usually, a circuit designer understands that the inductor and the capacitor control the stopband frequency. The designer may change the values of the capacitor or the inductor to move the W2 at node 2. Then, he/she may use a \ ll 3:. Figure 1.2. Series RLC circuit. SERIES KC CIRCUIT an? ---------- -+- ........... + ---------- + ............ +- ---------- + ----------- 3+ i o+ i 10+ i «at + s a i .40? $ i 2f- - + : ----..i. 1.0Kh 3.0Kh ifllh 30K" 100K" JOOKH 1.0Hh o V68“) Frequency Figure 1.3. Bandstop filter function at V2 of series RLC circuit. numeri the ()0 thenK safisfie Alt node ‘I The it Then the r Exa the 1 in [i 15 t1 CB Cap am] SPe. numerical circuit simulator to verify the modification. The modification may affect the Q0 unintentionally. The values are repeatedly adjusted by trial and error and the modifications repeatedly verified using the simulator until the specifications are satisfied. Alternatively, an experienced circuit designer may derive the transfer function at node 2, which is V2 _ (LS x cs x cs).s2 + GS V1 7 (LS x cs x as)s2 + (CS)s + GS. The formulas of Q0 and W, are, thus, found to be I o m x 9 z 9.. Q0 Wz = \/LS x cs' Therefore, this problem can be solved by increasing the value of LS x CS while keeping the ratio between LS and CS. [:1 Example 2 Figure 1.4 shows a CMOS op-amp and the schematic diagram to obtain the transfer function. Figure 1.5 shows the transfer function of this op-amp. The CL in Figure 1.4(b) is the parasitic capacitor from the circuitry connected to this op-amp. Is there any way that the stability of op-amp can be improved without affecting the GBW? Answer: Figure 1.5 shows the transfer function of the CMOS op-amp with a capacitive load. It is known that a capacitive load can affect the stability of an op- amp circuit dramatically. A circuit designer who designs the op-amp which fits the specific application may not be able to change the circuits that this op-amp connects laws M3 S ‘ E M4 M6 5 i—J c, _r_ 1:3 03.]? M1 M2 LDC/L— - 3 + 6 7 H M8 JMS M7J*—' Figure 1.4. (a) CMOS op-amp. (b) Open Loop gain circuit. conn find this lllllt and sci or O -Sl¢r <1 :¢ ~4 _1 4+ 4+ 1. Llh we seen 1.3a F. * v —r "a", er tom Lu me Frequency Figure 1.5. Transfer function of the CMOS op-arnp. connects to. What he/ she can do is to understand the effect of the capacitive load and modify the internal components of the op—amp so that it can be stabilized for this specific configuration. However, the numerical analysis like Figure 1.5 gives very little about how to improve this op-amp. If a formula like v6 3C1 x GM] — GM6 x GMl i7; ‘ "320,, x 01 + .90. x GM6 + (003-, + GDSG)(GD53 + G195.) K(s + 21) ' (s + M3 + m) is available, assuming GMI = 0M2 and GM3 = GM4 for symmetry, then the zero and poles can be obtained. 21 = _GM6 Cl ’ _ GM6 1%? (3L: a _ (01957 + 0056x0033 + cos.) 1’1 - (:1 )( (:1hfg , The loc haunt oithe‘ wincl If 04 GMS X GM] (0057 + Gossxaosa + GDSI )' dc gain = The location of pg represents the stability of the op-amp, which is determined by transistor 6 and the load capacitor. The circuit designers can change the W / L ratio of the MOS transistor to modify the value of 0M6. Also, GM1 01 ’ GBW = dc gain x p1 = which is independent of GMe. C] The above example shows that a numerical circuit simulator may not fulfill the needs for circuit analysis. In order to improve the quality of analog circuit design, a symbolic circuit analysis methodology providing the analytic solution to the circuits is developed. Without a symbolic circuit analyzer, it is very difficult for circuit designers to have an in-depth understanding of a complicated circuit. However, there are difficulties involved in symbolic circuit analysis. These problems are addressed in Chapter 2. The most common approaches to improve efficiency are by way of circuit decom- position. Many approaches have been proposed. However, the existing methods are not suitable for practical electronic subsystems like the op-amp and the power supply regulator. A new circuit level decomposition method and its variations are, therefore, developed and described in Chapter 3. Chapter 4 introduces a new numerical ap- proximation strategy. This strategy improves the memory consumption of a symbolic circuit analyzer. Besides having an efficient mathematical method for symbolic computation, it is also essential to have built-in functions to help the circuit designers perform analysis. Therefore, symbolic sensitivity analysis and symbolic stability analysis are introduced in C be in Cha process tion an in secc Fir 10 in Chapter 5 and Chapter 6. The implementation of Sspice version 2.0 is introduced in Chapter 7. In addition, second order filters are the most popular circuits in signal processing. The implementation and application of second order function identifica- tion are discussed in Chapter 7. Also, the error analysis due to a. non-ideal op-amp in second order filter implementation is discussed in the same chapter. Finally, the conclusions are given in Chapter 8. rn CHAPTER 2 SYMBOLIC CIRCUIT ANALYSIS 2.1 Introduction The importance of a symbolic circuit analyzer has been recognized by circuit design- ers, since the numerical circuit simulator, alone, cannot give insight into the behavior of an analog circuit [2] [3]. This has lead to the development [4] [5] of various symbolic analog circuit analyzers. Usually, symbolic circuit analysis involves finding network equations in the form of N (s, X) D(s, X) ’ H(s,X)= where N (s,X) and D(s,X) are polynomials in s and the symbolic network variables X. The method used [4] [5] could be the tree enumeration method, numerical inter- polation method, parameter extraction method, signal flow graph method, algebra method or iterative method. The common difficulties inherent in symbolic circuit an- , alyzers are their level of inefficiency for obtaining the circuit functions as compared to its numerical counterpart, their memory space consumption, and the interpretability of their results. These problems are addressed in this chapter. 11 Xuliz [6]. Fig: current possible On the lows equatic 12 Nullators and norators are interesting circuit primitives introduced in the 60‘s [6]. Figure 2.1 shows their symbols. A nullator is an element which does not allow current flow through it and the voltage across its terminals is zero under all the possible situations. The element is thus described by two equations : V=O;I=0. (2.1) On the other hand, the norator has an arbitrary voltage across it and , simultaneously, allows an arbitrary current to flow through it. This element has no constitutive equation. Together, the nullator and norator are referred to as a Nullor [3]. (a) (b) Figure 2.1. (a)Nullator; (b)Norator. Figure 2.2. N ullator-norator equivalent circuit of a VCVS All controlled sources, transistors, op-amps, and even inductors can be modeled using 0313 equivalen- been succ The r introduc briefly it [11] for s disadvan- version 2.2 2.2.1 Writin The dc and p1 strate‘ 13 using only resistors, capacitors and nullors [7]. Figure 2.2 shows the nullator-norator equivalent circuit of a voltage controlled voltage source (VCVS). This approach has been successfully implemented in Sspice [4]. The mathematical background for symbolic analog circuit analysis with nullors is introduced in section 2.2. Besides the matrix approach, the graph approach [8] [9] is briefly introduced in section 2.3. Finally, the existing computer programs [5] [4] [10] [11] for symbolic circuit analysis are mentioned in section 2.4 and the advantages and disadvantages of these approaches are discussed, so that the performance of Sspice version 2.0 can be improved. 2.2 Circuits with Nullors 2.2.1 N ullator-Norator Nodal Analysis Writing nodal network equations by inspection is illustrated in the following example. The details can be found in [3]. The purpose of this example is to take a closer look at. and provide a better understanding of circuits with nullors, so that the decomposition strategy of Sspice can be implemented. oo—~ Figure 2.3. A circuit with nullator and norator. Exarr functzl andn That . 11 12 13 14 Ther betvv COlu] PrOd 14 Example 3 Figure 2.3 shows a circuit with a nullator and norator. Find the transfer function of node 4 with respect to node 1. Answer: First, we find the nodal equations of the network with the nullator and norator removed and connect a current source with a value of one at the input. That is, ’11- ’1. DGl —G1 ‘ “Pl/'1‘ 12 0 —01 G1 + Gz + Ca —Gz —G3 V2 13 = 0 = -G2 02 + 0.; ‘ —G4 V3 I4 0 —G4 G4 + Gs —Gs V; .15. [0_ _-G3 —G'5 G3+G5+Gsd _V5‘ (2.2) Then, each nullator and norator is returned, one by one. Because there is a nullator between node 3 and node 5, V3 equals V5. V3 and V5 can be combined into V3,}; and column 5 of Equation (2.2) is added into column 3, thus, eliminating column 5. This produces [ q I l G1 “—61 V1 0 "GI G1+ 02 '1' Ga —Gz - Ca V , 2 0 = —Gz Gz + G: —G4 ' (2'3) V3.5 0 —G4 — Gs 04 + Gs . V4 _0‘ “G3 Ga+Gs+Gs "Gs J- Because of the norator across node 1 and node 3, there would be an arbitrary amount of current flow from node 1 into node 3 or from node 3 into 1. There should be the same amount of current with opposite signs shown at row 3 and row 5 on the left hand side of the above equation. Therefore, row 3 of Equation (2.3) is added into row 1 so that this arbitrary current can be cancelled. Then, row 3 is eliminated, thus, 15 resulting in the following equation. ’1,+13' ’1' ”G, —Gl—a2 62+G, —G, q _ v1. 12 __ o _ —Gl G1+G2+G3 £2-03 v2 1, — o — —G,-05 G,+G. V3,5 15 J _o] _ —Gs 03+Gs+06 —05 NV” (2.4) which is in the form of I=Y>23 b3! (’32 I733 Yb Find the admittance matrix for N. 1t f0 36 Naz' ‘lN, 3 2 C C . O I 3 o o e— —e Figure 3.1. Example 2 First, the admittance matrix of Na and Nb, connected to each other only at ground, is written as 011 012 013 021 022 023 031 032 033 y-H- = bll b12 b13 1m 522 1m _ bar 532 baa] Then, short node 2 of N, with node 1 of Nb, as described in Figure 3.1, which is the same as putting anullator-norator pair between these two nodes. Therefore, the fourth column and the fourth row of 1"” are added into the second column and row; 37 then, the fourth column and row of Y++ are removed. This results in 011 012 013 021 0224-511 023 512 513 Y4. = 031 032 033 521 522 (>23 531 532 533 J Again, node 3 of N a and node 2 of N b are shorted by adding the fourth column and row of Y‘l' into the third column and row; then, the fourth column and row are removed. As a result, the admittance matrix of N becomes an 012 013 021 022 + bu 023 + bl2 b13 G31 032 + 521 033 + 522 523 bal 532 baa Cl Based on this example, the relations among Ya, Y5, and det(Y) are explored by reversing the matrix construction process. Expanding Equation (3.1) at the second column yields det(Y) = -012 X Yl.2 + (022 + 511) X Y2,2 - (032 + bar) X 13.2 + 1’31 X 32.2 = -612 X Yl,2 + €122 X Y2,2 - 032 X 33.2 + 531 X Yes —0 X Yuri-bu X Y2,2 - 521 X 3,3,24‘531 X Ym p 011 021 det 031 012 022 032 033 + 522 013 023 + bl2 632 38 (’13 bzs baa + det 021 031 all bll bar 531 023 + 512 (’13 033 + 522 013 (>23 b33 532 Using the same method, the decomposed matrices are further decomposed at the third column and the second and third rows, iteratively, as follows : det(Y) = det +det 011 012 013 021 022 023 031 032 033 an 013 021 023 (>21 bar bza baa + det + det .l 011 012 021 022 b2: baz all 013 bu 031 033 531 lbs baa b13 baa + det + det Then, as the a entries and b entries are collected together, det(Y) = p det an 012 013 021 022 023 031 032 033 + det 011 012 021 022 b2: 532 523 — det (3.3) an an - 512 (’13 031 032 532 533‘ [an ' bu bu b13 521 522 as. ' _ 531 b3: baa J (3.4) an 012 031 032 512 513 b3: 533‘ 39 . . . . , an 013 011 013 011 -—det 021 023 + det 031 033 + det bu 512 b13 521 523 bn 513 521 (’22 I223 _ bar 533 . _ 531 533 . [ 531 532 533 4 According to Equation (3.5), all the decomposed matrices are block diagonal ma- trices. Each block consists of all a’s or all b’s and belongs to a specific sub-circuit. These blocks are variations of Y, or Yb obtained by eliminating columns or rows and are modeled by putting nullators and norators at the corresponding nodes. Decom- position information, therefore, can be provided at circuit level. Figure 3.2 shows the computation in a more illustrative way and corresponds to the six cases in Equa- tion (3.5). 3.3 The Algorithm The following is the algorithm which obtains the network determinant of a circuit by decomposition as shown in Example 4. ALGORITHM : Ndet_by_Decomposition(N) /* N is the network */ /* N is decomposable into Na and Nb */ /* The node numbers in Na are all less than the node numbers in Nb */ { ResultSNULL; P<-Identify,cut_nodes(N); /* Get the cut nodes except the GND */ Na,Nb<-Decompose(N,P); #_of-case-2**(#_of_P); For(i=0;i<#_of-case;i++) { For(j-O;j<#_of,case;j++) { 4O (c) T (s) Figure 3.2. The decomposition and composition of two sub-circuits connected at three nodes; (a) The whole circuit; (b)-(g) six cases. 41 Pu-encode-decimal-to_binary(i,#-of-P); /* when i==2 and #_of_P==4, Pu8’0010’ */ Posencode-decimal,to-binary(j,#-of_P); For(m-O;m<¢_of,P;m++) { If(Pu[m]=*1} { Put-nullator_between_P[m]_and_GND_in_Na; } else { Put_nullator_betveen_P[m]_and-GND_in_Nb; } Ir(Po[mJ==1} { Put-norator-between_P[m]-and-GND;in_Na; } else { Put-norator_betueen_P[m]_and-GND-in_Nb; } } If( Valid(Na) as ValidCNb) ) { A-Ndet(Na); s-Ndet(Nb); ResultSResu1t+A*B*Sign(N,Na,Nb); } Bemove_the_added_nullator_and_norator-at_P; } } Return(Result); } Suppose the sub-circuits, Na and Nb, are connected at n nodes, except the ground, the above algorithm would connect n nullators and n norators between each con- nection node and the GND, either in Na or in Nb, for all the possible combinations. Each combination is a decomposition case. Then, the algorithm needs to examine whether the newly formed sub-circuits are valid for each decomposition case. If both of them are valid, their network determinants can be obtained independently by any of the existing network determinant algorithms without decomposition. The network 3 42 determinants obtained are, then, multiplied together with an appropriate sign. In Example 4, there are only six valid decomposition cases. The validity of a circuit and the procedure to obtain the signs are defined next. Example 5 Figure 2.4 shows a circuit. What are the u and o indexes of node (4)? Answer: There are four nodes whose node numbers are less than 4. They are (0), ( 1), (2), and (3). Both node 0 and node 2 have no norators connected to them and are counted into two norator trees which are empty. Also, node 1 and 3 belong to the same norator tree. Therefore, the 0 index of node 4 is three. The u index of node 4 can be found in the same way and it is four. El Definition 14 (Inverse u nodes, iu nodes, iu(k,N)) iu(k,N) represents all the nodes whose u index is k in the network of N. Definition 15 (Inverse 0 nodes, io nodes, io(k,N)) io(k,N) represents all the nodes whose 0 index is k in the network of N. Actually, the u index and the 0 index represent the location of a node in an admittance matrix. If there is an element G connected to a node whose (u index, 0 index) is (j,i) and i 95 0, j 94 0, then there will be a term of +G at the entry of i’th row and j’th column in the corresponding admittance matrix. Because the order of columns and rows in an admittance matrix can affect the sign of its determinant, as shown in equation (3.5), this can be modeled by the permutations of the u and o indexes. Definition 16 (Decomposed 11 index, du index, du(p,N,case)) The du index of node p is the u index of node p in N with nullators and norators added under a specific decomposition case. N can be decomposed into Na and Nb. The node numbers of the nodes in Na are smaller than those in Nb. 43 Definition 17 (Inverse du nodes, idu(k,N,case)) idu(k,N,case) represents the set of nodes whose du indexes are k for the specific decomposition case of network N. Definition 18 (Decomposed 0 index, do index, do(p,N,case)) The do index of node p is the 0 index of node p in N with nullators and norators added under a specific decomposition case. N can be decomposed into Na and Nb. The node num- bers of the nodes in Na are smaller than those in Nb. Definition 19 (Inverse do nodes, ido(k,N,case)) ido(k,N,case) represents the set of nodes whose do indexes are k for the specific decomposition case of network N. Definition 20 (Connected du index, cdu index, cdu(k,N,case)) The connected du index is the u index of the nodes whose du index is k for a spe- cific decomposition case in network N before the decomposition scheme is applied. cdu(k,N,case)=u(idu(k,N,case),N). Definition 21 (Connected do index, cdo index, cdo (k,N,case)) The connected do index is the 0 index of the nodes whose do index is k for a spe- cific decomposition case in network N before the decomposition scheme is applied. cdo(k,N,case)=o(ido(k,N,case),N). Example 6 Figure 3.3(a) shows a circuit that consists of two parts, Na and Nb. By applying the above decomposition algorithm, a case, as shown in Figure 3.3(b), simular to Figure 3.2(d) results. Find the du and do indexes of nodes (1’) and (2’) for this case. Assume all the node numbers in Nb to be larger than those in Na. Also, find the cdu(du(2’ ,N,case) ,N,case) and cdo(do(1’ ,N,case) ,N,case). 44 Nb Na —e(1') —e(2) (0’) Nb v M =1; (4) e— (3) ’— (m A ‘ I Na (b) Figure 3.3. Example with Na and Nb 45 The (du index, do index) for (1’) in Figure 3.3(b) is (0,5) and for (2’) is (6,0). cdo(do(1’ ,N,case) ,N,case) is 3 and cdu(du(2’ ,N,case) ,N,case) is also 3. D According to the above definitions, each du or do index of a specific decomposition case has a cdu or cdo index which describes the relocation of the column or the row in the admittance matrix before the decomposition is conducted. This is referred to in section 3.2. When only one of the du to cdu permutation and the do to cdo permutation is odd, a -1 should be multiplied to this decomposition case. We may conclude the following algorithms. ALGORITHM : Valid(N) { usmax(all-the-possible-u_index(N)); osmax(all-the_possible_o_index(N)); if(u-=o) { return(1); } else { return(0); } } Sign(N,Na,Nb) { /* U is an array with the length of the maximum number of u index in N */ /* 0 is an array with the length of the maximum number of 0 index in N */ /* The length of U and the length of 0 should be the same */ k-max(all-the_possible_u-index(N)); For(i=0;i 0 while FEuazuate,DD(N,q,3) < 0 means that if the cir- cuit can be partitioned at two nodes, the application of decomposition improves the computation efficiency. If this circuit can only be partitioned at three nodes, then decomposition is not beneficial to this circuit. If the determinant obtaining algorithm is improved, then the computational com- plexity becomes N“ x ! Flmprovc(Na (I, f) S W- (38) Similar to Equation (3.7), this results in Fm rave N: if FEvaluate,Improve(quamif) S 109(2 X F] I ’EN/g q)qX 370 (771)) mprove , use qN/2 x N 2 = log( ...“ / ) ,). (3.9) 2xfxZ((m ——',——,_),,.) i=0 When f(N) = 1, Equation (3.9) is equal to Equation (3.7). Figure 3.4 shows the 48 trend of maximum number of cut nodes, m, that keep Fgwruateympww > 0 for different circuit dimensions, N, while the average connectivity, q, is 3.5. Average'connectivity 3.5 g 16 1 T 1 y j g N/2 14 * f(N)-1 -9— a +5; f(N)-N*§3v"—o—— o 12 - f(N)-2*‘N 4*- ' o-r . .9. 10 - . 9. . L ‘ '3 8 r: a e L - s ... . E '04 33 2 _ . z g 0 -" - 1 1 m 1 0 5 10 15 20 25 30 N, Dimension of the Network Figure 3.4. Maximum beneficial cut nodes analysis. According to Figure 3.4, as the dimension of the circuit increases, the acceptable number of cut nodes increases. Also, as the computation complexity of the network determinant obtaining algorithm improves, the acceptable number of cut nodes de- creases. In [23], it shows that the complexity of the resistor chain with length n is 0(2“) when the DD algorithm is used. On the other hand, the complexity for the SLE/ M algorithm [23] is 0(n2). Similarly, according to Equation 3.9), one can eas- ily find that decomposition becomes not so attractive for loosely connected circuits. Therefore, the application of decomposition to an ordinary circuit with a dimension less than 8 is not encouraged while using Sspice version 2. 0. 49 3.4 Exploiting Special Decomposition Opportu- nities According to the procedure described in Equation (3.2), it should show 16 decom- posed cases in, Figure 3.2; however, 10 of them consist of invalid sub-circuits. Their network determinants are identified to be zero, according to Theorem 2. Each case in Figure 3.2 is a circuit consisting of two valid sub-circuits connected to each other only at the ground. According to Lemma 1, the network determinants can be obtained from those of the sub-circuits. The above is a generalized procedure. For some situations, special rules may be very usefully to simplify the procedure. Theorem 4 A network N consists of two parts, N1 and N2, where N1 and N2 are valid circuit. If they are connected at two points, at the ground and at node x, then the network determinant of N is (-1)P+* x Ndet (1v1 ) x Ndet(Ng) + (—1)q+'c x Ndet (M) x Ndet(Ng). Here, N1 (N2) is N1 (N2) with node a: shorted to ground. p, q and k are the summa- tions of the o and u indexes of node a: in N1, N2 and N, respectively. Proof: The input admittance of N at a: is equal to Ndet(N) (—1)k x Ndet(N) Ndet(Nl) . + Ndet(Ng) ‘ (4)» x Ndet(Nl) (—1)o x Ndet(Ng) H)» x Ndet(Nl) (—1)9 x Ndet(Ng) Ndet(Nl) Ndet(Ng) H)» x Ndet(Nl) x Ndet(Ng) + my x Ndet(Nl) x Ndet(Nz) Ndet(Nl) x Ndet(Ng) (Theorem 1) (Theorem 1) 50 A where N is N with node x shorted to ground. Because Ndet(N) is equal to Ndet(Nl) x Ndet(Ng), this theorem is concluded. C] Similar to the theorem of Parameter Extraction [13], the network determinant can be decomposed into two parts, one consisting of terms with a specific element, say G, and the other consisting of terms without this element. It becomes a special case of Theorem 4 when N2 is a single element, and may result in the following corollary. Corollary 1 If there exists an element G connecting nodes p and q in network N. then the network determinant of N is equal to N det(N1)+(-—1)"""+"‘ x G x N det(Ng). Here, I: (l) is the largest o (u) index of p and q. When both 0 and u indexes of p are larger or smaller than those of q, m=0. Otherwise, m=1. N1 is a network of N without G; N; is a network of N with an additional pair of nullator and norator parallel with G. If either 0 or u indexes of p and q are equal, then N det(N2)=0. Example 7 According to Corollary 1, the network determinant of Figure 3.5(a) is equal to Ndet(N1)+ (—1) X 64 x Ndet(Ng). N1 is shown in Figure 3.5(b), and N2 is shown in Figure 3.5(c). Ndet (N1)=0 by Theorem 2. Theorem 5 If there exists a nullator (norator) connecting nodes p and q in network N, the network determinant, Ndet (N), is equal to Ndet(N1)+(—1)'j‘”'1 x Ndet(Nz). Here, j is the u (0) index of node p and l is the u (0) index ofq in the circuit ofN+. N1 is a circuit which relocates the nullator (norator) connecting p and q in N to p or q with a larger u (0) index in N + and ground. N2 is a circuit which relocates the nullator (norator) connecting p and q in N to p or q with a smaller u (0) index in N+ and ground. N+ is N without the nullator (norator) connecting p and q. When j=l, this nullator (norator) is redundant. 51 (1) 01 (2) 02 (3)03 (4)64 (5)05 (6)06 (7) ? (a) (l) 0‘ (2) 02 (3) 03 (4) (5) 05 (6) 06 ('7) ? (b) (1) 0‘ (2) 01 (3) (6) 06 (7) (0) - _ é- - (C) Figure 3.5. Example 3. 52 Proof: For the nullator, since the admittance matrix of N + can be laid out as 01,1 I o o al,j o o 0 al,’ 0 o o al,n+l an'l o o o an'j o o a an,’ o o o an’n+1 which is an n x (n + 1) matrix, the admittance matrix of N1 becomes 01.1 01,1“ alJ—l 01,l+1 arm-1 Y1 an,1 ° ' ° and ' ' ° an,l—l an,l+l ° ' ' an,n+1 if I > j; and lam 01.j—1 al,j+l 01,: 01,n+1 Y2 an,1 . . . an,j-l and-+1 . . . an", . . . aunt-+1 J Both Y1 and Y; are n X n matrixes. Also, the admittance matrix of N should be lam a1,,-+a1,, a1.1—1 a1.1+1 al,n+l an,l ' ' ' an,j + 0:1,! ‘ ° ' amt-1 an,l+1 ' ' ’ an,n+l J det(Y) = (_1),-_1 x l det = (-—1)J'-1 x det(Y“) 53 a1,,-+a1,: 01,1 al,j-l 01,j+1 dud-01,1 01,1 01.j-1 al.j+1 = (-l)j-'l X 2(050' + a“) X Yr]. i=1 det(Y1)= (—1)J'-1 x 01,5 01.1 01,1-1 det 01,1‘ 01.1 01.j—1 = (-1)""1 x det(Y‘H") = (.1):'-1 x in,» x v37. i=1 det(Yg) = (—l)’""1 x F 01.1 01,1 01.j-1 det 01.1 01,1 al,j—l = (—1)'-2 x det(Y+++) (4)” X 20%.!) X YIN- i=1 alJ-H 01J+1 01.141 al.j+1 “1.1-1 “1.1-H “1.1-1 01,I+1‘ 01,1-1 01.1—1 alJ-l 01,1-1 “1.1-H 01.l+1 “1.1-H “1.1-H al.n+1 01,n+1 01,n+1 al,n+l j al,n+l 01,n+1 54 + _ ++ _ +++ Because Yin —- Ya —— Yin , det(Y)) = (—l)"-1 X inlaid) X YES; i=1 det(Yz) = (—l)l-2 X £01.31) X Ytl. i=1 det(Y) = (—1)J"1 East-T, + (-1)"'1 ZauYi-S {:1 i=1 det(Yl) + (_1)J'-1 X (_1)U-2)-(j-1) X (_1)(l—2)—(j—1) X :0”sz i=1 l = det(Y1)+ (—1)"""1 x (—1)""’ x Z «.th i=1 = det(Y1)+ (—1)’-J'-1 x det(Yg). When j > I, det(Y) = det(Yl) + (—1)""'1 x det(Yg). This concludes the nullator part of the theorem. Similarly, the norator part of the proof can be done in the same way. C] Example 8 According to Theorem 5, the network determinant of Figure 3.6(a) is equal to the summation of the network determinant of Figure 3.6(b) and Figure 3.6(c). Table 3.1 shows the verification. Figure Network Determinant Figure 8(a) -GS*Gl Figure 8(b) -G3*GI-G2*Gl Figure 8(a) +G2*GI Table 3.1. Symbolic Network Determinants of Example 4. 55 (1) °‘ (2) “2 (3) G3 (a) (1) °' (2) m (3) (1) G‘ (2) “2 (3) 03 0 O 03 Figure 3.6. Example 4. 3.5 A Circuit Level Decomposition Application Figure 3.7 shows a circuit which consists of two parts, connected at 4 nodes, including the ground. Adm is a voltage controlled voltage source with an undefined transfer function. Supposing both Am and B are complicated circuits, the process for com- puting the symbolic network determinant of this circuit, ND, would need decomposi- tion so that the transfer function can be obtained efficiently. However, according to the methodology described in Equation (3.2)-(3.5) and Figure 3.2, it may produce 20 different cases. In this section, we will show how Theorem 4 and Theorem 5 further simplify the proposed circuit level decomposition strategy. Without affecting the circuit characteristics, two voltage controlled voltage sources with values of one are inserted between nodes A, B, D, E, and nodes C, F, ground. The voltage controlled voltage sources are substituted by the norator-nullator equivalent circuit as shown in Figure 2.2. This may produce Figure 3.8. In this way, we can 56 Figure 3.7. An Example Circuit with two parts. il Figure 3.8. The Equivalent Circuit 57 Table 3.2. o and u indexes. perform the decomposition at the inserted circuits so that the original circuits, Adm and B, are kept unchanged. - B is an m by m circuit and Adm is n by n. The inserted circuits produce extra nodes to Figure 3.8. All these nodes have their unique node numbers and L > K > J > I > H > G > AllOtherNodes. The 0 index and u index of each node can be listed as shown in Table 3.2. We assume that ho > a0, bu > an, do > ea, and du > eu. According to Corollary 1, the network determinant of Figure 3.8 is equal to NDla + (—1)9°+"“+1 x N02, (3.10) where NDia and ND2 are the network determinants of Figure 3.9(a) and Figure 3.9(c), respectively. This equation can be further simplified to (—1)9°+°‘u+1 x ND1 + (—1)9°+"«+l x ND2, (3.11) 58 where N01 is the network determinant of Figure 3.9(b). Again, by applying Corollary 1, ND1 is found to be ND11a+ (_1),-,+;, .x N012 = (_1)jo+cu+l X ND11 + (_1)jo+fu x N012, (3.12) where ND11a, N011, and ND12 are network determinants of those circuits shown in Figure 3.10. Because the circuit in Figure 3.10(c) has invalid sub-circuits, N01 = (-1)J'°+‘=«+1 x N011. (3.13) The same procedure can be applied to N02. Therefore, N02 = N021 + (-1)J'°+f~ x N022 = (—1)J'°+f~ x N022. (3.14) ND21 and ND22 are the circuits shown in Figure 3.11. Figure 3.11(a) has invalid sub-circuits. It can be concluded that ND = (_1)90+jo+cu+du X ND11 + (_1)go+jo+bu+fu+l X N022 = (.1)‘-‘«+0‘u+1 x N011 + (—1)”"+’" x ND22, (3.15) for go + jo is an odd number. In this example, a 20-case decomposition approach is reduced to only 2 cases. Each case has well decomposed sub-circuits. According to the above discussion and Theorem 1, if the sign adjustment of all 59 Figure 3.9. Cases expanded with respect to GI. (a) NDla, Network Determinant without 61. (b) N01, Further Simplification of (a). (c) N02, Network Determinant with Cl. 60 Figure 3.10. Cases expanded with respect to G2 of Figure 16(b). (a) NDlla, Network Determinant without G2. (b) ND11, Further Simplification of (a). (c) N012, Network Determinant with G2. 61 C (b) —; Figure 3.11. Cases expanded with respect to G2 of Figure 16(c). (a) ND21, Network Determinant without G2. (b) ND22, Network Determinant with 62. 62 the network determinants of the decomposed cases is one, the transfer function of the circuit in Figure 3.7 is illustrated in Figure 3.12. N det 5 _,< N det N det hall lineal Figure 3.12. Network Determinant Equation of obtaining transfer function Figure 3.13 shows a variation of the transfer function of Figure 3.12. It is done by applying a few simple algebraic operations so that its physical meanings can be understood from the transfer function. According to section 2.2, the transfer function of a circuit is the ratio of two network determinants which connect an extra nullator- norator pair to the input-output nodes and the ground of the circuit. The K, a, and ,6 in Figure 3.13 are ratios of network determinants. Therefore, they are the transfer functions of the specific circuits. According to Figure 3.13, K is the transfer function of the circuit in Figure 3.7 with its Adm replaced by an ideal op-amp because an ideal op-amp can be modeled by 63 Figure 3.13. a, 5 network representation of the transfer function. 64 a nullator-norator pair. This is shown in Figure 3.14. a of Figure 3.13 is the transfer function of B in Figure 3.7, accomplished by changing node C to be the new input," node A and B to be the new output, and by connecting an ideal op-amp with its input at the old Output of B and with its output at the old Input of B. This is shown in Figure 3.15. Similarly, fl is the transfer function of B accomplished by changing node C to be the input, node A and B to be the output, and short the original Input node to the ground. This is shown in Figure 3.16. Each of these figures represents a unique circuit. Also, according to Theorem 5, the Adm represents the transfer function of the voltage controlled voltage source in Figure 3.7. VIN a I _r_—— —; Transfer Function 19$- VIN Figure 3.14. Schematic diagram of the transfer function K. Through the above interpretation of Figure 3.13, one can find the sources of non- ideal effects of a circuit. Then, a circuit designer can concentrate on the decomposed a and 6 networks. 65 Ideal Op-cunp VOUT Transfer Function rm— Figure 3.15. Schematic diagram of the transfer function a. l— 721,—: VOUT VIN Transfer Function - Figure 3.16. Schematic diagram of the transfer function 6. CHAPTER 4 NUMERICAL APPROXIMATION STRATEGIES FOR SYMBOLIC CIRCUIT ANALYSIS The use of symbolic expressions to characterize input-output relations is an impor- tant analytic tool with a wide range of applications in the analysis and synthesis of networks and systems. However, the use of computer programs to accomplish sym- bolic analysis has some inherent problems related to memory consumption as well as, to the computation inefficiency of obtaining network determinants addressed in chapter 2 and 3. The need for huge memory space for a moderate size commercial chip would eventually further worsen the computation efficiency. An greater problem is the large amount of output generated for the results of the circuits with more than 20 components. The volume of output generated in the symbolic analysis process currently represents one of the most restrictive limitations on the symbolic analysis technique. In this chapter, the proposed solutions are presented for different stages of the symbolic analysis process, which include numerical analysis before, during, and 66 67 after computation. 4.1 Numerical Approximation After Computa- tion The need for numerical approximation after computation is illustrated in the following example. Mathematically, it is trading off accuracy for simplicity. Example 9 Use symbolic approach to find the transfer function of the CMOS op-amp in Example 2. Answer: For simplicity, the low frequency small signal CMOS model is used in this example. The component values of the small signal model of each transistor is obtained from Pspice by using .0? card. A symbolic program [4] would generate the following results, where V6 represents the open loop gain. Numerat or of : V6 TERMS SORTED ACCORDING TO POWERS OF 3 s**1 terms: + sCl*GM8*GM4*GM2*GM1 + sCi*GM8*GM4*GM2*GDSl ° + 8C1*GM8*GM3*GM2*GM1 + 8C1*GM8*GM3*GM2*GDSS 16 lines not shown It!*********************************************** NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT 68 + 2.543439-30 * s**1 - 1.942269-22 * s**o ************************************************ Denominator of: V6 TERMS SORTED ACCORDING TO POHERS OF 8 s**2 terms: sCL*sC1*GM8*GM3*GM2 - sCL*sCl*GM8*GM3*GM1 - sCL*sCl*GM8*GM3*GDSS - sCL*sC1*GM8*GM3*GD82 - sCL*sC1*GM8*GM3*GDSl - sCL*sCl*GM8*GM2*GDSS - sCL*sCl*GM8*GM2*GDSl - sCL*sC1*GM8*GM1*GD83 - sCL*sC1*GM8*GDSS*GD83 - sCL*sC1*GM8*GDSS*GDSl - sCL*sCl*GM8¥GDS3*GDS2 - sCL*sC1*GM8*GDSS*GDSl - sCL*sCl*GM8*GD82*GDSI - sCL*sC1*GM3*GM2*GD88 133 lines not shown ************************************************ NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT - 1.790789-36 * s**2 - 3.05371e-29 * s**1 - 1.14017e-26 * s**0 ************************************************ Clearly, the full symbolic result is too complicated to be used. Since the values of the components in this op-amp are known, and the coefficient of each order of s is dominated by only a few terms, the above symbolic result can be approximated and simplified. The following is the result of using 5% approximation. Numerator of : v6 69 TERMS SORTED ACCORDING TO POWERS OF 8 s**1 terms: + sC1*GM4*GM2*GM1 + sC1*GM3*GM2*GM1 s**0 terms: - GM6*GM4*GM2*GM1 - GM6*GM3*GM2*GM1 *ttt*##*********##***********ttttttttttttttttttt NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT + 6.78776e-26 * s**1 - 5.18338e-18 * s**0 *************sttstttststtsssstt***************** Denominator of: v6 TERMS SORTED ACCORDING TO POWERS OF 3 s**2 terms: - sCL*sCI*GM3*GM2 - sCL*sC1*GM3*GM1 s**1 terms: - sC1*GM6*GM3*GM2 - sCl*GM6*GM3*GM1 s**0 terms: - GM4*GM1*GDS7*GDS2 - GM4*GM1*GD36*GDS2 - GM3*GM2*GDS7*GDS4 - GM3*GM2*GD56*GDS4 - GM3*GM1*GDS7*GDS4 - GM3*GM1*GDS7*GDS2 - GM3*GM1*GDSS*GDS4 - GM3*GM1*GDSG*GDS2 *******$***************************************III 70 NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT - 4.74668e-32 * s**2 - 7.974439-25 * s**1 - 3.029e-22 * s**0 ' ***********************************************It! Now, the simplified result is ready for analyzing this op-amp. D The procedure for performing numerical approximation involves tedious floating point operations and sorting. When the size of the symbolic result increases, the computation time needed increases. Therefore, many approximation strategies have been proposed. 4.1.1 Numerical Approximation in ISAAC The numerical approximation algorithm implemented in ISAAC [5] [23] is briefly introduced in this section. ISAAC’s approach inspired the development of the ap- proximation method of Sspice version 2.0. The error definition being used in ISAAC is the accumulated absolute error (A : CA: ZIMQI Iglxll £=£, (4.1) where g(g) is the original expression, t,~(_x) are the pruned. terms, and go is the point of evaluation. Notice that in the numerator, the absolute values are summed. The error CA used in ISAAC is an estimation of the effective error, because the numerical values of the terms may cancel each other at the numerator of equation (4.1). The approximation algorithm of ISAAC consists of two steps [23]. First, all terms smaller than the fraction cm“. of the original expre’ssion’s mean value are discarded; 71 i.e., all t.-(x) terms are discarded for which 2: |t£(£o)l S m (4.2) lg(x)l n with n being the number of terms in the original expression g(x) and cm, the maxi- mum error as supplied by the user. Then, the remaining terms are sorted according to their magnitude and the smallest terms are removed as long as e < cm“. This approximation can be done for a specific frequency or over the whole frequency range. The numerical approximation approach implemented in ISAAC spends expensive resources on sorting and indicating errors specified by the circuit designer. But, the error estimation definition, which is based on the accumulation of the absolute values of the terms that are given away, falls short of accomplishing its goal. 4.1.2 Numerical Approximation in SCOPE SCOPE [24] is a Symbolic Circuit Output Processor and Evaluator. It allows the user to input numerical values for all the symbolic variables in order to generate a system function consisting of numerator and denominator polynomials in powers of s with numerical coefficients. This capability is also available in Sspice [4]. SCOPE also permits the user to retain any one of the symbolic variables as a sym- bolic quantity while numerical values are assigned to the other symbolic variables. This generates a symbolic input-output function consisting of numerator and denom- inator polynomials in powers of s with coefficients which are functions of a single symbolic variable. This is a mixed numerical and symbolic representation. How- ' ever, SCOPE is limited to either using only one symbolic variable format or using all symbolic variable format expressions. 72 4.1.3 Numerical Approximation in Sspice The numerical approximation technique of Sspice [4] is based on the fact that 1 f(8) = +1, filt-‘fi 22 when a >> b. Sspice finds the largest term of each coefficient of orders of s. Then. throws away all the t,- terms in which Itil ltlargestl < ézhmhazd- etlu-eahold should be given by the user. This method avoids the complicated sorting mechanism which is necessary in ISAAC. Sspice version 2.0 provides the actual nu- merical error generated by the above procedure. This gives the circuit designer a concrete basis with which to evaluate the quality of their approximations. Also, Sspice version 2.0 allows any number of symbols be substituted by their numerical values. This makes Sspice version 2.0 a complete mixed symbolic and numeric circuit analyzer and, thus, a more flexible one than SCOPE. 4.2 Numerical Approximation During Computa- tion In order to make symbolic circuit analysis practical for large circuits, effective numeri- cal approximation is essential. In the past, the objectives of numerical approximation were focused on providing more informative answers to the circuit designer. Huge symbolic solutions were reduced to a few dominant terms so that critical circuit characteristics could be identified [25] [4] [5]. This approach has been successfully 73 implemented in many symbolic analog circuit analyzers. It is called numerical ap- proximation after computation. Through the usage and implementation of Sspice, it has been found that full symbolic computation is highly memory consuming. Without a good approxima- tion strategy during computation, most of the existing computing systems cannot handle a circuit like an op-amp or a power supply regulator, because of the limited physical memory available. If we could approximate the intermediate results during computation, then the symbolic approach of circuit analysis would become practical. Two factors affect the applicability of a numerical approximation strategy : effi- ciency and reliability. Traditional numerical approximation techniques involve search- ing, sorting, and high precision floating point computation. All these are highly time consuming. Executing the numerical approximation only once after obtaining a spe- cific matrix determinant is acceptable. However, performing it many times during the determinant computation would not be desired. Since the matrix determinant can be obtained by decomposition, as described in section 3.2, numerical approximation can be applied only to the result of each sub-circuit, so that cpu time can be saved. I Furthermore, the existing approximation techniques, which throw away those unimportant terms, produce errors. If we apply the same technique during com- putation, the accumulation of errors may result in an unacceptable answer. The new technique , now, replaces the unimportant terms by their numerical values so that the accuracy of the results can be preserved. Therefore, the new approximation technique in Sspice makes this tool a mixed symbolic and numerical circuit analyzer. The application of the new technique still needs more attention. The mixed nu- merical and symbolical solution may have terms which should be cancelled with full symbolic computation, now, left as a part of the solution. This is due to the trunca- tion error of the floating point operation. Therefore, the user or the analyzer should check whether there exists duplicated component names [2] and circuit loops [9] . All 74 P1 92 1110.01 9‘ 1‘ R3 1 es la R5 100 c2100u— 122 m R4 C4 100.. IM R6100 . —-4 P11 P21 -.1_- P12 P22 03) Figure 4.1. A Example for Approximation these terms should be replaced by their numerical values as described for the new approximation strategy. Example 10 Figure 4.1 shows a circuit. Use the approximation during computation technique described above to find its network determinant. As shown in Figure 4.1(a), this circuit can be decomposed into P1 and P2. Accord- ing to section 3.2, the network determinant is equal to P11 x P21 + P12 x P22, where P11, P12, P21, P22 are the network determinants of the decomposed sub-circuits shown in Figure 4.1(b). Table 4.1 shows the network determinants with and without approximation. The threshold value is 0.05. This example shows that the application of the new approximation method to the decomposed sub-circuits can maintain the 75 without approx. with approx. +8C2*SC1*°1 +sC2*sC1*Gl P11 +801*G3*Gl +sC1*G3*Gl *301*G2*Gl +16'10*8 +sC4*sC3*GG +sC4*sC3*G5 *804*SC3*GG P21 +8C3*GG*G5 +8C4*8C3*G5 +scstcstc4 A +3C3*65*95 +303¢GS¢G4 *29'14*3 +scz*301*63*61 +sc2tsC1*GS*Gl P12 +sCl*GS*G2*Gl +sc1*63*G2*61 +sC4*GG +SC4*95 +sC4tG6 *8C3*65 +8C4*GS P22 +BC3*GS +29-8ts +GG*95 +G6*G5 *GG*G4 +2e-8 +GS*G4 Table 4.1. With and Without Approximation for P1 and P2 correct numerical values while reducing the number of terms for each case. E] 4.3 Numerical Substitution Before Computation For the approximation during computation strategy, the circuit designer can plug in the numerical values. They are identified or aesumed not to be the critical compo- nent of a circuit before computing the matrix determinant. This is called numerical approximation before computation. This technique has been extremely successful for analyzing large circuits. Circuit designers can. identify the critical components via their experiences and then verify their theory by running the circuit analyzer. 76 Example 15 in section 7.3 shows the application of this technique. CHAPTER 5 SYMBOLIC SENSITIVITY ANALYSIS In order to design a high—performance analog circuit, the designer should marshal every detail which may affect its functionality and performance. One of the most important measures which states the characteristics of a design is how sensitive the circuit is with respect to a specific element. Therefore, designers can design a more suitable circuit by trading off different factors. Sometimes, the changing of an ele- ment value may affect the sensitivity of other elements to a specific factor of merit. Therefore, a designer would appreciate not only to have the numerical value of the sensitivity measure but also its constitutions so that some trade offs can be considered .more in-depth. 5.1 The Implementation of Symbolic Sensitivity Analysis The calculation of sensitivity can be substantially simplified by applying the following rules which are called Sensitivity Algebra [3]. The symbolic sensitivity analysis, SEN() is done by applying the following rules recursively. 77 78 1. If H = c, where c is a constant, then SE = 0. 2. IfH = cx, then S}: =1. 3. If H = [cf(x)]", then 55’ = n51"). fISZ‘ + 12512 + + 35;». 4. IfH: f1($)+f2(1')+...+fn($), then 55’ = fl +f2 + -.-+fn 5. If H = f1(x)f2(x)...f,,(x), then 51’ = S," + 5,? + + Si". The following is an example to show how these rules work. Example 11 IfQ = 3_1—K, then 53 = 5k - 27K _3S§"< + (-K)S;;-"' 3 — K ___£"__ 3 — K The symbolic network functions of a circuit are generally of the form . N(3,P1,P2,u-,Pm) H = (8) 0(33P1,P2,u-,Pm), (5.1) where N and D are both polynomials. Therefore, the sensitivity analysis formula becomes N D H N D S, = .S‘,,,-.S‘,,,=—1V‘p—7)a __ N,xD—D,xN — NxD ’ where N, is a polynomial that includes the element p in every terms. The polynomial of D, also has the same pr0perty. Usually, the numbers of the terms in N and D are much greater than those in N, and D,, respectively. Therefore, the computation of N x D is very costly. If the user is choosing the'numerical approximation Option, then we can take advantage of approximating N and D before multiplying them to 79 get the denominator of Equation (5.2). Therefore, QSNO is implemented according to the following Quick Sensitivity Algorithm. Quick Sensitivity Algorithm : QSN(N/D,p) Np - NUM(SEN(N,p)) Dp - NUM(SEN(D,p)) If approximation is selected Then { Na 8 Significant terms in N; Da I Significant terms in D; } Else { Na I N; Da 8 D; } Return( (Np*D-Dp*N)/(Na*Da) ); One may also notice that OSN(H,p) improve the speed of the computation without sacrificing the accuracy of other than the threshold value used for numerical approx- imation, set by the user. However, SEN(SMY(H) ,p) may suffer unexpected errors. Finally, DIF (11.2) is implemented as SEN(H,x)*H/x. 5.2 Applications of Sensitivity Analysis Figure 5.1 is a Tow-Thomas active filter. We would like to evaluate the quality of this design. By using Sspice, the voltage of node 2, say V2, can be obtained as shown in Equation 5.3 with V, = 1. 302* G6 at G4 V2: —sC2*sCl*G4-sC2*G4*G1—GS*G3*G2° Figure 5.2 shows its frequency response. Sspice can identify that V2 is a bandpass filter function and provides its Ho and 80 Figure 5.1. Tow-Thomas Active Filter V2 of Tow-Thomas active filter 10 u 1 r Without ESR--— W1 ' SR of 119 ohm 4*- _2 I j 1 900 950 1000 1050 1100 Frequency Figure 5.2. Bandpass filter function of V2. I 81 Do. They are G5*G3*G2 CZ*CI*G4 Q _\/Cl*G5*G3*G2 °" Gl*\/02*G4 ' Also, by the use of 83:25 , one can find how resistor R3 affects the function of V2. W, = , and (5.4) (5.5) Sspice can give the following equation, G5*G3*GZ —sC2*sCl*G4—sC2*G4*G1—G5*G3*Gg (5'6) V2 _ Sea — which shows that R3 will affect V2 more at low frequencies than at very high fre- quencies. Figure 5.3 shows the plot. v v v SHIVZJZJI *- V db -IO ‘ 4* ‘ ‘ ‘ ‘ t—‘J- . A 4~ ‘ - - - A 100 1000 10000 Frequency Figure 5.3. Sensitivity of V2 with respect to R3. According to Equation 5.6, a designer can suppress SE3 by increasing the value of G4. On the other hand, Equations 5.4 and 5.5 show that Cl and C2 can affect the W, and Q, of the filter function V2. f 82 An interesting problem is how the imperfections of the capacitors affect the filter function. Ideally, the admittance of a capacitor has a phase angle of 90 degree. However, in reality, a capacitor may have a dissipation factor other than 0, which is usually modeled as a series resistor. We can utilize the sensitivity analysis capability of Sspice to study how dissipation factors affect the circuit. Suppose the capacitors of Figure 5.1 are mylar capacitors, the ESR would be around 119 52, which represents a dissipation factor of 0.0075. The following table shows the dissipation factors of different capacitors. DISSIPA’I‘ION FACTOR MYLAR 0.0075 CERAMIC(NPO) 0.0002 TANTALUM 0.04 Figure 5.2 shows the nonideal effect to the bandpass filter function of V2. The following is an Sspice input file for the Tow-Thomas active filter. Rs] and R52 are the series resistors of the nonideal capacitor C1 and C2, respectively. Tow-Thomas Active Filter vs 7 0 AC '1 R1 1 2 806K R2 2 3 4K R3 4 5 7.96K R4 5 6 1K R5 1 6 7.96K R6 1 7 100K C1 19 2 0.010 C2 20 4 0.010 . XOA1 0 1 2 IDEAL OP-AMP XOA2 0 3 4 IDEAL OP-AMP XOA3 0 5 6 IDEAL OP-AMP R82 3 20 1 R81 1 19 1 .END 83 Then, Sspice can give the expressions for W,, Q, and their sensitivities with respect to 681 and G82. The following are the Sspice printouts and their plots. With this printout, symbolic solutions can be obtained. Numerator of: No**2=TRM(DEN(V2),0)/TRM(DEN(V2),2) + GSZ*GSI*GS*GB*GZ Denominator of: Ho**2-TRM(DEN(V2),0)/TRM(DEN(V2),2) + GS2*GSI*G4*C2*C1 + GS2*G4*61*C2*C1 + GS*G3*G2*C2*C1 *tt***#***************t****##*********** Numerator of: SEN(No**2,GSl) + GS2*G4*GI + G5*G3*G2 Denominator of: SEN(No**2,GSl) + GS2*GSl*G4 + GSZ*G4*GI + GS*GS*G2 *##1##*********************************1H! Numerator of: Qo**2 + GS2*GS2*GSl*GS1*GS*G4*G3*G2*C2*C1 + GSZ*GS2*GS1*GS*G4*GB*G2*G1*C2*C1 + GS2*GS1*GS*GS*GS*GS*G2*G2*C2*C1 Denominator of: Oo**2 GS2*GS2*681*GS1*G4*G4*Gl*G1*C2*C2 2*GS2*GS2*GS1*G5*G4*63*G2*G1*C2*Cl GS2*GS2*GS*GS*G3*GB*G2*G2*C1*Cl 2*GS2*GS1*GS1*GS*G4*63*G2*GI*C2*C2 2*GS2*GS1*GS*GS*GS*G3*G2*GZ*C2*C1 + + -+ 4- + 84 + GS1*GS1*GS*GS*GB*G3*G2*G2*C2*C2 **************************************** Numerator of: SEN(Qo**2,GSl) + 2*GSZ*GSZ*GSZ*GSI*GS1*GS*G4*G4*G3*GZ*G1*C2*C1 - GSZ*GS2*GS2*GS1*GSl*G4*G4*G4*G1*Gl*G1*C2*C2 + 2*GS2*GS2*GSZ*GS1*GS*GS*G4*G3*G3*G2*G2*C1*C1 (Total 9 terms ) Denominator of: SEN(Qo**2,GSl) + GS2*GS2*GS2*GS1*GSl*GSl*G4*G4*G4*Gl*Gl*C2*C2 + 2*GSZ*GS2*GS2*GSI*GS1*GS*G4*G4*G3*G2*G1*C2*C1 + GS2*GS2*GS2*GS1*GSI*G4*G4*G4*G1*G1*G1*C2*C2 (Total 15 terms ) The characteristics of Tow-Thomas filter with respect to the ESR, therefore, can be illustrated in Figure 5.4, Figure 5.5, Figure 5.6, and Figure 5.7. These circuit analysis capabilities are not available with any other numerical SPICE like programs. Another active filter of the same class is the State Variable Active Filter, which is shown in Figure 5.8[4]. With V,,,=1, Sspice can identify that V6 is a bandpass filter which is very similar to V2 of the Tow-Thomas active filter in Figure 5.1. In the same way, we can study the Q0 and W0 of the filter and their sensitivities Bandpass Freq. of V2 SEN(W0,GSl) 85 Tow-Thomas Active Filter 1000.2 - .---"q - ---"w - - - -q - -1--"- 632-0 . 01 -— 1000 - 999.8 999.6 999.4‘ 999.2 l 999 998.8 998.6 998.4 998.2 - ---“1 - --IIMI - ----ul - I- - - 0.01 0.1 1 10 100 csle cs2-10 ..— csz-loo -+--. Figure 5.4. Wo of Tow-Thomas Filter. Tow-Thomas Active Filter T Tj—vvvvq v vvv‘ v 'Vvv'v‘ v v vvvvv GSZ-0.01 -—- GSZ-O.1 "" 0.01 0.001 552.1..” 652-10 '0— ’ 682-100 - 0.0001 l 1e-05 { E 18-06 { 18-07 { 1e-08 e “ - -- A --1_“- - - -u“ 0.01 0.1 1 10 100 Figure 5.5. Sensitivity of Wo of Tow-Thomas Filter. 86 Tow-Thomas Active Filter 52 - - hm--. - ---"-.. - ”m" 682810 *— GSZ-lOO *" " 0 o q 36 !- .. 34 ' 1 32 ' ‘ 30 A A A AAAl A A A AAAAAl A A A AAA A1 A A A AAA 0.01 0.1 1 10 100 681 Figure 5.6. Q0 of Tow-Thomas Filter. Tow-Thomas Active Filter 0025 v ' “""' *fi ' """' ' 'i""" ' ' """ GSZ-0.01 -- GSZ=0.1 ---° csz=1 °°2 032-10 «— GSZ-lOO 'rr' 3 0.15 . <9 6 9 5 0.1 l U) 0.05 ~ 0 - u 1 A . 0.01 0.1 1 10 '100 Figure 5.7. Sensitivity of Q0 of Tow-Thomas Filter. 87 R5 ‘VV‘v 10k R5 C1 2o—va— C2 , R7 10k R I! } ‘ 1 .010 R2 1:01“ 10k 5 o . VIN R 15'9“ } 15.91: 7 } 0 4 _ 3 T > - :- 10 RL _ 750k - 0 4.9911 R 3 10k RH Figure 5.8. State Variable Active Filter when there exist nonideal capacitors. Figure 5.10 demonstrates the value of Q0. Computing the Q0 sensitivity with respect to GSl, which is the series resistor modeling the dissipation factor of C 1, is a tedious job. This will result in a complicated equation, as shown in the following. Numerator of: SEN(Qo**2,GS1) - 432*GSC2*GSC2*GSC2*GSC1*GSC1*G4*G4*G4*G4*G1*C2*C2 + 96*GSC2*GSC2*GSC2*GSC1*GSC1*G4*G4*G4*G4*G1*C2*C1 - 432*GSC2*GSC2*GSC2*GSC1*GSC1*G4*G4*G4*03*Gl*C2*02 (Total 37 terms ) Denominator of: SEN(Oo**2,GSl) + 144*GSC2*GSC2*GSC2*GSC1*GSC1*GSCl*G4*G4*G4*G4*CZ*C2 + 288*GSC2*GSC2*GSC2*GSC1*GSCI*GSC1*G4*G4*G4*G3*C2*C2 Bandpass Freq. of V6 Qo 1000 1000 1000 1000. 1000. 1000. 1000. 1000. 1000.69 0. .7 .7 .7 88 State Variable Active Filter GS = . ---- csz=11~-- 632-100 -*" 01 0.1 1 10 Figure 5.9. Wo of the State Variable Active Filter. 52 50 4B 46 44 42 40 38 36 34 32 30 State variable Active Filter v v V'Vffif v v v VV"" v vvvvvv' v v v v GSZ-0.01'-—- Gsz=10 .._ , 1 100' --------- G- S'ZEQJL:::;_ """" 032-1 , ’ Gsz=10 ..— / Gsz=1oo -.-. . 01 0.1 1 10 100 Figure 5.10. Q0 of the State Variable Active Filter. 89 + 144*GSC2*GSC2*GSC2*GSC1*GSC1*GSC1*G4*G4*G3*GS*C2*C2 (Total 61 terms ) It is very hard to understand a complicated equation like the one above. With 1% approximation, Sspice can simplify the equation into a much simpler one, which is shown below. Numerator of: OSN(Oo**2,GSl) + 288*G4*G3*01*C1 + 96*03*03*01*C1 Denominator of: OSN(Qo**2,GSl) + 288*GSC1*G4*G4*C2 + 144*GSCI*G4*G3*C2 Figure 5.11 shows that with 1% approximation, the sensitivity equation can be simplified with little sacrifice to the accuracy. We may find that the ESR of C2 is very insensitive to the sensitivity equation of Q0. Also, we can improve the Q0 sensitivity with respect to the ESR of C1 _by increasing C2 and decreasing C 1. With all the information provided above, we can conclude that, basically, the Tow- Thomas filter in Figure 5.1 is as good as the state variable active filter in Figure 5.8 in terms of its Qo sensitivity with respect to the nonideal capacitor. Example 12 Figure 5.8 shows the schematic of the State Variable active filter, where the transfer function at node 6 is a bandpass filter function. When R1 = R2, and R5 = R4; = R7 always hold, this can be realized by a Programmable State Variable active filter chip set. The bandpass frequency is about 1000 Hz; and the Q0 is about 50. Suppose CIis a mylar capacitor which has the dissipation factor of 0.0075, this SEN(QO,GSl) 0.3 0.25 0.2 0.15 90 State Variable Active Filter #7 v v v v v v v—vv' v vvvvvvj v GSZ-0.01 -- GSZ-O.1 ----. GSZ=1~~n GSZ-lO *— GSZleO -r--- 10% Approx. 4*- 10 100 Figure 5.11.. Sensitivity analysis without approximation QSN(QO,GSl) 0.035 0.03 0.025 0.02 0.015 0.01 0.005 State Variable Active Filter v vvvvvv " w v v vvvvv' v V‘v’vvfi-v‘ v v v vvvvv GSZ-0.01 - 100 -- 10 100 Figure 5.12. Sensitivity analysis with approximation 91 would produce deviations in Q0 which are shown in Figure 5.13. This dissipation factor can be modeled by putting a series resistor of 11.9 (I with C]. Is there any way that we can improve this Qo error by changing the values of other components without aflecting the original design specifications while still using a mylar capacitor for C1 1’ V6 of State Variable active filter 18 . . Without ESR--— Wit- :SR of 119 ohm 4*- 900 950 1000 1050 1100 Frequency Figure 5.13. Bandpass filter function of V6 in Svaf Answer: Usually, what a circuit designer can do is to use the design formulas for the ideal case to find an alternative design for the same specifications, then plug in the nonideal capacitor model to do the simulation. Every time the designer fails to pass the function verification, he really doesn’t know how to make the next move, because it is too complicated. By solving Qo sensitivity symbolically with 1% approximation, we find that 8% _ (288*G4+96*G3)*G3*G1*Cl GS“ (288.G4+144.03).04.051.02.;2' (5.7) 92 Because G3 >> G4,for R3 = 4.49K, and R4 = 750K, and Q _ G3 x «:1 ° 3 x 6'4 x «02’ W G1 ° J01 x 02’ G51 1““ - m then, 83;, = 9 x D.F. x 0,, (5.8) where D.F. is the dissipation factor of C1. Therefore, there is no way that a circuit designer can accomplish the task stated in Example 12. C] CHAPTER 6 SYMBOLIC STABILITY ANALYSIS The stability of an analog circuit is one of the most important considerations for the circuit designers. Usually, the verification by using a numerical circuit simulator doesn’t provide enough information about the sources of instability. This leaves a great opportunity for the symbolic approach. A Since the symbolic circuit analyzer provides the transfer functions of a linear circuit in 8 domain, the stability of this circuit can be examined by doing the Hurwitz Test to the denominator of its transfer functions. 6.1 Hurwitz Test Fundamentals It is well known that the denominator of the transfer functions of a stable system shouldn’t have any zeros in the left half-plane and the zeros at the j-axis should be simple. The test for this property is known as a Hurwitz test, and the denominator is referred to as a Hurwitz polynomial. Before going into the details of this procedure, some of the important properties of Hurwitz polynomials are discussed. 93 94 Let the polynomial be written Q(s) = ao + als + 0232 + - - ' + ans” ‘ (6.1) with the even and odd parts m(s) = 00+ (1282 + ~- - + ans" n(s) = als + a;.,s3 + - - - + a,,.ls"‘l (6.2) for n even, and with the last terms interchanged if the degree n is odd. Q(s) is not a Hurwitz polynomial unless all coefficients are positive and no intermediate terms are missing. The only exception is the degenerate case in which the polynomial is an even or an odd function of s. Hurwitz polynomial can result only from the product of the following three kinds of factors (3 + a) for a real and positive, (32 + b2) for b real, (6.3) (s2 + 2as + a2 + b2) for a and b as above. Let m(s) n(5)° The zeros of the polynomials, m(s) and n(s), are all simple and are restricted to line 91(3) = (5-4) on the j-axis where they occur in conjugate pairs and alternate with each other. Thus n(s), being odd, contains 3 as a factor and hence is zero at s = 0. The next largest pair of zeros in absolute value belong to the polynomial m(s), the next largest are a pair of j-axis zeros contained in n(s), and so forth. This situation is the alternation property of the zeros of m and n along the j—axis. Such a function, 111(3), is the 95 driving-point impedance or admittance of a lossless network - one containing only inductors and capacitors [26]. Suppose w(s) is an impedance function and the order of the numerator is one degree higher than the denominator, then, 11/(3) = 7M3) - 018 (6-5) would still be a realizable LC driving-point impedance function. Similarly, I m — 023 (6.6) ¢Il(s) = would become a realizable LC driving-point admittance function. The pattern of the test is thus established. If continued in the same manner. it leads to a continued-fraction expansion of the rational function 211(3) of the form $09) = 018 + I (67) (123 + 1 033 + .+ 1 .+ (1,3 in which n is the degree of the original polynomial, and all coefficients a] - - - an must be positive if this polynomial is to have Hurwitz character. The discussion so far as this testing procedure is concerned has assumed that the given polynomial, Q(s), has no zeros on the j-axis. If it does, then the process of continued-fraction development will not continue for n terms but will terminate pre- maturely, and the j-axis factors will be placed in evidence at the point of termination. The reason for this behavior of the process is due to the fact that j-axis factors, as shown in set (6.4), have the form (32 + b”), which is an even function of s and hence if Q(s) = m(s) + n(s) contains such a factor then" it must separately be contained in both m(s) and n(s). In the rational function w(s) = gig-9)) such a common fac- 96 tor or factors cancels, and hence the continued division and inversion process would terminate sooner than it normally would. This process is similar to the procedure of obtaining the highest common factor of two given polynomials. Because the derivative of a Hurwitz polynomial is again a Hurwitz polynomial, it is shown [26] that (m+ H311) and (n+ dag) are Hurwitz polynomials when (m(s) +n(s)) is a Hurwitz polynomial. This yield a simple procedure for determining whether a given even polynomial has only simple j-axis zeros, for if it has only such zeros then its derivative likewise has only such simple zeros which alternate with those of the given polynomial. An even Hurwitz polynomial divided by its derivative must then be a ((2 function like Equation (6.7) and must yield a continued fraction with all positive coefficients. If this test fails, it may be concluded that the even polynomial does not have all simple j-axis zeros. The above discussions complete the mathematical development of Hurwitz test. 6.2 . Implementation of Hurwitz Test The implementation of Hurwitz test in Sspice follows the procedure described in section 6.1. The polynomial under test is verified to know whether the ratio of its even part and its odd part is a realizable RC admittance or impedance function. If the continued-fraction procedure is terminated prematurely, the common factor of the even and odd polynomials should be an even polynomial to continue the test. Otherwise, the polynomial under test is not a Hurwitz polynomial. Then, the ratio of the above common factor and its first derivative should be a realizable RC function, which is tested by the same continued-fraction procedure only once. The following is the algorithm. ALGORITHM : (Hurwitz Test) Hurwitz_t est (polynomial ) 97 { ‘ if( continued-fraction(polynomial,0)==Pass ) { return(Pass Hurwitz Test); } else { return(Fail Hurwitz Test); } continued-fraction(p,level) . /* p is the polynomial and level is an integer */ /* levels-1 represents there exist j-axis zeros */ /* level==0 when this algorithm was called by *l /* user’s command */ { p1=odd_polynomial(p); p2-even-polynomia1(p); if(p1->degreedegree) { P3'P1; Pi'pZ; P2'P3; } p38NULL; while( p2 is not a zero polynomial ) { A result-p1/p2; p3=result->remainder; p4-resu1t->quotient; if( p4 is a polynomial other than 8‘1 only and the coefficient 0f s‘l is positive and the coefficient of s‘O is 0 ) { return(Fail); } 01-92: P2'P3; } if( p1 is not an even polynomial) { return(Fail); else } { 98 if( p1 is larger than degree of 0 ) { else if(level=-1) { /* Polynomial has multiple zeros */ /'II at the j-axis */ return(Fail); } p2-d(p1)/ds; P4'P1*P23 if(continued-fraction(p4,1)==Pass) { return(Pass); } else { return(Fail); } } { return(Pass); } Example 13 Figure 5.8 is a State Variable Active Filter. If the op-amps are all - ideal, would this circuit always be stable when diflerent component values are assigned when R1 = R2, and R5 = R6 = R7? linsvnuu Applying the above algorithm, Sspice would give a report below. Hurwitz Test of DEN(V8) : The Following Rational Function Should Be >= 0 +2tc4tc1+2tcstc1 a ---------------- a +6*G4*G1 99 The Following Rational Function Should Be >8 0 +6*G4*C2 a ------- +8 +2+04+01+2+03+01 sssssssssst*ssssssssssssstsssssssssssssssssssss The Following Polynominal PASS the Hurwitz Test *******************************.**************** TERMS SORTED ACCORDING TO POWERS OF 8 s**2 terms: [0.000% error] +2 + sC2*sC1*G$ (99.34%) +2 + sC2*sC1*G4 (100.00%) s**1 terms: [0.000% error] +6 * sC2*G4*Gl (100.00%) s**0 terms: [0.000% error] +2 + 03+c1+01 (99.34%) +2 + G4*G1*G1 (100.00%) operation of HTZ(DEN(V8)) : ********>> Hurwitz Test Completed <<******** Therefore, the necessary conditions for a stable State Variable Active Filter are +2*G4*C1+2*63*C1 >’0 +6*G4*G1 “ ’ 100 +6*G4*C2 +2*G4*61+2*G3*Gi - This is alway true in Figure 5.8 when R; = R2, and R5 = R6 = R7. Therefore, this is a stable arrangement for a programmable State Variable Active Filter when ideal 'op-amps are used. [I] A circuit designer, thus, understands the stability of a circuit more in-depth so that he/ she can make the best decision. CHAPTER 7 IMPLEMENTATION OF SSPICE VERSION 2.0 7 .1 Matrix Reduction Method Nodal analysis is one of the most popular method for obtaining network functions. A circuit analyzer can layout the nodal equations in the form of I = Y x V. Therefore, the node voltages can be found by using Cramer’s rule which requires the values of two matrix determinants. One matrix is the admittance matrix Y; the other is Y with a column replaced by I for the corresponding node. Because, symbolic division is not preferred for expanded format, the matrix deter- minant is obtained by applying the following formula recursively : n-l det(Y) = X:(—1)"+1 x Gm x det(Ym), (7.1) i=1 where det(Ym) is the minor obtained by removing the first column and the i’th row 101 Cl 102 GZ G3 G4 Figure 7.1. Series resistor circuit. of Y; and Gm are the entries of the first column of Y. According to Equation (7.1), the computation complexity of obtaining matrix determinant depends not only on the dimension of the matrix but also the sparsity of the matrix. A matrix with less non-zero entries and less terms represents less computation and less cancellation while obtaining its determinant. This is because the additions and subtractions of a column or a row into another column or row within a matrix does not affect the determinant of the new matrix. If the application of these basic operations can make a matrix more sparse, then the computation complexity of find its determinant can be improved. The following is an example. Example 14 The admittance matrix of Figure 7.1 is [ G1 -01 o 0 Find the determinant of Y. —G1 G1 + G2 —G2 0 0 -02 G2 + G3 -03 0 0 —G3 G3 + G4 (7.2) 103 Adding the first column of Equation (7.2) into the second column results in I- '1 G1 0 0 0 —G1 G2 —G2 0 det(Y) = . (7.3) 0 —Gz 02 ‘1' G3 —G3 0 0 —G3 Ga + G, J Similarly, adding the first row of Equation (7.3) into its second row would produce G1 0 0 0 0 02 —Gz 0 det(Y) = . (7.4) O —G;» G: + G3 -Ga 0 0 -Gs Gs + G4 If we repetitively apply these rules to rest of the columns and rows, we may produce that _ . G1 0 0 0 0 G2 0 0 det(Y) = ' . (7.5) 0 0 G3 0 - 0 0 0 G4 ] The computing effort needed for Equation (7.5) is, thus, far easier than that of Equa- tion (7.2) when we apply Equation (7.1) for obtaining the determinant of Y. El Moreover, sparsity and the dimension of a matrix are not the only factors which affect the symbolic computation efficiency. In many cases, even though the application of the basic row or column operations cannot increase the number of zero entries in a matrix, the number of total terms may be decreased. This represents less cancellation during the computation. Also, if a column has only one non-zero entry, g;,,-, which is located at the i’th 104 row, then all the other entries in the i’th row can be set to zero. Similarly, if a row has only one non-zero entry, g,- ‘1', then all the other entries in the j’th column can be set to zero. This may further ease the searching process in Equation (7.1). This method has been found very effective for circuits with a dimension around 13 to 16. For example, the equivalent circuit of a chip bonding pad which has 14 components and whose dimension is 16, needs 77 seconds to produce its network determinant without the above matrix reduction algorithm using Sspice on a SPARC , 1 workstation. However, with the application of the reduction technique, Sspice takes only 7.7 seconds to Obtain the result. 7 .2 Obtaining Matrix Determinant Besides a good decomposition strategy and a matrix reduction method, an efficient algorithm for obtaining the determinant of an admittance matrix is equally important. This is especially true when there exists a tightly connected sub-circuit which is hard to be further decomposed. The determinant algorithm implemented in Sspice trades off between run time efficiency and memory consumption, which is very similar to the SLE/ M algorithm in [23]. The determinant of a matrix Y, idet( Y), can be calculated by the following formula n-l det(Y) = X:(-—l)i+l x Gm x det(Ym), (7.6) i=1 where det(Ym) is the minor Obtained by removing the first column and the i’th row of Y; and Gm are the entries of the first column of Y. The minors can be calculated recursively according to Equation (7.6). There are relationships between different minors; they may share the same sub-minors. Figure 7.2 shows the relations among the minors of the admittance matrix when calculating its determinant. 105 ~63 9 / Y(1,1)(3,2) J - \ 01+02+03 j‘ / Y(1.1)(2.2) Y(2, l)( l ,2) + ..... / -Gl-GZ j + Y(2,l)(3,2) l e \ ~63 Figure 7.2. Relations between minors. 106 There are different levels of minors. We define det(Y) itself to be the 0-level minor. Y(.- '1') shown in Figure 7.2 represents a matrix with the i’th row and j’th column of Y eliminated and is called a 1-level minor. Using a similar definition, Y(,-,,-),(,,,) represents a matrix with i and p’th row and j and q’th column eliminated and is referred to as a 2—level minor. For a matrix of dimension n, Sspice finds all the minors needed from 0-level to (n-1)-level, and establishes the relations among different minors. It also identifies the many minors that are actually the same. For example, Y(,-,_,-),(,,,) and Y(, 01.0.9) are the same 2-level minors. Finally, Sspice calculates the minors from the (n-I)-level down to 0-level. The value of the (n-1)-level minors can be obtained from the entries of the n’th column of Y directly. Whenever Sspice completes the calculation of all the i-level minors, it releases the memory spaces occupied by the value of (i+I)-level. Because the symbolic values of the minors always consume a large amount of memory space, this strategy makes it possible to handle more symbols. It is also found that both the numerator and the denominator of a transfer func- tion may share the same sub-minors. Saving the values calculated for those minors may preserve computation efficiency. However, we find that, usually, the computation of the numerator needs much less time than that of the denominator. For example, the bandpass filter of the benchmark circuits in [27] takes 33 seconds with Sspice version 2.0 on a SPARC-l station for the denominator and only 1.5 seconds for the numerator. Unlike the symbolic program described in [5], Sspice does not save the cal- culated minors with the exception of the 0-level ones, in order to save memory space. Internally, Sspice calculates the denominator first, because the transfer functions at different nodes have the same denominator. It only needs to obtain the numerator when a specific transfer function is needed. 107 7 .3 Implementation of Sspice Sspice version 2.0 accepts the user’s command interactively. Figure 7.3 shows the flow chart of Sspice. In this section, the advantage of using the decomposition approach is illustrated through the example of uA741 op-amp. The default mode for Sspice version 2.0 is computation without decomposition. It checks the validity of the input files, aborting when the input circuit consists of loops of voltage sources, of nodes connected to branches which are all current sources. and so on. Then, it generates the nullator-norator equivalent circuit and the nodal equations for the full circuit. For transistors, a corresponding model as defined in the input SPICE file is substituted in automatically. When the decomposition procedure is issued by the user, the admittance matrices for the sub-circuits will be constructed. One important mission for the circuit analyzer is to prepare critical information a circuit designer needs. Sspice has a well designed equation manipulator. It receives an equation from the user as a command, checks the syntax of this equation, puts the valid equation into a buffer and asks for the next equation. After the user gives all the functions, the equation manipulator begins to calculate the symbolic answers - for all the equations together. Because the symbolic answers always take longer to obtain than the numerical ones, users may want to key in all the commands one at a time and let the computer run. If the user wants to get the current flow through the resistor R1, and R1 is between node 3 and node 4, he/ she can key in "(V3-V4) #01", where G181/R1, to get the answer. Also, he/she can type in "SEN(V3-V4,G1) " to do the sensitivity analysis of the voltage across R1 with respect to itself. Users can also ask Sspice to plug in the numeric values of a set of components before the determinant computation is executed so that memory consumption and computation efficiency can be improved further. This produces partial symbolic solutions. 108 SPICE File Input Card Checking - l Nullator-Norator | Equivalent Circuit User's Command 1 Construct Nodal - Equations User’s Command Manipulator Build in Applications Network Determinant +’.,‘./ Solver Filter Identification , Non-ideal Op-am Error Analysns p ‘ Sensitivity Analysis , | "men?“ I Approxxmator l Outputs Figure 7.3. Flow Chart of Sspice. 109 For most situations of a medium size circuit, the symbolic solution can be overly long and circuit designers can find this hard to work with. Sspice can evaluate the numeric values for each term and throw away the insignificant terms. Usually, poly- nomials with hundreds of terms are dominated by only a few. Therefore, Sspice can do approximations for each coefficient of 3 according to a threshold value given by the user. The program can identify the most significant terms of an order of s, then eliminate those terms whose numerical values are smaller than the threshold value. By this method, the output of Sspice becomes more interpretable. Also, the errors due to this approximation are reported in the output. Example 15 Figure 7.4 shows the SPICE file of a 741 chip without compensation. The open loop gain is shown in Figure 7.5. This op-amp is unstable for closed loop gains less than 40db. How could we compensate this op-amp so that it becomes stable for all resistive feedback? Answer: By using Sspice, users can substitute in the high frequency transistor model [25] with a substrate capacitor. All the components are replaced by their numeric values except 016, 017, 023B, and R8. The Laplace variable 3 is left as a _ symbol. Also, this circuit are decomposed at three nodes so that the computation efficiency is improved. The cut set are node number 9, 16, and ground. Sspice, thus, produces a circuit function of 8, G8, and the high frequency model parameters Of 0238, 017, and 016 as shown in Figure 7.6. According to the Sspice output in Figure 7.6, the location of the first pole can be formulated to be 1 1.5798 x 10‘5 x 09117 x GPI16 + 1.1469 x 10"12 Zr x CPI238( 01117 x GM16 ~ 08 2.1732 x 10-10 x GP116 1.6858 x 10-12 3.1943 x 10'10 x GPI16 GM16 x G8 + 01117 - ' 01117 x GM16 ). 110 7415 OPERATIOIRL AMPLIIIR 80.61.6012 '.SUICRI 017411 4 5 1 13 25 0 Vi+ Vi- Vp+ Vp- Vout Vin 100 0 AC 1 Vet: 100 4 3270 vmsoo 131100015 'In 13 0 DC -15 031 2 4 6 13 M1 0.2 2 5 7 13 M1 083 8 3 6 13 M2 084 9 3 7 13 M2 OHS 8 10 11 13 M1 086 9 10 12 13 M1 037 1 8 10 13 M1 088 2 2 1 13 M2 039 3 2 1 13 M2 OHIO 3 15 14 13 M1 0811 15 15 13 13 M1 0312 16 16 1 13 M2 0313A 21 16 1 13 M2 .25 03133 17 16 1 13 M2 .75 Ofl14 1 21 24 13 M1 3 0315 21 24 25 13 M1 QH16 1 9 18 13 M1 OB17 17 18 19 13 M1 0.18 21 22 23 13 M1 Il19 21 21 22 13 M1 0&20 13 23 26 13 M2 3 0821 20 26 25 13 M2 Ofl22 9 20 13 13 M1 08233 13 17 23 13 M2 0fl233 13 17 9 13 M2 0824 20 20 13 13 M2 R1 11 13 1X R2 12 13 1X R3 10 13 SOK R4 14 13 SK R5 16 15 39K R6 24 25 27 R7 25 26 22 R8 19 13 100 R9 18 13 50K R10'22 23 40K R11 20 13 50K .MODEL M1 NPN (BF-200 18-13-14 VIP-125 VJ$-.75 + RB-185 30-15 CJE-.65P CJc-.36P TF-1.15N TRP4OSN CJSI3.2P MJ5-.Sl .MODBL M2 LPN? (BF-50 '15-18-14 VAP-SO VJSO.75 + RB-SOO 30-150 CJB-.1P CJC-1.0SP TP-27.4N TR-254ON CJ5-5.1P * MJs-.5) .0? .AC DEC 100 1 IOOMEG .PROBI .END Figure 7.4. The SPICE file of 741 chip without compensation. lll uA741 op-amp 120 --. -., --. --, . -, 1-, .fi q Without CC -*-J 100 P With CC-30p *—- 80 - 60 1 =8 40 - 20 ~ 0 -20 . -40 4.1 1.1 .~.1 1.1 L11 444 .11 1 10 100 1000 100001000001e+061e+07 Frequency uA741 op-amp 200 "I "l "1 Vi: vv. 'v' -7, Without CC *— 150 ’ With cc-3op * 100 - 50 - . degree b _200 .14 -.1 .11 .11 .-1 ..1 4.1 1 10 100 1000 100001000001e+061e+07 Frequency Figure 7.5. Frequency response of uA741 op-amp for gain and phase. 11j2 This op-amp can be made stable by decreasing the value of the first pole so that a reasonable phase margin is obtained at the frequency where the gain of the amplifier is unity. According to the above equation, the value of the first pole can be decreased by increasing the value of CPI233. This is done by adding a capacitor between the emitter and base of 023B. A 30pF. capacitor, CC, between node 17 and 9, therefore, compensates this op-amp with a phase margin about 80 degree. The function of a compensated 741 chip is also shown in Figure 7.5. D lulnrator 01: V25 +5.581520-246 1 .1122 +0.920526-235 1 .1121 +2.61725..2§4 1 .1126 +1.657050-214 1 .1119 +5.886450-205 1 31116 +9.60216o-196 1 .1117 +3.2ssvoo-2oz 1 .1116 +4.1a7zae-176 1 .1115 +1.1osose-169 1 .1114 +9.746660-162 1 .1113 -3.77414.-153 1 .1112 -1.67351.-1¢4 1 11111 -3.247636-136 1 s1110 -3.37697o—120 1 .119 -9.16272¢-121 1 .116 +2.625650-112 1 .117 +4 286020-104 1 .116 -7.021280-101 1 .115 +1.508330-88 1 3114 +4.370126-61 1 :11: +7 91454. -74 1 3112 +8.40643o-67 1 .111 +3.821700-60 1 .110 ° . ......ttttfittttitttfifitittttt..tQOOOOQOOO Dona-inator of: V25 TIRMS SORTED ACCORDING TO POIERS OF I I1'22 terns: [0.0001 error) +0.4749150—233 1 ICC1I1I1I1I1I1n1311131I1I1I1I1I1I1I1I1I1I1I10 (97.33t) 00.3904200-245 1 I1I1I1I1I1I1I1I1I1I1I1I1I1I1I1I1I1I1I1I1I1I (100.00.) I111 tor-I: [0.0001 error) +2.644150°56 ‘ ICC +1.105080-69 ' I £138,381) I110 torus: [0.0001 error] 01.636400-65 1 1 (100 00$) IUHERICAL VALUE OF ABOVE SYMBOLIC RESULT +1.463790-244 1 I1122 42.153240-233 1 I1121 +5.354560-223 1 11 + 1 11 +2.113310-203 1 01118 +4.140790-194 1 I111? +4.519690-105 1 :111: +::211;:::122 1 :11i: 91.476090-167 1 01114 15.106900-159 1 I1113 +1.33037o-150 1 01112 42.660990-142 1 31111 +4.11177o-134 1 I1110 +4.09797o-126 1 I119 14.455610-110 1 I110 13.020220-110 1 I117 +1 405230-102 1 I116 15.227350-05 1 I115 +1.261010-I7 1 I114 +2.00050o-00 1 3113 +1 000720; 73 1 I112 07.043500-‘7 1 I111 91.636400-05 1 I110 . Figure 7.6. Sspice output of open loop transfer function of 741 without compensation. 113 Without decomposition, a SPARC-2 workstation need 1 hour to finish the job. However, with the application of decomposition at node 9, 16, and the ground for the above example, Sspice version 2.0 accomplished the task within 4 minutes. Usually, circuit designers use trial-and-error to find the answer they need. This may require several runs of a symbolic simulator. This example demonstrates the importance of the composition and decomposition strategy. 7 .4 Second Order Filter Function Identification One of the most important circuit applications is signal processing. Analog filters play an important role for both analog and digital signal processings. In many cases, the characteristics of the analog filters determine the performance of the whole system. Therefore, analog filter function analysis is the first step toward a successful design. The primary function of a filter is to pass or to stop a band of frequencies between the input and output. Figure 7.7 shows the behavior of the magnitude of the ideal filter functions versus frequency. In each of these responses, there are pass bands and stop bands as the name of the filter indicated. The filters of Figure 7.7 represent the most desired response. Because circuits respond to a frequency with finite slopes, it is impossible to synthesize a circuit which has the ideal behavior. Circuit designer have to tradeofi among cost, performance, and other factors with an appropriate approx- imation. Second order approximation is one of the most commonly used techniques. Also, second order filter functions are the basic building blocks of many higher order filters. It would be valuable to circuit designers to have a tool to do in-depth analysis of second filter functions. 114 H ‘HTLPl lTarl LP‘—"| Heel 0 v >f 0- n :f fo f0- 1 T (0) (1:) ”mm. 11le H 111.51 ° 1. 7‘ 0 - :1 OJ f f0 . f1 00 (0) Figure 7.7. (a) Low Pass. (b) High Pass. (0) Band Pass. (d) Band Stop. (e) All Pass filter functions. The second order transfer function of a low pass filter is 2 H leo TLp(3) = . (7.7) .2 + (398 + w? The second order transfer function of a high pass filter is H 52 THp(3) = 1.5:,” . (7.8) s“ + (—)s + «23 The second order transfer function of a band pass filter is H5451 s TBP(3) = ° (7.9) 32+ 3’- 3+0)? (62.) . l 15 The second order transfer function of a band stop filter is Hb,(82 +1.03) TBs(8) = . (7.10) .2 + (311s + on: Q0 The second order transfer function of a all pass filter is H.132 — (9113 + «231 TAP(3) = o ' (7-11) .2 + (21:). +14? Sspice has the capability of generating detailed symbolic equations for second filter functions like Ha, and too. Also, these equations can be obtained with the special function command as described in section 7.6. 7 .5 In-Band Error Approximation Designing a filter circuit is usually done by specifying the filter parameters and then selecting a specific topological realization with resistor and capacitor values to meet these specifications. Circuit designers always consider the components are ideal so that the frame work of the design can be analyzed with much simplification. However, in building an active filter circuit with real components, there are deviations from the design parameters. One of the major contributors to errors is the nonideal effects of an op-amp. At very low frequencies, the open loop gain of an op-amp is approximated to be infinitely large. This is no longer true for frequencies larger than 50 kHz. Thus, the op-amp can be approximated by a single pole expression as follows : Aowo A: , s+wo (7.12) 116 where A, is the dc gain and Aofo, or 1.420%4, is the gain-bandwidth-product(GBP). For a TL084 quad op-amp, A0 = 200k and f0 = 22.2Hz. By plugging in the one pole model, Sspice can calculate the Q0 and W0 errors due to this dominant pole. The following is an example. Example 16 The following is a State Variable Active Filter using TL084 op-amps. State Variable Active Filter VIN 1 0 AC 1 R5 1 2 10K R5 2 4 10K R3 3 0 4.99K R4 3 6 750K R5 2 8 10K XNDA 3 2 4 TL084 R1 4 5 159K Cl 5 6 0.001U XNOA 0 5 6 TL084 R1 6 7 159K C2 7 8 0.0010 XNOA O 7 8 TL084 RL 8 9 10K RL 9 4 10K .END What is the Q0 and fo errors of this filter in comparison with the same design using ideal op-amps. Answer: Sspice would generate a report in the following. State Variable Active Filter ************* *00andfo11 ************* 117 0o is: 80RT{( + C1)*( + 4*G4*G4 + 8*G4*G3 + 4*G3*G3)} Z’I'Qllill'lEQJIQQQE’IZ; """"""""" = 50.4337 (2*PI*fo)**2 is: ( + 61*61) 7125.57 fo = 1000.97 Hz a##0##*********************¢****** * D00/00 = (D2-D0)foQo - Dfo/fo * t**********#********************** D2-DO: where kfi} . 1/GBP{i} The numerator is: +k TIMES + 8*G4*G4 + 28*G4*G3 + 20*03*G3 The denominator is: + 4*G4*G4 + 8*G4*G3 + 4*63*03 ***************************** * Dfo/fo 8 (D2-Dl)fo/(200) * ***************************** D2-D1 : where k{i} = 1/GBP{i} 118 The numerator is: +k TIMES + 44*C2*G4*G4 + 40*C2*G4*63 - 4*C2*G3*GS - 4*C1*G4*G4 - 8*C1*G4*03 - 4*CI*G3*63 The denominator is: ( + G41C2)*( + 12104 + 12103) ***************************** * NUMERICAL EVALUATION * ***************************** Dfo/fo 8 -0.000218473 D00/Qo 8 0.0573579 Therefore, both symbolic and numeric expressions of the Q0 and to errors are ob- tained. This is verified by using Pspice as shown in Figure 7.8. Both Sspice and Pspice outputs show that the errors due to the dominant pole are small. 7 .6 Special Functions Sspice has a built in equation editor to manipulate the answers for the users. For example, V(1,2) is interpreted as V1-V2. Right now, more functions have been implemented in Sspice, and many of them can be ~used as a part of the sensitivity analysis features. The followings are their brief descriptions. 119 State Variable Active Filter de(6) Date/Time run: 06/21/92 14:38:15 Temperature: 27.0 r' """""""""""""""""""""""""""""""""""" 1 34 - i ; Non-ideal Op-amp 33 a: 32 -: 1 Ideal Op-amp : 31 -: 30 , E 1.00000000Kh o 1 vdb(6) Frequency Figure 7.8. Pspice simulation of State Variable Active Filter using ideal and nonideal op-amps. 120 SEN (arg1,arg2) Perform sensitivity analysis of arg1 with respect to arg2 by using Sensitivity Algebra. Usually, arg1 is an expression, and arg2 is an element. 05N(arg1,arg2) Perform quick sensitivity analysis of arg1 with respect to arg2 by using Quick sensitivity algorithm which will be described in Section III. DIF(arg1,arg2) Perform the first derivative of arg1 with respect to arg2. TRMCarg1,arg2) Extract the coefficient of 3’s arg2’th order terms of argl’s numer- ator. NUM(arg) Extract the numerator of arg. DEN(arg) Extract the denominator of arg SMY(arg) Perform numerical approximation and numerator-denominator common factor elimination. HTZ(arg) Perform Hurwitz Test to the polynomial arg. 002(arg) Extract the square of the quality factor of a second order filter function, arg. 1402 (arg) Extract the square of the center frequency of a second order filter function, arg. 202(arg) Extract the square of the bandstop frequency of a second order filter func- tion, arg. Example 17 The sensitivity of V6 with respect to C] can be obtained by command- ing SEN(V6,C1). If numerical approximation is specified, the 05N(V6,C1) command can further improve the computation efficiency. SEN(002(V6) ,C1)/ 2 would give Q sensitivity with respect to C1 . 121 Example 18 The stability analysis of V6 can be done by doing Hurwitz Test to the denominator of V6. This is achieved by using HTZ(DEN(V6)). CHAPTER 8 CONCLUSIONS In this dissertation, the development and the applications of a symbolic analog circuit analyzer are presented. It has been understood that the use of symbolic circuit analyzer is not a one time solution. A circuit designer has to do trial and error many times in order to obtain the solutions he/ she needs. This requires extensive experience of using symbolic tools and in-depth understandings of the circuits. Adapting a symbolic circuit analyzer into the design platform with an appropriate education certainly would improve both of the above factors. On the other hand, a symbolic circuit analyzer should be made as flexible as possible so that circuit designers can fully utilize their imagination and knowledge without restriction. Sometimes, this may produce confusion among different interpretations of the results. Users have to understand the meanings of the results precisely so that the possibility of getting a faulty conclusion can be minimized. Besides efficiency, therefore, flexibility and interpretability are also the major concerns while developing Sspice version 2.0. In Chapter 3, a new strategy for circuit composition and decomposition approach was presented. Before, decomposition strategies based on graph algorithms didn’t provide a unified method to obtain the network determinant of a whole circuit from the decomposed subcircuits for both passive and active circuits. The presented new strategy alleviats this difficulty. Also, this strategy improves both the computation 122 ' 123 efficiency and memory consumption. It is hard to develop an unified method to find an optimum out set for all the possible circuits. However, the analysis provided in' Section 3.3.1 gives the hints of the possible solutions. The follow-up theorems in Section 3.4 shows that there are special cases that can be taken advantage of to further improve the efficiency. Section 3.5 shows an example which reduces a 20 case decomposition approach into only 2 cases. In Chapter 4, the approximation techniques implemented in Sspice are presented. For small circuits of less than 20 components, numerical approximation after com- putation technique usually is good enough. However, for larger circuits, numerical approximation during computation and before computation techniques are needed. Example 15 shows the combination of decomposition and approximation before com- putation to solve a well known problem. The symbolic sensitivity analysis and symbolic stability analysis in Chapter 5 and Chapter 6 explore new applications by providing suitable software tools. The examples in these chapters show that symbolic approach provides a better solution ' in comparison with the numerical approach. Chapter 7 explains implementation of Sspice version 2.0 including the matrix re- duction strategy. Sspice version 2.0 is a symbolic circuit analyzer, which is compatible with version 1.0, with extensive capabilities. It is no longer a pure symbolic circuit analyzer. Its internal data structures are now capable of handling both numeric and symbolic information. This provides more flexibility and efficiency for solving cir- cuit problems. Sspice version 2.0 has been tested and applied to the development of macromodels of power supply regulators [28]. The future of the symbolic approach depends on the integration of the symbolic analyzer into the existing numerical based design process and system. Then, circuit designers would have more opportunities for accessing symbolic analysis tools and get better educated in using them appropriately. By applying symbolic approach into a 124 design project, a circuit designer would find more needs and new applications of symbolic analysis. The needs for symbolic sensitivity analysis and symbolic Hurwitz test, for example, were discovered by circuit designers on their jobs. Symbolic analog circuit analysis is now basically applied to the nodal analysis platform. It is for linear circuits. There are other research opportunities which may be suitable for symbolic approaches for nonlinear circuits. Translinear analysis could be the next frontier for symbolic analog circuit analysis. BIBLIOGRAPHY BIBLIOGRAPHY [1] M. Ismail and S. Bibyk, “Cad latches onto new technieques for analog ics,” IEEE Circuits and Devices Magazine, pp. 11 - 17, Sept. 1991. [2] P. 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