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01413 7859

This is to certify that the
thesis entitled
FORCE CCWWUTATFD DIr ECT AC- DC CCI‘ VERTER
WITH CCNTRCL CF II‘PUT PCNER FACTCR

presented by
John Gemmell

has been accepted towards fulfillment I
of the requirements for

Masters , Electrical Engineering
degree in

Elias Strangas

 

 

Major professor

Date 7/29/96

0-7639 MS U is an Afﬁrmative Action/Equal Opportunity Institution

 

LIBRARY
MiChiQan State
University

 

 

 

PLACE IN RETURN BOX to remove thb chookout from your record.
TO AVOID FINES rotum on or bdoro date duo.

DATE DUE DATE DUE DATE DUE

 

 

 

 

3‘80. 11‘
:b-WT‘ u

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSU Is An Afﬁrmative ActionlEqual Oppormtty Institution
W1

FORCE COMMUTATED DIRECT AC-DC CONVERTER
WITH CONTROL OF INPUT POWER FACTOR

By

John Gemmell

A THESIS
Submitted to
Michigan State University
in partial fulﬁllment of the requirements
for the degree of

MASTER OF SCIENCE

Department of Electrical Engineering

1996

ABSTRACT

FORCE COMMUTATED DIRECT AC-DC CONVERTER
WITH CONTROL OF INPUT POWER FACTOR

By

John Gemmell

Various methods of implementing a force commutated direct AC-DC converter are
reviewed. A new commutation algorithm for the AC-DC converter is derived and a
suitable circuit topology chosen for implementation of a prototype converter. The results
of simulations of the prototype design are presented with emphasis on regenerative
capabilities of the converter. A physical converter was constructed and results of testing
are presented. Operation of the physical converter is compared and contrasted with the
results of simulation and theoretical expectations. Conclusions and the possible

application of the converter are discussed.

ACKNOWLEDGENIENTS

The work contained herein would not have been possible except for the support
and guidance of professor Elias Strangas. Initial ideas for the project were greatly
inﬂuenced by John Vincent, an engineer at the National Superconducting Cyclotron
Laboratory at MSU. I would also like to thank professors Wierzba and Schlueter for there

time and effort in being on my committee.

iii

TABLE OF CONTENTS

LIST OF TABLES .................................................................................. vi
LIST OF FIGURES ................................................................................ vii
CHAPTER 1
INTRODUCTION ................................................................................... 1
Cycloconverters and Direct Frequency Changers ...................................... 2
FCDFC Applied as a DC Source .......................................................... 4
CHAPTER 2
THEORECTICAL ASPECTS OF DIRECT FREQUENCY CHANGERS .................. 7
Fourier Analysis of the Generalized Transformation .................................... 7
Algorithms to Generate FCDF C Switching States ..................................... 12
Low Frequency Modulation Method ........................................... 13
Three Stage Rectiﬁer-Filter-Inverter Method ................................. 24
Scalar Algorithm ................................................................... 26
CHAPTER 3
PHYSICAL IMPLEMENTATION OF THE FCDFC ......................................... 30
Circuit Topologies and Commutation ................................................... 3O
Staggered Commutation Scheme ................................................ 31
The Active Choke ................................................................. 33
Seminatural Commutation ....................................................... 34
Zero Switching Loss Topology ................................................. 36
Power Electronic Components ........................................................... 39
Snubber Capacitors and Low Inductance Bus Work .................................. 40
Microcontroller Interface Electronics ................................................... 41
CHAPTER 4
COMPUTER SIMULATIONS .................................................................... 45
SPICE Model for the 1GBT ............................................................... 45
SPICE Circuit for the AC-DC Converter ................................................ 49
Output Waveforms ......................................................................... 50

iv

CHAPTER 5

EXPERIMENTAL SETUP AND TESTING .................................................... 55
Description of Hardware and Testing Performed ....................................... 55
Microcontroller Program .................................................................. 57
Output Oscilloscope Traces .............................................................. 58

CHAPTER 6

CONCLUSIONS .................................................................................... 63
Comparison of Simulation and Testing .................................................. 63
Summary and Conclusions ................................................................ 64

APPENDIX A ....................................................................................... 67

BIBLIOGRAPHY ........................... . ....................................................... 76

LIST OF TABLES

Table 3.1 - Phase-to—Phase Algorithm Switching States ....................................... 42

LIST OF FIGURES

Figure 1.1 - General FCDFC Topology and Bidirectional Switch ............................ 3
Figure 2.1 - General n-Input, p-Output Converter .............................................. 9
Figure 2.2 - Direct AC-DC Converter Topology .............................................. 15
Figure 3.1 - Single Output FCDFC with Input Filter Capacitors ............................. 31
Figure 3.2 - Staggered Commutation Scheme .................................................. 32
Figure 3.3 - Active Choke Topology ............................................................ 34
Figure 3.4 - Seminatural Commutation Topology ............................................. 36
Figure 3.5 - Zero Loss Bidirectional Switch .................................................... 37
Figure 3.6 - Zero Loss Switch Conduction States ............................................. 37
Figure 3.7 - Experimental FCDFC Block Diagram ............................................. 44
Figure 4.1 - 1GBT Symbol and Model ........................................................... 46
Figure 4.2 - Seminatural Commutation Single Output Topology ............................ 46
Figure 4.3 - Single Output Converter 1GBT Simulation ...................................... 48
Figure 4.4 - Two Output Seminatural Converter Topology .................................. 49
Figure 4.5 - Phase to Neutral Algorithm Simulation .......................................... 52
Figure 4.6 - Phase to Phase Algorithm Simulation ............................................. 53
Figure 4.7 - Demonstration of the Regenerative Capability of the FCDFC ................ 54
Figure 5.1 - Low Inductance Bus ................................................................ 56
Figure 5.2 - Converter Output Voltage ......................................................... 59
Figure 5.3 - Load Resistor Voltage .............................................................. 60
Figure 5.4 - Load Resistor Voltage Versus 0 .................................................. 61
Figure 5.5 - Load Resistor Voltage Versus y .................................................. 62

vii

Chapter 1

INTRODUCTION

The conversion of power from the 60 or 50 Hertz form in which it is generated
and distributed to other forms such as DC or variable frequency AC is required by a vast
number of applications. An ideal power converter would provide the required output
with minimal input current harmonics and control of the input power . The subject of this
thesis deals with the theory and construction of a force commutated power converter to

provide DC output with the control of input power factor.

1.1 CYCLOCONVERTERS AND DIRECT FREQUENCY CHANGERS

Power conversion from AC at a ﬁxed frequency to DC or AC of an arbitrary
frequency may be accomplished by a rectiﬁer-ﬁlter or rectiﬁer-ﬁlter-inverter topology
respectively. Neither of these topologies provides a regenerative supply or allows for the
control of the input power factor. The cyloconverter is a direct frequency changer (DFC)
which eliminates the need for intermediate stages in the conversion process.

Cyloconverters may be classiﬁed into naturally commutated direct frequency changers

2
(NCDFCs) and forced commutated direct frequency changers (F CDF Cs). F CDF C s can

provide both a regenerative supply and control of the input power factor.

Naturally commutated direct frequency changers (N CDFCs) are at present the
most widely used. Operation of the single phase NCDFC may be described by two
independently controlled rectiﬁers which can create an output voltage equal and opposite
to the other rectiﬁer. An AC output voltage is created by cycling between operation of
the positive rectiﬁer and negative rectiﬁer. Due to the nature of the commutation
scheme, the period of the output frequency of the converter must be an integral multiple
of the period of the input ﬁ'equency. Also, the harmonic content of the output voltage of
the NCDFC cannot be improved. For these reasons the applications of NCDFCs has
been limited to low speed motor drives.

Force commutated direct frequency changers (FCDFCs) resolve the problems of
output frequency limitation and harmonics by allowing switching at frequencies much
higher than the input ﬁ'equency. A diagram of a three phase to single phase FCDFC is
shown in Figure 1.1(a). Switches shown in the diagram must be bidirectional and capable
of interupting load current on demand. A possible implementation of the bidirectional
switch is shown in Figure 1.1(b). In the ideal case, only one switch is closed at any given
time. The switches are operated in a cycle with period equal to the sum of the on times
for each switch. Commutation of the switches is performed by a pulse width modulation
(PWM) algorithm which equates the average output voltage over the switching period to

the desired output value. FCDF Cs allow bidirectional power ﬂow and the control

3
algorithm may be developed to improve the input power factor. In general, input current

harmonics are determined by the switching frequency.

 

 

 

 

 

 

 

 

(o) FCDFC Topology (b) Bldlrectlonol Swl'tch

Figure 1.1 - General FCDFC Topology and Bidirectional Switch

Implementation of the FCDF C requires an algorithm which provides timing of the
switches to produce the desired input and output. A general condition allowing the design
of an algorithm based on the low frequency (ﬁmdamental) input and output behavior was
presented by Alesina and Venturini[ 1] using a Fourier analysis approach. In the same
paper, a method of generating the switching times was presented in terms of a low
frequency modulation matrix. Other algorithms have been presented based on different
approaches to the problem. A scalar algorithm, based on comparison of the input phase
voltages has been suggested by Roy et. al.[2]. Another approach to the problem,

presented by Kim and Eshani[3], is to factor the transfer ﬁrnction matrix into three parts.

4

Each factored term is then taken to represent a rectiﬁer, ﬁlter, or inverter operation. A

detailed discussion of each of the above methods is presented in Chapter 2.

A problem concerning the commutation of non-ideal switches must be addressed
when considering the circuit topology for a F CDFC. For an inductive load, the current
must be continuous. This may be acheived via a break-before—make commutation of the
switches at the cost of adding large capacitors. If ﬁlter capacitors are to be avoided , a
make-before-break commutation scheme must employed which would effectively short
circuit the input phases for small periods. A circuit topology using series diodes was
presented by Beasant, Beattie and Refsum[4] in which half the commutations are natural.
For obvious reasons the scheme was named seminatural commutation. Other schemes
which avoid the short circuit problem and reduce switching losses have been presented by
Pan, Chen and Sheih[5]. These schemes require a more elaborate topology. A discussion

of the circuit topologies discussed above may be found in Chapter 3.

1.2 THE F CDFC APPLIED AS A MAGNET DRIVER

Application of PWM to generate waveforms requires an ouput ﬁlter or a load
which acts as an output ﬁlter. The ﬁlter must act as an integrator, since any PWM
scheme equates the average of the output over a switching period to the desired value. A
large inductance will serve this purpose. Therefore, a DC drive for a magnet would be a

suitable application for a FCDFC. The regenerative capability of the FCDFC would also

5
allow energy stored within the magnet to be returned to the system upon denergization.

Conventional DC supplies are nonregenerative and do not provide for control of the input

power factor.

The original motivation for this project was provided by John Vincent, an engineer
at the National Superconducting Cyclotron facility located on the Michigan State
University campus. Large superconducting magnets are used at the facility to provide
deﬂection and focusing of particle beams. Presently, conventional DC sources are used
to drive the magnets and the energy stored is dissipated as heat. The application of a
FCDFC as a regenerative DC supply could improve operating efﬁciency, provide

reduction in low order current harmonics, and improve the power factor.

The chapters which follow deal with both the theorectical and practical aspects of
the design and implementation of a FCDFC as a DC supply for a magnet. Chapter 2
covers the theorectical aspects of the switching control algorithms. Different approaches
to the problem of generating the switching times are presented. A solution to the DC
problem is presented using the low frequency modulation method. Chapter 3 deals with
the physical implementation of the converter. Circuit topologies, commutation problems
and the microcontroller interface are all discussed. Chapter 4 covers the results of
computer simulations for the AC-DC converter. Ouput waveforms are presented.

Chapter 5 details the experimental setup for the AC-DC converter and presents the results

6
of testing. Finally, Chapter 6 provides conclusions including the practicality of using

FCDFCs for this application in the ﬁrture.

Chapter 2

THEORECTICAL ASPECTS OF
FORCE COMMUTATED DIRECT FREQUENCY CHANGERS

Theoretical considerations in the development of a switching algorithm for the
F CDFC are discussed below. A rigorous development of conditions relating the input and
output necessary for the existence of a switching algorithm were presented by Alesina and
Venturini[l]. These conditions are discussed below in Section 2.1 using an intuitive
approach. For a rigorous development of the conditions the reader is directed to the
original paper[l]. Section 2.2 describes different algorithms presented in the literature and

outlines solutions for the case of three phase input to a DC output.

2.] FOURIER ANALYSIS OF THE GENERALIZED TRANSFORMATION

Conditions necessary for the existence of an algorithm to provide high frequency
synthesis of p-outputs given n-inputs has been presented Alesina and Venturini[ l ]. An
intuitive development of these conditions is presented below along with a discussion of the

general switching topology for a FCDFC.

8

Assume a general F CDF C with p-inputs and n-outputs is fed from a set of sources
represented by the vector ﬁ(t) and is to produce a set of outputs represented by vector

ﬂ,(t). Let the transformation be given by a switching matrix M(t) as follows,
1.0) = M(t) - f.(t) (I)

The topology of the generalized switching arrangement labeling inputs, outputs and
switches is shown in Figure-2.1. Elements of the switching matrix M;,-(t), have a value of
1 if switch Sij is on and zero if Sij is off, where switch ng connects the ith input to the jth
output. In the ideal operation, none of the input lines are ever shorted and none of the
output lines are ever open circuited. This places a constraint on the elements of each row

of the matrix,

2.: MM (1) = 1 (2)

W‘1—/—.
Input-2.._/ Output-1

 

m‘ﬂ—/—.
Input-l—/—'

nput-a—/ Output-2

 

 

Inpu't- n-—/—t

W’I—J—
Irput-2_/ W-p

 

 

Input-n_>_.

Figure 2.1 - General n-Input, p—Output Converter

Suppose that the desired output of the converter is given by vector, fd(t), which is
bandwidth limited by a)... . Then the output can be synthesized if the switches can be
operated in such a way (i.e. the Mij(t) determined) so that for arbitrary a there exists as

such that,

 

Fo(w)—Fd(a))| <8 , Va) < to ,' (0b,. < w (3)

10

where F(co) is the Fourier transform of the function f(t) and fo(t) is given by equation (1).
The relation (3) implies that the output spectrum of the converter will be correct for
frequencies less than (ob... Ifan ideal low pass ﬁlter with cutoff frequency between tow and
m is applied to the output of the converter, the desired output will be achieved. Although
equation (3) states the problem, it does not provide insight as to whether the problem
admits a solution. The following existence theorem states that the problem admits a

solution if and only if,

inf{f,(t)} 3],,(1) Ssup{f,(t)} (4)

Therefore the only requirement for a solution to exist is that the functions to be
synthesized take on only values between the set of inputs. The existence theorem stated

above agrees well with intuition but a rigorous proof may be found in reference [1].

The existence theorem indicates when a solution, the switching matrix M(t), exists but
does not provide help in ﬁnding a solution. The deﬁnition of a low ﬁequency modulation
matrix, m(t), corresponding to the switching matrix, M(t), aids greatly in ﬁnding a
solution. The low frequency modulation matrix may be introduced intuitively by
considering a single input, single output converter having a perfect output ﬁlter with
cutoff frequency (or. Suppose the switch is operated at constant frequency a), >> (0f with

slowly varying pulsewidth. Let the kth pulsewidth interval be denoted by A}. , and the kth

ll

switching interval by A... If the pulsewidth then varies according to equation (5) then the

ﬁltered output would be approximated by equation (6).
[At] = m(t,) - IA ,| for some t, e A k (5)

Mt) = m(t) - £0) (6)

The argument above provides an intuitive argument in justifying the low frequency
modulation function. For a rigorous discussion the reader is again directed to reference
[1]. In the n-input, p-output case the above argument directly results in a low frequency
modulation matrix of dimension nxp identical to the switching matrix. Each element of the
matrix, m(t), corresponds to a particular switch in the converter. The value of mid-(t) may
then be regarded as the average time that switch Si,- is closed on an arbitrarily small
interval centered at time t. A constraint corresponding to equation (2) for the switching
matrix applies as well to the low frequency modulation matrix in addition to the contraint

imposed by equation (6). The constraints on mid-(t) are summarized below,

0 s m,'j(t) $1 Vt (7)

Z mm.(t) :1 v: (8)

12

The low frequency modulation matrix is of great utility in ﬁnding an appropriate
switching algorithm for a F CDF C . Determination of a valid low frequency modulation
matrix requires the simultaneous solution to equations (6) through (8). However, this set
of equations may not have a unique solution. The following section investigates various
methods of how the matrix m(t) may be determined. The different approaches are then

applied to the problem of the direct AC to DC converter.

2.2 ALGORITHMS TO GENERATE FCDFC SMTCHING STATES

An introduction to the problem of ﬁnding a suitable switching algorithm was
presented in the last section with the discussion of the low frequency modulation matrix.
The solution to the set of constraint equations in terms of the matrix elements will only be
unique and consistent if the number of constraining equations is equivalent to the number
of switches. If the problem is under determined, additional constraints may be imposed
which provide beneﬁcial results, such as control of the input power factor. The section
which follows presents three different methods to the problem of determining the
switching state matrix. Two of the methods use an approach based on solution of vector
equations containing the low frequency modulation matrix. The third method generates

the switching times directly via a scalar algorithm.

13
2.2.1 LOW FREQUENCY MODULATION METHOD

Constraints on the low frequency modulation matrix must be maintained for any
suitable switching state matrix. In general, the set of constraining equations will not be
suﬂicient for the problem to be uniquely determined. Additional desired constraints on
current and input power can be asserted which allow the system of equations to be
determined. The fundamental constraining voltage equations are given by (6) and (8) with
an additional current continuity equation relating the input and output current vectors.

These fundamental equations are written below in vector form.

LU) = _r_r__r(t)-K.(t) (9)
LU) = 4011.0) (10)
g-l =1. (11)

where the vectors in equation (1 1) represent column vectors with all elements unity of

dimension n ( number of inputs) and p (number of outputs) respectively.

The discussion will now be directed to the solution of the vector equations above

for the case of the direct AC-DC converter with topology as shown in Figure-2.2. The

14

ﬁgure shows the case of 3-inputs and 2-outputs corresponding to the practical case of
three phase AC as input and the positive and negative DC terminals as output. Writing the

fundamental equations (9) through (11) as one system of equations we arrive at equation

 

 

(12)below.

"V, V, V, o 0 0‘r - fV,/2‘

o o 0 V, V, V, m‘" —V, /2
"’12

I, o 0 -I, o 0 ’ I,

o I, o o -1, o .m” = I, (12)
"'21

o o I, o o -1, ’ 1,
"’22

1 1 1 0 o 0 ' 1
"’23

,0001 1,-'—_1_

 

 

 

 

The system can now be reduced by Gaussian elimination. Subtracting row 3 above

multiplied by the appropriate constant to eliminate column one yields equation (13).

 

 

rV, V, V, o o"- . Trig/2—1,V,/1,‘
m

o 0 V, V, V, "2 — ',/2
mm

1, o o —1, o , 13
-m :

o 1, o 0 -1, 2" 1, ( )
mm

1 1 1 o o 1-1,/1,
m

_0011 11-2’“_ ,

 

 

 

 

15

Va Vch

 

 

 

 

 

 

 

 

 

 

 

1 ll, :— a.
— Load Impedance
t g /—
/_ -10
1 1 1I

Figure 2.2 - Direct AC-DC Converter Topology

16

Further reduction of the system of equations is next performed using row 3 of equation

(13) to again eliminate the ﬁrst column resulting in the following equation.

o—J‘og‘i

 

— u—I OQVQV

u—l t-—I o 0.: 0.:

 

—

 

0 "ml - PV, /2—(1,V, +1,V,)/1,
V, '3 —V,/2
mm
-10 __: [c
m
0 2'2 1—(I,+1,)/1,
] Lm2,3_, 1

 

 

 

(14)

Reduction of the equation above once more will ﬁnally produce a form which provides

useﬁrl insight into the problem. Using row 4 of equation (14) to eliminate column 1 yields

equation (15). Equation (15) can be viewed as four linear algebraic equations in three

unknowns. For this set of equations to be consistent, it is immediately obvious that the

relations of equations (16) and (17) must be satisﬁed. These last two relations are merely

a statement of conservation of energy and Kirchoﬁ’s current law applied to the converter.

Since the input and output voltages and currents must satisfy these relations, we are left

with equation (18).
TV, V, V,
V, V, V

l
_1

 

l
l

1'
1—

-

 

FV, / 2 — (1,V, + 1,V, + 1,V,) / I,"
- —V, /2
l—(I, +1, +I,)/ I,

 

 

1

(15)

l7

 

 

KA=LK+AK+LK no
0:1,+1,+1, (17)
I 1
V, V, V, "’1' —V,/2 13
1 1 1 m“ ‘ 1 ( )
1m...

We are now free to choose constraints on mu , mu , mu subject to equation (18). As
yet we have not stated any relations between the input and output voltages and currents.
Given a balanced set of three phase input voltages, we would like to specify the
modulation matrix elements in such a manner that the input currents are also a balanced
three phase set at a speciﬁed power factor. The general form of the desired input voltages
and currents is as shown in equations (19) and (20). Input currents chosen in such a
manner will automatically satisfy the requirement of equation (17). The power
conservation equation of ( 1 6) can now be expressed in terms of the balanced three phase

power relation as stated in equation (21).

18
V i V,cos(w.t) I

I
IV, =|fﬁcos(co~t+2n/3)l (l9)
[VJ V,cos(a)-t+47r/3)J

C

I i I,cos(a)-t+@) I

I.
II, = I,cos(a).t+27r/3+O) (20)
I], Li,cos(m-t+47r/3+O)

V,1, = 3V,I,. cos(o) / 2 (21)

Now that the input quantities have been speciﬁed, relations for m2.) , mu , mu may be
found subject to equation (18). Remembering that the solution will not be unique, we are
free to choose a solution. It is easily shown that a solution consistent with (18) through
(21) is given by equation (22).

{"721} i l/3(l—Qcos(w-I+O)) I
[murl1/3(1-Qcos(w-t+2n/3+o))l (22)

"2,, L1/3(1—Qcos(w- 1+ 47: / 3+ o))j

where, Q = V, / V, cos(®)

The next step in ﬁnding the solution will be, to ﬁnd relations for mu , mu , m1,3 consistent
with the fundamental equations as expressed in (12), the input quantities as stated in ( l9)

and (20) and the previously determined values for mu , mu , mm found in (22). Again a

19

solution is found by inspection and veriﬁed. It can be easily shown that the solution
expressed in (23) below is consistent with all requirements. The ﬁnal expression for the
modulation matrix has dimension 2x3 and may then be expressed as shown in (24) in

terms of the elements of (22) and (23) .

[m,,[1/3(1+Qcos(a) 1+6)»
m,,=[.1(/31+Qcos(w t+27r/3+G))) (23)
[vii3 l/3(1+Qcos(w t+4nr/3+O))

[-rnlJ m1.2 ml.3

[ (24)
mm mm ”72.3

t):

11;

The modulation matrix elements must also be constrained by () to lie between zero and
one for all times. The allowed values of (2 which may be used are such that 0 < Q < 1,

corresponding to a maximum voltage transfer ratio of VJVicos(®).

Although the above development follows the general approach of reference [1], a
different variation for developing the modulation matrix will now be presented. The
impetus for pursuing this method lies in the microprocessor hardware implementation

which is explained in Chapter 3.

20

The underlying concept in this new approach lies in viewing the output as a single
voltage created by all six switches. In the previous discussion, the output voltage was
considered as being created by two separate output phases, each being determined by a set
of three switches. The output across the load was then viewed as the difference between
the constant voltages created at the two output phases. While the old method impressed
phase voltages at the outputs, the new method will directly treat the output voltage in
terms of phase to phase quantities. The method previously developed shall be refered to
as the phase to neutral algorithm, while the new method shall be denoted as the phase to
phase algorithm. The new system will now be viewed as having one output and six inputs

as described by equations (25) and (26) below.

 

 

1m;
mbc
m
[I/ab Vbc Vca I[bu Vcb Va ] . mm : V0 (25)
ba
mob
_ mac .1
f [ab '
Ibc
I
I0 : [mob mbc mca mba mob ma ] . [ca (26)
ba
lob
_ lac .1

 

 

21

The elements of the modulation matrix for the phase to phase algorithm correspond to a
set of two switches as opposed to a single switch for the phase to neutral method. Using a
constraint equation corresponding to equation (11) and writing Vji as 'Vij and 1,1 as ‘Iij we

may write the entire system as shown in (27) below.

 

 

 

 

 

 

_ 7 ”mob — _ _
V ab Vbc L/ca —Vab —I/ be -Vca V0
mbc
1 1 1 1 1 l l
mca
I, o o —I, 0 o . m = 1,, (27)
o 1, o o -1, o b“ 1,,
m
L 0 O 10 O O _10 .1 _m:_ 1. ca .J

Reducing the system above by Gaussian elimination yields the following equations.

V,1, = V,,1,, + V,,1,, + V 1 (28)

CO CO

mab+mbc+mca=(1-(Iab+1bc+]ca))/2 (29)

Equation (28) is just a statement of conservation of energy and will automatically be
satisﬁed. If the input currents and voltages are constrained to be balanced three phase,
then the currents no longer appear in (29). The following equations then are constraints

on the matrix elements.

22

"2,, +m,,+m,, =1/2 (30)
mba+m,,+m,,=l/2 (31)

As before we shall write the voltages and currents as balanced three phase sinusoids.

These relations are written below as equations (32) and (33).

V,, ‘— V,cos((o-t) ‘1

I
in, WV, cos(w- t+ 27: /3)JI (32)

V,cos(a)-t+47r/3)

1,, f 1,.cos(a)-t+O) 1|

1
I1,, = I,cos(a)-t+27t/3+O) (33)
11,1 Mam/3.9.1

Using equations (32) and (33) we may rewrite the last three rows of (27) as the three

equations shown below as (34).

m,,-m,, = I,cos(w-I+O)/I,

m, —m,,=l,cos(w-t+27r/3+O) (34)

C

mm —m,, = I,cos(w-t+47r/3+O)

23

Now we may ﬁnd a solution by inspection which will satisfy all constraints. Using (3 O) ,
(31) and (34) it is easily shown that a solution to the problem is given by the expression

below. It should again be noted that the solution is not unique.

1m," 1 (1+31, cos(a)-t+O)/I,)/6

mb, (1+3I,cos(w-t+27r/3+®)/I,)/6
m (1+3I,cos(a)-t+47r/3+O)/I,)/6
mb, 2 (1—31, cos(w-t+O)/I,)/6 (35)
"2,, (1—31,cos(w-t+27r/3+O)/I,)/6

ﬁt,” L(1—3I,cos(w-t+47r/3+®)/I,)/6_

 

 

 

 

For the elements of the modulation matrix to be valid, they must only take on values
between zero and one as expressed in (7). This inequality is expressed in terms of the
input and output currents, however we would like the relationship in terms of input and
output voltages. Using an expression for the three phase power we can then express the
inequality in terms of voltages as shown in (36). The actual limit on the output voltages is

then expressed by (3 7).

V,1, = 3V.1. cos(o) / 2 :> 31, /1, = 2V, /V,. cos(o) (36)

V, s V, cos(o) / 2 ' (37)

24

A comparison of the maximum voltage output possible from the previous development of
the phase to neutral algorithm expressed in (22) through (24) to that of (3 7) shows that
the second method yields a voltage transfer ratio of 0.87 with respect to that of the ﬁrst
method. Although this is a disadvantage, the phase to phase method can be implemented

more easily using microprocessor based control. This subject is discussed in Chapter #3.

2.2.2 THREE STAGE RECTIFIER-FILTER-INVERTER METHOD

A variation of the low frequency modulation method is obtained by factoring the
modulation matrix into three component matrices. Each matrix is then viewed as a
rectiﬁer, ﬁlter and inverter operation respectively. For this reason, the method is often
called indirect PWM while that of the previous section is referred to as direct PWM. An
investigation of the relative merits of indirect PWM versus direct PWM has been

performed by Ziogas et al[6].

A detailed discussion for the direct conversion of 3-phase at given frequency to
3-phase at an arbitrary frequency was performed by Kim and Eshani [3]. The discussion
below will be an adaptation of the method to the case of direct 3—phase AC to DC with
two output terminals. Using the same methodology as reference [3] the output will as

expressed in equation (38) below.

25

 

K. = h h,(t)h,.a(t)Z,-(t) (38)

‘— m(t)

The modulation matrix of section 2.2.1 for the phase to neutral algorithm will be
analogous to the product of all three matrices in (3 8) above. The ﬁlter and rectiﬁer
functions will be equivalent to the AC output case and may take the form shown in (39) '
and (40) below [3]. The inverter function will have constant elements for the DC output

case and is shown in equation (41).

hf(t)=;{-K—(:a:—)t)-[tl(a)t+7rl6-n€)—u(wt—rr/6-7rf)]

cos(
+ K(—1)’
cos(a) z - 27r / 3)

K(-1)‘
+cos(w1-4zz/3)["(m—7ﬂ/6_”€)_u(m—3ﬂ/2-ﬂ)li

 

[11(wt—7r/2—7r€)—u(cot-Srr/6-7rli)] (39)

 

r Z[u(wt+7r/6—7r€)—u(a)t-7r/6—7r€)](-1)l -
h,,,,(t) = Z[u(wt -7r /2—7r€) —u(a) t— Srt /6-7r€)](-1)' (40)
Z[u(wz-'7n/6—m?)—u(cor—_3n/2—ne)](-1)’J

 

 

26
where u(t) is the unit step ﬁrnction and K=1/V; is the gain of the ﬁlter.

IV,/2]

I... 1-1/,1. (41>

Substituting (3 9) through (41) into (3 8) the DC voltage developed across the load is then

given by the following expression.
v.41 412.41 -1]r...h,(t)l_w..(t)z.(r) 142)

It should be noted that the method above did not take into account the input current to the
device and therefore will not provide for the control of input power factor. Although the
approach uses the familiar analogies of rectiﬁer and ﬁlter stages, the lack of ability to

control the input power factor is a severe limitation.
2.2.3 SCALAR ALGORITHM

A scalar algorithm has been proposed and tested by Roy et al[4]. This scalar algorithm
applies to only a balanced three phase set of input voltages. The method separates the
domain of the input into regions over which two given input phases have opposite polarity
to the remaining phase. For a set of balanced three phase inputs, the entire time domain

may be divided into such regions. A derivation of the scalar algorithm is presented below.

27

The following equations are the basic scalar equations relating to output voltage and

switching time intervals for any 3-phase DF C scheme.

thk +V,t, +thm

 

Va T (43)
S
1,,+t,+t,,=Ts (44)

In equations (43) and (44), Ts represents the switching period, V1. the input voltage on
phase k, tk the switching pulsewidth of phase k, and k,l,m represents any permutation of
the input phases A,B,C. Suppose that at time t input phase m has polarity opposite to
both phases k and 1. Also suppose that k and l are chosen such that equation (45) holds.
Now tk and t. are chosen such that the equality in (46) is maintained. Note that (46) places

a constraint on the problem and will allow the problem to have a unique solution.

“
”a

(45)

O

l/\
s: |

I/\

u I"
H-
II
V"
111
E".

N-

(46)

Substituting the above equation into the basic scalar DFC equations (43) and (44) and

then solving for t. , tk , and t... yields the equations below. Before the equations are

28

applied, the correct permutation of the input phases corresponding to k , l , and m must be

determined in accordance with (45) and (46).

,_ (Ia—VJ. (,7)
,_
V;p,,+V,-V,,(1+p,,)

 

tr .—: Pratt (48)

z, = 7:. —(1+p,,,)t, (49)

Note that the duration over which a particular permutation remains valid corresponds to
an angular change of rt/6. The equation which applies to the pulsewidth of a particular

switch changes with the same frequency.

The evaluation of power factor for the balanced 3-phase output case using the scalar
algorithm can be found in reference [4]. For this case the scalar algorithm achieves a
unity power factor. The following expression for the input current applying to the
topology of Figure 2.2 can easily be derived from the previous discussion. Note that the
input current will have the same phase as the input voltage only if the input power remains

constant. Therefore the scalar algorithm applied to the DC output case will attain a unity

29

power factor only in steady state operation. The vector methods found using the low

frequency modulation matrix in section 2.2.1 did not suffer this limitation.

_ KLK _KLK
” V,3+V,2+V,f’1.5V,2

 

(50)

Chapter 3

PHYSICAL IMPLEMENTATION OF THE FCDFC

The implementation of a FCDFC requires that the switches comprising the
converter be commutated to change the connection of the output phases between any of
the input phases. Switching algorithms, previously discussed, assumed ideal commutation
of the switches so that the input phases are never shorted and the output phases never
open circuited. In a practical device, ideal commutation of the switches can not be
achieved. Either a ‘make before break’ or ‘break before make’ switching strategy must be
employed. In the later case, large output ﬁlter capacitors must be employed if the load is
highly inductive. If large output ﬁlter capacitors are to be avoided, a make before break
commutation scheme must be used. This commutation scheme must tolerate the short
circuit of the input phases for small periods. Circuit topologies of different commutation

schemes and aspects of the physical implementation of F CDFCs are presented below.

3.1 CIRCUIT TOPOLOGIES AND COMMUTATION

Different circuit topologies and switching strategies have been presented in the
literature which address the FCDFC commutation problem. The topologies which are
discussed below provide an overview of different strategies. All assume ‘make before

break’ commutation of the switches.

30

3.1.1 STAGGERED COMMUTATION SCHEME

A simple topology for the FCDF C is attained using bidirectional switches and is
shown in Figure-3.1 for the single output case. The input ﬁlter capacitors must be
included to allow switching of the input phases with a non-zero source inductance. A
working implementation of the scheme has been achieved by numerous groups including

Alesina and Venturini[l], and Pan and Chen[5].

\

E
,\
5

4
1

 

 

\

1

 

 

 

 

—b uh I
Figure 3.1 - Single Output FCDFC with Input Filter Capacitors

The commutation problem was solved by Alesina and Venturini in reference [1]
using a strategy they termed “staggered commutation”. Implementation of the
bidirectional switch includes two antiparallel transistors. The staggered commutation

scheme is described by Figure-3.2 and the sequence of events listed below.

31

32

1) Determine whether the switch turning on is at a lower voltage or higher voltage
than the switch turning off. The two devices in the switches which allow a current ﬂow
outward from the lower voltage switch and inward to the higher voltage switch are termed

“free wheeling “ devices for the events of step (2) below.

2) Stagger the commutation by sequentially,
a) turning on the freewheeling portion of the incoming switch,
b) turning off the nonfreewheeling portion of the outgoing switch,
c) turning on the nonfreewheeling portion of the incoming switch,

(1) turning off the freewheeling portion of the outgoing switch.

 

IEVICE

 

mm:
MICE

 

Figure 3.2 - Staggered Commutation Scheme

33

Operation of the “free wheeling” devices in the staggered commutation strategy
are analogous to the operation of the free wheeling diodes in a standard inverter bridge.
Therefore this type of commutation scheme does not require snubbering. A disadvantage
of the scheme is the complicated switching strategy and the required comparison of the

input phase voltages.

3.1.2 THE ACTIVE CHOKE

Another more elaborate topology introduced by Beasant and Refsum [4] which
uses bidirectional switches is shown in Figure 3.3. The essential idea is to provide an
interface circuit between the load and the switch matrix which would appear as zero
impedance to load currents but appear as an inﬁnite impedance to short circuit currents
caused by the commutation. The multiwinding transformer and diodes rectify the ﬂux in
the core due to currents entering from the three phase source. Additional windings which
carry only load current create a ﬂux within the core which opposes the ﬂux created by the
load current ﬂowing through the coils of the input phase windings. Therefore the current
which circulates between phases will cause a rectiﬁed ﬂux in the core with no opposing
ﬂux from the compensating windings since this no similar current ﬂows through the load.
The impedance seen connecting the load across any of the source inputs will be only the
leakage reactance. However short circuits of the source due to commutation will see
magnetizing reactance. The above discussion of course assumes that the turns of the input

windings and compensating coils are properly matched.

34

 

 

 

 

 

 

 

 

 

J BIDIRECTIDNAL

|__] |__] SWITCHES

\

 

 

 

 

 

1ct

 

Figure 3.3 - Active Choke Topology

3. 1.3 SEMINATURAL COMMUTATION

A simpler FCDFC topology was also investigated in [4] which solves the
commutation problem. The topology requires only unidirectional switches which may be
implemented using any transistor with the appropriate voltage, current and switching
capability. Diodes are used in series with the transistors and provide reverse blocking
during commutation. The scheme is illustrated in Figure 3 .4 below. Two separate stages

are used to provide 4-quadrant operation. The commutation control is provided by only

35

one stage at a time. A current zero crossing detector is required to control the transfer of

commutation between the positive and negative conducting stages.

When the output is to be commutated between source phases two situations occur
with equal frequency. The ﬁrst situation is that the outgoing source phase is at a higher
voltage than the incoming source phase. When the incoming phase is switched on, the
diode on the incoming phase is reversed biased and does not conduct. The outgoing phase
is then opened by the controlling commutation signal. Therefore the commutation of the
switch for this situation is forced. Consider now the second possibility where the
outgoing source phase is at a lower voltage than the incoming phase. When the incoming
switch initially closes, the diode is forward conducting but reverse biased. If the overlap
of the ‘make before break’ commutation exceeds the reverse recovery time of the diode
then the switch commutation is natural. Therefore, for this topology half the
commutations are provided naturally from the series diodes. For this reason the scheme
has been called “seminatural commutation”. The scheme requires relatively few
components and has a simple commutation scheme. The only complication in the
commutation is the zero current crossing detection to provide for 4-quadrant operation.
For two quadrant operation, the commutation scheme is extremely simple and the required
components are minimal. For this reason, the scheme was adopted for the experimental

work of this thesis.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

/ Di
Posl'tlve Stage
/ a>1
1L— Dutput
/ a<1
Negatlve Stage
/ 1<1

Figure 3.4 - Seminatural Commutation Topology

3.1.4 LOW SWITCHING LOSS TOPOLOGY

The last circuit topology to be discussed is also the most complicated. The
topology to be presented here is based entirely on the work of Pan era]. [5]. Central to
the scheme is the implementation of the bidirectional switch shown in Figure 3.5. The
switch uses a rectiﬁer bridge, similar to the simple bidirectional switch of Figure 1.2, but
implements the unidirectional switch with two transistor-diode conducting paths and a
capacitor. Figure 3.6 (a) through ((1) show the four diﬁ’erent conducting states which are
attainable. In the initial turn on conﬁguration (a), the transistors conduct until the

capacitor is discharged ﬁ'om its previous blocking voltage. The switch then enters the

37
steady state turn on conﬁguration (b) during which the capacitor plays no role. When the

transistors are then turned off, an initial turn off state (c) ensues in which the diodes
conduct and the capacitor is again charged. After the capacitor is completely charged the
switch enters the steady state oﬁ’ conﬁguration (d). The capacitor acts as a snubber

during commutation preventing voltage spikes across the transistors.

 

n

 

i2 02

 

 

 

 

 

 

Figure 3.5 - Zero Loss Bidirectional Switch

(a

K
) (b) (c)

 

_1'“'*‘1'

A
9.
v

Figure 3.6 - Zero Loss Switch Conduction States

 

 

38
During initial turn on, the blocking voltage across the capacitor implies that the

initial current through the switch will be zero. Therefore zero current switching occurs at
turn on. At turn off, the voltage across each transistor is zero if the capacitor is
completely discharged. Therefore zero voltage switching occurs at turnoff. So if the time
constants of the LC circuit is such that the capacitor is able to fully charge and discharge
within the switching interval, zero switching loss will be achieved. Reference [5] shows
that the condition for the above to be true is as shown in (51) below where the S and R

subscripts denote the switching and resonant LC circuit frequencies respectively.

fR>— (51)

In addition to zero loss, the bidirectional switch proposed above has advantage of
a simple commutation scheme. Both transistors in the switch are simultaneously signaled
off and on. No separate logic is required to determine modes of operation dependent on
voltage or current polarity as found in the staggered and seminatural commutation
schemes. The only disadvantage of the proposed switch is the additional components

required by the topology.

3.2 POWER ELECTRONIC COMPONENTS

Electronic components with suitable ratings and abilities must be found to
implement the topologies of the last section. Rectiﬁer diodes and transistors used as

unidirectional switches are all that is required.

Power switching diodes must be capable of canying the maximum current required
by the FCDFC and be able to commutate at a frequency well beyond the switching
ﬁ'equency used by the algorithm. Line frequency rectiﬁer diodes are unacceptable. The
speed of a diode is determined by t.T , the time it takes for charge carriers to be swept out
of the junction when reverse biased creating a depletion region. The actual time is
dependent upon conditions external to the diode. Standard conditions include initial
current of nlf with a change in current of 25 uA/second. Conversely the reverse recovery
ability of a diode may be characterized by Qrr , the charge which must be swept out of the
junction to create the depletion region. The value of Q" is independent of conditions
external to the diode. Available power switching diodes are categorized based their
reverse recovery time. Fast recovery diodes have t,, values of several microseconds or
less. Ultrafast recovery diodes are available with t,r values as low as a few nanoseconds.
The choice of acceptable diode recovery time is dependent upon the switching speed used
in the commutation. Ifdistortions due to diode reverse recovery are to be avoided, the
reverse recovery time must be small with respect to the switching period. Also, certain
topologies, such as seminatural commutation, place requirements on the maximum
reverse recovery time.

39

40

The present choice for high power switching is the insulated gate bipolar transistor
(IGBT). The IGBT has a structure which provides a low on-state voltage similar to a BJT
with input drive requirements similar to a MOSFET. IGBTs are currently available
capable of switching frequencies of 30kl-Iz . A SPICE model for the IGBT will be
discussed in Chapter 4. Packaging available for IGBTs is similar to other power

transistors. Available case styles include pin out, and ﬂat pack conﬁgurations.

Drivers for discrete IGBTs are widely available from a number of manufacturers.
These drivers have minimal power requirements. Most driver circuits contain
optoisolators to provide isolation of the commutation signal from the power circuit. Each

isolated IGBT will require a driver supplied by an isolated power supply.

3.3 SNUBBER CAPACITORS AND LOW INDUCTANCE BUS WORK

The circuit topologies of section 3.] did not address parasitic inductance of
electrical connections and capacitors. In the discussion of those schemes it was assumed
that the electrical connections from transistors are ideal, without any inductance. The
transistor could then interrupt arbitrary current without introducing a di/dt voltage spike.
It was also assumed that capacitors used in these schemes could support current
discontinuities. Obviously, any physical electrical connection or device will contain some
parasitic inductance. Extremely low inductance connections may be designed by

sandwiching thin copper bars together. This type of bus work also has the added beneﬁt

41
of reducing stray magnetic ﬂux and EM]. A discussion of the design of low inductance

bus may be found reference [7]. Specialized kits for designing prototype bus connections

are available. These kits allow the fabrication of specialized bus work with little effort.

Low inductance capacitors are now available for snubbers and applications such as
the FCDFC topologies discussed earlier. Besides the normal microfarad rating, these
capacitors have an additional rating in units of kV/usec. This rating reﬂects the capacitor
units ability to conduct current imposed by voltage spikes. . With regard to the design of
a F CDF C, the inductance of bus work and capacitors must be made small enough to

ensure the proper operation of the circuit topology chosen.

3.4 MICROCONTROLLER AND INTERFACE ELECTRONICS

Algorithms for creating the switching states of a FCDFC have been
discussed, however a method of physically generating the control signals has not been
addressed. Although the discussion which follows is directed toward the low frequency
modulation method, the ideas apply equally well to any FCDFC algorithm. The switching
states may be implemented using the parallel port of a microprocessor. Each pin of the
parallel port provides the control signal for one switch. Switching states are commuted by
calculation of the pulsewidth for a given switching state as a fraction of T, , the total
switching period. The fractional value above is the evaluation of the appropriate element
of the low frequency modulation matrix at that particular time. Since we must write to all

pins of the parallel port simultaneously, we would prefer an algorithm which views all

42

switch positions as a single state. The phase-to-neutral algorithm found in section 2.2.]
does not achieve this goal. The states for the switches associated with the positive output
are found independently of the states found for the negative output. For this case, the
sequence of parallel port states commutated within a switching period will change. This
complicates the generation of a switching sequence. The phase to phase algorithm, also
developed in section 2.2. 1, ﬁnds the positions of all switches as a single state. The
switching sequence will then be constant within the switching period. A sequence may
then be determined which minimizes the number of commutations of each switch within
the switching period. Table 3.1 below shows an ordering of states for the phase to phase
algorithm which minimizes the number of commutations. In the table, the P and N
subscripts denote switches connected to either the positive or negative output terminal.
The ‘+’ and ‘-’ symbols denote a conducting or nonconducting state respectively.

Conducting states shown determine the of the six switches of Figure 3.4.

Table 3.1 - Phase-to-Phase Algorithm Switching States

State A, By C, AN
Position
1

 

The microcontroller commutates between switching states by calculating

pulsewidths for each particular state and loading these states to an internal timer.

43
Simultaneously the switching state is written to the parallel port. When the timer has

reached the value which has been loaded, an interrupt is generated which causes the time
for the next state to be loaded and the process repeats. If a table of switching states
versus switching times is loaded into memory for an entire cycle of the input, then no

calculations need be performed.

It is inherent in every FCDFC algorithm that the switching sequence be
synchronized with the input power source. Using a microcontroller this may be achieved
by setting an external pin to generate an interrupt. The interrupt would then cause the
program to begin the switching sequence at the appropriate point. A zero crossing

detector can be used to generate the interrupt.

The microcontroller will generate control signals to switch directly between the
different states. However, we wish to implement a ‘make before break’ switching
strategy. Therefore a delay circuit is needed to provide for this requirement. The delay
circuit will ensure that the load is never open circuited. A block diagram of the describing
the entire system including microcontroller, zero crossing detector and delay circuitry is
shown in Figure 3.7. A description of the experimental setup used in this thesis is
contained in Chapter 5. A description and schematics of the circuits used for the zero

crossing detector and delay circuitry may be found there.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I Delay I I
MICRDCDNTRDLLERI > Circuitry I > I "0:5?513-56
/ Zero L
\ CrosslngI
..____l
A B C

Figure 3.7 - Experimental FCDFC Block Diagram

Chapter 4

COMPUTER SIMULATIONS

The previous chapters covered theoretical aspects of F CDF C algorithms and
several circuit topologies by which the converter could be implemented. To test the
operation of the converter a given topology must be implemented and an algorithm
chosen. This chapter deals with the simulation of the converter using PSpice. The
seminatural commutation scheme of Chapter 3 will be adopted and the low ﬁequency
modulation method chosen as the algorithm. First however, a discussion of a single
output converter using IGBTs is presented. The impetus for this discussion is use of

IGBTs in the experimental implentation of the converter in Chapter 5.

4.1 SPICE MODEL FOR THE IGBT

The Insulated Gate Bipolar Transistor (IGBT) has a structure which combines the
favorable input drive and switching characteristics of the MOSF ET and the low on state
voltage of the 811'. The symbol for the IGBT is shown below in Figure 4.1 along with a
model for the device [8]. Using PSpice, the model shown has been adapted suitably well
to describe the characteristic curves for Toshiba M075] l 881 1 device used in the
experimental work of Chapter 5. The model has been applied in the single output

seminatural commutation topology shown in Figure 4.2 below.

45

 

 

Id

 

(a) 1631' Synbol (b) IGBT Model

Figure 4.1 - IGBT Symbol and Model

 

 

 

 

 

 

 

Parasrtlc
Source Impedance Inductance
. ‘VO torV\
00 i l
.L .L
\‘1 Fﬂter
Capacitors

 

Load Impedance

 

TL— W

 

 

 

 

Figure 4.2 - Seminatural Commutation Single Output Topology

47

The single output topology was used to test the IGBT model in the seminatural
commutation scheme due to convergence problems encountered in the two output
scheme. Although it will not simulate the actual converter, the single output case will
simulate the operation of the IGBT in the circuit topology. The main reason for
simulating the actual device used is to test for voltage spikes caused by the commutation.
Figure 4.3 shows the output of the simulation for the single output converter connected to
a 208 VAC source. A parasitic inductance of O. 1 SuH was used. The collector-emitter
voltage was found displayed spikes exceeding the maximum phase-to-phase voltage by
approximately 100V. These spikes however do not coincide with overvoltages due to
commutation since they occur when the IGBT is turned on. The lower graph in Figure 4.3
shows the current ramping due to the application of the DC component created by the

converter. This behavior in the simulation agrees well with the theory.

Throughout this thesis, commutation of switches in PSpice was achieved by the
piecewise linear model (PWL). Inputs to the model were generated by a C program which
calculated the PWL comers in terms of the F CDFC algorithm and output these to a text
ﬁle for each switch. The text ﬁles were then pasted into a PSpice circuit ﬁle. Although

tedious, the process yielded useﬁrl results.

48

Single Phase Output - IGBT Test

500V’-'—------—--------—--—-—-------~—..-—.....__.._....._........_...I

0V

-500V

0A

Collector - Emitter Voltage

IINNﬂ \

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

: I I 11 :
E111II i 111. 111 I1 5
111111 -~ :
' ‘ I IIII l I '
I I i ;.I l 1 i
: -. ,1 :
: '1 :
I R=80 ohm L=300 mH. !
I theta = 0 . gamma = 1”0 I
i __________________________________________ 11 ......... I
o V(13)- V(5)

I Load Current I
i lkﬂn/VVVNNAWVNNC/Vk' I
' . . . i
03 Sms 10ms 15ms
D I(Lload)

Time

Figure 4.3 - Single Output Converter IGBT Simulation

4.2 SPICE CIRCUIT FOR THE AC-DC CONVERTER

Observing the IGBT model of Figure 4.1 it can be seen that the output
characteristics of the device are simulated by the BIT. Since modeling of the drive circuit
is not required, the MOSFET and sources may be viewed as part of the drive circuitry.
Therefore, in the simulation of the two output direct DC converter BJTs were used in
place of lGBTs. Care was taken to ensure that rise and fall times of the circuit were
within the limits for the physical IGBTs to be used in the converter. This allowed the
overall operation of the converter to be simulated. The circuit used to simulate the two
output converter using BJTs is shown below. The circuit topology is seen to be that of

the seminatural commutation scheme.

 

 

 

 

 

 

 

 

 

 

 

 

Parastttc
Van Sarce Irpedance 1mm,
U W .I. m
Vbn T m
U W _L ..
Vcrx Wy—m T T am
U Flter
_I_ W

 

 

 

 

Figure 4.4 - Two Output Seminatural Converter Topology

49

4.3 OUTPUT WAVEFORMS

The circuit of Figure 4.4 was entered into a PSpice circuit ﬁle. Several simulations
were obtained using different sets of PWL corner data to control the commutation. A
load inductance of 25 mil, load resistance of 6.8 Q and 12VAC phase to neutral source
were used to match the experimental converter. Each simulation began with zero initial
load current. Therefore the current in the load should increase as an LR series circuit with

a DC voltage applied. This behavior was conﬁrmed in each simulation.

Figure 4.5 is a simulation of the converter using the phase to neutral algorithm
discussed in Chapter 2. The upper and lower graphs show the voltage across the load
resistor for switching frequencies of 2kHz and SkHz respectively. Cyclic ﬂuctuations in
the harmonics can be seen due to the independent commutation of the positive and
negative output terminals. Output voltages obtained agree with the theory when the
collector-emitter saturation voltages of the two series transistors are taken into account.
Figure 4.6 shows an identical simulation for the phase to phase algorithm. No ﬂuctuation
in the harmonics is evident. The output voltage obtained is approximately a factor of ‘13/2

less than the phase to neutral algorithm as predicted.

Figure 4.7 demonstrates the regenerative capability of the FCDFC using the phase
to phase algorithm. In each graph of the ﬁgure, the voltage is turned on to the positive
maximum and then switched to a lower voltage. For a 'y of zero, the DC component of
the output voltage should also be zero. Therefore the decay of the load resistor voltage in

50

51
the upper graph of Figure 4.7 should match the time constant of the load. This agrees

well with the simulation. For the middle graph, the voltage is switched to -0.5 of the
maximum. The rate of decay of the load resistor voltage is seen to exceed that of the
natural time constant. This indicates that power is being transferred from the load to the
source. The lower graph displays the decay of the load resistor voltage when the output
voltage is changed to a negative maximum. This corresponds to the maximum rate that

energy may be removed from the load.

The simulations which are presented here will be compared with the results of the
experimental converter presented in the next chapter. These simulations have veriﬁed the
correct operation of both the phase to phase and phase switching algorithm and the

seminatural commutation circuit topology.

52

15v>r-------—-—----—----——-------------—---——---—--------——}

E

  

i
I

l I
I I
I I
I l
I I
10V{ 1
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Figure 4.5 - Phase to Neutral Algorithm Simulation

53

J

15V-r ------------------------------------------------------

10V

ZkHz Phase Phase Algorithm

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Figure 4.6 - Phase to Phase Algorithm Simulation

54

 

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Time

 

 

Figure 4.7 - Demonstration of the Regenerative Capability of the FCDFC

Chapter 5

EXPERMENTAL SETUP AND TESTING

Operation of a direct AC-DC converter was veriﬁed in the last chapter using
PSpice. The circuit topology used in the simulation was that of the seminatural
commutation scheme of Beasant [4] with the phase to phase switching algorithm
developed in Chapter 2. An experimental converter was developed based on the same
circuit toplogy and switching scheme. The following pages detail the design and testing of

the experimental converter.

5.1 DESCRIPTION OF HARDWARE DESIGN

The seminatural commutation scheme requires six transistors and diodes to
implement the desired 2-quadrant supply with two outputs. Transistors used were 75A,
600V Toshiba M675] 1881 1 1081‘s. Diodes used were stud mount 40A, 500ns tIt ,
600V lntemational Rectiﬁer 4OHFL60805 and 4OHFLR60805. The two different part
numbers correspond to cathode to stud and anode to stud conﬁgurations respectively. The
ratings of these devices far exceed the requirements of testing, however the original scope
of the project was to develop a prototype 20A,. 208VAC converter for testing at the
National Superconducting Cyclotron facility at Michigan State University. Although only
low power testing was performed, the converter developed should be capable of

operating with a 208 VAC 3 phase input and 20 amperes DC output.

55

56

For low power testing of the inductor, a source was provided by three wye
connected 120/12V , 2A voltage transformers. The largest inductor available for testing
was 25 mH. This inductor was used in series with a 6.8 Q resistor. Input ﬁlter capacitors
were provided by three 20 uF metal can capacitors. Snubbing of the input was provided
by two 1 [AF low inductance capacitors donated by the Illinois Capacitor Company. To
avoid the use of snubber capacitors across each IGBT, low inductance bus work was
required. A Proto BusTM kit purchased from Eldre Corporation was used in the design of
the bus. The kit includes tinned copper bus bar with equally spaced connection tabs,
adhesive insulting tape and plastic connectors. Figure 5.1 below shows the design of the

low inductance bus including connections of diodes, IGBTs and input snubbing capacitors.

Positive Terminal

A Snubber Caps
1!} Connected
40HFLR6OSOS C Directly to Bus
(Anode to Stud) Negative Terminal
' l
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Note A Phase section shown
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Figure 5.1 - Low Inductance Bus

5.2 MICROCONTROLLER OPERATION AND PROGRAMMING

Operation of the converter was controlled by a Little GiantTM microcontroller
manufactured by Z-World Systems. The microcontroller operates at 9.216 MHz using a
2180 processor. A 16 bit parallel port on the controller may be addressed in two 8 bit
sections. Each pin on a given port may conﬁgured for input or output. A pin conﬁgured
for input may be set to generate a vectored interrupt. Control of switches was provided
by six pins of the parallel port conﬁgured as outputs in the upper 8 bit division. A single
bit of the lower 8 bit division was conﬁgured as input to generate an interrupt used in
synchronizing the switching algorithm with the input voltage source. A simple op-amp

voltage zero crossing detector was used to provide synchronization.

The phase to phase switching algorithm was implemented in the microcontroller
program by a lookup table providing timer constants and switching states. A switching
state is retrieved from the table and written to the parallel port while the corresponding
time is loaded to the timer. An interrupt is generated upon time out causing the next
switching state in the table to be written and the next timer value loaded. The sequence
repeats until a synchronizing interrupt is generated causing the process to reset to the top
of the table. The table is intentionally made longer than one power system cycle so that a
synchronizing interrupt will always occur before the end of the table is reached. Values
for the table are generated by the program at start up using C functions provided by the

compiler. The switching state sequence and synchronizing interrupts were all written in

57

58

assembler to make the program faster. A minimum switching state pulsewidth of
approximately 15 us has been achieved. This minimum pulsewidth could cause deviations
from the results expected from the algorithm. More will be said of this problem when the
output oscilloscope traces are reviewed. The actual microcontroller program may be

found in Appendix A.

5.3 RESULTS OF TESTING

The converter developed was operated applying various parameters in the phase to
phase algorithm. Output was observed and plotted using a digital oscilloscope. The total
output voltage of the converter is shown in Figure 5.2(a) and (b) for the parameters
shown. The waveforms agree well with the expected operation of the converter. Current
through the load was monitored by observing the voltage across the series load resistor as
was done in simulation. In all cases the DC component observed was approximately 2/3
of that expected from simulation and theory. Figure 5.3(a) shows the load resistor voltage
for a gamma of 1.0 and a unity power factor. The voltage expected from simulation
would be approximately 12.5V. An actual load resistor voltage of about 8.5V was
observed. Operation of the converter for a variation in power factor angle is shown in
Figure 5.4 with identical values. The relative change in the output is as expected from
theory. In hindsight, it would have been informative to observe the voltage and current
waveforms at the 120V terminal of the source transformers to verify the input power

factor. For a ﬁnal veriﬁcation of the converter operation, the load resistor voltage was

 

 

 

 

 

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Figure 5.2 - Converter Output Voltage

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Chapter 6

CONCLUSIONS AND COMMENTS

Various methods of implementing FCDF Cs have been presented with regard to the
construction of a direct AC-DC converter. In Chapter 2, two diﬂ‘erent algorithms using
the low frequency modulation were presented. The ﬁrst method used the traditional
approach, viewing each output terminal separately in terms of the phase to neutral
voltages of the source. The second method derived a new algorithm based only on the
voltage between the two output terminals. This new algorithm developed allowed for a
simpler microcontroller implementation of the switching states. Adopting the new
switching algorithm, a circuit topology was chosen for the development of the prototype
converter. The converter design and switching algorithm were then simulated to conﬁrm
theoretical expectations. The discussion which follows reviews, compares and contrasts

the results obtained from theory, simulation and testing.

6.1 COMPARISON OF SIMULATION AND TESTING

The results of testing deviated from the theory and simulation with regard to both
the DC component of the output voltage and the magnitude of the ripple due to switchin
harmonics. Both of these comments can be ascertained from the ﬁgures of Chapter 4 and
Chapter 5. The ripple voltage magnitude depends strongly on the value of load inductance

used. The load inductor used was made especially for the project by Osborne. Its value

63

64

of inductance was not provided and was determined from measurement using an LR
circuit. A value of 25mH was computed from the measured time constant of the circuit
for a known resistance value. It is possible that this measurement is a source of error.
Another more deﬁnite source of error in both switching harmonics and DC level is the
minimum commutation time of a switch due to interrupt latencies. The algorithm used
will generate arbitrarily small pulsewidths which cannot be achieved with the
microcontroller. This will cause the switching period to be longer than expected,
decreasing the eﬂ‘ective switching frequency and therefore increasing harmonics. The
minimum commutation time will also cause phases with polarity opposite that of the
desired output to be commutated on for extended periods. The outcome will be a lower
DC component of the output. Figure 5.2(a) shows that the actual switching period is

approximately 550us compared with the desired switching period of SOOus.

Except for the problems mentioned above, the converter performed well during
low power testing. Variation of the relative voltage with power displacement 9, and
voltage utilization factor 7, agreed well with theory. Operation of the converter was
veriﬁed for changes in these parameters of the algorithm. Performance of the low
inductance bus with the seminatural commutation circuit topology proved exceptional.
No commutation induced voltage spikes were observed across the collector-emitter

terminals of the IGBTs and continuity of the load was maintained.

6.2 SUMMARY AND CONCLUSIONS

The converter developed performed well with the exception of the voltage output
magnitude and ripple. These problems may be greatly reduced by modifying the
microcontroller program to discard minimum pulsewidths. Switching to a given state
would then be skipped if the calculated pulsewidth was less than a predetermined value.
Both voltage output magnitude and ripple should improve with this modiﬁcation. A copy
of the microcontroller program used without the modiﬁcation is provided in Appendix A

as a reference.

Components of the prototype converter should allow its use for an input source
voltage of 208V and an output current of 20A. High power testing was not performed
due to both time constraints and lack of a suitable test load. The converter remains
assembled in the MSU Machines Laboratory. High power testing of the device could be

performed in the ﬁrture if a suitable load is obtained.

Another future development which would leverage the work performed in this
thesis would be the conversion of the device for four quadrant operation. The seminatural
commutation topology used would require that the power circuit hardware be duplicated
with the opposite current polarity. The only other component required would be a zero
current crossing detector to provide control logic between the positive and negative

current polarity devices.

65

66
The useful application of the direct AC-DC converter depends upon the load

providing ﬁltering of the switching harmonics. Future application of the device as a driver
for superconducting magnets used in nuclear experimentation was discussed in the
introduction. This would be an ideal application and could be pursued at the National

Superconducting Cyclotron facility on the MSU campus.

APPENDIX A

67

/*************************t#******************#************************/

/* */
/* Program 2PH_DFC.c */
/* */
/* */

/****#******¥**********#10!!!*********************************************/

/**********#*** Function Declarations ***************************/

int prt1__init (int tc); // initialize prtl
int tab(int a, ﬂoat A); // Pulsewidth for state AB
int tac(int b, ﬂoat B); // Pulsewidth for state AC

int tbc(int c, ﬂoat C); // Pulsewidth for state BC
int tba(int a, ﬂoat C); // Pulsewidth for state BA
int tcb(int 0, ﬂoat C); // Pulsewidth for state CB
int tca(int c, ﬂoat C); // Pulsewidth for state CA
void tabulateO; // Table Generator

/*******#************* Deﬁne GlOba] Variables **********,*****************/

#deﬁne TDEl 1 // PRT chl down-count enable bit
#deﬁne TIE] 5 // PRT chl interrupt enable bit

/************** Variables for Main and Output Functions ************/

static ﬂoat pi;

static int pwrnin;

static ﬂoat theta;

static ﬂoat AMPL; // DC output voltage amplitude

static int offset; // Column offset to toggle between zero state

static int j; // Counter timer

static struct tab { //**** Data structure of PWM times and states
char state; // Switching state

int widthAMPL; // Switching time for DC voltage

int widchero; // Switching time for Zero voltage

} table[240]; //**** End of data structure

68
lttﬁtt**#¢*************************************************************/

/* Main Program */

/**¥¥****************************************#*************************/

nodebug main(){

pi=3. 1416;
AMPL=O.99;
// DC voltage input
pwmin=10;
// Minimum pulsewidth
theta=-45 *pi/ 1 80;
// Input power factor
tabulate(); // Generate Switching Table
/*“‘* Set Port B for Output ***/
outport(PIOCB,Oxcf); // Set PIO B to mode 3
outport(PIOCB,OxOO); // Set all bits as output
/*** Set Port A for Interrupt ***/
outport(PIOCA,0xct); ' // Set PIO A to mode 3
outport(PIOCA,0x08); // Set only bit 4 as input
outport(PIOCA,PIOA_VEC); // Set interrupt vector
outport(PIOCA,0x97); // Enable interrupt for bit 4 low
outport(PIOCA,0xf7); // Mask bit 4 as interrupt
outport(PIODA,Ox08); // Write data to set bit 4 high

/*** Initialize time step counter ***/

i=0; /*** Note that later j will be loaded to register DE ***/
offset=1; /*** Column offset initialized to lst column m/

/*** Initilaize PRT 1 ***/
prt1_init(10); // switch timing interrupts

69

/**** Interrupt wait loop ***/

#asm nodebug

loop:

nop
jP 0,1001) ; loop and wait for interrupts

#endasm

}

/*******************************************#**************#*********/

/*

Deﬁne Pulsewidth Interrupt Service Routine */

/****************************************************************#***/

#INT_VEC PRT1_VEC pwm

#asm nodebug

pwmzz
di
push af ; save register pair af
push hl ; save register pair hl
push de ; save register pair de
ld hl,table ; load PWM switching table address to h]
ld de,(i) ; load time count to de
add hl,de ; add time count offset in dc to hl
ld b,(hl) ; load b with current switching state
outO (42H),b ; write switching state to P10 B
1d bc,(offset) ; load be with column offset to deﬁne voltage
add hl,bc ; add offset to hl
ld b,(hl) ; load b with current switching time
outO (14H),b ; load switching time to PRT] timer register
ld hl,04BOH ; load hl with table length
sbc hl,de ; subtract current position in table
jp nz,loopl ; if table length<>current position then jump
ld de,OOOOH ;* else reset current position for next cycle
jp loop2 ;* and skip incrementing position in de
loopl:
inc de
inc de
inc de ; increment de by length of data
element
inc de

inc de

loop2:
ld
inO
inO
Pop
Pop
Pop
er
reti

#endasm

70

(j),de ; save time counter value
l,(lOI-I) ;* read from TCR at 10H and
l,(l4H) ;* from TMDRIL to enable PWM timer

de ; restore de
hl ; restore hl
af ; restore af

; return from interrupt

/********#***********************************************************/

/* Deﬁne Synchronization Interrupt Service Routine */
/*********************#**********************************************/

#INT_VEC PIOA_VEC sag

#asm

sag: :
di
push
push
push
push
ld
ld
Pop
Pop
Pop
Pop
er
reti

#endasm

; disable interrupts
af
bc ; save registers
de
hl
de,OOOOH ; reset current position for synchronization
(j),de ; save time counter value
hl
de
bc ; restore registers
af

; enable interrupts

; return from interrupts

71

lttttt**********#****#*******************************************/

/* Deﬁne Port 1 Initialization Function */

/#¢*****#****¢¢**************************************************/

int prt1_init (int tc)

{
D10;
IRES (TCR, TDEl); /* disable count down */
IRES (TCR, TIEI); /* disable interrupts */

outport (TMDRIL, tc); /* set low byte of data reg */
outport (TMDRIH, tc >> 8); /"‘ set high byte of data reg */
outport (RLDRIH, to >> 8); /* set reload counter high byte value */

outport (RLDRlL, tc); /* set reload counter low byte value*/
ISET (TCR, TDEl); /* enable count down */
ISET (TCR TIEI); /* enable interrupts */
E10; /* enable interrupts */
}

/#***************************************************************/

/* Deﬁne pulsewidth time ﬁrnctions */
/***********************#**************#*************************/

/**¢******************#***t***#*******************/

/* Function: int ta(int k,ﬂoat gamma) */

/* Purpose: Computes vector A switching time. */
/#**************************************#*********/

int tab(int k,ﬂoat gamma)

{

int pw; // switching pulse width, output variable
ﬂoat t; // time for calculation

ﬂoat Ts; // switching period

/*** Set Switching Period to 1/80 of a power system cycle. ***/
Ts=384; // Set switching period to (I/60)/(20/9.216MHz)/40=192

t=k*(Ts/2+lO)*20/9216000; // Calculate
time

pw=ﬂoor((1+gamma*cos(2*pi*60*t +theta))*Ts/6); // Calculate
switching period for A phase

iﬂpw<pwmin) pw=pwmin;

retum<pw);
}

72

int tac(int k,ﬂoat gamma)

{

int pw; // switching pulse
width, output variable

ﬂoat t; // time for calculation

ﬂoat Ts; // switching period

/*** Set Switching Period to 1/80 of a power system cycle. ***/
Ts=384; // Set switching period to (1/60)/(20/9.216l\4Hz)/80=96

t=k*(Ts/2+lO)*20/9216000;
// Calculate time
pw=ﬂoor((l-gamma*cos(2*pi*60*t+4*pi/3 +theta))*Ts/6); // Calculate switching
period for B phase
iflpw<pwmin) pw=pwmin;
retum(PW);

}

int tbc(int k,ﬂoat gamma)

{

int pw; // switching pulse
width, output variable

ﬂoat t; // time for calculation

ﬂoat Ts; // switching period

/*** Set Switching Period to 1/80 of a power system cycle. "‘7
Ts=384; // Set switching period to (l/60)/(20/9.216l\/1Hz)/80=96

t=k*(Ts/2+lO)*20/9216000;
// Calculate time
pw=ﬂoor((1+gamma*cos(2*pi*60*t+2*pi/3 +theta))*Ts/6); // Calculate switching
period for B phase
iﬂpw<pwmin) pw=pwmin;
retum(l>W);

}

int tba(int k,ﬂoat gamma)

{

int pw; // switching pulse
width, output variable

ﬂoat t; // time for calculation

ﬂoat Ts; // switching period

73

/*" Set Switching Period to 1/80 of a power system cycle. ***/
Ts=384; // Set switching period to (1/60)/(20/9.216Ilez)/80=96

t=k*(Ts/2+lO)*20/9216000;
// Calculate time
pw=ﬂoor((l-gamma"‘cos(2*pi*60*t +theta))*Ts/6); // Calculate switching period
for B phase
itlpw<pwmin) pw=pwmin;
retum(PW);
}

int tca(int k,float gamma)

{

int pw; // switching pulse
width, output variable

ﬂoat t; // time for calculation

ﬂoat Ts; // switching period

/*** Set Switching Period to 1/80 of a power system cycle. ***/
Ts=3 84; // Set switching period to (1/60)/(20/9.216MHz)/80=96

t=k*(Ts/2+10)*20/9216000;
// Calculate time
pw=ﬂoor((l+gamma*cos(2*pi*60*t+4*pi/3 +theta))*Ts/6); // Calculate switching
period for B phase
iflpw<pwmin) pw=pwmin;
retum(pw);
}

int tcb(int k,ﬂoat gamma)

{

int pw; // switching pulse
width, output variable

ﬂoat t; // time for calculation

ﬂoat Ts; // switching period

/*** Set Switching Period to 1/80 of a power system cycle. ***/
Ts=384; // Set switching period to (l/60)/(20/9.216IVIHz)/80=96

t=k*(Ts/2+10)*20/9216000;
// Calculate time
pw=ﬂoor((l-garnma‘cos(2*pi*60*t+2*pi/3 +theta))*Ts/6); // Calculate switching
period for B phase
iflpw<pwmin) pw=pwmin;

74
retum(pw);

/**********************#******#********************************l

/"‘ Function: void tabulate() */
/***t**********************¥***********************************/
void tabulate()
{
int test;
static int i; // time step counter
static int Ts; // switching period
static char s_table[6]; // switching state table
s_table[0]='\xDB'; // state AB
s_table[l]='\xD7'; // state AC
s_table[2]='\xB7'; // state BC
s_table[3]='\xBD'; // state
BA
s_table[4]='\x7D'; - // state
CA
s_table[5]='\x7B'; // state
CB
/*** Generate the switching table ***/

for(i=0; i<240; i=i+6){

table[i].state=s_table[0];
table[i+ l ] . state=s_table[ l ];
table[i+2].state=s_table[2];

table[i].widthAMPL=tab(i/3, AMPL);
table[i].widchero=tab(i/3, 0);

table[i+1].widthAMPL=tac(i/3, AMPL);
table[i+]].widchero=tac(i/3, O);

table[i+2].widthAMPL=tbc(i/3, AMPL);
table[i+2].widchero=tbc(i/3, O);

table[i+3].state=s_table[3];
table[i+4].state=s_table[4];
table[i+5].state=s_table[5];

75

table[i+3].MdthAMPL=tba(i/3, AMPL);
table[i+3].widchero=tba(i/3, O);

table[i+4].widthAMPL=tca(i/3, AMPL);
table[i+4].widchero=tca(i/3, O);

table[i+5].widthAMPL=tcb(i/3, AMPL);
table[i+5].widchero=tcb(i/3, 0);

/*************¥*********** End OfZPH 2 C *****************************/

BIBLIOGRAPHY

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[2]

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[6]

[7]

[3]

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