"way «Var-i. ,1; .1mgmaqnnr...}1nHm: ' .H-i.» T3 “5931': 11*“ jg} ,! L, 'zjwtafgfiw
_-.:. 2, . - I24-1-Lw: _- E '.§..ili:1i' fig ””1, ’1'"- ‘iJIVP :
* !‘ M1‘*‘.t;=d’:»o‘ [' PM {12‘ {1? tit ‘66.; [tidy . “1“ ‘éfi:é '1' $3“? $1, ‘.. P.“ flip":

”th

.Iiu -.= 3 ‘ 30¢
ii"... {'1‘}. dfiflzm‘ . {rhlfiim -}£t
'. u‘i’l‘h ”If n l 1- .L H ‘ 1‘3 {Nah " ; i1. ‘
I; :' NW1"; 1 '. 7' JE§%%$51’*¥§
:7 ‘ :‘l ‘00. (“tlfiv‘i'fu'ah } . :ég‘vg Egg-g ’3‘
' ”it" lat fizofih‘i I 'kfiififi: ;: ‘gz‘flvéa‘, ”.1 g
.. k“,

1
I43?“ IF

, 0‘

31511111.: 41;, 1",":
’iszlé W. ';-‘I'}'I- :‘Wi,

vé NF)“. i“ LII-fat)

~ 7? 95“}:th .1 . ': Muir-1‘

$‘1"3.fl‘ i '< - , . ‘izslsv l: ,ug‘étL ”is“. 3‘ 1
1“ mu‘ur‘ -. 1; 5". 431.111“:
. ' . 4 :r '31),” g” N . ‘

K
Le

’34.

“It

3;. .

y.

u... .A.

52-. ~
‘.—.— .152

“13“;

4“!qu vw-rr
1112'..." ‘fi’fll
a.
'v ’IW-r‘ _
I ’ a-w

um. m-

m-n- ;3;
”may ‘
.
-.
.
..
2

.-:I_‘. g. 1}.
"IiI‘J

.._.
:1?"

,A. .n.

‘3’”.

.4

1
l ”‘d‘l‘ ling}! L
L a. h. V“ (.1... .‘ 2‘ I
t 5'“: .i‘ ' Mg. ”12% 1:392?“qu
“"3 141.1251 1:111 ‘ I’é" fgp, 9,911.1 1111; 111; .
h“ s I . u 1', I :g "“2
.9 :f!‘ '_!I‘k.h.§k xi Eidr‘ii‘i‘"'1fl"q}iié 2:1! 35- .‘

.4- s.—

9..
.3...

i

3-

253°

H
I

r

2

at”
N
a.

n 4 - I '-
v'J» N nah-Ir”

2..-...

1:24:

’3‘
m.
.....
".2: ..
.1 . .1”

-. taro
.-.‘_ub'

«- n;wfi;‘ =3:
- aria:

." :1]:

.5. 3.... ~ -, .- -
.... v». -
.‘_.4~vlv.-‘~

.2.

'r“
t’i

. .3

: I ,I 'V 3 ‘..‘ “!k’”!‘
“H'h” l: . :Ih:
’; ‘ _ ' ;: S1,;

. W
o

l [(f

l
. .3:
J

5,133“- ’- "2 |
5: iflififiwfim"
:‘Q‘i’fidé‘ -g I:

11:31: ’

*—<~p.—J—.m
w..— 9. -
_,,.. . .-
.4. NM
,9 A
an- -
._ g
.1

.7;

I'm
'."

- .-
,—

m
-
. ‘II
'D.‘
2 ”3"”
2.1.4:“? 1g: 3;,
.: 2 2% "’7'
. . , .1 .. .‘
" 2.. 1
~.

.. 1.2-4“...

 

39-9.--.

.’fi.—a
23.2

7.5;;0‘}
v
3....»- -
«J'LTS.
,1..- .

 

 

 

mm, IllIll/ll“!llllllllllllllllllllllllllllll

4 080 6125

     

 

 

.2
2? 3;: g: LIBRARY
Michigan State
University

 

 

This is to certify that the
thesis entitled
Amen/o OUTPUT STAGE FOR A Cmog
OPERATIONAL AMPL‘FlEK

presented by

mAN\St—t P. KAmAT‘.

has been accepted towards fulfillment
of the requirements for

{WASTE—K 0F SClENCEdegreein ELecmtcAL K

 

 

COMPUTER Elocer-‘Efi’rroq—

Vt/Z/

/ ”a Major professor/
Date [21/ fl / ?(/

0-7639 MS U is an Affirmative Action/Equal Opportunity Institution

 

 

 

PLACE IN RETURN BOX to remove this checkout from your record.
TO AVOID FINES return on or before date due.
MAY BE RECALLED with earlier due date if requested.

 

DATE DUE DATE DUE DATE DUE

 

AUG 'daUQWQ '41

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11m c-JCIRCIDmDuepss-p.“

A NEW

 

 

A NEW OUTPUT STAGE FOR A CMOS OPERATIONAL
AMPLIFIER

By

Manish Purushottam Kamat

A THESIS

Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

MASTER OF SCIENCE

Department of Electrical Engineering

1999

ABSTRACT

A NEW OUTPUT STAGE FOR CMOS OPERATIONAL AMPLIFIERS
By

Manish Purushottam Kamat

CMOS technology is dominant in the modern world due to its power efficiency.
Therefore Mixed-Signal ICs demand analog building blocks to be designed using CMOS
transistors. An operational Amplifier is one of the important analog building blocks. The
output stage of a CMOS Operational Amplifier presents a special problem in its design
for high output currents and rail-to—rail output voltage swings. This thesis presents a new
approach to design the output stage for a CMOS Operational Amplifier. Also presented in

this thesis is an instructional manual for Analog 1C Layout using a computer program

called LASI.

lwould like to
“odd also like
nicrstanding l
have done this i

Bandmpadh ya}

 

ACKNOWLEDGEMENTS

I would like to thank Dr. Gregory M. Wierzba for his guidance in the dissertation. I
would also like to thank Dr. Jacob Baker of University of Idaho, Boise, for his help in
understanding LASI. I would like to thank my parents without whose help I could not
have done this work in my Master’s degree. I would also like to thank my friend, Sruti

Bandyopadhyay, for her help in editing the figures in this dissertation.

iii

LBTOFTABL

 

UflOFHGl

1 INTRCH)[

1.1 IVRODL
I: BACKGR
U Basso

I

2 CONVExy
31 DGRODE
2.2 Mm;
23 Snu13g~

3AflWm

 

 

TABLE OF CONTENTS

LIST OF TABLES ................................................................................. vi

LIST OF FIGURES ............................................................................... vii

1 INTRODUCTION AND BACKGROUND“- - -- _- -- - - -- - 1

 

 

 

1.1 INTRODUCTION ......................................................................................................... 1
1.2 BACKGROUND .......................................................................................................... 2
1.3 THESIS OUTLINE ....................................................................................................... 2

2 CONVENTIONAL CLASS AB OUTPUT STAGE ....... 4
2.1 INTRODUCTION ......................................................................................................... 4
2.2 FUNCTIONING OF CLASS AB COMPLEMENTARY-PAIR OUTPUT STAGE ...................... 6
2.3 SIMULATIONS FOR CLASS AB COMPLEMENTARY-PAIR OUTPUT STAGE .................... 9
2.4 EFFECT OF RL ON THE OUTPUT VOLTAGE SWING ..................................................... 10

3 A NEW OUTPUT STAGE - -- -- 11
3.1 INTRODUCTION ....................................................................................................... 1 l
3.2 FUNCTIONING OF THE OLD OUTPUT STAGE ............................................................. 1 1
3.3 CURRENT STABILITY .............................................................................................. 14
3.4 A NEW OUTPUT STAGE ............................................................................................ 14
3.5 EXPECTATIONS FROM THE NEW OUTPUT STAGE ...................................................... 17

4 LEVEL 1 SPICE PARAMETER EXTRACTION FOR MOSFETS ................. 18
4.1 INTRODUCTION ....................................................................................................... 18
4.2 PARAMETER EXTRACTION FOR NMOS ................................................................... 18
4.2.1 Test circuit ..................................................................................................... 18
4.2.2 Extraction of K Fly and ano ........................................................................... 18
4.2.3 Extraction of GAMMA (21V) ........................................................................... 20
4.2.4 Extraction of LAMBDA (AN) .......................................................................... 21

4.3 TABLE OF LEVEL] MODEL PARAMETERS FOR NMOS ............................................. 22
4.4 PARAMETER EXTRACTION FOR PMOS .................................................................... 22
4.5 TABLE OF LEVEL] MODEL PARAMETERS FOR PMOS ............................................. 22

5 DESIGN OF THE NEW OUTPUT STAGE - - 23
5.1 INTRODUCTION ....................................................................................................... 23
5.2 CALCULATION OF MOSFET SIZES ......................................................................... 25
5.2.] Current delivering transistors ....................................................................... 25
5.2.2 Amplifiers for positive and negative half of the input signal ........................ 26

iv

5.3.3 F611;
.‘-.24 TM!
5.3 FRIQL'IS.
5.4 SPICE Sl.

 

5.2.3 Feedback circuitry ......................................................................................... 27

 

 

 

 

 

 

 

 

 

 

5.2.4 Two-stage OPAMP ........................................................................................ 29

5.3 FREQUENCY COMPENSATION .................................................................................. 31
5.4 SPICE SIMULATIONS .............................................................................................. 32

6 TESTING AND ANALYSIS OF THE OP-AMP CIRCUIT - - -34
6.1 INTRODUCTION ....................................................................................................... 34
6.2 TESTS ..................................................................................................................... 34
6.2.1 DC operating point and power dessipation .................................................. 34
6.2.2 DC characteristics ......................................................................................... 34
6.2.3 Frequency response ....................................................................................... 35
6.2.4 Output impedance .......................................................................................... 35
6.2.5 Common-mode rejection ............................................................................... 35
6.2.6 Power supply rejection .................................................................................. 35

6.2. 7 Short circuit current ...................................................................................... 36
6.2.8 Transient response ........................................................................................ 36
6.2.9 Capacitive loading ........................................................................................ 36
6.2.10 Change in the power supply values ............................................................... 36
6.2.11 Temperature dependence .............................................................................. 37
6.2.12 Harmonic distortion ...................................................................................... 37

6.3 ANALYSIS ............................................................................................................... 37

7 LAYOUT OF THE OPAMP - A AA 39
7.1 INTRODUCTION ....................................................................................................... 39
7.2 LAYOUT WITH LASI ............................................................................................... 39

8 CONCLUSION AND FURTHER IMPROVEMENTS - 40
9 APPENDIX A ------ AA A - - . A AA A A A _- A A -43
10 APPENDIX BAA A __ A -- ...... A .... A ......... AA57
11 APPENDIX C ...... _ ..... A AA A A AA A - 82
12 APPENDIXDA - A - AAAAAAAAAA A AAAAAA AA86
13 APPENDIX E A A -- 109
14 APPENDIX F A A A - - - A -- 112
15 BIBLIOGRAPHY _ . - 231

 

TABLE 11: IT
TABLE 3.1: Ti'
TABLE-1.1: Ll
TABLE 4.2; 11
TABLE 5.1: T
IABLE 5.2: T

TABLE 6.1: $1

 

LIST OF TABLES

TABLE 2.1: TRANSISTOR SIZES IN CONVENTIONAL OUTPUT STAGE ......... 9
TABLE 3.]: TRANSISTOR SIZES USED IN THE OLD OUTPUT STAGE .......... 12

TABLE 4.1: LEVEL 1 PARAMETERS FOR NMOS A- ...... - A21

 

 

TABLE 4.2: LEVEL 1 PARAMETERS FOR PMOS A A- - A - -A A A AA A 22
TABLE 5.1: TRANSISTOR SIZES IN THE OUTPUT STAGE A -- A AA A AAA-32
TABLE 5.2: TRANSISTOR SIZES IN THE TWO-STAGE OP-AMP -- - 33

 

TABLE 6.1: SPECIFICATIONS OF THE NEW OP-AMPAAAAA - - AA AA38

vi

 

F.g11e1.210ut_,
Figure 3.3: Sch.
Figure 2.4: Che?
Figure 3.1: Sch.I
551183.21 SCL‘.
Figure 3.3: Sch.
Figure 41: Test
Figure-11R}:
BETH? 5.1. Bl“
Figure 5.2; scu
Em 5.3; so.»
Figure 5.4: Sch-
Es’ire 8.1: Foi-
Fig-1138.1: V0}
Eg‘re 8.3. Ten
1:?qu “:31 In?
Figure All 01.".
Figure A}. 0111
29m: A4; 0U.
Fire. - .
Figure :2 gm
HELP A7 Sm
Figure ‘47: gm
Time A9 Sm
Rm «.1. ‘ in
Figure .410: Si
:EUTCAI‘I‘ Si
EQUIP. ' ~13:
F; A'Bl Si
Eire 3.]; M:

Figure 2.1: Sch}:

1:" ‘ '~‘
”633 \1..
li-‘A‘reB ‘ ‘
i MC

in» ‘~ -
1;“:lnB \
‘ ‘ li
J' \.
jphat . ‘
I
b I

 

LIST OF FIGURES

Figure 2.1: Schematic of a simple output stage ................................................................... 5
Figure 2.2: Output characteristics of the simple output stage ............................................. 5
Figure 2.3: Schematic of a conventional class AB output stage ......................................... 8
Figure 2.4: Characteristics of M4 in the conventional class AB output stage .................... 8
Figure 3.1: Schematic of the old output Stage ................................................................... 13
Figure 3.2: Schematic of the conceptual pseudo-source follower ..................................... 13
Figure 3.3: Schematic of the new conceptual output stage ............................................... 16
Figure 4.1: Test circuit for Level] parameter extraction for NMOS ................................ 19
Figure 4.2: Test circuit for Lele parameter extraction for PMOS ................................. 19
Figure 5.1: Block diagram of a simple feedback system .................................................. 24
Figure 5.2: Schematic of the new output stage ................................................................. 24
Figure 5.3: Source-degenerated Amplifier ........................................................................ 28
Figure 5.4: Schematic of the two-stage OPAMP .............................................................. 28
Figure 8.1: Folded Cascode op-amp .................................................................................. 41
Figure 8.2: Voltage Reference for Folded Cascode op-amp ............................................. 41
Figure 8.3: Temperature independent current source ........................................................ 42
Figure A]: Input file for PSPICE simulations. ................................................................ 44
Figure A.2: Output file with RLOAD of 50 ohms. ............................................................... 45
Figure A.3: Output file with RLoAD of 500 ohms. ............................................................. 46
Figure A.4: Output file with Rum) of 5000 ohms. ........................................................... 47
Figure A.5: Output file with no load. ................................................................................ 48
Figure A.6: Simulation plot ............................................................................................... 49
Figure A.7: Simulation plot (cont.). .................................................................................. 50
Figure A.7: Simulation plot (cont.). .................................................................................. 51
Figure A.9: Simulation plot (cont.). .................................................................................. 52
Figure A.10: Simulation plot (cont.). ................................................................................ 53
Figure A.11: Simulation plot (cont.). ................................................................................ 54
Figure A.12: Simulation plot (cont.). ................................................................................ 55
Figure A.13: Simulation plot (cont.). ................................................................................ 56
Figure B. 1: Measurement of KPN and V-mo for a small device. ........................................ 58
Figure B.2: Measurement of Km and VTNO for a small device (cont.). ............................ 59
Figure B.3: Measurement of Km and Vmo for a medium size device. ............................ 60
Figure B.4: Measurement of KPN and Vmo for a medium size device (cont.). ................. 61
Figure 8.5: Measurement of K»; and Vmo for a large device .......................................... 62
Figure B.6: Measurement of KpN and Vmo for a large device (cont.). ............................. 63
Figure B.7: Measurement of AN for a small device. .......................................................... 64
Figure B.8: Measurement of AN for a small device (cont.). .............................................. 65
Figure B.9: Measurement of AN for a medium size device. .............................................. 66
Figure B.10: Measurement of AN for a medium size device (cont.) .................................. 67
Figure B] 1: Measurement of AN for a large device .......................................................... 68

Vii

Figure 8.13: .\1
Figure 8.13: .\1
Figure 8.14131
Figure 8.15: .\1
Figure 8.16: .\1
Figure 8.17:31
Figure 8.18: .\1
Figure 8.19; .V.
Figure 8.20: .\1
Figure 8.21: 3‘.
Figure 8.22; .\‘.
Figure 8.23: 5'.
Egare82~1z M
figure C1: DC
58le C2: DC
5:311? C3: DC
Figure D1: D(
BET-'16 DZ: D('
Fume D3: D('
837116134: IX
Fl$1116 D5: D(
F1836 D6: D(
Figure D7; Fr:
FIE-ire D8. 1:1:
F1313 D9 0;.
Figure D10. C
Billie D11; ~
Figure D}:: F
Figure D13. F’.
Figure D14 Si

fl
— _-‘-’-

 

 

Figure B. 12: Measurement of AN for a large device (cont.). ............................................. 69
Figure B.l3: Measurement of Kpp and VTpo for a small device. ....................................... 70
Figure B.l4: Measurement of Kpp and VTPO for a small device (cont.). ........................... 71
Figure B. 15: Measurement of Kpp and VTpO for a medium size device. ........................... 72
Figure B.l6: Measurement of Kpp and V‘fpo for a medium size device (cont.) ................. 73
Figure B. 17: Measurement of Kpp and VTpo for a large device ......................................... 74
Figure 8.18: Measurement of Kpp and V‘rpo for a large device (cont.). ............................ 75
Figure B.l9: Measurement of hp for a small device. ........................................................ 76
Figure B.20: Measurement of hp for a small device (cont.). ............................................. 77
Figure B.21: Measurement of hp for a medium size device. ............................................. 78
Figure B.22: Measurement of hp for a medium size device (cont.). ................................. 79
Figure B.23: Measurement of 71p for a large device. ......................................................... 80
Figure B.24: Measurement of hp for a large device (cont.) ............................................... 81
Figure C.1: DC operating point for the new output stage. ................................................ 83
Figure C.2: DC operating point for the new output stage (cont.). ..................................... 84
Figure C.3: DC operating point for the new output stage (cont.) ...................................... 85
Figure D.1: DC operating point test. ................................................................................. 87
Figure D.2: DC operating point test (cont.) ....................................................................... 88
Figure D.3: DC operating point test (cont.) ....................................................................... 89
Figure D.4: DC operating point test (cont.) ....................................................................... 90
Figure D.5: DC transfer characteristics with no load. ....................................................... 91
Figure D.6: DC transfer characteristics with load. ............................................................ 92
Figure D.7: Frequency response with Cc = 10 pF ............................................................. 93
Figure D.8: Frequency response with Cc = 8 pF ............................................................... 94
Figure D.9: Output impedance. ......................................................................................... 95
Figure D.10: Common-mode gain ..................................................................................... 96
Figure DJ 1: CMRR. ......................................................................................................... 97
Figure D. 12: Power Supply Rejection Ratio (PSRR) for V35. .......................................... 98
Figure D. 13: Power Supply Rejection Ratio (PSRR) for VDD. ......................................... 99
Figure D. 14: Short circuit current. .................................................................................. 100
Figure D. 15: Transient Response for a 7V pusle. ........................................................... 101
Figure D. 16: Effect of capacitive loading (CLOAD = 100 pF). ......................................... 102
Figure D. 17: Effect of the change in the power supplies. .............................................. .103
Figure D.18: Effect of the change in operating temperature. .......................................... 104
Figure D.19: Effect of the change in operating temperature on the currents ............... 105
Figure D.20: Harmonic distortion for lKHz test signal. ................................................. 106
Figure D.21: Harmonic distortion for lOKI-Iz test signal. ............................................... 107
Figure D.22: 4.5 Vp-p output sine wave for lKHz test signal .......................................... 108
Figure E.l: Layout of the op-arnp. .................................................................................. 110
Figure E.2: Layout of the op-amp along with bonding pads. .......................................... 1 1]

viii

1 Introduction and background

1.1 Introduction

In the modern world, the CMOS technology is dominant over the bipolar technology
due to its several advantages in digital IC design. One of such advantages is reduced
power dissipation. Many times there is a need to fabricate analog circuit blocks on the
same chip that includes digital cirCuitry, thus giving rise to a mixed-signal system on a
single chip. In such situations, it is costly to combine both, the CMOS and the bipolar
technology, on a single fabrication run. Therefore there has been a strong attempt, in the
past few years, to design analog building blocks using only CMOS transistors. One of the
important analog building blocks is an operational amplifier. Designing an output stage
for a CMOS op-amp that delivers high output current and provides rail-to-rail output
voltage is a major challenge to an analog designer. Many ideas were proposed in the past
two decades to improve the performance of the CMOS output stage ([3], [7], [8], [9],
[10], and [11]). Most of the articles make use of the concept of a pseudo-source follower
amplifier in designing the CMOS output stage. This thesis presents a different topology
of the CMOS output stage but uses the concept of pseudo-source follower amplifier. Also

it makes a strong attempt to eliminate all the capacitors used in the previous output stages

that are generally incorporated to improve the frequency response.

12 Backgro

A course
l'nitersity, wax
were expected '
map posed
This created a

C1103 output .

13 Thesis

“it the
873861. Tnis
Chapter three
this thesis. 11 g.
the Ltt'cl 1 S
FACUIations. (
how the siZeg
Fe 511111113110:
Stage Op-amp

Show; the Ta

 

1 .2 Background

A course in CMOS Analog IC Design (EB 832), offered at Michigan State
University, was an important stimulant for the topic of this thesis. In this course, students
were expected to design a CMOS op.amp as the semester project. The output stage of the
op-amp posed many problems in achieving the required specifications for the op—amp.
This created an interest, by the author of this thesis, to conduct this research on the

CMOS output stage.

1 .3 Thesis outline

The thesis explains the design of a conventional CMOS output stage in the second
chapter. This chapter also explains the disadvantages of the conventional output stage.
Chapter three illustrates the design of the output stage in [3], which is the foundation of
this thesis. It also gives the conception of the new output stage. Chapter four shows how
the Level 1 SPICE model parameters are extracted from BSIMl model for use in hand
calculations. Chapter five explains in detail the design of the new output stage. It shows
how the sizes of the transistors and other components were calculated. Chapter six shows
the simulation tests conducted on the new output stage along with the accompanying two
stage op-amp. It also presents an analysis of the behavior of the op-amp. Chapter seven
shows the layout of the chip. Layout is performed using the software package called
LASI, which is an acronym for Layout System for Individuals. The Micro-electronic
research group at the University of Idaho developed LASI and it is free when used for
academic purposes. Chapter eight presents the conclusion and future research for

improvements of the CMOS output stage. The appendices contain all the simulation files

and pun-touts. .

larou: uszrtg 1..

 

and printouts. Also attached in the appendices is the instructional manual for analog IC

layout using LASI. A bibliography is presented as the last chapter in this thesis.

21 lntrodu

A simpip
he output of
sage needs u:
then ON and
Pair output st;

1’1

A Signif
tum‘entiona]
03:81" Stage
bliied SUCh ii
cum Due 1

Suffers from ‘1

 

2 Conventional Class A8 output stage

2.1 Introduction

A simple complementary-pair output stage gives unwanted crossover distortions in
the output of operational amplifier. This is due to the fact that the input to the output
stage needs to reach the threshold voltage of the current delivering transistors to turn
them ON and thus deliver current to the load. The schematic of a simple complementary-
pair output stage is shown in Figure 2.1 and its typical characteristics are shown in Figure
2.2.

A significant improvement over the simple complementary-pair output stage is the
conventional Class AB complementary-pair output stage. The key design part of this
output stage is the biasing of the current delivering transistors. These transistors are
biased such that they are not completely OFF in their quiescent state but conduct a small
current. Due to this, crossover distortion is greatly reduced. Nevertheless this output stage

suffers from a limited output Voltage swing that is 2V to 3V below the rail-to-rail voltage.

VDD

 

 

 

 

 

 

 

    
 

fi— NMDS
I—% PMDS
i—-
V88
Figure 2.1: Schematic of a simple output stage
vuur A
0 V _11. _ _ _

:\Crossover‘ Distortion
|

|

U V

1 +
VIN

 

 

Figure 2.2: Output characteristics of the simple output stage

2.2 Functioning of Class AB complementary-pair output stage

The schematic diagram of a Class AB complementary-pair output stage is shown in
Figure 2.3. The gate of M1 is biased at a certain DC level and M1 acts as a current
mirror. M2 and M3 act as constant voltage sources as long as M1 is in saturation. M2 and
M3 are diode connected NMOS and PMOS respectively and conduct current supplied by
the current mirror Ml. Therefore the voltages across their drains and sources remain
constant. M5 and M6 are current delivering MOSFETS connected in a common-drain
configuration (source follower). They are biased by the voltages across drains and
sources of M2 and M3 such that a small quiescent current flows through them when the
output voltage is at zero (Vom- = 0V). This is done to avoid the crossover distortion
problem in the output of the operational amplifier. Due to the common-source nature of
NMOS M4 and source-follower configuration of M5 and M6 the output is 180° out of
phase with the input.

When VIN starts rising in the direction of positive voltage, the gate drive of M4
increases and thus its conductance increases. Therefore the drain to source voltage of M4
starts decreasing. This is shown in Figure 2.4. This increases the gate drive of M6 and
M6 starts sinking more and more current through the load resistor as Vom goes in
negative direction. Finally a point is reached when M4 enters the triode region of its
characteristics and the output voltage changes in a non-linear fashion. A similar non-
linearity can be seen on the negative excursion of VIN. This non-linearity is due to M1

entering its triode region.

It is int;
case it occurs .
0:113th C1111:
due to .\11 e:
therefore the 1'

The to:
truthematieal

ortput range.

 

 

 

It is important to note that non-linearity in the first case is abrupt but in the second
case it occurs gradually. This phenomenon can be explained as follows. In the first case
only M4 changes regions but current in the branch does not change. In the second case
due to M1 entering the triode region, current in the branch changes gradually and
therefore the voltages driving source follower transistors change gradually.

The voltages at which the non-linearity creeps in can be found by doing a
mathematical analysis and an attempt can be made to determine the maximum linear

output range.

El

vy.“

A-“

FEW

 

VDD

 

 

v-BIAS It’- M1

 

 

 

 

 

 

 

p..—
F4 AEVDUT
2"
I;

 

VIN__ |:— M4

 

 

 

 

 

V33

Figure 2.3: Schematic of a conventional class AB output stage

 

 

 

 

 

ID A V635
V684
IDo fvsm
V638
f/vcm
VD:

Figure 2.4: Characteristics of M4 in the conventional class AB output stage

2.3 Simulal

Acome

 

1111111111U111CU1‘

hand calculat: .

Hand calculat;

llOSFETs us.

c(liftplertterttar'

 

2.3 Simulations for Class AB complementary-pair output stage

A conventional AB complementary-pair output stage is designed to deliver a
maximum current of +/- 25 mA. In the quiescent state M5 and M6 conduct 100 [LA in

hand calculations. It is assumed that the DC input voltage from the previous stage is -3V.
Hand calculations set the current through M1 at 1011A. Table 2.1 gives the sizes of all the

MOSFETS used in the circuit. SPICE simulations of the conventional class AB

complementary-pair output stage are shown in Appendix A.

Table 2.1: Transistor sizes in conventional output stage

 

 

 

 

 

 

 

MOSFETs Sizes (11111)
Ml 10.67/2

M2 19/2

M3 110.18/2
M4 2.77/10

M5 190/2

M6 1102/2

 

 

 

 

 

24 Effects

11 is Obs
aparticular so
116 can suppl;

“1131 11.;

 

interesting. \'
mm}: the chi
from 1116 plots
As 111 is a C

SUfficient you

2.4 Effect of RL on the output voltage swing

It is obvious that, as RL goes on decreasing the current required through it to attain
a particular voltage goes on increasing. There is a limit to the maximum current M5 and
M6 can supply. Therefore better swings are obtained for larger RL.

What happens to the currents flowing through M5 and M6 when R1, is infinite is
interesting. V3 follows V3 in the linear region of transfer characteristics. When RL is
infinity, the drain current of M5 should equal drain current of M6 in magnitude. It is seen
from the plots that for VIN = + 5V V954 is very small and M4 is deep in the triode region.
As M1 is a current mirror, a constant current flows through M1, M2, M3 and M4. Due to
sufficient voltage across the drains and sources of M2 and M3, M5 and M6 are ON and
are conducting equal currents of 151 HA. As VIN is reduced M4 slowly comes out of the
triode region and V934, V3 and V3 start rising. This makes Vsm reduce in magnitude
thereby reducing current through M1 by a small amount. This happens due to slope of the
MOSFET characteristics in the saturation region. As this current reduces V335 and V366
start decreasing and a point is reached when there is insufficient gate drive for M5 and

M6 to conduct and the current through them becomes zero.

10

2.1 V

- Jfi‘.‘”— .——_

31 Introd:

The res
Solid-State C
stage for CM

udosoure.
quiescent cur

the output 513

31’ Functil

The ou
Two amphfie
1161an “a
negative Titer

configurallor

131165 of the

 

 

3 A new output stage

3.1 Introduction

The research in the present thesis is based on a paper published in IEEE Journal of
Solid-State Circuits in January 1999[3]. This paper proposes a compact rail-to-rail output
stage for CMOS operational amplifiers. The output stage designed in this paper uses a
pseudo-source follower along with a conventional source follower. Controlling the
quiescent current in the driving transistors is a key design constraint. The schematic of

the output stage is shown in Figure 3.1.

3.2 Functioning of the old output stage

The output stage essentially works as the conceptual circuit shown in Figure 3.2.
Two amplifiers, Amp-P and Amp-N, are used to process the positive and negative half of
the input waveform. A negative feedback is provided around each amplifier. Due to the
negative feedback, the output impedance is greatly reduced. Due to the common source
configuration of the driving transistors, the output voltage can theoretically reach the
values of the supply voltages while still keeping the transistors ON.

The detailed functioning of the output stage can be explained from Figure 3.1 as
follows. The sum of the currents flowing through Mp2 and Mn3 should always be
constant as both currents flow into the current sink Mn5. When the input voltage at VIN
Starts going positive the gate overdrive of Mp2 reduces and that of Mn3 increases. This
increases the source to drain voltage of Mp6, which in turn increases the gate overdrive

0f Mp7. Thus Mp7 provides high currents to the load connected at the output of the stage.

11

Vom going positive increases the gate overdrive of Mp2 thus increasing the current
through it, which in turn reduces the current flowing through Mn3 thus providing
negative feedback. A similar action takes place when the input voltage is in its negative
half cycle. At this time Amp-N is active. Table 3.1 shows the sizes of all the transistors

and capacitors used in the old output stage. Transistor sizes are in urn/um.

Table 3.1: Transistor sizes used in the old output stage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOSFETs smut/11) MOSFETs Sizesm/p.) MOSFETs Sizes(ulu)
Mp1 115/5 Mn5 115/8 MnlO 65/8
Mnl 55/8 Mp6 60/5 Mp1 1 75/5
Mp2 115/5 Mn6 30/8 Mnll 60/8
Mn2 55/8 Mp7 1440/5 Mp12 75/5
Mp3 240/5 Mn7 1150/8 Mn12 60/8
Mn3 115/8 Mp8 190/5 Mp13 65/7
Mp4 125/5 Mn8 170/8 Mnl3 50/10
Mn4 55/ 8 Mn9 6/40 Ccl 3.5pF
Mp5 240/5 MpIO 120/5 Cc2 3.7pF

12

it“

’11-: - -~.A—.«
r

VIN

i
POSITIVE-HALF ERROR AMPLIFIER

NEGATIVE-HALF ERROR AWLIFIER

 

i
QUIBSCENT CURRENT
STABILIZATION CIRCUIT

Figure 3.1: Schematic of the old output stage

Amp-P I

VDD
I j VDUT
VSS

 

 

# . .J

 

 

 

 

 

>4

Amp-N

Figure 3.2: Schematic of the conceptual pseudo-source follower

 

 

i3 Cunent

aufhor has inci
and pulldowr
cutentdelive'

*tshold v01: .
@mgnxtol
al'OTded. For
E3116 VOTIClge (=1
the thin to s.'
3181111310 Fla".
Overdme 01 f
Clfluent. Map

Gm =¢

 

3.3 Current stability

In this circuit, quiescent current stabilization circuitry needs special attention. The
author has included this circuitry to take care of the random threshold voltages of pull-up
and pull-down transistors (Mp6 and Mn6). These devices are responsible for driving the
current-delivering transistors, Mp7 and Mn7. The author argues that a small change in the
threshold voltages of these devices may overdrive the current-delivering transistor thus
giving rise to a high quiescent current. With the added circuitry this situation can be
avoided. For understanding this let us suppose that Mp6 overdrives Mp7. Mp8 senses the
gate voltage of Mp7 and current in that branch increases. The increased current increases
the drain to source voltage of Mn9. When this voltage equals VTMpro-l-VTMnro both MnlO
and MplO fire-up and current in their branch grows tremendously. This increases the gate
overdrive of Mp12 and the gate of Mp7 is pulled up thus reducing the output quiescent
current. Mathematical calculations show that the current stabilization circuitry does not

let the currents in Mp7 and Mn7 rise beyond IQMAX where,

W
13. /L.
IQMAX = —g—9'xvrirpro xvii-LP); (3'1)
LMn(p)8

3.4 A new output stage

The new design is based on the same concept of pseudo-source follower but a
different topology is used to reduce the number of components in the output stage. Figure
3.3 depicts the conceptual design of the new output stage. The input voltage is applied at

VIN. Mnol and Mpol are positive and negative half amplifiers respectively. Both the

14

amplifiers me.
going posititc'
oterdnte oft
he amplifier
ieec'hack into

neg tire. The:

 

 

amplifiers make use of active loads made-up of current sources Ip0 and mo. As VIN starts
going positive the output of amplifier Mnol starts going negative thus increasing the gate
overdrive of the upper output transistor. Due to this Vom increases which is fed back to
the anlplifier Mnol through the controlled current source Ipl, thus bringing negative
feedback into the picture. A similar explanation can be given when the input starts going

negative. Then amplifier Mpol and controlled current source of Inl are operational.

15

 

MpXVDUT 1 1
t——
1 :}———VEUT

 

 

 

 

 

 

Inl:
M901 MnXVDUT

‘ Ll
VIN—i—IHJ “"0 30 :13

Figure 3.3: Schematic of the new conceptual output stage

16

 

 

3.5 EXP”

The first
thus the are:
eliminate the
of the output
uhch will b

reduce the ou

 

 

3.5 Expectations from the new output stage

The first objective to be achieved is the reduction in the number of transistors and
thus the area consumed. Also the author of this thesis feels that it is important to
eliminate the capacitors in the output Stage as they may degrade the frequency response
of the output stage for capacitive loading. The old output stage uses two capacitors,
which will be eliminated completely in the new circuit. An attempt will be made to

reduce the output impedance of the output stage.

17

4.1 Introd

The SF
damage of
mobilit) deg:
paruneters 11
These pm.

BSD“ 111on

42 Pararr

4.2.1 T951

 

 

4 Level 1 SPICE parameter extraction for MOSFETs

4.1 l ntroduction

The SPICE model that is being used in this thesis is called the BSIMl model. The
advantage of the BSIMI model over low-level models is that short-channel effect and
mobility degradation is modeled more accurately. In the BSIMl model values of Level 1
paramaers like threshold voltages, trans-conductance etc. are not specified explicitly.
These parameters are useful in hand calculations and therefore should be extracted from

BSIMI model using simple circuits and test signals.

4-2 Parameter extraction for NMOS

4. 2. 1 Test circuit

The test circuit used for the NMOS parameter extraction is shown in Figure 4.1.
Different Level 1 parameters depend on V95, V65 and VBS. For example, the threshold
Vohage of a MOSFET depends on VDS and V35 [4]. The effect of the three voltages on the
I-‘eVel 1 parameters depends on the size of MOSFETS. Therefore we have classified
MOSFETS as small, medium and large. Levell extraction is performed on MOSFETS of

all three sizes. The three sizes considered are 3u/2p. (small size), 1011/1511 (medium size),
SOP-’30}; (large size). The final values of the parameters are found by averaging the

Values for the individual device sizes. All the simulation plots are attached in Appendix

B.

18

F1.

 

 

 

 

VSB

NMDS +
F— “ VDS
+ *— —:l- 1 (vorioble)
+

 

 

I 1
<
m
U)
i
I
II}

Figure 4.1: Test circuit for Levell parameter extraction for NMOS

 

PMDS J _

-Ilh-.
_:£__JE:_——“_+ __ VSD
- +
VSG I VBS

 

 

 

Figure 4.2: Test circuit for Levell parameter extraction for PMOS

 

42.2 EXTFE

Agra

the DC turret

X ‘ 1111 tercel

This is the e
W“ by (4.
a“ not Straig
MOSFET “
aF'PFOximak.

The -
HV Cmge

 

 

4.2.2 Extraction of Km and Vmo

A graph of VID versus Vgs is plotted for different values of VDS. The equation for

the DC current through an NMOS device can be written as given in (4.1a).

 

 

W K
,/1,, = E g” (VGS-Vmo) (4.1a)
W K
810 e= — P” 4.1b
P L 2 ( )
X — int tercept = ano (4.1c)

This is the equation of a straight line with a slope given by (4.1b) and x-axis intercept
given by (4.1c). The plots are shown in Appendix B. It is obvious that the plotted lines
are not straight but are curved. This happens due to the change in threshold voltage of the
MOSFET with V95. Also the mobility of electrons in the channel changes with VDs. We
approximate the lower portion of the curve to a straight line and calculate Km and V10.

The average values of Km and VTo are written on the plots in Appendix B.

4.2.3 Extraction of GAMMA (7N)

Now that we know Vmo, if we change the bulk-bias we will see the VID versus
VGs curve intercepting the x-axis at a different value. The threshold voltage, considering

the body effect, is given by (4.2) in Level 1 SPICE model.

1N=ano+7/v(\/Vsa+¢ f) (4.2)

20

 

In (4.3) we R]

can calculate

 

42.4 Extra

lbs small-Si
l

I: ~

1.2..

“here ID is
resistance. \\
of Va; by F
resistance b}|

UMBDA t

4'3 Table I

Table l

 

 

 

In (4.2) we know the values of VTN, Vmo, V53 and {/2 (the flat-band voltage). Hence we

can calculate GAMMA (yN). Simulations are shown in Appendix B.

4.2.4 Extraction of LAMBDA MN)

The small—signal resistance of a MOSFET is given by (4.3) below.

1
112/1N

r:

 

(4.3)

Where ID is the DC current flowing through the MOSFET and r is the small-signal
resistance. We can obtain the small-signal resistance of a MOSFET for a particular value
of V55 by plotting ID versus VDS for that value of V05. Multiplying the small-signal
resistance by the DC bias current and then taking the inverse will result in the value of

LAMBDA (AN).

4.3 Table of Leve|1 model parameters for NMOS

Table 4.1 gives Level 1 model for NMOS.

Table 4.1: Level 1 parameters for NMOS

 

 

 

 

 

Parameters Value
V'mo . 0.8V
Km 37p.AN
GAMMA(7N) 0.7
LAMBDA (AN) 0.069

 

 

 

 

21

 

 

A simil

   

circuit is shox

4.5 Table

Levell

 

 

4.4 Parameter extraction for PMOS

A similar circuit as in Figure 4.1 is used for PMOS parameter extraction. This

circuit is shown in Figure 4.2. Simulations are shown in appendix B.

4.5 Table of Leve|1 model parameters for PMOS

Levell model for PMOS is shown in Table 4.2.

Table 4.2: Level 1 parameters for PMOS

 

 

 

 

 

Parameters Values

VTpo -0.85V

KP? lSttA/V
GAMMAO’P) 0.54
LAMBDA (11p) 0.05

 

 

 

 

22

5.1 Introdu

After it
an performei
elements con
feedback nett
circuits can t
Figure 5.1. F

i“ipedance.

We BA 1'
lhe System
5m“ (A) vat
R” an ind; .

MERLTI

 

5 Design of the new output stage

5.1 Introduction

After the conceptual understanding of the new output stage some hand calculations
are performed to design the individual elements of the output stage. The individual
elements consist of amplifiers for the positive and negative half of the input signal,
feedback networks and current delivering transistors. Each of the positive and negative
circuits can be simplified as a fundamental feedback system block diagram as shown in

Figure 5.1. For a system like this (5.1) and (5.2) give the voltage gain and the output
impedance.

 

 

G = l+fl4 (5.1)
_ 20
low — ”/34 (5.2)

Where BA is the open-loop gain of the entire system and 20 is the output impedance of
the system without feedback. Here we can see that if [3:1, having maximum open-loop
gain (A) will fetch us Gzl and Zour as small as possible. An attempt is made to make A

for an individual amplifier as high as possible. The feedback network is designed such

that [321. The schematic of the output stage is shown in Figure 5.2.

23

 

VBIAS-P

VIN

 

 

Gain = A

 

 

 

 

Feedback
Gain = 3

IOUT

 

 

 

 

 

 

 

 

 

 

Figure 5.1: Block diagram of a simple feedback system

tel L

oJ._

MFn3

 

 

 

 

 

 

 

 

 

 

 

 

lMp3‘ Mnl Mop
l‘ H MFnE I
._: Mf-‘pe 4| - VODUT
J‘ . J J:—
Mpl :1] Mn2 "—L‘ ”00
MFp3 CFJP_

 

VBIAS-N

 

Figure 5.2: Schematic of the new output stage

24

5.17“ .

h'l film "I.

 

52 Calcu

52.1 Curr

First
matimum CL
matimum w
NMOS at th
gate to sourc

V05 (V56)

 

II

 

5.2 Calculation of MOSFET sizes

5.2.1 Current delivering transistors

First attention is paid to the current delivering transistors. Set the target for the

maximum current delivered as 60mA and quiescent current as 300uA. Theoretically, the

maximum voltage that can appear across gate and source (V05 and V50) of PMOS and
NMOS at the output is 10V (VDD — V33). But from the author’s experience, maximum
gate to source voltage for both the transistors is a little more than half of the rail-to-rail.
V53 (V30) of 6V is assumed for hand-calculations and turns out to be close in the

simulations. Equations for the DC current through NMOS and PMOS are given in (5.3)

and (5.4) respectively.
W K

I Q = If!" (VGS _ V1702 (5-3)
W K

I Q = T'f’olso — VTP )2 (5'4)

After substituting the estimated voltages and the parameters from the Table 5.1 we obtain

the width to length ratios of the output transistors as given below.

 

l”. = fl (5.5a)
L Mon 5”

(W) = 4524,11 (55b)
L Mop Si“

25

 

 

The next step
have a quies:

we obtain fol

V63!“ :1.lt

VSG Mm : 10k

We have to

 

Bizsing volt‘
Simulations ;

Sizes are adj

The
cOllSisrs 0.
£3163 0f 3
the CmTe
mndfal

333on

them

M‘Dm

Ms.)

A

DC.

The next step is determining the biasing gate voltage required for both the transistors to
have a quiescent current of 300p.A. Using (5.3), (5.4), (5.5a) and (5.5b) for this purpose
we obtain following biasing voltages.

VOW, =1.168V (5.6a)

VSGMOP =1.06V (5.6b)

We have to make sure that the output of the previous stage is biased at these voltages.
Biasing voltages greater than these would result in more current. It is found from
simulations that these sizes of transistors cause more quiescent current. Therefore these

sizes are adjusted after doing the simulations.

5.2.2 Amplifiers for positive and negative half of the input signal

The positive amplifier consists of Mp1, Mp2 and Mp3 and the negative amplifier
consists of Mnl, Mn2 and Mn3. The input signal to the output stage is applied to the
gates of Mp1 and Mnl. The feedback circuitry provides inputs to Mp3 and Mn3 changing
the current flowing through them, thus providing a negative feedback. For the sake of
hand-calculations we assume that the quiescent currents flowing through Mp2 and Mp3
are of the same magnitude. The same rule applies to Mn2 and Mn3. Here we assume that
the DC current through Mp2, Mp3, Mn2 and Mn3 is IOuA and input voltage to the
output stage is 0V with respect to ground. Also let the biasing voltages at the gates of
Mp2 and Mp3 be 3.2V and for Mn2 and Mn3 it is -3.2V. Here we need to note that the

DC current through Mp1 equals the sum of the DC currents through Mp2 and Mp3. A

26

similar stater

(5.3:. and (S.-

(W) - I
K L 1,,“ ll
ll] 1
l— - —
\th,“ ll

 

 

similar statement holds true for the negative amplifier configuration. Use of the equations

(5.3) and (5.4) gives us the following values.

(BL) =__6# (5.7a)

L Mp1 100”

(Z) =_l_5-l.l_ (5.7b)
L Mnl 100/1

[K] {91.) = .128. (5.7c)
L Mp2 L Mp3 10”

(K) {K} = _5L‘_ (5.7c)
L Mn2 L Mn3 10”

5.2.3 Feedback circuitry

The feedback circuit is of special importance. It determines B for the system in
Figure 5.1. The feedback circuits for positive and negative amplifiers are nothing but
source-degenerated single transistor amplifiers. A simple source degenerated amplifier is
shown in Figure 5.3. As the resistors take a lot of space on the chip they are replaced by
diode connected transistors as can be seen from Figure 5.2. It is found from calculations
that if the source—degenerated amplifier is designed to have a gain of 0.33, the beta of the

circuit becomes unity. The equation of the gain for the source-degenerated amplifier is

given in (5.8).
Gain = -—g"'—'5D— (5.8)
(1+ ngS )

27

VDD

 

 

 

RD
VDUT
O: NMOS
____;;q VIN
RS
v
vss vss

Figure 5.3: Source-degenerated Amplifier

1933 “CD 9J3

MCCI

 

 

 

 

 

 

 

l—é’
CC VDUT

MR4 [1&3 "C t: rue
MR5 [17% MEAq—SaLJrfi—fllae ?

Figure 5.4: Schematic of the two-stage OPAMP

ET -
a: 9,5: Eat. pm

 

 

 

 

 

 

28

TWl

 

main fume:
and Plow-c
Offset Vol:
Consism 0

 

t1T‘u'lsl 310T:

in figure

b N. L

 

The sizes of the transistors used for source-degenerated amplifier are given below.

PK =7_# (5.9)
L prr 5.”

K _____15” (5.10)
L prz 100”

K) =££ (5.11)
L pr3 10”

=1 (5.12)

= fig (5.14)

l
] =95- (5.13)
l

5.2.4 Two-stage OPAMP

Two-stage op-amp is used to provide high gain for the whole op—amp circuit. The
main function of the output stage is to deliver high current, reduce the output impedance
and provide rail-to-rail voltage swing. The two-stage op-amp controls the voltage gain,
offset voltage and the slew-rate of the circuit. The two-stage op-amp in this design
consists of a differential amplifier followed by a cascode amplifier.AA simple voltage
reference is used to bias the current source of the differential stage and the cascode
transistors. The schematic of the two-stage OPAMP with the voltage reference is shown
in Figure 5.4. It consists of a voltage reference that biases the current source of the

differential amplifier and the loads of the cascode stage. We plan to have a total current

29

"Sffll

of 20m flowp
that we has-

I
cilierential s
l
transistors or

using (5.15)

Gain = ~

(“'1
\ julAIMLa
“left Iran:
10 is [he tot.
“Rode sta

affine leads

 

of 2011A flowing in the differential stage and SuA in the voltage reference. Let us assume
that we have a gain of 50 from the differential stage. It is always good to have a
differential stage with a low gain to avoid offset voltages due to the mismatches in the
transistors of the differential pair. We can calculate the sizes of the differential transistor

using (5.15) and are given in (5.16).

 

Gain =—2—-—* 3Y— *£fl- (5.15)
(AN +1?) L mums) In
[K] — £43. (5 16)
L mums) 10” '

Where transistor model parameters can be substituted from Table 4.1 and Table 4.2 and
ID is the total current flowing in the differential amplifier. We assume that the input of the
cascade stage is biased at -3V. From this information we can calculate the sizes of the

active loads in the differential stage. They are as shown in (5.17).

L szmzs) lot“

The size of the current mirror can be calculated by using the nMOS current equation. We
assume that the gate of the current mirror is at 3.2V. The size of the current mirror is

given in (5.18). Similarly (5.19), (5.20), (5.21) and (5.22) give sizes of the transistors of

the cascode stage.
L MCD My

30

 

   

[2‘1] =_35” (5.20)
L MCCl

10p
[K] =15fl (5.21)
L MCC2 10]!
(ll) :1”. (5.22)
L M18 10”

5.3 Frequency compensation

Frequency compensation is a very important step in op-amp design. This step
decides if the op-amp is going to be stable at all the frequencies by improving its phase
margin. [2] gives a method for compensating different kinds of OPAMPs. A capacitor of
10pf is used to compensate this OPAMP as shown in Figure 5.4 This capacitor creates a
dominant pole. A negative zero, which can be troublesome, is also developed as a side
effect. In order to eliminate this zero a resistor is added in series with the capacitor. The
value of the resistor can be calculated by using (5.23), which is also given in [7].

1
Z = 1
CC " RC
gmlB

This resistor is replaced by an nMOS device in the actual design, which is biased in the

 

(5.23)

 

triode region.

31

,_ a
ma-“Ti(.r .. I ..

5.4 SPICE
l

Table
sizes of the
with these 51
sizes were at

circuit is she

l

l

 

In“? LI

 

 

5.4 SPICE simulations

Table 5.1 gives the sizes of MOSFETS in the output stage and Table 5.2 gives
sizes of the MOSFETS in the two-stage op-amp. PSPICE simulations were performed
with these sizes of MOSFETS to check operating points of individual elements and the
sizes were adjusted to get the appropriate results. The operating points for the simulated

circuit is shown in the output file in Appendix C.

Table 5.1: Transistor sizes in the output stage

 

 

 

 

 

 

 

 

MOSFETS Sizes (um! um) MOSFETS Sizes (um/pm)

Mop 1437/5 Mn3 5/10

Mon , 577/5 pr1 7/5

Mpl 6/ 102 pr2 15/ 100
Mp2 15/10 pr3 4/10
Mp3 15/ 10 anl 7/ 10

Mnl . 18/102 an2 6/10
Mn2 5/10 an3 6/5

 

 

 

 

 

 

32

Table 5.2: Transistor sizes in the two-stage op-amp

 

 

 

 

 

 

 

 

 

 

 

 

 

MOSFETS Sizes (um/11m) MOSFETS Sizes (um/um)
MR1 8/10 M2B 3/ 10
MR2 8/10 MCD 35/ 10
MR3 4/11 MCCl 35/10
MR4 4/1 1 MCC2 45/ 1 0
MRS 3/9 M18 5/ 10
MIA 104/10 MC 4/27
MlB 104/10 CC 10pf
M2A 3/10

 

33

 

 

6.1 lntrod

Now
characteristt '
test results a

Orderasthe

6.2 Tes

62.1 DC

(almost 261‘
“Hit in

about the 0

6.2.2 D

OPAMP ii

“sz111 a}:

are ShOWn

6 Simulation-based Analysis of the op-amp circuit

6.1 Introduction

Now that the circuit is designed it is necessary to test it for its different
characteristics. We can use different test methods for measuring PSRR, slew-rate etc. The
test results are shown in Appendix D. The files attached in the appendix are in the same

order as the test described in this chapter.

6.2 Tests

6.2.1 DC Operating point and power dissipation

As can be seen from the output file the DC output voltage for zero input is -0.03V
(almost zero). Therefore the input offset voltage is almost zero. Power dissipation of the
circuit in the quiescent operating state is 6.45 mW. The output file also gives information

about the operating regions and the currents through each transistor.

6.2.2 DC characteristics

In this test, the differential signal is swept from —5V to 5V and the output of the
OPAMP is observed without any load connected to it. The output voltage is non-linear
without any load but becomes more nearly linear by connecting a resistor. Both the cases

are shown in the attached probe output.

34

’i-‘IM-

 

6.2.3 Fre

In t
frequencie:
gain of thz
margin is l

of Spf. the

624 Co

In t
Ollipm of (
"Olfige 501
the outpur

6.2.5 (:0

In
an AC Sig
2310, C03

[Cl-NR .

612.6 p:

 

tare ..

ta.

6.2.3 Frequency response

In this test the output of the opamp is observed for an AC exitation at different
frequencies. Gain curves and phase curves are plotted and it is found that the Open loop
gain of the OPAMP is 86.7 dB, the cross over frequency is 1.147 MHz and the gain

margin is 63°. The dominant pole is at around 40-50 Hz. With a compensation capacitor

of 8pf, the cross over frequency becomes 1.35MHz and phase margin 53°.

6. 2.4 Output impedance

In order to calculate output impedance, an AC voltage source is connected to the
output of OPAMP and the inputs are gounded. A plot of the ratio of the value of the
voltage source and the output current is plotted in the probe output file. It is observed that
the output impedance is resistive till nearly lOKHz. The value is 15 ohms and this is very

low as compared with other op—amps.

6. 2. 5 Common-mode rejection

In order to calculate the common-mode gain both the inputs are tied together and
an AC signal is applied. An ideal OPAMP is supposed to have a common-mode gain of
zero. Common-mode gain of this circuit is —0.35 dB. Also common-mode rejection ratio

(CMMR) is 87dB.

6. 2. 6 Power supply rejection

In this test the inputs of the circuit are grounded and one of the power supplies is

made variable by including an AC voltage source in series with the supply voltages. It is

35

.8.” ‘

‘II

 

seen that the

(VDD and Vt
6.2.7 Shor

A 18
measured \\

on the posit:

Irar

Califid the II

6.29 Ca;

The

I
he 0m131.11 .

Iii.

en;

f
0f po‘Wer

 

seen that the power supply variation gain is around 6-7 dB for both the power supplies

(V DD and V58)-

6. 2. 7 Short circuit cunent

A large amplitude sin wave is applied to the input and the output current is
measured with a small load (5 ohms). It is found that the short circuit current is +79 mA

on the positive side and —95 mA on the negative side.

6. 2.8 Transient response

Transient response is a little distorted and the slew-rate is 2V/us. This test is

called the transient response and is conducted by giving a large step input to the circuit.

6. 2.9 Capacitive loading

The effect of capacitive loading is observed by connecting a 100pf capacitor at
the output and plotting the frequency response. This test should not give any peak in the

response.

6.2. 10 Change in the power supply values

The power supplies are varied from +/-5V to +/-10V and the output
characteristics are plotted in PROBE. It is observed that the characteristics are distorted

for power supplies other than +/-5V.

36

"ruv ..

 

62.1 1 Tem

The

plotted. It '

temperature

6.2. 12 Ha r

T1311 3

 

peak Volta;

 

using two I.
the Simula:
“‘31 the to:

 

6.2.11 Temperature dependence

The temperature is swept from -20°C to 50°C and the DC characteristics are
plotted. It is observed that a small off-set is developed due to the change in the

temperature.

6.2. 12 Harmonic distortion

Transient analysis is performed using a sine waveform of lKHz frequency and
peak voltage of 0.45V. The OPAMP is put into a non-inverting feedback configuration
using two resistors such that the non-inverting gain is 10. A fourier statement is added to
the simulation file to find the harmonic components of the lKHz test signal. It was found
that the total harmonic distortion produced by the op-amp was 0.058%. A similar test was

perforemed using a test signal of 10KHz frequency and a peak voltage of 0.45V.

6.3 Analysis

It is seen that there is a scope for improvements in the frequency response and the
transient response. Also the power dissipation is not reduced as was expected. Power
dissipation is highly dependent on the quiescent current in the output stage. By reducing
this current a lower value for the power dissipation can be obtained. Transient response
depends on the power dissipation of the differential stage. As this power dissipation
increases the transient response improves because more current is available to charge the
compensation capacitor. These issues must be looked into while designing a better
OPAMP with the new output stage. Specifications of the designed op-amp and its

comparisn with the old op-amp are given in Table 6.1.

37

 

 

 

 

 

Table 6.1: Specifications of the new op-amp

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Specifications With old output stage With new output stage
Power dessipation 4mW 6.45mW
Rail-to-rail voltage +/- 4.6V +/- 4.45V

Open loop gain 78dB =87dB

Phase margin 65° 63°
Unity-gain frequency 0.8MHz 1.35MHz
CMRR - 87dB
PSRR - 6-7 dB
Short circuit current 60mA +79mA and -95mA
Slew-rate 8V/us 2V/ps
Harmonic distortion (lKHz) -70dB -l9dB
Output Impedance 1582
Area 0.65 mm2 0.3 mm2

 

 

 

38

 

 

7.1 lntror

layer.
process 3.11

example if

 

voltage rna
Oil-Set vo‘;

IEChniques

12 Lay

 

 

 

7 Layout of the OPAMP

7.1 introduction

Layout of analog integrated circuits needs a special care as the parasitic effects and
process gradients affect analog circuits far more than they affect digital circuits. For
example if the two transistors of the differential pair are placed far apart, their threshold
voltage may be mismatched giving rise to an off-set voltage in addition to the systematic
off-set voltage [7]. This type of unwanted effect can be minimized by proper layout

techniques.

7.2 Layout with LASI

Layout of this chip is performed by using software named LASI. The Micro-
electronic Research group in University of Idaho has developed this software. It is
available on-line and free when used for academic purposes.

Individual transistors and capacitors were laid out as cells of rank one and larger
circuits were developed by using these cells. Thus a method of hierarchical layout was

used. The layout is shown in Appendix E.

39

 

An (
tn[3] we!
response 2
were com
voltage sit
0f460 0hr

h w-
Cascode C
thereby n
tmnsistors
illC meUe
15mg a V1
Vohage re
Voltage re
be PTOVid

in the ref

 

a IOIdeG‘

freqUEm‘

 

8 Conclusion and further improvements

An output stage with fewer components and more current delivering capacity than
in [3] was designed but power dessipation increased. The slew-rate and the transient
response are not satisfactory. The two capacitors that were used in the old output stage
were completely eliminated without degradation in the frequency response. Output
voltage swing is not significantly improved. The new output stage can drive a resistance
of 460 ohms [3].

It was found that the transient response could be improved by including a folded
cascode OPAMP (Figure 8.1) instead of a two-stage OPAMP to drive the output stage,
thereby reducing the value of the compensation capacitance. Also the sizes of the
transistors in the output stage need to be redesigned to adjust the poles and the zeros in
the frequency response. Current mirrors of the folded cascode stage can be biased by
using a voltage reference circuit given in [5] and is shown in Figure 8.2. Use of this
voltage reference makes all the current mirrors in the circuit have a wide swing. The
voltage reference of Figure 8.2 needs a temperature independent current source that can
be provided by a circuit given in Figure 8.3. Use of this circuit minimizes the variations
in the reference voltage due to the changes in temperature. One more advantage of using
a folded cascode amplifier is that it improves the power supply rejection and makes

frequency compensation easier.

4O

”45:13]” E SE]
12:1 Cr 3,
STE I _ 1
:i l
VINA—L— VINB V83 ]_—DUT

.__. VB]

*‘1
l 1 1J
1%: :Pl

Figure 8.1: Folded Cascade op-amp

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1t VDD
Vp/Lp Vp/Lp

[Ht—4H1 -——|t— Vp/Lp
Wp/4Lp VB4
d: :pr/Lp *— ‘ V83

__,L_,_J.__ __l:—(‘)p/Lp

Wn/4Lrt_. .___ VFW/Ln
—EI lit—— vea
I Q
P -
—1 H
(fL Vn/Ln I? Wn/Ln
v v v 'vss

 

Figure 8.2: Voltage Reference for Folded Cascode op-amp

41

4xV/L

L5__l

 

 

 

 

LL;

it
L
if

.flLJW

Figure 8.3: Temperature independent current source

42

9 Appendix A

SPICE simulations for the conventional class AB output stage

43

""""*"AB-PUSHPULL OUTPUT STAGEitittttwtitii'
""TAKING INTO CONSIDERATION BODY EFFECT*"'*‘*'

‘****'POWER SUPPLIES AND BIAS VOLTAGES'**‘****"‘
VDD 7 0 5V

V83 4 O ~5V

VBIAS-P 6 0 3.7V

VBIASN 1 0 -3V

'*"'**‘MOSFETS AND OTHER COMPONENTS*********"*’

M1 5 6 7 7 CMOSP W=10.67U L=2U
M2 5 5 3 4 CMOSN W=19U L=ZU

M3 2 2 3 7 CMOSP W=110.18U L=2U
M4 2 1 4 4 CMOSN W=2.77U L=lOU
MS 7 S 8 4 CMOSN W=19OU L=2U

M6 4 2 8 7 CMOSP W=1102U L=2U

«sour 8 o 500 4——— at Mew;
U

*iifiifitittfiMOSFET MODELStttfiiiititifiiitfitfitifitiit

.MODEL CMOSN NMOS LEVEL=1 VTO=O.8 GAMMA=0.S LAMBDA=0.05 KP=50U PHI=O.6
.MODEL CMOSP PMOS LEVEL=1 VTO=-0.8 GAMMA=O.5 LAMBDA=0.05 KP=15U PHI=O.6

itiiifitfifitTEST SIGNALSQQG‘tfifiiittitfiflitfifiiitiittti

.0?
'.DC VBIASN -5 S 0.1
“.PROBE

ataattaaatEND OF SIMULATIONttttttitttifiiiiitttttt
.END

Figure A.l: Input file for PSPICE simulations.

44

Rour’ = 50:].

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( 1) -3.0000 ( 2) —1.7458 ( 3) .0097 ( 4) -S.0000
( 5) 1.8182 ( 6) 3.7000 ( 7) 5.0000 ( 8) .0013
"*‘ MOSFETS
NAME M1 M2 M3 M4 M5
MODEL CMOSP CMOSN CMOSP CMOSN CMOSN
ID -1.16E-05 1.16E-05 -1.16£-05 1.16E—05 1.458—04
VGS -1.30E+00 1.818+00 —l.76£+00 2.00E+00 1.828+00
VDS —3.18E+00 1.818+00 -1.76E+00 3.ZSE+00 S.OOE+00
VBS 0.00E+00 -S.01E+00 4.99E+00 0.00E+00 -5.00E+00
VTH -8.00E-Ol 1.SOE+OO -1 59E+00 8.00E-01 1.608+00
VDSAT —S.OOE—01 2.128—01 -1 618—01 1.208+00 2.218—01
GM 4.64E-OS 1.105-04 1.448—04 1.938-05 1.318-03
GDS 5.008-07 5.322—07 5.33E~07 4.99E-07 5.79E~06
GMB 1.SOE—OS 1.168—05 1.53E—OS 6.248-06 1.38E-04
CBD 0.00E+OO 0.00E+00 0.00E+OO 0.00E+00 0.00E+00
CBS 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGSOV 0.00E+00 0.00E+OO 0.00E+00 0.00E+00 0.00E+00
CGDOV 0.00E+00 0.00E+OO 0.00E+00 0.00E+00 0.00E+00
CGBOV 0.00E+00 0.00E+OO 0.00E+00 0.00E+00 0.00E+00
CGS 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGD 0.00E+00 0.00E+00 0.00E+OO 0.00E+OO 0.00E+OO
CGB 0.00E+00 0.00E+OO 0.00E+00 0.00E+OO 0.00E+00
NAME M6
MODEL CMOSP

ID —1.18£—04
VGS -1.75E+00
VDS -S.OOE+00
VBS S.00E+OO
VTH -1.60E+00
VDSAT —1.SlE-01
GM 1.562-03
GDS 4.74E-06
GMB 1.658-04
CBD 0.00E+00
CBS 0.00E+00
CGSOV 0.00E+00
CGDOV 0.00E+00
CGBOV 0.00E+OO

CGS 0.00E+OO
CGD 0.00E+00

CGB 0.00E+00

Figure A.2: Output file with RLOAD of 50 ohms.

45

RON ’ 573011.

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( 1) -3.0000 ( 2) -1.7458 ( 3) .0097 ( 4) -5.0000
( 5) 1.8182 ( 6) 3.7000 ( 7) 5.0000 ( 8) .0059
"" MOSFETS

NAME M1 M2 M3 M4 M5

MODEL CMOSP CMOSN CMOSP CMOSN CMOSN

ID -1.16E-05 1.16E-05 -1.16E-05 1.16E-05 1.388-04
VGS -1.30E+00 1.818+00 -1.76E+00 2.00E+00 1.BIE+00
VDS -3.18E+00 1.813+00 -1.76€+00 3.ZSE+00 4.99E+00
VBS 0.00E+00 -S.OlE+00 4.99E+00 0.00E+00 -S.01E+00
VTH -8.00E-01 1.6OE+00 -1.59E+00 8.00E-01 1.60E+00
VDSAT —S.00E-01 2.12E-01 -1.6lE-01 1.208+00 2.16E-01
GM 4.64E-05 1.10E-04 1.44E-04 1.93E-05 1.28E-03
GDS 5.00E-07 5.32E—07 5.33E-07 4.99E-07 5.53E-06
GMB 1_503-05 1.16E-05 1.53E-05 6.24E-06 1.35E-04
CBD 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CBS 0.00E+OO 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGSOV 0.00E+00 0.00E+00 0.008+00 0.00E+00 0.00E+00
CGDOV 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGBOV 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGS 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGD 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGB 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
NAME M6

MODEL CMOSP

ID -1.26E-04

VGS -1.7SE+00

VDS -S.01E+00

VBS 4.99E+00

VTH -1.6OE+00

VDSAT -1.S6E-01

GM 1.628-03

GDS 5.06E-06

GMB 1.71E-04

CBD 0.00E+00

CBS 0.00E+00

CGSOV 0.00E+00

CGDOV 0.00E+00

CGBOV 0.00E+00

CGS 0.00E+00

CGD 0.00E+00

CGB 0.00E+00

Figure A.3: Output file with Rm“) of 500 ohms.

46

NODE VOLTAGE NO DE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( 1) —3.0000 ( 2) -1.7458 1 3) .0097 ( 4) -S.0000
( 5) 1.8182 ( 6) 3.7000 ( 7) 5.0000 ( 8) .0090
* " " * MOSFETS

NAME M1 M2 M3 M4 M5
MODEL CMOSP CMOSN CMOSP CMOSN CMOSN

ID ~1.16£-05 1.16E-05 —1.lGE-05 1.16E-05 1.34E-04
VGS ~1.30E+00 1.81E+00 -1.76E+00 2.00E+00 1.81E+00
VDS -3.1BE+00 1.81E+00 -1.7GE+00 3.25E+00 4.99E+00
VBS 0.00E+00 -S.OlE+00 4.99E+00 0.00E+00 —5.01E+00
VTH -8.00E-01 1.608+00 -1.59E+00 8.003-01 1.6OE+00
VDSAT -S.00E-01 2.12E-01 -1.61E-01 1.ZOE+00 2.128-01
GM 4.64E-OS 1.1OE~04 1.44E-04 1.93Ee05 1.26E-03
GDS 5.008-07 5.328-07 5.33E—07 4.99E-07 5.368-06
GMB 1.50E-05 1.168-05 1.53E-05 6.24E-06 1.33E-04
CBD 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CBS 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGSOV 0.00E+00 0.00E+00 0.00E+00 0.00B+00 0.00E+00
CGDOV 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGBOV 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGS 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGD 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGB 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
NAME M6

MODEL CMOSP

ID -1.32E-04
VGS -1.7SE+00

VDS -S.OlE+00
VBS 4.99E+00
VTH -1.6OE+00
VDSAT -1.6OE—01

GM 1.65E-03

GDS 5.28E-06

GMB 1.7SE-04

CBD 0.00E+00

CBS 0.00E+OO

CGSOV 0.00E+00

CGDOV 0.00E+00

CGBOV 0.00E+00

CGS 0.00E+00

CGD 0.00E+00

CGB 0 . 00E+ 0 0

Figure A.4: Output file with Rm“) of 5000 ohms.

47

Roof = 0051.

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( 1) -3.0000 ( 2) -l.7458 ( 3) .0097 ( 4) -5.0000
5) 1.8182 ( 6) 3.7000 ( 7) 5.0000 ( 8) .0095

"" MOSFETS
NAME M1 M2 M3 M4 M5
MODEL CMOSP CMOSN CMOSP CMOSN CMOSN
ID -1.16E-05 1.16E-05 -1.16E-05 1.16E-05 1.33E-04
VGS -1.3OE+00 1.81E+00 -1.76E+00 2.00E+00 1.81E+00
VDS -3.18E+00 1.81E+00 —1.76E+00 3.ZSE+00 4.99E+00
VBS 0.00E+00 -5.01E+00 4.99E+00 0.00E+00 -5.01E+00
VTH -8.00E-01 1.60E+00 -1.59E+00 8.00E-01 1.60E+00
VDSAT -5.00E-01 2.12E-01 -1.61£-01 1.20E+00 2.12E-01
GM 4.64E-05 1.10E-04 1.44E-04 1.93E-05 1.26E-03
GDS 5.00E-07 5.32E-07 5.33E-07 4.99E-07 5.32E-06
GMB 1.50E-05 1.16E-05 1.53E-05 6.24E—06 1.33E-04
CBD 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CBS 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGSOV 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGDOV 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGBOV 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGS 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGD 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
CGB 0.00E+OO 0.00E+00 0.00E+00 0.00E+00 0.00E+00
NAME M6

MODEL CMOSP

ID -1.33E-04

VGS -1.768+00
VDS -S.OIE+00
VBS 4.99E+00
VTH -1.59E+00
VDSAT -1.60E-01
GM 1.66E-03
GDS 5.32E-06
GMB 1.75E-04

CBD 0.00E+00
CBS 0.00E+00
CGSOV 0.00E+00

CGDOV 0.00E+00

CGBOV 0.00E+00

CGS 0.00E+00

CGD 0.00E+00

CGB 0.00Et00

Figure A.5: Output file with no load.

48

fl; ‘IOQOI'IOOGOAB_PUSHPULL omm STAGEOQOOIOCIQOCOOI

Date/Time run: 07/09/99 18:49:48 Temperature: 27.0

(A) ABPUSHPULL1.dat

 

 

 

     

 

 

 

 

 

i ____________________________________________________________________________
:1 1.2V] 2 30M'1 3 8.0VT a.
l 3 I
i f VIN: -3.2021v. vour: .735v E
1 ; -352V. . roa sour: so onus ;
' 0.8v1 ZOmA- I I
6.ov~ I
0 av IOmAA I I
ov1 0A4 4.ov{ 4 2
-o.4v« -10ma1 f 5
2,0vi =~2.7979v vour: -.704v I
-0.8V< -20mx« E f
5 .—1.08v 3
>>: :
-1.2v-‘ -30mA4 ov+- ---------------- . -------------------------------------- a ------------ 4
-5.ov -4.ov -2.ov ov 2.0V 4.0V 6.0V

0 v18) [2 - mmsi . ID(M6) v17) - V(Sl

varxsu

Date: July 09. 1999 Page 1 Time: 19:07:39

Figure A.6: Simulation plot.

49

 

I) .1 .......'...AB‘PUSHPULL ompm STAGEOOOOOOOOQOIOOI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Date/Time run: 07/09/99 19:17:17 , Temperature: 27.0
I (A) ABPUSHPULL1.dat
1] 2.0v1 2 5.0111» 3 e. ' -------------------------------------------------------------- 7
. F013. 4901” fans}. :
l I
3 I
1 :
1
1 1.0V W' s
1 6. :
0v. : .
ox< 4.ov{ - s 1 4. e s: .
-1.ov
l ; vrzii=-2.85v. v1u=-1.425v -
2.0vi
-2.0V(
J J >>j
~3.ov -S.OrnA ov+ —————
-6.0V -4.ov -2.ov ov 2.0V 4.0V 6.0V
E) 13 V18) [2 I ID(MS) . ID(H6) [E] vt7) - v15)
1 _ VBIASN
Date: July 09. 1999 Page 1 Time: 19:23:15

Figure A.7: Simulation plot (cont.).

50

Date/Time run: 07/09/99 19:24:08

‘

#6-

..IIOQItQOOAB-PUSHPULL OUTPUT STAGEIOI'IQOI'tttI.
Temperature: 27.0

 

 

 

 

 

 

 

 

 

 

 

 

I (A) ABPUSHPULL1.dat 3
. i
:1 4.0V1‘ 2 600%]. 3 8.0V‘T """""""""""""""""""""""""""""""""""""""" 1
’ F09. Rev? .: suoo cum; :

I I "

; 3 400m»: 1
i I l a “
3 ; : ; ‘
1| 2.0V41 ' 6.0V“ |>
Q 200uA1 .

F 7 i I
1 - ,

; 1 .i
ov~ OA‘ 4.0V« 1

. 1i

5 1 :l
% —200uA- : N=-2.85V VOUT=-1.866V fl
. ‘1 ‘ ' ' .a

r f ’L/ w
-2_0v4 2.0V‘ . . . . . l. . . . . . . . . A . . . . . . . . ’1

‘i

‘ . ‘*?\\~1~_____;_*y____ . . H

-400uA+ ; ’ 8 O'SGMA w

>>T ' : ._

-4.ov« -600uAd ov-» ----- -———————<<1 -------- , ------------ Y ------------ r ------------ 1 ------------ u
-6;_qv -4.ov -2.ov ov 2.0V 4.0V 6.0vé

:lJ o V(8) [:j - ID(MS) . ID(M6) [i] a V(7) - V(5) ;

VBIASN 1

Date: July 09, 1999 Page 1 Time: 19:28:50

Figure A.8: Simulation plot (cont.).

51

 

h‘

 

 

A 7
littttt'tttAB_PUSHPULI-‘ OUTPUT STAGEO'i'iQIIDOIOCi
Date/Time run: 07/09/99 19:36:36 Temperature: 27.0
’ (A) ABPUSHPULL1.dat .

 

4.0v‘ 200uA1 8.0V+ --------------------------------------------------------------------------- N
- OUT: ‘2
vouw=2.53y-VIN=-3.1sv ’9“ R °° .

151.7UA

  

1
I :
2.ovJ 100uA1 6.0V4

‘ , VIN: -,2 . alsv VIN=—1..96V

l —2.0V~ —100uA« 2.ov§

 

l
|
l
I

 

 

 

 

 

,

 

j >>;
-4.ov ~200uAJ 0V4— ..... '
-6.0v -4.ov -2.ov ov 2.0V 4.0V 6.0V
0 we) [2] a 10045) 0 ID(M6) a V(7) - V(5)
‘ VBIASN
Date: July 09, 1999 Page 1 Time: 19:41:10

Figure A.9: Simulation plot (cont.).

52

.10
H tttififitl'tIAB_PUSHPULL OUTPUT STAGEitfitQ'tfiiiiti'
Date/Time run: 07/13/99 12:54:41 Temperature: 27.0

q (A) ABPUSHPULLl .dat

 

 

    
  
    
 
  

 

 

 

 

 

 

 

 

 

 

 

l1 zoom» 2.2v 0A+ --------------------------------------------------------------------- 1
2 3 . - . .
1 ' \ Curvt-AE Human. ~12. stem decvuma .
Z-OV‘ ; VIN = -3.15v
100nm «mu '
1.8v« 7 FOR R00? = INFINITY. 2
0A~ -auAJ I
I'GVT I VIN = -4.16v, . ~ 2
-100“. . . . . . = :
1.4V« V . . .
KEV: —2.9v ' ‘ ' fi‘ ' i
-2oomulJ 1.2vJ ‘v ------------ v ------------ r---- --------- . ------------ 4'
-6.0V -4.ov -2.ov ov 2.0V 4.0V 6.0V

0 mum o mom [2] - vm - we) . we) - V(2) a mun)

vamsn

Date: July 13, 1999 Page 1_ Time: 13:07:49

Figure A.10: Simulation plot (cont.).

53

 

 

X.

 

”4... . Tutu-0...! ,. .ml!
5

 

 

.OOOtOQiItOAB_PUsHPULI-' OUTPUT STAGEIGIICCO..OOQCt

Date/Time run: 07/13/99 12:54:41

 

 

 

(A) ABPUSBPULLl.dat

Temperature: 27.0

 

 

    
  

 

 

 

 

 

 

 

 

 

Date: July 13,

1999

Figure A.11: Simulation plot (cont.).

54

9 . ..................................................................... 1
11 8.0V 0A 3 4.0V? —\ _‘
g 7 . vm: -3.1sv vouw: 2.5466V . ‘
7 Li
I . . 4
. I ' l
i i :-
‘ ' 'l
6.ov~ 2.0v4 W i}
. ll
! l -SuA4 I
FM: «Tao-v- : 903;” :
4.0w ov~:
i ‘ vm: .-2.848V vou'r; -1.978V 3
~10uA« fl

2.0V1 -2.ov{
i = -2.85v :
. as omuc REGION .
ovJ -15uA« -------------------------- . ------------- , ------------ , ------------ 4
-6.0V -4.ov -2.ov ov 2.0V 4 ov 6.0V

[1] o vm - VlS) . mom 1:} a vm

vans»:

Page 1 Time: 13:18:03

 

 

ll “;

litififiiilI'AB,pUsHPULL OUTPUT STAGEQOOOOII'QOOOO'
Date/Time run: 07/10/99 14:07:59 Temperature: 27.0

(A) ABPUSHPULL1.dat

 

: 8.0V-r """"""""""""""""""""""""""""""""""""""""""""""""""" l

l

l

i \ V0543 6.1232V 1L

\ / I

: \\ l

l ~‘ I :0 R T I 5:-

I 6.0V“ . f . . . . K .OU / j
1 l
l

I I

l ' | 1

l .

. 1
2.0V{ . . . . . . . VDSSAT4= 0.967V . . . . . . . . . . . . J

 

 

 

ov+ ------------ r """"""""""" r ------------- v ----------- 1 ------------- V -------------- 4
-6.0V -4.0V -2.0V 0V 2.0V 4.0V 6.0V!

0 V(2) - V(4) i

VBIASN i

Date: July 10, 1999 Page 1 Time: 14:22:08

Figure A.12: Simulation plot (cont.).

55

A :3
OOII'DiI'.CAB_pUSHPULL OUTPW STAGEOOOOIOOCQIIQOI

Date/Time run: 07/10/99 14:40:18 Temperature: 27.0

i (A) ABPUSHPULL1.dat ?

' l

60m 1- ----------------------------------------------------------------------------------- ’

i
l
l

Sko't (\'(‘,\;\' (uv'flr‘k
' RWT'HIL

25.88 ma

 

 

Date: July 10, 1999 Page 1 Time: 14:44:02

Figure A.13: Simulation plot (cont.).

56

10 Appendix B

Extraction of LEVEL 1 SPICE parameters

57

Date/Time run:

'TEST CIRCUITS FOR DIFFERENT TRANSISTORS
03/27/99 19:00:29

Temperature: 27 . 0

 

S H N
a

a a 3

L---—--_-_-L---___---_L--_-------L----------L----------

a
3

a
8

04
0V

 

SQRT<ID(N1))

(D) tuttranaiatora .dat

24m-— -------------------------------------------------------------------

W/L- 30/20
. VBS!- OV. .
spon- SQR‘NK’_ l/ZL)
'(pu‘: ‘31.5-¢19
yt—
ano I- 0-3"

 

snopz- 5.635 3-1 ’45“; if”
‘———————————fiyrw’ ,

,'
r v,
of r '
a, ,‘ ,
I]; I r’
If! I I
, , .

,{282' snopa- 5.37 2-3

. ’t,”” ’ .
Ir,’ '
4?;5"«sbopsn 5.317 3-3

[1"

a
I
I
t
I
o
a
u
a
I
. . u -d
f .
VDS- 5V.-
,. y, '
1:3,," . ’.
yr 1 J'-
' v' I,"
f,“ V _/
o _, "/-'
.-"T-' J ‘ /"
”in" ‘
. ’r
,4' _ .
.l' ’7‘ /

-_-----------_---_--------_----__----------J---------

b .
c

 

Date: March 27.

1999

Time: 19:10:11

Figure B.l: Measurement of K»; and V-mo for a small device.

58

 

'TEST CIRCUITS FOR DIFFERENT WSISTORS
Date/Time run: 03/28/99 13:02:35 Temperature: 27.0

 

 

 

 

(D) teattranaietore.dat
20m7n------------------------—----------------------------------------------------------------------------'
: u/L - sum)
. - VDS -sv ‘ .
; vsa - 2v ,1
smpx- scams" u/zz.)
: K»; :ao-‘l'fl .1 ,, 2
15m; . . . . Vt. . . . . . . . . . . . . . 'o”IJ'- :
I 1’ = 0.67...
: N . . . ‘ (V': '1’9’.“ 7' --/ :
l J ' VDS. 1v 1
I VTN ‘3 "3V' I
I , i
510st 5.54 3-3,:,':::"':."’ 2
10ml . . [2’73"- . :
: /’/’//’,’: a
I ,1 1 ". ‘
1 /’ I», 1’ :
. snore: 5.656 3-3 ”0:1 ,t .
: ///’/’//I z
I . // /’I .
: /// z

I / , . ._
5m: 40.1, § PE,5.465 3.3
; //;f’ :
l // / I
: , /q.ovz- 5.4 2-3 :
I // I
u ., ./ :
: /"’// c
: 4/ .
I ’(c'.,’-’ :
0 ¢ j ‘M ' . - r —:
1.0V K 2.0V 3.0V 4.0V 5.0V

somummn =1.3\I
VIN vcs

Date: Ketch 28. 1999 Page 1 Time: 13:07:54

Figure B.2: Measurement of Km and Vmo for a small device (cont.).

59

 

'TBST CIRCUITS POE DIFFERENT TRANSISTORS
Date/Time run: 03/28/99 12:52:23 Temperature: 27.0

 

 

     
     
 

 

 

 

(C) teattranaiatorn.dat
15m7-------------------o----------------------------------------------—-----------------------------------7
1 WI. -1ow1su. /'
l vns - ov vos - 53:55:),
SLOPI - SQR'NK" wax.) ~ - - /,
3 Km ‘ 3“-“3I:.9. - . - i
I V L f;’-./ _V..r ’1 t
I VT... ' 0.8“. v ' ' . i
10”.; . . . . . . . /_,:
: '4’; ’,/ :
: - “,5; 12‘: ”1.1”" vos - 1v ;
: “317$: " ’.1,""’ i
: ’ -/"’ :
. swpz- 3 437 3-3 , ”’ .
Sad: 7.45 as- 3.386.2-3-
l I
I i
i “'0' pr:- 3.291 3-3 I
—~—~ / -—+ ——«—~ -— —~—~-——~ ~ ——
~5m+ ------------------- '1 ------------------ 1 ------------------- r ------------------- r -------------------- 4
W 1 av 2 av 3.0V 4 av 5 av
soarunmin
vcs
Date: March 28, 1999 Page 1 Time: 13:01:08

Figure B.3: Measurement of Km and Vmo for a medium size device.

60

 

'TEST CIRCUITS FOR DIFFERENT TRANSISTORS
Date/Time run: 03/28/99 13:10:22 Temperature: 27.0

 

 

     

 

 

 

 

 

(E) teattranailtore.dat

15mI."‘-"‘"""'""’""'-"'°"""""""”’"""""'"""‘"""'""“‘“‘""“”"‘"""""‘"""’°“‘I
I I
: i
; rm. - IOU/150 .1:
i vs: .- 2v (g:
I VDS 3 5V ,;i::” a
: K»: '= 3?- El‘. 4’5""
: vb .”."’. :
: u :32 :
10nd . . . . . . . . . . . . . . . . . . . 191:". u
I ‘ o v 25311.", I
: VT" ‘ 11$ swpe- 3.523 3-3 ;
l ,"”' " ‘/’o
| . .', ,w” .
i ”2.3. l,,/" I
.1 " -//./'vns - 1v
I [’4’ ’ ,«’ g
: 4‘43” /"/ i
2 .4239 r’/ I
3 , thi’ ,.// .
I ’6’”, '/."/ o
: swpz- 3.622 2-3 J: . . ;
5m: 2' :
i I
i ., I
' we“ I
I ,fl‘f o
I -', :
: "530%- 3.425 8-3 ;
I I
I I
: I
I I
0; I JCT W Y ‘ " r I.
ov 1.0V 1 2.0V 3.0V 4.0V 5.ov

-< soarumun) Vm=l~"5"

VGS

Date: March 28. 1999 Page 1 Time: 13:16:24

Figure 8.4: Measurement of Km and Vmo for a medium size device (cont.).

6]

 

.i? : 4 . : I _ ‘
r
.i .

'TBST CIRCUITS FOR DIFFERENT TRANSISTORS
Data/Tim run: 03/28/99 13:47:35 Temperature: 27.0
(I) tuttraruintorndat

 

E
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

 

I I
I I
I I
I I
I ,I
: NIL - 500/300 :1
I "I
; vs: - arov .~: :
20m 4 . . . . . . . . . . . . . . . . . . . . . . '4 . .1 1
' Km - 37. 81M . -
I - ‘ .13 ," . ' I
. n — . - a ’,'l'.’ I" a", I
I V‘ ,-‘."' 4 ' I ""‘ '
I Iv..".’ f, ' I
I ' ' ' ' ,ffi'," I
- Vmo ‘> 03V .
I .‘g'fl' .-" I
' O . I ‘4l'a.‘-' :’ I
I '. I." -‘ I
16" J \: I
' I

I ' [,r ”'I
' "’ I
g ,_ I
I , ,. I
I ' c5331." ' - ' I
' spon- 5 285 a 3 "’/ '
I ' - ”'l"ltl”o ’rr/ .
I $101..” ”I” ’4’ .
I ’._: t ,. ,’ .
J ." .,/" I
12” . “n: . "/' I
. :',’:" “/0, I
I ' 1. i.' ' (r '
I ,1]? ,.-" I
I ,ngII/ _,/” I
. . {L'I' I”, . l
. swpz- 5.3 9 2-3 ,Isg. .
- :4". .
: ' c.7313.” :
am .I . . “(ff/1" . . . I
. awlmpz - 5.137 2-3 .
I J11"- ' I
l I ’I,”'I‘ e I
I fli” I
I ,:;;" I
I 45"," I
I “‘9' I
I 1,0’ I
| A‘s” I I
I " I
J I
In , ,
l I
I I
I I
I I
I I
I I
. I
I I
I I
— . ————-- - — -—re—~~ -, ’—»«— ~ ~-—~——--~——»—l

 

O‘I' , .. -_._,_,_ ‘1

0V

fif I’

1.0V 2.0V ' 3.0V I I.ov s.ov
somuznuun vm.:o.8v

"* II\

 

 

 

Date: March 28. 1999 Page 1 Time: 13:52:06

Figure B.5: Measurement of K»; and Vmo for a large device.

62

'TBST CIRCUITS FOR DIFFERENT TRANSISTORS

 

 

 

 

 

 

Date/Time run: 03/28/99 13:52:23 Temperature: 27.0
(J) testtrmiatorl . dac

2mT"-----------~--------—-------~------------------~-------------------—--------—-----------------------.
I i
: II/I. - soc/30b ;
; vs: - 2v ,3;
20m4 . . . . . .‘,;:::.I
: K9” 3 364 pa- ,3;, :
I . V; I 4,3,}: "’ lz/JI
a I’ = mu; - 3 v :
16m; - VT“ = I. 3{?8.v x. I
I ”a I
I .5:::’:" I /’1
: ,3;;3109: - 5.566 3:3/3’ ;
: ,3;: _ ,// :
I 4”."1’ ’ ‘/, :
12“, J] . . . . . ”.137; »’ . .g///.’“ . :
. SLOPE = 5.727 2-3 , ,r-I’ .
i " I
i :
I I
saw: :
I I
i I
l I
: 1
«a: :
I I
i I
I I
: :
0+ - — —-—— r - 4
0V 4.0V 5.0V

" SQRTiID(H1)I

VGS

Date: March 28, 1999 Page 1 Time: 13:58:02

Figure 13.6: Measurement of K»; and Vmo for a large device (cont.).

63

 

Data/Till. run: 03/27/99 18:26:23

'TEST CIRCUITS FOR mm TRANSISTORS

Tamaratuta: 27 . O

 

   

 

 

 

 

(C) taattramiatorednt

250m7-~----------------~--,-v---------------~13»----—----------------------------~-------------------7
. 35:33 noon: onseoox‘ , . .
; INL- 30/20 ' . " ;
. apdxrzou- (rm-mnnm' (vnsz-vnsn .
; VSB- 0V / . _ ~I :
I A 7. Oc”‘{ . VGS {Eff
: LAHBDA- .osagjflw -4 """ .
200“ J. />"_5"'f"" . :
: ,2,» f'” ’ :
I ,r’”// . u
: /’ ,- , ‘
: ‘ ,. / vas . 3V .3 .:
150M-: - - 9’ ,4 LAMBDA- .0666J.____ .- ~ -.-~-’- T” ‘1' ;
1oou4 / mm- .0325 j, - —47 ~ -3- ‘ ' 'v
E I’ll’l'lf :1. I E
I ,5!" / m- .109 _ -_ .'_.—- ~—~ ';
sou... ’I-QJI'.‘ / . J -__ —r----~ . . I
: [95; /, .3 ********** " . :
i i/fx‘.’ / . . .
I ,1 mm- 166 VGS’ L5" 1
: :
~M ' flm—rfi - - - if: - _ 7 z: — _' .— __Y"_ . __ _ .34.. _: ‘ _ A___‘.—. -.’ ’ _;—._’— T’. _- _;_ "'T;'.—_'- .. — “4
av 1.0V 2.0V 3.0V 4.0V 5.0v

'— mun)

vns

Data: larch 27. 1999 Page 1 Tina: 18:33:43

Figure B.7: Measurement of M for a small device.

64

 

. .
1e ..:

.n'n

1..

.5
.(.
6-."
x
\l
a

 

 

. 9

t...

'TEST CIRCUITS roa DIPPBRBNT TRANSISTORS
Data/Tina tun: 03/27/99 18:36:36 Tamparatura: 27.0
(B) taattranaiatora.dac

 

33m noon: on? m J” :

u/L - 30/20 . ’1/ - . :

m - 2v " EEWION - (ID2-ID2)/ID1.(VDsz-VDSI)I . WW

2 - 0443‘! ,,, . I W I" ”in ' E

ZOOuA [3. ,g' , , . . 933391: ‘95}3h.fi,7, ' .__’H E
I I ‘ ,.,_ 4.. / ., Mr-” ,.-,_.- E

E
\

i\

\
------_---------------_--

100m: ”'"

VGS. 2.5V
// 1" l I . A- M. '
LAHBDA .1457 ‘-,_. -- -- ~‘“ ‘ .
5M 0 . . . - a I Wg'fl . . . . . :
/ 1,..—--—'- I
I, ,’/”<—-—‘ I
' vcs- 2v 1
'. . . mm- .2637 ;__________*__,,_v..._..,...~~--~~—~ -- ;
-W—M—fi-W |
I

r “.3. .. .—_ .33: 4:;53223::'1"“ “7.." 22:3”. _ :. ..-.-__~ _;_ __ #:2172sz " ‘f— " g T'::T; 5;.-. HT... .__’ L-’ A. I. ’.‘;:~1:;_;—;.l.‘____{
1.0V 2.0V 3.0V 4.0 5.0V

 

3
c

U <+ ---.--------L---—--------J------o---'-----_------L------------

ID(I1)

 

 

Data: latch 27. 1999 Page 1 Tina: 18:48:52

Figure B.8: Measurement of km for a small device (cont.).

65

 

 

 

 

 

1:2.)

 

"PEST CIRCUITS FOR DIFFERENT TRANSISTORS

Unto/Til. run: 03/27/99 18:50:39

Tamparatura: 2‘7 . 0

 

    

 

 

 

 

 

 

 

 

 

 

(C) taactranaiauaradat

15MT""-"'-""""'"""""'""""""""""“"""::_'_",‘.'«""""""""""°“'""""""""
: 33m: cuos 300:: ,1/ "’ ’ ;
l/L- 10011511 "
1 vsa- 0v , :
E 3: 0.04:} / / 5
100054: . , r,./’
1 / vss- 3.5V _
i / MD» .0305 I inflammwwwr—w ‘“' “W” :
: I «L'“’" '— ,__. . 2
: x 3
I ' / mm: .0016 V -/ 1 1 , - 1.. - -11 _ .__.:
sous-E /’ - , : - . :
: mm- .007 __ ____ __ h _;
l '. '_‘_.___~___.'._—————""-—’_ —.—_——' I
I MDA- .0517 VGS' 3V :
1 z'nmnn- _055 vcs- 1.5V :
0 _‘_ 7 _ , I _ - .. _.__..._. _ _._ -___.M ."___....1_. . ,_ - .._ -____.___._~____'
| I
-m ~ —~ — 1 r —r -=»- ~—- -~"*-*-------t
0v 1.0V 2.0v 3.0V 4.0V s.ov

" 10011)

E

Data: latch 27. 1999 Paga 1 Tina: 18:59:01

Figure B.9: Measurement of M for a medium size device.

66

 

3:: 7;:
R

t'.

. 1
I”.

'An_
In“.

If.
v

 

 

 

 

'TBST CIRCUITS FOR 01m TRANSISTORS
Data/Tina run: 03/28/99 13:16:56 Wratura: 27.0

 

 

 

 

 

 

 

 

 

(P) taatttanaiatora.dat
150M - --------------------------------------------- p- ------------------------------------------------------
I / |
I I, g
: 381113 3501331.: cues BOOK ;
I ' ‘1' '
; H/L - IOU/150 /' i
: 2 I 00 o“‘ / ‘_,.,,--7—~- -.. n+4 __._.. -:
/ “fl“ ______
I ' / ' Mg’wflflfl i
I I/ fry!” ,
: I K‘r/fl’ :
: , , If” . . :
100M .0: . . . . . '3’ . [,5/ E
: ./ /_./ VGS I 4V 1
I ‘ ' _ M
. / LAMBDA .031,” '__#__~_,H__,_,. ‘
: / ’_ ,. ”I’M” :
: , ~ 5“ :
I l ” ,
I ,’ I: I
: , ,' :
I ,' " ’ I
: ' " ' mm - .0023 ___,,_._.__.' —-7—~7-»~7-«—- -- -;
I ’I' / #:-H_.—-- _H_______.,_..——-———-—' M..— '
5011A1 ’ ' / - " ” J - - I
I / / , I I
: , , . ’ :
E f:",/ mm - .0059 M _V _____ _____.__“__
; "f ,’ fl _, g 1,- - - ,_.--~»*-————~_ ”'“—‘““" :
I I. I’ / I- I
: xiii!" xxx}. :
: /§’l-’/ .- ' ' um - .0532 ' “35.3.11“ .
I '{’:// 1" 7__— _ __-_— ________‘___ _ _ ._ _______« _.____ _ ___‘_ .
‘ 47/ ’l -v/ '
' .2"? I ”1” ‘ I
; y’j- mm - 0656 V68 ' 2.v '
I /’ —-—-—-*—*~" ' """‘—“" *"“"-"""“ ' ““"“",
0A 7 V V Y I
W 1.0V 2.0V 3.0V 4.0V 5.0V
0 IDlll)
VDS
Data: latch 20, 1999 Paqa 1 Tina: 13:29:05

Figure B.10: Measurement of In for a medium size device (cont.).

67

 

 

 

 

1M2;

\.....

Date/Tine tun:

'TEST CIRCUITS FOR DIFFERENT TRANSISTORS

03/28/99 13:34:14

Temperature: 27.0

 

300uA

200uA

100uA

n---—-----_—------L-----------_..-----l

   

0V

 

33133 MODEL: couos aooxf’ , "
w/L - sou/300 /’
vsa - 0v _£ //
') {0.th ' ’ ,’ '
rl. /’
/ . *- - ”J.” --_

/ ’47wr_,,4

 

3 IDiHl)

(G) testtzanaiators.dat

350m 7 ------------------------------- , ----------- ----------------------------------------------------------

LAMBDA I .0439

' .0434

m” ' -_99.99.--_1_--__-._I,_ .-

 

-._4—~*

 

'
:3 I I '____ ___._ i é__'__ F '~— '_'. — ~ ‘H .1
i. ,‘ I ~/ 77 - — r W'—“
'7 'r'.’ / /"
lfi' /' vcs - 1 5v
:;"/,.--" LAMBDA - .056 . '
. ‘.‘>/"_ _-- _ ._ ._ _ ,__ AA,_———- ~— ____.—__.__— ————- _____.__.__-—...4_-_ --
-0“ —;- r-..-_a-_1.- 12:-n ' - t‘..LY.‘?—.L". .31.:Irz-u-a.a.msx=::r::r—=n snag-u" nun-.3. u-_._v—_;—'-‘--1 '. 77- . a: x - _ _ ~ ' -..>..-‘..- _ ";M$‘.:"‘. '
5.0V

2.0V 3.0V

A.-----_--.o_-—-_-

 

 

Date: larch 28.

1999

Page 1

Time: 13:40:54

Figure B.ll: Measurement of AN for a large device.

68

 

é’l

 

 

'TBST CIRCUITS FOR DIM TRANSISTORS
Date/Tine run: 03/28/99 13:41:15

Temperature :

27.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(B) teattranaiatoradat

30M7----------------------------------------------;;;;-—---------------------~----—-----------------------'
I . /" I
I ’l ,f I
: II/L - soc/300 ’ / 2
: l // I
: vs; - 2v ‘ / 2
35m.: .AI.OO°.“3 . . /I . . . . f
I _ I / I

I /
I ’ 'W-e.‘
‘ a M .

/ _____r-
t J l ’ ‘FP—_,’r_’_,__—-—-"" - :
: f- 'I' :
200M1 ’- ;
: .
I / I
: r / . . VGS . 3 .5V :
150m «5 - / ~ / wwigfitfii. “p-11“... " 7‘ 7" .
g f ’ ’/ - if,” 1,--- ‘ """ - - I
E (,x . . ./' ~ 5
I I," ' .‘I . |
I .' ,6 l
: ’7“ r'. //1. :
100m“. /' mm -'.os1'6 ___ -04.”:
: ."II "I ’ . _______.———————~—b—-~ _‘ .fl _ __ :
; ,"fx’. l/ 11”,.---_—r— ,P--._...-. :
: /I /' ’ ”I " :
j '1 I .
: /./‘/' I, ’I/‘- o :
50“.; ’64-’34 mm - ..0569 . __J
' 'I'I‘ I, / "a n -._—‘—-H '
, /.-,-_; a ._._1 - a m M .
: ’Ifi‘yi-f," / ,,/ v” :
: ’597 x"! veg-2v ;
, _ _ _ ”a“ -_ --- mm; -061__ _ - __ - -_ -_— —. —- ..
: x/i/"fl’. . ' :
0A Ti V T V I 4
0V 1.0V 2.0V 3.0V 4.0V 5.0V
a 10011)
VDS

 

Date: larch 28. 1999

Figure B.12: Measurement of in for a large device (cont.).

69

Time: 13:46:40

 

31! ‘3

 

¥
I...

 

 

'TEST CIRCUITS FOR DIFFERENT TRANSISTORS
Date/Time run: 03/28/99 17:05:58 Temperature: 27.0

 

(N) teattranaiatora.dat

I
I
I-H
I “' .
r\\ “““““ H
I ‘s __
L\‘ \1“ ‘-\“
I ~.. '-._ -.,\ - I .
l ‘x_ "“m \, SLOPE I SORT (K' W/2L)
' “Fr. ““5 h “.
I ‘~._ "~..
F\\ ‘\x ”a “. . . , NIL l3U/2U
I \\.\ ‘~- ‘ ‘~.\
I ‘\ ‘-.. "a.
“~~ \. “a 7‘.
: \\ vas - 0v
l \ -".' “ V‘u - .
I ~\\ ‘*a‘
I \ ‘.\‘. \ -.‘
10”.: ‘~. . \ ._ ‘ ,
I .\\ x '1
N .
\‘ “ \-
\\‘-‘ “‘4 x
1‘ ‘ .\‘ \
\_\-A ~\
‘ \\ “.“\
\.~ ~ I.
\\‘ \ ‘ '\\ ‘s

“ ‘xm ‘ x ‘ KPP 7. 20.0% NA
‘ . - V'-

I“:~ VT'O I c.0033“;

In
8

4L-------------_------- -------------------
‘ r

  

 

 

O

C 90RTI¢ID(X1))

 

ISI'T ------------------------------------------------------------------------------------------------------

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
l
I
l
I
l
I
l
I
I
I
I
I
I
l
I
I
I
I
I
l
I
I
I
I
I
I
I
I
I
I
l
I
I
I
I
I
I
I
I
I
I
I
I

-S.0V -4.0V -3.0V -2.0V -1.0V 0V

 

Date: March 28, 1999 Page 1 Time: 17:13:39

Figure B.l3: Measurement of Kpp and VTpo for a small device.

70

 

Dace/Tine run: 03/28/99 17:14:52

"PEST CIRCUITS FOR DIFFERENT TRANSISTORS

Temperature: 27 . O

 

I
I
I
I
I
o. _
I ~'\\
I"‘\ ‘\
\
;\,‘\\\‘\\yns - -5v
I \\\\‘"\.\\\
K -.‘ '\\.‘
‘\\ "\:\, . ‘.\‘
‘\‘ \‘\‘ \s», ~‘\_
\\‘\ \ “ . \fl\\\‘\
1011: ~\~ .;f“\~3.j‘\
\\~. -._
‘—-‘_vns - -1v '
.. \ _\~ ‘

~\*Q‘\
‘N\'\:“
“. \:

(O) toacttanaietora.dat

15m - -------------------------------------------------------------------------------------------------------

I KP? " 20'45’1—6

§§993=3.878 2-3 .yzo.a?}

/ ' W's —\.‘LHV

 
   
       

N “‘9‘“?j53ig."_}‘-‘;p..‘ ves - 2v
snore - 3.82 3-3 ~ ~ :5
smpe- (.227 3-3
I". ..‘. “\‘\‘.\
SLOPE: 3.723 8-3 _‘\._:“‘~:\“/
‘ ‘ “ way -1.219v

 

—---------_----J----------------L----—-----_r--J----

'5.0V -‘.0V
5 SQR'N-IDIKIII

 

'5m+ """""""""" I ----------------

' ' ' ' 'w/xl - 3'0/20' ' ' :

I -------------------- r -------------------- . -------------------- 4
-3.0V -2.0V -1.0V 0V

 

Date: March 28, 1999

Page 1 Time: 17:22:18

Figure B.l4: Measurement of Kpp and VTpo for a small device (cont.).

71

 

'TEST CIRCUITS FOR DIFFERENT TRANSISTORS

Otto/Tim. run: 03/28/99 17:35:17

Temperature: 27 . 0

 

 

    
 
  
  

 

 

 

 

 

 

(R) toattrmistorsdat

9.0:.7--------------~---—----------------------------------------------------------------—------~---------.
3 \ i
I s . . w/L - 10U/150
I ~-\._ ves -cv
6.01:1 . . ‘
: vns - -1v‘ \-‘, :
: K ._ usual:
I P? :vl.:
4.0fl“ . . . . . I
I V‘I'INIO‘= -O.u?V:
; 93- 2.0306 3-3 ;
2.0m - - - - .
i :
I I
v'ro - -.8677v
o 4 "‘ ' T“. '——“ — -’._" ’ " ’7' "I- _"" "I ‘\ I
-s.ov -4.ov -3.ov -2.ov ov

a sown-10mm)

vcs

Date: latch 28, 1999 Page 1 Time: 17:39:08

Figure B.lS: Measurement of Kpp and VT") for a medium size device.

72

DutelTil. tun: 03/28/99 17:39:36

'TBST CIRCUITS FOR DIFFERENT TRANSISTORS

Temperature: 27 . 0

 

 

 

 

 

 

(S) teactzeneiecore.dec

san----------
I. I
6.0I-I 2
I ' I
:\ r".- I'lo‘IqPA_ :
I '1’ :
3 1?: 0.ch ;
‘oOI‘: . . . . . z
I II/L- IOU/150 :
: vas- 2v ;
2.01.: I
pon- 2.0407 2-3
I 0
m - -1.3123v
0+ W r 1 a; r 'I
-5.ov -c.ov -3.ov ~2.ov -1.ov ov

a sown-1mm“

vcs

Dete: larch 28. 1999 Page 1 Time: 17:0:26

Figure B.l6: Measurement of Kpp and vao for a medium size device (cont.).

73

"PEST CIRCUITS FOR DIFFERENT TRANSISTORS
Date/Tine run: 03/28/99 17:50:12 Temperature: 27.0

 

   

 

 

 

 

 

(V) teettrensietore.det

12:—-----—-------------~----~-------—------------~-------------------»----------—------------------------~.

1 1

E

10nd:

win-500nm:

vas - 0v 2

and. . . . . - :

: K"; I1-O8ufi ;

2 v V‘- 1

: YP°=—0-%‘I?-V :

«n4: :

zué E

wo- -.su1v

0.; .__., _______ _ 51* . .1,-:_,." .__..__.~-_.__ “T- ...7...: __ -____ ____,,_H 1- ., I j:

-s.ov -I.ov -3.ov -2.ov -1.ov ov
: SQRTPIDINIH

vcs
Date: larch 28, 1999 Page 1 Time: 17:53:06

Figure B.l7: Measurement of Kpp and VTPO for a large device.

74

'TBST CIRCUITS FOR DIFFERENT TRANSISTORS
Date/Tine run: 03/28/99 17:53:25 Temperature: 27.0

 

   
  

 

 

 

(w) teattranaietore.dat

I I

101:; 2

8n; 5

I’xl“> I

: \‘\- ‘

: “\\ :

I \_ I

6 5 vns- -1v 1

n4 0 . e e , o . I

I VIP: -—I-3Is'1-V :

5 (=05? :

I Menuzfl 1

I ’13— I

410-: we -500/3ou :

snore - 3.179 2-3 VBS ' 2v

I I

2n-E :

: . :

v'm - -1.3102v 2

I ' I

0% Y fir Y K“ r I

-5.0V -8.0V -3.0V -2.0V -1.0V 0V
: san(-ID(H1))

VGS
Date: larch 28. 1999 Page 1 Time: 17:56:07

Figure 8.18: Measurement of Kpp and V1~po for a large device (cont.).

75

 

_ 'TEST CIRCUITS FOR DIFPm TRANSISTORS
Date/Time run: 03/28/99 16:35:19 Tamerature: 27.0

 

 

 

 

 

 

(K) tuttranaiatoradat

Mj—-- “7.7 ——~———~ —_—..~-_.~—« ~———— .
= mm» ,7... ___.__,,__.___,__. 7,7
; unam- 268 ,0]. ;
I g ____..-.—~--—""” I /.'.’;I ,
I . _ -___ fl--.—-——v-r—‘ “"‘"— . /,.'r}‘F :
: 3257-;aLm———#«~ “3"" “ , ' :
2 0mm - 17 , ,‘ :
I - —’“'x I I I
. 7-...r"""”v’4 r ." l .
-‘OMW. _,,-_o—"' -7-"'—”—"‘- '4 ' D I I .'ll' // ' :
I—r‘ ‘ ’" "'_' W-W—g-W « "f. /,.”l,-":: :
. mm - .1271 /_/1 x ,- .- .
: / ,/ ’ I
: /:«/ ' ,1 :
: ,1. ’ ;
. _,,,./”’” - , / ,
: Kiri-ta ,/ / I' /I I
r’ - _ III ‘3 I
40:31 mm _111 // 7 Ix. I
I / l’ '1 .
I //” [I I, 'I' I
: ' ,_/ . ’, f :
; VDS - 4.31/7/ "I" _ ..«-" // :
:-»-~~””’imm- .096 //’/ ‘ A = 0-‘544 ;
; . l,./' . / . :
1 /4/1,,«/ ,1 x’asna 00031.: cuos 000x 1
-120“; ;,J—' ., w” . . . . . . (’7’ . ’1. v5! -. 0V . '
I ’7”! I” l I
. firm" ' ’ II/L - 30/20 .
I __/..’—" If . . ,3" . / . I
fr“ 7, / fouxrzoa: (102-mIIIIv02-v01I'102 :
: ,/"'/ / i
I // l/ :
: ("/// ’1', I
I ”VI/I. I," .
-160“ + --------------- “F:- r ---------------- 1' ------------- '- ----- v ------------------- 1 ------------------- ‘l
-5.ov «.ov -3.ov -2.0v -1.ov ov

a mum

vns

 

 

Date: larch 28. 1999 Page 1 Time: 16:46:11

Figure 3.19: Measurement of M: for a small device.

76

 

Date/Tim. run: 03/28/99 16:54:15

'TEST CIRCUITS FOR DIFFERENT TRANSISTORS
Tcmporaturo: 27.0

 

V,

-100uA 4

"Y"""-'-""P""

 

0‘ I» :__ ._-— "‘ __ _. __»_ ‘______‘ ___ _ __, _ ‘

: ##r‘ ’ ——— _r ’4 _ ~___‘ - ‘/l.-
' VDS - _ * _”_ . _ __ _f7_ 7- _ fl-__ ,,
: _. . ', 2V . 2337 IC{
. ‘ """ ,’ / 1'
: - r H—< 4“ _' ‘ A‘ V 1". I’l‘,
: -_ - I -—'~ _ -‘iv‘ - ,/h5
:‘4 ‘ ' " ” LAMBDA . 1739 I , //’, ’ .1
I ’ W I I
i ,..- l I
I _IM,J—-—-'-fl"i—fl’ I, I
I F ‘M- ’ ’
l r, '” r. l

' X‘HB 1M» — - 77,7 4 I / ,

-50uAJ 4fi_¥ '»’r_, .. 135 I

l
l
‘x
\
\
\
K\

_-" VI. ‘ ‘ /
- . . , um. .- 30/20

(L) toattransiltorn.dat

 

 

 

,, 7.-» ‘ /" ) -.-. 0.36 Z'L

. vss . -2v

 

 

Date: latch 28,

1999 Time: 17:01:17

Figure B.20: Measurement of kp for a small device (cont.).

77

 

'TEST CIRCUITS FOR DIFFERENT TRANSISTORS

Date/Time run: 03/28/99 17:23:21

Temperature: 27 . 0

 

 

 

 

 

 

 

 

 

 

 

(P) teeCtreneietox-e.dat

0m . _ .7 .j
I _ ,7. ”I” :
; vcs - -1.5v mumm- o )3, ;
r 7- « 7..-- --— ~ ~ 7, ~« —>- -——- ~——- 77.______, 77, —— -- — 7 — 7 ~~"" / :
I LAMBDA- 0 , ’ ,’ .- . .
“1°“ 1' ,l/ ‘ / l :
,__. 77 ~——-A-w«~—r~ 7—————4-——~ ,_ r.- .
: (I ;/ ’{ I
: I, :
2—— — —~ — ~ ~ 7 —— —*‘ 7-7 7 — 7 ~-—— 7.7.7,-.. ”’ _/ z
400:: 1 -/ x
: l 4” I!" If,- :
: /” I,‘ I]! e; /'/' :
:,__ «—— ———— _—-—... . — __ .— . ._..,—._._ v __.—-—<// // ff. 1": :
: VGS' ’3 5" mm- .003 I; ;
: ' / 7" A g 0 :
: , / :
-30“ /" . . . . ,
1I ,I’ 1m. -10w1su .
i VBS = UV 1
: ,/ ’ ' x :
r—-— m_,7 ,7-__u________7 / .
' / I
t / I
-80uA + """""""""" 1 """"""""""""" 'I ----------------- r '4 ----------------- 1 ----------------- "I
~5.0V -l.0V -3.0V -2.0V -1.0V 0V

" 100(1)

VDS

Date: latch 28, 1999 Page 1 Tine: 17:28:38

Figure B.21: Measurement of M» for a

78

medium size device.

 

'TEST CIRCUITS FOR DIM TRANSISTORS
Date/Tile run: 03/28/99 17:29:03 Temperature: 27.0
(0) teettraneietore.dat

0A —- ——~ 77“.: mg-— “.7;

 

 

 

 

i
I

M _-.._-3_V, ,,___,,- ' L _._,-,7--,...-_..,,,-7.- /

 

 

 

: ’7 _”" ' 'Launna - 0 I ,
I ’/
-5MJ' r // l.’ o

'”"—.'”‘ A A * “‘" * *”—-"* H" ' '”““"" I

I ,-

I I

-10uA . 7, .
mm - .005. ,’
/
'/ .
Vfl’i _‘v ‘ _—_.-.",,,.r‘r'/I [a I I

I . .- 9x -:. O
-30“ .o . . . . . . . . . . . . . . . . . . ,' . . . . .
. . . ./ 4' XVI/L - 100/ 150

’ vas - 2v

-25M

 

I

8

8

8

Q

‘

I

| I
l 8
: I
' I
—15M J. . . . . . . . . . . . . . . . . . . I / . "1' f1 .1. . . :
t ' ' ' g
I

.

 

 

Date: Hitch 38. 1999 Page 1 Time: 17:33:56

Figure 3.22: Measurement of M» for a medium size device (cont.).

79

 

'TEST CIRCUITS FOR DIFFERENT TRANSISTORS
Date/Time run: 03/28/99 17:45:50 Temperature: 27.0

 

 

 

 

('1‘) teettraneietore.dat
Duh ' ..... -.-.. 1.: ”‘7
. vcs - -1 5v .. .
I . 4 ” .-"/4.:‘ I
r" " "- 7,- * ‘* “ “ ~ * -7 ___ ““"""~ * — r ““”——— ___-, ”- “M " " 7,733“ :
; . . 7, .1724: ;
' 7//-' ’1...” I
:— ~ — ~47 ~ 7 ~ — 77 7-7 7- 77.7 u— —-——~ — ———— -7- , ~ 7-.., -"‘ - / .
: .x' I /’, :
/ ,’
: ‘,a/’ I], /r’.’ :
I ' /// I” I’ .' I
|__,_,_. _. 7___7_,,-7 7_, 7-? ,7 ______,___fi__“__.__ _____,___. M.“ _ v— ,._fi_.________———” ‘ I II |
z ",2‘ r :
-SOMJ' l a e e . a e I I u I I n e e e a o ”r": e I, , I
I --"/ / ’ ' :
,--' I l
: -/.—’4 (I, / I, .
l ' ”_'"" ’I 7 [I I
L" A _... 7 . V 7 v , —- ~ .—.— ——.——.—7 W W V “#77,. ’i ’4 , C
: VGS- -3.5V LAMBDA . o ,Il :
: ./"' It, :
: , / ,1 :
: /.//I 1’ / :
.1.” , - 7 ~ : * — 7. ~ - 7- .7. 7,- --~—*""’ / )co ;
i z / II/L csounou !
.. J . 7%“ . . . . . :
100m : ’7 / vas - 0v '
O /"/- .l :
I 7/ / .
I-_____._ H _._._____,7 “v.1.“ ___.7 .__...7__._._—-—""/ 1’ I
I ,’ I
I J" :
I _. / i
I 1;" l
I 7’" l
: /,/’// :
I dfldu‘“ I
r— "‘ ’- ' ‘
I 0
I I
I l
'150M 4' """""""""""" r """"""""""""" r ----------------- 1 ------------------- 1 ------------------- “l
-5.W -4.0V -3 0V -2 0V -1.0V 0V
:2 IDlNl)
VDS

 

 

Date: larch 28. 1999 Page 1 Time: 17:47:46

Figure B.23: Measurement of 1p for a large device.

80

 

 

 

 

 

 

 

 

 

 

 

 

”PEST CIRCUITS FOR DIFFERENT TRANSISTORS
Dace/Tine tun: 03/28/99 17:47:58 . Temperature: 27.0
(U) tuttraneietorndat
0A -— -- —- -'

L— .— f a __ - ~ #7
: VGS - ~2V / /C..'._" I
g _ a ’ Jr”; / 312-": E
““51 ff: , ', I
: - "itl— I 1‘ I I" :
. J‘A/ I I ' I
|—~ ..1 fl- ; MM # — mm flflfi V i M— , / , I
: 'l' / .' I
: / " '
I ,2 I I, 'I'l :
-‘on J. a - Ix" -/ . - z I, {/0 :
1““ _________._,,. _, ‘ k j/ 4 ’1’ '0" :
: VGS I -3.5V mm - o I”, ,I '1', :
I ' I ' I
. 1’ 1/ I‘ I
: ,/’ / ° , ’ :
~60Mj ;,,/'fi ‘/ ," :
: r _ _ _ _ ”flx'f'", / , :
F-" ‘ ”‘"‘ ‘ ' “W —"-’VH" 7H / '
: , x :
I 1’ / I
I ’ ’ // . I
I 1' I
I r" , g D I
‘80“ '1 2"” . u ’e . A . z
: ,x” ' ’ w/L - 5007300 :
I __ _____<4 ~—-.7—— _,_,4~”’ / I
T ’ vas - 2v ' i
' . 1/ . ‘
i ./ :
doom 1 ,/ ;
'120M 4‘ """""""""" r ---------------- r --------------- v ---------------- 1 ---------------- 4
-5.0V -4.0V -3.0V -2.0V -1.0V 0V

; mum

VDS

Dace: latch 28. 1999 Page 1 Time: 17:49:47

Figure B.24: Measurement of I... for a large device (cont.).

8]

 

11 Appendix C

Operating point simulations for the new output stage

82

 

 

NAME M1 6 M1 7 M1 8 M 1 M2
MODEL CMOS PB CMOSPB CMOSNB CMOSNB CMOS PB
ID -2.04E-05 -2.04E—05 2.04E-OS 1.663-05 -1.44E-OS
VGS -1.80£+00 -1.68£+00 2.33E+00 S.OOE+00 -5.00E+00
VDS -l.92£+00 -3.09E+00 5.00E+00 8.SSE+00 -8.76£+00
VBS 0.00E+00 0.00E+00 0.00E+OO 0.00E+OO 0.00E+OO
VTH —8.9ZE-01 -8.9lE-Ol 8.868—01 8.77E—01 -8.85£-01
VDSAT -7.S6E-01 -6.SBE-01 9.568-01 2.72E+00 -3.4SE+00
LinO/Satl -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00
if -1.00E+OO -1.00E+OO -1.00E+00 -1.00E+00 -1.00E+00
ir -1.00E+00 -1.00E+OO -1.00E+00 -1.00E+00 -1.00E+OO
TAU -1.00E+00 -1.00E+00 -1.00E+OO —1.00E+00 -1.00E+00
GM 4.258-05 4.9lE-OS 2.73E-05 7.508-06 5.968-06
GDS 2.203—07 1.79E—07 2.013-07 7.34E-08 0.00E+00
GMB 1.39E-05 1.612-05 1.3BE-OS 2.218-06 1.248-06
CBD 3.568—14 2.968-14 2.69E-15 2.84E-15 1.048-14
CBS 6.82E-14 6.828-14 5.113-15 6.58E-15 3.638~14
CGSOV 1.758-14 2.25E-l4 1.858-15 2.23E-15 8.978—15
CGDOV 1.758-14 2.25E-14 1.853-15 2.23E—IS 8.97E-IS
CGBOV 3.538-15 3.53E—15 3.54E-15 3.848-14 3.898-14
Derivatives of gate (ng/dey) and bulk (de/dey) charges
DQGDVGB 2.218-13 2.843-13 3.548-14 4.11E-13 1.098-12
DQGDVDB -1.7SE-14 ~2.ZSE-14 -1.8$E-15 -2.23E-15 -8.97E-15
DQGDVSB -1.81£-13 ~2.32£—13 -2.44E—14 -3.34E-13 -1.03E-12
DQDDVGB -1.7SE-14 -2.ZSE-14 -1.85E-15 -2.23E-15 -8.97E-15
DQDDVDB 1.753-14 2.255-14 1.853-15 2.238-15 8.978-15
DQDDVSB 0.00E+OO 0.00E+00 0.00E+00, 0.00E+00 0.00E+00
DQBDVGB -1.7dE-14 -2.14E-14 -7.SGE-15 -9.17E-14 -1.17E-13
DQBDVDB 0.00E+00 0.00E+OO 0.00E+00 0.00E+OO 0.00E+00
DQBDVSB -6.44E-14 -8.38£-14 -2.24E-14 -2.62£-13 -2.64E-13
NAME M3 M4 M5 M6 M7
MODEL CMOS PB CMOSNB CMOSNB CMOSPB CMOSPB
ID -8.588-06 7.32E-06 5.493-04 —5.49E-04 -8.03E-06
VGS -l.BOE+OO 1.BOE+00 1.24E+00 -1.3SE+00 -1.77E+00
VDS -1.3SE+00 1.24E+00 4.97E+00 -5.03£+00 -1.35£+00
VBS 0.00E+OO 0.00E+00 0.00E+OO 0.00E+00 0.00E+00
VTH -8.96£-01 8.868-01 8.218-01 -9.02£-01 -8.96£-01
VDSAT -7.53E-01 6.063-01 2.87E-01 -3.77E-01 -7.27E-01
LinO/Satl -1.00E+OO -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00
if -l.OOE+00 -1.00E+00 -1.00E+OO -1.00E+00 —1.00E+00
ir -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00
TAU —1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00
GM 1.793-05 1.568-05 2.4SE-03 2.288-03 1.748-05
GDS 8.148-08 4.838—07 1.34E-05 6.308-06 7.598-08
GMB 5.868-06 8.388-06 1.103-03 7.778-04 5.702-06
CBD 1.84E-14 4.158-15 1.7lE-13 9.29E-13 1.848-14
CBS 3.07E-14 5.853-15 2.998-01 2.708-12 3.078-14
CGSOV 7.4SE-ls 1.852-15 2.198-13 7.223-13 7.468-15
CGDOV 7.468-15 1.858—15 2.19E-13 7.228—13 7.463—15
CGBOV 3.533-15 3.54E-15 1.653-15 1.608-15 3.53E-15
Derivatives of gate (ng/dey) and bulk (de/dey) charges
DQGDVGB 9.623-14 3.54E-14 1.98E-12 4.878-12 9.628-14
DQGDVDB -7.46E—15 -1.BSE-15 -2.19E-13 -7.223-13 -7.465-15
DQGDVSB —7.69E-14 -2.38£-14 —1.4lE-12 -3.73E-12 -7.68£-14
DQDDVGB -7.46£-15 -1.BSE-15 -2.19£-13 ~7.22£-13 -7.46£—15
DQDDVDB 7.46E-15 1.858-15 2.193-13 7.223-13 7.463-15
DQDDVSB 0.00E+00 0.00E+00 0,008+00 0.00E+00 0.00E+00
Page: 1

Figure C.l: DC operating point for the new output stage.

83

 

 

DQBDVGB -9.43E-15 -7.56E-15 -2.12£—13 -2.64E—13 -9.43£—15
DQBDVDB 0.00E+OO 0.00E+OO 0.00E+OO 0.00E+00 0.00E+00
DQBDVSB -2.73£—l4 -2.30£-l4 -1.20E-12 -1.27E-12 -2.74E-14
NAME M8 M9 M11 M13 M10
MODEL CMOSNB CMOSPB CMOSNB CMOSNB CMOSNB
ID 7.068-06 —8.03E—06 8.038-06 8.038-06 1 085-05
VGS 1 788+00 -1.77E+00 3.0lE+00 1.968+00 1 783+00
VDS 1.24E+00 —1.77£+00 6.288+00 1.96E+00 1 788+00
VBS 0.00E+OO 0.00E+00 -1.96£+00 0.00E+00 0 OOE+00
VTH 8.86E-01 -9.14E¢01 1.4ZE+00 9.025—01 8 688-01
VDSAT 5.9SE-01 -7.09E-01 1.18E+00 7.008-01 6.08E-01
LinO/Satl -1.00E+00 -1.00E+OO -1.00E+00 -1.00E+OO —1.00E+OO
if -1.00E+00 -l.00£+00 -1.00E+OO -1.00E+00 -1.00E+00
ir -l.00E+00 -l.OOE+00 -1.00E+00 -1.00E+00 -1.00E+00
TAU —1.00E+00 —1.00E+00 -1.00E+00 -1.00E+00 -1.00E+00
GM 1.548-05 1.77E-OS 9.758-06 1.488-05 2.293’05
GDS 4.658-07 1.978-07 9.258-08 4.008-07 6.508-07
GMB 8.258—06 5.728-06 1.27E—06 8.108-06 1.183-05
CBD 4.15E-15 8.878-15 5.098-15 3.35E-15 4.67E-15
CBS 5.858-15 1.57E-14 7.79E—15 5.118—15 7.32E-15
CGSOV 1.858-15 3.448-15 5.658-15 1.478—15 2.612-15
CGDOV 1.858-15 3.448-15 5.658-15 1.47E-IS 2.618-15
CGBOV 3.54E-15 1.60E-15 3.768-14 3.548-15 3.548-15
Derivatives of gate (ng/dey) and bulk (de/dey) charges
DQGDVGB 3.54E-14 2.47E-14 9.3OE-13 2.88E-14 4.84E-14
DQGDVDB -1.85£-15 -3.44E-15 -S.65£-15 -1.47E-15 -2.61£-15
DQGDVSB -2.38£—l4 -l.79E-14 -7.6lE-13 -1.9OE-14 -3.36E-14
DQDDVGB -1.BSE-15 -3.44E-15 —5.6SE-15 -1.47E—15 c2.613-15
DQDDVDB 1.85E—15 3.448-15 5.655-15 1.478-15 2.618-15
DQDDVSB 0.00E+00 0.00E+00 0.00E+00 0.00E+OO 0.00E+00
DQBDVGB -7.S6E°15 -2.84E-15 —1.38£-13 -6.7SE-15 -9.17E-15
DQBDVDB 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00
DQBDVSB -2.3OE-l4 -5.7SE-1S —3.84E-13 -1.83E-14 -3.ZlE-14
NAME M12 M14 MC
MODEL CMOSPB CMOSPB CMOSNB
ID -1.08£—05 -1.0BE-OS 4.908-20
VGS -3.03E+00 -2.00E+00 4.07E+00
VDS -6.22£+00 -2.00E+OO ~1.0ZE—07
VBS 2,008+00 0.00E+00 -2.33£+00
VTH -1.37E+00 -9.16E-01 1.63E+00
VDSAT -1.47£+00 -8.98£-01 1.828+00
LinO/Satl -1.00E+OO -1.00E+00 -1.00E+00
if -1.00E+OO -1.00E+00 -1.00E+00
ir -1.00E+00 -1.00E+00 -1.00E+00
TAU -l.00£+00 -1.00£+00 -1.00E+00
GM 1.218-05 1.868-05 5.968-13
GDS 4.358-08 2.4OE-07 2.298-05
GMB 2.288-06 5.888-06 1.418-13
CBD 4.508-15 7.565-15 4.468-15
CBS 7.568-15 1.388-14 4.468-15
CGSOV 2.938-15 2.932-15 1.47E-15
CGDOV 2.938-15 2.938-15 1.47E—15
CGBOV 3.533-15 1.608-15 9.988-15
Derivatives of gate (ng/dey) and bulk (de/dey) charges
DQGDVGB 3.935-14 2.143-14 9.388-14
DQGDVDB -2.938—15 -2.93E—15 -4.19E-14
Page: 2

Figure C.

84

2: DC operating point for the new output stage (cont.).

 

DQGDVSB
DQDDVGB
DQDDVDB
DQDDVSB
DQBDVGB
DQBDVDB
DQBDVSB

Figure C.3: DC operating point for the new output stage (cont.).

-3.
-2.

2.
.OOE+00
-S.
.OOE+OO
-5.

105-14
93E-15
938-15
14E-15

14E-15

-l.
-2.
2.
0.
-2.
0.
-4.

54E-14
93E-15
93E-15
OOE+00
SSE-15
00E+00
81E-15

85

-4.
-4.
.68E-14
-2.
-9.
-2.
-1.

19E-14
19E-14

71E-14
98E-15
19E-14
373-14

12 Appendix D

SPICE testing of the new op-amp circuit

86

M:\thesis\final output stage\final_circuit.out 10/20/99 20:28:54

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( 1) -.OO35 ( 2) 3.6453 ( 3) 3.2008 ( 4) -5.0000
( 5) -3.7552 ( 6) -.0304 ( 7) 5.0000 ( 8) -3.2039
( 9) 3.2318 ( 12) -3.2208 ( 13) -3.0435 ( 14) 3.0007
( 17) 1.2415 ( 18) 3.0818 ( 19) -2.6721 ( 1A) 0.0000
( 18) 0.0000 ( 3A) 1.4016 ( 3B) -.9012 ( 16A) -2.6720
( 168) -2.6721

VOLTAGE SOURCE CURRENTS

NAME CURRENT

VDD -6.449E-04

VSS 6.449E-04

VINA 0.000E+00

VINB 0.000E+00

TOTAL POWER DISSIPATION 6.45E-03 WATTS

Figure D.1: DC operating point test.

87

~ - {inosrms

NAME MR1
MODEL CMOSPB
ID -4.488-O6
VGS -1.808+00
VDS —1.80E+OO
VBS 0.008+OO
VTH -9.028-01
VDSAT -7.498—01
LinO/Satl -1.00E+OO
1f -1.008+OO
ir -1.008+OO
TAU -l.008+00
GM 9.47E-06
GDS 2.528-08
GMB 3.088-06
CBD 1.258-14
CBS 2.17E-14
CGSOV 3.948-15
CGDOV 3.948-15
CGBOV 3.538-15
Derivatives of gate
DQGDVGB 5.25E-14
DOGDVDB -3.94E-15
DQGDVSB -4.068-14
DQDDVGB -3.94E-15
DQDDVDB 3.94E-15
DQDDVSB. 0.008+00
DQDDVGB -6.63E-15
DQBDVDB 0.008+00
DQBDVSB -1.448-14
NAME MlA
MODEL CMOSPB
ID -1.048-05
VGS -1.248+00
VDS —3.918+00
VBS 0.008+00
VTH -8.908-01
VDSAT -2.93E-01
LinO/Satl -1.008+00
if -1.008+00
ir -1.008+00
TAU -1.00E+00
GM 5.488-05
GDS 7.068-08
GMB 1.868-05
CBD 7.66E-14
CBS 1.988-13
CGSOV 5.228-14
CGDOV 5.228-14
CGBOV 3.538-15
Derivatives of gate
DQGDVGB 6.53E-13
DQGDVDB -5.228-14
DQGDVSB -5.298-13
DQDDVGB -5.228-14
DQDDVDB 5.228-14
DQDDVSB 0.008+00
DQBDVGB -4.50E-14
DQBDVDB 0.008+OO
DQBDVSB -2.018—13
NAME M36
MODEL CMOSPB
ID -2.048-OS
VGS -1.808+00
VDS ‘1.928+OO
VBS 0.008+00
VTH -8.928-01
VDSAT -7.56E-01
LinO/Satl -1.008+00
if -1.008+00
ir -1.008+00
TAU -1.00E+00
GM 4.258-05

Figure D.2: DC operating point test (cont.).

MR

CM
-4.
-1.
-1.

O.
-9.
-7.
-1.
-l.
-1.
-l.

UWWNHUNKD

(ng/d
5

-3.
-4
-3.
3.
0.
-6.
O.
-1.

M1

CM
-1.
-1.
-3.

0.
-8
-2.
-1.
-1.
~1.
-1.

WU‘U‘HQHQU‘

2

OSPB
488-06
808+00
808+OO
OOE+OO
028—01
498-01
008+OO
008+00
008+00
008+00

.47E-O6
.528—08
.088—06
.258—14
.178-14
.94E-15
.948-15
.538-15
ny) and
.258-14

94E-15

.06E-14

948-15
948-15
008+00
638-15
008+00
448-14

B
OSPB
048-05
248+00
918+00
008+00

.90E-01

938-01
008+00
008+00
008+00
OOE+00

.48E-05
.O6E—08
.868-05
.66E-14
.98E-13
.22E-14
.22E-14
.53E-15
(ng/dey)
6

.53E-13

-5.
~5.
-5.
5.
0.
-4.
0.
-2.

M1

228-14
298-13
228-14
228-14
008+00
508-14
008+00
018-13

7

CMOSPB

.048-05
.688+OO
.098+OO
.008+OO
.918-01
.588-01
.008+00
.008+OO
.008+00
.008+00
.918-05

MPS
CMOSNB
4.488—06
1.808+00
1.808+OO
0.008+OO
9.298-01
5.748—01
-1.008+00
.008+OO
-1.008+OO
-1.008+OO

and

MR3 MR4
CMOSPB CMOSPB
-4.488—06 -4.4BE-06
-2.308+OO -2.308+OO
-2.308+OO -2.308+OO
0.008+00 0.008+00
-9.158-01 -9.15E-01
—1.168+OO -1.168+00
-1.00E+OO -1.00E+00
-1.00E+OO -1.00E+OO
-1.008+OO -1.008+00
-1.00E+OO -1.00E+OO
6.068-06 6.068-06
0.008+OO 0.008+00
1.898-06 1.898-06
8.318-15 8.318-15
1.538-14 1.538-14
1.938-15 1.938-15
1.938-15 1.938-15
3.918—15 3.918-15

bulk (de/dey) charges
3.018-14 3.018-14
-1.938-15 -1.938-15
-2.228-14 -2.228-14
-1.938-15 -1.938-15
1.938-15 1.938-15
0.008+00 0.008+00
-5.588-15 -5.588-15
0.008+00 0.008+00
-7.398-15 -7.398-15
MZA M28
CMOSNB CMOSNB
1.048—05 1.048-05
2.338+00 2.338+00
2.338+00 2.338+00
0.008+00 0.008+00
9.298-01 9.298-01
9.248-01 9.248-01
-1.008+00 -1.008+00 ‘
-1.008+00 -1.008+00
-1.008+00 -1.008+00
-1.00E+00 -1.008+00
1.458-05 1.458-05
3.928-07 3.928-07
8.128-06 8.128-06
2.848-15 2.848-15
4.388—15 4.388-15
1.098-15 1.098-15
1.098-15 1.098-15
3.548-15 3.548-15
bulk (de/dey) charges
2.238-14 2.238-14
-1.098-15 -1.098-15
-1.438-14 -1.438-14
-1.098-15 -1.098-15
1.098-15 1.098-15
0.008+00 0.008+00
-5.958-15 -5.958-15
0.00E+00 0.00E+OO
-1.368-14 -1.368-14
M18 M81
CMOSNB CMOSNB
2.048—05 1.668-05
2.338+OO 5.008+00
5.008+OO 8.658+00
0.008+00 0.008+00
8.868-01 8.778-01
9.568-01 2,728+00
-1.008+00 -1.008+00
-1.008+00 -1.008+00
-1.008+00 -1.008+OO
-1.00E+OO -1.00E+00
2.73E-05 7.508-06

88

-1

.OlE-OS
.12E-O7
.92E-06
.53E-15
.03E-15
.09E-15
.09E-15
.16E~15

.02E-l4
.09E-15
.26E-l4
.O9E—15
.09E-15
.00E+00
.31E-15
.OOE+00
.24E-14

M15
CMOSPB

-2.
-1.
-3.

0.
-8.
-7.
-1.

-1

-1

uIAh-axnrah-o

088—05
808+00
768+00
008+OO
928—01
568-01
008+00

.OOE+OO
-1.

008+00

.008+00
.338-05
.558-07
.418-05
.738-14
.828-14
.758-14
.758—14
.538-15

.218-13
.758-14
.818-13
.758-14
.758-14
.008+00
.748-14
.008+OO
.448-14

MNl
CMOSPB

.448-05
.OOE+OO
.768+OO
.008+OO
.858-01
.458+00
.008+00
.008+OO
.008+OO
.OOE+OO
.968-06

M: \thesis\fina1 output stage\final_ circuit. out 10’20/99 20: 28: 54

GDS 2.208- 07 1.798- 07
GMB 1.398-05 1.618-05
CBD 3.568-14 2.968—14
CBS 6.82E-14 6.828-14
CGSOV 1.758-14 2.258-14
CGDOV 1.75E-14 2.25E-14
CGBOV 3.53E-15 3.53E- 15

Derivatives of gate (ng/dey) and
DQGDVGB 2.21E-13 2.84E- 13
DQGDVDB -1.758-14 -2.258- 14
DQGDVSB -1.81E-13 -2.32E-13
DQDDVGB -1.75E-14 -2.25E-14
DQDDVDB 1.758—14 2.258—14
DQDDVSB 0.00E+00 0.00E+OO
DOBDVGB -1.748-14 —2.148-14
DQBDVDB 0.008+00 0.008+00
DQBDVSB -6.448-14 -8.388-14
NAME MP2 MN2
MODEL CMOSPB CMOSNB
ID -8.588-06 7.328-06
VGS -1.808+00 1.808+00
VDS -1.358+00 1.248+00
VBS 0.008+00 0.008+00
VTH -8.968-01 8.868-01
VDSAT -7.53E-01 6.068-01
LinO/Satl -1.008+00 -1.00E+00
if -1.008+00 -l.008+00
ir —1.008+00 -1.008+00
TAU -1.008+00 -1.008+00
GM 1.798-05 1.568-05
GDS 8.148-08 4.838-07
GMB 5.868-06 8.388-06
CBD 1.848-14 4.158-15
CBS 3.078-14 5.858-15
CGSOV 7.468-15 1.858-15
CGDOV 7.468-15 1.858-15
CGBOV 3.53E-15 3.54E- 15

Derivatives of gate (ng/dey) and
DQGDVGB 9.62E-14 3.54E- 14
DQGDVDB -7.46E-15 -1.85E- 15
DQGDVSB -7.69E-14 -2.388-14
DQDDVGB ~7.468-15 -1.858-15
DQDDVDB 7.46E-15 1.85E-15
DQDDVSB 0.008+00 0.008+00
DQBDVGB -9.43E-15 -7.568-15
DQBDVDB 0.008+00 0.00E+00
DQBDVSB -2.738-14 -2.308-l4
NAME MN3 MFPl
MODEL CMOSNB CMOSPB
ID 7.068-06 -8.03E-06
VGS 1,788+00 -1.778+00
VDS 1.248+00 -1.778+00
VBS 0.008+00 0.008+00
VTH 8.868-01 -9.14E-01
VDSAT 5.958-01 -7.098-01
LinO/Satl -1.008+00 -1.008+00
if -1.008+00 -1.008+00
ir -1.008+00 -1.008+00
TAU -l.008+00 -1.008+00
GM 1.548-05 1.778-05
GDS 4.658-07 1.978-07
GMB 8.258-06 5.728-06
CBD 4.158-15 8.878-15
CBS 5.858-15 1.578-14
CGSOV 1.858-15 3.448-15
CGDOV 1.358-15 3.448-15
CGBOV 3.548- 15 1.608- 15

Derivatives of gate (ng/dey) and
DQGDVGB 3.548-14 2.478- 14
DQGDVDB -1.858- 15 -3.448- 15
DQGDVSB -2.388-14 -1.798-14
DQDDVGB -l.85E-15 -3.44E-15
DQDDVDB 1.858-15 3.448-15
DQDDVSB 0.008+00 0.008+00
Page: 2

Figure D.3: DC operating point test (cont.).

89

2.018- 07 7.348- 08
1.388-05 2.218—06
2.698—15 2.848-15
5.118-15 6.588-15
1.858—15 2.238-15
1.858-15 2.238—15
3.548- 15 3.848-14
bulk (de/dey) charges
3.548-144.118-13
-1.858- 15 -2 238-15
-2.448—14 -3 348-13
-1.858—15 -2.238—15
1.858-15 2.238-15
0.008+00 0.008+00
-7.568-15 -9.178-14
0.008+00 0.008+00
-2.248-14 -2.628—13
MON MOP
CMOSNB CMOSPB
5.498-04 -5.498-04
1.248+00 -1.358+00
4.978+00 -5.038+00
0.008+00 0.008+00
8.218-01 -9.028-01
2.878-01 -3.778-01
-1.008+00 -1.008+00
-1.008+OO -1.008+00
-1.008+00 -1.008+00
-1.008+00 -1.008+00
2.458-03 2.288-03
1.348-05 6.308-06
1.108-03 7.778-04
1.718-13 9.298-13
2.998-01 2.708-12
2.198-13 7.228-13
2.198-13 7.228-13
1.658-15 1.608-15
bulk (de/dey) charges
1.988-12 4.878-12
-2.198-13 —7.228-13
-1.418-12 -3.738-12
-2.198-13 -7.228-13
2.198—13 7.228-13
0.008+00 0.008+00
-2.128-13 -2.648-13
0.008+00 0.008+00
-1.208-12 -1.278-12
MFPZ MFP3
CMOSNB CMOSNB
8.038-06 8.038-06
3.018+00 1.968+00
6.288+00 1.968+00
-1.968+00 0.008+00
1.428+00 9.028-01
1.188+00 7.008-01
-1.008+00 -1.008+00
-1.008+00 -1.008+00
-1.008+OO -1.008+00
-1.008+00 -1.008+00
9.758—06 1.488-05
9.258-08 4.008-07
1.278-06 8.108-06
5.098—15 3.358-15
7.798-15 5.118—15
5.658-15 1.478-15
5.658-15 1.478-15
3.768-14 3.548-15
bulk (de/dey) charges
9.308-13 2.888-14
-5.658-15 -1.478-15
—7.618-13 -1.908-14
-5.658-15 -1.478-15
5.658-15 1.478-15
0.008+OO 0.008+00

UCDCDwt-JHO

1

8

0

.OOE+00
.248— 06
.048-14
.638-14
.97E-15
.978-15
.898-14

.09E-12
-8.
-1.
-8.

97E-15
03E-12
97E-15

.97E-15
0.
-1.

OOE+OO
178-13

.OOE+OO
-2.

648-13

MP3
CMOSPB

-8.
-1.
-1.

0.
-8.

-7

-1
-1

UQQWHUQH

-2

038-06
778+00
358+00
008+00
968-01

.27E-01
-1.

00E+00

.008+00
.008+00
-1.
.748-05
.598-08
.708-06
.848-14
.078-14
.468-15
.468-15
.538-15

008+00

.62E-14
.46E-15
.68E-14
.46E-15
.46E-15
.OOE+00
-9.

0.

43E-15
OOE+00

.74E-14

MFNl
CMOSNB

O\m<3r-»0H

-1
-1

-1

UNNQAH

.088-05
.788+00
.788+00
.008+00
.688-01
.088-01
.008+00
.008+00
-1.

00E+00

.OOE+00
.298-05
.508-07
.188-05
.678-15
.328-15
.618-15
.618-15
.548-15

.84E-14
.61E-15
-3.
-2.
.6lE-15
.00E+00

36E-14
61E-15

M:\thesis\fina1 output stage\final_circuit.out 10/20/99 20:28:54

DQBDVGB -7.568-15
DQBDVDB 0.008+OO
DQBDVSB -2.30E-14
NAME MFNZ
MODEL CMOSPB
ID -1.088-05
VGS -3.038+OO
VDS -6.228+00
VBS 2.008+00
VTH -1.378+00
VDSAT -1.47E+00
LinO/Satl -1.008+00
if -1.008+00
ir -1.008+00
TAU -1.008+00
GM 1.218-05
GDS 4.358-08
GMB 2.288-06
CBD 4.50E-15
CBS 7.568-15
CGSOV 2.938-15
CGDOV 2.938-15
CGBOV 3.53E-15
Derivatives of gate
DQGDVGB 3.93E-14
DQGDVDB -2.93E-15
DQGDVSB -3.108-14
DQDDVGB -2.938-15
DQDDVDB 2.93E-15
DQDDVSB 0.008+00
DQBDVGB -5.148-15
DQDDVDB 0.00E+OO
DQBDVSB -5.148-15

-2.
O.
-5.

848—15
008+00
758-15

MFN3

CM
-1
-2.
-2

0.
-9.
-8
-1.
-1.
-1.
-1.

1

OSPB

.O8E-05

OOE+OO

.008+00

008+00
168-01

.98E-01

008+00
OOE+OO
008+00
008+00

.86E-05

2.40E-07

HNNHNIU"

(dog/d
2

-2.
-1
-2.
2.
0.
-2.
0.
-4

.888-06
.568-15
.388-14
.938-15
.938-15
.608-15
ny) and
.148-14

93E-15

.54E-14

938-15
938-15
008+00
658—15
008+00

.81E-15

-i.
0.
-3.

MC

firia
ooa+oo
848-13

CMOSNB

2.
.07E+00
.028-07
-2.

1.

1.
-1.
-1.

4
-1

-1
-1

\OHHA-ht-‘Nm

bulk

9.
-4.
-4.
-4.

8.
-2.
-9.
-2.
-1.

02E-20

338+00
638+00
828+00
008+00
008+00

.008+00
.008+00
.968-13
.298-05
.418-13
.468-15
.468-15
.478-15
.478-15
.988-15
(de/dey)

38E-14
19E-14
19E-14
19E-14
68E-14
71E-14
98E-15
19E-14
37E-14

7-6.758-15
0.008+00
-l.838-14

charges

Figure D.4: DC operating point test (cont.).

90

-9.11£-15
o.ooa+oo
-3.218—14

eeeeeeeeee
'THE CO
MPLETE
OPERATI
ONAL
AMPLIFIER WITH THE
OUTPUT
STAGE""'
eeeeeeeee

[Deatze
lTime
run: 10/20/99 23 25
: :34

27.0

Temperature-

 

 

 

 

 

 

 

 

 

 

 

 

.1
. . I
. . u 1
. . . .
...... a. . . . 1
u lllll b- a - . 1‘
o a lllll I‘I - c - 7
. . . IIIIII .II . o . <
_ llllll U u o
. ..... u _ n n ...... r u _ . v 3
tleilll . . . . IIIIII Pl . . m 3
— IIJ IIIII o . a . IIIII bl . o .-
IJI-'I - - IIIII 58 O
H H . ...... . . u . ...... 1 n
u a n . -‘Illl . C n v
IIIIII >I . . . II1III. . _ . ..
_ IIIII LI . . . II.‘ IIIII _ . 3
. . IIIII LI . . . I4 ..... . 2
a _ o llllll .II - n . 14 lllll
w . u - llllllll . - . a 4‘ l.
IIII . IIIII . . _
L ..... H u . .. ..... .- . _ m
. I4 lllll . . c . IIIII but .
. . IJ IIIII . . . . IIIILII .1
. . . II. IIIIII . . . . IIIIi T
. _ . . IIIIIII . . . .
p . . . IWIIII . . .
v 1? O n - llq llll - u
— A b o v o 8‘ ||||| .
a g - > - - ~ 'J lllll
. . . . . . . . IA
IIIII ' ~ - . P n - o
-q IIIIII . . . . p . .
4 IIIII o > .
H . IJ. IIIIII u n . . > W
. . . I. IIIIIII . . . . 5
I . . . . IIIIII . . . .
IIIII .II _ . . .IWIIII. . . . .
_ IIIIsII . . . Ii IIIII . . O
. . IIIILIII . . . IqIIII I.
. _ . IIII.II . . . a IIIIII
\ll . . . . llllllll _ . . . 4
e IIIIII . . . . IIIIFII . . .
a IIIIIIIIII
.w . -.. ...... u u v u .. ..... r- u
t . . I. IIIIIII .t o . . . IIIIAIIII
C r! _ . . ”I.-a ...... . . U . .I‘
a - . u u . -.-v ...... u . u
( s C t - q """"" w u
. IIIII .
t H u . U . J ......
a . . . . . l
d . r . . _
p . . .
t . .
.1 ...... 4
u
C
r
.1.
C N
_ w
l
a 1
n
.1 e
f g
a
\I P
M
_ u
. _ . .
i . . .
_ . - n -
1 . . . P
. 4) - n u D
S n U u . U H .
my IIIII M H U H 1” n u .
T -. ...... a- . . . . . . V
IIIII L . . 4 .
5 ” H . IIIIIII “I . . . I h
l u A . - lllllll — u c -
fl IIIIII u n u - IIIIII u.‘ c c ' OI
l‘ I- a - _ n lllll P u w
u a d IIIII - - o —"0 ’hl - -
. IJIIII . . _ IIIII h)
C . U . II." IIIII . . . . IIIII A
A . . _ _ . ....... _ _ _ .
IIIII _ . r IIVIIII . . .
u __ ...... . _ ..... . .
IIII . I4IIII .
n n u ._ ....... n . . ...... .
c u u n n :4 ...... .. U n H
I!“ IIIIII _ a u _ llllll P--- - —
m H .. ...... n h u ...... ..- w
. . . IIJ IIIII . . . . IIIIII
. . . IIrIIII . . . . 9
. . . ,,..1IIII . . . 1
o > . . . IIc IIIII . I
I b a a c -4 llllll I. ) 0
. . .
S H u . . M 2
W . n ” vv r
. . m 9
On my
V1 t
(I. o_ C
I." a o
61;! 5
fi 3
Da

I

DC tra
nsfer characteristics with no load

Figure D.5

91

"nun-"m COMPLETE OPERATIONAL AMPLIFIER mm m ou'rpu'r semen-"n-NH"

Date/Time run: 01/14/00 13:24:15

27.0

Temperature:

 

 

(A) fina1_circuit.dat (active)

 

—--—-§---——1

----1

'f'

 

IIIIIII

---L----d-----L----

IIIIIII

 

lllllll

 
 
 
 

— ---L~---J-----b—--o<—-n--b—~--J-I—--.L-vu—q

IIIIIII

--_--.----q-----p----<----->----q—---->----4-----»----4

d---ooh----4-.

IIIIIII

 

lllllll

-.---..----- ---.--.-4—----.----¢.---.p---n‘.---->--.-a-----~-.--

.1

IIIIIIIIIIIII

A----q ----L---.J-----L-...q.----L.--.J-.---L-.--.-.-.-k..-.4

I IIIIII

 

----.'--- ------'-.--q-----'----4...--r----g--..-r-_--1--..

.1

      
 

IIIIIIIIIIIIII

-—.—-----t----

0

 

lllllll

-u—-‘---'-D—-‘-‘-----

-L-

u..-----b----‘.----

IIIIIII

IIIIIII

IIIIIII

 

villlll

 

pn-noqnno--.----d---o-~--u-.¢n--.-----.--—-

L----J---—------J----

IIIIIII

 

IIIIII

p-..-‘----.p-uu-‘c-u.-p-o--'-o---—----'-----

>----‘-----p----4-----b----.-----p---_.-_--------._ --

p.--.J----.p_--.J-----h--

 

 

.0V

5

0V

5.0mv

4.0mV

2.0mv

0V

-2.0mv

-0.0mV

-5.0mV

o V(6)

 

D‘te

:05

13:26

Time:

Page 1

January 14. 2000

ith load.

ics w

DC transfer characterist

Figure D.6

92

<'( -. IopC
"’""""'THE COKPLETE OPERATIONAL AMPLIFIER WITH THE OUTPUT STAGE“""""""

0P6 N LOOP GA , N (A) tinal_circuic.dac (active)

:1 DB(V(6))

n P(V(_6))

 

Figure D.7: Frequency response with Cc = 10 pF.

93

For (t -

OPL

"""""'THE COMPLETE OPERATIONAL AMPLIFIER WITH THE OUTPUT STAGE"""""""
Temperature

10/21/99 00:23:15

:27.

 

Da te/‘I‘ime run:

final_circuit.dat (active)

__...__ _-_-

 

 

  
 

 

  

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(A)
f 100 T f I Y
I """""" GAIf’E'SSW
i III:II:Iii1iiiiiiifiil:w
ll 50 ' ‘I
t ----- 1 -------------- r ------- . .
g‘ ------ J. -------------- .L ------- r ------- ‘ -------- r-----~. -------------- J. --------------- .‘ ------- 1
I I I 1 ' ' {CROSS (WER' =‘ $1535 '10!
’\
1R
! .......
I ....... ; ....... I
‘ .......
I ;
.} 180d e A T Y Y 7
f ------ 4 --------------- ‘r ------- » ------- ' --------------- 4 ------- « ------- 'r ------- r ------- . --------------- ; ------- 4
g -------- : ------- ~ ------- ------- ~ ------- : ---------------- ------- <
I >6r7—d81 ------- 4 ------- + -------------- j -------- + ------ f ------- « ------- r ------- > ------ 1 --------------- f ------- <
g -od : ' ' : ' + : t
,7 L ------ a ------- J ------- v -- ------- I -------- >— ------ v ------- 4 ------- :- ------- r ------ a --------------- 'v ------- 1
J ’ """ ‘ """" i """" r """"""" . """" * """ 7'“ """""" r """" NR """" ‘
i """"" _' """" 4 """" 1’ """""""" 1 W. """" 4 """" 1"'!5F{A‘SE"MAR"'G‘INH=3'53_Eleg'r'\eéi """ 1
! ‘193d : f f t f t t \
‘J (WW: ....... .............. f ........ L ...... . ....... r ....... j~ ....... L ...... «f ............... }---\.I
. ...................... ............... .' ....... 1 ....... L ....... L ...... 4 ............... ; ...... .\
i I I | l l I I
n ...... 4 ....... I ....... ; .............. : ........ _ ...... ; ....... I ....... ; ....... _ ....... : ............... ; ....... a
j SEL>>F 2 : : 7 ' t ;
‘ _400d[ 4 1_ 1 1 1
I 1.032 10112 1.00112 1.01012 10KHz 100m: 1 014112 101m:
:2 P(V(6))
Frequency
0 .
“he ‘ October 21, 1999 Page 1 Tune: 00:26:31

Figure D.8: Frequency response with Cc = 8 pF.

94

IDate/Time run: 10/20/99 23:40:27

!

"""""'THE COMPLETE OPERATIONAL AMPLIFIER WITH THE OUTPUT STAGE"""""""
Temperature: 27.0

001Fur IAAPEDANCE

(A)

final_circuit.dat

(active)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure D.9: Output impedance.

95

................ [W4
1.0x \ J
0.5x f
r ------ <3 --------
*aoo'r' “=‘f ‘15' bh'm'
0 Y L
1.082 10H: 10082 1.0KHz 10KHz IOOKHz 1 ONE: 10KHz
I o V(6) / I(IT)
L———~—~_____, Frequency
Date: October 20, 1999 Page 1 Time: 23:42:33

 

 

 

 

 

 

 

 

 

 

 

 

"""""'THE COMPLETE OPERATIONAL AMPLIFIER wITH THE OUTPUT STAGE""""'“""
lante/Time run: 10/20/99 23:43:21 Temperature: 27.0
! COMMON ”‘00? GAIN (A) final_circuit.dat (active)
9 0 fit m ,
I GAIN 3.: —o.3s (18 :\\L
I P """" 7 """"""""" T """" "
1 ~ ------ é ------- -------
J -40 ‘
I ----------------------- ‘f ------- ‘ - -
1 r ...... ....... - A ~
! SEL»1 E f E i 5 5 i
-80 A 4 A L L A
o DB(V(6)) Com/WON moo; PRIME
0d r5 ‘4 1 T ‘r r l T
1
l
i

 

 

 

 

 

 

 

 

 

 

l
'
I ~500dw. * ‘r . . A . ‘ 1
! 1.0Hz 10H: IOOHz 1.0KHz 10KHz IOOKHz 1.0MHz 10KHz
o P(V(6))
' Frequency
Page 1 Time: 23:45:47

 

\
Date; October 20. 1999

Figure B.10: Common-mode gain.

96

"OOOD‘itfiiTHE

10/20/99 23

Date/Time run:
r“

C max

:47:35
(A)

final_circuit.dat (active)

COMPLETE OPERATIONAL AMPLIFIER WITH THE OUTPUT STAGE""""'*""
Temperature:

27.0

 

 

 

'-‘-—‘_ v
L----:::::___

........

------. -- ......

 

----------------

 

................

 

:-—------L ...............

.......................

 

...............

........

 

 

 

 

 

 

 

 

 

 

 

*fi‘.______‘______ .4— —-—-——_——'

  

 

 

407\LUWH .......................................................
‘“‘~‘-__--.---_¥ _______ ' ...........................................
4___::"3"-—- “) """"""""""""""""""""""""
30 “-------> --------------------
1 on r
v 2:33 10H: 10on 1.01012 101m: 101m:
(“Menu/many)
. Frequency
Date. Oc
tOboe-r 20, 1999 Page 1 Time: 23:49:53

 

Figure DJ 1: CMRR.

97

 

"""""'THE COMPLETE OPERATIONAL AMPLIFIER wITH THE OUTPUT STAGE"""""""

(A) fina1_circuit.dat

° Dawmn

Figure D.12: Power Supply Rejection Ratio (PSRR) for V55.

98

"""""'THE COMPLETE OPERATIONAL AMPLIFIER WITH THE OUTPUT STAGE"""""""
Date/Time run: 10/20/99 23:56:03 Temperature: 27.0
F__——_—_

(A) final_circuit.dat (active)

 

 

 

 

W-__.__ _.._

 

 

 

 

 

 

 

 

 

 

 

1 ' 0H2 1on 10on 1.01012 101m: 100m: 1 . om: 101m;

 

 

° Dme)
Frequency
Date:
OCtober 20' 1999 page 1 Time: 23256'51

Figure D.13: Power Supply Rejection Ratio (PSRR) for VDD.

99

"""""'THE COMPLETE OPERATIONAL AMPLIFIER WITH THE OUTPUT STAGE*"*"""""
Date/Time run: 10/21/99 00:04:10

Temperature:

27.0

 

 

(A)

fina1_circuit.dat

(active)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-------------------- -:-----r----¢I---—-:---boo----------~ - ---a'-----l>---L- e-—~—u-----L----------u >-o---~-o---~-’
0A+ . : ' ' : ' : :
L I ’ (D I f I
.............. .L-.---4-----p --_d-.--.t. L‘-----..‘-‘-r-'--d-‘---h-'I -----I-_---I----.I.----L- ,-¢-_-_-I..---{
l '- I I I I 1 I I
- - ----- .-——L-‘. ---------- . ..... ----- : ..... : ----- '--- ..... ' ----- I—--4 ----- - qr; ..........
, J _ -1 ..... ' ..... ..... :-_-L_; ..... ..... L--Ie ..... : ........... : ..... ;__I-; ..........
. . . I . . I . I I .
- 1-; .......... - -------'---.I ..... z ..... I” 4 ..... '--- ........... --.-..4- -- ........... I
I I I I I l l I q r u
—Som [ I I I l : I I I
I I I I I I I I I t l
I l 1 I I i I I I I I
I I t l I . I I I I
----- 4 -- -}-|o-----¢~---~r----<----->---qP--oe----u—----y-----—-----»- b -----I----->---------->--p-¢--o--I-----
- ----- , -; ----- ', ----- L ..... - ........... ; ..... ;---I ------- j ----------- ' ----- ------------
I I l ' . I ' I l L 3 .
"‘I't -------- ----- 7""? ---------- ----- ----- f ----- * """"""" --------
' I: : Isc - 3' 95 m. ' : : : : : :J : :
}* ‘-1 """""" L1 """ l """""" 1 """ I"-(' 7 -------- I '---I """ r"~ '''' . """"""" ’v ---- r""w “““ I """
I I KG ' 3 J1 I I I V S I l I I
"1(3(3rn}\ I. i I If I 4; L ; L L l l L
Os 0.5ms 1.0ms 1 Sms 2.0ms
O I(ROUT)
Time

 

: OctOber 21, 1999

Figure D.14: Short circuit current.

100

Time:

00:06:16

I
l
I

I

 

 

 

 

"""""'THE COMPLETE OPERATIONAL AMPLIFIER WITH THE OUTPUT STAGE"""""""

Datea/”1‘itne run:

I—

27.0

Temperature:

10/21/99 00:29:01

 

.dat (active)

_circuit

final

(A)

 

 

 

 

 

       

 

    

 

I

   

I 1‘ I [Ill 1 [I
. . . . _ . . . . . .
. . . . . . . . . .
IIIII _II. F IIL; v ILII If IILII I IIhIII.I.IIFI PIIII.III.PII A
. . . _ . . o . . . -
. . s _ . . . . . . .
. . o — . . . . . . .
IIIJIIII‘IIIJI I4.III-IIII4 I IIIII d IIIIIII < IWI J. I I
. o . . . . . . . .
. . . . . . - . _ .
I LII-,P IIL. LII PIIItIIII knoll—.Itnbl I IIIII VIIIL IIIIIIII
. . o _ . g n . . - -
. . . . . . . . _ . .
. o . - n . g . _
i — II.‘ _ . . .
. . . . . . o
. u n . _ . c
IIIIIIIII V It-IIIvIIIOIIIIYIII‘ IIIIIIO
. _ . . _ . .
_ u c . . _ -
-.-u.---r---t ........ t--.-r---h ........ .
. . . . . . .
. . . . . . .
. . g . . . n
v0 all v11 IJI 1| I4I IWI I. IIIII d
_ . . . . .
. - a _ . .
p b L r L b u
. . . _ . .
_ . . . . . .
_ - . a . . o
IIII.IIII~.I.IJIIIIYIII II‘IIII4IIII I a
. . . . . . .
. . . .IK- . — -
-I.lells‘i.u|.nlnluxI-.L.IIITIII. IIIIIIII o
. . . . . .
g . . . . . .
_ . . . .
III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
. . . . . .
— . y . - -
. . . . -
. . _ . .
. . . . .
4-.-4----r.-Ic-.---I,I._----.---...-..f.-.-_
. . — . - o
. . _ . .
. . . . . .
III; IIIII 1IIIJIIII JIIII.\III¢ IIIIIIII d
. . _ . . .
. . _ . . .
IIIIIII rIIILIII. I..I .fII 5 III..-»
M _ . . . . .
v . . . _ . .
. . . . . .
4 d ‘J _ a .
. . . _ . .
. . . . . .
v..IIIII.IIIIIAI..IV I 5 YII . III IIIIIIIIIIIIIIIII
. . . _ . .
. . . c . .
iIIII_.II I. IIIIIIIIIIII .IIIII.III. .
.
.

 

 

 

 

IIIII

IIIIIII

 

 

 

 

 

 

16us

ldus

12us

10us

Bus

8
u
2

CD V(6)

Time

Page 1

00:30:21

Time:

 

October 21. 1999

Transient Response for a 7V pusle.

Figure D.15

101

Date/ Time run:

2!)

(APACI'IIVQ LODDMJO- COIN :

"""""'THE COMPLETE OPERATIONAL AMPLIFIER WITH THE OUTPUT STAGE"""""""

10/21/99 00:34:10

(A) final_circuit.dat (active)

Temperature:

27.0

 

 

 

   

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

‘T“'_“* T f T . .
L—— 2-- w ------ J -------- L ------ J: -------- I ------ I: --------------- a; --------
~ - -- -4 -I --------------- - ------ 4 --------------- --------
r- —‘ .J'- --r ...... .1 ............... J ............... 4| ............... J ........
-o - ' if L i A
r ‘- ------------- [ --------------- )--------I-------~—-----—Jl-—-'------------I. --------
L‘ - ----------------------------- [ ------ 1 -------- b ...... 1| --------------- ‘I --------
f" - - ---------------------------- )— --------------- r— -------------------------------
a '- a: --r ---------------------------------------------------------------
‘ L - - ............ - _______________________________________________ L _______________
~ --- ............ L ..............................................................
I--- I- ............... I ........ . .
K r -- ----------------------------------------------- I ——————————————— e ............... é ——————————————— e --------
L‘ ‘-“--|: 'I- ------------- L'-----1--------h--9----1-----~---------s-----~-~-v-----V: ----------------------
‘SO—L‘\ : 1 L 4'
1. T . I
032 1on mom 1. om: 10KHz 100m: 1. om: 10m:
‘3 Danna)
Frequency
Date:
Oct—Ohm: 21, 1999 Page 1 Time: 00:34:34

Figure D.16: Effect of capacitive loading (CLOAD = 100 pF).

102

"""""'THE COMPLETE OPERATIONAL AMPLIFIER WITH THE OUTPUT STAGE"""’""""

(active)

 

Figure D.17: Effect of the change in the power supplies.

103

"""""'THE COMPLETE OPERATIONAL AMPLIFIER WITH THE OUTPUT STAGE"""""""

(A)

 

Figure D.18: Effect of the change in operating temperature.

104

"“"'"'"THB COMPLETE OPERATIONAL AMPLIFIER wITII THE OUTPUT snornnnunrn

Date/Tine run

-20.0

Temperature

19:16

01/14/00 13:

 

 

(A) tina1_c1rcuit.dat (active)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

. . u _ - -
. . . . . . . “A. n n u H n u n u .
"0--. I 0 'l I I'll ‘0' I
H H .II A. A. LIIJIVIQI IJIIAI III A II1IIIAI IOIIITIIAI IYIII
. . .
vllI.II|-III-’II.I . . Q a H u U H n . . n
. 4 . I. IIIIJIIIlIII.ITIqI IlIIaI I.II I.vII..II1I ImIIIuIIImIIIuIIII
H . . . . . .fi . A . . . A . . . c
rltl.|loul IHIIIAI IVIILIIIrIII.I IF! ILIILI I'll LvIIPIIII IDIII.III.— '-
. c . . u u . . . . o . .III.IIA
VIIITIIOI I. . . Av .fi . . . . . . . . .
o . '1'-..I -W'I-“I-"nl|.' 0.- IrIU‘- 0" ‘VI-"II.A- -‘II'tl-.l.-"-|A
. . . . . . . .
h u n “I . . - . . . .Av . . u u n
. . . . u u 4 a q 4 q q a q q 4
Av . . . . . . . .
0--. IIIII - n
v . w IHIIIAI IrIILAIIIWIIIHIYIWI IIIILI tr.- L IIPIOII IhIIIrIIbIIIFIIA
. . . . . .
. . . . . . . . . . . . .
-0 0-- ’ 0 ‘I 0 I Q C O
f I” H .Y A rIILIIITIIIoIIIOI IIIIAI IVI AYIIVIIII IeIIITIIhIIIPIII
. . . . . . . . . . .
II. . . . . . .Av . . . . . . . . .
II'I . | 'l 0 0 0' 0-- |'- l - 0 '0 - 0 0 C
u u ”I J. 1 J. 11 o v. < 1. J ‘ JYII‘IIIAI I‘dllollldlltofillh
. . .
III.III-I LII-.. -fiIIL r I. u . . . . . . . .
. . . . -II .I III I II--eI -rI tvIIrIIII I»I--.III_III..II
. . . . . . . . . . . . I
. H . . . . . . A . . . . . . . .
. . . . . . . . . u .
. .
IIIHIIInI IuIIIhI IvIIJ.II “v . r . r . . . . . u n n
I ..-0 I‘- I In". I“- JWI“I-IA' "II'III II- '0‘
n h u . . . . . . . .A . . n .u "I
v--I.III.I I.III..- -r-I.“IIIuIIIuIII»I -IIIAI .rI cwIIrIIII I.--I.-III.-II..-II
. . . . . .
. . . . . .Av . . . . . . .
I.‘ -0- I I 0- I l 0- Q I O O
v I“ n "I A. v JIIIHAOIHIVIOI IIIISI IYI Lvtl'llll IOIIIYIICIIIVIIL
. . . . . . . .

I I. . . . . . o . .
.I.I-IAI IfiIIa- IIIIJIIIaTIJII.‘I -xIIhI .vI .4..--VIIII IuIIIVIIAIIIvIII
.F n H H n n n: H . . . . . . . .

b P h - - p
n u u u H n . . . . . . . . w u
f . . . . . . . .
IILIIIOI IYIIII IvIIL ITIILIIIOI I1IILI IrI LVIIth . .
. . . . .c. . . . . . . ”IIHIIIHIIIVIII
VIIIuvllnI IuIIIhI IYII. LA . . A . . . .0 . . . u
. . . . 1"“4 IInIvIflu IIIIHI IAII JwIIflle I<III1IIaIIIAIIIA
III.II . v . . .- A . . .
v . ImIII.III.“I IvIIunIIIrAIIAIthI IIIIbI I.II kIIIPIIJI IbIII.IIIL .
. . . . 3 . . . . . . o . . .III.III.A
.IILIII.I If . . . . . . . .3 .I . . . .
. . .II.I IwIIL. InIIIuIvIHI IIIILI IYI Lvonr III IOIIIYIIIIIIrIII
. . . . A
”I u u . . .v . . . . . . . u n u
. _ . H . g H u d J 4 )4 4‘ 4 fl 4
. . . . . . .
. h . .
VIIIIII IIIIII a- I III.III II.I I
u . . . v . m1 . w w- IJIIIHI I“: IHVIIWIII IwIIIH---A.--”.IIA
.IILIIIHI I.r s. . . .Av . . . . . . . . .
. . .II.I IrIIJIIIrIILIIIOI IIIILI IrI L.IIrIIII IaIIIfIItIIIrIII
. . . . . u n n . . . . . . . .
VIIJIIuao I1II..- IrIIJIIILAIJIvI I I . . . . . . . .
‘ 1"“- '1' I‘vl“.lll “"'1'-‘-.- -"
. . . . . . . . A . . . . . 1
1|--.l- h o o c c c u c u
. I.I I.IIII.I I IIIIIIIAIIIthI IrIII.I I.II I. II.III k . . .
. . . . . . . . . . . I I.III.II-I.III.IIII
I! P I H w Av . . . . . . . . . .
. . . . . . . . n I I I I I I I
TIII..III.I I.II. . . . . . H “Av ” H u n .
. u 1 ..I IIIIJIIIxAII-III‘I ILIIJI IfiI JYII‘IIII IdIII1IIaIIInIIII
. . n H . .Av . . . . . . . . . .
wIII.IIII nnnnnnnnnn YIII.I..Im.III.IvI.wI I III.III.IIII. . . . .
. . . . . . . 1 . . .II.IIIJI IuIII.IIII.III.IIII
. . . . . . . . . . .
VIII.III»I IrIILI I IILIII I . . . . . .
. . c o v . uA IHIVIWI ILOIJO l.'l Luvclqlllt IbllIrIILIUIVIIL
. . . . . . .v . . . . .
VII III I I II I I II . . . .
U” H ”I J- V JAIIIJIIJ'VI‘O Illll- I‘ll lel‘lll' I"IIO"IIlJ-III-‘IIL
. . . . . . . .
n u . . . . . . . . . . . u H H
. . n n . . . . . . . . . . . . :I
. . . . A . . . . . .
IIHIIIoI .uIIIdI IIIILIIIPAIIrvIeI ITIILI IrI L‘IIrIIII IbIIIrIIhIIIPII
. . . . . "Av . . . . . . . . . . I
.III.III4I I1II..I .v.I.II . . . . . . . . . .
. _ . J I1 IJIIIOI IrIIJI I1I J'IIqIIlu I4III1II4III1IIA
. . . . . . . . . .Av . . . . .
vll'llll' lo| - - - - a o
. . .I IuIIIrIIIIIIIIIIIrIII IIII I I.IIII.vI. . . . .
. . . . a . . I.IIIII II IIIIIIIIIIIII
. . . . . .Av . . . . . . . . . . .A
VIII.IIIpI IFIILI I II III . . . .
_ . . . f I” "IIIHIIIoI IIIIAI IWI In‘IIWIIII IsoIIrIIeIIIrIII
Inn .1 h . . . . . . . . . u u H u
. . . . I I I I J I I I I I
fIII. . . . u ”A “Av H . . . . . . . .
.---a---n--a- -.--4---q -J-I-a- -IIIA- -v- Ac--v--I- -n---r--A.--r--I
. . . . . . . . . . . . .
vlll.II|>I IrIILI III- I . A . . . ~
. . . . .“IIuAIInIfIwI IIIIL.I I.rI ....II.rIIII I>IIIrIILIIIrIII
. . . . . . . . . . . . . .
+IIJIII0I I1IIaI IIIIJIIITAIIITIOI IhIIJI 1. . . . . . .
I I J‘IIVIIII IoIII II III II
n n n n . .Av . . . . . . . ”I a. H. 4
VIII.III-I I.III._I -rIIInIIITAII.IvI.I I II.I . . . . . . .
. . . . . . d J a I.II JwIIWIIII IdIII.III..III.IIII
r . . > E H 5., . . . .v . . . . .
D L! F P P F D b
o u a a a
o 1 u o
a" 2 2 m 2
. _ 2

 

20mv

-15nv -10nv -5mv 0V va 10mv 15mv

-20mv

o ID(H15)

 

13:21:08

Time

Page 1

 

to: January 14. 2000

ting temperature on the currents.

In opera

Effect of the change '

Figure D.19

105

M: \thesis\final output stage\abopamp2.out 11/09/99 20:13:13

 

 

 

 

FOURIER COMPONENTS OF TRANSIENT RESPONSE we)

DC COMPONENT -

iiARMONIC FREQUENCY FOURIER NORMALIZED PHASE NORMALIZED
NO (HZ) COMPONENT COMPONENT (DEG) PHASE (DEC)
1 1.000E+03 9.995E-01 1.000E+00 -5.156E-01 0.000E+00
2 2.000E+03 2.163E-04 2.165E-04 -1.763E+02 -1.758E+02
3 3.000E+03 4.068E-04 4.070E-04 8.252E+01 8.303E+01
4 4.000E+03 2.509E-04 2.510E-04 1.633E+02 1.638E+02
5 5.000E+03 1.630E-04 1.631E-04 -9.997E+01 -9.945E+01
6 6.000E+03 5.196E-05 5.199E-05 -1.766E+02 -1.760E+02
7 7.000E+03 1.386E-04 1.387E-O4 -1.034E+02 -1.0298+02
8 8.000E+03 1.037E-04 1.037E-04 -3.267E+01 -3.215E+01
9 9.000E+03 5.626E-05 5.629E-05 6.335E+01 6.386E+01
TOTAL HARMONIC DISTORTION - 5.813578E-02 PERCENT
ETDURIER COMPONENTS OF TRANSIENT RESPONSE V(lB)
DC COMPONENT A 2.640906E-09
IiARMONIC FREQUENCY FOURIER NORMALIZED PHASE NORMALIZED
NO (HZ) COMPONENT COMPONENT (DEG) PHASE (DEG)
1 1.000E+03 1.000E-01 1.000E+00 1.037E-06 0.000E+00
2 2.000E+03 1.746E-09 1.7468-08 -9.959E+01 -9.959E+01
3 3.000E+03 6.064E-10 6.064E-09 -8.952E+01 -8.9SZE+01
4 4.000E+03 2.917E-10 2.917E-09 -1.347E+02 -1.347E+02
5 5.000E+O3 3.043E-10 3.043E-09 -1.242E+02 -1.242E+02
6 6.000E+03 1.318E-10 1.318E-09 —7.080E+01 -7.080E+01
7 7.000E+03 7.188E-11 7.188E-10 1.781E+02 1.781E+02
8 8.000E+03 2.206E-10 2.206E-09 1.572E+02 1.57ZE+02
9 9.000E+03 1.803E-10 1.803E-O9 1.175E+02 1.175E+02

2.954990E-05

TOTAL HARMONIC DISTORTION I

106

 

1.923007E-06 PERCENT

Fovvie r Analjsis
_ T

 

Figure D.20: Harmonic distortion for lKHz test signal.

 

M:\thesis\fina1 output stage\abopamp2.out 11/09/99 20:46:09

 

 

POUR-1‘39. COMPONENT—S OE TRANSIENT RESPONSE V(6)

DC COMPONENT -

HARMONIC

NO

\DQOLfl-DLIJNH

0<D~JO\UIhw»rorJ

FREQUENCY

(HZ)

.OOOE+03
.OOOE+03
.OOOB+03
.OOOE+03
.OOOE+03
.OOOE+O3
.OOOE+03
.OOOE+03
.OOOE+03

1.692396E-03

FOURIER

COMPONENT

HMHQNQNW-fi

.494E+00
.1858—03
.2275-03
.4738—04
.1523-03
.0152-04
.2188-03
.2273-04
.1353—03

TOTAL HARMONIC DISTORTION =

NORMALIZED
COMPONENT

NbNI-‘Ibl-‘IDQH

.000E+00
.086E-04
.956E-04
.663E-04
.788E-04
.783E-04
.710E-04
.954E-05
.525E-04

PHASE
(DEG)

-5.
-3.
.2628+01
.69ZE+02
.111£+01
.661E+02
.0898+01
.4588+02
.6768+01

doucnraaahbm

8878-01
809E+01

1.084481E-01 PERCENT

FOURIER COMPONENTS OF TRANSIENT RESPONSE V(lB)

DC COMPONENT -

HARMONIC

NO

\Dm‘JmU‘uwaH

\OCDQO‘U‘IEWNH

FREQUENCY

(HZ)

.OOOE+03
.OOOE+03
.000E+03
.OOOE+03
.OOOE+03
.OOOE+03
.OOOE+03
.000E+03
.OOOE+03

1.226381E-08

POURIER

COMPONENT

NHO‘UIHHNQA

.SOOE-Ol
.930E-09
.414E-09
.291E-09
.220E-09
.056E-10
.812E-10
.214E-09
.952E-10

TOTAL HARMONIC DISTORTION =

NORMALIZED
COMPONENT

O‘NHHNNU‘HH

.OOOE+OO
.762E-08
.365E-09
.869E-09
.7128-09
.124E-09
.514E-09
.697E-O9
.560E-10

PHASE
(DEG)

1
-1

-2

.028E-O6
.006E+02
-8.
-1.
-1.

486E+01
2118+02
3728+02

.389E+01
-1.
-1.

1.

573E+02
586£+02
6223+02

1.913577E-06 PERCENT

NORMALIZED
PHASE (DEG)

QHQHQHO‘UO

.OOOE+00
.7SOE+01
.3213+01
.69BE+02
.17OE+01
.667E+02
.1488+01
.464E+02
.7353+01

NORMALIZED
PHASE (DEG)

0.
*1.
-8.
-1.
-1.
-2.
-1.
-l.

1.

0008+00
0068+02
4863+01
2118+02
372E+02
389E+01
57BE+02
586E+02
6228+02

Figure D.21: Harmonic distortion for 10KHz test signal.

107

"“""“'OPERATIONAL AMPLIFIER WITHOUT OUTPUT STAGE"*""*“*"‘

Date/Time run: 11/09/99 20:46:06 “A A, 7 A- w 3:_-fl:q W‘_ *5 WA_ 77 , _Vu__rTemperatUre: 27.0
(A) abopamp2.dat (active)
5.0V ~ - ~75~— , . ~ , ~« ,, ,L,,.L:V,IA e»
‘3
I I
T
I
)-
I I
I I
4
0 ° 3 -
. , I
I ‘I(

"j "I I.“
. ' I
I I
i
0 E
l
I - I
I i I
I I , I
I - _
-5 - 0v - — -_. ,, I". , -7. _ "eve—-_- . _- Wk». .5. .-,-_._-___f_-__...____ _ ,L . ., , -.._.,I,__ 1*“ A L .7 ,.: - .. :.
Os 0.5ms 1.0ms 1.5ms 2.0ms'
V(6) '
Time
Date” November 09,” 199§ 1'" Page 1 Time: 20:46:33

Figure D.22: 4.5 Vp.p output sine wave for lKHz test signal.

108

13 Appendix E

Layout of the new op-amp circuit

109

 

 

Figure E.l: Layout of the op-amp.

110

15 14 13 12 11 10 9 8 7 6

T_.

 

 

H‘H—‘MH‘MQ—‘Mu—‘M

 

 

 

.26 2‘7.— 28— 29 30 31 :32 39— 34 55*

 

Figure B.2: Layout of the op-amp along with bonding pads.

111

14 Appendix F

Instructional Manual for Analog IC Layout using LASI

112

1 Standard CMOS process and Layout

Introduction:

The knowledge of the fabrication process is necessary for laying out IC chips by using a
software tool like LASI. The reason is that ICs are made using layers Of different
materials like n and p type silicon, poly-silicon, oxides etc. and there is a direct
relationship between these layers and the ones we use in LASI. In LASI these layers are
displayed in different colors. As we go through this chapter we will develop an
understanding of a relationship between the standard CMOS fabrication process and

layout in LASI.

Stande CMOS Process:

There are many CMOS processes available in industry. The standard CMOS process that
we are going to use is an n-well process. This means that the wafer we are going tO use
for fabrication is a lightly doped p-type substrate. On this p-type wafer we can make n-
channel MOSFETS. P-channel MOSFETS require an n-type substrate that can be Obtained
by creating an n-well in the p-type wafer. The sequence Of the fabrication process is

described here conceptually, neglecting some details.

The fabrication process starts with a p-type wafer as shown in Figure FL]. This p—type
wafer is our substrate for making n-channel devices. In Figure F.1.2 a mask is used to
expose the areas Of the wafer where an n-well is needed. An n-well is‘doped in the wafer
in the exposed areas. In Figure F.1.3 the areas where n and p channel devices would be
made are masked. A heavy p+ implant is performed in the unexposed areas as shown in
Figure F.1.4. This implant is done to increase the threshold voltage Of the parasitic nMOS
that may be formed. This issue will be explained later. In Figure F.1.5 a thick field oxide
is grown over the parasitic nMOS by a method called LOCOS‘. The mask in the active
areas (where the active devices will be made) is then removed (Figure F.1.6). In Figure
31.7 a thin gate oxide is grown over the active areas. In Figure F.1.8 n-type poly-silicon
Is deposited on the gate oxide where gates for the devices are to be made. The gate oxide
1s etched away where sources and drains for the devices are to be doped (Figure F.1.9).
The deposited poly-silicon acts as the mask for this purpose. For the p-channel devices a
P'tYPe implant is performed in the n-wells using a mask as shown in Figure F.1.10. This
Implant Will serve as sources and drains for p—devices. Similar to step 9 an n-type implant
for n{hf—Vices is done in Figure F.1.l 1. This implant will work as sources and drains for
thefithPe MOSFET. In Figure F.1.12 a protective layer Of SiOz is deposited over the
entire Wafer and then is heated tO make it uniform over the surface Of the wafer. Contact
holes are made in the protective layer of oxide by etching at the proper places so as to
make Connections to the first metal layer (Figure F.1.13). The Contact layer in LASI
re’lmis‘il'lts these contact holes for the connections between metal 1 and active areas and
metal .1 and poly-silicon. In Figure F.1.l4 the, first layer of metal indicated as Metal 1 is
deposued and in Figure F.1.15 useless metal is removed from the wafer. Figure F.1.l6

\
l
LOCal Oxidation Of Silicon

113

and Figure F.1.l7 are performed on a chip in which a second layer of metal is required
for connections. In these two steps a layer of SiOz is deposited on metal 1 and contact
holes are made for connections between metal 1 and another layer of metal (called metal
2). These contact holes are called via and are represented by the VIA layer in LASI.
Further the Metal 2 layer is deposited on the entire wafer. Metal 2 is then removed
wherever it is not required. A final insulation layer is deposited on the entire wafer to

protect it from contamination.

While drawing layers in LASI it is not necessary to follow the sequence of the fabrication
process. This means that one can draw an active layer before drawing poly-silicon layer

(in the fabrication process the sequence is just the opposite). Similarly one can draw
contact layers before even drawing the metal lines. The software takes the layers properly

as they are supposed to be taken.

Parasitic nMOSFET:

If we see the structure formed in the Figure F.1.l4 we can easily detect a parasitic nMOS
formed in the circuit. Imagine that n-well and the drain (or the source whichever is nearer
to the n-well) of the fabricated nMOS, which forms the drain and the source of this
parasitic nMOS. The field oxide between these then works as a gate oxide and the metal
1 lying on this oxide acts as gate for this nMOS. While this circuit is functioning if the
voltage on metal 1 layer takes a value such that it turns on this parasitic nMOS then an
unwanted connection will be established between n-well and drain of the fabricated
nMOS. Therefore a heavy implant of p+ material is performed and the field oxide is
made very thick. The threshold voltage of the parasitic nMOS increases as the implant is
made heavier and the oxide is made thicker. Thus more voltage on the metall line is

needed to turn on this parasitic device.

114

 

 

p— Substrate

 

Figure F.1.l: The p-type wafer to start with the fabrication process

115

 

 

 

 

if 1 M" N: '- ‘ T l “3““ \

K

D

‘ n- Well

! .

L;-\ ‘ .Wfl - .-. ........—'.vm- .. "a... ,, _.. .1 .u. a.“ 9r

p~ Substrate

 

Figure F .1.2: n-well is doped in the p-substrate

116

 

Oxide masks

n-MOS active area p-MOS active area

 

p- Substrate

 

 

 

Figure F.1.3: An oxide mask is developed on the entire wafer to protect the active areas

117

p—Type Implant

n-MOS active area p—MOS active area
_ —
hi 2% fizz-”3. - 1 . j .. .

p- Substrate

 

 

Figure F.1.4: A p-type implant is performed to increase the threshold voltage of the parasitic n-MOS

118

Field Oxide (LOCOS)

n—MOS active area ' _ q p-MOS active area

p- Substrate

 

 

Figure F.1.5: A thick field oxide is developed in the unmasked regions by the LOCOS method

119

n-MOS active area p-MOS active area

     

p- Substrate

 

Figure F.1.6: The oxide masks are removed by etching

120

Gate Oxide

p- Substrate

 

 

Figure F.1.7: A thin gate oxide is grown on all the active areas

121

p— Substrate

 

 

Figure F.1.8: An n-type poly-silicon layer is deposited at the places where the gates of MOSFETs are
going to he made

122

p— Substrate

 

 

Figure F.1.9: The gate oxide over the sources and drains of MOSFETS are etched away using the
poly-silicon gates as masks

123

p-Type Implant

 

$5.339?” v r-c .

’ ‘ . a"
mum;

p+

p- Substrate

 

 

Figure F.1.10: A mask is formed over the wafer to implant the source and drain for only pMOS

124

n-Type
Implant

 

p- Substrate

 

 

Figure F.1.ll: A mask is formed over the wafer and the source and drain implants for nMOS are
performed

125

Protective Oxide Layer

 

p- Substrate

 

Figure F.1.12: A protective layer of oxide is deposited on the entire wafer

126

p- Substrate

 

 

Figure F.1.13: Contact holes are etched in the protective oxide layer to make contacts to the sources,
drains and gates of the MOSFETS

127

Metal 1

 

p- Substrate

 

 

Figure F.1.14: Metal 1 is deposited on the wafer

128

Contacts

 

 

p- Substrate

 

 

Figure F.1.15: Metal 1 is etched away at the places where it is not required

129

 

p- Substrate

 

Figure F.1.16: Another layer of oxide is deposited to layout Metal 2

130

/ \ Metal 2

 

p- Substrate

 

Figure F.1.l7: Via cuts are made into the oxide layer and the Metal 2 is deposited

131

2 Basic commands in LASI
Cells in LASI:

LASI uses a hierarchical approach in the layout of an IC chip. A complex layout is made
from simpler objects called cells. A cell can be a simple MOSFET or a logic gate. The
cells are given ranks depending upon their level in the design. A cell that does not contain
any other cell has a rank of one. A cell that contains rank one cells has a rank of two. A
rank three cell can contain only cells with rank one and two. A technique to make use of
this type of design using cells of different ranks will be explained in the later chapters. In
this chapter the setting of the drawing directory and basic commands used in LASI will
be discussed.

After successful installation of LASI on your PC open the folder LASI in your root
directory. Create a shortcut for the main program of LASI, wlasi.exe, on your desktop.
Pointing on the icon of wlasi.exe click the right button on the mouse. A dropdown list
will showup. Select property by using the left button on the mouse. Select shortcut page
in the property dialog box. Type M:\lasi6\w2uchip in the start-in box and click the OK
button on the dialog box. This sequence of actions sets the folder w2uchip as drawing
directory.

Start LASI by double clicking on the shortcut. The program screen shows up with menu
items on the top and the right hand side of the screen. The name of the cell and its rank is
displayed on top left side on the screen. Every time you start the program the cell will be
‘none’ and the rank will be ‘0’. A few example cells are provided with LASI installation.
They are in .TLC (transportable LASI Cell) format. We need to convert them into a
binary format to work with them. Select sys menu from the top and select TLCin
command. Type ‘.’ for source and destination path indicating the present directory. Type
‘*’ for the source cell name. Click OK to start the conversion. A warning will be given
for replacing ‘the lesser cells’. Click OK for that. Now you can work with these cells in
LASI. All the commands of LASI are printed in Italics in this manual.

Simple non-editing commands:

Menu] and Menu2:

On the right side of the screen you will see the menu] button on top. Clicking on this
button changes some of the menu items in the two columns. Also the name of the button
changes to menu2. We will explain the use of some of these menu items later in this
chapter.

Grid:

The screen on which you will draw the shapes is blank and dark. Only a cross-hair
symbol appears. This is the origin of the space we are going to use for drawing. For the
purpose of drawing features accurately we need a reference grid. Select the grid
command in menu] on right. This will show a grid on the drawing screen. Clicking the
grid button again will remove the grid from the screen.

132

Sys:

Select Sys command from the top. It is the same command that we used for cell
conversion. A controlbox will openup. The controlbox contains commandbuttons. We are
going to use many of these commands in different phases of our layout. We will use
LasiDrc for doing a design-rule-check on our layout. Lasith is used to obtain a SPICE
file from the layout. T LCout is used to convert your cells to .TLC format to save them.

Help:

Locate Help command on top. You will have to use it frequently to find information
about commands and settings in LASI. Select Help. A small window will openup in top-
right side. Click on Topics. You will see topics available in LASI’s help. You can
navigate in LASI’s help by double clicking on one of these topics.

Now we will familiarize ourselves with some more commands in top menu items.

List, Fit, Xpnd, Zoom, Cell Commands:

Since the conversion of cells is over now, we would like to see the available cells. The
command that enables you to do so is called List. Selecting this command shows you a
list of cells. A cell can be opened by double-clicking the left button of mouse on its name.
Open the cell named N3X2. This is an nMOS with W/L of 3/2. Select Fit now. The cell is
now efliciently fitted in the available space. Select Xpnd now. What happens? Select
Xpnd again. The layout now looks very small. Select the Fit command for the layout to
occupy the entire area again. Select the Zoom command now. Point the mouse on top-left
comer of the red rectangle that represents the gate of this nMOS. Click the left button on
mouse once. If you move the mouse now you will see a resizable white-colored rectangle
made-up of dotted lines. Henceforth we will refer to this rectangle as Editing Rectangle
in this text. One vertex of this rectangle is fixed at the place where you clicked the mouse
before and the diagonally opposite vertex sitting on the mouse. Point the mouse at the
bottom-right comer of the gate so that the dotted rectangle covers the entire gate area.
Now click left button on the mouse once again. You will see that the gate of the nMOS
occupies the maximum area on the drawing space. In other words the area covered by the
dotted rectangle is zoomed-in. Use the Fit command to fit the entire nMOS on the screen.

Basic editing commands:

In this section we will study commands that are related to drawing the shapes and layers.
All the editing commands are in either Menu] or MenuZ.

Cell:

In order to practice editing commands we will make a new cell named ‘TestO’. Select the
Cell command from the menu items on top. A dialog box appears. Enter the name for the
new cell: TestO. Another dialog box opens up prompting you to enter the rank of the new
cell. As our cell is going to be a cell of the lowest level it’s rank is 1. Enter the rank. A
blank cell appears. Name and rank of the cell are displayed in top-left corner of the LASI
window. In case there is no grid use the Grid command to get one. The Cell command

133

can also be used as an alternative to the List command. Entering the name of an existing
cell in the Cell command’s dialog box opens that cell.

Now we are going to draw a IOumXIOpm n-well. First, we need to tell LASI that we
want to draw an n-well.

Layer:

Select the Layer command from menu] . A check-box type list of layers appears. Select n-
well and click OK. Name of the layer appears in the bottom-left comer of the LASI
window. Now whatever shape we draw will be n-well. To draw a shape on a different
layer we need to return to this command.

Obj:

Obj stands for object. Now that we selected a layer we can draw any shape we want. We
need to tell LASI what shape we want to draw by using the Obj command. Selecting this
Obj results in a list of two shapes: Box and Poly/Path. Double-click on ‘Box’. Now the
shape we want to draw is defined as a box or rectangle.

Add:

As we are going to add a box to the cell ‘TestO’ click Add. The name of the selected
command appears in the bottom-left comer of the LASI window. Now point the mouse
on the origin (cross hair) and click the left button on the mouse once. If you move the
mouse now you will see a dotted white-colored resizable rectangle, one vertex of which
is sitting on the mouse. The diagonally opposite vertex is at origin, the place where you
clicked your mouse previously. The distance between two adjacent dots on the grid
represents lum. Move the mouse so as to cover an area of 10me10um starting at the
origin. Click the left button on the mouse again. At this time you will see a dotted blue-
colored rectangle. This is our 10me10um n-well.

Now we want to make an n-well lSuleOum by increasing its length by Sum toward
the right. For doing this we have to follow a sequence of three commands: Get, Mov and
Put (which stand for get, move and put)

Get, Mov, Put:

Select Get. Click the left button of the mouse once on left side of the right edge of the n-
well. If you move the mouse you will see a dotted white-colored rectangle as you did
before. Click the mouse on the right side of the edge so that the two parallel sides of this
rectangle intercept only the right edge of the n-well and no other edge. You will observe
that the edge becomes highlighted. Select Mov now. Click mouse on any dot on the grid
once. Move your mouse 5pm horizontally towards the right. You will see a dotted line.
Click the mouse, once again and you will see the highlighted edge move 5pm towards the
right. The edge is still highlighted meaning it is still active. We have to deactivate it.
Select the Put command. Click your mouse on the left side of the highlighted edge and
click it on the right side of the edge once again. Now the edge is not active. Our n-well
has become lSuleOpm.

134

fGet:

This command works just like Get but it activates the whole shape. Select file! now. Try
to select the right edge of our n-well as you did before. What happens? The whole n-well
becomes active. fGet effectively means ‘get the full shape’. Now that we have selected
the whole n-well we would like to make a copy of it somewhere else in the same cell.

pr and aPut:

Select the pr command from Menu]. Click the mouse on any dot of the grid. Click it
again on a dot 20pm to the right of the previous dot. You will see the n-well copied and
pasted such that each point on the new n-well is 20pm right of a similar point on the old
n-well. Also it is interesting to note that our old n-well is deactivated and the new n-well
is activated. To deactivate this n-well we will not use our old Put command (although we
can use it). Select a command called aPut (put all) from Menu]. What happens? The
whole n—well is deactivated. This means that it is simpler to use aPut command than the
Put command. But there are some situations in which we have to use the Put command
instead of the aPut command. This will be clear from the following exercise. Save your
work.

 

Exercise:

1. Open the cell ‘TestO’ you created in this chapter by using the List command. Fit the
picture in the drawing space. Press the left arrow key on your keyboard. What
happens? Now locate the Last command on top. Click on it. What happens?

2. Fit ‘TestO’ on the screen again. Select the Cntr command from the top. Point the
mouse on any of the vertices of one of the n-wells. What happens?

3. In this chapter we saw how to make use of Get, Mov and Put to move an element on
the drawing space. Now Fit ‘TestO’ on the screen again. Select qMov (which stands
for quick move). Cover one of the n-wells in the editing rectangle. Click anywhere
on the screen. Move the mouse 5p vertically up and click again. What happens?

4. Now make a new cell and name it ‘Testl’. Draw a box of SuXSu of Poly] layer.
Select Get and cover only the top edge and the right edge of the box by the editing
rectangle. The two edges will get highlighted. Now select Mov. Click anywhere on
the screen. Now move the mouse through a distance of five dots at 45 degrees with
horizontal direction on the right. Click again. What happens? Now you should
understand the difference between Get and fGet.

5. Now select the View command. A table similar to the Layr command appears with all
layers checked. Uncheck the poly] layer by clicking on it. Now select Draw from the
top menu. What happens? Again use View and check the n-well layer and use Draw.
What happens? What is the use of the View command? What is the use of the Draw
command?

6. Now we want to delete ‘Testl’. Using the Help menu search for information about
Kill and use it to remove ‘Testl ’. Use List to check whether ‘Testl ’ is really removed.

135

3 Working with cells in LASI

Importance of using cells in the layout:

Let us assume that we are laying out a circuit which makes use of four lOquOu nMOSs
and three ZOKQ resistors. Suppose that we are using only one cell of rank one to layout
the whole circuit. We can do this by simply laying out one nMOS and one resistor. Then
we can make three more copies of nMOS and two more copies of the resistor. After
interconnecting these components our layout is ready. But what if we made a mistake in
the layout. Instead we wanted nMOSs of 15 quOu. Now we have to either make changes
to all four copies of nMOS or layout a separate chip. This would be even worse if we are
using copies of an entire circuit (e. g. four NAND gates) and we want to make changes to
all of them. A troublesome incident like this can be forestalled by using the ‘cell
approach’ to the layout. In this method we will layout nMOS in a cell with rank one. We
will layout the resistor in another cell with rank one. We will make use of these two cells
to layout the final circuit in still another cell with rank two. In this way the cell with rank
of two will contain four instances of the nMOS cell and three instances of the resistor cell
and not their actual copies. So later if we want to make changes to all of them we can
make changes to the parent cells. Here we can see how important the ‘cell approach’ to a
layout is. Therefore it is necessary to learn the LASI commands related to cells.

Adding a cell to the layout:

To learn the use of this command we will first create a cell with rank two. By making use
of the Cell command create a new cell ‘Testl ’ with rank two. Use the Obj command to
select ‘TestO’. Remember that this is a rank one cell that we created in the last chapter.
Now select Add. If you look at the bottom left comer of the LASI window you will see
the command displayed as ‘Add’ and the object displayed as ‘TestO’. If you place the
mouse on the drawing space you will see a dotted white rectangle, one vertex of which
rests on your mouse. If you move the mouse the rectangle moves along with it. Now
place the mouse on origin (cross hair) and click. You will see the blue color n-well placed
on the screen. If you move your mouse now you will see that the dotted white color
rectangle still appears with the mouse. It means that LASI is ready to place another
instance of ‘TestO’ although you don’t want to. Such types of commands in LASI are
called resident commands. To cancel them you should choose another command. Get is
an example of a resident command.

Cell commands:

cGet, cPut:

Now that we have already placed ‘TestO’ in ‘Testl’ we want to move to the left by 3p.
Select cGet from menu]. Cover the entire cell with the editing rectangle. Select Mov.
Click the mouse anywhere on the drawing space and click it again 3 u to the left. You will
see ‘TestO’ move to the left by 3 p. ‘TestO’ is still highlighted. To disable it select cPut
from menu]. Cover the cell with the editing rectangle and deactivate it. We can say that
cGet stands for ‘get the cell’ and cPut stands for ‘put the cell’.

136

Outl, Full:

Now select Out] from menu2. Cover the cell in the editing rectangle. Now LASI does
not show you the contents of the cell but only its outline. Also observe that within the
outline appears the name of the cell at the bottom left corner of the cell. This command is
useful when a cell contains many lower ranked cells and we want to concentrate on the
circuit of only one cell. Then you can convert all the other cells to their outlines. Next we
will see how Full works. Select Full from menu2. Cover ‘TestO’ (now turned into outline)
with the editing rectangle. This shows its contents again. Save your work.

 

Exercise:

1. Open ‘Testl ’ using the List or Cell command. Using Help find out more information
about cMov. Move ‘TestO’ Sp. to right using cMov. Try to move it by using qMov.
Does it work?

2. Highlight ‘TestO’ by using cGet. Select the Show command from menu]. What
happens? Try to understand the use of Show by using Help.

137

4 Layout of Bonding Pads

Bonding pads are used to connect the signals on the chip to the outer world. As they are
the part of the chip their layout is an important one and should be carried out along with
the layout of the other components. Signals from the circuit are connected to pads by
metal lines. Here we will consider a simple bonding pad without electrostatic discharge
(ESD) protection.

Simple Bonding Pad:

A simple bonding pad consists of a layer of meta12 over metall. The size of both the

metal layers should be lOOquOOu. They are connected to each other by using the VIA

layer. The cross-section of a bonding pad is shown in Figure F.4.l. The top layer of the

insulator (#3) protects the IC from contamination. For connecting meta12 to the outer

world an opening should be made in the insulation # 3. This opening is represented by the

OVGL (overglass) layer in LASI. The instructions to layout a simple bonding pad are

given below.

1. Create a new cell ‘TestPad’ with rank one

2. Select metall layer

3. Select Add

4. Select box Object

5. Starting from the origin layout metall of size lOOquOOp. (Figure F.4.2)

Note: The square of the above dimensions can be accurately laid by providing

attention to the coordinates of the cursor at bottom left corner of the LASI program

window. '

Layout meta12 of the same size over metall (Figure F.4.3)

Layout the overglass (OVGL) layer of 90uX90p. such that each side of overglass is

5]). inside from the metal edges (Figure F.4.4)

Note: Start the OVGL box at coordinates (51)., Su) and make a box of 90uX90u.

Hence the diagonally opposite vertex should be at coordinates (9511, 9511.).

8. Draw 94uX94u of the VIA to connect meta12 to metall such that each side of the
VIA is 311 inside meta12 (Figure F.4.5)

>19"

Design rule check:

Each fabrication process has its limitations. The process we will be using to fabricate our
chip is called Orbit 2-micron process. This process restricts the smallest dimension it can
reliably fabricate to 2p. Along with this there are other restrictions regarding how close a
metal layer could be to a poly layer and what distance is allowed between two n-wells
and so on. All of these restrictions are collectively called ‘design rules’. All the design
rules are explained in Chapter 5. While doing layout of a chip we should always follow
all design rules. LasiDrc command performs an automatic ‘Design-Rule-Check’ on your
IC. This command does not check some design rules. Chapter 8 explains how to use
LasiDrc and interpret it’s results.

Design-rules for layout of pads:

1. Sizes of metall and meta12 of a bonding pad must be lOOuXIOOp.
2. Distance between the edges of metals of adjacent pads should be 75p

138

3.

Size of the overglass of the pad must be 90uX90u and it should be centered on the
pad.

4. The VIA should be at least 3p inside the meta12
Design rules for pads are depicted in Figure F.4.6. LasiDrc does not check these rules.

 

Exercise:

1.

2.

By making use of tables in Appendix A of ‘CMOS circuit design, simulation and
layout’ find out total capacitance between the pad and substrate in ‘TestPad’.

Go through the design rules for MOSIS in Appendix B of ‘CMOS circuit design,
simulation and layout’.

139

Overglass cut in
Insulation #3 Via cut in
Insulation #2

lnsulalimi #3

 

 

Silicon

Figure F.4.1: Cross-section of a simple contact pad

140

 

Figure F.4.2: Metal 1 layer of lOOquOOp. is laid out

141

 

Figure F.4.3: Metal 2 is laid out on Metal 1

142

 

Figure F.4.4: Overglass is laid out

143

 

Figure F.4.5: VIA is laid out

144

)00 microns

075 micron

   

Figure F.4.6: Design rules for Pads

145

5 Layout of MOSFETS

In this chapter we will first consider the layout of medium size nMOS and pMOS
transistors. Later techniques for laying out small and large devices will be discussed.

Layout of a nMOS:

An nMOS can be directly fabricated in the p-substrate and therefore no well is needed. In

the process of learning we are going to layout an nMOS of W/L of 10111211. As the width

of our nMOS is going to be 101.1. the width of active layer is lOu. Now we have to

calculate the length of the active layer. This length depends upon number of contacts we

are going to have for connecting the source and drain of the nMOS to metall. In our

example we will have two contacts for the source as well as the drain. Design rule 6.4

(Appendix B of the textbook) says that the minimum spacing between active contacts and

the gate of the transistor should be 2]). and the minimum size of a contact is ZuXZu (DR

6-1)- Design rules 6.2 and 7.3 say that minimum metal and active overlap of contact is

1N» This makes the total length of the active region 211. + 2 x (2p + 2p. + 1p.) which equals

121).. The following steps will lead to the layout of a nMOS of W/L of lOuJZu.

1- C1‘eate a new cell ‘TestnMOS’ of rank one.

2- Draw an active layer box of lZquOp. (Figure F.5.1).

3- Draw n-select around the active box such that each side of n—select is 211 away from
the active (Figure F.5.2). This makes the active layer n-type.

4° Draw a polyl gate of Zn width in the middle of the active layer such that the gate
eXtension of the active is 2p. (DR 3.3). See Figure F.5.3.

5‘ lDraw two contacts of 2uX2p. for the drain and source such that they are 2]; away
from gate and 1p. away from the active edge (Figure F.5.4).

6° We could lay metal lines on the contacts as shown in Figure F.5.5 to make the layout
of the nMOS complete but generally metal lines are laid in the higher ranked cell so
7 t-hat the design could be made more compact.

The bulk for the nMOS is the p-substrate and is connected to VSS (negative power
supply) generally at the VSS bonding pad.

While typing the SPICE file one should note down that areas of the source and drain (PD
and I>8) are SitXlOu=50u2 and their perimeters (PD and PS) are 2 x (5p. + 10p.) = 3011.
A130 the number of squares of drain and source, represented by NRD and NRS
resIXBCtively, is two.

kayo!“ of a pMOS:
or layout of pMOS we have to make an n-well and a bulk connection. The other steps

SiInilar to that of the nMOS. Design rule 2.3 says that the minimum distance of the
sourCe”drain active to the well edge should be 511. DR 2.4 says that the minimum distance
Of Well contact to the well edge should be 311. The minimum spacing between the active
Of different implants should be On or 4p. As we may connect the bulk to a different
potential than the source we will have 4p. between different actives. The following are the
Steps derived, from the previous mentioned rules, to layout the pMOS. We are going to

make a loll/2].]. pMOS.

146

Create a new cell ‘TestpMOS’ of rank one.

Layout a box of active layer of size 101LX121L (Figure F.5.6).

3. Surround the active box by a p-select that makes it a p—type active layer (Figure
F.5.7). ’

4. Draw a polyl gate of Zn width in the middle of the active layer such that the gate
extension of the active is 211 (Figure F.5.8).

5. Draw two 21LX21L contacts for the drain as well as the source as we did for the nMOS
(Figure F.5.9).

6. Draw an active layer of lOuX4p. at a distance of 411 from the previous active layer.

This will make well contact (Figure F.5.10).

Draw n-select around this active layer to make it n-type (Figure F.5.l 1).

Draw contacts for the well connections. Copying the contacts for either the drain or

source to the well contact can do this. Also draw the n-well around this whole

structure such that its overlap of the active layer of pMOS is Su and that of the active

layer of well contact is 311 (Figure F.5.12).

9. Now draw the metal layers on contact without violating DR for metal to contact

overlap (Figure F.5.l3).

[Qt-—

90>!

Now that we know how to layout medium size MOSS we will learn the techniques for
very small and very large size devices. For the sake of understanding we will consider the
layout of 311/211 size for a small device and 4011/21). size for large device. Also we will
consider the layout of only nMOSs because layout of pMOSs are similar with a
difference of only a well.

Small nMOS:

We can not layout an active layer for a 2111211 device as a simple box in a way we did

before because then we won’t have enough space to place contacts without violating the

DRs. Therefore the following technique is used for this kind of small devices.

1. Create a new cell ‘SmallnMOS’ of rank one.

2. Draw an active box of 21tX41t (Figure F.5.l4).

3. Draw two 41LX411 active boxes on both of the sides of the previous box as shown in
Figure F.5.15.

4. Surround this structure by n-select such that its minimum overlap of active is 21t
(Figure F.5.16).

5. Draw a polyl layer of 211 width at the center of the middle active layer such that its
minimum overlap of the active is 21L as shown in Figure F.5.l7.

6. Draw 21tX21L active to metall contacts, one for each drain and source (Figure F.5.18).

7. Draw the metall lines for the drain and source connections as shown in Figure F.5.19.

While typing a SPICE file for this device one has to remember that areas of source and
drain are 41LX41L. Corresponding parameters in SPICE like AD and AS must be 41tX4p. =
16112 and PD and PS must be 2*(4p.+4p.) = 1611. Also the number of squares of drain and
source, represented by NRD and NRS respectively, should be equal to one.

147

Large nMOS:

If we attempt to layout a large size device in a same way as we did for a medium size

device we will end up in using the available space inefficiently. To fit a large device

compactly we will follow the technique described below.

1. Create a new cell ‘LargenMOS’ of rank one.

2. Draw an active box of 3611X1011 (Figure F520).

3. Surround the active by n-select so that its overlap of the active is 211 (Figure F.5.21).

4. Draw four polyl layers of 211 width such that the first from left and right are 511 in
from active edge and there is 611 between all polyl layers (Figure F.5.22).
Note: This is because we should leave some space for metall to active contacts.
Active layer overlap of contacts is 111. Also contacts should be placed 211 away from
the gate. Layout of a large device is somewhat difficult to understand. Therefore it is
suggested that you go through this procedure once again after you finish the layout of
this device.

5. Draw contact layers for contact with metall without violating DRs (Figure F. 5. 23).

6. Draw metall boxes on contacts (Figure F. 5.24).

The equivalent circuit of this‘type of layout is shown in Figure F.5.25. This structure of
four 10111211 devices in parallel is similar to a single 40111211 device. Adding currents from
four devices can prove this.

 

Exercise: 1
1. Layout a 40111411 nMOS in a new cell of rank one. Draw metal] connections to its

terminals.
2. Layout a 31111011 pMOS in a new cell of rank one. Do not draw metal] connections.

148

 

 

 

 

 

 

 

 

Figure F.5.1

149

 

 

 

 

 

 

 

 

 

 

 

Figure F.5.2

150

 

 

 

 

 

 

 

Figure F.5.3

151

 

 

Figure F.5.4

152

\\\\\\
\\

\ . \\\\\\\M

 

 

Figure F.5.5

153

 

 

 

 

l . \ .
l
‘ I I \

 

 

 

Figure F.5.6

154

 

 

 

 

 

 

 

 

 

 

Figure F.5.7

155

 

 

 

 

 

 

 

Figure F.5.8

156

 

 

 

 

    

lil‘il' . i!!-lli|.!ll‘ Ii
. .3. .\.1...l...l .2 ...—.vo._.(.o.._.=.w..2... . .
... L. I. . . 2.. é ....... .f.
s. . . . .. r . . . .
.1, 0......
1.5.?th . I

 

 

  

 

 

 

 

Figure F.5.9
1 57

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure F.5.10

158

 

 

 

 

 

 

Figure ES.“

159

 

 

          

    

        

     

 

 

 

_ _
_ .
h _
u .
. h
m .
_ in? “w... .3 .. J
. u . gfluudx . u _
_ h
n n
u n
r .
h .
w m
. _
m _
_ m

Figure F.5.12

160

 

   

.. ‘W {\wr
fix. §«%\e\x§®m

amused“? a». see
\Wewx

  

 

   
  

EK‘M‘g’.

 

 

  

sank. sedge.

§

    

   

§

Figure F.5.13

161

 

 

 

 

Figure F.5.14

162

 

 

 

 

 

 

 

 

 

 

Figure F.5.15

163

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure F.5.l6

164

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure £5.17

165

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure F.5.18

166

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure F.5.19

167

 

Helium

 

 

 

 

 

Figure F.5.20

168

 

 

 

 

 

- "'2' ' Li r . '
. 1’ - . - - ‘
'I' ' - '1 .(.« 1
I I 1 I l! q l 1
( 1". V t i r-(:
- '1 ' ' "('1 :

     

   

   

 

 

 

 

Figure F.5.2]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

    

 

 

i
o
.. u 4. .1
J 34 .iwmuudffi 7.: r
. c I u
A :7.” Tut-.3. . A
i t. . i
i 11, .4
.I :4 ...-.

 

 

 

 

 

 

 

 

Figure F.5.22

170

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure F.5.23

171

 

\‘\
\ \‘~\
,\ \ t

 

   

/V
/
I,”
[4’
l

A
/IL
yr
A
,,l
l 1

//'/4'1/// " .

 

,L; 1.4 '.

 

 

 

 

 

 

 

 

 

 

 

 

 

   

 

 

 

 

 

 

 

Figure F.5.24

172

 

 

I Drain

L
| Lll
Ell —ll 1 [—

Each Device
is 10u/2u

 

'2 Gate

 

 

if

 

 

 

 

 

 

 

 

Source

Figure F.5.25

173

6 Layout of Resistors and capacitors

Resistors:
Resistors are generally made-up of n-wells. The resistance of n-well depends upon its
resistivity and dimensions. In the terminology of chip layout resistance measurement is
based on sheet resistance of the material and its unit is ohm/square (written as $210). The
following derivation shows how we arrive at this unit. Consider the material shown in
Figure F61. The resistance of the slab can be written as follows.

_ p L

t W

The quantity p/t is called sheet resistivity (units 9/0) of the n-well and written as R0. It is
characteristic for a well. If one knows the sheet resistivity of the well then one can
calculate its resistance by using the ratio of its length to width. In the process we are -
going to use the value of sheet resistivity is 25009/0. Therefore resistance of an n-well
with length of 10011 and width of 1011 is 2500*(1001111011) = 25m.

Layout of small resistors:

Now we will discuss the layout of a small resistor. For laying out the resistors we do not

use the box as an Object but we use the path instead. We will layout a 25m resistor as

an example.

1. Create a new cell ‘Re325’ of rank one.

2. Select the Wdth command from menu]. A dialog box will show up. Enter the width of
the path as 10. This sets the width of the path to be 1011 (Figure R62).

3. Now select path Object and choose Add command. Select the n-well layer. Click the
mouse once at the origin. Take the mouse 10011 to the right. While you layout the
path you will not see a box as you did before but you will see just a white dotted line.
Now click the mouse again. After you decide the end-point of the path and click your
mouse the width of the path will be visible. Now you will see that the right edge of
the path is still active. Deactivate it by using aPut (Figure R63).

4. Now we want to make contacts to this n-well resistor to connect it to metall. To do
this make 411X411 active boxes on both the ends of the resistive path as shown in
Figure F.6.4. Along with active layers one has to draw n-select layers as shown.

5. Draw 211x211 contacts in both the active areas (Figure F.6.5).

Measurement of resistance using LASI:

LASI provides a command (Res in menuZ) to measure the resistance of a path. For the
purpose of using this command you need to make some changes to a file that LASI uses
when you open the program. This file is named forrn.dbd and exists in the working
directory (w2uchip). Open this file using notepad. This file contains numbers for all the
layers LASI uses in the layout. At the end of the file type the following command

Res = 2500 -800 ~1000 10

Note that there is a blank space between 2500 and -800. Similarly a blank space exists
between —800, -1000 and 10. Number 2500 represents sheet resistivity of n-well.
Number 800 is the end correction and 1000 is corner correction. Number 10 represents

174

the characteristic width of the path. Remember that we set the width of the path to this
value.

Save the file after making changes to ‘form.dbd’. Now reload LASI. Open the cell
‘Res25’. Select fGet and activate the whole resistor using the editing rectangle. Now
select the Res command from menu2. Click the Load button in the dialog box and click
Continue. Resistance value of the resistor will be displayed at the bottom of the LASI
window. Is the resistance 25 K52 as we expected? Although total number of squares in
our resistor is ten the squares at the two extreme edges can not be considered as complete
squares. This is because we have placed our connections on these two squares. Therefore
the end correction applies and we have to subtract 80052 from 25K52 which gives us
2420052 (the value given by LASI).

Layout of big resistors:

Layout of big resistors can not be done in a way similar to the smaller ones. Big resistors
are laid out in a serpentine way, as we will see shortly, to use the available space
' efficiently. There are two ways to do this. Let us take an example of a 100K52 resistor for
this purpose.

Wayl
. Create a new cell ‘Res100a’ of rank one.

1

2. Using path Object layout an n-well in a serpentine pattern as shown in Figure F.6.6.
For laying out an n-well in this fashion you will have to click the mouse at the origin
first then take it 10011 to the right then click it once more. Now you will see that the
well appears but the right most edge of the well is still aCtive. If you try to move your
mouse now you will see a dotted white line. This means that LASI is still ready to
layout the path. Now take the mouse 5011 up. Click it again. Now we have laid out
total of 25K52 + 12.5 K52 = 37.5K52 (without considering corner corrections and end
corrections). Take the mouse 10011 to left and click. Take the mouse 5011 up and click
and then take it 10011 to the right and click again. Now we have laid out mom of
resistance. Now deactivate the edge of the n-well using the aPut command.

3. Now we need to make contacts for connecting this resistor to metal]. First make
411X411 active boxes at the two ends of the resistor as shown. They should be placed
in the two end-squares in such a way that they are centered with the end-squares. Also
draw n-select around them such that its overlap of active is 211 (Figure R67).

4. Now place 211x211 contacts on the active region (Figure F.6.8).

Now measure the resistance of this resistor by using Res command of LASI as we did for
small resistor. Is the resistance 100 K52? If not, can you explain the value? The resistance
of the comer part is taken as 0.6*RD. In our case 0.6 of 2500 is 150052.

Way2
Avoiding corners is the preferred way of laying out resistors for analog circuit where

ratios of resistors are important.
1. Create another cell ‘ReleOb’ of rank one.
2. Layout 10011 n-well using path Object (Figure F.6.9).

175

3. Draw active boxes, n-select layers and contacts (Figure F610)

4. Using copy command copy this structure three times such that the spacing between n-
wells is more than 1011 (Figure F611)

5. Connect adjacent n-wells in a serpentine pattern using a metall layer as shown in-
Figure F.6.l2.

You can not measure the resistance of the whole structure by activating it and using the
Res command. Instead you have to measure the resistance of only one n-well by using the
Res command and multiplying by four. What value do you get? Is it 9680052?

Capacitors:

Capacitors are designed using polyl and poly2 layers. The Poly2 layer follows similar
design rules as the polyl layer. Design rules for capacitor formation are summarized
below.

 

Layout of small capacitors:

Capacitance per unit area between polyl and poly2 is given in Appendix A (page 856) of

the textbook. Typical value of this capacitance is 493 aF/11m2. We will layout 0.1972pF

capacitor for the sake of understanding the layout of a capacitor. The area required for
this capacitor is 2011x2011. Follow the steps given below to layout this capacitor.

1. Create a new cell ‘Cap2’ of rank one.

2. Layout a box of Poly2 of size 2011x2011 (Figure F613).

3. Layout a box of polyl of size 2411x2811 such that its overlap of poly2 on three sides is
211 each (see rule 4.3 in the above table) and the overlap of the fourth side is 611 to
accommodate contacts on polyl (rule 4.5 and DR for polyl and contact) (Figure
F614).

4. Layout contacts on polyl such that they are 311 away from the poly2 edge and 111
away from the polyl edge (Figure F615).

5. Layout contacts on poly2 such that they are 31.1 away from the poly2 edge and 211
away from each other (Figure F 6.16).

6. Layout metall boxes on contacts for connections (Figure F.6.17).

A capacitor on chip consists not only of the capacitance between polyl to poly2 but also
series resistance of polyl and poly2 and the contacts. Therefore series resistance is lower
if number of contacts is higher because contacts behave like resistors in parallel.

Layout of large capacitors:

Large capacitors are laid out as if they are interleaved fingers. This is done to reduce the
series resistance of the capacitor by adding more contacts. The layout of such a big
capacitor is shown in Figure F.6.l8. This is a 1.5776pF capacitor. While laying out

176

capacitor in this fashion attention is given to the rules in the previous table. Similar rules
are also given in Appendix B of textbook.

 

Exercise:
1. Make a capacitor of value 0.788 pF. Find the area of the poly2 needed for this
purpose.

2. Make a resistor of value 75K52 and place contacts.

177

fflfl‘f‘fi

    
 

L => length
W => width
1 => thickness

f) => resistivity

Figure F.6.l: The concept of resistivity

178

 

Figure R62

179

o

..
n.
..
1.
o.
u.
u
o
-.

-...
.,,,
_-

...

...

... ..
......
... ,
0 .....
. .....

.. ...
... r.

..1..
1.

o- ......~..
...... ... v

....... ..-,.
... . ,. .
. . ..

.. .... .... ,

... ,,,,.,..
.-...1.....,
... .. .
.... ...... 1
., . . ,
. .....
..... ... .

a
.
a.
—
l.
-
e.
n.
.o

u

o.
.o
a

......... ... ....
. ..u ............
....u ...:n....-... .
..1.. . ... . ... ...
... ......1 ...
.. ., ... .....,.. ..
. ... .... ...... .

.. .. ... ..

.... ............ ....

..........- ». ...

... ..... ... .......

.........,. .......,
.1 . .. ....,...

. .... . .. .. -

... ....,.............
...-.....1... .... ...
.. ...-...... ....

- ... .. .. ... ...
..............1.......
............_....,.....
.......u.c-. .......
......, . .. ....
......i.,.. .. .. ..
1 . .. .. ... . n
_-—---..—-—-- —
....,. ......... ...
. .. . ... . . .
.. ...1n...... 1.
.. 1. . .. ..
. .... ... .
.... ...............-
. ....................
... ... ..... .1...
. . ,. .i ..
.1. .. .

Figure F.6.3

..
..
..
s.
.-
—
.-
.-
u-

. <..
-. 1.

. ...

-. o.
. ..

 

 

Figure F.6.4

181

---
...
...
n\.
on.
...
u.
. .
.1-

s

.
-o
-.
.o
.o

 

 

 

 

.-.. ..
e . ..
.. .o
«a... ..
-.-..-
._—.-v
...

.1. 1.
... .
.., .
....

......
.n _.

... ....
...
.......
... ....
.....-._

. .
...,, ..
-—-.—.

.. ...
.. .
.. ,.

e.
..
-u
..

..-
.-
..
-

 

.....o. .......... ...... ....
......., ,. .. .
......... ...... ... .... .
.... ......... . ......
....1.... .... .........

. ....... .1.»......... ..
.......... . . .. .. .
..... .... .... ...... .. .
.. ... ,. . ..
.....-- -.--. ..... ..1-- ..
1...... .... .... .... . ...

.. .u .. . .. . .. .

., ..,. .......... ....... .,

........... .... . ........

, ...,-........1. ... .... . .

.-. —----—-—.-_._-.-.--

.4 .... .. ., . . . ....... . .
... .... ..... ........~.. ...
..., . .. . . .. .

..... .... ...... ... .... .
an . ..............,.. ..
. ... ..4.__‘,,,1,., ...
.......... .. .. ........ .
... HM. . .. ..........
o .. .. .. .. e
.... . .. -. .-

Figure F.6.5

... .
,. .

...
.1

...
..
...

.
. o

 

 

f‘fi’

 

 

-1..o

. -.
..
...-

...
....
..,

 

 

 

 

 

 

.
. 1

 

   

 

 

 

.—.——~._. ..

 

 

 

 

 

 

   

 

. . .

Figure F.6.6

183

 

 

 

 

 

 

 

—--..»--

.-.--.-._——.—.

 

 

Leis. _.'.‘.

 

 

 

o r‘
l >..
. ..
.. .
D .

 

 

 

 

 

 

 

---.-4-.—.—.

.—»~—.—no—

-’.«—~-.

_.-.—..—

 

 

---—..- .--—.--.- .—- —.—.-.-1-—.- .--.-1-—.—.

 

 

i:.-,.ii..i_ 4..-.1 i i.--i . 1.1....
. ... . .
. _
i ..-i... ii-.. ... j
. _
u -
_ _
_.
_ .
. 1
.
. _
_ _
. M
.
., _ _
.-
. “ .., ..
. .. v
., .
o
.. .
_ .
_ _
. ._
. _. ...
.. .
_
_ _.
a .-
_ .
_ m
. .
. .
_ _
.
_ .
m -
. ._
. _ .
. ..J ...
. . ..
.
._
, _
u .
.
. _
. .

Figure F .6.7

184

 

H . i . n . u
. ..... . ....... . .
I .-
.,., ... .. H.
. . _ .. ... .. k;
.. .. . p ..fi
. . . ..
. . . .... ..
..... . I.l.ii| I.I,
. ... H.
.. ,
. _ .. .
.... -1.
... ....
f ..
_ .. J
H. ...:
;_ ,.¢
.. m.
.7. .._.. ,.
. ,
. L.-
. .
..
._ . .
_ , .
. .
., .. .. _.
. ...
,. . _
. .
.
..
- .-
. .
._. .
.. w
. ..
:_ ..
_ ._
.. a.
._ . .
. 4.
..h ,_ ,.
. . .
. ._ . J. H
. .
... ....
..
.. ,.
. .-
H_. ..H
_ . ..
. ..... ...
..... ... ...
...... H... .....
...... . . _.
._ ....
_. I I... ....
..... ., ..
_ ,_
_ _.
....... H... H...
1 iii ..-I.i.i.i-i ..L ...
.
_
..
._.
..
_.
I:

 

 

 

p.—...—

l .

.-- '_’.‘I

.—..—.—..._............._-~....

-._-—.-._—.—

Figure F.6.8

185

.....

   

 

 

 

"'"‘“'""""““""‘-’-"’““"—""““"‘““‘"“"“""’""""-"""““““‘-'-'l"‘ ..
.. 1.—.-.—.—.———_.—-..—.—.-.—-—--.--.-—.—.-.-o—--...—.-—-—.—.— -.__.-...._.-—..-..J. ....-
.

Figure F.6.9

1

 

 

 

 

 

...
u..-
1..
.—
...
...
...

o .
...
-0
. .
.

. o

...
-..
...
o .
u»-

...

-0
1..

...

...

 

...-
_-

....... ...... .......
.... . . ..... .... .1
.. 1 ......-.. ......-
, . 4W1 .
.... .... .. . .......
......... . .......
.............-.. n
.... ....v...........
......1. ... .......¢
..-............. ....

.. . .......l.......
..................-...
....................
...-. ..,-. .....

Figure F.6.10

 

...

.-
4.-

..
.—
...
. -
...

...

...
-«

a»-

1..
...
...
~-
1..

....

 

-..-uh»

........
.... .,
........

 

 

v»..-
a—p-

 

 

Il' .
..
,,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

- ............................... i
l

l- ------------------------------- l
iif!) [i];

 

 

 

 

 

 

 

 

 

 

 

Figure E6.“

188

 

Figure F.6.12

189

 

Figure F.6.13

190

 

 

 

 

Figure F.6.14

191

 

 

 

 

 

Figure F.6.15

192

 

 

Figure F.6.16

193

s§§§§§§§§§x §sx
.\ \\\\\

 

 

Figure F.6.l7

194

ii .1 .... ill
31%"... .. . .u.

. i‘.\. .4.
E \
ktkhsh‘n

.5. .e ~\%&N““

mww

.. . u... . . .
hihvul‘ _~12.‘ hawv‘ . . ‘“\“«MIA\ K.‘ .
Sash: hum new \k. . . .. .

\\ Eh . .. ._ .mmNhkz
.s . . . . . . . .

N . ....xua‘ 3...“.

.4...
. M‘QR‘. mw“\nmlllwnkwfl
» .

 

Figure F.6.18

195

7 Design rules check in LASI - LasiDrc

In the exercise of chapter 4 you were asked to go through design rules for MOSIS process
given in appendix B of the CMOS book. There are MOSIS design rules for each layer
like metall and 2, polyl and 2, active, contacts etc. There are a total of fifty-three design
rules. After a layout is finished it is very important to see to it that all the design rules are
accurately followed otherwise there is a high probability that the fabricated circuit will
not work. In case of small circuits these rules can be manually checked but in case of
bigger circuits, in which checking these rules manually can be a time-consuming process,
some kind of automation is needed. A LASI command, LasiDrc, provides this
automation to you.

Setup for LasiDrc:

Using the System menu of LASI (one of the top menus) and then clicking the LasiDrc
button will start the design-rule-check program. Once the program starts you will see a
small LasiDrc window in top left corner of your screen. Click on the Setup. You will see
a dialog box as shown in Figure F.7.1. Some of the settings like lambda size, start check,
finish check and name of the report file automatically show up although you can change
them. You have to fill in the name of the cell on which you want to perform the design-
rule-check. Also check the ‘erase old report file’ option. Note that when you start the
LasiDrc it will check only for the portion of your layout visible on the screen. In order to
check for the entire layout you need to use the Fit command to make the whole layout
visible on the screen.

Using LasiDrc:

For sake of understanding how to use LasiDrc we will take an example of an n-well with
an active layer in it. We will purposely layout the ACTIVE layer such that it violates the
design rule and then see how LasiDrc shows us our fault. Follow the instructions given
below.

1. Create a new cell ‘WrongDrc’ of rank one.

2. Layout an n-well box of size 1011X101i.

3. Make a box of active layer in the n-well such that the overlap of the n-well of the
active is 311 (Figure F.7.2). Don’t draw any select layer. Remember that select overlap
of active should be 211 to indicate what type the active is.

Save the work using the Save command.

Fit the entire cell in the screen.

Now open the LasiDrc window using the System command.

Open settings and compare them to Figure F.7.3. Then click OK.

Now click on GO in the LasiDrc window. You will see that a small testing window
opens up and the program starts testing different areas of the screen. At the bottom of
testing window the current rule being checked for will be displayed (Figure F.7.4). As
soon as the program finds the violation of a design rule another window opens up and
the bad area is displayed in white background. Description of the design rule will also
be given along with the bad area. The program shows this violation for some time and
resumes the further check. The program refers to each violation as a ‘flag’. At the end

@991"?

196

of the testing the program tells you how many flags (violations) it found in your
layout. In this case it will be one.

9. Now select Read in the LasiDrc window. Click OK for opening ‘LASIDRC.RPT’
using notepad. Look for the check 10 and read the description. Close the report.

10. Now select Map from LasiDrc window. It shows you the flagged area in white. Close
it.

The previous example shows you how to use LasiDrc effectively. In a similar way you
can test any layout for design rules.

 

Exercise:

1. Create a cell of rank one with any name. Draw an n-well of 511x511 and check your
layout using LasiDrc. Is there any violation of design rules?

2. Create another cell of rank one with any name. Draw p-type active area of 511X511.
Draw a contact of the 111X111 size at the center of the p-type area. Check the layout
using the LasiDrc. Is there any violation of design rules?

197

 

tiarrieottellioDFlC ___,—____J
flame or [he—ck File 2||LHIP.UP.C

Slaitflic-CL ' I Fiiiisiiflierl' 5} l LanibdaSizmnum 1 I
Fl .olutinn Distance

1: lit-claim W in W: 3

Area Lei! :: Area Bottom

Scan Let! - ZOJHmII scan Flight 20.48uni
Scan Bottom ’ 25.13"!" Scan Top ZS‘G'H"
)4 Enable SCF'.’ Filt- Limit 10 J
J Enable- PAUSE F‘s-1'7- Time

Harm:- ot R epoil File

34 Engine Did Report File

 

Figure F.7.1: DRC setup

198

 

 

 

 

 

Figure F.7.2

199

 

Ham-e of Cell lo [‘le WHO "‘5 D R1:
Name of Che-cl. File 2| WHIP-“RC

Start fix-cl. 1 I Finish Check
Flemlution —_I

Checking \i-r'rndows

Lambda Size in urn 1

Distance

Area Lelt

Area Etc-11.3“. A4

ScarrFlight 13- "I“ I
Scarricrp llJJimi

Scan Lelt

Scan Bottom ' 1--”|l||l

_\d Enable SCF’Y File Limit JLJ
__I Enable PSZU 3E Pause Time 5
Name- 01 FiE'pOll. File IR . PT I

515‘? Old Report File
:4

Figure F.7.3

200

 

W

 

_.n‘r Lanrtvda:l
' Sum E:=-1 dum R: am 1:11 alum

 

Figure F.7.4

201

8 An Example of layout

Objective of this chapter is to understand how to layout a chip using the hierarchical
approach. We are going to use an example of a differential amplifier designed using the
MOSIS n-well process. We will make use of the same amplifier to illustrate the SPICE
file extraction in the next chapter.

Differential amplifier circuit: -
We are going to layout the differential amplifier shown in Figure F8]. This amplifier is
designed to have an AC gain of 30 and a current of 2011A in the current mirror. The
design can be verified using standard design formulas. The models for the devices used in
this design are given below.

.MODEL CMOSN NMOS VTO=0.5 KP=45U GAMMA=0.5 LAMBDA=0.05 PHI=0.7
.MODEL CMOSP PMOS VTO=-0.5 KP=15U GAMMA=05 LAMBDA=0.05 PHI=0.7

Instructions for Layout:

Broadly this amplifier consists of three parts. One current mirror (M5), two amplifying
devices (M1, M2) and two active-loads (M3, M4). We will layout one current mirror, one
amplifying device and one active load in separate cells of rank one.

Current Mirror

Create a new-cell ‘CURRENTMIRROR’ of rank one. Draw a pMOS of size 10111511 as
shown in Figure F.8.2. Remember that it needs an n-well. Read all the rules for active,
polyl, n-well and contact from appendix B of the textbook. Check the layout using the
LasiDrc.

Amplifier
Create another cell ‘AMPLIFIER’ of rank one. Draw a pMOS of size 15111511 as shown in

Figure F.8.3. Check your layout using LasiDrc.

Active Load

Create a cell ‘ACTIVELOAD’ of rank one. Draw an nMOS of size 5111511 as shown in
Figure F.8.4. Remember that this is nMOS and it does not need a well. Check the layout
using the LasiDrc.

Differential Amplifier _
Now create a cell ‘DIFFAMP’ of rank two. Select the Object command. Double-click on

‘CURRENTMIRROR’ once. You will see this cell on the arrowhead. It will be placed at
a point wherever you click the mouse. Click the mouse near origin. In a similar fashion
add two ‘AMPLIFIERS’ and two ‘ACTIVELOADs’ to the current cell. By using the cGet
(cell get) and Rot (rotate) commands position the cells as shown in Figure F.8.5. Pay
proper attention so as not to violate design rules. Then place metall, contact and polyl
layers as shown in Figure F.8.6. Check the layout again using LasiDrc.

In this chapter we laid out a complete differential amplifier using hierarchical approach.
We laid out different components in separate cells of rank one. The final circuit was laid

202

out in a cell of rank two using the previous cells of rank one. The advantage of using this
approach can be easily noticed. If we were to make a complete amplifier in a single cell
of rank one then we have to layout every single component in the circuit. But in
hierarchical layout we made only one active-load and amplifying transistor but used them
twice in a cell of a higher rank.

 

Exercise:
1. Make the circuit shown in Figure F.8.7 using LASI. You will need this layout for

exercise of the next chapter.

203

 

CZ)

 

VDD =5V

VBIAS- 334w O__IIJM5W/L-10U/SU

®

M1 W/l. -15w5u@I_O zO—I M2 W/L =15U/5u

@ Vout (DC) - -3 .333v

M3 W/L - SUISU @I——I M4 W/L - SUISU

O VSS = -5V

@

 

 

 

Figure F.8.l: Schematic of a differential amplifier

204

 

 

 

 

 

 

 

 

Figure F.8.2: Layout of the current mirror

205

 

 

 

 

 

 

Figure F.8.3: Layout of the differential transistor

206

 

 

 

Figure F.8.4: Layout of the active load

207

 

..- —.-.—.-.—-—.——--

. a .
. u .
u o .
. . .
. a .
. o .
. o .
. . .
. a .
u o o
. . .
. a .
. u .
. o o
. u .
. u .
. o .
u o .
. . .
. . u

. . .
. . u
u u u
. . .
a u .
. . a
. . .
. . .
. . .
n . .

 

 

 

 

 

 

 

 

 

 

 

 

 

. u .
. u .

. .
Ill.
. n .
. o v
. . .
. a u
. o .
ll! .
. u .
. a .

. . .
. u .
. . .
. o .
. . .
. . .
. . .
. . .
. c o
. u .
. u .
. a .
. . .
. u .
. . .
. o

. a .
. u .
. a .
. . .

 

0..
. .
...
...
...
...
...
...
...
...
...
...
...
...
...
...
all.
...
..
..
..
.r
r
o.
.
..
...
...
a.
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...

 

 

nos-Mod no-0 ..-

 

a

.

.

.— ..— ..-

—.-—.--——---—--

——v- —.v —.

 

 

 

 

      

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

... .. ....... . ....... .
...... ....... . ....... .
...... ....... . 0...... .
...... ....... . . ..... .
...... ....... . ...-... .
...... ....... . ....... .
...... ...-... . ....... u
...... ...»... . ....... .
...... ....... . ....... .
loll .I'.I.I|.. ,u .1.Illl. I...
...-I. Ian‘caa.. .- cal. a
...... .....u....lul .... -
..... ...... .. .W .... o
. u
. .
. I. .u
n .
. p u.
» .a
a .
. .
m ...
. . .a. .
. ...
. w ..
. ..
.
. o
. n.
. .-
. ..
...-a ...... . v. .... .
. .... ....... . . .... .
...... ....u.. Ia .... .
.11.... ll. V..l.l...i. . .-.. ...
...... ....... . ....... o
...... ....... . ....... .
...... ...-... . ....... .
...... ....... ....... .
...... ....... . ....... .
. .... ..... . . ....... .
...... ...-... . ....... .
...... ....... . ....... .
II-
.
o
c
.
.
..
I.
.
II
,I
..
so
. .
..
u
u
.
.
u
u
...-I IIQI.I,.. ’. l... I
...... ...-...... ..I u.:. .
...-u ...:..~... ‘...... o
10". lo'llu I--|
...... ....... . ....... .
...... ....... ..u.... .
...... ......~ . ...-... .
...... ....... . .v..... o
...... .. .... . . ..... .
...... ...v... . ....... .
...... ....... . ....... .
...... .....,« . ....... .

.— oo— -1

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

........u ..... n
......uo. ..... .
.......o.. ....o .
......... ..... .
......o.. ....u .
......a.o ..... .
......... ..... .
.......... ..... .
......... ..... u
.......u.. ..... -
..o...e..a a..a. a
......uun. ...a. o
.......... ..... o
. ........ ..... .
...-...... ..... .
.......... ..... .
.......... ..... .
...-...... ..... o
.......o.. ...... .
..... .... ..... .
.......u.. ....o .
.......... ..... .
.......... ..... .
.......... ..... o
. ........ ..... .
.......... .. . .
.......... ....» .
.......... ..... u
.. .....
w. H.U_._..

... .4
fl .
. ......
..... ...ic .....

B.
.......... ....-
.......... ....o
....u ...! 1....
1...... Iiir.i ...
....;\.vbn'aol. .... i
y ;. I.\ait. ... .

. ..vi...ri.. L
. .....i..:.0 .. .
. o.vi cull ... .
.nwlr.-.ak1...n Lnrbh.
..... .... ......

. ‘.
.........- ..... o
......ouc ....o .
......u... .... o
.......... ...A. .
......... ..... o
.......... ..... .
......o.. ....a .
.......c.. ...o. .
.......... ..... .
......o.. ....n .
.......... ..... .
.......... ..... .
... ..... ..... .
......ouoa ...-u .
.......o.- ..... a
..u....uuo ..... u
........ou ..... -
....-.... ..... u
.......n.. ....u .
.......... ....u .
......... ..... .
......u... an... .
......o.. .u... .
......... ..... .
u......oou ..... .
......... ....u .

Placement of. the individual transistors of the differential amplifier

Figure F .8.5

208

.‘s
- my
§Z§Z§Lx m
M“ :1, :

“PVZQ

ilfifiéfili

 

Figure F.8.6: Interconnections of the transistors

209

 

 

- VDD - 5v
G) M1: W/l. - sursu
VBIAs-3.345v
0e)
v... o___l M2: WIL = 5U/5U
* vss = 5v

 

Figure F.8.7: Schematic of a simple amplifier

210

9 Extraction of SPICE file using Lasith

After your circuit is laid out you will always want to extract a SPICE file to check

whether the circuit works the way you want. This can be done easily by using another

program provided in LASI — Lasith. In order to use Lasith effectively we have to first

label the nodes, connections and devices along with their parameters in a specific way.

There are different text layers provided by LASI for different purposes that can be

selected using tLyr (text layer) in menu2. These layers are given below.

1. Connector text is used to tell LASI where the connections are made from a lower-
ranking cell to a hi gher-ranking cell.

2. Device text is used to label transistors. This label will be used in SPICE file to refer
to that device. .

3. Parameter text is used to write parameters of the device. Parameters mean model
name, length, width, areas of source and drain etc. for a transistor.

4. Node text is used to label final nodes on the connections. These nodes will appear in
SPICE file along with the transistors.

The following example shows how to make a layout for SPICE extraction. For this

purpose we will use the layout of the differential amplifier that we made in the previous

chapter.

Node labeling for SPICE file extraction:

Following instructions will show you how to label the layout for this purpose.

1. Open cell ‘CURRENTMIRROR’ and Fit it on the screen.

2. In menuZ select tLyr and select CTXT (connector text). After this click on the Text
command to be able to type on the layout.

3. Label the connections with the connector text as shown in Figure F.9.1. The vertex of
the text will be placed at a point wherever you click your mouse. If you can not see
the vertex of the text press the ‘t’ key followed by the Draw command. For the drain
and source connections make sure that you place the vertex on the contacts. Similarly
for polyl make sure that you place the vertex on the edge of the polyl. For bulk
connection place the text in the n-well but not on active area. Remember that labels of
drain, gate, source and bulk are in an order acceptable to SPICE.

Open ‘AMPLIFIER’ now and Fit it on the screen.

Label the layout with the connector text as shown in Figure F.9.2.

Open ‘ACTIVE’ and Label it with the connector text as shown in Figure F.9.3.

Open ‘DIFFAMP’ now and Fit it on the screen. It looks like Figure F.9.4.

Now we are going to label the MOSFETS. Using the Outl (outline) command convert

all the cells to their outlines first. Then select DTXT (device text) using the tLyr

command and select the Text command to be able to type on the layout.

9. Label the devices as shown in Figure F.9.5. Make sure that the vertices of the device
labels are inside their respective cells.

10. Now we are going to give the parameters of each transistor on the layout. Select
PTXT (parameter text) from the tLyr command. Using the Text command type the
parameters of each transistor in the respective cells. Again make sure that the vertices
of parameter texts are within the respective cells’ boundaries. Now the layout should
look like Figure F.9.6.

”HE’S"?

211

11. The last step in labeling is placing the nodes. The nodes in SPICE file will be directly

taken from the NTXT (node text) layer. Now convert your layout to a full cell view
from the outline view by using the Full command. Your layout must be crowded by
text now. Use the View command and deselect device and parameter texts. Now use
the Draw command to redraw the screen. You will not see device and parameter
labels although they still exist in the layout. Now select NTXT (node text) from the
tLyr command. Using Text start typing node-labels as shown in Figure F.9.7. Notice
that node 3 and 6 are on the metal layers because the metal intersects the contacts on
the devices that are already labeled in a lower rank with connector text. In case of
bulk connections we need to place the node text on the connector text in the cells of
lower rank. Similarly for inputs of the differential amplifier (node 1 and 2) we need to
place the node text on the connector text on the polyl of the cells of lower rank.
Notice the placement of node 5. The node label for this node is placed on the contact
to show that the drain of M1 and the drain and gate of M3 share this node.

Spice file extraction:

1.

Now that we have labeled the nodes and devices our layout is ready for the SPICE
file extraction. We need to make two files, header and footer, for incorporating our
power-supplies, transistor models and test signals. Open the text editor of SPICE.
Type two files as shown in Figure F.9.8. Remember to include a carriage return after
the last word of each file. These files will be included in their proper places in the
final SPICE file extracted by Lasith.

Using System menu start the Lasith program. You will see a small program window
similar to LasiDrc in top left comer of the screen. Open Setup. You will see some of
the text boxes already filled-up with default settings. Enter the name of header and
footer files and enter the name of cell to be extracted (DIFFAMP) as shown in Figure
F.9.9. Click OK.

Now click the GO command. You will see the process of extraction in progress. If
you have done errorless labeling of nodes you will get a message box saying that
there were no errors. Click OK for it.

Now open ‘w2uchip’ folder and open ‘diffampcir’ file. This is the SPICE file for
your layout of differential amplifier. Compare it with Figure F.9.10.

Summary:
We saw how to label the connectors, nodes, devices and parameters with the help of the
example of differential amplifier. Here are tips about how to label a layout in general.

1.
. are to be made to the next higher ranked cell. This normally will be where

The vertex of the connector text must be placed within a cell where the connections

interconnection layers join the interconnection layers of the next higher ranked cell.
Since the connector text tells LASI how cells are connected upward in the cell
hierarchy connector text in the top cell is unnecessary.

Within a cell, the vertex of the node text should be placed on a path or the box used
for interconnection. If it is located on a cell of a lower rank it will not have any effect.
Node labeling for body connections is done in a separate way than the other nodes. In
this case the node label is placed exactly over the connector text in the lower ranked
cell. Notice the body connections in the previous example.

212

..
....‘fl
..

5. If two different layers are used for interconnections using contacts or via (for example

polyl and metall) the node label is placed on the intersection of the two layers.

6. If an element in the layout is not an active device it does not need a labeling.

Step for labeling:

1.

We label the terminals of nMOSs and pMOSs in an order that SPICE expects. In
order to do this we go to individual cells and label the Drain, Gate, Source, Bulk as l,
2, 3, 4 using CTXT (connector layer). To see the vertex of the text press ‘t’ on the
keyboard followed by the Draw command.

Next we have to label the MOS devices. The lower ranked cells are added to a higher
ranked cell to make a bigger circuit. We place the names of the MOS devices on the
lower ranked cells using DTH (device text layer).

The third step is typing in the sizes of the devices by using PTXT (parameter text
layer).

Now we need to tell LASI which nodes are inputs, output and transistor terminals.
For this purpose we use NTXT (node text layer) and label the nodes using the tips
given before.

Lastly, if this higher ranked cell is to be used in still higher ranked cell as a sub-
circuit then we need to label connectors in this cell using the connector layer.

In this chapter we learned how to label a layout for SPICE extraction by using different
text layers. We learned this using the example of a differential amplifier, which we laid
out in the previous chapter. This chapter also gave tips for SPICE file extraction.

 

Exercise:

1.

Label the layout from exercise of the previous chapter for SPICE extraction. Extract a
SPICE file and run operating point test (. OP) on the circuit.

213

 

 

 

 

 

 

 

 

 

 

.... N v
. . . n .
v.
n \ n o
. x u .
.Ht ... T . . c
i. . . .
. ,. . .
. .
. ... 1
.7 . Inl.’

.I.l.|.l.l.l.l.l..l..l-l-l ........ . ..... J

 

 

-..—_._,,..-_--.-,_._-

 

 

 

 

 

 

 

 

nllslet'l'nlo-It't'crlltllI't'nl.'l'l'.u

_-- -_._._.-_.___L.‘..4 ;;u“n..-LAA._.

._ ..- .

Figure F.9.1

214

 

 

 

 

 

 

 

 

 

Figure F.9.2

215

 

 

 

Figure F.9.3

216

.. \
a .. figfi

m-
m ‘1'-

a‘é‘f‘a

 

Figure F.9.4

217

 

 

 

 

Figure F.9.5

218

 

Figure F.9.6

219

I“

I: :: km! 3
-- \ V ..
55 .. V3, ;-_
" .‘Kh ;:
1.,;f§-,E '3? "f-

swmsfl E
- Emma, ...

“ - i: L

:2 ‘3‘ 1‘
I: §:&\\\x§§
:: mmmwl .
~W&V‘w¢n\\s-. 2: E‘V‘S‘g‘g‘g
”Ah“ 5* . 'l «W

.H
" «Sign ,. '
..: ‘

 

Figure F.9.7

220

 

 

 

r IDIFFERENTIAL AMPLIFIER LAYOUT

*HEADER FILE: CONTAINS POWER SUPPLIS
*AND INPUTS

VDD 7 0 5V

V88 4 0 —5V

VBIAS 8 D 3.345V

 

ViDIFFERENTIAL AMPLIFIER“ LAYOUT

*HEADERFILE CONTAINING MODELS FOR
“TRANSISTORS ANDT

.MODEL CMOSN NMOS VTO=D.S KP-lSU GANNA=D.S LANBDA=0.US PHI=0.7
.MODEL CMOSP PMOS VTO=—0.S KP-lSU GAMMA=0.5 LAMBDA=O.US PHI=0.7

*TEST SIGNALS
VINl l 0 0V
VINZ 2 0 0V

*TESTS CONDUCTED
.OP

IEND 0F SINULATION

 

Figure F.9.8

221

 

 

 

Figure F.9.9

222

 

 

HICIOSII'D Text Editor I

      

:. ' " H' ” N ' ' fig ___ f ' LL m
*** SPICE Circuit File of DIFFANP made by LASICKT on 05/01/99 14: E“

* START OF DIFFHEADER.CIR
“DIFFERENTIAL AMPLIFIER LAYOUT

“HEADER FILE: CONTAINS POWER SUPPLIS
INPUTS

VDD 7 0 5V

V58 4 0 —SV

VBIAS 8 0 45V

I END OF DIFFNEADER. CIR

*NAIN CIRCUIT DIFFAMP
N3 5 5 4 OSN U= 5U

U
NS 3 B 7 7 CMOSP U- 10U L-SU

I START OF DIFFFOOTER CIR
*DIFFERENTIAL AMPLIFIER LAYOUT

IHEADERFILE CONTAINING MODELS FOR
ITRANSISTORS AND TESTS

.MODEL CMOSN NMOS VTO-U.S KP=45U GAMMA=0.5 LAMBDA-0.05 PHI-0.7
.MODEL CMOSP PMOS VTO=-D.S KP=15U GAMMA=U S LAMBDA-0.05 PHI=0.7

*TEST SIGNALS
VINl 1 0 UV
VINZ 2 0 UV

*TESTS CONDUCTED
.OP

:END OF SINULATI ON
END OF DIFFFOOTER. CIR
END

 

Figure F.9.10

223

10 Advanced topics in Layout

Now that we have learned the basics of IC layout process let us focus our attention on the
special issues in layout. Before doing this we have to understand the importance of these
issues. Performance of the fabricated Integrated Circuit highly depends upon uniformity
of the fabrication process. A fabrication process is a batch process, which means that
many wafers containing many chips go through different Steps at the same time. Due to
the physical factors involved every chip on the wafer does not get the same treatment and
there are gradients in different properties of a chip. Examples of properties that show
gradients are threshold voltage, resistivity, thickness of layers and many others. Mostly in
analog circuits ratios of components and symmetry are important issues. Techniques to
layout symmetric components will be discussed in this chapter. In addition several other
issues such as resistance of the active contact and width of metal lines will be discussed.

Resistance of metal layers:

The drawn width of a metal layer depends upon its resistivity. Although the metal layer is
made up of a substance having high conductivity it has got a finite resistance. Current
flowing through metal produces a voltage drop across it. Due to this phenomenon the
signal becomes weaker as it passes through metal lines in our circuit. Therefore while
laying out metal one should provide attention to its width. Sheet resistances of metall and
meta12 are given in Appendix A of textbook.

Current carrying capacity:

The width of a metal layer also depends upon a phenomenon called electro-migration. If
a narrow metal line conducts excessive current the momentum of electron causes metal
atoms to migrate from their original positions creating spots of high resistance and
subsequent failure of the connection. Current density in metall and meta12 should be
below 2mA/um to avoid electro-migration.

Metals connected to VDD and ground:

The substrate is connected to VSS. Therefore a capacitor is formed between the substrate
and any metal line connected to either ground or VDD. If metal layers connected to
ground and VDD occupy as much area as possible then supply voltages will be nearly
constant.

Active contacts and via:

Each contact and via represents a contact resistance. Values of these resistances are given
in Appendix A of the textbook. To reduce this contact resistance at the place of contact
one should include as many contacts and vias as possible. Then all these contact
resistances will form a parallel structure and the effective resistance will be much lesser
than an individual contact resistance.

Consideration for temperature distribution:

If there is a power device on the chip it will create a temperature gradient on the chip
away from the device. If one needs to place two matched resistors in the vicinity of this
device the approach shown in Figure F.lO.l should be followed. The wrong approach is

224

also shown in Figure F.lO.l. This is because we want temperature to affect both the
resistors in a similar way so as to maintain the matching between the two.

Guard-rings, dummy elements and common centroid geometry: _

Guard-rings are used in many places to avoid the current flowing between the parts of a
component. In the resistor shown in Figure F. 10.2 guard-rings formed of p+ layer provide
a means of stopping the minority current flowing between the resistive elements of that
resistor. Similar guard rings are laid out around a capacitor. If we see the fr gure in Figure
F.10.2 we will observe that the resistive elements on the two extreme sides of the
structure do not have a same environment as the ones at the center have. For this purpose
two dummy resistive elements are introduced on the other side of these original elements
on the extreme side. Dummy elements are not used as resistors but they just sit there to
provide same environment for all the resistive elements. This idea is shown in Figure
F.10.3. Common centroid geometry is used to take care of the matching of two or more
elements. Equivalent elements of two resistors that should be matched are interleaved in
figure Figure F.lO.4. Due to this structure, process gradients affect both the resistors in
the same way. In a similar way two or more MOSFETS can be matched.

Matched capacitors:
Matched capacitors are laid out in a similar way. The layout is shown in Figure F.10.5.
Notice the way one capacitor is made up of two parts.

 

Exercise: .

1. Using the concept of guard-rings, dummy elements and common centroid geometry
layout two matched lOOKQ resistors in LASI

2. Using a similar concept layout two matched capacitors of any value.

225

 

 

Right Approach

T1

Power
Device

 

Wrong Approach

Figure F.10.1

226

 

Substrate biasing

 

tu~.-‘ __ . .-..r . , .....7 ,

. . ‘ .;a. , , ‘23,... . p . .. ‘ . (we‘r.,w'

\

l , k

.‘ c
, r

- .

. . , K

.1. /

r ‘ ,, _' l

3 ._ 3 ‘- .. f

 

 

 

 

 

 

 

 

 

Figure F.10.2

227

 

 

 

Dummy

 

 

Actual Resistor

r_——_————_.-l

L

 

 

 

n-wells

Figure F.10.3

228

I
I
i
I
l
I
l
i

 

 

Dummy

 

 

 

 

£-

 

 

R1

 

 

 

 

R2

 

 

 

Dummy

 

 

 

 

 

 

 

 

 

 

 

 

 

R1
Interleaved Resistor Structure

Figure F.10.4

229

Polyl Common Cenboid

 

Protective well

well biasing

 

Figure F.10.5

230

 

15 Bibliography

[1] P. R.Gray and R.G. Meyer, “Analysis and Design of Analog Integrated Circuits”,
J ohn-wiley and sons, 1994.

[2] Johns David A. and Martin Kenneth, “Analog Integrated Circuit Design”, John Wiley
and Sons, Inc. 1997.

[3] Sekerkiran Barbaros, “A Compact Rail-to-Rail Output Stage for CMOS Operational
Amplifiers”, IEEE Journal of Solid-State Circuits, VOL. 34, NO. 1, January 1999.

[4] Massobrio G. and Antognetti P., “Semiconductor Device Modeling”, McGraw-Hill,
Inc. 1993.

[5] Baker Jacob, Li Harry and Boyce David,”CMOS Circuit Design, Layout and
Simulation”, IEEE Press 1997.

[6] K. R. Laker and W. M. C. Sansen, “Design of Analog Integrated Circuits and
Systems”, McGraw-Hill, 1994.

[7] P. R. Gray and R. G. Meyer, “MOS Operational Amplifier Design - A Tutorial
Overview”, IEEE Journal of Solid-State Circuits, Vol. SC-l7, No. 6, December 1982.

[8] Brehmer, K. E. and Wieser, J. B., “Large Swing CMOS Power Amplifier”, IEEE
Journal of Solid-State Circuits, Vol. SC-18, No. 6, December 1983.

[9] Fisher, J. A., “A High-Performance CMOS Power Amplifier”, IEEE Journal of Solid-
State Circuits, Vol. SC-20, No. 6, December 1985.

[10] Nagaraj, K., “Large-Swing CMOS Buffer Amplifier”, IEEE Journal of Solid-State
Circuits, Vol. 24, No. 1, February 1989.

[11] Saether, Hung, Qi, Ismail and Aaserud, “High Speed, High Linearity CMOS Buffer
Amplifier”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 2, February 1996.

231

 

 

[12] LASI software Help.

[13] José Franca, Yannis Tsividis (editors), “Design of Analog-Digital VLSI circuits for
Telecommunications and Signal Processing”, second edition, Prentice Hall, 1994.

232

""5

 

 

 

111‘“