i LIBRARY Michigan State University PLACE IN RETURN BOX to remove this checkout from your record. To AVOID FINES return on or before date due. MAY BE RECALLED with earlier due date if requested. DATE DUE DATE DUE DATE DUE 6/01 clelRC/DatoDuo.p65-p.15 CLASS G AMPLIFIER By Adam Darwin Downey A THESIS Submitted to Michigan State University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE \ Department of Electrical and Computer Engineering 2002 ABSTRACT CLASS G AMPLIFIER By Adam Darwin Downey Power efficient circuits are becoming more important as technology advances to using more portable devices such as cell phones, walkmans, and laptop computers. A Class G Amplifier is a power amplifier that can achieve better power efficiency than the Class B Amplifier. This thesis presents using an Operational amplifier with a Class G power stage and feedback to lower the total harmonic distortion of the amplifier. This thesis shows how to solve the stability problems associated with the Class G Amplifier. Also presented here is the examined efficiency of this amplifier. In addition, this thesis presents the lab work verifying the performance of the amplifier. Copyright by ADAM DARWIN DOWNEY 2002 ACKNOWLEDGEMENTS I would like to thank Dr. Gregory M. Wierzba for his guidance in the thesis. I would also like to thank my parents for their continuing support in my efforts to obtain my Master's degree. iv TABLE OF CONTENTS LIST OF TABLES viii LIST OF FIGURES ix 1 INTRODUCTION AND BACKGROUND - 1 1.1 INTRODUCTION .................................................................................................. l 1.2 BACKGROUND .................................................................................................... 1 1.3 THESIS OUTLINE ................................................................................................ 2 2 DESIGNING CLASS G AMPLIFIER ‘3 2.1 INTRODUCTION .................................................................................................. 3 2.2 CLASS G AMPLIFIER DESIGN #1 ..................................................................... 4 2.2.1 STAGE ONE ANALYSIS - LARGE SIGNAL MODEL ............................ 5 2.2.2 STAGE TWO ANALYSIS - LARGE SIGNAL MODEL ........................... 9 2.2.3 STAGE TWO ANALYSIS - Q1 IN SATURATION REGION ................. 11 2.2.4 STAGE TWO ANALYSIS - Q1 STAYS IN ACTIVE REGION .............. 14 2.3 CLASS G AMPLIFIER DESIGN #2 - USING DIODES .................................... 16 2.3.1 STAGE ONE ANALYSIS - LARGE SIGNAL MODEL .......................... 17 2.3.2 STAGE TWO ANALYSIS - LARGE SIGNAL MODEL ........................ 20 2.3.3 LIMITATIONS OF DESIGN ..................................................................... 23 2.3.3.1 STAGE ONE ANALYSIS ................................................................. 24 2.3.3.2 STAGE TWO ANALYSIS ................................................................. 25 2.4 KEEPING TRANSITORS FROM SATURATIN G ............................................. 26 3 USING AN OPERATIONAL AMPLIFIER WITH FEEDBACK 27 3.1 INTRODUCTION ................................................................................................ 27 3.2 PSPICE SIMULATIONS OF STAGE ONE ........................................................ 27 3.3 PSPICE SIMULATIONS OF STAGE ONE AND STAGE TWO ...................... 30 3.4 ADDING A CLASS B STAGE ............................................................................ 34 4 POSSIBLE ISSUES TO CONSIDER ‘37 4.1 INTRODUCTION ................................................................................................ 37 4.2 USING SHOTTKY DIODES ............................................................................... 37 4.3 POWER SUPPLY ISSUES .................................................................................. 41 5 CONSTRUCTION OF THE CIRCUIT 43 5.1 INTRODUCTION ................................................................................................ 43 5.2 BREADBOARD LAB DATA .............................................................................. 43 5.3 PERFORATED PROTOTYPE BOARD LAB DATA ........................................ 45 5.3.1 USING SWITCH MODE POWER SUPPLIES ......................................... 45 5.3.2 USING BATTERIES .................................................................................. 48 6 NOISE ANALYSIS / IDENTIFYING NOISE IN LAB DATA 42 6.1 INTRODUCTION ................................................................................................ 52 6.2 PROBLEMS WITH OSCILLATIONS AND OP-AMPS .................................... 52 6.3 OSCILLATING THE POWER LINES ................................................................ 53 6.4 PUTTING INDUCTORS ON THE POWER LINES .......................................... 58 7 BETA ANALYSIS 62 7.1 INTRODUCTION ................................................................................................ 62 7.2 CONVERTING CIRCUIT TO BETA NETWORK ............................................. 62 7.2.1 BETA NETWORK ..................................................................................... 63 7.2.2 IDENTIFYING STABILITY PROBLEMS ............................................... 63 7.3 SIMPLIFYING THE BETA NETWORK ............................................................ 65 7.4 VERIFYING USING SSPICE ............................................................................. 67 7.4.1 IDENTIFYING THE PROBLEM .............................................................. 70 7.5 FIXING THE STABILITY PROBLEM .............................................................. 70 7.5.1 ADDITIONS TO THE CIRCUIT ............................................................... 71 7.5.2 REEVALUATIN G USING SSPICE .......................................................... 72 7.5.3 VERIFYING WITH PSPICE ...................................................................... 73 7.5.4 VERIFYING WITH LAB DATA ............................................................... 76 8 EFFICIENCY AND TOTAL HARMONIC DISTORTION 77 8.1 INTRODUCTION ................................................................................................ 77 8.2 PSPICE SIMULATIONS ..................................................................................... 77 8.3 LAB DATA .......................................................................................................... 79 8.4 TOTAL HARMONIC DISTORTION ................................................................. 83 8.5 EFFICIENCY FOR AUDIO ................................................................................. 83 9 DESIGN IMPROVEMENTS 85 9.1 INTRODUCTION ................................................................................................ 85 9.2 USING BETTER OP-AMP TO LOWER THD ................................................... 85 9.3 USING MORE BIASING TO LOWER THD ...................................................... 86 10 FUTURE STUDY 89 vi 10.1 INTRODUCTION .............................................................................................. 89 10.2 IDENTIFYING STABILITY PROBLEMS USING CLOSED-LOOP APPROACH ....................................................................................................... 89 10.2.1 TRANSIENT RESPONSE ........................................................................ 90 10.2.2 AC FREQUENCY RESPONSE ................................................................ 94 10.2.3 ANOTHER TEST USING AN INVERTING AMPLIFIER DESIGN ...... 98 11 CONCLUSION 104 APPENDIX A -- - 106 APPENDIX B - - 107 APPENDIX C - - _ - _ -- - - 114 APPENDIX D 115 APPENDIX E 120 APPENDIX F - - 131 APPENDIX G - - 134 BIBLIOGRAPHY -136 vii LIST OF TABLES Table 8.3.1: Measuring Class B efficiency ....................................................................... 80 Table 8.3.2: Measuring Class G efficiency ....................................................................... 82 viii LIST OF FIGURES Figure 2.1: Schematic of basic Class G amplifier design ................................................... 4 Figure 2.2: Schematic of Class G amplifier design #1 ....................................................... 4 Figure 2.2.1.1: Simplified schematic of design #1 when VIN > O ....................................... 5 Figure 2.2.1.2: Schematic of Stage One - large signal model ............................................. 6 Figure 2.1.1.3: Graph of Stage One VIN and Vom ............................................................. 8 Figure 2.1.1.4: Simplified Schematic of Stage One ............................................................ 8 Figure 2.1.1.5: Graph of base current and emitter current of Q1 ........................................ 9 Figure 2.2.2.1: Q; in Active Region ................................................................................. 10 Figure 2.2.2.2: Q; in Saturation Region ............................................................................ 10 Figure 2.2.3.1: Schematic of Stage Two - Q in Saturation Region ................................. 11 Figure 2.3.3.2: Graph of base and emitter currents of transistor Q1 ................................. 13 Figure 2.2.3.3: Graph of base and collector voltages of transistor Q1 .............................. 13 Figure 2.2.4.1: Schematic of Stage Two - Q; in Active Region ....................................... 15 Figure 2.3.1: Schematic of design #2 ................................................................................ 17 Figure 2.3.1.1: Schematic of Stage One - large signal model ........................................... 17 Figure 2.3.1.2: PSpice circuit file with schematic ............................................................ 18 Figure 2.3.1.3: Graph of VIN and vow ............................................................................. 19 Figure 2.3.1.4: Graph of the base and emitter current of transistor Q1 ............................. 19 Figure 2.3.2.1: Schematic of Stage Two - large signal model .......................................... 20 Figure 2.3.2.2: Graph of VIN and Vom - Stage One and Stage Two ................................ 21 Figure 2.3.2.3: Graph of 131, 132, 151/20, and 1152/20 .......................................................... 22 Figure 2.3.2.4: Graph of VBC of transistor Q1 ................................................................... 22 Figure 2.3.2.5: Graph of current spikes in base of transistor Q1 ....................................... 23 Figure 2.3.3.1: Schematic of circuit with protection diode added .................................... 24 Figure 2.3.3.1.1: Schematic and equations ....................................................................... 24 Figure 2.3.3.2.]: Schematic and equations ....................................................................... 25 Figure 3.1.1: Schematic using Op—Amp with feedback in design .................................... 27 Figure 3.2.1: Graph of Vm and output voltage of Op-Amp .............................................. 28 Figure 3.2.2: Graph of current flowing from Op-Amp ..................................................... 29 Figure 3.2.3: Graph of the collector voltage of Q1 ........................................................... 29 Figure 3.2.4: Graph of Vom across the load ..................................................................... 30 Figure 3.2.5: Graph of Vom - closer view ........................................................................ 30 Figure 3.3.1: Graph of VIN and output voltage of Op-Amp .............................................. 31 Figure 3.3.2: Graph of current from Op-Amp .................................................................. 32 Figure 3.3.3: Graph of the base currents of transistors Q1 and Q2 .................................... 32 Figure 3.3.4: Graph of the collector voltage of transistor Q1 ............................................ 33 Figure 3.3.5: Graph of the current from power supplies V1 and V2 ................................. 33 Figure 3.3.6: Graph of Vom across the load ..................................................................... 34 Figure 3.4.1: Schematic of Class G with an additional Class B stage .............................. 35 Figure 3.4.2: Graph of maximum Vom ............................................................................ 35 Figure 3.4.3: Graph of VIN and the output voltage of the Op-Amp .................................. 36 Figure 3.4.4: Graph of VQUT ............................................................................................. 36 Figure 4.2.1: Graph of current from all power supplies ................................................... 38 Figure 4.2.2: Schematic of amplifier with noise and PN junction diodes ........................ 38 ix Figure 4.2.3: Graph of noise in Vom due to PN junction diodes ..................................... 39 Figure 4.2.4: Graph of current from power supplies using Schottky diodes .................... 40 Figure 4.2.5: Graph of very]: using Schottky diodes .......................................................... 40 Figure 4.3.1: Graph of currents from the power supplies using a 10kHz Signal .............. 41 Figure 4.3.2: Graph of the current from V2 - rise time analysis ....................................... 42 Figure 5.2.1: Picture of breadboard circuit ....................................................................... 44 Figure 5.2.2: Plot Of VOUT and VOP-AMP ............................................................................ 44 Figure 5.3.1.1: Plot of Vom and VQP.AMP ......................................................................... 46 Figure 5.3.1.2: Plot of Vom and Vop.AMp - closer view ................................................... 46 Figure 5.3.1.3: Plot of +/- 15 volt power supply pins ....................................................... 47 Figure 5.3.1.4: Plot of +/— 15 volt power supply pins - closer view ................................. 47 Figure 5.3.1.5: Plot of Vom and VQP-AMP with bypass capacitor added ........................... 48 Figure 5.3.2.1: Schematic of power supply using batteries .............................................. 48 Figure 5.3.2.2: Plot of Your and Vop-AMp ......................................................................... 49 Figure 5.3.2.3: Plot of +/- 12 volt power supplies ............................................................ 50 Figure 5.3.2.4: Plot of +/- 12 volt power supplies with bypass capacitor added .............. 50 Figure 5.3.2.5: Plot of +/- 12 volt power supplies while playing music ........................... 51 Figure 5.3.2.6: Plot of +/- 12 volt power supplies with capacitor while playing music ...51 Figure 6.2.1: Simplified "real" Op-Amp ........................................................................... 53 Figure 6.3.1: Graph of Your and VQP-AMP - oscillating power supplies out of phase ....... 54 Figure 6.3.2: Close up view of Figure 6.3.1 ..................................................................... 55 Figure 6.3.3: Graph of Vom and Vop-AMp - oscillating negative power supply only ....... 56 Figure 6.3.4: Close up view of Figure 6.3.3 ..................................................................... 56 Figure 6.3.5: Graph of Vom and VOP.AMPI- oscillating positive power supply only ........ 57 Figure 6.3.6: Close up view of Figure 6.3.5 ..................................................................... 57 Figure 6.3.7: Graph of Vom and Vop.AMP - oscillating power supplies in phase ............. 58 Figure 6.4.1: Schematic for testing stability ..................................................................... 59 Figure 6.4.2: Graph of Vow ............................................................................................. 60 Figure 6.4.3: Graph of Your and N»; .............................................................................. 60 Figure 6.4.4: Graph of Vom, -Vm, and power supply pins .............................................. 61 Figure 6.4.5: Graph of power supply pins - close up view ............................................... 61 Figure 7.2.1: Giacoletto's transistor model ....................................................................... 62 Figure 7.2.1.1: Beta network - high frequency model ...................................................... 63 Figure 7.2.2.1: Graph of II/Bl and |Adm| .......................................................................... 64 Figure 7.2.2.2: Close up view of Figure 7.2.2.1 ............................................................... 65 Figure 7.3.1: Schematic of simplifying the beta network ................................................. 65 Figure 7.3.2: Simplified schematic when VBIAS = 6.133 volts ......................................... 66 Figure 7.3.3: Simplified schematic when VBIAS = -6.232 volts ........................................ 66 Figure 7.3.4: Graph of WW and |Adm| where VBIAS = 6.133 volts ................................... 66 Figure 7.3.5: Graph of ll/Bl and |Adm| where VBIAS = -6.232 volts ................................. 67 Figure 7.5.1: Adding RADD to lower the Q value .............................................................. 70 Figure 7.5.1.1: Adding RADD in original circuit ................................................................ 71 Figure 7.5.1.2: RADD in Series with CADD ......................................................................... 72 Figure 7.5.1.3: Adding RADD and CADD in series .............................................................. 72 Figure 7.5.3.1: Graphing the gain of Vow/VAC ................................................................ 74 Figure 7.5.3.2: Graphing the Form VII and Form VIII of the output equation ................ 74 Figure 7.5.3.3: PSpice circuit file to plot Form VII and VIII .......................................... 74 Figure 7.5.3.4: Graph of Beta Network Analysis with VBIAS = 6.133 volts ..................... 75 Figure 7.5.3.5: Graph of Beta Network Analysis with VBIAS = -6.232 volts .................... 76 Figure 8.2.1: Schematic of Class B - efficiency testing .................................................... 78 Figure 8.2.2: Graph of Class G verses Class B efficiency ................................................ 79 Figure 8.3.1: Graph of Class B and Class G efficiency - lab data .................................... 82 Figure 9.3.1: Schematic model for improved Class G amplifier ...................................... 86 Figure 9.3.2: Schematic of Class G with more biasing ..................................................... 87 Figure 9.3.3: Graph of Vom (MAX) at 20 kHz ................................................................ 87 Figure 9.3.4: Efficiency of Class G with more biasing and Class B amplifier ................. 88 Figure 10.2. 1: Schematic of example circuit .................................................................... 89 Figure 10.2.1.1: PSpice files with schematic .................................................................... 91 Figure 10.2.1.2-A: PSpice output graphs .......................................................................... 92 Figure 10.2.1.2-B: PSpice output graphs .......................................................................... 92 Figure 10.2.1.2-C: PSpice output graphs .......................................................................... 93 Figure 10.2.1.2-D: PSpice output graphs .......................................................................... 93 Figure 10.2.2.1: PSpice file with schematic ..................................................................... 94 Figure 10.2.2.2: Graph of Beta Network Analysis ........................................................... 95 Figure 10.2.2.3: Close up view of Figure 10.2.2.2 ........................................................... 95 Figure 10.2.2.4: Graph of Beta Network Analysis, Gain = 1 ........................................... 97 Figure 10.2.2.5: Graph of Beta Network Analysis, Gain = 100 ....................................... 98 Figure 10.2.3.1: PSpice file with schematic using inverting amplifier ............................. 99 Figure 10.2.3.2-A: PSpice output graphs ........................................................................ 100 Figure 10.2.3.2-B: PSpice output graphs ........................................................................ 100 Figure 10.2.3.2-C: PSpice output graphs ........................................................................ 101 Figure 10.2.3.2-D: PSpice output graphs ........................................................................ 101 Figure 10.2.3.3: Graph of Beta Network Analysis ......................................................... 102 Figure 10.2.3.4: Close up view of Figure 10.2.3.3 ......................................................... 102 Figure 10.2.3.5: Graph of Beta Network Analysis, Gain = 100 ..................................... 103 Figure 10.2.3.6: Graph of Beta Network Analysis, Gain =1 .......................................... 103 Figure B-l: Basic negative-feedback topology ............................................................... 107 Figure B-2: Example graph of Adm and NB .................................................................. 108 Figure B-3: Graph of Adm, 1/[3 and the phase of Adm + l/B ......................................... 113 Figure 0-1: PSpice circuit file ........................................................................................ 114 Figure D-l: PSpice circuit file ........................................................................................ 115 Figure D-2: PSpice small signal bias solutions ............................................................... 116 Figure D-3: PSpice circuit file ........................................................................................ 117 Figure D-4: PSpice circuit file ........................................................................................ 118 Figure D-5: PSpice circuit file ........................................................................................ 119 Figure E-l: PSpice circuit file ......................................................................................... 120 Figure E-2: PSpice small signal bias solutions ............................................................... 121 Figure E-3: PSpice operating point information ............................................................. 122 Figure E-4: PSpice small signal bias solutions ............................................................... 123 Figure E-S: PSpice operating point information ............................................................. 124 Figure E-6: PSpice circuit file ......................................................................................... 125 Figure B-7: PSpice circuit file ......................................................................................... 126 Figure E-8: PSpice circuit file ......................................................................................... 126 Figure E-9: Sspice results ............................................................................................... 127 Figure E-lO: Sspice results ............................................................................................. 128 Figure E-l 1: Sspice results ............................................................................................. 129 Figure E-12: Sspice results ............................................................................................. 130 Figure F -1: PSpice circuit file ......................................................................................... 131 Figure F-2: PSpice circuit file ......................................................................................... 132 Figure F-3: PSpice THD results ...................................................................................... 133 Figure F-4: PSpice THD results ...................................................................................... 133 Figure G-l: PSpice circuit file ........................................................................................ 135 xii Chapter 1: Introduction and Background 1.1 Introduction In the modern world, audio amplifiers sacrifice power efficiency for better sound quality. However, with the increasing use of portable devices such as cell phones, walkmans, and laptop computers, the need for audio circuits to use less battery power is increasing. With a more efficient amplifier, a large power amplifier could be made smaller because the amplifier would operate at lower temperatures, which would require less heat sinks. There are articles that discuss using a Class G amplifier for an improved efficiency circuit [7] [8] [10]. However, few discuss the overall performance of the circuit in audio applications. This thesis presents using an Operational amplifier with feedback along with the Class G amplifier to produce a more efficient circuit that would be suitable for audio applications. 1.2 Background A course in Application of Analog Integrated Circuits (ECE 484), offered at Michigan State University, was an important stimulant for the topic of this thesis. In this course, students learn about using operational amplifiers for audio circuits, filters, and some of the stability problems associated with them. Motorola expressed interest in a study of the Class G amplifier to increase battery life in cell phones. With an existing interest in audio circuits and an application for a major company, this inspired the author of this thesis to conduct research on the Class G amplifier. 1.3 Thesis Outline The thesis begins in chapter two by explaining the design of a Class G output stage. This chapter shows two possible designs for the output stage with equations and shows which design will be better to use in this thesis. Chapter three introduces using an operational amplifier with feedback to the Class G output stage to lower the distortion. Chapter four addresses some known issues with this Class G amplifier before building the circuit in the lab for testing. In chapter five, construction details as well as performance results are presented. This chapter will show stability problems with this new amplifier design. Chapter six analyzes the lab data and uses PSpice to located the stability problem by making the computer simulation match the results found in lab. Chapter seven performs a Beta Network Analysis on the computer simulation circuit that matches the lab data to further identify what is causing the stability problem. This chapter uses a new technique for finding the stability problem. A program called Sspice (Symbolic SPICE), developed by Dr. Gregory Wierzba at Michigan State University, is used to approximate the symbolic representation of the circuit when it is unstable. After identifying the problem, a solution is implemented to eliminate the stability problem. Chapter eight analyzes the efficiency and total harmonic distortion of the final circuit. Chapter nine offers some more possible design improvements. Chapter ten presents future work on using a closed-loop analysis approach to identifying stability problems. Chapter eleven presents the conclusion. The appendices contain all the PSpice simulation files. The appendices also contain information on Sspice and the Beta Network Analysis Technique. A bibliography is presented as the last chapter in this thesis. Chapter 2: Designing Class G amplifier 2.1 Introduction The Class G amplifier gives improved power efficiency compared to the conventional Class B amplifier. The Class B amplifier is not very efficient for small input signals because there is a large voltage drop across the output transistors with current flowing through the transistors and causing them to dissipate power as heat. The Class G amplifier switches to a lower voltage power supply during times when the input signal is small. The output transistors will not get as hot and use less power [4] [10]. This, in turn, increases the efficiency of the amplifier. This improved efficiency will keep the amplifier cooler requiring less heat sinks and will use less energy to operate. The schematic of the general design of the Class G amplifier is shown in Figure 2.1. The Class G amplifier introduces multiple power supplies to achieve this improved efficiency. This new amplifier requires more circuitry than the class B design and careful considerations must be made to keep the circuit stable. This chapter will Show two possible designs for controlling the Class G amplifier shown in Figure 2.1. V2 02 v1 D1 01 01 ' 02 RL oz: _ v1' ' v2' Figure 2.1: Schematic of basic Class G amplifier design 2.2 Class G Amplifier Design #1 j> V1 02 01 R1 RL 1;.- V1' V2' Figure 2.2: Schematic of Class G amplifier design #1 Design #1 of the Class G amplifier is shown in Figure 2.2. This design uses a complementary pair layout commonly used in the Class B amplifier design except with more transistors. A main characteristic of this design is the use of resistors in the base of transistors Q1 and Ql'. The functionality of this circuit design can be analyzed in stages. The first stage will be when only the power supply, V1 is being used. The second stage will be when only the V2 power supply is being used. For each stage, the large signal and the small signal model Of the circuit will be analyzed. The same analysis can be applied to the circuit when the negative power supplies are active due to the symmetry of the circuit design. 2.2.1 Stage One Analysis - Large Signal Model Stage One of the Class G amplifier is Operational when only the lower value power supply is being used. Particularly, for this analysis, this stage is on when the input signal is positive but small enough that only power supply, V1, is supplying current. Power supplies, Vl', V2, and V2' will not be supplying any current to the circuit. Figure 2.2.1.1 shows a simplified schematic of the design #1 when VIN is positive. Transistors Q1' and Q2' will be in Cut-Off. V2 j V1 QZ D1 R1 01 m 6 RL Figure 2.2.1.1: Simplified schematic Of design #1 when VIN > 0 Figure 2.2.1.2 shows the large signal model of the first stage when VIN is greater than VBE(on) of Q1 but less than the voltage required to put transistor,Q2, into the Active Region and causing transistor, Q2, to be in Cut-Off. V1 Dl Ff 13*18 ll _, R1 [I 01 Your VIN RL Figure 2.2.1.2: Schematic of Stage One - large signal model The equation for Your using the large signal model can be solved as follows. Vour=(B+1)*IB*RL _ VIN ”VOUT - VBE(ON) 1 _ B R, (VIN-VOUT-VBE ON) VOUT=(13+1)* R1 ‘ )*RL R R =(B+1)*(VIN‘VBE(ON))*EL‘(B+1)*VOUT*‘R—L‘ 1 1 = (B + 1) * (VIN -VBE(ON)) * RL R R 1+ +1 *—-L- 1 (l3 ) R1 _—_ (l3 + 1) * (VIN " VBE(ON)) _R_1 RL+(B+1) (VIN - VBE(ON)) VOUT = R1 ————————+1 RL*(B+1) The equation for Your shows that the smaller R; is, the closer Vom will equal Vm - VBE(ON)~ Using PSpice, an example of what VIN and Vom would look when only the smaller power supplies are being used is shown in Figure 2.1.1.3. The simplified schematic Of the circuit simulated is shown in Figure 2.1.1.4. °V~ Vour -2.0Ve -4.0V r 1 r Os 0.5m: 1.0m: 1.51115 2.01213 uvtIO) oVilS) Time Figure 2.1.1.3: Graph Of Stage One VIN and Your VIN RL Figure 2.1.1.4: Simplified Schematic Of Stage One Figure 2.1.1.5 shows the base current Of Q1 (13) and the emitter current Of Q1. The emitter current was divided by 20 to fit on the graph. ISmA‘ 15(01) IOmA‘ 18(01) 5mA~ 0A r Y 1 I I Y I Y 0: 0.2m: 0.4ns 0.6ms 0.8ms 1.0m: 1.2m: 1.4m: 1.6m: o IBtQZ) o -IE(QZ) v 18(01) A -IE(Ql)/20 Time Figure 2.1.1.5: Graph Of base current and emitter current of Q1 From the graph of VIN and Your (Figure 2.1.1.3), cross over distortion is observed. This Stage One Of the Class G amplifier is the same as a Class B amplifier. However, the maximum output voltage for this stage is less than the Class B amplifier because Of the diode connected the V1. The maximum efiiciency of the Class G amplifier Operating in Stage One will be lower than the Class B amplifier also because of the diode connected to V1. 2.2.2 Stage Two Analysis - Large Signal Model Stage Two happens when VIN has increased above Vl-Vm causing diode D1 to open circuit and disconnect V1 from the circuit. In Stage Two, transistor Q2 is in the Active Region. But, depending on the value of R1, transistor Q; can be either remain in the Active Region (Figure 2.2.2.1), or go into the Saturation Region (Figure 2.2.2.2). V2 I 13*132 32' l l I l l I V BE B*IBI R1 I *——’VV‘—‘[ | ——> 131 VBE VIN a RL Figure 2.2.2.1: Q in Active Region v2 [MB 4 . I VBE :_ VCE(SAT) R1 HWH . l VBE VIN Figure 2.2.2.2: Q in Saturation Region 10 2.2.3 Stage Two Analysis - Q1 in Saturation Region Choosing R1 small enough will cause transistor Q] to go into the Saturation Region. This implies that Vac of Q is greater than VBC(ON) of Q1 and la is less than 13*181- v2 ‘ [3*132 I 82. I 1" Yea :_ VCE(SAT) R1 I l ’_‘W I"r Your 131 BE VIN RL Figure 2.2.3.1: Schematic of Stage Two - Q in Saturation Region A large signal model Of the Class G amplifier in stage two where transistor Q is in the saturation region is shown in Figure 2.2.3.1. The equation for Vom can be found using the model as shown below. For simplification purposes, assume that VBEHON) = VBE2(ON). ll (V352 + VCE(SAT) - VBEI) ~ YCE(SAT) 1 = Bl R1 R1 Your =((B+1)*132 +IBI)*RL V Your = VIN "Yam - 1131 * R1 Your = YIN - YBEI " VCE(SAT) The equations Show that the current in 131 is controlled by the value of R1. As the value of R1 is decreased, the base current of Q1 increases. As long as Rl's value is small enough for Q to be in the Saturation Region, Your = VIN - VBEHON) - V335“). Figure 2.2.3.2 shows a PSpice simulation graph of the currents in transistor Q1. This graph shows that the base current of Q1 jumps up as VIN increases to where Q2 goes into the Active Region. However, the emitter current of Q1 does not jump up indicating the Q; is now in the Saturation Region. (The emitter current was divided by 10 to fit on the graph.) 12 IOOIA IE(Q1) SOmA- 18(01) OA‘ ‘50?qu r r T 05 0.5a: 1.0m: 1.5a: 2.0m: o ibtql) o -ie(q11/10 Tine Figure 2.2.3.2: Graph Of base and emitter currents Of transistor Q1 Figure 2.2.3.3 shows that the base voltage of Q1 exceeds the collector voltage Of Q1. The characteristics for an NPN Transistor in the Saturation Region are 13>0, Ic>0, Ic< B*IB, and VBE>VBE(ON). This graphs helps to verify that Q is indeed in the Saturation Region. 10.25V 8.00V1 4.00V4 0V~ 6us 100us 200us 300us 400us SOOus n thl) o V(13) Tine Figure 2.2.3.3: Graph of base and collector voltages Of transistor Q; 13 The following equations were used to find what values of R; will satisfy the conditions needed to have transistor Q1 go into the Saturation Region. IC1*RL YIN - VBEl _1 YCI=.(SAr) 2.2.4 Stage Two Analysis - Q1 Stays in Active Region The other case that can happen is when transistor Q1 remains in the Active Region. Figure 2.2.4.] shows the simplified large signal model of this case give thath is positive. 14 V2 *1 132 Ynez B 82 l l I ' l' W131 R1 YBEI h—Wh‘l ' l ’ Your 131 VIN RL Figure 2.2.4.1: Schematic Of Stage Two - Q in Active Region For both transistors Q1 and Q2 to be in the Active Region, the following conditions must be met. ICI = l3 * IBl IC2 = l3 * 1132 131 > O 132 > O VBEI > VBE1(ON) Ynez > VBEZ(ON) These equations will be true when R1> (3+1)*RL VIN - VBEI _1 YCE(SAr) 15 Solving for Your gives the following equations: IC1=l3"1131 IC1==(l3+1)"'1132 Your = (1131 +(B+1)*132)*RL =(B+1)*IBI*RL R =(B+1)*(YIN ‘Your ‘VBEI)*E'I:‘ R1 v * —————+1 =v —v YIN - VBEI Your = R l—‘ “1 (3+1? RI. This result is the same as the case for Stage One. Resistor R1 needs to be large enough to keep Q in the Active Region but at the same time, as R, is increased, Your will decrease. As the maximum Vom decreases, so does the maximum efficiency (given that Your can not exceed V2). 2.3 Class G Amplifier Design #2 - Using Diodes A second design is to use a diode instead of the resistor to keep Q in the Active Region in Stage One and Stage Two. Figure 2.3.1 shows a simplified schematic of this design when VIN is positive. 16 f V1 QZ Dl DBl #i 01 VIN a r RL Figure 2.3.1: Schematic Of design #2 2.3.1 Stage One Analysis - Large Signal Model v1 D1 I I [.f [5*13 18 . YURI IVBEI 01 II I III Your VIN RL Figure 2.3.1.1: Schematic of Stage One - large signal model Figure 2.3.1.1 shows the simplified schematic Of Stage One of this design (when VIN is positive). The following shows the equations for Your and the base current of transistor Q1. 17 Your = YIN - YBE - YDBI B _ Your RL ‘(B+l) = YIN ‘VBE ‘VDBI RI."‘(l3+1) An example circuit was modeled using PSpice to examine the voltage and current levels of this design when it is in Stage One. Figure 2.3.1.2 shows the PSpice circuit file along with the schematic of the circuit simulated. Class G V2 2 0 V1 3 O VlP 4 0 V2P 5 O VIN lO O 02 2 10 Q1 13 11 Q3 14 12 Q4 5 10 12 4 -4 -12 DC 13 15 15 14 Amplifier 0V AC TIP31 TIP31 TIP32 TIP32 D81 10 11 DlN4l48 D82 12 10 DlN4l48 Dl 3 13 D1N58l7 DZ 14 4 D1N5817 RL 15 0 10 .TRAN .lU 20000 0 .MODEL DMOD D .LIB ECE484.LIB .LIB DIODE.LIB .PROBE .END 1 SIN 0 3 1k .lU VIN v2 v1 02 01 . Ql D ‘ 01' oz in 02' v1' ? V2' Figure 2.3.1.2: PSpice circuit file with schematic The results for VIN and Your are shown in Figure 2.3.1.3. Notice that there is more crossover distortion than in the case where a resistor was used in instead Of DB. and D32. 18 4.0V VIN 2.0V 1“//' Your OVW ‘ -2.0V~ ‘S .0V 1 r r 03 0.5a: 1.0m: 1.5m: 2.0m: o VIIVIN) o VIIRLI Time Figure 2.3.1.3: Graph Of VIN and Your Figure 2.3.1.4 shows the base and emitter current, 13 and 15, Of transistor Q1. The emitter current was divided by 20 to fit on the graph. IOmA IE(QI) SmA‘ OA‘ ‘1‘ IB(QI) 'SM 1 r 1 OS 0.5m: 1.0m: 1.5m: 2.035 0 18(01) v -IE(Ql)/20 Tine Figure 2.3.1.4: Graph of the base and emitter current of transistor Q1 19 2.3.2 Stage Two Analysis - Large Signal Model For Stage Two, transistor Q will remain in the Active Region and transistor Q2 will be in the Active Region. The large Signal model of Stage Two is shown in Figure 2.3.2.1. v2 *1 182 VBEZ B 82 I N i *I YDBI YBEI B Bl {III J,I|I——I» v . our 181 VIN (b i“ Figure 2.3.2.1: Schematic of Stage Two - large signal model Using the model from Figure 2.3.2.1, the equation for Your, 131, and 132 can be found as follows: Your =YIN ‘VBEI ‘VDBI [Bl =_VQIL RL *(B+1) I = *I 82 (3+1) BI A PSpice example of this circuit Operating in Stage One and Stage Two was simulated using the same circuit as in Figure 2.3.1.3 but the input voltage was changed 20 from 3 volts peak-tO-peak to 10 volts peak-tO-peak. (VIN 10 0 DC 0V AC 1 SIN 0 10 1k) The graph of VIN and Your is shown in Figure 2.3.2.2. Notice that there does not seem to be any distortion when VIN increases to where power supply V2 in now on and V1 is now disconnected from the circuit. Or, there doesn't seem to be distortion when V2 is turned off and V1 is turned back on. 10V YIN 5V4 1“//’ 0V‘ Your -5v« 'IOV Os 0.5ms 1.0m: 1.5m: 2.0m: O VIIVIN) o VIIRL) Time Figure 2.3.2.2: Graph of VIN and Your - Stage One and Stage Two The base and emitter currents Of transistor Q1 and Q2 are shown in Figure 2.3.2.3. The emitter currents were divided by 20 to fit results on the graph. When V2 is on and V1 is Off, the emitter currents of Q1 and Q2 are about equal to each other. The base currents of Q1 and Q2 are also about equal to each other. This corresponds to the equations derived previously. The graph and equations also show that when the Class G Operates in Stage Two, it takes twice as much base current for a given output current than it would in the Class B amplifier circuit. 21 60mA 40mA‘ 0A- ‘20M Ti f r 03 0.5m: 1.0ms 1.5m 2.01113 0 18(01) 0 18102) v -IE(Ql)/20 A -IE(QZ)/20 Time Figure 2.3.2.3: Graph of 131, 132, 151/20, and 152/20 Figure 2.3.2.4 shows the graph of VBC of Q1. This graph shows thath does not saturate when V2 is on because VBC < ngou). In fact, VBc is about 0 volts when V2 is on. 5V 0V4 -SV1 '10V‘ ‘15V 1 f I 03 0.5m: 1.0m: 1.5m: 2.0m: a VI11,13) Time Figure 2.3.2.4: Graph Of Vac of transistor Q1 22 When looking at the base current Of transistor Q2, one can notice that there are current spikes when V2 turns on and also when V2 turns Off. This is shown in Figure 2.3.2.5. These current spikes may cause noise problems. ISmA IOmAT 5““ \4 0A“ '\ Os 0.5m: 1.0m 1.5m: 2.0m D 18102) Time Figure 2.3.2.5: Graph Of current spikes in base of transistor Q1 2.3.3 Limitations of Design For a typical transistor such as the TIP31A Power Transistor, the base-emitter reverse breakdown voltage is around 5 volts. To keep from destroying the transistor, V53 of all the transistors must stay less than 5 volts (Yr-:13 < 5 volts). TO accomplish this, a diode is placed on the base lead of Q2 and Q2' to prevent reverse breakdown of the transistor [8] [10]. Another diode must be added to the base of Q to keep it in the Active Region to compensate for adding the diode to the base of Q2. The simplified schematic of this new circuit is shown in Figure 2.3.3.1 (V m is positive). A similar design can be found in reference [4]. 23 V2 N j; .. D1 Q1 VIN RL Figure 2.3.3.1: Schematic of circuit with protection diode added 2.3.3.1 Stage One Analysis Again, the large signal model of this circuit in Stage One is created and analyzed to solve for Your and 13 (Figure 2.3.3.1.1). *Ifi VOBI YOBI VBEI <11SQDII|B B '|I|—-[|II-——-[l|i——-< In Your VIN Kb in Your = YIN - VBEI - 2 "' YDBI ___ Your RL"'(l3+1) = YIN "YBEI “2*YOBI RL*(B+1) Figure 2.3.3.1.]: Schematic and equations 24 The effect of adding the extra diode is that Your will be smaller than VIN by three diode drops instead of two. This will cause the crossover distortion to increase by another diode drop. 2.3.3.2 Stage Two Analysis The large signal model of this new circuit with the protection diode is shown in Figure 2.3.3.2.1 along with the equations for Your, 131, and 132. Again, Your will be smaller than VIN by three diode drops. V2 A I 0 BY” A Ynez YBE2 HIP—ill * YDBI YDBI YBEI o B 18‘ r—illHIIF—l'l Your 181 VIN RL Your = YIN " YBEI ‘ 2 * YDBI I _ Your 131-___, RL (134-1) 132= *IBI (3+1) Figure 2.3.3.2.]: Schematic and equations 25 2.4 Keeping Transistors from Saturating It is a good idea to keep the transistors in this circuit from saturating [4], because the maximum current in the collector of the transistor is 13*132 when the transistor Q; is in the Saturation Region and more current will go through the base of Q1. More power will be lost because of the diodes connected to the base thus making the circuit less efficient for analog amplification. Another point to keeping the transistors from saturating is that the switching speeds of the transistors are slower if the transistor is coming out of the Saturation Region and into the Active Region. 26 Chapter 3: Using an Operational Amplifier with Feedback 3.1 Introduction In order to get rid of the crossover distortion and distortions due to the B of the transistor changing with current, an operational amplifier (Op-Amp) with feedback may be used to bias this circuit (Figure 3.1.1). An LF411 Op-Amp will be used. However, the output current of the LF411 is limited to 25mA. This will limit the maximum output voltage. To analyze the effects of the Op-Amp on this circuit, VIN will be kept small enough to keep the Op-Amp from current limiting. Rf ———-———Ivv~ V2 ioz v1 RIN Fir DI VIN RL V2' Figure 3.1.1: Schematic using Op-Amp with feedback in design 3.2 PSpice Simulations of Stage One This circuit was simulated using PSpice. The input voltage (VIN) is small enough to keep transistors Q2 and Q2' in cutoff so that only the smaller power supplies are active (V 1 and Vl') which is denoted as Stage One. Figure 3.2.1 shows the graph Of VIN and the 27 output voltage of the Op-Amp. The output voltage of the Op-Amp jumps to compensate and eliminate the crossover distortion. Figure 3.2.2 shows the current coming in and out of the Op-Amp which would also be the base currents of transistors Q1 and Ql'. There is a current spike as transistor Q1 and Q1' goes from the Cut-Off Region to the Active Region. Figure 3.2.3 shows the collector voltage of transistor Q1. The graph shows that when the power supply V1 is on (current flowing) the collector voltage drops due to the diode D1. The voltage across the load resistor, Vom, is shown in Figure 3.2.4. The crossover distortion has been greatly reduced by the addition of the Op-Amp. However, by closer inspection, there can. be seen some ringing in the output as Your crosses zero volts which is a sign Of marginal stability problems (see Figure 3.2.5). VOP-AMP OV-I ‘5.0V I ' I 0: 0.5ms 1.0m: 1.5m: 2.0m: D VIIVIN) o V110) Tine Figure 3.2.1: Graph Of VIN and output voltage Of Op-Amp 28 2.0mA‘ OA-I -2.0mA‘ -4.0mA r f I 03 0.5m: 1.0m: 1.5m: 2.0m: D I (VOPAHP) Tine Figure 3.2.2: Graph of current flowing from the Op-Amp 5.2V 5.0VdM— ‘.6V 7 r l’ 05 0.5na 1.0m: 1.5m: 2.0m: o V(13) Time Figure 3.2.3: Graph of the collector voltage Of Q; 29 OV‘ -2.ov4 Os 0.5m; 1.0m: 1.5m: 2.0m: D VIIRL) Tine Figure 3.2.4: Graph of Your across the load $00mV« 0V4 -500InV v I I I I r 447us 460ua 480us 500us SZOus 540us SGOus D VltRL) Time Figure 3.2.5: Graph of Your - closer view 3.3 PSpice Simulations of Stage One and Stage Two The input voltage (VIN) here is large enough to need the use of the larger power supplies (V2 and V2') but small enough to keep the Op-Amp from current limiting. 30 Figure 3.3.] shows the graph of VIN and the output voltage of the Op-Amp. The output voltage of the Op-Amp jumps twice to compensate and eliminate the crossover distortion and the switching of the power supplies. Figure 3.3.2 shows the current coming in and out of the Op-Amp. Figure 3.3.3 shows the base currents Of transistors Q1 and Q2. The base current of Q2 must quickly jump up to match the current that is going into the base of transistor Q1 when power supply V2 turns on. Figure 3.3.4 shows the collector voltage of transistor Q1. The graph shows that when the power supply V1 is on (current flowing) the collector voltage drops due to the diode D1. Then the collector voltage rises as power supply V1 is turned Off and the current increases coming from power supply V2. Figure 3.3.5 shows the current coming from the power supplies V1 and V2. Notice how quickly the current changes during the switching Of the power supplies. The voltage across the load resistor, Your, is shown in Figure 3.3.6. There is no visible distortion in the output due to the switching of the power supplies because of the addition Of the Op—Amp at this frequency. 10V YIN sv- VOP-AMP 0V] -5V- ‘ 1 0V I I I 05 0.5m: 1.0m: 1.5m: 2.0m: D V1(VIN) o VIIO) Time Figure 3.3.1: Graph of VIN and output voltage of Op-Amp 31 0A- -20mA< -40mA r I v 05 0.5ms 1.01115 1.5ms 2.0m: 0 IlVOPAHP) Time Figure 3.3.2: Graph Of current from Op-Amp lOmA 5m» IB(Q1) 0.. IBIQz) -5mA v r 1 Os 0.5m: 1.0m: 1.5ms 2.0a: 0 18(01) v 18(021 Time Figure 3.3.3: Graph of the base currents of transistors Q; and Q2 32 7 . ov« 6.0V-i s.ov-— J J Os 0.5m: 1.0m: 1.5ns 2.0m: D V(13) Time Figure 3.3.4: Graph of the collector voltage of transistor Q. BOOmA 1(v2) 400mA4 1(v1) 0A '400mA r I I 03 0.5m: 1.0m: 1.5m: 2.0m: O -IIVZI o -I(V1) Time Figure 3.3.5: Graph of the current from power supplies V1 and V2 33 0V4 -8.0V l’ f F Os 0.5ms 1.0ms 1.51115 2.01113 CI V1 (RL) Time Figure 3.3.6: Graph of Vom across the load 3.4 Adding a Class B Stage Adding the Op-Amp improves the performance of the Class G amplifier, but the maximum voltage swing of the circuit is limited by the current from the Op-Amp. An Op-Amp can be powered with +/- 18 volts. In order to get the most voltage swing out Of the Op-Amp without current limiting, another Class B stage was added to the output of the Op-Amp. The Class B stage will cause all the base currents for transistors Q1, Ql', Q2, and Q2' to come from the larger power supplies (V 2 and V2') instead Of from the Op- Amp. Figure 3.4.1 Shows the new circuit schematic. 34 F—-—-—-——-’\/\/*r Rf V2 :2 V1 N m RIN Ql VIN RL I0 ’2‘ C? N -l”-—’V\/\—J i4 02' V2' Figure 3.4.1: Schematic of Class G with an additional Class B stage Figure 3.4.2 shows a PSpice graph of Your across the load resistor. With V2 equal to +18 volts and V1 equal to 6 volts, the maximum output voltage is 13.7 volts because Of the diode drops, the output voltage limit of the Op-Amp, and the [3 of the transistors changing as the current increases. 20V 13.96 Volts 10V< OV‘ -10V4 -13.78 Volts '20v fl f I 0: 0.5m3 1.0ms 1.5m: 2.0m: a VllaL) Time Figure 3.4.2: Graph Of maximum Vom 35 Now by setting VIN to equal 13.7 volts peak, the output voltage of the Op-Amp can be seen without clipping in Figure 3.4.3. The output voltage is the maximum voltage swing for this Op-Amp, therefore it is not current limiting. Figure 3.4.4 shows Your across the load resistor without any visible distortion. 20V YIN Iov- / YOP-AMP ov~ -10V‘ —zov . , T Os 0.5m: 1.0m: 1.5m 2.0m: a V1(VIN) o V(100) ‘1‘ me Figure 3.4.3: Graph of VIN and the output voltage of the Op-Amp 20V 10V< 0V< '10V‘ -20V Os 0.5m: 1.0m 1.5m: 2.0m D VIIRL) Tine Figure 3.4.4: Graph Of Vom 36 Chapter 4: Possible Issues 4.1 Introduction There are some design considerations with the Class G amplifier. The effects of switching between power supplies are looked at more closely. The power supplies that are used will have an impact on the performance of the circuit. Also, the diodes that are part of the lower power supplies have an impact on the performance Of the circuit because Of the switching. 4.2 Using Schottky Diodes The Class G amplifier uses diodes to keep current coming from the larger power supplies from going into the smaller power supplies. For this circuit, a small signal PN junction diode is not sufficient because it cannot handle the high amount of current needed to pass through the diode (about 1 Amp for this test circuit). When a PN junction 1N4001 rectifier diode was used for D1 and D2, which can handle the large current, large distortions appeared in the output current of the power supplies in the PSpice simulations (Figure 4.2.1). Figure 4.2.1 shows this spike in current only happening when the amplifier switches from the smaller power supply to the larger power supply. This distortion is due to the fact that a PN junction diode can store charge. 37 SBSmA .00.... 10’ 2) I(Vl) I(V1P) , t . I \ \ i 3' I(V1) /" I(V1P) _,,.,,,. I(V2P) 0A -S3SmA fir r T v r 0.493ms 0.600m5 0.800m3 1.000ms 1.200ms 1.400ms 1.505m3 D 'IIVI) o -1(V2) V -IIVIPl A -I(V2Pl Time Figure 4.2.1: Graph Of current from all power supplies This spiking in the current coming from the power supplies will cause problems when there is some high frequency noise in the circuit. Figure 4.2.2 is the circuit which has a 1 kHz sine wave source plus a 500 kHz sine wave source used to simulate noise. Figure 4.2.3 shows the graph of the output voltage with major distortions happening in the areas where switching between the power supplies occur. Rf V2 RIN , :2 V1 Fl 01 RL 02' ? V2' V2’ K 7; V1' V2' 0 "Z C, h) III—aw Figure 4.2.2: Schematic of amplifier with noise and PN junction diodes 38 5.56V 4.00V< OV‘ -4.00V-I '6.38V I I v r 1 0.477ms 0.600ms 0.800ms 1.000ms 1.200m: 1.400ms 1.509ms D VliRL) Time Figure 4.2.3: Graph of noise in Vom due to PN junction diodes A way to eliminate this problem of noise in the output voltage is by using Schottky diodes for D1 and D2 [10]. Schottky diodes do not have a PN junction but instead have a metal to semiconductor junction. They will not store as much charge as the PN junction diodes do [1]. Figure 4.2.4 shows the graph of the current coming from the power supplies but this time, there is not the spike in current when the circuit switches from the lower power supply tO the larger power supply. 39 568mA .00.... I(V2) I(V1) I(V1P) \\ \ Y I(Vl) / I(V1P) We 1(V2P) '559M I I F I I 0.487m5 0.600ms 0.800m3 1.000ms 1.200ms 1.400ms 1.507m3 o -I(V11 o -I(V2) v -I(V1P) a -I(V2P) Time Figure 4.2.4: Graph Of current from power supplies using Schottky diodes Again, the circuit was tested by adding a 500 kHz signal to the 1 kHz VIN signal to simulate noise. Refer to Figure 4.2.2 for the schematic. Figure 4.2.5 shows the output voltage of this circuit. By replacing the PN junction diodes D1 and D2 with Schottky diodes, the noise problem in the output is eliminated. 5.56V 4.00V-I OV‘ -4.00V1 “6.381) I I r r I 0.477m3 0.600ms 0.800ms 1.000ms 1.200ms 1.400ms 1.509ms D VIIRL) Tine Figure 4.2.5: Graph of Vom using Schottky diodes 40 4.3 Power Supply Issues The transient response of the power supplies will be an important factor for the stability of the Class G amplifier. This is because when V1 is turned off and V2 is turned on, the current of V2 must instantly match the current that was coming from V1. The currents coming from the power supply using a 10kHz sine wave is shown in Figure 4.3.1. This graph indicates how fast the power supply V2 must be able to switch. 542mA 400M- 1(V2) I(V1) I(V1P) . ’\ \ I(V1) / I(V1P) “W I(V2P) -528mA 05 20us 40us 60us 80us 100us D -I(V1) o -I(V2) v -I(VIP) A -I(V2P) Time Figure 4.3.1: Graph of currents from the power supplies using a 10kHz signal 41 542mA 400mAq (15.4u,388m) (14.7u,140m1 0A“ -400mAq °SZBmA r I I T 1 Os 20us 40o: 60us 80us locus o -I (V2) Time Figure 4.3.2: Graph of the current from V2 - rise time analysis By analyzing the current coming from power supply, V2 (Figure 4.3.2), the change in current over time can be calculated as follows: _ =354286iz3505‘Ii 15.4u - 14.7u sec sec The rate of increase equals [9.1.] _ 388m - 140m (It Some power supplies may not be able to switch this fast. 42 Chapter 5: Construction of the Circuit 5.1 Introduction An actual circuit was constructed to Observe the performance of the Class G amplifier. This tested if the circuit worked at all, if it showed signs of being more efficient than the Class B amplifier, and how music sounded when it was played through the Class G amplifier. The main benefit Of building this circuit was the identification of the stability problem, which will be discussed in this chapter. 5.2 Breadboard Lab Data The Class G amplifier was first built on a breadboard (Figure 5.2.1). The circuit was laid out to keep the connecting wires as short as possible. XANTREX power supplies where used to provide enough current to test this circuit. A function generator provided the test Signal of a lkHz sine wave. The circuit that was constructed used quarter—watt resistors. The transistors used were TIP3] (NPN) and TIP32 (PNP) with heat sinks attached. The small signal diodes were 1N4148 and the diodes for the power supplies were 1N5817 Shottky diodes. The output of the Class G amplifier showed high frequency oscillations. Figure 5.2.2 shows the output of the Op-Amp and the voltage across a] load resistor (10 O). This high frequency oscillation appeared when the input signal was large enough to cause the Class G amplifier to use the larger power supplies. After many attempts at rebuilding the circuit, the source of the high frequency oscillations could not be found. The decision was made to take the circuit Off the breadboard and solder the circuit onto a perforated 43 board. No further calculations were made due to the fact that the circuit seemed to be unstable. Figure 5.2.1: Picture of breadboard circuit Figure 5.2.2: Plot of Vou'r and Vop.AMp 44 5.3 Perforated Prototype Board Lab Data The circuit was taken Off the solderless protoboard and rebuilt on a radio shack perf-board to see if the parasitic capacitances of the solderless protoboard were effecting the performance of the Class G amplifier. 5.3.1 Using Switch-Mode Power Supplies The protoboard circuit was hooked up to XANTREX switch-mode power supplies. Figure 5.3.1.1 is the graph of the output of the Op-Amp and the output across the 10 Q load. There is a high frequency oscillation appearing in the output causing distortion. Figure 5.3.1.2 Shows a close up view of the high frequency oscillations that are showing up in the output. The graph shows that the frequency of the oscillation is about 12 MHz. Figure 5.3.1.3 is the graph of the AC signal of the +15 volt power supply pin and the -15 volt power supply pin. Again, the high frequency oscillations appear. Figure 5.3.1.4 is a close-up view Of the high frequency oscillations showing up on the power pins. The graph shows that the frequency of the oscillation is about 16 MHz. Figure 5.3.1.5 shows the output of the Op-Amp and the output voltage across the load when a 0.01uF capacitor was place from the +15 volt supply to the -15 volt supply. This is a suggested technique to eliminate high frequency oscillations [5] [6]. The high frequency oscillations have been eliminated. However, it is still unknown at this point what is causing the high frequency oscillation. 45 Figure 5.3.1.1: Plot of Vom and Vop.AMp Figure 5.3.1.2: Plot of vour and Vonm - closer view 46 Figure 5.3.1.3: Plot of +/- 15 volt power supply pins Figure 5.3.1.4: Plot of +/- 15 volt power supply pins - closer view 47 Figure 5.3.1.5: Plot of Your and Vop.AMp with bypass capacitor added 5.3.2 Using Batteries Since there were high frequency oscillations in the output of the Class G amplifier using switch mode power supplies, it could not be determined if the power supply was becoming momentarily unstable. The protoboard was tested using four 6 volt lantern batteries in the configuration shown in Figure 5.3.2.1 in replace of the switch mode power supplies. +12 and -12 volts was achieved by putting two 6 volt batteries in series. I +12v ;£:_—__—+6v 'iLr -6v VT" ~12v Figure 5.3.2.1: Schematic Of power supply using batteries 48 Even when using batteries, a high frequency oscillation still appeared in the output of the Op-Amp and the load resistor shown in Figure 5.3.2.2. Figure 5.3.2.3 shows the +12 and -12 volt power supply pins (AC coupled). Notice the power supply voltages are not held constant and also contain the high frequency oscillation. A capacitor was place between the +12 and -12 power supplies and the high frequency oscillations seemed to disappear as shown in Figure 5.3.2.4. The voltage drops, however, still remain. Instead of using a lkHz sine wave for the input, music from a CD player was used for this circuit. Figure 5.3.2.5 shows the +/- 12 volt supply pins without the added capacitor. Figure 5.3.2.6 shows the +/- 12 volt supply pins afier the capacitor was added. The added capacitor has eliminated the high frequency noise problems in the circuit. Figure 5.3.2.2: Plot of Vou’r and VOP-AMP 49 Figure 5.3.2.3: Plot of +/- 12 volt power supplies Figure 5.3.2.4: Plot of +/- 12 volt power supplies with bypass capacitor added 50 Figure 5.3.2.5: Plot of +/- 12 volt power supplies while playing music Figure 5.3.2.6: Plot of +/- 12 volt power supplies with capacitor while playing music 51 Chapter 6: Identifying Noise in Lab Data 6.1 Introduction The lab data results presented a high frequency oscillation indicating that the Class G amplifier has a stability problem. A Beta Network Analysis method was used to try and identify that the simulated Class G amplifier was unstable. However, this method did not show that the circuit would be unstable. The simulated circuit also did not show high frequency oscillations in the output when noise was added to the input. Since the simulated data was not matching the lab data, the simulated circuit model needed to be revised. This chapter explains how the simulated circuit model was revised. Since the lab data showed that the power supply pins were oscillating, the circuit model was analyzed when the power pins were forced to oscillate by adding an AC component. This proved to be helpful in identifying the source Of the stability problem. Then, the model was revised by removing the AC component from the power supply pins and allowing the power lines to oscillate on their own by using inductors. While trying to find ways to revise the Class G model, general problems with oscillations in Op-Amp circuits were also noted. 6.2 Problems with Oscillations and Op-Amps From Analog Devices application notes [2], the Op-Amp can be simplified tO the circuit in Figure 6.2.1. This schematic Shows that most of the voltage difference between the amplifier output and the negative supply appears across the compensation capacitor. 52 Because the negative PSRR is limited at high frequencies, the oscillations on the negative power supply will appear on the output. For testing the stability Of the circuit, one method is to analyze the beta network Of the Op-Amp (See Appendix B) [15]. This will test the stability of the circuit due to gain-bandwidth—product, input and output impedance, but because the Op-Amp is removed during the beta network analysis, it will not account for high frequencies coming through the Op-Amp via the negative supply. V+ ~IN /'\ +IN E OUTPUT p—___ CURRENT MI RROR l V” v ' Figure 6.2.1: Simplified "real" Op—Amp 6.3 Oscillating the Power Lines New stability problems came from the lab results. The problem that was found was that when Q was active and Q2 was just becoming active, the output would have a lot of distortion at the top of the wave. Lab results also showed that the power lines for the +15 and -15 volts where oscillating out of phase at a high frequency. In order to figure out where this problem was coming from, the power supplies in the PSpice circuit model where made to oscillate at 12MH2 by adding an AC component to the voltage 53 sources V2 and V2'. The PSpice circuit model used the full model of the 741 Op-Amp (ICL8741) [16] so that the power pins of the Op-Amp would also be modeled. Figure 6.3.1 shows the Your and VOPAMP with the power supplies oscillating out Of phase by 180°. This graph shows the same output that was Obtained from the circuit built in lab. Figure 6.3.2 shows a close up view of Figure 6.3.1 in the location where the output is oscillating along with the large power supply lines. 20V VOPAMP 10V- Your OVT '10V- 'Zov I I I Os 0.5m 1.0m: 1.5m: 2.0m: D vtl9) o V(li) Time Figure 6.3.1: Graph of Your and V0p-AMP - oscillating power supplies in out of phase 54 16.6V 15 ' OV‘W/W +15 Volts YOPAMP .o.ov.\/W\//\/ Your WWW -15 Volts 693.3us 693.4us 693.5us 693.6us 693.7us 693.8us 693.9us 694.0ua o V(l9) o V(ll) v VIZ) A v(5)+20 Tine Figure 6.3.2: Close up view of Figure 6.3.1 The circuit was tested by oscillating only the negative power supply, by oscillating only the positive power supply, and by oscillating both power supplies in phase. The results from these three tests can be seen in Figure 6.3.3, 6.3.4, 6.3.5, 6.3.6, and 6.3.7. Oscillating the negative power supply has more of an effect on the output than oscillating only the positive power supply. Also, oscillating the power supplies out of phase causes more distortion in the output than oscillating the power supplies in phase. The PSpice circuit file used for these tests can be seen in the Appendix for Chapter 6. 55 20V +15 Volts VOPAMP IOVe Your CV-4 -10V< -15 Volts -20V 1 u r 03 0.5m: 1.0m: 1.5m: 2.0m: o V(19) o V(11) v v(2) A V(Sl Tine Figure 6.3.3: Graph Of Your and Vop-AMp - oscillating negative power supply only -15 Volts WWW 0V4 594.7us 594.8us 594.9us 595.0us $95.1us 595.2us 595.3us a V119) o V(lll v vt2) A V(5)+17 Tim. Figure 6.3.4: Close up view of Figure 6.3.3 56 20V +15 Volts VOPAMP 10V‘ Your 0V- -10Vd -15 Volts —2ov , r r Os 0.5ms 1.0m: 1.5m: 2.0m: a V(19) o V111) v v12) A 9(5) Tine Figure 6.3.5: Graph of Your and VOP-AMP - oscillating positive power supply only 16.56V +15 Volts moot/«WW 10.00V4 5.45V ‘l' I V 1' I 741.600u3 741.700u3 741.800us 741.900us 742.000us DV(19) oVill) vvl2) AVIS) Time Figure 6.3.6: Close up view of Figure 6.3.5 57 20V VOPAMP IOV‘ 0V- -10V‘ -20V r ' ' Os 0.5ms 1.0m: 1.5m: 2.0ms Ov(19) 0 VIII) Time Figure 6.3.7: Graph of Your and Vop-AMp - oscillating power supplies in phase 6.4 Putting Inductors on the Power Lines When the large power supplies were made to oscillate at 12MHz, the output Of the circuit was similar to the output of the built circuit in the lab. Another approach was used to test the stability of the circuit with the Op-Amp. Because the change in current of the power supplies is so high (di/dt), it was assumed that inductance in the power supply leads would cause problems with the output of the circuit. To see how the circuit would behave if the power supply lines were allowed to oscillate, a small inductance was added to the large power supplies. This will not affect the DC voltages needed to power the Op- Amp, but will, however, allow high frequencies to get from the output stage transistors to the negative power supply pin Of the Op-Amp. Figure 6.4.1 shows the new schematic of this circuit to be analyzed by PSpice. 58 Figure 6.4.1: Schematic for testing stability The circuit in Figure 6.4.1 has a VIN of lkHz and an added noise signal VNOISE of 400kHz. The circuit will amplify the added noise in the circuit if the circuit is marginally stable. The output Of this circuit is shown in Figure 6.4.2. In most Of the output wave, the 400kHz signal appears but it is attenuated. However, when the larger power supplies are being used, the noise signal has caused a high frequency oscillation at the top Of the waveform. Figure 6.4.3 shows Your with VIN on top to clearly that the noise signal is being amplified only at the tOp Of the output wave. This output looks just like the output that was achieved in the lab. Figure 6.4.4 shows that the positive power supply is oscillating with a larger magnitude than the negative power supply. Figure 6.5.5 shows a close up view of the positive and negative large power supplies. This graph shows that the oscillations are out of phase, which is similar tO the lab data collected. 59 5.0V‘ OV- ~5 . 0V I r I 1.0ms 1.5m: 2.0m: 2.5m: 3.0ms A V(19) Time Figure 6.4.2: Graph of Vom 5.ov~ OV- ‘5 . 0V r f I 1.0m: 1.5m: 2.0m: 2.5m: 3.0m: A V(19) o -V(1) Time Figure 6.4.3: Graph Vom and -Vm 60 20V * +15 V0118 10V< ov- VOUT °10V~ -15 Volts ——4II-I-ur e c M———o——————— -20V 1 r v 1.0m: 1.5m: 2.0m: 2.5ns 3.0ns A V(19) o -V(1) V V121 A V(Sl Tine Figure 6.4.4: Graph Of Vom, -V[N, and power supply pins ° ‘10 ‘O¢""“\: 9" '1.77v f F I r r T 2 2314a: .2313ms 2.2316ns 2.2317ms 2.2318ms 2.2319ms 2.232033 7 V(2)- -15 A V(5)+125 < L Tina Figure 6.4.5: Graph of power supply pins — close up view 61 Chapter 7: Beta Analysis Method 7.1 Introduction The Beta Network Analysis Method (See Appendix B and reference [15]) was used to Show the stability of the circuit. With this particular problem, only part of the output waveform is unstable. In order for the Beta Network Analysis Method to show that the circuit can become unstable, many input biasing points need to be tested first. PSpice was used to get the numerical results for the AC models of the transistors and diodes in the circuit. 7.2 Converting to Beta Network Circuit To convert the Class G amplifier to a beta network for analysis, high frequency models were used for the transistors and the diodes. The high frequency model for the transistor is the Giacoletto's hybrid-1r model shown in Figure 7.2.1 [11] [12]. C B - I, l l\ C_BC + C BE _u_ . Ro _ /"'\ Vpl . Rpl . - gm*Vp1 E Figure 7.2.1: Giacoletto transistor model 62 7.2.1 Beta Network The transistors and diodes in the circuit were replaced with their high frequency AC models. The Op-Amp was replaced with its input resistance and capacitance, and its output resistance. m J! 41 q" 1\ fi\ I _ ,. I c_ac c a: _.. <] Ro ~ V91. 1. RP ql'Vpi c_or ' .1: IL -- I. A ., W1 1\ II 1\ 1\ C IC w [.ml _DC R_Dl ? c a: _ I l Ito‘, c II: 3.. I i an ,~ v92 “pi :’ ~ VpI RpI - gn-Vpi - SI'VPI no . III In. vans c III: ] ‘ i _i " ’I‘ V 1 I llo - 9..th ' ,- th apt . ll - 1. .. vrtc II J 6‘] '- v’ :14“): r’” 1: m c SC ,2 II c oz ac - I! l\ «_02 t I C B! 2 Ro \ II V91" Ipl % W1 qu'th LVZ P ; Figure 7.2.1.1: Beta network - high frequency model 7.2.2 Identifying Stability Problems The beta network was analyzed by changing the input biasing level and Observing the gain of 1/ B compared to the Open-loop gain Of the Op-Amp. The phase angle where these two plots cross gives the phase margin of the full circuit. The values for the transistor and the diode models were Obtained from PSpice by setting the input of the original circuit to the desired biasing level and observing the small signal bias solution 63 from the PSpice output file. For most of the biasing levels, the phase margin indicated that the circuit would be stable. However, there were two biasing levels (6.133 volts & - 6.233 volts) that caused the gain of 1/ [3 to cross the open-loop gain of the Op-Amp a second time! The phase margin at these two points indicated that the circuit would be unstable (Figure 7 2.2.1 & Figure 7.2.2.2). 12C 100< 50d Vbias . 6.133 volts \ Vbiaa - -6.232 volts (20.81H,-42.01) (23.62H,-Q2.85) ‘50 r V I v IOOmHz 1.0Hz 100Hz IOKHz 1.0HHz IOOHHz 0 o -VdB(77) v A VdB(73) Frequency Figure 7.2.2.1: Graph of %l and [Adm] 35 “‘0‘ SEL>> O o -VdB(77) v a VdB(73) 0d -200d< -400d , 17.42MB: 30.00an a o Vp(73)+Vp(77) Frequency Figure 7.2.2.2: Close up view of Figure 7.2.2.1 7.3 Simplifying the Beta Network LVZ - 11 A a? I l\ I l\ c— o c an..- <> - gn‘Vpi I. K 1% J, C_3C [\fV\;]I;JVNFJ ' O a: .. ‘ c 3!: _J- "N ’1‘ Vpl Rpt qn'Vpi - qn'Vpi L VIIAS VAC Figure 7.3.1: Schematic of simplifying the beta network The beta network was then simplified to just focus on what was causing the gain ~ of MB to cross the open-loop gain of the Op-Amp a second time (Figure 7.3.1, 7.3.2, & 7.3.3). The output of 1/ B of the simplified circuits was compared to the original beta 65 circuit and is shown in Figure 7.3.4 & Figure 7.3.5. 26———<~———43 AggfiIVA' 11 R 0818 CBC _A GMA'Vl2,3) _ l/Z'RL VOUT 77 ;: CBC 2 ' l/Z‘RL Figure 7. 3. 2: Simplified schematic when VBIAS — 6.133 volts 2(_0__® 3 V”. 12 R 0818? CBC_ B GMB‘V(3.2) — l/Z‘RL VOUT 77 LVZP :: CBC 2P " 1/2‘RL Figure 7 ..3 3: Simplified schematic when VBIAS— — -6. 232 volts 50 Simplified Beta Circuit Original Beta Circuit -50 V f j' I Y I T 1.0Hz 10H: 100Hz 1.0KHz IOKHz 100KB: 1.0MHz IOHHz D o -VdB(77) lOOHHz Frequency Figure 7.3.4: Graph of % where VBIAS = 6.133 volts 66 80 40* Simplified Beta Circuit Original Beta Circuit -4C 1.0Hz D o -VdB(77) IOHz 100Hz Figure 7.3.5: 7.4 Verifying Using Sspice 1.0KHz IOKHz IOOKHz Frequency Graph of 1.0HH2 10MB: 100MHz where VBIAS = -6.232 VOltS These simplified circuits were then analyzed using Symbolic SPICE (Sspice). To cause the graph of the gain of 1/ B to shoot down towards negative infinity like it does, the Laplace Transform of the output equation must contain a second order zero, which will be called a "Form VII", with a very high Q [15]. This will be the same as saying IN (77) (which is 1N our) will have a second order pole, which will be called a "Form VIII", with a very high Q value [15]. Sspice found the symbolic output equation along with the numerical output equations shown. The first Sspice analysis was performed while using VBIAS = 6.133 volts. The equation obtained from Sspice for the IN our is as follows: 67 1_.9181e-30-(s+.9052e10)~(sz+.2775e6-s+.1981e17) V 77) B .1239e-2o-s2+.2667e-4 S 82 S 6.17 [ +1) + +1 ' 1.44GHz-2n (22,4MHZ.2n)2 (22.4MHz-2n)-507 2 S +1 [(23.35MH7.-2n)2 J 2-(LV2-(CBCA +CBC2)-sz +1) RO-GMA-RL-REQDBIB Numerator of V(77) = Form VIIof 1 V 7 7) = (va - (CBCA + CBC2) - 32 +1) 52 S = + +1 2 l t i [J I * i] * oo LV2-(CBCA +CBC2) 211: LV2-(CBCA+CBCZ) 2n fc ~ 1 * J— LVZ - (CBCA + CBCZ) 21: Q z oo Using the approximator option in Sspice with a threshold of 0.9, the denominator can be found to be: Denominator of V(77) = —2- - [CBCA - s + i) ~ (LV2 - CBCZ) - 32 + 1) RL R0 Form VIII of V(77)=1/(LV2 . CBC2) . s2 +1 J 1 I fez ___—._ LV2-CBC2 21: ono The second Sspice analysis was performed while using VBIAS = -6.232 volts. The equation obtained from Sspice for the IN our is as follows: 68 _1_ _ .2239e-29-(s+.6806e10)-(s2 +.3097e6-s+.1470e17) V(77) B .2592e-20-52 +.4198e-4 2 5.34-[ 3 +1) 5 + 8 +1 1.08GHz-21t (19,3MHZ.2,.)2 (19.3MHz-21t)-391 " 2 8 +1 [(20.25MHz-21t)2 ] 2-(LV2P-(CBCB+CBC2P)-52 +1) Numerator of V(77) = RO-GMB-RL . REQDBIBP Form VIII of —1— = (va9 - (CBCB + CBC2P) - 52 +1) V(77) 52 S + 2 l l 1 ,_1_ [f ._].,, LV2P-(CBCB+CBC2P) 211: LVZP-(CBCB+CBC2P) 21: 1 1 f = *— c \/LV2P~(CBCB+CBC2P) 21: Q = 00 Using the approximator option in Sspice with a threshold of 0.9, the denominator can be found to be: Denominator of V(77) = —2—- . (CBCB - s + L) - (LVZP . CBC2P) - $2 + 1) RL R0 Form VIII of V(77)=1/(LV2P - CBC2P) - 52 +1) f -J 1 .1 ° LV2PoCBC2P 2n ono 69 7.4.1 Identifying the problem The Q of the simplified circuits at the two different biasing levels is too high. A Q this high means that at this frequency, the noise will be greatly amplified in the circuit to the point where the output will oscillate at this frequency. This is the stability problem with the original circuit and can be fixed. 7.5 Fixing the Stability Problem 2 I, 4 "* 1Y7 1 no a 0313 CBC_A GMA'Vl2,3) - 1/2'81. vour 14 vac Lv2 cac_. anon 1/2‘RL Figure 7.5.1.: Adding R191) to lower the Q value To fix the stability problem previously shown, the Q of the simplified beta network circuits must be dramatically lowered. The general equation of Vour for the circuit in Figure 7.5.1 is shown below (general equation). Before the resistor RADD was added to the circuit, Q1= co and Q2=3 62.8. The stability problem can be solved by adding a small resistance, RADD into the circuit to lower the values of Q1 and Q2. A value of 10 Ohms was chosen for RADD, which lowered Q1 to 0.068 and Q2 to 0.074 (Numerical Analysis). 70 General Equation: A[ 5 2+ 5 +1] VOUT= (WI) “”01 VAC [is—+1]- 52 + 3 +1 W3 (w2)2 W2-Q2 Numerical Analysis: 2 0.285 . S + 8 +1 VOUT = [(23,37MHZ.2,,)2 (23.37MHz.2n)-0.068 J VAC [ s J 32 8 +1 - + +1 1.607GHz - 21: (21.29MHz-211)2 (21 .29MH2 - 21:) - 0.074 7.5.1 Additions to the circuit Adding the resistor of 10 Ohms would cause problems at low frequencies (Figure 7.5.1.1). At low frequencies, too much current would be going through RADD and cause the circuit to not function properly or become very inefficient. V2 RADD QZ or Figure 7.5.1.1: Adding RADD in original circuit By adding a capacitor in series with RADD, CADD (0.01uF), the desired effect can be achieved without the major power losses at lowfrequencies (Figure 7.5.1.2). Figure 7.5.1.3 shows how this would be added to the simplified circuit. 71 V2 CADD QZ CADD or Figure 7.5.1.2: RADD in Series with CADD 2 —W~ K 1 RO R DBlB CBC_A GMA*V (2, 3) " A _1_ 1/2*RL CADD 14 VOUT VAC fb LV2 CBC_EJ\ RADD 1/2*RL Figure 7.5.1.3: Adding CADD and RADD in series 7.5.2 Reevaluating Using Sspice The capacitor in series with the resistor (RADD and CADD) was added to the simplified circuit where RADD equals 109 and CADD equals 0.001uF. The output equation was reevaluated using Sspice and shown below (Numerical Analysis). The capacitor affected the center frequency of the Form VII and Form VIII and also added a pole and a zero at very close frequencies. The pole and zero, because the frequencies are so close (343MHz and 284MHz), can be approximated to cancel each other out. The Form VII and VIII center frequencies are the same (1.59MHz) with low Q values (6.3) so they also 72 can be approximated to cancel each other out. This leaves only a pole at 1.6GHz. Therefore, the capacitor in series with the resistor should eliminate the stability problem. Numerical Analysis: 2 S S 5 0.284 +1. + +1 Vow (343.3MHz-21t ][(1,59m.2n)2 (1.59MHz-2n)-6.31 J I . II . J 52 . ————+l- +1- + +1 1.607GHz- 2n 284.9MHz- 21: (1.59MI-Iz: 2102 (1.59MHz- 21:) - 6.32 0.284 ~ ~ ___s__ +1) (16070112- 211 7.5.3 Verifying with PSpice The numerical analysis equation can then be verified using PSpice to plot the equation. Figure 7.5.3.1 shows the gain of VOUT/V AC of this modified circuit. Figure 7.5.3.2 shows the graph of the numerical analysis equation separated into a Form VII and a Form VIII. This graph shows the canceling of the pole and zero described above. The PSpice file to plot the Form VII and Form VIII is shown in Figure 7.5.3.3. 73 -10 -15< -20 1.0KHz IOKHZ lOOKHz 1.0MHl IOMHZ 100MHz 1.06Hz D VdBlI‘l Frequency Figure 7.5.3.1: Gain of VOUT/V AC using C ADD in series with RADD 80 4‘10-1 o h D I l I _‘Oq -80 1.0KHz 10KB: 100KB: 1.0HHz IOHHz lOOHflz 1.06Hz D VdBlZO) o VdBlZl) Frequency Figure 7.5.3.2: Graphing the Form VII and Form VIII of the output equation The PSpice circuit file: Plotting Forms 7 and BVAC l 0 AC 1 * V14 is the output voltage of the circuit above The Form 7 of the equation for this simplified circuit ES 20 0 LAPLACE {V(1,0)} {3“2/(23.37e6*2*3.14l6)“2+s/((23.37e6*2*3.1416)*0.068)+1} * The Form 8 of the equation for this simplified circuit E6 21 O LAPLACE {V(1,0)} {l/(s‘2/(21.29e6*2*3.1416)“2+s/(21.29e6*2*3.1416*0.074)+1)} .AC DEC 9000 1000 lOOOMEG .PROBE . END * Figure 7.5.3.3: PSpice circuit file to plot Form VII and VIII 74 Now, going back to the original Class G amplifier circuit using actual parts and not the AC models, the Beta Network Analysis is performed again with the addition of RADD and CADD (RADD = 10 Q, CADD = 0.001 11F). The graph of the Beta Network Analysis when VBIAS equals 6.133 volts is shown in Figure 7.5.3.4. The graph shows a plot of the phase of the beta network plus the Op-Amp. This plot indicates that the phase margin is 180°-108 ° = 72 °, which is stable. The graph of the Beta Network Analysis when VBIAS equals -6.232 volts is shown in Figure 7.5.3.5. The graph shows a plot of the phase of the beta network plus the Op-Amp. This plot indicates that the phase margin is 180°—103 ° = 77 °, which is also stable. 0d \ A A -100d4 ' ' “ -200d< (509.3K,'108.3) -300d-4 SEL>> ‘400d D Vpl73)9Vp(77l 100- 50~ O'l‘r " "' "' "' \ r ‘r r r F v r 1.0Hz 10H: lOOHz 1.0KHZ IOKHZ IOOKHZ 1.0HHZ lOHHz 100MHz a -VdB(77) o VdB(73) Frequency Figure 7.5.3.4: Graph of Beta Network Analysis with VBIAS = 6.133 volts 75 i (3 Cl. -200d4 (520.0K.'103.3) -300d4 SEL>> -4OGd O Vp(73l+Vp(77l 100‘ 50~ r r r r T ‘T f 1.0Hz 10H: lOOHz 1.0KHZ IOKHZ IOOKHZ 1.0MHZ IOHHz 100MHz a -VdB(77) o VdBt73) Frequency Figure 7.5.3.5: Graph of Beta Network Analysis with VBIAS = -6.232 volts 7.5.4 Verifying with Lab Data The Addition of RADD and C ADD were tested in the lab. The circuit in the lab produced exactly the same results that were achieved when the bypass capacitor was added (See Figure 5.3.1.5). Therefore, it can be concluded that one way to help eliminate stability problems for this Class G amplifier design is to include RADD and CADD. 76 Chapter 8: Efficiency and Total Harmonic Distortion 8.1 Introduction The reason for the Class G amplifier is to have a power amplifier that will be more efficient than the Class B amplifier without sacrificing sound quality. With a more efficient circuit, the overall circuit temperature would be cooler and would use smaller heat sinks. More importantly, though, if the circuit were using portable power supplies (batteries), the life of the battery would be extended. This chapter will examine the efficiency of the amplifier and measure the Total Harmonic Distortion using PSpice. 8.2 PSpice Simulations The Class G amplifier circuit was tested using a voltage ratio for V1 to V2 of 1:3. This is suggested to be the best result for music production [4]. In this case, V1 equals 6 volts and V2 equals 18 volts. The efficiency of the Class G amplifier can be measured by dividing the average power of the load by the average power of the power supplies. AVG(VRL * IRL) Efficiency = AVG(V1 * 1V1) ‘1' AVG(V11 * Ivy) '1' AVG(V2 * Ivz ) + AVG(V21 * IVZ') To compare the efficiency of the Class G amplifier to the Class B amplifier, a Class B amplifier circuit was modeled shown in Figure 8.2.1. This Class B circuit uses an Op-Mp and an additional Class B stage because the Op—Amp cannot provide enough current for the voltage swing required. Also note that the Class B amplifier can have a 77 voltage swing that is closer to the power rails than the Class G amplifier. However, only the full voltage range of the Class G amplifier was used to test the efficiency of the Class B design. The power supplies were at +/- 18 volts but the output voltage range was from 0 to +/- 13.7 volts. The efficiency of the Class B amplifier will continue to'increase a little more as the input voltage increases before clipping begins. The graph of the efficiency is shown in Figure 8.2.2. This graph does show that the efficiency of the Class G amplifier is better than the Class B amplifier when the signal is smaller than the lower power supplies. The efficiency equations for the Class B amplifier are: AVG(VROUT "‘ IROUT) Efficiency = * .. AVG(VHIGH IV(HIGH)) + AVG(VLow 1V(LOW)) VHIGH VHIGH VHIGH LF411 Q2N3904 TIP31 VIN * ' a ° Q2N3 90 6 TI p32 ROUT -+- VLOW VLow VLOW T Figure 8.2.1: Schematic of Class B - efficiency testing 78 63:: tIh-I ZIII~ .‘ r r r I r r I 2 I 6 I 1. 12 1b a Vat8((008(0(19)l1(lL)))I(IUG(0(2)¢-1(02))000¢(0(5)O-I(02P))0lflc(0(3)O-I(U1))¢IUG(0(§)O-I(U1P))),3l) o Vat8((OUG(0(20§)01(lout)))/(IUG(U(2OI)I-1(UNICM))OOUG(U(ZI1)I-l(0L00))).al) 00L Figure 8.2.2: Graph of Class G verses Class B efficiency The graph of the efficiency for the Class G amplifier is comparable to the articles referenced in this thesis. 8.3 Lab Data The Class G amplifier and the Class B amplifier were built in the lab. The Class G amplifier used +/- 15 volt and +/- 5 volt power supplies. The Class B amplifier used +/- 15 volt power supplies. Both amplifiers were tested using a lkHz input sine wave. The magnitude of the input was incrementally increased from 0 until the output began to clip. The efficiency of the Class B amplifier for different voltage output levels is shown in Table 8.3.1. This table shows the output voltage level and the current fi'om each of the power supplies. The table also shows a calculation for the average power out, the average power in, and the average efficiency. Table 8.3.2 shows the results of testing the Class G amplifier The plot of the efficiencies for both amplifiers is shown in Figure 79 8.3.1. Notice that the Class G amplifier does show and improved efficiency over the Class B amplifier. This result is similar to the efficiency measure by PSpice. Voltage Measured Average (pzakoto-pgak) Current from Power Average Power (W) Power ”Bid Q SUPP'Y (MA) Efficiency +15 Volt 1 -15 Volt Power Out I Power In 0.43 8.5 9.4 0.0023 0.2685 0.86% 0.799 13.2 14 0.0080 0.4080 1.96% 1.186 25 20 0.0176 0.6750 2.60% 1.606 32 29 0.0322 0.9150 3.52% 1.981 37 35 0.0491 1.0800 4.54% 2.378 40 40 0.0707 1 .2000 5.89% 2.755 49 47 0.0949 1 .4400 6.59% 3.147 57 50 0.1238 1.6050 7.71% 3.533 61 60 0.1560 1.8150 8.60% 3.928 68 68 0.1929 2.0400 9.45% 4.33 78 72 0.2344 2.2500 10.42% 4.7 82 83 0.2761 2.4750 11.16% 5.16 85 89 0.3328 2.6100 12.75% 5.54 59 93 0.3836 2.2800 16.83% 5.9 98 96 0.4351 2.9100 14.95% 6.29 100 100 0.4946 3.0000 16.49% 6.65 110 110 0.5528 3.3000 16.75% 7.07 115 115 0.6248 3.4500 18.11% 7.43 119 120 0.6901 3.5850 19.25% 7.82 120 125 0.7644 3.6750 20.80% 8.44 130 130 0.8904 3.9000 22.83% 8.75 140 140 0.9570 4.2000 22.79% 9.12 140 140 1.0397 4.2000 24.75% 9.62 150 150 1.1568 4.5000 25.71% 10.05 160 160 1.2625 4.8000 26.30% 10.36 160 160 1.3416 4.8000 27.95% 10.73 170 170 1.4392 5.1000 28.22% 1 1.25 180 180 1 .5820 5.4000 29.30% 1 1.65 180 180 1 .6965 5.4000 31 .42% 11.97 190 190 1.7910 5.7000 31.42% 12.35 200 200 1.9065 6.0000 31.78% 12.79 200 200 2.0448 6.0000 34.08% 13.17 210 210 2.1681 6.3000 34.41% 13.49 210 210 2.2748 6.3000 36.11% 14.42 230 230 2.5992 6.9000 37.67% 15.18 240 240 2.8804 7.2000 40.01% 16.15 250 250 3.2603 7.5000 43.47% 16.8 270 270 3.5280 8.1000 43.56% 17.68 280 280 3.9073 8.4000 46.52% 18.43 290 290 4.2458 8.7000 48.80% 19.23 300 300 4.6224 9.0000 51.36% 19.83 310 310 4.9154 9.3000 52.85% 20.83 330 330 5.4236 9.9000 54.78% 21.61 330 340 5.8374 10.0500 58.08% 21.93 340 350 6.0116 10.3500 58.08% Table 8.3.1: Measure Class B efficiency 80 (peg/fligpeeak) Measured Average Current from Power Across 100 Suppl 1 (mA) Average Power (W) Power Load +5 Volt -5 Volt +15 Volt ~15 Volt Power Out Power In Efficiency 0.602 8 7 4.3 4.3 0.0045 0.1690 2.68% 0.819 10 10 4.32 4.32 0.0084 0.1796 4.67% 0.968 15 15 4.36 4.36 0.0117 0.2058 5.69% 1.157 19 19 4.4 4.4 ‘ 0.0167 0.2270 7.37% 1 .354 20 20 4.43 4.43 0.0229 0.2329 9.84% 1.544 21 23 4.5 4.5 0.0298 0.2400 12.41% 1.68 25 25 4.54 4.54 0.0353 0.2612 13.50% 1.871 27 27 4.6 4.6 0.0438 0.2730 16.03% 2.062 30 30 4.71 4.71 0.0531 0.2914 18.24% 2.262 32 33 4.72 4.72 0.0640 0.3017 21.20% 2.468 38 38 4.76 4.76 0.0761 0.3329 22.87% 2.629 39 39 4.8 4.8 0.0864 0.3391 25.48% 2.825 40 40 4.85 4.85 0.0998 0.3456 28.87% 3.028 42 42 4.9 4.9 0.1146 0.3571 32.10% 3.171 43 43 4.96 4.96 0.1257 0.3639 34.54% 3.333 50 50 5 5 0.1389 0.4001 34.71% 3.581 52 53 5.03 5.03 0.1603 0.4110 39.00% 3.722 56 56 5.08 5.08 0.1732 0.4325 40.04% 4.01 59 59 5.12 5.12 0.2010 0.4487 44.80% 4.19 60 60 5.18 5.18 0.2195 0.4555 48.18% 4.34 62 62 5.21 5.21 0.2354 0.4664 50.48% 4.52 66 66 5.25 5.25 0.2554 0.4876 52.37% 4.71 70 71 5.38 5.38 0.2773 0.5115 54.21% 4.86 75 75 5.4 5.4 0.2952 0.5371 54.97% 5.01 78 78 5.45 5.45 0.3138 0.5536 56.67% 5.28 80 80 5.5 5.5 0.3485 0.5651 61.66% 5.43 82 82 5.56 5.56 0.3686 0.5769 63.88% 5.58 83 83 5.64 5.64 0.3892 0.5844 66.60% 5.75 88 88 5.71 5.71 0.4133 0.6115 67.59% 5.9 91 91 5.79 5.79 0.4351 0.6289 69.19% 6.26 98 99 5.9 5.9 0.4898 0.6672 73.42% 6.67 100 100 5.9 5.9 0.5561 0.6772 82.12% 6.98 103 104 6.22 6.22 0.6090 0.7018 86.78% 7.45 1 10 1 12 6.68 6.68 0.6938 0.7506 92.43% 7.74 120 119 7.4 7.4 0.7488 0.8222 91.08% 8.17 117 117 22 22 0.8344 1.2452 67.01% 8.34 105 105 30 30 0.8694 1.4252 61.01% 8.53 98 100 35 40 0.9095 1.6152 56.31% 8.65 90 91 40 50 0.9353 1 .8002 51.96% 8.88 80 82 50 60 0.9857 2.0501 48.08% 9.19 78 79 60 70 1.0557 2.3401 45.1 1% 9.55 69 70 80 80 1 .1400 2.7451 41 .53% 9.9 60 60 80 90 1 .2251 2.8501 42.99% 10.33 60 60 100 100 1 .3339 3.3001 40.42% 10.65 58 59 100 110 1.4178 3.4401 41.21% 11.03 52 50 110 120 1.5208 3.7101 40.99% 1 1.34 49 50 120 130 1.6074 3.9951 40.24% 1 1.75 45 45 130 140 1 .7258 4.2751 40.37% 12.08 42 42 140 150 1.8241 4.5601 40.00% 12.5 41 41 140 150 1.9531 4.5551 42.88% 81 12.84 40 40 150 160 2.0608 4.8501 42.49% 13.27 40 40 160 170 2.2012 5.1501 42.74% 13.55 39 39 1 70 180 2.2950 5.4451 42.1 5% 13.96 39 39 170 190 2.4360 5.5951 43.54% 14.25 39 39 180 190 2.5383 5.7451 44.18% 14.64 39 39 190 200 2.6791 6.0451 44.32% 14.97 38 38 190 200 2.8013 6.0401 46.38% 15.34 38 38 210 210 2.9414 6.4901 45.32% 15.85 38 38 220 220 3.1403 6.7901 46.25% 16.21 32 32 230 230 3.2846 7.0601 46.52% 16.6 31 31 230 230 3.4445 7.0551 48.82% 16.97 30 30 240 240 3.5998 7.3501 48.98% 17.23 30 30 250 250 3.7109 7.6501 48.51% 17.65 28 28 250 250 3.8940 7.6401 50.97% 17.88 28 28 260 260 3.9962 7.9401 50.33% 18.34 25 25 260 260 4.2044 7.9250 53.05% 18.69 25 25 270 270 4.3665 8.2250 53.09% 19.09 24 24 280 280 4.5554 8.5200 53.47% 19.28 23 23 280 280 4.6465 8.5150 54.57% 19.54 23 23 290 290 4.7726 8.8150 54.14% 20.28 22 22 300 300 5.1410 9.1 100 56.43% 20.59 22 22 310 310 5.2994 9.4100 56.32% 20.92 20 20 310 310 5.4706 9.4000 58.20% Table 8.3.2: Measuring Class G efficiency Class B & Class G Efficiency 100% ' A + Class B 0 3° 4’ _._ Class G > 2 60% .2 - J/ O E 40% m . 20% 0% ‘ 1 f 1 O 5 10 15 20 25 Output Voltage (V) Figure 8.3.1: Graph of Class B and Class G efficiency - lab data 82 8.4 Total Harmonic Distortion The Total Harmonic distortion of the final circuit, including the added resistors and capacitors, was analyzed using a LF411 for the operational amplifier. This test circuit, however, did not include the inductors of the power lines. The measurement was taken at lkHz, 10 kHz, and 20 kHz at maximum output voltage (without clipping). This test used a 10 Q resistor for the load. Using PSpice to analyze the first 20 harmonics, the THD at 1 kHz, 10 kHz, and 20 kHz was 0.0184%, 0.174%, and 0.354% respectfully. It is generally believed in hobbyist magazines that a total harmonic distortion of less than 1% is considered inaudible. The data can be found in Appendix F. 8.5 Efficiency for Audio The Class G amplifier has been shown to be more efficient than the Class B amplifier when the input signals are relatively small compared to the power supplies. This can be beneficial for audio circuits where the input is spending more time at lower voltages than it is at high voltages. Studies show that under music listening conditions, an audio amplifier is called upon to deliver full or nearly full output for only a small fraction of the time it is operating [8]. One way to analyze this is by using the crest factor (the ratio of peak level to rms level) [7] [8]. Symphonic music, for example, has a high crest factor compared to popular music because the volume of symphonic music is always changing from long periods of sofi to long periods of loud. Speech has a crest factor that is between popular music and symphonic music. With speech, though, people rarely speak at full volume. This means that a Class G amplifier would work for audio devices involving speech, like cell phones and walkie-talkies. Since the majority of the 83 time the volume would be medium to low, the efficiency of the Class G amplifier would become even better because the circuit would be spending more time in the area where the circuit is more efficient. 84 9 Design Improvements 9.1 Introduction This chapter offers some improvements to the basic Class G amplifier design to increase efficiency and lower the total harmonic distortion. By analyzing the basic design of the Class G amplifier and by using bipolar-junction transistors (BJTs) to get the general equations that describe the basic behavior of the Class G amplifier, more advanced designs could be created. Many Class G amplifier designs may have been overlooked in the past due to the stability problem. By using the Beta Network Analysis method describe in this thesis, it is possible to identify the source of some stability problems. 9.2 Using Better Op-Amp to Lower THD Using an Op-Amp with high bandwidth and high slew-rate such as the LF411 compared to the UA741 Op-Amp will lower the THD. An Op-Amp with higher bandwidth can switch faster than an Op-Amp with lower bandwidth. The Op-Amp with more bandwidth will reduce the distortion caused by crossover. An Op-Amp that uses less power will help to improve the efficiency of the circuit for small input signals. This would‘be more useful in designs that require a Class G amplifier with a low output wattage, such as building the entire Class G amplifier on an integrated circuit chip. 85 9.3 Using More Biasing to Lower THD Another improvement for lowering the THD would be to not require the Op-Amp output voltage to jump as much due to crossover. This could be done by adding more biasing (VBIASI and VBIAS2) to the Class-G output stage shown in Figure 9.3.1. This design is similar to that of the Class AB amplifier. Now, the Op-Amp would only have 10 COITCCI a small amount 0f CI'OSSOVCI'. —————W Rf v2 v2 v1 02 01 RIN V2 1 + 01 L“ 11 VBlASl VIN o + VBIASZ , RL __ 01 —T- _".- _ DZ V2' +4 02' 37 V2' V2' Figure 9.3.1: Schematic model for improved Class G amplifier A possible circuit that would implement the model shown in Figure 9.3.1 is shown in Figure 9.3.2. This circuit uses diodes to get the proper biasing voltage levels for VBMSI and VBIASZ and uses Op-Amps to provide the necessary current. The THD was tested at 1 kHz, 10 kHz, and 20 kHz using PSpice to analyze the first 20 harmonics. The measurement was taken at the maximum output voltage without clipping. The THD at 1 kHz, 10 kHz, and 20 kHz was 0.0147%, 0.134%, and 0.279% respectively. Figure 9.3.3 86 shows the output of this circuit at maximum voltage (13.7 volts) at 20 kHz with very small amounts of visible distortion. The efficiency of this circuit is shown in Figure 9.3.4. This new circuit would need more components and the efficiency would be less for a trade off of lower THD. 1k V2 —Ia .. j; v. 01 1k 01 VIN E10 1 -+- 0 oz =1: 1 (22' 13 v1 <7 v2' Figure 9.3.2: Schematic of Class G with more biasing 20V - 10V- 0V -10V- ‘20V 1 1— 1 I 0: ZOus 40us 60us 80us 100us a V(19) Tine Figure 9.3.3: Graph of Vour (MAX) at 20 kHz 87 GOCw 400m4 200m‘ G , r 45* 1 r T 0 0.2 0.4 0.6 0.8 1.0 1.2 D YatX((AVG(V(191‘I(RL))l/(AVGIVI2)'-I(V2))tAVG(V(Sl'-I(VZP)l+AVGlV(3)'-I(V1)l+AVG(V(4)‘-I(VIP))).3B) O YatXl(AVG(V(204)'IlRoutlll/lAVGlV1200)'-I(VHIGH)l+AVG(V(201)'-I(VLOH))),3m) VAL Figure 9.3.4: Efficiency of Class G with more biasing and Class B amplifier 88 Chapter 10: Future Study 10.1 Introduction There may be a way to identify stability problems with Op-Amp circuits using a closed-loop approach and PSpice. By having a closed-loop approach, circuits could be quickly analyzed for verification of stability problems. This chapter will use common Op-Amp circuits such as inverting and non-inverting amplifiers to show how this identification technique may be applied to circuits with and without stability problems. 10.2 Identifying Stability Problems using Closed-Loop Approach Here is a proposed technique to find how stable a closed-loop Op-Amp circuit is without needing to replace the Op-Amp with a model and analyzing the beta network. @ , E vs 9 9’9?sz Figure 10.2.1: Schematic of example circuit A non-inverting amplifier example circuit was used to develop the steps necessary to find the stability of the circuit using different gains shown in Figure 10.2. 1. The gain of this circuit is [1+ g). The Adm of the Op-Amp was chosen to be: 89 27:00) , 27r(10k) , 27r(100k) 100k * . s + 27r(10) s + 27r(10k) s + 211(100k) 10.2.1 Transient Response First, the circuit was analyzed by stepping the voltage of VS from 0 to 0.5 volts and observing the transient response. The gains tested were 9, 10, 11, and 12. Resistor R1 was 1k!) and resistor R2 was changed to achieve the‘desired gains (8kQ, 9kQ, IOkQ, and lle). Figure 10.2.1.1 shows the PSpice files used to simulate this circuit. Figure 10.2.1.2-A through Figure 10.2.1.2-D show the output of the circuit at node 2. When the gain (of the circuit was 9 and 10, the circuit began to oscillate indicating that the circuit is unstable. And, when the gain of the circuit was 11 and 12, the circuit had some ringing in the output but was being dampened indicating that this circuit is marginally stable. 90 Stability Testing vs 1 0 PULSE (0 .5 100) R1 3 0 1K R2 2 3 8K' x1 1 3 2 OPAMP .SUBCKT OPAMP 1 2 3 RIN 1 2 IOOMEG EADM 3 0 LAPLACE {V(l,2)} {(100K)*(6.28*10)*(6.28*10K)*(6.28*100K)/ + ((S+6.28*10)*(S+6.28*10K)*(S+6.28*100K))} .ENDS OPAMP .TRAN .010 4000 0 .010 (:> .PROBE . (:) .END - VS Stability Testing VS 1 O PULSE (O .5 IOU) R1 3 0 1K __ R2239K " R1 IVA/94+ R2 X1 1 3 2 OPAMP .SUBCKT OPAMP l 2 3 RIN l 2 lOOMEG EADM 3 0 LAPLACE {V(1,2)} {(100K)*(6.28*10)*(6.28*10K)*(6.28*100K)/ + ((S+6.28*10)*(S+6.28*1OK)*(S+6.28*100K))} .ENDS OPAMP .TRAN .010 4000 O .010 .PROBE .END Stability Testing VS 1 0 PULSE (O .5 100) R1 3 0 1K R2 2 3 10K X1 1 3 2 OPAMP .SUBCKT OPAMP 1 2 3 RIN l 2 lOOMEG EADM 3 O LAPLACE {V(1,2)} {(100K)*(6.28*10)*(6.28*10K)*(6.28*100K)/ + ((S+6.28*10)*(S+6.28*10K)*(S+6.28*100K))} .ENDS OPAMP .TRAN .010 4000 O .010 .PROBE .END Stability Testing VS 1 0 PULSE (0 .5 IOU) R1 3 0 1K R2 2 3 11K X1 1 3 2 OPAMP .SUBCKT OPAMP 1 2 3 RIN 1 2 IOOMEG EADM 3 0 LAPLACE {V(1,2)} {(100K)*(6.28*10)*(6.28*10K)*(6.28*100K)/ + ((S+6.28*10)*(S+6.28*10K)*(S+6.28*100K))} .ENDS OPAMP .TRAN .010 4000 0 .010 .PROBE .END Figure 10.2.1.1: PSpice files with schematic 91 H 8k 1+ E) = 9 NOT STABLE r 500: 1 10003 I 1500: r . ZOOua 25005 1 Boone 350us 0: 4000: o V(2) Tine Figure 10.2.1.2-A i = [I + ?EJ=10 NOT STABLE [3 1k 4V4 Os 5003 10005 15005 20005 25003 300u: 35003 4000: u V12) Figure 10.2.1.2-B 92 l=[l+%)=ll STABLE B 1k 12V 8V- 4V4 OV- ‘4V 1 r - 1 r v T I 03 500: 1000: 15003 2000: 2500s 3000: 3500: 40003 a V12) Tine Figure 10.2.1.2-C 1 11k - = 1+— =12 STABLE 0 1k 121: UV- NJ 0V< ”"0: 5003 10003 1500:. 2001.13 2500: 30003 3500: 4000: a V(2) Tile Figure 10.2.1.2-D Figure 10.2.1.2: PSpice output graphs 93 10.2.2 AC Frequency Response The AC analysis was performed on the same circuit. Instead of stepping the voltage of VS, like in the transient analysis, the frequency of voltage V8 with amplitude of 1 was swept from 100mHz to 10MHz. Again, the gain of the circuit was changed to be 9, 10, 11, and 12. Figure 10.2.2.1 shows the PSpice file used for simulation. The phase shift due to the Op-Amp can be seen by plotting the difference between the phase of V2 and V(1,3) shown in Figure 10.2.2.2. The phase matches the predicted open-loop phase shift of the Op-Amp. Figure 10.2.2.2 also shows the gain of the Op-Amp by V(2) V(l 3)) and the gain at node 3. Upon closer examination of the graph measuring dBL (Figure 10.2.2.3), it is observed that when the gain of node 3 crosses the gain of the Op- Amp with a negative slope, the phase angle will tell the phase margin of the circuit. The Phase margin is definedcas PM = 180° - léAdm " BI. Stability Testing VSlOACl >__...__® R1 3 0 1K . VS 9 R2 2 3 {VAL} <:> o————J\A¢u——_ X1 1 3 2 OPAMP .SUBCKT OPAMP 1 2 3 R2 RIN l 2 lOOMEG - R1 EADM 3 0 LAPLACE {V(1,2)} + {(100K)*(6.28*10)*(6.28*10K)*(6.28*100K)/ + ((S+6.28*10)*(S+6.28*10K)*(S+6.28*100K))} .ENDS OPAMP .PARAM VAL = 1 .STEP PARAM VAL LIST 8K 9K 10K 11K .AC DEC 1000 .l IOMEG .PROBE .END Figure 10.2.2.1: PSpice file with schematic 94 ~06 -100d' -200d< SEL>> -300: o o v a VplZl-Vpl1,3) -209 v I r r f ,7 , 1003flz 1.0K: 10H: 100K: 1.0KHz 10KB: 100KB: 1.0HH1 lOHHz o o v n dB(V(2)/V(1,3)) o + x A dB(V(1,3)) Frequency Figure 10.2.2.2: Graph of Beta Network Analysis -160d (28.4619K,-l76.52521 (30.2451K,-178.53021 (31.9892K,-180.3784l (33.8661K,-182.2582) ~1703+ -180d4 -1996 D o v a Vpl2l-Vpll.3l 54 (30.2451K,19.9359) 40- (31.9892K,18.9612) (28.4619K,20.9787) (33.8661K,17.9659) 204 \ SEL>> 22.3KB: 30.0KB: 41.1KB: O e V a dBlVlZl/V11.3ll o 4 x A dB(V(1.3)) Frequency Figure 10.2.2.3: Close up View of Figure 10.2.2.2 95 The phase margin, according to the graph (Figure 10.2.2.3) of the different gains, are as follows: Gain = 9 => PM =180° -l—182.26° -_- —2.26° Gain =10 => PM =180° - —180.37° = -0.37° Gain =11: PM =180° - —178.53° =1.47° Gain = 12 => PM =180° - -l76.53° .-. 3.47° When the phase margin is between 0° and 45°, the circuit is said to be marginally stable. When the phase margin is less than 0°, the circuit is said to be unstable and will oscillate. The phase margin, when the gain of the beta network is 9 and 10, shows that the circuit will be unstable. The phase margin, when the gain is 11 and 12 shows that the circuit will be stable but will have ringing in the output. The following would be a procedure for analyzing a closed-loop Op-Amp circuit and finding the phase margin: Step 1. Plot the difference in phase angle between the phase of the output and the phase across the input terminals of the Op-Amp. Step 2. Plot the gain of the Op-Amp by finding the difference between the gain of the output and the gain of the voltage across the input terminals of the Op-Amp. Step 3. Plot the gain of the voltage across the input terminals of the Op-Amp. Step 4. Check to see if the gain of the voltage across the Op-Amp crosses the gain of the Op-Amp. 96 A. If it does, check to see if the gain of the input terminals crosses the gain with a negative SIOpe. i. If it does, use the phase plot at this frequency to measure the PM. ii. If it does not, find where the gain of the input terminals is maximum. Use the phase plot at this frequency to measure the PM. (See Figure 10.2.2.4) B. If it does not, find where the gain of the input terminals is at it's maximum value. Use the phase plot at this frequency to measure the PM. (See Figure 10.2.2.5) -0d -100d'1 (87.9023K,-214.8371) -ZOOd‘ -300d D Vp(2)-Vp(l.3l 100 (87.9023K.4.59654) -100 SEL>> ”ZOO r r r r v v r 100mHz 1.0Hz 1082 100K: 1.0KHz 10KB: 100KB: 1.0HHz loan: 0 dB(V(2)/Vll.3)) o dBlV(1.3)) Frequency Figure 10.2.2.4: Graph of Beta Network Analysis, Gain = 1 97 (11.1944K.‘144.S792) -100d‘ '200d‘ -300d O Vp(21-Vp(1.3) 100 0" //l (11.1944K,4.133;::7\7“\‘\‘\-\\\\“\‘\\\\‘\ ‘100‘ SEL>> ‘200 r I r r r f r lOOmHz 1.0K: 10H: lOOHz 1.0KH2 10KB: 100KB: 1.0Hflz 10MB: 0 dBlV121/V11.3)l o dBlVll.3l) Frequency Figure 10.2.2.5: Graph of Beta Network Analysis, Gain = 100 10.2.3 Another Test Using an Inverting Amplifier Design The same Op-Amp is used in this circuit but now the layout is an inverting amplifier (Figure 10.2.3.1). The results of the inverting amplifier slightly differ from the non-inverting amplifier circuit. Figure 10.2.3.2 shows the transient response of the circuit with a gain of 8, 9, 10, and 11. A gain of 10 for the non- inverting circuit was unstable, but a gain of 10 for the inverting circuit was stable. Figure 10.2.3.3 shows the phase and gain of the Op-Amp along with the plot of gain of V(3). Figure 10.2.3.4 shows a closer view of Figure 10.2.3.3 with the measurements to find the phase margin. Figure 10.2.3.5 and Figure 10.2.3.6 show more examples of measuring the PM when the circuit has a gain of 100 and a gain of 1, respectively. The PM for the different gains can be seen below. 98 Gain =8 => PM = -1.97° Gain =9: PM =—o.14° Gain =10: PM =1.69° Gain =11 :>-PM = 3.87° VS 1 0 AC 1 ' R1 1 3 1K ‘ R2 3 2 {VAL} vs a __L— X1 0 3 2 OPAMP ? .SUBCKT OPAMP l 2 3 RIN 1 2 lOOMEG —— EADM 3 0 LAPLACE {V(1,2)} + {(100K)*(6.28*10)*(6.28*10K)*(6.28*100K)/ + ((S+6.28*10)*(S+6.28*10K)*(S+6.28*100K))} .ENDS OPAMP .PARAM VAL = 1 .STEP PARAM VAL LIST 8K 9K 10K 11K .AC DEC 1000 .1 lOMEG .PROBE .END ’ Stability Testing CD R1 I >__‘ + Figure 10.2.3.1: PSpice file with schematic using inverting amplifier 99 l = (E15) = 8 NOT STABLE a 1k Figure 10.2.3.2-B 100 10V- 0V- ~10V-1 ‘ 0: so'us loans 156m 205m 251m: Joan: 35311: Aoous u V(2) Time Figure 10.2.3.2-A 1 9k — = — =9 NOT STABLE B 1k 0V- 5V1 ‘A‘ V 1' I Y I r l 05 SOus 100us ISOus ZOOu: 250us JOOus 350us “Wu: 0 V(2) -1- {1913] =10 STABLE B 1k 0V4 -5v« 'lov r v I r I 1 I 03 SOus 100us ISOus 200us 250115 300us JSOus 400us a V(2) Tine Figure 10.2.3.2-C 1 11k —= — =11 STABLE {3 1k 4V 0V-‘ '4V" -av. -12.; I T F I I T v 05 SOus 100us lSOus ZOOus ZSOus 300us 350m 400us a V(2) T130 Figure 10.2.3.2-D Figure 10.2.3.2: PSpice output graphs 101 1806 93d‘ Odd SEL>> -IOCd a e v a Vp(2)-Vp(3l 10c -100~ ‘200 1 I I I I I r IOOmHz 1.0K: 10H: 100Hz 1.0KHz 10KB: 100KB: 1.0KHz lOHHz a o v A dB(V(2)/V(3)) o + x A dB(V(3)/V(1)) Frequency Figure 10.2.3.3: Graph of Beta Network Analysis (28.1204K.3.873$4) (30.0466K,1.68691) (31.7609K,-142.2495n) (33.5738K.-1.97224) 0dq ~10: O 0 V A Vp(2)-Vp(3) 52. I) (30.0466K.20.0502) 40.0‘ (28.1204K,21.1341) (31.7609K.19.1071) (33.5738K.18.1181) 20.04 SEL>> 4.3 v “"“ 23.3KB: 30.0KB: 41.¢Kflz a o v e dB(V(2)/V(3)) o o x A dB(V(3)/V(1)) Frequency Figure 10.2.3.4: Close up view of Figure 10.2.3.3 102 180d (11.1686K,35.5010) 93d‘ Oda -93d4 a me-me 100 0‘ “‘_‘ 1// (11.1686K,4.01722) -100‘ SEL>> ’200 I I I I I I I IOOmHz 1.0Hz 10Hz 100Hz 1.0KHz IOKHz IOOKHz 1.0HHz IOHHz D dB(V(2)/V(3)) o dB(V(3)/V(1)) Frequency Figure 10.2.3.5: Graph of Beta Network Analysis, Gain = 100 180d 93d< (87.9023K,-34.8371) Od‘ -93d< D Vpl2l-th3) 200 /—/l (87.9023K,-115.403$) SEL>> ”400 I I I T I I IOOmHz 1.0Hz 10H: lOOHz 1.0KHz 10KB: IOOKHZ 1.0HH2 lOHHz D dB(V(2)/V(3)) o dB(V(3)/V(1)) Frequency Figure 10.2.3.6: Graph of Beta Network Analysis, Gain = 1 103 Chapter 11: Conclusion This thesis has shown the basic design of a Class G amplifier, using bipolar junction transistors, with the help of circuit modeling and equations to get the desired performance with the fewest number of parts. Using this design, an operational amplifier with feedback was used to lower the Total Harmonic Distortion. Data collected from the lab of the Class G amplifier with the Op-Amp showed an output that was only partially unstable. This stability problem caused concern in the performance of the Class G amplifier and needed to be solved before further analyzing this amplifier. Before any methods could be used to identify the source of the problem, the simulated circuit model had to be revised to match the data collected in the lab. This was done by making sure the Op- Amp was fully modeled and by including wiring inductances that may be coming fiom the power supply wires. Once the Class G amplifier was properly modeled, the cause of the stability problem was identified using a variation on the Beta Network Analysis Method. This involved using a small signal input and changing the input biasing level because the output was only unstable at certain levels. With the help of Sspice, a mathematically proven solution to the problem was found and experimentally confirmed to work. While studying the stability problem of the Class G amplifier, a proposed technique for identifying if a circuit would be stable or not using a closed-loop analysis was given. This technique needs to be further examined but it would allow Op-Amp circuits to be examined without remodeling the circuit, which is used for the Beta Network Analysis Method. 104 The Class G amplifier was shown to be a more efficient circuit than the Class B amplifier for small input signals. The trade off for more efficiency is the cost and space of more circuit components. The Total Harmonic Distortion was also shown to be at reasonable levels for audio applications. The Class G amplifier could be used in portable devices with a specially developed battery, which would provide the necessary voltages to help increase battery life. This thesis also proposes more study of the Class G amplifier to gain better performance. Using bipolar transistors for analysis lays down the “ground work” for more designs such as Class G amplifiers using FETs, MOSFETs, and combinations thereof. More work also needs to be done using more than four power supplies and identifying how the Class G amplifier can be optimized for different applications, such as amplifying speech versus amplifying symphonic music. 105 Appendix A Sspice Sspice - Circuit Analyzer and Approximator Sspice (Symbolic Simulation Program with Integrated Circuit Emphasis) ‘ Developed by Vivek Joshi, Anupam Srivastava, James MacKay, Sin-Min Chang, and Dr. Gregory Wierzba with support from Michigan State University. Evaluation and Approximation "Besides analyzing circuits, Sspice can also optionally evaluate its results and even make some global approximations. In sorting by powers of the Laplace variable 5 many terms may be added or subtracted. Given numeric values for the coefficients for each power of s, Sspice finds the largest magnitude term. Using a user specified threshold magnitude, Sspice multiplies the largest magnitude term by the user specified threshold magnitude and then discards any terms for that power of s which are below this value." Copyright 1991 by Michigan State University Board of Trustees 106 Appendix B Beta Network Analysis Method An operational amplifier circuit can be modeled as a basic feedback topology shown in Figure B-l. X,“ + X0 __p f } f +— Figure B—l: Basic negative-feedback topology The overall gain of the system including the effects of feedback is written as MS) Af(s)=1+A(s)-f Stable amplifier operation requires the magnitude of the loop gain, |A(s)f|, to be less than unity when its phase angle approaches 180°. The magnitude of the loop gain (in decibels) can be expressed as the difference of the magnitude of the open-loop gain and the -‘-| f The loop gain is the difference between the open-loop gain and the inverse of the magnitude of the inverse of the feedback ratio. 20 - log|A(s) - f | = 20 . log|A(s)| — 2O - log feedback ratio [3]. 107 The gain for an inverting Op-Amp is: ___VOUT 9.132.: 1 VIN R1 1+__1_.l ADM B Testing the stability of the Op-Amp circuit with the following conditions: W ADM-Ac o s+wo 1_ Bo (32+w22) B 82+—?‘— s+w22 O 100 50‘ ~20 lomflz lOOmHz 1.0Hl IOHZ 100Hz 1.0KHZ 10KB: 100KB: 0 -VdB(3) o VdBtZ) Frequency Figure B-Z: Example graph of Adm and 1/ B Figure B-2 shows the graph of the gain of Adm and 1/ B. Notice that the gain of US crosses the gain of the Op-Amp more than once. 108 Substituting ADM and B into the gives the following equations: 1 1 . Bo.(s2+w,2) w w Ao-——°—— 52+——Z-s+wz2 s+wo Q0 R2 1 . _ R1 (s+wo).Bo-(s2+w22) 1+ w Ao -wo {32 +—z--s+w22] 0 Gmn=-——- R1 2 W2 2 Ao-wo-[s +—-s+wz] 0 R2 R1 2 W 2 2 2 Ao-wo-(s +—7‘—-s+wz ]+(s+wo)-Bo-(s +wz) O 2 W2 2 A -w -s +—-s+w R2 0 0[ Z] 0 R1 A. s3 +wo (Afljsz +w22-——&—+1-s+wo-wzza[é+1) B B-Q-wz B The next steps will show that equation can take on the following form: 2 wz 2 Ao-wo-[s +—-s+wz] 0 R1 (s+X)-(s2 -Y-s+w22) 2 W2 2 Ao-wo-[s +—-s+wz] 0 R2 R1 s3 +[x—Y]-s.2 +(wz2 —X-Y)-s+X-w22 109 Solving for X and Y: Let X equal the following: X = wo [é- +1) B Now solve for the coefficient of s'. wzz -X-Y=w22- $351.44 B'Q-wz What happens as Q goes to infinity? lim Y=—B———=O Qaw (—+l)-oo A Now solve and verify the coefficient of $2 X-Y=wo (lg-+1] Y=O The revised equation for the gain of the circuit is: 2 2 Do not cancel (32+wz2) from the = -53. . A0 ' w° '(5 + wz ) numerator and the denominator .Rl S+w0. 5+1 ~[52 +w22] because they will notbeequal. This is B only an approxrmation to solve for the R2 Ao'wo'(52+wzz) -n‘[..w.-(%+IJH(S+ ‘szlls'mfl 110 The above equation indicates that as the Q of the circuit gets larger and larger, the transfer function shows that the circuit will be unstable and oscillate at the frequency l- W22 Here is an example: Given: 21t-O.l A =100k-—— ”M s + 2n - 0.1 _1__10. 52+(27t-3Ok)2 B 52+W-s+(2n-3Ok)2 ' 1E6 R1 = 1k R2 =1k Using Matlab to solve for the roots of the denominator, the following Matlab code will show the gain symbolically. syms s; syms wl w2 A B Q; R2 = 1e3; R1 = 1e3; ADM = (A*wl/(s+wl)); disp('Adm = ') pretty(ADM) Beta = ((s“2+w2/Q*s+w2‘2) / (B*(s“2+w2“2))); disp('l/Beta = ') pretty(1/Beta) $01 = ~R2/Rl * 1/( 1 + l/ADM * l/Beta ); sol = simplify(sol) disp('GAIN = ') pretty(sol) 111 MATLAB Results: » example.m GAIN = 2 2 / 2 2 — wl A (s Q + w2 s + w2 Q) / (wl A s Q + wl A w2 s + wl A w2 Q / 3 2 2 2 + Q B s + Q B s w2 + Q B WI 3 + Q B wl w2 ) Now just analyzing the denominator, the following Matlab code will give the numerical results of the denominator and the roots of the numerator and denominator (notice that they are indeed different). wl = O.l*2*pi; w2 = 3OE3*2*pi; A = 100E3; B = 10; Q = 10; num = -A*w1*(5“2*Q+w2*s+w2“2*Q); den=(A*wl*s“2*Q+A*wl*w2*s+A*wl*w2“2*Q+Q*B*s“3+Q*B*s*w2“2+Q*B*wl*s“2+Q*B *wl*w2“2); 1| roots_num roots_den vpa(solve(num,s),3) vpa(solve(den,s),3) MATLAB Results: roots_num = [ -.942e4+.188e6*i] [ -.942e4-.188e6*i] roots_den = [ -.609e4] [ -.19e3-.189e6*i] [ -.l9e3+.l89e6*i] These roots confirm that the approximated equation for finding the roots is reasonable. Using the derived equation, the roots for the denominator are: 112 ,/|— w,2 = y/(Zn - 30k)2 = 0.188e6 rad/sec Figure B-2 shows the gain of Adm and 1/b plotted on the same graph. The graph shows that there are 2 points of intersection. Figure B-3 includes the phase of Adm plus the phase of the beta network. This graphs shows that the phase margin of the circuit is negative indicating that it is unstable. This shows that a Beta Network Analysis can be used to test for stability when the graph of Adm and 1/ B intersect at multiple points. All intersections must have a positive phase margin to be stable. -100d«\ Jr '200d O Vp(2)+Vp(3) 100 504 O4 SEL>> lOmHz lOOmHz 1.0Hz 10H: 100B: 1.0Kflz 10KB: 100KB: 0 -VdB(3) o VdBtZ) Frequency Figure B-3: Graph of Adm, I/B and the phase of Adm + l/B 113 Appendix C Class G Amplifier V2 2 0 12 V1 3 O 5 VlP 4 O -5 V2P 5 O -12 VBIAS A 101 2.1V VBIASP 101 B 2.1V VIN 1 N DC 0V AC 1 SIN 0 5 1k Om O O VNOISE N 0 DC 0V AC 1 SIN 0 .1 500K X1 0 30 2 5 100 LF411 VOPAMP 100 101 O RIN 1 3O 1K RF 15 30 1K QA 2 A 10 Q2N3904 QB 5 B 105 Q2N3906 OZ 2 20 13 TIP31 01 13 ll 15 TIP31 QlP 14 12 15 TIPBZ QZP 5 23 14 TIP32 D82 10 20 D1N4l48 DBlA 10 21 DlN4l48 0818 21 11 D1N4l48 081A? 12 22 D1N4148 DBlBP 22 105 D1N4148 DBZP 23 105 D1N4l48 Dl 3 l3 D1N5817 DZ 14 4 D1N5817 RL 15 0 10 .TRAN 10 20000 O 10 .MODEL DMOD D .LIB ECE484.LIB .LIB DIODE.LIB .PROBE .END Figure C-l: PSpice circuit file 114 Appendix D Forcing the power lines to oscillate *.cir file Class G Amplifier v2 200 0 15 *v203c X 0 sin 0 .4 12Meg V1 3 O 5 VIP 4 O -5 V2? 500 0 ~15 *v2posc Y 0 sin 0 -.4 12Meg LVPZ 5 500 1U LV2 2 200 10 * Input Sources VIN 1 a DC 0v AC 1 SIN 0 -4.5 1K *R0 110 11 75 VNOISE A 0 DC 0v AC 1 SIN o .4 400K *VBIAS B C {VAL} X1 0 10 2 5 11 ICL8741 RIN 1 10 1K RF 19 10 1K QA 2 11 12 Q2N3904 QB 5 11 12 Q2N3906 Q2 2 13 16 TIP31 Q1 16 15 19 TIP31 Q1? 21 18 19 TIP32 Q2? 5 20 21 TIP32 082 12 13 DlN4148 DBlA 12 14 DlN4l48 0818 14 15 DlN4l48 081A? 18 17 DlN4148 D818? 17 12 01N4148 DBZP 20 12 DlN4148 01 3 16 DlN5817 D2 21 4 DlN5817 XL 190 0 GlZHlOO VXL 190 19 CV *RL 19 0 10 .PARAM VAL = 1 .STEP PARAM VAL LIST 0 .TRAN .10 30000 10000 .10 .LIB ECE402.LIB .LIB DIODE.LIB .LIB IC.LIB .OP .PROBE .END Figure D-l: PSpice circuit file 115 The small signal bias solution output from PSpice: **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C **** CURRENT STEP PARAM VAL = -4.2 ii***ii‘k‘kiflkfl'kt*i'ki'kiinki'it‘kii'kt'hi**********************************§i*i******** NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE 1 1) -4.2000 1 2) 15.0000 1 3) 5.0000 1 4) -5 0000 1 5) -15.0000 1 B) -4.2000 1 10) 205.7E-06 1 11) 7.0695 1 12) 6.3292 1 13) 5.6231 1 14) 5.6148 1 15) 4.9005 1 16) 4.9277 1 17) 6.3292 1 18) 6.3292 1 19) 4.2007 1 20) 6 3292 1 21) -5.0000 1 190) 4.2007 1 200) 15.0000 **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG c **** CURRENT STEP PARAM VAL = -3 *******i‘ii’ii'i'ti*******************it**i**i******i**********************fi*i*i** NODE VOLTAGE NODE VOLTAGE NOOE VOLTAGE NODE VOLTAGE 1 1) -3.0000 1 2) 15.0000 1 3) 5.0000 1 4) -5 0000 1 5) -15.0000 1 8) -3.0000 1 10) 209.5E-06 1 11) 5.7695 1 12) 5.0621 1 13) 4.9304 1 14) 4.3741 1 15) 3.6862 1 16) 4.6523 1 17) 5.0621 1 18) 5.0621 1 19) 3.0007 1 20) 5 0621 1 21) -5.0000 1 190) 3.0007 1 200) 15.0000 **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C **** CURRENT STEP PARAM VAL = 3 iii****i'i******************************if‘ki‘k'kiti'k'kiii‘fl‘iit***#***************** NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NOUE VOLTAGE 1 1) 3.0000 1 2) 15.0000 1 3) 5.0000 1 4) -5.0000 1 5) -15.0000 1 B) 3.0000 1 10) 243.3E-06 1 11) -5.9535 1 12) —5.2050 1 13) 5.1698 1 14) -4.0288 1 15) -2.8150 1 16) 5.0000 1 17) -4.5003 1 18) -3.7956 1 19) -2 9993 1 20) -5.0834 1 21) -4.6526 1 190) -2.9993 1 200) 15.0000 **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE - 27.000 DEG c **** CURRENT STEP PARAM VAL = 4.2 **i'i'*‘ki*i'*fi'tiiiii'k'ktiiti*****************i*****iiii'i'itti'kii*i************i**** NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE 1 1) 4.2000 1 2) 15.0000 1 3) 5.0000 1 4) -5.0000 1 5) -15.0000 1 B) 4 2000 1 10) 247 1E-06 1 11) —7.2658 1 12) -6.4822 1 13) 5.1684 1 14) -5.2700 1 15) -4.0151 1 16) 5.0000 1 17) -5.7470 1 18) -5.0117 1 19) -4.1993 1 20) -5.7570 1 21) -4.9496 1 190) -4.1993 1 200) 15.0000 Figure D-2: PSpice small signal bias solutions 116 Class G V2 2 a VZOsc a V1 3 0 VlP 4 0 V2P 5 b Amplifier 15 0 sin 0 5 -5 -15 .4 12MEG v2posc b 0 sin 0 -.4 12MEG * Input Sources VIN 1 0 DC 0V AC 1 SIN O 8 1K X1 0 10 2 5 11 ICL8741 RIN 1 10 1K RF 19 10 1K QA 2 11 12 Q2N3904 QB 5 11 12 Q2N3906 Q2 2 13 16 TIP31 Ql 16 15 19 TIP31 Q1? 21 18 19 TIP32 Q2? 5 20 D82 12 DBlA 12 D818 14 DBlAP 18 DBlBP 17 DBZP 20 D1 3 16 D2 21 4 .LIB IC. .PROBE .END 21 13 14 15 17 12 12 TIP32 DlN4148 DlN4148 DlN4148 DlN4148 DlN4148 DlN4148 D1N5817 DlN5817 * Speaker Model XL 190 0 G12H100 VXL 190 19 0V .TRAN 10 20000 0 10 .LIB ECE402.LIB .LIB DIODE.LIB LIB Figure D-3: PSpice circuit file 117 Class G Amplifier V2 200 O 15 *VZOSC X 0 sin 0 .4 12Meg V1 3 0 5 VIP 4 0 -5 V2P 500 O -15 *v2posc Y 0 sin 0 -.4 12Meg LVPZ 5 500 1U LV2 2 200 1U * Input Sources VIN 1 a DC 0V AC 1 SIN 0 -4.5 1K *R0 110 11 75 VNOISE A 0 DC 0V AC 1 SIN 0 .4 400K *VBIAS B C {VAL} X1 0 10 2 5 11 ICL8741 RIN l 10 1K RF 19 10 1K QA 2 11 12 Q2N3904 QB 5 11 12 Q2N3906 Q2 2 13 16 TIP31 01 16 15 19 TIP31 QlP 21 18 19 T1932 Q2? 5 20 21 TIP32 082 12 13 DlN4148 DBlA 12 14 DlN4148 D818 14 15 DlN4148 DBlAP 18 17 DlN4148 DBlBP 17 12 DlN4148 D82? 20 12 DlN4148 D1 3 16 DlN5817 D2 21 4 D1N5817 XL 190 0 GlZHlOO VXL 190 19 0V *RL 19 0 10 .PARAM VAL = 1 .STEP PARAM VAL LIST 0 .TRAN .1U 3000U 10000 .10 .LIB BCE402.LIB .LIB DIODE.LIB .LIB IC.LIB .OP .PROBE .END Figure D-4: PSpice circuit file 118 Class G Amplifier V2 2 a v20sc a V1 3 0 VlP 4 0 V2? 5 b 15 0 sin 0 5 -5 -15 .4 lZMEG v2posc b 0 sin 0 -.4 12MEG * Input Sources VIN 1 0 DC 0V AC 1 SIN 0 8 1K X1 0 10 2 5 ll ICL8741 RIN 1 10 1K RF 19 10 1K QA 2 11 12 Q2N3904 Q8 5 ll 12 Q2N3906 Q2 2 13 16 TIP31 Q1 16 15 19 TIP31 QlP 21 18 19 TIP32 Q2? 5 20 DBZ 12 DBlA 12 D818 14 DBlAP 18 DBlBP l7 DBZP 20 D1 3 16 D2 21 4 XL 190 21 13 14 15 17 12 12 TIP32 DlN4148 DlN4148 DlN4148 DlN4148 DlN4148 DlN4148 DlN5817 D1N5817 * Speaker Model 0 G12H100 VXL 190 19 0V .TRAN 1U ZOOOU 0 10 .LIB ECE402.LIB .LIB DIODE.LIB .LIB IC.LIB .PROBE .END Figure D-S: PSpice circuit file 119 Appendices E Full Beta Network Circuit File Beta Analysis V2 200 O 15 V1 3 0 5 VlP 4 O -5 V2? 500 0 -15 rlvp2 499 500 1 r1v2 199 200 1 LVP2 5 499 10 LV2 2 199 10 VBIAS l A {VAL} VNOISE A 0 AC 1 *X1 0 10 2 5 11 ICL8741 RIXl 77 0 2MEG CIXl 77 0 2P ROXl 1 11 75 RIN 0 77 1K RF 19 77 1K QA 2 11 12 Q2N3904 Q8 5 11 12 Q2N3906 Q2 2 13 16 TIP31 Q1 16 15 19 TIP31 QlP 21 18 19 TIP32 Q2? 5 20 21 TIP32 DBZ 12 13 DlN4148 DBlA 12 14 DlN4148 D818 14 15 DlN4148 DBlAP 18 17 DlN4148 D818? 17 12 DlN4148 DBZP 20 12 DlN4148 D1 3 16 D1N5817 D2 21 4 D1N5817 RL l9 0 10 * ICL8741 POLE GRAPHING VH 70 0 15 VL 71 0 -15 VIN 100 0 AC 1 VIO 100 8 226.080 X1 B 0 70 71 73 ICL8741 ROUT 73 0 10K .PARAM VAL 1 .STEP PARAM VAL LIST 6.133 -6.232 .AC DEC 2000 1MEG IOOMEG .LIB ECE402.LIB .LIB DIODE.LIB .LIB IC.LIB .OP .PROBE .END Figure E-l: PSpice circuit file 120 **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C **** CURRENT STEP PARAM VAL a 6.133 ***iitiiit***i****************t*tiiiti*********i*******tiiiiititttititittitii* NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) 6.1330 ( 2) 14.9960 ( 3) 5.0000 ( 4) ”5.0000 ( 5) “15.0000 ( A) 0.0000 ( B)-226.1E~06 ( 11) 6.1314 ( 12) 5.4342 ( 13) 5.1041 ( 14) 4.7658 ( 15) 4.0974 ( 16) 4.6697 ( 17) 5.4342 ( 18) 5.4342 ( 19) 3.4231 ( 20) 5.4342 ( 21) ‘5.0000 ( 70) 15.0000 ( 71) ’15.0000 ( 73) 55.85E-06 ( 77) 1.7111 ( 100) 0.0000 ( 199) 14.9960 ( 200) 15.0000 ( 499) ‘15.0000 ( 500) ‘15.0000 Figure E-2: PSpice small signal bias solutions 121 *iii OPERATING POINT INFORMATION TEMPERATURE = 27.000 DEG C CURRENT STEP PARAM VAL = 6.133 *******************iiflkiflkiiflt*i'k'kiti'iti**fli'tti‘kti‘itti‘kiifi‘kti********i*** **** DIODES **** NAME DBZ DBlA DBlB DBlAP DBlBP MODEL DlN4148 DlN4148 DlN4148 DlN4148 DlN4148 ID 3.45E-06 3.64E-03 3.64E-03 -2.94E-13 -2.94E-13 VD 3.30E-01 6.68E-01 6.68E-01 -3.38E-06 -3.39E-06 REQ 1.42E+04 1.34E+01 1.34E+01 1.15E+07 1.15E+07 CAP 6.39E-12 8.67E—10 8:67E—10 4.00E-12 4.00E-12 NAME DBZP D1 D2 MODEL DlN4148 DlN5817 D1N5817 ID -4.98E-13 3.40E-01 -2.41E-12 VD -5.74E-06 3.30E-01 -2.86E-09 REQ 1.15E+07 1.12E-01 1.19E+03 CAP 4.008-12 6.62E-10 4.72E-10 **** BIPOLAR JUNCTION TRANSISTORS NAME QA QB Q2 Ql QlP MODEL QZN3904 Q2N3906 TIP31 TIP31 TIP32 IB 2.14E-05 4.25E-12 3.45E-06 3.64E-03 2.96E-13 IC 3.62E-03 -4.78E-11 5.29E-05 3.40E-01 -9.54E—12 VBE 6.97E-01 6.97E-01 4.34E-01 6.74E-01 2.0lE+OO VBC -8.86E+00 2.1lE+01 -9.89E+00 -5.7ZE-01 1.04E+01 VCE 9.56E+00 -2.04E+01 1.03E+01 1.25E+00 -8.4ZE+00 BETADC 1.69E+02 -1.12E+01 1.SBE+01 9.34E+01 -3.22£+01 GM 1.34E-01 -1.09E-12 2.04E-03 9.52E+00 -8.42E-14 RPI 1.38E+03 1.BlE+14 1.13E+04 8.06E+00 4.34E+14 RX 1.00E+01 1.00E+01 1.00E-01 1.00E-01 1.003-01 R0 2.29B+04 3.1OE+11 2.0BE+06 2.9SE+02 8.41E+11 CBE 4.69E-11 6.33E-12 3.25E-10 1.90E-07 1.03E-10 CBC 1.66E-12 1.39E-12 4.48E-11 1.17E-10 5.84E-11 CJS 0.00E+00 0.00E+OO 0.00E+00 0.00E+OO 0.00E+00 BETAAC 1.BSE+02 -1.97E+02 2.30E+01 7.6BE+01 -3.66E+01 CBX/CBXZ 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 FT/FTZ 4.39E+08 -2.25E-02 8.7BE+05 7.99E+06 -8.32£-05 NAME QZP MODEL TIP32 IB 4.96E-13 IC -1.ZSE-11 VBE 1.04E+01 VBC 2.04E+01 VCE -1.00E+01 BETADC -2.51E+01 GM -1.00E-13 RPI 4.34E+14 Rx 1.00E-01 R0 7.67E+11 CBE 5.64E-11 CBC 4.77E-11 CJS 0.00E+00 BETAAC —4.34E+01 CBX/CBXZ 0.00E+00 FT/FTZ —1.53£—O4 Figure E-3: PSpice operating point information 122 **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C **** CURRENT STEP PARAM VAL ' “6.232 ii*********t*t**************titiii*iti*******************************ii**t**** NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) -6.2320 ( 2) 15.0000 ( 3) 5.0000 ( 4) -5.0000 ( 5) ‘14.9950 1 A) 0.0000 ( B)‘226.1E'06 ( 11) '6.2307 ( 12) ‘5.4944 ( 13) 5.1695 ( 14) '4.3310 ( 15) '3.1671 ( 16) 5.0000 ( 17) -4.8142 ( 18) -4.1340 ( 19) '3.3514 ( 20) ‘5.2084 ( 21) “4.6710 ( 70) 15.0000 ( 71) ‘15.0000 ( 73) 220.8E—06 ( 77) '1.6753 1( 100) 0.0000 ( 199) 15.0000 ( 200) 15.0000 ( 499) ‘14.9950 ( 500) ‘15.0000 Figure E-4: PSpice small signal bias solutions 123 **** OPERATING POINT INFORMATION TEMPERATURE = 27.000 DEG C CURRENT STEP PARAM VAL = -6.232 i*ifiiitiii'k'k‘ki*‘kiiiti‘k‘kii'ii'kii'ki******iii*************i**fitii’tii‘i'iiti***§***** **** **** DIODES NAME DBZ DBlA DBlB DBlAP DBlBP MODEL DlN4148 DlN4148 DlN4148 DlN4148 DlN4148 ID -7.09E-09 -5.02E-09 -5.02E-09 4.58E-03 4.58E-03 VD —1.07E+01 -l.l6E+00 ~1.16E+OO 6.80E-01 6.80E-01 REQ 1.52E+10 4.27E+09 4.28E+09 1.088+01 1.08E+01 CAP 1.42E-12 2.68E—12 2.68E—12 1.08E-09 1.088—09 NAME DBZP D1 D2 MODEL DlN4148 D1N5817 D1N5817 ID 1.40E-06 8.50E—09 3.32E-01 VD 2.86E-01 1.01E—05 3.29E-01 REQ 3.49E+04 1.19E+03 1.14E—01 CAP 5.61E-12 4.72E-10 6.618-10 **** BIPOLAR JUNCTION TRANSISTORS NAME QA QB 02 01 01? MODEL Q2N3904 QZN3906 TIP31 TIP31 TIP32 IB -2.88E-11 -1.79E-05 -7.09E-09 -5.0ZE-O9 —4.58E-03 1C 5.52E-11 -4.56E-03 1.36E-08 1.50E-08 -3.32E-01 VBE -7.36E-01 -7.36E-01 1.69E-01 1.84E-01 -7.83E-01 VBC —2.12E+01 8.76E+00 -9.83E+00 -8.17E+00 5.37E-01 VCE 2.05E+01 -9.50E+00 1.00E+01 8.35E+00 -1.32E+00 BETADC -1.91E+00 2.SSE+02 -1.92E+00 -2.99E+00 7.26E+01 GM -2.77E-13 1.70E—01 7.29E—08 1.27E-07 8.08E+00 RPI 4.16E+14 1.45E+03 8.67E+06 6.00E+06 6.4OE+00 RX 1.00E+01 1.00E+01 1.00E-01 1.00E-01 1.00E-01 R0 6.40E+11 6.02E+03 5.45E+10 3.16E+10 3.0ZE+02 CBE 3.76E-12 4.46E-11 2.14E-10 2.16E-10 1.11E-07 CBC 1.28E-12 2.24E-12 4.49E-11 4.838-11 1.19E-10 CJS 0.00E+OO 0.00E+00 0.00E+00 0.00E+00 0.00E+OO BETAAC —1.15E+02 2.46E+02 6.32E-01 7.65E-01 5.17E+01 CBX/CBXZ 0.00E+00 0.00E+00 0.00E+00 0.00E+00 0.00E+00 FT/FTZ -8.73E-03 5.77E+08 4.49E+01 7.66E+01 1.16E+07 NAME QZP MODEL TIP32 IB -1.40E-O6 IC -5.94E-05 VBE -5.37E—01 VBC 9.79E+OO VCE -1.03E+Ol BETADC 4.24E+01 GM 2.29E-03 RPI 2.21E+04 RX 1.00E-01 RO 1.85E+06 CBE 3.17E-10 CBC 5.958-11 CJS 0.00E+OO BETAAC 5.07E+01 CBX/CBXZ 0.00E+00 FT/FTZ 9.69E+05 Figure E-S: PSpice operating point information 124 Class G Amplifier Vbias 6.133 Simplified * Input Sources VBIAS A 1 {VAL} VNOISE 1 0 AC 1 LV2 4 0 1U GMA 4 3 2 3 0.134 CBEA 2 3 4.69E-11 CBCA 2 4 1.66E-12 GM2 4 0 8 0 2.04E-3 CBEZ 8 0 3.25E-10 CBC2 8 4 4.48E-11 GMl 0 12 11 12 9.52 RPII 11 12 8.06 CBEl 11 12 1.90E-7 REQDBZ 3 8 1.42E4 REQDBIA 3 10 13.4 CAPDBlA 3 10 8.67E-10 REQDBlB 10 11 13.4 CAPDBlB 10 11 8.67E-10 RF 12 77 5 RIN 77 0 5 RO A 2 75 *******************~k***** * ICL8741 POLE GRAPHING VH 70 0 15 VL 71 0 -15 VIN 100 0 AC 1 VIC 100 B 226.08U X1 B 0 70 71 73 ICL8741 ROUT 73 0 10K ************************* .PARAM VAL = 1 .STEP PARAM VAL LIST 6.1 .AC DEC 900 l lOOMEG .LIB IC.LIB .OP - .PROBE .END Figure E-6: PSpice circuit file 125 Class G Amplifier Vbias 6.133 Simplified * VNOISE 1 0 AC 1 LV2 4 0 1U GMA 4 3 2 3 0.134 CBCA 2 4 1.66E-12 CBC2 O 4 4.48E-11 REQDBlB 3 11 13.4 RLl 11 77 5 RL2 77 0 5 R0 1 2 75 * .AC DEC 900 1 100MEG .PROBE .END Figure E-7: PSpice circuit file Class G Amplifier Vbias -6.232 * VNOISE 1 0 AC 1 LV2? 5 0 10 GMB 3 5 3 2 .170 CBCB 2 5 2.24E-12 CBC2P 0 5 5.95E-1l REQDBIBP 3 12 10.8 RLl 12 77 5 RL2 77 0 5 R0 1 2 75 *- .AC DEC 900 1 100MEG .PROBE .END Figure E-8: PSpice circuit file 126 Class G Amplifier Vbias 6.133 Simplified [0 ] [-GO SCBCA+GO 0 [0 ] [0 ~GMMA Y 2,3 [0 ] [0 Y 3,2 -GMMA [0 ]=[0 0 -GEQDBlB [0 ] [0 O O [1 ] [1 0 0 [0 ] [0 0 0 Y( 2,3 ) = +GMMA+GEQDBlB Y( 3,2 ) = -sCBCA+GMMA Y( 3,4 ) = +sCBCA+sCBC2-1 Y( 4,5 ) = +GL1+GEQDBlB -sCBCA 0 Y 3,4 0 0 O sLV2+1 0 0 -GEQDBlB 0 0 0 Y 4,5 -GL1 -GL1 GL2+GL1 0 0 O 0 OOOI—‘OO -sLV2 ][V1 1 1[V2 1 1[V3 1 11V4 1 ][V11] ][V77] )[v79] *Ignore nodes 78 and higher if present. They are used for internal numbering. Numerator of: v77 TERMS SORTED ACCORDING TO POWERS OF S s**2 terms: + SLVZ*SCBCA*GO*GMMA*GL1*GEQDBIB + SLV2*SCBC2*GO*GMMA*GL1*GEQDBlB s**0 terms: + GO*GMMA*GL1*GEQDBlB ***********************************************i' NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT + 1.238938-021 * s**2 + 2.666668-005 * s**0 ******************i'k'k‘k-k'k‘k‘k‘k‘ki'k'k‘k**************** Denominator Of: v77 TERMS SORTED ACCORDING TO POWERS OF s s**3 terms: + SLV2*SCBCA*SCBC2*GMMA*GL2*GL1 + sLV2*sCBCA*SCBC2*GMMA*GL2*GEQDBIB + SLV2*SCBCA*SCBC2*GMMA*GL1*GEQDBlB + sLV2*SCBCA*sCBC2*GL2*GLl*GEQDBlB s**2 terms: + sLV2*SCBCA*GO*GMMA*GL2*GL1 + SLV2*SCBCA*GO*GMMA*GL2*GEQDBlB + sLV2*SCBCA*GO*GMMA*GL1*GEQDBlB + SLV2*SCBCA*GO*GL2*GL1*GEQDBIB + sLV2*sCBCA*GMMA*GL2*GL1*GEQDBlB + sLVZ*sCBC2*GO*GMMA*GL2*GLl + SLVZ*SCBCZ*GO*GMMA*GL2*GEQDBlB + SLV2*SCBC2*GO*GMMA*GL1*GEQDBlB + sLV2*sCBC2*GO*GL2*GL1*GEQDBlB s**1 terms: + SCBCA*GMMA*GL2*GL1 + sCBCA*GMMA*GL2*GEQDBlB + SCBCA*GMMA*GL1*GEQDBIB + SCBCA*GL2*GL1*GEQDBIB s**0 terms: + GO*GMMA*GL2*GL1 + GO*GMMA*GL2*GEQDBIB + GO*GMMA*GL1*GEQDBIB + GO*GL2*GL1*GEQDBIB ************************************************ NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT + 9.18079e-031 * s**3 + 8.31135e-021 0.000164601 * s**0 ************************************************ Figure E-9: Sspice results 127 * s**2 + 2.04928e-014 * s**l + Class G Amplifier Vbias 6.133 Simplified and using Sspice approximator option [0 ] [-GO sCBCA+GO 0 -sCBCA 0 [0 ] [O -GMMA Y 2,3 0 -GEQDBlB [0 ] [0 Y 3,2 -GMMA Y 3,4 0 [0 ]=[O 0 -GEQDBlB O Y 4,5 [0 ] [0 0 0 0 -GL1 [1 ] [1 0 0 0 0 [0 ] [0 O 0 sLV2+1 O Y( 2,3 ) = +GMMA+GEQDBlB Y( 3,2 ) = -SCBCA+GMMA Y( 3,4 ) = +sCBCA+sCBC2-1 Y( 4,5 ) = +GL1+GEQDBlB *Ignore nodes 78 and higher if present. They are numbering. 0 0 ][V1 ] 0 0 ][V2 ] O 1 ][V3 ] -GL1 0 ][V4 ] GL2+GL1 O ][V11] 0 0 ][V77] 0 -sLV2 ][V79] used for internal RESULTS APPROXIMATED USING A THRESHOLD MAGNITUDE OF: 0.90 Numerator of: v77 TERMS SORTED ACCORDING TO POWERS OF s s**2 terms: + sLV2*sCBC2*GO*GEQDBlB s**O terms: + GO*GEQDBIB *******i**************************************** NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT + 4.4577e-020 * s**2 + 0.000995023 * s**0 ************ii********************************** Denominator Of: v77 TERMS SORTED ACCORDING TO POWERS OF s s**3 terms: + sLV2*sCBCA*sCBC2*GL2 S**2 terms: + sLV2*SCBC2*GO*GL2 s**1 terms: + sCBCA*GL2 S**O terms: + GO*GL2 ************************************************ NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT + 1.48736e-029 * S**3 + 1.19466e-019 * s**2 + 3.326-013 * s**1 + 0.00266666 * s**0 ***********************************************i Figure E-10: Sspice results 128 Class G Amplifier Vbias -6.232 [0 ] [-GO sCBCB+GO 0 -SCBCB 0 O 0 ][V1 ] [0 ] [0 -GMMB Y 2,3 0 Y 2,5 0 0 ][V2 ] [O ] [O Y 3,2 -GMMB Y 3,4 0 O 1 ][V3 ] [0 ]=[0 0 Y 4,3 0 Y 4,5 -GL1 0 ][V5 ] [0 ] [0 O 0 O -GL1 GL2+GL1 O ][V12] [1 ] [1 0 0 0 0 0 O ][V77] [0 ] [0 0 0 sLV2P+1 O O -sLV2P ][V79] Y( 2,3 ) = +GMMB+GEQDBlBP Y( 2,5 ) = -GEQDBlBP ,Y( 3,2 ) = -sCBCB+GMMB Y( 3,4 ) = +sCBCB+sCBC2P-1 Y( 4,3 ) = -GEQDBlBP Y1 4,5 ) = +GL1+GEQDBlBP *Ignore nodes 78 and higher if present. They are used for internal numbering. Numerator of: V7? TERMS SORTED ACCORDING TO POWERS OF s S**2 terms: + sLV2P*sCBCB*GO*GMMB*GL1*GEQDBlBP + sLV2P*sCBC2P*GO*GMMB*GL1*GEQDBlBP s**0 terms: + GO*GMMB*GL1*GEQDBIBP ************************************************ NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT + 2.59155e-021 * s**2 + 4.19752e-005 * s**0 ************************************************ Denominator of: V7? TERMS SORTED ACCORDING TO POWERS OF s S**3 terms: + sLV2P*sCBCB*sCBC2P*GMMB*GL2*GL1 + sLV2P*sCBCB*sCBC2P*GMMB*GL2*GEQDBIBP + sLV2P*sCBCB*sCBC2P*GMMB*GL1*GEQDBIBP + SLV2P*SCBCB*SCBC2P*GL2*GL1*GEQDBlBP s**2 terms: + sLV2P*sCBCB*GO*GMMB*GL2*GLl + sLV2P*sCBCB*GO*GMMB*GL2*GEQDBlBP sLV2P*sCBCB*GO*GMMB*GL1*GEQDBlBP sLV2P*sCBCB*GO*GL2*GLl*GEQDBlBP SLV2P*SCBCB*GMMB*GL2*GL1*GEQDBlBP SLVZP*SCBCZP*GO*GMMB*GL2*GLl sLV2P*sCBC2P*GO*GMMB*GL2*GEQDBlBP SLV2P*SCBC2P*GO*GMMB*GL1*GEQDBlBP SLVZP*SCBC2P*GO*GL2*GL1*GEQDBlBP s**1 terms: + sCBCB*GMMB*GL2*GL1 + sCBCB*GMMB*GL2*GEQDBlBP + sCBCB*GMMB*GL1*GEQDBlBP + sCBCB*GL2*GL1*GEQDBlBP s**0 terms: + GO*GMMB*GL2*GL1 + GO*GMMB*GL2*GEQDBlBP + GO*GMMB*GL1*GEQDBIBP + GO*GL2*GL1*GEQDBlBP *************i*i'ab******************************* NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT + 2.239le-030 * s**3 + 1.52401e-020 * s**2 + 3.7632e-014 * s**1 + 0.000223999 * s**0 ************************************************ Figure E-ll: Sspice results + + + + + + + 129 Class G Amplifier Vbias -6.232 OOOt-‘OO ][V1 1 ][V2 1 ][V3 1 ][VS 1 ][V12] ][V77] -sLV2P ][V79] used for internal [0 ] [-GO sCBCB+GO 0 -sCBCB O O [0 ] [O —GMMB Y 2,3 0 Y 2,5 0 [0 ] [0 Y 3,2 -GMMB Y 3,4 0 O [0 ]=[0 O Y 4,3 0 Y 4,5 -GL1 [0 ] [O O O 0 -GL1 GL2+GL1 [l ] [1 O O 0 0 0 [0 ] [O 0 0 sLV2P+1 0 O Y( 2,3 ) = +GMMB+GEQDBIBP Y( 2,5 ) = -GEQDBlBP Y( 3,2 ) = -sCBCB+GMMB Y( 3,4 ) = +sCBCB+sCBC2P~1 Y( 4,3 ) = -GEQDBlBP Y( 4,5 ) = +GL1+GEQDBlBP *Ignore nodes 78 and higher if present. They are numbering. RESULTS APPROXIMATED USING A THRESHOLD MAGNITUDE Numerator Of: v77 TERMS SORTED ACCORDING TO POWERS OF s s**2 terms: + sLV2P*sCBC2P*GO*GEQDBlBP s**0 terms: + GO*GEQDBlBP ************************************************ NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT + 7.34566e-020 * s**2 + 0.00123456 * s**0 ***********************************************i Denominator of: v77 TERMS SORTED ACCORDING TO POWERS OF s s**3 terms: + sLV2P*sCBCB*sCBC2P*GL2 s**2 terms: + SLV2P*SCBC2P*GO*GL2 s**1 terms: + SCBCB*GL2 s**0 terms: + GO*GL2 ***********************************************i NUMERICAL VALUE OF ABOVE SYMBOLIC RESULT + 2.6656e-029 * s**3 + 1.58666e-019 * s**2 + 4.48e-013 * s**1 + 0.00266666 * s**0 *********************************************** Figure E-12: Sspice results 130 OF: 0.90 Appendix F Class G Amplifier V2 2 0 18 V1 3 0 6 VIP 4 0 -6 V2P 5 0 -18 * Input Sources VIN 1 0 DC 0V AC 1 SIN 0 {VAL} 1K X1 0 10 2 5 ll LF411 RIN 1 10 1K RF 19 10 1K QA 2 11 12 Q2N3904 QB 5 11 12 Q2N3906 Q2 2 13 16 TIP31 Q1 16 15 19 TIP31 QlP 21 18 19 TIP32 Q2P 5 20 21 TIP32 D82 12 13 DlN4148 DBlA 12 14 DlN4148 D818 14 15 DlN4148 DBlAP 18 17 DlN4148 DBlBP 17 12 DlN4148 DBZP 20 12 DlN4148 D1 3 16 D1N5817 D2 21 4 DlN5817 RL 19 O 10 *********************************** * Class B Amplifier for Comparison VHIGH 200 0 18 VLOW 201 0 -18 X8 1 204 200 201 202 LF411 QHl 200 202 203 Q2N3904 QLl 201 202 203 Q2N3906 QH2 200 203 204 TIP31 QLZ 201 203 204 TIP32 ROUT 204 0 10 *********************~k********~k**i* .PARAM VAL = 1 .STEP PARAM VAL 0 13.7 0.1 .TRAN 1U 3000U 0 10 .LIB ECE402.LIB .LIB DIODE.LIB .LIB IC.LIB .OP .PROBE .END Figure F-l: PSpice circuit file 131 Total Harmonic Distortion Test Circuit Class G Amplifier V2 2 0 18 V1 3 0 6 V1P 4 0 -6 V2P 5 0 -18 * Input Sources VIN 1 0 DC 0V AC 1 SIN O 13.7 1K X1 0 10 2 5 11 LF411 *ICL8741 RIN 1 10 1K RF 19 10 1K CADDI 2 80 0.010 RADDl 80 13 10 CADD2 5 81 0.010 RADD2 81 20 10 QA 2 11 12 Q2N3904 QB 5 11 12 Q2N3906 Q2 2 13 16 TIP31 Q1 16 15 19 TIP31 QlP 21 18 19 TIP32 Q2P 5 20 21 TIP32 D82 12 13 DlN4148 DBlA 12 14 DlN4148 D818 14 15 DlN4148 DBlAP 18 17 DlN4148 DBlBP 17 12 DlN4148 DBZP 20 12 DlN4148 D1 3 16 D1N5817 D2 21 4 D1N5817 RL 19 0 10 .TRAN .10 20000 00 .10 .LIB ECE402.LIB .LIB DIODE.LIB .LIB IC.LIB .OP .FOUR 1K 20 V(l9) .PROBE .END Figure F-2: PSpice circuit file 132 FOURIER COMPONENTS OF TRANSIENT RESPONSE V(19) DC COMPONENT = HARMONIC H O\D(D~JO\U1D(JBJP‘Z O RJF‘F‘HIJFAF‘P‘P‘H C>@(D~JO\U1A(»erd NIAPABJFJHIarArak-H101D~JOTUIA1JIOIJ 8.462706E-05 FREQUENCY (HZ) .OOOE+03 .OOOE+03 .OOOE+03 .OOOE+03 .OOOE+03 .OOOE+03 .OOOE+03 .OOOE+03 .OOOE+03 .OOOE+04 .100E+04 .ZOOE+O4 .300E+O4 .400E+04 .500E+04 .600E+O4 .700E+O4 .BOOE+04 .900E+04 .OOOE+O4 H-dIdcnra\Jh1m14~4raa1h-w1acnrad3h-H FOURIER COMPONENT .37OE+01 .753E-04 .606E-04 .7808-04 .5518-04 .703E-04 .1628-04 .6968-04 .2328-04 .6038-04 .9028—04 .569E-04 .129E-O4 .4638-04 .778E-04 .4078—04 .O61E-O4 .294E—04 .624E-04 .224E-04 NORMALIZED COMPONENT .000E+00 .280E-05 .282E-05 .299E-05 .242E-05 .243E-05 .958E-05 .238E-05 .OO9E-05 .170E-05 .768E-05 .146E-05 .934E-05 .068E-05 .677E-05 .027E-05 .884E-05 .449E-06 .565E-05 .936E-06 (DU‘KJU'IHU'IHU‘HUTf-‘ml-‘U‘l-‘ONHQHH mmmqmmmqumqumqmr-‘mra PHASE (DEG) .800E+02 .597E+01 .013E+02 .965E+01 .761E+01 .664E+01 .012E+02 .144E+01 .743E+01 .601E+01 .003E+02 .354E+01 .784E+01 .54SE+01 .886E+01 .559E+01 .84lE+01 .SOlE+01 .704E+01 .769E+01 NORMALIZED PHASE (DEC) 0. -4. -4. -6. -8 -1. -1. -1. ~1. .886E+03 -1. -2. .26ZE+03 -1 -2 -2. -2. .784E+03 -2. -3. .3238+03 -3. -2 -3 000E+00 459E+02 387E+02 3OBE+02 .223E+02 167E+03 159E+03 348E+O3 S4ZE+O3 879E+03 066E+O3 605E+03 601E+03 9818+03 3ZSE+03 502E+03 TOTAL HARMONIC DISTORTION = 1.814640E-02 PERCENT Figure F -3: PSpice THD results FOURIER COMPONENTS OF TRANSIENT RESPONSE V(19) DC COMPONENT = 7.012749E-05 HARMONIC FREQUENCY FOURIER NORMALIZED PHASE NORMALIZED NO (HZ) COMPONENT COMPONENT (DEG) PHASE (DEG) 1 1.000E+04 1.370E+01 1.000E+00 1.798E+02 0.000E+00 2 2.000E+04 3.461E-04 2.526E-05 -1.297E+02 -4.893E+02 3 3.000E+04 8.629E-03 6.299E-O4 1.005E+02 -4.390E+02 4 4.000E+04 6.546E-04 4.778E-05 ~1.753E+02 -8.945E+02 5 5.000E+04 8.406E-03 6.135E-04 1.04OE+02 -7.951E+02 6 6.000E+O4 1.032E-03 7.535E-05 -1.452E+02 -1.224E+03 7 7.000E+04 8.101E-03 5.913ET04 1.125E+02 -1.146E+03 8 8.000E+04 1.316E-03 9.602E-05 -1.592E+02 -1.598E+03 9 9.000E+04 7.882E-03 5.753E-O4 1.159E+02 -1.502E+03 10 1.000E+05 1.662E-03 1.213E-04 -1.393E+02 -1.937E+03 11 1.100E+05 7.697E-03 5.618E-04 1.247E+02 -1.853E+O3 12 1.200E+05 1.910E-03 1.394E-04 -1.463E+02 -2.304E+03 13 1.3OOE+05 7.484E-03 5.462E-04 1.273E+02 -2.210E+03 14 1.400E+05 2.233E-03 1.630E-04 -1.300E+02 -2.647E+03 15 1.500E+O5 7.303E-03 5.331E-04 1.356E+02 -2.562E+03 16 1.600E+05 2.418E-03 1.765E-04 -1.342E+02 -3.011E+03 17 1.700E+05 6.994E-O3 5.105E-04 1.375E+02 -2.919E+03 18 1.800E+05 2.738E-03 1.999E-04 -1.204E+02 -3.357E+03 19 1.900E+05 6.763E-03 4.936E-04 1.457E+02 ~3.271E+03 20 2.000E+05 2.852E-03 2.082E-04 -1.229E+02 -3.719E+03 TOTAL HARMONIC DISTORTION = Figure F4: PSpice THD results 133 1.746231E-01 PERCENT Appendix G Class G Amplifier with more biasing V2 2 0 18 V1 3 0 6 VIP 4 0 -6 V2P 5 0 -18 * Input Sources VIN 1001 0 DC 0V AC 1 SIN.0 {VAL} 20K E2 1 0 1001 0 .2 X1 0 10 2 5 ll LF411 *ICL8741 RIN 1 10 1K RF 19 10 5k * Biasing Network RBIAS 2 A 10K DBIASl A AA DlN4148 DBIASlA AA AAA DlN4148 DBIASZ AAA 11 DlN4148 DBIASB 11 BBB DlN4148 DBIASB BBB BB DlN4148 DBIAS4 BB B DlN4148 RBIASP B 5 10K X2 A 41 2 5 41 LF411 X3 8 42 2 5 42 LF411 QA 2 41 12 QZN3904 QB S 42 120 02N3906 CHI 2 22 0.010 R81 22 13 10 C82 5 23 0.010 R82 23 20 10 02 2 13 16 TIP31 01 16 15 19 TIP31 01? 21 18 19 TIP32 QZP 5 20 21 TIP32 D82 12 13 DlN4148 DBlA 12 14 DlN4148 DBlB 14 15 DlN4148 DBlAP 18 17 DlN4148 D818? 17 120 DlN4148 D82P 20 120 DlN4148 D1 3 16 D1N5817 D2 21 4 DlN5817 RL 19 0 10 ttiiflititi*fitfifliittittifli********** * Class B Amplifier for Comparison VHIGH 200 0 18 VLOW 201 0 ~18 *El 1000 O 1 O 10 X8 1001 204 200 201 202 LF411 081 200 202 203 QZN3904 QLl 201 202 203 Q2N3906 082 200 203 204 TIP31 QL2 201 203 204 TIP32 ROUT 204 0 10 **ti*iiviti*iifiit****t**t*ii**i**i*1k *(AVG(V(19)*I(RL)))/(AVG(V(2)*—I(V2))+AVG(V(5)*-I(VZP))+AVG(V(3)*- I(V1))+AVG(V(4)*-I(V1P))) *YatX1 (AVG(V(19) *I (RL) ) ) / (AVG(V(2) *-I (V2) )+AVG(V(5) *-I (V2P))+AVG(V(3) *- I (V1) )+AVG(V(4) *-I(V1P) ) ) . 3m) ‘rYatX((AVG(V(204)*I(Rout)))/(AVG(V(200)*-I(VHIGH))+AVG(V(201)*-I(VLOW))).3m) 134 .PARAM VAL = 1 .STEP PARAM VAL O 13.8 0.1 .TRAN .1U 300U 0 .10 .LIB ECE402.LIB .LIB DIODE.LIB .LIB IC.LIB .OP .FOUR 20K 20 V(19) .PROBE V(19) I(RL) V(2) I(V2) V(S) I(V2P) V(3) I(Vl) V(4) I(VlP) V(204) I(Rout) + V(200) I(VHIGH) V(201) I(VLOW) V(1001) V(l) .END Figure G-l: PSpice circuit file 135 Bibliography [1] Li, S. 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