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THE DESIGN OF LOW-POWER INTEGRATED RADIO-
FREQUENCY FRONT-END IN CMOS

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SHAOLEI QUAN

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THE DESIGN OF LOW—POWER INTEGRATED RADIO—
FREQUENCY FRONT —END IN CMOS

By

Shaolei Quan

A THESIS
Submitted to
Michigan State University
in partial fulﬁllment of the requirements
for the degree of
MASTER OF SCIENCE
Department of Electrical Engineering

2003

ABSTRACT

THE DESIGN OF LOW—POWER INTEGRATED RADIO—
FREQUENCY FRONT-END IN CMOS

By

Shaolei Quan

Previous attempts to design low-power radio-frequency (RF) front-end in standard
CMOS technology have failed to produce satisfying results in terms of design optimization
and topology improvement. The problem of how to reduce front-end power without
degrading RF performance remains challenging. A review of the literature shows that a

good rationale as well as innovative design techniques is needed to deal with the problem.

For each building block in low-IF front-end, this thesis identiﬁes the major tradeoff
involved in the design, then analyzes the tradeoff to derive new design techniques and cir-
cuit topologies. Such rationale leads to several design methods effectiveness of which is
later demonstrated by the design and layout of a 2.4-GHz Bluetooth receiver front-end in
TSMC 0.18-um CMOS technology. A novel method for noise-constrained optimization for
low power is developed for integrated CMOS low noise ampliﬁer (LN A). A novel analyz-
ing method as well as modiﬁed topology is developed for Gilbert mixer to improve linear-
ity. Finally, a novel low—power implementation of complex analog ﬁlter, which is the
asymmetric polyphase network ﬁlter with Nauta’s transconductor, is developed for image

rejection in the front-end.

ACKNOWLEDGMENTS

First, I am deeply grateful to Professor Chin-Long Wey, who is my previous thesis
advisor, current thesis co-advisor, and all-time friend, for his guidance without which this
thesis simply would have been impossible. His stimulating insights have been constant

inspiration for me. His encouragement and experience helped me through many difﬁcult

times during the thesis work.

Second, I would like to thank Professor Gregory M. Wierzba, my current thesis
advisor, for his considerate instruction and thoughtful suggestions that have enabled me to
improve and ﬁnalize the thesis work. I am also indebted to Professor Wierzba for the efforts

he has devoted to securing the resources needed by my future research based on this thesis

work.

Third, I would like to thank Professor Andrew Mason and Professor Peixin Zhong
for their generous participation as readers for this thesis work despite their busy schedule
in the ﬁnal weeks of semester. I am grateful for their invaluable suggestions on how to

improve the thesis.

Finally, this thesis work was supported in part by the National Science Foundation

under the grant number CCR-0098053.

iii

TABLE OF CONTENTS

LIST OF TABLES ..................................................... vi
LIST OF FIGURES ................................................... vii
CHAPTER 1
INTRODUCTION ...................................................... l
1.1 RF Transceiver ................................................... 4
1.2 Low Power RF Receiver Front-End ................................... 9
1.3 Thesis Objective and Organization ................................... 10
CHAPTER 2
BACKGROUND ...................................................... 13
2.1 Preliminaries .................................................... 14
2.2 Front-End Architecture ........................................... 17
2.3 Front-End Building Blocks ......................................... 22
2.3.1 Low Noise Ampliﬁer ........................................... 22
2.3.1.1 Common—source cascode LNA with inductive degeneration .......... 23
2.3.1.2 Topology improvement of CSID LNA ........................... 25
2.3.1.3 Design optimization of CSID LNA ............................. 26
2.3.2 Mixer ....................................................... 26
2.3.2.1 Gilbert cell ................................................ 28
2.3.2.2 Topology improvement of Gilbert cell ........................... 30
2.3.2.3 Design optimization of Gilbert cell ............................. 31
2.3.3 Integrated Continuous-Time Filter ................................. 32
2.3.3.1 OTA-C continuous time ﬁlter .................................. 32
2.3.3.2 Complex analog ﬁlter ........................................ 35
2.4 Research Topics .................................................. 36
CHAPTER 2
DESIGN APPROACH .................................................. 39
3.1 Low Noise Ampliﬁer .............................................. 39
3.1.1 Tradeoff between Performance and Power .......................... 39
3.1.2 Noise Analysis ................................................ 45
3.1.2.1 NMOS Transistor model ...................................... 47
3.1.2.2 Integrated inductor model ..................................... 43
3.1.2.3 Derivation of noise factor ..................................... 48

iv

3.1.2.4 Noise—constrained optimization for minimum power ................ 53

3.1.2.5 Mapping from to SI] ........................................ 57
3.2 Downconversion Mixer ............................................ 59
3.2.1 Tradeoff between Performance and Power .......................... 59
3.2.1.1 Two-step approach for linearity analysis of mixer .................. 60
3.2.1.2 Derivation of IIP3 for NMOS device ............................ 62
3.2.1.3 Derivation of IIP3 for mixer ................................... 64
‘3.2.2 Topology Improvement of Mixer for High Linearity .................. 68
3.3 Complex Analog Filter ............................................ 70
3.3.1 Analysis of Image Rejection with Asymmetric Polyphase Network ....... 74
3.3.1.1 Asymmetric polyphase network ................................ 74
3.3.1.2 Operation of complex analog ﬁlter based on polyphase network ...... 76
3.3.2 Active Implementation of CAP ................................... 79
CHAPTER 4
SIMULATION RESULTS ............................................... 82
4.1 Design Speciﬁcation for Bluetooth Front-End .......................... 82
4.2 Circuit Design ................................................... 83
4.2.1 LNA .................... ' .................................... 83
4.2.2 Mixer ....................................................... 84
4.2.3 Complex Analog Filter .......................................... 86
4.2.4 Impedance Matching between Building Blocks in Front-End. . .‘ ......... 87
4.3 Post-Layout Simulation Results ..................................... 87
CHAPTER 5
CONCLUSIONS ..................................................... 101
REFERENCES ....................................................... 103

LIST OF TABLES

Table 4.1: Post-Layout Simulation Results of MRFEC ............................................... 100

vi

LIST OF FIGURES

Figure 1.1: A Simpliﬁed Conﬁguration of GSM Network ............................................... 5
Figure 1.2: Architecture of Analog Transceiver: (a) Transmitter; and (b) Receiver ....... 7
Figure 1.3: Architecture of Digital Transceiver: (a) Transmitter; and (b) Receiver ......... 8
Figure 2.1: RF (Receiver) Front-End for 1.9 GHz PCS Headset ................................... 15
Figure 2.2: Image Rejection in RF Front-End ................................................................ 18

Figure 2.3: Front-End Architectures: (a) High IF; (1)) Zero IF; (c) Low IF; and Image
Rejecting (Weaver) ......................................................................................................... 20
Figure 2.4: Integrated LNA Topologies: (a) Classic; (b) LC-Folding; and (c) CMOS
Current-Reusing .............................................................................................................. 24
Figure 2.5: Small-Signal Circuit for Noise and Gain Calculation in Classic CSID LNA
Design ............................................................................................................................. 27
Figure 2.6: Integrated Mixer Topologies: (a) Gilbert Cell; (b) LC-Folded Gilbert Cell; (c)
Triode-Biased Mixer; and (b) Pass-Gate Mixer ............................................................. 29

Figure 2.7: Integrated Gm—C Filter Topologies: (a) Classic; (b) OTA; (c) Balanced; and

(d) Q-Enhanced ............................................................................................................... 34
Figure 2.8: Nauta’s Transconductor ............................................................................... 38
Figure 3.1: Low-IF Architecture of Proposed Front-End ............................................... 41
Figure 3.2: Generic Model of Input Stage of CSID LNA .............................................. 41
Figure 3.3: Cascode LNA with Inductive Source Degeneration .................................... 46

vii

Figure 3.4: Small-Signal Equivalent Circuit for Noise and Gain Calculation in Classic

CISD LNA Design .......................................................................................................... 46
Figure 3.5: Small-Signal Model of NMOS Transistor for Hand Calculation ................. 49
Figure 3.6: Simpliﬁed Model of Integrated Inductor ..................................................... 49
Figure 3.7: Small-Signal Circuit of Input Stage of CSID LNA ...................................... 52
Figure 3.8: Small-Signal Circuit for Calculating Noise Factor ...................................... 52
Figure 3.9: Two-Level Design Approach ....................................................................... 61
Figure 3.10: Input Stage of Gilbert Cell ......................................................................... 61
Figure 3.11: Source Degenerated Input Stage of Gilbert Mixer ..................................... 65
Figure 3.12 Nonlinearity Model of NMOS Transistor with Source Degeneration ........ 67
Figure 3.13: Transconductance Stage of Gilbert Cell with Active Degeneration .......... 71
Figure 3.14: Modiﬁed Gilbert Cell ................................................................................. 71
Figure 3.15: Downconversion with Quadrature LO Signals .......................................... 73
Figure 3.16: Spectrum Translation in Complex Filtering ............................................... 73
Figure 3.17: One Phase of a Generalized N-Phase Network .......................................... 75
Figure 3.18: 4—Phase Passive RC Network ..................................................................... 75

Figure 3.19: Circuit Conﬁguration for Image Rejecting with 4-Phase RC Polyphase

Network .......................................................................................................................... 77
Figure 3.20: Active Resistor with Transconductor ......................................................... 80
Figure 4.1: Circuit Conﬁguration for LNA Simulation .................................................. 89
Figure 4.2: Minimum Noise Factor versus Power for Different Q-Value ...................... 90

Figure 4.3: Min. Noise Factor versus Power for Different Degree of Input Matching ..90

viii

Figure 4.4: Simulated Curve of Minimum Noise Figure versus Power with Perfect Input

Matching ......................................................................................................................... 91

Figure 4.5: Simulated Curve of Minimum Noise Factor versus Power with Imperfect

Input Matching ................................................................................................................ 91
Figure 4.6: Noise Factor versus Gate Overdrive for Q==3.0........; ................................... 92
Figure 4.7: Circuit Conﬁguration of Mixer without Degeneration ................................ 93
Figure 4.8: Circuit Conﬁguration of Mixer with Active Degeneration .......................... 93
Figure 4.9: Simulated IIP3 Performance for Three Mixer Versions .............................. 94
Figure 4.10: Simulated IIP3 Curve for 2mW Mixer with Active Degeneration ............ 94
Figure 4.11: Circuit Conﬁguration for Active Polyphase Filter Simulation .................. 95

Figure 4.12: Simulated Frequency Response of 4-Phase Filter with Nauta’s Gm Cell: (3)

Signal Gain; and (b) Image Gain .................................................................................... 96
Figure 4.13: 822 of LNA for Frequencies from 2.4-GHz to 2.5-GHz ............................ 97
Figure 4.14: 811 of Mixer for Frequencies from 2.4—GHz to 2.5-GHz .......................... 97
Figure 4.15: Impedance Matching Network between LNA and Mixer .......................... 98

Figure 4.16: 811 of Mixer with Impedance Matching Network for Frequencies from 2.4-
GHz to 2.5-GHz .............................................................................................................. 98

Figure 4.17: Front-End Layout ....................................................................................... 99

ix

1 INTRODUCTION

A radio—frequency (RF) communication system transmits information using radio
waves of frequencies from 400MHz to 2.SG-Hz [l]. The RF spectrum lies between the

VHF spectrum and the microwave spectrum.

The unique combination of several characteristics of RF electromagnetic waves
makes it suitable for personal communication purpose. First, compared with those of VHF
band, the higher frequencies of RF band make it possible to accommodate more channels,
to increase channel capacity, and to increase signal-to-noise ratio (SNR) according to Shan-
non’s theorem [2]. Second, unlike its microwave counterpart, most work in RF circuit
design can be done with a lumped model due to the relatively large wavelengths (120m—
75cm) of RF waves [3,4]. In this way the design process becomes simpler and system cost
is reduced. Finally, compared with microwave waves, RF waves suffer less propagation
loss from atmospheric absorption caused by water vapor and molecular oxygen. Such
absorption is a major factor affecting the performance of RF communication systems in

practice [4].

One historically important RF application is radar, such as L-band Synthetic Aper-
ture Radar (SAR) for ocean imaging [5], and C-band weather penetration radar for com-
mercial airlines [6]. Another major RF application has been wireless communication
systems since 19708, when satellite mobile radio systems operating in UHF frequency band

of approximately 400MHz were launched [7]. However, the high costs of satellite mobile

radio systems prevented them from being widely used in public domain. The emerging of
cellular mobile radio communication systems in late 19708, such as Nordic Mobile Tele-
phone (NMT) system by Ericsson, and Advanced Mobile Phone Service (AMPS) by
AT&T Bell Laboratories, arguably marked the beginning of portable communications rev-
olution which would fundamentally change people’s life style in the following decades [8].
Other important RF applications include global positioning system (GPS) and cordless tele-

phony.

Cellular mobile radio systems provide their users with opportunities to travel freely
within the service area and simultaneously communicate with any telephone, fax, data
modem, and electronic mail subscriber anywhere in the world [7]. Advances in VLSI and
RF IC technologies keep making the cellular mobile radio headsets cheaper, smaller, and
less power-consuming. Consequently, since 19803 the market of cellular mobile radio sys-
tems (cellular phones) has been experiencing explosive growth, and the trend is expected
to continue at least in the near future [1]. The ﬁrst generation of cellular mobile radio,
AMPS, employs FDMA with analog FM and FDD modulation. Today, the widely used
second generation GSM employs TDMA with digital coding modulation GMSK to achieve
better performance than that of the ﬁrst generation. Meanwhile, the third generation
CDMA based on direct-sequence CMDA and FDD with OQPSK that offers more robust
operation and more channel capacity than GSM is right on the way [3]. All generations of

cellular mobile radios operate in the RF band.
A GPS (global positioning system) is a system for determining a user’s position in
space as well as in time. A GPS consists of satellites (transmitters), receivers (GPS radio),

and land control centers for satellite—monitoring. The satellites transmit RF signals contain-

ing position and clock time information, while the receivers recover the information from
received RF signals [9]. For example, the NAVSTAR GPS includes 24 L-band polar-orbit
satellites transmitting signals at 1575.42 MHz and 1227.6 MHz simultaneously. The
received RF signal for civilian use yields an rrns position error of about 50-100m. With
more accurate signaling, the error can be reduced to around 15m [10]. The GPS receiver is
widely used in navigation systems. The FCC has mandated location ﬁnding for cell phones
with GPS as the prevailing technology, and GPS radio is expected to be standard equipment
for cars in the near future [11,12]. As a result, the demand of GPS receivers, particularly

those of low cost, low power and small size is rapidly increasing in recent years.

Cordless telephony has been using RF frequencies to provide short-range voice
communication since the birth of analog cordless standard known as CEPI‘ICTI operating
in the bands 914-915/959-960 MHz [13]. The efforts to increase the number of channels as
well as channel capacity result in several digital cordless standards which employ carriers
of higher RF frequencies, digital signaling and modulation schemes including TDMA,
FDD, and GFSK. One good example of digital cordless telephony framework is the widely
used Digital European Cordless Telephone (DECT) standard that operates in the bands
1880-1950MHz and has many advanced features such as trafﬁc balance and uncoordinated
operation [13]. Because of its low cost and ﬂexibility, digital cordless telephony has a rap-

idly expanding market [14].

While the demand for traditional RF applications keeps growing, the use of RF
bands to provide radio links for local-area data communication such as wireless LAN is
increasingly attractive [15]. There are many technologies competing to implement the

function of data transfer between communication devices and PCs, and Bluetooth is the

most promising one due to its longer connection distance than other standards such as IrDA
[16][l7]. A Bluetooth radio operates in the unlicensed 2.5 GHz industrial, scientiﬁc, and
medical (ISM) RF band with features of low cost, automatic service discovery and ad hoc
device connection. Such salient features make Bluetooth suitable for a wide range of appli-
cations such as automobile, laptop, PDA, etc [18]. Other technologies for short-range RF

communication such as ultra-wideband wireless standard [114] are also emerging.

1.1 RF Transceiver

A RF communication system in the strict sense refers to a set of sub-systems that
operate independently and communicate with each other using RF radio links. Figure 1.1
shows a simpliﬁed conﬁguration of GSM system consisting of several sub-systems [19].
MHS (Mobile Headset Sub-system) is the mobile radio carried by user as personal commu-
nications terminal; BTS (Base Transceiver Station) manages the RF radio links with nearby
MHS’s; BSC (Base Station Controller) deals with radio resource management and han-

dover.

From the perspective of RF system design, the sub-systems of RF communication
system are quite similar in framework in most cases despite their difference in speciﬁca—
tion. For example, MHS and BTS in Figure 1.1 may share the same framework because of
their similar functions of transmitting and receiving RF signals. Consequently, in the wide
sense each of the sub-systems is considered a RF communication system itself, or in other

word, a transceiver.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Figure 1.1: A Simpliﬁed Conﬁguration of GSM Network.

A RF transceiver usually consists of a receiver and a transmitter. The receiver
recovers the information data from RF signal received with antenna, whereas the transmit-
ter modulates RF signal with the information data and sends RF signal to open air with

antenna.

Historically the RF transceiver was ﬁrst implemented with analog modulation tech-
niques, and later with digital modulation techniques. Generic architectures of analog RF
transceivers and digital RF transceivers are shown in Figure 1.2 and Figure 1.3, respec-
tively [20]. Compared with their analog-modulation counterpart, digital-modulation trans—
ceiver (DMT) has several important advantages. First, a DMT consumes less power due to
the higher level of integration. Second, a DMT is less sensitive to system noise and there-
fore produces higher SNR. Third, a DMT requires much less tuning work. Finally, more
complicated functions such as image rejecting in digital domain can be performed with the
use of DSP in a DMT. Today, digital-modulation transceiver has been widely used in main-

stream RF applications for wireless communications [19].

The analog electronics for processing RF signal in a transceiver, as shown in Fig-
ures 1.2 and 1.3, is called transceiver front-end. A RF transceiver front-end consists of
transmitter front-end and receiver front-end. Compared with transmitter front-end, the
receiver front-end consumes more power and is much more difﬁcult to design because of
the hostile operating environment for typical wireless applications [3]. Thus, low-power
design methodology for receiver front-end has been greatly needed for portable communi-
cation applications. Unless stated otherwise, by “front-end” we refer to receiver front-end

in the rest of this thesis.

 

 

 

 

 

 

 

 

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Figure 1.2: Generic Architecture of Analog Transceiver: (a) Transmitter; and (b)

Receiver.

 

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(b)
Figure 1.3: Generic Architecture of Digital Transceiver: (a) Transmitter; and (b)
Receiver.

1.2 Low Power RF Receiver Front-End

Examination of consumer electronics market shows that the great demand of RF
portable communications systems is driven by the development of low-cost and small-foot-
print wireless headsets [22]. The major contributors to the cost and size of such headsets
are the transceiver integrated circuits (IC) and the battery. Therefore, it is desirable to
increase integration level of transceiver IC to minimize the number of discrete components
for less cost and smaller size. Since there is no substantial improvement expected in perfor-
mance of battery technology in the near future [23], reduced power consumption of trans-
ceiver IC relaxes the requirements of battery such that cheaper battery can be used to cut
the cost. Therefore, the low-power monolithic transceiver IC that operates without discrete
components and consumes minimal power is particularly attractive for portable wireless

communication terminals [22].

The fundamental tradeoff in RF transceiver IC design is the balance among cost,
power and speed. To achieve the goal of low power and monolithic integration, innovations
in various aspects of RF transceiver design and implementation are required [24]. Particu-
larly, the choice of semiconductor technology is of crucial importance, since the RF perfor-
mance of transceiver 1C is limited by RF characteristics of the semiconductor technology
used for fabrication. Traditionally, RF IC’s are fabricated with GaAs technology featuring
high gain and low noise. However, the GaAs fabrication process is generally expensive and

unstable [1,4].

Recently, CMOS technology has become a serious contender to the conventional

GaAs technology for RF 1C realization [25]. Advance of CMOS technology has made it the

dominant choice for realizing the baseband digital electronics in transceiver [26]. Therefore
the implementation of transceiver analog electronics in CMOS technology is attractive due
to the promise of integrating the whole transceiver on a single chip. On the other hand, the
RF performance of CMOS technology has been improving rapidly, where RF IC transceiv-
ers up to 5 GHz have been reported [27]. Considering that the front-end is the most power
hungary part in a RF transceiver [1], it is natural to develop the low-power RF front-end in

CMOS technology.

1.3 Thesis Objective and Organization

Despite the many research efforts on the design and implementation of low-power
integrated CMOS RF IC in past years, a fully-integrated CMOS transceiver for wireless
voice communication terminals such as GSM headsets is still not commercially available.
When the requirements of image-rejecting and intermodulation are relaxed, however, full
integration of RF transceiver becomes possible, as is in the case of many wireless data com-
munication applications such as Bluetooth [29,92,99]. The bottleneck of realizing a high-
perforrnance low-power monolithic RF transceiver IC is the design of its front—end compo-
nents [1]. The difﬁculty for such design comes in three ways. First, RF performance of
CMOS technology is inherently inferior to that of GaAs technology in terms of gain and
noise. This disadvantage often makes it a very difﬁcult job to balance the tradeoff between
power and speed in front-end design. Second, unlike the design of CMOS VLSI circuits,
there is not much help available from CAD tools in CMOS RF IC design, including the

front-end design. Therefore, the design cycle tends to be long, and no optimum results are

10

guaranteed. Third, the lack of high-quality passive integrated circuit components, such as

hi gh-Q integrated inductors, degrades the front—end performance seriously [3].

As mentioned before, RF receiver front-end consumes more power than transmitter
front-end and is much more difﬁcult to design because of the hostile Operating environment
for typical wireless applications [3]. For this reason, this research will focus on the devel-

0pment of the receiver front—end design.

The objective of this thesis study is to explore the problems of designing and devel-
oping low-power monolithic receiver front-end IC using standard digital CMOS technol-
ogy, referred to as MRFEC, for portable RF wireless communication applications. The
main focus is placed on how to Optimize the building blocks (LNA, mixer, image—rejecting
ﬁlter) of MRFEC in terms of both design methodology and circuit topology. For each
building block, the major tradeoff affecting its performance is identiﬁed, then novel anal-
ysis methods are developed to treat such tradeoff, ﬁnally novel design guideline or circuit

tepology is derived from the analysis results. The thesis is organized as follows.

Chapter 2 reviews the literature on RF CMOS front-end design. Existing work is
examined at four levels in front-end design: device technology, integrated circuit compo-
nent, RF building block, and front-end architecture. Emphasis is put on important RF build-
ing blocks (LNA, mixer, and irnage-rejecting ﬁlter) and front-end architectures (low-IF,
high-IF, zero—IF, and image-rejecting). The chapter is concluded with a summary of

research topics involved in this thesis work.

Chapter 3 describes the proposed approaches for the design of front-end building
blocks. For each building block, a novel analysis is ﬁrst given to characterize the RF behav-

ior, then our efforts to improve RF performance in terms of either design optimization or

11

topology improvement are presented. The chapter begins with a novel analysis of LNA
noise behavior, then derives a method to perform noise-constrained optimization for mini-
mum power consumption. Followed is the discussion on design of downconversion mixer,
which analyzes the linearity issue of Gilbert-cell mixer in a novel manner based on feed-
back system model. Subsequently a new topology of Gilbert cell is proposed. Next a thor-
ough analysis on image-rejecting operation of complex analog ﬁlter is presented. This
chapter is concluded with a novel implementation of complex analog ﬁlter in silicon based

on lattice prototype.

In Chapter 4, a 2.4 GHz front-end for Bluetooth is designed with the techniques pro-
posed in preceding chapters, and is implemented in TSMC 0.18-um digital CMOS process.
Post-simulation results from Cadence SpectreRF tools are analyzed and compared with
those in the literature. Our designed MRFEC consumes considerably less power than those
reported, with comparable performance in the other aspects. Therefore, the effectiveness of

our design approaches is clearly demonstrated.

Finally, Chapter 5 summarizes the thesis work, presents future research directions

on low-power integrated RF front-end in CMOS, and gives the conclusion.

12

BACKGROUND

The design of integrated front-end is a complicated job involving tradeoffs at four
levels: device technology, integrated circuit device, front-end building block, and front-end
architecture [24]. RF characteristics of device technology impose physical limits on RF
performance of the front-end, particularly limiting its frequency response. To utilize the
device technology to its full potential in terms of RF-band operation, how to construct inte-
grated circuit devices such as integrated transistors becomes important. Further, to accom—
modate advantages and disadvantages of available integrated circuit devices, the topology
of RF building blocks such as LNA has to be carefully designed to meet the speciﬁcation
while consuming minimum resources such as power, chip area, etc. Finally the front-end
architecture determines how the front-end speciﬁcation should be distributed among RF

building blocks, and consequently inﬂuences the front-end performance signiﬁcantly.

Research efforts to design low-power high-performance integrated front-end at the
mentioned four levels could be broadly classiﬁed into two categories: design optimization
and topology improvement. Design optimization concerns modeling and analyzing circuits
and devices to derive the optimum values of design parameters such as the optimum
number of ﬁngers in a multi-ﬁnger transistor structure [48]. Meanwhile topology improve-
ment involves modifying circuit structure or device layout to promote RF performance

such as gain, stability, etc. One example is 3D spiral inductor [44].

13

Existing work on RF front-end design in digital CMOS technology addresses vari-
ous issues at the higher three levels which are integrated—device level, building-block level,
and architecture level [1]. Most design techniques at integrated-device level, however, are
not scalable and could not be implemented with standard digital CMOS process without
increasing costs [45]. For example, the fabrication of high-quality metal-insulator-metal
(MIM) capacitor requires two additional masking steps beyond those needed for a pure
logic process ﬂow [44]. For this reason, emphasis will be given to design efforts at build-

ing-block level and architecture level in following discussion.

2.1 Preliminaries

A RF front-end provides a convenient interface between electromagnetic ﬁelds and
digital signal processing [32]. From the perspective of signal processing, major functions
of a RF front-end include gain (to convert the usually weak signals to convenient amplitude
levels for further processing) and frequency conversion (to translate signals to convenient

frequency bands for further processing).

A typical CMOS RF (receiver) front-end for 1.9-GHz PCS (Personal Communica-
tion Standard) headsets with heterodyne architecture is shown in Figure 2.1 [33]. As the
ﬁrst component in the receiver chain, the duplexer (DUP) isolates the received signal from
transmitted signal. After passing the duplexer, the RF signal is ampliﬁed by the low noise
ampliﬁer (LNA). The bandpass ﬁlter BPFl suppresses the image, while the mixer down-
converts the receive band to an intermediate frequency (IF) centered at 260 MHz. The IF
signal is further ﬁltered by the bandpass ﬁlter BPF2 before it is ampliﬁed by an IF ampliﬁer

[33]. The building blocks (LNA, mixer, ﬁlter, etc.) involved here will be explained shortly.

14

 

IF ampliﬁer

(1930-1990) MHz LNA BPFl Mixer BPF2
L DUP % %
”X; ”7&5

(230—290) MHz

 

 

 

 

 

 

 

 

 

 

 

 

L01 (1700 MHz)

Figure 2.1: RF (Receiver) Front-End for 1.9 GHz PCS Headset [33].

15

The key parameters for measuring performance of a RF front-end are gain, noise
factor, gain compression point, third-order interception point, blocking point, and power
consumption. Gain describes the signal-amplifying capability of front-end. Noise factor
describes to what degree the front-end degrades the signal-to-noise (SNR) ratio of signal.
Gain compression point, third-order interception point, and blocking point characterize

front-end linearity in different aspects.

The voltage gain of a front-end is deﬁned as

where A": is the amplitude of IF signal at front-end output, and ARF is the amplitude of RF

signal at front-end input.

The noise factor of a front-end is deﬁned as

_ SNRin
" SNRom’

 

where SNRin and SNRout are signal-to-noise ratios at front-end input and output, respec-

tively. Then the noise ﬁgure of a front-end is given by
NF = lOlogF

Assuming the input signal to front-end has single frequency component (DRF and
amplitude ARF, the voltage gain Gv decreases as A“: increases due to the effect of nonlin-
earity. Consequently, AME, in, the gain compression point, is deﬁned as ARF for which G\,

is 1 dB less than what it is supposed to be in the ideal case (e.g. without nonlinearity).

Consider the case that the input signal to front-end has two frequency components

of a)“: and (”block’ for which amplitudes are ARF and Ablock, respectively. Then Gv

16

decreases as Ablock increases for ARF « Ablock due to the effect of nonlinearity. Hence the

blocking point Ablock, in is deﬁned as Ablock for which Gv drops to zero.

Consider the case that input signal to front-end has two frequency components of
map] and (’3sz , for which amplitudes are AR“ and AR”, respectively. Due to the effect of
nonlinearity the output signal contains new frequency components of (em and (”1132 given
by

mm = 2‘”er ’ mm.

mm = 203mm ‘ wRFI

For wireless applications employing FDMA, it is quite likely that tom and tom lie in the
frequency bands for some other channels [3]. Consequently, Gv, the voltage gain for output
signal at 03m decreases as ARFI and ARFZ increase, and so does the voltage gain for output
signal at (011:2. This effect is usually caused by the third-order nonlinearity of front-end

[105]. Assuming ARF] and ARI—:2 always have the same value, then All” is deﬁned as ARFI

for which Gv for frequency component (cm at front-end output drops to zero.

2.2 Front-End Architecture

The most important consideration in choosing front-end architecture is the perfor-
mance of image rejection. As shown in Figure 2.2, both the signal and its image fall into
the same IF band after downconversion. Therefore in the presence of a strong image, the
signal may be overwhelmed after downconversion. The common approach to solving this
problem is to reject the image signal with a BPF or LPF before the downconversion stage
[105]. A common measure for the degree of image rejection is image-rejection ratio (IRR),
which is deﬁned as the ratio of signal power to image power at front-end output while both

signal and image have the same power at front-end input.

17

 

 

 

Figure 2.2: Image Rejection in RF Front-End.

l8

The integrated active ﬁlter in silicon can only achieve IRR no more than 40 dB [34].
This disadvantage essentially limits the use of integrated CMOS RF front-end in lucrative
mobile communication applications such as GSM headsets that usually require IRR higher

than 80 dB [80]. Front-end architecture plays a dominant role in addressing this issue.

The key design parameter of front-end architecture is intermediate frequency (IF),
which indicates the tradeoff between image rejection and channel selection [3]. A higher
IF results in higher degree of image rejection, lower degree of channel selection, and more
power consumption. Good understanding of this point is important for choosing proper
front-end architecture to meet design speciﬁcation.

Four types of front-end architecture are available: hi gh-IF architecture, zero-IF
architecture, low-IF architecture, and image-rejecting architecture [88].

The high-IF architecture is shown in Figure 2.3 (a). Typical value of IF for such
architecture ranges from 80 MHz to 300 MHz for RF applications [102]. While relaxing the
requirement of image ﬁltering, the use of high IF, however, results in IF processing elec-
tronics of high power consumption.

The zero-IF architecture is shown in Figure 2.8 (b), where image rejecting ﬁlter as
well as IF processing electronics is eliminated, and only a LPF is needed for channel selec-
tion [3]. Such architecture, however, is sensitive to L0 leakage, DC offset, and 1/f noise

[3]. One way to deal with the disadvantages of zero-IF scheme is to employ multiphase

downconversion at the cost of increased design complexity and more power consumption

[112].

I9

LNA Image Reject Filter Channel Select Filter IF Amplifier

x6) BPF BPF—>—>

 

 

 

 

 

 

 

 

 

 

 

 

Ito
(a)
LNA Channel Select Filter Baseband Ampliﬁer
Ito
(b)

 

. 250 kHz
‘ Active 8 bit

Integrated

Sequence AID 4
Asymmetric

I I I I
Polyphase
L84 Filter ~48)»
O O

 

 

 

 

 

 

 

 

 

 

 

 

 

LPF

 

x(t) __,.,

 

 

L. LPF

 

 

 

 

((1)

Figure 2.3: Front End Architectures: (a) High IF; (b) Zero IF; (c) Low IF [88]; and ((1)
Image Rejecting (Weaver).

20

 

The low-IF architecture is shown in Figure 2.3 (c). Typical value of IF for such
architecture ranges from IM to 3M for RF applications [28]. The use of low IF makes the
receiver insensitive to DC offset and beyond the 1/f noise comer while maintaining the

advantages of zero-IF scheme.

One image-rejecting architecture (Weaver) is shown in Figure 2.3 (d). The image-
rejecting architecture removes image by cancellation. Therefore no image-rejecting ﬁlters
are needed. However, the scheme is sensitive to mismatching of integrated components.
Consequently the image rejection ratio is limited to 40dB, which is too low in the cases of

personal wireless communication applications such as GSM [3].

Current trends in RF front-end research are multiband, wideband, and auto-tuning
for mismatch. Multiband operation is achieved by using multiple LNA’s and mixers [99],
meanwhile wideband Operation is achieved by using LNA’s with feedback loop [31]. It is
also shown recently that the phase error caused by mismatch in Weaver architecture can be

calibrated with least mean square (LMS) technique [101].

In the design of integrated front-end in CMOS, the low-IF scheme appears attrac-
tive because it is amenable to integration without troubles such as DC offset and 1/f noise.
However, a low IF makes it difﬁcult to reject image signal before downconversion. In a
typical low—IF Bluetooth front end, OJRF and to"; equal 2.4 GHz and 2 MHz, respectively.
Considering that the typical IRR requirement for Bluetooth front end is 50dB, then the
required attenuation in the transition band of IR ﬁlter around (0L0 is about 250,000 dB per
octave! To eliminate this problem, the image could be removed after downconversion with

a complex analog ﬁlter (CAF) [98], as will be explained later in this chapter.

21

2.3 Front-End Building Blocks

2.3.1 Low Noise Ampliﬁer

An ideal low noise ampliﬁer (LNA) ampliﬁes the incoming signal without adding
noise or causing distortion. The most important function of LNA in a RF receiver is to alle-
viate the degradation of system noise performance caused by the inherently noisy RF fre—
quency-conversion devices (e.g. RF mixer) in following stages. Meanwhile a typical LNA
itself exhibits nonlinear and noisy characteristics that degrades system performance mainly
due to the use of active devices [3]. As a result, merits from the use of LNA are partially
offset by the disadvantages introduced simultaneously. A general characterization of
LNA’s impact on noise factor of overall RF receiver is given by the Friis equation [107]

..+ Fm-l
AplApz...A

 

 

Fz—l
F“), = 1+(F1—l)+ A +. , (2.1)

P1 ptm-l)

where Ftot is noise factor of the RF system; Apm and Fm are available power gain and noise
factor of the k-th stage, respectively. TO minimize the system noise factor Fm, LNA is usu-
ally the ﬁrst gain stage in a RF receiver, and therefore determines noise factor of the overall

system according to the Friis equation.

Major requirements of LNA include low noise ﬁgure (NF), (reasonably) high gain,
good linearity, good input/output (10) matching, and good reverse isolation [3]. For the
LNA to be used in portable applications such as GSM headsets, low power consumption is

also required.

22

Conventionally there are three topologies for single-transistor LN A: common
source (CS), common gate (CG), and common drain (CD) [3]. CD scheme hardly provides
any gain, and CG scheme results in high noise ﬁgure. Consequently, CS scheme has been
the dominant topology for the gain stage of RF LNA in CMOS because of its potential of

high gain and low noise [62].

It is often difﬁcult for a single—stage CS LNA to meet all requirements simulta-
neously, particularly when both good reverse isolation and high gain are required [3].
Therefore a current buffer is usually added to LNA as the second stage to improve reverse
isolation for better stability without reducing LNA gain. The current buffer also extenuates
the Miller effect. In practice an output buffer is often needed as the third stage of LNA to

drive SO-Q load.

2.3.1.1 Common-source cascade LNA with inductive degeneration
The classic common-source LNA topology is shown in Figure 2.4 (a) [54]. Such
topology is often called the common-source cascode LNA with inductive degeneration
(CSID LNA) in the literature. Note that the output buffer stage of LNA is not shown in the
ﬁgure. In a CSID LNA, transistor M1 provides enough gain while transistor M2 serves as
a current buffer. The cascode structure saves power because of current reuse. Good input
matching as well as low noise ﬁgure is achieved by tuning parameters of LNA input net-
work such as Ls, Lg, M1 bias, and M1 width. Larger output swing is achieved by use of
inductive load Ld. The major advantage of CISD topology over its competitors is its capa-
bility of achieving good input matching without adding noise or limiting the transconduc-

tance of input stage. The good reverse isolation exhibited by the topology is a plus.

23

Vdd

 

Ld
M2
Li:

C M1

Rs
Ls

‘E

(a)

 

—————l B’as
13:;an 1 TI RF Output

0))

_a

RF Output

 

RF Input I

(C)

Figure 2.4: Integrated LNA Topologies: (a) Classic [54]; (b) LC-Folding [33]; and (c)

CMOS Current-Reusing [53].

24

2.3.1.2 Topology improvement of CSID LNA

The major challenge in CSID LN A design toward low-power integrated implemen-
tation in CMOS is how to reduce power without affecting RF performance [24]. Many
efforts have been devoted to addressing this challenge in terms Of topology improvement,

and several trends are observed.

The ﬁrst trend is to save power with reduced power supply voltage. The main Obsta-
cle to the use of low supply voltage is the cascode structure employed in CSID LNA. One
proposed technique eliminates cascode structure by use of LC folding structure shown in
Figure 2.4 (b) and l-V power supply [33]. The problem of linearity degradation caused by
reduced supply voltage is solved by reducing LN A gain slightly [33]. The use of LC-fold-
ing technique with silicon-on-insulator (SOI) technologies in LNA could further reduce

supply voltage to as low as 0.5 V [58].

The second trend is to save power by reusing drain current with PMOS transistor
for larger gain. The classic topology for LNA with CMOS current-reusing is shown in
Figure 2.4 (c), where CMOS ampliﬁer is extensively used to increase gain. Traditionally
LNA with such topology suffers from the poor RF performance of PMOS transistor.
Recently PMOS technology has been improved signiﬁcantly and low-power low-noise-

ﬁgure LNA with PMOS and NMOS inductive degeneration has been reported [60].

The third trend is to save power by increasing Q—value of the RLC network at LNA
output with active negative conductor [55]. The increased Q-value typically means larger
gain, such that less current of LNA is needed to meet design speciﬁcation. However, the
resultant power saving depends heavily on the effectiveness of available LNA optimization
methods, since negative conductor itself contributes considerable power consumption.

25

2.3.1.3 Design optimization of CSID LNA

The classic methodology for design optimization of CSID LNA uses the small—
signal equivalent circuit of LNA input stage shown in Figure 2.5 for noise and gain calcu-
lation, where Jim is RMS value of the gate-induced noise and 1.2 d is RMS value of the

drain current noise, both exhibited by transistor M1 [54].

In this methodology, the major tradeoff between RF performance and power con-
sumption Of LNA is identiﬁed as the one between the magnitude of gate induced noise and
that of drain current noise. Intuitively, this is because that for ﬁxed gate overdrive of tran-
sistor M1 a larger device width results in smaller input-referred drain current noise yet
larger gate induced noise. Therefore, a minimum noise factor can be calculated for given

power budget as well as a minimum power for given noise factor.

2.3.2 Mixer

A downconversion mixer in front-end translates the signal spectrum from RF carrier
frequency (several Giga-Hz) to IF frequency (up to several hundred MHz) [4]. The mixer

input is usually the ampliﬁed RF signal from LNA, ﬁltered or not.

Performance of mixer is mainly characterized by its noise factor, linearity, and con-
version gain [3]. The mixer linearity is further measured by two parameters, namely, 3-dB
compression point A__l dB and input third-order intercept point IIP3. Ideally a mixer should
have low noise factor, high linearity and reasonable (several st) conversion gain. In mixer
design for integrated front-end, the additional requirement of low power consumption has

to be met.

26

 

 

 

Figure 2.5: Small-Signal Equivalent Circuit for Noise and Gain Calculation in Classic
CSID LNA Design [54].

27

There are two fundamental types of integrated mixer available: square-law-based
mixer and multiplier-based mixer [105]. Usually the latter is preferred due to its superior

performance of port isolation.

2.3.2.1 Gilbert cell

In practice the dominant topology for multiplier-based mixer is the Gilbert cell
shown in Figure 2.6 (a) [105]. The Gilbert cell consists of two stages, namely, transconduc-
tance stage and multiplying stage. For the transconductance stage, the differential drain
current of M1 and M2 is modulated by differential RF input signal connected to their gates.
For the multiplying stage, the different drain current of M1 and M2 is multiplied by differ-
ential LO signal connected to gates of M3, M4, M5, and M6. The differential IF output
results from the combination of the drain currents of M3, M4, M5, and M6 in some speciﬁc

pattern.

Several important advantages make Gilbert cell attractive in integrated mixer
design [105]. First, mixers based directly on multiplication generally exhibit superior per-
formance because they ideally generate only the desired intermodulation product. This
merit is crucially important for mixer in integrated front—end where the available linearity
is limited by the low power budget. Second, because the inputs to a multiplier enter at sep-
arate ports, there can be a high degree of isolation among all three signals (RF, L0, and IF).
Finally, the use of double balanced structure eliminates the LO frequency in output spec-
trum, which may have overloaded the subsequent stage because of the typically high value

of L0 magnitude. Furthermore, it can be shown that the IIP3 of double balanced structure

is twice that of the active single-balanced mixer [108].

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V”; _ _
VREL I I—I % ”'IF ’ ii
I i I
(a) (b)
+
IF
‘_ - + RF —
g? H i j]? KI: I I—IF—l +
:‘r; I; MRFl 1%:ng 1:0 m 1:
“DE MRFZPI— 3.! I.— > IF
_ :j m f H
MLOl MLOZ MLOi‘ MLO4 I——m—4 -
+ E , II 5 i.
L0 v - v r
" 63
<5
(C) (d)

Figure 2.6: Integrated Mixer Topologies: (3) Gilbert Cell [105]; (b) LC~Folded Gilbert
Cell [33]; (c) Triode-Biased Mixer [69]; and (d) Pass-Gate Mixer [66].

29

2.3.2.2 Topology improvement of Gilbert cell

Similar to the design Of low-power integrated LNA, the key issue in low-power
integrated mixer design is how to reduce power without degrading mixer RF characteris-
tics, particularly mixer linearity. And progress has been made in two trends to address this

issue.

The ﬁrst trend is to save power with reduced power supply voltage. The use of LC—
folding structure in Gilbert cell results in the mixer topology shown in Figure 2.6 (b), for
which supply voltage can be as low as 1 V [33]. Another advantage of Gilbert cell with LC-
folding is the increased linearity [33]. The major disadvantage of LC-folding Gilbert cell
scheme is that the LC tank has to be tuned exactly at RF input frequency, which is very dif-

ﬁcult for integrated LC implementation.

The second trend is to develop novel mixer scheme for low supply voltage and high
linearity. The key idea here is to use transistors biased in triode region that is conventionally
undesired. Consequently the supply voltage can be reduced and linearity improved. By
contrast, transistors in a Gilbert cell are typically biased in saturation region with emphasis
on reducing noise and switching nonlinearity [105]. One proposed mixer topology based
on triode-biased transistors is shown in Figure 2.6 (c), where transistors MLOl-4 serve as
multiplying stage and transistors MRFl—4 serve as transconductance stage [69]. Further
improvement has been proposed to implements LO switch with MOS pass gate transistors
as shown in Figure 2.6 (d) [66]. In this way, mixer power is further reduced because less

transistors are used when compared with the scheme in Figure 2.6 (c).

30

2.3.2.3 Design optimization of Gilbert cell
The most important part of design Optimization for integrated mixer is distortion
analysis, which analyzes nonlinear effects (e.g. intermodulation) and predicts IIP3 as well

as other linearity parameters.
Generally there are two ways to deal with distortion analysis in integrated circuits.

One way is to employ Taylor series to model the interrnodulation behavior as given

by following equation [3]
y(t) = ao+alx(t) +a2x(t)2+a3x(t)3+ , (2.2)

where x(t) is the input AC signal (e.g. vrfcos (orft ), and y(t) is the output AC signal.
Therefore in the case of two-tone interrnodulation, the value of IIP3 is determined by coef-
ﬁcients a2 and a3 . Such method has been known to predict mixer gain characteristics well

but not mixer IIP3 [97].

The other way is to model mixer interrnodulation behavior with Volterra series [96],

where the mixer output is represented in following form

y(t) = Al(s)x(t)+A2(sl,sz)x(t)2+A3(sl,sz,s3)x(t)3+ , (2.3)

where x( t) is AC input signal, and An( °) is the Volterra series coefﬁcient which is a linear
function of 11 number of frequencies. Though the way using Volterra series predicts mixer
interrnodulation behaviors very well, the computation involved is quite complicated and is
not suitable for hand calculation in design. For this reason, such approach mainly ﬁnds its

applications in RF simulators such as Cadence SpectreRF.

31

2.3.3 Integrated Continuous-Time Filter

Integrated ﬁlters are needed in front-end for image rejecting and channel selection.
General requirements of integrated ﬁlters are high Q, low insertion loss, high dynamic rage,

and low power consumption [82].

Conventionally there are two classes of integrated ﬁlters, which are switched-
capacitor (SC) ﬁlter and continuous-time (CT) ﬁlter [75]. The SC ﬁlter utilizes the excel-
lent matching characteristics of CMOS integrated capacitors, yet suffers from aliasing
effect. The CT ﬁlter does not has the aliasing problem of SC ﬁlter, yet suffers from the sig-
niﬁcant process variation of digital CMOS technology, because center frequency of the
ﬁlter heavily depends on the absolute values of integrated capacitors and transistors. Clas-
sic techniques for implementing integrated CT ﬁlter are active R-C ﬁlter [74] and active
MOSFET-C ﬁlter [77]. All these implementations of SC ﬁlters and CT ﬁlters employ inte-
grated Operational ampliﬁers (OpAmp’s). Hence the poor performance of integrated
OpAmp available in CMOS technology becomes a common limiting factor for conven-
tional analog ﬁlters. Because of the drawbacks mentioned above, the operating ﬁequency
range of conventional SC and CT ﬁlters in standard digital CMOS technologies is less than

1 MHz [5].

2.3.3.1 OTA-C continuous time ﬁlter
Recently CT ﬁlters implemented with operational transconductance ampliﬁers
(OTAs) and capacitors have received much attention due to its good performance in high-

frequency range [5,76]. A practical implementation of transconductor is called a OTA, and

32

integrated OTA-C bandpass ﬁlters in CMOS Operating at 10.7 MHz and 12 MHz have been

reported [78,1 10].

A typical ﬁrst-order IOWpass OTA-C ﬁlter is shown in Figure 2.7 (a) [5], where an
integrator is constructed by the capacitor and transconductor on the left, meanwhile the

transconductor on the right acts as an active resistor.

Three reasons account for the success of integrated OTA-C ﬁlter. First, the use of
OTA instead of OpAmp in the ﬁlter makes high-frequency operation possible due to the
low impedances of transconductor internal nodes [83]. Second, the use of OTA enables the
tuning of ﬁlter after fabrication [76]. Finally, the use of OTA relaxes output swing and dc-

gain requirements, hence reduces the power consumption [111].

General requirements of OTA are low power, low noise, and high linearity. For
active ﬁlter in integrated RF front-end for image rejecting, linearity is a particularly impor-
tant issue because of the signiﬁcant magnitude of ampliﬁed signal from previous gain

stages (LNA and mixer) that appears at ﬁlter input.

Compared with conventional passive RC ﬁlters, OTA-based active ﬁlters still suffer
from performance loss in several important aspects, which are increased power consump-
tion, degraded linearity, and reduced quality factor at high frequencies [79]. Low linearity
results from the inherent nonlinearity of transconductor and capacitor, meanwhile low Q is
mainly caused by the mismatching of integrated components. The key to reduce the perfor-
mance loss is to use OTA that behaves well at RF frequencies. Ideally such OTA should

have high DC gain, low noise, high output impedance, low input impedance, enough band-

width, and excellent linearity.

33

 

 

 

 

V2

 

 

 

(a) (b)

 

 

 

 

 

V2

 

 

 

 

 

 

 

(C) (d)

Figure 2.7: Integrated OTA-C Filter Topologies: (a) Classic [6]; (b) OTA [112]; (c)
Balanced [80]; and (d) Q-Enhanced [88].

34

Several efforts have been made to deal with the problems of integrated OTA-C ﬁl-
ter. In Figure 2.7 (b), a capacitor is connected in a feedback loop around the high gain
ampliﬁer which makes the input of the ampliﬁer to appear as a virtual ground [111]. In this
way, the requirement of output swing is relaxed, and linearity is improved. In Figure 2.7
(c), a balanced structure of transconductor cell is designed to cancel the second-order non-
linearity at the output [79]. In Figure 2.7 (d), negative conductor is used to boost the Q-

value of integrated OTA-C ﬁlter [87].

Among the proposed schemes of OTA for improving linearity, Nauta’s scheme in
Figure 2.8 [81] is attractive because of its good linearity and high quality factor
[83][106][3]. Being based on inverters, this balanced transconductor is very suitable for
low voltage applications; further, the absence of nodes internal to the transconductor
enables the straightforward implementation of advanced ﬁlter architectures, since the only
parasitic time constants introduced by the transconductor are those associated to the distrib-

uted nature of the transistor channels [109].

2.3.3.2 Complex analog ﬁlter

The use of low IF in RF front—end relaxes the requirement of channel selection ﬁlter
and reduces power consumption of analog electronics for IF signal processing [88]. Mean-
while troublesome effects such as DC offset, ﬂicker noise, and mixer LO feedthrough are
avoided. These advantages may, however, be offset by the expensive external bandpass
ﬁlter (BPF) required, since the high value of quality factor (Q) of image-rejecting ﬁlter
resulting from low IF can not be achieved with available integrated BPF, either passive or
active [45]. To reduce Q—value of needed BPF while maintaining a low IF, the image-reject-

ing function has to be performed on IF signal after the downconversion stage, when the

35

downconverted signal and image are the same in frequency yet opposite in phase. In this
way the required Q-value of BPF could be reduced to as low as three for Giga-Hz front-
ends [64]. To reject the image a complex analog ﬁlter that attenuates negative-frequency

components while keeping positive-frequency components has to be used.

There are two ways to build a complex analog ﬁlter: frequency translation [109] and
sequence asymmetric ﬁltering [94]. The ﬁrst way converts a low pass ﬁlter (LPF) into a
complex band pass ﬁlter (BPF) employing frequency translation. The second way attenu-
ates the input signal sequence Of negative phase using asymmetric polyphase network (also
called lattice). The frequency-nanslation-based approach has been popular since its design
process is similar to that of common LPF. However, the lattice-based approach has the
potential of achieving less power consumption than the frequency-translation one does.
The reason is that the gyrators heavily used in frequency-translation approach are no longer

needed in lattice-based approach.

Existing research efforts tend to construct analog complex ﬁlter using frequency-
translation approach based on operational transconductance ampliﬁer (OTA), and focus on
the design optimization Of LPF prototype needed, such as Butterworth LPF [64], or Che-

byshev LPF [109].

2.4 Research Topics

Though much progress has been made toward low power in the design of integrated
CMOS front-end, power consumption remains the major factor limiting the use of such
front-end in commercial portable communication applications. The problem here is how to

effectively reduce front-end power without degrading RF performance or increasing costs.

36

One promising solution is to develop novel ways of analyzing front-end to gain a good
understanding of front-end behavior at RF frequencies. Based on the analysis, efﬁcient
methods of design Optimization for low power can be developed without adding costs, as

have been shown by several previous attempts [54][57].

In this thesis work we investigate novel ways of analyzing front-end building blocks
by considering several factors that affect building-block performance signiﬁcantly, such as
the very low quality factor of integrated inductor. Effects of such factors have not been
properly accounted for in previous work on design analysis within the low-IF front-end
architecture we used in this thesis work. We further showe that good design analysis helps
develop novel topology for front-end building blocks. The tOpics investigated in the thesis

work are listed below.

1) Analyze the noise performance of RF CMOS LNA with integrated inductors of
very low (<10) quality factor. Develop method of noise-ﬁgure-constrained Optimization for

reducing LNA power.

2) Analyze the linearity performance of RF CMOS mixer implemented with Gilbert

cell. Develop new mixer topology for improving linearity.

3) Analyze the image-rejecting operation of complex analog ﬁlter based on asym-
metic polyphase network. Develop new way to implement the complex analog ﬁlter for

saving power.

37

 

 

 

 

 

 

 

 

 

T r-I BI— —i EH
L4 H H ’H
q - E _ j ._:

 

Figure 2.8: Nauta’s Transconductor [106].

38

DESIGN APPROACH

The proposed front-end employs the low-IF architecture shown in Figure 3.1 and
has three types of building block: low noise ampliﬁer (LNA), mixer, and complex analog
ﬁlter (CAF). The received RF signal is ﬁrst ampliﬁed by LNA, then is downconverted to
two quadrature signals I and Q with the mixers. The resultant I and Q signals at IF fre-
quency are ﬁltered by the CAF to reject the image. The L0 signals needed by mixers are

generated externally.

In proposed front-end the LNA employs CSID topology, the mixer is based on Gil-
bert cell, and the complex analog ﬁlter uses asymmetric polyphase network. Our proposed

methods for analyzing and designing the front-end building blocks are detailed below.

3.1 Low Noise Ampliﬁer

3.1.1 Tradeoff between Performance and Power

The ﬁrst step in LNA design for low power is to understand how the LNA perfor-
mance varies with power consumption. Particularly, short-channel effects of MOS transis-

tors have to be preperly considered.

As mentioned in Chapter 2, LNA performance is described by a set of parameters
including noise factor (or noise ﬁgure), gain, linearity, input/output matching, and reverse

isolation, etc. According to the Friis equation, however, the fundamental function of LNA

39

concerns only two parameters: noise factor and gain. The reason is that LNA noise factor
adds to the noise factor of front-end, and LNA gain reduces the noise contributions from
building blocks that follows LNA in receive path. Hence for simplicity without losing gen-
erality, our study here will focus on how the power consumption is related to noise factor
and voltage gain of LNA. This issue has not been treated well in the literature and an in-

depth discussion is worthwhile.

In following analysis we begin with the LNA that employs long-channel NMOS
devices, then study the LNA in the case of short-channel NMOS devices by considering

major shortchannel effects.

The input stage of CSID LNA determines noise factor the front-end, and is typically
implemented with a single NMOS transistor [54]. Meanwhile the output stage of LNA pro-
vides the input stage with a steady load to maintain a reasonable gain. Therefore the noise
factor and gain of LNA can be calculated using the small-signal equivalent circuit shown
in Figure 3.2, where the output stage is represented as an impedance ZL. Only the drain cur-
rent noise Of NMOS transistors is considered since it dominates the intrinsic noise of MOS
devices at RF frequencies [3]. The root mean square (RMS) value of input-referred drain
current noise is given by [54]

V2n,in,ch = 4leAf. (3.1)

gm

where k is Boltzmann’s constant, T is the absolute temperature in kelvins, yequals 2/3 for
long-channel NMOS devices in saturation, gm is device transconductance, and Af is the

noise bandwidth in hertz.

 

 

 

 

 

 

 

 

 

 

 

 

 

Complex IR Filter
V ‘ ..
I. '
D , E! w
°.__l
LNA '
Mixer I I
I:

 

Figure 3.1: Low-IF Architecture of Proposed Front-End.

 

 

Input Stage Output Stage
v, ,c L 3, L9; """"" L """"" if: """""" ,__, w

 

 

 

Figure 3.2: Generic Model of Input Stage of CSID LNA.

41

The device transconductance of long-channel NMOS devices is given by

2rd

, 3.2
WV... I )

 

gm = (ng-

where Pd is power consumption, Vgs is gate-source bias voltage, Vt is the threshold voltage

of NMOS devices, and Vdd is power supply voltage. For a given IC fabrication process, Vdd

and Vt are usually ﬁxed.

It follows that

 

(3.3)

The value of gate overdrive VgS—Vt is chosen only large enough tO keep the
NMOS transistor in active region, and changes little around several hundred millivolts
[105]. Hence for simplicity without losing much accuracy it is reasonable to assume that

the value of V gs — Vt is constant.

Referring to Figure 3.2, the minimum noise factor is

— —I—. (3.4)

Meanwhile the voltage gain is calculated by
|Av| = ngRLI‘ (3.5)
It follows from equation (3.3) that
3... °C Pd- (3.6)
Finally we have

42

cc Pd, (3.7)

A, 0: Pd. (3.8)

From above relations it is clear that higher power budget generally results in lower
noise factor and higher gain. To reduce the power, however, we would prefer the minimum
(or nearly minimum) power budget required to meet the design speciﬁcation. In practice
the tuning of AV is much easier than that of noise factor since the former is determined by
LNA input stage (gm) and LNA output stage (21), while the latter depends almost solely
on the characteristics of LNA input stage. Therefore the design of LNA is essentially to
Optimize design parameters such that the speciﬁed noise factor is achieved with minimum
power consumption and reasonable gain. Note that the gain of LNA output stage can be uti-
lized as an additional degree of freedom to compensate the gain loss resulting from the opti-

mization on LNA input stage.

So far our analysis is based on long-channel NMOS device model. For short-chan-

nel transistors, the preceding analysis is still valid and explanations follow.

The I—V characteristics Of short-channel NMOS devices with velocity saturation

effect is given by [105]

1
Id, short: Id, longl + 9V (1 ’ (3-9)
0

where I¢long is the drain current calculated with long-channel assumption, 0 is a small real

number between zero and unit, and Vod is the gate overdrive. It is easily seen from above

43

equation that in short-channel regime gm has weaker dependence on gate overdrive than it

does in longchannel regime, as is characterized by following relation

06

 

m l (7))
_.= — - . (3.10)
Pd (Vgs — Vt

With constant gate overdrive, the same relations between performance and power
can be drawn as those in equations (3.7) and (3.8). Two important Observations are made
here. First, while reduced gate overdrive can increase the value of (gm/Pd) effectively in
long-channel regime, such effect tends to diminish as the IC technology scales down, as is
shown in equation (3.10). The reason is that reduced channel length increases the strength
of horizontal electric ﬁeld in device channel, therefore the effect of velocity saturation
becomes signiﬁcant at lower drain-source voltage, and larger value of 0 is needed to model
such change of device behavior [105]. Second, it can be shown that the value of short-chan-

nel (gm/Pd) is smaller than that of long-channel, as illustrated by following equation

(gm/Pd)short= 1__ 9(Vgs _ Vt) . (3.11)
(gm/Pd)long 2

The typical value of 0 for 0.18-um process is 0.4 VI. For a gate overdrive of 0.4 V,

the value of short-channel (gm/Pd) is about 8% less than of long-channel.

Consequently, in short-channel regime the low power requirement is more stringent
due to the reduced (gm/Pd) ratio. This makes the development of low-power design meth-
odology even more desirable. On the other hand, the value of gm becomes less sensitive to

the change of Pd, therefore new methods to reduce power consumption have to be explored.

3.1.2 Noise Analysis

The circuit topology of CSID LNA to be studied is shown in Figure 3.3. As men-
tioned in Chapter 2, the classic method for noise analysis deals with the tradeoff between
induced gate noise and drain current noise of NMOS devices [54]. While this method works
well for LNA with external inductors, it has problem dealing with the design of integrated
LNA in CMOS. To see why, we ﬁrst note the fact that currently available integrated induc-
tors exhibit low values of quality factor between 3 and 10 [41]. Then it is seen from Figure
3.4 that with such integrated inductors a lower bound Of noise factor exists for LNA with

CSID topology:

RI
F . >1“? (3.12)

min

where R] is the series resistance of Lg. At the frequency of 900 MHz, the typical inductance
of Lg is 9nH, and quality factor is 3. In this situation Fmin is larger than 1.8 (2.5 dB)! Further
examination shows that the required inductance of Lg increases as the width of transistor
M1 decreases. Since the thermal noise from low-quality Lg directly adds to the LNA noise

factor, the impact of Lg overwhelms that of gate-induced noise as device width reduces.

As a result, we observe a new tradeoff dominating the design of integrated LNA in
CMOS, which is the tradeoff between gate inductor noise and drain current noise. Note that
the noises from integrated inductors Ls and Ld are ignored for simplicity since they do not
have signiﬁcant impact on LNA noise factor. For a detailed treatment of the new tradeoff,
we ﬁrst describe the transistor and inductor models involved in hand calculation, then

derive the noise factor of LNA as well as degree of input matching.

45

Vdd

 

 

Figure 3.3:

 

 

 

Figure 3.4: Small-Signal Equivalent Circuit for Noise and Gain Calculation in Classic
CISD LNA Design [55].

46

3.1.2.1 NMOS Transistor model

Recently the I-V model of NMOS transistor considering velocity saturation effect
has been widely used in the research on short-channel RF CMOS LNA design, where the
square-law model is in general considered inapprOpriate due to short-channel effects
[54,62]. However, it can be shown that for small gate overdrive the conventional square-
law I-V model still holds for short-channel transistors. As we will see shortly, for LNA with
CSID topology, large gate overdrive will result in the use of large integrated inductance,
which is not favorable due to the signiﬁcant degradation of LNA noise performance. So

that for simplicity, square-law equation is used in our work to model DC characteristics of

NMOS transistor

W 2

1
ID = inncoxl-J—“v(ml , (3.13)

where LC“ is effective channel length of transistor M1 in Figure 3.3, V0d is the gate over-
drive Of transistor Ml given by
V0d = Vgs—Vm, (3.14)
le is the threshold voltage of M1.
The power is given by
P = IDVdd , (3.15)
where Vdd is the supply voltage.

The small-signal model of NMOS transistor for hand calculation is shown in Figure

3.5, where

47

 

 

2

Cgs = ECOXWLefI’ (3.16)
W

gm = I’lnCOXL Vod' (3-17)
eff

The transition frequency of NMOS transistor, (DT , is given by

_gm_3un
(”T-C

 

V d. (3.18)
85 2I-zeff 0

Note that for speciﬁc fabrication process “’1‘ is solely determined by gate overdrive

when velocity saturation effect is ignored.

3.1.2.2 Integrated inductor model
For hand calculation, we use the circuit in Figure 3.6 to model the integrated induc-

tor, of which the quality factor is given by

Q = _ (3.19)

where RL is the series resistance Of integrated inductor. The typical value of QL is between

3 and 10 [45].

3.1.2.3 Derivation of noise factor
The small-signal circuit for the input stage of CSID LNA is shown in Figure 3.7.
The series resistance of L8 is ignored since usually the following relation holds for frequen-

cies of Giga-Hz:

3.20
Ls « Lg' ( )

48

 

 

 

Figure 3.5: Small-Signal Model of NMOS Transistor for Hand Calculation.

Figure 3.6: Simpliﬁed Model of Integrated Inductor.

49

The input impedance is given by

Zia = (Rtg+wTL,)+s(Lg+L,)+-l—. (3.21)
ng8

At the working frequency (00 the input impedance becomes real when

toga, + Ls)ch = 1. (3.22)
At this time the input resistance is given by

In

2. = Rin = RLg+rnTLs. (3.23)

Usually we want that Rin is equal to R8 for perfect input matching which is, how-
ever, difﬁcult to achieve in practice. To account for the effect of imperfect input matching,

we deﬁne the following relation

L
”La + wTLs = CR5, (3.24)

where C is a positive real number between unit and zero indicating the degree of imperfect

input matching.

At high frequencies, the series resistance of L8 accounts for a considerable portion
of input resistance of CSID LNA because of the low QLg. Particularly, too large integrated

Lg will make perfect input matching impossible when following relation holds

since C is always larger than unit. Therefore there exists an upper bound on the value of

Lg . which is around 18nH for too of 1.8G Hz and QLg of 4.

50

The small-signal circuit for calculating noise factor of CSID LNA is shown in
Figure 3.8. Here we consider only channel noise of transistor M1 and thermal noise of the

input stage. The noise of transistor M2 is ignored. The noise sources in the ﬁgure are char-

acterized by
vﬁs = 4kTRs, (3.26)
vim = 4kmLg = 4kT(%), (3.27)
rid = 4kTGgm), (3.28)

where gm is the transconductance of M1. The transconductance of LNA input stage at res-

onance is

G = g Q- = g (1)0(L5+Lg) . (3-29)
m m ”‘ mRS+RLg+toTLs

With equations (3.23) and (3.24) we have

G = gm , (3.30)
m (1+C)Rs(ongs

Finally the noise factor of LNA is given by the following equation

 

3kTgm 1
F = 1+[4kTRL + J
8 3G; 4kTRs
L (a) C )2
= 1+_%_E+Z(1+g)2Rs_Lg_aL, (3.31)
m

SL8

51

 

 

 

 

 

.. 1d
D? «:0
as
Cgs :: nggs
C— Vs
Ls

 

Figure 3.7: Small-Signal Circuit of Input Stage of CISD LNA.

 

 

2
v 0
vi“ ARIg RLg Lg v S 1d
" + W—{m—Ar—o - o
% \IJ ., g 4_
Rs g
mVs

 

 

IL
I
~
:1
a.

.54.:

 

Figure 3.8: Small-Signal Circuit for Calculating Noise Factor.

52

 

 

 

._ _-___.._.—_._.._

3.1.2.4 Noise-constrained optimization for minimum power

Based on preceding analysis, we propose a novel methodology for noise-con-
strained optimization Of CSID LNA design. The methodology is essentially to choose opti-
mum parameter set for LNA such that given noise factor could be achieved with minimum
power consumption. Further, it can be shown that the problem of noise-constrained optimi-
zation for minimum power is equivalent to that of power-constrained optimization for min-

imum noise.

As mentioned earlier in this chapter, the down-scaling of IC technology makes it
desirable to explore new ways to reduce LNA power besides the method based on noise-
power tradeoff. One promising way is to employ imperfect input matching. Though perfect
input matching is usually assumed in classic treatment of CISD LNA design [55], such
requirement may be relaxed for LNA in some wireless applications. In fact, the required
811 for Bluetooth LNA is only -10dB [104]. As will be shown, by adjusting S“ the noise
factor can be reduced without increasing power. Consequently a quantitative method,
which is not available in the literature, is needed to balance the tradeoff between the degree

of input matching and noise factor.

To gain good insight into the noise-constrained optimization, we rewrite the noise

factor in equation (3.31) as the function of Vod.

Let

L = Lg+Ls. (3.32)

tot

With equations (3.23-31) we have

53

 

 

V
L = i‘. (3.33)
to! K]
where
4 1
K = -ID —(n 22L . .
3D I11: 0 eff (3 34)

Note that K1 is linear function of ID.

Let
Kz- _ 1.—-—5 II" (3.35)
Leff
With equation (3.24), we have
Lg 2: Ltot (3.36)

With above equations, noise factor of LNA can be expressed in terms Of V0d as

below:

2
K1 1 + movod

_ . (3.37)
K2\/—3dK1RsQI-8

F~l+ 3-2(I+C) Rs—

With equations (333-337) the minimum noise factor given above can be rewritten

 

as
F ~ 1 + 1 67(1 + 2;)":8 (”3'6 (3.38)
min ~ . ROHZK? 2K3 4Qﬁg,
when

54

 

 

l 2K2R2 0.2
( +C) 1 5(2ng . (3.39)

devd :{
0 0,013! szo

Particularly, in the case of perfect input matching where C is equal to unit, the min-

imum noise factor can be rewritten as

 

0.6
to
PM“, = 1+2.9 ° , (3.40)
. - 0.2 0.2 0.4 0.6
R5 K1 K2 QLg
when
2 2 0.2
V = [M] . (3,41)
0d,§= I K (D
2 0

Since power consumption P is linear function of K1 , equation (3.38) indicates that
for given power budget there exists a minimum noise factor. In other words, there exists a
minimum power consumed by LNA to maintain a desired noise factor. To be speciﬁc, for

given noise factor F the minimum power required is given by

= _1_l.675(1+C)4 onoo

 

 

Pm = VDDID 2 (L1), QingR.’ (3.42)
when
K: K = [29 “’36 I. (3.43)
l i,min ' RELKg4QI0.g6(F_l

Several important observations are made from equation (3.42). First, lower noise
factor requires higher power consumption. This point agrees well with the conclusion from
our qualitative analysis earlier this chapter. Second, both the degree of input matching and

55

the quality factor Of integrated inductor can be used to reduce power for given noise factor.
This is evident from equation (3.42), where both lower C and higher QLg results in lower
Pmin . However, low C, which means degraded input matching, may cause troubles such as
antenna leakage and reduced gain. Meanwhile high QLg simply makes the design of inte-
grated inductor for use in LNA more difﬁcult. Nonetheless, equation (3.42) reveals new

ways to perform noise-constrained optimization on LNA toward low power.

Based on the preceding analysis, a four-step methodology for the design of low-

power noise-constrained LNA is formulated below.

1. LNA noise factor is determined from the design speciﬁcation of RF front-end.
This can be done with the help of Cadence SpectreRF tools using behavioral

simulation [115].

2. The bias and sizes Of NMOS transistor M1 of LNA input stage as shown in Fig-
ure 3.3 are calculated from equations (3.13), (3.39), and (3.43) by assuming C of
unit value and low inductor quality (e.g. QLg= 3). Values of L8 and Ls are
determined from equations (3.24), (3.32), and (3.33). Inductances and transistor
sizes in LNA output stage are chosen using the classic power-optimization
method [105]. The theory value of power consumption for the calculated param-
eters is determined from equation (3.42). Necessary simulation should be per-

formed to tune the design parameters.

56

3. To further reduce power, the value of L8 could be reduced to degrade input
matching. This means reduced value of C, and only the bias of transistor M1
needs to be changed as speciﬁed in equation (3.39). The resultant side effects
include degraded LNA linearity and reduced LNA gain. Therefore simulation is

needed to closely monitor the overall performance of LNA.

4. With design manpower permitting, higher quality factor Of integrated inductor
(e. g.QL 3= 8) can be used to achieve even less power. To do so, advanced design
techniques [116] for integrated inductor in CMOS have to be applied, and more

design time is expected.

3.1.2.5 Mapping from I; to 811

In practice the degree of input matching is represented as S, I, one of the scattering
parameters (S-parameters), instead of C in design speciﬁcation. Following discussion pre-
sents a way to convert C deﬁned by equation (3.24) to 811 which is the input reﬂection

coefﬁcient deﬁned by following equation [105]

Z —Z
S = L 0, .

 

where ZL is load impedance, and Z0 is the characteristic impedance of transmission line.

Assume that the source is perfectly matched to the other end of transmission line,

so that
20 = Rs' (3-45)

At resonance, the input stage of LNA exhibits pure resistance, so that

57

At this time

RID-R

 

 

 

ISllI = S - (3.47)
Rin + R5
The above equation can be rewritten as
ISIII = ——§l - . (3.48)

 

 

1+C

where C indicates the degree of input matching, and is deﬁned by equation (3.44). For

given Sll , possible values of C are

c, - (3.49)

C2 = l—tI—S—‘il. (3.50)

Based on previous analysis, Cl is always preferred for 811 calculation. Therefore
theory value of S] I could be estimated with equation (3.49). For example, in Bluetooth
applications 81 l is usually required to be less than -10dB, this translates to a minimum C
of 0.52. Consequently, C could be reduced to as low as 0.52 in exchange for reduced power

consumption.

58

3.2 Downconversion Mixer

3.2.1 Tradeoff between Performance and Power

Adopting the same rationale used for LNA analysis, we ﬁrst study how the mixer
performance changes with power consumption. As mentioned in Chapter 2, the most
important parameters of mixer performance include noise factor, conversion gain, and lin-
earity. A mixer typically exhibits noise factor much higher than that of LNA due to its non-
linear function of frequency manipulation which translates noise in multiple RF bands to
the IF signal band [90]. However, high noise factor is hardly a concern in mixer design
since the noise requirement of mixer can be greatly relaxed according to the Friis equation
with a properly-designed LNA. Furthermore, the use of a high-performance LO oscillator
could reduce the mixer noise effectively. Conversion gain of several st is normally
required for a mixer so that the LNA gain can be reduced to achieve better stability. For the
active mixer commonly used in integrated RF front end, the conversion gain is proportional
to the magnitude of LO signal, and little power is drawn from external LO source [70].
Therefore enough conversion gain can be achieved without increasing mixer power by

using a low-power LO oscillator with appropriate magnitude.

The key parameter of mixer performance that limits the reduction in power con-
sumption is linearity. This is because portable wireless applications typically requires the
use of high-linearity mixer, of which the linearity dominates that of RF front-end [108].
Meanwhile the already tight power budget of portable wireless applications makes it difﬁ-
cult to further reduce power without degrading mixer linearity, considering that better lin-

earity usually requires more power, and present methods for linearity analysis are either

59

unaccurate or complicated as mentioned in Chapter 2. Therefore good technique for linear-
ity analysis is needed in low-power mixer design to develop a good understanding of how

mixer linearity varies with power consumption.

Our work in this thesis gives a novel two«step approach to analyzing mixer linearity

in terms of power consumption, and details are given below.

3.2.1.1 Two-step approach for linearity analysis of mixer

One important observation in active mixer design is that MOS device is the only cir-
cuit component capable of performing frequency translation in an active mixer, hence its
linearity accounts for that of the RF front-end. By contrast, noise factor of LNA is deter—
mined by both circuit topology and MOS device noise. Consequently, the mixer linearity
is determined by the linearity of NMOS devices used, and can be studied with a two-step

approach described below (for simplicity only third-order intermodulation is discussed

here).

1. The input-referred interception point of third-order intermulation (IIP3) for

NMOS transistor that dominates the mixer linearity is derived.

2. The IIP3 of mixer is determined from that of NMOS transistor by use of a map-

ping circuit network.

The two-step approach is also illustrated in Figure 3.9. The ﬁrst step provides
insight on the tradeoff between IIP3 and power of NMOS device, whereas the second step
gives insight on the tradeoff between IIP3 and power of the mixer. In this way, lots of com-
plicated computation is saved, and the impacts that the NMOS devices have on the mixer

linearity in terms of intermodulation become clear.

60

(mm,

 

 

 

In put-Stage I
Network
_ .................. L 3191?; - ..
Leveli
Iramoa.
NMOS Tx J

 

 

Figure 3.9: Two-Level Design Approach.

lIDc)
‘IEI‘I,
.‘3 1 I M1

Vgs(t) _
\r

 

Figure 3.10: Input Stage of Gilbert Cell.

61

3.2.1.2 Derivation of IIP3 for NMOS device

One important source of nonlinearity the transistor exhibits is the velocity satura-

tion effect for short-channel devices, which is given by following equation [105]

2 1
I = MV -——-—, 3.51
D °dl+0V0d ( )

where V0d is gate overdrive voltage, 0 is a positive real number used to represent the

degree of velocity saturation. The value of 0 ranges from zero to unit. M is given by

1 W
M = ECOXUDE. (3.52)
Next we deﬁne
Vin = Vgs—V,, (3.53)

where Vgs the large-signal gate-source voltage Of NMOS device in Figure 3.10, and Vt is

threshold voltage of NMOS device.

To calculate IIP3, we represent the drain current 1D in power series shown below
ID = K0 + Klvin + szfn + 1(3va + ..., (3.54)
where Kll is the n-th coefﬁcient of power series.
With equations (3.51) and (3.54) we have

2 1 2 3
mm = Ko + KIVin + szin + K3Vin + .... (3.55)

In normal cases we have

0 < evin < 1, (3.56)

62

such that the Taylor expansion can be applied to the left term of equation (3.55). Hence

M(vfn — 0V?n + éezvfu + ...) = K0 + KlVin + szfn + 1(3an + .... (3.57)
It follows that

K0 = 0, (3.58)

Kl = , (3.59)

K2 = M, (3.60)

K3 = _Me, (3.61)

K4 = éMGZ. (3.62)

In the case of two-tone intermodulation, we have the following input
VIII = Vb, + Vrf(C0S0)rf1I + COS (Oral) , (3'63)

where Vb’ is the bias voltage.

Then it can be shown that magnitude of frequency component 0)rfl in output In is

given by

A = 2K2Vb'v,,. (3.64)

out,rfl

Magnitude of frequency component (2cos 0),“ t — cos (amt) is given by
3 3 , 3
ADULIM = ZK3vrf+ 3K4Vb Vrf. (3.65)

To calculate IIP3, we let

63

IAout.rflI = IAoutJMI' (3.66)

Finally we have

 

8 Vb,
IIP3 = A. = _*.. , _
where the condition
, 1
0 < V < — 3.68
b 29 ( )

usually holds.

Therefore better linearity in terms of IIP3 can be achieved with higher bias voltage,
which means higher power consumption. An important observation from equation (3.67) is

that for the same gate overdrive, the HP3 improves as the process scales down.

3.2.1.3 Derivation of IIP3 for mixer

After the IIP3 Of NMOS device is derived, the IIP3 of mixer can be determined with
a mapping circuit network. For the Gilbert mixer, the transconductance stage is the major
contributor to mixer nonlinearites [96], and its mapping circuit network is shown in Figure
3.11, where Z8 is used for source degeneration to improve mixer linearity. In practice, Z5

is implemented with either an inductor or a resistor.

Ignoring the gate current of NMOS transistor, the gate voltage is given by
Vg = V0d + Vt + 102s , (3.69)
where ID is given by equation (3.51).

Taking the second order approximation, Vg could be rewritten as

64

 

Figure 3.11: Source Degenerated Input Stage of Gilbert Mixer.

65

2 3
V8 = V0d + V, + MZS(V0d — 0Vod) . (3.70)
Generally it is difﬁcult to express ID in terms of V3 in a understandable way. Here
we use a novel approach to attack this problem.

The circuit of mixer input stage in Figure 3.11 is represented with the closed-loop
model shown in Figure 3.12. Part Of the output current ID is fed back to input V8 with a
feedback gain of F, then the difference between V8 and the feedback signal VD’ is pro-
cessed by a nonlinear function A(v) , whose output is further ﬁltered to remove all fre-

quency components except 00,,.
The input voltage is given by
Vg(t) = Vgo+vgcosw,,t. (3.71)
The output current is given by
ID(t) = IDo + idcos (1),,t. (3.72)
Since F(v) is a linear function of Zs ,
F(v) = Fsconstant. (3-73)
The feedback output is given by
VD(t) = FID = IDOR + idRcosw,ft. (3-74)
It follows that the transient gate-to-source voltage of NMOS transistor is given by

V0,,(t) = (V850 — IDOR) + (vg — idR)cos00,,t. (3.75)

66

filter

V,(t) ., ’ v36) I AM * 1010
V'Dtt) , -
II F(v) F

Figure 3.12: Nonlinearity Model of NMOS Transistor with Source Degeneration.

 

 

 

 

 

 

 

67

 

 

Note that in this model the nonlinearity of transconductance stage of mixer is intro-

duced by the nonlinearity of A(v).

Finally IIP3m,xc,, the estimated input-referred third-order interception point of

mixer, is given by

where IIP3NMOS is the input-referred third-order interception point of NMOS device.

Therefore the use of source degeneration in a mixer actually provides a negative
feedback loop that improves the HP3 of mixer. Nonetheless, the IIP3 of NMOS transistor
in transconductance stage fundamentally determines the mixer IIP3. Equation (3.76),
together with equation (3.67), provides an effective way to estimate mixer linearity in terms

of IIP3 from power budget.

3.2.2 TOpology Improvement of Mixer for High Linearity

Though the use of source degeneration technique improves mixer IIP3, it degrades
the mixer performance in terms Of gain compression. This point has never been mentioned

in the literature, and will be discussed below.

Denote the input-referred gain compression point of NMOS device by IGCPNMOS .
and assume A’(v) to be the ideal gain function of NMOS device without any nonlineari-
ties. Then according to the deﬁnition of gain compression point, the following relation

holds:

Meanwhile the transconductance of mixer is given by

68

 

_ Agvz 1

gm,mixer - I+A(V)Zs = 1‘41
A(v) s

(3.78)

Therefore IGCPmixer , the input-referred gain compression point of mixer, satisﬁes

the following equation

 

 

 

 

 

, z 0.891 1 . (3.79)
+ Z , + Z
A(IGCPmixcr) s A (IGCPmixcr) S
It follows that
0.12225 + , 1 z 1 . (3.80)
O.89lA(IGCPm,,e,) A(IGCPmixer)

Compare equation (3.80) with equation (3.77), it is clear that

IGCPmixer < IGCPNMOS. (3.81)

Therefore with the use of source degeneration the mixer linearity improves in terms

of intermodulation, yet suffers in terms of gain compression.

To alleviate the degradation of mixer gain compression point caused by source
degeneration. we propose a modiﬁed topology of Gilbert mixer. The idea is illustrated in
Figure 3.13, where an active resistor is used in place of ZS. The long-channel NMOS

device M2 gives active resistance

 

R(v) = 2M1V d. (3.82)

where M is a constant. Meanwhile the gain function in Figure 3.12 could be written to the

ﬁrst order approximation as

69

 

 

A(v) = KVo,l , (3.83)
where K is a constant determined by transistor bias point.

Therefore we can further write
A(v)R(v) = C. (3.84)

where C is a constant. Consequently, transconductance of the modiﬁed mixer is

g’m, mixer = AIL - A(v). (3.85)

l+A(v)Zs ‘ 1+C

 

It is seen from above equation that the new mixer topology does not have the trouble
of degradation in gain compression, meanwhile maintains the advantage of high IIP3.

Finally the complete topology Of improved Gilbert mixer is shown in Figure 3.14.

3.3 Complex Analog Filter

One key issue in RF receiver design is image-rejecting [3]. Given RF input x( t)
consisting of input signal at frequency (1),, and its image at frequency (Dim, we want to

downconvert the signal from (I),f to (0,, without introducing the image at (am, where
X(t) = VrfCOS (Drft + VimCOSwunt 9 (3'86)
mif = wlo — 0)rf = (Dim - (010 ' (3'87)

The conventional approach to rejecting the image is to ﬁlter x( t) before downcon-
version to remove the image at frequency coin, . Such approach, however, is not appropriate

for front-end using low-IF architecture, where the image is rejected after downconversron.

70

 

 

Figure 3.13: Transconductance Stage of Gilbert Cell with Active Degeneration.

IF Out

 

 

 

 

 

 

 

 

 

 

Figure 3.14: Modiﬁed Gilbert Cell.

71

Consider the output of mixer when no function of image-rejecting is performed

before downconversion:

v v v. v
'f locostnift + -%J%ost0,ft+ (3.88)

 

x’(t) = x(t)v,ocostn,ot =

For simplicity without losing generality, we omit the frequency components other
than (0,, resulting from frequency manipulation of mixer and complex ﬁlter throughout the
discussion in the rest of this chapter. From equation (3.88) it is clear that after downconver-
sion the signal spectrum overlaps that of the image. Consequently, the image can not be

attenuated with BPF ﬁlter in real domain.
To distinguish the image from the signal after downconversion, consider the mixer

output with LO signal of vlo sin (clot:

 

v v ,
x”(t) = x(t)v,osin(0,ot = _,__v,2v ——'—°sinu),,t— ”g l"srnor,,t-I- (3.89)

where the phase of IF signal is different from that of the image by the degree of 180.

As a result, if we mix x( t) with a pair of quadrature LO signals as shown in Figure

3.15, the resultant output can be written in complex form

y(t) = y1(t)+ij(t) = X(t)VIOCXP(jw10t)
(3.90)

_,__v,2v ——'°exp(ju),ft) + —'——v"; Vl——°exp(—j(0,,t) +.

It follows that the image contributes the frequency component of —(0if in the output,
whereas the signal contributes the frequency component Of 00,f as shown in Figure 3.16.
Therefore, a complex analog ﬁlter is needed to reject the image in the complex domain after

downconversion.

72

r+®—> me

I SimoLot
X(t) ...

j coswLot

+®———> YQ (I)

Figure 3.15: Downconversion with Quadrature LO Signals.

 

Image I Complex Filter

’—-‘

I ‘ .
l

I, Signal

LL.

0

   

 

 

Figure 3.16: Spectrum Translation in Complex Filtering.

73

As mentioned in Chapter 2, the complex analog ﬁlter (CAF) needed for image
rejection in low-IF front-end is conventionally implemented with frequency-translation
approach. Our work in this thesis explores the way of image rejection using asymmetric
polyphase network, which has the potential of achieving less power consumption than the
frequency-translation approach. In following discussion we ﬁrst analyze image-rejecting
operation of complex analog ﬁlter based on passive-RC implementation of asymmetric

polyphase network, then give an active OTA-C implementation of the ﬁlter.

3.3.1 Analysis of Image Rejection with Asymmetric Polyphase Network

3.3.1.1 Asymmetric polyphase network

A polyphase signal is a set of two or more vectors having the same frequency but
different in phase [17]. A polyphase signal is said to be symmetric if its vectors have the
same magnitude and are equally spaced in space. A positive polyphase signal has a clock-

wise phase order, while a negative sequence has an anti-clockwise phase order. The follow-
ing sequence is a example of positive and symmetric polyphase signal
{CXPUCDOJ CXPthkeXPthh-j“1900101 -
A N-phase polyphase network has N input ports and N output ports. One phase of
a generalized N-phase network is shown in Figure 3.17.

The open-load voltage gain referred to the k-th port of N-phase network is given by

V- Y +ex '0 Y
Hk(S) = k,OllI = 1 p0 ) 2.

(3.91)
Vk, in Y1"‘ Y2

 

 

A 4-phase passive-RC polyphase network is shown in Figure 3.18, where

74

 

Ik,Out

 

 

Vk,out

 

L e—Je Vk,out

 

Figure 3.17: One Phase of a Generalized N -Phase Network [94].

V1,in»——wa—«,—w V1,Out

V2411 V2,out

 

 

V3,in V3,Out

& I—
V4,in «4 «WA—0 V4,0ut

Figure 3.18: 4-Phase Passive RC Network.

 

 

 

 

 

75

—
WI—
0

(3.92)

Y2 = sC. (3.93)

Therefore the open-load voltage gain referred to the k-th port of network is given by

 

V .
HkIS) = vk,out ___ 1+ :x-péth)“, (3,94)
k,in

where

“t = RC . (3.95)

To show how the polyphase network could be used as complex analog ﬁlter, we

have the following result according to equation (3.94):

111,000) 2

Hk(-j(0)

 

= (l — sin 9(1)T)2 + (costitor)2 (3 96)
(1 + sin Gait)2 + (cos 0001)2

 

It follows that negative frequency components are attenuated for 0 < 0, whereas

positive frequency components are attenuated for 0 > 0.

3.3.1.2 Operation of complex analog ﬁlter based on polyphase network

To show how the 4-phase polyphase network could be used to perform image-

rejecting in the complex domain, consider the circuit conﬁguration in Figure 3.19, where

yitt) = Viz—mlexptiwift) + cxM-iwirm + 1923’! exp (jwift) + apt-imum . (3.97)

V V V- V
yltt) = Lgﬁl—iexptiwift)+icxp(-iw,ft)1 + "“ '°

TIiCXprift) -iexp(—iw”t)] . (3.98)

76

 

 

4—Phase Network

 

 

+ Vl,in Vl,out _° Y'.(I)+

+

 

y,(t) ”\P [‘0— V2,in V2,out _o y’Q(t)_

 

r\
O

V3,in V3,0ut —c Y'.(t)-

 

 

yQ(t) N

V4,in V4,0ut ——o Y'Q(t)+

O

 

 

 

Figure 3.19: Circuit Conﬁguration for Image Rejecting with 4-Phase RC Polyphase
Network.

77

 

The input of 4-phase network in Figure 3.19 can be represented as the sum of fol-

lowing symmetric polyphase signals

vrfvlo

 

 

 

Sm = 4 exptiwdt>{1.j.-1,-i}. (3.99)
8.42 = v'fv'°eXp(-jw,ft){l.-j,—l.—j}. (3.100)
S...) = n%’9xp<jm..t){1.4-1.1}. (3.101)
Sim,2 = vimv“’exp(—jm,,r){1,j,—1,—j}. (3.102)

Note that Sml and S”,2 are sequences of the signal, while Sim,1 and 31:11.2 are
sequences of the image. For image rejecting, we want to attenuate sequences of the image

while keeping sequences of the signal.

For Srf’, we have

 

 

9 = ’15:, (3.103)
HrfJI‘”) = 113:: (3.104)
For Sm2 we have
9=§, awn
1142(0) = 1,3311. (3.106)

78

 

 

 

For Sim,l we have

 

 

0 = ’5‘, (3.107)
Himjm) = 1132):. (3.108)
For Sim,2 we have
0 = —’§‘, (3.109)
Him,2((0) = 1132);. (3.110)

Consequently at frequency (00 = i, the image component is completely removed

from output signal in Figure 3.19.

Finally the output signals in Figure 3.19, which are quadrature signals with the

image removed, are given by
Y’im = Vim-V3,...) (3.111)

Y’Qa) = V4,out"'VZ,out' (3'112)

3.3.2 Active Implementation of CAF

The major obstacle to integration of passive-RC polyphase ﬁlter is the passive resis-
tors used. Therefore we propose a novel way to implement the active complex analog ﬁlter
by replacing passive resistor with active resistor constructed from operational transconduc-
tor ampliﬁer (OTA). Circuit topology Of the active resistor is shown in Figure 3.20 [5].

where the resistance is given by

79

 

 

 

 

Figure 3.20: Active Resistor with Transconductor [6].

80

R = —, (3.113)

and gm is the transconductance of OTA. Time constant (1) of such active ﬁlters can be

adjusted by changing bias condition Of OTAs after chip fabrication.

Compared with the frequency-translation implementation of CAF using OTAs and
capacitors, our proposed implementation has the advantage of low power consumption,
because no gyrators are needed. The disadvantage is weak out-band rejection, of which
impacts on ﬁlter performance could be alleviated by cascading several polyphase networks

and using high-perforrnance OTA, such as the Nauta's transconductor [81].

81

4 SIMULATION RESULTS

To demonstrate the effectiveness of the proposed design techniques in Chapter 3,
an integrated CMOS front-end was designed for 2.4-GHz Bluetooth applications. The
frontvend was laid out in TSMC 0.18-tlm CMOS technology with Cadence Virtuoso layout
editor. The parasitic parameters were extracted from the front-end layout for post-layout

simulation with Cadence SpectreRF tools.

This chapter describes the design process of the front—end, discusses some practical
issues involved, and compares the post-simulation results with those of a recently-reported
Bluetooth receiver IC in similar 0.18-ttm CMOS technology. The comparison shows that
our front—end implementation achieves less power consumption and better linearity, yet

worse image-rejection performance.

4.1 Design Speciﬁcation for Bluetooth Front-End

A Bluetooth receiver operates in the RF band from 2.400 GHz to 2.4835 GHz. The
channel bandwidth is 2 MHz. The required sensitivity is ~70 dBm for 0.1% bit-error-rate
(BER), which translates to a NF of 26dB and IIP3 of -l7.5 dBm. Image-rejection-ratio is
required to be at least 33 dB, and conversion gain 18dB to 22dB [65][114]. The power con-
sumption should be as small as possible. The input of front-end is required to be matched

to 50 Q with S“ no higher than -11 dB.

82

4.2 Circuit Design

The low-IF architecture in Figure 3.1 is used for the front-end that consists of LNA,
mixer, and complex analog ﬁlter. The LNA employs the cascode topology with inductive
source degeneration in Figure 3.3. The mixer employs the modiﬁed Gilbert cell topology
proposed in Figure 3.14. The complex analog ﬁlter for image rejection consists of two 4-

phase lattice-based ﬁlters in Figure 3.18 connected in series.

4.2.1 LNA

The ﬁrst step in designing LNA is to specify the key performance parameters. A
4.5-dB noise ﬁgure is stipulated for LNA to make sure the front-end noise ﬁgure is no less
than 26 dB as required by Bluetooth speciﬁcation. The gain is expected to be no less than

15 dB. And IIP3 should be higher than -17.5 dBm.

The second step is to apply the proposed noise-constrained design techniqes to
designing LNA of circuit conﬁguration in Figure 4.1. The curves shown in Figure 4.2 and
Figure 4.3 resulting from our work in Chapter 3 are helpful to simplify the design task.
From Figure 4.2, the chosen value for the on—chip inductor quality factor is 3.0, for which
a noise ﬁgure less than 2.7 dB can be achieved at 2.44 GHz with 2-mW power consump-
tion. To further save power and boost perforrnace, the input matching degree of LNA is
degraded to 0.9 according to Figure 4.3. To ﬁnd out if the proposed method provides
enough design accuracy, theory prediction and simulation results for Q of 3.0 are plotted in
Figure 4.4 and Figure 4.5. It is seen from Figure 4.4 that for power consumption between
4 mW and 12 mW, the predicted noise ﬁgure differs from simulated data by less than 0.5

dB. which is accurate enough for hand-design purpose. Power consumption less than 4 mW

83

is rarely found in practice for LNA in standard CMOS technology [I]. It is seen from Figure
4.5 that our method characterizes the tradeoff between noise ﬁgure and degree of input
matching very well. Therefore the prOposed design method gives theory prediction that

agree well with simulation results for power ranging from 4 mW to 12 mW.

The third step is to determine the bias and sizes of transistors as well as values of
inductances in the LNA. The smallest channel length (0.20 um) allowed by the technology
is used for all transistors in the LNA. The width of transistor M1 is carefully chosen to make
sure that the transistor works in weak saturation region. Particularly, the width of transistor
M2 is the same as the width of transistor Ml as a rule of thumb [105]. The gate overdrive

is determined with the help of the curve in Figure 4.6.

The ﬁnal step is to calculate values of the inductances used in LNA with equations
(3.24), (3.32), and (3.33). The values of the inductances used in practice are smaller than
those calculated because of the increased gate-source capacitance of NMOS device caused

by short-channel effects.

4.2.2 Mixer

First, the key performance parameters of mixer are speciﬁed. An IIP3 of -8 dBm is
stipulated for the mixer to make sure the front-end has good linearity. A conversion gain

no less than 3 dB is preferred. Noise ﬁgure should not exceed 15 dB.

Second, the modiﬁed topology for the Gilbert cell proposed in Chapter 3 is vali-
dated by simulating the circuits shown in Figure 4.7 and Figure 4.8. The mixer in Figure
4.7 employs the classic topology without source degeneration, whereas the mixer in Figure

4.8 is modiﬁed using active source degeneration as proposed in Figure 3.13. A third mixer

84

with 100—!) resistive source degeneration is also simulated. The three ports of mixer (LO,
RF, and IF) are carefully matched to 50 Q with input/output matching network as illustrated
in Figure 4.7 and Figure 4.8. The power of LO signal is 0 dBm. IIP3 points for three ver-
sions of mixer are simulated for input power ranging from -25 dBm to 10 dBm with Spec-
treRF PSS and PAC analysis modes. The simulated data is plotted in Figure 4.9. It is seen
from the simulation results that resistive degeneration improves the mixer IIP3 for low
power consumption (less than 1.5 mW in our case). However, for higher power consump-
tion, the linearity performance of mixer with resistive degeneration is no better than that
without any degeneration. The reason is that the voltage drop on the degenerating resistor
increases linearly as the drain current increases. Consequently the gate overdrive of
transconductance transistor tends to be reduced. Meanwhile the mixer with our proposed

technique has the best performance in terms of IIP3 among the three versions.

The disadvantage Of our proposed technique can also be observed in Figure 4.9. For
extremely low power consumption, the performance of active degeneration technique is
worse than that of resistive degeneration, because a minimum voltage drOp is required for

the degenerating transistor to work in active region.

Finally, a power consumption of 2 mW is chosen for the proposed mixer, which
results in a IIP3 of around -2 dBm as shown in Figure 4.10. Due to the difﬁculty for ana-
lyzing the mixer behavior in aspects such as noise ﬁgure and conversion gain, intensive

simulation work is used to determine the bias and sizes of transistors in the mixer.

85

4.2.3 Complex Analog Filter

Circuit conﬁguration for the complex analog ﬁlter is shown in Figure 4.11. The
transconductor cell is implemented with Nauta’s scheme in Figure 2.8. The phase differ-
ence between two input signals to the polyphase network is 90 degree to model the quadra-
ture output signals from downconversion mixers in Figure 3.15. The attentuation on both

the signal and the image is measured with transcient analysis.

For Bluetooth applications, the ﬁlter shall have a center frequency of 2 MHz and a
bandwidth of 2 MHz [65]. In the design we use the ﬁlter prototype in Figure 3.18. The
values of resistor and capacitor have to be carefully selected. A small resistor may overload
the preceding mixer stage and increase the power of transconductance cell, meanwhile a
large resistor makes transconductance cell sensitive to the process variation. In our case of
polyphase network ﬁlter, all resistors have the value of 80 k!) and all capacitors 1 pF. For
a resistance of 80 k9, the required transconductance of the transconductor cell is 12.5 [IS
according to equation (3.20). Such transconductance approximately translates to a drain

current of 50 11A for the technology in use.

Frequency responses of the designed ﬁlter for the signal and the image are shown
in Figure 4.12 (a) and in Figure 4.12 (b), respectively. The 3-dB bandwidth for the signal
is 2.5 MHz, and the gain is higher than 1 dB over the passband centered at 2 MHz. Note
that the simulated 3-dB bandwidth (2.5 MHz) is slightly larger than that required by the
Bluetooth speciﬁcation (2 MHz). This is to compensate the bandwidth loss caused by the
cascading of several polyphase networks for higher degree of image rejection. For the
image 13-dB attenuation is achieved over the 3-dB passband of the signal, which translates
to the image-rejection ratio (IRR) of 14 dB. Since the minimum requirement of IR for

86

Bluetooth applications is 33 dB [65], a cascaded network of at least three 4-phase
polyphase ﬁlters is needed to provide sufﬁcient image rejection. However, in the thesis

project only two ﬁlters are used due to the concern of design complexity.

4.2.4 Impedance Matching between Building Blocks in Front-End

One important issue in practical fronteend design is the impedance matching
between front-end building blocks, particularly the matching between LNA and mixer.
Conventionally the degree of input impedance matching is described by S 11 parameter, and
the degree of output impedance matching by 822 parameter. Assuming the characteristic
impedance is 50 Q, the simulated 822 values for LNA are plotted in Figure 4.13 for frequen-
cies from 2.4 GHz to 2.5 GHz, and the simulated S” values for mixer are plotted in Figure
4.14 for the same frequency range. From the ﬁgures it is clear that both LNA output and
mixer input exhibit capacitive characteristics. To achieve perfect impedance matching
between LNA and mixer, the LC network shown in Figure 4.15 is employed, for which a
0.39-pF capacitor and 1.3 nH inductor are used. Fortunately, the values of capacitor and
inductor are small enough for on-chip integration. With the impedance matching network

nearly perfect impedance matching is achieved as shown in Figure 4.16.

4.3 Post-Layout Simulation Results

The proposed integrated RF front end is laid out using Cadence Virtuoso in TSMC
0.18-ttm digital CMOS technology as shown in Figure 4.17. The post-layout simulation

results are summarized in Table 4.1.

87

Several Observations are made when comparing the simulated performance of the
front-end with the measured performance of a similar chip reported recently [114]. First,
the power consumption of our implementation is 20% less than that reported in the litera-
ture. This shows that our design techniques for low power are effective. Second, the linear-
ity of our implementation is much better than that reported in the literature. This is because
our implementation uses the proposed mixer topology as well as impedance matching net-
work between receiver building blocks. Third, our implementation has worse image-reject-
ing peforrnance than that reported in the literature. To solve this problem in the future,

three-stage cascaded ﬁlter should be used.

88

 

 

 

 

 

 

 

E——1>—W\/——m“——IE———l
Port 0 ‘ 3L8
4‘ 0.55 V
47

Figure 4.1: Circuit Conﬁguration for LNA Simulation.

89

 

 

 

(00 = 2.44 GHz

2.4 ‘ QL 3.0 Vdd = 1.8 V
TSMC 0.18 pm Process

  
 

 

 

 

6 8 10 12 14
Power (mW)

Figure 4.2: Minimum Noise Factor versus Power for Different Q-Value.

 

 

 

 

 

2.5 .
(t)0= 2.44 GHZ
Vdd = 1.8 V
QL = 3.0
TSMC 0.18 l1 m Process
2.3
2.1 _
1.9 0 51 ‘ 15
Power (mW)
Figure 4.3: Minimum Noise Factor versus Power for Different Degree of Input
Matching.

90

 

 

5 — Theory curve
0., '4’" Simulation curve

 

 

 

 

NF min (dB)
'1’

 

 

 

2 - -
l r _
0 l l L l L l

0 2 4 6 8 10 12 14

Power (mW)

Figure 4.4: Minimum Noise Figure versus Power with Perfect Input Matching.

 

‘<>

 

 

 

 

 

 

4 I — Theory curve , '
--°- - Simulated curve 9"
3.5 - -
A 3 _ I ‘ ‘ x ‘ d
a N
.525 (00 = 2.44 GHz t; < 1 ,
ID = 2.683 mA
E 2 _ QL = 3.0 q
TSMC 0.18 um Process
1.5 r ‘

 

 

 

—35 -3) -2'5 -20 —1‘5 -10 _é 0
511 (dB)

Figure 4.5: Minimum Noise Factor versus Power with Imperfect Input Matching.

91

 

NF (dB)

14

12

10

 

(0 =2.44 GHz ' ' '
_ (21:55 10:1'0 mA
V d d=l.8 V
_ TSMC 0.18 pm Process .
ID=3.0 mA
ID=5.0 mA
ID=7.0 mA
- \\

 

 

 

00 0.05 0.1 0.15 0.2 0.25 0.3 0.35

V0,, (V)

Figure 4.6: Noise Factor versus Gate Overdrive for Q=3.0.

92

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

i '2: =m 35
T“ l
Lomé—dT 1. l5 1- 1 M3 1?}?
M2
RF mf ' “ ‘ I'Lj. J,
I... .

 

 

 

Figure 4.7: Circuit Conﬁguration of Mixer without Degeneration.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IF
f m 5;
”Ti” ‘i *1 “*3
RB?“ *‘T I) I.
I E% Active Source
i ,’ Degeneration

Figure 4.8: Circuit Conﬁguration of Mixer with Active Degeneration.

93

 

 

 

 

 

 

 

 

 

 

 

 

- + - Mixer without degeneration
8 "' - .0 - e e a o e “
Mixer wrth resrstrve degeneration
- + - Mixer with proposed active degeneration
6 ~ .4" -
A ’ I * - ‘ 0
E 4 ~ " x ,- - -— — : -
- -9' '
m “ ———————
E 2
El " '
<4 ,'
0 ' g, ’4 ‘
II‘III’ III
—2 h o ’ I .., II F
+ - -+- ' ‘I‘ ~ - 4’
-4 ' ‘“ ' ‘ '
0 10 12

4 6 8
Power (mW)
Figure 4.9: Simulated HP3 Performance for Three Mixer Versions.

 

 

0.00 { IIP3=2.19 dBm /
- /

-20.0 ; .,..‘4":>‘-r”"

I -e-zre’Jj/I/f
dBm : / ./ '

- /./
- ///./
,9/

-80.0
-100 7 .....

-30 -20 prf (dBm) 10 20

Figure 4.10: Simulated IIP3 Curve for 2mW Mixer with Active Degeneration .

94

 

 

 

 

 

 

 

l—o

 

T

 

Quadrature
Input

 

 

 

 

 

Quadrature
Output

 

 

>83?

 

 

 

 

.L
L

 

 

 

>83?

 

 

 

 

 

 

_l_

T

 

 

A
A

 

 

 

 

 

I
T

 

 

Figure 4.11: Circuit Conﬁguration for Active Polyphase Filter Simulation.

95

 

 

 

 

 

 

 

 

 

 

 

Gain (dB)

 

 

 

 

 

 

 

 

 

 

 

 

2 4
Frequency (MHz)

(3)

 

 

 

 

 

Gain (dB)

 

 

 

 

-30

 

 

 

 

 

 

 

 

 

 

-40
2 4 6
Frequency (MHz)

0))

Figure 4.12: Simulated Frequency Response of 4-Phase Polyphase Filter with Nauta’s
Gm Cell: (a) Signal Gain; and (b) Image Gain.

 

96

 

 

 

 

'_-—-L---

 

 

 

 

 

 

 

 

 

 

 

Figure 4.14: S“ of Mixer for Frequencies from 2.4-GHz to 2.5-GHz.

97

 

b
a
I

 

 

 

 

"1 ' N on
LNA E 1:on : Mixer
"mile-Io; Kilt-chimﬁ'u'oiwork

Figure 4.15: Impedance Matching Network between LNA and Mixer.

 

 

 

 

 

 

 

Figure 4.16: S“ of Mixer with Impedance Matching Network for Frequencies from 2.4-
GHz to 2.5-GHz.

98

 

 

'nu'wvn
llllll
--_----

 

IR Filter

 

Figure 4.17: Front-End Layout.

Table 4.1: Post-Layout Simulation Results of MRFEC

 

 

 

 

 

 

 

 

 

MRFEC F. Beffa et al.[ 1 14]
Idd 3.0 mA 3.6 mA
Conversion Gain 18 dB 21.4 dB
Image Rejection Ratio 20 dB 28 dB
IIP3 -5.89 dBm -18 dBm
Noise Figure 8 dB 13.9 dB

 

100

 

CONCLUSIONS

This thesis deals with the problem of designing low-power monolithic receiver
front-end IC in standard digital CMOS technology for portable radio-frequency wireless
communication applications. Such design is difﬁcult largely because of the complicated
balances among power, speed, and linearity. Proper decisions have to be made to address
the balance issue at four design levels, namely, technology level, device level, building
block level, and architecture level. The designers have much more control over the design
at building-block level than they have at the other three levels. Therefore success of the
whole front-end design heavily depends on the design quality at building block level, which

entails various design techniques and circuit topologies.

This thesis has proposed effective design techniques and circuit topologies for low-
power RF front-end design in CMOS. The rationale behind the thesis work is that, for each
design problem we ﬁrst identify the major tradeoff involved, then develop methods or cir-
cuit styles to address such tradeoff. For integrated LNA, the major design tradeoff was
identiﬁed to be the balance among power, thermal noise of low-Q inductors, and channel
thermal noise of transconductance transistors. Therefore we proposed a novel method for
noise-constrained optimization of integrated CMOS LNA for low power. For integrated
Gilbert mixer in CMOS, the major design tradeoff was identiﬁed to be the balance between
power and linearity of mixer tranconductance stage. Therefore we proposed a novel method

to analyze the linearity performance of mixer transconductance stage, which lead to a novel

101

 

modiﬁed topology of Gilbert Cell. For integrated image-rejecting ﬁlter in CMOS, we did
not identify the major design tradeoff due to tight time budget for the thesis. Rather, we
explored a novel implementation of integrated image-rejecting ﬁlter, which is the asym-
metric polyphase network ﬁlter with Nauta’s transconductor.

An integrated CMOS front-end for 2.4-GHz Bluetooth applications has been
designed and laid out using the design techniques and circuit topologies proposed in this

thesis. The simulation results have shown that the frond—end power is signiﬁcantly reduced

 

compared with similar implementations in the literature. Meanwhile, the front-end perfor-
mance is still good except that image-rejection-ratio (IRR) fails to meet the Bluetooth
requirement. Better image rejecting could be achieved as long as we identify the major

design tradeoff for integrated complex ﬁlter and develop methods for optimization in

future.

In conclusion, this thesis presented several effective design techniques and circuit

topologies for the design of integrated CMOS front-end. Further, this study outlined a

number of interesting research topics for future research:

1. How to model the relationship between intrinsic IIP3 of NMOS device and that

of the whole mixer in a quantitative way.

2. How to identify the major tradeoff involved in the design of integrated image-

rejecting ﬁlter.

3. How to optimize the tradeoffs among building blocks of RF receiver for low

power and integrated implementation.

102

REFERENCES

[I] A. A. Abidi, “Low-Power Radio-Frequency IC’s for Portable Communications,”
Proc. of the IEEE, vol. 83, pp. 544-569, 1995.

C. E. Shannon, “A Mathematical Theory of Communication,” Bell System Techni-
cal Journal, vol. 27, pp. 623-656, 1948.

 

[2]

B. Razavi, RF Microelectronics, Prentice Hall, Prentice Hall, Upper Saddle River,

[31
NJ, 1998.

[4] K. Chang, I. Bahl, and V. Nair, RF and Microwave Circuit and Component Design
for “Wireless Systems, John Wiley & Sons, New York, 2002.

[5] R. A. Shuchman, J. D. Lyden, and D. R. Lyzenga, “Estimates of Ocean Wavelength
and Direction from X- and L-Band Synthetic Aperture Radar Data Collected During
the Marineland Experiment,” IEEE Journal of Ocean Engineering, vol. 8, pp. 90-96,

1983.

[6] T. N. Anderson, “Double-Ridge Waveguide for Commercial Airlines Weather Radar
Installation,” IRE Transactions on Microwave Theory and Techniques, vol. 3, pp. 2-

9, 1955.
[7] A. D. Kucar, “Mobile Radio: An Overview,” IEEE Communication Magazine, pp.
72-85, November, 1991.

[8] V. Perugini, “Any Time, Any Where: The Social Impact of Emerging Communica-
tion Technology,” IEEE Transactions on Professional Communication, vol. 39, pp.

4-15, 1996.
[9} P. Moore and P. Crossley, “GPS Applications in Power Systems. I. Introduction to
GPS,” Power Engineering Journal, vol. 13, pp. 33-39, 1999.
[10} W. W. Wu, “Satellite Communications,” Proceedings of the IEEE, vol. 85, pp. 998-
1010, 1997.
103

[11]

[12]

[13]

[14]

[15]

[16]

[17]

[18]

[19]

[20]

[21]

[22]

[23]

F. Behbahani et al., “A Fully Integrated Low-IF CMOS GPS Radio with On-Chip
Analog Image Rejection,” IEEE Journal of Solid-State Circuits, vol.37, pp. 1721-
1727, 2002.

G. B. Frank and M. D. Yakos, “Next Generation Digital GPS Receiver,” IEEE AES
Magazine, pp. 10-15, July, 1990.

J. E. Padgett, C. G. Gunther, and T. Hattori, “Overview of Wireless Personal Com-
munications,” IEEE Communication Magazine, pp.28-41, January, 1995.

F. Howett, “DECT — Beyond CT2,” IEE Review, vol. 38, pp. 263-267, 1992.

D. G. Leeper, “A Long-Tenn View of Short-Range “Wireless,” Computer, vol.34, pp.
39-44, 2001.

M. Wolf and D. Kreb, “Short-Range Wireless Infrared Transmission: the Link Bud-
get Compared to RF,” IEEE Wireless Communications, vol. 10, pp. 8-14, 2003.

P. Bhagwat, “Bluetooth: Technology for Short-Range Wireless Apps,” IEEE Inter-
net Computing, vol. 5, pp.96-103, 2001.

K. V. S. S. S. S. Sairam, N. Gunasekaran, and S. R. Reddy, “Bluetooth in Wireless
Communication,” IEEE Communications Magazine, vol. 40, pp.90-96, 2002.

J. D. Vriendt et al., “Mobile Network Evolution: A Revolution on the Move,” IEEE
Communications Magazine, vol .40, pp. 104-111, 2002.

J. T. Stonick, “RF Communication Systems,” Class Notes, online at http://
www.cce.orst.edu/~jts, 2000.

C. Raynaud et al., “High-Frequency Performance of Submicrometer Channel-
Length Sillicon MOSFET’s ,” IEEE Electron Device Letters, vol. 12, pp. 667-669,
1991.

B. Razavi, “RF CMOS Transceivers for Cellular Telephony,” IEEE Communica-
tions Magazine, v0. 41, pp.144-l49, 2003.

C. A. Warwick, “Trends and Limits in the “Talk Time” of Personal Communica-
tors,” Proceedings of the IEEE, vol. 83, pp. 681-686, 1995.

104

 

[24]

[25]

[26]

[27]

[28]

[29]

[30]

[31]

[32]

[33]

[34]

L. E. Larson, “Radio Frequency Integrated Circuit Technology for Low-Power
Mreless Communications," IEEE Personal Communications, vol.5, pp. 11-19,
1998.

A. A. Abidi, G J. Pottie, and W. J. Kaiser, “Power-Conscious Design of Wireless
Circuits and Systems,” Proceedings of the IEEE, vol. 88, pp. 1528-1545, 2000.

G. M. Blair, “Designing Low-Power Digital CMOS,” Electronics & Communica-
tion Engineering Journal, vol. 6, pp. 229-236, 1994.

P. H. Woerlee et al., “RF-CMOS Performance Trends,” IEEE Transactions on Elec-
tron Devices, vol.48, pp. 1776-1782, 2001.

A. Ajjikuttira, “A Fully-Integrated RFIC for Bluetooth Applications,” Solid-State
Circuits Conference, 2001. Digest of Technical Papers, ISSCC. 2001 IEEE Intema—
tional, pp. 198-199.

D. Pascoli et al., “A Single-Chip 1.8 GHz Image Reject RF Receiver Front-End
with Boot-Strapped Inductors”, Electronics, Circuits and Systems, 2002. 9th Inter-
national Conference on, vol. 1, pp. 15-18, 2002.

S. Sabouril, “A Single-Chip GaAs MMIC Image-Rejection Front-End for Digital
EurOpean Cordless Telecommunication,” Microwave Theory and Techniques, vol.
48. pp. 1318-1325, 2000.

Adiseno, M. Ismail, and H. Olsson, “A “Ede-Band RF Front-End for Multiband
Multistandard High-Linearity Low-IF \Vireless Receivers,” IEEE Journal of Solid-
State Circuits, vol. 37, pp. 1162-1168, 2002.

P. G. M. Baltus, “Optimizing RF Front End for Low Power,” Proceedings of the
IEEE, vol. 88, pp. 1546-1559, 2000.

E. Abou-Allam, J. J. Nisbet, and M. C. Maliepaard, “Low-Voltage 1.9-GHz Front-
End Receiver in 0.5-um CMOS Technology,” IEEE Journal of Solid-State Circuits,
vol. 36, pp. 1434-1443, 2001.

B. Razavi, “CMOS Technology Characterization for Analog and RF Design,” IEEE
Journal of Solid-State Circuits, vol. 34, pp. 268-276, 1999.

105

 

[35]

[36]

[37]

[38]

[39]

[40]

[41]

[42]

[43]

[44]

[45]

C. H. Diaz, D. D. Tang, and J. Sun, “CMOS Technology for MS/RF Soc,” IEEE
Transactions on Electron Devices, vol. 50, pp. 557-566, 2003.

J. N. Burghartz et al., “RF Potential of a 0.18-um CMOS Logic Device Technol-
ogy,” IEEE Transactions on Electron Devices, vol. 47, pp. 864-870, 2000.

E. Morifuji et al., “Future Perspective and Scaling Down Roadmap for RF CMOS,”
Proceedings of IEEE International Symposium on VLSI Technology, pp. 163-164,
1999.

C. S. Kim et al., “Gate Layout and Bonding Pad Structure of a RF n-MOSFET for
Low Noise Performance,” IEEE Electron Device Letters, vol.21, pp. 607-609, 2000.

Y. Cheng, et al., BSIM3v3.1 User’s Manual, Univerisity of California, Berkeley,
1997.

Y. Cheng et al., “High-Frequency Small Signal AC and Noise Modeling of MOS-
FETs for RF IC Design,” IEEE Transactions on Electron Devices, vol. 49, pp. 400-
408, 2002.

J. N. Burghartz, D. C. Edelstein, M. Soyuer, H. A. Ainspan, and K. A. Jenkins, “RF
Circuit Design Aspects of Spiral Inductors on Silicon,” IEEE Journal of Solid-State

Circuits, vol. 33, pp. 2028-2034, 1998.

J. R. Long and M. A. Copeland, “The Modeling, Characterization, and Design of
Monolithic Inductors for Silicon RF IC’s,” IEEE Journal of Solid-State Circuits, vol.

32, pp. 357-369, 1997.

C. P. Yue and S. S. Wong, “On-Chip Spiral Inductors with Patterned Ground
Shields for Si-Based RF IC’s,” IEEE Journal of Solid-State Circuits, vol. 33, pp.
743-752, 1998.

C.-C. Tang, C.-H. Wu, and S.-I. Liu, “Miniature 3-D Inductors in Standard CMOS
Process,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 471-480, 2002.

J. N. Burghartz, M. Soyuer, and K. A. Jenkins, “Microwave Inductors and Capaci-
tors in Standard Multilevel Interconnect Silicon Technology,” IEEE Transactions on
Microwave Theory and Techniques, vol. 44, pp. 100-104, 1996.

106

[46]

[47]

[43]

[49]

[50]

[51]

[52]

[53]

[54]

[55]

[56]

G. D. Alley, “Interdigital Capacitors and Their Application to Lumped-Element
Mircowave Integrated Circuits,” IEEE Transactions on Microwave Theory and
Techniques, vol. M'IT-18, pp. 1028-1033, 1970.

J. N. Burghartz, M. Soyuer, and K. A. Jenkins, “Integrated RF Components a SiGe
Bipolar Technology,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 1440-1445,
1997.

C. C. Lin et al, “A Full Cu Darnascene Metallization Process for Sub-0.18um RF
CMOS SoC High Q Inductor and MIM Capacitor Application at 2.4 GHz and 5.3
GHz,” Interconnect Technology Conference, 2001, pp. 113-115.

H. Samavati, A. Hajimiri, A. R. Shahani, G N. Nasserbakht, and T. H. Lee, “Fractal
Capacitors,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 2035-2041, 1998.

C.-M. Hung, Y.-C. Ho, I-C. Wu, and K. O, “High-Q Capacitors Implemented in a
CMOS Process for Low-Power Wireless Applications,” IEEE Transactions on
Microwave Theory and Techniques, vol. 46, pp. 505-511, 1998.

J. Hauptrnann, F. Dielacher, R. Steiner, C. C. Enz, and F. Krummenacher, “A Low-
Noise Ampliﬁer with Automatic Gain Control and Anticlipping Control in CMOS
Technology,” IEEE Journal of Solid-State Ciccuits, vol. 27, pp. 974-981, 1992.

C. Toumazou and S. M. Park, “Wideband Low Noise CMOS Transimpedance
Ampliﬁer for Gigahertz Operation,” [EB Electronics Letters, vol. 32, pp. 1194-1196,
1996.

A. N. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE Journal of
Solid-State Circuits, vol. 31, pp. 1939-1944, 1996.

D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,”
IEEE Journal of Solid-State Circuits, vol. 32, pp. 745-759, 1997.

C.-Y. Wu and S.-Y. Hsiao, “The Design of a 3-V 900-MHz CMOS Bandpass
Ampliﬁer,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 159-168, 1997.

A. R. Shahani, D. K. Shaeffer, and T. H. Lee, “A 12-mW Wide Dynamic Range
CMOS Front-End for a Portable GPS Receiver,” IEEE Journal of Solid-State Cir-

cuits, vol.32, pp. 2061-2070, 1997.

107

[57]

[58]

[59]

[60]

[61]

[62]

[63]

[64]

[65]

[66]

[67]

H. Samavati, H. R. Rategh, and T. H. Lee, “A S-GHz CMOS Wireless LAN
Receiver Front End,” IEEE Journal of Solid-State Circuits, vol. 35, pp.765-772,
2000.

M. Harada, T. Tsukahara, J. Kodate, A. Yamagishi, and J. Yamada, “2-GHz RF
Front-End Circuits in CMOS/SIMOX Operating at an Extremely Low Voltage of
0.5V,” IEEE Journal of Solid—State Circuits, vol.35, pp. 2000-2004, 2000.

G. Grarnegna, M. Paparo, P. G. Erratico, and P. D. Vita, “A Sub-l-dB NF +- 2.3-kV
BSD-Protected 900-MHz CMOS LNA,” IEEE Journal of Solid-State Circuits, vol.
36. PP. 1010-1017, 2001.

F. Gatta, E. Sacchi, F. Svelto, P. Vilmercati, and R. Castello, “A 2-dB Noise Figure
900-MHz Differential LNA,” IEEE Journal of Solid-State Circuits, vol. 36, pp.
1444-1452, 2001.

P. Andreani and H. Sjoland, “Noise Optimization of an Inductively Degenerated
CMOS Low Noise Ampliﬁer,” IEEE Transactions on Circuits and Systems 11: Ana-
log and Digital Signal Processing, vol. 48, pp. 835-841, 2001.

J.-S. Goo, H.-T. Ahn, D. J. Ladwig, Z. Yu, T.H. Lee, and R. W. Dutton, “A Noise
Optimization Technique for Integrated Low-Noise Ampliﬁers,” IEEE Journal of
Solid-State Circuits, vol. 37, pp. 994-1002, 2002.

Q. Huang, P. Orsatti, and F. Piazza, “GSM Transceiver Front-End Circuits in 0.25-
um CMOS,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 292-303, 1999.

W. Sheng et al., “A 3-V, 0.35-um CMOS Bluetooth Receiver IC,” IEEE Journal of
Solid-State Circuits, vol. 38, pp. 30-42, 2003.

J. Ryynanen et al., “An RF Front-End for the Direct Conversion WCDMA
Receiver,” RFIC Symposium, 1999 IEEE, pp. 21-24, 1999.

J. Crols and M. S. J. Steyaert, “A 1.5 GHz Highly Linear CMOS Downconversion
Mixer,” IEEE Journal of Solid-State Circuits, vol.30, pp. 736-742, 1995.

A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, and A. A. Abidi, “A 1 GHz CMOS
RF Front-End IC for a direct-conversion wireless receiver,” IEEE Journal of Solid-
State Circuits, vol. 31, pp. 880-889, 1996.

108

. [68]

[69]

[70]

[71]

[72]

[73]

[74]

[75]

[76]

[77]

[78]

H. M. Wang, “A 1-V Multigigahertz RF Mixer Core in 0.5-um CMOS,” IEEE Jour-
nal of Solid-State Circuits, vol.33, pp. 2265-2267, 1998.

F. Svelto, M. Conta, V. Della Torre, and R. Castello, “A Low-Voltage Topology for
CMOS RF Mixers,” IEEE Transactions on Consumer Electronics, vol. 45, pp. 299-
309, 1999.

P. J. Sullivan, B. A. Xavier, and W. H. Ku, “Doubly Balanced Dual-Gate CMOS
Mixer,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 878-881, 1999.

M. S. J. Steyaert, J. Janssens, B. de Muer, M. Borremans, and N. Itoh, “A 2-V
CMOS cellular Transceiver Front-End,” IEEE Journal of Solid-State Circuits,
vol.35, pp. 1895-1907, 2000.

B. Razavi, “A 5.2-GHz CMOS Receiver with 62-dB Image Rejection ,” IEEE Jour-
nal of Solid-State Circuits, vol.36, pp. 810-815, 2001.

H. Sjoland, A. Karimi-Sanjaani, and A. A. Abidi, “A Merged CMOS LNA and
Mixer for a WCDMA Receiver,” IEEE Journal of Solid-State Circuits, vol.38, pp.
1045-1050, 2003.

M Banu and Y. Tsividis., “Fully Integrated Active RC Filters in MOS Technology,”
IEEE Journal of Solid-State Circuits, vol. SC-18, pp. 644-651, 1983.

H. Khorramabadi and P. R. Gray, “High-Frequency CMOS Continuous-Time Fil-
ters,” IEEE Journal of Solid-State Circuits, vol. 8019, pp. 939-948, 1984.

M. Banu and Y. Tsividis, “An Elliptic Continuous-Time CMOS Filter with On-Chip
Automatic Tuning,” IEEE Journal of Solid-State Circuits, vol. SC-20, pp. 1114-
1121, 1985.

J. M. Khoury and Y. P. Tsividis., “Analysis and Compensation of High-Frequency
Effects in Integrated MOSFET-C Continuous-Time Filters,” IEEE Transactions on
Circuits and Systems, vol. CAS-34, pp. 862-875, 1987.

Y.-T. Wang and A. A. Abidi., “CMOS Active Filter Design at Very High Freuen-
cies,” IEEE Journal of Solid-State Circuits, vol.25, pp. 1562-1574, 1990.

109

[79]

[80]

[81]

[82]

[83]

[84]

[85]

[86]

[87]

[88]

[89]

W. M. Snelgrove and A. Shoval, “A Balanced 0.9-um CMOS Transconductance-C
Filter Tunable Over the VHF Range,” IEEE Journal of Solid-State Circuits, vol. 27,
pp. 314-323, 1992.

A. M. Durham, J. B. Hughes, and W. Redman-White, “Circuit Architectures for
High Linearity Monolithic Continuous-Time Filtering,” IEEE Transactions on Cir-
cuits and Systems 11: Analog and Digital Signal Processing, vol.39, pp. 651-657,
1992.

B. Nauta, “A CMOS Transconductance-C Filter Technique for Very High Frequen-
cies,” IEEE Journal of Solid-State Circuits, vol.27, pp. 142-153, 1992.

J. A. Macedo and M. A. Copeland, “A 1.9-GHz Silicon Receiver with Monolithic
Image Filtering,” IEEE Journal of Solid-State Circuits, vol.33, pp. 378-386, 1998.

E. Sanchez-Sinencio and J. Silva-Martinez, “CMOS Tansconductance Ampliﬁers,
Architectures and Active Filters: a Tutorial,” IBE Proceedings on Circuits, Devices,
and Systems, vol. 147, pp. 3-12, 2000.

H. Voorman and H. Veenstra, ”Tunable Hi gh-Frequency Gm-C Filters,” IEEE Jour-
nal of Solid-State Circuits, vol.35, pp. 1097-1108, 2000.

F. Behbahani, Y. Kishigarni, and A. A. Abidi , “CMOS Mixers and Polyphase Filters
for Large Image Rejection,” IEEE Journal of Solid-State Circuits, vol.36, pp. 873-
887, 2001.

J. B. Hughes, A. Spencer, A. Worapishet, and R. Sitdhikom, “1 mW CMOS
Polyphase Channel Filter for Bluetooth,” IBE Proceedings on Circuits, Devices and
Systems, vol.l49, pp. 348-354, 2002.

F. Dulger, B. Sanchez-Sinencio, and J. Silva-Martinez, “A 1.3-V S-mW Fully Inte-
grated Tunable Bandpass Filter at 2.1 GHz in 0.35-um CMOS,” IEEE Journal of
Solid-State Circuits, vol.38, pp. 918-928, 2003.

J. Crols and M. S. J. Steyaert, “A Single-Chip 900 MHz CMOS Receiver Front-End
with a High Performance Low-IF Topology,” IEEE Journal of Solid-State Circuits,
vol.30, pp. 1483-1492, 1995.

W. R. Curtice, “Nonlinear Analysis of GaAs MESFET Ampliﬁers, Mixers, and Dis-
tributed Ampliﬁers Using the Harrnonic Balance Technique,” Microwave Theory
and Techniques, vol.35, pp. 441-447, 1987.

110

[90] H. Darabi and A. A. Abidi, “Noise in RF-CMOS Mixers: a Simple Physical
Model,” IEEE Journal of Solid-State Circuits, vol.35, pp. 15-25, 2000.

[91] H. Darabi et al., “A 2.4-GHz CMOS Transceiver for Bluetooth,” IEEE Journal of
Solid-State Circuits, vol.36, pp. 2016-2024, 2001.

[92] R. Fujimoto, K. Kojima, and S. Otaka, “A 7-GHz 1.8-dB NF CMOS Low-Noise
Ampliﬁer,” IEEE Journal of Solid-State Circuits, vol.37, pp. 852-856, 2002.

[93] S. H. Gala], H. F. Ragaie, and M. S. Tawﬁk, “RC Sequence Asymmetric Polyphase
Networks for RF Integrated Transceivers,” IEEE Transactions on Circuits and Sys-
tems 11: Analog and Digital Signal Processing, vol.47, pp. 18-27, 2000.

[94] M. J. Gingell, “Single Sideband Modulation Using Sequence Asymmetric
Polyphase Networks,” Electrical Communication, vol.48, pp. 21-25, 1973.

[95] S. Kang, B. Choi, and B. Kim, “Linearity Analysis of CMOS for RF Application,”
IEEE Transactions on Microwave Theory and Techniques, vol.51, pp. 972-977,
2003.

[96] L. F. Keng and R. G Meyer, “High-Frequency Nonlinearity Analysis of Common-
Emmitter and Differential-Pair Transconductance Stages,” IEEE Journal of Solid-
State Circuits, vol.33, pp. 548-555, 1998.

[97] S. A. Maas, “Two-Tone Interrnodulation in Diode Mixers,” IEEE Transactions on
Microwave Theory and Techniques, vol.38, pp. 1964-1971, 1990.

[98] P. van Zeijl et al., “A Bluetooth Radio in 0.18-um CMOS,” IEEE Journal of Solid-
State Circuits, vol.37, pp. 1679-1687, 2002.

[99] S. Wu and B. Razavi, “A 900-MHz/ 1.8G-Hz CMOS Receiver for Dual-Band
Applications,” IEEE Journal of Solid-State Circuits, vol.33, pp. 2178-2185, 1998.

[100] A. Zolfaghari and B. Razavi, “A Low-Power 2.4-GHz Transmitter/Receiver CMOS
IC,” IEEE Journal of Solid-State Circuits, vol.38, pp. 176-183, 2003.

[101] L. Der and B. Razavi, “A 2-GHz CMOS Image-Reject Receiver with LMS Calibra-
tion,” IEEE Journal of Solid-State Circuits, vol.38, pp. 167-175, 2003.

111

[102] T. Yarnawaki et al., “A 2.7-V GSM RF Transceiver 1C,” EBB Journal of Solid-
State Circuits, vol.32, pp. 2089-2096, 1997.

[103] F. Piazza and Q. Huang, “A 170 MHz RF Front-End for ERMES Pager Applica-
tions,” EEB Journal of Solid-State Circuits, vol.30, pp. 1430-1437, 1995.

[104] Bluetooth Speciﬁcation Version 1.0 B.

[105] T. H. Lee, The Design of CMOS Radio-Freqency Integrated Circuits, Cambridge
University Press, 1998.

[106] B. Nauta, Analog CMOS Filters for Very High Frequencies, Kluwer Publishers,
1993.

[107] H. T. Friis, “Noise Figures of Radio Receivers,” Proceedings of the IRE, vol. 32,
pp. 419-422, 1944.

[108] B. Leung, VLSI for \Vrreless Communication, Prentice Hall, 2002.

[109] P. Andreani, S. Mattisson, and B. Essin, “A CMOS Gm-C Polyphase Filter with
High Image Band Rejection,” Proceedings of European Solid-State Circuits Confer-

ence, pp. 419-422, 2000.

[110] A. Tajalli, and S. M. Atarodi, “Design considerations for a 1.5-V, 10.7-MHz band-
pass Gm-C ﬁlter in a 0.6-um standard CMOS technology,” Proceedings of the 2003
International Symposium on Circuits and Systems, vol. 1, pp. 521-524, 2003.

[111] S. Lindfors, K. Halonen, and M. Ismail, “A 2.7-V elliptical MOSFBT-only ng-
OTA ﬁlter”, EBB Transactions on Circuits and Systems 11: Analog and Digital Sig-

nal Processing, vol. 47, pp. 89-95, 2000.

[112] K. Lee et al., “A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless
local loop using multiphase reduced frequency conversion technique,” EBB Journal
of Solid-State Circuits, vol. 36, pp. 800-809, 2001.

[113] F. Beffa, R. Vogt, W. Bachtold, E. Zellweger, and U. Lott, “A 6.5-mW Receiver
Front-End for Bluetooth in 0.18-m CMOS,” Proceedings of 2002 EBB Radio Fre-

quency Integrated Circuits Symposium, pp. 391-394, 2002.

112

 

[114] G R. Aiello and G D. Rogerson, “Ultra-Wideband VVrreless Systems,” EBB Micro-

wave Magazine, vol. 4, pp. 36-37, 2003.
[115] --, “Behavioral Modeling of RF Circuits in Spectre,” Cadence SprectreRF Docu-
mentation, 1999.

Circuit Model for On-Chip Spiral

[116] Y. Cao et al., “Frequency-Independent Equivalent-
. 38, pp. 419-426, 2003.

Inductors,” EEE Journal of Solid-State Circuits, vol

113

 

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