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This is to certify that the
thesis entitled

Analysis and Design of Post-CMOS Thermally Controlled Biosensor
Array Microsystems

presented by

Nathan Andrew Dotson

has been accepted towards fulfillment
of the requirements for the

Master of degree in Electrical
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ANALYSIS AND DESIGN OF POST-CMOS THERMALLY CONTROLLED
BIOSENSOR ARRAY MICROSYSTEMS

By

Nathan Andrew Dotson

A THESIS

Submitted to
Michigan State University
In partial fulfillment of the requirements
for the degree of

MASTER OF SCIENCE
Department of Electrical and Computer Engineering

2004

ABSTRACT

ANALYSIS AND DESIGN OF POST-CMOS THERMALLY CONTROLLED
BIOSENSOR ARRAY MICROSYSTEMS

By
Nathan Andrew Dotson

A post-CMOS design and fabrication methodology has been investigated
for the generation of a microsystem which supports a protein-based biosensor
array with thermal control. Implementation of this microsystem design requires a
clear understanding of the various layers and their role in CMOS processing
technology, especially when the MEMS structures are to be fabricated post-
CMOS. In this work, cost-effective post-CMOS design and fabrication
methodology has been developed utilizing an experimentally-derived
understanding of the various CMOS layers in the AMI CSF/N 0.5um process
available through the MOSIS service. Derived techniques have been applied to
the design of thermally isolated biosensor sites for fabrication on MOSIS
integrated circuit die. A study of the laws governing heat transfer has been
completed for proper integration of temperature control to the designed biosensor
sites. Necessary circuitry for the control and design of the thermal system has
been designed and is discussed in this work. The results of this thesis work
enable the construction of thermally controlled biosensor array microsystems

through basic MEMS fabrication steps.

To my grandfather,
James Bloom
and
to my wife,

Kerry

iii

Acknowledgements

I would first like to express my sincere gratitude to Dr. Mason, for his guidance,
advice and encouragement over the three years of my graduate work at Michigan State
University. Dr. Mason has been extremely patient and understanding throughout my
research and has helped me work through frustrations and disappointments. He has
helped me continue on, completing work that seemed overwhelming over a year ago.
The opportunity to achieve my research goals with the level of academic freedom
Professor Mason has allowed was a hard adjustment to make initially, but one that in
retrospect has proven invaluable.

I am also grateful for the much needed advice and resources that were provided
by both Dr. Worden and Dr. Hogan. The opportunity to stop by almost any time and
receive pointers, especially in the area of heat transfer, proved to be a great helping hand
in my understanding and completion of this work. I would also like to extend my thanks
to Dr. Aslam for his contributions in the area of MEMS. The courses he has made
available and his willingness to provide advice at most any time have encouraged my
work and allowed me to achieve my goals.

I would like to thank everyone in the Amsac research group. The hours of help
and assistance from Peter Kim, in the cleanroom and out, can never be repaid, but will
always be remembered. J ichun and Junwei were always there as great examples of how
research should be conducted and were ready and willing to help in any situation.

I thank my parents for all of their support and encouragement, without them none

of this would have been possible. Whenever I have been in need, there was always

iv

somewhere for me to turn no matter what the situation and I am extremely grateful for
that.
I would finally like to thank the ECE Department at Michigan State University for

the support and opportunity to further my education through research and coursework.

TABLE OF CONTENTS

LIST OF FIGURES ....................................................................................................... ix
LIST OF TABLES ........................................................................................................ xii
LIST OF TABLES ........................................................................................................ xii
Chapter 1. Introduction ....................................................................................................... 1
1.1 Motivation ................................................................................................................. 2
1.2 Previous Research ..................................................................................................... 3
1.3 Summary ................................................................................................................... 3
Chapter 2. CMOS Post-Fabrication Processing and Heat Transfer Background ............... 5
2.1 Post CMOS Processing ............................................................................................. 6
2.1.1 Photolithography ................................................................................................ 7
2.1.2 Film Deposition ............................................................................................... 11
2.1.3 Etching Techniques .......................................................................................... 14
2.2 Basic Heat Transfer Analysis .................................................................................. 18
2.2.1 Conduction ....................................................................................................... 18
2.2.2 Convection ....................................................................................................... 20
2.2.3 Radiation .......................................................................................................... 20
2.3 Material Properties Affecting Heat Transfer .......................................................... 21
2.3.1 Thermal Conductivity of Solids ....................................................................... 21
2.3.2 Thermal Conductivity of Liquids ..................................................................... 22
2.3.3 Thermal Conductivity of Gases ....................................................................... 22
2.3.4 Density ............................................................................................................. 22

vi

2.3.5 Specific Heat .................................................................................................... 23

2.3.6 Thermal Diffusivity ......................................................................................... 24
2.4 One-Dimensional Steady-State Conduction ........................................................... 25
2.4.1 General Conductive Energy Equation ............................................................. 25
2.4.2 Plane Wall Fixed Surface Temperatures .......................................................... 28
2.5 Thermal Equivalent Circuit ..................................................................................... 30
2.5.1 Thermal Resistance .......................................................................................... 33
2.5.2 Thermal Boundary Layer: Flat Plate ................................................................ 33
2.5.3 Heat Capacity of a Polysilicon Resistor ........................................................... 36
2.5.4 Temperature Coefficient of Resistance ............................................................ 36
2.6 Self-Heating Limitations in Sensor-Resistors ......................................................... 37
2.7 Verification of Thermal Equivalent Circuit Analysis ............................................. 38
2.8 One Dimensional Systems: Transient Analysis Fixed Surface Temperature ......... 38
Chapter 3. MOSIS Post-Processing and Thermal Analysis of Biosensor Array Sites ..... 40
3.1 Proposed MEMS Structures .................................................................................... 41
3.2 MOSIS Post-CMOS Processing ............................................................................. 43
3.2.1 Photolithography .............................................................................................. 44
3.2.2 MOSIS Post-CMOS Metal Deposition ............................................................ 46
3.2.3 MOSIS Post-CMOS Etching ........................................................................... 46
3.6 Simulation and Heat Transfer Analysis Results for Isolation Structures ............... 51
3.6.1 Validation of Heat Transfer Analysis .............................................................. 52
3.6.2 Resistor Value for Heating Element ................................................................ 56
3.6.3 Simulation Results and Comparison for Possible Structures ........................... 58

vii

Chapter 4: Biosensor Array Microsystem ........................................................................ 61

Chapter 4: Biosensor Array Microsystem ........................................................................ 61
4.1 Array Site Selection Circuitry ................................................................................. 62
4.2 Heater Array ............................................................................................................ 64
4.3 Temperature Sensing Network ............................................................................... 66

4.3.1 Resistive Bridge Network ................................................................................ 66
4.3.2 Temperature Array Sites .................................................................................. 68
4.4 Thermal Isolation Design ........................................................................................ 70
4.5 Ambient Temperature Sensor ................................................................................. 70
4.6 Three Electrode System .......................................................................................... 71
4.7 Results ..................................................................................................................... 71
4.7.1 MEMS Post-Processing Results ...................................................................... 71
4.7.2 Circuit Functionality ........................................................................................ 73
4.7.3 TCR of Polysilicon Temperature Sensor Resistor ........................................... 73

Chapter 5: Conclusions and Future Work ......................................................................... 74
5.1 Future Work ............................................................................................................ 74
APPENDIX ................................................................................................................... 76
BIBLIOGRAPHY ......................................................................................................... 91

viii

LIST OF FIGURES

Figure 2-1: Basic flow chart for VLSI design ..................................................................... 7
Figure 2-2: Basic photolithographic exposure system setup .............................................. 8

Figure 2-3: a. Clear field mask. B. Dark field mask. Light is permitted through clear
regions and protective polymer will be removed in these regions. Both types of
masks will be utilized in post-CMOS fabrication steps. ........................................... 10

Figure 2-4: A. Isotropic etch, note that the etch rate is the same for all directions. B.
Anisotropic etch, note, the etch is direction dependant which adds some control to
the etching process. C. Mask erosion and undercut which can result from very long

etches ......................................................................................................................... 15
Figure 2-5: Graphical representation of Fourier 's Law ....................................... 19
Figure 2-6: Control solid for general conductive energy equation ............................ 25
Figure 2-7: Heat transfer by conduction in a plane wall ....................................... 29

Figure 2-8: (a) Heat transfer through a composite wall. (b) Equivalent thermal resistance
of composite wall ...................................................................................................... 29

Figure 2-9: (left) thermal equivalent circuit for a biosensor heater, and (right) diagram of
the base layers that comprise the biosensor structure without structural etch release.
................................................................................................................................... 31

Figure 3-1: (Left) Suspended structure formed by an anisotropic etch procedure. (Right)
Isolated diaphragm formed using a backside etching procedure ............................. 43

Figure 3-2: (Left) Initial experimental setup with MOSIS die attached to a silicon wafer.
(Right) Proposed die holder for MOSIS die. Consists of a recessed area in either
aluminum or T eflon. .................................................................................................. 45

Figure 3-3: Basic block diagram of biosensor chip for backside etch design. Light grey
regions represent heater regions, dark grey regions represent areas where

electronics are present. ............................................................................................. 47

Figure 3-4: Microstructure design with residuals left in designed openings to silicon
substrate. Residuals are a result of the AMI planarized process. ........................... 48

ix

Figure 3-5: First sacrificial etch design. Metal and via layers are used as sacrificial
layers. In this design a post-CMOS metal etch will be performed to remove all
metal and via layers leading to the silicon substrate, not protected by a PR mask
layer. An additional oxide etch may be required to successfully reach the silicon
surface, but this will be determined through experimental trial. After all layers are
removed an anisotropic etch step will be performed to undercut and realize
suspended MEMS structures. .................................................................................... 49

Figure 3-6: Second sacrificial etch design. Insulating dielectric layers are used as
sacrificial layers. In this design, a post-CMOS oxide etch will be performed to
remove all dielectric layers leading to the silicon substrate, not protected by a PR
mask layer. After all oxide is removed an anisotropic etch step will be performed to
undercut and realize suspended MMS structures. .................................................. 50

Figure 3-7: Basic block diagram of biosensor chip for frontside sacrificial etch design.
Light grey regions represent heater regions, dark grey regions represent areas
where electronics are present. .................................................................................. 51

Figure 3-8 (Left) Basic biosensor array site with no post-processing steps performed,
(Right) layer structure taken into consideration for basic heat flow modeling. ....... 52

Figure 3-10: (Left) Cross—section of basic biosensor array site with etch release steps
performed and water above and below the heating element, (Right) layer structure
taken into consideration for basic heat flow modeling. ............................................ 54

Figure 3-11: (Left) Sealed air cavity biosensor array site with etch release and fill steps
performed, (Right) layer structure taken into consideration for basic heat flow
modeling. ................................................................................................................... 55

Figure 3-12: (Left) Basic biosensor array site with etch release and fill steps performed,
(Right) layer structure taken into consideration for basic heat flow modeling. ....... 55

Figure 3-13: Comparison of various structures. Y-axis is a I -I 0 scale for the particular
value of interest, 10 being a maximum value. X-axis composed of various structures.
Structures with low power characteristics, low process complexity, and high

thermal isolation are the most desired structures .................................................... 59
Figure 4-1: Basic block diagram of MEMS biosensor chip design .................................. 61
Figure 4-2: Photograph of fabricated circuit die prior to MEMS fabrication procedures

................................................................................................................................... 62
Figure 4-3: Schematic of NOR decoder used in array selection circuit design ................ 63

Figure 4-4: Bridge configuration for temperature sensing network of ME MS system ..... 66

Figure 4-5: Circuit schematic array temperature sensing site ......................................... 69

Figure 4-6: Die photo of chromium patterns transferred onto MOSIS die through
standard CMOS processing steps ............................................................................. 72

Figure 4-7: (Left) Photograph of heater array site surface after etch and release steps.

(Right) Same array site with focus on the bottom of the etched pit approximately4o
microns in depth. ....................................................................................................... 72

xi

LIST OF TABLES

Table 1: Wet etchants and basic properties. ..................................................................... 17
Table 2: Maximum Allowable Power Dissipated Across Heater Element. ...................... 57

Table 3: Current required to provide sufficient Joule heating effects from polysilicon
heating element in water without thermally isolated WMS structure. Voltage levels

formatted as bold are too high for AM process. ...................................................... 57
Table 4: Operational comparison of various structures operated at 70 °C. ..................... 58
Table 5: Bit line selection for column and row decoders. ................................................ 63
Table 6: Current levels through heater resistors through Spice circuit simulation. ........ 65

Table 7: Physical parameters and thermal properties for thermal modeling of suspended
structure with water as liquid above and below using [27] ...................................... 76

Table 8: Physical parameters and thermal properties for thermal modeling of suspended
structure with water as liquid above and below using Eq. 2-25 ............................... 77

Table 9: Heat transfer results for multiple heater resistor values for suspended structure
with water above and below ..................................................................................... 78

Table 10: Physical parameters and thermal properties for thermal modeling of suspended
structure with air as liquid above and below using [27] .......................................... 79

Table 1 1: Physical parameters and thermal properties for thermal modeling of suspended
structure with air as liquid above and below using Eq. 2-25 ................................... 80

Table 12: Heat transfer results for multiple heater resistor values for suspended structure
with air above and below .......................................................................................... 81

Table 13: Physical parameters and thermal properties for thermal modeling of suspended
structure with water as above and air below using [27] .......................................... 82

Table 14: Physical parameters and thermal properties for thermal modeling of suspended
structure with water as liquid above and air below using Eq. 2-25 ......................... 83

Table 15: Heat transfer results for multiple heater resistor values for suspended structure
with water above and air below ................................................................................ 84

xii

Table 16: Physical parameters and thermal properties for thermal modeling of structure
with water as liquid above and no thermal isolation below using [27] .................... 85

Table 17: Physical parameters and thermal properties for thermal modeling of structure
with water as liquid above and no thermal isolation below using Eq. 2-25 ............. 86

Table 18: Heat transfer results for multiple heater resistor values for structure with water
above and no thermal isolation below ...................................................................... 87

Table 19: Physical parameters and thermal properties for thermal modeling of structure
with air as liquid above and no thermal isolation below using [27] ........................ 88

Table 20: Physical parameters and thermal properties for thermal modeling of structure
with air as liquid above and no thermal isolation below using Eq. 2-25 ................. 89

Table 21: Heat transfer results for multiple heater resistor values for structure with air
above and no thermal isolation below ...................................................................... 9O

xiii

Chapter 1. Introduction

Micro-Electro-Mechanical Systems (MEMS) is the combination of mechanical
elements, transducers, and electronic circuitry on a common silicon wafer through
microfabrication technology. The electronic circuitry is fabricated using IC fabrication
technologies such as CMOS, while the MEMS components are fabricated using
compatible rnicromachining processes that selectively etch away parts of the silicon
wafer or add new structural layers to form the mechanical and electromechanical devices.
These rnicromachining processes, in many instances, must be performed very carefully in
a controlled process flow and developing these processes can be quite difficult depending
on the MEMS devices and the fabrication process used for the circuitry. MEMS
technology has opened the doorway to an entirely new category of “smart” products by
combining the computational power of microelectronics with the observational and
control capabilities of sensors and actuators. Sensors within the system extract
information from the environment by the measurement of parameters such as mechanical,
thermal, biological, or numerous other attributes. The electronics then process the
information derived from the sensors and control the environment for some desired
outcome or purpose. MEMS devices are created using many of the same fabrication
steps as integrated circuits and, because of this, many types of sensors can be scaled
down to the micron level at low cost without sacrificing the reliability and functionality
of the transducer. There has been a trend to miniaturize and generate all types of sensors

in MEMS systems, but MEMS biosensor systems are still in the early stages and there are

many challenges involved in combining biosensors with control circuitry in one system-
on-chip. Traditionally biosensors are quite large and integrating them into a microsystem
can pose a problem. Research in the area of biosensors and their applications has been
widely studied and investigated at macroscopic level. However, interest has shifted to the
area of MEMS biosensors for several reasons. First, it is believed that by scaling down
the biosensors to a microscopic level, a more robust sensor can be developed. Not only
can a sensor be more sensitive and accurate, but also many more sensors can be placed
into one system-on-chip that will allow for multiple element detection in a solution. One
other important reason for the push of MEMS biosensors is the ease of mass-fabrication
and lower cost biosensor systems that can be developed using VLSI design and foundry

services.

1.1 Motivation

Biosensor systems have been developed for several applications to date, but one
critical area has been overlooked. Temperature plays a vital role not only in the operation
of biosensors, but also in the lifetime of the sensor. This thesis proposes a technique for
improving biosensor lifetime and functionality by integrating temperature control within
the sensor along with low cost fabrication techniques to realize biosensor microsystems.
Polysilicon resistive elements are used to heat up biosensor structures to the Optimal
operating temperature. This is the chosen method for temperature control for several
reasons:

0 Polysilicon is a common material to all CMOS processes.

0 Polysilicon heaters are well characterized and controlled within the operating

range of many biosensors.

0 Heating of these devices improves the overall Operation of the device.

0 Device performance can be controlled and tailored to different applications via
temperature control.

0 By utilizing polysilicon as both a temperature sensor and heating element, each
biosensor site can contain individual temperature control and sensing capabilities

which will in turn improve the operation of the biosensor.

1.2 Previous Research

To date several key areas have been investigated which contribute to this work;
biosensor functionality, thermal isolation schemes, and post-CMOS processing
techniques. Thermal isolation is a key aspect of this thesis. Methods for generating
thermally isolated structures have been established and covered in numerous works [1-7].
Most of these structures are fabricated through a rnicromachining process post-electronics
fabrication. Thermal isolation is an important aspect since uniform heating of the
biosensor sites is desired, but elimination of cross-heating between array elements is also
a key factor behind thermal isolation. Post-CMOS processing techniques have been used
to generate all types of structures and devices in the MEMS arena from MEMS
accelerometers to micropumps [2, 8-16]. Previous work has shown that not only can
functional MEMS devices be fabricated individually, but they can also be mass fabricated

using foundry services and even be developed and integrated into commercial products.

1.3 Summary

Chapter 2 covers the background information on post-CMOS MEMS processing
techniques as well as the background heat transfer material and used for the design and

generation of post-CMOS thermally isolated structures independent of biosensors. The

design methodology for structures to be generated via a standard CMOS foundry service
and the challenges involved will be addressed.

Chapter 3 addresses the specific processing steps involved for the AMI CSF/N
process available through the MOSIS foundry service along with a description of the
thermal analysis and how it applies to the structural design of several possible thermal
isolation structures for biosensor arrays that are possible through this design.
Experimental results for generating structures and analyzing their thermal characteristics
will also be covered.

Chapter 4 covers the design of a thermally controlled biosensor array microsystem. A
description of the microsystem and all of the necessary circuitry for realizing this system
are covered. Along with the chip design, preliminary simulation results will be given,
and testing techniques will be discussed.

Chapter 5 presents the conclusions of this work and will also show the long term

goals and future work to be generated from this project.

Chapter 2. CMOS Post-Fabrication Processing and Heat
Transfer Background

The combination of mechanical elements, transducers, and electronic circuitry on
a common silicon wafer through microfabrication technology is becoming common
practice in the engineering world. However, most services that offer such capabilities are
limited in their scope or can be quite expensive. In terms of saving money, any MEMS
steps that can be performed “in-house” are always desired. There are some downsides to
this approach when producing MEMS devices. First, most cleanroom facilities at the
university level are very limited in their ability to produce small feature-size electronics.
Sub-micron feature sizes are basically not available unless an outside foundry service is
used. This is an important point since most control and readout circuitry for MEMS
devices are quite advanced and require large chip areas. Also, most academic
cleanrooms do not have multi-metal/multi-poly fabrication capabilities which further
limits the scope of the electronics. Another critical consideration is process
compatibility. Many times a foundry 'service is used to produce the circuit chip and post-
processing steps will be performed on these chips to realize MEMS structures. The post-
processing steps required in most all cases are not trivial and careful design and post-
processing procedure characterization are required to generate working MEMS
microsystems.

Laws of heat transfer must also be considered when designing MEMS systems for

thermal applications. A thorough understanding of the laws as they apply to the system is

critical for both an efficient design and predicting the systems operational behavior. This
chapter focuses on background material for MEMS post-processing techniques and the
challenges involved when combining electronics and structural devices, as well as basic

heat transfer analysis as it applies to MEMS design.

2.1 Post CMOS Processing

Post CMOS processing consists of steps taken on silicon wafers or die after circuitry
has been fabricated. Multiple procedures can be performed post-CMOS such as
photolithography, material etching, and material deposition. There are several key points
that must be carefully considered when performing process steps on silicon wafers:

0 The steps taken must be compatible with CMOS technology.
0 Low Temperature
0 Prevent contamination

o The wafer must be well protected.

0 There must be consistency in the process steps.
Without careful consideration of such issues, the CMOS circuitry can be rendered useless
or the functionality may differ from the designed plan. Figure 2.1 shows a flow chart by
which most integrated circuitry or ICs are designed. Traditionally in circuit design little
consideration needs to be given to such issues as post-CMOS photolithography, but when
designing MEMS systems this is a consideration that needs addressed from the first step
of functionality for the system. Each step along the way, not only does the circuitry need
to be properly designed and tested, but the MEMS portion of the design also needs very
careful design planning, especially when the chip will be processed afier fabrication to

realize one working system on-chip.

 

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In this work, photolithography, material etching, and material deposition have been
implemented on fabricated wafers. Techniques for performing these steps and key issues

for each are to be discussed [17].

2.1.1 Photolithography

Lithography is the most expensive, complex, and critical process in mainstream
microelectronic fabrication. As mentioned, lithography is very expensive and accounts
for upwards of one-third of the total fabrication cost. To put this into perspective a

Pentium 4 processor has approximately 20 masks required. Each of these masks has a

cost of around one million dollars and also, each of these masks needs to be carefully
aligned to prior layers, which is a very complex process with feature sizes that are around
0.15pm in newer processor technologies.

Figure 2.2 shows a simple system for optically exposing a wafer during
processing procedures. Some type of an optical source is used to shine light through a
mask. The image from the mask is then projected onto the wafer surface, which is then
coated with some photosensitive material known as photoresist. There are two parts of
optical photolithography, the design and operation of the exposure system that passes the
mask image onto the wafer and the chemical processes that happen within the photoresist
to realize that mask image. The basic physics of optical exposure will be discussed. The
tools for photolithography are optical, which means they use light as the exposing

radiation whether it is visible light or some wavelength of ultraviolet.

 

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Mask aligners are the optical tools used to pass the image of a mask onto a silicon

surface. There are several types of aligners used for microfabrication; however the only

one to be discussed is the contact aligner since that is the aligner used in this research.
The contact aligner is the simplest type of aligner. In contact alignment printing, the
mask is pressed against the photoresist-coated wafer during exposure. The biggest
advantage of these systems is the small features that can be generated using relatively
inexpensive equipment. In a typical contact system, the mask is held image side down in
a frame just below the microscope objectives of the system. Adjustment screws are used
to move the wafer with respect to the mask for alignment purposes. Once the wafer is
aligned to the mask, they are put into contact with each other, the microscope is retracted,
and the wafer/mask is ready to be exposed to the light source. The wafer is then exposed
to the high intensity light.

Ideally during this exposure step the entire wafer needs to be in contact often
referred to as “hard contact” with the mask. This means that the distance between the
wafer and the mask basically goes to zero so effects due to diffraction are minimized and
there is essentially a perfect transfer of the mask image onto the wafer surface. The gap
can never truly be zero due to the thickness of the photoresist layer. Also, the mask is
usually not in complete contact with the wafer since the wafer and the mask are not
totally flat. By using very thin masking layers and thin layers of photoresists, however,
very small feature sizes are possible during the hard contact. The major downfall of hard
contact lithography is the defect generation due to the contact between the resist coated
wafer and the mask. These defects cannot be avoided and they are generated both on the
wafer and mask during every contact cycle. Because of this, contact printers are used

mainly for research or other applications that can tolerate a large amount of defects.

The mask used in the photolithographic process is a key component on the
fabrication process. The mask is in most all cases a glass plate that is transparent to
ultraviolet light. This glass is then patterned with the desired pattern. Traditionally the
pattern of interest is generated on the glass by depositing a very thin layer of metal,
usually chromium or gold. In mass fabrication the pattern is usually repeated multiple
times so many copies of the design can be fabricated simultaneously. Depending on the
polarity of the mask, positive or negative as seen in Figure 2.3, light can either pass
through the patterned regions or pass through the regions outside of the pattern onto the
photoresist.

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a.Clear Field b.Dark Field

  

Figure 2-3: a. Clear field mask. 3. Dark field mask. Light is permitted through clear regions and
protective polymer will be removed in these regions. Both types of masks will be utilized in post-C MOS
fabrication steps.

The photoresist, often referred to as PR, is a polymer whose chemical properties
are altered when it is exposed to UV light. Upon exposure, the PR can be developed in a
“developer” much like that used in traditional photography. Depending on the type of PR
used there are two results that can be expected. Positive PR is used to etch away areas
that have been directly exposed to UV light. Negative PR is hardened in areas that have

been exposed to UV light and therefore cannot be removed in the developer solution.

Negative PR requires a more complex procedure to realize patterns and for that reason
positive PR is used in this research. PR is in liquid form that is spun onto a wafer at
speeds of a few thousand RPM’s. Depending on the spinning speed and the
characteristics of the PR, a uniform PR thickness in the range of one to tens of microns
can be realized. Careful process characterization must be developed for
photolithography in this work, issues and solutions for photolithography will be presented

in later chapters.

2.1.2 Film Deposition

In standard CMOS fabrication, film deposition is the procedure by which various
layers of conductive and insulating materials are deposited onto the surface of a silicon
wafer. There are two major types of deposition techniques, physical vapor deposition
and chemical vapor deposition.

Physical vapor deposition is capable of depositing many materials onto a surface.
The material to be deposited is placed in a chamber that is pumped down to vacuum; the
material is then transformed into a gas phase by a variety of methods. In this fashion,
atoms of the source material are able to be transferred to the target. It is necessary for the
molecular species of the source material to be in a gaseous phase and there are three
standard techniques utilized to create this condition; evaporation, sputtering, and ion
beam deposition. Physical vapor deposition is typically used to deposit most metals,
insulators, and semiconductor films in standard IC processes.

One method for transforming the source material into the gas phase is to use
evaporation techniques. The source material is heated so that it melts and then

evaporates and there are three approaches, thermal evaporation and electron-beam

ll

evaporation, used to achieve this goal. Thermal evaporation is the easiest of the three and
requires the most basic system. The material to be deposited is place inside of a crucible
in a vacuum chamber and the crucible is then heated until the material evaporates.
Heating of the crucible is accomplished in several fashions, but resistive and inductive
heating techniques are the most common in practice. The temperature required to
evaporate the material depends on the vapor pressure of the material and on the pressure.
The downfall to this method of deposition is that few materials can be deposited in this
fashion. Deposition is limited to metals such as Al, Au, and metals with higher vapor
pressures.

Another common technique used to evaporate materials is electron-beam
evaporation. A high-energy electron beam is used to heat and melt the source material in
e-beam evaporation. Higher temperatures can be achieved using this technique and
because of this, a wider range of materials can be deposited. In addition to metals with
lower vapor pressures, some insulators can be deposited. Also, since the crucible is not
directly heated as much, the possibility of contamination through e-beam evaporation is
lowered when compared to thermal evaporation. For these reasons, e-beam evaporation
is commonplace in the IC industry today.

The third method of physical vapor deposition is sputtering. Basically sputtering
consists of bombarding the source material with an ion beam. The ion beam is generated
through an arc discharge in a pressure range of 1-100uTorr, with voltages of 500-1000V.
The ion beam is then formed into a narrow column, accelerated and then impinged upon
the source. As the ions hit the source, the source atoms are knocked off and land on the

substrate. Sputtering is the best of the three PVD methods for a few reasons. First,

12

sputtering offers excellent cleanliness and control to the deposition process. Another key
feature is the fact that both deposition of materials and etching can be performed at the
same time. This is accomplished by focusing the ion beam on the wafer to achieve
etching. Multiple ion beams can be used in this fashion to achieve deposition and
etching. Sputtering is also very desirable due to the wide range of materials that are able
to be deposited; insulators such as silicon oxide that in other cases must be thermally
grown can be deposited.

A key feature of each PVD technique is the fact that the temperature of the source
material in each is raised significantly, but the temperature of the substrate is typically
maintained at or near room temperature. This is of particular importance when dealing
with MEMS post-processing as in this work. The temperature of fabricated devices
cannot be raised too much or the Al used in the fabrication process may melt.

The alternative to physical vapor deposition is chemical vapor deposition.
Chemical vapor deposition is used to deposit thin films onto a substrate from a gas phase.
Several types of chemical vapor deposition techniques are available; low pressure
chemical vapor deposition, plasma-enhanced chemical vapor deposition, and photo
chemical vapor deposition. Most all of these techniques raise the substrate temperature
above 300°C, so these are performed at higher temperatures than the physical vapor
deposition techniques already discussed and can cause problems especially in fabricated
circuitry. Chemical vapor deposition techniques are mostly used for the deposition of
insulators and semiconductor materials due to the conformal nature of the deposition.

Due to temperature, complexity, and contamination issues that may arise due to CVD

l3

techniques, these techniques are not favorable for use in this research and will not be

discussed in further detail.

2.1.3 Etching Techniques

The etching process in CMOS and MEMS fabrication consists of removing a
selected material by adding a substance to the environment, usually a liquid or gas that
will selectively attack a target material. When discussing etching it is useful to begin
with a discussion of prime factors in the etching process. The main factor is the etch rate,
which is defined as thickness etched over time. A high etch rate is usually desired in the
manufacturing environment, but if the etch rate is too high, the process may be very
difficult to control and reproduce. It is very common to have etch rates on the order of
hundreds or thousands of angstroms per minute. Another important factor is the etch rate
uniformity which is measured in percentage variation of the etch rate. This is ofien
quoted across the wafer and from one wafer to another. Another very important etching
factor, especially in MEMS design is the selectivity of the etchant. Selectivity is the ratio
of the etch rates of various materials, such as a PR mask or an underlying layer,
referenced to the film that is being patterned or material being etched away. In many
cases photoresist is used as the making layer in CMOS fabrication, so etchants must be
selected that do not etch PR. When post-CMOS processing is to be implemented, careful
planning in the design phase for all phases of the design is crucial for a working system.
One area for careful consideration must be substrate damage. For example, p-n junctions
have been shown to degrade under certain types of etching. The amount of degradation

depends not only on the etch process, but also on the depth and type of junction.

14

Etchants must be chosen for post-CMOS processing that will not effect the active
circuin and this may prove difficult in certain scenarios.

After the design phase the type of etchant to be used must be decided upon. The
first consideration to be taken into account when choosing an etchant for post-processing
is whether to use an isotropic or an anisotropic etchant. Some etchants are purely
isotropic, which means they will etch the target material at the same rate in all directions.
Many times these etchants are avoided, if possible, since there can be considerable
reduction in feature sizes, especially as a layer’s thickness becomes larger. The other
type of etchant, anisotropic, is often preferred since the exact pattern and dimension of
the mask can be patterned onto the thin-film material. Often times, the masking layer is
attacked by the etchant at a greatly reduced rate. So for long etches, mask erosion and

undercut may be a problem. Examples of these etching techniques are seen in Figure 2.4.

Undercut

     

A. B- C.

Figure 2-4: A. Isotropic etch, note that the etch rate is the same for all directions. B. Anisotropic etch,
note, the etch is direction dependant which adds some control to the etching process. C. Mask erosion and
undercut which can result from very long etches.

The next major consideration is whether to choose a wet or dry etching process.
Wet etching is a purely chemical process that, if not performed carefully, can have

serious drawbacks: a lack of anisotropy, poor process control, and excessive

contamination to the system. However, wet etching can be highly selective and often
does not damage the substrate. As a result it continues to be used for a wide range of
applications. A more complete overview of wet etching can be found elsewhere [18].

The reactive species is oflen present in the etching solution, so wet chemical
etching consists of three processes: movement of the etchant species to the surface of the
wafer, a chemical reaction with the exposed material to be etched that produces soluble
by-products, and movement of the reaction products away from the surface of the wafer.
All three of these processes must occur and the slowest one, referred to as the rate
limiting step, determines the etch rate. Since it desired to have a large, uniform, well
controlled etch rate, the wet etch solution is often agitated in some manner to assist in the
movement of etchant to the surface and the removal of the etch product.

For most chemical wet processes, the film or material to be etched is not directly
soluble in the etchant solution. It is usually necessary to change the material to be etched
from a solid into a liquid or a gas. If the etching process produces a gas, this gas can
prevent the movement of fresh etchant to the surface through the formation of bubbles.
This is a problem in wet chemical etching since the formation of these bubbles cannot be
predicted, although the problem does appear to be the most pronounced near the edges of
a pattern. Agitation in the wet chemical etch can help to reduce this problem, at the same
time preventing the bubbles from adhering to the surface if they do happen to form.
Microscopic bubbles of trapped gas have been linked to this phenomenon [19]. Another
common problem in wet etching is that of resist scumming. Resist scumming occurs
when some of the exposed PR layer is not removed during the developing step. This can

be caused by several factors including incomplete exposure and PR layer non uniformity.

16

This can be a major factor when etching, since even a thin layer of PR can retard the wet
etch process.
Wet etching is used to pattern a wide variety of materials. A table of common

wet etchants and the materials they etch is found in Table 1.

Table 1: Wet etchants and basic properties.

 

 

 

 

 

 

 

 

 

 

 

Material Wet Etchant Masking Material
SiO2 Buffered Hydrofluoric Acid (BHF) Photoresist
Si3 N 4 Hot Phosphoric Acid Silicon Dioxide
Al Phosphoric + Acetic + Nitric Acid Photoresist
Cr Hydrochloric Acid (HCl) Photoresist
Au Potassium Iodine (KI) Photoresist
Si (Isotropic) HF + HNO 3 + Acetic (1 :3:8) Silicon Dioxide or Silicon Nitride
Si KOH, TMAH, EDP Silicon Dioxide or Silicon Nitride
(Anisotropic)

 

Isotropic etching is sufficient for many applications, but some technologies including
MEMS require directional specific etching to realize structures. Many times the bulk
silicon is etched away from patterned areas to create such structures. Common
anisotropic wet etchants for silicon etch the (100) and (110) directions much faster than
the (111) directions and the specific etch rates have been reported [20-26]. This type of
etching is widely used when creating MEMS structures post-CMOS, especially when
electronics on-chip are located near structural elements as a preventative measure against
device contamination and malfunction. Isotropic etchants and the issues involved with
post-CMOS processing on MOSIS die will be discussed in further detail later.

The other major technique used for etching is dry etching. There are several
techniques used for dry etching that are common place in microfabrication today: plasma

etching, reactive ion etching, high density plasma etching, and ion milling. There are

17

 

some definite advantages to dry etching when compared to wet etching. Dry etches are
usually much easier to start and stop than typical immersion wet etching. Also these
etching procedures are less sensitive to small temperature changes of the wafer. These
two factors make dry etching more repeatable than most wet etches. Another key feature
is the high anisotropy of dry etching. Usually plasma environments have far fewer
particles in the system than in wet etching, which can lead to much less chemical waste
and a reduced chance of contamination to the wafer. Dry etching has its advantages, but
usually these systems are much more expensive and require a high level of attention. Dry
etching may be utilized in the future in this research, but for the current work, wet etching

techniques are used for the cost and ease of experimental setup.

2.2 Basic Heat Transfer Analysis

The area of thermal science in the engineering world includes thermodynamics
and heat transfer. Heat transfer’s role is to supplement thermodynamic analyses, which
consider only systems in equilibrium, with additional laws that allow prediction of time
rates of energy transfer. These laws are based upon the three fundamental laws of heat

transfer, conduction, convection, and radiation [27].

2.2.1 Conduction

A temperature gradient within a homogeneous substance results in an energy

transfer rate within a medium that can be calculated by Fourier ’s Law

q : —M a—T Eq. 2']
an

18

6T . . . . .
here 6— rs the temperature gradient in the direction
n

normal to the area A. The thermal conductivity k is
an experimental constant for the medium involved,

and this constant may depend on other properties,

 

such as temperature and pressure which will be

discussed in further detail later. The units for k are
Figure 2-5: Graphical representation of

I47 °K _ Fourier '5 Law.
m.

The minus sign in Fourier 's Law is required by the second law of
thermodynamics, which states: thermal energy results from a thermal gradient which
must be from a warmer to a colder region.

If the temperature profile within the medium is linear as shown in Figure 2-6
above, it is allowable to replace the temperature gradient with

A_T = M E 2-2
Ax x2 — xl q.
This type of linearity is always seen in a homogeneous medium of fixed k during steady
state heat transfer.

Steady state heat transfer occurs whenever the temperature at every point within

the body, including the surfaces, is independent of time. If the temperature changes with

time, energy is either being stored in or removed from the body. The storage rate is

0T
qstored = mcp 5 Eq. 2-3

where the mass m is the product of volume V and density p [27].

2.2.2 Convection

Whenever a solid body is exposed to a moving fluid having a temperature
gradient from that of the body, energy is carried or convected from or to the body by the

fluid.

If the temperature of the upstream temperature of the fluid is Tao and the surface

temperature of the solid is 7:, , the heat transfer per unit time is given by

q=hA(];—Too) Eq.2-4
which is known as Newton’s law of cooling. This equation defines the convective heat

transfer coefficient h as the constant proportionality relating the heat transfer per unit

time and unit area to the overall temperature difference. The units of h are "Z712 °K'

The fundamental energy exchange at a solid-fluid boundary is by conduction, and this
energy is then convected away by the fluid flow. From earlier equations we obtain

6T
hA(TS — Too) 2 —kA (5)5 Eq. 2-5

where the subscript on the temperature gradient indicates evaluation in the fluid at the
surface [27]. Convection can be via two modes forced convection and natural
convection. Natural convection will be the mode of convective heat transfer in this work

and the analysis will be discussed further in later sections.

2.2.3 Radiation

The third mode of heat transmission which does not really apply to this research is

due to electromagnetic wave propagation, which can occur in a total vacuum as well as in

20

a medium. Experimental shows that radiant heat transfer is proportional to the fourth
power of the absolute temperature, whereas conduction and convection are proportional

to a linear temperature difference. The fundamental Stefan-Boltzmann law is

q = 0A T 4 Eq. 2-6
where T is the absolute temperature. The constant a is independent of surface, medium,
and temperature; its value is 5.6697 ><10'8 W / m2 -°K 4 .

The ideal emitter or blackbody, is one which gives off radiant energy according to

the Stefan-Boltzmann law. All other surfaces emit somewhat less than this amount, and

the thermal emission from many surfaces can be represented by

q = 80A T 4 Eq. 2.7

where a, the emissivity of the surface, ranges from zero to one [27].

2.3 Material Properties Affecting Heat Transfer

2.3.1 Thermal Conductivity of Solids

Thermal conductivities of numerous pure metals and alloys are well known and
widely available. The thermal conductivity of the solid phase of a metal of known
composition is primarily dependent only upon temperature. In general, k for a pure metal
decreases with temperature; alloying elements tends to reverse this trend.

The thermal conductivity of a metal can usually be represented over a wide range

of temperature by

k =k0(1+b6+c62) Eq.2-8

21

where l9 = T — Tmf and k0 is the conductivity at the reference temperature 7:4 . For

many engineering applications the range of temperature is relatively small and
k = k0(1+b6I).

The thermal conductivity of a nonhomogeneous material is usually very
dependent upon the apparent bulk density, which is the mass of the substance divided by
the total volume occupied. This total volume includes the void volume, such as air
pockets within the overall boundaries of the piece of the material. The conductivity also
varies with temperature. As a general rule, k for a nonhomogeneous material increases

both with increasing temperature and increasing apparent bulk density.

2.3.2 Thermal Conductivity of Liquids

For most liquids, k is usually temperature dependent on temperature but
insensitive to pressure. Thermal conductivities of most liquids decrease with increasing
temperature. The exception to this is water, which exhibits increasing k up to 150 °C and
decreasing k after this point. Water has the highest thermal conductivity of all common

liquids except the liquid metals.

2.3.3 Thermal Conductivity of Gases

The thermal conductivity of a gas increases with increasing temperature, but is
essentially independent of pressure for those close to atmospheric. At high pressures, the

effect can be very significant.

2.3.4 Density

Density can be defined as the mass per unit volume. Density data for most

solids and liquids are only slightly temperature dependent and are negligibly influenced

22

by pressure up to 100 atm. The density of a gas, however, is strongly dependent upon the
pressure as well as upon the temperature. In the absence of specific gas data, the density

can be represented by

p : pl (L) Eq. 2-9
Pi

The specific volume is the reciprocal of the density,

V = —— Eq. 2-10
and the specific gravity is the ratio of the density to that of pure water at a temperature of
4°C and a pressure of one atmosphere. Thus

5 = — Eq. 2-11

where S is the specific gravity.

2.3.5 Specific Heat

The specific heat of a substance is a measure of the variation of its stored energy

with temperature. From thermodynamics the two specific heats are:

 

 

Bu
specific heat at constant volume: Cy E .—
aT .
- _ ah
specrfic heat at constant pressure: C p = —5T
p

Here u is the energy per unit mass and h is the enthalpy per unit mass. In general, u and h
are functions of two variables: temperature and specific volume, and temperature and

pressure, respectively. For substances which are incompressible, solids and liquids,

23

CI) and cv are numerically equal. For gases, however, the two specific heats are

considerably different. The units of Cp and C, are J /kg-°K .

For solids, specific heat data are only weakly dependent upon temperature and are
even less affected by pressure. It is usually acceptable to use to use the limited specific
heat values at constant pressure, over a fairly wide range of temperatures and pressures.
Specific heats of liquids are even less pressure dependent than those of solids, but they
are somewhat temperature influenced.

Gas specific heat data exhibit a strong temperature dependence. The pressure
effect is slight except near the critical state, and the pressure dependence diminishes with

increasing temperature. For most engineering calculations specific beats for gases found

in common tables are suitable for pressures up to 1.4x106 Pa.

2.3.6 Thermal Diffusivity

A useful combination of terms already considered is the thermal diffusivity a,

defined by

a E —- Eq. 2-12

It is seen that a is the ratio of the thermal conductivity to the thermal capacity of the
material. Its units are mz/s . Thermal energy diffuses rapidly through substances with

high a and slowly through those with a low a [27].

24

2.4 One-Dimensional Steady-State Conduction

The conductive heat transfer rate at a point within a medium is related to a local
temperature gradient by Fourier’s Law Eq. 2-1. In many one-dimensional problems we
can write the temperature gradient simply by inspection of the physical situation. The
situation we are dealing with can be modeled from this basic heat transfer situation by

taking the physical geometry of the situation into consideration.

2.4.1 General Conductive Energy Equation

 

 

 

Consider a small control volume consisting of Y,
the parallelepiped shown at the right. This may be an #2147; "X /..i r
,xj/ / 3
element of material from a homogeneous solid or i y
. , _ qxl > .p i i >qx2
homogeneous fluid so long as there rs no relative ‘ I
,'/—“t—:?" «a
motion between the macroscopic material particles. /,
Z1

Heating of this material then results in an energy flux Figure 2-6: Comm] solid for

general conductive energy
per unit area within the control volume. This flux is, in equation-

general, a three-dimensional vector. For simplification reasons, heat flow is only shown
in the x direction.
Application of the first law of thermodynamics to the control volume yields the

general conduction equation through the following procedure:

For the control volume shown above, the first law of thermodynamics can be
expressed as

(1)

(rate of heat transfer in) + (rate of work in) + (rate of other energy conversion)=

(rate of heat transfer out) + (rate of work out) + (rate of internal energy storage)

25

For an incompressible substance the net work done on the control volume is
converted to internal energy. Denoting the rate of energy conversion (from work,

chemical reaction, etc.) as q'" , (1) becomes

(2)

m 5U
qxl +qu +qu +q AxAyAz = qx2 +qy2 +5122 +1???

Examining the heat transfer terms in (2). In the x-direction the two terms may be

grouped to form

(3)

6T 6T
— =—AAz k— — k—
q. q.. ,, [ a) ( a.)

by the application of F ourier’s Law. Notice that k may be temperature dependent and

because of this, spatially dependent. By a Taylor series expansion about the center

point P.

(a erase—Ti
(ix x, dx 2 6x 6x

(a ail-WEI
6x x2 6x 2 6x 0x

so that (3) becomes

 

(4)
qt, -qx2 =AyAz Ax—a-[ka—T]+...
' 6x 6x

Similarly,

26

(5)
6 6T
qyl—qyzzAxAz Ay—[k—]+...
5y 5y

(6)

6 5T
— =AxA 132— k— +...
qzl qu Y[ az[ 52] :l

Finally, the internal energy storage per unit volume and per unit temperature is
the product of density and specific heat, so
(7)

29.
at

6T

Substituting expressions (4) through (7) into (2), dividing by the volume AxAyAz, and
taking the limit as Ax, Ay, Az simultaneously approach zero yields the general

conduction equation.

6 6T 6 6T 6 8T ,, 6T
_ k— +_ k— +— k— +q =pc— Eq.2-13
6x 6x 6y 8y 62 62 at

This equation is for the temperature T as a function of x, y, z, and t. Here, k is the
thermal conductivity, p is the density, c is the specific heat per unit mass, and q'" is the
rate of internal energy conversion (“heat generation”) per unit volume. A common
instance of q m is provided by resistance heating in an electrical conductor.

In most engineering applications k can be taken as a constant, and Eq. 2-12

reduces to

air 62T 62T q'"__1_a_T

+ + + _ ,
8x2 ay2 622 k a a: W“

 

 

where a is given by Eq. 2-1 1 [27].

27

2.4.2 Plane Wall Fixed Surface Temperatures

The simplest heat transfer problem is that of one-
dimensional, steady-state conduction in a plane wall of
homogeneous material having constant thermal conductivity (VA

and with each face held at a constant uniform temperature as

shown at the right.

 

Separation of variables and integration of Eq. 1 where
Figure 2-7: Heat transfer

the gradient direction is x results in by conduction in a plane
wall.
x2 72
(IL dxz-kAI, dT Eq.2-15
l l
or
T — T T — T
q = —kA 2 l = _kA 2 I
x2 — xl Ax

This equation can be rearranged as

_ TI — T2 _ thermal potential difference

 

_ Eq. 2-16
Ax/kA thermal resrstance

Notice that the resistance to the heat flow is directly proportional to the material
thickness, inversely proportional to the material thermal conductivity, and inversely
proportional to the area normal to the direction of heat transfer.

These principles are readily extended to the case of a composite plane and can be
directly applied to the various layers in the CMOS design flow. The case for the
composite plane which will later be extended to multiple layers is shown in Figure 2-8 (a)

below:

28

 

3.x; X
f kaA kbA
\\ |
q—H .. a» q e—/\,_._/\,_.
i l \ “‘\~. l T1 T2 T3
E a b //
l 2 3

(a) (b)

Figure 2-8: (a) Heat transfer through a composite wall. (b) Equivalent thermal resistance of composite

wall.

In the steady-state the heat transfer rate entering the left face is the same as that leaving

the right face. Thus,

_ T2_T3

Yl—TZ
q— ___.____
Axb/kbA

—————- d
Axa/kaA an q

Together these give:

T, —T.
Axa/kaA)+(Axb/kbA)

 

q = ( Eq. 2-17

Equations 12 and 13 illustrate the analogy between conductive heat transfer and
electrical current flow, an analogy that is rooted in the similarity between Fourier’s and

Ohm’s laws. It is convenient to express F ourier’s law as

. overall temperature difference
conductive heat flow = Eq. 2-18

summation of thermal resistances

 

In the case of Figure 2-8 (a) above the total thermal resistance is simply the sum of the
two resistances in series as shown in Figure 2-8 (b) above. The extension to three or

more layers is obvious.

29

2.5 Thermal Equivalent Circuit

The above arguments and analyses can be combined to form an electric circuit
that will simulate the operation of our MEMS biosensor system. In performing these
simulations and the basic heat flow analysis that follows from these results, there are
several assumptions that have been made to simplify the model for basic design and
characterization:

0 Material is much longer and wider than it is thick, so that only the vertical heat

flow must be considered

0 Region inside the heater material has a uniform temperature, T]: (final

temperature after heating)
0 All transfer is by conduction within the solid and a convective boundary layer
between our structure and the fluid environment (negligible radiation)
0 A conductive analysis is used when analyzing sealed air cavities due to small
finite geometry of sealed cavity
0 Temperature changes are small enough that the thermal conductivity, k, can be
assumed constant (generally, k is a function of temperature, layer thickness, and
doping)
The basic thermal circuit for spice simulations is shown below [28]. This circuit
allows simulations to be run on proposed biosensor structures. These are important
simulations since they give estimates of what temperatures can be realized for the CMOS

process that will be used when fabricating these MEMS devices.

30

liquid reservoir

’ thin film layer

biomimedic membrane
electrode metal
metal3

dielectric
meta|2

dielectric
meta|1

dielectric

190le

dielectric

.' i polyi

dielectric (FOX)

 

silicon substrate

 

0

solid heat sink

 

Figure 2-9: (left) thermal equivalent circuit for a biosensor heater, and (right) diagram of the base layers
that comprise the biosensor structure without structural etch release.

The components used in this thermal model are defined by the following:
RH is the heater resistance [Ohms]
V is the voltage across the heater resistor [Volts]
V=IHRH, where In is the heater electrical current
CT is the heat capacity of the heater [Joules/Kelvin]
RT] is the thermal resistance above the heater [Kelvin/Watt]
Rn is the thermal resistance below the heater [Kelvin/Watt]
T1: is the final temperature [Kelvin]
To is the initial (background) temperature [Kelvin]
V,” is the equivalent thermal voltage due to temperature difference, dT = TF-To [Kelvin]
IQ is the equivalent thermal current [Watts]
[Watt = Volt * Amps = Voltz/Ohm]

[Joules = Watt * seconds]

31

The thermal equivalent circuit can be analyzed by looking at basic conduction and
convective heat transfer and building the heat flow model for the structure.

The difference in temperature, = T]: — To, (created by delivering electrical power
to the heater) generates a heat flux out of the heater given by Fourier’s law for heat
conduction, Eq. 1 above. Where VT =dT/dn is the change in temperature over vertical
distance x, k is the thermal conductivity [25 Watts/(Kelvin-meter)] of the heater material
and JQ has units of [Watts/meterz].

If we assume the surface area through which this heat flows is a square around the
heater element with a side length of W [meters], then we can express the total heat

current through the surface as

6T
1 =kW2— [3.2-19
Q ax q

where the negative sign is dropped since temperature decreases with increasing distance,

x, from the heater. Solving this for dT we get,

T T XI IQ a IQ X 20
F _ o 2 — x = — f Eq.2-
0 W2 W2

where Xf is the distance from the heater that the temperature reaches To. For a more
general expression, we note that the temperature will drop to some value T, (TF>T,>T0) at

a distance Xi from the heater which will be given by the expression

 

1
TF—T. Q

r = kWZ X,- Eq.2-21

32

2.5.1 Thermal Resistance

It is useful at this point to introduce the notation of thermal resistance of a

material, RT, defined the temperature drop across the material per unit heat current, or

er-A—Zz X,= 1, Eq.2-22
IQ kW“ hW“

 

where X is the thickness of the material. This expression combined with ideas laid out in
the section dealing with heat transfer through a plane wall above, made for this structure,
suggest that a series of adjacent thermal resistances will add linearly so that the total
equivalent thermal resistance is just the sum of individual thermal resistances for this

structure.

 

Xi
RT = 2 kW2 , Eq. 2-23

2.5.2 Thermal Boundary Layer: Flat Plate

In modeling the thermal resistance layers for the circuit simulations and heat
transfer analysis, the liquid-sensor interface must be analyzed to determine the behavior
of this interface.

When a fluid at one temperature is along the surface of a plane which is at another
temperature, the behavior of the fluid cannot be described by typical hydrodynamic
equations alone. There is an additional thermal boundary layer which develops. In these
situations, a temperature gradient exists across the thermal boundary layer. The equation
heat transfer in natural convection between fluids and solids of definite geometric shape

are of the form:

33

 

—=b 2 k

ltL L3P/zgfl/AT [Cpru]
Eq. 2-24
kl 1“] f

b and n are constants dependent on the system, in our case we have a heated horizontal
plate facing upwards so the components of the equation are defined by:

b=0.54

n=0.25

h= heat transfer coefficient (this is what we are solving for)

L: length of horizontal square surface

k f = thermal conductivity of fluid

pf = density of fluid

g = gravitational acceleration

,8] = coefficient of volumetric expansion of fluid

AT = temperature change dependent on environment and heater temperature

pf = absolute viscosity of the fluid

cp’ = specific heat of fluid

Solving for this heat transfer coefficient will allow us to determine the thermal
resistance of this boundary layer which is an key parameter in the thermally equivalent
circuit [29]. This method for determining the heat transfer coefficient may not be fully
accurate for heat transfer at the micro scale, as certain assumptions are being made as to

the size of the system.

34

An additional method for determining the heat transfer coefficient due to natural
convection across a wider range of systems is given by a different approach [27]. The
thermal boundary layer at this level consists of a laminar flow system. The heat transfer

coefficient is given by the following equation:

 

 

Eq. 2—25

I“

Here Nu L is the Nusselt number which is a ratio of the heat transfer coefficient from the

surface of interest to the conductivity of the fluid. The Nusselt number is a firnction of

the Raleigh number which is described by:

Ra = Gr - Pr Eq. 2-26
In this equation, Gr and Pr are the Grashof and Prandtl number respectively. The
Grashof-Prandtl number product is used to determine what analysis is applicable to a
naturally convective system. For a constant surface temperature, The following equation
can be used for determining the Nusselt number across the entire range of Raleigh

numbers.

0.670Ra,%
[1+(0.492/Pr)%6]/9

 

 

Nu, = 0.68+ Eq. 2-27
In this equation all properties for natural convection are evaluated at the Fluid
temperature. The Prandtl is given as a constant for the particular fluid of interest and the

Grashof number is then given by:

g 3 ( Ts - T... ) L3 0C buoyancy force

v viscous force

Gr:

 

Eq. 2-28

The components used in this equation are defined by the following:

35

g = gravity constant
B = coefficient of volumetric expansion of fluid
L = Characteristic length of convective surface
v= kinematic vicosity
Both of these techniques for determining the heat transfer coefficient have been

used for analysis of thermal array sites in chapter 3.

2.5.3 Heat Capacity of a Polysilicon Resistor

The heat capacity of a material can be expressed as

CT = pthLCm Eq. 2-29

where pm is the mass density of the material (2330 kg/m3 for polysilicon), t, W, and L

are the thickness, width, and length, respectively, of the material, and Cm is the specific
heat per unit mass (753 J/(kg-Kelvin) for polysilicon). Heat capacity is sometimes given

as a per volume constant, such that

C, /V = pm Cm Eq. 2-30

2.5.4 Temperature Coefficient of Resistance

Resistance of a material is a function of temperature (unless specifically designed
otherwise). The temperature coefficient of resistance (TCR), orR, is itself generally a

function of temperature, but can often be assumed constant over a small temperature

range. The TCR is defined as

36

_ RT-Rro
05,, . R10(T-7i>)

 

Eq. 2-31

where, RT is the resistance at temperature T and RTo is the resistance at temperature T o.
The resistance of the polysilicon is also a function of stress in the material. However the
change in resistance due to stress is negligible compared to the change due to temperature
and can be neglected for basic analysis.

Extraction of QR is very important for the characterization and performance of the
polysilicon resistor that will be acting as a temperature sensor. This parameter must be
found through experimental analysis of the resistor in a highly controlled temperature

environment over a wide temperature range to ensure accuracy in temperature readings.

2.6 Self-Heating Limitations in Sensor-Resistors

When using resistors to measure temperature, it is important to minimize self heating due
to the current applied to measure the resistance. If the sensor-resistor is in good thermal
contact with the background temperature reservoir, there will be limited self heating.
However, in thermally isolated structures (where there is a large thermal resistance
between the resistor and the background temperature reservoir), heat produced from the
readout current will not dissipate well. As a result, only a small amount of electrical
power can be applied to the sensor-resistor without substantial self-heating. This is a
consideration that must be made when designing readout circuitry for the temperature

sensing resistor.

37

2.7 Verification of Thermal Equivalent Circuit Analysis

When checking what types of analysis with which to model the system it is
important that we look at the Biot number. The Biot number is dimensionless, and it can

be thought of as the ratio

Bi- resistance to internal heat flow _ resistance of solid

 

 

. — . Eq. 2-32
resrstance to external heat flow resrstance of film

Whenever the Biot number is small, the intemal temperature gradients are also small and
a transient problem can be treated by the “lumped thermal capacity” approach wherein
the object for analysis is considered to have a single mass-averaged temperature.

This is the situation that arises in our thermal model. The thermal resistance of
the thin film layer is much higher than the internal resistances which allows for the use of
a lumped analysis when considering the various structural possibilities for MEMS

biosensors as seen in tables contained in the Appendix.

2.8 One Dimensional Systems: Transient Analysis Fixed Surface

Temperature

Another key component in analyzing various structures for thermal isolation is the
transient characteristics of heat transfer. For some proposed structures there is no thermal
boundary layer of high resistance providing thermal isolation between array sites. In
these cases there is silicon substrate, an oxide layer, or a combination of the two
separating the biosensor array sites. In these cases, the temperature at a distance x away
from our heater layer into the silicon substrate, oxide, or other material can be
approximated by this particular analysis. In this manner we will see if sufficient thermal

isolation coinciding with proper operation of an array site is feasible.

38

In considering this transient conduction problem, it can be treated approximately
by considering the body to be initially at some uniform temperature and suddenly having
the temperature of part of the surface changed to and held at a known constant value
different from the initial temperature.

The solution to this conductive problem is approximated by using the transient
analysis for a semi-infinite body. The solution to a temperature at some distance x below

the surface is

 

T(x,t)-TS x
"——=er E .2-33
T,—T fl 4m) 4“

3
Values for the Gaussian error function can be obtained from various mathematical tables.

From such analysis MEMS structures can be designed and their behavior modeled

down into the body of the MEMS chip.

39

Chapter 3. MOSIS Post-Processing and Thermal Analysis of

Biosensor Array Sites

Analysis of the biosensor array sites is a key component in the design of the
MEMS biosensor system. Operation of the system as a whole must first be analyzed by
thermal analysis and simulation techniques on individual array site structures to gain an
understanding of their operation. After testing and characterization of individual sites has
been completed, a better understanding of how these sites will operate and interact with
one another can be achieved. On the whole, interaction between array sites is not desired.
Ideally in a biosensor array system each array site will be sensing for a different
substance and one site should not interfere with the operation of any other sites in the
system. One key aspect to this work is the idea of temperature controlled biosensor array
sites. It is known that in biosensors there is usually some temperature for which
operation of the biosensor is optimized and this is usually at room temperature or above.
Also of note is the fact that longevity of the biosensor itself can be lengthened by keeping
the biosensor in a low temperature environment. These two factors must be combined to
not only extend the lifetime and operation of the sensor itself, but also to achieve the best
results from the sensor. In order to achieve this goal, each array site is designed with a
heating element and a temperature sensing element. However, each array site must be
sufficiently thermally isolated from the system to ensure proper operation of the
biosensors. In order to ensure operation of the system, thermodynamic and heat transfer

analysis is a crucial component in the design of the biosensor array sites. This chapter

40

focuses on heat transfer analysis and the basic principals involved that will lead to several

design possibilities for array sites.

3.1 Proposed MEMS Structures

The basic fabrication techniques covered thus far are vital for the successful
fabrication of MEMS devices. In IC fabrication, the primary interest is in the electronic
properties of the materials used. The materials are used to design transistors and other
circuit elements in combination to build complex devices sometimes consisting of
millions of transistors. One of the key features of microelectronics and planar
microfabrication technologies is its ability to form millions of electronic devices on a
small substrate and then utilize these simple functions to implement a complex task, cost
effectively. MEMS fabrication uses many of the same techniques as IC fabrication to
generate complex systems of mechanical devices. There are many microstructures of
different shapes, sizes, and materials that can be fabricated. These structures include
beams, diaphragms, bridges, and numerous other structures. Many of these structures
need specialized techniques to be fabricated. For the proposed MEMS biosensor chip,
there are a few possibilities for creating isolated thermal structures post-CMOS which are
derived from two basic techniques: silicon bulk rnicromachining and surface
rnicromachining.

Silicon bulk rnicromachining is a very common technique used in MEMS
fabrication. Bulk rnicromachining consists of removing the bulk silicon, usually using
wet etching techniques, to realize MEMS structures. It is very common to use backside
etching which is taking away silicon from the backside of the wafer to realize thin films

and diaphragms. This can be a very useful technique; however backside alignment to

41

circuitry and structures on the front side can be extremely difficult. Another common
technique in bulk rnicromachining is to utilize some masking layer on the frontside of a
wafer and to etch the bulk silicon from underneath.

Surface micromachining is ofien referred to as sacrificial rnicromachining. In
surface rnicromachining deposited thin films are used for both mechanical and sacrificial
layers. All types of standard CMOS materials can be used. Multiple steps are required in
this process to realize some structures, but in many cases surface rnicromachining can be
described by two steps. In the first step, a mechanical layer is deposited over a sacrificial
layer and somehow anchored to the bulk substrate. In the final step the sacrificial layer is
etched away to release the mechanical microstructure. A critical requirement in this
release process is that an etchant removes the sacrificial layer very quickly and stops on
the mechanical structure. One of the main advantages of surface rnicromachining is that
many layers can be deposited and patterned on top of one another.

The desired MEMS structure for the heated biosensor array is one that will
provide sufficient thermal isolation for each array site from its nearest neighbor. Two
techniques, backside bulk rnicromachining and a combination of frontside sacrificial
rnicromachining and bulk rnicromachining, can be used to generate a structure capable of
providing such isolation. Examples of these structures can be seen in Figure 3.1. The
issues, including feasibility, associated with each of these structures and the chosen

fabrication process will be discussed in further detail.

42

Etched pit after 2 step etch

      
 

Metal 3

_ Electrode

 

Backside Etched Pit

 

 

Figure 3-1: (Left) Suspended structure fbrmed by an anisotropic etch procedure. (Right) Isolated
diaphragm formed using a backside etching procedure.

3.2 MOSIS Post-CMOS Processing

As previously mentioned the fabrication of circuitry for control of a MEMS
system is usually always performed by a fabrication service. In this research the MOSIS
service is used for the base fabrication of the MEMS system. MOSIS is a low-cost
prototyping and small-volume production service for VLSI circuit development. Since
1981, MOSIS has fabricated more than 50,000 circuit designs for commercial firms,
government agencies, and research and educational institutions around the world [30].

The process being used is AMI Semiconductor’s (AMIS) C5F/N 0.5 micron
process. This is a non-silicided CMOS process with 3 available metal layers and 2 poly
layers, and a high resistance layer. Stacked contacts are supported. The process is for 5
volt applications. PiP (poly2 over poly) capacitors (950 aF/umz) are available but not
used for this research. This is a planarized process which does add some degree of

difficulty into the design and post-fabrication processing which will be discussed. In

43

addition to this issue, the circuit die to be fabricated are 3mm x 3mm x 500nm which
poses several problems. These and other issues will be discussed as the processing
techniques already discussed are applied to the MOSIS die. Trial experiments were
performed on 2.2mm x 2.2mm x 500nm die to gain some insight into the post-processing

steps on MOSIS die and to workout some critical issues involved with these steps.

3.2.1 Photolithography

As previously mentioned lithography is the most expensive, complex, and critical
process in mainstream microelectronic fabrication. The very first step to be performed on
MOSIS die will be photolithography and difficulties associated with photolithography
become apparent. The post-processing flow will consist of deposition of biosensor
electrodes followed by etching procedures to generate thermally isolated regions.

The first photolithography step that must be performed on the die is the spinning
of PR. Normally on the wafer level when the PR is being spun across a large uniform
surface such as a fit“ wafer, uniformity of the PR layer across the wafer is not an issue.
When dealing with individual MOSIS die, however, uniformity of the PR layer on the die
surface is a crucial requirement. As discussed previously, small nonuniformities in the
PR layer can result in fabrication faults. In the first experiments a die was attached to the
surface of a wafer and patterning of PR was attempted. The wafer was placed on the
spinner and PR was spun on and after the necessary steps, patterning in the mask aligner
was attempted. Initial patterning yielded poor results and after investigation it was found
that the PR layer was not uniform across the surface of the die. Due to the viscosity and
surface tension of the liquid PR at the corners of the die, caused by the height of the die

above the wafer, the PR was thicker at the four corners. As mentioned, patterning of the

44

PR was inconsistent and results were poor. This issue needed to be resolved in order to
ensure repeatability and consistency when performing the post-processing
photolithographic procedure. There are a couple of solutions to this problem, one is to
use a spray-on type PR layer and the other is to design a die holder for post-processing

steps that leaves the die surface level with the holder on the spinner.

. D' .
1e nger Dre

/' / \

l/ ‘ 'OV,
7 t \A "
{‘1‘- ‘ . “:'$ 'JDIII' "- " 1‘0“.“ ’- [I 5 ¢ i' x" u ' _ 'V'n . "9] I‘- ‘ :1 - ' :"“u u ‘l‘flls’h' L. " - ‘L'Im ‘L.“ . . '. t In. a I 0‘ « l’ e ’ '.- -14U

 

Figure 3-2: (Left) Initial experimental setup with MOSIS die attached to a silicon wafer. (Right) Proposed
die holder for MOSIS die. Consists of a recessed area in either aluminum or Teflon.

The first option to use a spray-on PR was not chosen for a couple of reasons. First, a new
process would have to be learned and perfected. Also, these chemicals can be quite
expensive when compared to conventional photoresists. The option of creating a holder
is chosen for this work. Preliminary experiments were conducted using die holders from
MOSIS for PR application as seen in figure 3-3. This approach yielded much better
uniformity across the die. There were still some issues, but they were greatly reduced
and the PR could be effectively patterned with some consistency. When a specially
designed die holder is made results should improve for the PR application. There are two
die holders that will be made for this research one made out of glass for PR and material

deposition steps and a holder made from Teflon for etching procedures.

Microfiche Masking

Masking procedures were performed on MOSIS die using transparency masks

generated through microfiche technology [31, 32]. This masking technique can achieve

45

features in the 1-10um range depending on the reduction ratio used when generating the

microfiche. For this work a 25x reduction was performed onto film by MicroGraphics

Plus, Inc. [33].

3.2.2 MOSIS Post-CMOS Metal Deposition

The next key processing technique will be to deposit the various metal layers
needed for the formation of a working biosensor system. Electron beam evaporation will
be used in this research for the deposition of the metal layers. One major reason this
approach has been chosen is due to the die temperature. The die is held basically at room
temperature so there will be no thermal complications to the fabricated die. Another
reason electron beam evaporation has been chosen is because of the reproducibility of the
deposition. The system being used is very precise and basically identical results can be
achieved from one sample to the next. As previously mentioned, metal layers have been
deposited on MOSIS die. The results showed patterns were successfully transferred to
the die surface, but there were some inconsistencies in the transferred pattern. The results
improve with better PR uniformity so the design and implementation of the mentioned

die holders should yield acceptable results.

3.2.3 MOSIS Post-CMOS Etching

The final step in processing the MOSIS die will be to perform etching steps to
generate thermally isolated structures for the temperature controlled array sites. There
are two possibilities for generating thermal isolation regions on a MOSIS die. The first is
a backside etching technique. This technique is attractive because of the relative ease of

backside etching, the problems associated with a biosensor array containing electronics,

46

however, prevent this method from being practical. Figure 3-3 shows a very rudimentary

block diagram of the frontside of the die if backside etching is to be implemented.

   

 

 

 

 

 

. . ‘1'5-‘775‘5‘35'3'7" '3 V5 “9-“???
E“ _ I] If" ' - Electronic
I I I ‘9 j
I I I ,1: l
I I I i: '.

I.“ .

. pl

I I I g
I I I hit; . A
I I I

 

Figure 3-3: Basic block diagram of biosensor chip for backside etch design. Light grey regions represent
heater regions, dark grey regions represent areas where electronics are present.

The first issue that comes to mind when considering a backside etch is the presence of
electronics on the frontside of the die. Often with backside etching, the etching is
allowed to proceed for a long period of time after which the etch stops on some layer,
usually an insulator. This is a huge issue for this layout, since the etch would dissolve the
necessary doped layers for transistor operation if it was allowed to continue until
reaching the oxide at the wafer surface. A simple one step anisotropic etch would not
work for this setup. In order for backside etching to work, a two step etch procedure
would be required. The first etch would be a large, one region, timed bulk etch. This
step would not require careful alignment and would need to be stopped at some depth
below the surface where electronics in the array would not be affected. The second etch
would be consist of nine separate anisotropic etch regions that would need to be masked
by some layer that is not effected by the etchant and then aligned to features on the

frontside to ensure proper isolation for each array site. This is a complex procedure that

47

would be very difficult to duplicate time and time again if it was even achievable with the

fabrication facilities used for this work.

Residual
Material

 

Figure 3-4: Microstructure design with residuals left in designed openings to silicon substrate. Residuals
are a result of the AM planarized process.

The second option is to use a frontside processing procedure utilizing process
layers as the appropriate masking and sacrificial layers to realize a thermally isolated
structure. Ideally we would like to have a series of layers that would leave an opening to
the silicon surface after fabrication steps. Normally this would consist of drawing layers
of Active, Contact, via layers, and Overglass. These layers generate the appropriate
openings in passivation layers between the material layers in a CMOS process. This is
exactly what happens in a CMOS process which has larger feature sizes. In these
processes a conformal surface does not cause serious issues for device fabrication and
their operation. However, when feature sizes are scaled down and more layers are added
to a process it becomes very difficult to fabricate devices unless the surface is planar
between all layers as they are generated. In a planarized process there are many more
design rules that must be followed especially when dealing with interconnect layers such

as contact or via. Because of these restrictions and the nature of the planarized process,

48

openings to the silicon substrate are not possible directly from the fabrication facility.
Preliminary test procedures were created on past fabrication runs to test the validity of
this hypothesis. As seen in the Figure 3-4, residues can clearly be seen in the regions that
one might expect to contain bare silicon. The AMI C5F/N process does not allow for
oversize contacts or vias so materials are deposited into these regions. This material can
be etched away, but it is difficult to mask the rest of the die to protect against the harsh
chemicals used to perform such an etch. Because of this problem, it is necessary to use a
sacrificial micromachining technique which employs the existing layers in the AMI
C5F/N process to expose the silicon surface. There are two possibilities here which both
incorporate openings in the overglass layer from the fab house as a starting point after all

electrode deposition has been carried out.

    

 

 

Overglass
Metal3 :_ .. I I . / Via2
Metalz‘ _ ,. ._ ' ——-— Vial
Metal] IIIII‘IIIIII_IMIIIII‘III " “___
POIyz IIIIII III! I IEI‘I II III ‘ CC
Poly] lIlIlllIlIrIIIL TIILIII :

Figure 3-5: First sacrificial etch design. Metal and via layers are used as sacrificial layers. In this design
a post-CMOS metal etch will be performed to remove all metal and via layers leading to the silicon
substrate, not protected by a PR mask layer. An additional oxide etch may be required to successfully
reach the silicon surface, but this will be determined through experimental trial. After all layers are
removed an anisotropic etch step will be performed to undercut and realize suspended LEMS structures.

49

It is imperative that any post-processing for the addition of features, such as
electrodes, other than the etched structures be carried out before the rnicromachining
steps. After these steps have been carried out the entire wafer other than the areas to be
sacrificed be protected by the PR masking layer. The sacrificial designs are illustrated in
Figures 3-5 and 3-6.

Overglass

Poly 2
Poly 1

 

Figure 3-6: Second sacrificial etch design. Insulating dielectric layers are used as sacrificial layers. In
this design, a post-CMOS oxide etch will be performed to remove all dielectric layers leading to the silicon
substrate, not protected by a PR mask layer. After all oxide is removed an anisotropic etch step will be
performed to undercut and realize suspended ME MS structures.

Both of these designs will utilize a PR masking layer, since it is not attacked by
the aluminum or oxide etchant. The etching procedure in the case of sacrificial structure
with metal layers and vias will consist of a two etch process. The first etch will be an
aluminum etch. This will clear out the metal 3,2, and 1 layers. After the metal is etched
away, there will be hundreds of contact holes down to the silicon, but there will also be
oxide passivation layers with via and contact holes through them. So the second etch step
will be to conduct an oxide etch to remove these layers and expose the silicon surface.
Another option is to conduct an isotropic silicon etch as the second step. This will

undercut the bottom passivation layer and should expose a large area of silicon that can

50

then be etched with an anisotropic etchant to create the suspended structure as proposed.
The second option is to again mask the die in PR only exposing the overglass openings
and then performing an oxide etch on the remaining oxide underneath the opening. This
oxide layer is around 2pm thick so the etch will be a longer etch. After the silicon is
exposed an anisotropic etch will be performed to realize the proposed MEMS suspended
structure. This structure will provide excellent thermal isolation and support for the

biosensor system.

 

 

-5117". Eli :' : ‘Ic
' Regions

 

 

 

 

Etched Plt
Regions

 

 

Heater Regions

 

 

Figure 3-7: Basic block diagram of biosensor chip for frontside sacrificial etch design. Light grey regions
represent heater regions, dark grey regions represent areas where electronics are present.

3.6 Simulation and Heat Transfer Analysis Results for Isolation Structures

The following subsections provide descriptions of thermal analysis as it applies to
the estimation of heat transfer out of the system due to convection, choice of resistive
heating element, and finally a comparison and discussion of the various thermal isolation
schemes possible through this design. All thermal power estimations were made at the

high end of the biosensor operational spectrum with the assumption that the maximum

51

temperature difference between the heater and ambient environment will be around 70°C.

This was done so that a high end limit could be established for device characterization.

3.6.1 Validation of Heat Transfer Analysis

The first step in the analysis of the proposed structures is to verify the appropriate
modeling for the thermal structures. This discussion will begin by showing the possible

thermal structures available through this design.

Non-Thermally Isolated Structure

The first possible structure for the biosensor array site is the simplest one, no
post-processing steps performed on the die, and its basic structure is shown in Figure 3-8
below.

liquid reservoir

thin film layer
biomimedic membrane
electrode metal
metal3

dielectric
metal2

dielectric
metal1

dielectric
pols/2

dielectric
po|y1
dielectric (FOX)

/

Electrode Region I

silicon substrate

 

   

solid heat sink

Figure 3-8 (Left) Basic biosensor array site with no post-processing steps performed, (Right) layer
structure taken into consideration for basic heatflow modeling.
There are two possible environments in which this system can operate, air or
water. Both of these systems operate under the assumption that there is a high thermal

resistance above the heater due to the heat transfer characteristic of the thin film layer.

However, there is very little thermal resistance below the heating element due to the high

52

conductivity of the silicon layer. This structure offers low thermal isolation, however the
chip can be operated with minimum post-processing. The downsides to this approach are
limited operational range and thermal contamination to surrounding array sites. These

issues will be discussed in subsequent sections. mm" 1mm" 2 "“P “c"

Thermally Isolated Structures

Several other structures are possible in

  
 

Metal 3
_ Electrode

this design with varying degrees of post-

processing steps and each of these structures

 

introduces thermal isolation into the design.

 

Each thermal isolation variation stems from

Figure 3-9: Suspended Island Structure.
the suspended island as seen on the right. The
suspended island is one of the most basic and widely utilized MEMS structures. Quite

often this design shows up in thermal isolation and heating applications. This structure

was decided upon due to ease of fabrication and wide use in the MEMS arena.

Basic Suspended Island

The most basic and easily fabricated structure for thermal isolation is the
suspended island structure. There are two operational possibilities for this structure;
operation in air or in water. Figure 3.9 shows the situation where the microsystem is
immersed and operated in an aqueous environment. This is the most likely structure and
operating environment for biosensor applications. There is also the possibility of
operating this structure in air, however this situation would only be used for little more

than verification of functionality for the heating and temperature sensing array. The

53

structure is exactly as shown in Figure 3-10, except the water is replaced with air. In

both instances, operation in air or water, this structure provides high thermal isolation and

allows for a wide operational range.

liquid reservoir

1 hin film
biomimedic membrane
electrode metal
meta13
dielectric
metalZ
dielectric
metal1
dielectric
poly2
dielectric

poly1

dielectric (FOX)
t hin film
liquid

 

silicon substrate
solid heat sink

 

Figure 3-10: (Left) Cross-section of basic biosensor array site with etch release steps performed and water
above and below the heating element, (Right) layer structure taken into consideration for basic heat flow
modeling.

Sealed Cavity

Another thermal isolation design possible with the suspended island as a base for
fabrication in the sealed cavity design. This structure is generated via standard low
temperature, conformal oxide deposition after the heater region has been undercut. The
steps involved in generating this structure are more advanced, which is a negative for this
structure. There are again two operational possibilities for this structure; operation in air
or in water, however the cavity below will always consist of air. Figure 3.1] shows the
situation where the microsystem is operated in air. There is also the possibility of
operating this structure in an aqueous environment, which would be used in biosensor

applications.

54

liquid reservoir

thin film layer
biomimedic membrane
electrode metal
metal3
dielectric
metal2
dielectric
metalt
dielectric
poly2
dielectric
poly1
dielectric (FOX)

 

air
silicon substrate

 

 

solid heat sink

Figure 3-11: (Left) Sealed air cavity biosensor array site with etch release and fill steps performed,
(Right) layer structure taken into consideration for basic heat flow modeling.

Etched Pit Filled with Insulator

The final envisioned variation on the suspended island structure involves
releasing the structure and the filling the pit region with a spin on dielectric using basic

fabrication techniques. The cross-section of this structure is shown below

l1 WW1 liquid reservoir

thin film layer
biomimedic membrane
electrode metal
meta

dielectric
metal2

dielectric
meta|1

dielectric
pom

dielectric

Spin-(3n Dielectn'
Layer

poly1
dielectric (FOX)

dielectric
silicon substrate

 

   

solid heat sink

Figure 3-12: (Left) Basic biosensor array site with etch release and fill steps performed, (Right) layer
structure taken into consideration for basic heat flow modeling.

55

Thermal Modeling Approach

As discussed in chapter three a thermally equivalent circuit can be used to
estimate operation of the Joule heated system. In all of the structures proposed above,
both thermally and non-thermally isolated, one thing is constant, a fluid/solid interface
where heat transfer due to natural convection is occurring. The fluid can either be air or
water as shown above. There are two equations which can be utilized in determining this
coefficient; Eq. 2-24 and Eq. 2-25. It is important that an accurate estimate is found for
this parameter to provide a decent prediction of the system’s operation, since this layer is
the largest thermal barrier in all cases. Simulations were run on each structural variation
for each equation and then the results were compared to comparable structures and
MEMS systems in literature. Through experimental trial it is found that Eq. 2-25
provides a more accurate estimate of the heat transfer coefficient for our heating situation
due to the agreement between the expected operational results and other works. For this
reason Eq. 2-25 is used when determining the heat transfer coefficient for analysis in this
section. Results from Eq. 2-24 can be observed for all structures in the tables of the

Appendix.

3.6.2 Resistor Value for Heating Element

This design incorporates several resistor values for the polysilicon. heating
element. These values were chosen before proper heat transfer analysis could be carried
out to give a better idea of an appropriate resistor value. The values of 3400, 1.05m,
and 2.616) were chosen due to the lOOmicron square size constraints and these are
comparable to values in literature. In determining which resistor value is the most

appropriate, the peak output power dissipated from the heater resistor must be determined

56

for this process. The maximum power a resistor can dissipate is given by P= V2 / R . The

maximum voltage that can be used for this AMI process is 10V without causing damage
to the metal supply lines, therefore the maximum power can easily be determined for

each of the resistor values.

Table 2: Maximum Allowable Power Dissipated Across Heater Element.

 

340 0 Heater 1.05 k!) Heater 2.6 k!) Heater

 

 

Power dissipated at

10V peak voltage 294 mW 95-2 mW 38-5 mW

 

 

 

 

In order to determine how these values fit into the analysis of the system, the heating of
the structure with the worst thermal isolation is used to determine the maximum needed
power to heat to the peak temperature of 70°C. Table 3 shows results for this simulation

which was carried out in Spice.

Table 3: Current required to provide sufficient Joule heating eflects from polysilicon heating element in
water without thermally isolated MEMS structure. Voltage levels formatted as bold are too high for AM]

process.

 

Heater Structure with Water Above and No Isolation Below

 

Power 340 Q Resistor 1050 Q Resistor 2600 S2 Resistor
Scenario Estimated Power Estimated Power Estimated Power and

and Voltage Level and Voltage Level Current Level for 70°
for 70° Temperature for 700 Temperature Temperature Change

 

 

 

 

 

Change Chgge
Spice Thermal 232.8 mW 232.8 mW 232.8 mW
Modeling
using Eq. 2-25 8.897 V 15.6 V 24.6 V

 

From these simulations it is clear that the only heater value that is suitable across all
structural possibilities while still maintaining the maximum temperature is the 3000
resistor. The other resistor values are suitable for structures that provide thermal

isolation, however the 3409 heater is used for all testing and characterization purposes.

57

 

 

The values for all structures for all heater resistive values can be found in table form in

the Appendix.

3.6.3 Simulation Results and Comparison for Possible Structures

The structure of choice for this work is one that can provide sufficient iZR

heating, provide appropriate thermal isolation, and is also easy to fabricate. Table 4

provides a breakdown of each structure and its operational characteristics including

fabrication complexity.

Table 4: Operational comparison of various structures operated at 70 °C.

 

 

 

 

 

 

 

 

340 9 Heating Power Voltage Level Current Level Processing
Element at Required Complexity
70°C
N on-isolated Low
structure in 200.6 mW 8.26 V 24.3 rnA No masking
air required
Non-isolated Low
structure in 232.8 mW 8.897 V 26.2 mA No masking
water required
3'33““ Medium
. 13.73 mW 2.16 V 6.35 mA 1 Masking step
structure in .
required
water
Ellisfiflnded Medium
. 303.7 uW 0.321 V 0.944 mA 1 Masking step
structure In .
. required
arr
Sealed air High
“my . 303.7 aw 0.321 v 0.944 mA Mult‘l’le
structure in masking and
air etching steps
Sealed air High
“my . 7.07 mW 1.55 v 4.56 mA M‘m‘ple
structure In masking and
water etching steps

 

 

 

 

 

58

 

The following graph shows data for the structures in graphical form including the level of
thermal isolation provided when compared to the structure with the best thermal

isolation.

Performance Results for each Structure

Scaled Value 10 Considered Highest

 

 

 

 

 

 

 

. o 0 'x . s L _
«<9 . 9&9 be” 606 60$ «C? rI Power Required Normalized
$0 0; be, 00 \0 ’b‘ IVottage Level Nmnarized
o Q ’0 6 ElCurrent Level Normdlzed
e 0 0°.) 90 \e _ ,
(9Q % 00 El Process Complexrty Normalized
(~00 ‘b ULevel orrhormai isolation
Structure

Figure 3-13: Comparison of various structures. Y-axis is a 1-10 scale for the particular value of interest,
10 being a maximum value. X-axis composed of various structures. Values are normalized to values of 0-
10 based on maximum value for category fiom Table 4. Structures with low power characteristics, low
process complexity, and high thermal isolation are the most desired structures.

59

Figure 3-13 shows that the best isolation is provided by the structures with air
above and below, however these structures are not feasible for a biosensor since they
need an aqueous environment and will only prove useful for operational testing. The
structures, which are immersed in water, show the best performance results overall are
for the isolated structure with the sealed air cavity. There is a tradeoff for this structure,
in that it is very difficult to fabricate. Because of these factors the optimal structure for
biosensors is the suspended island structure in water. This structure provides high
thermal isolation, it can be operated across the entire operational range, and the

fabrication process is basic.

60

Chapter 4: Biosensor Array Microsystem

An array for biosensor applications has been designed. The biosensor array
consists of a 3x3 array of elements. Each array site has individual temperature sensing

and heating capabilities. The block diagram for this chip design is shown in Figure 4-1,

 

 

 

 

 

below.
as m? .. a Chip
. ' ' .. . Temperature
. Reference Ele trode] ~ . Sensor
Array Site ;‘ t: Heater ,
Control _2 d Auxrllory
Circuitry ‘ ii on Electrode

s4.» Temperature «C
Sensor Arroy »

 

 

 

. a
.‘

 

 

“'1' ”Us

TeSt Circuitry

 

 

 

 

L.

 

 

 

 

 

 

Figure 4-1: Basic block diagram of MEMS biosensor chip design

The necessary control circuitry for the array consists of row and column decoders
and signal buffers. This and other circuitry will be the major focus of this chapter. The

design principals and simulations will be covered.

61

 

Figure 4-2: Photograph of fabricated circuit die prior to MEMS fabrication procedures
4.1 Array Site Selection Circuitry

This research consists of an array of elements for the purpose of multi element
testing and thermal characterization. Anytime an army of elements is used there needs to
be some kind of decoding in order to select the array site of interest. In this design the
decoder used is a NOR type decoder as seen in Figure 4.3. The operation of this circuit is
straight forward. There are two control bits, S0 and 81, which determine which bit line
will be activated. The row and column decoders are identical in this design and both use
the above circuit. The only input combination for any of the NOR gates that will yield a
high output is 00. Therefore depending on the input signals, only one bit line can be

logic high at any time. The operation of the decoder is given in Table 5.

62

 

=>
so Y \fn _ PG r—r— \Blt 3
SI ——/ "/1 /“'j ' —,-:."\f J ,

Figure 4—3: Schematic of NOR decoder used in array selection circuit design.

Table 5: Bit line selection for column and row decoders.

 

 

 

 

 

 

 

Selection Bit Input (SO 81) Bit Line Activated
00 Bit 0
01 Bit_l
10 Bit 2
11 Bit_3

 

As seen in Figure 4-3, each bit line is equipped with a transmission gate followed
by a discharge resistor. The transmission gate is controlled by an enable bit. This is
simply present so that the array as a whole can be turned on or off. The ground
connected transistor is present to discharge the bit line immediately when it is no longer
active. Due to the large loads on the bit lines, there is a longer delay in the response of

the bit lines that could cause errors in array operation.

63

 

There are two main blocks which utilize this row and column decoding scheme;
the heater array and temperature sensing array. Each of these blocks has its own
decoding network with select bits independent of the other network. This feature is to not
only keep one block’s operation completely independent of the other, but also to allow
for testing of thermal isolation by checking if there is thermal leakage form one array site
to adjacent sites. One other thing to note is the presence of four bit line for the rows and
columns, yet we are using a 3x3 array. There was not sufficient chip area available to
generate a 4x4 array so the array dimensions were brought down. Due to this factor, row

bit_0 and colunm bit_3 are not connected to any active circuitry in the system.

4.2 Heater Array

A key feature of the design is the ability to incorporate heating into each array
site. There are two main advantages to this feature. First, the lifetime of the biosensors is
extended. Secondly, the sensors are more robust. The heaters are simple polysilicon
resistors of varying sizes that will experience joule heating due to the power across the
resistor. This is a common technique uSed in numerous research for heating MEMS and
circuit designs [34-3 8]. Polysilicon heaters have been designed using a serpentine type of
design in several sizes. The amount of current through each heating element is basically
limited by the Maximum allowed Vdd for the AMI process. This voltage is 5 volts,
however a voltage of 10 volts may be safely used due to the direct connection to the
voltage source with wide supply lines. However, larger voltages may cause the metal
lines to degrade over time. There are several heater iterations that have been designed for
the array sites. All of the resistive poly heaters cover the same chip area, 100nm x

100nm, yet they do differ in resistive values. The purpose of this is to determine what

64

resistive value will yield the best heating results and controllability given our process and
thermal operation range for the biosensors. Four resistive values, 1950, 3000, 1.05m,
and 2.6m, have been implemented into the 9x9 array. These values coincide with values

used in prior research of polysilicon heaters. The following table shows the results from

circuit simulations for the maximum current through each heater for 5V and 10V.

Table 6: Current levels through heater resistors through Spice circuit simulation.

 

 

 

 

 

 

Resistive Value Current at 5V Supply Current at 10V Supply
195 9 19.23 mA 38.46 mA
340 O 12.69 mA 25.38 mA
1.05 k!) 4.56 mA 9.12 mA
2.6 k!) 1.89 mA 3.78 mA

 

 

 

 

These current levels are also in line with those reported in research for achieving
joule heating effects for temperatures up to 180°C for systems that provide sufficient
thermal isolation. The temperature range we will be working in is roughly 0-100°C, so
there should be no major issues with achieving the desired response from the heating
elements under heating conditions with sufficient thermal isolation. This becomes
apparent when looking at the heat transfer analysis for each of the proposed structures as
laid out in Chapter 3. It is also seen that for the situation where there is no thermal
isolation, a wide operational temperature range may not be possible with the restrictions
placed on the current levels due to voltage limitations for the AMI process used for
device fabrication. The approximations made through basic heat transfer analysis will

need to be verified through testing of the polysilicon heating system.

65

4.3 Temperature Sensing Network

The ability to accurately measure the ambient temperature as well as the
temperature at each array site is key to proper operation and calibration of the system.
There are several main components that will allow these goals to be achieved from a
design standpoint. The design and operation of the resistive bridge circuit for
temperature sensing at the array sites, the temperature sensor array sites, and the basic

ambient sensor will be discussed.

4.3.1 Resistive Bridge Network

A Wheatstone bridge is used for detecting the small variations in the resistive
value for the temperature sensor resistor. The Wheatstone bridge circuit basically
consists of two voltage dividers with matched resistors. The bridge configuration

designed for this chip is shown in the Figure 4-4.

R 51:53 R
V_Temp l
———O C)-

 

R 'T_sensor
l

Figure 4-4: Bridge configuration for temperature sensing network of MEMS system

The bridge circuit operation is quite straight forward. A control voltage is applied
to the circuit which will establish a voltage differential which is defined by the two
voltage dividers. In this system, all resistors are matched on the layout and, other than
the temperature sensor resistor which is located at an array site, all resistors are very close
on chip to ensure device matching. The first voltage divider in the middle of the circuit is

governed by the following:

66

R V
V : V ’ — :——-IN E 04.]
our, IA [R+R) 2 q

Since the resistors are matched this is the behavior we expect from the circuit. The
second voltage divider is a bit different. The resistors are also matched, however one of
these resistors is being used as a temperature sensor. This changes the circuit because the
temperature sensor is located directly above a heating element and is at a temperature
different from the background temperature of the rest of the chip. The resistive value of

the temperature sensor will be R + ART , where ART is given by the following equation:
AR = apRAT

where ap is the TCR of the polysilicon temperature sensor resistor as described in 3.4.4.

Using this relationship we have an equation for the second voltage divider given by,

R + AR
Var/r, = Vm {—2 R + AR) Eq. 4-2

If there is no difference in temperature the temperature sensor will have a AR of
zero so the output voltage will simplify to Eq. 4-1. The voltage of interest in the bridge
circuit, to determine if there is any temperature difference is the difference between

V0,”! and Vorm- The output voltage, V_temp given in Eq. 4-2, will correspond to a

temperature difference on the temperature sensor resistor.

 

—ART
V r = [5.4-3
-emp [2(2R+ART)] q

Ideally, with no heating and the chip at some constant temperature, this output voltage
would be zero. In order to achieve this, however, all resistors would have to be perfectly

matched and interconnect resistances would also need to be matched. At first glance this

67

equation may seem useless, however when we combine and rearrange the above

equations, the result is:

4V _ temp

AT =
—ap (Vm +2V_temp)

 

Eq. 4-4

This is an important relationship since the temperature at the temperature sensor can be

found given ap is known. The TCR will be found by characterizing the change in

resistance of a temperature sensor resistor over a wide temperature range in a highly
controlled temperature environment. AT is the difference in temperature between the
reference temperature at which the chip is held and the temperature at the heated array
site which is connected to the bridge circuit. In order to ensure accuracy in the
temperature readings, careful derivations of the resistance and TCR must be made. Also,
the changes in resistance will be small relative to the overall resistor value so the

V _temp must be amplified to ensure small changes in temperature will accurately be

recorded.

4.3.2 Temperature Array Sites

Each array site in this design has a temperature sensor with the sole purpose of
measuring the temperature at the array site relative to the background temperature. The
temperature sensing operation of the resistors is based on the TCR of the material as
previously described. This is a common technique used in many commercial temperature
sensing devices. However, a material such as platinum is usually used for the
temperature sensing resistor. Polysilicon is used in this research due to the availability of
the material in the chosen fabrication process and the close proximity of the layer with

respect to the heating layer. Polysilicon temperature sensors have been designed using a

68

serpentine type of design as with the heaters. Contrary to the operation of the heating
elements, self heating of the temperature sensing resistor would be detrimental to the
accuracy of temperature measurements. These effects cannot be completely eliminated,
however they can be kept at a negligible level. The amount of current through each
heating element must be kept very small in order to achieve basically no self-heating and
there are two basic techniques which can be employed to do this. The first is to make the
resistive value of the temperature sensing resistor large. Due to Ohm’s Law the current
will be reduced. The voltage driving the bridge readout circuit can also be reduced to
minimize the current levels. Since the voltage difference due to temperature will be
amplified when performing temperature measurements, reducing the drive voltage should
not pose any major operation issues. Again careful testing and characterization of the
readout process will be required to find the optimum readout condition. The variable that
was designed and cannot be changed is the nominal value of the temperature sensing and
bridge circuit resistors. These resistors were all designed with resistance values of 200

kg). The circuit schematic for a temperature sensing site is seen in Figure 4-5.

Bridge Connection

?

.. R
Buffer I

I'OW _-

col—

 

Figure 4—5: Circuit schematic array temperature sensing site.

69

The circuit is controlled by the described decoding scheme. The signal is then
buffered to provide the necessary drive to the large transistor, which, when enabled,
connects the chosen temperature sensor into the bridge circuit. There is only one bridge
circuit for the entire array so the buffer must be capable of driving the large capacitance
associated with the nine array sites basically in parallel. The response time of the array
bridge combination circuit is on the order of microseconds which is more than adequate
for proper operation of this feature. The reason behind the large transistor is to minimize
the resistance of the MOSFET. In doing so the voltage dividers of the bridge circuit
should be closely matched. Additional simulations on the expected operation of the

temperature sensing network, given the TCR of the poly resistors is known.

4.4 Thermal Isolation Design

As previously discussed the need for thermal isolation in this design is key. The
suspended structures will be generated by taking advantage of the fabrication layers
available and performing post-CMOS fabrication micromachining techniques. It is
imperative that extreme care is taken when performing these procedures to ensure circuit
functionality and to minimize contamination to the system. These points and in depth

coverage of the thermal isolation designs are covered in Chapters 2 and 3.

4.5 Ambient Temperature Sensor

There is also the need to know the background temperature of the environment for
accurately performing the temperature measurements using the bridge circuit.
Generation one of this design uses a simple polysilicon resistor as the temperature sensor.
This approach is crude but will give a decent approximation of environmental

temperature to ensure that the basic operation of the thermal array can be verified.

70

4.6 Three Electrode System

A traditional three electrode sensor system is possible through this design. Each
array site contains a working electrode. There is one reference electrode and auxiliary
electrode for the chip. Together all of these electrodes can be connected to a readout

device and measurements such as cyclic voltammeter can be performed.

4.7 Results

Results were achieved for this design, in depth characterization was not done. A
3mm x 3mm circuit die was fabricated through the MOSIS foundry service using the
AMI CSF/N 0.5 micron process. This chip contains all blocks as described in this
document. Basic functionality was verified through laboratory simulation and

experiment in several areas.

4.7.] MEMS Post-Processing Results

MEMS post-processing steps were successfully achieved on the MOSIS die.
Successful photolithographic and deposition steps were carried out as seen in Figure 4-6.
The PR application was carried out using a standard PR spinner with the die in a holder
as previously described. Patterns were then generated on the die surface using a Karl-
Suss contact mask aligner. The masks used were standard CMOS masks. Metal

deposition steps were carried out in an e-beam evaporation system.

71

t
=.100 Microns

l-—-l

 

Figure 4-6: Die photo of chromium patients transferred onto MOSIS die through standard CMOS
processing steps.

The next and most important verification was to perform the necessary steps and
show that the design for generation of suspended structures was successful. Suspended

structures were generated ass seen in figure 4-7.

 

Figure 4-7: (Left) Photograph of heater array site surface after etch and release steps. (Right) Same array

site with focus on the bottom of the etched pit approximately4o microns in depth.

The etching procedure consisted of an aluminum etch followed by an oxide etch

to reach the silicon substrate. The final etching step was an anisotropic wet etch in

72

TMAH for almost 60 minutes. More experiments are required to perfect this procedure,

but the design has been verified though trial.

4.7.2 Circuit Functionality

Functionality of the individual circuit blocks was not necessary for this work.
The only circuitry that was tested was an individual array site for functionality. Using a
probe station and a microscope, a voltage was applied across a 3000 heater. The
resistance across the temperature sensor resistor directly above the heating element was
then monitored and showed an increase in resistance with temperature. This was the

expected result, however more in depth testing will be required to fully characterize this

MEMS device.

4.7.3 TCR of Polysilicon Temperature Sensor Resistor

The temperature coefficient of resistance for the polysilicon temperature sensor
was determined using the methodology discussed in 2.5.4 above. In order to extract the
necessary parameters accurately a highly controllable temperature environment was used.
A Bryant temperature chamber was used to control the temperature of the environment
over the range from —0.7°C to 65°C. A precise platinum temperature sensor was used to
provide temperature readings from within the chamber while resistive measurements
were made. Multiple resistive measurements were taken across the temperature range
and the TCR was determined to be 4.803x104K". This result is agreement with values

that are to be expected for doped polysilicon.

73

Chapter 5: Conclusions and Future Work

One of the main focuses of this work was to gain a clear understanding of the
various structural layers in a CMOS fabrication process for the design and
implementation of micromachined MEMS devices. A methodology for characterization
of a process, using test structures and past designs, for fabrication of MEMS devices
through a commercial planarized CMOS process was developed during the course of this
research. Necessary processing steps were carried out to show validity in the design and
the results indicate that this design was sound and thermally isolated suspended structures
are possible in small feature size planarized processes. These structures have the
potential to be used for thermal control of biosensor systems.

Another main focus of this research was the characterization and heat transfer
analysis of the heated array sites. Analysis and simulation on a basic level have shown
that proper device functionality is possible over the operating range of interest using the
AMI process and its limitations. This will be beneficial in future work and shows how
CMOS rnicromachining technology for a process with newer materials and applications

can be applied for MEMS applications

5.1 Future Work

Future work on this design will consist of full characterization and testing of the
thermal array. From heating to temperature sensing all aspects need to be tested so that
improvements can be made to this design. Biosensor material will also be deposited onto

the array sites to achieve a working sensor. Combining all findings from this work and

74

the testing procedure, necessary modifications will be made to the design and future

versions of this MEMS system will be generated.

75

APPENDIX

Table 7: Physical parameters and thermal properties for thermal modeling of suspended structure with
water as liquid above and below using [27].

 

Suspended Structure with Water as Liquid Above and Below

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer Material Approximate Thermal Heat Transfer Thermal
Name Thickness Conductivity, Coefficient Resistance
k due to Natural RT
(W/m'Ko) Convection, h (1y)
(calculated W
using
Eq. 2-24)
(W/m2 -K°)

Stagnant Water N/A N/A
Layer
(H20) 2773.78 36,015
Metal 3 Al, Cr, Au 130
Electrode Combo
Region 0.7 pm 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Metal 2 A1 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Metal 1 A1 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Poly 2 Polysilicon 0.4 pm 25 1.6
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.48
Poly 1 Polysilicon Heater Region: Heater Region:

N/A N/A N/A N/A

Field Silicon 1 ~15 34.73
Oxide Dioxide 0.4 pm
Stagnant Water N/A N/A
Layer
(H20) 2773.78 36,015

 

 

 

 

 

 

76

 

Table 8: Physical parameters and thermal properties for thermal modeling of suspended structure with
water as liquid above and below using Eq. 2-25.

 

Suspended Structure with Water as Liquid Above and Below

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer Material Approximate Thermal Heat Transfer Thermal
Name Thickness Conductivity, Coefficient Resistance
k due to Natural R,
(W/m-K°) Convection, h (1y)
(calculated W
using data
from Eq. 2-25)
mm. rK°)

Stagnant Water N/A N/ A
Layer
(H20) 9913 10,088
Metal 3 Al, Cr, Au 130
Electrode Combo
Region 0.7 pm 0.389
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.48
Metal 2 A1 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Metal 1 A1 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Poly 2 Polysilicon 0.4 pm 25 1.6
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.48
Poly 1 Polysilicon Heater Region: Heater Region:

N/A N/A N/A N/A

Field Silicon 1-15 34.78
Oxide Dioxide 0.4 pm
Stagnant Water N/A N/A
Layer
(H20) 9913 10,088

 

 

 

 

 

 

77

 

Table 9: Heat transfer results for multiple heater resistor values for suspended structure with water above

and below.

 

Suspended Structure with Water as Liquid Above and Below

 

 

 

 

 

 

Power 340 Q Resistor 1050 Q Resistor 2600 Q Resistor
Scenario Estimated Power Estimated Power and Estimated Power and
and Current Level Current Level for 70° Current Level for 70°
for 70° Temperature Temperature Change Temperature Change
Chaqge
Eq. 2-12 3.866 mW 3.866 mW 3.866 mW
Calculation
using Eq. 3.37 mA 1.919mA 1.219mA
2-24
Spice 3.866 mW 3.866 mW 3.866 mW
Thermal
Modeling 3.37 mA 1.919 mA 1.219 mA
using Eq.
2-24
Eq. 2-12 13.73 mW 13.73 mW 13.73 mW
Calculation
Using Eq. 6.35 mA 3.617 mA 2.30 mA
2-25
Spice 13.73 mW 13.73 mW 13.73 mW
Thermal
Modeling 6.35 mA 3.617 mA 2.30 mA
using Eq.
2-25

 

 

 

 

78

 

Table 10: Physical parameters and thermal properties for thermal modeling of suspended structure with
air as liquid above and below using [27].

 

Suspended Structure with Air as Liquid Above and Below

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer Material Approximate Thermal Heat Transfer Thermal
Name Thickness Conductivity, Coefficient Resistance
k due to Natural R1
(W/m'K°) Convection, h (1y)
(calculated W
using
Eq. 2-24)
(W/m2 -K°)

Stagnant Water N/A N/A
Layer
(H 20) 40.16 2,490,075
Metal 3 Al, Cr, Au 180
Electrode Combo
Region 0.7 pm 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Metal 2 A1 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Metal 1 A1 0.7 um 180 0.389
Oxide Silicon 1 -15

Dioxide 0.5 um 43.48
Poly 2 Polysilicon 0.4 pm 25 1.6
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Poly 1 Polysilicon Heater Region: Heater Region:

N/A N/A N/A N/A

Field Silicon 1-15 34.73
Oxide Dioxide 0.4 pm
Stagnant Water N/A N/A
Layer
(H 20) 40.16 2,490,075

 

 

 

 

 

 

79

 

Table 11: Physical parameters and thermal properties for thermal modeling of suspended structure with
air as liquid above and below using Eq. 2-25.

 

Suspended Structure with Air as Liquid Above and Below

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer Material Approximate Thermal Heat Transfer Thermal
Name Thickness Conductivity, Coefficient Resistance
k due to Natural R1
(W/m-K°) Convection, h (1y)
(calculated W
using data
from Eq. 2-25)
( W / m2 - K ° )

Stagnant Water N/A N/A
Layer
(”20) 216.8 461,254
Metal 3 Al, Cr, Au 180
Electrode Combo
Region 0.7 pm 0.389
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.48
Metal 2 A] 0.7 pm 180 0.389
Oxide Silicon 1 .15

Dioxide 0.5 pm 43.48
Metal 1 Al 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Poly 2 Polysilicon 0.4 pm 25 1.6
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Poly 1 Polysilicon Heater Region: Heater Region:

N/A N/A N/A N/A

Field Silicon 1-15 34.78
Oxide Dioxide 0.4 pm
Stagnant Water N/A N/A
Layer
(H20) 216.8 461,254

 

 

 

 

 

 

80

 

Table 12: Heat transfer results for multiple heater resistor values for suspended structure with air above

and below.

 

Suspended Structure with Air as Liquid Above and Below

 

 

 

 

 

 

Power 340 Q Resistor 1050 Q Resistor 2600 Q Resistor
Scenario Estimated Power Estimated Power and Estimated Power and
and Current Level Current Level for 70° Current Level for 70°
for 70" Temperature Temperature Change Temperature Change
Change
Eq. 2-12 1.43 uW 1.43 pW 1.43 11W
Calculation
using Eq. 64.8 pA 36.90 uA 23.50 uA
2-24
Spice 1.485 pW 1.485 uW 1.485 pW
Thermal
Modeling 66.1 pA 37.60 uA 23.90 uA
using Eq.
2-24
Eq. 2-12 303.45 uW 303.45 pW 303.45 pW
Calculation
Using Eq. 0.945 mA 0.538 mA 0.342 mA
2-25
Spice 303.7 uW 303.7 pW 303.7 pW
Thermal
Modeling 0.945 mA 0.538 mA 0.342 mA
using Eq.
2-25

 

 

 

 

81

 

Table 13: Physical parameters and thermal properties for thermal modeling of suspended structure with
water as above and air below using [27].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sus ended Structure with Water Above and Air Below
Layer Material Approximate Thermal Heat Transfer Thermal
Name Thickness Conductivity, Coefficient Resistance

k due to Natural R1
(W/m'K°) Convection, h (1y)
(calculated W
using
Eq. 2-24)
(W/m2 -K°)

Stagnant Water N/A N/A
Layer
(H20) 2773.78 36,015
Metal 3 Al, Cr, Au 130
Electrode Combo
Region Gym 0.389
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.48
Metal 2 A1 0.7 pm 180 0.389
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.48
Metal 1 A1 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Poly 2 Polysilicon 0.4 pm 25 1.6
Oxide Silicon 1.15

Dioxide 0.5 pm 43.48
Poly 1 Polysilicon Heater Region: Heater Region:

N/A N/A N/A N/A

Field Silicon 1-15 34_73
Oxide Dioxide 0.4 pm
Stagnant Air N/A N/A
Layer
(Air) 40.16 2,490,075

 

 

 

 

 

 

82

 

Table 14: Physical parameters and thermal properties for thermal modeling of suspended structure with

water as liquid above and air below using Eq. 2-25.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sus ended Structure with Water Above and Air Below
Layer Material Approximate Thermal Heat Transfer Thermal
Name Thickness Conductivity, Coefficient Resistance

k due to Natural R1
(W/m-K°) Convection, h (1y)
(calculated W
using data
from Eq. 2—25)
(W/m2 -K°)

Stagnant Water N/A N/A
Layer
(H20) 9913 10,088
Metal 3 Al, Cr, Au 130
Electrode Combo
Region 0.7 11111 0.389
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.48
Metal 2 A1 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 am 43.48
Metal 1 A1 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Poly 2 Polysilicon 0.4 pm 25 1.6
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Poly 1 Polysilicon Heater Region: Heater Region:

N/A N/A N/A N/A

Field Silicon 1 -15 34.73
Oxide Dioxide 0.4 pm
Stagnant Air N/A N/A
Layer
(Air) 216.8 461,254

 

 

 

 

 

 

83

 

Table 15: Heat transfer results for multiple heater resistor values for suspended structure with water
above and air below.

 

Suspended Structure with Water Above and Air Below

 

 

 

 

 

 

Power 340 Q Resistor 1050 Q Resistor 2600 S2 Resistor
Scenario Estimated Power Estimated Power and Estimated Power and
and Current Level Current Level for 70° Current Level for 70°
for 70° Temperature Temperature Change Temperature Change
Chme
Eq. 2-12 1.93 mW 1.93 mW 1.93 mW
Calculation
using Eq. 2.38 mA 1.356 mA 0.862 mA
2-24
Spice 1.936 mW 1.936 mW 1.936 mW
Thermal
Modeling 2.38 mA 1.356 mA 0.862 mA
using Eq.
2-24
Eq. 2-12 6.97 mW 6.97 mW 6.97 mW
Calculation
Using Eq. 4.53 mA 2.58 mA 1.64 mA
2-25
Spice 7.07 mW 7.07 mW 7.07 mW
Thermal
Modeling 4.56 mA 2.59 mA 1.65 mA
using Eq.
2-25

 

 

 

 

84

 

Table 16: Physical parameters and thermal properties for thermal modeling of structure with water as
liquid above and no thermal isolation below using [27].

 

Heater Structure with Water Above and No Isolation Below

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer Material Approximate Thermal Heat Transfer Thermal
Name Thickness Conductivity, Coefficient Resistance
k due to Natural R1
(W/m-K°) Convection, h (1y )
(calculated W
using
Eq. 2-24)
(W/m2 -K°)

Stagnant Water N/ A N/A
Layer
(H20) 2773.76 36,015
Metal 3 Al, Cr, Au 180
Electrode Combo
Region 0.7 pm 0.389
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.48
Metal 2 Al 0.7pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 gm 43.48
Metal 1 A1 0.7 pm 180 0.389
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.46
Poly 2 Polysilicon 0.41m 25 1.6
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Poly 1 Polysilicon Heater Region: Heater Region:

N/A N/A N/A N/A

Field Silicon 1-15 34.73
Oxide Dioxide 0.4 pm
Silicon Silicon
Substrate 500 1.1m 148 337.8

 

 

 

 

 

 

85

 

Table 17: Physical parameters and thermal properties for thermal modeling of structure with water as
liquid above and no thermal isolation below using Eq. 2-25.

 

Heater Structure with Water Above and No Isolation Below

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer Material Approximate Thermal Heat Transfer Thermal
Name Thickness Conductivity, Coefficient Resistance
k due to Natural RT
(W/m'Ko) Convection, h (1y)
(calculated W
using data
from Eq. 2-25)
(W/m2 -K°)

Stagnant Water N/A N/A
Layer
(H 20) 9913 10,066
Metal 3 Al, Cr, Au 130
Electrode Combo
Region 0.7 mm 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Metal 2 Al 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.46
Metal 1 Al 0.7 pm 180 0.389
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.48
Poly 2 Polysilicon 0.4 pm 25 1.6
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Poly 1 Polysilicon Heater Region: Heater Region:

N/A N/A N/A N/A

Field Silicon 1-15 34_73
Oxide Dioxide 0.4 pm
Silicon Silicon
Substrate 500 pm 148 337.8

 

 

 

 

 

 

86

 

Table 18: Heat transfer results for multiple heater resistor values for structure with water above and no
thermal isolation below.

 

Heater Structure with Water Above and No Isolation Below

 

 

 

 

Power 340 Q Resistor 1050 Q Resistor 2600 Q Resistor
Scenario Estimated Power Estimated Power and Estimated Power and
and Current Level Current Level for 70° Current Level for 70°
for 70° Temperature Temperature Change Temperature Change
Change
Power 209.8 mW 209.8 mW 209.8 mW
Calculation
for Spice 24.80 mA 14.13 mA 8.98 mA
Thermal
Modeling
using Eq.
2-24
Power 232.8 mW 232.8 mW 232.8 mW
Calculation
for Spice 26.2 mA 14.89 mA 9.46 Ma
Thermal
Modeling
using Eq.
2-25

 

 

 

 

87

 

Table 19: Physical parameters and thermal properties for thermal modeling of structure with air as liquid
above and no thermal isolation below using [27].

 

Heater Structure with Air Above and No Isolation Below

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer Material Approximate Thermal Heat Transfer Thermal
Name Thickness Conductivity, Coefficient Resistance
k due to Natural R7
(W/m'Ko) Convection, h (1y)
(calculated W
using
Eq. 2-24)
(W/m2.1<°)

Stagnant Water N/A N/A
Layer
(”20) 40.16 2,490,075
Metal 3 Al, Cr, Au 180
Electrode Combo
Region 0.7 pm 0.389
Oxide Silicon 1 -15

Dioxide 0.5 pm 43.46
Metal 2 A1 0.7 pm 180 0.389
Oxide Silicon 1 -15

Dioxide 0.5 gm 43.48
Metal 1 A1 0.7 pm 180 0.389
Oxide Silicon 1-15

Dioxide 0.5 am 43.48
Poly 2 Polysilicon 0.4 pm 25 1.6
Oxide Silicon 1 ~15

Dioxide 0.5 pm 43.48
Poly 1 Polysilicon Heater Region: Heater Region:

N/A N/A N/A N/A

Field Silicon 1-15 34.78
Oxide Dioxide 0.4 pm
Silicon Silicon
Substrate 500 pm 148 337.8

 

 

 

 

 

 

88

 

Table 20: Physical parameters and thermal properties for thermal modeling of structure with air as liquid
above and no thermal isolation below using Eq. 2-25.

 

Heater Structure with Air Above and No Isolation Below

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer Material Approximate Thermal Heat Transfer Thermal
Name Thickness Conductivity, Coefficient Resistance
Ir due to Natural R1
(W/m'K°) Convection, h (1y)
(calculated W
using data
from Eq. 2-25)
(W/m2 ~K°)

Stagnant Water N/A N/A
Layer
(H20) 216.6 461,157
Metal 3 Al, Cr, Au 180
Electrode Combo
Region 0.7 pm 0.389
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Metal 2 A1 0.7 pm 180 0.369
Oxide Silicon 1-15

Dioxide 0.5 pm 43.48
Metal 1 A1 0.7 pm 180 0.389
Oxide Silicon 1-1 5

Dioxide 0.5 pm 43.48
Poly 2 Polysilicon 0.4 pm 25 1.6
Oxide Silicon 1 -15

Dioxide 0.5 11"! 43.48
Poly 1 Polysilicon Heater Region: Heater Region:

N/A N/A N/A N/A

Field Silicon 1-15 34.78
Oxide Dioxide 0.4 pm
Silicon Silicon
Substrate 500 pm 148 337.8

 

 

 

 

 

 

89

 

Table 21: Heat transfer results for multiple heater resistor values for structure with air above and no
thermal isolation below.

 

Heater Structure with Air Above and No Isolation Below

 

 

 

 

Power 340 Q Resistor 1050 Q Resistor 2600 Q Resistor
Scenario Estimated Power Estimated Power and Estimated Power and
and Current Level Current Level for 70° Current Level for 70°
for 700 Temperature Temperature Change Temperature Change
Change
Power 200 mW 200 mW 200 mW
Calculation
for Spice 24.3 mA 13.8 mA 8.77 mA
Thermal
Modeling
using Eq.
2-24
Power 200.6 mW 200.6 mW 200.6 mW
Calculation
for Spice 24.3 mA 13.82 mA 8.78 mA
Thermal
Modeling
using Eq.
2-25

 

 

 

 

90

 

[1]

[2]

[3]

[4]

[6]

[8]

[91

[10]

BIBLIOGRAPHY

J. J. Ho, Y. K. Fang, W. J. Lee, F. Y. Chen, W. T. Hsieh, S. F. Ting, M. S. Ju, S.
B. Huang, K H. Wu, and C. Y. Chen, "The dynamic response analysis of a
pyroelectric thin-film infrared sensor with thermal isolation improvement
structure," Ieee Transactions on Electron Devices, vol. 46, pp. 2289-2294, 1999.

G. S. Chung, "The fabrication of micro-heaters with low-power consumption
using $01 and trench structures," Metals and Materials International, vol. 8, pp.
347-351, 2002.

H. Ji-song, T. Kadowaki, K. Sato, and M. Shikida, "Fabrication of thermal-
isolation structure for microheater elements applicable to fingerprint sensors,"
Sensors and Actuators A: Physical, vol. 100, pp. 114-122, 2002.

E. H. Klaassen, R. J. Reay, C. Storrnent, and G. T. A. Kovacs, "Micromachined
thermally isolated circuits," Sensors and Actuators A.“ Physical, vol. 58, pp. 43-
50, 1997.

V. Lysenko, S. Perichon, B. Remaki, and D. Barbier, "Thermal isolation in
microsystems with porous silicon," Sensors and Actuators A: Physical, vol. 99,
pp. 13-24, 2002.

R. J. Reay, E. H. Klaassen, and G. T. A. Kovacs, "Thermally and electrically
isolated single crystal silicon structures in CMOS technology," Electron Device
Letters, IEEE, vol. 15, pp. 399-401, 1994.

B. W. van Oudheusden and A. W. van Herwaarden, "High-sensivity 2-D flow
sensor with an etched thermal isolation structure," Sensors and Actuators A:
Physical, vol. 22, pp. 425-430, 1989.

W. L. Benard, H. Kahn, A. H. Heuer, and M. A. Huff, "Thin-film shape-memory
alloy actuated micropumps," Journal of Microelectromechanical Systems, vol. 7,
pp. 245-251, 1998.

J. Chen and K. D. Wise, "A high-resolution silicon monolithic nozzle array for
inkjet printing," Electron Devices, IEEE Transactions on, vol. 44, pp. 1401-1409,
1997.

D. Davazoglou and T. Dritsas, "Fabrication and calibration of a gas sensor based
on chemically vapor deposited WO3 films on silicon substrates: Application to
H2 sensing," Sensors and Actuators B: Chemical, vol. 77, pp. 359-362, 2001.

91

[11]

[12]

[13]

[14]

[15]

[16]

[17]

[18]

[19]

[20]

[21]

[22]

J. J. Ho, Y. K. Fang, W. J. Lee, F. Y. Chen, W. T. Hsieh, S. F. Ting, K. H. Lee,
M. C. Hsieh, C. P. Chang, and K. H. Wu, "Analysis of substrate effects on the

response of pyroelectric thin-film infrared sensors," Microscale T hermophysical
Engineering, vol. 3, pp. 263-272, 1999.

G. Kaltsas, A. A. Nassiopoulos, and A. G. Nassiopoulou, "Characterization of a
silicon thermal gas-flow sensor with porous silicon thermal isolation," Sensors
Journal, IEEE, vol. 2, pp. 463-475, 2002.

A. M. Madni and L. A. Wan, "Microelectromechanical systems (MEMS): an
overview of current state-of-the-art," Aerospace Conference, 1998. Proceedings,
IEEE, vol. 1, pp. 421-427, 1998.

R. Nayve, M. F ujii, A. Fukugawa, and M. Murata, "High resolution long array
thermal ink jet printhead fabricated by anisotropic wet etching and deep Si RIE,"
presented at Micro Electro Mechanical Systems, 2003. MEMS-03 Kyoto. IEEE
The Sixteenth Annual International Conference on, 2003.

Y. Wang, Z. H. Li, D. T. McCormick, and N. C. Tien, "A micromachined RF
microrelay with electrotherrnal actuation," Sensors and Actuators a-Physical, vol.
103, pp. 231-236, 2003.

S. Y. Wu, Q. Lin, Y. Yuen, and Y. C. Tai, "MEMS flow sensors for nano-fluidic
applications," Sensors and Actuators a-Physical, vol. 89, pp. 152-158, 2001.

S. A. Campbell, The Science and Engineering of Microelectronic Fabrication,
2nd ed. New York: Oxford University Press, 2001.

W. A. Kern and C. A. Deckert, "Chemical Etching," in Thin Film Processing, J.
L. Vossen, Ed. New York: Academic, 1978.

K. McAndrews and P. C. Subanek, "Nonuniform Wet Etching of Silicon
Dioxide," Journal of the Electrochemical Society, vol. 138, 1991 .

K. Sato, M. Shikida, Y. Matsushima, T. Yamashiro, K. Asaumi, Y. Iriye, and M.
Yamamoto, "Characterization of anisotropic etching properties of single-crystal
silicon: effects of KOH concentration on etching profiles," presented at Tenth
Annual International Workshop on Micro Electro Mechanical Systems, 1997,
Nagoya, Japan, 1997.

M. Elwenspoek, U. Lindberg, H. Kok, and L. Smith, "Wet chemical etching
mechanism of silicon," presented at IEEE Workshop on Micro Electro
Mechanical Systems, 1994, Oiso, 1994.

G. T. A. Kovacs, N. I. Maluf, and K. E. Petersen, "Bulk rnicromachining of
silicon," Proceedings of the IEEE, vol. 86, pp. 1536-1551, 1998.

92

[23] O. Tabata, "Anisotropy and selectivity control of TMAH," presented at Micro
Electro Mechanical Systems, 1998. MEMS 98. Proceedings, The Eleventh
Annual International Workshop on, 1998.

[24] K. Tokoro, D. Uchikawa, M. Shikida, and K. Sato, "Anisotropic etching
properties of silicon in KOH and TMAH solutions," presented at International
Symposium on Micromechatronics and Human Science, 1998. MHS '98.,
Nagoya, Japan, 1998.

[25] M. Shikida, K. Sato, K. Tokoro, and D. Uchikawa, "Comparison of anisotropic
etching properties between KOH and TMAH solutions," presented at Micro
Electro Mechanical Systems, 1999. MEMS '99. Twelfth IEEE International
Conference on, 1999.

[26] W. Sonphao and S. Chaisirikul, "Silicon anisotropic etching of TMAH solution,"
presented at IEEE International Symposium on Industrial Electronics, 2001 ,
Pusan, 2001.

[27] D. Pitts and L. Sissom, Heat Transfer, Second ed. New York: McGraw-Hill,
1997.

[28] S. D. Senturia, Microsystem Design. New York: Kluwer Academic Publishers,
2001.

[29] W. McCabe, J. Smith, and P. Harriott, Unit Operations of Chemical Engineering.
New York: McGraw-Hill, 2001.

[30] "The MOSIS Service Web Site," www.mosisorg.

 

[31] T. Deng, J. Tien, B. Xu, and G. M. Whitesides, "Using Patterns in Microfiche as
Photomasks in 10-um-Sca1e Microfabrication," Langmuir, vol. 15, pp. 6575-6581,
1999.

[32] T. Deng, H. Wu, S. T. Brittain, and G. M. Whitesides, "Prototyping of Masks,
Masters, and Stamps/Molds for Soft Lithography Using an Office Printer and
Photographic Reduction," Analytical Chemistry, vol. 72, pp. 3176-3180, 2000.

[33] "MicroGRAPHICS Plus, Inc.." 3016 W Bluewater Hwy, Ionia, MI 48846, (800)
682-7893.

[34] H. Lakdawala, "Temperature Control of CMOS Micromachined Sensors," in

Electrical and Computer Engineering: Carnegie Mellon University, 2002, pp.
206.

93

 

 

[35]

[36]

[37]

[381

M. Ehmann, P. Ruther, M. von Arx, H. Baltes, and 0. Paul, "Ageing behavior of
polysilicon heaters for CMOS microstructures operated at temperatures up to
1200 K," presented at Micro Electro Mechanical Systems, 2001. MEMS 2001.
The 14th IEEE International Conference on, 2001.

M. Gaitan, J. Suehle, J. R. Kinard, and D. X. Huang, "Multijunction thermal
converters by commerical CMOS fabrication," presented at IEEE Instrumentation
and Measurement Technology Conference, Irvine, CA, 1993.

U. Kang and K. D. Wise, "A high-speed capacitive humidity sensor with on-chip
thermal reset," Electron Devices, IEEE Transactions on, vol. 47, pp. 702-710,
2000.

S.-W. Lee, H.-C. Kim, K. Kuk, and Y.-S. Oh, "A monolithic inkjet print head:

DomeJet," presented at Micro Electro Mechanical Systems, 2001. MEMS 2001.
The 14th IEEE International Conference on, 2001.

94

 

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