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This is to certify that the
thesis entitled

Digital Phase Detection in a Variable Frequency RF System

presented by

Adam Molzahn

niversity

LIBRARY
gan State

Michi
U

has been accepted towards fulfillment
of the requirements for the

MS. degree in Electrical Engineering

 

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MSU is an Affirmative Action/Equal Opportunity Institution

PLACE IN RETURN BOX to remove this checkout from your record.
To AVOID FINES return on or before date due.
MAY BE RECALLED with earlier due date if requested.

 

DATE DUE

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2/05 c:/CIRC/DateDue.inddop.15

 

Digital Phase Detection
In a Variable Frequency RF System

By

Adam Molzahn

A THESIS
Submitted to
Michigan State University

in partial fulfillment of the requirements
for the degree of

MASTER OF SCIENCE
Department of Electrical and Computer Engineering

December 2005

ABSTRACT

Digital Phase Detection
In a Variable Frequency RF System

By

Adam Molzahn

In cyclotron control systems, accurate phase and amplitude information derived from
the radio frequency voltages applied to the accelerating electrodes (dees) is crucial to the
successful operation of the accelerator. A small tolerance of :l:0.1% in amplitude jitter
and :l:0.05° in phase jitter of the sinusoidal radio frequency drive signal is required for the
measurements. This thesis focuses on the design and implementation of an FPGA-based
phase meter module with a discussion regarding further additions to convert the module to
a fully functional phase and amplitude control system.

The sinusoidal analog voltages from each cyclotron dee are brought in and mixed up
to SOMHz with a local oscillator frequency from a high quality frequency synthesizer. The
SOMHz waveform is sampled using high speed analog to digital converters (ADC) and
the resulting digital samples are fed into a field programmable gate array (FPGA). Using
inphase and quadrature (I and Q) vector data gathered from the digital waveform, the phase
and amplitude are calculated and compared to a reference signal.

The phase information from each module is used in the existing cyclotron control sys-
tem to replace the obsolete analog vector voltmeters and provide a display for each dee

station.

This thesis could not have happened without the love
and support of Destinee and Ashton, who have helped

keep me sane through all of life’s twists and turns.

iii

ACKNOWLEDGNIENTS

Many people helped me get where I am today. I’d like to thank John Vincent, first
and foremost, for his unending support and cynicism which drove me to try and meet and
exceed his expectations. Thanks for holding me to a higher standard. I would also like to
thank Dale Smith for giving me the opportunity to learn from some of the best technicians
and engineers in the accelerator field. For board layout and design problems, I have to
thank Brian Drewyor for teaching me the ropes. I would not have made any progress on
the research for this project had it not been for the discussions I had with Michael O’Farrell,
he was a great sounding board with lots of excellent feedback. Without the help of Mark
Davis the programming side of this project would have been a bear. And Larry Doolittle,
whose work was the seed that started this project, deserves kudos for putting up with my
relentless questions. Finally, I’d like to thank Leo Kempel for getting me here and being
undyingly optimistic.

On a special note, I’d like to thank my wife Destinee and my son Ashton. They have
helped me more than they could possibly know. You are my motivation.

Thank you.

iv

ABSTRACT ....................................... ii
ACKNOWLEDGMENTS ................................ iv
LIST OF TABLES ................................... vii
LIST OF FIGURES ................................... viii
1 Introduction ..................................... l
2 Module Input and Mixing .............................. 7
2.1 Description of the Input Stage ........................ 7
2.2 Mixer Theory ................................. 8
2.3 Mixing and Harmonic Interference ...................... 9
2.4 Evaluating the Effects of Harmonic Interference ............... 11
3 Conditioning the Input Channels ..... ‘ ..................... 18
3.1 Dealing with Variable Input Levels ...................... 18
3.2 Noise and Interference Considerations .................... 20
3.3 Interference Analysis ............................. 21
4 Phase Lock Loop ................................... 24
4.1 General Operation ............................... 24
4.2 Modulating the VCXO ............................ 25
4.3 Creating the Clock Signals .......................... 26 .
5 Signal Digitization .................................. 28
5.1 Nyquist Zones ................................. 28
5.2 Vector Data Using N yquist Zone Manipulation ............... 30
5.3 ADC Implementation ............................. 32
5.4 Signal Preparation ............................... 34
5.5 High Speed DAC Output ........................... 35
6 The Field Programmable Gate Array ........................ 37
6.1 FPGA Connections .............................. 37
6.2 Collecting I/Q Vector Data .......................... 38
6.3 Conditioning the Inputs ............................ 39
6.4 Creating the DAC Output ........................... 40
6.5 Buffering the Inputs .............................. 40
6.6 Data Bus Transfers .............................. 41
6.7 Conclusion .................................. 43

TABLE OF CONTENTS

7 The Microcomputer ................................. 44

7.1 The ZWorld Microcomputer ......................... 44

7.2 Interacting with the ZWorld .......................... 45
7.2.1 The User Interface .......................... 45

7.2.2 Serial Programming ......................... 46

7.2.3 User Commands ........................... 46

8 Signals and Interlocks ................................ 51
8.1 External Signals and Status Indicators .................... 51

8.2 Housekeeping Circuits ............................ 52

9 Phase Meter Performance .............................. 55
9.1 Determining Module Channel Offsets .................... 55

9.2 Determining Phase Accuarcy ......................... 58

9.3 Calculation Accuracy Dependence on Amplitude .............. 59

9.4 Performance Analysis ............................. 61

A FPGA Code in Verilog ................................ 66
B ZWorld C-Code ................................... 79
C Digital I/O usage for the ZWorld .......................... 93
D Phase Meter Schematics ............................... 95
BIBLIOGRAPHY .................................... 107

vi

2.1

2.2

3.1

6.1
6.2
6.3

7.1
7.2
7.3

8.1

9.1
9.2

CI

LIST OF TABLES

Harmonic Mixing for RF=9MHz, IF=50MHz, L0’=IF+RF=59MHz,

L0+=IF-RF=41MHz .............................. 10
Harmonic Mixing for RF=33MHz, IF=50MHz, LO‘ =IF+RF=83MHz,

L0+=IF-RF=17MHz .............................. 15
Digital Attenuator Control Bits. ....................... 19
HQ Determination. .............................. 38
FPGA Commands. .............................. 42
ADC Mode Select. .............................. 42
Telnet Interface Description. ......................... 46
ZWorld Telnet Command List. ........................ 47
Telnet Interface Description. ......................... 47
DAC Binary Output Chart. .......................... 54
Phase Meter Specifications .......................... 63
Channel to Channel Cross-Talk ........................ 64
Telnet Interface Description. ......................... 94

vii

LIST OF FIGURES

1.1 System Overview. .............................. 2
2.1 PI Attenuator. ................................. 8
2.2 Bessel Bandpass Filter Response. ................ ‘ ...... 15
3.1 Channel 1 FFI‘ Plots at 9MHz(a), 18MHz(b) and 27MHz(c) at the input to

tile: 1%J[)(ZI ................................... 222!
3.2 Channel 2 FFI‘ Plots at 9MHz(a), 18MHz(b) and 27MHz(c) at the input to

thus I\J[)(3 ................................... 2222
3.3 Channel 3 FFI‘ Plots at 9MHz(a), 18MHz(b) and 27MHz(c) at the input to

tilt: [ALIJKCI ................................... 2223
4.1 Power Supply for PECL Compatibility ................... 26
5.1 Undersampling 50MHz using f}=40MSPS .................. 33
5.2 RF Transformer Section ............................ 34
5.3 The figure on the right (b) shows the DAC I/Q square wave output and the

figure on the left (a) is the FFT of the square wave ............. 35
6.1 Handshaking Timing ............................. 41
7.1 Telnet Interface ................................ 45
8.1 Bipolar DAC Configuration ......................... 54
9.1 Test Setup 1 .................................. 56
9.2 Measured Channel-to-Channel Offset .................... 57
9.3 Test Setup 2 .................................. 58
9.4 Module Phase Accuracy ........................... 59
9.5 Phase Accuracy Amplitude Dependence ................... 61
9.6 Calculated Amplitude Accuracy ....................... 62
DJ System Overview ............................... 96
DZ Mixer Stage .................................. 97
D3 Signal Conditioning (CH 1 and LO) ..................... 98
DA Analog to Digital Converters (CH 1) ..................... 99
D5 Phase Lock Loop ............................... 100
D6 Xilinx XC28150 FPGA ........................... 101
D7 ZWorld Microcomputer ........................... 102
D8 Interlocks ................................... 103
D9 DAC Output ................................. 104
D.10 Housekeeping Circuitry ........................... 105

viii

CHAPTER 1

Introduction

The successful operation of the superconducting cyclotrons at Michigan State University
depends heavily on the ability of the RF controls system to precisely regulate the volt-
age applied to the accelerating electrodes (dees, beam buncher, etc). For acceleration, the
cyclotron employs three electrodes, called dees, which are nominally 120° out of phase
with each other. High accuracy phase measurements are necessary to allow the cyclotron
operators to precisely set the phase between the dees to tune the beam[1].

The purpose of this thesis project is to develop a digital phase meter to accurately read
the phase between the three dees and the beam buncher on the K500 and K1200 cyclotrons.
This thesis presents a detailed discussion of the theory, hardware and software desired to
create a high quality phase meter.

In the cyclotron control system’s current incarnation, one station is set up to regulate
each of the three dees in the cyclotron and one station is set up to regulate the beam buncher.
Three external phase meters read the phase of the RF between the A and B stations, the A
and C stations and the A station and the beam buncher on each cyclotron[2]. This module
is meant to replace those three obsolete analog phase meters with a digital module that will
read each phase andreport the readings back to the control system. Beyond this project,

additional technologies have been added to facilitate replacing the multiple existing analog

 

   

  
   
   
   
 
 

Reference

Distribution
Cavity

0 Omar

Control
Host

    

     
 

Controller

Test Prints

    
   

Ethernet Fast Tuner

C ontrol

Slow Tuner
Interface ‘

 

 

 

Figure 1.1. System Overview.

tuning and regulation modules with one digital system per dee that monitors, tunes and
regulates all within a single module. Figure 1.1 shows an overview of the entire control
system. This thesis will detail the components contained within the dotted lines labeled
Controller.

Construction of a phase meter requires seven main stages: (1) a fixed attenuator to deal
with the high maximum voltages of the low level radio frequency (LLRF) signals from the
cyclotron, (2) a mixer stage where the RF signals are mixed from their variable frequencies
to an intermediate frequency, (3) a variable digital attenuation stage to handle the wide
range of LLRF signal levels, (4) a fixed amplification stage to condition the signal to the full

scale of the analog to digital converters (ADCs), (5) an ADC stage to sample and digitize

the waveforms, (6) a field programmable gate array (FPGA) stage to process the raw data,
and (7) a microprocessor stage to deal with communications, calibration and controls. The
remaining components are intended to extend the functionality of the module beyond a
simple phase meter and will be discussed but not fully utilized in the final implementation.
For a complete schematic overview see Appendix D, Figure D. 1.

Five RF inputs are included on the front of the module. One is for the reference, which
is used to control the phase lock loop and synchronize the clocks that control the FPGA and
ADC sample timing. The reference can be any frequency, fr: f, as long as it can be related

to the ADC sampling frequency, fs, according to the following formula,

N
fref=§*fr (1.1)

where N and R are both integers[3]. The reference signal is digitized; therefore it is bene-
ficial to make

fref:% (1'2)

to generate the correct type of vector data[4], which will be discussed later. Three of the
other inputs are the RF signals from which phase information is to be extracted. In the
cyclotron, these signals range from 9MHz to 27MHz with voltage levels from -7dBm up
to +33dBm. This module is designed to handle all of these signals without modification.
However, by changing the mixers, some filters and the fixed input attenuators, it can be
extended to work in virtually any system. The final input is a local oscillator (LO) signal
that is used in conjunction with the mixers to shift the frequency of the RF signals whose

phases are desired to a common intermediate frequency (IF).

The front panel also includes a high speed DAC output that is for use as the RF control
signal once that capability has been added to the module. An RF On/Off input and a reset
input are included as interlock signals from the control system. A fault signal output and
a fast tuner signal output make up the last two connections on the front panel. The back
panel connections include an Ethernet plug, a miscellaneous connector and a NIM crate
power connector. A CPU reset button on the back panel is connected to the microprocessor
to allow the module to be reset manually. LEDs are included to indicate CPU activity,
RF status and module readiness are included to give quick feedback as to the state of the
module.

The maximum RF voltages presented to the input of the module are too high for the
mixers to handle without being overdriven. Therefore, a fixed high power attenuator using
standard surface mount resistors is designed to match the maximum RF voltage to the
maximum input voltage of the mixers. This makes the attenuator reconfigurable for any
system specifications while easily handing the power requirements

In the mixer stage, three mixers are used to mix the LO with the three RF inputs to create
the IF, which is sampled and manipulated digitally. A high quality frequency synthesizer
phase locked to the reference signal creates the LO frequency. For this system, the 10MHz
phase reference on the back of the signal generator is the module reference and is already
locked to the LO.

Due to the frequency dependence and operating requirements of the cyclotron, the volt-
age levels at the output of the mixers are not constant. Therefore, after mixing, the signals
enter the digital attenuation stage to condition them for amplification. Variable digital at-

tenuators are controlled by a 6-bit word from the FPGA.

The signals pass through a fixed amplification stage to condition them to be sampled
by the ADCs. A chain of RF amplifiers and attenuators condition the signal levels to match
them to the input requirements of the ADCs. It is imperative they are matched as closely
as possible to full-scale to utilize all of the precision of the ADCs without overdriving the
inputs. Low amplitudes result in a loss of sensitivity and accuracy with regard to changes
in the signal while overdriving the inputs distorts the waves and corrupts the vector data
being taken.

The ADC stage digitizes the signals in such a way that the samples taken can be con-
sidered the in-phase (I) and quadrature (Q) values of the vector representing the RF input
signal [5, 6, 7]. I and Q map to the polar coordinate system as the real and imaginary axes,
respectively, and can be used to directly calculate the phase and magnitude of the sampled
signal.

The digitized signals are read by the FPGA in real time. A history buffer keeps track
of past inputs and outputs and is used for filtering and storing samples as I and Q data.
This data is sent to the microprocessor to determine the phase between the RF inputs. The
FPGA also takes care of interlocks, digital to analog converter output and various other
housekeeping tasks that will be detailed later.

The microprocessor is the heart of the system, manipulating the data and handling com-
munication. The bus controller allows data to be shared asynchronously with the FPGA so
that phase and magnitude can be calculated and other components on the PC board can be
configured. Various user interface panels display board parameters and chip settings over a
telnet connection hosted here as well. Configuration data is either generated or loaded by

the microprocessor and sent via the serial programming interface to set up the rest of the

supplemental chips.

The software used to do the work detailed in this thesis includes Xilinx Integrated
Software Environment 7.1i for Verilog code development and compilation, Protel DXP
8.3 SP 3 for schematic capture and printed circuit board layout and design, AutoCAD 2005
for layouts and designs, Chipscope Pro 6.3i for FPGA verification, MATLAB R14 for
graphing and numerical manipulation, N MAKE 6.00 for C—code compliation and Dynamic
C 8.61 for ZWorld C-code development.

Test equipment included a Rhode and Schwarz 3.3GHz signal generator, 2 PTS 250
frequency synthesizers, a Hewlett Packard 8508A vector voltmeter and a Hewlett Packard

E4402B spectrum analyzer.

CHAPTER 2

Module Input and Mixing

2.1 Description of the Input Stage

This phase meter must be able to accept a wide number of input frequencies and voltage
levels. Specifically designing for the cyclotron, a front end was developed that could ac-
cept frequencies from 9 to 27MHz at amplitudes varying from lOOmVRMS (—7dBm) up
to lOVRMS (+33dBm), but also be configurable to other ranges[l, 7]. This was accom-
plished using an attenuator and mixer stage at the input of each RF channel of the module
(Appendix D, Figure D2). The mixer is used to convert the radio frequency (RF) input
signal to a common intermediate frequency (IF). The maximum signal level that can be
handled on the RF port of the mixer is +ldBm. Therefore, a fixed high power attenuator
is necessary to match the maximum input voltage to that of the mixer. Mth a maximum
of +33dBm coming into the module, ~32dB of attenuation is required. A —29dB PI style
attenuator (Figure 2.1) for a 509 system can be easily constructed using values for R1,R2

and R3 based on the following equations:

R1=R2 = % 1 253.59 (2.1)
10 +1 __1_

50:1in —1 R3

 

Figure 2.1. PI Attenuator.

R3=1*(10i€—1) Mama (2.2)
2 10m

where dB is the amount of attenuation required for the attenuator[8]. This style attenuator
allows for easy modification and can be designed to handle the large amount of power
dissipated by using a high power resistor for R1. The attenuator reduces the maximum
level down to +4dBrn and a standard low power 3dB RF attenuator can be used to match to

the desired +1dBm.

2.2 Mixer Theory

In an ideal mixer, the RF input signal is multiplied by a local oscillator (LO) signal to create
a new signal with sidebands equal to the sum and difference of the RF and LO frequencies

[9, 10]. Specifically,

 

 

RF =A1sin(w1t+01) (2.3)
L0 = Azsin((o2t + 92) (2.4)
A A A A
RFakLO = ‘2 'cos((co1+m2):+91+ez)— ‘2 lCOS((01—(Dz)t+91-92) (2.5)

RF * L0 = sum — difference (2.6)

The phase of the RF signal, 01, is preserved and offset by +02 and -02 even though the
frequency has changed. Hence, there is a one to one correspondence between the phase
of the new signal and the phase of the old signal. The resultant waveform is filtered to
select the desired sideband (IF). The recommended input signal level for the LO port on
the mixer is +7dBm (0.5VRMS). With three input channel mixers and one output channel
mixer, the signal generator connected to the LO port on the module must supply +19dBm
(2.0VRMS). Standard signal generators cannot supply this much voltage, so a single stage
amplifier and attenuator chain is employed. The gali-Sl RF amplifiers used in this design
have a ldB compression point of +18.3dBm and a gain of +18dB. For this reason, the
required input level to the module is reduced to +8dBm and is immediately attenuated by
-9dB to -1dBm. The signal is then amplified. up to +17dBm and distributed to the four
mixers using a matched resistive voltage divider circuit. +17dBm is within the range of
linear operation for the gali-S 1 amplifiers and supplies enough current to drive the mixers
correctly by delivering +5dBm (0.4VRMS) at each mixer LO input. It is important that the
signal path lengths for each LO trace are equalized on the PCB for each of the mixers on
the RF input channels to make 02 the same. By ensuring that 92 is equal for each of the RF
inputs, the resultant multiplication of sine waves produces three signals that are all offset

by the same value. In this manner, the channel-to-channel phase is independent of the 02’s.

2.3 Mixing and Harmonic Interference

Harmonic frequencies on the RF input can adversely affect the mixing process and the sub-

sequent filtering. Assume the input signal contains harmonic frequencies (OJRF, 2 at (03p,

Table 2.1. Harmonic Mixing for RF=9MHz, IF=50MHz, L0‘=IF+RF=59MHz, L0+=IF-
RF=41MI-Iz.

 

 

 

 

 

 

 

Harmonic Freq. L0“ + h * RF LO" — h a: RF LOJr + h * RF L0+ -— h a: RF
9 68 50 50 32
18 77 41 59 23
27 86 32 68 14
36 95 23 77 5
45 104 14 86 4
54 113 5 95 13
63 122 4 104 22

 

 

 

 

 

 

 

 

3 * (03p, 4 * to”, ...h >1: to”) and that the LO contains only the fundamental frequency with—
out harmonics. Any harmonic frequency that may mix back near the [F will be hard to filter
out and will distort the phase. In the interest of finding the highest and lowest harmonic
frequencies that might be a problem for this system in the cyclotron, it is advantageous to
look at the low end of the cyclotron frequency scale which will have the closest spaced har-
monics and will be the hardest to filter. Using a 9MHz RF and analyzing both the RF+LO
and RF-LO frequencies table 2.1 can be generated. No matter the input frequency, the
lowest harmonic that could potentially create a filtering problem is at a higher frequency
for IF=LO-RF than for IF=LO+RF. Note that negative frequencies simply fold back into
the positive realm with a 180° phase shift. A simple analysis of the frequencies created
during mixing shows that certain RF harmonics can have sums or differences that will fold
directly onto the IF frequency corrupting the true signal and causing phase error. Assume a
signal enters the module containing the RF and the 2"" harmonic of the RF. The harmonic
mixes with the LO onto the IF and is then ideally filtered so that only the IF passes giving
a signal of the form,

IF = Alej(wlrt+¢i) +Azej(mll’t+¢2) (2_7)

10

with (1)1 the desired phase of the signal and $2 the phase due to the unwanted harmonic

frequency. Manipulating this equation to determine the phase and amplitude of the IF gives
IF = e19!“ (A1 cos(¢, ) +A2 00501») + j(A1 sin(¢1)+A2 sin(¢2) (2.8)

Rotating (p1 and ¢2 so that m = 0 and (11,2 = (1)2 — 4)] yields an equation for the phase equal

10

9]F = tan"l(I—m) = tan—l( A281n(¢2) ,
Re A1 +A2 COS(¢2)

 

) (2.9)

2.4 Evaluating the Effects of Harmonic Interference

Evaluating this expression for different values of (11,2 shows that 0": = 0° when ¢'2 = 0° and
01; = tan‘1 (Ag/A1) when ¢I2 = 90°. The argument of the inverse tangent will always be
between 0 and :tAz /A1, therefore 0”: will be between 0 and :l:tan‘1(A2/A1). If ¢'2 does
not vary with time, as is the case with a pure harmonic, then the phase read by the module
will include a static error added in equal to 91;. However if ¢'2 varies with time, it will
show up in the reading as phase noise, varying with time.

Further analysis of the magnitude gives the equation

 

A22 A2 I
M =A — — .
0g”? l\/1+A1 +A1COS(¢2) (210)

If the ratio of the harmonic to the RF is low, the magnitude of the signal is nearly equal
to the magnitude of the fundamental component. Otherwise, the magnitude of the signal

varies based on the phase q); and the ratio of the amplitudes. Once again, if (11,2 is a time

11

varying signal the magnitude will fluctuate. It is important to determine which harmonics
will mix to the IF frequency so they can be prefiltered out before the mixing process.
There are two different ways to select a LO frequency to produce the desired IF. In the first
approach, the LO frequency is chosen so that IF=LO+RF. This will be referred to as the
sum. In the second approach, the LO frequency is chosen so that IF=LO-RF. This will be
referred to as the difference. Let

IF=RF+L0 (2.11)

Assume some harmonic of RF = h*RF can mix with the LO onto the IF where,

IF=h*RF—L0 (2.12)
IF can be rewritten as,
IF=h*RF—IF+RF (2.13)
and certain RF frequencies at,
21F
RF = — 2.14
h + l ( )

will have problematic harmonics at,

 

h*RF = *ZIF (2.15)

h + l
The lowest frequency will be (h=2),

h*RF= gIF (2.16)

12

The highest will be at (h-—+ co).

h*RF=2*IF (2.17)

Using an L0 such that the sum is kept and the difference is filtered out (IF = RF+LO)

certain frequencies image to the IF following the equation,

 

 

2*h
h*RF—h+l*lF (2.18)
which leads to
2*IF
h— RF —1 (2.19)

with h=l equal to the fundamental RF frequency, h=2 equal to the 2"” harmonic, h=3
equal to the 3"! harmonic and so on. The solution for h corresponds to a harmonic image
of the RF that will mix exactly to the IF and cause phase noise or phase error, depending on
its origin. If h is not an integer, then no harmonic image of the RF will mix exactly to the
IF. Using an L0 such that the difference is kept and the sum is filtered out (IF = RF-LO)

yields a center band image frequency of

 

 

h*RF= 2*};*IF (2.20)
which leads to
2*IF
= l O
h RF + (221)

Examining the limits of both equations shows at h=2 the problematic harmonic fre-

quency for the sum is (4/ 3) =1: IF and for the difference is 4 =1: IF. For h = 00 both equations

13

converge on 2 =1: IF. Using a low pass filter to remove any harmonic frequency greater than
or equal to (4/ 3) =1: IF would guarantee that no image of a harmonic would mix back onto
the IF. This filtering is left up to the individual users because of the wide range of input
filters that would be required for the module to work in a broad range of applications.
After mixing, a bandpass filter centered on the IF is required to condition the mixer
output because certain harmonics that may have passed through the initial filtering process
could mix to frequencies both higher and lower than the IF. In an ideal system with a band
pass filter that only allows the center frequency to pass and sufficiently attenuates any other
frequencies, this analysis would be complete, however in a non-ideal system the filter has
some finite bandwidth. For this module, the bandwidth is defined as the frequency band
in which the frequency content is attenuated by less than -20dBc (dB to carrier) as this
would sufficiently reduce any unwanted signals to the point they would no longer cause
significant errors. The pass band sets the minimum frequency for the RF because any
frequency lower than the bandwidth of the filter will produce a signal whose two frequency
components both mix into the pass band and cannot be filtered. It is not sufficient to simply
filter out harmonics greater than or equal to (4/ 3) at [F because some lower frequencies
may mix into the pass band of the post-mixer filter as well. For example, using a SOMHz
IF and a 33MHz RF, the second, third and fourth harmonics of the fundamental are 66MHz,
99MHz and 132MHz (Table 2.2). The filter used to condition the mixer output is a four
pole Bessel bandpass filter with constant phase delay and sharp sidebands (Figure 2.2).
The -3dBc frequencies of the filter are 48.75MI-Iz and 51.25MHz. The ~40dBc frequencies
are 42.01MHz and 59.01MHz. The desired -20dBc attenuation occurs around 44MI-Iz and

56MHz for a bandwidth of about 6MHz. According to Table 2.2, the 66MHz harmonic

l4

 

Table 2.2. Harmonic Mixing for RF=33MHz, IF=50MHz, L0‘=IF+RF=83MHz, L0+ =IF-

 

 

 

 

 

 

 

 

 

 

- l OdB/div

3ONflh:

SOMHZ

 

70NHLZ

Figure 2.2. Bessel Bandpass Filter Response.

15

RF=17MHZ.
Harmonic Freq. L0" + h an: RF LO‘ -— h at RF L0j + h =1: RF L0+ — h =1: RF
33 1 16 50 50 16
66 149 17 83 49
99 182 16 l 16 82
132 215 49 149 115
OdBc

 

will mix with the sum LO of 17MHz to create 49MHz and 83MHz. If that harmonic is not
filtered out before mixing, the 49MHz signal will pass through the filter and be digitized
along with the desired 50MHz signal causing phase noise to show up in the reading. The
same type of problem arises from choosing the difference LO of 83MHz, however the
frequency of the harmonic increases to 132MHz. Adding in the bandwidth of the filter,
Few. changes the equations for the harmonic frequencies that will mix into the pass band

to

h
h RF=—2]F:tF .2
* h+l( BW) (22)

for the sum L0 and to

h
h*RF = h—T(21F:tF3w) (2.23)

for the difference L0. The lower limit of the sum equation moves to

41F -— F
__7-_Brz (2,24)
3
and the upper limit moves to
21F + FBW (2.25)
The lower limit of the difference equation move to
21F — Fgw (2.26)
and the upper limit moves to
41F + FBW (2.27)

16

The higher minimum problematic harmonic makes it easier to filter the inputbefore mixing
when using the difference LO frequency because there is more separation between the RF
and the frequencies that need to be filtered out. For instance, for the cyclotron running at
between 9MHz and 27MHz, using a SOMHz IF and a LG such that IF=LO-RF, a low pass
filter on the input would be require -20dB of attenuation at 94MHz to catch any harmonics
that might mix into the passband. This same filter would not work for a system used in the
Rare Isotope Accelerator (RIA) where the RF runs at 805MI-Iz[7]. Therefore, the filtering
is left up to the user so a suitable filter can be used without limiting the application of the
module.

Tire mixing process is one of the most crucial steps in designing a phase meter module
because the ability to design for one IF given a number of RF inputs makes the system much
less complicated and more versatile. However, care must be taken in the preparation of the
signals because, as has been shown, any inputs that are not sufficiently clear of harmonics

and other types of noise can adversely affect the module measurements.

17

CHAPTER 3

Conditioning the Input Channels

Once the RF input signals have been mixed and conditioned to a common IF frequency,
the signal must be matched to the input levels required by the analog to digital converters
(ADCs). The closer to full scale these signals are the more accurate the digitization and
subsequent measurement. For an input voltage range of +33dBm to -7dBm the output of
the mixer stage should be between - ldBm and ~41dBm. In order to condition this variable
signal to a constant full-scale ADC input signal, a digital attenuator is placed in series with

a fixed chain of amplifiers and attenuators.

3.1 Dealing with Variable Input Levels

First, the low level signal is amplified using a gali-51 +18dB amplifier to separate it from the
noise floor before it is attenuated again. The signal passes into the digital attenuator section
where, depending on the input RF frequency and voltage level, it is variably conditioned to
a constant value. 6 bit digital attenuators are used to give an attenuation range from 2.5dB
to 31.5dB in 0.5dB steps (Table 3.1). To accommodate the wide range of levels that may
be encountered, two digital attenuators are cascaded to provide a minimum attenuation of

-5.0dB (-2.5dB insertion loss). Both attenuators are connected to the same control bits,

18

Table 3.1. Digital Attenuator Control Bits.

 

Digital Control Bits Attenuation (dB)

 

 

 

 

000000 2.5
000001 3.0
101000 22.5
111110 31.0

 

 

111111 31.5

 

 

 

so a one bit change on the control lines is equal to a 1dB change in attenuation. The
result is that any signal within the specified levels can be conditioned to within 1dBm
of the target constant value of ~28dBm. The signal is then amplified up to +17dBm to
match to near the full-scale value of the ADCs and stay within the tolerances of the gali-
51 amplifiers (+18.3dBm 1dB compression point). A chain of static attenuator pads and
gali-Sl amplifiers (Appendix D, Figure D3) is used to condition to the desired levels. The
attenuator pads are used to increase the stability of the gain stage by decoupling the inputs
of cascaded amplifiers. By adding a lossy component between amplifiers, the interaction
between them is dampened.

Each amplifier is biased to around 4.2V using +12V and a 120W resistor. A 4.7pH
inductor is placed in series with the DC biasing circuit to reduce the RF from the amplifier
so that it does not couple to the DC bias network. A 0.1pF capacitor to ground between the
resistor andthe inductor provides a RF ground to further limit the effects of the amplifier
on the bias network[10]. The DC blocking capacitor values were chosen such that their
reactance is low enough so as not to attenuate the IF as it passes into the 50 (2 input of the

next amplifier.

19

3.2 Noise and Interference Considerations

Due to the large amount of attenuation and amplification needed to handle the variable
inputs, internally generated noise created by the amplifiers, mixers, attenuators and in-
terference from other RF signals on the board could pose a real problem if not handled
prOperly. Interference occurs when other RF signals couple either capacitively from trace
to trace or as bleed-through in the case of mixers and filters. In general, thermal noise,
also known as Johnson noise, shot noise and flicker noise make up the sources of internally
generated noise in a system. Amplifiers and resistances introduce noise as a result of the

random thermal motion of electrons following the equation[10, l 1],

v2 = 4kTR( f)A f (3.1)

where k is Boltzman’s constant, T is the absolute temperature, Af is the bandwidth and
R(f) is the frequency dependent resistance. The noise factor (F) of a part is defined as the
ratio of the signal to noise ratio (SNR) at the input to the signal to noise ratio at the output

(Equation 3.2)[10, 11].

SNRIN

= 3.2
SNROUT ( )

 

Converting the noise factor to dB yields the noise figure (NF). The noise figure of an at-
tenuator is equal to the attenuation and the noise figure of an amplifier is typically given in
the specifications sheet. The loss through the mixer is approximately 4.7dB, therefore the

noise figure of the input section including the attenuators is 37.7dB. Using the noise figures

20

of cascaded parts, the noise factor of a section of circuitry can be calculated [10, 11] using,

F2 —1 F3 —1 FN —1
F =F + + +...+
O 1 CM 0211ze GAlGA2---GA(N—l)

 

 

(3.3)

where F1, F2, ..., FN are the noise factors of each stage and GM, 0A2, GAN are the gains
of each stage converted from dB. From the specifications sheet, the noise factor of the
gali-Sl amplifiers is 3.5dB and the gain is 63.1. The noise factor of the attenuators in the
chain is 3dB and the gain is 0.5. Using the formula above, the noise figure of the amplifier
chain is 2.29, which corresponds to a noise factor of 3.6dB. This means the input stage
reduces the SNR by 37.7dB and the amplifiers add enough noise to the system to reduce
the SNR by another 3.6dB. Taking readings for each channel using a spectrum analyzer
(HP Model E44028) shows that the noise floor at the input to the ADCs is much lower than
the signal, although signal coupling is a problem at certain frequencies. This leads to the
fair assumption that the signal to noise ratio at the input is much higher than can be read by
the spectrum analyzer and that most of the fluctuations in the signals being digitized are a

result of interference.

3.3 Interference Analysis

Figures 3.1a, b and c show the fast Fourier transform (FFI‘) of the signal being sampled on
the module input channel 1 at 9, l8 and 27 MHz. Figures 3.2 and 3.3 show the same for
the module inputs on channels 2 and 3. Notice the amount of interference on channel 2 is
much higher than that of channels 1 or 3. This is mostly due to the physical layout of the
channel with respect to the LO traces and the FPGA filter capacitors. For channels 1 and 3,

21

 

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Figure 3.1. Channel 1 FFT Plots at 9MHz(a), 18MHz(b) and 27MHz(c) at the input to the

ADC

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0

Figure 3.2. Channel 2 FFT Plots at 9MHz(a), 18MHz(b) and 27MHz(c) at the input to the

ADC

any interference frequency is at least 30dB down from the fundamental SOMHz signal so

it is safe to say that the signals are relatively clean when being sampled and that the noise

and interference for those channels is negligible.

22

2.2-222.2Marker 22222222Marker Marker

 

 

 

22*: 14500000 MHz 50 OOOOMHz . 1 50.0000 MHz
. i7. , -191 dBm . l]: ., -19 67 dBm , -19 06 dBm

17:1: i:§.:.’: ‘*“ 17"“ m 31 i *1; - l “:51“:

7% V~7*‘7_ 77‘7“ wk RJVWM 77“” 212x...»- LLTQJ 34”” fiijkw" Lurk“ Lam ljkuww
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a b

0

Figure 3.3. Channel 3 FFI‘ Plots at 9MHz(a), 18MHz(b) and 27MHz(c) at the input to the
ADC

23

CHAPTER 4

Phase Lock Loop

For this phase meter to be useful in an environment where multiple modules are to be com-
pared against each other, a stable reference must be used to synchronize the internal clocks
in each module. The phase lock loop IC (PLL) compares the phase of the generated clock to
the phase of the reference signal, providing a control signal to the voltage controlled crystal
oscillator (VCXO) to adjust the frequency of the clock and synchronize them[12] (Appen-
dix D, Figure D.5). Connecting the reference signal to each separate module ensures the
modules are locked to each other. In this way the phases calculated by each module are

synchronized to the same reference.

4.1 General Operation

The main PLL chip, the ADF 4001 , has two RF inputs. The first input is the reference signal
generated by a high quality signal generator. The reference signal will is used to lock the
phase of each of the clocks generated by the VCXO on the board. The second input port

on the PLL chip is the feedback from the output of the VCXO. The PLL compares the two

24

signals by dividing them in such a way that [13],

R
fVCXO = 1V *freference (4-1)

R is a 14-bit programmable number that can take integer values from 1 to 16,383. N is a

l3-bit programmable number that can take integer values between 1 and 8,192.

4.2 Modulating the VCXO

A phase frequency detector (PFD) runs at the frequency of the divided signals and compares
them to generate a current output based on the amount of phase variation. The chip can be
programmed for either a positive or negative current output, where a positive current output
means when the reference phase lags the VCXO phase the current pulse will be positive
and vice versa. The ADF 4001 modulates using a bipolar pulse width modulated (PWM)
current output which has a maximum frequency equal to that of the PFD. The higher the
PFD frequency the faster the PLL can control the VCXO. The modulation limit of the
VCXO is lOkHz and the typical design rule is to set the loop bandwidth of the inverting
integrator to be 1 / 3 of the modulation limit to get good performance [3, 12], leading to

Equation 4.2.

l 1

BW = — = _—
‘00” 21tRC 2n15ko3nF

= 3.54kHz (4.2)

The output of the integrator is used as the control voltage to the VCXO. 3.5kHz is well
within the specified modulation bandwidth of the VPLD54TE VCXO, so to remove any

high frequency noise or interference from the control voltage line, a low pass filter with a

25

 

 

:- vm ADJ

4:]- 610 if R1 iL

 

 

 

 

IN OUT - Vour

 

Figure 4.1. Power Supply for PECL Compatibility

3dB comer frequency of around 7kHz limits the oscillations at its input. The slow response
of the VCXO to the control voltage keeps the clock signal very stable once it has locked.
The VCXO on this board has a center frequency of 8OMHz and a pull range of around

8kHz for an input voltage range of 0 to 3.3V.

4.3 Creating the Clock Signals

The differential output is positive emitter coupled logic (PECL) compliant and requires that
each pair be terminated into VCC minus 2.0V[ ] 4]. The LT1964 produces an output voltage
of,

R
V,,,, = —l.22V(l + 172) (4.3)
1

Referring to Figure 4.1, setting R2 = 12m and R1 = 18k!) this power supply maintains
the -2V necessary to run the PECL outputs correctly. The VCXO differential outputs are
run to a PECL clock divider with both fvcxo and fvcxo / 2 outputs that converts from the
sine wave output of the VCXO to square wave clock signals. Since all of the outputs are

generated from the same input, the phase of each clock output is locked. A fvcxo output

26

and a fvcxo / 2 output are converted from differential to single ended signals to clock the
DAC and the FPGA. The other fvcxo / 2 output is routed to a 1 to 1 RF transformer whose
primary center tap is terminated into -2V and whose secondary center tap is terminated to
ground. This signal is routed to each ADC to initiate sampling. Any variation in sampling
times will show up as a phase error, therefore the PCB traces must be closely matched
from the transformer to each ADC to ensure that all of them sample at the same instant.
One of the fvcxo / 2 lines must also be fed back to the PLL to make sure the phase of
the clock signals is locked to the phase of the reference. Using one reference for multiple
meters locks the sampling in each module to the same reference and ensures the phase data

collected in each module is coherent.

27

CHAPTER 5

Signal Digitization

The RF input signals have been mixed to a common IF and conditioned to a level at or near
the full scale input of the analog to digital converters (ADCs) where they will be digitized
and transferred to the FPGA. Digitizing signals can sometimes yield unwanted effects if
the sample frequency is not sufficient to recover the entire signal. However, with careful

manipulation, it may be possible to recover all of the information that is required.

5.1 Nyquist Zones

Generally speaking, when the frequency content of a signal is not known explicitly, N yquist
criterion states that to recover all of the frequency content within the signal without losing
any information you must sample at a minimum of two times the highest frequency that
may exist in the signal. Frequencies that lie within the band starting at O and going up to
one half of the sampling frequency (f,) are contained within the 1” Nyquist zone. From
f, / 2 to f, is the 2"" Nyquist zone, f; to 3 * fs / 2 the 3’4 Nyquist zone and so on. Setting f,
sets which zone a frequency will be contained in. Sampling a signal creates images of the
frequency, f, at,

fimagezlimfvif' (5-1)

28

where m = 1,2,3...
Given a frequency spectrum in the 1" Nyquist zone, the orignal signal may have been
contained in an even Nyquist zone, in which case the original frequency spectrum is a

mirror image of the l" Nyquist zone with frequencies equal to,

n — l
f n = (_—2_& — f (52)
whereas an original signal contained in an odd Nyquist zones will have frequency content

equal to,

f. = (1:211 +f (5.3)

where n is the Nyquist zone in question and f is the frequency content of the signal in the
1" Nyquist zone.

When a signal is sampled using an f, such that some of the frequency content is outside
the 13, Nyquist zone, aliasing occurs. Aliasing is the method by which frequency content
contained in higher Nyquist zones folds back as an image into the lst Nyquist zone. Images

of the higher frequencies appear at,

fimage = lmfs _ f highl (5-4)

where m is the integer required to bring fimage into the 1“ Nyquist zone. This method is
called undersampling and is useful in certain applications when the frequency content of

the signal is known. For more information, see [7, 15].

29

5.2 Vector Data Using Nyquist Zone Manipulation

A vector modulation/demodulation technique is applied to map the frequency of interest
(IF) to the complex plane to facilitate setting/reading of the phase and amplitude. The In
Phase (I) value and the Quadrature (Q) value map to the real and imaginary axis of the

complex plane. Using Euler’s identity the signal may be cast in the following form,

V,p(t) = Re{|vp|ef(wlr‘+¢) = I + jQ} (5.5)

The magnitude and phase can be determined from the I and Q values of the vector using

the equations[5],
Magnitude(M) = \/ 12 + Q2 (5.6)
and
Phase(0) = tan-Mg) (5.7)
V1p(t) may be written as,
V]F(t) = Vp COS(0)1FI + ¢) (5.8)

Using a sampling frequency to, = 40)IF yields a sampling interval that is periodic with a
time step of,
_ 21tk 21tk kn

A: _ = = _ 5.9
(0,- 4601)? 2(1)”: ( )

mmk=qhzmqnzau

This gives a rotation of 12‘- or 90° between each sample. V1p(k) can be recast into the

30

form,

k1!
V1F(k) = VpCOS(¢ - ‘2“) + Voffset (5.10)

where sequential values of k correspond to sequential sampled values which may have a
slowly varying offset of Voffse, and a coordinate plane rotated by 90° steps such that A

9 = — £2“- . The following values are further defined,

V1p(0) = Vpcos(¢) + Voffm E I+ (5.11)

v,p( 1) = V, cos(¢ — g) + voffm = VP sin(¢) + Voffm a Q+ (5.12)
V1p(2) = Vp cos(¢ — n) + Voffm = —Vpcos(¢) + Voffse, _=_ I’ (5.13)
V,p(3) = Vpcos(¢ — 2211)+V0ffse, = —Vp sin(¢) + Voffse, E Q“ (5.14)
(5.15)

These samples repeat to form a recurring set of four values that are used by downstream

microprocessors to create the I and Q values where[4, 5],

+ _ _
[=1 2] =Vpcos(¢) (5.16)

 

and

=_Q_+-_Q:

Q 2

= vpsin(¢) (5.17)

By taking the subtraction, Voffm will be removed leaving only the magnitude of the IF
multiplied by either a cosine, for I, or sine, for Q. The digitized channels each have a set

of I and Q values which were all taken simultaneously so that they can be used to calculate

31

the phase between channels.

To gather samples 90° apart requires an ADC that can sample at a rate of f3 = 4f1p,
which could pose problems for higher IFs since conventional ADCs are limited to around
105 mega samples per second (MSPS). By moving the IF to a different Nyquist zone,
undersampling can be used to lower the sampling frequency required while still retaining

sequential I, Q, -I and -Q values according to the equation[4, 7],
f3 = __ (5.18)

where n = 1,3,5...
By forcing the IF into a higher Nyquist zone (n1), the same I,Q, -I and -Q values will

be sampled but the bandwidth will change according to the equation,

BW = g = é—Nyquistgw (5.19)

The bandwidth refers to the image frequency created based on the IF and the sampling
frequency and will always be % the minimum Nyquist bandwidth because four samples per

cycle are required instead of the minimum two as defined by Nyquist[15].

5.3 ADC Implementation

The phase module uses the ADSSS42 ADCs with a maximum sample rate of 80MSPS.
According to Equation 5.18, to gather I/Q data when the 50MHz IF is in the 1“ Nyquist

zone, a sampling rate of 200MHz is required, well beyond the maximum sampling rate of

32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

/‘\ r * r ’5 1
/ \
I, \\ I \ I] \‘
I 1 ’ \ I
I \ I, \ ’ \\
0.8 r- I 1 , ‘\ I 1 r“
1 1 ’ ‘ 1 1
1 ’ 1 1
0 6 1’ 1‘ f 1 1' ‘1
f 1 I ‘ l 1
l 1 1
l! ‘1 I ‘ 1l ‘1,
0.4 ‘ l l 1 I '
1 ‘1 1 1 , \
f 1 ' ‘ l ‘1
O) I ' ‘ I 1
1 ‘1 I ‘ l 1
'0 0.2 ~. . 1 1 1 H
a 1 ' 1 1
1 ‘ I 1 1 1
E1. ‘ ' ‘ 1 ‘
,1»- 1 11 41 .4
<6 0* f 1 j 1
1 l l 1
2 ' 1 1
1‘ 1! , 1
-0.2 +- 1 , 1 l1 -
‘1 ‘ ‘ 1
1 ' ‘ 1
1 ' ‘ I
l 1
“0.4 ’— “ l 1 1’ "1
1 ’ ‘ I
1 1
1 1
1 1
‘1 ,1 1‘ 1’ —— 50111112
-0.8 ~ ‘1 ’1 1‘ ,’ t Sampled Pains
\\ ’1 1 ,’ --- 10MHZ
1
X ’ ‘ / 11 U l
_1 _F l l l
0 0.5 1 1.5
Time

Figure 5.1. Undersampling 50MHz using _f_,=40MSPS

conventional technology. Nyquist zone manipulation using an undersampling technique is
used to shift the IF into a frequency realm that can be easily handled by readily available
technology. Choosing n=3 in Equation 5.18 to put the 50MHz IF into the 3rd Nyquist
zone, an 1‘} of 40MSPS will be necessary. This creates a lOMHz image of the 50MHz
IF (Figure 5.1). 40MHz is also four times lOMHz, meaning each sample is 90° delayed
from the one before it. These samples will correspond exactly to the samples taken from

the 50MHz signal sampled at 200MHz, thereby reducing the required sampling frequency

33

 

R18

 

 

 

 

 

W——
. .. ,_ n 25 r
1 m 1115‘
2 R20
‘ 499
6 1
Trirr-szr f - 3'9
25

 

Figure 5.2. RF Transformer Section

without losing any phase information.

5.4 Signal Preparation

To prepare the signals for the ADS5542,the single ended IF signals are passed through
a 1:1 RF transformer (Figure 5.2), which converts them to differential signals as per the
requirements of the ADCs (Appendix D, Figure D4). The center tap on the secondary side
of the RF transformer is connected to the common mode pin of the ADC to put a DC bias
of 1.65V (Vjc-Q) on each signal branch. The common mode voltage generated by the ADC
must be very clean to ensure stable signals, therefore a 100 resistor in series with the center
tap and two filter capacitors, in parallel and connected to ground, are required. A 49.9!)
resister between the positive and negative paths matches the impedance of the transmission
line and the 259 resisters in series with the inputs to the ADC help to dampen any reflected

signals and ringing due to the sample and hold nature of the chip[l6].

34

 

Magnitude

30

 

50

Amplitude

70 90 ‘

 

 

 

Frequency (MHz) Time
a

Figure 5.3. The figure on the right (b) shows the DAC I/Q square wave output and the
figure on the left (a) is the FFT of the square wave

5.5 High Speed DAC Output

This module has been designed so that it can be extended to replace the existing phase con-
troller and do all of the regulation necessary to run a cavity or cyclotron dee. The output of
the module is set by a high speed digital to analog (DAC) converter that is controlled by the
FPGA (Appendix D, Figure D.9). Clocking the output at f_,, the FPGA repeatedly sends
l4-bit I, Q, -I and -Q values sequentially to the DAC (Figure 5.3). These values are set by
the microprocessor and will dynamically update based on the phase that is desired and the
phase that is being read off the RF input channels. The fs/4 square wave output that this
method creates contains spectral lines at the fundamental f, / 4 and at all odd harmonics
of fs/4[4]. It is important to keep the sampling frequency as high as possible so that the
IF is in the lowest Nyquist zone that can be maintained. The higher the Nyquist zone the
higher the odd harmonic required to get back to the IF. Since the harmonic levels fall of as

a function of 1 / f 2, the lower the starting frequency the lower the level at the IF[4]. The

35

DAC output is then filtered through a bandpass filter set at the IF to remove the higher and
lower harmonics, leaving a clean IF signal. This IF signal is mixed with the LO frequency
to recreate the original RF. The LO+IF is filtered out using a low pass filter with a comer
frequency such that the maximum RF may pass without much attenuation but the minimum
LO+IF will be filtered out. The required level at the output is +13dBm (lVRMS). An am-
plifier and attenuator chain using two gali-Sl amplifiers with +18dB of gain and multiple
attenuators of various sizes are used to condition the signal to the correct level while main-
taining stability in the same fashion as before. This feature is meant to be implemented at

a later date and is documented to be extend the module for cavity and cyclotron control.

36

CHAPTER 6

The Field Programmable Gate Array

The field programmable gate array (FPGA) is the data collection hub and is used to read
and store the data sampled by the ADCs. Samples are separated into I, Q, -I and -Q values
and transferred to the microprocessor for phase and magnitude calculations. The FPGA is
also used to set the digital attenuators in the amplifier/attenuator chain to condition the IF
and for sending I/Q data to the high speed DAC for RF control (Appendix D, Figure D.6).
Pins are made available for connecting a DSP card to expand into the control realm in a

future project[5].

6.1 FPGA Connections

The high speed and large number of pins configurable as inputs and outputs makes the
FPGA a prime candidate for collecting and routing all of the information to the correct
places. Each ADC in this module is connected in parallel, each using 14-bits for data and a
1-bit as an RF over range indicator. A high speed DAC also has a 14—bit data bus and a l-bit
power down control line connected to the FPGA. A 16-bit data bus connects the FPGA to
the microprocessor, using 8-bits configured as inputs to the FPGA from the microprocessor

and 8-bits configured as outputs from the FPGA to the micr0processor. Two handshaking

37

Table 6.1. I/Q Determination.

 

 

 

 

 

Sample # Counter Value I/Q Value

l,5,9,13... 0 l
2,15,10,14... 1 Q
3,7,11,15... 2 -I
4,8,12,16... 3 -Q

 

 

 

 

 

bits, one set by the FPGA and one set by the microprocessor, synchronize the data transfer
between. A 4-bit command bus controlled by the microprocessor is used to indicate to the

FPGA what data is required and how it is to be utilized.

6.2 Collecting I/Q Vector Data

The ADCs are configured to sample the IF on the rising edge of the sampling clock, and the
digital information is ready and stable on the data bus at the falling edge of the clock. The
clock is used as an input trigger for the FPGA and an event is set to trigger on its falling
edge to read the input values from each of the four ADC data buses. As was discussed
before, the IF is undersampled to yield digital data that is periodic with a frequency of f3 / 4
. Each input is run through a first order digital band pass filter that has a center frequency

of f} / 4 corresponding to the difference equation,

y[,,]_£[fl_2’["_-Zl (6.1)

2 2

to remove any noise that may have been picked up by the ADC during sampling[15]. A
2-bit counter casts the sample as being either I, Q, -I or -Q, naming the first sample I, the

second Q, the third -I, the fourth -Q and then repeating as in Table 6.1. Each channel is

38

latched in parallel, so on the first falling edge of the clock the FPGA reads and stores IA, 13,
[C and [35; simultaneously. On the next falling edge of the clock, it reads and stores Q1,

Q3, QC, QREF and so on. In this manner, the channel to channel phase is conserved.

6.3 Conditioning the Inputs

If the phase of the inputs is not changing, the HQ values should be constant as well. So, to
reduce the effect of interference and digital noise on any of the ADC inputs, a low pass filter
is implemented on the raw data that is sent to the microprocessor. To increment(decrement)
the value currently held in an I, Q, -I or -Q register by l-bit, the current input must be
greater(less) than the stored value for some specified number of clock cycles. If the value
of the input dips below(raises above) the stored value for one clock cycle, the process is
restarted.

The maximum number of clock cycles required to increase by l-bit is specified by the
variable ’center’ and is referred to as the filter factor. The number of clock cycles required
to move by 1-bit can be set anywhere from 1 up to ’center’. The more cycles required to
move the stored value, the less fluctuation the phase measurement will have. However, the
system response to a real phase change will be slower following the equation,

% =1: fscycles/s * 360°
filter factor 214bits

 

At(deg/s) = (6-2)

For example, with f, = 40MHz and a filter factor of 1,000 cycles, the result will allow a
maximum rotation of 219.7° per second. An 180° shift would take 0.82 seconds to settle to
the correct phase. Requiring a high number of cycles may cause problems with accuracy

39

on a signal that contains a large amount of interference that is not completely random. If
the sample value fluctuates around some median number due to random noise, eventually

the I, Q, -I and -Q values will be accurate.

6.4 Creating the DAC Output

Two branches of code are run on the falling edge of the clock. The first branch of code cre-
ates an RF output by sending I/Q data to the high speed DAC. In the current implementation
of the code, l/Q data from one of the four input channels is selected and directly fed through
to the DAC. Eventually, the HQ data will be set by a control processor that calculates the
phase desired and compares it to the phase that is being read. The control processor will
transfer the four I/Q values to the FPGA and they will be continuously cycled to the DAC

until a new phase or magnitude is required.

6.5 Buffering the Inputs

The second and most important branch of code to the phase meter is the double buffering
of the HQ data for transfer to the microprocessor. After every fourth sample is taken, the
values stored in the registers for I, Q, -I and -Q for each input are shifted to another set
of registers that are read directly by the microprocessor. If the FPGA is in the process of
sending the HQ values to the microprocessor the buffers will not be updated. This allows the
FPGA to continue latching data from the ADCs in real time without affecting the data that
is being read over multiple cycles by the microprocessor. Once the transfer has completed,

the FPGA is able to shift the HQ data into the buffers again.

40

Command

 

 

 

 

. . . Data read by
1n1trated by .
ZWorld ZWorld from FPGA
handZWorld
handFPGA

 

 

 

 

Command FPGA reset,
received and ready for new

processed by command
FPGA

Figure 6.1. Handshaking Timing

6.6 Data Bus 'h‘ansfers

Transferring the data to the microprocessor requires handshaking, which is also handled on
the rising edge of the clock. This ensures that the commands are sent and received by the
FPGA at a periodic rate and synchronized to the rest of the operations. The FPGA samples
the microprocessor handshaking bit to determine if a command is waiting to be executed
on the command bus. When the handshaking bit transitions, it triggers a command bus read
and initiates command processing. The FPGA sets its own handshaking bit to relay to the
microprocessor as to the status of the command processing. The timing of the handshaking
is illustrated in figure 6.1.

On a positive transition of the microprocessor handshaking bit the FPGA reads the

command bits and determines the action to take according to Table 6.2. Any data that

41

Table 6.2. FPGA Commands.

 

 

 

 

 

 

 

 

 

 

Command Action
0000 Set digital attenuators
0001 Set ADC channel to DAC
0010 Send an I value to ZWorld
0011 Send a Q value to ZWorld
0100 Send a -I value to ZWorld
0101 Send a —Q value to ZWorld
0110 Read high 8-bits of filter factor
0111 Read low 2-bits of filter factor
1000 unfreeze I, Q, -I, -Q buffer update

 

 

 

 

Table 6.3. ADC Mode Select.

 

 

 

 

 

ADC Mode Value DAC Output Source
00 Channel 1
01 Channel 2
10 ‘ Channel 3
1 1 Reference Channel

 

 

 

 

must be read from the microprocessor is latched and any data that needs to be sent to the
microprocessor is set up on the data bus. The FPGA responds that it has finished processing
the command and waits for the microprocessor to read any data it needs and release the data
bus.

Setting the digital attenuators and the ADC mode are simple reads from the data bus.
The 6-bit attenuator value requires a single read and the value is shuffled directly to the
output pins connected to the chips. The ADC mode selects the input channel that is passed
through to the DAC output according to Table 6.3.

The 8-bit data bus requires that the values be broken up and sent in two sections. The
bits on the command bus determine whether the I, Q, -I or -Q values are to be read, while

the data bus from the microprocessor tells the FPGA the channel to send and whether to

42

send the high or the low byte for that channel (See Appendix A for a complete description).
The FPGA loads the required data onto the data bus to the microprocessor and toggles its
handshaking bit high to indicate the command has been processed and the data is available.
Once the 8-bits have been read, the FPGA goes back into normal operation and waits for
the next command from the microprocessor. However, the HQ buffer updates do not resume
until all of the HQ values have been read and the command has been issued to begin again.

The final command allows the microprocessor to change the filter factor to change the
number of cycles required to increase and decrease the HQ values stored in the FPGA. It is

defined as a 10-bit number and requires two bus transfers to transmit the entire value.

6.7 Conclusion

The high speed and parallel processing of the FPGA makes it a robust solution for routing
and storing massive amounts of data in real time. Without these capabilities, the techniques
used to make this phase meter work would not be possible. For future exploration, the
FPGA could be integrated into more of the control and data processing algorithms the

expand on its role in the phase meter.

43

CHAPTER 7

The Microcomputer

7.1 The ZWorld Microcomputer

The ZWorld Rabbit Core 3200 microcomputer is the CPU of choice for this project. Nearly
any microcomputer could be used as long as it has the ability to communicate over Ethernet
and has a serial programming interface (SP1). Changing the microcomputer would require
changing the connector on the board and rewiring the new connector to the existing pe-
ripherals. The World was used because of the vast amount of code already developed for
Ethernet and Telnet communication here at the lab making integration into the cyclotron
control system much easier. The code specifically written for this thesis is included in the
Appendix B.

The ZWorld handles all of the external communication and configures the chips on the
board. It provides the initialization routines and data to get the module up and running.
Through the ZWorld telnet interface, the user can set and change all of the configurable
options on the board. Most importantly, the ZWorld microcomputer is responsible for
reading in the raw data from the FPGA and calculating phase and magnitude information.
For a schematic of the ZWorld connections see Appendix D, Figure D.2. Lastly, it manages

all bus communication with the FPGA to initiate data transfers.

44

.~ ‘ C:‘\W1NNI\system32‘\telnet.exe

13:34:31
Cthate: 108(B)(2588) ConRate: 394 Ttl u Errs: 0/1884

5.952
0.229

Degrees
U)

ananh aha-aca

De
Degree:

8
1
B
B
0
Q
6
1
1
B
1
8
0
B
1
1
' 1

R)
Offsctfl
Offsctn

 

 

Figure 7.1. Telnet Interface

7.2 Interacting with the ZWorld

There are a number of digital I/O ports on the ZWorld microcomputer that are used to
communicate with the various chips on the board. These include four sets of serial transmit
and receive ports, 13 digital inputs to the ZWorld and 24 digital outputs from the ZWorld.

A complete list of I/O port configurations can be found in Appendix C.

7.2.1 The User Interface

For this thesis, the front end (Figure 7.1) displayed by the ZWorld over the telnet connection

contains most of the pertinent information as to the status of the module Table 7.1.

45

Table 7.1. Telnet Interface Description.

 

 

 

 

Telnet Label Description
DI-XX Displays the value being read on the XX digital input pin
DO-XX Displays the value being sent to the XX digital output pin
/IN IT Initialization pin on the FPGA, used for configuration timing

 

DONE Done pin on the FPGA, indicates the FPGA has been programmed
PROG Program pin on the FPGA, used to initiate FPGA programming

 

 

 

 

 

 

 

 

 

Filter Displays the stored filter factor
Dig. Atten Displays the digital attenuation (dB)
ChX Phase Displays the phase as 901x — 0,4
ChX Mag Displays the magnitude of channel X
OffsetAB Displays the static offset from Channel 1 to Channel 2
OffsetAC Displays the static offset from Channel 1 to Channel 3
Ref Phase Displays the phase of the reference
Ref Mag Displays magnitude of the reference

 

 

 

 

7 .2.2 Serial Programming

The ZWorld is responsible for setting up all of the chips on the phase meter board. The
phase lock loop, the FPGA, the fast ADCs, the slow ADC, the slow DAC, the digital attenu-
ators and the EEPROM are all configured using the serial programming interface. The EP-
ROM and the FPGA are both serially programmed with files stored on the network[l7, 18].
The ZWorld can transfer a configuration file from an Ethernet connection to the FPGA or
to the EEPROM. It can also write the file from the EEPROM to the FPGA when there is no

network connection.

7.2.3 User Commands

The Telnet interface allows the user to input commands to configure everything from the
fast ADC’s mode to the PLL divide ratios. The FPGA and EEPROM configurations are

both initiated by the EPICS control system. The commands in Table 7.2 are implemented

46

Table 7.2. ZWorld Telnet Command List.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Telnet Command Description
init # Initialize the PLL (values 0-7)
config # Reconfigure the PLL without initializing (values 0-7)
ncount # set the N-Counter Register for the PLL (values 1- 1023)
rcount # set the Reference Counter Register for the PLL (values 1-1023)
dig # # set output bit (0-23) to either 1 or O
setatten # set the digital attenuators (values 5-45)
setadc # set the AD85542 ADC mode (values 0-3)
read # set the channel that is fed through to the DAC (values 1-4)
filter # set the filter factor
offsetab # set the phase offset between Channel 1 and Channel 2
offsetac # set the phase offset from Channel 1 to Channel 3
Table 7.3. Telnet Interface Description.
M3 M2 M1 Output
0 0 0 Three-State Output
0 0 1 Digital Lock Detect
0 l 0 N -Divider Output
0 1 1 AVDD
1 0 O R-Divider Output
1 0 1 N-Channel Open Drain Lock Detect
l l 0 Serial Data Output
1 1 l DGND

 

 

 

 

in the current incarnation of the ZWorld program. The PLL can be configured for diag-
nostics so that pin 14 on the ADF 4001 outputs various internal signals that would not
normally be available for probing (Figure 7.3). The bits in the initialization register and
the configuration register are the same. The initialization register must be loaded first after
power is applied to the chip to reset the inner workings. For changes after the chip has
been initialized, the configuration register should be modified. Only the diagnostic values
M3, M2 and M1 are configurable by the user. The rest of the bits are set by the ZWorld

program to put the ADF 4001 in normal operation mode with a current output of 5mA

47

 

and a phase frequency detector timeout of three cycles. The fastlock is turned off and the
phase frequency detector polarity is set to positive so that when the VCXO phase leads the
reference phase the charge pump output is positive and when the VCXO phase lags the
reference phase the charge pump output is negative. These settings are applied when both
confi g and init commands are run. The rcount command sets the VCXO frequency divide
ratio to the the user specified value, sets the antibacklash pulse width to 1.3ns and sets the
lock detect precision to 3 cycles. The ncount command sets the reference frequency divide
to the value specified by the user. For a complete description of these parameters see the
[13].

An interrupt routine, running once every 10ms, handles processing commands from the
user interface (UI) as well as data transfer to and from the FPGA and phase calculations.
On its first run, the interrupt routine sets up the PLL to run with MUXOUT configured as
digital lock detect, sets the VCXO divide ratio to 4 and sets the reference frequency divide
ratio to 1. This assumes a lOMHz reference and a 40MHz sampling frequency. The IF
sampling ADCs are configured to run in normal operation mode.

The ZWorld must initiate all bus transfers by toggling a handshaking bit to trigger the
FPGA. Before the handshaking bit is toggled high, the command to be executed and any
data pertaining to that command must be written to the outputs. Next, the handshaking bit
is toggled. Setting the command and data bits first allows them to settle before the FPGA
reads them. The ZWorld waits for a response from the FPGA that the command has been
read and processed. Once that response has been received, the ZWorld reads any data the
FPGA has set and releases the bus.

The main task of the interrupt routine is to retrieve the HQ data from the FPGA and

48

calculate the phase. The I/Q values are stored as 16-bit numbers and require two 8-bit bus

transfers for retrieval. The process of reading the entire set of I/Q data and calculating the

phase requires 67 passes through the interrupt. The interrupt is triggered every lOms so the

phases are updated at a rate of,

Tupdm = 67cycles =1: 10'3 s/ cycle = 0.673

The phase of each channel is calculated using,

The phase between each channel is determined using,

9cm = 91 -9ref '
91:12 = 92 - eref

9ch3 = 93 - Ore f

which leads to channel to channel phase to be taken as

9ch1-ch2 = 9cm — 9ch2 = 91 - 92
9(:hl-ch3 = 9chl _ ec113 = 91- 93

9c112—ch3 = 9.112 - 9ch3 = 92 — 93

49

(7.1)

(7.2)

(7.3)

(7.4)

(7.5)

(7.6)

(7.7)

(7.8)

The magnitude is calculated using,

Magchl = 1/112 + Q? (79)
Magchz = 1/1§ + Q3 (7.10)
Magda = 1/I§+ Q3 (7.11)
Mag”, = ,/I,2,_,f+ Q34 (7.12)

The ZWorld microcomputer does an excellent job of handling the module configuration,
processing the data and acting as the front end for the user interface. The low phase update
rate requirements of the phase meter make the ZWorld an ideal chip for calculating phase,
however, when control is implemented, the task of calculating phase will rest on a much

faster DSP.

50

CHAPTER 8

Signals and Interlocks

A final section of interlocks, monitoring systems and supplemental hardware allow this
module to be practically useful to the existing cyclotron system. These systems monitor
the status of the external RF control system to control the functionality of the module and

monitor the functionality of the module to relay the module status to the external system.

8.1 External Signals and Status Indicators

A set of LEDs provides vital information at a glance regarding the operation of the module.
The microprocessor controls the status of these three LEDs (Appendix D, Figure D.8).
Located on the back of the module, the activity LED lights when the CPU is busy being
updated. On the front of the module, the RF On LED relays the status of the RF in the
module and the Ready LED lights when the configuration process is done and the module
is in working order.

Two signals from external systems are buffered and connected to the FPGA as inter-
locks. An RF enable signal connects to the front of the module and is generated by the RF
control system to turn the RF on and off. A module reset signal is also generated by the

cyclotron control systems. Both signals tie directly to the FPGA and are used as inputs,

51

responding quickly to any change on either one.

The FPGA creates a high-speed fault signal, which is used to indicate a problem with
the RF anywhere inside the phase module. The fault can be tied to any type of internal
workings including a loss of RF or an overload signal from an ADC that has an RF level
that is out of range, to name a few. This signal will, again, be more useful once the cavity

control has been instantiated.

8.2 Housekeeping Circuits

In addition to status LEDs and interlocks, there are a couple of other housekeeping cir-
cuits that monitor the inner workings of the module and report the information back to the
microprocessor (Appendix D, Figure D.10). An ADS7825 l6-bit 4—channel serial ADC is
used to read slowly varying voltages. The full-scale input of the ADC is 10V with a conver-
sion time of 20115 and an acquisition time of Sps. The maximum sample frequency of the
ADC is 40kSPS, which is plenty fast to sample the aforementioned signals since they are
expected to be slowly changing and their values need only be monitored periodically. Two
of the four channels are connected to signals on the board, with the other two left as spares
for future use. An analog temperature sensor monitors the temperature of the board and
outputs a voltage of 250mV at 25C with a slope of lOmV/C. An amplifier is used to con-
dition the voltage output of the temperature sensor to utilize more of the full-scale input of
the ADC to reduce digitization error and give a more accurate reading. The control voltage
for the VCXO is also conditioned and sampled so the lock status of the PLL can be moni-

tored. The conditioning is done by four op amp circuits, which are set up as non-inverting

52

amplifiers and follow the equation,

R
Vout=Vin(1+§;-) (8.1)
l

where R; and R2 are chosen to try and use as much of the full scale of the ADC as possible.

The Spartan II XCZS 150 FPGA used on this board requires a configuration file that is
130,012 bytes, which is larger than the available flash memory on the microprocessor. The
FPGA configuration memory is volatile meaning that it loses the information when power
is removed from the chip. An AT25P1024 leit serial EEPROM with 131,072 bytes of
available storage space is used to store the configuration file when the power is oftIl9]. The
EEPROM communicates with the microprocessor using the Serial Programming Interface
(SP1). On power up, the microprocessor can pull the configuration data from the EEPROM
and send it to the FPGA or transfer it over Ethernet. This allows the module to work even if
it is not connected to a network from which it can download the latest FPGA configuration
data.

The last housekeeping circuit is the 4-output 12-bit serial DAC model MAX5742. The
four outputs are individually configurable and are intended to output a voltage proportional
to the different phase readings taken by the module. To be compatible with the current
system running the cyclotron, the DAC voltage outputs must be bipolar. Each output is
connected to an op amp according to the schematic shown in Figure 8.1. This gives a
swing range of :l:Vref, which is :1:2.5V for this module. Each instruction must be sent
to the DAC serially on the SP1 bus as a 16-bit string of values where the least significant

12 bits correspond to the output voltage (Table 8.1). The most significant four bits of the

53

 

 

 

 

 

 

 

 

 

 

 

 

 

111 R2
——/vv\, ’VW—
+2.7v10 +5.5v Vt
REF vw
V0111
DAC_ +
0111_
MAXIM V-
MAX5742 111 =82
J_—

 

 

 

Figure 8.1. Bipolar DAC Configuration

Table 8.1. DAC Binary Output Chart.

 

DAC Contents Analog Output
111111111111 +V,,f(§%§%
1000 0000 0001 Hmfi)

 

 

 

 

 

 

 

 

 

 

100000000000 0
011111111111 — ”0%)
000000000001 — ref(é@'§)
000000000000 ‘Vref

 

instruction are the control bits and tell the DAC which outputs are going to be changed and
how to change them.

The DAC outputs are accessible on the connector on the back of the module and can be
connected to the existing phase control modules to display the phase for each station in the
cyclotron.

The supplemental hardware and interlock system is designed to monitor the status of
the overall system and is mostly intended to facilitate implementing the next phase of the

project by making it easier to add control elements to the phase meter.

54

CHAPTER 9

Phase Meter Performance

The purpose for developing this module was to replace the obsolete analog vector volt-
meters (Model HP 8508A) currently being used in the cyclotron. The specifications for the
existing voltmeter claim an absolute accuracy of :l:1° in the frequency range of lMHz to
100MHz[20]. T‘wo test setups were used to determine the accuracy of the newly constructed

phase meter.

9.1 Determining Module Channel Offsets

In the first test setup (Figure 9.1), a single signal generator (Rohde&Schwarz Model
1090.3000.13) is split using a Janel Laboratories 2-50MI-Iz four-way splitter (Model
PD7905) and run into the three RF input channels on the phase meter. Another signal
generator (PTS Model 250) is connected to the LO port. The vector voltmeter (HP8508A)
is connected in parallel with the module across channels 1 and 3 to take reference phase
information. Using the phase control on the Rohde&Schwarz signal generator, the phase
of the output RF is rotated with respect to the lOMHz reference signal from 0° to 360° in
10° steps. The channel 1 to channel 3 phase, OVM, is measured by the vector voltmeter and

compared to the channel 1 to channel 3 phase as measured by the module, 0m“), . The

55

Local Oscillator

 
 
   
 
 
 

 

Vector Vol‘tmeter

 

  
  
 

 

 

 

 

 

 

 

 

 

 
   

 

    

  
 

HP 8508A . PTS 250
AQ 8% /a 9 Signal Generator
° 0
'0 0 RF
“9"— Rohde&Schwarz
0
KO Splitter Signal Generator
;’cer Module

 

 

 

 
    

lOMHz Reference

Figure 9.1. Test Setup 1

static offset,005 , incurred by the filtering is calculated as,

905 = GVM - 9mm (9- 1)

for each reading. The average offset over all of the readings is calculated and subtracted
from the module readings. In general the average offset was between 14° and 17°, depend-
ing on the frequency of the input. The adjusted module measurements are subtracted from
the vector voltmeter measurements and plotted against the channel 1 phase reading on the
module (Figure 9.2).

The process is repeated for 9, 15, 21, 25 and 27MHz input signals. The results show
that, minus a fixed offset, the module readings deviate less than :t0.6° from the vector
voltmeter, well within the specified limits of the absolute accuracy. The largest deviations

occurred when channel 1 read 0°, 180° and 270°. This could be due to errors in the digital

56

Channel Offset (Split Single Source)

Deviation From Mean Offset
(Degrees)

 

O 60 1 20 180 240 300 360
Channel 1 Phase Measurement (Degrees)

 

 

 

+9MHZ +15MHZ +21MHZ +25MHZ +27MHZ

 

Figure 9.2. Measured Channel-to-Channel Offset

calculation as either I or Q become very close to zero and the argument of the inverse
tangent goes to either 0 or co. Since the channel 1 and channel 3 readings are offset by
approximately 15°, half of the digitization error could be attributed to each channel and
the large offset could be a result of the errors adding. This would suggest that 90° should
also be a problematic area, although the error appears to cancel itself out instead of adding
at 90°. However, since the errors are entirely within the specified absolute accuracy of the
vector voltmeter, there is no way to discern which module is giving the most accurate phase
reading. These results suggest that the phase meter module is at least as good as the vector

voltmeter.

57

Local Oscillator

 
  
  
 
 
 

 

Vector Voltmeter
HP 8508A

11ng

 

  
 
 

PTS 250

O 0
K Signal Generator

Rohde&Schwarz
Slgnal Generator

 

 

 

 

 

 

 

 

 

  
 

 

 
  

 

 

 

   

 

 

Phase Meter Module PTS 850

 
 

 

Signal Generator

 
 

lOMHz Reference

Figure 9.3. Test Setup 2

9.2 Determining Phase Accuarcy

Test setup 2 (Figure 9.3) adds another signal generator (PTS Model 250) connected to
the channel 3 RF input of the module and forgoes the splitter in favor of connecting the
Rohde&Scwarz signal generator directly to the channel 1 RF input. The vector voltmeter
is connected in parallel with the module to measure the phase between channels 1 and 3.
The signal generator connected to channel 1 is rotated through phases from 0° to 360°
using 10° steps, but this time the phase of the second signal generator is held constant. The
phase rotation of the signal generator is only accurate to approximately :i:0.6°, so a single
step can be between 94° and 106°. The vector voltmeter measurements of channel 1 to
channel 3 are taken as the baseline readings and are recorded and compared to the channel

1 to channel 3 measurements displayed by the module. The average offset of the module

58

Module Phase Measurment Accuracy

 

 

.v‘t

 

A 0.4
e
as) 0.3
:1—
_g"0.2
29.110
5.13% "'
_L“e 0
:2
0:18.01
VOQ -
2>-‘-"
Sum-0.2
'89

8 -0.3
2>

04

reading to the vector voltmeter is computed and subtracted from the module reading. The
adjusted reading is subtracted from the voltmeter reading and plotted to determine the phase
accuracy (Figure 9.4). As the results show, for input frequencies of 9, 18 and 27MHz, the
maximum deviation from the vector voltmeter reading is :l:0.3°. Once again, this is well

within the :1: 1 ° accuracy of the voltmeter and the source of the error cannot be ascertained.

9.3 Calculation Accuracy Dependence on Amplitude

The previous tests were run with the ADCs sampling waveforms at full scale, which is
the ideal situation when dealing with digitization errors. To determine the susceptibility of

the module’s phase and amplitude measurements to channel input amplitude variations, the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

60 1 20 180 240 300
Module Chl Phase Measurment (Degrees)

 

+27MI-Iz +18MI-Iz +9MHz

 

 

 

Figure 9.4. Module Phase Accuracy

59

360

test setup is left as it was in the previous test. The vector voltmeter phase is recorded and
compared to the module phase measurement as the channel 1 input amplitude is stepped
from +13dBm to -10dBm using -1dB steps. The channel 3 amplitude is set to +13dBm
and held constant. The digital attenuators are set to provide the ADCs with a full-scale
signal given +13dBm on the input. The specifications for the vector voltmeter require at
least -7dBm to guarantee the stated accuracy. The test is again run at 9, 18 and 27MHz.
Plotting the data vs. signal input amplitude (Figure 9.5) shows that to maintain an accuracy
of i0.5° requires the input amplitude be within 5dB of full-scale. To maintain an accuracy
of :l:1°, which is the absolute accuracy of the vector voltmeter, the amplitude can be as low
as l3dB down from full scale.

The amplitude is determined from the same samples as the phase, therefore a loss in ac-
curacy of the signal amplitude measurements is expected as well. The amplitude calculated
by the module is recorded as a function of the channel 1 input amplitude. The calculated
change in amplitude is compared to the actual amplitude change of the signal generator
and plotted (Figure 9.6). The amplitude calculations were less susceptible to the change
in input than the phase measurements, maintaining an error of around +/-0. 1dBm from an
input of +13dBm down to near +3dBm.

Taking i0.5° and :l:0.2dBm to be accurate measurements in both phase and ampli-
tude, an input can be up to 5dB down from full scale on the ADCs and still be considered
correct. The amplitude dependence tests were run at a fixed digital attenuator setting, how-
ever the digital attenuators can be always be changed to allow the internal amplification
chain to match the signal to the full scale of the ADCs as long as that signal is within the

specifications of the module. This will change the range of inputs that will maintain an

60

Module Phase Reading (Ch 1-
Ch3) - Vector Voltmeter Phase

Reading (Chl-Ch3)

Module Phase Accuracy v. Amplitude

L.b o _L
m-smocn-s'tnm

I
N

 

1'0
1.11

-1 0 -5 0 5 1 0 1 5
Signal Generator Amplitude (dB)

1
_s
U‘

 

 

 

+27MHz +18MHz +9MHz

 

Figure 9.5. Phase Accuracy Amplitude Dependence

acceptable level of accuracy. For instance, to run at OdBm, the digital attenuators can be
set so that OdBm on the input will still be full-scale at the ADCs and the range for accurate

measurements will shift to OdBm to -5dBm.

9.4 Performance Analysis

The results of these experiments show that the digital phase meter does meet the required
specifications set forth by the obsolete analog vector voltmeters and could be a viable a1-
temative for use in any RF system and specifically for the cyclotron. The prototype board
used to generate this data still has some interference issues that are known and are to be

addressed in future builds. It is worth noting that channel 2 had a very high amount of noise

61

Measured Amplitude Accuracy

 

d

 

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01

 

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2
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.61:
A10
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-10 -5 O

5 10

Signal Generator Amplitude (dB)

 

 

+27MHz +18MHZ +9MHZ

 

 

Figure 9.6. Calculated Amplitude Accuracy

due to its close proximity to the FPGA bypass capacitors and the LO channel. Because of
the excess interference, measurements were only taken on channels 1 and 3. Steps were
taken to isolate the RF channels in the latest board design; unfortunately it was not avail-

able for testing in time. Even given the interference issues present, this module could be

implemented without further modification as a high accuracy phase meter.

62

 

Table 9.1. Phase Meter Specifications

Voltage Input Range (dBm)
Frequency Input Range (MHz)
Phase Accuracy (Degrees)
(+13dBm Input Full-Scale)

Phase Resolution (Degrees)
Amplitude Accuracy (dBm)
(+13dBm Input Full Scale)

Amplitude Resolution (mV)

-7 to +33

9 to 31

:l:0.4 (+13dBm to +10dBm)
:l:.7 (+13dBm to +8dBm)
:l:l.2 (+13dBm to OdBm)
0.088

:l:0.1 (+13dBm to +3dBm)
i0.2 (+13dBm to -3dBm)
$0.5 (+13dBm to -10dBm)
0.5

*Channel crosstalk was calculated by connecting one input and terminating the rest.

The level of the signal was measured at that input (dBm) and the signal level at the in-

put of the ADC (dBm) for other inputs was subtracted from that level to determine the

interference.

63

Table 9.2. Channel to Channel Cross-Talk

CH1 +13dBm Input

CH2 +13dBm Input

CH3 +13dBm Input

LO +7.5dBm Input

CH 1 -CH2
CH1 -CH3
CH1-Ref

CH2-CH1
CH2-CH3
CH2-Ref

CH3-CH1
CH3-CH2
CH3-Ref

LO-CHl
LO-CH2
LO-CH3
LO-Ref

9MHz
80dB
80dB
80dB
9MHz
80dB
80dB
80dB
9MHz
80dB
80dB
80dB
59MHz
40dB
30dB
40dB
44dB

1 8MHz
80dB
80dB
80dB
l 8MHz
80dB
80dB
80dB
1 8MHz
80dB
80dB
80dB
68MHz
47dB
32dB
53dB
46dB

27MHz
80dB
80dB
80dB
27MHz
80dB
80dB
80dB
27MHz
80dB
80dB
80dB
77MHz
37dB
25dB
32dB
50dB

APPENDICES

65

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78

APPENDIX B

ZWorld C-Code

79

INariable Initialization
int initcount, config, setAtten, ADCcommand, ADCVal, get_IQ, PLL_Setup,

ReadIA, ReadIB, ReadQA, ReadQB, ReadlmA, ReadImB, ReadeA, ReadeB,
ReadIC, ReadQC, ReadImC, ReadeC, IA_Val_Read, IB_Val__Read, QA_Val_Read,
QB_Val_Read, ImA_Val_Read, ImB_Val_Read, QmA_Val_Read, QmB_Val__Read,

IC_Val_Read, QC_Val_Read, ImC_Val_Read, QmC_Val_Rmd, IRef_Val_Read,
QRef_Val_Read, lmRef_Val_Read, QmRef_Val_Read, ReadIRef, ReadQRef,
ReadlmRef, ReadeRef, filterVal;

float ReadlA_Mag, ReadIB_Mag, ReadIC_Mag, ReadQA_Mag, ReadQB_Mag, ReadQC_Mag,
ReadImA_Mag, ReadlmB_Mag, ReadlmC_Mag, ReadeA_Mag, ReadeB_Mag,
ReadeC__Mag, phaseA, IValA, QValA, magnitudeA, phaseB, IValB, QValB,
magnitudeB, phaseC, IV alC, QValC, magnitudeC, phaseAB, phaseAC, phaseBC,
divide_val, phaseRef, IValRef, QValRef, magnitudeRef, ReadIRef_Mag,
ReadQRef_Mag, ReadImRef_Mag, ReadeRef_Mag, offsetAB, OffsetAC;

ulong rcount, ncount, OutVal;

boo] writeSPlData, writelnit, writeRCount, writeNCount, writeConfig,
changeAtten, newAtten, fpgaBusy, writeADC, newOutVal, changeADC,
getting_IQ, firstRun, New_IQ, changeFilter, changeFilterZ, filtered;

”Telnet User Interface Declaration

xstn'ng DevStateStr {

"DI-00:. DO-OO: . DO-l6: .",

"DI-01:. DO-Ol: . DO-l7: .",

"DI-02: . DO-02: . DO-l8: .",

”DI-03:. DO-03: . DO-l9: .",

"DI-04: . DO-04: . DO-ZO: .",

"DI-05:. DO-OS: . DO-2]: .",

”DI-06:. DO-06: . D0-22: .",

"DI-07: . D0-07: . DO-23: .",

" Chl Phase: Degrees ",

"DI-08: . DO-08: . Chl Mag: Vpp ",
”DI-09: . DO—09: . Ch2 Phase: Degrees ",
"/INIT: . DO-IO: . Ch2 Mag: Vpp ",
”DONE: . DO-ll: . Ch3 Phase: Degrees ”,
”DI-12: . DO-12: . Ch3 Mag: Vpp ",
"Ref Phase: DO-I3: . Chl - Ch2: Degrees ”,
" Ref Mag: PROG: . Chl - Ch3: Degrees ",
" OffsetAB: DO-lS: . Ch2 - Ch3: Degrees ",
" OffsetAC: Dig. Atten: ",

};

//
// process a mum-character command from the diagnostic terminal/console
//
void ProcessStrCmd(char 'cmd, LinkProc ’lp)
{

char ‘ptr;

int i, chan, state, digState;

ulong mask, OutValLong;

float volts;

boo] valided;

char ‘msg, *temp, ‘cmdStr;

 

 

80

Stacthr();
msg = getBuf(90 + 90 + 90); temp = msg + 90; cmdStr = temp + 90;

strcpy(cmdStr, cmd); ptr = strtok(cmd, " ");
state = 0; valided == false;
strcpy(msg, ”cmd parser error”);

while (ptr AND (state != 999)) {

//se1ect parse the user input command
switch (state) {

case 0: // which command did they type?
if (strcmpi(ptr, "offsetab") = 0) {state = 101; break; }
if (strcmpi(ptr, "setadc”) = 0) {state = 102; break;}
if (strcmpi(ptr, "dig") = 0) { state = 103; break; }
if (strcmpi(ptr, ”init") = 0) {state = 104; break; }
if (strcmpi(ptr, "rcount") == 0) {state = 105; break; }
if (strcmpi(ptr, "ncount”) = 0) {state = 106; break; }
if (strcmpi(ptr, ”config") = 0) {state = 107; break; }
if (strcmpi(ptr, "setatten”) = 0) {state = 108; break;}
if (strcmpi(ptr, "Read") = 0) {state = 109; break;}
if (strcmpi(ptr, "filter”) = 0) {state = 110; break;}
if (strcmpi(ptr, "offsetac") = 0) {state = 111; break; }
sprintf(msg, "Unrecognized command: %s", ptr);
state = 999; break;

case 101: //change the offset value stored for channel 1 to channel 2
offsetAB = atof(ptr);
if ((offsetAB < -180) OR (offsetAB > 180)) {
sprintf(msg, ”Offset must be between -180 and 180 degrees");
state = 999; break; }
sprintf(msg, ”Offset has been set to °/od ", offsetAB);
valided = true; state = 999; break;

case 102: //set the ADC mode
ADCcommand = atoi(ptr);
if ((ADCcomrnand < 0) OR (ADCcommand > 3)) {
sprintf(msg, "%s is an Invalid ADC Setting", ptr); state = 999;
break; }
HeriticalSection;
writeSPIData = writeADC = true;
-critica18ection;
sprintf(msg, "Configuring the ADCs to test mode °/od", ADCcommand);
valided = true; state = 999; break;

case 103: // set state of a Digital output channel
chan = atoi(ptr);
if ((chan < 0) OR (chan > 23)) {
sprintf(msg, "Invalid DigOut chan #: %s", ptr); state = 999;
break; }
if (1 (ptr = strtok(NULL, " "))) break;
digState = atoi(ptr);
sprintf(msg, "Setting DigOut bit °/od to: %s",
chan, digState ? "0n" : "011“);
mask = 1L << chan;
++criticalSection;
if (digState) digitalOut |= mask; else digitalOut &= ~mask;
~cr1'tica18ection;
valided = true; state = 999; break;

81

case 104: ”configure initialization register

initcount = atoi(ptr);

if ((initcount < 0) OR (initcount > 7 )) {
sprintf(msg, "Initialization command out of valid range: %s", ptr);
state = 999; break;

}

++criticalSection;

writeSPIData = writelnit = true;

--criticalSection;

sprintf(msg, "Configuring Initilization Register");

valided = true; state = 999; break;

case 105: ”configure the R-Count Register

rcount = atoi(ptr);

if ((rcount < 1) OR (rcount > 1023)) {
sprintf(msg, "Divide value out of valid range: %s", ptr);
state = 999; break;

1

HeriticalSection;

writeSPIData = writeRCount = true;

-criticalSection;

sprintf(msg, "Setting the R-Count Register to %d", rcount);

valided = true; state = 999; break;

case 106: ”configure the N-Count Register

ncount = atoi(ptr);

if ((ncount < 1) OR (ncount > 1023)) {
sprintf(msg, "Multiply value out of valid range: %s", ptr);
state = 999; break;

1

HeriticalSection;

writeSPIData = writeNCount = true;

«criticalSection;

sprintf(msg, ”Setting the N-Count Register to %d", ncount);

valided = true; state = 999; break;

case 107: //configure the configuration register
config = atoi(ptr);
if ((config < 0) OR (config > 7)) {
sprintf(msg, "Configuration command out of valid range: %s", ptr);
state = 999; break;

++critica1Section;

writeSPIData = writeConfig = true;
"criticalSection;

sprintf(msg, "Configuring register");
valided = true; state = 999; break;

case 108: ”change the digital attenuator value
setAtten = atoi(ptr);
if ((setAtten < 5) OR (setAtten > 45)) {
sprintf(msg, ”Attenuation setting out of range: %s", ptr);
state = 999; break;

sprintf(msg, "Setting the digital attenuators to %s db", ptr);
HeriticalSection; newAtten = true; ~criticalSection;
valided = true; state = 999; break;

case 109: //set the DAC source to channel 14

ADCVal = atoi(ptr) - l;
if((ADCVal < 0) OR (ADCVal > 3)) {

82

sprintf(msg, "%d is not a valid ADC. Select ADC 1-4", ADCVal + 1);
state = 999; break; }
sprintf(msg, "Now reading from ADC %d", ADCVal + 1);
++criticalSection; changeADC = true; --critica1Section;
valided = true; state = 999; break;

case 110: //set the filter factor
filterVal = atoi(ptr);
if ((filterVal < 0) OR (filterVal > 1000)) {
sprintf(msg, "%d is not a valid filter value. Select 0—1000",
filterVal);
state = 999; break; }
sprintf(msg, "Setting Filter Value to %d", filterVal);
HeriticalSection; changeFilter = true; ”critica1Section;
valided = true; state = 999; break;

case 111: //set the channel offset between channels 1 and 3
offseMC = atoi(ptr);
if ((offsetAC < -180) OR (OffsetAC > 180)) {
sprintf(msg, ”Offset must be between -l80 and 180 degrees");
state = 999; break; }
sprintf(msg, "Offset has been set to %d ”, OffsetAC);
valided = true; state = 999; break;

}
if (ptr) ptr = strtok(NULL, " ");

}
strCmdState = false;

//-- what state were we in when we ran out of cmd string to parse? -—
switch (state) {

case 999: // msg supplied by cmd parser state machine
break;

default:
strcpy(msg, "Incomplete command");

if (! valided)
ProcessStrCdeommon(cmdStr, msg, 1p); // not valid dev cmd - check generic ones
else
if (*msg)
if (StreamDisp)
Shostg(msg);
else {
respShownTime = MS_TIMER - 5000;
DispStr(0,23, msg, true);
respShownTime = MS_T1MER;
}

freeTo(msg);
}

//
// Update data based on digital and analog input values and determine new
// values for the digital and analog outputs

//

// !!!!! WARNING !!!!!

//

// This function is called by the timer-interrupt driven function that reads

 

83

// and writes the Analog and Digital I/O values. It should be limited to
// processing current input values and updating output values that will become
// the active values on the next interrupt (currently, this interuupt occurs
// every 10ms, so this routine must take considerably less time than that to
// do EVERYTHING it needs to).
//
nodebug void UpdateDeviceStateO
{
ulong bit, secTime, mask, attenBits, OutValLong, ADCValLong, filterValLong;
int i, rate;
char bqu4];

 

divide_va1= 8192.0;
/Nerify the ADC chip select is high to prohibit SP1 loads on the ADCs
digitalOut = digitalOut | 0x008000; WriteDigOutputsO;

//on initial power up, configure the PLL and ADCs to run in default mode
if (firstRun)

{
switch (PLL_Setup)
{
case 0:
writeSPIData = writelnit = true; initcount = 1; PLL_Setup~H-; break;
case 1:
writeSPIData = writeConfig = true; config = 1; PLL_Setup~H; break;
case 2:
writeSPIData = writeRCount = true; rcount = 4; PLL_Setup++; break;
case 3: ‘
writeSPIData = writeNCount = true; ncount = 1; PLL_Setup+-+; break;
case 4:
writeSPIData = writeADC = true; ADCcommand = 0; firstRun = false; break;
default:
firstRun = false; break;

}
}

//if a new set of [IQ values have been read from the FPGA, calculate the phase
if (New_lQ)
{

//Convert the 14-bit integer values read in for I, Q, -I and -Q for each channel to

//floating point numbers between -1 and 1
ReadIA_Mag = ((float)Read1A/divide_val)-1;
ReadIB_Mag = ((float)ReadIB/divide_val)—1;
ReadIC_Mag = ((float)Read1C/divide_val)—1 ;
Realeef__Mag = ((float)ReadIRef7divide_val)—1;
ReadlmA_Mag = ((float)Read1mA/divide_va1)-1;
ReadImB_Mag = ((float)ReadlmB/divide_val)-1;
ReadlmC_Mag = ((float)ReadlmC/divide_va1)-1 ;
ReadlmRef_Mag = ((float)ReadlmRef/divide_val)— 1;
ReadQA_Mag = ((float)ReadQA/divide_va1)-1;
ReadQB_Mag = ((float)ReadQB/divide_val)-1;
ReadQC_Mag = ((float)ReadQC/divide__val)- 1;
ReadQRef_Mag = ((float)ReadQRef/divide_val)- 1;
ReadeA_Mag = ((float)ReadeA/divide_va1)- 1;
ReadeB_Mag = ((float)ReadeB/divide_val)—1;
ReadeC_Mag = ((float)ReadeC/divide_val)-1;
ReadeRef_Mag = ((float)ReadeRef/divide_val)— 1;

”Determine the l and Q values for each channel
lValA = (Read1A_Mag - ReadImA_Mag)/2;
QValA = (ReadQA_Mag - ReadeA_Mag)/2;
lValB = (ReadIB_Mag - ReadImB_Mag)/2;

84

QValB = (ReadQB_Mag - ReadeB_Mag)/2;
lValC = (ReadIC_Mag - ReadImC_Mag)/2;

QValC = (ReadQC_Mag - ReadeC_Mag)/2;
IValRef = (ReadIRef_Mag - ReadImRef_Mag)/2;
QValRef = (ReadQRef_Mag - ReadeRef_Mag)/2;

”Determine the magnitude of each channel
magnitudeA = sqrt(QValA"QVa1A + WalA’IValA);
magnitudeB = sqrt(QValB*QValB + IValB‘lValB);
magnitudeC = sqrt(QValC‘QValC + IValC‘lValC);
magnitudeRef = sqrt(QVa1Ret"QValRef + lValRef‘lValRef);

”calculate the phase for each channel, if there is no data being read from the ”F PGA, output 0
”Refemence Channel phase
if ((QValRef = 0 AND IValRef = 0) | (magnitudeRef < 0.01))

{
phaseRef = 0.0;
1

else

phaseRef = atan2(QVa1Ref,IVa1Ref)/PI"180.0;
if (phaseRef < 0) phaseRef = 360 + phaseRef;

1
”Channel 1 phase
if ((QValA = 0 AND IValA = 0) | (magnitudeA < 0.05))

{
phaseA = 0.0;
1

else

phaseA = atan2(QValA, IValA)'180.0/PI-phaseRef;
if (phaseA < 0) phaseA = 360 + phaseA;

1

”Channel 2 phase
if ((QValB = 0 AND lValB = 0) | (magnitudeB < 0.05))
{

phaseB = 0.0;
1

else

1
phaseB = atan2(QValB,IValB)‘180.0/PI-phaseRef;
if (phaseB < 0) phaseB = 360 + phaseB;

”channel 3 phase
if ((QValC = 0 AND lValC = 0) I (magnitudeC < 0.05))

{
phaseC = 0.0;
1

else

{
phaseC = atan2(QValC,lVa1C)"'180.0/PI-phaseRef;
if (phaseC < 0) phaseC = 360 + phaseC;

1

”calculate the phases between the sets of channels
”channel 1 to channel 2
if (phaseA = 0 OR phaseB = 0)
phaseAB = 0;
else
phaseAB = phaseA - phaseB - offsetAB;
”channel 1 to channel 3
if (phaseA = 0 OR phaseC = 0)

85

phaseAC = 0;
else
phaseAC = phaseA - phaseC - OffsetAC;
”channel 2 to channel 3
if (phaseB = 0 OR phaseC = 0)
phaseBC = 0;
else
phaseBC = phaseB - phaseC;
”convert the phase to —180 to 180 scale
if (phaseAB > 180) phaseAB = phaseAB - 360;
else if (phaseAB < -l80) phaseAB = 360 + phaseAB;

if (phaseAC > 180) phaseAC = phaseAC - 360;
else if (phaseAC < -180) phaseAC = 360 + phaseAC;

if (phaseBC > 180) phaseBC = phaseBC - 360;
else if (phaseBC < -180) phaseBC = 360 + phaseBC;

”allow new I/Q data to be collected
New__lQ = false;
1

//-- if we don't have "possesion" of the SP1 connection to the FPGA, then —-
//-- try to get it again (the ComLoop() process can take it away when --
//-- temporarily needed by a remote client) -
if (! fpgaLink) fpgaLink =
(ComLink ‘) SPlLink_(FPGA_SPIPort, CLK_1MHz, NORM_LOW_LATCH_RISE);

//-- use the SP1 link (If we currently own it) to talk to the FPGA -
if (writeSPIData AND fpgaLink) {
// Set up SP1 data for the High Speed ADCs
if (writeADC)

{
SPlLink_reconfig((SPILink ’)fpgaI.ink, CLK_1 MHz, NORM_HIGH_LATCH_FALL);
bquO] = 0er | (0x06 & (ADCcommand << 1));
buf[1] = 0x00;

1
”set up SP1 data for the PLL to set the Initialization Register
else if (writelnit)

{
buf[0] = 0x1f;
buf[1] = 0x80;
bquZ] = (0x70 & initcount << 4) | 0x83;

1
”set up SP1 data for the PLL to set the R-Count Register
else if (writeRCount)

1
bqu0] = 0x01;
bufll] = (char)(0x00f & rcount >> 6);
bufl2] = (char)(0x0fc & rcount << 2);

1
”set up SP1 data for the PLL to set the N—Count Register
else if (writeNCount)

{
butIO] = (char)(0x003 & ncount >> 8);
bqul] = (char)(0x0ff & ncount);
bqu2] = 0x01;

1
”set up SP1 data for the PLL to set the Configuration Register
else if (writeConfig)

{
buflO] = 0x1f;

86

bufll] = 0x80;
bufl2] = (0x70 & config << 4) | 0x82;

1

if (writeADC)

{

”toggle the chip select low on the ADCs to allow an SP1 load of 16 bits
digitalOut = digitalOut & 0xff7fff; WriteDigOutputsO;

”Write 2 bytes out the SP1 output to the ADCs on the falling edge of sclk
fpgaLink->write(fpgaLink, buf, 2);

”toggle the chip select high on the ADCs to prohibit SP1 loads to the ADCs
digitalOut = digitalOut I 0x008000; WriteDigOutputsO;

1

else

{

”Write 3 bytes out the SP1 output to the PLL on the rising edge of sclk
SPILink_reconfig((SPlLink ’)fpgaLink, CLK_1MHz, NORM_LOW_LATCH_RISE);
fpgaLink->write(fpgaLink, buf, 3);

”toggle the PLL Load Enable pin to load the internal initialization register
digitalOut = digitalOut l 0x010000; WriteDigOutputsO;

”Toggle the PLL Load Enable pin to prepare for the next register load
digitalOut = digitalOut & Oxfeffff; WriteDigOutputsO;

1

writelnit = writeRCount = writeNCount = writeConfig = writeSPIData = false;

writeADC = false; -

1
”as long as the F PGA is not being read for I/Q data, transmit data on the data bus to set the digital
”attenuators, the DAC source ADC and the filter factor value
if (!FPGA_Cmd_Read)

”send new digital attenuator values
if (newAtten AND !getting_lQ) {
attenBits = (ulong)setAtten - 5;
”set up the data on the bus
attenBits = ((attenBits << 14) & 0x300000) | ((attenBits << 8) & 0x003f00);
digitalOut = ((digitalOut & 0xcfc010) | attenBits) | 0x000000;
WriteDigOutputsO;
”toggle handshaking bit
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = true;
newAtten = false;

1
”change the DAC source ADC
else if (changeADC AND !getting_lQ)

”set up the data on the data bus
ADCValLong = ((ulong)ADCVal << 8) & 0x003100;
digitalOut = ((digitalOut & 0xcfc0f1) | ADCValLong) | 0x000001;
WriteDigOutputsO;

”toggle the handshaking bit
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = true;
changeADC = false;

1
”change the filter factor value
else if (changeFilter AND !getting_lQ)

{
”set up the first byte of data on the data bus
filterValLong = (((ulong)filterVal << 12) & 0x300000) |

87

(((ulong)filterVal << 6) & 0x003f00);
digitalOut = ((digitalOut & OxcchfO) | filterValLong) | 0x000006;
WriteDigOutputsO;
”toggle the handshaking bit
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
changeFilter = false; changeF i1ter2 = Hue;

1
”set up the last 2 bits of data on the data bus
else if (changeFilter2 AND !getting_lQ)

filterValLong = ((ulong)filterVa1 << 8) & 0x000300;
digitalOut = ((digitalOut & 0xcfc0f0) | filterValLong) | 0x000007;
WriteDigOutputsO;

”toggle the handshaking bit
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
changeFilterZ = false;
filtered = true;

1
”gather the ”Q values from the F PGA
else

getting_IQ = true;
switch (get_lQ)
1

case 0: ”Give the command to send out the 1 value from the FPGA
digitalOut = (digitalOut & OxfchfO) | 0x000002; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 1: ”Read the high byte ofl from the FPGA
ReadDigInputs();

IA_Val_Read = (inthigitalIn & 0x00ff) << 8;

”Give the command to send out the 1 value from the FPGA
digitalOut = (digitalOut & 0xffc010) | 0x000102; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 2: ”Read the low byte of 1 from the FPGa
ReadDigInputs();

ReadlA = (IA_Val_Read l (inthigitalIn & 0x00fi)) & 0x3 fff;

”Give the command to send out the Q value from the FPGA
digitalOut = (digitalOut & 0xffc0f0) | 0x000003; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd__Read = Hue; get_lQ++; break;

case 3: ”Read the high byte of Q from the FPGA
ReadDigInputs();

QA_Va1_Read = (int)(digitalln 8r. 0x00fi) << 8;
”Give the command to send out the Q value from the FPGA
digitalOut = (digitalOut & Oxfchfll) | 0x000103; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
F PGA_Cmd_Read = true; get_lQ++; break;
case 4: ”Read the low byte of Q from the FPGA
ReadDigInputs();
ReadQA = QA_Va1_Read | (inthigitalln & 0x00fl);
”Give the command to send out the -1 value from the FPGA
digitalOut = (digitalOut & 0xffc010) | 0x000004; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
F PGA_Cmd_Read = Hue; get_lQ++; break;
case 5: ”Read the high byte of -1 from the FPGA
ReadDigInpuN);
ImA__Val_Read = (int)(digitalln & 0x00ft) << 8;
”Give the command to send out the -1 value from the FPGA
digitalOut = (digitalOut & 0xffc0f0) | 0x000104; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

88

F PGA_Cmd_Read = Hue; get_lQ++; break;

case 6: ”Read the low bye of -1 from the FPGA
ReadDigInputs();

ReadImA =(1mA_Va1_Read | (inthigitalIn & 0xft)) & 0x3fff;
”Give the command to send out the -Q value from the F PGA

digitalOut = (digitalOut & 0xffc0fll) | 0x000005; WriteDigOutputsO;

digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

F PGA_Cmd_Read = Hue; get_lQ++; break;

case 7: ”Read the high byte of -Q from the FPGA

ReadDigInputs();
QmA_Va1_Read = (inthigitalIn & Oxft) << 8;

”Give the command to send out the -Q value from the FPGA
digitalOut = (digitalOut & 0xffc010) | 0x000105; WriteDigOutputsO;
digitalOut = digitalOut | 011080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 8: ”Read the low byte of -Q from the F PGA and reset the sequence

ReadDigInputs();
ReadeA = QmA_Va1_Read | (inthigitalln & Oxft);

”Give the command to send out the I value from the FPGA
digitalOut = (digitalOut & 0xffc0f0) | 0x000202; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 9: ”Read the high byte of I from the FPGA
ReadDigInputs();
lB_Val_Read = (inthigitalIn & 0x00ff) << 8;

”Give the command to send out the 1 value from the FPGA
digitalOut = (digitalOut & OxffCOfD) | 0x000302; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;
case 10: ”Read the low byte of 1 from the FPGa
ReadDigInputs();
ReadlB = (lB_Val_Read | (inthigitalln & 0x00ff)) & 0x3ffi‘;

”Give the command to send out the Q value from the FPGA
digitalOut = (digitalOut & 0xffc010) | 0x000203; WriteDigOutputsO;
digitalOut = digitalOut l 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 11: ”Read the high byte of Q from the FPGA
ReadDigInputs();
QB_Val_Read = (inthigitalln & 0x00ft) << 8;

”Give the command to send out the Q value from the FPGA

digitalOut = (digitalOut & Oxffcom) | 0x000303; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 12: ”Read the low byte of Q from the FPGA
ReadDigInputs();
ReadQB = QB_Val_Read | (inthigitalln & 0x00ft);

”Give the command to send out the -1 value from the FPGA

digitalOut = (digitalOut & 0xffc0fl)) | 0x000204; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
F PGA_Cmd_Read = Hue; get_lQ++; break;

case 13: ”Read the high byte of -I from the FPGA
ReadDigInputs();
lmB_Va1_Read = (inthigitalln & 0x00fi) << 8;

”Give the command to send out the -1 value from the F PGA

digitalOut = (digitalOut & OxffCOfO) | 0x000304; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
F PGA_Cmd_Read = Hue; get_lQ++; break;

case 14: ”Read the low bye of -1 from the F PGA
ReadDigInputs();
ReadImB = (lmB_Va1_Read | (inthigitalln & Oxft)) & 0x3fff;

”Give the command to send out the -Q value from the FPGA

digitalOut = (digitalOut & 0xffc010) | 0x000205; WriteDigOutputsO;

89

digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 15: ”Read the high byte of -Q from the FPGA
ReadDigInputs();
QmB_Va1_Read = (inthigitalln & Oxff) << 8;
”Give the command to send out the -Q value from the FPGA
digitalOut = (digitalOut & 0xffc010) | 0x000305; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

F PGA_Cmd_Read = Hue; get_lQ++; break;

case 16: ”Read the low byte of -Q from the FPGA and reset the sequence
ReadDigInputs();
ReadeB = QmB_Va1_Read | (inthigitalIn & Oxfl);

”Give the command to send out the I value from the F PGA
digitalOut = (digitalOut & 0xffc010) | 0x000402; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 17: ”Read the high byte of 1 from the FPGA

ReadDigInputs();
lC_Val_Read = (int)(digitalln & 0x00fi) << 8;

”Give the command to send out the 1 value from the F PGA
digitalOut = (digitalOut & 0xffc010) | 0x000502; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

F PGA_Cmd_Read = Hue; get_lQ++; break;

case 18: ”Read the low byte ofl from the FPGa

ReadDigInputs();

ReadIC = lC_Val_Read | (inthigitalln & 0x00ft);

”Give the command to send out the Q value from the FPGA
digitalOut = (digitalOut & Oxffcom) | 0x000403; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

FPGA_Cmd_Read = Hue; get_lQ++; break;

case 19: ”Read the high byte of Q from the FPGA

ReadDigInputs();

QC_Val_Read = (inthigitalIn & 0x00ff) << 8;

”Give the command to send out the Q value from the FPGA
digitalOut = (digitalOut & OxffCOfO) | 0x000503; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

F PGA_Cmd_Read = Hue; get_lQ++; break;

case 20: ”Read the low byte of Q from the FPGA

ReadDigInputs();

ReadQC = QC_Val_Read | (inthigitalln & 0x00fl);

”Give the command to send out the -1 value from the FPGA
digitalOut =(digita10ut & 0xfl'c010) | 071000404; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

F PGA__Cmd_Read = Hue; get_lQ++; break;

case 21: ”Read the high byte of -1 from the FPGA

ReadDigInputs();
lmC_Va1_Read = (inthigitalln & 0x00fi) << 8;

”Give the command to send out the -I value from the FPGA
digitalOut = (digitalOut & 0xffc010) l 0x000504; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 22: ”Read the low bye of -1 from the FPGA

ReadDigInputs();

ReadlmC = lmC_Va1_Read | (inthigitalln & Oxff);

”Give the command to send out the -Q value from the FPGA
digitalOut = (digitalOut 8r. 0xffc0fl)) l 0x000405; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 23: ”Read the high byte of -Q from the FPGA

ReadDigInputs();

QmC_Va1_Read = (inthigitalIn & Oxfi) << 8;

”Give the command to send out the -Q value from the FPGA

9O

digitalOut = (digitalOut & 0xffc010) | 0x000505; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 24: ”Read the low byte of -Q from the F PGA and reset the sequence
ReadDigInputs();
ReadeC = QmC_Va1_Read | (inthigitalIn & 0x11);

”Give the command to send out the I value from the FPGA
digitalOut = (digitalOut & OxfchfD) | 0x000802; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 25: ”Read the high byte of I from the FPGA

ReadDigInputs();

IRef__Val_Read = (int)(digitalln & 0x00ft) << 8;

”Give the command to send out the I value from the F PGA
digitalOut = (digitalOut & 0xffc010) | 0x000902; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

F PGA_Cmd_Read = Hue; get_lQ++; break;

case 26: ”Read the low byte of I from the FPGa
ReadDigInputs();
Realeef = IRef_Va1__Read | (inthigitalIn & 0x00f1);

”Give the command to send out the Q value from the FPGA
digitalOut = (digitalOut & 0xffc010) | 0x000803; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 27: ”Read the high byte of Q from the FPGA

ReadDigInputs();

QRef_Val_Read = (int)(digitalln & 0x00fi) << 8;

”Give the command to send out the Q value from the FPGA
digitalOut = (digitalOut & 0xffc0fll) | 0x000903; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

F PGA_Cmd_Read = Hue; get_lQ++; break;

case 28: ”Read the low byte of Q from the FPGA

ReadDigInputs();

ReadQRef = QRef_Val_Read | (inthigitalln & 0x00ff);

”Give the command to send out the -I value from the FPGA
digitalOut = (digitalOut & 0xffc010) | 0x000804; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_IQH; break;

case 29: ”Read the high byte of -I from the FPGA

ReadDigInputs();

ImRef_Val_Read = (inthigitalIn & 0x00ff) << 8;

”Give the command to send out the —I value from the FPGA
digitalOut = (digitalOut & 0xffc010) | 0x000904; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

F PGA_Cmd_Read = Hue; get_lQH; break;

case 30: ”Read the low bye of -I from the FPGA

ReadDigInputs();

ReadImRef = ImRef_Val_Read | (inthigitalIn & Oxft);

”Give the command to send out the -Q value from the F PGA
digitalOut = (digitalOut & 0xffc010) l 0x000805; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;

F PGA_Cmd_Read = Hue; get_lQ++; break;

case 31: ”Read the high byte of-Q from the FPGA

ReadDigInputs();

QmRef_Val_Read = (inthigitalIn & Oxfi) << 8;

”Give the command to send out the -Q value from the FPGA
digitalOut = (digitalOut & 0xffc010) | 0x000905; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ++; break;

case 32: ”Read the low byte of -Q from the FPGA and reset the sequence
ReadDigInputs();
ReadeRef = QmRef_Val_Read | (inthigitalIn & Oxff);

91

digitalOut = (digitalOut & 0xffc010) I 0x000008; WriteDigOutputsO;
digitalOut = digitalOut | 0x080000; WriteDigOutputsO;
FPGA_Cmd_Read = Hue; get_lQ = 0; getting_IQ = false; New_IQ = Hue;
break;

default: ”Reset to read I value
get_IQ = 0; break;
1
1

1
”wait for the FPGA to respond that it has finished processing a command
else if( digitalln & 0x1000)

F PGA_Cmd_Read = false;
digitalOut = digitalOut & 0x17 ffff; WriteDigOutputsO;
1

”-- blink activity LED @ 4 Hz if calibrating, 8 Hz for normal operation ---
if (calibrating) mask = 0x0080; else mask = 0x0040;
if (flashBad) mask = 0x0200; ” reduce to 1 Hz if a hardware problem
if (TICK_TIMER & mask)
ClearBits(digitalOut, ACT IVITY_LED);
else
SetBits(digitaIOut, ACTIVITY_LED);
1

92

APPENDIX C

Digital I/O usage for the ZWorld

93

Table C. 1. Telnet Interface Description.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name Description
DOOO-D003 Command Out
DOO4-D06 ExHa Output
D007 Activity LED
D008-DOO9, D020, D021 . Data Bus Out
DOlO-D013 ExHa Output
D014 FPGA Program Pin Connection
D015 Fast ADC Enable
D016 PLL Enable
D017 PROM Enable
D018 ExHa
D019 Handshaking Out
D022 Slow DAC Enable
D023 Slow ADC Enable
DIOO-DIO7 Data Bus In
D108-D11 l ExHa Input

 

94

 

APPENDIX D

Phase Meter Schematics

95

 

 

Power Connections

 

 

 

T
U

 

Mixer Stage
Input 1

 

 

 

 

Input 2 L" _ , rSignalflCQ 11de nlng

 

TI [‘11-

 

4
Input 3 f—[D .
. ? 5
Local Osc1llato?—[g
Referencb

 

‘ IE

1.2!]?

 

 

 

Digital Supply Voltage
Analog Supply Voltage

   
   

AGND

,, RC1117M33

E

RC1117M33

EE

MIC5209— 2 SBS

 

 

LM340— 5 0

 

 

 

 

E E

L15

Figure D. 1. System Overview

 

 

 

 

 

33pF

 

 

 

fPGA

      
 

hitcrlock ,

 

 

 

 

 

Interlocks

 

 

 

 

 

 

 

 

    
 

SIGN/ELLE ,

     

External Connections

ZWQRLD ,, W,

IZVIX‘

   
 
 

1'10 ()1 1M 1 WAT!

 

   
 
   
 
  
 

 

 

 

   

 

(15:
L16 0.111111;-
81111751 471111 +17dBF£TI\]/IS)
‘ 1.6V
+8.0dBm A1128 (
(0.58V RMS) PAT-9 ‘ _ (‘154
1 3 1 RlSl
10 W ~ I 103111
N 4 . 11.111111: 1152
'9dB 11411 Arm K5266750M725M751) Arm
\AIXER Mrf.” 111.1 , PAT-1
1p 2 W 3 1 1 IN OUT 2 1 1 j 3719110111;
, N V i .0 N " —1dBm max
+33dBm max pip} (0.2oov RMS)
(10V RMS) RIbO R162 ' —41dBm mm
mm» R159 R161 ' ? = -; (0.002v RMS)
574771777 -+1dBm max '
—7dBm mm (0.252V RMS)
(0.100V RMS) ~39dBm mln
(0.0025V RMS)
? -29dB ? ? {1.153
311
“Tm K526(1750M-2.5M-50 A'rrzs
PAT-”l 11112 7 . PAT-1
——1—1'\/v~‘—3——1-1' IN OUT WLFWELOHE>
N V i o -1dBm max
+33dBm max (2121:10B0rx 111114?)
(10V RMS) R164 R166 ' ‘
R163 R165 1 1 ? _ (0.002v RMS) ‘
1WD W 1 1dBm max T
—7dBm min R172 " ' (0.252V RMS)
(0.100v RMS) 535 °‘ " f39dBm min
1.0.0025V RMS)

 

 

.———— \2
R154 ‘ _\
10 ‘ '*

        
  

 

K5266-50M-25M-50 A1127
{$113717 W” PAT-1
N " —1dBm max
+33dBm max (9.1310501111911115)
(10V RMS) R168 R170 ‘
H a R167 m9 ‘7' ? (0.002v RMS)
_ 7P +1dBm max '
(EdisorBVmRrRIS) (géijsszv RMS) ' °
. - m mm
10.00st Ems) F1 gure D.2. Mlxer Stage
? '29dB ?
97

 

 

 

000000 : —5dB
000001 = —6dB

 
 
   
 
    

 

fit?

51

52

101000: -45dB 1213111 1111-11 :3
111110z-67dB >1

111111Z-68dB

   

1‘1 6
GALI-Sl

   
    
 

111

‘ 1 111 l
11RI’-A'1'46 1 0 111(F-AT4610

 

 

 

 

_ RFIN
”C111 , , so
SI
52 1 15
s3 RFOUT
34
SS
+17dBm max
+18dB (1-5VRMS) gooooaooaooamo‘
—23dBmmin ozzzzzzzzzzz::z: —28dBm
(0.0159v RMS) 90000130000070"? (0.0089V RMS)
oo'mlm‘m‘oln’oo ©|2|:|§ 2|: 2|
2;: -22.SdB to -2 5dB :5 -22.5dB to -2.5dB

+18dB —3dB +18dB -3013 +18dB -3dB

 

    

   
     
  

      
 
 

1.6V RMS 7 ‘
( +17dBni (‘88 (87 W“ (186 .VN C84 C83
‘ "111161711“P-| 3 1 i l 3 I ,1
0.01111‘ 0.01uF Arr!" 0.01uF Am" 0.01uF 0-0'“F Am
PAH PA —3 PAN
4.71111 1119 U17
GALl-S 1 emu—51
C80 C79 (78

? 0.01uF R116 —
IZOOHMIWATT

R118
120 OHM 1 WAIT

1 IZVDC

1 12V1)C

R127

120 OHM 1WA'1'1‘
C113

L14 0.01m”?

4.7uH

AT1'16
PA'HS

   

C115

0.01u17

 

-8d§ HEB
Figure D.3. Signal Conditioning (CH1 and L0)

98

 

l
l

 

 

thExtcnd thExtcnd <
[_1
<
D

SCLK

m

SE\

+711—

N:i_Cl: *NOTE: Placc Bypass Capacitors Near Each Digital Power Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 
 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1101. 11 01uF +3.3VDD
C3 C4
*NOTE: Place Bypass Capacitors Near Each Analog Power Pin ().luF 0.1uF
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Figure D.6. Xilinx XCZSISO FPGA

101

 

 

 

 

 

 

 

 

 

 

   
 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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102

 

 

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105

Figure D.10. Housekeeping Circuitry

 

 

BIBLIOGRAPHY

106

BIBLIOGRAPHY

[l] J. Vincent, L. Foth, A. McGilvra, J. Priller. The NSCL Control System Michigan State
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[2] T. Berenc, J. Brandon, J. Vincent. CCP Phase Regulation System R.F. Note #121,
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[3] A. Fox. Ask the Applications Engineer-30 Analog Dialogue 36 — 03,
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[4] L. R. Doolittle Plan for a 50MHz Analog Output Channel. LBNL, Berkeley Califor-
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[5] W. Zabolotny, K. Pozniak, R. Romaniuk, T. Czarski, I. Kudla, K. Kierzkowski, T.
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[6] C.Ziomek, P. Corredoura. Digital I/Q Demodulator: Stanford Linear Accelerator Cen-
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[7] M. J. O’Farrell. Low Level Radio Frequency Control of RIA Superconducting Cavities.
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[10] F. A. Losee. RF Systems, Components, and Circuits. Artech House, Inc, Norwood,
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[11] R.K. Feeney, D.R. Hertling. RF Circuit Design: Active Circuits Georgiea Institue of
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[13] Analog Devices. 200MHz Clock Generator PLL‘ Device Data Sheet,
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[14] Maxim Semiconductor. HFAN-01.0: Introduction to LVDS, PECL, and CML. Appli-
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107

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108