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DESIGN, IMPLEMENTATION AND TESTING OF A
HYBRID ALGORITHMIC ZA AID CONVERTER

presented by

Cheong Kun

has been accepted towards fulfillment
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DESIGN, IMPLEMENTATION AND TESTING OF A
HYBRID ALGORITHMIC 2A A/D CONVERTER

By

Cheong Kun

A THESIS

Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

MASTER OF SCIENCE
ELECTRICAL AND COMPUTER ENGINEERING

2005

ABSTRACT

DESIGN, IMPLEMENTATION AND TESTING OF A
HYBRID ALGORITHMIC 2A A/D CONVERTER

By

Cheong Kun

With the proliferation of miniaturized and autonomous sensors there has been an
ever-increasing demand for reconfigurable analog-to—digital converter (ADC)
architectures that can efficiently trade-off speed and resolution with its power
consumption. This work describes design, implementation and testing of a
dynamically reconfigurable ADC, which can be integrated as a smart front-end to
low-power sensor. The ADC utilizes the principle of extended data conversion to
achieve adaptation between a sigma—delta (2A) and an algorithmic converter. Based on
the input signal statistics, the adaptation can be directly parameterized and used for
dynamic reconfigurability to achieve an optimum trade-off. A pseudo—differential
ADC architecture has been implemented using switched-capacitor techniques and its
functionality has been validated through extensive simulations. A prototype of the
ADC has been fabricated using a standard 0.5um CMOS process and has been tested
to be fully functional. The ADC can achieve 8-bit in first-order 2A mode and 4-bit in

algorithmic 2A mode and consumes only 8.6uW during operation.

To my parents
Siu-Lai Chow and Yam-Chun Kun
and my fiancée

J in ing JIANG

iii

ACKNOWLEDGMENTS

I would like to start by giving my sincere appreciation to my advisor, Dr.
Andrew Mason. I have been very honored and privileged to have worked under his
supervision, and I have benefited a lot from his continuous guidance and from being
exposed to his excellent professionalism during my entire graduate study. I am really
moved by his kind understanding and generous efforts to help me rush out of school.
My earnest appreciation will go to my co-advisor, Dr. Shantanu Chakrabartty, who
gave me direction and encouragement throughout the work, without which it will be
impossible for me to accomplish so many. I will remember forever those days and
nights we worked together in the lab, and his discussions with me, which gave me a
glance of the brilliance as an analog circuit designer. I would like to thank Dr. Peixin
Zhong, for serving the thesis committee in his busy schedule, and also his FPGA
board which played a major role in the testing of my chip.

I sincerely thank Mr. Wilhelm Gattinger, former President and CEO of
Siemens Ltd. Hong Kong, Ms. Shih-ying Tan, Ms. Rebecca Tse, and all other
colleagues in Siemens AG, who supports my graduate study and providing me the
opportunity to start my career.

I would like to thank Mr. Jichun Zhang and Mr. Zhaohui Huang for valuable
discussions on analog circuit design techniques. I would like to thank Mr. Junwei
Zhou and Mr. J inwen Xi for their help on digital circuits and Verilog programming. I

would like to thank Mr. Amit Gore, for his assistance on setting up the test station. I

iv

would like to thank Mr. Chao Yang and Mr. Yue Huang and for helping me to
complete my thesis.

I would like to thank some good friends here in East Lansing, including Lucy
Lee, Timothy and Annabelle Chang, Yu Luo, Chuan Lu, Zhiwei Zeng, Jun Yuan,
Yuan Fan, Yin Zhan, Xin Liu and Na Yang. They helped me in so many ways,
especially during my hard time, that till now I couldn’t find a good way to express my
appreciation.

My special thanks will go to my fiancée, Jingjing Jiang, whose patience,
support, and impeccable understanding allowed me to write this thesis. Finally,
warmest thanks must go to my parents, Siu-lai Chow and Yam-chun Kun. Without

their love this work would never have come to existence.

TABLE OF CONTENTS

Chapters Page
1. Introduction .............................................................................. 1
1.1 Mixed-Signal Systems and Data Converters ............................... 2

1 .1 .l Mixed-Signal Systems ............................................. 2

1.1.2 ADCs and DACs .................................................. 3

1.1.3 ADC Parameters and ADC Types .............................. 4

1.2 Motivation: Dynamic Reconfigurable ADC 5

1.3 Direction: Reconfigurable Architecture ...................................... 8

1.3.1 Selection of ADC Architectures .................................. 8

1.3.2 Review of Adaptive / Reconfigurable Techniques ............ 9

1.4 Conclusion ....................................................................... ll

2. Hybrid Algorithmic 2A ADC .............. . ........................................... 15
2.1 Review of Extended Counting Technique ................................. 16

2.2 Introduction to Hybrid Algorithmic 2A ................................... 21

2.2.1 Architecture and Operation ..................................... 21

2.2.2 Multiple Extended Conversion ................................ 24

2.2.3 Hybrid Algorithmic 21A ........................................ 25

2.2.4 Summary ......................................................... 29

2.3 Analysis of Hybrid Algorithmic 2A Architecture ....................... 30

2.3. 1 Behavioral Verification ......................................... 30

2.3.2 Resolution/Speed Configurability .............................. 31

2.3.3 Benefits in Energy Saving ...................................... 33

3. Circuit Implementation ............................................................... 38
3.1 Circuit Design and Simulation ............................................. 40

3.1.1 Cascoded Inverter Amplifier ................................... 40

3.1 .2 Integrator ......................................................... 42

3.1 .3 Comparator ...................................................... 45

3.1.4 Sample and Hold ................................................ 49

3.1.5 l-bit DAC (Analog MUX) ..................................... 53

3.1.6 Whole System Schematic and Simulation ................... 54

3.2 Circuit Layout ................................................................ 56

3.2.1 Floor Flaming .................................................... 56

3.2.2 Layout of the Basic Components ............................. 56

3.2.3 Layout of the Sub-Blocks ...................................... 57

3.2.4 Layout of the Whole Chip ...................................... 57

vi

4. Testing & Results ...................................................................... 59

4.1 Fabricated Chip ............................................................... 59
4.2 Test Setup ...................................................................... 60
4.3 Testing of Circuit Components .............................................. 62
4.3.1 Testing of the Op Amp Voltage Followers ................... 62
4.3.2 Testing for the Cascoded Inverter Amplifiers 63
4.3.3 Testing for the Integrator ......................................... 64
4.3.4 Testing for the Comparator ..................................... 66
4.3.5 Testing for the Sample and Hold (SaH) ....................... 67
4.4 System Testing ................................................................. 69
4.4.1 1st-order 2A operation .......................................... 69

4.4.2 Hybrid Algorithmic 2A operation 72

5. Conclusions ............................................................................. 76
5.1 Achievements ................................................................. 76
5.2 Possible Improvements ....................................................... 77

vii

LIST OF TABLES

Table Page
2.1 Comparison of Algorithmic, First-order 2A, and Hybrid Algorithmic 2A

architectures ........................................................................... 28
3.1 Approximate Process Data for 0.5 pm CMOS process ........................... 39
3.2 Operation of the inverter based integrator ......................................... 43
3.3 Operation of the inverter based comparator ....................................... 46
3.4 Operation of the differential comparator .......................................... 47
3.5 Operation of the simple sample and hold ......................................... 50
3.6 Operation of the sample and hold with CDS technique ......................... 51

viii

Figure

1.1

1.2

1.3

1.4

1.5

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

3.1

3.2

3.3

LIST OF FIGURES

Page

Modern mixed-signal system converts analog signals to digital domain in

order to utilize the powerful DSP technology ..................................... 3
Blocks of analog-to-digital interface ............................................... 4
Blocks of digital-to-analog interface ............................................... 4
Typical signals from a micro gas chromatography (pGC) system ............. 6

Dynamic reconfigurable ADC in multi-channel neural probes applications. 7
Extended Counting ADC in counting conversion: resettable lst-order 2A 16
Extended Counting ADC in extended conversion: algorithmic mode ......... 18

Proposed Hybrid Algorithmic 2A ADC architecture that adds a sample and
hold component and an analog MUX to a conventional lst-order 2A

architecture ........................................................................... 2 1
Behavioral simulation of the Hybrid Algorithmic 2A conversion ............ 30
Behavioral simulation of the Hybrid Algorithmic 2A conversion 31

Different configurations for a 12-bit Hybrid Algorithmic 2A conversion 32

The ADC can be reconfigured to different speed vs. resolution combinations
by varying M and L .................................................................. 33

Normalized energy consumption for the Hybrid Algorithmic 2A architecture

at different configurations ........................................................... 36
Schematic for the cascoded inverter amplifier .................................... 4O
Simulation results for the cascoded inverter amplifier ........................... 41
Schematic of the inverter based switched-capacitor integrator ................. 42

ix

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3.16

3.17

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

Operation of the inverter—based integrator: integrating 200mV each clock 44

Simulation result shows the linearity of the inverter-based integrator ......... 44
Schematic of a basic switched-capacitor comparator ............................. 45
Schematic of a differential comparator ............................................ 46
Simulation waveforms of the differential comparator ........................... 48

Simulation testing the resolution and offset of the differential comparator 49
Schematic of the simple sample and hold circuit ................................. 49
Simulation waveforms to verify the function of the simple sample and hold.50
Schematic of the sample and hold with CDS technique ........................ 51
Operation of the sample and hold with CDS technique ......................... 52
Schematic of the Sample and Hold with Time-Shifted CDS technique ....... 52
Operation of the Sample and Hold with Time-Shifted CDS technique ....... 53
Schematic of the 1-bit DAC (analog MUX) ...................................... 54

Simulation waveforms of the Hybrid Algorithmic EA ADC: L=16, M=2 55

Fabricated Hybrid Algorithmic EA ADC v1.0chip photo ....................... 59
Setup of testing the A/D converter chip ........................................... 60
Photo of the testing station ready to test the chip ................................ 61
Waveform of testing the op amp voltage follower ............................... 63
Waveform of testing the cascoded inverting amplifier .......................... 64
Clock for testing the integrator ...................................................... 65
Waveform when testing the integrator 65
Clocks for testing the comparator .................................................. 66

4.9

4.10

4.11

4.12

4.13

4.14

4.15

4.16

Waveform testing the comparator .................................................. 67

Clocks for testing the sample and hold ............................................ 68
Waveform when testing the sample and hold .................................... 68
Clocks for lst-order 2A operation ................................................. 69
Waveform of lst-order 2A operation .............................................. 70
The counter value displayed in the LED at the end of each conversion ...... 70
Clocks for Hybrid Algorithmic 2A operation .................................... 72
Testing waveform of Hybrid Algorithmic 2A operation ........................ 73

xi

Chapter 1
Introduction

A/D converters are one of the most important elements in modern mixed-signal
systems. In many sensor systems, there is tremendous value to dynamically controlling
the resolution vs. speed tradeoff to optimize the quality of measurement data and assist in
power management.

This chapter first describes the importance of ADC in modern mixed-signal systems.
Then the motivation of this work is introduced: to dynamically controlling the resolution
vs. speed tradeoff to optimize the quality ’of measurement data and assist in power
management. Next, previous research on reconfigurable ADC architectures are reviewed
and a possible solution is given: to design a reconfigurable ADC that can reconfigure

between Algorithmic and Sigma-Delta (2A) architectures.

1.1 Mixed-Signal Systems and Data Converters
1.1.1 Mixed-Signal Systems

The world is becoming more digital everyday: Cell phone (digital communication),
MP3 (digital audio), digital camera (digital image), DVD (digital video), HDTV, to name
just a few. Benefits from the fast development of digital signal processing (DSP)
technology during the past decades and Moore's law driven very large scale integration
(VLSI) technology, digital system often exhibit lower sensitivity to noise and higher
accuracy, offer more robustness and better consistency, allow easier design and test
automation, and so on.

However, our real world is analog. All, naturally occurring signals in the physical
world, such as sound waves, visual images, temperature, pressure, vibrations, and so on,
are analog. Furthermore, human beings perceive and retain information in analog form [1].
For an electronic system to interact with the real world, as well as to utilize the powerfiil
DSP technology and computing capability, data acquisition, conversion, and
reconstruction circuits must be used as interface of digital processors with the analog
world.

Modern electronic systems often convert analog signals to digital signals, perform the
processing in digital domain, and convert the result back to analog signals, as illustrated
in Figure 1.1. Such kinds of systems are called mixed-signal systems. Examples include
wireless communication (GSM mobile phones, CDMA), measuring
equipments/instruments (Medical & CCD imaging, digital oscilloscope), consumer

electronics (HDTV, digital cameras), and so on.

 
 
    

Voice. Image,

 

 

 

 

 

 

 

 

., « Heat, Pressure, _ W . ,
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6 O ? . .
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by. ’s'J', [1"; _
Analog Signal . . . .
Digital Signal Analog Signal
(v°”°9°' curn'") ...ororroro...

 

 

 

Figure 1.1. Modern mixed-signal system converts analog signals to digital domain in
order to utilize the powerful DSP technology.

1.1.2 ADCs and DACs

Among the components in an analog interface, analog-to-digital (A/D) converters
(ADCs) and digital-to-analog (D/A) converters (DACs), are key components since they
generally define the resolution and bandwidth of the overall system[1][2][3].

The analog-to-digital interface converts a continuous-time, continuous-amplitude
analog input to a discrete-time, discrete-amplitude digital signal. Shown in Figure 1.2 is
this interface in more detail. First, an analog low-pass filter limits the input signal
bandwidth so that subsequent sampling does not “alias” any unwanted noise or signal
components into the actual signal band. Next, the filer output is “sampled” so as to
produce a discrete-time signal. The amplitude of this waveform is then “quantized,” i.e.,
approximated with a level from a set of fixed reference, thus generating a

discrete-amplitude signal. Finally, a digital representation of that level is established at

the output [1].

__.Low-Paee I: I Sampling Ii I E
Fllter Circuit Ouanliar

’fs

 

‘90
did

 

 

 

 

 

 

 

Figure 1.2. Blocks of analog-to-digital interface.

The digital-to-analog interface converts a discrete-time, discrete-amplitude digital

input to a continuous-time, continuous-amplitude analog output. This interface is depicted

in more detail in Figure 1.3.

‘ [£me 0......” H '""°'” Straw” p.

Figure 1.3. Blocks of digital-to-analog interface.

 

 

 

 

 

 

1.1.3 ADC Parameters and ADC Types

The most fundamental parameters for the ADC and DAC are: resolution, speed and
power consumption.

0 Resolution, normally expressed in number of bits, describes how accurately the

ADC or DAC can represent their input analog or digital signals. For example, an

8-bit ADC can distinguish the difference equal to 1/256 of reference voltage.

0 Speed, often equivalent as Sampling Rate and expressed in Sample-per- second
(Sps), describes how fast is the ADCs or DAC conversion. For example, a 1M
Sps ADC can finish one conversion in 1118.

0 Power Consumption, expressed in Watt, describes how much power the ADCs or
DACs consume when running. Sometimes we care more about Energy
Consumption for each conversion, which is the product of power consumption

and conversion time and expressed in J, J-per-conversion, or J-per-bit.

Other ADC parameters include: static parameters: error, gain error, differential
non-linearity error (DNL), and integral non-linearity error (INL); dynamic parameters:
signal-to-noise ratio (SNR), signal-to-noise and distortion ratio (SINAD), effective
number of bits (ENOB), total harmonic distortion (THD), and spurious-free dynamic
range (SF DR). They are explained in detail in Appendix A.

A/D converters’ performance is generally determined by their structure. A/D
converters can be classified into two general groups: Nyquist-rate and oversampled.
Nyquist-rate A/D converters can be further divided into several subclasses. Refer to

Appendix B for ADC architectures.

1.2 Motivation: Dynamic Reconfigurable ADC

With the proliferation of miniaturized and autonomous sensors there has been an
ever—increasing demand for reconfigurable analog-to-digital converter (ADC)
architectures that can efficiently trade-off speed and resolution with its power
consumption.

For example, in wireless sensor networks [6] environmental monitoring systems or
‘listening’ devices (acoustic, vibration, etc.), there are opportunity to minimize power
consumption when the incoming signal is inactive. Figure 1.4 shows a typical output
waveform from a micro gas chromatography (uGC) system[7]. The arriving time of the
peak identifies the molecular species present, and the size of the response indicates the
amount of gas involved. It can been seen that the signal is under a threshold during the
most of time, which allows to monitor the signal with low resolution during the inactive

period to save power, and adjust to high-resolution mode when the peaks arrive.
11 1213

no 113113 11 LLL 1M

.1 CL

i. UJJUJLJJL

..... WcéN
CCN

 

 

I I I I T
100 200 300 400 500
Time (a)

Figure 1.4. Typical signals from a micro gas chromatography (uGC) system.

In some other sensor systems, it is desirable to quickly scan sensor arrays before

measuring a specific element with high resolution For example, in multi-channel neural
probes [8] it is desirable to quickly scan many channels at low resolution, as shown in
Figure 1.5(a), and then sample signals at high resolution from the most active channels, as

shown in Figure 1.5(b).

quickly scanning

naI in active 3' nals
for active signals yz g :9

with high resolution

M ' -.‘
JM ADC 8b—10b M7 _1 ADC fl2b-16b
W —— ' ~ :

low resolution high resolution —-

II - fast conversion If - I low conversion
M t :
W

(a) (D)

W

 

 

 

 

 

 

 

 

Figure 1.5. Dynamic reconfigurable ADC in multi-channel neural probes applications.

To meet the demands described above, the goal of this thesis is to design an A/D with
the following specifications:

0 Resolution: configurable, moderate to high, 10-bit ~l 6-bit;

' Speed: configurable, low to moderate; 10 kHz ~ 100 kHz;

0 Power: As low as possible;

0 Dynamic reconfigurability of the resolution! speed trade-off to assist sensor

applications and power management.

1.3 Direction: Reconfigurable Architecture
1.3.1 Selection of ADC Architectures

For low-power ADCs, the most commonly used architectures are: Successive
Approximation Register (SAR) architecture [9], Integrating architecture [10], Algorithmic
architecture [11][12], and Sigma-Delta (2A) architecture[13]-[21]. They achieve low
power consumption because of their simplicity in circuits [Appendix B].

Algorithmic/SAR ADCs normally find application where the input signal ranges at
100 kHz — 1 MHz and resolution requirement is not critical [9][10][11][12]. Due to the
limitations of component mismatch, it is very hard to achieve a resolution higher than 10
bits.

On the other hand, 2A ADCs can easily achieve a resolution higher than 16-bit using
over-sampling and noise shaping techniques [13]-[21]. However, because of the large
number of clocking cycles required for each conversion, 2A architecture are generally
used for low speed applications (less than 100 kHz).

Although each of these A/D architectures is well suited to achieve one of the design
goals of this thesis, neither can meet all the requirements. This thesis seeks to explore
the feasibility of developing a circuit that combines the benefits of each single
architecture into a hybrid structure that achieves all design specifications and can be

dynamically reconfigured between the architectures.

1.3.2 Review of Adaptive / Reconfigurable Techniques

The variation of ADC resolution/speed can be accomplished by:

(l) Clocking reconfiguration: adjusting the clock frequency or oversampling ratio
(OSR). This technique can be applied to any ADC architecture to increase the speed of
ADC. Particularly in BA architecture, increasing the OSR could increase the resolution.

(2) Circuit parameter reconfiguration: varying circuit parameters, such as size of
capacitors, biasing currents of the opamps, and so on.

(3) Architecture reconfiguration: reconfiguring the architecture between architectures.
This reconfiguration could possible enjoy the advantage of both architectures and provide
more range of control than adjusting clocking or circuit parameters within a single
architecture.

Previous research in reconfigurable ADC architectures focus mainly on the pipelined
architecture[Appendix B], where reconfigurable networks similar to those in Field
Programmable Gate Arrays (FPGA) are used to scale pipeline stage depth or re-group the
pipeline stages to optimize resolution and/or speed of a pipelined ADC [22][23][24].
However, pipelined architectures are tailored to high speed (lM-lOOMHz) applications,
and their circuit complexity is not well suited to low-power sensor applications where
input signal range rarely exceeds IOOkHz.

In 2001, K. Gulati and H.-S. Lee proposed a low-power reconfigurable ADC that can
reconfigure its architecture between pipelined and 2A modes [25]. This ADC can achieve
a wide range of bandwidth and resolution with adaptive power consumption. However,

due to the intrinsic difference between the pipelined and 2A architectures, the system

requires very complicated circuits in order to realize the reconfigurability.

To achieve the goals of this thesis, another approach is needed. Recall that the
algorithmic ADC has approximately 8-bit to 12-bit resolution at ~100k Hz while the 2A
can easily achieve 12-bit to l6-bit resolution at ~10k Hz. A combination of these two
would be well suited to sensor applications. An important observation is that the
algorithmic ADC and 2A shares very similar analog components: a multiply-by-two (for
algorithmic) or an integrator (for EA) that can be easily be implemented using the same
core in switch-capacitor circuits; a comparator; and a 1-bit DAC. This suggests there
should be a smart way to reconfigure between these two architectures. We will show in
Chapter 2 that, by using extended counting technique, we can realize the reconfigrability

between algorithmic and 2A architectures and enjoy the benefits of both architectures.

10

1.4 Conclusion

We will build an AfD converter for implantable or wireless sensor applications that

will benefit from the dynamic reconfiguration of the resolution/speed tradeoff.

Summary of requirements:
0 Resolution: configurable, moderate to high, 10-bit ~16-bit;
' Speed: configurable, low to moderate; 10 kHz ~ 100 kHz;
0 Power: As low as possible;
0 Dynamic reconfigurability of the resolution/speed trade-off to assist sensor

applications and power management.

Possible Solution:

Reconfigure between Algorithmic architecture and EA architecture

11

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architecture for UTRA-TDD system," Electronics Letters, Vol. 38, pp. 1732 - 1733,
Dec. 2002

Hui Liu, and M. Hassoun, "A 9-b 40-MSample/s reconfigurable pipeline
analog-to-digital converter," IEEE Trans. on Circuits and Systems 11: Analog and
Digital Signal Processing, Vol. 49, pp. 449 - 456, July 2002

13

[25] K. Gulati and H.-S. Lee, “A low-power reconfigurable analog-to-digital converter,” in
Proc. ISSCC, 2001, pp. 54—55.

14

Chapter 2
Hybrid Algorithmic 2A ADC

Chapter 1 demonstrated that, for wireless and implantable sensor application, there is
tremendous value to an A/D converter with dynamic speed vs. resolution
reconfigurability. The SA and algorithmic ADC architectures are candidates for sensor
applications because of their high/moderate resolution and moderate/fast conversion
speed, and their simplicity in circuit design compared to other ADC architectures.

This chapter first reviews the extended counting technique. Then the Hybrid
Algorithmic 2A ADC, developed through this thesis research, is introduced to meet
reconfigurability and low-power requirements. Finally, behavioral analysis of system

reconfigurability, energy-saving benefits and design tradeoffs are presented.

15

2.1 Review of Extended Counting Technique

In 2001 P. Rombouts, W. D. Wilde and L. Weyten introduced the extended counting
technique, which is a compromise between the high accurate but relatively low speed of
22A modulation and higher speed but lower accuracy of algorithmic A/D conversion [1].
The converter successively operates first as a first-order 2A modulator to convert the
most significant bits, and then the same hardware is used as an algorithmic converter to
convert the remaining least significant bits.

For one A/D conversion, the converter first operates as a resettable ISt-order 2A

modulator, as shown in Figure 2.1. V [ i] , D [ i] and Vfb [ i] are respectively the

——’ Vres

reset

. COMPARATOR
V [1]

D J' DU] DIGITAL Bu]
INTEGRATOR COUNTER

( 1-BIT DAC ) +Vref
...-III III‘
Vfbli] .0 g

—O—+--'{
O
O
...... IIIII
LO-Vref

Figure 2.1. Extended Counting ADC in counting conversion: resettable ls'-order 2A.

 

 

  

 

 

 

C
III I.

outputs of the integrator, comparator and the 1-bit DAC . The integrator integrates the
difference of its two inputs Vin and Vfb [ i] :

V[i+1]=V[i]+(Vin-Vfb[i]). (2.1-l)
The comparator compares V [ i] with respect to analog ground and generates the digital
code D [ 1]:

DD] = {—1, if V[i] > Agnd (2+2)

1, ifV[i]SAgnd.

16

The l-bit DAC takes the output of comparator D [ i] and convert it back to +Vref if D [ i]
is +1 or —Vref ifD[i] is -1:

+Vref, ifD[i]= 1

WW] 2 {-Vref, if D[i] = —1

}= D[i]-Vref. (2.1-3)

Combining Equation 2.1-1 to 2.1-3 provides the transfer function of the lst-order 2A
modulator:
V[i]:V[i—1]+(Vin—D[i—l]-Vref). (2.1-4)

If the converter is reset before every conversion, thus V[O] = 0 and D[O] = 0, then

V[1]= Vin,
V[2] = V[l] + (Vin -D[l] - Vref) = 2 - Vin - D[1]- Vref
V[3] = V[2] + (Vin — D[Z] - Vref) = 3 - Vin — (D[l] + D[2]) - Vref

If the recursion continues for L steps, then:

L—l
V[L]=L-Vin— z D[i]-Vref (2.1-5)
i=1

It can be proven that V[i] remains bounded [1]:
—2-Vref S V[i]S 2-Vref (2.1-6)
One additional step is performed to obtain the residue voltage for extended

conversion. In this step, the input is Vagnd instead of Vin. Thus,

L
Vres = V[L]—D[L] - Vref = L - Vin - z D[i]-Vref (2.1-7)
i=1

This mode is called the “counting conversion.” It can be proven that Vres is more
restrictively bounded [1]:

—Vref S V[i] S Vref (2.1-8)

The input Vin can be reconstructed by:

17

L
X D[i] - Vref + Vres

Vrn=i=1 2.1-9
L ( )

 

If Vres is known, then Vin can be perfectly reconstructed (assuming there are no errors in
D[i]). Furthermore, Vres will be divided by L, which means, the error when we measure
Vres will be suppressed by the number of clocks in the counting conversion phase. Thus,
a coarse but faster algorithmic A/D conversion can be used to measure the Vres and
improve the resolution of the A/D conversion while does not cost too much additional
clock steps. This mode is called the “extended conversion”, which is shown in Figure 2.2.

SAM PLE/HOLD
COM PARATOR

     
 

Vres—DO V [i ]

 

if

{-0 +Vref
......I III

A
g v

. ‘
O
’0'... III.
LO -Vrof

( 1-BIT DAC )
Figure 2.2. Extended Counting ADC in extended conversion: algorithmic mode.

 

 

...-ll.-

During the extended conversion, the same hardware is used to convert the least
significant bits. The integrator is configured as the X2 multiplier and also sample and
hold (SaH). The SaH samples Vres in the first step of extended conversion,

V[L+1]= Vres (2.1-10)
and then converts the Vres in standard algorithmic conversion:
V[i+1]=2-V[i]-D[i]-Vref fori>L (2.1-11)

After M steps,

18

M _ .
V[L+M+1]=2M-Vres— 2 2M J-D[L+j]-Vref
1:1

From Equation 2.1-10 to 2.1-11, Vres can be measured as:

M _.
Vresz Z 2 J-D[L+j]-Vref

J' =1
Combine Equation 2.1-9 and 2.1-13,

L M _-
z D[i]+ z 2 J-D[L+j]

Vin=l:1 J

 

=1
-Vre
L f

(2.1-12)

(2.1-13)

(2.1-14)

The resolution of extended conversion R and the required number of clock cycles for one

conversion N is given by:

R=Iog2(L)+M
N=L+M+l

(2-15)

Where L is the number of clocks in counting conversion and M is the number of clocks in

extended conversion.

The key ideas behind this extended counting technique are:

I. An algorithmic conversion follows a 1‘”-order 2A conversion to extend the

resolution.

11. The error during the second phase will be suppressed by the number of clock

cycles L in the first phase. i.e., the oversampling in the first phase helps the

resolution of the second phase too. This is why the second phase could be a

coarse conversion. If the second phase is not an algorithmic conversion, but an

SAR or other conversion type, it will also work. The algorithmic type is chosen

due to the similarity of hardware components between ls‘-order 2A and

19

algorithmic converters; both have a comparator, a 1-bit DAC, a subtractor, and
an integrator/x2 multiplier, allowing the same hardware to be reused.

An understanding of the key ideas of the extended counting technique leads to some
interesting questions posed below. Exploring these questions and the subsequent
expansion of the extended counting technique to a reconfigurable A/D platform: represent
the initial innovation of this thesis:

0 What if a third phase is added?
0 What if the second phase is not algorithmic but remains 2A?
0 Will the oversampling in the first and second conversion help to suppress the

error made in the third conversion or not?

20

2.2 Introduction to Hybrid Algorithmic 2A
2.2.1 Architecture and Operation

Consider the architecture shown in Figure 2.3. A Sample and Hold (SaH) component
and an analog MUX is added to the conventional first-order EA architecture. By
iteratively sample and hold the residue voltage Vres from the integrator, and switch the
analog MUX to feed the Vres to the input of the first-order 2A, multiple extended

conversions can be achieved.

 

    

- {09".V€"9°E‘a.' 1.sl.-<2rqer.2.A ...............................
Proposed‘Hybn'd Algorithmic 2A . , " I
I.‘

Figure 2.3. Proposed Hybrid Algorithmic 2A ADC architecture that adds a sample and
hold component and an analog MUX to a conventional lst-order 2A architecture.

A three phase extended conversion case is analyzed below to explain the operation of
the proposed hybrid algorithmic 2A ADC architecture. During the first phase, the MUX
chooses Vin, the system performs L1 clock cycles of the first-order 2A counting
conversion, and the residue Vm, is generated and held by the SaH. As a result of the

first phase conversion:

L1
2 D[i]-Vref +Vres1

V'n = i=1— 2.2-1
1 L1 ( )

21

During the second phase, the MUX switches to the output of SAH, which should ideally
equal to Vres]. The system performs L2 clock cycles of first-order 2A conversion and
generates a second residue VresZ, which is also held by the SaH. As a result of the second

phase conversion:

L1+ L2
2 D[i]-Vref +Vres2

Vres1=i=Ll+1

L2 (2.2-2)

During the third phase, the same circuit is reused to perform L3 clock cycles of first-order

21A conversion. As a result of the third phase conversion:

L1+ L2 +L3
Z D[i]-Vref

Vres2 z i = L1 + L2 231 . (2.2-3)

 

Combine Equation 2.2-1 to 2.2-3,

 

 

 

(L1 . L1+L2 _ L1+L2+L3 \
2 DD] 2 D11] 2 D[i]
Vinz 1:1 +i=LI+1 +i=LI+L2+I -Vref (224)
L1 L1-L2 L1-L2-L3
K 1
Error Suppression:

To analyze the ability of this circuit on suppressing errors, assume V6,”, Venz
represent error signals when measuring Vmsl in the second phase and Vres; in the third

phase, respectively. Thus,

22

L1+L2
Z D[i]-Vref + Vres2
i=L1+1

 

 

Vresl = + Verrl,
L2 (2.2-5)
L1+ L2 + L3
2 D[i] - Vref
Vres2 = i :L1+L2231 +Verr2

Take Equation 2.2-5 into Equation 2.2-1, the signal Vin can now be expressed as:

 

 

(L1 . L1+L2 L1+L2+L3 .1
2 DD] 2 D111 2 DD] V 1 V 2
Vin: 1:1 +1=L1+1 +1=L1+L2+1 'VI‘Ef‘I’ err + err (22'6)
L1 L1-L2 L1-L2-L3 L1 L1-L2
K /

 

 

Equation 2.2-6 shows that Vern is suppressed by a factor of L1 (as in basic extended
counting conversion) and that Venz is suppressed by (Ll'Lz), the product of counting
numbers in the first and second phase, meaning in a three phase extended conversion case,
the error during the third phase will be suppress by the number of clocks in the second

phase AND the first phase.

Resolution

If there is no error or the error is limited to an acceptable level, the third phase will
generate sz with a resolution (in bits) defined by log2(L3). Together with the second
phase, Vresl has (log2(L2)+ log2(L3)) bits of resolution, and together with the first phase,
Vin has (log2(L1)+ log2(L2)+ log2(L3)) bits of resolution. Thus, the optimal resolution of

the three phase example is:

R = log2(L1)+log2(L2)+log2(L3) (2.2-7)

Speed:

23

In the first phase, 1 clock of integrator reset and L1 clocks of counting is required.
The final step generates Vresr, which combines with the integrator reset step for the
second phase. Thus the second phase requires only L2 clocks of counting. In the same

way the third phase requires L3 clocks. Thus, the total clock cycles required, N, is:

N =1+L1+L2 +L3 (2.2-8)

Summary

This analysis shows that all the beneficial properties of the extended counting
technique are retained. Additionally, this modified architecture has some significant
benefits over traditional extended counting, including capability for dynamic

reconfigurability, as discussed later in more detail.

2.2.2 Multiple Extended Conversion
The analysis above describes a three phase extended conversion technique. This
can be expanded to an arbitrary number of phases, M. This multiple-phase extended

conversion concept is described by:

 

 

L1 L1+L2
Z D[i]-Vref +Vresl Z D[i]-Vref +Vres2
Vin=i=1 , Vresr=i=L1+1 (2.2-9)
L1 L2
(z=L1+L2+---+LM_1)+L

D[i]-Vref+Vres

(i=L1+L2+-~-+L )+1
Vres(M_1)= M21
M

M
(2.2-10)

24

 

 

 

 

 

/ (i=L1+---+LM \
L1 L1+L2 Z D[i]
2 DD] 2 D[i] .

. .=1 '=L1+l lle+m+LM-1+1
sz +l +---+ -Vref (2.2-ll)
L1 Ll-LZ L1-L2 ----- L
M
t i

M
R = log2(L1)+log2(L2)+L +log2(LM) =i§110g2(Li) (2.2-12)

M
N=1+L1+L2+~~+LM=1+i>ElLi (2.2-13)

where all variables are as previously defined.

 

 

 

If the number of clock cycles in each phase are equal, i.e., L1 = L2 =--- = LM = L ,
then:

L 2L

2 D[i]-Vref +Vresl Z D[i]-Vref +Vres2
Vin=l=1 , Vres1=i=L+1 (2.2-14)

L L
M -L
2 D[i]- Vref + Vres M
_ i=(M-1)-L+1

Vres(M _1) — L (2.2 15)

M _ . jL
Vin = 2 L J z D[i] -Vref (2.2-l6)

j=1 i=(j—1)L+1
R = M -log2(L) (2.2-17)
N=l+M~L (2.2-18)

Equation 2.2-17 and 2.2-18 implies the resolution/speed reconfigurability capability of
the Hybrid Algorithmic-2A architecture, which will be addressed in detail in Section

2.3.2.

2.2.3 Hybrid Algorithmic 2A

25

The multiple-phase extended conversion technique introduced by this thesis work has

been termed Hybrid Algorithmic 2A conversion. Although there are no algorithmic

conversions in any phase, the rational for this terminology is discussed below:

1.

The reconstructed equation of Hybrid Algorithmic 2A, Equation 2.2-16,
M _ - jL
Vin = 2 L J z D[i] ~Vref (2.2-16)
j=l i=(j—1)L+1

jL
consists of two nested summations. The inside part 2 D[i] is exactly
i = (j — 1)L +1

M _ .
the same as in first-order 2A, while the outside part 2 L J is very similar to the

j=1

M .
X 2_' -D[i] function of an algorithmic ADC. The difference is, in algorithmic
i =1

conversion, each cycle converts 1 bit resulting in the 2" term, while in Hybrid

Algorithmic 2A conversion the number of bits converted during each cycle/phase is

M _ .
not necessary 1, but (logzL). Thus the Z L 1 term appears. If we choose L=2,
,- =1

which means each 2A conversion only converts 1 bit, then the behavior of Hybrid
Algorithmic 2A conversion will be the same as an algorithmic conversion.

From a coding point of view, the digital output codes of a Hybrid Algorithmic 2A
conversion is bit-weight encoded, as is an algorithmic or SAR conversion. Each

output code is bit weight encoded: the first output D[l] is divided by 2, the second

M .
output D[2] is divided by 22, and so on, such that. Vin = Z 2—1 -D[i] - Vref . In other
i =1

words, the output code is binary bit-weight encoded. In comparison, all the digital

outputs of a first-order 2A conversion are equally weighted. When reconstructing the

26

output, all the digital outputs are indistinguishably summed up and divided by the

L
Z 011']

total number of clock cycles in one conversion: Vin = l—zlL—mVref . This is referred

to as pulse width density (PWD) encoded. In the Hybrid Algorithmic 2A conversion,
the output from the 1St conversion phase is first summed up and then divided by L, the
output from the 2nd phase is summed up and divided by L2, and so on. Thus, the
output within one conversion phase is PWD encoded, while the output between
conversion phases are bit-weight encoded (the output from the 1St phase has the most
significance, and the output from the last phase has the least significance). The output
code shows weight encoded characteristic because bit weight information is encoded

into the system by feeding back the residue from between phases.

. From component architecture point of view, the core of Hybrid Algorithmic 21A is the
same as a first-order 2A conversion, as shown in Table 2.1. However, in adding a SaH
component and an analog MUX to the front end, the structure is very similar to the

SaH and MUX in Algorithmic conversion.

27

TABLE 2.1.

EA architectures.

Comparison of Algorithmic, First-order 2A, and Hybrid Algorithmic

 

Algorithmic

SAMPL EIHOLD

COMPARATOR

    

(1-BIT DAC) —O#Vro£
...-II llll‘
: - l> L

v. (E :‘
‘IIIIII I'll:
-V:e£

(refer to Figure 2.2)

 

 

 

Data-Reconstruct Equation:

M
Vin = 22" -D[i] ~ Vref
i=1

 

Encoding: Binary Bit-Weight

 

N=M

 

R=M

 

Sigma-Delta (ZA)

INTEGRATOR
COMPARATOR

D[i] DIGITAL B [1]
couurtn

    

 

Data-Reconstruct Equation:

iota

Vin = M

 

- Vref

 

Encoding: PWD

 

N=L

 

R=|092(L)

 

 

Hybrid Algorithmlc {A

 

 

 

 

 

Data-Reconstruct Equation:

V. =[ZL‘J‘ ’Z DriJJ-V,

j— i=(j‘l)L+1

 

Encoding: Combined
FWD and Big-Weight

 

N=1+M-L

 

(refer to Figure 2.3)

 

R= M- Iogz(L)

 

 

28

2.2.4 Summary

The new Hybrid Algorithmic 2A conversion essentially has two conversion loops:
an inner first-order 2A conversion loop, which is characterized by the number of
counting steps L in each phase, and an outer algorithmic conversion loop, which is
characterized by the number of phases M, or the number of times of residue feed-back
(M-l).

If L is large and M is kept small, which means longer counting conversion and fewer
residue feed-backs, the system behaves more XA-like, with high resolution but low speed.
The number of clock cycles increases exponentially with respect to resolution. Notice
that when M=1, there is only one conversion phase, and the architecture degenerates into
first-order 2A conversion.

If L is small and M is large, which means less counting but frequently residue
feed-back, the system behavior will is more Algorithmic-like, with relatively low
resolution but high speed. The total number of clocks increases linearly with respect to
resolution. Notice that when L=2, during each phase only 1 bit is converted and the
system behavior becomes very similar to a conventional algorithmic conversion.

M and L is fully determined by the clocking scheme: how many steps of counting
and when to feed-back the residue. By adjusting M and L through different clock schemes,
the system can be dynamically reconfigured at the architectural level to be more
XA-like or more algorithmic-like and is thus easily tailored in real time to application

demands.

29

2.3 Analysis of Hybrid Algorithmic 2A Architecture

2.3.1 Behavioral Verification

Behavior of the Hybrid Algorithmic 2A conversion is simulated and verified in
MATLAB. Figure 2.4 shows a case where 12-bit is achieved in 49 clocks by setting L=16
and M=3 (3 phases and 4-bit each phase). The input is a DC voltage equals to
(0.6- Vref); the triangle wave shows the output of the integrator and the square wave
shows the comparator output. Within each phase the waveform is exactly similar as
first-order 2A conversion. At the end of each phase the residue is generated, sampled and

fed as input to the next phase.

V: Output of the Integrator D: Output of the Comparator L=16 M=3 NoB=12
1.5 . . e .

 

 

____ _____L_J

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

'1 '50 10 2o 30 4o 50

Clock Cycles

 

Figure 2.4. Behavioral simulation of the Hybrid Algorithmic 2A conversion. A 12-bit
conversion is achieved in 49 clocks by setting L=16 and M=3.

To check if the output digital code represents the input, a sine wave is applied at the

30

input and output digital code is reconstructed back to analog voltages. As shown in Figure
2.5, the reconstructed voltage tracks the input voltage, verifies the function of the Hybrid

Algorithmic 2A conversion.

Output Waveform fi=lkHz fs=1MHz OSR=5EIU M=3 L=1B R=12

Vin, D, Bi

 

 

 

 

 

 

 

 

l l l l 1 l l l
0 100 200 300 41]] 500 600 711] 80.1 930
time (us)

Figure 2.5. Behavioral simulation of the Hybrid Algorithmic 2A conversion.

2.3.2 Resolution/Speed Configurability
The optimal resolution R for the Hybrid Algorithmic 2A conversion are given by:
R = M -log, (L) (2.2-17)
At one specific resolution R, two parameters M and L are adjustable, providing a wider
range of configurability than is available in other conventional ADC architectures. To
illustrate the flexibility of configuration of M and L, consider a 12-bit Hybrid Algorithmic

2A conversion as an example. As shown in Figure 2.6, the 12-bit conversion can be done

31

in one phase using first-order EA conversion by configuring M=1 and log2L=12, as in (a);
or be divide into two phases, 6-bit + 6-bit by making M=2 and log2L=6, as in (b). It can
also be divided into three phases, 4-bit + 4-bit + 4-bit, by making M=3 and log2L=4, as in
(c), or in other configurations shown in Figure 2.6. Furthermore, as derived in section
2.2.2, the Hybrid Algorithmic EA circuit does not necessarily have equal clock cycles in
each phase, which means the 12-bit conversion can be implemented as for example 3-bit
+ 3-bit + 2-bit + 2-bit + 2-bit, as shown in (g), or other combinations of bit-per-phase and

phases, using this very flexible architecture.

 

 

 

 

 

 

12m
(8) I I M=1, logZ(L)=12
6-bit 6-bit
(b) I I I M=2, logZ(L)=6
44m 44m 44»:
(c) I I I I M=3. lothL)=4
34m 34m 34m S-bit
24m 24m 24m 24m 24m 24m
“’1 l l I l I I I ”=5. '°92(L1=2
14m 14m 14»: um 14m 14m 14m 14m 14m 14m 14m 14m _ _
“I I I I I I I I I I 1 I I I ”42' ”92“)"
34m 34m 24m 24m 24m M=5, 1092(L1)=I092(L2)=3
19’ I I I I I I

 

WIL31=IOOZIUI=IOIIZIL5I=2

Figure 2.6. Different configurations for a 12-bit Hybrid Algorithmic EA conversion.

The total number of clocks needed N for the Hybrid Algorithmic EA conversion is
given by: N =1+M ~L (2.2-18)
With the wide range of M and L configurations, we can get different kinds of resolution
versus speed combination. Figure 2.7 shows the possible resolution and speed

combinations when M and log2(L) varies from 1 to 16 respectively.

32

 

 

 

 

 

 

 

 

 

 

 

 

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<mQ5m 2— ea H:

33

2.3.3 Benefits in Energy Saving

As described in Chapter 1, power or energy consumption is a key circuit design
constraint for implantable or portable devices. Hybrid Algorithmic EA converter
architecture provides the opportunity of trading off resolution and speed with power
consumption according to signal activity or channel activities.

The energy consumed in one conversion is given by:

E = (PAna log + PDigital ) . Tconv (23-1)
where P Ana log and PDigitaI stands for analog and digital power consumption
respectively. P Ana log is the product of supply voltage and tail current:

P Ana log = VDD 'ID (2'3'2)
Thus P Ana log is fixed once VDD is determined and the biasing is fixed (thus ID fixed). PDigi ta 1
consist of two parts:

PDigital : Pstatic + denamic (23-3)
Pstatic is the static power consumption of digital circuits. If the digital circuits are all

static CMOS circuit, Pym can be ignored. 'c’ the dynamic power of digital

tic denamt

circuit, can be estimated by:

— a u 2 a
P dynamic "“ CL VDD fCLK (2'34)

in which a is switching activity and C L is the average load capacitance. a is fixed

once the algorithm is fixed. C L is fixed once the circuit is determined.

Tconv is the conversion time, and is the product of clock cycle and number of clocks in

one conversion:

1
Tconv = tCLK -N -N (2.3-5)

fCLK

34

Taking Equation 2.3-2, 2.3-3, 2.3—4, 2.3-5 into Equation 2.3-1, we get:

_ . . . 2. ..___1_.
E‘(VDD 10” CL VDD fCLK) f N
CLK
V I (2.3-6)
_ DD“ D . . 2 .
—( +a CL VDD ) N
CLK

If only the case of fixed clock rate f CL K is considered, then the energy consumption

for each conversion is directly proportional to the number of clocks required for each
conversion.
For Hybrid Algorithmic EA converter architecture, the number of needed clocks N
for R-bit resolution is given by Equation 2.2-17 and 2.2-18, as listed below:
R = M ~log2(L) (2.2-17)
N=1+M-L (2.2-18)
The flexibility of the combinations of L and M shown in Figure 2.7 provide the
possibility of energy saving. Figure 2.8 shows the normalized energy consumption of
the Hybrid Algorithmic EA architecture at different L and M configurations. It can been
seen from Figure 2.8, and also be proven from Equation 2.2-17 and 2.2-18, that
increasing M, the number of conversion phases, will reduce N, the total number of clocks
required, and thus energy consumption for each conversion. It matches the fact that with
larger M, the architecture is more like algorithmic architecture, and achieves lower energy
consumption. In best case, L=2 and M=R, meaning an R-bit conversion is completed by
l-bit each phase and R phases, Hybrid Algorithmic EA architecture degrades to pseudo
algorithmic architecture, the total number of clocks becomes

N = 1+ 2R (2.3-7)

35

approximately twice of the clocks needed for real algorithmic conversion.

500

mm
("WWW“) 400—

300

 

200

 

100

 

 

Figure 2.8. Normalized energy consumption for the Hybrid Algorithmic 2A architecture
at different configurations.

36

REFERENCES

[1] P. Rombouts,W. DeWilde, and L.Weyten, “A 13.5-b 1.2-V micropower extended
counting A/D converter,” IEEE J. Solid-State Circuits, vol. 36, pp. 176—183, Feb. 2001.

[2] J. D. Maeyer, P. Rombouts, and L. Weyten, "A double-sampling extended-counting
ADC," IEEE J. Solid-State Circuits, vol. 39, pp. 411 - 418, Mar. 2004.

37

Chapter 3
Circuit Implementation

A Pseudo-differential circuit implementation of the Hybrid Algorithmic EA A/D
architecture described in chapter 2 was designed and fabricated using standard 0.5um
CMOS process available through MOSIS. The circuits were implemented with
switched-capacitor topology and correlated-double sampling techniques were used to

overcome the effects systematic biases in the circuits.

3.0 Process parameters

The standard 0.5um CMOS process available through MOSIS [1][2][3] has a
Lambda of 0.3um and allows operation at 3V~5V supply voltage. It provides 3 metal
layers and 2 poly layers, and a high resistance layer. PiP (poly2 over poly) capacitors
(950 aF/um’) and the HRP (High Resistance) option are available. Some basic process
parameters for hand calculation are summarized in Table 3.1. The SPICE comer
parameters and the electrical parameters extracted by MOSIS for the fabrication run is

summarized in Appendix D.

38

Table 3.1 Apgroximate Process Data for 0.55m CMOS process

 

 

 

 

 

 

 

 

L,,-,, = 0.6 urn t,, = 140 A

Ac...’ = 120 MANZ V.C..’ =40 ILA/V2
vm, = 0.7 v VTO, = .09 v

A = 0.06 V"

y, = 0.47 v"2 y, = 0.58 V“2

(1),, = 0.38 v (In, = 0.39 v

K = 0.7

 

 

39

 

3.1 Circuit Design and Simulation

The circuit components, such as the integrator, the comparator and the sample/hold
were designed using switched-capacitor circuit techniques [6]. Correlated Double
Sampling (CDS) technique was used for the sample/hold circuit. The system level
simulations verify the functionality of the circuit. A critical component of the
implementation is a cascoded inverter which is used instead of conventional operational

amplifiers to achieve low-power operation.

3.1.1 Cascoded Inverter Amplifier
A cascoded inverter, as shown in Figure 3.1, was designed to act as a high gain
amplifier. M1 and M2 are current source load. M4 is a common source amplifier and M3

is a common base amplifier.

VOUT

VIN

 

Figure 3.1. Schematic for the cascoded inverter amplifier.

The transistor sizes and biasing voltages of the cascoded inverter were carefully

40

chosen in order to achieve a high gain and moderate speed with a reasonably power
consumption. With a size of W/L = 30u/6p. for M1 and M2, W/L = 20u/6u for M3 and
M4, and biasing of VDD = 3V, Vbl = 1.9V, Vb; = 1.7V, and ng = 1.4V, simulation shows
that the CIA has a gain of 57dB around the middle point where VIN = Vour = VMID =
828mV. Figure 3.2 shows the operation of the cascoded inverter amplifier. A drain

current Id of 2.54 ILA leads to a power consumption of less than 8uW.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GAIN ll 1d a
89 -'= GAIN 2.54500 ." ”W5
A 50 . 2.54300 .
g < - 4 a A e a
v 20 . V2.5410u .
-1@ - ‘ 253900 ......... .L..
1 1K 1 IO '. 0.0 5. u 19“
freq ( Hz J time s )
AC Response Input-Output Chorocteristic 1
a: AN A: ’1"
90m .“ NUT 3.5 -: /our
1
A 2.9
A 5
> I_ ’
... r 8 1.0 .
I
9.0 -r a: e. _ r + on ,,,,,, L ----.LL---_A--‘-1
1 K 1 16 ' 0.0 1.0 2.0 3.0
freq ( Hz 1‘ IN (V)

 

 

Figure 3.2. Simulation results for the cascoded inverter amplifier.

Compared to conventional operational amplifiers, this cascoded inverter amplifier
has advantages of simple structure, low power and compact size. The disadvantages
include relatively lower gain and lower dynamic range. The lower dynamic range results
from asymmetrical position of VMID relative to the rail voltages. This is unlike the case
in traditional op-amp based designs where virtual ground can be dynamically adjusted.
For a cascoded inverter VMID is fixed by transistor size and biasing. VMID eventually

determines the analog virtual ground of the system. However, in switched-capacitor

41

. A. l" ...-“I,

 

circuits, biasing the input at VMID is automatically achieved by shorting the input and

output during circuit reset as discussed below.

3.1.2 Integrator
A cascoded-inverter based switched-capacitor integrator, as shown in Figure 3.3, was
designed and simulated. CMOS switches are used in order to reduce the on-resistance and

balance clock feed through. Cl=C2=100fF. 81 and 82 are none-overlapping clocks.

 

 

 

 

 

 

SR
._/
0-——-”—0
cz
VIN1 31 Cl 32" vour
D—/—-0—-I _. e -—D
vgz j2 31' A
Q7Vagnd

Figure 3.3. Schematic of the inverter based switched-capacitor integrator.

The circuit operates as follows: In the initial step, SR is closed to set the voltage on
node A, the input to the cascoded inverter amplifier, to VMID where the gain is maximum.
Then SR is opened, validating the operation of the integrator. During phase I (sample
phase), SI, 81’ are closed while Sz, 82’ are open. VIN1[n] is applied to C1 storing charge
amount = (VMID- INI[n])-Cl on the right plate of C1. Assuming at this time Vour =
VOUT[n], the charge on the left plate of C2 is (VMID -VOUT[n])-C2. During phase II
(integrate phase), 81, 81’ are open while Sz, 82’ are closed. an2[n+1/2] is applied at C1
forcing the charge on the right plate of C1 to be (VMID- IN,[n+l/2])-Cl . Denoting Vour

= VOUT[n+l] at this time, then charge on the left plate of C2 is (VMID -VOUI.[n+l])-C2.

42

n z a haired,

:d-f

 

Table 3.2 summarizes the operation of the inverter based integrator.

Table 3.2 Operation of the inverter based integrator

 

 

 

 

Phase SR 8, 82 Vol. on c1 Vol. on C2
Initial 1 0 0 N/A 0
Sample 0 1 0 VMID -VIN1 ["1 VMID 'Vour In]
Integrate 0 0 1 Vmo -V.N2 [n+1/2] Vmo —V0UT [n+1/2]

 

 

 

 

 

 

 

 

Appling charge conservation at node A:
-VINI[n]-C1-Vom[n]-C2 = -VIN2[n+l/2]-Cl - VOUT[n+l]-C2 (3.1-l)
Thus,
VOUT[n+1] = Vom[n] + (le[n] - Vm,[n+1/2])-C1/C2 (3.1-2)
During operation, node A should be kept at VMID = 828mV all the time, otherwise the
gain of the CIA will greatly decrease. Figure 3.4 shows the simulation clocking and

waveforms of the integrator. 200mV is integrated in each clock.

Figure 3.5 demonstrates the linearity and large dynamic range achieved by the
integrator when its output integrated from 0V to 3V. It also compares the result with an
ideal integrator, as shown by the dashed line. The simulations results indicate that the

circuit can achieve linearity of > 10 bits with a dynamic range of 0.3V-2.5V.

43

"V L‘ .d' l' Jinn”
, .

 

(V)

(V)

(V)

(V)

Transient Response I! 0

 

 

 

 

 

 

 

. I: /OUT
3'” M ’5‘ 3.0 Pa: /A
2.0 I
1.0 i
0.0 -4 . . - . - A . . :
3.0 ° 52 2.0 L
r
2.0 .
1.0 3. I
0.0 ..... . r
1.0 '1
3.0 '=
2.0 » ..
I 2
1.0 . ,3
J
0.0,-,, ..... 9.-.---SSSEI 0.0 ......... . ......... . i,
0.0 5.00 100 0.0 5.00 100 ,.
time(s) time(s)

 

Figure 3.4. Operation of the inverter-based integrator: integrating 200mV each clock.

 

 

 

 

Tronsient Response 0
a: /A
3‘” pl: /OUT
I
2.0 L
I
I
1.0
¥ :
0,6 ‘ ......... I L L i l ......... I A L A L #1 ......... I
0.0 2000 4000 6000 0000 1 0m

Figure 3.5. Simulation result shows the linearity of the inverter-based integrator.

44

3.1.3 Comparator

Figure 3.6 shows the schematic for a basic inverter based switched-capacitor
comparator circuit. 10 and 11 are cascoded inverter amplifiers, whose inverting point is at
VMID z 800mV. 12 is a normal CMOS inverter, whose inverting point is at VDD/Z :1 1.5V.

A D Flip-Flop is added at the output to latch the comparison result.

SR SR
/ /

 

 

IO 11 IZ

c1 DOUT
D—/——1>——”—1 A A Latch —D
B A our1 our2 our>

Figure 3.6. Schematic of a basic switched-capacitor comparator.

 

 

 

 

 

 

 

 

 

 

During phase 1 (sample phase), SI and SR are closed, setting node A, OUTI and
OUT2 to VMID, and storing charge (VIN,[n]-VMID)-Cl on capacitor C1. Then in phase II
(compare phase), 81 and SR are open and 82 are closed. The voltage on the node B
becomesVIN,[n+l/2]. Assume the voltage on node A becomes VA. Since SR is open,
charge conservation on C1 gives:

(erlnl'vmml'CI = (VIN,[n+1/2]-Vx)-Cl (3.1-3)
Then,

VA = VMID+ (VIN2[n+1/2]-VINI[n]). (3.1-4)
If VINI[n]<VIN2[n+l/2] ,VA is higher than VMID, which will pull down VOUT“ thus
pulling up VOUTZ, then pulling down VOUT and DOUT = 0 .
If VINI[n] > szln+1/21 , VA is lower than VMID , which will pull up VOUT, , thus pulling
down VOUT, , then pulling up VOUT and DOUT =1 .

Table 3.3 summarizes the operation of the basic inverter based comparator.

45

 

Table 3.3 Operation of the inverter based comparator

 

 

 

 

 

 

 

 

 

Phase SR 8, 8, Vol. on node B Vol. on node A
Sample 1 1 0 Vm, [n] Vmo
Compare 0 0 1 Vm [n+1/2] Vmo +(VOUT [n+1l2]- Vm [n])

 

The problem with this basic inverter based switched-capacitor comparator is that it

compares two voltage from two different times, erM and VIN2[n+l/2] . To compare
two voltages at the same time instant, some modifications to the topology are necessary.

Figure 3.7 shows the schematic of a differential comparator that eliminates the time

discrepancy [7].

D_/

82

Vagnd

82
VIN" S 1 C2
D—/

Bn

During phase I (sample phase), the SR switches are closed to settle node OUTlp,
OUTln and OUT2p, OUT2n to the middle point. SI and 81’ are closed, settling node Ap
and An to the common mode voltage (VIN, +Vm-)/2 . Thus (VIN+ ‘Vm-)/2 and
'(Vm+ -VIN_)/2 are sampled on C1 and C2, respectively. During phase II (compare phase),

82 and 82’ are closed, pushing the voltage on Ap and An to [VAGND- (VIN, -VIN_)/2] and

SR

0
Ap I Il I2 DOUTp
- - >~ -
OUTlp OUT2p our-’

82’

31' 52,

1 UT1n OUT2n our . DOUTn
~ . - >~ -
An I
I4 I5 I6

SR

46

Figure 3.7. Schematic of a differential comparator.

 

[VAGND+ (VlN+ ‘Vm-)/2l respectively. Eventually VAGND = VMID.

If Vm+ >Vm- , VAp is lower than VMID and VAn is higher than ern-

DOUT+ = l and DOUT- = 0.
If VIN, <Vm- ,

Dom, =0 and Dov, =1.

Ap

is higher than VMID and VAn is lower than V1010-

Table 3.4 summarizes the operation of the differential comparator.

Table 3.4 Operation of the differential comparator

Thus

Thus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Phase SR 3. 8, Vol. on node B Vol. on node A
Sample 1 1 0 Vgp VIN + V»
(Vm. +Vm-)/2
V3" . VIN- VA"
Compare 0 0 1 VBI, ero VII, VMID- (VIN, -VIN_)/2
V3,, VN, VMID+ (VIN, 'Vm.)/2

 

 

Switch S" helps to cancel out the common mode voltage, and only the differential

mode voltage on C1 and C2 is sampled during the sample phase. In normal operation, the

cross-coupled 82’ structure bypasses the inputs to the second stage inverters before the

output of the first stage inverters change, thus helping the speed of the comparator. If

somehow the inputs to both of inverters are higher or lower than VMID , then because of

the cross-coupled structure, a competition will decide the output of the inverters, ensuring

that the inverter chain gives out complementary digital output. At the end of compare

phase, the two latches latch the output of inverters and hold the value during the sample

phase. Figure 3.8 shows the simulation waveforms of the differential comparator.

47

SJ

2!

(V)

13
DJ
&5
23

(V)

15
1!
ll
2‘

(V)

13

Transient Response

“/33

 

 

 

 

 

 

 

 

 

 

Ii

 

 

 

 

 

 

 

A A A

 

 

v '

time ( s)

(V)

(V)

(V)

(V)

 

 

3.0 3’9"“
2.0
1.0
0.0 - - - s - --.

 

 

 

 

 

 

 

 

 

-‘ L. __l
2.- I
1.0 _
0.0 I - - . - - - - L - -
0.0 5.00

time ( s)

Figure 3.8. Simulation waveforms of the differential comparator.

In order to determine the resolution and offset of the comparator, a sinusoid wave is

applied to one input of the comparator while the other input is kept at a DC value.

vINln INln 0 sin (2.00 50u 50k 2u)
vINlp INlp 0 dc 2.00

Ideally the latched comparator output should be a square wave with 50% duty cycle. By

changing the amplitude of the sine signal, varying the DC offset, and watching if the

output is still a square wave, we can know the resolution and offset of the comparator.

The simulation shown in Figure 3.9 verifies that the differential comparator has a

resolution less than SOuV and offset less than SOIIV.

48

Transient Response

 

 

 

 

 

(V)

 

(V)

 

(V)

 

 

0.00 20.00 710.00‘ H 00.00 ““101... ‘ ”1000

Figure 3.9. Simulation testing the resolution and offset of the differential comparator.

3.1.4 Sample and Hold

Figure 3.10 shows a simple inverter based sample and hold circuit. At initialization,
SR is closed to set the voltage on node A at VMID. During phase I (sample phase), 81 is
Closed to sample (VIN - MID)in capacitor C. During phase 11 (hold phase), 31 is open and $2 is
closed, storing VIN at Vour- Table 3.5 summarizes the operation of the simple sample and

hold. Simulation waveforms shown in Figure 3.11 verify the function of the circuit.

 

 

 

 

82
/
SR
/
VIN 31 C vour
D I A D

Figure 3.10. Schematic of the simple sample and hold circuit.

49

Table 3.5 Operation of the simple sample and hold

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Phase SR 8, S; V." Vol. on C Vow
Sample 1 1 0 VIN In] VIN InJ'VMID VMID
“Old 0 0 1 VIN [n+1/2] VIN [nl‘VMID VIN [n]
Transient Response 1! m a
a: [SI 5: 0 IA
3" I 2.10 .'= 4'"
A 2.0
> I 1.90 . 4
0.0 I 1.70 .
-° /SZ
3.. 1.5. n I)
A 2.0
> A 1.30
v 1.0 :
0.0 - - - - - - - - - A 1.10 .
/ I
9.0m .
0 A
> 700111 ‘0
500m, - - - g - - - - 1
0.0 50v

 

time ‘( s )

 

Figure 3.11. Simulation waveforms to verify the function of the simple sample and hold.

A disadvantage of circuit is that it is very sensitive to the finite gain of the inverter
amplifier. If the amplifier gain is not infinite but -A, when the output is Vour, the input
biasing to the inverter will become (VMID-Vom/A). For the inverter amplifier, the gain is
maximum when the input is biased at VMID. Drift of the input bias will quickly degrade
the gain of the inverter amplifier and the circuit will malfunction. To overcome this
problem, the inverter amplifier has to be reset in each sample phase to set the bias at VMID.
However, this will pull the sample and hold output back to VMID in every cycle,

introducing unwanted noise into the circuit.

50

An improvement on the simple sample and hold circuit is to employ the Correlated
Double Sampling (CDS) technique [9]. Figure 3.12 shows the schematic of a sample and

hold circuit with CDS technique.

 

I:>—/
B
81 ’
VLVagnd

Figure 3.12. Schematic of the sample and hold with CDS technique.

 

 

 

Capacitor Cds is added to sample the offset between node A (VMID) and node G
(Vagnd) during initialization. In this case the offset should ideally be zero. Since the
charge on capacitor Cds can not change after SR is open, the voltage over Cds will not
change. Furthermore, node G is reset to Vagnd every cycle, thus node A is indirectly reset
to VMD Table 3.6 summarizes the operation of the sample and hold with CDS technique.
Figure 3.13 shows the simulation waveforms to verify the function of the circuit.

Table 3.6 Operation of the sample and hold with CDS technique

 

Phase SR 81 S, V... vs VA Vol. on C1 Vol. on Cds Vou-

 

Inltial 1 1 0 N/A Vagnd VMID N/A Vagnd-VM.D=0 N/A

 

Sample 0 1 0 V», [n] Vagnd Vmo V.” [n]-VM.D Vagnd-VM.D=0 V.” [n-1]

 

 

”Old 0 O 1 VIN [n+1/2] Vagnd VMID VIN Inl‘VMID Vagnd-VM.D=0 VIN [n]

 

 

 

 

 

 

 

 

 

 

51

 

Transient Response 1! a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

. : IA -: ID 0: IG
3'. n./SR 2.1. ;: IOUT 0: [INI
- 2.0
> 1.0 L90
... 1.7.
v/SZ .
3‘ 3 1.50
A 2.0 i
’ f5
3 1.0 I > 1.30
0.0 i - - - - - - - - - 1.10
:/51
30. El II“ T 9..
. 2.0
> M .
v 1,.
0.0“3--3----- T500 W00J“A““‘500
time(s) ' time(s)

 

Figure 3.13. Operation of the sample and hold with CDS technique.

It can be seen that the inverter amplifier only has to be reset once during initialization.
After that Cds will hold the VMID and bias the amplifier. The voltage output will not be
forced to VMID during sample phase. However, during sample phase there is no feedback
for the amplifier since both SR and 82 are open, making the output of the amplifier
unstable, as shown in Figure 3.13. This problem can be overcome using Time-Shifted
CDS (TS-CDS) technique [9] as shown in Figure 3.14.

/

Bp I L
VIN 51’ Cds vour
Vagnd<}_+ G
Dd. —]I—« A be »—D

 

 

 

 

 

 

 

 

 

 

 

 

51
Figure 3.14. Schematic of the Sample and Hold with Time-Shifted CDS technique.

Another set of CD8 sample and hold with opposite clocking phase is added into the

52

original CDS sample and hold to form the other half circuit. When the upper half circuit
is in sample phase, meaning $1 is closed and S; is open, the lower half is in its hold phase,
presenting the voltage stored on C2 at the output. When the upper half circuit goes to hold
phase, 81 is open and S; is closed, the lower half goes to its sample phase. Thus at any
time one half of the circuit will drive the output. Figure 3.15 shows the operation of the
sample and hold circuit with Time-Shifted CDS technique [9]. Notice the OUT signal
more closely follows the input than the results in Fig. 3.11 and 3.13, demonstrating the

improvement in using this technique.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transient Response I! a
. : [G : AN! : IOUT
3" " ’5' 2.19 .: ’A I; ’3 ‘
A 2.0
z 1.0 1.90
O
J 1.70
3" .: I52
2'. 1.50
> A
v 1.0 :
I» 1.30
0.0 - - - - - - - - -
3.. I: ISR t“
A 2.0
> 900m
v 1.0
1.30:- ‘ :‘ -: ‘ ‘: ‘ ‘: : 5'0“ 7”“‘5 4 - 4 - - L 5|.“
' time(s) ' time(s)

 

Figure 3.15. Operation of the Sample and Hold with Time-Shified CDS technique.

3.1.5 l-bit DAC (Analog MUX)
The analog MUX is constructed using two CMOS switches. Figure 3.16 shows the
schematic. S and Sn are complementary signals. When S is high, Voufivml; when S is

10W, VOUTzleO-

53

  

L5“ Function
S=1 OUT=IN1
8:0 OUT=INO
8

Figure 3.16. Schematic of the 1-bit DAC (analog MUX).

3.1.6 Whole System Schematic and Simulation

A fully differential circuit implementation of the Hybrid Algorithmic 2A ADC
architecture proposed in Chapter 2 was designed using the sub-blocks described above:
the inverter-based integrator, the differential comparator, the sample and hold with
Time-Shifted CDS technique, and the l-bit DAC. The system schematic is included in
Appendix E.

The Hybrid Algorithmic 2A circuit is simulated and the transient simulation
waveform is shown in Figure 3.17. It shows a case of L=16 and M=2 (4-bit each phase
and 2 phases). Clock rate is 500 kHz. OuS — 2uS is the initial step (reset). 2 uS — 34uS is
the first phase and 34uS-66uS is the second phase. By comparing Figure 3.20 and Figure
2.4, especially noticing the similarity of the waveform on the integrator output

(INT__OUTp), the function of the Hybrid Algorithmic 2A circuit is verified.

54

3.0
2.0
1.0
0.0

(V)

5.0
2.0

(V)

- 1.9
5.0
2.0

(V)

-1.0

3.0
2..
1.0
0.0

(V)

Transient Response

 

 

 

 

 

 

 

 

(V)

(V)

(V)

(V7

 

‘5' I: ’1”.pr

 

 

—-
v a v
ALLA-uAd-AAJLu-ALAWAAALI

1.5 A: AN'LJNZp

 

 

 

 

1.0 :.
”WM
0.0 20}. 40.. 50..
time ( s )

Figure 3.17. Simulation waveforms of the Hybrid Algorithmic 2A ADC: L=16, M=2.

55

3.2 Circuit Layout
3.2.1 Floor Planning

A typical mixed-signal circuit contains active analog cells (opamps or comparators),
passive components (resistors or capacitors), switches, and digital logic (for example,
none-overlapping clock generator). Before designing the layout of the components, it is
necessary to define the floor plan of the analog block. The general rules to follow are:

- put the analog critical components as far as possible from the digital elements

- make the connections to the critical nodes as short as possible

- avoid crossover between the analog biasing lines and digital busses
The layout of the chip follows the typical floorplan of a switched-capacitor circuit and a
typical floor plan for a fully differential switched-capacitor circuit suggested by Franco

Maloberti in [10].

3.2.2 Layout of the Basic Components

The basic components in the switched-capacitor circuits are the cascaded inverting
amplifier, the capacitor pool, and the switches. Figure E2 in Appendix E shows the
layout of the cascaded inverting amplifier. It occupies a compact area of 35pm X 40pm.

The capacitors are made by PiP (poly2 over poly) capacitors. Figure E3 in Appendix
B shows the layout of a capacitor pool containing two matched lOOfF capacitors. The
layout follows the common centroid structure rule [10]. Each small capacitor block has
around SOfF capacitance. The upper-left and lower-right blocks form Cl and the

upper-right and lower-left blocks form C2. The whole capacitor pool is shielded by an

56

 

nwell, which is connected to a reference (VDD in this design).

3.2.3 Layout of the Sub-Blocks

The circuit sub-blocks: the integrator, the comparator, the sample and hold, and the
analog MUX (l-bit DAC) are carefully layout-ed following the floor plan described in
section 3.2.1. All layout use only metal 1 and metal 2, providing the possibility to cover
the entire analog core using metal 3 for shielding. All the sub-blocks passed DRC and

LVS. The layout of the sub-blocks can be found in Appendix E.

3.2.4 Layout of the Whole Chip

The integrator, comparator, sample and hold, and analog MU X (l-bit DAC) were
placed and connected to form the analog core of the Hybrid Algorithmic 2A ADC. The
layout follows the floor plan discussed in section 3.2.1. Analog bus was put on the right
hand side and the digital bus was put on the left hand side. The analog core passed DRC
and LVS.

Non-overlapping clock generator circuits for the integrator, comparator and sample
and hold were added to the layout. Opamp voltage followers were added for observing
the analog voltages during test. The whole circuit was put in a 1.5mm X 1.5mm 40-pin
pad frame. The 1/0 pins, observation pins and power pins were connected to the pad

frame. Layout of the whole chip is included in Appendix E.

57

REFERENCES

[1] MOSIS Integrated Circuits Fabrication Service: http://wwwmosisorg/ .
[2] MOSIS Educational Program (MEP): http://www.mosis.org/products/mep/ .

[3] AMI CSN process webpage:
http://www.mosis.org/Technical/Processes/proc-ami-c5n.html

[4] NCSU Cadence Design Kit: http://www.cadence.ncsu.edu/CDK.html .
[5] The IIT standard cell library: http://vlsi.ece.iit.edu/proiects/scells/.
[6] RE. Allen & D. R. Holberg, CMOS Analog Circuit Design Second Edition Chapter 9.

[7] P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog
Integrated Circuits, Wiley, 2001

[8] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000

[9] Jipeng Li and Un-Ku Moon, "A 1.8-V 67-mW 10-bit lOO-MS/s pipelined ADC using
time-shifted CDS technique," IEEE J. Solid-State Circuits, vol. 39, pp. 1468 - 1476,
Sept. 2004.

[10] J .E. Franca, Yannis Tsividis, edited, "Design of Analog-Digital VLSI Circuits for
Telecommunications and Signal Processing", Second Edition, Prentice Hall, 1994,
Chapter 11 by Franco Maloberti, "Layout of Analog and Mixed Analog-Digital
Circuits".

58

Chapter 4
Testing & Results

4.1 Fabricated Chip

The Hybrid Algorithmic 2A ADC v1.0 chip was fabricated using a standard 0.5u
CMOS process available through MOSIS. A micrograph of the fabricated prototype is
shown in Figure 4.1. The chip is packaged in DIP40. The pin out and description is given

in Appendix D.

‘i.

ii iii.

“it s

(3+
. A

“i if;

4

ii

I}
w _

i.

’1'

W ,V ‘. V.” ', r ' :l ". ‘ -- ‘4‘. ‘,r it .
aria .11.: i .. ‘. ~. *5
Figure 4.1 Fabricated Hybrid Algorithmic 2A ADC v1.0chip photo.

 

59

 

4.2 Test Setup

A key component in mixed-signal design is a reliable test-station, which can be used
for evaluating and benchmarking the performance of fabricated chips. A general-purpose
analog/mixed-signal IC testing station has been developed in the Adaptive Integrated
Microsystems Laboratory to verify the function and measure the performance of the A/D
converter chip. Details about the specifications and design of the test station is
summarized in Appendix E and can be also be found at
http://www.egr.msu.edu/aimlab/teststation.htm.

Figure 4.2 shows the setup for testing the A/D converter chip. All the biasing,
reference voltages and input signals are generated using NI-DAQ card and the DAC array.
Clocking, control logic and the counter/shift register for the ADC are implemented from
the FPGA. The MATLAB code for generating analog biasing and the F PGA Verilog code

for generating clocking and control signals are attached as Appendix F.

 

 

 

 

 

 

 

 

 

I

' I
: ONTRO :
. I LOGIC I
' I
' I
' I
i COUNTER 3m:
I 2 MUX / REGISTER .
: Nl-DAQ, INTEGRATOR | :
. DAC array: ' -.' I
I I ( 1-BIT DAC ;,' .
l . _ , Vref , " |
IBIaSIng, . ...IOIII can: . I| I
| Vref, : A: VIP: if . I: '
:Vln I ADC Chip ‘.."".i."": :l. FPGA Board :
l : Vref :: |
' I

Figure 4.2. Setup of testing the A/D converter chip.

Figure 4.3 shows a photograph of the testing station ready to test the ADC chip. The

NT-DAQ card and the FPGA board are connected to the testing motherboard. The

60

daughter board is mounted on the motherboard and the A/D converter chip is put in the

socket.

 

Figure 4.3. Photo of the testing station ready to test the chip.

61

4.3 Testing of Circuit Components
4.3.1 Testing of the Op Amp Voltage Followers

The first step for testing the ADC chip is to test the Op Amp voltage followers and
find suitable biasing to the Op Amps so that we can have observation to the internal
analog voltages available. All the voltage followers have the same circuit and layout,
and share the same biasing, thus we can test any one of the voltage followers.

To test the voltage follower connected to the INT_INlp node (refer to Appendix E
for schematic and pin description), whose input can be directly accessed through the INp
pin by switching the analog MUX to 0, apply a ramp signal in INp pin and observe the
output at INT_IN1p pin. Figure 4.4 shows the waveform when testing the Op Amp
voltage followers. Channel 1 is the input and Channel 3 is the output. It can be seen that
when the input is 780mV ~ 2.5V, the output tracks the input, while for input voltage
lower than 780mV, the output is always 780mV; and for input voltage higher than 2.5V,
there is a noticeable voltage drop at the output. In latter testing, it should be remembered
that an observation voltage of 780mV could mean that the input is actually less than
780mV.

In Cadence simulations, with a biasing of VPBl=2 . 3V, VPBZ=1.8V, VNBl= 0 . 9v,
VNBZ=0 . 7v, the voltage follower can function correctly with input signal frequency as
high as 100 kHz. However, in real circuit testing, with the above biasing, the voltage
follower can only track its input when the input signal is less than 100 Hz. A possible
explanation is that in Cadence simulation, the pad capacitance is not considered while in

the actual chip the voltage follower does not have enough drive capability for the big pad

62

capacitance with above biasing. Afier changing the biasing to VPB1=1 . 7V; VPB2=1 . 5V;
VNBl=1.3v; VNB2=1.1V; the voltage follower can correctly follow the input signal up to

100 kHz.

 

Figure 4.4. Waveform of testing the op amp voltage follower.

4.3.2 Testing for the Cascoded Inverter Amplifiers

The second step was to test the cadcoded inverter amplifiers and set the biasing. A
trick is used there: INT_CLK] and INT_CLKZ are closed at the same time in order to
vary the voltage on node INT_Ap by varying REF (agnd). A summary of the

configuration for testing the cascaded inverter amplifiers is shown below:

INT_S1 = 1; |NT_82=1;
Apply a ramp signal in REF pin (pin 24);
Observe the INT_Ap pin (pin 13) and INT_OUTp pin (pin 12).

Figure 4.5 shows the waveform when testing the cascaded inverting amplifer.

Channel 1 is the input and Channel 4 is the output. Comparison to the input-output

63

characteristic shown in Figure 3.2, this waveform demonstrates that the cascaded inverter
amplifier is functioning as expected. Notice that the output can only go as low as 780mV.
This is due the problem of voltage follower as described in section 4.3.]. Testing shows
that when the biasing is VBl=2 . 2V, VBZ=2 . 0v, VB3=1 . 4V, the cascaded inverter

amplifier has a gain around 2000 (66 dB). Testing results also show that Vmid E7 80mv .

.LI

1

IilxilJlJqu

nu nunun-unununuuuu-uan-nn-onnun-uuuuu-ou nnnnnnnnnnnnnnnnnnnnn

...- ...................

 

Figure 4.5. Waveform of testing the cascaded inverting amplifier.

4.3.3 Testing for the Integrator

To test the integrator, the clocks shown in Figure 4.6 are applied and the switches are

set as follows:
MUX_S = 0; CMP_S1 = 0; SH__S1 = 0: SH__32 = 0;
The waveform shown in Figure 4.7 is generated and the inputs are set as:

INp = Vmid+0.1V; REFp= Vmid; REFn= Vmid

64

In Figure 4.7 channel 1 (top) is the reset (INT_SR), channel 2 is the clock (INT_CLKI),
channel 3 is the output of the integrator (INT_OUTp), and channel 4 (bottom) is the input
to the cascaded inverter amplifier (INT_Ap). It can be seen clearly that the integrator is
integrating the difference between its two inputs (INp and DAC_OUTp), and the
integrator output is increasing while the cascaded inverter amplifier input remains at
Vmid=780mV. This waveform matches the integrator simulation result as shown in
Figure 3.4, demonstrating the integrator operates correctly.

. i 5
SR —l ‘ . l ‘ ‘ ‘ ‘
o . .
l ’.

 

 

....--.u....o.— ...................

...-u...nun-......mun....—u...uuuuuuuIunu-u-un-n—u-u-n—uu-nn-Inuni—...”...u-u—nu-un

‘ [WIN 1‘“ "Vi :
i .......

.‘ fl'dlum'fm

u ‘JIIEI'I..1“.i
‘l’li‘il‘ l‘i-Illii‘

 

- ‘ . . . .
I'blr'lri’ ..................................... ‘r

Figure 4.7. Waveform when testing the integrator.

65

4.3.4 Testing for the Comparator

Because the inputs to the comparator could not be directly accessed, the integrator
was used to vary the inputs to the comparator, and then the output of the comparator was
examine. Figure 4.8 shows the clocks used to test the comparator. Other switches value

and input stimulus for testing the comparator are as follows:

MUX_S = 0; SH_S1 = 0; SH_SZ = 0;
INp = Vmid+0.08V; REFp= Vmid+0.2V; REFn= Vmid-0.2V;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

._.1—. i I i T—l‘: fill—ll

Figure 4.8. Clocks for testing the comparator.

Under this configuration, the output waveform is shown in Figure 4.9. Channel 1 is
the reset signal (INT_SR), channel 3 (next to top) is one input to the comparator
(INT_OUTp) and channel 4 is the other input to the comparator (INT_OUTn). Channel 2
(bottom) is the latched output of the comparator (FF_OUTp). It can be seen clearly that
when VINp > VINn, FF_OUTp = l, and when VINp < VINn, FF_OUTp = 0. This is
exactly the same as expected in Section 3.1.3. Further observation of the FF_OUTp pin
and the FF_OUTn pin shows that they always produce complementary outputs. The

comparator operates correctly.

66

..............
..........
...........
..........
.....

. I“

.i [i I] I‘M I
.....~II.1'-l’...... ......... I!

: . : , . . -I
. .
i ‘l'f'llfil I . .' . . . 5

l l
..............

I‘l‘ i’HI I I i I I MIN". I l I iiif'll‘flhiii’ig

II,’ . .

........................

o
.--..,..-...n ....-~ .................

 

Figure 4.9. Waveform testing the comparator.

4.3.5 Testing for the Sample and Hold (SaH)

To test the sample and hold, the integrator is kept running to vary the input to the
sample and hold. The input is sampled and held and the output is observed. Figure 4.10
shows the clock scheme for testing the sample and hold. Figure 4.11 shows the waveform
when testing the sample and hold. Channel 1 (top) is the reset signal (SH_SR). Channel 2
(bottom) is the clock of the sample and hold (SH_CLK1). Channel 3 is the output of the
comparator (INT_OUTp) and also the input to the sample and hold. Channel 4 is the
output of the sample and hold (INT_INlp). Test results show that the sample and hold
functions correctly but has noticeable offset error between the input signal and the output
signal. As observed in Matlab system behavior simulation, this offset error will greatly

degrade the resolution for algorithmic mode operation.

67

 

Figure 4.11. Waveform when testing the sample and hold.

68

4.4 System Testing
4.4.] l“-order 22A operation

For the chip to operate in 15t-order 2A mode, the clocks were generated as shown in
Figure 4.12. The integrator and comparator were kept run and the sample and hold was

shut off. The biasing and stimulus are set as:

VDD = 3.3 V;VB1 = 2.2 V; V132 = 2.0 V; VB3 = 1.4 V;
VPBl 1.7 V; VPBZ = 1.5 V; VNBl = 1.3 V; VNB2 = 1.1 V;
Vmid = 780 mV; VREF = 200 mV; Vin = 160 mV;

INp = Vmid+Vin; INn = Vmid-Vin;

REFp= Vmid+VREF; REFn= Vmid—VREF;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4.12. Clocks for 15t-order 2A operation.

Figure 4.13 shows a ISt-order 2A operation runs in 256 clock cycles (8-bit). Channel 1 is
the reset signal (INT_SR). Channel 3 is the output of the integrator (INT_OUTp).
Channel 2 is the latched output of the comparator (FF_OUTp), and channel 4 is the LSB

of the counter. The counter is implemented in the FPGA, and increases its value by one at

69

the end of each clock if the comparator output is 1. The counter value is displayed in the

LED display on the FPGA board, as shown in Figure 4.14.

 

Figure 4.14. The counter value displayed in the LED at the end of each conversion.

70

It can be seen from Figure 4.13 and Figure 4.14 that:

0 The integrator output has a similar shape as in the MATLAB system behavioral
simulation shown in Figure 2.4 and in the Cadence system level simulation shown in
Figure 3.17.

0 The latched comparator output goes to 0 every 10 clocks, which means the ratio of Is
over to overall clocks is 9/10. This corresponds to the input voltage value over
reference voltage value = (Vin+VREF)/(REFp-REFn) = 200mV+160mV / 2*200mV
= 0.9.

0 The LSB of the counter flips only when the latched comparator output is l. The
implementation of the counter is correct.

0 The displayed counter output is E6 in hex value. (E6/FF)h = (230/256)d = 0.898,
which is very close to the input voltage value.

All of the above suggests that the chip in ls'-arder 2A operation is functionally correctly.

Further testing and performance measurement shows that the lst-order 23A can achieve 10

bits resolution.

71

4.4.2 Hybrid Algorithmic 2A operation

Figure 4.15 shows the clock setup for the ADC chip operating in the Hybrid
Algorithmic 2A mode with 3 phases algorithmic conversion and 4 clocks of 2A
conversion in each phase. INT_SO goes to 1 at the end of each phase to generate the
residue. The residue is then sampled by the sample and hold and feed back to the input by

switch the MUX.

Reset! Initial 1st Phase 2nd Phase 3rd Phase Reset

p.-
P— -

SR'

 

 

SO

 

. I..- E.____

_ Flu—db

s1 4 l 1

 

 

52
52 _ . “,—

 

 

 

 

 

 

 

 

 

 

S1 I . I i I
S1_

 

l
l
l
l

52

 

 

SR i

 

 

 

51 a
s1_ .

 

 

i I
52 l 'L I I
52- : I 1 I

 

 

 

 

 

 

 

MUX_S I T . 3 l ‘
i I I ' I . ,

Figure 4.15 Clocks for Hybrid Algorithmic 2A operation

 

 

 

 

 

 

 

 

The biasing and stimulus is the same as in the Tit-order 21A operation. The waveforms for
Hybrid Algorithmic 2A operation are shown in Figure 4.16. Channel 1 is the reset signal

(INT_SR). Channel 4 is the output of the integrator (INT_OUTp) and channel 3 is the

72

output of the opposite integrator (INT_OUTn). Channel 2 is the clock of the sample and

hold (SH_CLK1). It can be seen from Figure 4.16 that:

0 In the first phase, the ADC runs in normal 15‘-order 2A mode. The integrator outputs
have the similar shape as in Figure 4.13.

0 In the second phase, the integrator outputs go high dramatically. Obviously the ADC

does not function correctly.

 

Figure 4.16 Testing waveform of Hybrid Algorithmic 2A operation

Possible reasons for the Hybrid Algorithmic 2A operation does not work well are:
0 The offset of the sample and hold phase added a common mode voltage at both the
positive half and negative half integrator outputs. This common mode error gets

integrated on both of the integrators, forming the second phase waveform in Figure

73

4.16

0 The small error between the input signal common mode and the analog ground (VMID)
gets integrated on the positive half and negative half integrators together, forming a
large common mode offset error at the end of first phase. This common mode error is
sampled and gets integrated again in the second phase. But since now the error is

large, the integrator outputs go high at a much faster speed, as shown in Figure 4.16.

The integrators are not differential, but rather are formed by two separate integrators.
Since there is no common mode cancellation scheme in the integrators, any offset in the
input will get integrated on both integrators‘at the same time. An improvement to the
current design would be to use differential integrator and add common mode cancellation

in the circuit. This should allow the ADC to function as expected.

74

REFERENCES

[l l] M. Burns, G. W. Roberts, An Introduction to Mixed-Signal Ic Test and Measurement,
Oxford University Press, 2001.

[12] J. Franca and Y. Tsivids, Design of Analog-to-Digital VLSI Circuits for

Telecommunications and Signal Processing, Chapters 9 & 12, Prentice Hall Inc.,
Englewood Cliffs, NJ, 1994.

75

Chapter 5
Conclusions

5.1 Achievements

This work has introduced a novel Hybrid Algorithmic 2A A/D topology that can
achieve real-time reconfiguration between 2A and algorithmic architectures to optimize
the trade off between its resolution and speed and to assist power management. Analysis
has demonstrated that by iteratively feeding back and resample the residual of a 2A
conversion, the behavior of the A/D converter approaches to an algorithmic conversion.
By varying the number and ratio of sampling and feedback cycles, the A/D converter is
capable of self-adjustment between a more ISA-like architecture (with higher resolution
and slower speed) and a more algorithmic-like architecture (with faster speed and lower
resolution).

A pseudo—differential circuit implementation of the Hybrid Algorithmic 2A A/D
converter was designed in switched-capacitor topology and fabricated in a in a standard
0.5um CMOS process. The prototype chip was tested to be fully functional. The A/D
converter can be configured in first-order EA mode to convert 8-bit resolution at 2 kHz, or
in algorithmic 2A mode to convert 4-bit resolution at 62.5 kHz. The analog circuits
consumes only 8.6uW during operation. The concept of the Hybrid Algorithmic 2A A/D

converter has been verified.

76

5.2 Possible Improvements
Future generations of the Hybrid Algorithmic 2A A/D converter could be improved
by addressing the following issues:
0 Employ a fully differential integrator rather than two separate integrators to
overcome the common mode voltage problem described in section 4.3.2.
0 Increase the drive capability of the comparator latch output to the chip pad frame.
The current version uses minimum sized transistors that created a bottleneck of
the chip operation speed.
0 Employ rail-to-rail voltage follower buffers to analog test pads for better

observation of the internal analog voltages.

77

   

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