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This is to certify that the
dissertation entitled

Multilevel Back-to-Back Converters
— Topologies and Control Strategies

presented by

Zhiguo Pan

has been accepted towards fulfillment
of the requirements for the

Ph. D. degree in Electrical Engineering

 

 

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DATE DUE

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2/05 p:lC|RC/DateDue.indd-p.1

- u -'-—._ l_ L..-

Multilevel Back-tdBack Converters
—— Topologies and Control Strategies

By

Zhiguo Pan

A DISSERTATION
Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of
DOCTOR OF PHILOSOPHY

Departn'lent of Electrical and Computer Engineering

2005

 

ABSTRACT

Multilevel Back-to-Back Converters

— Topologies and Control Strategies
By

Zhiguo Fan

The paper presents a detailed analysis of the charge balance mechanism using
five-level back-to—back system as an example. The analysis starts from the funda-
mental frequency switching. Based on the switching angles in the system, the charge
flowing into and out of each voltage junction are calculated and the charge balanc-
ing constraints are given. The optimized switching angles with minimum THD are
chosen.

Although the voltage balancing control in fundamental frequency switching can
successfully balance the dc bus voltage, the input and output current have relatively
high harmonic components. T we methods are proposed to reduce the harmonic in
the current waveforms. For the higher modulation index operation, selective harmon-
ics elimination PWM was implemented by adding more switching pulses. For the
Tower modulation index operation, voltage shifting method is proposed, which uti—
lizes the line-to-line redundancy. Simulation results showed that these two methods
can effectively reduce the harmonics.

The voltage balancing control is also extended to carried-based SPWM technique,
which is capable of eliminating all lower harmonics. A triplen harmonic offset voltage
is added to the sinusoidal reference voltage, which changes the average current. flowing
into or out of the inner junctions while keeps the output line—to—line voltage the same.

The effects and limits of the offset voltages are analyzed in detail. A novel carried-

based SPVV M with voltage balancing control is proposed.

A new multilevel converter topology is also proposed. The proposed topology
can significantly reduce the number of clamping diodes with a slightly increase in
the total devices rating of the switching devices. The rating ratio of the reduced
diodes and increased switching devices is 4:1. It will be the higher in the topology
with higher number of voltage levels.

In the rectifier side, the number of switching devices can also be reduced. A novel
simplified five-level rectifier which only requires two switching devices per phase leg
is proposed. The total devices rating required in the proposed topology is only one
fourth of those in the fully active rectifier. Furthermore, the total devices rating of
diodes is also reduced by one third. The control strategy for new topology is also
discussed. Although the new topology introduces some harmonics and doses not
have regenerative capability, it could be used as a cost-effective alternate for some
applications.

A five-level, three-phase back-to—back 10—kW converter prototype based on the
topology with reduced number of clamping diode is fabricated and experimentally
tested. The proposed voltage balancing control strategies are implemented. Experi-

mental results are shown to demonstrate the proposed control strategy.

Copyright © by
Zhiguo Pan
2005

ACKNOWLEDGMENTS

I want to express my sincere gratitude to my advisor, Dr. Fang Z. Peng, for his
guidance, encouragement and support during my graduate studies. His impressive
knowledge and technical skills have been a source of inspiration and a model for me
to follow.

I also want to thank my committee members, Dr. Hassan Khalil, Dr. Charles
MacCluer, Dr. Robert Schlueter and Dr. Elias Strangas, for inspiring classes, valu-
able advices, and for serving on my advisory committee.

I would also like to acknowledge all members of Power Electronics and Motor
Drive Laboratory. It is an honor to be part. of it and witness its growing. Especially
I would like to thank Fan Zhang, Jin Wang, and Suilin Wang for sharing with me
their practical experiences.

With much love, I thank my parents, Kuncai and Guoxiu, for their loving care
and unconditional support. This dissertation is their accomplishment as much as it
is mine.

Finally, and most importantly, I must thank my wife Yisheng, who has always
been there with her love, support, understanding and encouragement for all my

endeavors.

TABLE OF CONTENTS

LIST OF TABLES ix
LIST OF FIGURES x
1 Introduction 1
1.1 Background ................................ 1
1.2 Medium Voltage Drive .......................... 2
1.3 Multilevel Converter ........................... 3
1.4 Outline ................................... 3

2 Summary of Previous Works 5
2.1 Introduction ................................ 5
2.2 Multilevel Converter Topologies ..................... 6
2.2.1 Diode—Clamped Multilevel Converter .............. 7

2.2.2 Capacitor-Clamped Multilevel Converter ............ 10

2.2.3 Cascaded Multilevel Converter .................. 12

2.2.4 Generalized Multilevel Converter Topology ........... 14

2.3 Emerging Multilevel Converter Structure ................ 16
2.3.1 Hybrid Multilevel Cells ...................... 16

2.3.2 Asymmetric Multilevel Cells ................... 18

2.3.3 Multilevel DC—DC Converter ................... 19

2.3.4 Multilevel Converter with Reduced Count of Devices ..... 21

2.4 Multilevel Converter Control Strategy .................. 22
2.4.1 Selective Harmonic Elimination ................. 24

2.4.2 Carrier-based SPWM ....................... 25

2.4.3 Space Vector PWM ........................ 27

2.4.4 Definition of Modulation Index ................. 28

2.5 Back-to-Back Structure .......................... 31
2.6 Capacitor Voltages Balancing Techniques ................ 34
2.7 Summary ................................. 35

vi

3 Novel Voltage Balancing Control Method 36

3.1
3.2

3.3
3.4
3.5
3.6

3.7

3.8

Introduction ................................ 36
Voltage Balancing Control in Fundamental Frequency Switching . . . 37
3.2.1 Charge Balancing Analysis .................... 42
3.2.2 Simulation Results of Proposed Voltage Balancing Control . . 49
Effect of the Rectifier Modulation Index [W R .............. 55
Selective Harmonics Elimination PWM ................. 59
Voltage Shifting Method for Low Modulation Index Operation . . . . 63
Carrier-based SPWM Control ...................... 73
3.6.1 Control of Average-Inner-Junction-Current ........... 78
3.6.2 Voltage Balancing in the Carrier-based SPWM Control . . . . 83
3.6.3 Simulation Results of Carrier-Based SPWM Control ...... 87
DC Bus Voltage and Reactive Power Control .............. 94
3.7.1 DC Bus Stabilization ....................... 94
3.7.2 Input Reactive Power Control .................. 97
Summary ................................. 99

4 Multilevel Converter Topology with Reduced Number of Devices 100

4.1 Introduction ................................ 100
4.2 Multilevel Inverter with Reduced Number of Clamping Diodes . . . . 101
4.3 Multilevel Rectifier with Reduced Number of Switching Devices . . . 108
4.3.1 Replacing the Top-most and Bottom-most Devices ...... 108
4.3.2 Proposed Simplified F ive—level Rectifier ............. 110
4.4 Summary ................................. 115
5 Experimental Validation 118
5.1 Introduction ................................ 118
5.2 Hardware Implementation ........................ 118
5.3 DSP Control System ........................... 123
5.4 Experimental Results ........................... 127
5.4.1 Voltage Balancing Control with Fundamental Frequency
Switching ............................. 127
5.4.2 Selective Harmonic Elimination PWM Control ......... 133
5.4.3 Voltage Shifting Method in Low Modulation Index Operations 135
5.4.4 Carrier-based SPWM Control .................. 139
5.4.5 Simplified Five-level Rectifier .................. 144

Summary ................................. 145

6 Conclusions and Recommendations 148
6.1 Contributions ............................... 148

6.2 Recommendations for Future Work ................... 149

Reference 151

viii

2.1

2.2

2.3

3.1
3.2

4.1

4.2
4.3

4.4

5.1
5.2

5.3

LIST OF TABLES

Output voltages and corresponding switching states of a five-level

diode-clamped converter .......................... 8
Output voltages and corresponding switching states of a. five-level

capacitor-clamped converter ........................ 11
Maximum output voltages for different control strategy ........ 31
Optimal switching angles for A4 R = 0.9 .................. 47
Switching angles for SPWM waveform ................. 73

Output voltages and corresponding switching states of the proposed
five-level converter topology. ....................... 104
Comparison of the proposed topology and the traditional topology. . 106

Comparison of the proposed seven-level topologies and the traditional

topology .................................. 108
Detailed comparison of three different front-end topologies ...... 116
THD of the waveforms at rated output power. ............. 129
Comparison of THD of fundamental frequency switching and PWM

control (MR 2 0.8, M, = 0.7) ...................... 135
Current THD of carrier-based SPWM control ............. 140

ix

2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18

3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9

LIST OF FIGURES

Converter phase legs with different number of levels ..........
Diode-clamped multilevel converter topologies ..............
Capacitor-clamped multilevel converter topologies ............

Cascaded multilevel converter topology ..................

Generalized multilevel converter topology and its deducing topologies.

Cascaded multilevel converter using three-level converter cells. . . . .
Active neutral-point-clamped converter ..................
Multilevel dc-dc converter without inductors ...............
Simplified multilevel dc—dc converter. ..................
Vienna rectifier ...............................
Reduced-devices-count rectifier topologies 1. ..............
Reduced-devices-count rectifier topologies 2. ..............
N -level staircase voltage waveform. ...................
Carrier-based SPWM output waveform for a five-level converter. . . .
Space-vector diagrams. ..........................
Relationship between output voltage and reference voltage .......
Series-parallel connection of the back-to-back system. .........

F ive—level diode-clamped back-to-back converter structure. ......

Equivalent circuit of a. five-level converter. ...............
Fundamental frequency switching of five-level converter .........
Active currents flowing out of the capacitor junctions ..........
Reactive currents flowing out of the capacitor junctions .........
Five-level diode-clamped back-to—back converter structure. ......
Voltage and current waveforms of the rectifier and inverter side.

Capacitor junction equivalent circuit. ..................
Optimal switching angles for M R = 0.9 ..................
Simulation results of f1111(l8111(‘Ilt£—1.l frequency control for A I H = 0.9 and

M, = 0.9. .................................

6

7
10
13
15
17
19
20
21
22
23
23
25
26
28
29
32
33

38
39
40
41
43
44
48

3.10

3.11

3.12

3.13

3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
3.25
3.26
3.27
3.28

3.29

3.30
3.31
3.32
3.33
3.34
3.35
3.36

3.37
3.38
3.39

Simulation results of fundamental frequency control for MR 2 0.9 and

M 1 = 0.8. ................................. 51
Simulation results of fundamental frequency control for NR = 0.9 and

M 1 = 0.5. ................................. 52
Simulation results of fundamental frequency control for 111,; = 0.9 and

M1 = 0.3. ................................. 53
Simulation results of fundamental frequency control for M R = 0.9 and

M I = 0.1. ................................. 54
Minimal T HD of the voltage balancing control output. ........ 55
THD vs. 611 for M1 = 0.6 ......................... 58
Comparison of THD for different M R . ................. 58
Extension of the fundamental frequency switching to PWM. ..... 59
Line-to—line voltage waveforms and their spectra when M 1 = 0.7. . . . 60
THD performance of the selective harmonics elimination PWM. . . . 61
Simulation results of SHE-PWM control for IV! R = 0.8 and 1W, = 0.7. 62
Comparison of voltage waveform when M 1 = 0.5. ........... 63
Line voltage redundancy of three-phase systems ............. 64
Offset voltage for harmonics optimization. ............... 66
Phase voltage after the offset voltage is added .............. 66
Offset voltage when 1W, is less than 0.4 .................. 68
Optimized output voltage waveform when 1W; = 0.3 ........... 69
THD performance of the voltage shifting optimization. ........ 70
Simulation results of voltage shifting method for M R = 0.9 and M 1 =

0.5 ...................................... 71
Simulation results of voltage shifting method for M R = 0.9 and M 1 =

0.3 ...................................... 72
The five—level SPWM output voltage and inner junction current. . . . 74
Average-inner-junction—currents for different M and mf. ....... 77
Inner junction current for a given reference voltage. .......... 79
Offset voltage with minimum inner junction current ........... 81
Offset voltage with maximum inner junction current. ......... 83

Relationship of average-inner-junction-current [(2.09 and pulse width W 85

Relationship of average-inner-junction-current I ’ and modulation in-

dex M ....................... 9 ............ 86
Required pulse width for 1"“,g = 0.3 ................... 87
Offset voltage waveforms for M = 0.75 .................. 89
Offset voltage waveforms for M = 0.5. ................. 89

xi

3.40 Offset voltage waveforms for M = 0.25 ........... ' .......
3.41 Offset voltage waveforms for M = 0.1. .................
3.42 Simulation results of SPWM control for MR 2 0.75 and M, = 0.5. . .
3.43 Simulation results of SPWM control for [HR = 0.75 and M 1 = 0.25.

3.44 Simulation results of SPWM control for M R = 0.75 and M, = 0.1. . .
3.45 Power flow of the back-to—back system. .................
3.46 Equilibrium point of dc voltage. .....................
3.47 Feed back control of the voltage of the dc bus. .............
3.48 Phasor diagram of leading, in phase and lagging current. .......
3.49 Optimal switching angles of different A! R. ...............

4.1 Diode—clamped N-level converter phase leg ................
4.2 Reduction of the clamping diodes in the multilevel converter ......
4.3 Proposed five-level converter topology with reduced number of clamp-

ing diode. .................................
4.4 Combination of three multilevel converter cells. ............

4.5 Two different topologies of revised seven-level converter. .......

90
90
91
92
93
94
96
96
97
98

101
102

107

4.6 F ive—level rectifier phase leg with reduced number of switching devices. 109

4.7 Space vector diagram of five-level rectifier. ...............
4.8 Proposed simplified five-level rectifier ...................
4.9 Fundamental frequency switching for the proposed five-level rectifier.

4.10 Simulated dc bus voltages for the proposed rectifier ...........
4.11 Simulated ac waveforms for the proposed rectifier ............
4.12 Gate drive signal for the switch SP3 ....................
4.13 PI control for the SPWM voltage balancing. ..............

5.1 System layout of the prototype. .....................
5.2 Compact intelligent power module. ...................
5.3 Picture of the prototype ..........................
5.4 Layout of the phase leg board .......................
5.5 DSP board based on Analog Devices ADSP-21065L ...........
5.6 Control Diagram of the fundamental frequency switching control.
5.7 Error compensation of the switching angles. ..............
5.8 Block diagram of voltage error compensation feedback control. . . . .
5.9 DC bus voltages for flip—10.9 and 1111209 ................
5.10 AC waveforms for .\IR=0.9 and AII=0.9. ................
5.11 Input power factor for Mgr—0.9 and 1111209 ...............
5.12 DC bus voltages for 11],,»209 and 1W;=0.8 ................

xii

110
111
112
113
114
114
115

120
121
122
123

. 124

125
126
128
128
129
130

5.13
5.14
5.15
5.16
5.17
5.18
5.19

5.20
5.21
5.22

5.23
5.24

5.25
5.26
5.27
5.28
5.29
5.30
5.31
5.32
5.33
5.34
5.35
5.36

AC waveforms for AIIR=0.9 and 111,208. ................ 131
Input power factor for M 320.9 and M [20.8 ............... 131
DC bus voltages for MR=0.9 and lit/[=05 ................ 132
AC waveforms for A/IR=0.9 and M,=0.5. ................ 132
Input power factor for NI R=0.9 and Ill/1:05 ............... 133
AC waveform of SHE-PWM for Ill/320.8 and A1120]. ........ 134
AC waveform of fundamental frequency switching for MR=08 and

IV! [:07 ................................... 134
DC bus voltage waveform of voltage shifting method. ......... 136
AC waveform of voltage shifting method for 1W 3 = 0.9 and A11=0.5. . 137

AC waveform of fundamental frequency switching for 1W 3 = 0.9 and
M1=0.5 ................................... 137
AC waveform of voltage shifting method for [W R = 0.9 and M 1:03. . 138
AC waveform of fundamental frequency switching for M R = 0.9 and
M 1:03 ................................... 138

AC waveform of voltage shifting method for 1W 3 = 0.9 and [W 1:01. . 139
Transit performance of DC voltage waveforms of the SPWM control. 141
Transit performance of AC waveforms of the SPWM control. ..... 141
AC waveforms of SPWM control for M R = 0.75 and M1 = 0.75. . . . 142
AC waveforms of SPWM control for M R = 0.75 and M1 = 0.6 ..... 142
AC waveforms of SPWM control for M R = 0.75 and M I = 0.45. . . . 143
AC waveforms of SPWM control for M R = 0.75 and M1 = 0.3 ..... 143
AC waveforms of SPWM control for M R = 0.75 and M1 = 0.15. . . . 144
Simplified five-level rectifier simulated from fully active recitfier. . . . 145
DC waveforms of the proposed five-level rectifier. ........... 146
AC waveforms of the proposed five-level rectifier. ........... 146
AC waveforms of the proposed five-level rectifier with SPVVlVI control. 147

xiii

CHAPTER 1

Introduction

1 . 1 Background

Since its introduction in the mid-50s, power electronics has consistently changed the
way we generate, transmit and utilize the electricity. Especially in the last three
decades, it has been finding wider application in industry, commercial, residential,
consumer electronics, traction and other areas. Today, it is safe to say that wherever
you can find electricity, you can find the use of power electronics.

One of the most important aspect of power electronics is the energy saving. For
example, it is estimated that in this country roughly 60 percent of generated electrical
energy is consumed in electrical machine drives and 20 percent is consumed in light.-
ing. Adjustable speed drive and high frequency fluorescent lighting can significantly
contribute to energy saving in these areas [1].

Most of electrical drives are used in pumps, blower and compressor-type load.
It has been well established that the use of adjustable speed drive (ASD) can save
considerable amount of energy compared with the throttle control with fixed-speed
drive. As power electronics equipments become cheaper and energy expenses keep
rising, more and more electrical motors will be driven by power electronics converter.

The use of ASD can replace the mechanical transmission used in the industry before.

W’ithout moving mechanical parts, ASD can lower the maintenance cost and increase
reliability. Nowadays, diesel-electrical hybrid drives are widely used in locomotives
and ships. The ASD enables the soft start of high power electrical motors, which
replaces the complex start equipment. The ASD can also improve power factors of
driving systems or provide regeneration ability.

The early ASD was implemented by dc motor and thyristor rectifier. Dc motors
have the disadvantages of high cost, high rotor inertia and maintenance problems
with commutators and brushes. Commutators and brushes, in addition, limit the
machine speed and peak current, cause EMI problems, and do not permit a machine
to operate in dirty and explosive environments [2].

From the mid-60$, the new control methods such as pulse-width modula-
tion(PWM), vector control, field-oriented control and direct torque control signif-
icantly improve the control performance of the ac drives. Nowadays ac drives are

progressively replacing the dc drives.

1.2 Medium Voltage Drive

In the medium-voltage drive field, the thyristor and GTO-based current source in-
verter used to dominate. Although a voltage source inverter has a lot of advantages
such as reduced line harmonics, better power factor, substantially smaller filters,
and a higher system efficiency, it only became practical after the recent availability
of high voltage insulated gate bipolar transistors (IGBT).

The introduce of IGBT in the early 1980’s has changed the trend of power elec-
tronics. The power rating and performance of the IGBT are continuously improving.
The IGBTs with rating of 3.3 kV and 1.2 kA are commercial available, and IGBTs
with 6.6 kV and 0.6 kA have been introduced. These IGBTs make it possible to

increase the PWM switching frequency from 500 to 1500 Hz or more to minimize

harmonic currents at both the input and output while simultaneously achieving in-

verter efficiencies of 98% or higher [3—7].

1.3 Multilevel Converter

Another important. development in the medium voltage drive is the multilevel con-
verter topology. The unique topology of multilevel converters allow them to reach
higher voltage rating without the use of step-up transformers or series connection of
switching devices.

The multilevel converter synthesizes the staircase output voltage which ap—
proaches the sinusoidal waveform with minimum harmonics. In order to satisfy
the same harmonics requirement, the frequency needed by the multilevel converter
is much lower than the conventional converter. Therefore the multilevel converter
can achieve higher efficiency.

The multilevel converters also have lower dV/dt. It has been found recently that
the high dV/dt in the high-power PWM converter can induce corona discharge and

lead to bearing or winding insulation failure.

1.4 Outline

In this thesis, a multilevel converter system for motor drives is developed. The
proposed converter is based on a diode-clamped back-to—back structure.

Chapter 2 presents a review of the literature on different multilevel converter
topologies. Three different topologies are discussed: diode-clamped, flying capac-
itor, and cascaded, with their operation principles . This chapter also includes a
description of the back-to—back structure.

Chapter 3 presents the challenge of implementing the diode-clemiped multi-

level converter — voltage unbalancing of the dc bus. The detailed capacitor
charge/discharge mechanism is given. A voltage balancing control method is then
proposed based on the analysis. The improvements of low modulation index opera-
tion based on PWM control and line-to-line voltage redundancy are also proposed.
Simulation results of all proposed control methods are provided.

Chapter 4 presents a revised multilevel topology with reduced number of devices.
The proposed topology reduces the number of clamping diodes. Another new topol-
ogy which reduces the number of switching devices is also proposed, along with the
new control methods.

Chapter 5 presents the experimental results for the proposed control methods.
The experimental results are based on a 10-kW scaled-down prototype.

Chapter 6 concludes this thesis. Contributions are summarized. The plans for

the future work are given.

CHAPTER 2

Summary of Previous Works

2.1 Introduction

This chapter presents a review of the technical literatures regarding the development
of multilevel converter topologies and control strategies. Three major multilevel
converter topologies are discussed: diode-clamped, capacitor-clamped, and cascaded.
Their main features and operation principles are explained, and the advantages and
disadvantages of each topology are outlined. The generalized multilevel converter
topology and several newly emerged multilevel converter topologies are also included.

This chapter also covers the control methods been used in the multilevel convert-
ers including: selective harmonic elimination, carrier-based multilevel PWM, space
vector PWM, and space vector control.

In addition, a widely used converter configuration, back—to—back structure, and
its advantage/ disadvantage are discussed. At last, the voltage unbalance problem is
addressed, and the voltage balancing control methods proposed in previous works

are also included.

CJ'I

 

 

 

 

 

 

 

 

V _l__—
V dc ,--\
du_
4x
Vdc ‘—
P.%F Vdc ([ :
a Z:
l Vdc_L
0 0 0
(a) (b) (C)

Figure 2.1. Converter phase legs with (a) two levels, (b) three levels, and (c) n levels.

2.2 Multilevel Converter Topologies

In the traditional two—level converter topology, the output is connected to either the
positive or the negative dc bus through switching devices, which generates an output
voltage with only two levels. Multilevel converters can generate voltage waveforms
with more steps. Figure 2.1 shows a schematic diagram of one converter phase leg
with different numbers of level, in which the action of the power semiconductor
devices is represented by an ideal multi-select switch with different positions.

Considering that n is the number of the levels of the phase voltage output by
each phase leg, as shown in Figure 2.1 (c), the number of levels in the line-to—line
voltage is 2N — 1.

As the number of levels increases, the output voltages have more steps, which
approach the sinusoidal waveform with reduced harmonic distortion. Bhagwat pro-
posed a. generalized topology based on bidirectional switches consisting of two anti-
paralleling thyristors in 1983 [8]. However. the semiconductor switches may have

the different voltage stresses. The total device rating is very high because the up—

(i

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2.2. Diode-clamped multilevel converter topologies. (a) Three-level. (b)
Five-level

per/ lower most switch may be required to sustain the whole dc voltage, which limits
the usage of the topology in the higher voltage application. Therefore, several topolo-

gies have been proposed to reduce the device rating in the multilevel converter.

2.2.1 Diode-Clamped Multilevel Converter

The multilevel concept starts with the neutral point clamped inverter, proposed by
Nabae in 1981 [9]. The topology of the neutral point clamped inverter is shown in
Figure 2.2 (a). In this circuit, the dc bus voltage consists of two capacitors, Cl and
C2, in series. The center tap of the two capacitors is defined as the neutral point.
12.. Two diodes DP] and D,” clamp the switch voltage to half the level of the dc
bus voltage. Switches SP1 and S,” are con’iplimentary switches. At any time, one

and only one switch out of the two switches is turned on. Same for Switches SN

Table 2.1. Output voltages and corresponding switching states of a five—level diode-
clamped converter.

 

 

 

 

 

 

Output v00 SP1 SP2 SP3 SP4 Sn] S712 S113 87,4
Vdc 1 1 1 1 0 0 0 0
3Vdc/4 0 1 1 1 1 0 0 0
Vdc/ 2 0 0 1 1 1 1 0 0
de/4 0 0 0 1 1 1 1 0
0 0 0 0 0 1 1 1 1

 

 

 

 

 

 

 

 

 

 

 

and Sng. The output voltage 2100 has three levels: Vdc, Vdc / 2 and 0. When switches
SP1 and 5102 are turned on, the output voltage is Vdc; when switches SM and Sn; are
turned on, the output voltage is 0; and when switches Sn] and 5102 are turned on,
the output voltage is Vdc/ 2. The neutral point clamped converter is essentially a
three—level diode-clamped converter.

The diode-clamped multilevel topology was extended to higher number of levels
by Choi in 1991 [10]. An n-level diode-clamped converter typically consists of n — 1
capacitors with same voltage value on the dc bus and n — 1 pairs of complimentary
switching devices in series. Figure 2.2(b) shows a five-level diode-clamped converter
in which the dc bus consists of four capacitors: C1, C2, C3 and C4. Assuming the dc-
bus voltage is Vdc, the voltage across each switching device is Vdc / 4. There are four
pairs of complimentary switches, (SP1, Sm), (Sp-2, SW2), (SP3, Sn3), and (SP4, S,,.;).
The voltage outputs and their corresponding switch states are given in Table 2.1,
where “1” means that the corresponding switch is turned on, and “0” means turned
off.

Although each active switching device is only required to block a voltage level of
Vac/(n — 1), the clamping diodes need to have (.lifferent voltage ratings for reverse
voltage blocking. Taking BM in Figure 2.2(b) as an example, when the output.

voltage is 0, all lower devices Sn] ~ Sm are turned on, Dnl needs to block three

capacitor voltages, or 3Vdc / 4. Similarly. Dp3 also needs to block 3Vdc / 4, ng and ‘Dng
need to block Vdc / 2, and DPI and D,,;; need to block Vdc / 4. Assuming that the voltage
ratings of all clamping diodes are the same as the ratings of the switch devices, Dnl
and DPI require three diodes in series. Therefore the number of diodes required
for each phase will be 12. For a N-level converter phase leg, the total number of
clamping diodes required will be (N — 1) x (N —— 2) . This number represents a
quadratic increase in N. When N is sufficiently high, the number of diodes required
will make system impractical to implement [11].

Diode-clamped multilevel converters have been used in adjustable speed drive for
high power medium voltage (2.4 kV to 13.8 kV) [12-14] and static var compensation
[15—17]

The main advantages and disadvantages of multilevel diode-clamped converters
are [11,18]:

Advantages:

All the phases share a common dc bus, which minimized the capacitance re-

quirements of the converter;

The capacitors can be precharged as a group;

Easy to build back—to—back topology;

Efficiency is high for fundamental frequency switching.
Disadvantages:

0 Real power output is difficult because the intermediate dc levels will tend to

overcharge or discharge without precise monitoring and control;

0 The number of clamping diodes required is quadratically related to the number

of level, which can be cumbersome for higher number of levels.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2.3. Capacitor-clamped multilevel converter topologies. (a) Three-level. (b)
F ive-level.

2.2.2 Capacitor-Clamped Multilevel Converter

Capacitor-clamped multilevel converters, also called flying capacitor multilevel con-
verters [11] or multicell converters [19,20], are multilevel converter using capacitors
instead of diode to clamp voltage. Figure 2.3(a) illustrates a three-phase capacitor-
clamped converter. A clamping capacitor Cl is added instead of the clamping diodes.
Similar with the diode-clamped topology, when switches SP1 and SP2 are turned on,
the output voltage is Vdc; when switches SM and 5,12 are turned on, the output volt-
age is 0. But there are two switch states that output voltage Vac/2.. one is switches
SP1 and Sng are turned on, the other is SP2 and SR1 are turned on. Clamping capac-
itor Cl is charged when SP1 and Sn] are turned on, and is discharged when Sng and
SP2 are turned on. The charge of C1 can be balanced by proper selection between

two switch states.

10

Table 2.2. Output voltages and corresponding switching states of a five-level
capacitor-clamped converter.

 

 

 

 

 

 

Output ’Uao Capacitor Path SP1 SP2 SP3 SP4 Sn] 87,2 SR3 5714
Vdc V04 I I I I 0 0 0 0
V03 0 I I I 0 0 0 I
3Vd /4 V04 — V03 + V02 I 0 I I 0 O I 0
C VC4 —- VC2 + V(71 1 I 0 I 0 I 0 0
V04 - VCI I I I 0 I O 0 0
VC‘Q 0 0 I I 0 0 I I
VC3 — VC1 0 I I 0 I 0 0 I
Vd /2 V04 - V02 I I 0 O I I 0 I
C V03 —- V02 + V01 0 I 0 I 0 I 0 0
V04 - V03 + V02 — V01 I 0 I 0 I 0 I 0
V04 - V03 + VCl I 0 0 I 0 I I 0
VC1 0 0 0 I 0 I I I
Vdc/4 VC2 — VCl 0 0 I 0 I 0 1 1
V03 — V( 2 0 I 0 0 I I 0 I
V04 — V( 3 I 0 0 0 I I I 0
0 0 0 0 0 0 I I I I

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2.3(b) shows a five-level capacitor-clamped converter. Three clamping
capacitors, Cl, Cg, and (73, whose voltage are Vac/4, VdC/2, 3Vdc/4, respectively.
are used to replace the clamping diodes in the diode-clamping topology. The four
complimentary switches pairs are changed to (SP1, SM), (SP2, 8,,3), (SP3, 8,12) and
(SP4, Sm). The voltage synthesis in a five-level capacitor-clamped converter has more
flexibilities than three-level converter.

Table 2.2 shows a list. of the outputs and all corresponding switching states.
In Table 2.2, the capacitors following positive signs are in discharging mode, while
those following negative signs are in charging mode. By proper selection of capacitor
combinations, it is possible to achieve charge balance of the capacitors.

Similar to the diode-clamping topology, the capacitor-clamped topology requires

capacitors with higher voltage rating to clamp the voltage. Assuming that the voltage

11

ratings of the clamping capacitors are the same as that. of the main dc bus capacitors.
an N-level converter requires a total of (N — 1) x (N — 2) / 2 clamping capacitors per
phase leg in additional to N — 1 main dc-bus capacitors.

The main advantages and disadvantages of multilevel capacitor-clamped convert-
ers are: [11,18]

Advantages:

0 Phase redundancies are available for balancing the voltage levels of the capac-

itors;
0 Real and reactive power flow can be controlled;

0 The large number of capacitors enables the converter to ride through short

duration outages and deep voltage sags.
Disadvantages:

Control is very complicated;

Switching frequency and switching losses are higher;

The large numbers of clamping capacitors are both more expensive and bulky

than clamping diodes in the diode-clamping topology;

Precharging all the capacitors to the voltage levels at startup is complex.

2.2.3 Cascaded Multilevel Converter

Another widely used multilevel converter topology is cascaded multilevel converter,
which is a series connection of single-phase H—bridge inverters with separated dc
sources. Figure 2.4 shows the circuit for one phase leg of a nine—level converter
with four cells in each phase. Each cell is a single-phase full-bridge inverter which

generates voltages with three output levels: +Vdc, 0 and —Vdc. The output phase

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C 5,13. 5,. a
1:: v o
Vac S 1%} S 1 I
12 14
C 5,,ng S23J
2—_ V
f? 2
a as
5311(3) S33J
C,J_ ,,
/'\ 3
V4? 532-94} 534-1
C MIG 3,,1
4:: ”4 j,
Vdc SQUQ 844-]
V
1
’ Li 1

 

 

 

Figure 2.4. Cascaded multilevel converter topology.

13

voltage is synthesized by the sum of the four outputs, i.e. 11110 = v1 +112 + 113 + 114. The
resulting output ac voltage swings from —4Vdc to +4Vdc with nine levels. Therefore
the number of levels in the output phase voltage N in a cascaded converter is defined
as N = 2s + 1, where s is the number of separated dc sources.

Cascaded multilevel converters have been used in adjustable speed drive [21—23],
electric hybrid vehicle [24] and static var compensation [25—27].

The main advantages and disadvantages of cascaded multilevel converters are
[11,18k

Advantages:

o The least number of components is required among all multilevel converter

topologies to achieve the same number of voltage levels;

0 Modularized circuit layout and packaging is possible because each level has the

same structure;

0 Since all multilevel cells are identical, rotation can be used to balance the

output power and power loss of each cell.
Disadvantages:

0 Isolated dc sources are required for real power conversions.

2.2.4 Generalized Multilevel Converter Topology

Peng proposed a generalized multilevel converter topology in 2001. The existing
multilevel converters, such as diode-clamped and capacitor-clamped multilevel con-
verters, can be derived from this generalized topology. 1\‘Ioreover, the generalized mul-
tilevel converter provides a true multilevel structure which can balance each dc. volt-
age level automatically at any number of levels regardless of active or reactive power

conversion without any auxiliary circuits, thus in principle providing a con‘iplete

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(d) (6)

Figure 2.5. Generalized multilevel converter topology and its deducing topologies.

multilevel topology that. embraces the existing multilevel converters [18.28]. F ig-
ure 2.5(a) illustrates the generalized five-level converter. Figures 2.5(b)-(e) illustrate
some topologies that can be deduced from the generalized topology. Figures 2.5(b)
shows that a novel diode-clamped topology can be deduced by removing all clamping
capacitors and replacing all inner clamping switches by clamping diodes. This diode
clamping topology solves the diodes series problem of the conventional diode clamp-
ing inverter. In the new structure, not only the main switches are clamped by the
clamping diodes, the clamping diodes are also clamped mutually by themselves [29].
The original diode-clamped topology can be obtained by swapping the diode clamp-
ing paths, as shown in Figures 2.5(c). Similarly, the capacitor-clamped topology can
be deduced by eliminating all inner clamping switches, as shown in Figures 2.5(d).
Figures 2.5(e) shows a novel active neutral-point-clamped multilevel converter [30],
which will be discussed in next section, can also be deduced from the generalized

topology.

2.3 Emerging Multilevel Converter Structure

2.3.1 Hybrid Multilevel Cells

Recently, several hybrid multilevel topologies have been introduced. One is to replace
the H-bridge inverter in a cascaded multilevel inverter by multilevel diode-clamped
or capacitor-clamped inverters [31, 32]. By doing this, the amount of separated dc
sources can be reduced. Figure 2.6 shows the a nine—level cascaded inverter phase leg
implemented by diode—clamped three-level inverters. When the H-bridge inverters
are used, four isolated dc sources are required for each inverter cell, as shown in
Figure 2.4. If three—level inverters are used, the number of voltage level is doubled

for each cell, therefore only two cells are needed, which requires only two isolated dc

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J J
V ’1 -\
dc J J
a
fit)
J J
J J
J J
J J
n
O
J J
Vdc
’l‘
J J

 

 

Figure 2.6. Cascaded multilevel converter using three-level converter cells.

source. Obviously, the diode-clamped three—level inverter cells can be replaced by
capacitor-clamped cells.

Barbosa proposed an active neutral-point-clamped multilevel converter topology
based on the combination of neutral-point-clamped inverters and capacitor-clamped
inverters [30]. The proposed concept is shown in Figure 2.7(a), which is an arrange-
ment for three-level inverters connected in series. Two of such subsystems are con-
nected in parallel with the dc-link capacitors. The first. subsystem is comprised of
85, 86, Sg, Sm, and ('2. while the second subsystems is comprised of 57. 5'8. SI],

81-2, and C3. A third subsystem (SI, 32, S3, S4. and (71) is then used to connect

17

 

the converter to the output phase. The concept is similar to the generalized P3C
multilevel inverter in [28]. However, the topology is further simplified by eliminating
all capacitors except C1, as shown in Figure 2.7(b). The proposed active neutral-

point-clamped multilevel converter has following advantages:
0 Eliminates the extensive usage of clamping diodes;

o Requires only one clamping capacitors, while still keeps the capability to bal-

ance the dc bus voltages.

0 Limits the switching frequency of the outer and clamping switches (85, Se, S7,
5'8) to the fundamental frequency of the output voltage even with the PWM

output voltage waveforms.

2.3.2 Asymmetric Multilevel Cells

In previous analysis, all the voltage levels of the cascaded multilevel inverter cells
are the same. However, it is possible to have different voltage levels among the cells
[33—36]. In [33], the two dc-bus voltages are configured as 2:1, therefore the inverter
has seven output voltage levels instead of five levels in the symmetric configuration.
If the two dc-bus voltages are configured as 3:1, the number of output voltage levels
will be further increased to 9, while the number of the isolated dc sources required
is still 2.

Analysis of asymmetric multilevel inverters reveals that “big cells”, which have a
higher voltage, are usually operated with a lower switching frequency, whereas “small
cells”, which have a. lower voltage, are operated with a higher switching frequency.
It can be further identified that “big cells” deliver mainly active power, whereas the
“small cells” deliver mainly reactive power. This makes it possible to replace the

isolated dc sources in “small cells” by capacitors [37 39]. By doing that, the inverter

18

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2.7. Active neutral-point-clamped converter.

avoid a larger number of isolated voltage sources, while keeping a higher number of

output voltage levels and lower voltage harmonics.

2.3.3 Multilevel DC-DC Converter

The multilevel topology can also be used in dc-dc applications. The phase legs in
the full-bridge phase-shift-modulated dc-dc converter can be replaced by a three-level
converter [40,41]. With phase-shift operations, this circuit has inherent soft-switching

capability.

19

 

 

l
r...
\l I

 

 

\I
I

out

e—cV —>
\I
II
\I
ll

 

 

\l

 

 

Er

 

 

 

 

 

 

 

Figure 2.8. Multilevel dc—dc converter without inductors.

Based on the generalized multilevel inverter structure, Peng has proposed a four-
level dc—dc converter, as shown in Figure 2.8 [42]. The most unique feature of this
topology is that it eliminates the use of magnetic components. Therefore it can
achieve more compact size, lighter weight, and higher efficiency. It also provides the
possibility of integrating all components into one power IC module. The four-level
can be further simplified, as shown in Figure 2.9 [43]. The new topology can be seen
as one phase leg of a four-level capacitor-clamped inverter. However, the phase leg
outputs constant dc voltages instead of ac staircase voltages in the previous analy-
sis. The redundancy of the capacitor-clamped structure has been used to balance
the voltage across each capacitor. Power loss analysis and other derivation of this

topology has been discussed in [44,45].

20

 

\I
II

\I
ll

 

 

\I
II
\I
ll
\1
II

V

 

 

\L

ll

 

a
\I
II

I—

 

 

 

 

 

‘————~.V —>
\I
If

 

Figure 2.9. Simplified multilevel dc-dc converter.

2.3.4 Multilevel Converter with Reduced Count of Devices

Despite the advantages of the multilevel converter discussed before, wider applica-
tions of multilevel converters are limited by the large number of devices and difficulty
to balance dc bus voltages. The large number of devices not only increases the com-
plexity and cost of the system, but also makes it difficult to layout the system.

Some simplified topologies with reduced number of devices has been proposed.
Most of them are used as multilevel active rectifiers that do not require regenerative
capability. A three-level simplified rectifier, also called Vienna rectifier is shown in
Figure 2.10 [46].

Figure 2.11(a) shows a similar reduced-devices—count three-level rectifier [47].
This topology can be extended to higher number of voltage levels, as four-level recti—
fier shown in Figure 2.11(b). The general idea of the reduced-devices—count rectifier
is that the uppermost and lowermost switching devices in the multilevel structure

may not be necessary for rectifier operation. Therefore, another reduced-devices-

21

 

 

\I
ll

 

 

\I
ll

 

 

 

Figure 2.10. Vienna rectifier.

count multilevel rectifier is introduced [48], as shown in Figure 2.12. Although the
performance and the number of devices are the same for both topology, there is a ma-
jor difference between the total devices ratings. Although the circuit in Figure 2.12
has higher total diodes ratings than that in Figure 2.11, the total switching devices
ratings in Figure 2.12 is lower than that in Figure 2.11, especially when number
of voltage level is higher than three. Since the switching device is more expensive
and more difficult to be connected in series, the circuit in Figure 2.12 has more

advantages.

2.4 Multilevel Converter Control Strategy

The control methods used in multilevel converters can be divided into two cate-
gories according to the switching frequency: fundamental frequency switching and
pulse width modulation(PWM). In the fundamental frequency switching, the switch
switches one or two times during one fundamental cycle of the output voltage, gen-
erating a staircase waveform. The switching angles in the fundamental frequency

control usually chosen to eliminate or minimize selected harmonics. Two most pop-

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(b)

Figure 2.11. Reduced-devices-count rectifier topologies 1.

 

 

”\Vdc

 

 

 

 

 

 

 

 

 

 

 

Figure 2.12. Reduced-devices-count rectifier topologies 2.

23

ular control methods in traditional converter, carrier—based sinusoidal pulse width
modulation(SPWM) and space vector PWM, have also been extended to multilevel

converters.

2.4.1 Selective Harmonic Elimination

From the staircase waveform shown in Figure 2.13, the amplitude of any harmonic: of
the waveform can be calculated by applying Fourier series analysis. Assuming all the
voltage levels are equal and 01;, is the kth switching angle of the staircase waveform,

the nth harmonic can be expressed as

21,, == 54; 2W cos(nak)]. (2.1)

k=l

With m switching angles, it is possible to eliminate up to m—l harmonic contents.
Usually, the most significant low-frequency harmonics are chosen for elimination. In
the cascaded seven-level converter, the three switching angles can be chose so that
the 5th and 7‘“ harmonics can be eliminated [49]. Optimization techniques have also
been introduced. The optimization starting point is obtained using a phase-shift
harmonic suppression approach. Based on that, another less computationally de-
manding harmonic suppression technique, called a mirror surplus harmonic method,
is proposed for five-level inverters [50].

Resultant theory has been introduced to calculate the switching angles in seven-
level inverters [51]. Unlike other iterative numerical solutions, the resultant theory
approach gives the exact. range of the modulation index for which solutions exist
and all possible solutions. The results show that the 5‘” and 7’“ can be eliminated
when and only when modulation index m falls in [1.15 2.52] or some isolated points
around 0.8, 0.82, and 2.76. where m is defined as m = ffi/(.sl’;1C/7r). This method has

been improved by adding one switching angles and considering different switching

24

 

m’f: J1

 

 

Figure 2.13. N-level staircase voltage waveform.

pattern for different modulation indices [52]. The unified approach can eliminate
5‘”, 7th, and 11th harmonics for most modulation indices. For five switching angles,
symmetric polynomials has been used to reduce the computational burden. Therefore
the harmonics up to 13“ can be eliminated [53]. For the lower modulation indices
operation, more pulses can be added to reduce the harmonics [54]. Furthermore,
by adding more PWM switching pulses, all harmonic contents below 53‘“ can be

eliminated [55].

2.4.2 Carrier-based SPWM

Based on the popular carried-based SPWM in the two-level converter, several mul-
ticarrier PWM techniques have been developed to reduce the harmonic distortion.
Subharmonic PWM (SH-PWM) has be been proposed in [56]. For a N —level inverter,
there are N —1 carriers with the same carrier frequency fc and the saune amplitude as
each dc bus capacitor voltage. Because of the multiple carriers. the reference changes

from a carrier band to anther carrier band. In each carrier bz-II'lCl. the resulting out.-

 

Y I l I T
2“ . A . 1 . i A i i. i ,1 i, a
:1 f1 ‘I 1 1‘ 1 ,1: [1 f1 /1 11 11
/ l 1’1 :1. l1 f ‘2 l1 . 1. ,-’ ‘1
‘1 1 . . ‘1 1"; j H, ,l‘, 1 1‘1 11
“ i f ‘ -. j l l ' i I l . I I l I f l ,' i « L
— l‘ ‘ f f ‘ l t , l I I. I l ‘- ' '1 l i
1'51 tWri/z ‘1‘1/‘1-[11’1/1/1/1.1=1:l
2:, ': l I ; [“i f )i l I if i
l if if '11" I1] 1." ‘11 if ‘1. ‘1 ‘1 f ‘11 1.
1 n 1" I; [if V if 0‘ t ” A f f \f ’ f )1 i f I f L,
1 ,1 -» 1 1. 1 1 1 .
. - 1 1 1 -‘ 11 l ’1 1 11 c
l ‘1 i l -’ ‘ I ‘ “ l 1" “~ 1 i l l \ l ‘1
lit: 1"‘1/1/l [‘1 111’ '1'.
f “ i l l
0.5- i l l‘ f l / '1‘ f 1 / 1 l \1 If ‘1‘ ‘1‘ / '1‘ / \ j ‘1 l 1
i - j I ' - 1
l f l l f l f; ‘2, f l. ’l \ l ‘1, ,l i l‘ / l l [I
‘l! i "i l ‘ I I L,
11 1l 1 11 1,- 1 1/ - u
i V r \l i ‘i f
0 1" 1 ,1 f, ,1 1 ,, ,
f . .
ll l ‘ l ‘ ‘

f -
'4 for
-‘\
\
.r- ’ ‘T’
.4
\\
~I—flflflr
4"
”0"
-\
\\\
/__,/—'"
”.r'“
/‘
\\\-—.
Vvflflf.
”Irv"

—1.5-‘

 

‘1']
r ., ”1
' W

 

' ": ”1
f ‘1 / l (l ”l '
ll \ / [I f]\ ll i
1 ll I (I; [I / \ ’l l‘ =[i I; \l / l‘ [I ‘
if ‘1‘] V \f l/ if [if \i/ ERl -'
o pi/3 2pi/3 pi 4W3 '

 

5p1/3

Figure 2 14 Carrier-based SPWM output waveform for a five level converter

put voltage is determined by the comparison between the reference voltage and the

0
carrier voltage Similar as in the two—level inverter. Figure 2 14 shows the five-level
output voltage waveform for SH PWM

A very common practice in industrial application for the carrier based PWM IS

the injection of a third harmonics to increase the output voltagc [23,31]. Steinke
proposed switching frequency optimal PWM (SFO-PWM) where a different triplen
harmonic voltaore is used [12,57]. This method takes the instantaneous average of

the maximum and minimum of the three reference voltages (V l * V *) as the offset

7 t c "
voltage. The SFO- PWM increases the maximum modulation index bv 15 C7c.

In multilevel PWM the sw1tching frequency is a function of the displacement
phase angle between the carrier set and the modulation waveform

It. can be less
than or greater than the carrier frequency

By adjusting the displacement phase

26

angle in multilevel PWM switching strategies, switching losses can be minimized
for a more efficient multilevel inverter [58]. Also some new control methods have
been proposed to reduce power loss by avoiding the narrow pulses [59]. The T HD
performance for different displacement phase angle has been studied in [60].

In carrier-based PWM and switching-frequency optimal PWM, the top and bot-
tom switches are switched much more often than the intermediate devices. A new
control method to balance device switching frequency in a diode clamped inverter

has been proposed [58].

2.4.3 Space Vector PWM

The space vector technique can also be easily extended to multilevel inverters [61—66].
For the two level inverter, there are 7 vectors in the space vector diagram, including
zero vector. The three-level inverter has 19 vectors, as shown in Figure 2.15. Similar
diagram can be generated for inverter with higher number of levels. Any voltage
vector within the hexagon boundary of the diagram can be synthesized by three
adjacent voltage vectors as

Til/i + TjVj + Tka)

._<
v_ T ,

 

(2.2)

where T,, T], and Th are the duty cycles for each voltage vector, respectively. Corn-
pared to carrier-based SPWM, space vector PWM generally has higher output volt-
age capability and lower current ripple.

In the space vector diagram of two-level inverters, only the zero-vector has redun-
dant switching states, (000) and (111). But in the space vector diagram of three-level
inverters, the six inner non-zero voltage vectors also have redundant switching states.
Generally, the vectors closer to the center and the vectors in the inverter with higher

numbers of voltage levels have more redundancy. The redundancy can be utilized to

27

(020) (120) (220)

 

221)
(021) (121) (110) (210)

(010) ,3 ’3
(011) (000) 5"” (122) (000) lfiA (200)

111) (100) ‘z;’ (011 (111)
(112) (212)

Ibo 101) (012) (001 (101) 201)

(010 110)
V

 

 

(a)

 

(002) (102) (202)
(b)

Figure 2.15. Space-vector diagrams:(a)three—level, (b)five—level.

avoid narrow pulses [67], minimize losses by not switching the highest current [68],

eliminate common mode voltage [69,70], and balance the dc bus voltage.

2.4.4 Definition of Modulation Index

Modulation index is a very important control parameter in the converter. However,
there are serval different definitions in the existing literatures, which is confusing
sometime. In the section, all the definitions and their relationship will be addressed.

Modulation index origins from carrier-based SPWM in traditional two-level in-
verters. It is originally defined as the peak value ratio between the sinusoidal refer-
ence and the triangular carrier. Usually the peak-peak value of the triangular carrier

is the same as the dc bus voltage. Therefore. it can be expressed as

 

,Hz
lpk
ma "

_ rah/2'

28

 

1-4 t r r r r T

1.2~

    

1 _, , Normal 7
Modulation

 

 

0,3 - ..... . ' ............ 1

Ratio between output fudamental

voltage(peak) and dc bus voltage

0.2. ............. .. ........ ..

 

 

 

o . . . i . .
0 0.5 1 1.5 2 2.5 3 3.5

Peak value ratio between the sinusoidal reference and the triangluar carrier

Figure 2.16. Relationship between output voltage and reference voltage.

When ma is less than 1, the fundamental component of the output PWM voltage
satisfies
Vdc

Vpk 2 p76 = ma ' 7. (2.4)

In the overmodulation region, which is when ma becomes greater than 1, the si-
nusoidal reference and the triangular carrier no longer have intersection every cycle.
Thus the fundamental component of the output PWM voltage is no longer propor-
tional to the modulation index ma. Also lower order harmonics will be introduced.
Therefore, overmodulation needs to be avoided. Figure 2.16 shows the relationship
between the reference voltage and output fundamental voltage. It can seen that in
the normal modulation region, the output voltage keeps the same as the reference

voltage, however, the increase of the output fundamental voltage becomes slow after

29

reaching the overmodulation region. Eventually. the maximum output voltage can
be obtained is 4/7r, which is 1.273.

In Chapter 2.4.2, some techniques have been introduced to increase output voltage
without overmodulation. For most of them. a triplen harmonic offset voltage is added
to the sinusoidal reference. Since the reference voltage now is no longer sinusoidal,

the definition of the modulation index also changes to

 

m = Vpk

a Vdc/Z,

where the actual output voltage is used instead of the reference voltage.
In some multilevel literature, especially in the fundamental frequency switching

control, there are another widely used definition of modulation index, which is the

ratio between the output voltage and maximum obtainable voltage,

 

 

V k V A,
A! = p = p . 2.
Vmax 2vdc/7T ( 6)
The relationship between A! and 771,, is given by
A! = Ema. (2.7)

The advantage of this definition is that the modulation index is always less or equal
than 1. Also in some cascaded multilevel literature, dc voltage of one cell is used
instead of the total dc voltage. Therefore. the modulation index in this case should
be divided by the number of voltage levels.

For different control strategy, the maximum output voltages without overmodu-
lation are different. Table 2.3 shows the maximum obtainable modulation index for
different control method. For the sinusoidal PW M, modulation index 772,, can only

go up to 1 without introducing lower order harmonics. However, by injecting third

3( l

Table 2.3. Maximum output voltages for different control strategy

 

 

 

 

 

 

Control Strategy M 171,,

Sinusoidal PWM 0.785 1
Sinusoidal PWM w/ third harmonic injection 0.906 1.155
SFO-PWM 0.906 1.155
Space Vector PWM 0.906 1.155
Maximum(allows harmonics) 1 1.273

 

 

 

 

 

harmonic or using SF O-PWM, ma can go up to 1.1547, same as the space vector
PWM. If the lower harmonics are allowed, the maximum ma will be 1.2732. Modu-
lation Index M’ is also shown in the table. In this dissertation, the modulation index

definition in (2.6) will be used.

2.5 Back-to-Back Structure

Back-to—back structure is a converter configuration consists of two identical inverters
with a shared dc-bus. The back-to-back structure is widely used in the power system
by being connected to the power system in a series-parallel arrangement, as shown in
Figure 2.17. Therefore, both the current demanded from the utility and the voltage
delivered to the load can be controlled simultaneously. This series-parallel active
filter has been referred as a universal power conditioner when used on electrical
distribution systems, and as a universal power flow controller when applied at the
transmission line level.

Lai proposed the back-to-back diode-clamped topology as a high-voltage dc in-
tertie between two asynchronous ac systems or as rectifier/ inverter system for high-
voltage motors ASD [11]. The diode-clamped inverter has been chosen over the other

two basic multilevel circuit topologies for the following reasons [71]:

o All six phases (three on each inverter) can share a common dc link. Conversely,

31

 

 

 

 

 

—'SL—\AW —* La
V Sb I Sb V Lb
Utility Load
VSc _>ISC VL:

 

 

 

 

 

 

 

 

 

 

 

 

i111 3113

 

 

 

Series Parallel Ia,
Inverter T Inverter [Ca

 

 

 

 

 

 

 

 

 

Figure 2.17. Series-parallel connection of the back-to—back system.

the cascade inverter requires that each dc level be separate, and this is not

conducive to a back-to—back arrangement;

a The multilevel capacitor-clamped converter also shares a common dc link. How-
ever, each phase leg requires several auxiliary capacitors. These extra capaci-

tors would add substantially to the cost and the size of the converter.

Figure 2.18 shows a three-phase five-level rectifier/ inverter back-to—back system,
which can generate a nine-level line—to—line voltage waveform. The system consists of
two identical five—level converters with a shared dc bus. The left half-side is connected
to the utility and acts as a rectifier; the right half-side is connected to the load and
acts as an inverter. Compared with the diode bridge rectifier, the active rectifier
reduces the input current harmonics significantly. The active front. end rectifier also
allows the power to flow bidirectionally, and provides regeneration capability [72] [73].
Another advantage of the back-to—back system is that it can control the power factor.

The system can inject / absorb desired reactive power to/ from the grid or realize the

32

Source Load

 

Rectifier 1 Inverter

Figure 2.18. Five-level diode-clamped back-to-back converter structure.

unity power factor control [11].
The main advantages and disadvantages of the back-to—back structure are:

Advantages:

0 Lower input current harmonics;

o Bidirectional power flow control;

0 Ability to control voltage of the dc bus;
0 Ability to control input power factor.
Disadvantages:

o More switching devices are required;

0 Control is more cor’nplex.

33

2.6 Capacitor Voltages Balancing Techniques

The multiple dc bus capacitors provide the capability of output multilevel voltage
waveform. However, it also requires additional circuits and special control methods
to keep the capacitor voltages well balanced.

The self—voltage-balancing for the cascaded multilevel converter is relatively
straightforward because of the symmetry of the capacitors. However, a slight voltage
imbalance may occur because of the parameter difference and control tolerance. A
simple control strategy is proposed to balance the dc bus voltages in reactive and
harmonic compensation application [74]. For the cascaded multilevel inverter pow-
ered by isolated dc source for hybrid electric vehicles application, similar control can
be used [24].

The voltage balancing for the capacitor clamped multilevel converter is also fairly
easy because of the phase voltage redundancy. Different switching combinations have
different charge/discharge effects for the clamping capacitors. By proper selecting
the output switching combination. The capacitor voltages can be balanced while
keeping same output voltage [75,76]. Recent research also shows that because of
the spontaneous clamping capacitor current control loop, the clamping capacitor
voltage in the three-level capacitor clamped inverter has self-balancing capability
under sub-harmonic PWM modulation when the load is not pure-reactive [77].

For the three-level diode-clamped converter, because there is only one additional
voltage junction, the neutral point, and the symmetry of the upper and lower capaci-
tors, it also has self voltage balancing potential. However the neutral point has a. low
frequency ripple at three times of the fundamental frequency. Some new researches
have addressed on eliminating or attenuating the low frequency ripple [78 83].

The voltage balancing of diode-clamped multilevel converter with higher number

of voltage levels is more. complicate, which limits their wider application. Corziue

34

proposed a dc-dc front end to regulate the center capacitor voltage of a four-level
converter [84]. PWM hysteresis control method has been proposed to regulate the
dc bus of a five-level rectifier [85]. Then the multi—band hysteresis comparators con-
trol strategy has been extended to a five-level back-to—back system. Although the
technique is simple, the characteristics are not sufficient as a motor drive system.
Thus an improved control strategy using the space vector PWM has also been pro-
posed. The improved control strategy is able to solve the voltage ripples in the dc

link [86,87]. Similar voltage balancing technique have also been discussed in [13,88].

2.7 Summary

Three most widely used multilevel structure have been identified: diode-clamped, ca-
pacitor clamped, and cascaded H bridge. Their main feature and applications were
introduced, and the relative advantages and disadvantages were discussed. Some
recently proposed topologies, include generalized multilevel converters, hybrid mul-
tilevel cells, asymmetric multilevel cells, multilevel dc-dc converters, and simplified
topology with reduced number of devices, were also outlined.

Different multilevel converter control methods, fundamental frequency switch-
ing, carrier-based SPWM, and space vector PWM, were reviewed. the back-to—back
diode-clamped rectifier / inverter topology was also reviewed and chosen for multilevel
adjustable speed drive applications because of its advantages.

The main obstacle that prevents the multilevel diode-clamped converter from
being widely used is the voltage unbalance problem. The previous work of voltage
balancing control were outlined. In the next chapter, a novel voltage balancing

control for five—level diode-clamped back-to-back system will be proposed.

CHAPTER 3

Novel Voltage Balancing Control
Method

3.1 Introduction

The topology of the multilevel converter makes it an ideal solution for medium voltage
drive, which cannot be directly implemented by the traditional converter topology
due to the limited voltage ratings of power devices. Three different types of multilevel
converters: diode—clamped, capacitor-clamped, and cascade multilevel converter have
been reviewed in the previous chapter. All topologies have their own demerits for
the motor drive applications. The cascaded multilevel converter needs separated dc
buses, which requires bulky isolation transformers. The application of the capacitor-
clamped multilevel converter is also limited because the clamping capacitors make
the system bulky and expensive, especially when the number of levels is high. The
diode-clamping multilevel converter, however, has the voltage unbalancing problem
between the dc—link capacitors when the number of levels is greater than three.

In this chapter, a voltage balancing control theory for the multilevel back-to-l'mck
rectifier/inverter system is presented. The method relies on coordination between

the rectifier and the inverter to achieve capacitor charge balance and at the same

36

 

, Output
5 Current

 

 

 

_.-.--.-,---_,--__ __ _

Figure 3.1. Equivalent circuit of a five-level converter.

time minimize the switching harmonics of both the rectifier and inverter. The volt-
age balancing mechanism is analyzed based on a five-level back-to—back system. The
principle of the proposed control method is derived from fundamental frequency
switching control and then extended to selective harmonic elimination PWM. Then
the improved control method is also introduced, which reduces the harmonic com-
ponents in the low modulation index operation. Furthermore, the voltage balancing
method is extended to carrier-based PWM control, which can eliminate lower har-
monics while keeping dc bus voltage balanced. At the end of this chapter, the DC

bus voltage and reactive power control is also discussed.

3.2 Voltage Balancing Control in Fundamental
Frequency Switching

Figure 3.1 shows the equivalent circuit of a five-level diode-clamped converter. The

output is connected to different voltage junctions according to the switching states

37

 

 

 

 

 

 

 

 

 

 

 

_< ~< ,5? ,S US
11

 

 

 

Figure 3.2. Fundamental frequency switching of five-level converter.

shown in Table 2.1, which can be represented by a multi-select switch. The simplest
way to control a multilevel converter is the fundamental frequency switching control
wherein the switching devices generate an N -level staircase waveform which tracks a
sinusoidal waveform. In this control each switching device only needs to switch one
time per fundamental cycle, which results in low switching losses and low electro-
magnetic interference. Figure 3.2 shows a five—level staircase waveform. Because of
the symmetry of the waveform, there are only two switching angles that need to be
determined in this control strategy, which are 61 and 62. It can be assumed that 01
is always less than 62.

According to the topology of the multilevel inverter, it can be seen that the
current flowing out of each voltage junction is determined by the output. current and
the output of the phase leg. The current flowing out of voltage junction V5 is given

by

. 2'1, for '00 = V5
zO’ut5 : 9 (31)
0 for 110 aé V5

where vo is the output voltage of the inverter phase leg.

38

 

m5

 

 

 

 

 

 

 

 

m4

 

 

 

 

 

 

 

m3

 

 

 

 

 

 

 

 

m2

 

 

 

 

 

[55
N

 

 

 

in!

 

 

 

 

 

3,

 

 

5.51;: s 5: 51,515 3 5 55,515,}: 5 51,5: 3 ,5: 5 ,3: ,3 s 5

 

 

Figure 3.3. Active currents flowing out of the capacitor junctions.

In general, the current flowing out of junction V1, is given by

. iL fOI' U() = Vx
Zoutx = , (3.2)
0 for 00 7g VI

where :1: equals 1, 2, 3, 4, or 5.
Figures 3.3 and 3.4 illustrate the waveforms of the current flowing out of each
voltage junction. Assuming that the load current is sinusoidal, we can decompose the

load current into two com orients: active current and reactive current. Figure 3.3
("n

39

 

in5

 

 

 

 

 

 

 

 

 

m4

 

 

 

 

 

 

 

 

 

 

m3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

in]

 

 

 

 

 

:21:in *V US $81,515! ‘53 UV NVNVWV ,fi MY NVNVWV ‘V 0“." NY «1‘1”: “V U:

 

Figure 3.4. Reactive currents flowing out of the capacitor junctions.

shows the case when there is only active current. The output current will flow out
of different voltage junction, V1, V2, V3, V4 or V5, according to the switching state
of the inverter. The different shaded areas shown in Figure 3.3 represent the charge
flowing into the each voltage junction over one period. It is obvious that, the currents
flowing out of voltage junction V4 and V5, 730,,” and fonts, are always positive, while
10,,“ and tout-2 are always negative. The average current flowing out of the junction
V3, 10mg is zero on average because of the symmetry of the. current waveform.

Figure 3.4 shows the case where the line current is 90 degrees leading the phase

40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3.5. Five-level diode-clamped back-to—back converter structure.

voltage. It is obvious that the average current flowing out of each voltage junction
over one period is always zero, which means that reactive currents have no effect on
average voltage of each junction.

From the above analysis, the voltage of V4 tends to decrease because there is
always positive current flowing out, while the voltage of V2 tends to increase. As time
continues, the voltage of junction V, will keep falling and the voltage of junction V2
will keep raising, until they reach V3. Thus, the five-level converter will degrade to
three—level converter eventually. Therefore, for a multilevel converter with a number
of levels higher than three, some additional circuit or control strategy must be added
to overcome the voltage unbalance problem. The back-to-back structure illustrated

in Chapter 2.5 provides this possibility.

41

3.2.1 Charge Balancing Analysis

In the back-to-back structure, two identical five-level converters are connected with
a shared dc buses, as shown in Figure 2.18. The left half-side is connected to the
utility and acts as a rectifier, while the right half-side is connected to the load and
acts as an inverter. Because of the symmetry of three phase legs, the system can be
simplified to Figure 3.5, where only one phase leg is considered.

In the back-to-back structure, because of the symmetry of the system, the un-
balance tendencies of both sides have a potential to compensate each other. With a
proper control strategy, net current flowing into each level can be regulated to zero.

Since the reactive components of the current for both the rectifier and inverter
have no effect on the voltage balance, only the active components of the currents
need to be considered. The voltage and the active current waveforms are illustrated
in Figure 3.6. Figure 3.6(a) shows the voltage and current waveforms of the rectifier,
where VR and V31 are the rectifier staircase voltage waveform and its fundamental
component, respectively, and i3 is the active rectifier current waveform. Figure 3.6(b)
illustrates the waveforms of the inverter. The average currents flowing out of each

voltage junction can be expressed as

1 27r—012

10,,“ = —/ ILsint’fdfl; (3.3)
T n+912
1 “+012 21r—011

10,,” = __ (/ iLsian6+/ ILsianB); (3.4)
T «+01; 27r—012
1 911 «+611

[0mg = —- (/ ILsiiiOdH+f ILsinfldB); (3.5)
T -911 1r—9Ii
1 912 7r-911

101114 = — (/ [Lsi116(10+/ ILsin0d9>; (3.6)
T 911 w—om
1 “If—912

and [0,,t5 = T/ '17,,siiifldf). (3.7)
912

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V- w R,w <1
5 ,[v / . ‘ a I]
If _ 1 / IR “ R]
4 / ' ' \ Tc
4 ., l I \
V - . L \JIN .
J 6 6 \l\‘_—//
V 1-- RI R2 ..... \' ‘ x
2 I“ ] x7
V r , ’ if
1 i' A
V V0
5 , ***** V01
4 ' r. \
3 /
V 0,, 612 \\\ #//
2 \ \4 s __ _ __ p .1? I
VI

 

Figure 3.6. Voltage and current waveforms of the rectifier and inverter side.

where [L is the amplitude of the load current, and 011, 612 are the switching angles
of the inverter side.

According to the symmetry of sinusoidal waveform, it can be concluded that
10,,“ = — 0mg” 101122 = — 01114, and [0&3 = 0. Similarly, the average currents flowing
into each voltage junction can be obtained as [M ~ I,,,5. Accordingly, the simplified
equivalent circuit can be drawn as Figure 3.7. Because of the symmetry, we only
need to balance two voltage junctions, the outer junction V5 and the inner junction
V4.

In order to balance junction V4, the average net charge flowing into the junction

V4 should be zero, i.e.
9R2 912
/ iRsinddf) :/ iLsinddfl. (3.8)
0

R1 911

Then we can get the charge balancing equation.

[3((208632 — cosflm) = 1,,(cos9r2 — C086“), (3.9)

43

 

 

 

 

Figure 3.7. Capacitor junction equivalent circuit.

where I L is the amplitude of the input current.
Also, the input and output active power of the dc link capacitors has to be

balanced, which is also the charge balance equation for junction V5,

[”0333 = fvoiL. (3.10)

Assuming that the three—phase currents are balanced and sinusoidal, only the funda-
mental components need to be considered. Therefore, we can get the power balancing
equation,

VRIIR = Vail/.1 (3-11)

where V121 and V01 are the fundamental components of the rectifier voltage 2);; and
output voltage 110, respectively.
Eliminating I R and I L from (3.9) and (3.11), we can get the voltage balancing

equation, which is

V01(cos 6m — cos 6m) : 1",“(cos 611 — cos 612). (3.12)

44

Modulation index is frequently used to represent the output voltage of the in-
verter. Here the modulation index is defined as the ratio of the output voltage to
maximum obtainable output voltage. In the back-to—back structure, there are two
modulation indices, the rectifier modulation index, AIR, and the inverter modulation

index, A! 1, which are defined as

AIR 2 VRl/VMaxa (313)

and AI] = VOl/VMax, (3.14)

where VMax is the root-mean-square (RMS) value of the maximum obtainable output

voltage when both 61 and 62 are zero, which is expressed as

2
VMax = i ' Vdc- (3.15)
7r
Substitute (3.13) and (3.14) into (3.12), we can get

A11(cos 0m — cos 632) = M'R(cos 911 — cos 012). (3.16)

On the other hand, the fundamental component of the rectifier voltages can
be obtained from Fourier series analysis of the waveform shown in Figure 3.6 and

expressed as functions of the switching angles and the dc-link voltage by

V31 = —/ vRsinQdH
0

031 0R2
= Q - (/ Vdc si116’d6 +/ Vdc sin 6(10)
7T 1r—6m 4 77—632 4
\/§ Vac
7T
Villa

 

 

T ' (2 (308631 + ZCOSQR‘Z)

(cos 6m + cos 0m)
x . 2 .

 

(3.17)

Therefore the rectifier modulation index MR satisfies

AIR 2 (COS 6R1 + COS 932)/2. (3.18)

Similarly, the inverter modulation index All, satisfies

M, = (cos 011 + cos 6’12)/2. (3.19)

Solve the equations of (3.16), (3.18), and (3.19), we can get,

632 = arccos(2MR——c056m); (3.20)
M
611 = arccos(—I—c056m); (3.21)
MR
M1
61-2 2 arccos(2]l[1——cosflm). (3.22)
MR

It can be seen that the other three switching angles can be calculated from a
given 631. Therefore, there are a lot of switching angle combinations that satisfy the
voltage balance equation, which can be used to reduce the total harmonic distortion
(THD) of the both voltages. The THD of different switching angle combinations are
calculated, and the switching angles with the lowest THD is chosen.

Since the rectifier side of the back-back system is connected to the utility, MR is
usually set to 0.9. For a given inverter modulation index, M 1, the optimal switching

angles of both sides can be calculated and shown in Table 3.1 and Figure 3.8.

46

Table 3.1. Optimal switching angles for NR = 0.9.

 

M 1

0m

0122

911

012

 

1.000

0.4510

0.4510

0.0000

0.0000

 

0.975

0.3996

0.4975

0.0638

0.3110

 

0.950

0.3338

0.5449

0.0737

0.4448

 

0.925

0.2476

0.5908

0.0845

0.5480

 

0.900

0.1485

0.6249

0.1485

0.6249

 

0.875

0.1105

0.6333

0.2604

0.6702

 

0.850

0.1226

0.6309

0.3558

0.7034

 

0.825

0.1192

0.6316

0.4271

0.7380

 

0.800

0.0938

0.6361

0.4844

0.7741

 

0.775

0.1305

0.6292

0.5476

0.8007

 

0.750

0.1258

0.6302

0.5975

0.8322

 

0.725

0.1258

0.6302

0.6448

0.8621

 

0.700

0.1242

0.6306

0.6891

0.8915

 

0.675

0.1242

0.6306

0.7314

0.9201

 

0.650

0.1234

0.6307

0.7717

0.9481

 

0.625

0.1226

0.6309

0.8104

0.9755

 

0.600

0.1175

0.6319

0.8472

1.0028

 

0.575

0.1184

0.6317

0.8835

1.0291

 

0.550

0.1289

0.6295

0.9197

1.0542

 

0.525

0.1335

0.6285

0.9543

1.0794

 

0.500

0.1297

0.6294

0.9874

1.1050

 

0.475

0.1234

0.6307

1.0195

1.1305

 

0.450

0.0895

0.6368

1.0495

1.1571

 

0.425

0.0749

0.6388

1.0805

1.1820

 

0.400

0.0735

0.6390

1.1116

1.2060

 

0.375

0.0721

0.6392

1.1422

1.2298

 

0.350

0.0707

0.6393

1.1724

1.2534

 

0.325

0.0693

0.6395

1.2023

1.2768

 

0.300

0.0678

0.6397

1.2318

1.3001

 

0.275

0.0663

0.6398

1.2610

1.3232

 

0.250

0.0663

0.6398

1.2900

1.3461

 

0.225

0.0633

0.6402

1.3186

1.3689

 

0.200

0.0633

0.6402

1.3472

1.3916

 

0.175

0.0648

0.6400

1.3755

1.4142

 

0.150

0.0617

0.6403

1.4037

1.4367

 

0.125

0.0617

0.6403

1.4317

1.4592

 

0.100

0.0648

0.6400

1.4597

1.4816

 

0.075

0.0600

0.6405

1.4875

1.5039

 

0.050

0.0583

0.6407

1.5153

1.5262

 

 

0 . 0 2 5

 

0.0762

 

0.6387

 

1.5431

 

1.5485

 

47

 

Switching Angles(rad)

 

1.6 I I I ‘F T I I I I

 

 

 

 

.1
Ian," —gr1
.~u —- r2
14" " ‘-. o
s l1
‘.‘ oi2
1.2- ‘.‘
.~’
‘1
s
1" 's .
'8,
‘1
s, .
0.8" x,
\I
s

.0
a:
U

.0
A
I

0.2 F

A

f"

 

 

 

 

o l L l l 1 l l
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Modulation Index of the inverter MI

Figure 3.8. Optimal switching angles for A! R = 0.9.

48

3.2.2 Simulation Results of Proposed Voltage Balancing
Control

Based on the optimal switching angles calculated in Table 3.1, simulation models
are set up to verify the proposed voltage balancing control control strategy. The
simulations are conducted under several different inverter modulation index, 0.9,
0.8, 0.5, 0.3, and 0.1. The detailed simulation waveforms are given in Figures 3.9 to
3.13.

From the simulation results, it can be seen that the voltage balancing can be
achieved in the entire operation range. The THD optimization are also very effective.
The input currents are quite sinusoidal in high modulation index operation. The load
used in the simulation is a R — L load with a power factor of 0.8. The load is directly
connected to the output of the inverter without any additional filter. If a L — C filter

is used in the output, the harmonics in the output current can be further reduced.

49

MR=O.9 MI=O.9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V) 3 t('5)
100001 _ ‘ ‘ Source Voltage
500.0 ‘ ‘ ‘ ‘
2, 0.0 ‘ Rectifier Voitage
-500.0 ‘
-1 000.0 - (A) 2 1(8)
40-0 1 Input Current
A 20.0 ‘
3 0.0 1
-20.0 ‘
-40.0- (v) ”(5)
1000.0 - OW vouage
A 500.0“. mm
2 0.0 ‘ V
-500.0 ' L’L
40'0 _ Output Current
A 20.0 ‘
$ 0.0 -
-20.0 “
-40.0 ' (v) : t(S)
800.0 ' v5
600.0‘ v4
a 4000- v3
200.0 ' V2
0.0 d r l I T l I
0.5 0.51 0.52 0.53 0.54 0.55

t(s)

Figure 3.9. Simulation results of fundamental frequency control for Iii/R = 0.9 and
IV]; = 0.9.

50

MR=O.9 MI=O.8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V) : t(s)
1000-0 _ Source Voltage
500.0 ‘. ‘ l ‘ .
E 0.0 ‘ Rectifier Voltage
-500.0 ‘
-1000.0 ‘ (A) : t(s)
40-0 - Input Current
20.0 ‘
3: 0.0 J
-20.0
-40.0J (V) ”(3)
1000-0 - Output Voltage
A 500.0 -
a 0.01
-500.0 7
-1 000.0 ‘ (A) : t(s)
40°C - Output Current
20.0 '1
5‘: 0.0 “4
-20.0 7
-40.0 " (v) I “3)
8000‘ v5
600.0 ' v4
5 400.0‘ _ _ v3
200.0 ‘ V2
0-0 J F I I l I
0.5 0.51 0.52 0.53 0.54 0.55

t(s)

Figure 3.10. Simulation results of fundamental frequency control for AIR = 0.9 and
M I = 0.8.

51

1000.0 '
500.0 '
0.0 ‘
-500.0 '

(V)

MR=0.9 MI=0.5

 

 

-1000.0 ‘
20.0 ‘

(A)

0.0 ‘

 

(V) 2 1(5)
Source Voltage

 

Rectifier Voltage

 

 

 

 

 

-20.0 '

1000.0 '
500.0 '
0.0 1
-500.0 ‘

(V)

 

(A) :t(s)
Input Current

 

 

 

 

-1000.0 ‘

40.0 -
20.0 4
0.0 -
-20.o ‘

(A)

 

(V) ”(8)
Output Voltage

 

 

 

 

 

-40.0
800.0 '

 

(A) :t(s)
Output Current

 

 

 

 

 

600.0 "

(V)

400.0 ‘

200.0 "

(V) :t(s)
v5

 

 

v4

 

 

 

 

0.0 '

 

 

 

 

W

0.5

0.52

0.54 0.56

t(s)

 

0.6

Figure 3.11. Simulation results of fundamental frequency control for MR 2 0.9 and

M, = 0.5.

52

MR=0.9 Ml=0.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V) :t(S)
1000.0 ' Source Voltage
500.0 '
3 0.0 ‘ I Rectifier Voltage
-500.0 '
-1000.0 ' (A) :t(s)
10.0 ‘ ' Input Current
5‘: 0.0 -
10 0 J
' ' (V) :t(s)
1000.0 ‘ Output Voltage
A 500.0 ‘
.>, 0.0. wwflmum
-500.0 1
-1 000.0 - (A) : t(S)
40-0 ‘ Output Current
A 20.0 ‘
3 0.0 ‘ W
-20.0 ‘
800.0 - v5
600.0 ‘ v4
5 400.0 ‘ v3
200.0 ‘ v2
0-0 - I I I I
1 .0 1 .05 1 .1 1 .15
t(s)

Figure 3.12. Simulation results of fundamental frequency control for MR 2 0.9 and
11]] = 0.3.

53

MR=0.9 Ml=0.1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V) 21(5)
100°") _ . Source Voltage
500.0 ‘
E 0.0 - Rectifier Voltage
-500.0 ‘
-1000.0 ‘ (A) :t(s)
10'0 - Input Current
3 col ,
.l
"0'0 (V) :t(s)
10000 ' Output Voltage
500.0 ‘
’>‘ .11 . lLll “Hum .ttTrJuuTL
v 0-0 I'll W l
-500.0 ‘
-1000.0 ' (A) : t(s)
40'0 ' Output Current
A 20.0 ‘
S 0.0 .. W
-20.0 ‘
800.0 ' v5
600.0 ‘ v4
B 400.0 1 v3
200.0 1 v2
0.0 - f l I l
1.0 1.1 1 2 1.3

tfs)

Figure 3.13. Simulation results of fundamental frequency control for AIR 2 0.9 and
M, = 0.1.

54

 

 

 

 

 

100 ._ . . .
90 ........ I. .. ., ..... .1 .. ._
80~ . q

. : lnverterTHD

9i 70.. ..... .......... ..

C i I . . . . , .

2 : t : : ' : :

5' 60" ....... . ...... , I ,' .......... I ... _....

.9 ' : : : : : t

D i . ‘ I i I , i i

.9 50 ........ . ,1 ...‘

g I C I ' Z I ‘ '

Minimum ._

é 4° - THD

E : : : : : : ; : :

'2 30.. ...... ....... ..... ..... ....... ...... .......
20 ........ ....... ...... ...... ......

RectifierTHD ' i . : 3 ; ;
10-1’. ....... I ........ I. "TT'\_. ....... ....... v.4
0 l t P i 1 L

 

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Modulation Index of Inverter MIl

Figure 3.14. Minimal THD of the voltage balancing control output.

3.3 Effect of the Rectifier Modulation Index M R

Based on the optimized switching angles above, THD of the corresponding voltage
waveforms are calculated and shown in Figure 3.14, where the harmonics are counted
up to the 40th order and all triplet harmonics are excluded. Figure 3.14 also shows the
minimum THD of the staircase waveform without the voltage balancing constraint
for different modulation indices.

The THD is determined by switching angles, therefore by M R, M 1, and voltage
balance constraints. The minimum values are shown in Figure 3.14. However, the
THD on the inverter side is much higher than the minimum because of the voltage
balancing constraints. For the rectifier side, the THD is always about 10%, which is

close to the minimum THD for modulation index of 0.9, 8.7%.

Although the modulation index of the rectifier, MR, is set to 0.9 before, it may
be changed to obtain lower THD. Change of AIR affects the system performance in

the following ways,

0 AIR have direct influence on the rectifier THD;

0 AIR have indirect influence on the inverter THD via voltage balancing con-

straint ( 3.16);

o M R and input voltage determine the dc bus voltage, a crucial parameter for

selection of the power devices and dc bus capacitors.

The rectifier THD is usually close to the minimal THD, as shown in Figure 3.14.
Therefore optimized M 3 could be picked out of the minimal THD curve, which has
three local minimums can be used as candidates: 0.72, 0.9, and 0.95.

Although the switching angles of the rectifier side 931 and 6’32 may be changed to
get lower THD, their maximum and minimum values can be obtained from (3.18),

which is

03 631 S arccos(]l"IR), (3.23)

arccos(MR) g 632 S arccos(2MR — 1). (3.24)

From (3.21) and (3.22), the switching angles of the inverter side can also be calcu-
lated. Similarly, we can get the maximum and minimum values of 6,1 and 6,2,

M
arccos ——1 3 0,1 3 arccos M], (3.25)

MR
(201]? - 1) ° 11]]
MR '

 

arccole _<_ 6,2 S arccos

For example, if MR and ill, are 0.9 and 0.6, respectively. the switching angles

satisfy

0 5 6m 3 0.4510 3 6m 3 0.6435, (3.27)

0.8411 g 611 3 0.9273 3 6,2 3 1.0083. (3.28)

Accordingly, we can calculate the possible range of the switching angles for the same

1W; when 111;; equals 0.95 and 0.72, which is

for MR 2 0.95
0 S 631 S 0.3176 S 932 S 0.4510, (3.29)
0.8872 S 011 S 0.9273 S 912 S 0.9662. (3.30)

for MR 2 0.72
0 S 9m S 0.7670 S 932 S 1.1152, (3.31)
0.5857 S 611 S 0.9273 S 612 S 1.1954. (3.32)

It can be seen that when [M R is lower, the switching angles have a wider range,
and when M R is higher, the switching angles have a narrower range. Figure 3.15
shows the curve of the THD of the inverter side vs. switching angle 911. The inverter
voltage has higher THD at both ends and a optimal point in the middle where
611 equals 0.7604. However, the optimal point may not be reached because of the
limitation of 611. For example, 611 has to be larger than 0.8872 when MR equals
0.95, therefore, the minimum THD in this case is 27.9%. When MR equals 0.9, the
range of 611 becomes [0.8411, 0.9273], making it possible to have a THD as low as
22.6%. When 11!}; is reduced to 0.72, the lower limit of 611 becomes 0.5857, which
makes it possible for the inverter side to get minimal THD.

Figure 3.16 shows the comparison of the input / output voltage THD for different

1113. Generally, the lower AIR, the more freedom for the switching angles. and lower

Q”!
‘1

 

40 I I I I' I I I I I .

      

 

 

 

 

 

 

 

 

   
    
    
 

 

 

 

 

 

 

 

35
30 . ....................
: THD ol the
.3 Output Voltage
.9
o
.9
g 20 .. ........
E
a
I
E 15.. ..........
O
[—
10 ...................... . .
5 _.
O 1 l 1 # L
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Switching Angle 0”
Figure 3.15. THD vs. 611 for M, = 0.6.
100 I . I I I I I T I I
1 -o- Rect. THD “$30.95
90 _ —O— Inv. THD 041:0.95 .1
+ Rect. THD 15:09
80 1. -0— 1m]. THD Mq-IQQ ..
lnverterTHD + “9‘17”” ”1:50-72
2;: 70 r + Inv. THD Mq=0.72 .
r: ‘ Min.Tl—ID
.9
E 60 - ‘
.2
o
.2 50 r -
C
O
E.
I 40 - ~
E
.2 30 1 ~
20 - .~'
Rectifier THD '
10 ~ * -
o I A l l l l k l

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Modulation Index of Inverter Ml

Figure 3.16. Comparison of THD for different [W R .

 

 

 

 

V4 """" ! """" flit
V3 '

Y Y
K-time K-time l3
Switchings Switchings
01 " 9x 91m " 92x

 

 

 

 

Figure 3.17. Extension of the fundamental frequency switching to PWM.

THD for the inverter side. However, the lower [if 3 also lower the rectifier voltage.
Because the rectifier voltage usually equals to the input voltage, the lower M 3 re-
quires a higher dc bus voltage. The dc bus voltage for M R = 0.72 is 32% higher than

that for 114;; = 0.95, which increases the system cost substantially.

3.4 Selective Harmonics Elimination PWM

One way to improve the voltage balancing control is to increase the number of pulse in
each fundamental cycle. Figure 3.17 illustrates the voltage waveform of the proposed
selective harmonics elimination PWM. There are K transitions for each change from
one voltage level to another. Obviously, fundamental frequency switching is the
special case of this multiple pulses control where K = 1.

Using the same method in the fundamental frequency switching, optimized
switching angles can be obtained by minimizing the phase voltage THD under the
constraint of charge balance. In the following calculation, the number of pulses is
set to K = 9 as an example.

The optimizing program tries to minimize the harmonics up to 25th. Higher

harmonics in the voltage have less effect on the current waveform because of the

59

 

 

 

 

 

G

 

.2 04 ,
5:3 A035

2 =2

3 3 ”3 THD=14.9"o

0) $025 A -
%_ g 02 F fl
2 >015 _ THD(upt025"‘)

£' =1.03%

§_ 01

n: 005 r—’%

 

 

 

 

1

57

1113 1719 2325 2931 3537 A143 4749

'2 :3 3
Angle (Pad) Angle (rad)
(a) The rectifier THD (up to 25th ) is 1.03%, and total THD is 14.9%.

 

THD= 17.5%

Voltage (p.u.)

THD (up to 25‘”)
=3.04%

Rectifer Voltage Iine-to-Iine
O

    

 

 

 
   

 

2 3 4 6 11 2931 3637 “43
Angle (rad) Angle (rad)

(b) The rectifier THD (up to 25m ) is 3.04%, and total THD is 17.5%.

Figure 3.18. Line-to—line voltage waveforms and their spectra when M 1 = 0.7.

filtering by line and load inductances. The lower harmonics can be further reduced
with larger K.

The modulation index of the rectifier 1W}? is set to 0.8 in order to get lower
inverter THD. Optimal switching angles for different M, are calculated. Figure 3.18
illustrates the line—to—line voltage waveforms and their spectra when M, is 0.7. It
can be seen that although some higher harmonic components still exist. the lower
harmonics are significantly eliminated. The voltage THD up to 25th is only 1.03%

for the rectifier side and 3.04% for the inverter side.

60

 

100

90» ~-
70+

so- ------ -~  .

     
    

4o. ‘ ....... j. g _ ; V.
30* ..... FundamentalFrequencyé .......
‘ ' ' Switching ;

Total Harmonic Distortion (up to 27th) (%)

   
   

   

 

 

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Modulation Index of the Inverter M.

 

Figure 3.19. THD performance of the selective harmonics elimination PWM.

Figure 3.19 shows the output voltage THD comparison between the multiple
pulses method and fundamental frequency switching method. It can be seen that
the output voltage THD of the multiple pulses control is only about 5 ‘70 when M I
is higher than 0.5. The THD is relatively higher when M 1 is lower than 0.5.

Figure 3.20 shows the simulation results of the selective harmonics elimination
PWM control with voltage balancing control when MR and M R are 0.8 and 0.7,
respectively. As can be seen, the capacitor voltages remain balanced and the voltage
waveforms have more pulses, which leads to a low THD of the voltage waveform.

Therefore the input and output currents are both sinusoidal.

61

MR=O.8 MI=0.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V) :t(s)
w '1? Rectifier Voltage
2 0.0 '
u
(A) :t(s)
20.0 ‘ Input Current
g 0'0 . W
-2o.o ' (V) : KS)
5000 that} rt'i‘iiiltw {tilting} 0mm" Voltage
E 0.0 - litk till‘ lit“ HM M11 ”Mid”
lliltlilttj "ll w 1.) ill
-5oo.o ‘ (A) : t(s)
20.0 ' Output Current
-20-0 ' (V) : t(s)
600.0 - v5
v4
400.0 ‘

 

 

(V)
E:

 

200.0 ‘

 

 

 

 

 

 

 

0.0", T I j

1.5 1 .52 1.54 1.56
t(s)

Figure 3.20. Simulation results of SHE-PVVh‘I control for MR 2 0.8 and M, = 0.7.

62

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

      

 

 

 

 

 

 

Y .g-r "-I — -—
b 2 ‘2
q, o
" O
3% E1 ......................... IR .............................
o w
m o ..................................................
1
1.5
2

L-
o — —
E 51 ';‘..‘;bb‘dur.couub3;b‘.‘.';.'.
> (D
E o ............ .1] ................

l l l

0 0.5 1 1.5
g 2 _ ............... ' ................ ' . . |_ ' '
E E1 . ....................... .. .., .,_. Higgguggfl
go'o MM?" ' [J ..... 1.1 ........... .
-— 1 l L l l l
0 0.5 1 1.5 2 2.5

 

N

 

 

Inverter Side
w/o Constraint
0 .a

 

 

 

Figure 3.21. Comparison of voltage waveform when M 1 = 0.5.

3.5 Voltage Shifting Method for Low Modulation

Index Operation

Although the THD of the input or output voltage can be reduced by adding more
pulses, it is very effective when M 1 is higher than 0.6. However, when It], is lower
than 0.6, the THD can not be reduced significantly even with more pulses been
added.

In order to illustrate how the voltage balancing control affects the output THD,
the voltage and current. waveforms in different control methods have been shown
in Figure 3.21 as an example, where M, is 0.5 . Figures 3.21(a) and (b) show the
voltage and current waveforms of both sides with the optimized switching angles. The

shadow area in Figure 3.21(a) shows the total charge flowing into junction V4 from the

63

 

 

Figure 3.22. Line voltage redundancy of three~phase systems.

rectifier side. In order to balance the dc capacitor voltages, the total charge flowing
out of junction V21, which is the shadow area in Figure 3.21(b), must be the same as
that flowing into the junction. Since the switching angles of the rectifier side and
input current are relatively small, the total charge that can be output from junction
V4 is limited, which also limits the elapse time that the inverter can output V4, as
shown in Figure 3.21(b). Compared with the optimized output waveform without
constraints shown in Figure 3.21(d), it can be seen that the output time interval
of voltage level V4 is reduced by the voltage balancing constraint. As the result,
the THD of the output voltage increases from 15.6 ‘70 to 25.3% PWM control has
been introduced to lower the harmonic component of the output voltage. However,
even with additional pulses introduced by the PWM control, the lowest THD can
be achieved is only 20.7% because of the voltage balancing constraint. as shown in

Figure 3.21((:).

64

Figure 3.22 shows the three-phase staircase voltage waveforms with minimum
THD when M, = 0.5. However, it requires more current to be output from two
inner junctions V4 and V2 than the maximum current they can output, which is
limited by the charge balancing constraint. Therefore, it is desirable if we could
generate the same output waveform with less power output from the inner junctions.
Fortunately, line—line redundancy of three-phase systems provides this possibility.
When the switching angle 02 is greater than 7r/3, there are some periods in the
switching cycle that only voltage levels V2, V3, and V4 are used, as the shadowed
period shown in Figure 3.22. For example, during period T1, the outputs of the three
phase voltages are V4, V2, and V5, respectively. If we add one voltage level to all three
phase voltages, which would make the three phase voltages to be V5, V3, and V4, the
power output from the inner junctions will be reduced, while the output line voltages
keep the same. Based on the previous analysis, an offset voltage 'Uoffset can be added
to all three phase voltages to reduce the power output from the inner junctions. In

order to keep the symmetry of three phase voltages, ’Uoffset needs to satisfy

Uoffset“) = ”offset“ — 271/3). (3.33)

On the other hand, in order to keep each phase voltage symmetrical, 210,138, also

needs to satisfy

voffset(t) = —voffset(7r—t) (3.34)

and ’Uoffset(t) = voffsetbr + t). (3.35)

The phase voltage with voffset is shown in Figure 3.24. It can be seen that.
the time interval of V4 is reduced. Furthermore, the inverter will output V4 in the

negative half cycle, which further reduces the power output from the inner junctitms.

65

 

 

 

 

“V. (...... I! .. ...;{..\.A...Aw_-..la
..u . .v . . 7.
Lin.” 1....W.¢hsvurrt.o..v..<..ux .. .

 

:0. I .9... O r 0;. "Ii.

. .
.... ......VHB: ..li.

. ....t‘..‘.‘.‘ ‘.1.\

 

.. ...C'.’V.|§J9..o.bsifi
~A.. . . .. .

......

I ...I..
....”i. .....‘..I.

 

 

 

" MAJ. wield-904.1“!

 

 

 

 

 

 

 

 

9.3.13]. 13...... . r ..

........
.....

 

 

 

 

r 14.5 . . v
".0... v........\ u . even... .. .

 

 

 

‘e.a..‘u.w.1......¥ ..ta‘tudr...... ....n
3 uk...... 1.. .....t %.I.I :v ,0

 

 

 

 

.. q E... . Aribmvbuaycnzf

.wuta‘wtt ......

.....(u I II. .9... cc...o\.‘

 

 

 

 

3... £1iMXA~¢..wY Fm... .-

~ . .. . . . . . .
z! 0\ Sect. .1.T....O..o.

 

 

 

. l 7...... .1 ..

flit.) f

 

 

...-lila‘.‘4l 1‘- ..I ...IIJI ID
. . — .. . . Q 0
a} . ..usvr... .....J\.\.o... . . a I.
b..1.f.i .‘ ‘r .1... .Iu.‘ .3131: . ... ..I.

 

 

1.1:! dJ-‘L.

 

P... ....vvfiifiuré .. .

 

3
/

. /

TI.

 

 

27:

 

5M3

 

41t/3

 

 

 

27t/3

n/3

 

Figure 3.23. Offset voltage for harmonics optimization.

 

Figure 3.24. Phase voltage after the offset voltage is added.

The charge flowing out of V4 is given by

Q = /7:0ut4d6
“/3“! 92 7r+a
= 2 / ILsin6d0+/ ILSlIlgdg'l-f [LSlIl6d6
01 7T/3+O 1r

2 2°IL°[C0891—C0862+2COS(O+7l'/3)—1], (3.36)

where a is the pulse width of 'Uoffset. It can be seen that the total charge flowing
out of the inner junctions can be adjusted by the pulse width 0 of the offset voltage
to achieve the charge balancing. Therefore the charge balancing constraint shown in

(3.16) is changed to
011(cosflm — cos 632) = MR [cos 611 — cos 612 + 2cos(a + 7r/3) - 1]. (3.37)

However, this strategy requires the switching angle 612 to be greater than 7r/3,
which is true only when M, is less than 0.56. If that is satisfied, the charge balancing
can be satisfied by adjusting a only, and meanwhile. the line voltage outputs of both
sides can achieve minimized THD simultaneously.

When M1 is less than 0.4, only three voltage levels are needed to output the
desired voltage. The voltage can be output by the either top two, middle two, or
bottom two capacitors. According to the previous analysis, if the voltage is output
by the bottom two capacitors, the output current. will be drawn from junction V1
and V3; if the voltage is output by the top two capm-itors, the output current will be
drawn from junction V3 and V5. In order to keep voltage balancing, the output needs
to be rotated between three capacitor pairs, as shown in Figure 3.25. The arrows
in the figure show the current flowing into or out of each junction. It can be seen

that the voltage balancing can be easily achieved by adjusting the duty cycle of each

67

 

 

Figure 3.25. Offset voltage when [M I is less than 0.4.

capacitor pairs, D1, Dz, and D3. The switching angles of the rectifier side keep the
optimized angles with minimum THD, which is 0.1485 and 0.6249, respectively, for
a modulation index of 0.9. The average current flowing into junction V5 and V4, Iin5

and 1,7,4 are given by

2 1r/2
1...,5 = — / IRsin6d9=1.03313 (3.38)
77/2 02
2 92
and [um = —/ IRsin0d6=0.277IR. (3.39)
7r/2 91

Then the duty cycles need to satisfy

 

[in
D1 = 03 = I 502 = 4.55D2. (3.40)

1114

68

ll

Al

0 KB 21t/3

 

. 415/3 Sir/3 23c

‘
r

 

 

 

Figure 3.26. Optimized output voltage waveform when M 1 = 0.3.

Therefore, we can get

and D2 5:: 0.1. (3.42)

Since the output frequency is usually proportional to the modulation index, the
number of switchings per cycle with low modulation index operation could be in-
creased to 3 to achieve lower harmonics without increasing the actual switching
frequency, and it can be doubled to 6 because only half of the switching devices are
switching during rotation. The rotation not only reduces the harmonics components
of the output voltage but also balances the capacitor voltage. Figure 3.26 shows
the optimized output voltage when M, = 0.3. The THD of the voltage waveform
dropped from 81.3% to 16.93%. Figure 3.27 shows the comparison of the THDs be-
tween the original control and the proposed control, which shows that. the proposed
control can significantly reduce the harmonic components in the low modulation
index operation.

With the proposed control method discussed above, optimal switching angles have

been calculated, and simulations are conducted to verify the control performance.

69

 

100

90*

m
o
r
i

70...... ........ ....... ....... ........ ..... ........

50. ..... ....... . ....... .. ....... ‘

    

40 .....................................................................

: : : :Original Voltage . :
30 ... ............ - ........ ' ......... Balmng COMIOI ..... . . . . . . . .......

lrnproved Control

Total Harmonic Distortion (up to 43th) (%)

 

 

,0- ........ g ........ 3 .....

 

 

 

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Modulation Index of the Inverter Ml

Figure 3.27. THD performance of the voltage shifting optimization.

Figures 3.28 shows the simulation results for M 1 = 0.5. It can be seen that dc bus
voltages are well balanced in the steady-state operation. The voltage and current
waveforms of the rectifier (input) and inverter (output) are also shown. Although the
output phase voltage waveform may have higher harmonic components, the line-line
voltage waveform still maintains minimum THD. Because the voltages of both sides
have been optimized simultaneously, the current waveforms are nearly sinusoidal.
Similarly, simulations based on the switching rotation method were also conducted.
The dc bus voltages are well balanced in the steady-state operation. Figure 3.29

shows the simulation waveforms for M 1 = 0.3.

70

400.0
200.0
0.0
-200.0
400.0
10.0

(V)

 

0.0 "
1

MR=O.9 Ml=0.5

 

 

 

 

 

 

(V) :t(S)
Rectifier Voltage

 

(A) :t(s)

Input Current

 

 

 

 

 

(V) :t(S)
Output Voltage

 

 

 

 

 

(A) fit?)
Output Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V) = 1(8)
Output Phase Voltage

 

 

 

 

 

 

 

 

 

 

 

 

(V) ”(8)
v5

 

v4

 

 

 

 

v3

 

 

 

 

 

 

 

.5

t(s)

Figure 3.28. Simulation results of voltage shifting method for MR 2 0.9 and M, =

0.5.

MR=O.9 MI=O.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V) :t(s)
400.0 Rectifier Voltage
A 200.0
v 0.0
~200.0
-400.0 (A) :t(s)
10.0 J Input Current
2
- .. /\/\/\/\/V\/\/\/\
-10.0 (V) :t(s)
200.0 Jfl. 3 Output Voltage
3 0-0 1t if] LILLrlrrmlL7|
“at =
-200.0 (A) :t(s)
i Output Current
2‘
(V) 11(8)
400.0] Output Phase Voltage
2: 200.0
0.0 fl ' (V) :t(S)
400.0 ‘ v5
v4
’5 200.0 - v3
v2
1
0.0 l7 I I I
1.5 1.55 1.6 1.65

t(S)

Figure 3.29. Sinnilation results of voltage shifting method for MR 2 0.9 and M, =
0.3.

72

Table 3.2. Switching angles for SPWM waveform

 

Pulse 1 2 3 4 5 6 7 8
Start Angle 0.1147 0.2704 0.3943 0.6513 0.8651 1.0511 1.2201 1.3259
End Angle 0.2450 0.3508 0.5198 0.7058 0.9196 1.1766 1.3004 1.4562

 

 

 

 

 

 

 

 

 

 

 

 

 

3.6 Carrier-based SPWM Control

The carrier-based sinusoidal pulse width modulation(SPWM) Control is proven to be
able to effectively reduce the lower harmonic components. The implementation of the
carrier—based SPWM technique has been reviewed in Chapter 2.4.2. Figure 3.30(a)
shows the five—level SPWM voltage waveform, where the modulation index M is
0.7, and the carrier frequency factor 771,, which is defined as the frequency ratio of
the triangular carrier to the fundamental frequency, is 15. The sinusoidal reference
voltage ure,» is given by

2
Uref = E01 ° Vdc sin 6. (3.43)

Unlike the traditional two-level converter, which only have one triangular carrier, the
five-level converter has four triangular carriers, each one representing one capacitor
in the dc bus.

Assuming the current is sinusoidal and in phase with the voltage, we can generate
the current flowing into or out of the inner junction V4 according to the voltage
waveform, as shown in Figure 3.30(b). The average—inner-junction-c1irrent, 10,9,
which is defined as the average current following into/out of the inner junction V4,

can be calculated according to the current waveform by

271' .
'2. I .
[avg 3 C2)” = 3:: - Ewes-63,- — cos (9,3,), (3.44)

 

where 6,. and t)... are start and end angles of the pulses, as shown in T tll)l(‘ 3.2. and

73

 

.
Triangular Carriers

 

 

 

 

 

 

 

 

 

 

 

ih , , , ‘(bi

 

“Z/ll ..

Figure 3.30. The five-level SPWM output voltage and inner junction current.

ka is the peak value of the current.
The peak current [pk is determined by the input/output power and recti-

fier/ inverter voltage, as shown in

P 2P
[pk = \/§_ = ___[__ r
fly}? \/3 ' A’I ' VMaz

Substitute (3.45) into (3.44), we can get

I __ P . Z,(cos (98,- — c0506.)
avg \/67TVAI(1I 1” .

 

(3.46)

In order to sim lif the anal sis, the averarreeinner-'unction—current can be nor-
P Y Y o

malized by choosing the base value as

Nip

1a,, use = —. 3.47
9,1) fifl'l/A'lax ( )

Accordingly, The per unit value of the average-inner-junction-current I ,’,,,Q is given as

 

I’ _ 2,.(cos 63,- — cos 68,-)

— . .4
avg 4A1 (3 8)

In order to keep the voltage of the inner junction balance, the average-inner-
junction-current flowing into V4 in the rectifier side, [avgyn must equal to the average-
inner-junction-current flowing out of V4 in the inverter side, 10.09pm. Since Iavgbase
for both sides are the same, we only need to compare the per unit value. The per

unit value I ’

avg is related to the switching angles and the modulation indices only.

Once the control strategy is determined, Ifwg can be calculated without the actual
voltage and current. The usage of the per unit value makes the analysis more simple
and universal. For example, the switching angles in the current waveform shown in
Figure 3.30(b) can be calculated as shown in Table 3.2. Therefore, the per unit value
of the average-inner-junction-current can be calculate by (3.48) as 0.3498.
Similarly, the per unit value can be used for the reference voltage, Vref, and the

current, 2'4. The base voltage chosen is the voltage of each dc bus capacitor, which

is Vdc / 4, and the base current for L; is ka. Therefore, we have

, ”ref 8
= = _ M, 3.49
ref Vdc/4 71' ( )

and if, = i4/ka. (3.50)

 

Accordingly, the voltage of the five dc bus junctions become i2, :l:1, and 0. For the

SPWM control method, the peak value of the reference voltage V,.’ef needs to be less

75

than or equal 2. Therefore, the modulation index needs to satisfy

2
M < — = 0.7854 ."1

which means the maximum modulation index in this case is 0.7854.

For analysis of the SPWM control method, the switching angles are determined
by not only the modulation index, but also by carrier frequency factor and the phase
angles of each carrier. Therefore it is complex to calculate all the switching angles,
especially when the carrier frequency factor, m f, is high. However, when the carrier
frequency is far greater than the fundamental frequency, the sinusoidal reference can
be assumed as a constant value during on switching cycle. Thus the duty cycle of

the PWM waveform can be calculated by

when 15248}. 32 Dv5=v,'.ef—1
DV4 = 2 - 1):.” (3.52)

when 0 _<_ def S 1 D“ = 01.6}

Dvg = 1 — def (3.53)
when —1Sv;.ef30 Dv3='v,'.ef+1
0V2 = ‘05:] (3.54)

when —2Sv;ef§—1 DV2=U;ef+2

Dv1 = —1 — 5;”. (3.55)

According to the voltage waveform, the duty cycle of the current. flowing into

junction V1 can be written as

(3.56)

 

 

 

 

 

 

 

 

 

' ' __ High m' Simplification
. *. m'=7
1b‘l‘J #:X-fi‘i‘!‘ mf=15
O)
__a
5 can
5
o
C
.9
8 0.6” ..........
D
_,
E;
C
s
8. 0.4
S
m
>
<
0.2 _. . .............................................................
l»
1* n
0 i 1 i J l i i i
o 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Modulation Index

Figure 3.31. Average—inner-junction-currents for different M and 771;.

It can be further simplified to

014(6) =

1— abs(1— abs(% sin 6)) when 6 _<_ 7r

(3.57)
0 when v.8; > 7r

Assuming the switching frequency is high enough, the average-inner-jun(_:t.ion-current

in per unit value can be obtained by

1!

avg

22

1 27r

W 0
1 271'
m o Di4-sin6dd

1 7' 81W

-— 1— —c.l:———.' .. 5.“
4M 0 abs(1 ‘1)s( 7r sm6)) s1nl9dl9 (358)

i4 (16

Figure 3.31 shows the average-inner-junction-current of the SPW’M control for

\1
RI

different modulation indices and different carrier frequency factor. The solid line
shows the results of the simplification when carrier frequency factor is high. The
stars show the average current for different modulation indices when m; = 7, and
the dots show the results when m f = 15. It can be seen that results of the simplified
methoed are close to the results got from the actual switching angles, especially
when m f is greater than 15. Since m f are usually greater than 15 in most cases, the
average-inner-junction-current will no longer be related to 7m, which makes it easier
to analyze the charge balancing.

However, it can also be seen that different It! have different I’ In order to

avg '

I
avg,in

keep the voltage balanced, the average input current has to equal the output

I

avgmt. Unfortunately, it can only be guaranteed when both

average output current
M R and M) are less than 0.4, which means the five-level converter has degraded
to a three-level converter or M R equals M], which limits the capability to perform

variable frequency drive.

3.6.1 Control of Average-Inner-Junction-Current

In Chapter 3.5, we have tried to add an offset voltage to all phase voltage to adjust
the average current flowing into the inner junction without changing the output line-
to—line voltage. Similar method can be adopted for the SPWM control. Figure 3.32
shows the approximate waveform of the duty cycle of current 2'4. By adding proper
offset voltage, it is possible to change the duty cycle and consequently change the
average current flowing into junction V4. From Figure 3.32(b), it can be seen that
D,.; is higher when 'vjef is close to 1, and it is lower when “brief is close to 0 or 2. If

we want to reduce average—inner-junction—current I ’ we need to reduce the duty

avg?
cycle 0,4, which means choosing an offset voltage that make vief closer to 0 or 2.

On the contrary, if we want. to increase I ’ we need to choose an offset. voltage that

avg)

makes vief closer to 1. Figure 3.32(c) shows the equivalent current flowing into/ out

78

 

 

 

(a)
o pi/3 2pi/3 pi 4pi/3 5pi/3 2pi

 

 

 

 

 

 

1 T T I I T
._V
'5
.9 A
3. 9f 0 5 .
b
3
o 0 1 l 1 1 (b)
O pi/3 2pi/3 pi 4pi/3 5pi/3 2pi

 

(C)
0 pi/3 2pi/3 pi 4pi/3 5pi/3 2pi
Angle (rad)

 

 

Equivalent i'4
(Di4 sun 0)

 

Figure 3.32. Inner junction current for a given reference voltage. (a) reference
voltage. (b) duty cycle of inner junction current i4. (c) equivalent 2'4.

of junction V4, which is defined as
2748,,(6) = D,-4 - sin 6. (3.59)

In order to keep the symmetry between the three phase. voltages and within each

phase voltage, the offset voltage added to each phase. conga, needs to satisfy

Daffsedl) = Uoffsedt — 27173),
voffset“) = _voffset(7r _ t)
and coffin“) = voffsedrr + I). (3.60)

79

Therefore, for each 27r cycle waveform of 'Uoffser» only 7r / 6 can be changed indepen-
dently. Since the average—inner-junction-current is proportional to the integration of
the production of the duty cycle D and sin 6,

1 21r
I’ —

avg — m 0 D ' S111 6616, (3.61)

the duty cycle D has more influences on [avg when sin 6 has higher value. Therefore,
the offset voltage voffset will be chosen based on its value at [7r/ 3, 7r / 2], where sin6
reaches its peak.

Take the waveforms shown in Figure 3.32 as an example, where M equals 0.7. In

order to reduce I {my to the minimum, the offset voltage is chosen as

voffset(6) = 2 — Uref(6) when 6 E [7r/3, 7r/2]. (3.62)
From (3.60), the rest part of Uoffset can be given by

v;6f(6 + 7r/3) — 2 when 6 E [0,7r/3]

2 — 'vief(6) when 6 E [7T/3, 27r/3]

'Uoffset,min(6) = (3.63)

voffset,,m~,,(6 — 27r/3) when 6 E [27r/3, 47r/3]
voffset,,m-,,(6 — 47r/3) when 6 E [47r/3, 2a]

The sinusoidal reference voltage, oflset voltage, and the phase reference voltage,
which is the sum of the first voltage, are shown in Figures 3.33(a) and (b). Based
on the phase voltage, the equivalent inner junction current 2],“, can be calculated
by (3.59) and shown in Figure 3.33(c). It can be seen that. the new phase voltage
equals 2 when 6 is in [7T/3, 27r/ 3] tlmrefore the inner junction current in that range
becomes 0. Therefore, even though the equivalent current is slightly higher than

before, the average current is still much lower than that without the. offset voltage.

80

 

offset and Vr

V

 

 

 

 

 

 

PhaseVoItage
O

 

 

- (b)

 

 

 

 

 

 

_2 1 1 l
1 V Y Y I I
.‘—' I o
E go‘s I- avg =0.26951 «1
g ' v
.5 o’- 0 ‘4:
E v
0 5 l 1 l l l (c)
' o pi/3 2pi/3 pi 4pi/3 5pi/3 2pi

Figure 3.33. Offset voltage with minimum inner junction current.

The average-inner-junction—current of this control method I’ is 0.2695.

avg,min

Similarly, we can choose an offset voltage to maximize the average current by

making the phase voltage equals 1. Therefore the offset voltage is chosen as

voff,,e,(6) = 1 — v;6f(6) when 6 E [rt/3, 7r/2]. (3.64)

According to the symmetry constraints (3.60) the offset voltage for 6 6 [7r / 6, 7r/ 3] is
given by

coffse,(6) = 1):.Cf(27T/3 — 6) — 1 when 6 E [7r/6, 7r/3]. (3.65)

On the other hand, the phase voltage with the offset voltage can not exceed 2,

otherwise, the line-to—line voltage will be changed. Thus the offset voltage also needs

81

to satisfy

Uoffset(6) S 2 — {Ufef(6)' (3'66)

Therefore the offset voltage with maximum average current in range [7r/6.7r/3] is

given by
voffset(6) = min(2 — '1);6f(6), ’U;6f(27T/3 — 6) — 1) when 6 E [7r/6, 7r/3]. (3.67)

And the full offset voltage can be obtained from the symmetry constraints given in

(3.68).

r
min(2 — v;ef(7r/3 — 6), v;8f(7r/3 + 6) —1 when 6 E [0, 7r/6]

min(2 — 'v;8f(6),v;ef(27T/3 — 6) -1 when 6 E [7r/6, 7r/3]

n1ax(v;ef(27r/3 — 6) — 2,1 — v;6f(6) when 6 E [7r/3, 7r/2]
voffset,ma$(6) = <
max(v;ef(6 — 192/3) _ 171— Ufef(7r _ 9)

voffset,max(6 — 27r/3 when 6 E [27r/3, 47r/3]

 

)
)
)
) when 6 e [7r/2, 27r/3]
)
)

when 6 E [47r/3, 27r]
(3.68)

U0ffset,maz(6 — 471/3

Figure 3.34(a) shows the reference voltage and the corresponding offset voltage
based on the previous analysis. The phase reference voltage after the offset voltage
been added is shown in Figure 3.34(b). It can be seen that the new phase voltage
is close to 1 when 6 is within [7r/ 3, 27r/ 3], therefore the duty cycle of the current is
also close to 1 in [7r/3,27r/ 3], where the current reaches its peak. The equivalent
inner junction current 174..., is shown in Figure 3.33(c). Although the offset voltage
added slightly reduced the current duty cycle when 6 is within [0, 7r / 3] and [27r/ 3. 2].
the overall average current. is maximized. The average-inner-junction-current of this

control method I’ is 0.4236.

avanaI,

82

 

and v
ref

oflset
o

V

 

 

(a)

 

 

PhaseVoItage
O

(b)

 

 

 

I
N

 

 

d
u

r I

I '=0.42361 .

inner

p
m
I

'sine)

 

Equivalent i'4
(0,,
O

 

 

l l l l l (C)
pi/3 2pi/3 pi 4pi/3 5pi/3 2pi

 

P
or
0

Figure 3.34. Offset voltage with maximum inner junction current.

3.6.2 Voltage Balancing in the Carrier-based SPWM Con-
trol

In the previous section, the effect of the offset voltage on the average-inner-junction-
current is discussed, and maximum and minimum values of the average current when
modulation index equals 0.7 are given as an example. However, we also need to find
a way to easily adjust the average current to any value between the maximum and
minimum.

From Figure 3.33, it can be seen that offset voltage Voffset,min has three positive
pulses and three negative pulses. The widths of all the pulses are 7r / 3. If the pulse
width is reduced, the average current will be increased accordingly. Similarly, the

average current will be reduced if the pulse width of the Voffsemmx is reduced. The

83

offset voltage with different pulse width W is defined as

r .voffsetmmw) when 6 e [Egg—17, _ _ab_sz<u_> 21-75447, + w]
and W > 0
voffset(W,6) = i voffset,mm(6) when 6 E [2kT+17r _ LEE), 21%;” + grim] ,
and W < 0
( 0 else

 

(3.69)
where k equals 0,1,...,5.

The pulse width W in (3.69) satisfies —7r/3 S W 3 7r/3. The sign of the W
represents which offset voltage is chosen. When W is greater than 0, it represents
the new offset voltage is based on 'Uoffset,min. When W is less than 0, it represents
the new offset voltage is based on voffsetmax. The absolute value of W determines
the pulsed width based on the chosen offset voltage. The effect of the corresponding
offset voltage can be calculated as shown before. Figure 3.35 shows the relationship

between I ’ and W when the modulation index equals 0.7. It can be seen that the

avg

average current can be changed to any given average current I"mg between 1,2,va

and Ifwgmm by adjusting the pulse width.
Similarly, Igvgmx and Ifwgmin for different modulation indices can be calculated

and shown in Figure 3.36. The top line shows the maximum average current vs.
modulation indices, and the bottom line shows the minimum average current vs.
modulation indices. The area in between is the operation region of the carrier-based
SPWM control.

In order to balance the voltage of the dc bus. the average input current from the,
rectifier side needs to be equal to the average output current from the inverter side.
In the adjustable speed drive applications, the rnmlulatirm index of the rectifier, A IR.

usually keeps constant, and the modulation index of the inverter, All 1, varies from

84

 

0.5

0-45 t l =0.4236

I
avg,rnax

avg
.0
g -
1

  

0.35 -

.0
w

 

0.25 r

.0
m
1

Average Inner Junction Current I'

O

L.

01
T

V
offsetmin

voffsetmax

 

0.05 r

 

 

 

o

A
_._._._._V_._._,_._.-,_._._._

o A

o l
pi/3 pi/6 pi/6 pi/3

Pulse \Mdth W

Figure 3.35. Relationship of average-inner-junction-current Ifwg and pulse width W

0 to M R for different output speed. In order to be able to find an average-inner-
junction-current which can be generated by both sides, the following equations need

to be satisfied for any given M R and 111;,

Idvg,ma.r(]l/[R) > Ic’wg,min(]ljl)v (370)
Idtvg,n1in(A[R) < Ic’wg.max(jlll)' (371)
Therefore, 1W}; needs to satisfy
Igvgmwa) > max(I(',,,g,mm(1W)) for 1)] < MR, (3.72)
(’wg,min(A[R) < min(1clrvg,max(A/I)) for 1I\l< J'l/R. (3.73)
It. can be seen from Figure 3.36 that the I;,,,g,,,,a$(1ll) is decreasing function. so

85

 

 

avg

    

Average Inner Junction Current I'

-0-2 —— ———————————— l'avg‘min .
(D
N
—o 4 — —————————— gel
0'I
-0.6 r— ———————— g

 

 

 

c':

(D
T
I
l
l
I
I
I
I

 

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Modulation Index M

Figure 3.36. Relationship of average-inner-junction-current Ifwg and modulation in-
dex M

(3.73) is always satisfied. On the other hand, 669mm has a peak value of 0.2695 at
[W = 0.7. Thus MR needs to satisfy Qmax(MR) > 0.2679. Therefore AIR needs to
satisfy

MR < 0.7826. (3.74)

It is desirable to have a higher M R for higher device utilization, however it is also
important to leave some margins. Therefore M R can be set to be 0.75. The average

input current for the rectifier needs to satisfy

min(1€,lvgemfllf(0 ~ 075)) 2 Iriwg 2 max(](,1vg.mm(0 N 075)): (3.75)
which is
03264 2 1,1,9 2 0.2695. (376)

86

 

......

F’
A

.0
n)
omwumn

 

..... . ..........

Pulse WIdth of the Offset Voltage
3 o
I
I
l
I
_L

 

C
h
I
L4,

9:

a:
T.

i

 

 

 

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Modulation Index

 

.0
I»

c:
)—

Figure 3.37. Required pulse width for I ' — 0.3

avg '-

I
avgfin

Therefore the average input current can be set to 0.3. For the inverter side,
the average output current Ifwgmt needs to keep 0.3 for all modulation indices from
0 to 0.75 to keep charge balancd.

For M = 0.7, the required pulse width of the offset voltage for Ifwg = 0.3 can be

calculated from Figure 3.35. Similarly, the pulse widths required for other modulation

indices can be calculated and shown in Figure 3.37.

3.6.3 Simulation Results of Carrier-Based SPWM Control

Based the pulse width given in Figure 3.37, the offset voltage can be generated
and added to the phase voltage. In the rectifier side, M R keeps 0.75. The carrier

frequency is 2 kHz. The pulse width of the offset. voltage is set to 0.49 so that the

87

I

avg‘m, becomes 0.3. The sinusoidal reference and the Offset

average input current,
voltage, the phase reference voltage, and the equivalent inner junction current are
shown in Figure 3.38.

The average output current of the inverter side is also set to 0.3 by choosing
proper offset voltage for different 1W 1. Figures 3.39 to 3.41 show the offset voltage
waveforms for [W] equals 0.5, 0.25, and 0.1, respectively. It can be seen that the
output average current keeps 0.3 regardless the modulation index. Therefore, the
voltage of the dc bus can be well balanced. The simulations based on proposed offset
voltages are conducted. The detailed simulation waveform are given in Figures 3.42

to 3.44. The dc bus voltages are well balanced, and both input and output currents

are sinusoidal.

88

 

rel

 
 

 

and v

L1,.
W=0.49 Voffset

 
  

offset

V

 

 

(a)
_2 I l
0 pi/3 2pi/3 pi 4pi/3 5pi/3 2pi
2 . . V. . . . . . , 1 .

 

 

    

PhaseVoItage
o _A

 

 

 

 

 

 

 

 

-1 r-
_2 ... ______ . . 4. , , (b)
0 pi/3 2pi/3 pi 4pi/3 5pi/3 2pi
1 1' r I I I
=-' I' o 3
E g 0 5 " avg- ‘
if)
g ' t o
a D
0" v
L“ (c)
_o.5 .1 l. J. I. 1. I
pI/3 2pI/3 pI 4pI/3 SpI/3 2pI

Figure 3.38. Offset voltage waveforms for [W = 0.75, (a). the sinusoidal reference
and the offset voltage, (b). the phase reference voltage, (c). the equivalent inner

junction current.

 

   
 

 

 

 

 

 

 

 

   

 

 

 

 

 

 

 

2 T T l l l
E
>
2
m. 0 Voffset
8
:5 W=0.638
_2 A l 1 1 1 (a)
0 p'I/3 2pi/3 pi 4pi/3 5pi/3 2pi
2 ....1 1...“... ...1. .,
Q)
6
>
O)
U)
m
.C
0 pi/3 2pi/3 pi 4pi/3 5pi/3 2pi
1 T 1 I I I
...-V
E .
g
m
.2
(:7 \f“
In
(C)
-0-5 .‘ ‘. ‘. f f .
0 pI/3 2pI/3 pI 4pI/3 SpI/3 2pI

Figure 3.39. Offset voltage waveforms for M = 0.5. (a). the sinusoidal reference and
the offset voltage, (b). the phase reference voltage. (c). the equivalent inner junction

current.

89

 

 

 

 

 

 

 

 

 

 

 

 

 

2 I I I I I
E, Voffset ——
; vref
E o
E
‘6 W=0.3692
>
-2 f l 1 L 1 (a)
0 pi/3 2pi/3 pi 4pi/3 5pi/3 2pi
C)
0)
g
o
>
o
:8
If
(b)

 

 

 

 

o pi/3 2pi/3 pi 4pi/3 7 : 5pi/3 2pi

 

 

 

Equivalent i'4
(DM'SInG)
O

 

 

, , (C)
pi/3 2pi/3 pi 4pi/3 5pi/3 2pi

 

l.
0

Figure 3.40. Offset voltage waveforms for M = 0.25, (a). the sinusoidal reference
and the offset voltage, (b). the phase reference voltage, (c). the equivalent inner

junction current.

 

vrel

 

 

 

 

and v
re
0 to
<
o .
2
3.

 

 

 

 

 

 

Voffset
E
. II
’ P
w
8

 

 

PhaseVoItage

 

 

 

 

 

0.5 I I I I I
f.” I‘
6 35 E” "9:03
'6 .‘7’ 0
.2 a
:I 0 KJ V—
g v
_O 5 1 l L (C)

 

 

 

Figure 3.41. Offset voltage waveforms for M = 0.1, (a). the sinusoidal reference and
the offset voltage, (b). the phase reference voltage. (c). the equivalent inner junction

current.

90

 

 

MR=0.75 Ml=0.50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V) :t(s)
1000.0 7 Source Voltage
500.0 ‘
a 0.0 - Rectifier Voltage
-500.0 ‘
-1 000.0 ‘ (A) : t(s)
20.0 ' Input Current
'20-0‘ M :t(s)
1°°°~° _ Output Voltage
9 500-0 .WTIMLWI‘ WWW.“ W
v 0.0 III , I III '
-5oo.o I“ " “uh-r“ Mimi
-1000.0 (A) :t(s)
20.0 ‘ Output Current
5 0.0 M
-20.0 (V) 21(8)
800.0 . ,5
600.0 ‘ v4
5 400.0 * v3
200.0 V2
0-0 - I I I I I I
1 .95 1.96 1.97 1 .98 1.99 2.0

t(s)

Figure 3.42. Simulation results of SPWh’I control for MR = 0.75 and ill, : 0.5.

91

MR=0.75 Ml=0.25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(V) :t(s)
1000'0 , , Source Voltage
500.0 "
E 0.0 ‘ Rectifier Voltage
-500.o ‘ ,
.l
-1000.0 (A) :t(s)
4.0 Input Current
A 2.0
3 0.0
-2.0
“4.0 ' (v) ”(3)
1000.0 Output Voltage
500.0 _ ‘ mm, ‘
E 0.0 1.18.le ! ' ‘ Mlfilmmu
-500.0 '
4000.0 - (A) :t(s)
10.0 ‘ Output Current
g 0.0 ‘ W
-10 of
' (V) :t(s)
800.0 - v5
600.0 . v4
3 400.0 ‘ A: Av; _A A. A: _V vs
200.0 ‘ V2
0-0 -r I I I I I
1.9 1.92 1.94 1.96 1.98 2.0
t(s)

Figure 3.43. Simulation results of SPWM control for NR = 0.75 and ill, 2 0.25.

92

1000.0 1
500.0 .

E 0.0 -
-soo.o -

MR=0.75 Ml=0.1

 

 

-1000.0 ‘
2.0 '

3 0.0‘

 

 

 

 

 

-2.0 ‘

1 000.0
500.0
0.0
-500.0
-1000.0

4.0 '
A 2.0 ‘
33 0.0 ‘
-2.0 i
-4.0 ‘

800.0 7

(V)

600.0 *
3 400.0 1

200.0 ‘

 

 

 

 

(V) 21(5)
Source Voltage

 

Rectifier Voltage

 

(A) 3(8)
Input Current

 

(V) : 1(8)
Output Voltage

 

 

 

 

 

 

 

 

 

 

 

0.0 ‘
1

(A) ”(8)
Output Current

 

(V) ”(8)
v5

 

 

 

 

 

v4

 

v3

 

 

.8 1.85 1.9 1.95 2.0

Figure 3.44. Simulation results of SPWM control for MR = 0.75 and ill, = 0.1.

93

 

 

@ @ DC ® @
Pm BUS _P21L>

V0

 

 

 

Figure 3.45. Power flow of the back-to—back system.

3.7 DC Bus Voltage and Reactive Power Control

In the previous sections, we focused on the voltage balance of the dc bus capacitors
in the back-to-back structure. Now we will discuss the implementation of the other
two important features of the back-to-back structure, the dc bus voltage stabilization

and the input reactive power control.

3.7 .1 DC Bus Stabilization

Figure 3.45 shows the power flow of the system. The back-to—back converter can be
viewed as two voltage sources, rectifier voltage VR and inverter voltage V0, sharing
the same dc bus.

For the rectifier side, two voltage sources are connected via an inductor. The

power flow from the utility voltage source V3 to the rectifier voltage VR is given by

V3 V3

L

 

Pm = 3 sin 6, (3.77)

where (5 is the phase difference between V5 and V3. When V5 is leading V3, 6 is
positive. The power flows from the utility source to the rectifier. When V5 is lagging
V3. 6 is negative. The input power is negative , so the power flows from the rectifier
back to the source. Therefore the bidirecticmal power flow control ability of the

back—to-back can implement the energy regeneration easily.

94

For the inverter side, the inverter is directly connected to load. The power flowng

to the load is given by
V6

P01tt23R)

(3.78)

where R is the phase resistance of the load.
The rectifier voltage VR and inverter voltage V0 is controlled by modulation

indices AIR and 111,, respectively,

W5de

71'

V0 = M, - VMax = M,-

 

(3.79)

When the input power Pm does not equal the output power PM, the net power
flow will result in the voltage increase or decrease of the dc bus. For example, if Pm
is greater than Pout, the voltage across the whole dc bus, Vdc, will increase. Since
P0“, is a quadratic function of Vdc, while Pm is proportional to Vdc, there exists a
new stable equilibrium point where Pin equals Pout, as shown in Figure 3.46.

It can be seen that several factors will affect the equilibrium value of Vdc. If
the load decreases or M, increases, the Pout vs. Vdc curve will move up, thus the
equilibrium value of Vdc will decrease. Similarly, the increase of 6 and MR will result
in the increase of Vdc.

In order to stabilize the voltage of the dc bus, the input power of the dc bus Pm
has to be adjusted to follow the output power Pom. Since adjusting M R will change
the power factor and input current, adjusting 6 is the only practical way to stabilize
the voltage of the dc bus. Therefore, a feedback control is introduced to stabilize the
dc bus voltage, as illustrated in Figure 3.47, where the voltage difference of the actual

voltage Vdc and the reference voltage Vd; is obtained and fed into a PI controller.

P } Po... lRl Mil

 

 

 

Figure 3.46. Equilibrium point of dc voltage.

 

PI >

 

 

 

 

Figure 3.47. Feed back control of the voltage of the dc bus.

96

 

 

 

 

s
V
“S . V > Vs Currentisleading
V R jISXL R 008 5 Voltage
IS VS o o
, V : vs. Current is In phase
VR ‘ ISXL R 006 5 with Voltage
VS a o
5 P V < Vs Currentislaggmg
- R
Is V ISXL ‘ Voltage

Figure 3.48. Phasor diagram of leading, in phase and lagging current.

3.7 .2 Input Reactive Power Control

Figure 3.48 shows the phasor diagram of the rectifier side. It indicates that the source
current can be either leading, lagging or in phase with the source voltage according
to different phase difference 6 and modulation index M R.

It can be seen that when VR is greater than V3, the input current is leading the
source voltage, producing a leading power factor. The system injects reactive power
to the utility. When VR is smaller than VS, the input current is lagging the source
voltage, producing a lagging power factor. The system absorbs reactive power from
the utility.

Also when VR 2 VS/ cos6 is satisfied, the input current will be in phase with the
input voltage, producing the unity power factor.

Therefore, by adjusting M R, we can get the unity power factor, or inject. / absorb
desired reactive power in/ from the utility. The switching angles shown in Table 3.8
are results of MR = 0.9 only. Considering the vary of the input voltage V5 and
the phase difference 6, a larger set of switching angles for different. 11],, need to
be calculated. With the method discussed in Chapter 3.2.1, the optimal switching

angles when MR varies from 0.85 to 0.95 are shown in Figure 3.49.

97

.6

Switching Angles (rad)
.0 .o
O) O)

0.4

0.2

Optimal Angles with MR = [0.85:0.01:0.90]

 

 

v I v r

 

 

 

 

 

I

 

Switching Angles (rad)
0
be

0.4

0.2

0.2 0.4 0.6 0.8 1
Modulation Index of the Inverter M.

 

Optimal Angles with MR = [0.90:0.01:0.95]

 

 

 

 

 

 

 

 

\ _ 6R1
H 9R2
811
el2
‘\ f1 .
fffl‘fir _
\mfi‘k .
.. is".
\
\
\
\\
\\\ ..
\ _
0.2 0.4 0.6 0.8 1

Modulation Index of the Inverter MI

Figure 3.49. Optimal switching angles of different. NI 3.

98

In the carrier-based SPWM, MR can also be changed. In the balanced carrier-
based SPWM control, the pulse width of the offset voltage needs to be changed
according to M R to keep the average inner junction current in the rectifier side same.
But 111,; must be less than a certain value in order to keep the charge balanced.
When desired [avg equals 0.3, the maximum MR equals 0.764. The desired 1,1,9
can be changed to get higher maximum M 3. However, as mentioned in (3.74), the
maximum M R to guarantee voltage balanced is 0.7826. Similarly, a feedback control

can be introduced to realize the unity power factor control, or achieve other desired

power factor.

3.8 Summary

In this chapter, the detailed capacitor charge/discharge mechanism in the multi-
level back-to—back converter was analyzed. The voltage balancing constraint for the
switching angles was given. The voltage balancing control was proposed by choosing
the switching with lowest THD under the voltage balancing constraint.

Although the fundamental frequency switching is the simplest control methods,
it has relatively higher harmonic components, especially with low modulation index.
Therefore, several revised control methods were proposed to improve the control
performance.

Furthermore, a new voltage balancing control based on carried-based SPWM,
which can effectively eliminate the lower order harmonic in the output voltage, was
proposed. The voltage balancing effects of the triplen harmonic offset voltage added
to all three phase voltages were discussed. The proposed control utilized the offset.
voltage to control the average currents flowing into and out form the inner junction.
The voltage balancing was achieved by selecting proper offset voltages for both sides.

At last, dc bus voltage stabilization and input power factor control were implemented.

99

CHAPTER 4

Multilevel Converter Topology

with Reduced Number of Devices

4. 1 Introduction

Although multilevel converters have a lot of advantages over the traditional two-
level converters, their complexities still present a major challenge. Take a five-level
converter as an example, 24 switching devices and 18 diodes (36 if the diode with the
same voltage rating as switching device) are needed. If the back-to—back structure is
used, the number of devices will be doubled. The large number of devices not only
increases the control complexity and system cost, but also increases the difficulty of
layout and lowers the reliability.

In this chapter, a revised multilevel topology based on the back-to—back diode-
clamped structure is introduced. The proposed topology has reduced the number of
clamping diodes. New control methods for the revised topology are also included.
For the rectifier side, the number of devices can be further reduced. A novel five—
level rectifier front-end is proposed. Its control strategy and control performance are

included. Detailed comparison shows its advantages and disadvantages.

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N
.I S
N-l
Vdc/(N-l) ,.\ p‘ )
D
VAL] I PfN'U ’
DWJ, $1}sz
.Dp3
" J S 1
V3 fi p v0
D "3 J Sn(N-l)
Vd/(N-I) ,N
p2
V 2 ’
Dn2 J Sn2
V dc/(N-I )

Figure 4.1. Diode-clamped N-level converter phase leg.

4.2 Multilevel Inverter with Reduced Number of
Clamping Diodes

Figure 4.1 shows the topology of an N -level converter phase leg. The voltage rating
of each switching device remains Vdc/ (N — 1), but the voltage rating of the clamping
diodes will increase with the increase of N. The total voltage rating of each clamping
diode pair, Dpx and Dm. is always Vdc. For example, the voltage ratings of DP, and
07.1 are (N — 2)Vdc/ (N — 1) and Vdc/ (N — 1), respectively, and the voltage ratings of
0,02 and Dn2 are (N — 3)Vdc/ (N — 1) and 2Vdc/ (N — 1), respectively. It can be seen
that the voltage ratings of some diodes are much higher than those of the switching

devices, especially when N is high. In medium voltage drives, the required voltage

101

 

 

 

 

 

 

\l

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V2
J
—: 5.3.
1
SM J

 

 

 

(b)

Figure 4.2. Reduction of the clamping diodes in the multilevel converter.

rating of the clamping diodes is much higher than the maximum voltage rating of the
available devices. Assuming that the clamping diodes with the same rating voltage as
the switching devices Vdc are used, the number of the diodes required for each phase
will be (N — 1) x (N — 2). The number of clamping diodes increases quadratically
with the increase of number of levels, N, which increases the system cost significantly
and makes the system extremely hard to layout when N is sufficiently high.

Figure 2.2 (b) shows a traditional diode-clamped five-level converter, where six
diodes with total voltage ratings of 3chC are used. The diodes provide the conducting
path when the converter outputs the inner three voltage levels, V4, V3, or V2. For
example, when switches SP2, SP3, SP4, and SM are turned on, the converter output
is clamped to voltage junction V4 via DP, and Dnl. There are two current paths
between V, and the output. When the output current is positive, the current flows

through diode Dpl, switches SP2, 5123 and SP4. When the output current is negative.

102

Two-level

 

 

Converter

——————— 1

: V S 41

I 5 '

I J lg : Three-level
Vdc/4 l :: v‘ Converter

I r"-‘--j

I

 

 

-
‘

 

 

 

 

L1__-_£%l
V 4 _Z '
61/ V1 DpZ: V0
3 D |
V dc/4 :: "2:
’ " ‘‘‘‘ 1
l Vzl S“: l
i J I i
, ..
Vd/4l T :3;
I
J I
IV '
L:1__§El
Two-level
Converter

Figure 4.3. Proposed five-level converter topology with reduced number of clamping

diode.

the current flows through switch Sm and diode Dal. As we mentioned before, diode
Dpl only needs to block the voltage of one capacitor, VCap, which is Vdc/ 4. Diode
Dnl needs to block the voltage of 3Vcap, as shown in Figure 4.2 (a).

It can be seen that diode D", is only used to provide the current path for the
negative current when the converter outputs V4. Therefore, if an active switching
device is used to replace the diode Dpl, diode D1,, can be eliminated from the topol-
ogy. Similarly, we can use another switching device to replace diodes Dp3 and Dn3,
as shown in Figure 4.2(b). Although two new switching devices are added, the total
number of active switching devices remains 8 because switches (SP3, SP4) and (Sn-1,

Sng) can be replaced by two devices with voltage rating of 2VCap.

103

Table 4.1. Output voltages and corresponding switching states of the proposed five-
level converter topology.

 

 

 

 

 

 

OUtPUt UaO Spl SP2 Sp3 3114 Sn] 3712 $113 5714
V5 1 1 0 1 0 0 0 0
V4 1 1 1 0 O 0 0 0
V3 1 0 0 0 1 0 0 0
V2 0 0 0 0 I 1 1 0
V1 0 0 0 0 l l 0 1

 

 

 

 

 

 

 

 

 

 

 

The proposed topology can also be redrawn as a combination of the two-level
and three-level converter cells as shown in Figure 4.3. Since a two-level converter
replaces the original positive bus of the three-level converter, the voltage stresses on
the two inner switching devices and two clamping diodes are increased. The required
voltage ratings of the switching devices SP1 and Sm, and the clamping diodes ng and
Dn2, are 21/001,. All other switching devices only need to block V001,. The switching
pattern of the proposed multilevel converter topology is given in Table 4.1.

Compared with the traditional diode-clamped five-level converter shown in Fig-
ure 2.2(b) , it can be seen that the number of clamping diodes is reduced significantly.
In the proposed topology, only 2 diodes are needed, and the total voltage rating is
only Vdc, while 6 diodes with total voltage rating of 3V0,C are needed in the traditional
topology. On the other hand, the total voltage rating of the switching devices have
a slight increase from 8Vdc to 10Vdc. Equivalently, each switching device replaces 4
diodes with same voltage rating. Considering the price of the high-voltage diodes
and switching devices, the proposed topology not only has fewer components, but
also is more cost-efficient. The detailed comparison of two topologies is given in
Table 4.2.

The proposed topology can be easily extended to the multilevel converters with

higher number of levels. For a diode-clamped N-level converter, it can be imple-

104

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K:—
N _1 T Clamp
2. Converter —
Capacrtors (N -Level)
2
L’\
f
Output
N ,11 < Converter ——
C apacrtors (N -Level)
1
k
r.—:—-
Clamp
Cangichiltors Converter
.l. (N 2—Level)
(I‘—

 

 

 

Figure 4.4. Combination of three multilevel converter cells.

mented by a combination of three different multilevel converter cells, as two-level
and three-level converters shown in Figure 4.3. To generalize this, Figure 4.4 shows
a structure that is a combination of three multilevel converter cells. Assuming that
the number of levels of the output converter is N,, and the number of the clamping

converters is N2. The relation of N1, N2, and N is given by

For example, if the two clamping converters are, two—level converters, the output
converter will be an N — 2 level converter. And if the two clamping converters are
three-level converters, the output converter will be an N — 4 level converter, so on

and so forth. It can be seen that the higher the number N is. the more flexible the

105

 

 

Table 4.2. Comparison of the proposed topology and the traditional topology.

 

 

 

 

 

 

 

 

 

 

Proposed Traditional
Topology Topology
Number of the Clamping Diodes 2 6
Total Voltage Rating of the Clamping Diodes 4Vdc 12V“,C
Maximum Voltage Rating of the Clamping Diodes 214,C 3V0,C
Number of the Switching devices 8 8
Total Voltage Rating of the Switching devices 101/dc 8Vdc
Maximum Voltage Rating of the Switching devices 2Vdc Vdc

 

 

combination could be. The structure even can be cascaded to minimize the number
of devices and total device rating if the level number of the clamping converter is
higher than 5.

Figure 4.5 shows two different topologies of a seven-level converter phase leg.
The left one is a combination of three three—level converters. If all upper switches
are turned on, the clamping diode DP, needs to block VCap plus the whole dc bus
voltage of the clamping converter, (N2 —1)VCap, which is 21/00,, in this case. Similarly,
the voltage rating of clamping diodes Dnl and the inner most switching devices,
SP1 and Sng need to be increased to 3Vdc. The right one is a combination of a
five-level converter and two two-level converters as clamping converters, where the
voltage rating of all other clamping diodes in the output converter and the inner
most switching devices, SP1 and Sng need to be increased by VCap. The comparison
of two topologies and the traditional one is given in Table 4.3.

From Table 4.3, it can be seen that both proposed topologies reduce the total
voltage rating of the clamping diodes significantly at a price of increasing the total
voltage rating of the switching devices slightly. The ratios of the reduced diodes
rating and increased switching devices rating in the two topologies are 5:1 and 6:1,

respectively.

106

 

 

d

 

 

.5 l: 5
l t— L
I. ——--,-____l
“C4
Q

-\l'

 

V2

 

Cl:
C.

\ I

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4.5. Two different topologies of revised seven-level converter.

107

Table 4.3. Comparison of the proposed seven-level topologies and the traditional

topology

 

 

 

 

 

 

Proposed Topology Proposed Topology Traditional
in Figure 4.5(a) in Figure 4.5(b) Topology

Number of the Clamping 6 8 10
Diodes
Total Voltage Rating of 101/Cap 181/00,, 301/00,,
the Clamping Diodes
Number of the Switching 12 12 12
devices
Total Voltage Rating of 16VCap 14VCap 121/00,,
the Switching devices
Maximum Voltage Rating 3VCap 2VCap V0,”,
of the Switching devices

 

 

 

 

 

 

VCap = Vdc/6

4.3 Multilevel Rectifier with Reduced Number of

Switching Devices

4.3.1 Replacing the Top-most and Bottom-most Devices

In the rectifier side of the back-to-back structure, the number of clamping diodes can
be reduced as discussed in 4.2. Furthermore, the number of switching devices can
also be reduced.

According to the analysis in 2.3.4, the uppermost and lowermost switching devices
can be replaced by diodes in the rectifier application. Therefore, the phase leg of the
five-level rectifier shown in Figure 4.3 can be simplified to Figure 4.6.

The primary concern with reduced-devices-count rectifiers, which is the limita-
tion on the performance due to the reduced number of switching devices, has been
addressed in [48]. Although four-level rectifiers are discussed as examples in [48]. its

conclusions can be easily extended to five-level rectifiers.

108

 

 

 

 

 

Figure 4.6. Five-level rectifier phase leg with reduced number of switching devices.

The space vector diagram for five-level rectifiers with reduced number of switching
devices is shown in Figure 4.7. Some of the space vectors marked with “x” are no
longer available due to the absence of the switching devices. The remaining voltage
vectors are available for use by the modulation. However, the vectors marked with
“0” do not have redundant states any more. The resulting area available for voltage
synthesis is indicated by the dotted hexagon.

In order to determine the limitation imposed on the reduced-devices—count recti-
fier, the voltage vector must lie inside the dotted hexagon. Based on analysis in [48],

the primary limitation is the bottom-most edge of the hexagon requiring that

vi 3 (4.2)

109

 

 

 

 

 

'0', “‘Q
x x e—c .; t t o H
I
. /
x x q o o o o ,l
0‘ I'
‘. I
x x e I; o o b
‘~. .’
\x‘ ['0

 

Figure 4.7. Space vector diagram of five-level rectifier.

The limitation on the command q-axis current is

1 4v;_\/2VLL]
wuL 9 3 '

 

litil S (4.3)
Equation (4.3) may be used to evaluate the suitability of the five-level reduced-

devices—count rectifier under specific operation conditions.

4.3.2 Proposed Simplified Five-level Rectifier

Uncontrolled diode bridge rectifiers are the simplest way to converter input ac voltage
to dc voltage on the dc bus, where only 6 diodes are required. However, during the
operation of the inverter, the voltage junction V4 will keep falling because the positive
current flowing out of it to the load. Similarly, the voltage junction V; will keep rising

because the negative current. flowing out of it. Eventually. capacitor (72 and ('3 will

110

 

 

 

Figure 4.8. Proposed simplified five-level rectifier.

be completely discharge, and capacitor C, and 0.; will be both charged to half of the
dc bus. The five—level converter then converges to a three-level converter.

The five-level active rectifier, on the other hand, not only feeds current to the
positive and negative dc bus, but also provides current path to inner junctions to
balance the junction voltages. Therefore, it requires more switching devices. From
the analysis in Chapter 3.2.1, the average current flowing out of the neutral point
is always zero if the output currents are balanced and symmetric. Therefore it. is
possible to further simplify the rectifier by eliminating the neutral point. current
path.

Figure 4.8 shows the schematic of the proposed simplified five-level rectifier. Com-
paring with the schematic shown in Figure 4.6, clamping diodes 0,02 and I)”, are
removed, and the switching devices (SP1, SP2) and (Sm, Sng) are replaced by two

diodes. On the other hand, the proposed topology can be seen as a derivation from

111

 

Phase Voltages

Va vb c

W >
Diode Conduction Sequence

c Da Da Db Db ['3 DC
D’b 25'5 DC DC D’a [m 253

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sa J U 1

Sb 1 [_l l

Sc —l 1 LJ

S 'a 1 LJ 1—

S 'b LJ 1 l—

S'C I—LI—‘L >

 

Figure 4.9. Fundamental frequency switching for the proposed five-level rectifier.

uncontrolled diode bridge rectifier. The upper diode in phase a is split to Dal and
Dag, and an active switching device So is added between voltage junction V4 and
the middle point of Dal and Dag, which provides a current path to voltage junction
V4. In this topology, the voltage stresses on diode Dal and switching device 30 are
limited to one capacitor voltage level, while diode D02 needs to block a voltage of
three capacitors. The total charge flowing into voltage junction V4 could be con-
trolled by proper control strategies. By regulating the net charge flowing into the
voltage junctions to zero, the voltage of the dc bus can be balanced. Compared to
the fully active rectifier structure, the proposed topology has much less number of
active devices.

The simplest way to control the proposed rectifier is the fundamental frequency

switching. The active switch is switching twice every fundamental cycle, allowing

112

 

(V): 1(8)
600.0

 

 

 

 

 

 

02
w—‘n-‘v‘-r‘~*mJ-'-¢'”mer2—~ r~-——-p-m‘—-J—-l——_:—-. ct
114
400.0 1
WWW
300.0. "3
E
“- _-~*~---*\.fi—q—N~~P\x-\r’-w— --..-"‘~"—\-.«-‘—'~\/—‘-v~”\—V-"\.u*‘ V‘"-v—"~.«
200.0
1 00.. ‘ W~MWfHPWW
0.0 '
I I I I
0.9 0.92 0.94 0.90 0.90 1.0
t(s)

Figure 4.10. Simulated dc bus voltages for the proposed rectifier.

currents to flow into inner voltage junctions V4 and V2 and charge capacitors C2 and
C3. The phase voltages and the control signals of the switching devices are shown
in Figure 4.9. The voltage unbalance is measured and fed into a PI controller. The
pulse widths of the all gate signals are controlled by the PI controller to balance
the voltage on each voltage level. Figures 4.10 shows the simulation result of the
dc junction voltages for the proposed fundamental frequency control. Figures 4.11
shows the simulation result of the ac waveforms. Although the dc bus voltages are
well balanced, the rectifier draws pulsed current from the utility and introduces a lot
harmonics just like the diode bridge rectifier.

In order to lower the harmonic components in the input current. SPWM control

is introduced. The SPWM gate signal for the switching device SP3 is the same as SP3

113

(V)

(A)

(A)

(V): t(s)

 

 

 

 

 

 

 

 

 

 

Output Voltage
300.0 - ____.....______.
0.0 - -
-300.0 -
-000.0 (A): 1(8)
40.0 Output Cmem
20.0 -
0.0 ~
-20.0 -
3': (A): t(s)
' Input Cutout
10.0 - > ------- - - - - - - .......
0.0 . . l

40.0..-- --- --- --- -- -
403-; ————__

0.0 0.92 0.94 0.5 0.90
t(s)

 

 

Figure 4.11. Simulated ac waveforms for the proposed rectifier.

 

2.5 . w T

1.5

0.5 I-

-O.5

-1.5 -

 

-2 - .
(a)

 

—2.5

 

ON~ k 5..., ,._,

 

 

Li 3} (b)

O F F ...—-..;— :_L ...—s. -__l_._ l I 1 1

o pI/3 2pi/3 pi 4pi/3 5pi/3 2pI

 

Figure 4.12. Gate drive signal for the switch SP3.

114

 

 

 

 

 

 

 

 

 

 

 

 

\I
II

 

 

 

AAE_#AAA AAA 1 AAA
VVV'4'vvv———vvv———vv

\I
II

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4.13. PI control for the SPWM voltage balancing.

in the fully active rectifier, as shown in Figure 4.12. Since the other switching devices
are replaced by diodes. The charge balancing may not valid any more, therefore, a
feedback control has been implemented to balance the inner junction voltage. The
error of the junction voltage is fed into a PI controller, and the PI controller changes
the offset of the sinusoidal reference to adjust the average current flowing into the
junction V4, as shown in Figure 4.13. The comparison of three front-end topologies
has been conducted and shown in Table 4.4. Similar control can be implemented to
balance voltage junction V2. Although the simplified five-level converter has higher
input harmonics, it significantly reduced the number of switching devices and diodes
used in the rectifier. Therefore the proposed five-level rectifier could be a cost-
effective alternate for the applications that does not have strict input harmonics

requirement and does not require regenerate capability.

4.4 Summary

In this chapter, several simplified topologies with reduced number of devices was

proposed to reduce the system complexities and costs.

115

Table 4.4. Detailed comparison of three different front-end topologies

 

 

 

 

 

 

 

 

 

 

 

 

Diode Fully
Bridge Active Proposed
Rectifier Rectifier Rectifier
Number of active devices 0 24 6
Total voltage ratings of active devices 0 6Vdc 151/dc
Number of diodes 6 18 12
Total voltage ratings of diode 6Vdc 9V6,C 6V0,C
Voltage balancing ability N 0 Yes Yes
Input Current Harmonics Very high Low Medium
Regenerative Capability No Yes No

 

 

Based on the analysis of the current path for each voltage junction, the topology
with reduced number of clamping diodes was proposed. The proposed topology added
a small numbers of switching devices to provide a current path to voltage junctions
so that a large number of clamping diodes can be removed. In the five—level topology,
the ratios of the reduced diodes rating and increased switching devices rating is 4:1.
It will be higher in the topology with higher number of levels. The control strategy
of the proposed topology was also included. The proposed topology with reduced
number of clamping diodes has the same performance as the traditional one.

In the rectifier side, the number of switching devices can also be reduced. One
way is to replace the top-most and bottom—most switching devices by diodes. A
novel simplified topology was also proposed in this chapter which only requires two
switching devices per phase leg, and each switching device only needs to block the
voltage of one dc capacitor. Furthermore, the proposed topology does not require
additional clamping diodes. The total ratings of the diodes required are the same
as those in the uncontrolled diode rectifier. The control strategy was also discussed.
The control performances of three different front-end topologies are compared in

detail. Although the new topology introduces some harmonic components in the

116

input current and does not have regenerative capability, it could be used as a cost-

effective alternate for some applications.

117

CHAPTER 5

Experimental Validation

5. 1 Introduction

In order to validate the simulation results obtained in the previous chapters, a five—
level, three-phase back-to—back 10-kW converter prototype was fabricated and ex-
perimentally tested. The prototype is based on the topology with reduced number
of devices proposed in Chapter 4.2. It has been used as an adjustable speed drive
to experimentally demonstrate the voltage balancing control developed previously in
Chapter 3.2.1. Next, the simplified five-level rectifier and its corresponding control
strategy are also verified.

In this chapter, a detailed description of the hardware will be given, followed
by the implementation of the DSP control system. Experimental results for all the

control strategies discussed in previous chapters are shown.

5.2 Hardware Implementation

Figure 5.1 illustrates the system layout. of the prototype converter. Since the con-
verter has six phase legs and each of them has eight switching devices. there are 48

switching devices in total. 48 optical fibers transmit the gate drive signals from the

 

   

  

    

    

Voltage Voltage

 
 

Gate Drive
Gate Drive

  
 
  
 

  
 

Speed
Command

 
   

DSP Board

  

Figure 5.1. System layout of the prototype.

DSP board to these 48 switching devices. Meanwhile, fault signal of each phase leg
is fed into the DSP board. In case of any errors, all the gate drive signals will be
blocked out for protection. The usage of the optical fibers not only increases the
isolation strength of the system, but also has high resistance to the electromagnetic
noise, resulting higher reliability, especially in the high-voltage, high-power system.
An external potentiometer is connected to the DSP board and serves as the speed
command input.

There are four dc voltage sensors to sense voltage across each capacitor. Two ac
voltage sensors are used to detect the phase angles of ac line voltage. Two current
sensors are used to get the input current in order to calculate input power factor.

A 460 V, 5 HP induction motor is used as the load. Since we do not have the
facility to load the induction motor, some resistors are added to draw required real
power from the converter.

The main circuit is based on the five-level back-to—back system with reduced

119

 

Figure 5.2. Compact intelligent power module.

clamping diodes. The main parameters are given by

Input Voltage 480 V
Input Frequency 60 Hz
Output Voltage 0 ~ 480 V
Output Frequency 0 ~ 60 Hz
Output Current 12 A

DC Bus Voltage 660 V

The active switching device chosen is PS21353-G from PowerEx. It is a 600 V
/ 10 A, six-pack intelligent power module (IPM), which integrates power devices,
drivers, and protection circuitry in an ultra compact dual—in-line package, as shown
in Figure 5.2. The three outputs of the six—pack IPM are connected together to
make the IPM a 600 V / 30 A dual module. The usage of the compact IPM can
significantly reduce the size and complexity of system. The clamping diodes used

were IR HFA25TB60, which are rated for 600 V, 25 A in a. TO-220 package. Each do

120

 

Figure 5.3. Picture of the prototype.

capacitor consists of six 200V, 1500 IIF electrolytic capacitors in parallel so it can be
distributed to six identical phase legs. The effective capacitance of each dc voltage
level of converter is 9 mF.

The system consists of six identical phase leg submodules, as shown in Figure 5.3.
Each phase leg submodule is implemented by a PCB, which is constructed of four
layer and has a maximum continuous capacity of 20 A for the power circuitry. The
IPM, diode and capacitor are soldered on the PCB board, whose layout is shown in
Figure 5.4.

The left side of the phase leg board is the control circuitry. There are eight optical
receivers to receive the gate drive signals to control each power device. If any device
has any fault, which include over-current and under—voltage. the fault signal will be

sent back to the DSP board via a optical fiber. Each module also has its own status

121

 

 

 

 

 

 

 

 

 

 

Optical Fiber Interface Supply Electrical Interface
l._l
Fault Signal<——-—~— I ...........
Status LED(Grecn,o 3 Driver E V5
Fault LED(Red o g and IPM
Fault Reset O Fault Capacitor
E ; Ouput
PWM —l—E 2
Gate
. D'
Drive rode I: V,
Signal [I
Capacitor
IPM
E V:
EACPhaseVoltage
1 Driver : Terminal
3 and
: : IPM
O Fault I Capacitor
, | ; Ouput
:l' ----------- ' D I: V.
Diode
o Driver '
: Ca acitor
° : and IPM p
Q ; Fault
:1 Ouput l: V]
7 | '. ..........

 

 

 

 

 

Figure 5.4. Layout of the phase leg board.

and fault LED indication.

The right side is the power circuitry, where four capacitors are connected in
series as dc bus. The IPMs and diodes are connected to the dc bus. There are five
dc voltage level terminals V5, V4, V3, V2 and V,. which can be used to interconnected

with other phase legs. The ac phase voltage terminal is connected to the utility via

input inductance for the rectifier side or to the load for the inverter side.

122

 

 

Figure 5.5. DSP board based on Analog Devices ADSP-21065L.

5.3 DSP Control System

The voltage balancing control is implemented by a DSP board based on ADSP-
21065L by Analog Devices, as shown in Figure 5.5. The ADSP—21065L is a general
purpose, programmable 32-bit DSP that allows users to program with equal efficiency
in both fixed-point or floating-point arithmetic.

Since there are 48 switching devices in the system, it is diflicult and also unnec—
essary to have all of them direct controlled by the DSP. Although each phase leg has
eight switching devices, which have a total 28 : 256 combinations of. switch states,

there are only five valid switching states, as shown in Table 4.1. A programmable

123

 

 

 

 

 

 

 

 

 

 

 

 

. SQ— g
I Reactive V R MR _L
4» Current PI l/me r _. ,\
Calculation

 

 

 

 

 

 

 

 

Switching
Pattern
Table

Phase
Detector

   

 

.5:
§%
§%

1 i

ii

)l

fir

\I
ll

 

 

  

 

 

ll

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5.6. Control Diagram of the fundamental frequency switching control.

logic device (PLD) is used as a decoder between DSP and optical interfaces. The
DSP sends the switching states to the PLD, the PLD decodes it to the actual gate
drive signals and sends them out. the PLD also generates the dead time between the
switching states.

Figure 5.6 shows the control diagram of the DSP program. A software phase
locked loop is implemented in the DSP program to get the phase angle of the input
voltage. The phase angle of the rectifier gate drive signals is determined by the
input voltage phase angle and the calculated phase difference required for dc voltage
stabilization. The phase difference between the input voltage and input current is
also calculated and used to control the rectifier modulation index M R to realize unity
power factor control. The reactive current reference I go can also be adjusted to get.
a leading or lagging power factor.

The optimal angles shown in Table 3.1 are based on some idealized assumptions.
Unfortunately, it may not be guaranteed in the actual system due to the distribution
of the devices parameters. control errors and tolerances, which leads to that the

voltage error no longer can be neglected. Therefore a. closed-loop feedback control is

124

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ll
V5 r \
V4 ' \ 71: 2E
V3 w >
V 6, 0 72' — 02 \
2 7t — 6,
VI 03 \ 372' - 03
()4 37: - 6!,

 

 

Figure 5.7. Error compensation of the switching angles.

muoduc; Ed to improve the performance of voltage balance strategy.

Figure 5.7 shows the voltage waveform of the rectifier. Taking V4 as an example,
if V4 has a positive error, then the net charge flowing into junction V4 needs to be
reduced - We can either increase 631 or decrease 632 to reduce the charge flowing into
junctigh V4. Also we can decrease 611 or increase 612 in the inverter side to increase
the Ch arge flowing out of junction V4. Obviously, the corrective component will be

much Smaller if we change all of these four angles simultaneously, i.e.

6,,“ = 631+A6v4 (5.1)
(9’,22 = rim—A9” (5.2)
a}, = 9,1—A6v4 (5.3)
a}, = 612+A6V4, (5.4)

thre A0“ is the corrective component output from the PI controller.

Similarly, we can modify the switching angles to compensate the voltage error of

,
:3 ..-
Q111d V2, as shown below

0R1 = 631 — Aer/3 + Aer/'4 (5.5)

6's = 9R2—A9v'4 (5.6)

125

 

 

   
     

Initial Switching
Angles
(Lookup-Table)

 

E i gure 5.8. Block diagram of voltage error compensation feedback control.

03a
03.4
6'11
0'12
0'13

I
014

7r + 9m + Aflvg — A0V3
7r + 0m — Agvz

611 + A6V3 — A0”

912 + ABM

7r + 0“ — A0v2 + A0“

71' + 012 ‘l‘ Agvg.

(5.7)
(5.8)
(5.9)

(5.10)

(5.11)

(5.12)

The detailed block diagram of the voltage error compensation feedback control

is
gllown in Figure 5.8.

126

Bee-arise of the selective harmonics elimination PWM and low modulation index
OPtImization are also based on pre-calculated switching angles table, they can be

implemented by similar program.

5.4 Experimental Results

5.4.1 Voltage Balancing Control with Fundamental FI'e-

quency Switching

Figure :5 - 9 illustrates the the voltage waveform of each voltage level when the inverter
mod‘fla-t. ion index M 1 is 0.9. The vertical axis ranges from O V to 800 V. It can be
seen th at the voltage of dc-bus is stabilized at 660 V and all voltage level are well
balanced.

Figure 5.10 shows the detailed ac waveforms. The output frequency is 60 Hz.
Thereih, Ch1 is the input current, Ch2 is the motor current, which is much smaller
than t 1‘18 input current because R—L load current is excluded, and Ch3 and Ch4 are
the St aircase line-to-line voltage waveforms of rectifier and inverter, respectively. The
scale of the voltage is 200 V/ div, and the scale of the current is 5 A/ div.

1bl‘om Figure 5.10, it can be seen that the input current is almost sinusoidal.

A 1EDPT is applied to obtain the spectrum of the input current. The THD of input
cuernt is calculated to be 6.1%. Similarly, the THD of other waveforms are obtained

and Shown in Table 5.1.

1“\igure 5.11 shows the phase difference of the input phase voltage and input phase
Current. It shows that the reactive current is reduced. The input voltage and input

(:le 1‘ent are almost in phase, resulting a power factor of 0.95. The power factor can

bQ
flirthcr increased by using a better PI controller.

Figures 5.12 to 5.14 are detailed waveforms when A]; is 0.8, and the output

127

Figure

MR=()

F

 

 

 

—'—‘*‘

 

 

 

 

j 100 V/diV

 

5.9. DC bus voltage waveforms of fundamental

- 9 and MI=O.9, time: 4 ms/div.

 

 

 

 

 

 

 

 

128

II“-

frequency switching for

. .. Input

Current

”37 (5 A/div)

'- ,. 1:1: Motor
Current
.. . (5 A/div)

"1‘: Rectifier
. Voltage
"'71 (200V/div)

...."::11 Output
'3” ’ Voltage
1 (200 V/div)

1%1111; 5.10. AC waveforms of fundamental frequency switching for AIR=O.9 and
I =09, time: 5 Ins/div.

Table 5.1. THD of the waveforms at rated output power.

 

THD
Input Current 6.1%
Motor Current 5.0%

Rectifier Current 10.4%

Output Current 9.5%

 

 

 

Phase
91%; A .-
// \xt
// 1;
I .......................
\ If/f ;\\
// \l
’q/ \

   

 

 

 

 

Figure 5.11. Input power factor for M 320.9 and 111,209.

129

 

 

 

 

 

 

,f ' ‘6'
r
x. .
.
:5-
? * r - r “ r 5
kénmww.5 A ‘Wwwxww V
- -. 4
:2; . H
._ 3 .
Pau: .. ...... ....L... .-.
. .E
r . - r vvvvvvvvvvvvv _ .__.__ _ - V
3
. . _ V
2
1, 100 V/le
i
_-1_—
2

 

 

Figure 5.12. DC bus voltage waveforms of fundamental frequency switching for

MR:O - 9 and MI=O.8, time: 4 ms/div.

frequ§ncy is 54 Hz.
F i.gures 5.15 to 5.17 are detailed waveforms when M} is 0.5, and the output

f1‘eqtlelicy is 33 Hz.

130

 

 

 

 

 

 

 

 

 

Rectifier

- +2333}; Voltage
(200V/div)
1:::. Output

,. - Voltage

Figure 5.13. AC waveforms of fundamental frequency switching for MR=0.9 and

M1=0 - 8, time: 5 ms/div.

 

Phase
voltage

 

 

 

 

Figure 5.14. Input power factor for MR=0.9 and MI=O.8.

131

 

 

 

 

l . .

f’ &>

> K

g- ‘Q‘M‘Lm 1 --:~» ........... o F .
y L . ..__' v A 1 i L i ‘____.___-_‘ L
j w ‘ r -' w W v A A

- t
1 A A .........

100 V/div

 

 

 

=1.-

Figurg 5.15. DC bus voltage waveforms of fundamental frequency switching for
MR=O .9 and M,=0.5, time: 10 ms/div.

 

 

.. Input
' Current
(5 A/div)

' Motor

 

Current

‘ (5 A/div)

Rectifier

 

 

 

 

.
.
-. ......
*V‘f" ‘. .. ""'".". 5’1... ...... ‘ft ............
. k. '1 x.
..... . ... .. .. A .. ,.
-- . L.’\ .\J‘ C (.49..
. , . . l
,, ..”.. ...! ...... .‘_ ’ ..I..,.
...v t... FT") ' “.... ..AH ...“ ,___'
_. .................................... ..
a.-- -

 

' Voltage
‘ (200 V/div)

' Output
j Voltage
. _ (200 V/div)

l glue 5.16. AC waveforms of fundamental frequency switching for M3200 and

12:09, time: 10 Ins/div.

132

 

voltage

   
  

 

i
it .

 

 

 

Figure 5.17. Input power factor for M 320.9 and NII=O.5.

54- 2 Selective Harmonic Elimination PWM Control

FigurQ 5.18 shows experimental waveform of the PWM control when M R and M I are
0'8 a-11d 0.7, respectively. It can be seen that it can create nearly sinusoidal current
wave forms. The experimental of the original voltage balancing control under same
cond itions are also shown in Figure 5.19 as a comparison. The THD of the waveforms

in b ch control methods have been calculated and shown in Table 5.2.

133

zd/K‘K—J/rm‘w

 

;

 

 

II

...» n... ......u ..--..

 

Rectifier
Voltage
(1000 V/div)

Output
Voltage
(1000 V/div)

_ Input

Current
(20 A/div)

Motor
Current
(5 A/div)

Figure 5.18. AC waveform of SHE—PWM for AIR=0.8 and Ml=0.7, time: 4 ms/div.

EC

 

. . . <._.-- . . . . . - , . r a I r r p - u - u I - n e c-(

 

 

 

 

 

Rectifier
Voltage
(1000 V/div)

Output
Voltage
( 1000 V/div)

Input
Current
(20 A/div)

Motor
Current
(5 A/div)

F i gure 5.19. AC waveform of fundamental frequency switching for AIR=O.8 and

1x1120.7

, time: 4 ms/div.

134

Table 5.2. Comparison of THD of fundamental frequency switching and PWl\"I con-
tI‘Ol (AIR 2 0.8. A1] = 0.7)

 

 

 

 

Fundamental
Frequency PWM
Switching
Input Current 6.1% 4.6%
Motor Current 5.0% 2.2%
Rectifier Current 13.0% 11.8%
Output Current 15.1% 12.9%

 

5.4.3 Voltage Shifting Method in Low Modulation Index
Operations

The voltage shifting method in low modulation index operations has been imple—
mented. Figure 5.20 shows the voltage waveforms of each voltage levels during
steady-state operation. It can be seen that the voltage of do bus is stabilized at
330 V and all voltage levels are well balanced.

Figure 5.21 illustrates the detailed waveforms when the modulation index of the
inverter is 0.5 and the output frequency is 35 Hz. Therein, Girl is the input current.
Ch2 is the output current. 0123 and Ch4 are the staircase line-to—line waveform of
rectifier and inverter, respectively. It can be seen that the current waveforms are
almost sinusoidal. Similarly, F FT is performed to obtain the spectrum of the input
current. The THD of the input current is calculated to be 9.9%. Similarly, the THD
of output current is calculated as 5.6%.

Fig 5.22 shows the waveform for the original voltage balancing control under same
Conditions for a comparison. Although each voltage level is still well balanced, the
Output voltage and current have much higher harmonic content clue. to the charge
balancing constraint.

Similarly, we can get the experimental waveforms of both control methods when

135

 

............................................................................................

 

...tu-..........4.L.A-.. ......................................................................

.............................................................................................

................................................................................................

..............................................................................................

............................................................................................

«if

50 V/div

 

 

 

Figure 5.20. DC bus voltage waveform of voltage shifting method.(time: 10 ms/ div)

M 1 is 0.3 and the output frequency is 22.5 Hz, as shown in Figures 5.23 and 5.24.
The proposed control method can get nearly sinusoidal waveform even with low mod—
ulation index. Compared with the original control method, it significantly reduces

the harmonic components. Figure 5.25 illustrates the experimental waveforms for

A11 = 0.1.

136

 

Rectifier
' .5: Voltage
(100 V/div)

Output
r.‘ I Voltage
‘ '. H; (100 V/div)

. . Input
..I.i.; (SA/div)
Motor
Current
.. ..ifi (SA/div)

 

 

 

 

 

 

 

 

Figure 5.21. AC waveform of voltage shifting method for AIR = 0.9 and M,=0.5,
time: 10 ms/div.

 

‘i'iiiW‘fiiiii{5171;322:3771::;;;:::;ié‘."."* {if}“Fifiifféfl Ram“
’77 (100 V/div)
K411“: Output
Voltage
(100 V/div)

 

 

"L”."L Input

. 3 (5 A/div)
1';,:::': Motor
(5 A/div)

 

 

 

 

 

Figure 5.22. AC waveform of fundamental frernu—mcy switching for M R = 0.9 and
011:0.5, time: 10 ms/div.

 

.1- 1:. "11,11 11' ,1 1.11 1'". 1 F1 Rectifier
. _1‘ 11:13) 1,.1f1'1l1fl'j/111 l; 1 1: ‘1 1‘ .1 .15. f1 1’ it Voltage
1" if. tjlu’1flrx l!) h" 33;? , (100 V/diV)
‘ ' ' ‘ Output

1 Voltage

‘_- (100 V/div)
_ Input
Current

 

 

 

 

 

 

 

I» :15} (5 A/div)

 

Figure 5.23. AC waveform of voltage shifting method for MR = 0.9 and MI=O.3,
time: 20 ms/div.

 

1 . ..‘1; Rectifier
, 5'3 Voltage
’ i (100 V/div)
1 '91: Output
_ 1. _ " Voltage
iii-'1; (100 V/div)

 

 

 

   

(5 A/div)

 

 

 

3,1» 11111}, 11 :11: Motor
‘1 it“ w Alt/”Vt 0mm
I ' El 16: 1: ‘ 1: '1: (5 A/le)

r t V1

 

 

Figure 5.24. AC waveform of fundamental frequency switching for [VI]; = 0.9 and
MI=0.3, time: 20 nrs/div.

138

 

" "11".(Lii‘
1 1.1 t 1‘1 t 1.1 ’1 1 1 Recufier
r.-'lv1'l..i.vV. : 2‘ VI 1 ,‘ \- it" a 1.111.“
:f'ittui 1322.”:1 :1..ir 5'?‘llt‘*.':'l.!i ft 43.“. t ‘2 “ r: " *:¢ :1‘
1 «1,1111 1 Voltage
.1. 1.111.1.11";.1.1.1‘:111:;.,11.1.1.11.11.11 1111111111111111.1',,t .
" 3' '1' :11 31" {W 7" i -l’ ‘l l‘ ;" 13?. ‘1 .‘ ( )
r f‘ail t “11:45! If? .t. {1.21 -! : .L' If ’1." 1. 100 V/le

 

. .'_‘.’ . .
111.1

. Output
‘ Voltage
1 (100 V/div)

I ' Input
Current
(5 A/div)

“-'.:i.‘i’.: Motor
_ '3‘ Current
. 'j} (SA/diV)

 

 

 

 

 

 

 

Figure 5.25. AC waveform of voltage shifting method for M R = 0.9 and M 1:01,
time: 50 ms/div.

5.4.4 Carrier-based SPWM Control

The carrier-based SPWM control has also been implemented. Instead of store pre-
calculated switching angles in the previous control, the pulse widths of the offset
voltage for different modulation indices shown in Figure 3.37 are stored. For given
M R and M1, offset voltages have been generated based on the required pulse width
and added to the sinusoidal reference voltages. The output voltage and duty cycle
in each phase are calculated and sent to the PLD. The PLD decodes signals from
the DSP to the gate signals that drive corresponding switching devices. With the
higher switching frequency and lower harmonic current, the control errors of the dc
bus voltage are negligible. Therefore the closed-loop voltage control is not necessary.

Experiments have been conducted for ten different modulation indices. The dc
bus voltages are all well balanced in the experiment. The lower harmonics in the

currents are also effectively eliminated. The spectra of the input currents and output,

139

Table 5.3. Current THD of carrier—based SPWM control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Input Harmonic Output Harmonic
Freq. MI Current THD Current Current THD Current
60 0.750 14.38 4.7% 0.75 15.93 1.1% 0.17
54 0.675 11.67 4.9% 0.63 14.67 1.8% 0.27
48 0.600 9.05 8.1% 0.81 13.64 2.1% 0.29
42 0.525 7.29 9.5% 0.77 12.66 2.4% 0.31
36 0.450 5.50 9.7% 0.59 11.72 3.1% 0.36
30 0.375 3.73 15.6% 0.65 10.69 3.0% 0.32
24 0.300 2.69 19.4% 0.58 10.04 2.5% 0.25
18 0.225 1.80 25.9% 0.52 9.39 2.6% 0.25
12 0.150 - - - 9.08 2.9% 0.26
6 0.075 - - - 9.36 4.1% 0.38

 

currents are also calculated. The THDs of the current are calculated and shown in
Table 5.3. The THD of the output current is less than 5% in the whole operation
range. The THD of the input current for full load and 60 Hz output frequency is 4.7%,
which is also less than 5%. Although the input current THD becomes higher in lower
modulation index operation, it is mainly because of the lower fundamental current,
while the value of the input harmonic current keeps about same. Figures 5.26 and
5.27 show the dynamic operation of the whole system, where the motor is accelerated
from zero to full speed, 1800 rpm, in 4 seconds. The dc bus voltage are shown in
Figure 5.26. It can be seen that the dc bus voltages are still well stabilized and
balanced. Figure 5.26 shows the ac waveform and motor speed. The detailed ac

waveform for five different modulation indices are shown in Figures 5.28 to 5.32.

140

 

Figure 5.26. Transit performance of DC voltage waveforms of the SPWM control,
Chl ~ Ch4: V2 ~ V4(50 V/div) time:500 ms/div.

 

 

 

 

Figure 5.27. Transit performance of AC waveforms of the SPWM control, Chl: M0-
tor Speed(300 rpm/div), Ch2: Output Voltage(100 V/div). (713: Input Current(10
A/div). ('h4: Output Current(10 A/div) time:500 ms/div.

141

 

 

Figure 5.28. AC waveform of SPWM control for M3 = 0.75 and M1 = 0.75,
ChlzRectifier Voltage(100 V/ div), Ch221nverter Voltage(100 V / div), Ch3zlnput Cur—
rent(10 A/div), Ch4:Output Current(10 A/div), time:5 ms/div.

 

 

Figure 5.29. AC waveform of SPWM control for MR = 0.75 and M, = 0.6,
ChlzRectifier Voltage(100 V/div), Ch221nverter Voltage(100 V/div). ('h321nput Cur-
rent(10 A/div), Ch420utput Current(10 A/div), time:5 ms/div.

142

 

 

Figure 5.30. AC waveform of SPWM control for MR = 0.75 and M1 = 0.45,
Ch12Rectifier Voltage(100 V / div), Ch2:Inverter Voltage(100 V / div), Ch3:Input Cur-
rent(5 A/div), Ch420utput Current(10 A/div), time:5 ms/div.

 

 

 

 

Figure 5.31. AC waveform of SPWM control for MR = 0.75 and M, = 0.3,
ChlzRectifier Voltage(100 V/div), Ch2zlnverter Voltage(100 V/div), Ch3zlnput Cur-
rent(5 A/div). (,r'h420utput Current(10 A/div), time:5 ms/div.

143

 

Figure 5.32. AC waveform of SPWM control for MR = 0.75 and M1 = 0.15,
ChlzRectifier Voltage(100 V/div), Ch2zlnverter Voltage( 100 V/ div), Ch3zInput Cur-
rent(2 A/div), Ch4:0utput Current(10 A/div), time:10 ms/div.

5.4.5 Simplified Five-level Rectifier

In the phase leg schematic shown in Figure 5.33(a), each switching device has a built—
in anti-parallel diode. Therefore, we can change the fully active rectifier front-end to
proposed simplified five-level rectifier by disabling the gate signals for all switching
devices but SP3 and Sns. Without gate drive signals, the switching devices are always
turned off and act as a diode. Also, the clamping diodes, ng and Bug, will not be
turned on. Therefore, the rectifier is equivalent to the schematic in Figure 533(1)),
which is exactly the same as the proposed rectifier.

The fundamental frequency switching and SPWM have been implemented to
control the proposed rectifier. Figure 5.34 shows the dc waveforms of the proposed
five-level rectifier with fundamental frequency switching. It can be seen that the dc

bus voltages are still well balanced. The at- waveforms are shown in Figure 5.35.

144

 

 

 

 

 

 

 

(a) (b)

Figure 5.33. Simplified five-level rectifier simulated from fully active recitfier.

The output voltage is nine-level staircase waveform, and the output current is nearly
sinusoidal. However, the input current has narrow pulses which introduce a lot of
harmonics. Figure 5.36 shows the ac waveforms for SPWM control. The input

harmonics are significantly reduced.

5.5 Summary

A five-level back-to—back 10 kW converter prototype was fabricated and experimen-
tally tested. The converter was used as a three-phase adjustable speed drive for an
induction motor to validate the proposed topology with reduced number of clamping
diodes and demonstrate the voltage balancing controls developed in Chapter 3.
The experiments successful demonstrated that the dc bus voltages can be well

balanced by proposed voltage balancing controls. Even with the fumlamental fre-

 

 

 

 

 

.
it u. 1' \
_L -- .... ... 1-..- .... -... .. . -_ m_..___..
...................................................................................................
.
.
..................................................................................................
L a . ..
n uuv-u—v u —— 1 ‘1 W In. 1 ww—
.
...................................................................................................
.
u L 1“ I n- - M l
w _..... .. ...—.... ._ ....r ...—.... .. ..
. ""-
...................................................................................................
...................................................................................................
_‘ AA - _ “A; M ..-: h - mu“- A‘M—M‘ nan—n-.- m m.‘ A A.‘
...................................................................................................
-
1‘
I ...................................................................................................
.3»

 

 

 

Figure 5.34. DC waveforms of the proposed five-level rectifier with fundamental
frequency control. Chl ~ Ch4: V5 ~ V2(50 V/ div) time:5 ms/div.

 

f 3 \7 141‘. :n} 151k .fi 3 5 I
. p . . ° :

 

 

 

 

 

 

Figure 5.35. AC waveforms of the proposed five-level rectifier with fundamental
frequency control, Chl: Output Voltage(100 V / div), Ch2: Output Current(5 A / div),
Ch3: Input Current(20 A/ div), time:5 ms/ div.

146

 

 

 

 

 

 

 

Figure 5.36. AC waveforms of the proposed five-level rectifier with SPWM control,
Chl: Output Voltage(100 V/div), Ch2: Output Current(10 A/div), Ch3: Input
Current(10 A/div), time:5 ms/div.

quency switching, the input and output currents have a relatively low harmonic
components. As the improvement for the fundamental frequency switching, the volt-
age shifting method and selective harmonic elimination SPWM demonstrated their
capability of reducing harmonic current. The carried-based SPWM control was also
implemented. The experimental results showed that the SPWM can achieve lower
harmonic in input and output current in all modulation index range.

The prototype was also been used to simulate the proposed simple five-level
rectifier topology by removing unused gate drive signal. The test results showed that

the simplified rectifier has the capability to balance the dc bus voltage.

147

CHAPTER 6

Conclusions and Recommendations

6. 1 Contributions

This work has the following contributions so far:

a The charge/dicharge mechanism has been analyzed in detail. The voltage
balancing equations have been derived, based on which, the optimal switching
angles with lowest THD for the fundamental frequency switching control have

been calculated;

0 A selective harmonic elimination PWM voltage balancing control has been
proposed, which has further reduced the voltage THD when the modulation

index is high;

0 A novel triplen harmonic injection method has been proposed, which utilizes
the line-to-line voltage redundancy to reduce the voltage THD when the mod-

ulation index is low;

0 The triplen harmonic injection method has been extended to the. carried—based
SPWM. The effect of the offset voltage on the charge balancing was analyzed.

Based on that, a carried—based SPWM with voltage balancing capability was

148

proposed, which can effectively eliminate the lower harmonics while keep dc

bus voltage balanced.

o A novel five-level converter topology with reduced number of clamping diodes
has been proposed. The topology has been extended to converter with higher

number of levels.

0 A novel simplified five-level converter has been proposed. The proposed topol-
ogy can significantly reduce the system complexity and cost. The control
strategy for the proposed topology is also included. Although it has higher
harmonics in the input current, its simplicity and low-cost make it a possible

cost-effective alternate for the fully active rectifier.

o A 10 kW prototype with reduced number of clamping diodes has been built.
A DSP—based control system has been implemented based on proposed control

strategy. Experiments have been conducted to validate the previous analysis.

6.2 Recommendations for Future Work

In the carrier-based SPWM control with voltage balancing control, the voltage ref-
erence has been shifted to and stays level V1 or V2 for a certain period. During such
period, there is no need to for the switching devices to switch. Therefore, the offset
voltage added in the voltage balancing control actually reduces the switching losses.
Further work could be conducted to find out how much is the reduction and how to
further reduce the switching losses.

C(gnnmon—mode voltage has drawn more and more attentions recently. Shaft and
bearing currents caused by common-mode voltages of PWM inverters have been
identified as the reason of some Inc-mature bearing failures. However, the offset

voltage added to all three phase voltage is also a common-mode voltage. Further

149

investigation could be conducted to identify the effect of the offset voltage on the
common-mode voltage. If it increase the common-mode voltage, different control
strategy could be developed to reduce the common-mode voltage.

The SPWM control for the proposed five-level rectifier still introduces some har-
monics in the input current. Space vector modulation could be developed to further
reduce the harmonics.

The multilevel topology has more freedom compared with the traditional two-
level topology. The freedom can be utilized to implement the fault-tolerate operation,
which is another advantage of the multilevel converter. Most of the fault tolerate
operations proposed so far are based on capacitor-clamped or cascaded topology.
Further investigation could be done based on the diode-clamped topology to improve

the system availability.

 

Reference

[1] B. K. Bose, ed., Power Electronics and Varible Frequency Drives — Technology
and Application. Piscataway, NJ: IEEE Press, 1997.

[2] B. K. Bose, ed., Modern Power Electronics and AC Drives. Upper Saddle River,
NJ: Prentice Hall PT R, 2002.

[3] S. Bernet, “Recent developments of high power converters industry and traction
applications,” IEEE Transaction on Power Electronics, vol. 15, pp. 1102 - 1117,
Dec. 2000.

[4] B. K. Bose, “Power electronics in motion control —— technology status and recent
trends,” IEEE Transaction on Industry Applications, vol. 29, pp. 902 — 909, Sep.
1993.

[5] J. D. V. Wyk, “Power electronic converters for motion control,” Preceeding of
IEEE, vol. 82, pp. 1164 — 1193, Aug. 1994.

[6] T. M. Jahns and V. Blasko, “Recent advances in power electronics technology
for industrial and traction machine drives,” Preceeding of IEEE, vol. 89, pp. 963
— 975, Jun. 2001.

[7] H. Stemmler, “High power industrial drives,” Preceeding of IEEE, vol. 82,
pp. 1266 - 1286, Aug. 1994.

[8] P. Bhagwat and V. Stefanovic, “Generalized structure of a multilevel PM in-
verter,” IEEE Transaction. on Industry Applications, vol. IA-19, pp. 1057 — 1069.
Nov. 1983.

[9] A. Nabae, I. Takahashi. and H. Akagi, “A new neutral—point-clamped PWM
inverter,” IEEE Transaction on Industry Applications, vol. IA-l7, pp. 518 --
523,Sep.1981.

151

 

[10]

[11]

[12]

[13]

[14]

[15]

[16]

[17]

[18]

[19]

N. S. Choi, J. G. Cho, and G. H. Cho, “A generalcircuit topology of multilevel
inverter,” in Proceeding of the 22nd Power Electronics Specialists Conference,
vol. 1, pp. 96 - 103, Jun. 1991.

J. S. Lai and F. Z. Peng, “Multilevel converters - a new breed of power convert-
ers,” IEEE Transaction on Industry Applications, vol. 32, pp. 509 — 517, May
1996.

R. W. Menzies, P. Steimer, and J. K. Steinke, “Five level GTO inverters for large
induction motor drives,” IEEE Transaction on Industry Applications, vol. 30,
pp. 938 — 944, Jul. 1994.

G. Sinha and T. Lipo, “A four-level inverter based drive with a passive front
end,” IEEE Transaction on Power Electronics, vol. 15, pp. 285 - 294, Mar. 2000.

R. Sommer, A. Mertens, M. Griggs, H. J. Conraths, M. Bruckmann, and
T. Greif, “New medium voltage drive systems using three-level neutral point
clamped inverter with high voltage IGBT,” in Proceeding of the 14th Applied
Power Electronics Conference and Exposition, vol. 3, pp. 1513 — 1519, Oct. 1999.

N. S. Choi, Y. C. Jung, H. L. Liu, and G. H. Cho, “A high voltage large
capacity dynamic VAR compensator using multilevel voltage source inverter,” in
Proceeding of the 23rd Power Electronics Specialists Conference, vol. 1, pp. 538
— 545, Oct. 1992.

N. S. Choi, G. C. Cho, and G. H. Cho, “Modelling and analysis of a static VAR
compensator using multilevel voltage source inverter,” in Conference Record of
the 28th IEEE IAS Annual Meeting, vol. 2, pp. 901 - 908, Oct. 1993.

C. Hochgraf and R. Lasseter,‘ “A transformer-less static synchronous compen-
sator employing a multi-level inverter,” IEEE Transaction on Power Delivery,
vol. 12, pp. 881 — 887, Apr. 1997.

J. Rodriguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of
topologies, controls and applications,” IEEE Transaction on Industry Electron-
ics, vol. 49, pp. 724 — 738, Aug. 2002.

T. A. Meynard, H. Foch, P. Thomas. J. Courault, R. Jakob, and M. N ahrstaedt,
“Multicell converters: Basic concepts and industry applications,” IEEE Trans-
action on Industry Electronics, vol. 49, pp. 995 - 964, Oct. 2002.

152

 

[20]

[21]

[22]

[23]

[24]

[25]

[26]

[271

[281

[291

[301

T. A. Meynard, H. Foch, F. Forest, C. Turpin, F. Richardeau, L. Delmas,
G. Gateau, and E. Lefeuvre, “Multicell converters: Derived topologies,” IEEE
Transaction on Industry Electronics, vol. 49, pp. 978 - 987, Oct. 2002.

L. Tolbert, F. Z. Peng, and T. G. Habetler, “Multilevel converters for large
electric drives,” IEEE Transaction on Industry Applications, vol. 35, pp. 36 —
44,Jan.1999.

R. Teodorescu, F. Blaabjerg, J. K. Pedersen, E. Cengelci, and P. N. Enjeti,
“Multilevel inverter by cascading industrial VSI,” IEEE Transaction on Industry
Electronics, vol. 49, pp. 832 - 838, Aug. 2002.

P. Hammond, “A new approach to enhance power quality for medium voltage
ac drives,” IEEE Transaction on Industry Applications, vol. 33, pp. 202 — 208,
Jan.1997.

L. Tolbert, F. Z. Peng, T. Cunnyngham, and J. Chiasson, “Charge balance
control schemes for cascade multilevel converter in hybrid electric vehicles,”
IEEE Transaction on Industry Electronics, vol. 49, pp. 1058 — 1064, Oct. 2002.

F. Z. Peng, J. McKeever, and D. Adams, “A power line conditioner using cascade
multilevel inverters for distribution systems,” IEEE Transaction on Industry
Applications, vol. 34, pp. 1293 — 1298, Nov. 1998.

G. Joos, X. Huang, and B. T. Ooi, “Direct-coupled multilevel cascaded se—
ries VAR compensators,” IEEE Transaction on Industry Applications, vol. 34,
pp. 1156 — 1163, Sep. 1998.

F. Z. Peng and J. S. Lai, “Dynamic performance and control of a static var
generator using cascade multilevel inverters,” IEEE Transaction on Industry
Applications, vol. 33, pp. 748 - 755, May 1997.

F. Z. Peng, “A generalized multilevel inverter topology with self voltage balanc-
ing,” IEEE Transaction on Industry Applications, vol. 37, pp. 611 — 618, Mar.
2001.

X. Yuan and I. Barbi, “Fundamentals of a new diode clamping multilevel in-
verter,” IEEE Transaction on Power Electronics, vol. 15, pp. 711 — 718, Jul.
2000.

P. Barbosa, P. Steimer, J. Steinke, L. Meysenc, M. Winkelnkemper, and

7

N. Celanovic, “Active neutral—point—clamped multilevel converters,’ in Proceed-

ing of IEEE International Electric Machines and Drives Conference, May 2005.

153

[31]

[321

[33]

[341

[35]

[36]

[37]

[38]

[39]

[40]

W. A. Hill and C. D. Harbourt, “Performance of medium voltage multi-level
inverters,” in Conference Record of the 34th IEEE IAS Annual Meeting, vol. 2,
pp. 1186—1192, Oct. 1999.

A. Joseph, J. Wang, Z. Pan, L. Chen, and F. Peng, “A 24-pulse rectifier cas-
caded multilevel inverter with minimum number of transformer windings,” in
Conference Record of the 40th IEEE IAS Annual Meeting, vol. 1, pp. 115 - 120,
Oct. 2005.

M. D. Manjrekar, P. K. Steimer, and T. A. Lipo, “Hybrid multilevel power
conversion systems: A competitive solution for high-power applications,” IEEE
Transaction on Industry Applications, vol. 36, pp. 834 — 841, May 2000.

C. Rech, H. Pinheiro, H. A. Grilndling, H. L. Hey, and J. R. Pinheiro, “Analysis
and comparison of hybrid multilevel voltage source inverters,” in Proceeding of
the 33rd Power Electronics Specialists Conference, vol. 1, pp. 491 — 496, Jun.
2002.

M. D. Manjrekar and T. A. Lipo, “A hybrid multilevel inverter topology for drive
application,” in Proceeding of the 13th Applied Power Electronics Conference
and Exposition, vol. 1, pp. 523 — 529, Feb. 1998.

B. Diong, S. Basireddy, K. Corzine, and Y. Familiant, “Multilevel inverters with
equal or unequal sources for dual-frequency induction heating,” in Proceeding of
the 19th Applied Power Electronics Conference and Exposition, vol. 2, pp. 825
— 831, Feb. 2004.

M. Veenstra and A. Rufer, “Control of a hybrid asymmetric multi-level inverter
for competitive medium-voltage industrial drives,” in Conference Record of the
38th IEEE IAS Annual Meeting, vol. 1, pp. 190 — 193, Oct. 2003.

K. A. Corzine, M. W. Wielebski, F. Z. Peng, and J. Wang, “Control of cascaded
multilevel converter inverters,” IEEE Transaction on Power Electronics, vol. 19,
pp. 732 — 738, May 2004.

P. Steimer and M. Manjrekar, “Practical medium voltage converter topologies
for high power applications,” in Conference Record of the 36th IEEE IAS Annual
Meeting, vol. 3, pp. 1723 -— 1730, Oct. 2001.

F. Canales, P. Barbosa, and F. Lee, “A zero voltage and zero current switching
three-level DC/ DC converter,” in Proceeding of the 15th Applied Power Elec-
tronics Conference and Exposition, vol. 1. pp. 314 320, Feb. 2000.

154

 

[41]

[42]

[431

[44]

[45]

[46]

[47]

[48]

[49]

[50]

[51]

I. Barbi, R. Gules, R. Redl, and N. O. Sokal, “DC/ DC converter for high input
voltage: four switches with peak voltage of v1" / 2, capacitive turn-off snubber,
and zero-voltage turn-on,” in Proceeding of the 29th Power Electronics Special-
ists Conference, vol. 1, pp. 1 — 7, May 1998.

F. Z. Peng, F. Zhang, and Z. Qian, “A magnetic-less dc—dc converter for
dual-voltage automotive systems,” IEEE Transaction on Industry Applications,
vol. 39, pp. 511 — 518, Mar. 2003.

F. Peng, F. Zhang, and Z. Qian, “A novel compact dc—dc converter for 42 V
systems,” in Proceeding of the 34th Power Electronics Specialists Conference,
vol. 1, pp. 33 — 38, Jun. 2003.

Z. Pan, F. Zhang, and F. Peng, “Power losses and efficiency analysis of mul-
tilevel dc—dc converters,” in Proceeding of the 20th Applied Power Electronics
Conference and Exposition, vol. 3, pp. 1393 - 1398, Mar. 2005.

F. Zhang, F. Peng, and Z. Qian, “Study of the multilevel converters in dc-dc ap-
plications,” in Proceeding of the 35th Power Electronics Specialists Conference,
vol. 2, pp. 1702 - 1706, Jun. 2004.

J. Kolar, U. Drofenik, and F. Zach, “VIENNA rectifier II-a novel single-stage
high-frequency isolated three-phase PWM rectifier system,” IEEE Transaction
on Industry Electronics, vol. 46, pp. 674 — 691, Aug. 1999.

Y. Zhao, Y. Li, and T. Lipo, “Force commutated three level boost type rectifier,”
IEEE Transaction on Industry Applications, vol. 31, pp. 155 - 161, Jan. 1995.

K. A. Corzine and J. R. Baker, “Reduced-parts-count multilevel rectifiers,”
IEEE Transaction on Industry Electronics, vol. 49, pp. 766 — 774, Oct. 2002.

S. Sirisukprasert, J. S. Lai, and T. H. Liu;, “Optimum harmonic reduction with
a wide range of modulation indexes for multilevel converters,” IEEE Transaction
on Industry Electronics, vol. 49, pp. 875 - 881, Aug. 2002.

L. Li, D. Czarkowski, Y. Liu, and P. Pillay, “Multilevel selective harmonic elimi-
nation PWM technique in series-connected voltage inverters,” IEEE Transaction
on Industry Applications, vol. 36, pp. 160 — 170, Jan. 2000.

J. Chiasson and K. Z. D. Tolbert, L.M.and McKenzie, “Control of a multi-
level converter using resultant theory,” IEEE Transactions on Control Systmns
Technology, vol. 11, pp. 345 — 354, May 2003.

155

 

[52]

[53]

[541

[55]

[561

[571

[581

[59]

[60]

[61]

J. Chiasson and K. Z. D. Tolbert, L.M.and McKenzie, “A unified approach
to solving the harmonic elimination equations in multilevel converters,” IEEE
Transaction on Power Electronics, vol. 19, pp. 478 - 490, Mar. 2004.

J. Chiasson, L. Tolbert, and K. Z. D. McKenzie, “Elimination of harmonics in a
multilevel converter using the theory of symmetric polynomials and resultants,”
IEEE Transactions on Control Systems Technology, vol. 13, pp. 216 - 223, Mar.
2005.

Z. Du, L. Tolbert, and J. Chiasson, “Modulation extension control for multilevel
converters using triplen harmonic injection with low switching frequency,” in
Proceeding of the 20th Applied Power Electronics Conference and Exposition,
vol. 1, pp. 419 — 423, Mar. 2005.

Z. Du, L. Tolbert, and J. Chiasson, “Harmonic elimination for multilevel con-
verter with programmed PWM method,” in Conference Record of the 39th IEEE
IAS Annual Meeting, vol. 4, pp. 2210 — 2215, Oct. 2004.

G. Carrara, D. Casini, S. Gardella, and R. Salutari, “A new multilevel PWM
method: A theoretical analysis,” IEEE Transaction on Power Electronics, vol. 7,
pp. 497 — 505, Jul. 1992.

J. K. Steinke, “Switching frequency optimal PWM control of a three-level con-
verter,” IEEE Transaction on Power Electronics, vol. 7, pp. 487 — 496, Jul.
1992.

L. M. Tolbert and T. G. Habetler, “Novel multilevel inverter carrier-based PWM
method,” IEEE Transaction on Industry Applications, vol. 35, pp. 1098 - 1107,
Sep. 1999.

Y. Lee, B. Suh, and D. Hyun, “A novel PWM scheme for a three-level voltage
source inverter with gto thyristors,” IEEE Transaction on Industry Applications,
vol. 32, pp. 260 — 268, Mar. 1996.

V. Agelidis and M. Calais, “Application specific harmonic performance evalu-
ation of multicarrier PWM techniques,” in Proceeding of the 29th Power Elec-
tronics Specialists Conference, vol. 1, pp. 172 ~ 178, May 1998.

Y. H. Lee, R. Y. Kim, and D. S. Hyun, “A novel SVPWM strategy considering
dc-link balancing for a multi-level voltage source inverter,” in Proceeding of the
13th Applied Power Electronics Conference and Exposition, vol. 1, pp. 509 —
514, Mar. 1998.

156

 

[621

[63]

[641

[65]

[661

[67]

[68]

[691

[70]

[711

B. McGrath, D. Holmes, and T. Lipo, “Optimized space vector switching
sequences for multilevel inverters,” IEEE Transaction on Power Electronics,
vol. 18, pp. 1293 — 1301, Nov. 2003.

L. Li, D. Czarkowski, Y. Liu, and P. Pillay, “lV’Iultilevel space vector PWM
technique based on phase-shift harmonic suppression,” in Proceeding of the 15th

Applied Power Electronics Conference and Exposition, vol. 1, pp. 535 ~ 541, Feb.
2000.

J. H. Seo, C. H. Choi, and D. S. Hyun, “A new simplified space-vector PWM
method for three-level inverters,” IEEE Transaction on Power Electronics,
vol. 16, pp. 545 — 550, Jul. 2001.

N. Celanovic and D. Boroyevich, “A fast space-vector modulation algorithm for

multilevel three-phase converters,” IEEE Transaction on Industry Applications,
vol. 37, pp. 637 — 641, Mar. 2001.

J. Rodriguez, L. Moran, P. Correa, and C. Silva, “A vector control technique
for medium-voltage multilevel inverters,” IEEE Transaction on Industry Elec-

tronics, vol. 49, pp. 882 - 888, Aug. 2002.

H. Liu and G.H.Cho, “T hree-level space vector PWM in low index modulation
region avoiding narrow pulse problem,” IEEE Transaction on Power Electronics,
vol. 9, pp. 481 — 486, Sep. 1994.

B. Kaku, I. Miyashita, and S. Sone, “Switching loss minimised space vector
PWM method for IGBT three-level inverter,” IEE Proceedings of Electric Power
Applications, vol. 144, pp. 182 — 190, May 1997.

H. Zhang, A. Von Jouanne, S. Dai, A. Wallace, and F. Wang, “Multilevel in-
verter modulation schemes to eliminate common-mode voltages,” IEEE Trans-
action on Industry Applications, vol. 36, pp. 1645 — 1653, Nov. 2000.

H. J. Kim, H.-D. Lee, and S. K. Sul, “A new PWM strategy for common-mode
voltage reduction in neutral-point-clamped inverter-fed ac motor drives,” IEEE

Transaction on Industry Applications, vol. 37, pp. 1840 '- 1845, Nov. 2001.

L. Tolbert, New Multilevel Carrier-Based Pulse Width Illadulation Techniques
Applied to a Diode-Clamped Converter for Use as a Universal Power Condi-
tioner. PhD thesis, Georgia Institute of Technology. 1998.

157

 

[r21

[73]

[741

[751

[76]

[771

[78]

[79]

[801

[811

J. Rodriguez, J. Pontt, G. Alzamora, N. Becker, 0. Einenkel, and A. W’einstein,
“Novel 20—MW downhill conveyor system using three-level converters,” IEEE
Transaction on Industry Electronics, vol. 49, pp. 1093 — 1100, Oct. 2002.

J. Rodriguez, L. Moran, J. Pontt, J. L. Hernandez, L. Silva, C. Silva, and
P. Lezana, “High-voltage multilevel converter with regeneration capability,”
IEEE Tmnsaction on Industry Electronics, vol. 49, pp. 839 — 846, Aug. 2002.

F. Z. Peng, J. McKeever, and D. Adams, “a multilevel voltage-source inverter
with separte dc sources for static VAR generation,” IEEE Transaction on In-
dustry Applications, vol. 32, pp. 1130 — 1138, Sep. 1996.

X. Kou, K. Corzine, and Y. Familiant, “Full binary combination schema for
floating voltage source multilevel inverters,” IEEE Transaction on Power Elec-
tronics, vol. 17, pp. 891 — 897, Nov. 2002.

K. A. Corzine and X. Kou, “Capacitor voltage balancing in full binary com—
bination schema flying capacitor multilevel inverters,” IEEE Power Electronics
Letters, vol. 1, pp. 2 —- 5, Mar. 2003.

X. Yuan, H. Stemmler, and I. Barbi, “Self-balancing of the clamping-capacitor—
voltages in the multilevel capacitor-clamping-inverter under sub-harmonic PWM
modulation,” IEEE Transaction on Power Electronics, vol. 16, pp. 256 — 263,
Mar. 2001.

N. Celanovic and D. Boroyevich, “A comprehensive study of neutral-point volt-
age balancing problem in three-level neutral-point-clamped voltage source PWM
inverters,” IEEE Transaction on Power Electronics, vol. 15, pp. 242 — 249, Mar.
2000.

P. Josep, R. Pindado, D. Boroyevich, and P. Rodriguez, “Limits of the neutral-
point balance in back-to-back—connected three-level converters,” IEEE Transac-
tion on Power Electronics, vol. 19, pp. 722 — 731, May 2004.

D. Zhou, “A self-balancing space vector switching modulator for three level
motor drives,” IEEE Transaction on Power Electronics, vol. 17, pp. 1024 —
1031, Nov. 2002.

D. H. Lee. S. Lee. and F. Lee, “An analysis of midpoint balance for the neutral-
point-clamped three-level VSI,” in Proceeding of the 29th Power Electronics
Specialists Conference, v01. 1, pp. 193 199. May 1998.

158

[821

[83]

[84]

[851

[86]

[871

[88]

D. Zhou and D. Rouaud, “Experimental comparisons of space vector neutral

point balancing strategies for three-level topology,” IEEE Transaction on Power
Electronics, vol. 16, pp. 872 - 879, Nov. 2001.

R. Tallam, R. Naik, and T. Nondahl, “A carrier-based PWM scheme for neutral-
point voltage balancing in three-level inverters,” in Proceeding of the 19th Ap-
plied Power Electronics Conference and Exposition, vol. 3, pp. 1675 — 1681, Feb.
2004.

K. Corzine, J. Yuen, and J. Baker, “Analysis of a four-level DC/ DC buck con-
verter,” IEEE Transaction on Industry Electronics, vol. 49, pp. 746 — 751, Aug.
2002.

T. Ishida, K. Matsuse, K. Sasagawa, and L. Huang, “DC voltage control strategy
for a five-level converter,” IEEE Transaction on Power Electronics, vol. 15,
pp. 508 — 515, May 2000.

T. Ishida, T. Miyamoto, T. Oota, K. Matsuse, K. Sasagawa, and L. Huang,
“A control strategy for a five-level double converter with adjustable DC link
voltage,” in Conference Record of the 37th IEEE IAS Annual Meeting, vol. 1,
pp. 530 - 536, Oct. 2002.

T. Ishida, K. Matsuse, T. Miyamoto, K. Sasagawa, and L. Huang, “Fundamental
characteristics of five-level double converter with adjustable DC voltages for
induction motor drives,” IEEE Transaction on Industry Electronics, vol. 49,
pp. 775 — 782, Aug. 2002.

M. Marchesoni and P. Tenca, “Diode—clamped multilevel converters: A practica-
ble way to balance DC-link voltage,” IEEE Transaction on Industry Electronics,
vol. 49, pp. 752 — 765, Aug. 2002.

159

   

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