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This is to certify that the
dissertation entitled

MULTILEVEL iNVERTERS AND THEIR APPLlCATlONS IN
POWER SYSTEM

presented by
Jin Wang

has been accepted towards fulfillment
of the requirements for the

 

 

 

 

Doctoral degree in Electric @gineering
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DATE DUE

DATE DUE

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2/05 p:/ClRC/DateDue.indd-p.1

 

 

MULTILEVEL INVERTERS AND
THEIR APPLICATIONS IN POWER
SYSTEM

BY

J in Wang

A DISSERTATION

Submitted to
Michigan State University
in partial fulﬁllment of the requirements
for the degree of

DOCTOR OF PHILOSOPHY

Department of Electrical and Computer Engineering

2005

ABSTRACT

Multilevel Inverters and their Applications in Power Systems

by

J in Wang

A power system composes three interconnected subsystems: generation,
transmission, and distribution. With the ongoing expansion and deregulation, there
are also three major trends to reform the power systems: 1) to utilize distributed
generation (DG) to meet the increasing power demands; 2) to utilize Flexible AC
Transmission devices (FACTS) to improve the transmission and distribution systems;
and 3) to utilize Custom Power devices to improve the power quality to the end users

at the distribution level.

Power electronics inverters are enabling parts of DC and core parts of FACTS and
Custom Power devices. In the power electronics inverter family, multilevel inverters
are the newest breed. Compared with other inverters, multilevel inverters have two
distinguished features that make them more suitable for the aforementioned power
system applications: 1) the multilevel structures enable the utilization of low voltage
rating power semiconductor devices in high voltage applications; 2) and the almost

near sinusoidal output voltage waveforms from the multilevel inverters make it

possible to eliminate the output ﬁlters and zigzag transformers, which are often
connected aﬁer traditional inverters. Three major issues involved with multilevel
inverters in power systems are DC bank voltage maintenance. balance of DC banks,

and harmonics optimization of the inverters’ output voltage.

This dissertation ﬁrst summarizes the previous works on FACTS, Custom Power,
DC and multilevel inverters, and discusses the major application issues for cascade
multilevel inverters. A new harmonics elimination method for multilevel inverters is
proposed. Then, in the main part of the dissertation, two applications of cascade
multilevel inverters in FACTS devices — a new Uniﬁed Power Flow Controller
(UPFC) and a Universal Static Synchronous Compensator (U-STATCOM) — are
proposed. Unlike conventional UPFC, in the proposed UPFC, cascade multilevel
inverters can be used without compromising power ﬂow controllability. The
proposed U-STATCOM can be used to compensate not only reactive power and
harmonics but also load current imbalance. The circuit structures, control methods,
comparisons with conventional solutions, and simulation results are shown for both
cases. Furthermore, new applications of multilevel inverters in Custom Power and
D6 are presented as the extended applications of cascade multilevel inverters in

power systems.

In the end, the realization of the control unit for a seventeen level cascade
multilevel inverter is described. Experimental results based on the inverter are

Shown to prove the validity of proposed harmonics elimination method.

To my mother, father, and wife

ACKNOWLEDGEMENTS

Foremost, I would like to acknowledge all the invaluable help from my advisor, Dr.
Fang. Z. Peng, without whom this work would not have been possible. This dissertation
comes from numerous discussions with him, from his keen insight and guidance in a
fruitful research area. I would like to thank all my committee members, Dr. Schlueter, Dr.
Strangas, and Dr. MacCluer. Their insightful comments and suggestions have enhanced
the technical soundness of this dissertation. I am grateful to my friends and colleagues
from the Power Electronics and Motor Drive Laboratory. Not only the knowledge, but
also the research experience and friendship I gained here will be beneﬁcial for the rest of
my life. I would like to express my great appreciation to Mr. Zhiguo Pan, Mr. Alan
Joseph, and Mr. Eduardo I. Ortiz for the assistance in the tests of cascade multilevel

inverter, and Mr. Joel Anderson for helping revising my dissertation.

My thanks go to my family, especially my wife and my parents. Without their years

of encouragement and continuous support, I would not have reached this point.

TABLE OF CONTENT

I. INTRODUCTION ........................................................................................................... l
1. 1. Background .......................................................................................................................... 1

1. 2. Flexible AC Transmission Systems ..................................................................................... 3

1. 3. Custom Power ...................................................................................................................... 4

1. 4. Distributed Generation ......................................................................................................... 5

l. S. Multilevel Inverters .............................................................................................................. 7

l. 6. Outline of the Dissertation ................................................................................................... 9

11. SUMMARY OF PREVIOUS WORKS ............................................ ' ........................... l 2
2. 1. Introduction ........................................................................................................... 12
2. 2. FACTS Devices ..................................................................................................... 13
2. 2. 1 Structures and Functions of FACTS ............................................................... 13

2. 2. 2 History and Trends ......................................................................................... 18

2. 2. Custom Power Devices ......................................................................................... 21

2. 3. Distributed Generation [126-138] ......................................................................... 25
2. 4. Multilevel Inverters ............................................................................................... 26
2. 4. 1. Diode Clamped Inverter [13-23] ................................................................... 26

2. 4. 2. Flying Capacitor Multilevel Inverter [24-30] ............................................... 29

2. 4. 3. Cascade Multilevel Inverter [31-42] ............................................................. 31

2. 5. Applications of Multilevel Inverters in Power System ......................................... 34

2. 6. Summary ............................................................................................................... 36
III. REAL APPLICATION ISSUES OF MULTILEVEL INVERTERS ......................... 37
3. 1. Introduction ........................................................................................................... 37
3. 2. DC Bank Voltage Maintenance and Balance ........................................................ 38

3. 2. 1. DC Bank Voltage Maintenance .................................................................... 38

3. 2. 2. Balance of DC Bank Voltages ...................................................................... 41

3. 3. Harmonics Elimination ......................................................................................... 44
3. 3. 1. Existing Harmonics Elimination Methods .................................................... 44

3. 3. 2. Proposed Harmonics Elimination Method .................................................... 47

3. 4. Summary ............................................................................................................... 55
IV. A NOVEL UPFC WITH CASCADE MULTILEVEL INVERTER .......................... 56
4. 1. Introduction ........................................................................................................... 56
4. 2. The Conventional UPFC ....................................................................................... 57

vi

4. 3. Two Problems of the Conventional Conﬁguration ............................................... 61

4. 3. 1. Zigzag Transformer ....................................................................................... 61

4. 3. 2. The Problem with Cascade Multilevel Inverter ............................................ 64

4. 4.The Proposed Conﬁguration .................................................................................. 65

4. 5. Comparison of the New and Conventional Conﬁgurations .................................. 70

4. 7. Simulation Results ................................................................................................ 84

4. 8. Summary ............................................................................................................... 86
V. DELTA-CONNECTED UNIVERSAL STATCOM ................................................... 87
5. 1. Introduction ........................................................................................................... 87
5. 2. The Circuit Candidates of STATCOM ................................................................. 88

5. 3. The Proposed U-STATCOM ................................................................................ 91

5. 3. 1. Proposed U-STATCOM ............................................................................... 91

5. 3. 2. The compensation theory [91] ...................................................................... 91

5. 4. Control Scheme and Reference Current Detection ............................................... 94

5. 4. Simulation Results ................................................................................................ 98

5. 5. Summary ............................................................................................................. 101
VI. EXTENDED APPLICATIONS OF MULTILEVEL INVERTERS ........................ 102
6. 1. Introduction ......................................................................................................... 102
6. 2. DVR Circuits ...................................................................................................... 102
6. 3. Proposed DVR Circuit. 104
6. 3. 1. The Theory of Two Non-identical Inverter in Cascade .............................. 104

6. 3. 2 Control of Proposed DVR System ............................................................... 108

6. 4. Applications of Cascade Multilevel Inverters in DG .......................................... 1 13
6. 4. 1. Proposed Applications Examples ............................................................... 113

6. 4. 2 DC-DC Circuit Selection ............................................................................. 115

6. 4. 3. Comparisons Between Two Cases .............................................................. 118

6. 4. 4 Experimental Veriﬁcation ............................................................................ 124

6. 5. Summary ............................................................................................................. 127
VII. A 17 LEVEL CASCADE MULTILEVEL INVERTER AND EXPERIMENTAL
RESULTS ....................................................................................................................... 129
7. 1. Introduction ......................................................................................................... 129
7. 2. The 17 Level Cascade Multilevel Inverter .......................................................... 130
7. 3. The Realization of the Control Unit .................................................................... 132
7. 3. 1. Hardware of the Control Unit ..................................................................... 132

7. 3. 2. Control Signal Generation .......................................................................... 135

7. 3. 3. Inverter Module Voltage Balancing ............................................................ 140

vii

7. 3. 4. Fault Protection Scheme ............................................................................. 141

7. 4. The Experimental Results ................................................................................... 145
7. 4. Summary ............................................................................................................. 148
VIII. CONCLUSIONS .................................................................................................... 149
8. 1. Conclusions ......................................................................................................... 149
8. 2. Contributions ....................................................................................................... 151
8. 3. Recommendations for Future Work .................................................................... 153

viii

2.1:
2.2:
2.3:
3.1:
4.1:
6.1:
6.2:
7.1:

7.2:

LIST OF TABLES

Summary of FACTS Conﬁgurations .......................................................................... 18
The DGs and their interface to grid ........................................................................... 25
The feasible applications of multilevel inverters in power system ............................ 35
Switching angles examples ........................................................................................ 51
Part of the simulation results of the new conﬁguration ............................................. 85
The efﬁciency comparison ....................................................................................... 126
The summary of the comparisons ............................................................................ 127
The gate drive CPLD decoding table. ...................................................................... 140
The switching angles for MI=0.84 ........................................................................... 145

ix

LIST OF FIGURES

1.1 : The two bus power system diagram. ........................................................................... 3
1.2: The nine level waveform. ............................................................................................ 7
2.1: The VSI structure. ...................................................................................................... 14
2.2: STATCOM Conﬁguration. ........................................................................................ 15
2.3: SSSC conﬁguration .................................................................................................... 15
2.4: UPFC Conﬁguration. ................................................................................................. 16
2.5: IPFC conﬁguration. ................................................................................................... 17
2.6: BTB DC Link conﬁguration. ..................................................................................... 17
2.7: The installation of FACTS devices in United States. ................................................. 19
2.8: The basic Online-UPS system. .................................................................................. 22
2.9: The DVR structure. .................................................................................................... 23
2.10: The Six level diode clamped inverter and its line-line waveform. ........................... 28
2.11: The 6 level ﬂying capacitor multilevel inverter ....................................................... 30
2.12: 11 level cascade multilevel inverter ......................................................................... 32
2.13: The phase voltage of an 11 level cascade multilevel inverter. ................................ 33
3.1: The DC bank voltage maintenance for shunt connected inverter. ............................. 39
3.2: Example of real power ﬂow in UPFC. ...................................................................... 41
3.3: 11 level voltage waveform and general current waveform ........................................ 42
3.4: Rotation for DC bank balancing ............................................................. 43
3.5: 11 level voltage waveform and equal area criteria. ................................................... 45
4.1: Conventional circuit conﬁguration of UPFC .............................................. 58
4.2: Basic UPF C control function. .................................................................................... 60
4.3: The 48 pulse inverter. ................................................................................................ 62

4.4: The short connection when cascade multilevel inverters are connected back-to-back.

........................................................................................................................................... 64
4.5: The proposed circuit conﬁguration of UPF C .............................................. 66
4.6: The proposed UPF C with cascaded multilevel inverter. ........................................... 67
4.7: The equivalent circuit of UPFC. ................................................................................ 68
4.8: The relationship between 17C and TC. ...................................................................... 69

4.9: The full view of total VA rating between the new and conventional conﬁguration. 73

4.10: The ratio of total VA rating between the new and conventional UPFC conﬁguration.

........................................................................................................................................... 74
4.11: The 6 —- 6 projects of the Figure 4. 9. ...................................................................... 77
4.12: The vector diagram of the system. ........................................................................... 77
4.13. The relationship between inverter voltages and 6 . ................................................. 78

4.14: The active power, reactive power and receiving end line current when 6 : 45° and
(5 changes from 0° to 360°. .............................................................................................. 79

4.15: The P-Q pairs when 6 = -—25°, VC 2 0.5 p.u. and c3 rotates from 0° to 360°. ....... 80

4.16: The P-Q pairs when 6 changes 0°to -45°, VC = 0.5 p.u. and 5 rotates from 06° to

359.4°. ............................................................................................................................... 82
4.17: Operating points that have the same power but different VA rating ratio. .............. 84
4.18: Currents through both inverts and the line in the new conﬁguration. ..................... 85
5.1: The system conﬁguration of wye connected STATCOM. ........................................ 89
5.2: The imbalance compensation with wye structure. ..................................................... 90
5.3: The U-STATCOM structure and one phase voltage waveform ......................... 92
5.4: The general three-phase compensationnetwork. ........................................................ 93
5.5: Control diagram ............................................................................... 96
5.6: The uncompensated system current. .......................................................................... 99
5.7: The compensated system current and inverter voltages and currents. ..................... 100

xi

6.1: lhec
6.2: The l
6.3: Cast‘
64: ﬁre

6.5: The

 

 

6.1: The cascade multilevel inverter based DVR ............................................................ 103
6.2: The proposed DVR system. ..................................................................................... 105
6.3: Cascade 3/3 vector plots. ......................................................................................... 107
6.4: The vector plots of maximal distention. .................................................................. 108
6.5: The staircase control of the bulk inverter (Inverter 1). ............................................ 109
6.6: Conditioning inverter control diagram ..................................................................... 1 10
6.7: The simulation result of the separate control. .......................................................... 112
6.8: The proposed topology 1. ........................................................................................ 113
6.9: The proposed topology 2. ........................................................................................ 114
6.10: The proposed topology 3. ...................................................................................... 114
6.11: The general diagram of isolated dc-dc converter ................................................... 116
6.12: Two conﬁgurations of the secondary side in the isolated dc-dc converter. ........... 119

6.13: The transferred power and RMS current on the transformer in these two cases. .. 123

6.14: The experimental waveforms of the two different cases. ...................................... 125
6.15: Test setup of the DC-DC converter. ...................................................................... 126
7.1: The 17 level cascade multilevel inverter. ................................................................ 130
7.2: The schematic of the 17 level cascade multilevel inverter. ..................................... 131
7.3: The control unit diagram .................................................................. 172

7.4: Picture of the DSP board. ........................................................................................ 133
7.5: The connection of the keyboard/displayer. .............................................................. 134
7.6: The connection of fault signal .................................................................................. 135
7.7: The storage unit in the table. .................................................................................... 136
7.8: The detailed functional diagram of the CPLD. ........................................................ 138
7.9: The inverter module structure. ................................................................................. 139
7.10: Rotation of switch states between modules ............................................. 142

xii

7.11: The fault protection scheme. .................................................................................. 143

7.12: The detailed function block of the control unit ......................................... 144
7.13: The phase voltage when MI=0.84 .......................................................................... 146
7.14: The line-line voltage when MI=0.84. .................................................................... 147

xiii

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EST.

M.
14

CHAPTER 1
INTRODUCTION

1. 1. Background

With the ongoing expansion and growth of the electric utility industry, including
deregulation in many countries, the generation and transmission systems are being
pushed closer to their stability and thermal limits. Meanwhile the focus on quality of
power distribution has become greater than ever. Environmental impacts also play a
larger role than ever in investment decision makings, in all levels of power systems.
Thus, at the beginning of the let century, with major blackouts threatening the whole
world, power systems are now at a dawn of reformation. Optimization of the already
established transmission system, implementation of new technologies to ensure power
quality, and utilization of renewable energy, now become three major reformation

directions. And in this global battle of power system reformation, power semiconductor

 

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answers the call.

The very beginning of Power Electronics can be traced back to 1912, when E.F.W
Alexanderson of General Electric patented his magnetic ampliﬁer, which worked like an
ac-ac converter [12]. Modern power semiconductor based Power Electronics started with
the applications of thyristors in 19605. Since then, several generations of power
semiconductor devices have been developed. Now the Isolated Gate Bipolar Transistor
(IGBT) has become the major device used in high power conversions. IGBT rated at
4500 Volts, 900 Amperes are already available in the market. With the development of
solid devices, Power electronics circuits also evolve. Summarized in big categories, till
now, there have been DC-DC converters, DC-AC inverters, and AC-AC converters. The
power range of the converters and inverters varies from several watts to hundreds of
mega watts. Nowadays, converter and inverter based power electronics equipments have

been widely used in all levels of power systems:

1) for the transmission systems, Flexible AC Transmission Systems (FACTS) are
adopted to control the system voltage, compensate reactive power, and improve

system stability and transmission capacity;

2) for the distribution system, numerous Custom Power devices are used to

improve the power factor, compensate voltage sags, and eliminate harmonics;

3) for the distributed power generation, the power electronics equipments are

utilized as interfaces between the renewable energy sources and the grid

1. 2. Flexible AC Transmission Systems

In transmission systems, to avoid over stable and thermal limitations, the traditional
solution has been to construct more transmission lines and substations. However,
experience throughout the last several decades proves that it has been more and more
expensive, time consuming and controversial to construct new transmission lines. It has
been widely recognized that more efﬁcient utilization and better control of the existing
power system is the only way to achieve both operational stability and ﬁnancial
proﬁtability. To achieve these goals, Flexible AC Transmission Systems (FACTS) is the

only right choice [44-49].

FACTS devices provide improved transmission system operation with minimal
infrastructure investment, environmental impact, and implementation time. To better
illustrate how FACTS devices improve operation of the transmission line, some basics of
the power system will ﬁrst be introduced. Figure 1.1 is the well-known power system

diagram. When considering the power ﬂow and voltage stability, a two bus power

system can be Simply described as the sending end voltage, 1750, and the receiving end

voltage, 17R , connected together by the transmission line impedance, X .

u.

17.90 V R

Sending end X Recieving end

Figure 1.1: The two-bus power system diagram.

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Equations P
X

, (1.1)

_ (VR €039 - Vso)Vso

and =
Q X

 

(1.2)

describe real and reactive power transferred from the sending end to the receiving end,
where (9 iS the angle difference between I730 and 17R. From these equations, it can be
seen that in transmission system, there are three basic variables that can be used to
control the active and reactive power ﬂow:

0 Voltage (both Sending and Receiving ends);

0 Angle; and

O Impedance.

FACTS devices indeed are devices that enhance the transmission capacity by
dynamically changing these three variables. Depending on functions, FACTS devices are
usually installed at the ends or the middle point of the transmission line. Compared with
the corridor needed by a new transmission line, installations of FACTS devices require

almost no additional space [44-49].
1. 3. Custom Power

The term ‘Custom Power’ is usually used to describe advanced equipments that

installed in distribution systems to improve power quality for end-user customers.

Power quality is related to reliability issues in power system. A power quality

problem is an occurrence manifested in a nonstandard voltage, current, or frequency

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deviation that results in the failure or mis—operation of end-user equipments. In the
distribution system, power quality now has become a major concern for the end users.
Although, in the last two decades, numerous efforts have been put in place to increase the
power quality of existing systems, it seems that power quality still has not reached the
desired levels to be consistent with the high degree of automatization and sophistication

of modern electronic equipments. The major power quality problems are [93-97]:

0 voltage sag

0 voltage swell

O voltage ﬂicker

O momentary interrupt

O impulsive transient voltage

0 oscillation transient voltage

0 voltage harmonics

O three-phase voltage unbalance.

Recently, more and more Special attention has been focused on critical loads, such as
medical centers, automobile manufacturing plants, the semiconductor industry,

broadcasting facilities, and commercial buildings.

1. 4. Distributed Generation

Traditionally, the focus of power generation has been on large central stations. Power

is generated from central power plants and transmitted to end users, which generally are
hundreds of miles away. With the world wide rapid increase of demands on power
generation, 80,000 MW per year, and deregulation in most regions, small and local
generation-Distributed Generation (DG), will play a more and more important role in
power system. Research by Electric Power Research Institute (EPRI) indicates that, by

year 2010, 25% of the new generation will be DO [129].
DG technology includes [126-129]:
C Combustion Turbines: 1-30 MW
0 Reciprocating Engines: 10 kW-lO MW
0 Micoturbines: 1-300 kW
0 Fuel Cells: 1 kW—20 MW
0 Biomass: 5 MW maximum
0 Wind turbines: 1 kW- 1 MW
0 Photovoltaic: 1 kW- 1 MW

Due to environmental concerns, more effort has now been put into the clean DG
methods, such as, geothermal, solar thermal, photovoltaic, and wind generation, as well
as fuel cells that use hydrogen, propane, natural gas, or other fuels to generate electricity

without increasing pollution.

For solar, wind and fuel cell based DG, Power electronics is one of the enabling
technologies. Power electronics equipments are used as interfaces between the power

sources and the grid to distribute the generated power and provide ancillary services.

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One of the main obstacles in the commercialization of aforementioned types of DG is
the high installation cost. The converters or inverters used in the DG are usually the most
expensive parts in the systems. So to reduce the cost of the power electronics interface
and at the same time achieving maximum power efﬁciency and quality, now has become

very important and urgent.

1. 5. Multilevel Inverters

Multilevel Inverters were ﬁrst introduced in 1981 by Nabae [13]. Now there are three
major types of the multilevel inverters: diode-clamped, ﬂying-capacitor clamped and
cascade multilevel inverter. The general concept of multilevel inverters involves
producing an AC waveform from small voltage steps by utilizing a bank of series
capacitors or separated DC sources. To visualize the idea, a general nine level waveform

is shown in Figure 1.2.

 

 

 

 

 

 

Figure 1.2: The nine level waveform.

The small voltage steps shown in Figure 1.2, yield several of the advantages of the

multilevel inverters [1, 2]:
1) very low dv/ dt and distortion in the voltage output waveform;
2) low distortion in the input current;
3) enable the utilization of low voltage devices in medium voltage applications;
4) low switching frequency; and
5) low common mode voltages.

These advantages lead to a promising future of multilevel inverters in medium

voltage drives and power system applications.

Being a new breed of inverters, multilevel inverters attract researches on themselves
as well as their industrial applications. The ongoing research topics of multilevel inverter

include [1-12]:
1) maintenance and balance of DC bank voltages;
2) output voltage harmonics elimination;
3) PWM control method, especially at low modulation index;
4) circuit structures and soft switching; and

5) applications in power systems.

1. 6. Outline of the Dissertation

This dissertation mainly proposes two feasible applications of cascade multilevel
inverters in transmission systems. The real application issues of multilevel inverters are
discussed. One practical harmonics elimination method is proposed. Extended

applications of multilevel inverters in power systems are also presented.

Chapter 2 reviews the most current developments in FACTS, Custom Power, DG, and
multilevel inverter technologies. The feasible applications of multilevel inverters in

power system are summarized.

Chapter 3 discusses the real application issues of multilevel inverters in FACTS
devices. Current solutions are summarized and a new harmonics elimination method is

proposed.

Chapter 4 proposes a novel Uniﬁed Power Flow Controller (UPFC) circuit
conﬁguration. The proposed conﬁguration has several unique features and advantages
over the conventional conﬁguration. As a result, cascade multilevel inverter can be used
in the new conﬁguration to lower the cost, volume, and increase the reliability. Detailed
comparison between the new and conventional conﬁguration is made. Analytical and

Simulation results are also presented.

Chapter 5 introduces a Universal Static Synchronous Compensator (U-STATCOM)
based on a delta-connected cascade multilevel inverter. It is believed that the cascade
multilevel inverter will be the major circuit to be used in STATCOM. Recently, all the

researches regarding STATCOM have been focused on the wye-connected cascade

 

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multilevel inverters. But STATCOM with this kind of circuit structure can only
compensate reactive power and harmonics. Other than reactive power and harmonics
compensation, the proposed U-STATCOM can also be used to compensate negative
sequence current caused by unbalanced loads. The compensation theory based on delta-
connected compensation network is illustrated. The operation principle and control
scheme are veriﬁed by Simulation results. For extended applications, the proposed circuit

structure also can be used in D-STATCOM (STATCOM in distribute system).

Chapter 6 shows extended applications of multilevel inverters in Custom Power and
DG. For Custom Power, a non-traditional cascaded multilevel inverter structure is
proposed for a Dynamic Voltage Restorer (DVR). The non traditional multi-level
inverter is created by cascading two uneven H-bridges. In this way, the inverter structure
can operate as a nine-level cascade multilevel inverter and naturally splits the power
conversion into two parts: 1) a higher-voltage lower-frequency power inverter, and 2) a
lower-voltage higher-frequency conditioning inverter. The control strategy of the uneven
cascade multilevel inverter is presented. For DG, three applications cascade multilevel
inverters are proposed. The DC voltage regulator that used to transfer power from DC
source to the cascade multilevel inverter is discussed in detail. An optimized circuit of
the DC voltage regulator is identiﬁed. The analysis and comparisons between different
circuits are shown to support the selection. The experimental results are also presented at

the end of the chapter.

Chapter 7 Shows a 17 level 1 MVA cascade multilevel inverter and the realization of
its control unit. Experimental results from the inverter are shown to verify the proposed

harmonics cancellation method.

10

Chapter 8 summarizes the content and the contributions of this work. Some

recommendations for future work are also presented.

11

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2.1.

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CHAPTER 2

SUMMARY OF PREVIOUS WORKS

2. l . Introduction

Since their initial introduction, multilevel inverters have received much research
attention in all industrial areas. The ﬁrst applications of multilevel inverters in power
SYStem are three level diode clamped inverters, which at the time were used in
STATCOMS and UPFCS [76-78]. The newest trend of multilevel inverter applications in
POWer system are the multilevel inverter based STATCOM [85-88], Back-to-Back DC

Link [62-64], and DVRs [114, 115].

This chapter reviews the technical literature regarding the applications of multilevel
iererters in power systems. First, the basic system structures and newest developments
of different types of FACTS, Custom Power devices and DG interfaces are shown and
explained. Then, technical literature of developments of multilevel inverters and their

application in power system are fully reviewed and summarized.

l2

IUIﬂt

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It‘ﬂC

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hill t

[1011

2. 2. FACTS Devices

2. 2. 1 Structures and Functions of FACTS

Started in the 1970s, after more than two decades developments, FACTS devices have

turned from concepts presented in papers to real Mega watts devices around the world.

The early FACTS devices were mostly thyristor controlled devices. By far, the most
widely installed FACTS device is the thyristor controlled reactor or capacitor based Static
VAR Compensator (SVC), which mainly controls voltage by injecting or absorbing

reactive power to and from the grid. Till now, more than 1000 SVCS have been installed

world widely [45-49].

With the development of power electronics, nowadays researches on FACTS devices
are mainly focused on Voltage Source Inverter (VSI) based devices. VSI utilizes self-
cOIIlmutated power electronics devices, such as GTOS and IGBTS, to inverter DC to AC.

Figure 2.1 shows a general three-phase VSI with IGBTS.

Compared with thyristor controller FACTS devices, the V81 based FACTS devices
have better dynamic response and more versatile functions. That is the reason they are

n0W also popularly called as FACTS controllers.

Major FACTS devices includes:
. Static Synchronous Compensator (STATCOM)—Controls voltage;

. Static Synchronous Series Compensator (SSSC)-Controls voltage, angle and

impedance;

l3

0 [n1

0 hit

0 Bar

lrur

I1

each

 

 

 

 

O Uniﬁed Power Flow Controller (U PFC)-Controls voltage, angle and impedance;

0 Interline Power Flower Controller (IPFC)- Controls voltage, angle and impedance;

0 Back to Back DC Links (BTB)-Controls the power transmission between two

transmission systems.

 

II

 

)1

Bank

 

 

 

 

 

 

Figure 2.1: The VSI structure.

Figure 2.2 through Figure 2.6, together with a Short description of the functions of

each device gives the basic idea of how the FACTS devices beneﬁt the grid.

0. STA TCOM [78-92]

STATCOM is a VSI shunt connected to the grid. The VSI is controlled to inject or
absorb reactive current to or from the grid, thus supporting the voltage and improving the

System stability.

14

 

 

@1750 me 1 “lo

Sending end X 1 Recieving end

 

1 i
gvsm

 

 

 

nu-vn-Io

Figure 2.2: STATCOM Conﬁguration.

b. sssc [59-61]

SSSC is a VSI connected in series with the grid through a transformer. It acts like a
Voltage source cascaded with the receiving end of the system. Thus by changing the

receiving end’s voltage, phase, and impedance, it changes the power ﬂow over the grid.

 

 

@EVSO ' ........ ! VR:@

Sending end X i I i Recieving end

 

 

 

 

Figure 2.3: SSSC conﬁguration.

15

c. UPFC [65-76]

A UPFC is the combination of a STATCOM and a SSSC by back-to-back connecting
them together with a common DC link. With this combination, the UPFC inherits all the

functions of the STATCOM and SSSC and maximize the operational region [65-72].

 

IVSO r..._.._.._.._.l_.7;..;: VR
{9 | 1 I..T_..I WP 65 “—
Sending end I “JUL/'3 1 :: X Recieving end

 

 

VSI ll UPFC

PH 1 ‘j.

 

 

 

 

 

 

1 's‘rxrcoM F's-SS6 '1

Figure 2.4: UPFC Conﬁguration.

d. IPFC [57, 58]

IPF C is designed for use in multi-line transmission system. The VSIs share the same
DC link, and are series connected in different transmission line. In other word, an IPFC
is a combination of several SSSCs with one common DC link. In this structure, power
ﬂows from line to line through the DC link. With proper control, the power exchange
between different lines can be conditioned and optimized. Similar as the SSSC, an IPFC

controls the grid’s voltage, phase and impedance.

l6

SOUP
DC 1
[‘01)]

101111

 

 

 

 

 

 

 

 

 

 

 

 

I D - O O - I O — 0 O - I O - O I - D 0

Figure 2.5: IPFC conﬁguration.

e. BTB DC Link [62-64]

A Back-to-Back DC Link is used to connect two asynchronous systems together.
Viewed from the each side of the systems, BTB DC link functions either as a voltage
source or load depending on the direction of the power ﬂow. The structure of the BTB
DC Link is a combination of two STATCOMS with one common DC link. It controls the
power ﬂow between two asynchronous systems by allowing power ﬂow through the

common DC Link.

I
—l—TT0 :%é—— vs1 % vs1-— 1+—: To

SystemlL l System2

——-—-—-——————_————-—d

Back-To-Back DC Link

 

 

 

 

 

 

 

 

 

 

Figure 2.6: BTB DC Link conﬁguration.

17

From the ﬁgures and descriptions above, it can be seen that the FACTS devices can be
Simply described as VSIS, either shunt or series connected to the grid through

transformers. Table 2.1 summarizes circuit structures of FACTS devices.

Table 2.1: Summary of FACTS Conﬁgurations

 

FACTS Device Number of VSI Conﬁguration

 

 

 

 

 

STATCOM 1 Shunt
SSSC 1 Series
Shunt+Series back-
UPFC 2
to-back
N (number of the .
Serres
IPFC High Voltage
back-to-back
Lines)
Back-to-Back DC 2 Shunt
Link back-to-back

 

 

 

 

 

2. 2. 2 History and Trends

Though it is not quite widely recognized, the world’s ﬁrst functional STATCOM was
installed in 1991, in Inuyama Substation, Japan. The STATCOM is rated at 80 MVA,

and connected to 154 kV bus. It was built and installed by Mitsubishi Electric [63, 78].

18

The world’s ﬁrst UPFC was commissioned in Inez, Kentucky, USA, in 1998, by
American Electric Power (AEP). The UPFC is composed of one i- 160 MVA

STATCOM and one .+_ 160 MVA SSSC [76, 77].

In 1999, the wolrd’s ﬁrst VSI based Back to Back DC link was put into operation in
Japan. The BTB conveys 53 MVA of power between one 50 Hz and one 60 Hz system at
275 kV [63, 64].

Figure 2.7 shows the major FACTS devices that already have been installed in United

States.

 

  

UPFC, Inez Substation, 1998
160 Mvar STATCOM & 160
Mvar SSSC

    
   
 
 
  

 

 

  

200 Mvar
Convertible Static
Compensator,
Marcy Substation,
1998

 
   
   

 
  
 

  

TCSC, Slatt
Substation,
1 993

 

    
 
   
 

 

-~ STATCOM, Sullivan

‘ ﬁt 50 MW Back-To-
. - Substation, 1995

Back HVDC Link,
EaglePass, 1995

 

 

 

 

Figure 2.7: The installation of FACTS devices in United States.

In the newest developments of FACTS devices, two major projects show the trends of

the FACTS.

One is the i 75 MVA STATCOM for the 400 kV British National Grid [86, 87]. The
STATCOM was built by Alstom and installed at East Clayton, UK, in the year 2000.
The highlight of this project is that a cascade multilevel inverter is used as the basic
circuit structure for the STATCOM. This, from one aspect, shows that the cascade
multilevel inverter would be one of the major circuit candidates for the new STATCOMS

in the years to come.

Another project is the i 200 MVA Flexible Multi-functional Compensator, also
called Convertible Static Compensator, which was commissioned at Marcy Substation,
NY, in year 2002 [53, 54]. This Compensator stands for the latest generation of FACTS
devices. The Compensator has two 100 MVA inverters and can be conﬁgured into 11
different conﬁgurations for a total of four basic operating modes: STATCOM, SSSC,
UPFC, and IPFC. This project shows that the one of the major requirements for the next

generation of FACTS devices will be multi-functional.
The success of both projects shows that the trends of the FACTS are:
1) utilization of cascade multilevel inverters; and
2) realization of multi functions with one installation.

But one inconsistency exists in these two trends. That is cascade multilevel inverter
can not be back-to-back connected. It is generally believed that cascade multilevel
inverters can not be used in UPFC and IPFC. Trying to overcome this problem and
widening the applications of cascade multilevel inverter, this work proposes a new UPFC

circuit conﬁguration and a Universal STATCOM in the following chapters.

20

2. 2. Custom Power Devices

As Custom Power devices are in their infancy, there are very few useful standards to
enable customers and suppliers to communicate performance requirements on these
devices. But with the high demand of better power quality, all types of Custom Power
Devices have already been installed around the world for both industrial and residential

purposes [93-99].
The most common Custom Power Devices include:

0 Uninterrupted Power supply (UPS)-Corrects voltage sag, momentary interrupt,

and acts as backup power;
0 Dynamic Voltage Restorer (DVR)-Corrects voltage sag;

O Shunt/Series Active Power Filter (APF)-Compensates harmonics and voltage

unbalance;

O Uniﬁed Power Quality Conditioner (UPQC)-Compensates harmonics, voltage

imbalance, reactive power, and voltage sag;

0 Distributed STATCOM-Compensates reactive power, adjusts user end voltage.

Custom Power equipments are also based on VSIS. The conﬁgurations of Custom
Power equipments are similar with the FACTS controllers. These two types of systems
can be seen as applications of VSIS at different power system levels. Besides UPS,
Custom Power devices are usually installed in medium voltage system (10 kV to 35 kV).
The current ratings of Custom Power devices typically ranges from 300 A to 1200 A.

The structures and operating principles of these devices are introduced as following.

21

1L ('1

the

W“

W.

0111

a. Uninterrupted Power Supply (UPS)

UPS is the most widely used Custom Power devices. Currently there are three major
types of UPS in the market: 1) Standby UPS; 2) Line Interactive UPS; and 3) Online UPS

(also called ‘True UPS’).

Among these three, the Online UPS is the most promising and is receiving most of
the research attentions. Figure 2.8 shows its basic structure. For this type of UPS, the
power is sent to the load through the UPS all the time. During normal conditions, the
battery in the UPS is charged, the power ﬂows from the grid through the UPS to the load.
When there is interrupt or voltage sag, the VSI is controlled to generate a stable voltage

output. The battery is forced to supply partial or full power to the load.

Filter

aco— Battery —}— VSI l T0

 

 

 

Input Charger

 

 

 

 

 

 

 

Figure 2.8: The basic Online-UPS system.

b. Dynamic Voltage Restorer (DVR) [114-125]

A DVR’S main function is to correct voltage sag. Research shows that voltage sags
contribute 92% of the voltage disturbance in power systems. Besides DVR, there have

been several other commercially available solutions for voltage sag:

1) Static Transfer Switch (STS), which utilizes thyristor switches to transfer the
load from the main power supply to a backup line; the drawback is the need for

two power line;

22

2) Superconducting Magnetic Energy Storage (SMES), which provides a ride-

through solution; high cost and the need for cooling are the main drawbacks;

3) Different storage type based UPS, like Flywheel UPS and battery UPS; the

maintenance and cost are the limiting factors of their application.

DVR is usually used in medium voltage level and to compensate the voltage sag for
all the loads that are connected to the feeder. Compared to other solutions mentioned
above, DVRs have better performance, lower cost, less maintenance, and in some cases,
have a comparatively smaller size. Figure 2.9 shows one basic structure of a DVR. It
combines a VSI and a series-connected transformer to inject additional voltage during
voltage sags. A grid connected rectiﬁer or power storage device will supply the real

power needed by the VSI.

In recent papers, it has been shown that the newest trend for the DVR is the
utilization of cascade multilevel inverters [114, 115]. In Chapter 6, an uneven cascade

multilevel inverter based DVR is also presented.

1; """" ‘ """"" aw- """" *

From Power 1 Iii??- ? To

Source i l ‘ Load

 

 

 

 

 

Rectiﬁer % VSI

 

 

 

 

 

 

 

Figure 2.9: The DVR structure.

23

c. Active Power Filters (APF) [105-1 10]

APFs are mainly used to compensate the harmonics in current and voltage. There are
two kinds of APFs: shunt APF and series APF. The shunt APF is a VSI shunted with the
grid. It injects harmonics current to neutralize the harmonics in the load current. Series
APF is a VSI series connected to the grid to generate a harmonics voltage to correct the

input voltage and block the harmonics in the load current.

The realization of the APF needs an effective harmonics detection method and a
coordinated control strategy. The harmonics detection methods are always strongly
related with instantaneous power theory. Thus, the history of APF is also a history of
instantaneous power theory and other modern power theories. Though the ﬁrst Shunt
APF was built more than 16 years ago [105], the research on APF still remains a hot topic
in the power electronics world. New circuit structures, new control strategies, and

arguments of different power theories still can be seen very often [100-104].

d. Unified Power Quality Conditioner (UPQC) [111-113]

UPQC is a combination of Shunt and Series APF by connecting them back-to-back
together. The circuit structure is exact the same as its FACTS relative: UPFC. The
difference is that the UPQC is aimed at the distribution system and mainly compensates

harmonics, reactive power and system imbalance.

e. Distributed STA T C 0M (D-S TA T C 0M)

24

(I)

51

‘r?

D-STATCOM is the application of STATCOM at the distribution level. A D-
STATCOM is usually installed near critical load and only guarantees the voltage and
stability of the load direct paralleled with it. In recent years, D-STATCOM has become
very popular as more and more end users begin to understand the damage that can be

caused by the voltage problems [91].

2. 3. Distributed Generation [126-138]

As mentioned in Session 1.4, power electronics equipments are interfaces between
the distributed power sources and the grid to distribute the generated power and provide
ancillary services. Table 2.2 summarizes the types of DOS that involve power electronics

interfaces.

Table 2.2: The DOS and their interface to grid

 

 

 

 

 

DG Interface to Grid
Photovoltaic dc-ac inverter
Wind turbine ac-ac converter
Microturbine ac-ac converter

Fuel Cell dc-ac inverter

 

 

 

 

With the proper interface with the grid, DG can beneﬁt the power system from all

perspectives. The beneﬁts are summarized as following [126-129]:

utility perspective

)9 transmission capacity relief

25

6’1

> distribution capacity relief

> hedge against high market prices

end-user perspective
> efﬁcient use of energy from combined heat and power

‘P improved reliability by having backup generation and ancillary services (reactive

power, voltage sag compensation, etc)

> incentives from utility to provide capacity reserve or power market hedge

commercial power producer perspective
> owner market (to sell power)

> to sell ancillary services (reactive power, standby capacity, etc.).

Recent research about DG includes maximum power tracking of photovoltaic and
wind turbine, low cost inverter system, stability and other problems when connected with

grid, and applications of cascade multilevel inverter.

2. 4. Multilevel Inverters

2. 4. 1. Diode Clamped Inverter [13-23]

The multilevel inverter family started with the 3 level diode clamped inverter in 1981
[13]. The ﬁrst industrial application of the diode clamped inverter was for the bullet train

in Japan. After two decades’ of development, the diode clamped inverter has become the

26

1.01.

111

most widely used multilevel inverter in the world [14-23]. In the 1990’s, people began to
propose and build diode clamped inverters with more than 3 levels. Figure 2.10 shows
the structure of a three phase, 6 level diode clamped multilevel inverter and its output
line-line voltage waveform. In the DC bus of the inverter, there are ﬁve capacitors in

series. The voltage cross each capacitor is Vdc- Thus by turning on and off the switches

following a particularly sequence at pre-calculated angles, the phase voltage can be 0, 1

Vdc , 2 Vdc , 3 Vdc , 4 Vdc , and 5 Vdc correspondently. By proper synthesizing Vao and
Vbo together, the line-line voltage, Vab, can change from -5 Vdc to +5 Vdc- In real
applications, 61 ~ 05 , is usually calculated according to the desired modulation index and

harmonics elimination. In multilevel inverters, the modulation index is deﬁned as the

following:

V

Mlzzlii, (2.1)
gN'Vdc

where Vpeak is desired peak value of fundamental frequency in the staircase waveform,

N is the maximum number of the level. In equation (2.1), the coefﬁcient %[ is the

amplitude of the fundamental component of a unit square waveform.

27

 

(a). The 6 level diode clamped inverter.

5rd,
4rd,

311,,
2rd,
lVd.

 
 
 
 
 

(b) The line-line voltage.

Figure 2.10: The six level diode clamped inverter and its line-line waveform.

28

In the diode clamped inverter, three phases share the same DC bank, which makes the
back-to-back connection possible. The switching frequency of the inverter is minimized
to the fundamental frequency. Each active switching device has same voltage and current
stress. However, each clamping diode in the circuits needs to clamp different voltage

levels. For example, the clamping voltage for D1 and D1 ' is Vdc, whereas D4 and D4.

clamp 4 Vdc .
In summary, the major advantages and disadvantage of the diode clamped inverter are:

Advantages:
0 Low switching frequency;

9 Feasibility for back-to-back connection;

Disadvantage

6 Different voltage ratings for different clamping diodes.

Till now, diode clamped inverters have mostly been used in medium voltage drives
[15-17]. The major power system applications of this kind of inverter include
STATCOM, interface between DC and AC transmission line, and back-to-back

connected power conditioners [18-20].
2. 4. 2. Flying Capacitor Multilevel Inverter [24-30]
Flying capacitor multilevel inverters were ﬁrst introduced by Meynard and Foch in

1992 [24]. A three-phase, 6 level ﬂying capacitor multilevel inverter is shown in Figure

29

J

Cu

2.11. Each capacitor shown in Figure 2.11 has the same voltage. All the switching

devices have the same voltage and current stress.

This kind of inverter has similar structure as the diode clamped inverter. The
difference is that it utilizes capacitors other than diodes to clamp the voltage. With this
kind of structure, the ﬂying capacitor multilevel inverter has more switching state
redundancy in producing the staircase waveform. But at the same time, the bulky
capacitors also make the system more expensive and difﬁcult to build. The charge and

balance of the capacitors in the inverter also makes the control more complex [25-28].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2.1 1: The 6 level ﬂying capacitor multilevel inverter.

30

SUIlllll

.i ii iii l

Disuel

Fl
suinh

t-i‘t 0

2. 4.

1mm,
dislre.
and I:
lllt" nu

liliffT

The advantages and disadvantages of ﬂying capacitor multilevel inverter are

summarized as following:

Advantages:
0 More switch state redundancy;
0 Large number of capacitors, which enables better performance during voltage
sags;
Disadvantages:
6 High cost and high volume caused by the large number of the capacitors;

6 More complex control required to balance the voltages cross each capacitor.

Flying capacitor multilevel inverters are suitable for all the applications that are
suitable for diode clamped inverters. But due to their disadvantages, applications of this

type of inverters are seldom reported [29, 30].

2. 4. 3. Cascade Multilevel Inverter [31-42]

Cascade multilevel inverter is quite different from the aforementioned two multilevel
inverters. It utilizes H-bridge inverter units by cascading them together to produce

desired staircase waveform. Each H-bridge has a separated DC source and can produce 0

and i1 Vdc voltage levels. Thus, the phase voltage would have 2N+1 levels, where N is

the number of separated DC sources per phase. Figure 2.12 shows the wye-connected

three~phase 11 level cascade multilevel inverter.

31

L-
I—
I—
l—

l? :Ellééllér 135

<
8
S:

<
8

8S

 

I
II
II

 

 

 

 

 

 

RF

L

val J3 JBﬂVdc

va2

L.
l—

 

 

 

 

 

 

 

 

 

 

5
5

L
[—

 

 

 

ll

 

 

 

 

 

 

va3

5
5

L.

 

 

 

va4

 

 

 

 

 

 

’V.

 

 

l—
L.

 

 

 

va5

 

 

 

 

 

 

Vdc

RS

L

 

 

 

L
l L L , L L l L L t L L
\l \L 11 J1 .
L

 

 

 

 

0

Figure 2.12: 11 level cascade multilevel inverter.

Each module in Fig 2.12 produces a three level staircase waveform at different duty
cycle. AS modules’ outputs are cascaded with each other, the phase waveform as shown

in Figure 2.13 can be achieved.

32

C131

[lift

  
    
    
 

 
    

 

     
   

 

 

--—--------- h------
-------¢----_--«b------

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1111 1:
1111 V1 ' 11'11
val :111I l '1111' ‘1 ii
iii! . ii iiL—V—Ji ii
1.5111: "r 1
'11
va5[ 11' l

 

 

Figure 2.13: The phase voltage of an 11 level cascade multilevel inverter.

Because the H-bridge can be modularized, the cascade multilevel inverter is now the
most favored circuit for new designs of power system compensation and large motor

drives. Applications of cascade multilevel inverters in HEV are also proposed [41].

As for power system applications, Peng, Lai, Joo, Visser and other authors have
demonstrated that cascade multilevel inverters can be either shunt or series connected to
the grid to act as power conditioners such as STATCOM and DVR [36-40]. Full
comparisons between different circuit candidates for STATCOM are made in [85]. It is

proved that the cascade multilevel inverter is by far the best choice for STATCOM.

33

I”.

in

I
8.1;)

One of the most important features of the cascade multilevel inverter is that separated
DC sources are needed. This feature, on one hand, prevents connecting two cascade
multilevel inverters back-to-back together; on the other hand, makes cascade multilevel
inverters the best choice for many conditions that a lot of DC sources that are used for

generation purpose, such as fuel cells and photovoltaic cells in DG.

The main advantages and disadvantages are summarized as following:

Advantages:

O Utilization of modularized H-bridges, which lowers the cost and makes the
manufacture and maintenance much easier;

9 Maximal utilization of the DC sources by producing 2N-l level phase voltage;

0 The best choice for HEV, fuel cell and photovoltaic applications where many

small DC power cells are involved;

Disadvantages

O The need for separate DC sources, which makes it not infeasible for back-to-back

connection applications.

2. 5. Applications of Multilevel Inverters in Power System

After the above review of FACTS device, Custom Power, DO and the multilevel
inverters, the feasible application of multilevel inverters in power systems can be

summarized in Table. 2.3.

34

Table 2.3: The feasible applications of multilevel inverters in power system

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FACTS
Back-to-Back DC
STATCOM SSSC UPFC IPFC
Link
Diode Clamped
. 1 1 1 1 1
Multilevel Inverter
Flying Capacitor
, 1 1 1 1 1
Multilevel Inverter
Cascade Multilevel
1 1 x x x
Inverter
Customer Power
UPS DVR APF UPFC D-STATCOM
Diode Clamped
1 1 1 1 1
Multilevel Inverter
Flying Capacitor
, 1 1 1 1 1
Multrlevel Inverter
Cascade Multilevel
1 1 1 x 1
Inverter
DG
Fuel Wind
Photovoltaic Microturbine
Cell Turbine
Diode Clam ed
p 1 1 1 1
Multilevel Inverter
Flying Capacitor
1 1 1 1
Multilevel Inverter
Cascade Multilevel
1 1 1 1
Inverter

 

 

 

 

 

 

35

 

2. 6. Summary

In this chapter, the developments of FACTS, Custom Power and DG were reviewed
ﬁrst. Then three major multilevel inverters were introduced one by one. Their circuit
structures, advantages and disadvantages were explained. The literature about their
developments and applications were reviewed. In the end, their feasible power system

applications of multilevel inverters were summarized.

By utilizing multilevel inverters in power system applications, the bulky transformers
usually used for traditional inverters can be eliminated, whereas the stresses on the
switches can be greatly reduced. Because of its modular structure, among the three major
types of the multilevel inverters, cascade multilevel inverter is the most suitable one for

power system application.

All the applications of multilevel inverters in power systems have some common
implemental issues. So before breaking into detailed application cases, the next chapter
will ﬁrst address the following most common implemental issues of multilevel inverters:
maintenance and balance of DC bank voltages and harmonics elimination in output

voltage.

36

CHAPTER 3

REAL APPLICATION ISSUES OF
MULTILEVEL INVERTERS

3. 1. Introduction

DC bank (capacitor) voltage maintenance and balance, and output voltage harmonics
elimination are the three most important issues for real applications of multilevel
inverters in power systems. Without well maintained and balanced DC banks, the
synthesis of a stable staircase voltage waveform would be impossible. To meet the THD
requirement of the power system, the switching angles of multilevel inverters must be

optimized to eliminate the lower order harmonics.

This chapter introduces the methods to maintain and balance the DC bank voltages,

and proposes a practical harmonics elimination method.

37

3. 2. DC Bank Voltage Maintenance and Balance

3. 2. 1. DC Bank Voltage Maintenance

In all the power system applications of multilevel inverters, it is always crucial to
maintain DC bank voltages at a certain value. But depending on different applications,
the ways to maintain the voltages are also different. Summarized in the nature of the
applications, basically, there are three different conditions for DC bank voltage
maintenance:

1) pure reactive and harmonics compensation;

2) back-to-back connected applications; and

3) distributed generations applications.

a) pure reactive and harmonics compensation

In the case of STATCOM, SSSC, and APF, the multilevel inverter only outputs or
absorbs reactive power. Ideally, no real power is consumed by the inverter. Thus, the
DC bank voltage should automatically maintain. But in the real applications, there is
always power loss in the multilevel inverters. Besides power loss on parasitic resistance
in the bus bar, wires, inductors and capacitors, the switches and diodes have switching
loss and conduction losses. In most cases, the major power loss of multilevel inverters is
from the switches and diodes. Without compensating for the power loss in the inverter,
the DC bank voltages will drop gradually, and the desired functions of the inverter can

not be realized.

38

To. to
nlue. 1h.
FOlVCI. I

needed h

In 1h
SIAICI
line is 1

figure 3

ASS
bank 1'0
llle llt‘e

\‘Ollatm
\ \

 

To compensate for the power loss and adjust the DC bank voltages to the desired
value, the inverter needs to be controlled to absorb or output a small amount of real
power. Usually, a simple PI controller would be used to decide how much real power is

needed by the inverter.

In the cases where multilevel inverters are Shunt connected to the utility line, such as
STATCOM and Shunt-APF, the real power exchange between the inverter and the utility

line is realized by controlling the inverter to send and absorb real current as shown in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3. 1.
(9
»
=1 + Synthesizer Inverter
Vd: I
PI Controller —>
Vd:

Figure 3.1 : The DC bank voltage maintenance for Shunt connected inverter.

Assuming all the DC banks in the multilevel inverter are balanced, only one DC bank

V01tage is monitored. The monitored voltage, Vdc , is compared with the desired DC

bank voltage, V36. The result is fed into the PI controller to calculate the amplitude of

the needed real current. Then, together with the detected phase angle of the utility phase

voltage, 6’, an instantaneous real current reference, ireal , can be synthesized. The

39

multilevel inverter would be controlled by the combination of the reactive current

command, ireawve , and real current reference, ireal°

Similarly, in the series connected cases, such as SSSC and Series-APF, the multilevel
inverters could be controlled to output a voltage in phase with the utility phase current to

absorb or output real power to maintain the DC bus voltage.

Another commonly used method for shunt connected inverter is to control the Shunt
inverter to output a voltage, which has a Slight angle difference from the grid voltage. In
this method, the inverter and grid can be seen as two AC voltage sources connected
together through the inductor. Thus, the power ﬂow in these cases will obey equation
(1.1) and (1.2). With the Slight angle difference between inverter voltage and grid

voltage, real power can ﬂow into or out of the inverter.

b) back-to-back connections

In the back-to-back connection systems like UPFC, UPQC, IPFC, and BTB, the DC

bank acts as a link to transfer the real power from one inverter to another.

For example, in UPF C, the SSSC is controlled to inject a voltage to the utility line. If
the phase angle difference between the injected voltage and utility phase current is not
90°, real power ﬂow will occur between the SSSC and the utility line. Thus, the SSSC
will charge or discharge the DC link. To maintain the DC link voltage, the STATCOM
should be controlled to absorb or output the same amount of real power to charge or
discharge the DC link to make the total charge or discharge to zero. At the same time,
the power loss in both inverters will tend to lower the DC link voltage. So the

STATCOM also needs to be controlled to compensate for the power losses. Figure 3.2

40

Show:

the re

21m

16‘

Vii]

bill.

shows one example of the real power ﬂow in the UPFC. The shadowed arrows indicate

the real power ﬂow in the UPFC.

@175";

Sending end

 

  

X Recieving end

 

 

 

 

UPFC

 

 

 

 

 

 

. .
.
.u-v.— h-.—..—-

I S—TATCOM SSSC i

 

Figure 3.2: Example of real power ﬂow in UPFC.

c) distributed generations

In DG, the DC banks of the inverters are powered by energy sources like fuel cells
and wind turbines. Between a DC bank and an energy source, there always is a voltage
regulator to regulate the input voltage to the DC bank. Depending on applications, the
regulator can be a dc-dc converter or a rectiﬁer cascaded with a DC-DC converter. The

DC-DC converter will be discussed in detail in Chapter 6.

3. 2. 2. Balance of DC Bank Voltages

Though the circuit structure and applications of multilevel inverters may be different,
the methods to balance the DC bank voltages can be the same. In this section, an 11 level
Voltage waveform and corresponding general current waveform is used to Show how to

balance the DC bank voltages.

41

AS Shown in Figure 3.3, each level of the voltage waveform is realized by utilizing
the voltage on different DC banks. The current has a phase angle difference from the
fundamental of the voltage waveform. Thus, the current has both reactive and active
components, which stands for a general condition. The power consumption on each DC

bank can be calculated as:

_ 1 ”9n . 27r—6n .' .
Pray—{(5)7 Vdc.r(e)-de+L+6n Vdc 1(a) dd). (3.1)

Since 6,, is different for each level, the power consumption on each DC bank during

one fundamental cycle is also different. Further more, the conduction loss and switching
losses that faced by each DC bank are also different too. So, without any voltage balance

procedure, the DC bank voltages in the multilevel inverter would be different from each

  
       
   
   
 

other.
6 /11 level staircase voltage
991.31%: ________ <94 .,-7."i‘:‘:- Current
19913119154 ______ ..:’ _________ , _______ " /
1.3913311; _3_ , 192..- ,,,,,,,,,,,,
99.391112. 91 ...........................
13.93.311.191. r.

- ------ - - , Fundamental Voltage
DQBankJ. ........................... '

DC. Bank. .2. . ‘
DC Bank 3 ‘

 
 

DC Bank 5 ' ' '

 

Figure 3.3: 11 level voltage waveform and general current waveform.

One Simple solution to avoid the unbalance between the DC banks is to rotate the

SWitching angles between DC banks, as Shown in Figure 3.4. By rotating the switching

42

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43

angles through each DC bank, after ﬁve fundamental cycles, each DC bank would have
experienced exactly the same amount of power consumption. Thus, the DC bank

voltages will be balanced.

3. 3. Harmonics Elimination

Since the ﬁrst introduction of the multilevel inverters, many harmonics elimination
methods have been proposed [6, 9, 139-143]. But harmonics elimination still remains as
a major and hot topic for the multilevel inverters. A Simple and practical way to solve

this problem is still needed.

To answer the call of a simple solution, a new practical harmonics elimination
method is proposed in this dissertation. Unlike other methods published before, the
proposed method does not need to solve high order polynomials. Only four simple
equations and minimum calculation time are needed to realize the elimination of selected

harmonics. Experimental results based on the proposed method will be Shown in Chapter

7.

3. 3. 1. Existing Harmonics Elimination Methods

Till now, there are two major types of harmonics elimination methods: 1) PWM
methods, which include both Sinusoidal PWM and space vector PWM methods [140-143];

and 2) optimized switching angles methods [6, 9, 139].

The PWM methods are usually used when the number of voltage steps is quite limited,

e.g., 2 or 3 steps. The performance of these methods is decided by the switching

44

frequency. The higher the switching ﬁ‘equency, the lower the harmonics content in the

lower frequency range.

Optimized switching angle methods are often used for cases with more voltage steps.
The switching frequency in these methods is the same as the fundamental frequency. The

number of eliminated harmonics is decided by the number of voltage steps.

In this section, only Optimized switching angle methods are discussed. The general 11
level voltage waveform is shown again in Figure 3. 5 as an example to explain how the

optimized switching angle methods work.

 

 

Figure 3.5: H level voltage waveform and equal area criteria.

The Fourier series expansion of the voltage waveform shown in Figure 3.5 is

00
War!) 2 Z 4:: (cos(m61) + - - ~cos(m6N )) sin(ma)t) , (3. 2)
m=l,3,5,---

 

where N is the number of switching angels and m is the harmonic order.

45

Based 0'

found by St‘.

In this‘

Where l’F

 

 

eliminatigi
S\\'llClllng

group “'0
Melt
2mm (2

equating

 

Based on equation (3.2), ideally, the optimized switching angles, 61—65 , can be

found by solving the following equation groups

{ 4Vdc

 

7: (cos(61) + cos(62) + cos(63) + cos(64 ) + cos(65 )) = VF
i cos(561) + cos(562) + cos(5c93) + cos(56l4 ) + 008(565) = O . (3. 3)

 

i cos(13t91) + 0030 362) + cos(1363 ) + cos(l 364) + cos(1365) = O

In this equation group, the ﬁrst equation will guarantee the desired modulation index,
where VF is the desired fundamental voltage. The followed equations will ensure the
elimination of 5m, 7m, 11‘“, and 13th harmonics. To eliminate more harmonics, more
switching angles and more voltage steps are needed. But with more angles, the equation

group would have more equations and higher orders.

Methods proposed in [6, 9, 139] essentially are methods that try to solve the equation
group (3. 3) with different approaches. Due to the high order polynomial nature of the

equation groups, there are several disadvantages of these kinds of methods:

1) these methods usually involve complex algorithm and huge calculation time;
when the number of switching angle increases, the capability limitation of

contemporary computer algebra software would be easily reached;
2) the number and order of polynomial equations increase with the switching angles;
3) only N —l harmonics can be eliminated;

4) the algorithms in these methods are often based on special theories, which makes

it difficult for users to re-perform the methods.

46

Researches shows that to solve the simplest case like equation groups (3. 3), it still
takes special algorithm and long calculation times to solve. For larger and higher order
equation groups, there would be a point that to ﬁnd the solutions becomes impractical [6,

9,139].

3. 3. 2. Proposed Harmonics Elimination Method

A. The Basic Idea of the Proposed Method

The proposed method in this work tries to solve the harmonic elimination problems
from a totally different approach. No high order multi-variable polynomial equations

would be involved in proposed method.

Unlike all the other methods, the proposed method is not originated from equations,
but from the basic ideas of switching angle initialization and utility line harmonics

compensation.

To better illustrate the proposed method, equal area criteria and harmonics

compensation principle of APF are ﬁrst introduced and restated as following:

I) The equal area criteria for switching angle calculation.

In the earlier papers about multilevel inverters, the equal area criterion is introduced
as one method to calculate the initial value of switching angles. The calculated initial
values will be used in the process of solving equation group (3. 3). The basic idea of

equal area criteria is also shown in the circled area of Figure. 3.5.

47

The initial switching angle, 6k is found by solving

$1: $2, (3.4)

where S 1 and S 2 are the areas of the shadowed part in Figure. 3. It has been proven that
by using the equal area criteria, the fundamental of the stair case waveform would
resemble the sinusoidal modulation waveform. However, with only equal area criteria,

no harmonics elimination can be realized.

The proposed method tries to answer the question of how to utilize the initial values
from equal area criteria to ﬁnd the optimized angles without solving the high order multi-

variable polynomials equations.

2) Harmonics injection in Active Power Filters

As mentioned in Chapter 2, Active Power Filter (APF) is used to eliminate voltage

and current harmonics in utility line.

APFs will inject new harmonic voltages or currents into the utility line to eliminate
harmonics that already exist in the utility line. The injected harmonics would have the
same amplitudes but opposite phase angles of the selected harmonics they are intended to

eliminate. Thus the harmonics in the utility line are neutralized.

The key point of harmonics elimination in APF is to realize harmonics elimination
by injecting new harmonics. Combining equal area criteria and the idea of harmonics

injection together, a new method to ﬁnd optimum switching angles can be found.

48

B. The Proposed Method

The proposed method indeed is a combination of equal area criteria and harmonics

injection. The basic idea behind this method is described as following:

1)

2)

3)

4)

by using equal area criteria, pure sinusoidal modulation waveform, h] = vsin a)! ,

will derive a set of angles 61 — 6N;

the staircase waveform formed by 61 -— 6N will have the fundamental component,

hi , and harmonics content h3,h5,h7 whm , the fundamental component, hi , will

resemble the sinusoidal modulation waveform, hl ;
ideally, if take (—h5 —h7 --—hm) as the modulation waveform, by using equal
area criteria, another set of angles, (91” 49;?) , can be found; the staircase

waveform formed by (91h —c9;t', would have component —hg ~11"; --—h;,, and
other higher order harmonics; due to the nature of equal area criteria,
—h; —h'7 ..—h;,, will resemble -—h5 —h7 --—hm;

so if use h1 -h5 —h7 --—hm as the modulation waveform to ﬁnd a series of
switching angles, the selected harmonics content in the resulted staircase
waveform would be around h5 +117 --+hm —h'5 —h'7 ~-—h;,, ; because
— h; —h:; ~— h;,, resembles — h5 ——h7 ~-— hm, the harmonics elimination is partly

realized.

49

5) if the same process in 2)-4) is iterated, the harmonics“ elimination can ﬁnally be

realized.

To implement this idea, the following ﬁve steps need to be followed.

1) ﬁrst, based on equal area criteria, ﬁnd the initial switching angles (61 — 6N) for a

given modulation waveform, h] , at a certain modulation index;

2) then ﬁnd the non-third harmonics content ( h5,h7 whm ) of the staircase
waveform formed with switching angles , (91 — 6N; the 5th, 7th, and all the way to

the mth harmonics are the selected harmonics for elimination;

3) subtract the harmonics content, h5,h7 whm , from the original modulation
waveform h to form a new modulation waveform, h—h5 —h7 n—hm; for the
ﬁrst iteration, hzhl; from this step, the modulation waveform would have

injected harmonics and become nonsinusoidal;

4) ﬁnally, use the new nonsinusoidal modulation waveform to calculate a new set of

(61 — (9 N ) based on the equal area criteria;

5) repeat steps 2)-4) until achieving the best switching angles, which would result in

zero selected harmonics content.

In step 1), the modulation waveform is pure sinusoidal, after step 3), the harmonics
are already injected; the modulation waveform would never be sinusoidal again. The

more the iteration, the more the harmonics in the modulation waveform. Though the

50

 

for

in

int

n}

modulation waveform has large injected harmonics content, the stair case waveform

formed by the ﬁnal switching angles would have almost no selected harmonics.

To prove the concept, this method has been used to calculate the switching angles for
the case shown in Figure 3.3. In the calculations, ﬁve harmonics are chosen for

elimination. After about 100 times of iterations, the values of 5th, 7th, 11th, 13th, and 17th

harmonics drop under 10‘6 p.u, which means these harmonics are totally eliminated.
The number of totally eliminated harmonics is equal to the number of switching angles,
N . For a desktop computer with a 2.8 GHz CPU, the calculation time of one modulation
index is less than 1 second. Table 1 shows the switching angle examples for modulation

index at 0.85 and 0.86. The modulation index is deﬁned as:

——————, <3. 5)
3N-V...
72'

where VF is the peak value of the fundamental components.

Table 3.1: Switching angles examples

 

61(rad.) 62 (rad) 63 (rad) 64 (rad) 65 (rad)

 

MI=0.85 0.11466 0.25769 0.41205 0.6465 1.0134

 

MI=0.86 0.11465 0.2577 0.41202 0.64646 1.0134

 

 

 

 

 

 

 

 

51

C. The Four Equations

To perform the 5 steps listed above, there are only four equations that need to be

calculated:

Equation 1: to use the equal area criteria, 5k , the junction point of the modulation

waveform and voltage level k must ﬁrst be found. For a modulation waveform with

harmonics contents, it is difﬁcult to ﬁnd a symbolic solution for 5k , but a numeric value

can easily be found by doing simple iterations of the following equation:

'Vdc + 115 sin(55,c ) - - ~ hm sin(m6k)
VF cos(§k)

 

6k = arctg(k ). (3.6)

Equation 2: after 6 k s are found, the switching angle, 6k , can easily be calculated from

6k = ké‘k - (k _1)5k—l + VF (008(5k ) — COS(§k_1)) - §51(COS(5§k ) — COS(5§k_1))

---—&"—(cos(m6k)—cos(m§k_1)), (3~ 7)
m

where m is the order of the harmonic;

Equation 3: with a new set of 6k , the new harmonics contents can be found as

N

2
hm = k=1§mN W (cos(m6k) — cos(m(rr — 6k ))); (3. 8)

52

Equation 4: to perform iterations of step 2)-4) mentioned earlier in this section, the

modulation waveform would have a general expression as:

VF sin(a)t) — h5 _ S sin(5£ot) - - - —hm _ S sin(mwt) , (3. 9)

where hm S is the sum of the hm found after every iteration,

iter

hm_, = zhm. (3.10)

i=1,2,3-«iter

For different numbers of switching angles and eliminated harmonics, the four
equations will remain the same. Since there is no multi-variable polynomial, the
calculation time has a near linear relationship with the number of the switching angles.
No huge increase in calculation time is expected when there is a small change in the

number of the switching angles.
D. Application Issues of Proposed Method

Like all the other switching angle optimizing methods, the proposed method also has
its limitations. Thus, modiﬁcations of the proposed method are needed at certain
modulation index and voltage step combinations. The following part of this section will

discuss the limitations and possible solutions.

1) In equal area criteria method, hi is not totally equal to h] , thus the fundamental

component of the ﬁnal staircase waveform will be slightly different from the

original modulation waveform. This means that try to ﬁnd the switching angles

53

2)

3)

for a modulation index, a different initial modulation index is needed. This
problem can be solved by calculating switching angles at different initial
modulation indexes and using these to form a mapping table between the initial

and desired modulation index.

Directly applying the proposed method will not always guarantee desired
harmonics elimination for all the modulation indexes with all kinds of voltage

steps. This is mainly caused by possible multiple solutions or no solutions of 5k

after harmonics injection. With a pure sinusoidal waveform, at each voltage step,

there is only one solution of 6k. But after the harmonics injection, the

modulation waveform may have more than one junction point at a certain
voltage step, meanwhile, the junction at the highest voltage step may disappear.
In these cases, judgment and corresponding modiﬁcation in the method should

be made.

It is quite difﬁcult to ﬁnd a symbolic solution for 5k , thus the harmonics

elimination is very hard to be qualitatively described. This makes it not very
inconvenient to further modify this method to improve the harmonics
elimination performance at different switching angle numbers and modulation

indexes.

54

3. 4. Summary

In this Chapter, ﬁrst, methods to maintain DC bank voltages at different application
situations were summarized. Then, a universal DC bank voltage balancing method was

introduced. Finally, a practical harmonics elimination method was proposed.

In the applications of multilevel inverter in power systems, there are three conditions
for DC voltage maintenance. In this chapter, the conditions of reactive power
compensation and back-to-back connection were discussed. The voltage regulator used
in DG will be discussed in Chapter 6. For DC bank voltage balance, one universal
method is introduced. The same method was used in the experiments that will be shown

is Chapter 7.

Before the proposed method, the optimized switching angles are always found by
solving high order multi-variable polynomial equation groups, whereas the proposed
method only involves four simple equations. Compared with the existing methods, the

proposed method is much simpler and more practical.

Since the applications of multilevel inverter in power systems and their implemental
issues have been fully reviewed and discussed, from the next chapter, individual

application cases will be discussed.

55

Chapter Four

A NOVEL UPFC WITH CASCADE
MULTILEVEL INVERTER

4. 1. Introduction

The idea of the Uniﬁed Power Flow Controller (UPFC) was ﬁrst proposed by L.
Gyugi in 1992 [65]. By far, the UPFC is the most sophisticated FACTS device. Since its
ﬁrst introduction, many papers about the UPFC have been published in the last decade.
Papers by Gyugi, Sen, Fujita, Keri and many other authors summarize the UPFC’s theory,
modeling, analysis, control, and ﬁeld applications [65-73]. Papers by Fardanesh and
Sanchez examine the possibility of using diode clamped multilevel inverters for the
UPFC [75, 76]. Papers by Wang investigate the multivariable design of a multiple-

functional UPF C [74].

However, till now, almost no paper has ever challenged the UPFC’s back-to-back

circuit conﬁguration. In this Chapter, the functions of the UPFC, as well as its

56

conventional conﬁguration, are brieﬂy described, and then a new circuit conﬁguration is
proposed. Comparisons between the new and conventional conﬁgurations show that the
proposed conﬁguration has several unique features and advantages over the conventional
conﬁguration. As a result, the cascade multilevel inverter can be used in the new
conﬁguration to lower the volume and cost, and at the same time increase the reliability

of the system. Analysis and simulation results are presented.

4. 2. The Conventional UPFC

The UPFC combines the functions of several FACTS devices and is capable of
realizing voltage regulation, series compensation, and phase angle regulation at the same
time, thus realizing simultaneous separate control of active power and reactive power

transmitted over the line. The conventional circuit conﬁguration of the UPFC is shown

in Figure 4.1 [65-74].

As it can be seen, the conventional UPF C conﬁguration consists of two voltage
source inverters. Inverter 1 is in parallel with the transmission line, while Inverter 2 is in
series with the transmission line. The two inverters are connected back-to-back through a
common DC-link. This arrangement enables real power ﬂow in either direction between

the two inverters.

57

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n ............ ..i.i_.w ......... p ....... w ........... I”
go see:

@ ER
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58

 

HUCC‘

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110m
tint
gene]

proxi

than:

lhﬁ rg‘

Md

Between the two inverters, Inverter 2 provides the main ﬁmction of the UPFC by

injecting an AC voltage 17C through a series connected transformer. 17C has controllable

magnitude VC (0 5 VC 5 VC max) and phase angle 6 (0 S 6 S 360° ). Thus, Inverter 2 can

be considered as a synchronous AC voltage source. Because the transmission line current
ﬂows through this voltage source, Inverter 2 needs to exchange active and reactive power
with the transmission line through the transformer. The needed reactive power can be
generated independently by Inverter 2 itself. The active power exchange is actually

provided through the common DC link.

Thus, the basic function of the Inverter 1 is to supply or absorb the real power
demanded by Inverter 2 at the common DC link. Besides this, Inverter 1 also can

generate or absorb reactive power independently.

Figure 4.2 is a vector diagram of Figure 4.1, illustrating the principle of the UPFC.

When 17C is added to the system, the equivalent sending end voltage changes from 1750

to I75 , the angle difference between the sending end and the receiving end voltages

changes from (9 to 6', the active and reactive power transmitted from the sending end to

the receiving end over a transmission line changes from

P: VSOVR 81116 (41)
X
and Q ___ __ (VR 6036 — V30 )Vso (4. 2)

 

X

59

' _ VSVR sin 0'
X

to P (4. 3)

and Q. :_(VR cosi—VSWS'

 

(4. 4)

 

 

Figure 4.2: Basic UPFC control function.

where V50 is the amplitude of I750 , V5 is the amplitude of I7 S , VR is the amplitude of

VR, and X is the line impedance. The equations show power transmitted over the

transmission line can be modiﬁed to the desired value by controlling the injected voltage,

—‘

VC.
To summarize, the features of the conventional conﬁguration are:

1) Both inverters share the same DC link;

2) Both inverters need to exchange active power with each other and the

transmission line;

60

3) A transformer is usually used as an interface between the transmission line and

each inverter.

4. 3. Two Problems of the Conventional Conﬁguration

4. 3. 1. Zigzag Transformer

In the real applications of FACTS devices like the UPFC and the STATCOM, multi-
pulse inverters with zigzag transformer were often used to substitute for the inverters as
shown in Figure 4.1. The multi-pulse inverter is formed by back-to-back connecting
several three phase inverters, and then cascading the AC outputs at secondary sides of the

zigzag transformer. One 48 pulse inverter with zigzag transformer is shown in Figure 4.3.

In the multi-pulse inverter, each three phase inverter cell is controlled to output the
same three level line-line voltages. The switches in the inverters turn on and off only

once per fundamental cycle. Thus, the switching losses of the devices are minimized.

The zigzag transformer will realize the phase shifting and output cascading. The
purpose of the phase shifting is to optimize harmonics content. The primary sides of the
zigzag transformer are delta-connected to eliminate 3rd harmonics. The phase shifting of
each secondary side for the 48 pulse inverter is 75°. The total output of the multi-pulse
inverter with zigzag transformer will resemble the waveform of multilevel inverters. The

phase voltage of the 48 pulse inverter has a maximum of 23 voltage levels.

61

)H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

\— L. l— L. L. l_ 1— l_ l_ L. L. L— l._ L_ l—
|_ L— \_ L. l— L. L L l— |_ L. l— L— L—

 

 

 

 

 

 

 

Figure 4.3: The 48 pulse inverter.

62

By utilizing the zigzag transformer, the harmonics and switching loss are both limited.
However, the zigzag transformer also brings many problems to the multi-pulse
transformer. The disadvantages of using the zigzag transformer are summarized as

following:

1) Unlike switching devices, zigzag transformers are always custom-made.
Compared with regular transformer, the cost of zigzag transformer is much higher.

In the multi-pulse system, zigzag transformer is the most expensive part.

2) Zigzag transformers are usually very bulky. The transformer itself alone would

make up more than half of the volume of a FACTS device.

3) The power loss on the zigzag transformer would contributes more than half of the
total power loss. For a 40 MVA, 48 pulse inverter, the power loss on the

transformer is around 1.2%, which is twice of the power losses on the switches

[85].

4) The operation and maintenance of the zigzag transformer is very crucial, which

will strongly affect the reliability of the multi-pulse inverter.

Furthermore, compared with multilevel inverters with the same amount output
voltage levels, researches Show that the multi-pulse inverter would have higher cost,
higher volume, higher power loss and higher THD in the output voltage [36-40, 85].
Thus, in the future practices of FACTS devices, multilevel inverters will be the major

circuit candidates.

63

635

bar
are
fun
p.111

C00

4. 3. 2. The Problem with Cascade Multilevel Inverter

Among the three major types of multilevel inverters, the cascade multilevel inverter is
the one most suitable for most FACTS applications. The reason for this is that the H-
bridge in the cascade multilevel inverter can be modularized, which would make it much

easier for manufacture and maintenance.

But unfortunately, the cascade multilevel inverter can not be used for the back-to-
back conﬁguration of conventional UPFC structure. If two cascade multilevel inverters
are back-to-back connected as shown in Figure 4.4, short connections of DC banks will
form during certain operation states. In Figure 4.4, the dashed line Shows one current
path that indeed shorts the upper capacitor. When the shadowed parts in the inverters

conduct at the same time, the upper capacitor will be shorted.

42s a
.V ..... —._)_,‘

 

 

 

A
‘t
ul ‘1‘

 

 

     
 

 

 

 

 

 

 

 

 

 

 

 

Figure 4.4: The short connection when cascade multilevel inverters are connected back-

to-back.

64

4. l.

4. 4.

 

4. 4.The Proposed Configuration

4. 4. l. The Proposed Configuration

In an attempt to eliminate the zigzag transformer and utilize the cascade multilevel
inverter in the UPFC, a new UPFC circuit conﬁguration as shown in Figure 4.5 is

proposed. In the proposed conﬁguration,

1) each inverter has its own DC bank, thus cascade multilevel inverters can be

used in place of Inverter 1 and Inverter2;

2) since cascade multilevel inverters can be utilized, the zigzag transformer is no

longer needed in the proposed conﬁguration;

3) there would be no active power exchange between the two inverters and the

line because the two inverters use separated DC banks;

4) unlike the conventional back-to—back DC link coupling, the two inverters are

coupled face-to-face on the AC sides instead.

Like in the conventional conﬁguration, Inverter 2 in the new conﬁguration is still
controlled to generate the desired [Q to control the active and reactive power ﬂow, thus

acting as a controlled voltage source.

Inverter l, the parallel inverter, rather than supplying or absorbing active power for
Inverter 2, injects a current to the line to guarantee that active power ﬂowing into both of

the inverters be zero.

While cascade multilevel inverters can be used for this circuit configuration, the

Zigzag transformers are no longer needed. However, for Inverter 2, a connection

65

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66

transformer is still needed to connect the inverter to the utility line. Compared with the

zigzag transformer, the connection transformer is much cheaper, much smaller, and more

reliable.

The proposed conﬁguration utilizing cascade multilevel inverters is shown in Figure

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4. 6.
17% I “C IVS I7R
mm X
C1 :11: "“ _’I‘ 01
i $339393 Cascade i
J:‘ ”V9 er Invener
C5 L —-L C5
Inverter 1 Inverter 2
Figure 4.6: The proposed UPF C with cascaded multilevel inverter.

4. 4. 2. Control Strategy

Figure 4.7 is the equivalent circuit of the proposed conﬁguration. When Inverter 2 is

controlled to output the desired compensation voltage, 17C , the voltage drop on Inverter 1
would automatically be I750 —I7C. To ensure zero active power ﬂow through both

inverters, Inverter 2 current, 7C , and Inverter 1 current, (TC -7 ), should be

67

perpendicular to their voltage drops, 17C and (1750 - 17C ), respectively, where I is the
receiving end line current.
In summary, the control command for Inverter 2 is the desired compensation voltage,

17C , While the control command for Inverter 1 is TC —7 . 17C can easily be calculated

according to the power demand of the system. After I7C is given, the desired 7C — i can

be found by the following analysis:

 

 

 

 

r7509 ,__ 11 92$

 

 

 

 

Figure 4.7: The equivalent circuit of UPFC.

To ensure that the active power ﬂowing into Inverter 2 is zero, given that the phase

angle 0f the 17C iS (5' , the phase angle of 7C should be

ziC = 5i900, (4. 5)

68

 

I
1"
”

 

Figure 4.8: The relationship between VC and TC .

Based on the analysis above and Figure 4.5, the equation of the active power ﬂowing

into Inverter 1 can be written as

1’1 =(I750—VC)°(7C—7)

= VSOIC cos(6 :t 90°) + VCI cos(6 — 62) — V501 cos 62 = 0. (4. 6)

From equation (4. 6), the amplitude of TC could be found to be:

__ V501 cos (92 - VCI cos(5 — 62)

 

1C O (4. 7)
V30 cos(6 i 90 )
Combine equation (4. 5) and (4. 7), we have
7C=VSOIcosaz-VCICOS(6_62)4§i900. (4.8)

 

V50 cos(5 i 900)

69

In equation (4. 8), V50, 1 , and 62 can be measured with sensors; VC and 6 are pre-
calculated. Since I is measured with sensors, after 7C is decided, the control command

of Inverter 1, (IC - I ), is also decided.

4. 5. Comparison of the New and Conventional Conﬁgurations

The proposed conﬁguration of the UPFC has several advantages over the

conventional one:

1) In the conventional conﬁguration, there is active power exchange between the two
inverters, whereas in the new conﬁguration there is no active power exchange
between the two inverters and both inverters only provide (or absorb) reactive

power;

2) Cascade Multilevel Inverter can be used to eliminate the zigzag transformers,
which reduces power losses, cost, and volume, and increases reliability of the

system;

3) The modular structure of cascade multilevel inverters and its inherent redundancy

provide greater ﬂexibility to system design and maintenance;

4) The total VA rating of the UPFC can be greatly reduced under most load

conditions, which will be veriﬁed in the following section.
4. 6. VA Rating Analysis
For the conventional UPFC, the VA rating for Inverter 1 and Inverter 2 are:

70

 

5,0 = \/(VC -1cos(2 17C — 2i»2 + (V501,)2 ,and $20 = VCI, (4. 9)

where Iq is the reactive current that Inverter 1 generates for reactive power

compensation. In the equation, VC ~1cos(ZI7C—ZI) is the real power required by

Inverter 2. Therefore, the total VA rating of the conventional UPF C conﬁguration is

 

so = $10 + $20 = Jo/C -1cos(z 17C — 21))2 +(V501q)2 + VCI. (4. 10)

For the proposed UPFC, the VA rating for Inverter 1 and Inverter 2 are:
SW=|r750—17C|.|iC—i+iq|,and SZN=VCIC. (4.11)
Thus the total VA rating of the new UPFC conﬁguration is
SN =VC-1C+|VSO—VC|.|iC—i+iq|. _ (4.12)

Figure 4.9 and 4.10 Show the ratio of the total VA rating between the new and

conventional conﬁguration, S N /SO.

According to equation (4. 7) and (4. 12), in the new conﬁguration, when 6 is exactly
at 0 ° and 360° , the Inverter 2 current and total system VA rating would become inﬁnite.
This means that the new conﬁguration is not suitable for 6 very close to 0°. Further
calculations show that when 6 changes from 06° to 359.4°, the Inverter 2 current and

system VA rating will be in an acceptable region.

71

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(b) VC = 0.5p.u. and Iq = 0.25 p.u.

72

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- —0.25 p.u.

(c) VC = 0.5p.u. and Iq
Frgure 4 9 The ﬁrll vrew of total VA rating between the new and conventional

conﬁguration.

 

(3) VC = 0.5 p.u. and 1(1 = Op.u

73

 

 

1‘1 'I'I
1 ”unﬁl‘luluflfll

l

 

(0) VC = 0.5 p.u. and Iq = -0.25 p.u.
Figure 4.10: The ratio of total VA rating between the new and conventional UPFC

conﬁguration.

74

Thus, in Figure 4.9 and 4.10, calculation results of SN /SO at —45° $19 30° and

06° S 6 S 359.4° are shown. Figure 4.9 is the full view of the plot. Figure 4.10 shows
operating areas where the VA rating can be greatly reduced with the proposed
conﬁguration. Normalized voltages, currents and impedance are used in all the

calculations. The transmission line impedance, X , is ﬁxed as 0.1 p.u.

Figure 4.11 shows the 0—6 plan projects of the points in Figure 4.9. The shaded

areas in the plots are the areas in which the VA rating ratio, S N / SO , is smaller than 1

whereas the blank areas represent the areas with the VA rating ratio greater than 1. In all
the ﬁgures, the shaded areas are much larger than the blank areas. And the major blank
areas are all almost in near the center of each ﬁgure. Figure 4.9 to Figure 4.11 can be

explained and further explored by the following illustrations:
Illustrations 1:where and why some points has VA rating ratio greater than 1

In the center area of Figure 4.11, as 6 moves to the center (180°) from both directions,

17C begins to point towards the origin of I750. This is shown as an example in Figure 4.
12. As a result, '1750 —— 17C! , the amplitude of the voltage of the Inverter 1 in the proposed

conﬁguration, becomes larger whereas the amplitude of the new sending end voltage, VS,

in both configurations, become smaller. When 6 becomes 180°, they attain

75

 

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Iq =0p.u.

0.5 p.u. and

(a) VG =

 

 

.U.

and [q = 0.25p

= 0.5 p.u.

(1)) VC

76

 

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EEEIEE

 

—0.25 p.u.

q:

= 0.5 p.u. and I

(C) VC

Figure 4.11

The 19 — 6 'projects of the Figure 4. 9.

 

iagram of the system

: The vector d

Figure 4.12

.13. From equation (4. 1),

4

1gure

tively as shown in F

immum respec

dm

11‘ max1mum an

the

rtional to V5, and affected by the

and (4. 2), it is known, the transferred power is propo

angle difference between the sending end and receiving end voltage. One example of

77

transferred power and receiving end line current at the condition that (9 = —45° and

06° 5 6 S 359.4° are shown in Figure 4.14.

 

Inverter 1
7 Voltage
p.u.

 

 

 

 

i ‘ Sending

: End

Voltage
p.u.

 

 

 

 

Figure 4.13: The relationship between inverter voltages and 6 .

By comparing Figure 4.13 and Figure 4.14, it can be concluded that the areas that the
VA rating ratio is greater than 1 in Figure 4. 11 (the blank areas) are also the areas in
which the smallest power is transferred. And in this area, Inverter 1 in the new

conﬁguration will have a higher total voltage stress than in other areas, whereas the

receiving end line current is smaller. Thus S N / S0 becomes greater than 1 in the center

blank area.
According to calculation results, the major reason for the blank area around 350° is
the large amplitude of the Inverter 2 current at some compensation conditions.

Furthermore, the purpose of a UPFC is to transmit more power without compromising

stability. Therefore, the blank areas are normally not operating regions of the UPFC.

78

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 .......... . ...... --------- --------- f ---------- -------- , """ g“: Reactive
. . . - - - ' Power
p.u.

: : System
5 Current
: : p.u.

0 1 I 1 1 l l l

o 50 100 1511 200 250 300 360

Figure 4.14: The active power, reactive power and receiving end line current when

6? = 45° and 6 changes from 0° to 360°.

Illustrations 2: the total P-Q pairs covered by the shaded area

After Illustration 1, another remain question is whether the full function of the UPFC

can be achieved within the Shaded area in Figure 4.11. This question can be answered by

the P-Q plot.

In the papers dealing with the UPF C, the P-Q plot is often used to Show the function
of the UPFC by showing the basic controllable pairs of active and reactive power (where

Iq = 0) by plotting the reactive power, Q, versus active power, P. Figure 4.15 is an

example of this.

79

 

 

 

 

 

 

 

 

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. 4.4144454»
0-3 r + + 1’ 7' +151. .
+ *1.»
4- +
t 1
o 13 + 1' +4
D- + $ -
4* +
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(p-U-) at +
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0.2 ” 4* +* .1
+ 4.»
I 4*
0.. + .1. *1 1
i +
3'» t 4’ +
10 2 ~ *4 41- 1' »-
' *+++4++ 1’
.0-4 1 l l 1 1 l
-0.2 0 0.2 0.4 0.6 0.8 1 1.2
P (p.u.)
(a) all the P-Q pairs
1 I V j I I T
++++++
0'8 ' + +4”? '1
4 +-
t 1‘
§ '0‘ 2
06 ~ + + + .
+ .2:
Q 1.- 1* *1
- * ‘1
(p.u.) ,1 +
+ +
4-
0.2 " 4* .9. ..
+ 1+
+ 3
+
0 E 1. *
02’ -
_04 i l l 1 l 1
~02 U 0.2 0 4 0 6 0.8- 1 1 2
P (p.u.)

(b) P-Q pairs at which the VA rating ratio is smaller than 1

Figure 4.15: The P-Q pairs when 6 = ~25°, VC = 0.5 p.u. and 6 rotates from 0° to 360°.

80

Figure 4.15(a) shows all the basic P-Q pairs when 6 = —25°, VC =0.5 p.u. and 6

rotates from 0° to 360°. Figure 4.15(b) shows only the basic pairs that have a VA rating
ratio smaller than 1 at the same condition. Comparing Figure 4.15(a) and (b), some
portion of the P—Q plot in Figure 4.15(a) is missing in Figure 4.15(b). So if all the P-Q
plots at different 6 are put into one ﬁgure, it will be easy to ﬁgure out the total missing
P-Q pairs. Figure 4.16(a) shows the plots of all the basic P-Q pairs that the UPFC can
achieve when 0 changes from 0° to -45°. Figure 4.16(b) shows the plots of the basic P-

Q pairs that have VA rating ratio less than 1 under this condition.

 

0.8 ~

(Fl-LL) 0.4 -

 

 

 

I I l I

l I
$0.6 04 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4

 

_04 i I 1

P (p.u.)

(a) all the P-Q pairs

81

 

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(b) P-Q pairs at which the VA rating ratio is smaller than 1

Figure 4.16: The P-Q pairs when 0 changes 0°to -45°, VC = 0.5 p.u. and 6 rotates from

06° to 359.4°.

The following conclusion can be drawn from Figure 4.16:

1) The operating area with VA rating ratio smaller than 1 (shaded areas in Figure

4.11(a)) covers almost all the basic P—Q pairs that the UPFC can achieve;

2) The pairs not covered are those that have both smallest active and reactive powers,

which usually are not in the operating area of the UPFC;

So it can be concluded that within the shaded area in Figure 4.11(a), the basic

functions of the UPFC can be fully realized.

82

Illustrations 3: the VA rating optimization

Another interesting phenomenon that found from the VA rating analysis is that the

VA rating of the system can be optimized in some load conditions.

In Figure 4.9, different points may yield the same power transmitted. In other words,
if a required active and reactive power is given, different operating points that transfer the
same desired power can be found, and the operating point with the smallest total VA
rating ratio can be chosen from these points, which means the VA rating of the system

can be optimized.

Figure 4.17 shows the operating points that have the same power transfer but different
VA rating ratios. The ‘ * ’ points in Figure 4.17 are points extracted from Figure 4.9. At
these points, the transferred active and reactive powers are almost the same. Thus the

point that has the smallest VA ratio can be selected to minimize the UPFC’ VA rating.

 

 

b
"a i
c
‘-
.

' / 300
200

 

 

100

 

(a) VC = 0.5 p.u. and 1,, = 0 p.u.

0.99 p. u. <P <1.01p.u. and 1.12 p. u. <Q <l.14p.u.

83

."
,.' .
.

..-
..»
.

 

 

 

400

 

(b) VC = 0.5p.u. and Iq = 0.25 p.u
0.99 p. u. <P <l.01p.u. and 0.83 p. u. <Q <0.85 p.u.

Figure 4.17: Operating points that have the same power but different VA rating ratio.

4. 7. Simulation Results

Simulations of the proposed and conventional conﬁgurations have been carried out.
In the simulations, the system voltage is 1 pu constant. To make good verify of the
analysis performed above, the transmission line impedance is ﬁxed at 0.1 pu. Simulation
results of the points in Figure 4.17(a) are summarized in Table 4.1. In Table 4.1, P and

Q are the power transmitted with the UPFC; S N / SO is the ratio of the total VA rating

between the new and conventional conﬁguration.
Figure 4.18 shows the simulation waveforms of the proposed conﬁguration at the
Operation point A (6 210° and t9 = —38.750 ). i is the receiving end current; Q is the

Inverter 2 current; 7C — i is the Inverter 1 current. In the simulation results, the Inverter

84

2 current is much smaller than the load current, 7 , which is the reason that the total VA
rating of the proposed conﬁguration is much smaller than the VA rating of the
conventional conﬁguration. The simulation results agree with the analytical results
obtained in the previous section and clearly show that the new UPFC is feasible and

advantageous over the conventional UPFC in terms of required VA rating.

Table 4.1: Part of the simulation results of the new conﬁguration

 

A B C D E F

 

5 (Deg) 10 5 5 360 355 355

 

6(Deg.) -38.75 -40 -40.625 -41.875 -43.125 -43.75

 

P (p.u.) 1.002 0.996 1.009 1.001 0.992 1.004

 

Q(p.U) 1.125 1.127 1.138 1.133 1.123 1.134

 

SN/So 0.42478 0.43604 0.43523 4.3776 4.3445 4.3488

 

 

 

 

 

 

 

 

 

 

-100 ~-

 

 

 

 

 

5: 10°, VC = 0.5 p.u., a: —38.75°,and Iq :0

Figure 4.18: Currents through both inverts and the line in the new conﬁguration.

85

4. 8. Summary

In this chapter, a new conﬁguration of the UPFC has been proposed, which provides a
feasible alternative to the conventional UPF C. The operation, analysis, and features of
the new conﬁguration were illustrated. Simulation results were shown to verify the

operation and control principle.

It is shown that the functions of UPF C can be fully realized with optimized system
VA rating. Thanks to the proposed face-to-face structure, the cascade multilevel
inverters can ﬁnally be used in the UPFC application. As a result, the four major
advantages of the new conﬁguration of the UPFC, as stated at beginning of session 4.5,

make the proposed circuit conﬁguration very promising for new designs of UPFC.

This chapter proposed a cascade multilevel inverter solution for the most complicated
FACTS device: UPFC. In the next chapter, another cascade multilevel inverter solution

for the most widely used modern FACTS device — STATCOM will be proposed.

86

Chapter Five

DELTA-CONNECTED UNIVERSAL
STATCOM

5. 1. Introduction

Power system compensation and conditioning has been a long existing problem.
Compensation with power electronics devices ﬁrst appeared in the later 19708. At that
time, thyristor controlled reactor or capacitor based Static VAR Compensator (SVC)
were used in the power system to compensate reactive power. Since then, more than
1000 SVCS have been installed worldwide. In the last decade, the VSI based Static
Synchronous Compensator (STATCOM) began to take over the place of the thyristor
based SVCS. Compared with the traditional SVCS, the STATCOM has better dynamic
response, larger compensation range and less dependence on the system voltage [43]. It
mainly provides reactive power compensation, voltage regulation, harmonics

compensation and system stability improvements.

87

By far, Static the STATCOM is the most widely installed modern FACTS device.
Several STATCOMS with a power rating at the mega watt level have already been
installed in real power systems [77-80, 86]. And with the urgent demand of system
compensation in both transmission and distribution systems, the STATCOM now

receives more and more research attention each year.

In this Chapter, a new delta-connected cascade multilevel inverter STATCOM is
proposed. Unlike the conventional STATCOMS, the proposed STATCOM circuit not
only can be used to compensate reactive power and harmonics, but also can be used to

compensate negative sequence current caused by load imbalanced. Thus it is named as

the Universal STATCOM (U-STATCOM).

5. 2. The Circuit Candidates of STATCOM

Multi-pulse inverters and multilevel inverters are the major circuits used in
STATCOMS [77-80]. Full comparisons between these two circuits have already been
performed [85]. The ﬁrst generation STATCOMS were all built with multi-pulse inverter

circuits.

In 1995, the cascade multilevel inverter was introduced to be an alternative circuit of
the STATCOM [38]. Then lots of researches have been done towards the cascade
multilevel inverter STATCOM. In year 2000, a 75 MVASTATCOM with cascade
multilevel inverter structure has been installed in the power systems in U. K [86, 87].
Compared with the multi-pulse inverter STATCOMS, no zigzag transformer is needed in

the cascade multi-level inverter STATCOM. The cost, volume and power loss are

88

greatly reduced. The control also becomes quite simpliﬁed. Since year 1995, the

cascade multilevel inverter has become the trend in the application of STATCOM.

Recently, most researches have been focused on the STATCOM with three-phase
wye-connected cascade multilevel inverter. Figure 4.1 shows its system conﬁguration.

The three-phase wye-connected cascade multilevel inverter is connected to the utility line

through the inductor La, b, C . The cascade inverter’s output voltage v: b c is controlled to

be fundamentally in phase with the system voltage Vas,bs,cs- Then the reactive power

produced or absorbed by the STATCOM is decided by the following equation:

 

 

 

 

 

 

 

VC —- Vas
= a. . __ V , (5. I
Q XL as )
Vas
V [15‘ 7
Va. 4
La Lb Lc
C C C
Va Cascade Vb Cascade VC Cascade
Multilevel Multilevel Multilevel
Inverter Inverter Inverter
Phase a Phase b Phase c

 

 

 

Figure 5.1: The system conﬁguration of wye connected STATCOM.

 

 

 

1E

 

 

 

where X L is the impedance of the inductor L0,)”. Ideally, there will be no real power

exchange between the inverter and the utility line. The DC capacitors in the inverter will

sustain the desired voltage.

However, in most cases, the power system will have an unbalance load. At
unbalanced conditions, the wye connected cascade multilevel inverter still can be used to
compensate reactive power. But it cannot be used to correct the imbalance of the system

currents. To explain this, one simple example is shown in Figure 5.2.

 

 

4..

Figure 5.2: The imbalance compensation with wye structure.

To compensate the imbalance current shown in Figure 5.2, the STATCOM with wye

structure would be controlled to output a compensation current, iac, which is in phase

with the inverter output voltage, vac. Thus, there must be real power exchange between

the inverter and the utility line. And the real power exchanges will overcharge or
discharge the DC capacitors in the inverter. This is against the basic operating principle

of the STATCOM.

90

For general imbalance compensation with wye structure, if there was imbalance in the
active component of the line current, there would be active power exchange between the

inverter and utility line.

To overcome this problem, this paper proposes a U-STATCOM with a delta-

connected cascade multilevel inverter.

5. 3. The Proposed U-STATCOM

5. 3. 1. Proposed U-STATCOM

Figure 5.3 shows the U-STATCOM circuit structure and one line-line voltage
waveform. Each phase leg of the STATCOM will have several full bridge inverter
modules and one output inductor. The inverter module can be either a two-level H-
bridge or three-level H-bridge depending on application requirement. The three phase
legs of the inverter are connected to each other head to tail by the output inductor, L.

Then the whole cascade multilevel inverter becomes delta-connected to the utility lines.

To illustrate the function of the U-STATCOM, the fundamental compensation theory

will ﬁrst be introduced.
5. 3. 2. The compensation theory [91]

With balanced three-phase voltage, an ungrounded three-phase load can always be

represented by a delta-connected network as shown in Figure 5.4(a) [91]. The load

91

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92

- I I - I I I . 1 I I . l
admlttances Yab = Gab +jBab, ch = Gbc +ijC and Yca =Gca +1800 can be complex
and unequal. It has been proven that just one delta-connected pure reactive network is
needed to fully compensate the reactive power and system unbalance as shown in Figure
5. 4(b). The pure reactive compensation network is deﬁned by:
I . .
.53 = 1sz = 1<—Bf,, + Gé. —G,’,, M3")

. . l
< 11;. =18}; =J<—B,’,, + 01,, —G... N3). (5. 2)
pig, = nga = j(—B§,, + of” —G’b N?)

a

 

 

 

 

 

 

 

 

a. Uncompensated b. Balanced load c. Equivalent Y
unbalanced load after compensation connection

Figure 5.4: The general three-phase compensationnetwork.

After compensation, the equivalent wye-connected system is totally resistive and

balanced as shown in Figure 5.4(c). The equivalent phase admittance, G, is equal to

I I l
Gab+Gbc+GC0'

93

To realize the active compensation based on this compensation theory, the admittance

Yr

ab,bc,ca

can be substituted by the U-STATCOM shown in Figure 5.3. The only criteria

for this substitution is that the cascade inverter output voltage, vgb bc ca , should be

controlled to keep the current on the inductor L (seen in Figure 4.3) equal to the current

onYr

a b, b C, C a . This guarantees the following two things:

1) full compensation of reactive power and load imbalance;

2) no real power ﬂows through the inverter.

5. 4. Control Scheme and Reference Current Detection

A. System Control Scheme

To realize compensation for both the reactive power and load current imbalance,

C

ab bc ca, should be controlled to be in phase with

ideally the inverter output voltages, v

C

The current output of the inverter, iab,bc,ca’

the utility line-line voltages, vab,bc,ca'

should always be 90° lagging or leading the inverter voltage to produce or absorb the
needed reactive power. However, the inverter will always consume a small amount of
active power because of the power losses on the switches and capacitors. So in the real

C

ab be M , will have a very small lag angle

control, the inverter control reference, v

difference, aab,bc,ca << 06° [36], from the utility line-line voltages. By introducing this

small lagging angle to the voltage command, the resulted output voltage of STATCOM

94

will have a phase difference from the grid voltage. Thus, real power will ﬂow into the
STATCOM to charge the DC capacitor..

Figure 5.5 shows the control diagram of reactive power and load current imbalance
compensation. The total control is a combination of the output voltage control and the

DC voltage control.

In the output voltage control loop, a reference current, 12b,bc,ca’ is ﬁrst calculated

based on the sensed load currents and system voltages. This reference current will

guarantee both the reactive power and load current imbalance and compensation. Then
. . C4- .
the amplitude of inverter output voltage, Vab,bc,ca’ is calculated based on the current

reference.

For var and harmonics compensation, the method to keep the capacitors in different
inverter modules equally charged or discharged has been discussed in Chapter 3. By
properly rotating the voltage levels produced by each module, the DC voltages on each
capacitor will always be kept same. So for the DC voltage control, it is only necessary to
sense one capacitor voltage per phase. The sensed voltage is compared with a reference
voltage, V56. Then a PI controller is employed to calculate a small lagging angles,
aab,bc,ca'

The ﬁnal voltage command of the inverter, vggbcma’ is synthesized from 196ng ,

aab,bc,ca and the system line-line voltage phase angles, Bahama, which are obtained

from phase lock loops.

B. Reference Current Detection Method

95

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96

From the Figure 5.5, it can be seen that, the whole control strategy is built based on

. . 4

the correct detection of the reference current amplitude, 10b1,“, To calculate the
.1. . . .

Iab,bc,ca , the most direct method 1S to ﬁgure out the compensating susceptances,

Br

ab b C ca , and the input voltage’s amplitude, V .

r
ab,bc,ca '

There are several methods to get the value of compensating susceptances, B
The conventional way is to express the susceptances in terms of instantaneous currents

and voltages [91].

r
ab,bc,ca

It is proved that B can be calculated by

r 1
l13gb = —3—V—[1m(1a)+1m(1b)—Im(1c)l

, 1
4 Bbc = —3—V[Im(1b)+1m(IC)—1m(1a)] , (5. 3)

r 1
13,, = —§/—[Im(lc ) + Im(Ia) — 1m(1,, )]

 

l

where Im(Ia,b,c)are the imaginary parts of the phasors of the load current. Because

J2 Im I a, he is the maximum value of reactive current, which appears when the phase

voltage is zero, so there is

i ,b, (I)
Im(la,b,c) : ill/€— Va,b,c(’)=0

dira,b,C(I)/dt>0

(5- 4)

97

The zero crossing of the voltages, current amplitude at that time and the voltage

amplitude, V , can be detected with sensors. By substituting equation (5. 4) into equation

(5. 3), B 2 b be ca is then expressed in the terms of the instantaneous currents and voltages

as the following

r

1 . . .
Bab=-'37§—I; 1.20) va(t)=0 +1150) vb(t)=0 _lc(t) vc(t)=O

dva(t)/dt>0 dvb(t)/dt>0 dvc(t)/dt>0_
r 1 . . .
]Bbc =“73—E‘l; 1150) 11b(1)=0 “cm vC(t)=0 —la(l) va(t)=0 . (5. 5)
L dvb(t)/dt>0 dvc(t)/dt>0 dva(t)/dt>0_

r

l . . .
Bea - 773-17 ICU) vC(t)=O + 151(1) va(t):0 ”1150) 11,,(1)=0
[ dvc(t)/dt>0 dva(t)/dt>0 dvb(t)/dt>0_

h—

 

 

 

 

 

 

:11
After the V and B;b,bc,ca are known, the reference current I ab,bc,ca can be found

out with case.

5.4. Simulation Results

The major functional difference between the U-STATCOM and conventional
STATCOM is the compensation of load current imbalance. Simulation of the

compensation of unbalanced load current with U-STATCOM as shown in Figure 5.3 is

presented.

98

In the simulation, the system line-line voltage is 60 Hz, 13 kV. The unbalanced load

is described by Y C: b =Yblc=0.02 S and Ycla =0 S. In this case, the compensation

susceptances are

 

1
.3’ =-——————
“b 50\ﬁ§
1r- , . (5.6)
be 5005
850:0
L

The amplitudes of the reference currents are 1;}, =Igc—I—i’b— , and [:0 =0. The

50¢?

phase angles of the references are — 90° , -30 ° and 0° respectively.

Figure 5.6 shows the uncompensated three-phase current. Figure 5.7 shows the

compensated three-phase system currents, inverter voltages and currents.

 

1000.0 I

 

 

 

 

 

4000.0? 1 i 1 1 I 1
0.17 0.175 0.18 0.185 0.19 0.195 0.2

t(s)

 

Figure 5.6: The uncompensated system current.

It can be seen that, after compensation, the system three-phase current becomes

balanced. The goal of compensation is achieved. There is almost a 90° ’3 difference

99

between the inverter fundamental voltages and currents, which means there is almost no
real power ﬂow between the inverter and the system. There are third harmonic
components present in the inverter currents. This is because the staircase inverter voltage
is optimized to minimize the 5th, 7"“, and 11th harmonics. The 3lrd harmonic does not
affect the total compensation result. The simulation result veriﬁes the circuit structure

and control scheme of the U-STATCOM.

 

 

 

 

 

 

500.0”

33 0.0:

-500.0

400.0“ 20000.0]

A2000“

A

33 0.0: :3 0.0:

-2000: .

-4000 - 20000.0.

 

800.0 I 20000.0]

400.0:
2 0.0: > 0.01
V V

-4000:

 

4300-0“ -20000.0‘
400.0 ‘ 20000.0]

 

 

A2000:
3 0.01 a 0.0-
-2000 -

 

 

 

 

 

 

-4000- 20000.01, i i i 1
0.52 0.53 0.54 0.55 0.56

t(S)

Figure 5.7: The compensated system current and inverter voltages and currents.

100

5. 5. Summary

STATCOM is the most popular modern FACTS device. Researches have shown that
cascade multilevel inverter is the best circuit choice for the next generation of
STATCOM. A 75 MVA STATCOM based on cascade multilevel inverter has been built
and installed in the year 2000. However, till now, the cascade multilevel inverter based
STATCOMS all utilize three phase wye-connection. With wye-connection, in terms of

compensation varieties, only limited compensation can be realized.

In this chapter, the U-STATCOM was proposed to realize universal compensation of
the power system. Other than reactive power and harmonics, the proposed U-STATCOM
can also compensate the negative sequence current caused by unbalanced loads. The
circuit structure and the basic compensation theory were introduced. The control strategy
and compensation component detection method were shown. Simulation results of load

current imbalance compensation with proposed U-STATCOM was presented.

Chapter 4 and 5 proposed applications of cascade multilevel inverters in FACTS
devices for the transmission systems. In the next chapter, extended applications of

cascade multilevel inverter in the distribution systems will be introduced.

101

Chapter Six

EXTENDED APPLICATIONS OF

MULTILEVEL INVERTERS

6. 1. Introduction

Chapter 4 and 5 mainly deal with the applications of multilevel inverters in
transmission systems. While in this chapter, extended applications of multilevel inverters
in other levels of power systems are presented. For Custom Power, one DVR circuit with
an uneven cascade multilevel structure is proposed. For DG, the DC voltage regulator for

cascade multilevel inverters is fully discussed.
6. 2. DVR Circuits

Among all the power quality problems, voltage sag is the number one cause of

equipment failure and other economic damages in the distribution system. Thus, the

102

Dynamic Voltage Restorer (DVR) has become the most researched Custom Power device.
In the early papers of the DVR [116-119], the theory and operating principle of the DVR
is well described. The design of circuit parameters were summarized [120]. Field
experiences of the DVR have been often reported [117, 122, 124]. Cascade multilevel
inverter was ﬁrst proposed as a circuit topology for the DVR by Peng’s paper [36, 37].
The utilization of the cascade multilevel inverter eliminates the line frequency
transformer in the old circuits, thus reduces the cost and volume. In 2003, a cascade
multilevel inverter DVR was built and reported [115]. But widespread application of the

cascade multilevel inverter in the DVR is also constrained by the need of separated DC

SOUTCCS.

As shown in Figure 2.9, the most common DVR circuit topology is one VSI
connected in series with the grid through a line transformer. The DC bank of the VSI can
be either powered from the grid through a rectiﬁer or a backup DC source such as battery
packs and fuel cells. The line transformer in the DVR system is the efﬁciency killer. It
also makes the system bulky and expansive. That is the reason that the cascade

multilevel inverter was introduced. Figure 6.1 shows the one structure of DVR that

utilizes the cascade multilevel inverter.

T‘l ._ _f—I _ l' l .

ac input 1:3 {31 1:};
H-bridge H-bridge H-bridge

T - L, 1 1
DC DC DC
Sourc_e__ Source Source

Figure 6.1: The cascade multilevel inverter based DVR.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

103

The transformer is no longer needed in this structure. But the separated dc bank
either need isolated DC regulator or multiple separated DC source to supply the power.

The need of separated DC sources really becomes a bottleneck of the application of the

cascade multilevel inverter in the DVR.

6. 3. Proposed DVR Circuit.

The proposed DVR circuit is shown in Figure 6.2. Inverter 1 is a bulky power
inverter. Voltage compensation is realized solely by Inverter 1. Inverter 2 is a smaller

sized inverter whose dc bus voltage is only 1/3 Inverter 1. The major job of inverter 2 is

to compensate the harmonics produced by Inverter 1. Thus, Inverter 2 can also be called

as a conditioning inverter.

6. 3. l. The Theory of Two Non-identical Inverter in Cascade

In the proposed circuit, two inverters with different dc bus voltages are cascade
connected. Similar circuit topology for an open winging motor has been proposed in one
of author’s paper [31]. The difference is that in the paper [31], two three level diode

clamped inverters are cascaded. Since the H-bridge inverter also has three-level output,

the mathematic essences behind the two circuits are exactly the same.

104

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

j

 

 

 

 

 

 

 

 

 

 

 

 

1+1

 

 

 

4' :34» i»
: 6.1 1——1 I
: Dc _I_ i “
I Source H—bridge H-bridge
: Inverter 1 Inverter 2
ac i
input ] l l L l
I L t.
1 DC __I_ If;
: Source ’1: H-bridge H-bridge
: - Inverter l Inverter 2
I
: l [___] f
' L. I—
1 DC _I_ I?!
: Source T H-bridge H-bridge
1 r Inverter l Inverter 2
I
L _________________________________

Three phase DVR

Figure 6.2: The proposed DVR system.

Load

The output voltages of the Inverter 1 and Inverter 2 may be expressed as:

[vag ng ch ]T=[sa Sb SclTVdc (6.1)

T
and [vagx vng vch]

=lsax be Sex lTVdcxa (6-2)

where 50, Sb , and SC are the switching states for the Inverter 1 and sax, SbX’ and scx

are the switching states for the Inverte 2. For three-level inverters, the switching states

correspond to the output voltage levels and can have the values of 0, 1, or -1. When just

considering the effects of the two inverters on the load, the load phase voltages can be

expressed in terms of the vag and vagx as

105

vas vag + vagx
vbs = ng-I-ngx . (6. 3)

vcs ch + vch

The effective Iine-to-line load voltages may be expressed in terms of the phase voltages

as

Vabs I -l 0 Vas
Vbcs = 0 l -I vbs . (6. 4)
vcas -l 0 l vcs

Since in the proposed circuit structure, the DC bank voltages are no longer identical,
the numbers of output voltage levels in phase and line-line voltage no longer follow the
general rules. At this condition, it is necessary to look at the voltage vector plot of the
proposed circuit structure to analysis the voltage levels in the output voltages. The
voltage vector plot is formed by plotting the space vector of phase voltages in the d-q
stationary reference frame for all possible combinations of switching states. In the case
as shown in Figure 6.2, vector plots vary widely depending on the ratio of the DC
voltages. Figure 6.3 shows the voltage vector plots of the proposed cascade inverter for
several DC voltage ratios, whereas Figure 6.4 shows the maximal distention. Therein,

the axes of each subplot of Figure 6.3 are the same as those shown in Figure 6. 4.

. . . . V .
As shown in Figure 6.3, when the voltage who 18 set to Vdcx 2 —%°—, the vector plot

appears as several three-level vector plots arranged in a three-level pattern. If the voltage

ratio is increased further to Vdcx = Vdc /2 and Vdcx = Vdc , the cascade-3/3 inverter can

operate as a seven-level and five-level inverter respectively. However, these modes of

106

operation are not as desirable as that of maximal distention, which yields the highest

power quality.

In general, the voltage rating which yields maximal distention for an arbitrary number

of voltage levels is

nx-l

 

Va'cx =
Vdc

’
r1’1x .’1x

(6. 5)

where n and nx are the voltage levels of the upper and lower inverter respectively. For

the connection of two 3 level inverters, the maximal distention is achieved when

Vdc
Vdcx :

. At this condition, the vector plot is the same as that of a nine-level inverter.

Thus, the proposed DVR is capable of emulating. a maximum of nine voltage levels.

 

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u cccccccc . no.
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04.0 010‘ 00.0 .1“
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as I so a a... .00.
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can .m. A I... n o ..‘.‘C
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o I .i. I
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‘4 0 Jill
.......... s...
'- a.-
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II .0.
............
' ll IDI'
QQQQQQQQQQQQ
I on
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......

 

..... I C I
O O 1 Q Q I I
C I l I I I 0 I
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I Q Q Q ‘ 0 I D I

oooooooooooooooo

uuuuuuuuuuuuu

Figure 6.3: Cascade 3/3 vector plots.

107

Figure 6.4: The vector plots of maximal distention.

6. 3. 2 Control of Proposed DVR System

There are two ways to control the two inverters. One is joint control, which utilizes
multiple Sinusoidal Pulse Width Modulation (SPWM); another is separated control.
Compared with joint control, separated control makes the system more robust and

ﬂexible [31]. In this chapter, only separated control will be introduced.

The separate inverter control utilizes isolated algorithms for the bulky power Inverter
1 and the smaller conditioning Inverter 2. The Inverter 1 is controlled by the staircase, or
low switching frequency PWM method to provide the voltage needed to compensate for
the voltage sag, whereas the Inverter 2 utilizes high-frequency PWM to shape the
compensation voltage and current and achieve high power quality. It should be noted

that, as with the separate-inverter control, Inverter 2 only perform harmonics elimination

108

and does not consume real power, thus does not need a dc power supply to support its DC

bank.

The staircase control of the bulky Inverter 1 is shown in Figure 6.5. By controlling

the switching angle, a , the fundamental of the staircase waveform can be controlled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11
Vdc" vag
a it 27;
_ Vdc
11 g
V dc vcg
— Vac ;
l 5
2Vdc I l vac i
Vdc E E 5
— Vdc _l _U,
—2Vdc

Figure 6.5: The staircase control of the bulk inverter (Inverter 1).

The control reference for the Inverter 2 is the harmonics content in the output voltage

of Inverter 1. The total harmonic content of the phase voltage can be expressed as

vag,h : vag - Vag,f a

(6. 6)

where Vag,f is the fundamental component of vag. The fundamental component, Vag,f

109

can be obtained simply through a low pass ﬁlter. However, it should be noted that a
three-phase vector PLL circuit based on the line-to-line voltages gives better performance
because the three-phase line-to-Iine voltages contain no triplens and their lowest
harmonic is the 5‘“. Once the phase angle information is obtained by the PLL circuit, the
synchronous frame method can be used to extract the fundamental component. After

vag, f is found, the control reference for the conditioning Inverter 2 is also found.

Another consideration of the separate inverter control is the DC voltage control of the
conditioning inverter. In order to maintain maximal distention, the DC capacitor voltage
on the conditioning inverter should be kept at one third of the DC voltage of the bulk
inverter. To achieve this, a straightforward PI control is adopted to regulate active power
ﬂow into the conditioning inverter. The control scheme of the conditioning inverter is

shown in Figure 6.6 for the a-phase.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+
Inverter 1 Load
Conditioning _L v
Inverter " dc"
V68
Fundamental
and harmonics PWM
detection Generator

 

 

 

 

 

 

 

 

 

 

 

Vdcx
-- PI regulator #65" V20:

Figure 6.6: Conditioning inverter control diagram.

 

 

 

110

. * . . . .
Therein, Vdcx IS the DC voltage reference, which is set to one third of Vdc- The

* . . . . .
voltage vag,1 is a unit Sine wave in phase With the phase voltage vagJ and can be

directly obtained from the vector PLL circuit . The resulting reference voltage is used as
an input for the PWM modulator of the conditioning inverter. Similar control channels

are used for the b- and c-phase.

Figure 6.7 shows simulation results of the cascade multi-level inverter using the
separate control, in which a) is the DC voltage of the conditioning inverter; b) is the load
current; c) is the total load line-line voltage; (I) is the bulk inverter line-line voltage; e) is

the conditioning inverter line-line voltage; and f) is the harmonics in the line-line voltage

of the bulk inverter. In simulation, Vdc was set to 600 V, and a was set to 15°. It can be

seen that the DC link voltage of the conditioning inverter is kept at one third of the dc
voltage of the bulk inverter. The total line-to-line voltage is improved from the bulk
inverter ﬁve-level waveform by the conditioning inverter and the maximal distention of
the cascaded inverter is realized. The proposed circuit structure and control strategy are

proved.

The cascade multilevel inverter with uneven DC bank voltages can be used in a lot of
low voltage and low power applications to achieve good power quality with minimum
circuitry. But for high voltage and high power applications like UPFC and STATCOM,
the uneven structure is no longer attractive. In these applications, the bulky inverter will
be very expensive and hard to design, manufacture, and maintain. With only two
modules, high voltage devices will be used. This will become impractical when the

voltage level is higher than several kilo volts.

Ill

a)

d)

e)

300.0 ., ,, (V1 : is)

l Ave: 200.09 "Z i V
200.0.1_._ We 2,2,, ,2 3- _‘ki‘ S
l V_
100.0 1; duo

0
0.0 ll

(A) 3 t($3)
100:0 j RMS:52845;

; 1'
ii ' QS _ ,
0.0 51 J:
l 1‘7 Ir, J‘
ll ‘
-IO0.0 1
300.0... 2 - -- 2...- (V) 40
1 .31“) ’ "i
400'0" r .a‘ .. ,1 Vas _vbs
0'00? " l": ' ‘ ”r 1’”
'400.0 i," 1'1. (J, . L \
-800.0!1 _ jlj’PMMM 51PM
800.01, : , (V) : “3)
40°01: Z ‘ Vag “V18
0.0 ‘
-400.0 ] ’ 1
-800.0
200.0 ,1 , W M (V) 2 1(8)

. Vex ‘ ngx

 

 

200.0? _ : (V) - t(s)

‘1 1' . 1 [I v h _vb,
0.0-[i . ' 1 ll 11"“. l} 'ij' » l , III; ll] \{l ag gr
I! 1" l l‘ "l 1" s.
1‘ '3‘ '~ »- .3" 31 ‘1].
-200. 0 ‘_ .,z_; __ 1

1.66 1.68 1.7 ((3)

Figure 6.7: The simulation result of the separate control.

112

6. 4. Applications of Cascade Multilevel Inverters in DG

6. 4. 1. Proposed Applications Examples

The cascade multilevel inverter is the best choice for certain types of DG, where
many separated power supply units are involved, such as photovoltaic, fuel cell and wind
farm. Figures 6.8-6.10 shows three proposed application examples of cascade multilevel
inverters in DG. The circuit topology in Figure 6.8 is aimed at fuel cell and photovoltaic
applications, where separated DC sources are available. The topology in Figure 6.9 is for
a wind farm, where the ac voltage from the wind turbines are ﬁrst converted to DC then
applied to the cascade multilevel inverter. Figure 6.10 is proposed for the cases that high
power quality is required whereas only one DC power supply unit is available to supply

the power.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ac output
”1 __J
DC DC __ 14:,
Source Regulator T H-bridge
DC DC .8},
Source P Regulator T H-bridge __1
1 ‘ ‘ ;
. ﬂ ._1
DC DC __ JG
Source Regulator A .
r— l H-bridge

 

 

 

 

 

 

 

 

 

Figure 6.8: The proposed topology 1.

113

ac output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FE DC ——J
ac % -——l Rectiﬁer ’7‘ JG
’ Regulator T 6-.....
H r
soiiiice % I] Rectiﬁer RegiIator :1: JG
_ _ H-bridge
1 i *1
l

 

 

 

 

 

 

 

ac Rectiﬁer DC ___. JG
source Regulator T H-bridge

Figure 6.9: The proposed topology 2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

__J
DC __ J4}
__ R°g“l°t°r T H-bridge
DC DC _L 1%}
Source Regulator T .
_ H-bridge __1
__|
DC 4L JG
L Regulator T H-bridge

 

 

 

v

 

 

 

 

 

 

Figure 6.10: The proposed topology 3.

In all three circuits, DC voltage regulators are needed to make sure each module in

the cascade multilevel inverter has the same input dc voltage. One thing that must be

114

noticed is that the DC voltage regulator is needed only in DG applications. In FACTS
devices, where in most cases, there is no real power exchange from the inverter to the
utility line, the DC voltage on each capacitor of the cascade multilevel inverter can be
self-maintained and balanced with proper control. In the proposed DVR, the DC power
is from the utility line through the rectiﬁer, and the voltages on each capacitor can also be
self-balanced. In DG, real power ﬂows through the cascade multilevel inverter itself.
There is no way to balance the capacitor voltages just by rotating the switching. sequence.

Thus, a DC voltage regulator is needed for each module in the cascade multilevel inverter.

The DC voltage regulator partly decides the performance and cost of the whole DG
system. So it is important to ﬁnd the optimized DC regulator circuit with the best
performance, lowest cost and smallest volume for the applications of cascade multilevel

inverters in DG.
6. 4. 2 DC-DC Circuit Selection

In general, there are two types of DC-DC converters: isolated and non-isolated.
Usually, non-isolated DC-DC converters like buck, boost, buck-boost, and Cuke
converter are used at low power applications. In the cases of DG, utilizing these types of
converters will result in high cost and low efﬁciency. Moreover, in the circuit shown in
Figure 6.10, isolation is needed. So this chapter mainly focuses on comparisons of
isolated dc-dc converters. The general diagram of an isolated DC-DC converter is shown

in Figure 6.11.

115

For isolated DC-DC converters, forward, push-pull, half bridge and full bridge can be
considered as topology candidates [131-138]. The advantages and disadvantages of these

topologies are fully discussed in [131, 137]. In general, forward and push-pull converters

Transformer

 

 

 

 

 

 

 

 

Input
Capacitor

DC/AC AC/DC

1—1

 

 

 

 

 

 

 

Figure 6.11: The general diagram of isolated dc-dc converter.

are not suitable for high power applications. Forward converters have restrained duty
cycles and lossy resetting of excitation; in push-pull converters, the two halves of a
center-tapped winding cannot be equal or symmetrically wound, and the power switch
on/off times as well as their forward voltage drops are never equal. These irregularities,
which exist in practice, can contribute to transformer core saturation and result in the
converter failure. In both forward and push-pull converters, the voltage rating of the
device is two times that of the half and full bridge. Though the full bridge, compared
with the half bridge, has more components, the current in the devices and the transformer
turns ratio can both be reduced to half. The current ripple in the front end capacitor is
also minimized. The voltage and current stresses on the devices in the full bridge are the

smallest in all of the four topologies.

There are also several topology options for the secondary Side of the DC-DC
converter, such as diode rectiﬁer, controlled rectiﬁer, voltage doubler and controlled

voltage doubler. All these four topologies have the same device voltage rating. For the

116

secondary side, which is directly connected with the cascaded multilevel module, the

major concerns for the topology selection should be:
1) Efﬁciency;
2) Cost;
3) The resulted transformer turns ratio;

4) Power control ﬂexibility.

Voltage doubler circuits will give smaller transformer turns ratio. But it will also lead
to a large current ripple in the output capacitor. The current ripple will result in low
efﬁciency, and possible overheat of the capacitor and reduced lifetime of the capacitors.

So in the applications of DG, a voltage doubler should only be used when the power is

less than 10 kW.

By using the active switches, there will be more ﬂexibility in controlling the power
ﬂow and voltage. Active devices will also create more possibility in the control the
current waveforms over the transformer, thus the current stress on switches will be
depressed. However active switches are more expansive. Furthermore experimental
results also show that active control of the secondary side, in order to achieve a higher
voltage transfer ratio than in the non-controlled case, will greatly lower the overall
system efﬁciency. Therefore, a full analysis and comparison between the controlled and

non-controlled case is performed in the next session.

117

6. 4. 3. Comparisons Between Two Cases

The circuit structures of controlled and non-controlled case are shown in Figure
6.12(a) and (b). The transformer primary side referred equivalent circuits of the two
conﬁgurations are shown in Figure 6.12(c) and (d), respectively. The correspondent
voltages and current waveform over the transformer are shown in Figure 6.12 (e) and (t).
It is found that the voltage doubler and full bridge rectiﬁers yield the same voltage and
current waveforms. The only thing that will make a difference in the current and voltage
waveforms is whether the secondary is controlled or not. So, the controlled voltage

doubler and uncontrolled full bridge are shown in Figure 6.12(a) and (b), respectively.

Case I. Controlled rectifier

In Figure 6.12, Ls is the leakage inductance of the transformer. The full bridge and
voltage doubler are controlled to switch at high frequency to produce two square voltage
waveforms with a phase shift, 19, as shown in Figure 6.12(e). The two square-wave
voltages are impressed across the both sides of the transformer, respectively. So the

current over the leakage inductance would look like the is as shown in the Figure 6.12(c).

As is is a function of wt , where a) is the switching frequency, the current waveform can
be analyzed as following:

At 0 radian in Figure 6.12(c), the primary side voltage becomes positive while the
secondary side voltage remains negative, creating a positive voltage across the leakage

inductance making the current increase until cat = (9, where the secondary voltage

changes polarity from negative to positive. The current at this point can be written as

118

 

.111;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IE} 05 c2?
- (a)
-143 P 4m- ‘ .
81:?“ VPT f? V51 [.0er
[1:3 153...“:53013...
* (C)
v IG—wt=2n-D'
e“ T — _
E; of It 27: :0”
ivs: T— —:-]—-
E; : La):
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3" l i \/l
K
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Transformer

15 3 ‘IE 3 Inductance II Ignored ‘

‘41 1'? ”ST
I

Monetizing

 
   

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(d)

Vpr) Id—an=27r->l _-
35° 1’9 I

E; 0 7t 27: I La)!
.,vs? T'_ ___
a, 2 Vs :

E: i a)!
a; .

3: w L; w

1.34 l

g a)!
u 5

Figure 6.12: Two conﬁgurations of the secondary side in the isolated dc-dc converter.

15(6) 2

Vp-l'

Vs

 

119

19+is(0),
s

cot=6

(6. 7)

where VP and VS are the amplitudes of the transformer primary side and secondary side

voltage.

With proper control, VS can be smaller, bigger or equal to VP. The peak current will

be minimized when VS = VP is met. Figure 6.12(c) shows the case of VP < V5.

At cat = :9 , the secondary side voltage becomes positive while the primary side
voltage remains positive, making the voltage across the leakage inductance negative,
allowing the current to decay until (at = 7r, where the primary voltage changes from
positive to negative,

VP -

VS(7r—6)+is(6), wt=7r. (6. 8)
st

 

is(”) =

At this point, the primary side voltage becomes negative while the secondary side
voltage remains positive, creating a negative voltage across the leakage inductance,
making the current keep decreasing until cat = n+6, where the secondary voltage

changes polarity again,

VP+

 

VS(7z—0)+i,(7z), wt=7r+6l. (6.9)

is(7r+t9) = — coLs

After the secondary voltage changes polarity, the secondary side voltage becomes

negative while the primary side voltage remains negative, making the voltage across the

leakage inductance positive allowing the current to increase to point 1, where

120

is(27r)=—%—ESK§(7I—6)+is(n+0), cot=27r. (6.10)

Because is (6) = —is (7: + 6) and is(7r) = —is(27r), the exact relationship between the

current and voltages can be found as equation (6. 11) and (6. 12) by solving equation(6.

7)-(6. 10)

2VP5 '1' (VS — VP)7Z'

i 6? =
S( ) ZmLs

 

(6.11)

21/56 '1‘ (VP — Vs)7f
2(0Ls .

 

(6. 12)

1.50”:

From the representation of is (cut) , the RMS value of the transformer current and the

power transferred through the transformer can be found as:

 

Irms

 

_l-Jﬁ 12-m62-VP-VS—8-93-VP-VS—2-n3.VP-VS+7:3.VSZ+”3.VP2
24-7: 7r-f2-Lsz ’

(6. 13)

1 (—7r+6)

and P=——-9-Vp-VS'(—————]. (6.14)

Three conclusions can be made based on the Figure 6. 12(e) and the equations

obtained above:

1) The power is transferred through the leakage inductance;

121

2) By controlling the phase shift of the voltages between the two sides of the
transformer, the power transferred over the transformer as well as the secondary

side dc voltage, V5 , can be precisely controlled;

3) If the system is controlled to have V5 z VP , the current wave form would be
rather ﬂat, which means the peak current can be smaller.

In summary, for the controlled rectiﬁer case, the voltage angle difference, 6, and the

secondary side voltage, VS , are both controllable by properly coordinating the control of

the primary side and secondary side. The power transferred over the transformer, P , can

be variable at ﬁxed secondary dc voltage, VS- VS can be equal to or larger than the

primary voltage VP .

Case 2. Uncontrolled Rectifier

The analysis of the uncontrolled case can be made by using the same method used for
the controlled case. In uncontrolled case, (9 is no longer controllable, the relationship

between 0 and VS , is found as

6:”.M, (6.15)
2-VP

where VP > V5 .

The power transferred over the transformer and RMS value of the current are

122

 

(6. 16)

 

and (6. 17)

 

From equations 6. 15-6. 17, it can be seen that 6 decides both the secondary side

voltage, VS , and the transferred power, P. For the diode rectiﬁer, VS can not be equal
to or larger than V p , thus, the controllable ranges of output voltage and power are quite

limited.

Figure 6.13 shows the comparisons of the power transfer ability and the RMS current

over the transformer in the two cases.

 

 

 

 

 

 

 

Power VS.Theta Current VS.Theta
0‘16l . Y . ~ —~ 0 25 . . . 1
0.14 l
/ ' ,” _,. . r— I 0.2
0.12 I“ ,,
Controlled , ‘. ’/ 1 V .‘l
j , *’ _ 0‘5 Controlled " ...—- ..
1 ' m Rectlﬂer yr"
0. 0.08 ' ,'/ -’ '/ i E iii/V. ‘1'}, D'Ode
,, x/ , _ T "’ Rectiﬁer
..»;:}fga.i ,, , / 1
006* I.)gfﬁtﬂi}’ Vb :(16VP ,..,
. *7 ' ‘J , '1. 1 ' " ' ' ”
yr {:1}? ‘2 ﬁKRectlﬂer _l_ I, - I...‘
0.02 / E 3t ‘ I .'
0‘ I 1 I . 1 -J - l o L 1 1 1 1
0 . 20, 40 60 80 100 0 ‘. 2Q’ 40 60 80 100
' Theta (Degree) Theta (Degree)

Figure 6.13: The transferred power and RMS current on the transformer in these two

cases.

123

For the uncontrolled diode rectiﬁer case, there is only one power curve and one
current curve related to 6. In the controlled rectiﬁer case, for both power and current,
there is a region related to each 6 respectively. Figure 6.13 only shows several most

often used curves in the region that VS changes from 0.6 VP to 1.2 VP .

One major observation from the Figure 6.13 is that when 6 changes from O to 20
degree, which is the common DC-DC converter operating area, the controlled rectiﬁer
has a higher RMS current, whereas there is no big difference in the power transferred in
both cases. This means there will be more power loss on the transformer and switches in
the controlled rectiﬁer case. Besides the power losses introduced by the RMS current,
switching loss of high power devices at high frequency is also much larger than the
rectiﬁer diodes reverse recovery loss. In one word, the controlled rectiﬁer case will not

have better efﬁciency than the uncontrolled case.

Further research on the system stability shows that the controlled case is stable while
the uncontrolled case is asymptotically stable, which means the uncontrolled case would

have better stability performance.

6. 4. 4 Experimental Veriﬁcation

Experimental results on one 5 kW fuel cell DC-DC converter is shown in Figure 6.14.
Figure 6.15 is a photo of the testing setup. In the experiments, the input power to the dc-
dc converter is supplied by a 12 V battery. The transformer turns ratio is 1:8. The
secondary side is a voltage doubler with two IGBTS. The DC-DC converter is connected

to a resistive load. For the controlled case, the secondary side IGBT was controlled to

124

switching at 20 kHz. For the uncontrolled case, the IGBTs were not switching, and
therefore all the current goes through the free wheeling diodes paralleled with the IGBT.

The efﬁciency comparison results are summarized in Table 6.1.

 

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V m. 100V/dlv
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415/d1v '
L I 1111111111111111111111 L ‘ '11:; 444 A‘__L'

 

(b) The uncontrolled rectiﬁer case

Figure 6.14: The experimental waveforms of the two different cases.

125

MOSFETs
and its Gate
Drive

[PM and its . i ,

Pre-d rive Tra nsformer

DSP Control
Board and
Mother board

 

Figure 6.15: Test setup of the DC-DC converter.

Table 6.1: The efﬁciency comparison

 

Vp (V) Vs Efﬁciency

 

Uncontrolled Case 1 1.2 78.5 91%

 

Controlled Case 1 1.15 79 68%

 

 

 

 

 

 

The waveforms shown in Figure 6.15 resemble the idea analytical waveforms. In the
controlled case, during the phase shiﬁing, there is a voltage drop on the primary voltage.
This is caused by the voltage drop on the leakage inductance of the transformer. The
measured efﬁciency also veriﬁes the analysis. The experimental results veriﬁed the

analytical results.
Table 6.2 summarizes the comparisons between the controlled and uncontrolled cases.

Based on the comparison results, it can be concluded that the full bridge inverter

cascaded with a high frequency transformer and uncontrolled rectiﬁer would be the

126

optimized circuits for the isolated DC regulator in the DG applications of cascade
multilevel inverters. The controlled rectiﬁer has a larger controllable output voltage and
power range. But the when the cost, efﬁciency, and stability are the major concerns, the

uncontrolled rectiﬁer becomes more practical.

Table 6.2: The summary of the comparisons

 

Controlled Rectiﬁer Uncontrolled Rectiﬁer

 

Controllable Voltage Larger controllable output

Range voltage range

 

Larger controllable output
Controllable Power Range

power range

 

_ . Better system stability
System Stab111ty

performance

 

Almost square waveform Triangular Waveform with
Transformer Current

 

 

with less peak current higher peak current
Efﬁciency Higher Efﬁciency
Cost Lower Cost

 

 

 

 

 

6. 5. Summary

In this chapter, the applications of multilevel inverters in distribution system were
proposed. With the UPFC and U-STATCOM proposed in Chapter 4, and 5, applications
of multilevel inverters in all levels of power system have been demonstrated. After

ﬁguring out the optimized DC regulator circuit, together with the methods mentioned in

127

Chapter 3, the question of how to maintain and balance of the DC banks in multilevel

inverters has been fully answered.

Since all the different levels of applications of multilevel inverters and their
implementation issues have been addressed, in the next Chapter, one 17 level cascade
multilevel inverter together with the realization of its control unit will be shown. With
the 17 level cascade multilevel inverter setup, the harmonics cancellation method

proposed in Chapter 3 will be experimentally veriﬁed.

128

Chapter Seven

A 17 LEVEL CASCADE MULTILEVEL

INVERTER AND EXPERIMENTAL RESULTS

7. 1. Introduction

A 17 level cascade multilevel inverter is shown in this chapter. Each module of the
cascade multilevel inverter indeed is a three level diode clamped H-bridge. Thus, each
module can output a 5 level voltage. For each phase, a total of four modules are cascaded
to output a 17 level phase voltage. The realization of the control unit for the inverter is
described in detail. Experimental results from this inverter are used to prove the

harmonics elimination method prOposed in Chapter 3.

129

7. 2. The 17 Level Cascade Multilevel Inverter

A 17 level, 1 MVA, 6000 V cascade multilevel inverter is shown Figure 7.1. The
inverter was designed and built in house at Power Electronics and Motor Drive
Laboratory of Michigan State University. Each phase of the cascade multilevel inverter
has four modules, resulting in a total of 12 modules. Each module is a diode clamped H
bridge with a maximum 5 level output. This topology makes it possible for the total
output phase voltage to have a maximum of 17 level phase voltage and 33 level line-to-

line voltage. Figure 7.2 shows the schematic of the cascade multilevel inverter.

 

Figure 7.1: The 17 level cascade multilevel inverter.

130

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 7.2: The schematic of the 17 level cascade multilevel inverter.

131

The inverter was designed as an induction motor drive. The power capacity of each
module is 83 kVA. The rated DC bank voltage for each module is 1225 V. The
maximum DC voltage is 1600 V. The rated current is 96 A. The system is designed to
ensure operation under and up to 120% rated current. Thus, 1200 V, 200 A, IPMs are

used as switching devices. Each 1PM integrates two IGBTs and their gate drive circuits.

7. 3. The Realization of the Control Unit

7. 3. 1. Hardware of the Control Unit

The control unit of the cascade multilevel inverter consists of a DSP board, 12 gate
drive boards, three current sensors and a keypad with a LED displayer. Figure 7.3 shows

the diagram of the control unit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

>
K P d d
Displlayfrl ‘ ‘ 36 Channels of Fiber 12 Gate
R3232 Optical PWM Output .
Dr1ve

DSP Board < Boards

Current 1 6 Channels of Fiber

Sensor 3 Optical Fault Output

 

 

 

 

 

Figure 7.3: The control unit diagram.

The DSP board is the core part of the control unit. It receives the control command

from the keyboard, generates the control signals for the gate drives, sends information to

132

the displayer for display, responses to the outputs of the current sensors, and realizes the
protection of the system during fault conditions.

The DSP board is shown in Figure 7.4.

Extension
board3

Extension
board2

Extension
board 1

Base board

 

Figure 7.4: Picture of the DSP board.

The DSP board consists of one base board and three extension boards. The base
board has one DSP chip, one CPLD chip, 16 channels of A/D, one R8232
communication port, one can bus, 8 channel optical inputs and 16 channel optical outputs.
The calculation, command response, communication, A/D conversion, part of logic
combination, and generation of control signals are realized inside the DSP chip. The

CPLD performs the most of the logic combinations. Each extension board receives 16

133

control signals from the CPLD and outputs 16 optical signals. In the case of the 17 level

cascade multilevel inverter, only two extension boards are utilized.

The DSP board communicates with the keyboard and displayer through a RS232
serial communication port. The connection diagram of the keyboard and displayer is
shown in Figure 7.5. During operation, the initial control parameters are setup with the
keypad and displayer. Then, the DSP board generates 36 coded control signals to 12 gate

drive boards.

 

 

 

 
    
  
 
 
  
 
 

Terminal

 

 

_M--..r~wk.‘-_“ r..-..w‘
. 1

”a 4....— 1226-1

3 . 3°, l power supply

L4...

 

PCAT
wired adapter

coiled cable

‘/ To R8232 Port
on DSP Board

Figure 7.5: The connection of the keyboard/displayer.

For each module of the cascade multilevel inverter, there is one gate drive board to
drive the 8 switches. Since the IPMs already integrate the gate drive circuit, the 12 gate
drive board’s main functions are receiving optical control command, decoding, and
realizing protection at fault conditions. Each gate drive board has three optical inputs for

control signals and one optical output for fault output. The core part of the gate drive

134

board is a CPLD chip. This CPLD chip decodes eight control signals, realizes
protections, and sends out a fault output at fault conditions. Since each gate drive board
has one fault output, total there are 12 fault outputs. As the DSP board only has 8 optical
receivers, every two fault signals from the inverter modules are ﬁrst cascaded, then sent
to the DSP. Thus there are total 6 fault outputs to the DSP board. The fault output

connection is shown in Figure 7.6.

      

   

DSP
ISOl7 Fault In Fault In
[$018
18019

Figure 7.6: The connection of fault signal.

7. 3. 2. Control Signal Generation
In the control of the multilevel inverter, there are two ways to generate control signals
for the inverters:
l) at higher modulation index, utilizing optimized switching angles to control the

inverter to output staircase waveform;

135

2) at lower modulation index, utilizing the multiple carrier PWM method to

generate PWM signals to control the inverter to have PWM output.

a. stair case waveform generation

To realize the staircase waveform, one simple solution is to use lookup tables. Tables
are used to store all the switch states and their angle intervals. To better illustrate this

idea, a simple example is shown in Figure 7.7.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 7.7: The storage unit in the table.

For a ﬁxed modulation index, the waveform is divided into many small divisions by
the edges of step changes in the three phases. Each angle interval, A6 , and its three

Phase switch states, 81, S2 and S3, are stored in the following format in the table:

136

.WORD 972 . ;P1ength,, time length of angle interval, A5 , at 60 Hz

.WORD lﬂlﬂlllglLQQB ;Sl, phase a switch states
A1 A2 A3 A4

.WORD IQLOIMIQQLLLQB ;SZ, phase b switch states
Bl BZ B3 B4

.WORD 1M1M1MILLQB ;S3, phase 0 switch states
C1 C2 C3 C4

In this example, ‘Plength’ equals 927, and stands for the time length of A6 when the
fundamental frequency is 60 Hz. The calculation of ‘Plength’ can be expressed as

A5

ﬂ'X

 

Plength = O/50><10"9. The underlined 12 bits in each switch states word is the

status of the 12 output pins of DSP.

To drive the 8 switches in one inverter module, at least 3 inputs to the gate drive
board are required. So a total of 36 independent outputs from DSP board are needed.
The DSP chip alone does not have this output capacity. Thus, a time sharing scheme is
used in the software to generate 12 control signals for one phase at a time. 12 Pins on the
DSP chip are conﬁgured as general I/O pins to fulﬁll this task. The statuses of these 12
1/0 pins are decided by the bits in 81, S2, and S3. A GP timer inside the DSP is used to
count the time of the switch status. An additional four I/O pins are fed into the CPLD as
timing control pins. Three of them decide which phase the 12 control signals belong to.
The fourth timing signal will ﬂip all the 36 output at the time that a new switch state

starts. The functional diagram of the CPLD for this method is shown in Figure 7.8.

b. PWM generation

To generate PWM signals, for regular inverter with only six control signals, the

DSP’s build-in PWM unit can be utilized to directly realize hardware PWM. But for a

137

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PhaseA
EnA Buffer $
Registers
EnB 36
Phas B
1:j>J > $ W?" :> 81$}:
. Registers
12 inputs L—l/ Register 36
Outputs
PhaseC
EnC 4% Buffer 91}
“4 Registers
EnAll I

 

 

 

 

Figure 7.8: The detailed functional diagram of the CPLD.

ITlllltilevel inverter with at least 36 control signals, there are not enough independent
Ontput pins in the DSP’s PWM unit to accomplish this. In this case, there are two

methods to realize PWM signals.

One method is to use the exact same method used for the staircase waveform. The
switch states and time interval of PWM can be pre-calculated and stored in tables. The
problem with method is that at very low modulation index, where more PWM pulses are

involved, the table becomes very large. The total number of tables that can be saved in

the 32 kbyte of the ﬂash of the DSP chip is limited.

Another method is to utilize the hardware PWM and software allocation at the same
time. In this method, sinusoidal reference waves will be cut into several sessions by
voltage levels. Then after the corresponding offset has been subtracted from each section,
the section will be used to compared with the same triangular carrier wave to generate
PWM signals. However, the PWM generated at this time only means a voltage level

change in the output. It even does not show in which level the change happens. Thus,

138

soﬁware must kick in to decide, at a particular time, which section to be compared with
the triangular and which voltage level has to be changed, and eventually encode at least
four additional controls pins to feed the CPLD. Since software is involved in the PWM
generation, timing is still very important. The best way to guarantee the timing is to use

Compare interrupt from the EV block of DSP.
C- decoding in the CPLD of the gate drive board

It is mentioned that the CPLD on the gate drive needs to decode the three inputs
Signals to eight control signals. If the three control inputs to the CPLD on the gate drive
bGard are named as K1, K2, and K3, and the 8 control signals to the switches are Sal,

Sa2, Sbl, Sb2, Sal’, Sa2’, Sbl’, and Sb2’, the relationship between them can be
Summarized in Table 7.1. The control signals and their correspondent switches are

Shown in Figure 7.9.

 

 

 

 

 

 

salJ Sbl J
4

 

 

 

Figure 7.9: The inverter module structure.

139

Table 7.1: The gate drive CPLD decoding table.

 

 

 

 

 

 

 

 

 

K1 K2 K3 Sal SaZ Sbl Sb2 Sal’ SaZ’ Sbl’ Sb2’
1 l l 1 1 l 1 1 l 1 1
1 1 0 1 0 l 0 0 l 0 1
l 0 l l 0 1 1 O l 0 0
1 0 0 0 0 1 l l l O 0
0 1 l 0 0 1 0 1 l 0 l
0 l 0 l 0 0 0 0 l 1 l
0 O l l 1 0 0 0 0 1 1
0 O O l l l 0 0 0 O l

 

 

 

 

 

 

 

 

 

 

 

 

 

When K1, K2, and K3 are all ‘1’, all the control signals to IGBT are also ‘1’. Due to
the circuit nature, at all the other conditions, Sxx should be complimentary with Sxx’.
Based on Table 7.1, the relationship between Kx and Sxx can be described with

following equations:
Sal=K1&K2&K3+K1&K2&K3+K1&K_2&K3
+E1&K2&‘1?§+F1&K‘2&K3+1?1&1?2&k’3
Sa2=K1&K2&K3+E1&I?2&K3+l?l&i<_2&1?3
Sbl=K1&K2&K3+K1&K2&E3+Kl&I—<_2&K3
+K1&I?2&K3+E1&K2&K3+I?1&K2&K_3

Sb2=K1&K2&K3+Kl&I?2&K3+K1&I—(_2&K3

7. 3. 3. Inverter Module Voltage Balancing

Each phase of the inverter has 4 modules. To keep the voltages on the modules
balanced with each other, the DC bank voltage balance method introduced in Chapter 3 is

used. In the programming, module voltage balancing is realized inside DSP. The main

140

idea is to rotate the switch states from one module to another every fundamental cycle.

The rotation scheme is shown in Figure 7.10. Since the inverter is designed for induction

motor drive. The DC banks of the inverter are powered by isolated rectiﬁers. Thus, DC

voltage maintenance is not needed in this case.

7. 3. 4. Fault Protection Scheme

There are four levels of protection in the whole system:

1)

2)

3)

4)

The ﬁrst level is inside the IPMS. Each IPM has over current, over temperature
and UVLO protection. When one of the faults happens, the IPM will protect
itself and send a fault output to the gate drive board.

The second level of protection is inside the CPLD of the gate drive board. The
fault outputs from the IPMS are fed to the CPLD. Once the CPLD detected fault,
it will wait 6 ,us , then shut down the module and send fault output to DSP board.
The 6 ,us waiting period is to ensure that the faulty IPM has enough time to soft
shut down.

The fault inputs to the DSP board are ﬁrst fed to the CPLD chip, the CPLD will
shut down all the output immediately. At the same time, a protection signal is
fed to the DSP chip.

The protection signal will trip hardware blocking of DSP’s I/O ports and initiate
a protection interrupt routine. The interrupt routine will again block all the I/O

and disable all the interrupts, show “Stopped” on the displayer, then wait for

141

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142

manual reset. The load current sensor outputs are also fed to the DSP chip. If the
peak current is bigger than 200 A, the program will goes to the protection routine

and shows “Over Current” on the displayer.

The diagram of protection scheme is shown in Figure 7.11.

 

One or more lPMs
protect themselves and
send fault output to the

CPLD on Gate Drive
Board

 

 

 

 

 

 

V
The CPLD on the gate drive
board wait for 6 us, and then
shut down the module send

fault output to the DSP Board

 

 

 

 

 

 

The CPLD on on the Gate
Drive Board will shut down
the whole inverter
immediately, send a fault Load current has peak
output to DSP, mg a fault current higher than 200 A

indicator on the DSP board

 

 

 

 

 

 

 

 

 

 

 

 

 

ﬂue DSP will block all the yo

. . t
outputs, disable all the interrupts outputs, disable all the,1,nterrup S

, ,, . show Over Current on the
show ‘ Stopped on the displayer \

/ \ displayer.

The DSP will block all web)

Figure 7.11: The fault protection scheme.

The detailed function blocks of the control unit are shown in Figure 7.12. In the
experiments of the 17 level cascade multilevel inverter, look up tables are used to

generate staircase waveform and PWM waveforms.

143

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144

7- 4. The Experimental Results

Experiments have been carried out to prove the harmonics cancellation method
proposed in Chapter 3 with the l MVA 17 level cascade multilevel inverter. In the
experiments, the dc bank voltage of each inverter module was ﬁxed at 800 V, thus each
voltage level was 400 V. The modulation index was ﬁxed as 0.84. Six harmonics, 5th, 7th,

1 1 th, 1 3‘“, 17h and 19th, are optimized with eight switching angles listed in Table 7.1.

In calculation results, the selected harmonics are less than 1 pico p.u. Figure 7.13(a)
shows the phase voltage. Corresponding FFT analysis of the waveform is shown in
Figure 7.13(b). Figure 7.14 shows the line-line voltage and its FFT analysis. Both FFT
results in Figure 7.13 and Figure 7.14 show the selected harmonics are eliminated. In the
line—line voltage, there are also no third harmonics. The experimental results verify the

proposed method.

Table 7.2: The switching angles for MI=0.84

 

 

 

 

 

6l (rad.) 62 (rad) 63 (rad) 6, (rad)
0.05995 0.18863 0.28101 0.36322
MI=0.84 65 (rad.) 66 (rad) 67 (rad.) 68 (rad)
0.50503 0.63771 0.87771 1.0889

 

 

 

 

 

145

 

p.u.vahie

 

......................
. - {

 

1

 

..................................................

y. .o n . ... . . . .. J... . u .. n . . ...“.

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:"f f 2000 V/div

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. 5.: >
' 'r ' - ' a ﬁrm; ' ' a '"l" guinea. ‘ - 5 . t
g I!
H 0

Phase Voltage

 

 

(a). The phase voltage at MI=0.84

 

1 " 7 z z
0.9 - 3 1 5
0.8 '
0.7 -
0.6 '
0.5 '
0.4 -

 

 

 

 

Harmonics

(b). FF T analysis result

Figure 7.13: The phase voltage when MI=0.84.

146

 

 

 

 

 

 

....w. .................. ‘2”
“33 %“ﬁ “3'5 ‘o
“6 “a ‘t 1‘ *1. a
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_é I! . .2 . w s
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c ‘1’ . Line-line .f, .5
1.. ..q. . . . . . . . . . . .. . . . . . . .1. .......
. _t . voltage . r. .
, l . , . . ' .
. - 1’, - P » 2000 V/dlv A l." a" -
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(a). The line-line voltage at MI=0.84

 

 

 

l l l l l l
0.9 . ......................................................................... 1
0.8 . ......................................................................... _
0.7 . ........................................................................ -

a, 0,6. ......................................................................... -

%

g 05. ......................................................................... _

.

‘3‘ 0.4. ......................................................................... .
0,3 . ......................................................................... -
0,2 . .................................................... . .................... _
0.1 . ......................................................................... _

0 oooeooooeooooeooooeooooeooeoeooooo

 

 

Harmonics

(b). FFT analysis result

Figure 7.14: The line-line voltage when MI=0.84.

147

7. 4. Summary

In this chapter, a lMVA 17 level cascade multilevel inverter was shown. The
hardware and software realization of its control unit were described in detail.
Experimental results were shown to prove the harmonics elimination method proposed in

Chapter 3.

148

Chapter Eight

CONCLUSIONS

8. 1. Conclusions

Multilevel inverters are the next generation inverters for utility applications. With
multilevel inverters, the bulky transformers used in FACTS, Custom Power and DG
devices are no longer needed. The power loss, volume, and cost of these devices will be
greatly reduced, whereas the reliabilities of the devices will be increased. Among the
three major multilevel inverters, the cascade multilevel inverter is the most suitable one
for power system applications. In the cascade multilevel inverter, the H-Bridge can be
modularized. For high voltage and high power applications, this characteristic of the
cascade multilevel inverter will greatly increase the ﬂexibility in the design, manufacture,

and maintenance.

149

The major effort of this work was to propose new ways of utilizing cascade multilevel
inverters in FACTs devices. Extension applications of multilevel inverters, real
implementation issues, as well as the realization of a DSP based control unit for a 17

level cascade multilevel inverter were also presented.

The most important issues for the implementations of multilevel inverters are output
voltage harmonics elimination and DC bank voltage maintenance and balance. In
Chapter 3, a new harmonics elimination method based on equal area criteria and
harmonics injection was proposed. The basic idea and steps for the realization steps of

the proposed method were described in detail.

In power system applications, there are three conditions for DC voltage maintenance:
1) pure reactive and harmonics compensation, 2) back-to-back connection structures, and
3) voltage regulation in DG. The ﬁrst two conditions were discussed and shown in
Chapter 3 and 4. The method for DC voltage regulation in D0 was shown in Chapter 6.
The optimized DC voltage regulator circuit has been identiﬁed and proved by

experimental results.

The most important applications of multilevel inverters in the power system are
FACTS devices for the transmission system. But for the most advanced FACTs device—
the UPFC, the cascade multilevel inverter can not be used since it can not be back-to-
back connected. In Chapter 4, a new face-to-face UPFC circuit structure was proposed.
The circuit analysis, operating principle, and control strategy of the proposed structure
were presented. Full comparisons between the conventional and proposed structures

were carried out. Simulation results were used to verify the proposed structure.

150

As for the most commonly used FACTS device—the STATCOM, a delta-connected
cascade multilevel inverter structure was proposed in Chapter 5. The current imbalance
compensation theory, compensation component detection method, control strategy and

simulation results were presented.

Extended applications of multilevel inverters in power system were discussed in
Chapter 6. For Custom Power, a DVR with uneven cascade multilevel inverter structure
was proposed. Three examples of applications of cascade multilevel inverter in DG were

also Shown.

A 1 MVA 17 level cascade multilevel inverter was introduced in Chapter 7. The
realization of the DSP based control unit was fully described. Experiments were

performed to verify the harmonics elimination method proposed in Chapter 3.

8. 2. Contributions

This work has contributed to the existing body of knowledge as follows.

0 A new UPFC circuit conﬁguration has been proposed. Beneﬁting from the
proposed face-to—face conﬁguration, the cascade multilevel inverter can be used.
With proper control, no active power ﬂows through either inverter. The total VA
rating of the proposed conﬁguration iS smaller than the conventional
conﬁguration at most operating conditions. Thus the stress and power loss on the
devices could be reduced, which will further increase the total efﬁciency and

reliability.

15]

A delta-connected cascade multilevel inverter based Universal STATCOM has
been proposed. Unlike the conventional STATCOM, the proposed U-
STATCOM can be used to compensate imbalance in the load current without
active power flow through the inverter. Thus universal compensation can be

realized.

A new harmonics elimination method has been proposed. Many harmonics
elimination methods have been pr0posed in the last decades. But no Simple and
practical method has ever been found. Almost all the proposed methods need to
solve multi-variable, high order polynomial equation groups. The method
proposed in this work only involves ﬁve steps and four Simple equations. It is

much simpler and more practical than all the other methods.

An uneven cascade multilevel inverter - based transfomerless DVR with only one
DC source per phase has been proposed. The proposed DVR Shows the
possibility and advantages of utilizing uneven cascade multilevel inverter in low
voltage and low power situations. For the high voltage and high power
applications, the uneven structure will reduce the beneﬁts of utilizing the cascade
multilevel inverter since in the uneven structure the H-Bridges can no longer be

modularized.

The optimized DC voltage regulator circuit for application of cascade multilevel
inverter in DG has been identiﬁed. Compared with other circuits, the optimized

circuit has the lowest voltage and current stress and the highest efﬁciency.

Three applications of cascade multilevel inverters have been proposed for

different types of DG.

152

O A DSP based control unit for a 17 level cascade multilevel inverter was realized.
For the commercially available DSPs, a single DSP chip is usually designed to
drive a maximum of three 6-switch inverters at one time. In the realization of the
control unit with only one DSP chip, time Sharing scheme and lookup tables are

used to overcome this problem.

8. 3. Recommendations for Future Work

The proposed face-to-face conﬁguration for UPFC can also be extended to other
applications. One direct example is the Uniﬁed Power Quality Conditioner (UPQC).
The main functions of the UPQC are to eliminate harmonics, compensate reactive power,
and correct system imbalance in the distribution systems. Though the functions of UPQC
are quite different from the UPFC, they have the same back-to-back structure. The same
active power ﬂow control strategy used in the UPFC can also be used in the UPQC.
Even when the UPQC is controlled to correct current or voltage imbalance, the active

power ﬂow through both inverters can be controlled to be zero.

The uneven cascade multilevel inverter structure used for the DVR can also be used
for some DG applications, where the power rating is not too high and only one DC or AC
source is available. The DC bank of the major inverter will be connected to the power
source. The load current also ﬂows though the power source, the cascade multilevel
inverter, and the load. But because the conditioning inverter is controlled to output only
harmonics voltage, there would be no active power exchange between the conditioning

inverter and any other part of the circuit. Thus, with proper control, the load would have

153

a high quality voltage input. And at the same time, the DC voltage of the conditioning

inverter automatically remains constant.

The same idea behind the proposed harmonics elimination method can be applied to
calculate optimum PWM for high power inverters. In high power inverters, to reduce the
switching loss, switching frequency is limited to very near the fundamental frequency.
Thus, high harmonics content will appear in the output voltage of the inverter. To
eliminate the harmonics, optimum PWM angles are usually calculated based on complex
algorithm like linear least squares with constraints. In this case, to simplify the PWM
switching angle calculation, the equal area criteria and harmonics injection can also be
used. The same ﬁve steps and Similar equations as in the method proposed in Chapter 3

can be used to calculate PWM angles.

154

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Instantaneous Power Theory. APF and UPQC

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DVR

[114]Loh, P.C.; Vilathgamuwa, D.M.; Tang, S.K.; Long, H.L. “Multilevel Dynamic
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[115]Visser, A.J.; Enslin, J.H.R.; de T Mouton, H., “Transformerless series sag
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[l 16] Haque, M.H., “Voltage sag- correction by dynamic voltage restorer with
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[119]Ghosh, A.; Jindal, A.K.; Joshi, A., “Design of a capacitor-supported dynamic
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[120] Choi, S.S.; Li, B.H.; Vilathgamuwa, D.M., “Design and analysis of the inverter-
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[121]Vilathgamuwa, D.M.; Wijekoon, H.M.; Choi, S.S., “Interline dynamic voltage
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[123]El-Khattam, W.; Elnady, M.; Salama, M.M.A., “Distributed generation impact on
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[125]Fitzer, C.; Barnes, M.; Green, P., “Voltage sag detection technique for a dynamic
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Distributed Generation

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[127]H. B. Puttgen, P. R. MacGrego, F. C. Lambert, “Distributed generation: semantic
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[131]Fuel Cell Handbook (Sixth Edition) DOE/NETL, 2002

[132]T. A. Nergaard, J. F. Ferrell, L. G. Leslie, J. S. Lai, “Design considerations for a
48 V fuel cell to split single phase inverter system with ultracapacitor energy

storage”, in Conf. Rec. Power Electronics Specialists Conference, 2002. pesc 02.
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[134] H. Li, F. Z. Peng, J. S. Lawler, “A natural ZVS medium-power bidirectional
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[135]G. K. Anderson, C. Klumpner, S. B. Kjaer, F. Blaabjerg, “A new green power
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[136]J. Mazumdar, I. Batarseh, N. Kutkut and O. Demirci, “High frequency low cost
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[137]Jin Wang; Peng, F .Z.; Anderson, J.; Joseph, A.; Buffenbarger, R, “Low cost fuel
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[138]Haiping Xu; Li Kong; thui Wen, “Fuel cell power system and high power DC-
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Harmonicsﬁlimination

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170

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171

List of Projects and Publications

Projects since Aug. 2001:

2003~2005: Leaded the design, building and testing of a 260 kVA Auxiliary

Power Supply for passenger train.
2004~2005: Participated in 50 kW Z Source Inverter Project.

2003~2005: Programmed and tested 1 MVA Cascade Multilevel Inverter for

induction motor drive.
2004: Completed 1.5 MVA Traction Inverter Module programming and testing.
2002~ 2003: 50 kW Universal Inverter Module programming and testing.

2002~2003: Completed the 10 kW Fuel Cell Inverter System, leaded in designing,

building, programming and testing.

2002: Performed Simulation and analysis of Cascade Multilevel Inverter’s control

strategy.
2002: Designed and completed a Sensor-Less Drive for Brushless DC motor.

2002: Completed 10 kW Z Source Inverter prototype, participated in building,

programming and testing.

2001: Performed simulation and analysis of a novel Multi-LevelConverter based

of Uniﬁed Power Flow Controller (UPFC).

Publications:

IEEE Transaction Papers:

172

[1]

[2]

[3]

[4]

[51

Jin Wang and F.Z. Peng "Uniﬁed Power Flow Controller Using the Cascade
Multilevel Inverter, " IEEE Trans. Power Electronics, Volume: 19, Issue: 4, pp:
1077-1084, July 2004

Jin Wang, F .Z. Peng, Joel Anderson, Alan Joseph, and Ryan Buffenbarger “Low
Cost Fuel Cell Converter System For Residential Power Generation,” IEEE Trans.
Power Electronics, Volume: 19, Issue: 5, pp: 1315-1322, Sep. 2004

Keith A. Corzine, Mike W. Wielebski, Fang Z. Peng, and Jin Wang, “Control of
Cascaded Multi—level Inverters” IEEE Trans. Power Electronics, Volume: 19, Issue:

3, pp: 732-738, May 2004

Fang Z. Peng, Alan Joseph, Jin Wang, Miaosen Shen, Lihua Chen, Zhiguo Pan,
Eduardo Ortiz, and Yi Huang, “Z-Source Inverter for Motor Drives” IEEE Trans.
Power Electronics Volume 20, Issue 4, pp: 857~863, July 2005

Miaosen Shen, Jin Wang, Alan Joseph, Fang Z. Peng, Leon M. Tolbert, and Donald
J. Adams, “Constant Boost Control of the Z—Source Inverter to Minimize Current

Ripple and Voltage Stress”, accepted by IEEE Trans. Power Electronics

Major Conference Papers:

[6]

[7]

Jin Wang, Yi Huang, and F .Z. Peng, “A Practical Harmonics Elimination Method
for Multilevel Inverters”, accepted by 40th Industry Application Society annual
meeting. Hong Kong, 2005

Alan Joseph, Jin Wang, Zhiguo Pan, Lihua Chen, and Fang Z. Peng, “A 24-Pulse
Rectifier Cascaded Multilevel Inverter with Minimum Number of Transformer

Windings”, accepted by 40th Industry Application Society annual meeting. Hong
Kong, 2005

173

 

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

Fang Z. Peng, Jin Wang, and Fan Zhang, “Development of a 1.5 MVA Universal
Inverter Module for Traction Drive and Utility Applications” 36th IEEE IEEE
Power Electronics Specialists Conference PESCOS, pp: 2290~2295, June, 2005

Miaosen Shen, Alan Joseph, Jin Wang, Fang Z. Peng, and Donald J. Adams
“Comparison of Traditional Inverters and Z-Source Inverter” 36th IEEE Power

Electronics Specialists Conference PESCOS, pp: 1692~1698, June, 2005

F.Z. Peng and Jin Wang “A Universal STA TCOM with Delta Connected Cascade
Multilevel Inverter”, 35‘h IEEE Power Electronics Specialists Conference PESC04,
pp: 3529~3533, June, 2004

Jin Wang and F .Z. Peng “Design Guideline of the Isolated Dc-dc Converter in
Green Power Applications”, 4‘11 IEEE International Power Electronics and Motion

Control Conference. IPEMC04, Volume 3, pp: 1756~1761, 14-16 Aug. 2004,

Jin Wang and F .Z. Peng “Low Cost Fuel Cell Inverter System For Residential
Power Generation”, 19th IEEE Applied Power Electronics Conference and

Exposition, 2004. APEC '04, pp: 367~373, Feb. 2004

Miaosen Shen, Jin Wang, Alan Joseph, and Fang Z. Peng, Leon M. Tolbert, and
Donald J. Adams, “Maximum Constant Boost Control of the Z—Source Inverter”
39th Industry Application Society annual meeting. 2004, IASO4, pp: l42~147, Oct.
2004

Miaosen Shen, Alan Joseph, Jin Wang, and Fang Z. Peng, “Study and comparison
of Inverters for Fuel Cell Application” IEEE Workshop on Power Electronics in
Transportation. 2004

Jin Wang and F.Z. Peng “A Novel Conﬁguration of Unified Power Flow
Controller”, 18th Applied Power Electronics Conference and Exposition, 2003.
APEC '03, Volume: 2, 9-13, pp: 919~924, Feb. 2003

174

[16] Keith A. Corzine, Mike W. Wielebski, Fang Z. Peng, and Jin Wang, “Control of
Cascaded Multi-level Inverters ” IEEE International Electric Machines and Drives

Conference, 2003. IEMDC'O3,Volume: 3, 1-4, pp:1549 — 1555, June. 2003

[17] Yunping Chen, Xiaoming Zha, Jin Wang, and Jianjun Sun “Uniﬁed Power Quality
Conditioner: the Theory, Modeling and Application”, IEEE International
Conference on Power System Technology, 2000. PowerCon 2000,Volume: 3,
pp:1329 — 1333, Dec. 2000

175