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This is to certify that the dissertation entitled Minority Carrier Injection in Schottky Barrier Diodes presented by Mohsen Alavi has been accepted towards fulfillment of the requirements for Ph.D. degreein Electrical Engineering AK W Major professor Date AW i2], [986 MS U is an Affirmative Action/Equal Opportunity Institution 0- 12771 RETURNING MATERIALS: lV1£31_i Place in book drop to LIBRARJES remove this checkout from __—. your record. FINES will be charged if book is returned after the date stamped below. IIINORITY CARRIER INJECTION IN SCHOTTKY BARRIER DIODES BY Mohsen Alavi A DISSERTATION Submitted to Michigan State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Department of Electrical Engineering and Systems Science 1986 %\ s n it 52 $. ABSTRACT "MINORITY CARRIER INJECTION IN SCHOTTKY BARRIER DIODES" By Mohsen Alavi For low to moderate current densities, current flow in Schottky barrier diodes (SBDs) is primarily due to majority carrier injection over the metal-semiconductor interface. However, at high current den- sities, such as are encountered in advanced integrated circuits, minority carrier effects become significant. The objective of this study was to experimentally verify and quantify minority carrier injec- tion in platinum-silicide SBDs, develop boundary conditions expressing carrier injection at the metal-semiconductor interface which extend to high injection conditions, and correlate the results with numerical simulation. Two experimental measures of minority carrier injection have been investigated, minority carrier storage and conductivity modulation. Also, new methods have been devised to accurately determine the barrier height of the SBD from its I-V characteristics. Minority carrier storage has been experimentally determined by integration of the reverse bias switching current which, after correc— tion for capacitance stored charge, yields the minority carrier charge removed from the diode on switching from forward to reverse bias. The stored charge was found to increase monotonically both with temperature and forward biased current over the experimental range of 27°C to 125°C and 104 A/cm2 to 105 A/cmz. For 12.5X12 pm unguarded SBDs fabricated on a 1 pm thick n-type epitaxial layer, stored minority carrier charge at 105 A/cm2 was on the order of 10-5 C/cmz, For guarded SBDs, the stored 5 C/cm2 at 105 minority carrier charge was higher, on the order of 5X10— A/cmz. Conductivity modulation was investigated by current-voltage measurements at current densities up to 4X105 A/cm2 and was found to be appreciable, causing the series resistance of the diode to decrease by approximately a factor of 5 at the higher currents, One dimensional numerical simulation results using traditional boundary conditions agree well with both charge storage and conduc- tivity modulation measurements up to 5X10A A/cmz. At higher current densities, however, there is significant difference between simple simulation results and experiment, and additional phenomena including hole tunneling, image-force induced band-gap shrinkage, hole barrier height lowering at high injection, Auger recombination, and lateral voltage drop are considered. ACKNOWLEDGEMENT I wish to express my greatest appreciation to my parents for their continued support and encouragement throughout my studies. To Dr. D.K. Reinhard, my thesis adviser, I express my deep gratitude for his guidance throughout this project. Special thanks are also due to C.C. Yu for providing the numerical simulation results and helpful discussions, and to my guidance committee members, Dr. P.D. Fisher, Dr. J. Asmussen, Dr. C. Foils, and Dr. J. Freeman. This work was supported by the International Business Machines Corporation. ii TABLE OF CONTENTS LIST OF TABLES ................................................ LIST OF FIGURES ............................................... CHAPTER ONE: INTRODUCTION .................................... 1.1 Statement of Problem ................................. 1.2 Preview of Contents .................................. 1.3 Main Contributions of this Work ...................... CHAPTER TWO: BACKGROUND ...................................... 2.1 Introduction ......................................... 2.2 Structure of a Planar SBD ............................ 2.3 Current Transport Mechanisms ......................... 2.4 Effects of Minority Carrier Injection ................ 2.5 Review of Previous Work on Minority Carrier Injection 2.5.1 Theory ........................................ 2.5.2 Experiment .................................... CHAPTER THREE: EXPERIMENT 3.1 Introduction ......................................... 3.2 Test Devices ......................................... 3.3 Measurement of Minority Carrier Storage .............. 3.3.1 Experimental Method ........................... 3.3.2 Correction for the Parasitic Capacitance ...... 3.3.3 Experimental Limits and Accuracy .............. 3.3.4 Minority Carrier Storage Results .............. 3.4 Measurement of Current-Voltage Characteristics ....... 3.4.1 Experimental Method ........................... 3.4.2 Experimental Limits and Accuracy .............. 3.4.3 Current-Voltage Results ....................... CHAPTER FOUR: THEORETICAL SIMULATION ......................... 4.1 Introduction ......................................... 4.2 Basic Theory ......................................... 4.2.1 Basic Equations ............................... 4.2.2 Carrier Generation ............................ 4.2.3 Carrier Recombination ......................... 4.2.4 Traditional Boundary Conditions ............... 4 3 The Effect of Image Force on Boundary Conditions ..... 4.3.1 Energy Bands Near the Barrier ................. 4.3.2 Low Bias Condition ............................ 4.3.3 High Bias Condition ........................... iii 4.4 Effect of Tunneling on Boundary Conditions ........... 70 4.5 Correction for the Lateral Voltage Drop .............. 74 4.6 Method of Approach ................................... 78 4.6.1 Approach of the Previous Work ................. 78 4.6.2 Approach of this Work ......................... 78 4.6.3 Parameter Determination ....................... 79 CHAPTER FIVE: BARRIER HEIGHT DETERMINATION ................... 81 5.1 Introduction ......................................... 81 5.2 Barrier Height Lowering and the Ideality Factor ...... 82 5.3 The Activation Energy Method ......................... 88 5.4 The Richardson’s Constant Method ..................... 89 5.5 Modified Norde's Method .............................. 90 5.6 Results and Discussions .............................. 94 5.7 Chapter Summary and Conclusions ...................... 104 CHAPTER SIX: COMPARISON OF SIMULATION AND EXPERIMENT ......... 106 . Introduction ......................................... 106 6.2 Basic Simulation ..................................... 108 6.2.1 Simulation Method ............................. 108 6.2.2 Current-Voltage Comparison .................... 108 6.2.3 Stored Minority Carrier Comparison ............ 111 6.3 S’mulation Corrected for Lateral Voltage Drop ........ 114 6.3.1 Simulation Method ............................. 114 6.3.2 Current—Voltage Comparison .................... 115 6.3.3 Stored Minority Carrier Comparison ............ 115 6.3.4 Additional Remarks ............................ 120 6 4 Boundary Condition Corrections ....................... 122 6.4.1 The simulation method ......................... 122 6.4.2 Current-Voltage Comparison .................... 122 6.4.3 Stored Minority Carrier Comparison ............ 124 6.5 Consideration of Auger Recombination ................. 128 6.5.1 The Simulation Method ......................... 128 6.5.2 Effect of Auger Recombination on the Simulation 128 6.5.3 Effect of Auger Recombination on Experiment ... 131 6.6 High Temperature Comparison ............................ 136 CHAPTER SEVEN: CONCLUDING REMARKS ............................ 145 7.1 Summary of Major Results and Conclusions ............. 145 7.2 Suggestions for Further Investigations ............... 148 APPENDIX A: DETAILS OF EXPERIMENT ............................ 150 A.l Krakauer’s Method .................................... 150 A.2 Charge Integration Measurement ....................... 152 A.2.l The Circuit ................................... 152 A.2.2 Data Acquisition .............................. 155 A.3 Sample Mounting ...................................... 157 A.4 Current-Voltage Measurement .......................... 158 A.5 Test Device Integrity ................................ 159 APPENDIX B: DERIVATION OF THE HIGH INJECTION HOLE TUNNELING BOUNDARY CONDITION ............................... 161 iv APPENDIX C: DERIVATIONS CORRESPONDING TO BARRIER HEIGHT MEASUREMENT METHODS .............................. C.l Modified Richardson’s Constant Method ................ C 2 Modified Norde's Method .............................. LIST OF REFERENCES page 165 165 166 169 LIST OF TABLES Table page 5-1 Experimentally determined current density axis intercepts and ideality factors. ..................................... 96 5-2 Barrier height values obtained from; (a) original Richardson's constant method using Equation 5-7, (b) modified Richardson’s constant method using Equation 5-17. ..................................................... 97 5-3 Barrier height values obtained from; (a) original Norde’s method, (b) Norde's method modified by Schwartz et. al. [47] to account for the ideality factor n, (c) Norde's method modified to account for barrier lowering AO, as in this work. ................................................ 99 6-1 Hole Auger lifetimes and Auger diffusion lengths in silicon under various conditions. (a) For Auger coefficient, g - 10.31 cm6/s, (b) for g - 7 X 10.31 cm6/s. 132 vi LIST OF FIGURES Figure page 1-1 Minority carrier injection results in excess carrier storage which changes device characteristics in two principal ways. (a) The bulk conductivity is modulated. (b) Switching delay is induced. 2-1 Structure of a planar SBD. (a) Unguarded. (b) Guarded. ..... 11 2-2 Energy band diagram of a planar SBD neglecting the effects of image—force at the metal—semiconductor interface. ....... 12 2-3 Current transport mechanisms over the metal semiconductor interface. ................................................. 13 2-4 Dynamics of reverse-recovery for a semi-infinite device initially under low to moderate forward bias. (a) Hole concentration profile. (b) Switching current. .............. 16 2-5 SPICE simulation results for the current through a diode excited by a sinusoidal signal when minority carrier storage is not present. ............................................ 24 2-6 SPICE simulation results for the current through a diode excited by a sinusoidal signal when minority carrier storage in the diode is significant. ............................... 25 3—1 Metallization layout of the unguarded SBD. 3-2 Doping profile of silicon under the anode of the SBD. Data from C.C. Yu [4]. .......................................... 31 3-3 Response of a 30 ”m2 unguarded test device to sinusoidal excitation at room temperature. (a) Shows the response at a peak current density of 2.67 X 104 A/cm2 and does not show a significant amount of minority carrier storage. (b) Shows the response at a peak current density of 105 A/cm2 and evidence of minority carrier storage is clearly observed. .. 32 3—4 Diagram of the circuit for minority carrier charge storage measurement along with its equivalent circuit. ............. 34 Figure page 3-5 Idealized reverse-recovery waveforms. (a) Corresponds to a purely capacitive response while (b) shows the minority carrier induced switching delay. ........................... 37 3-6 Measured reverse-recovery response of the unguarded test diode at room temperature, corresponding to a forward current density of 5.6 X 103 A/cm2 prior to switching. ..... 40 3-7 Measured reverse-recovery response of the unguarded test diode at room temperature, corresponding to a forward current density of 7 X 104 A/cm2 prior to switching. ....... 41 3-8 Measured reverse-recovery waveforms of the unguarded test diode at room temperature. Values of current density prior to switching are (a) 5.5X1O3 A/cmz, and (b) 4.2X104 A/cmz. . 43 3-9 Measured reverse-recovery waveforms of the unguarded test diode corresponding to a current density of 4.2 X 104 A/cm prior to switching. (a) Shows the response at 27 °C, and (b) shows the response at 125 °C. .......................... 44 3-10 Measurement results for the charge density associated with stored excess minority carriers at four temperatures. The results correspond to average of the data obtained for four unguarded devices. ......................................... 45 3-11 Measurement results for the charge density associated with stored excess minority carriers at three temperatures for a guarded device. ............................................ 46 3-12 Comparison of room temperature results of the stored minority carrier charge density between guarded and unguarded devices. ......................................... 47 3-13 Switching response of a guarded diode at room temperature corresponding to a current density of 4.2 X 104 A/cm2 prior to switching. .............................................. 49 3-14 Current-voltage measurement circuits. (a) The low bias circuit; (b) the high bias circuit (above 1 mA). ........... 50 3-15 Measured J-V characteristics of an unguarded device at four temperatures. .............................................. 52 3-16 Linear plot of the room temperature J-V characteristics of the unguarded device emphasizing high current densities. ... 53 3-17 Measured J-V characteristics of a guarded device at three temperatures. .............................................. 55 viii Figure page 4-1 Energy band diagram of the device near the metal- semiconductor interface under low bias conditions. ......... 65 4-2 Energy band diagram of the device near the metal- semiconductor interface under high bias conditions (beyond flatband). ................................................. 69 4-3 A triangular approximation of the potential barrier for holes at the metal-semiconductor interface under high bias conditions (beyond flatband). .............................. 72 4-4 Cross section of the unguarded diode and the parasitic resistances involved, used as a model for the lateral resistance correction to the simulation. ................... 75 4-5 The diode equivalent circuit used to correct the lateral voltage drop in the n+ buried layer. ....................... 76 5-1 A hypothetical set of observed data with exaggerated non- ideal effects. ............................................. 85 5-2 Plots of F(V) as defined by Equation 5-20 for a-l.5 using the experimental data of Figure 3-15. ...................... 100 5-3 Plots of Equation 5-5 at 27°C using the barrier height value of; (a) original Norde's and Richardson's constant method (0.866 V), (b) modified Richardson's constant method (0.871 V), (c) modified Norde's method (0.881 V). The experimental data is marked with X. ........................ 101 5—4 Comparison of experiment with plots of Equation 5-5 at elevated temperatures using the barrier height values obtained from modified Norde's method and experiment. The experimental data is denoted by X. ......................... 103 6-1 Comparison between current-voltage characteristics of the experiment and the traditional simulation for bias up to one volt. ...................................................... 109 6-2 Simulation results of the J-V characteristics showing the sensitivity of the simulation on the value of the barrier height. .................................................... 110 6-3 J-V comparison between the experiment and the traditional simulation for high injection conditions. .................. 112 6-4 Comparison between the experiment and the traditional simulation for the charge density associated with minority carrier storage in the unguarded device. ................... 113 6-5 Low bias comparison of the measured J-V characteristics with the simulation corrected for lateral voltage drop. ......... 116 ix Figure page 6-6 Effect of lateral voltage drop correction to the simulation for current densities up to 105 A/cmz. ..................... 117 6-7 Comparison of the lateral voltage drop corrected simulation and experiment for an extended bias range. ................. 118 6-8 Simulation results for the charge density of stored minority carriers with and without correction for the lateral voltage drop. ...................................................... 119 6-9 Traditional simulation results for the minority carrier injection ratio. ........................................... 121 6-10 Comparison of simulated and measured J-V characteristics with the simulation including the effects of lateral voltage drop, image-force induced bandgap shrinkage, and hole barrier height lowering. ................................... 123 6-11 Linear plot of the current-voltage characteristics comparing the measured results, the simulation corrected for the lateral voltage drop only, and the simulation corrected for lateral voltage drop as well as the image-force induced bandgap shrinkage and the hole barrier height lowering. .... 125 6-12 Plot of the current-voltage characteristics over an extended range and comparing the measured results, the simulation corrected for the lateral voltage drop only, and the simulation corrected for lateral voltage drop as well as the image-force induced bandgap shrinkage and the hole barrier height lowering. ................................... 126 6-13 Comparison of minority carrier charge-storage results between the traditional simulation and the simulation corrected for image-force induced bandgap shrinkage and hole barrier height lowering. ................................... 127 6-14 Current-voltage characteristics resulting from the traditional simulation with and without consideration of Auger recombination. ....................................... 129 6-15 Minority carrier stored-charge density results from the traditional simulation with and without consideration of Auger recombination. ....................................... 130 6-16 Traditional simulation results for minority carrier profile at a forward current density of 1.1 X 105 A/cm2. ........... 134 6-17 Comparison of minority carrier stored-charge density results of the traditional simulation and experiment. .............. 135 6-18 Traditional simulation results for the J-V characteristics of the device at four temperatures. ........................ 137 Figure page 6-19 Traditional simulation results for the minority carrier stored-charge density at four temperatures. ................ 138 6-20 Comparison of the J-V characteristics obtained from the traditional simulation and experiment at 85 °C. ............ 139 6-21 Comparison of the J-V characteristics obtained from the traditional simulation and experiment at 100 °C. ........... 140 6-22 Comparison of the J-V characteristics obtained from the traditional simulation and experiment at 125 °C. ........... 141 6-23 Comparison of the minority carrier stored-charge density obtained from the traditional simulation and experiment at 85 °C. ..................................................... 142 6-24 Comparison of the minority carrier stored-charge density obtained from the traditional simulation and experiment at 100 °C. .................................................... 143 6-25 Comparison of the minority carrier stored-charge density obtained from the traditional simulation and experiment at 125 °C. .................................................... 144 A-l Diagram of the circuit for measurements using Krakauer's method. .................................................... 151 A-2 A simplified schematic of the pulse generator circuit and the resulting pulse. ....................................... 153 A-3 Diagram of the circuit used to condition the retrace portion of the horizontal sweep raster of the sampling oscillosc0pe to generate a 7 ps down-going pulse suitable for triggering the A/D converter. ......................................... 156 xi CHAPTER ONE INTRODUCTION 1.1 Statement of Problem Schottky barrier diodes (SBDs) are widely used in electronic circuits for a variety of functions. Current flow in these diodes, at low to moderate current densities and temperatures, is primarily due to majority carrier injection from the semiconductor to the metal over the metal—semiconductor interface. The lack of minority carrier injection, and therefore lack of minority carrier storage, leads to considerable SBD speed advantages as compared to p-n junction diodes. At sufficiently high current densities or temperatures, however, minority carrier effects in Schottky barrier diodes become significant. The issue is of current interest in advanced bipolar logic circuits that utilize SBDs. As bipolar integrated circuits are scaled down in size, higher current densities are necessary to exploit advantages of scaling related improvements in speed. This is in part because the junction voltages required to turn on a bipolar junction transistor do not scale down since they are already low. Gate delay times in a digital circuit may be expressed in general form as t - GOV/J (1-1) d where Co is the capacitance per unit area to be charged and discharged over a voltage range V by a current density J. Since Co increases with scaling due to decreasing depletion layer widths, the current density must also increase to avoid increased delay times. The combination of higher current densities and unscaled voltages result, in turn, in a higher density of dissipated power and hence, larger operating temperatures. Current densities as high as 1.3X1OS A/cm2 have been reported in high performance bipolar switching circuits that have been fabricated with VLSI device dimensions [1]. At such current levels, SBD models which incorporate minority carrier injection effects are required. Minority carrier injection is further pronounced in guarded SBDs in which p-type guard rings are used to avoid undesirable effects associated with high electric fields at the electrode edge. Injection of minority carriers leads to excess carrier storage in the bulk of the device. The stored excess carriers, in turn, change SBD characteristics in two principal ways, as illustrated in Figure 1-1. Static current-voltage characteristics are altered because of conductivity modulation induced by excess carriers, and dynamic properties are modified due to carrier-storage induced switching delay times. So, in circuits operating at high current densities, minority log I A (a) r FORWARD V d. REVERSE Delay (b) Figure 1-1 Minority carrier injection results in excess carrier storage which changes device characteristics in two principal ways. (a) The bulk conductivity is modulated. (b) Switching delay is induced. carrier injection has to be properly considered for its effects on the value of the bulk conductivity as well as the added switching delay. Another motivation for understanding the phenomenon is the possible latching of an integrated circuit Schottky diode and an adjacent npn transistor caused by minority carrier injection, due to a mechanism similar to the latching of a silicon controlled rectifier (SCR), [2]. The purpose of this study is to provide experimental quantification of minority carrier injection in planar platinum- silicide Schottky barrier diodes and to correlate the results with a numerical device simulation in order to aid in establishing correct device models. Specifically, two experimental measures of minority carrier injection are investigated. First, the charge due to stored minority carriers is measured by current integration during the diode switching transient from forward to reverse bias. Secondly, the conductivity modulated forward I-V characteristics of the device are measured under large forward bias conditions. The results are then correlated with a numerical simulation of the basic equations governing carrier transport in the device. 1.2 Preview of Contents Chapter 2 covers the background material, starting with a brief discussion of the physical structure of an SBD and various mechanisms of current transport in the device. Then, the attention is focused on minority carrier injection in SBDs, discussing its effects and reviewing the previous theoretical and experimental studies of the phenomenon. Chapter 3 presents the experimental part of the study. Specifically, a measurement technique is described which detects the pico-coulombs of charge associated with minority carrier storage, which discharge in nanosecond time frames, for current densities as high as 105 A/cmz. Additionally, a method is described to measure conductivity modulated forward J-V characteristics for current densities as high as 4 X 105 A/cmz. The experimental results, along with the experiment’s limits and accuracy are presented after the discussion of each measurement method. Chapter 4 describes the theoretical simulation, starting by discussing the basic theory of carrier transport in the device. Then the approach to the solution of the problem by previous investigations is briefly discussed and finally, other phenomena beyond the previous work are explored and new corrections are made.to the traditional theory. Specifically considered are energy gap shrinkage, hole barrier height lowering, and hole tunneling at high injection, all of which result from the effect of the image-force on the valence-band in silicon near the junction. Additionally, a method is presented to correct the one dimensional simulation for the lateral voltage drop in the n+ buried layer. An important parameter in the numerical simulation is the value of the barrier height of the device. Since the value of the barrier height depends on the processing involved in the fabrication of the device, It must be measured for the devices under study. Chapter 5 describes various I-V methods for the measurement of barrier height and demonstrates shortcomings of each method theoretically as well as experimentally. A modification of one of the methods is then proposed which provides highly accurate results for the value of the barrier height. This method is then used to determine the barrier height at four temperatures. Chapter 6 is devoted to the comparison of the experiment and simulation results. First, the correlation between experiment and theory based on the traditional simulation is examined and shortcomings of the simulation are demonstrated. Subsequently, lateral voltage drop, hole barrier height lowering, image-force induced energy-gap shrinkage, and Auger recombination are considered separately and the effect of each phenomenon on correlation of simulation and experiment is observed Finally, high temperature comparison of simulation and experiment is discussed. Chapter 7 includes the summary and conclusions of the work and discusses recommendations for further studies of the phenomenon. The chapter is followed by three appendices which contain the details of various experimental procedures (Appendix A), and derivations of some of the theoretical results developed in this work (Appendices B, C). 1.3 Main Contributions of this Work This thesis presents a comprehensive study of minority carrier injection in Schottky barrier diodes by direct measurement of both minority carrier storage and forward J-V characteristics, correlated with numerical simulation. Such a study has not been previously reported. Furthermore, the experiment extends reverse-recovery minority carrier storage measurements to current densities several orders of magnitude higher than previously reported [3]. Theoretically, modifications of some forward I-V methods for determining the barrier height of an SBD are developed to improve their performance, and one modification is shown to generate highly accurate results. The numerical simulations were performed by C.C. Yu [4] at IBM corporation. The contributions of this work to the simulation were the inclusion of effects due to hole barrier lowering, energy gap shrinkage, Auger recombination, and buried-layer lateral voltage drop. CHAPTER TWO BACKGROUND 2.1 Introduction A metal-semiconductor contact may show rectification properties or the characteristics of an ohmic contact depending on the choice of metal and semiconductor as well as the impurity concentration in the semiconductor and the processing involved in its fabrication. The asymmetric nature of electrical conduction between metal contacts and semiconductors such as copper and iron sulphide was first discovered in the late 19th century and while the rectification mechanism was not understood, contacts between metal points and metallic sulphides were used extensively as detectors in early experiments on radio. The rapid growth of broadcasting in the 19205 owed much to the "cat's-whisker" rectifier which consisted of a tungsten point in contact with a crystal, usually of lead-sulphide [5]. In 1938, Schottky and, independently Mott, pointed out that the observed direction of rectification in a metal-semiconductor contact could be explained by supposing that majority carriers from the semiconductor passed over a barrier through the normal processes of drift and diffusion. Mott assumed that the barrier region of the semiconductor was devoid of charged impurities so that the electric field was constant and the electrostatic potential varied linearly as the metal was approached. In contrast, Schottky supposed that the barrier region contained a constant density of charged impurities so that the electric field increased linearly and the electrostatic potential quadratically [5]. Schottky’s assumption on the shape of the barrier conforms fairly closely to what usually occurs in practice, so that barriers associated with metal-semiconductor contacts are often referred to as Schottky barriers and contacts which have rectifying properties are referred to as Schottky barrier diodes. Modern planar SBDs are extended area contacts formed by the deposition of metal films in high-vacuum. Such planar contacts are much more stable and reproducible than point contacts. The SBD is usually fabricated using n-type semiconductors since a larger barrier height and consequently, more rectification is achieved. This chapter discusses the structure of a planar SBD, considers various mechanisms of current transport in the SBD, and then focuses on minority carrier injection, discussing its effects and reviewing the previous theoretical and experimental studies of the phenomenon. Throughout the remainder of this work, n-type devices are considered while similar arguments could be made and parallel conclusions could be drawn for p-type devices. 10 2.2 Structure of a Planar SBD In bipolar silicon integrated circuits, SBDs are fabricated as follows. A lightly to moderately doped n-type epitaxial layer is grown on a p-type substrate on top of which is a heavily doped n-type (n+) area, and then a metal layer is deposited on the epitaxial layer to form the anode. A metal contact to an n+ region that is connected to the n+ buried layer forms the cathode ohmic contact. A p-type guard ring is sometimes fabricated around the anode to eliminate undesirable leakage currents caused by the high electric fields present at the edge of the metal. Figure 2-1 shows examples of the cross sections of the guarded and unguarded SBDs and Figure 2-2 shows the energy band diagram of the planar SBD, neglecting the effect of the image force at the junction. As will be shown later, minority carrier injection is much more profound in guarded devices due to the presence of the guard ring as an additional source of minority carriers. 2.3 Current Transport Mechanisms The various ways in which electrons can be transported across the junction of an SBD under forward bias are shown schematically in Figure 2-3. The mechanisms include the emission of electrons from the semiconductor over the top of the barrier into the metal, quantum- mechanical tunneling through the barrier, recombination in the space charge region and minority carrier injection [5]. The principle mechanism of current flow in the SBD is the emission of majority carriers over the barrier which is governed by the thermionic emission, as well as diffusion and drift in the depletion 11 anode cathode 4 ‘13 ‘1" ox—f metal ox. met. ox n 5+ n n+ (a) anode cathode ‘t ? —o_x_.— metal ox. met. ox P P n '—’* 5* r1 r1+ Figure 2-1 Structure of a planar SBD. (a) Unguarded. (b) Guarded. 12 metal semiconductor cathode anode ohmic contact -1]'_ “fl’ ] ] Figure 2-2 Energy band diagram of a planar SBD neglecting the effects of image-force at the metal-semiconductor interface. The horizontal axis is not to scale. The position of the contact is denoted by x0, the position of the edge of the depletion layer is denoted by xw, and the interface of the epitaxial and the n+ buried layers is denoted by x1. Vj is the applied junction voltage and Ob is the barrier height. 13 metal semiconductor Figure 2-3 Current transport mechanisms over the metal semiconductor interface. (a) Thermionic emission. (b) Tunneling of majority carriers. (c) Recombination in the depletion region. (d) Minority carrier injection. Ob is the barrier height of the interface. 14 region of the device. The current-voltage relationship for the combined thermionic emission-diffusion process is developed by Crowell and Sze [6] and is given by ** 2 J - A T exp(-q¢b/kT) {exp(qu/kT) - 1) (2-1) where J is the current density, A** is the modified Richardson's constant, Vj is the junction voltage, and Ob is the barrier height of the diode as shown in Figure 2-3. In this work, Equation 2-1 is referred to as the ideal Schottky diode equation and the other processes of current transport shown in Figure 2-3 cause departures from this ideal behavior. Quantum-mechanical tunneling of majority carriers through the barrier and carrier recombination in the depletion region are significant at low bias. Minority carrier injection, on the other hand, is significant at high injection and introduces additional delays in the switching response of the diode. 2.4 Effects of Minority Carrier Injection Under forward bias, minority carriers are injected into the bulk of the semiconductor and travel for an average distance equal to their diffusion length before they recombine with electrons. For semiconductors with large diffusion lengths compared to the thickness of the epitaxial layer, such as silicon with a diffusion length on the order of tens to hundreds of micrometers, most of the minority carriers reach the cathode before being recombined. Therefore, minority carrier 15 injection leads to the presence of excess minority carriers throughout the bulk. In a device that is heavily forward biased, the excess hole concentration in the bulk of the semiconductor can be substantially higher than the material's equilibrium concentration. These excess holes, in addition to the excess electrons stored in the bulk to maintain quasi charge neutrality, give rise to an increase in the the bulk conductivity 0. The increase in conductivity (or conductivity modulation), A0, is given by 40 - q(#n4n + #pAP) (2-2) where An and Ap are excess electron and hole concentrations and #n and up are electron and hole mobilities. Conductivity modulation results in a decrease of the resistance of the epitaxial layer. Therefore, the diode conducts a larger value of current for a given voltage compared to the case of no modulation. The excess holes also affect the switching characteristics of the device. Upon rapid switching from forward to reverse bias, a reverse transient current, much larger than the diode’s steady-state reverse current, flows to sweep the excess holes out of the device. Figure 2-4 shows the minority carrier profile in the bulk during the transition from forward to reverse bias, and the current through the diode, during the reverse-recovery for a semi-infinite device initially under low to moderate forward bias. As shown in this figure, for times tO to t3, the reverse current remains relatively constant since the presence of minority carriers pins the junction voltage near its value prior to switching until the hole concentration at the edge of the space charge 16 >- XW X A (o) i t0 t3 t4 tm C,,C , and Minority J P Carrier Remnants R h _ —Minority Carrier Removal 03) Figure 2-4 Dynamics of reverse-recovery for a semi-infinite device initially under low to moderate forward bias. (a) Hole concentration profile. (b) Switching current. C. and C correspond to the junction and parasitic capacitances respectively. 17 region, xw as shown in Figure 2-2, becomes small. The pinning is due to the boundary condition [7]; Pn(xw) - Pnoexp(qu/kT) (2-3) where Pno is the equilibrium minority carrier concentration in the bulk. The primary source of reverse current during the exponential decay after t3 in Figure 2-4 is the discharge of the junction and parasitic capacitances. Minority carrier removal, however, may also continue as the junction becomes reverse biased, as shown for time CA. The boundary condition of Equation 2-3 is based on the assumption that the minority carrier quasi-Fermi level at the edge of the depletion region, xw, lines up with the metal Fermi level. This assumption is only valid at low to moderate injection levels and fails at high injection [8]. Additionally, the minority carrier profiles shown in Figure 2-4 correspond to a semi-infinite bulk. Therefore, the reverse-recovery response shown in this figure does not necessarily describe the exact switching behavior of a planar diode under high injection. As will be shown from switching measurements described in Chapter 3, however, the observed response is similar to that of Figure 2-4. The value of reverse current upon switching (IR as shown in Figure 2-4) is determined primarily by the equivalent resistance of the switching circuit as seen by the diode, as well as the final reverse voltage that the device reaches after switching. Therefore, IR is independent of the amount of stored minority carriers. The effect of minority carrier storage is merely to lengthen the time involved in the reverse-recovery. Consequently, the time during which IR is constant 18 (from tO to C3 in Figure 2-4) is called the storage delay time and serves as a figure of merit for the amount of stored excess minority carriers. 2.5 Review of Previous Work on Minority Carrier Injection 2.5.1 Theory Historically, the interest in minority carrier injection was initially focused on point contacts which were used as emitters in the early bipolar transistors. An example of the theoretical study of point contacts is the work by Braun and Henisch [9] who developed a closed form expression for the ratio of minority carrier current to the total current (minority carrier injection ratio). While the point contact is a good injector of minority carriers, the planar SBD shows much smaller values of minority carrier injection ratio. In 1965, Sharfetter analyzed the phenomenon in planar SBDs under steady-state dc bias and developed an expression for the minority carrier injection ratio in these devices [3]. The expression developed in his work for the excess minority carrier storage depends on the value of the recombination velocity for holes at the n-n+ interface originally introduced by Gunn [10]. His analysis was limited to low injection conditions. Others, including Chuang [7,11], Green and Shewchun [12], Wagner [l3], Masszi et. al. [14], and C.C. Yu [4] have extended the analysis to the higher injection levels as well. Chuang [7] solves the one dimensional steady-state dc carrier transport equations analytically and develops implicit equations to calculate the total amount of minority carriers stored in the device. 19 The boundary conditions used to obtain the analytical solution, however, limit the results to moderate injection levels. His solution is based on the use of boundary conditions at the edge of the depletion region xw, and the n-n+ interface, x1 (see Figure 2-2). In particular, he assumes a constant velocity, independent of the hole concentration, for holes at the n-n+ interface, x1. This assumption is also used by Sharfetter for low injection conditions [3]. At xw, the boundary condition used in reference [7] is based on Equation 2-3. As discussed previously, this boundary condition is obtained by using the assumption that the quasi-Fermi level for holes is essentially the same as the metal's Fermi level. So, to the extent that the assumptions made to obtain these boundary conditions fail under high injection, Chuang’s results are limited to moderate injection levels. In fact, in a recent publication [8], Chuang and Wagner reported that under high injection, the hole quasi-Fermi level is significantly lower than the metal's Fermi level. It must also be noted that the charge associated with the total excess minority carrier storage, Qp’ obtained from Chuang’s equations, reflects the total charge between xw and x1 and does not include the depletion region or the n+ region. In another paper [11], Chuang developed an analytical expression for the I-V characteristics of the planar SBD which was shown to give accurate results for current levels extending to high injection (up to 104 A/cmz). That work, however, did not produce a solution for the amount of charge associated with the stored excess minority carriers. Green and Shewchun [12] solve the one dimensional equations numerically, under both steady-state dc and small signal ac conditions. The dc solution is used to get the the total minority carrier stored Charge, Qp’ and the ac solution is used to obtain a small signal 20 equivalent circuit model for the device. Their choice of device structure is somewhat different from what was previously discussed. Specifically, they do not have the n+ buried layer in their analysis. In other words, the cathode ohmic contact is assumed to be directly connected to the epitaxial region (see Figures 2-1, 2-2). Their boundary condition for electron current at x0 is originally due to Crowell and Sze [6] and is based on the assumption that excess electrons at xo travel to the metal with an average velocity equal to their thermal velocity. The boundary condition used by Green and Shewchun on hole current at xo assumes that the above argument is true for holes at that point as well, and the boundary conditions applied at the ohmic contact assume no excess carriers there. The method presented by their work can be limited in two ways. First, by neglecting the n+ region, the effects of the n-n+ interface as well as the minority carrier storage in the n+ region are not accounted for. Secondly, the boundary condition on hole current applied at xo does not consider the effect of image force on the valence band which results in an energy gap shrinkage near the barrier and also leads to hole barrier height lowering and tunneling of holes through the barrier at high injection. The effect of image force on the valence band near the barrier will be discussed in detail in Chapter 4. The numerical simulation described above was later used by Clark et. al. [15] to explain the difference between minority carrier injection behavior of point contacts and planar devices. A simulation similar to the work of Green and Shewchun was also used by Wagner [13] to develop a large signal model for the device. His model consists of ideal diodes, resistors, capacitors, and a constant current source and, since the model was developed to match the simulation results, the 21 limitations of the simulation as described above, apply to the model as well. Recent modifications of the numerical simulation include the work by C.C. Yu [4] who considered the n+ region of the device and the work by Mosszi et. al. [14] who considered the effect of hole barrier lowering at high injection on the hole current boundary condition. 2.5.2 Experiment Early experimental work on minority carrier injection in SBDs also focused on point contacts and is reviewed by Henisch [l6] and Smith [17]. For example, the original Haynes—Shokley experiment studied hole injection from a metallic point rectifying-contact on n-type germanium [18]. Experimental observations of minority carrier induced conductivity modulation in planar epitaxial silicon SBDs have been reported in the literature. An example is the work by Jager and Koseak [19] on 45 pm diameter devices for current densities up to 103 A/cmz. Also, metal emitter transistor structures have been used to measure minority carrier injection in planar silicon SBDs by Yu and Snow [20] and in GaAs SBDs by Chan et. al. [21]. Direct measurement of minority carrier storage in planar SBDs, based on the reverse-recovery experiment, has only been reported for low injection conditions (10 A/cmz) by Sharfetter [3]. The technique involves the integration of the reverse-recovery current with respect to time to obtain the total charge removed from the device upon switching. Subsequent correction of the total charge for the charge associated with the parasitic and junction capacitances then yields the charge associated with the excess minority carriers. The difficulty of 22 this measurement is due to the fact that, unlike p-n junctions, planar SBDs are primarily majority carrier devices and minority carrier injection corresponds only to a small fraction of the total current flow. Consequently, reverse-recovery of the switching response usually lasts, at most, on the order of nanoseconds and hence, high time resolution circuits and test devices with low values of parasitic capacitance are required for such measurements. The reverse-recovery method is used in this work to measure the excess minority carrier storage in the device and will be explained in greater detail in Chapter 3. Various methods have been used to measure the storage delay time in p-n junctions and, while the time scales of interest for SBDs may be small compared to p-n diodes, the same experimental methods are applicable in principle to SBDs. The most common and straightforward method is to switch the diode from forward to reverse bias and observe the diode current during the transient [22]. As discussed in section 2.4, the storage delay time corresponds to the time between t0 and t3 as shown in Figure 2-4. Various circuits reported in the literature for this type of measurement differ mainly in the circuits used to control the amplitude of the forward and reverse current upon switching [23,24,25]. This method has been used by Zetter and Cowly [26] for qualitative observations of minority carrier injection in SBDs. Dean and Nuese [27] reported a "refined" step recovery method in which the switching diode is the terminating load on a single 50 O coaxial line of arbitrary length. The method involves the observation of the incident and reflected waveforms of a single transmitted pulse using a high impedance probe. During the storage delay time, the diode is highly conductive, and the reflection coefficient is negative. After 23 the storage delay time, the diode approaches an open circuit in an exponential fashion and the reflection coefficient approaches unity. Consequently, the reflected signal can be used to obtain the storage delay time. This method was used by Dean and Nuese to measure storage delay times on the order of nanoseconds in GaAs p-n junctions. An advantage of this method is that only one electrical line is required to contact the test diode. The one-port connection makes it easy to vary ambient conditions, such as temperature. A disadvantage is the requirement of a high impedance probe. The fastest sampling probes are 500 rather than high impedance. A double pulse experiment has been used by Silver et. al. [28], to avoid confusion between true storage delay currents and displacement currents due to capacitance. The method is useful for special cases where displacement currents are usually large, but it was not reported to achieve very high time resolutions. The last measurement method to be discussed here was developed by Krakauer [29]. Unlike the methods previously discussed, which observe the response of the diode to input pulses, this method excites the diode with a sinusoidal input. Figures 2-5 and 2-6 show SPICE simulation results of the response of a diode to sinusoidal excitation. Figure 2—5 shows the response of a device with purely capacitive charge storage corresponding to a linear reverse-recovery current. Figure 2-6, on the other hand, shows the response of a device in which some minority carrier storage is present. As shown in this figure, the reverse-recovery current due to excess minority carriers can easily be distinguished from the linear capacitive current. Krakauer developed an expression, for a figure of merit concerning the excess minority carrier storage in the device, which is related to the exciting 24 C 20 " 10 F A A A _ r \ / \ a : / J E, 0 '- \v 3.’ : Purely Capacitive ’5 - Discharge U r -lO C -20 LllLlLll llJLllll lJLl 111L 0 5 10 15 Time (ns) Figure 2-5 SPICE simulation results for the current through a diode excited by a sinusoidal signal when minority carrier storage is not present. 25 II I 20 t t- 10 / " ,4 _ I ‘\\\ ‘\\Y 5 ' I ” Capacitive t : r Discharge 3 Q -10” Minority b Carrier C Removal -20 _ ”1.11 1 111 11 11 1 1 1 11 1 1 1 11. 11,1 1 O 5 10 15 Time (ns) Figure 2-6 SPICE simulation results for the current through a diode excited by a sinusoidal diode is significant. signal when minority carrier storage in the 26 frequency, the voltage of the source, the impedances involved in the circuit, and the ratio of If to Ir as shown in Figure 2-6. The advantages of this method are its ability to distinguish capacitive effects from excess carrier storage effects as well as the fact that the driving frequency need not be very high and, consequently, high time resolution measurement circuits are not needed. The method, however, is useful only for obtaining a figure of merit for minority carrier storage in the device and does not provide quantified information about stored charge, nor does it provide any information about conductivity modulation. Krakauer's method has been used in the literature for SBDs [30,31] as well as p-n diodes [32,33] and is also sometimes used by SBD manufacturers in their device specifications. In this study, as will be discussed in Chapter 3, the method is used for qualitative observations of the minority carrier storage phenomenon. CHAPTER THREE EXPERIMENT 3.1 Introduction As previously discussed, the two major effects of minority carrier injection on SBD properties concern modification of the switching response of the diode and modification of the forward bias I-V characteristics. This chapter describes experiments which quantify both of these effects, and provide a basis of comparison with simulation. For the switching experiment, the emphasis of both the experiment and simulation is on determining the total amount of stored excess carriers that are removed during the transient from forward to reverse bias. This is as opposed to determining the switching delay time, since there are problems with determining the delay time in both the experiment and simulation. Because of pulse noise and the effect of parasitic capacitance, an experimental determination of delay time is 27 28 to some degree subjective. Furthermore, delay time is a function of the test circuit. However, the fundamental cause of the delay time, which is the stored excess carriers, can be measured accurately and is not a function of the test circuit. For the simulation, a steady-state numerical solution provides values for the stored excess carriers but a time dependent solution, which is much more difficult to carry out, is required in order to obtain values for the delay time. Therefore, the primary thrust of the switching measurements is to obtain values for the stored excess carrier charge, rather than switching delay times which result from the stored carriers. In the process of carrying out the experiments, approximate delay times are obtained but they do not form the basis of comparison with theory. The effect of minority carrier injection on conductivity modulation is determined from the overall I-V characteristics which depend on junction characteristics as well as the characteristics of the series epitaxial layer. Direct comparison of the theoretically and experimentally determined I-V characteristics of the device provides the insight necessary to check the adequacy of the theory in treating the effects of conductivity modulation. This chapter discusses experimental methods to measure the total excess carrier storage in the device for current densities extending to 105 A/cm2 at several temperatures. The conductivity modulated J-V characteristics are also measured for current densities as high as 4x105 A/cmz. Results of such experiments are presented for unguarded and guarded devices. The primary emphasis of the work, however, is on unguarded devices in which injection over the metal—semiconductor interface is the only source of minority carriers. 3.2 Test Devices All experimental data was obtained from planar platinum-silicide epitaxial test diodes provided by IBM. The test device in the experiment using Krakauer's method was unguarded and had an anode area of 30 pmz. With that exception, the results reported here for unguarded devices are on devices with an anode area of 150 pm2 and a 1 pm thick n-type epitaxial layer doped approximately at 2.5X10l6cm-3 and grown over an n+ buried layer. The guarded SBD device area was 189 pmz. Each test diode, along with several other types of test devices, is fabricated on a 0.15 cm2 chip. Except for the Krakauer experiment, test devices had two pairs of available terminals, allowing four terminal measurements. Fig. 3-1 shows the top view of the metallization layout of the 150 pm2 unguarded SBD and Fig. 3-2 shows the doping profile of silicon under the anode of that device. 3.3 Measurement of Minority Carrier Storage 3.3.1 Experimental Method Before the excess minority carrier storage was measured, Krakauer's method, as described in Chapter 2, was used to obtain a qualitative knowledge of the current densities at which the phenomenon is significant in platinum-silicide SBDs. The sinusoidal signal which was used to excite the diode, had a frequency of about 50 MHz. Figure 3-3 shows the response of the diode for peak current values of 2.5 X 104 and 105 A/cmz. As can be seen from this figure, for a peak 4 2 . . . . Current value of 2.5 X 10 A/cm , excess minority carrier storage 15 15.7,u,m 3 a pm Cathode 3.5 fLTfl A 12 #m Anode V l2.5,u.m Figure 3-1 Metallization layout of the unguarded SBD. 31 ,021= A 20- f 0,110 E / 5 E g — _ 19 ..10 E a: .. s- : H _ C 8 18‘ =10 _ 3 a m : .5 _ D. ,3 1017 = _—_-—”/////// 1016 T l l l l l I l l l l l l fir T 0.00 0.05 0.10 0.15 0.20 x10'3 Distance from the Metal-Semiconductor Interface (cm) Figure 3-2 Doping profile of silicon under the anode of the SBD. Data from C.C. Yu [4]. Current (8 mA/div.) O Time (5 ns/div.) Current (12.6 mA/div.) O Time (5 ns/div.) Figure 3—3 Response of a 30 pm2 unguarded test device to sinusoidal excitation at room temperature. (a) Shows the response at a peak current density of 2.67 X 104 A/cm2 and does not show a significant amount of minority carrier storage. (b) Shows the response at a peak current density of 105 A/cm2 and evidence of minority carrier storage is clearly observed. 33 not observed while, for 105 A/cm2, evidence of excess carrier storage is clear. It must be noted, however, that these values of current density, which correspond to sinusoidal excitation, do not relate directly to what would be expected from switching measurements which correspond to excess minority carrier storage under the quasi steady- state dc conditions that hold when the diode is pulsed into the forward bias state. As previously discussed in Chapter 2, if an appreciable fraction of the forward bias current in the device is due to minority carriers, then upon rapid switching to reverse bias, a reverse current flows while the excess carriers stored in the quasi-neutral regions are being swept out. Integration of the reverse-recovery current yields the total charge removed from the diode. In order to determine the charge associated with stored minority carriers, the total charge obtained from the integration must be corrected for junction and parasitic capacitance stored charge. With this correction, current integration yields the charge associated with excess minority carriers stored in the device prior to switching provided that the lifetime of excess carriers is much larger than the reverse-recovery time such that excess carrier recombination is negligible during reverse-recovery. The reverse-recovery currents to be measured last on the order of nano-seconds. Therefore, the test circuit must have a high time resolution. Special care must also be taken in mounting the sample in order to avoid any significant parasitic capacitance exterior to the device. The test circuit along with its equivalent circuit is shown in Fig. 3-4. A 10 ns wide pulse at 375 Hz is used to forward bias the device from a fixed reverse bias of -2 V. The low duty cycle of the pulse helps avoid self heating in the device at high current densities. 34 PULSE DC PDVER GENERATOR SUPPLY 20 n8 [— l BIAS INSERTIDN UNIT FUNCTCIHJO-l SAMPLING USCILLUSCUPE A/D CONVERTER Figure 3-4 Diagram of the circuit for minority carrier charge storage measurement along with its equivalent circuit. Re denotes the equivalent resistance of the driving circuit and Rs corresponds to the input impedance of the sampling oscilloscope. 35 The reverse-recovery was observed on the falling edge of the pulse with a sampling oscilloscope and then digitized. The resulting fall time of the overall circuit was observed to be about 450 ps. Low-loss, low- dispersion coaxial cables with General Radio connectors were used for interconnections in the circuit. The length of the cables were chosen such that no reflections would arrive at the sampling oscilloscope while the step recovery was being observed. Additionally, the length of the cable going to the triggering input of the sampling oscilloscope was chosen such that sufficient delay for proper triggering was obtained. The coupling capacitor in the bias insertion unit provided the isolation of the oscilloscope's trigger input from the dc supply. Attenuators were used to improve impedance matching and to suppress reflections. The bare chip containing the diode was wire bonded in our laboratory and mounted in a modified General Radio coaxial sample insertion unit. The parasitics of the sample mount were observed to be negligible compared to the chip parasitics. To perform the experiment at elevated temperatures, the sample mount was heated using a hot plate controlled by a digital temperature controller which detected the sample temperature using an RTD (resistance temperature detector) sensor. Detailed information regarding the equipment used in each circuit, sample mounting, data collection, and test device integrity is provided in Appendix A. 3.3.2 Correction for the Parasitic Capacitance At low forward bias, the minority carrier injection level in a planar device is negligible [3], as verified by the Krakauer experiment previously described, and the entire switching current is due to the 36 discharge of the junction capacitance and the parasitic capacitance. Therefore, integration of the low bias current waveform provides the means to correct for capacitive stored charge. Fig. 3-5 shows idealized waveforms of the reverse-recovery associated with the low injection, primarily capacitive case, and the high injection case which includes the discharge of minority carriers. If the dominant parasitic capacitance is in parallel with the junction capacitance of the diode, then the voltage across the capacitor remains relatively constant from low to high injection since the junction voltage of a forward biased diode does not change much with increasing current. Therefore, the reverse current upon switching remains approximately constant (i.e. I = I 2R 1R in Fig. 1) since the initial conditions for discharge are approximately equal. Specifically, I1R = 12R 2 (ij - Vr)/(Req + Rs) (3-1) where ij is the voltage drop across the junction of the forward biased diode, Vr is the reverse bias voltage, and Re and Rs are the Circuit's equivalent resistors as shown in Figure 3-4. In this case, integration of the low injection waveform provides a constant charge to be subtracted from high injection charge integrations. If, on the other hand, the voltage across the dominant parasitic capacitance changes considerably, then IR increases as the forward bias level increases (i.e. 12R > 11R) and the low bias capacitive charge must be multiplied by IZR/IlR before being subtracted from the high injection charge integration. For the device in this study, IR was observed to remain relatively constant as forward bias changed and the low injection Current Time I1R 1———— (a) 11 JJ 2 a n w :3 U Time I2R —-— (b) Figure 3-5 Idealized reverse-recovery waveforms. (a) Corresponds to a purely capacitive response while (b) shows the minority carrier induced switching delay. 38 waveform integration was used as a constant correction to charge integrations. 3.3.3 Experimental Limits and Accuracy Experimental conditions were varied to check the validity of the measurement technique. To verify that during the 10 ns of forward current the diode does reach its steady-state conditions, reverse— recovery after a 14 ns wide pulse was observed and found to be the same as results associated with the 10 ns wide pulse. Also, if the effect of parasitic capacitance is subtracted correctly, then results obtained for minority carrier storage should be independent of the dc reverse bias. To verify this, the experiment was performed using higher values of reverse voltage and agreement with the -2 V results was observed. As discussed previously, if the excess carrier lifetime is not much larger than the reverse-recovery time, then some of the excess carriers recombine before they can be swept out in the reverse-recovery and they are not observed in the experiment. The lifetimes associated with trap assisted recombination are on the order of ps. Therefore, trap assisted recombination is insignificant during the reverse- recovery. The Auger recombination lifetime, on the other hand, is inversely proportional to the square of carrier density and reaches values on the order of a fraction of a ns as the carrier concentration reaches 1020 cm-S. As will be shown later in Chapter 6, for the bias range of interest, the concentration of excess carriers in the device does not reach high enough values for Auger recombination to be significant during reverse-recovery in the lightly doped epitaxial region. In the 39 n+ region, however, the doping density reaches values in excess of 1020 cm-3 and therefore, some of the excess carriers stored in the n+ region recombine before they are swept out in reverse-recovery. It will be shown in Chapter 6 that an upper bound on this effect can be determined from the simulation. The upper limit on the applied forward current was essentially imposed by the pulse generator. While the generator used in the experiment was capable of supplying more current than the maximum value of current reported here, in other words beyond 105 A/cmz, the falling edge of the pulse was too noisy and the desired time resolution could not be obtained. The test equipment was checked for proper calibration and did not contribute significant error to the data. The primary source of error was found to be due to the possibility of minority carrier discharge during the fall time of the pulse. Considering all sources of error, the reverse-recovery charge integration results are considered to have less than 5% error over most of the bias range. Measuring the temperature of the sample using two independent probes confirmed the accuracy of the temperature measurements to within one degree Celsius. 3.3.4 Minority Carrier Storage Results Typical reverse-recovery currents observed at low and high injection are shown in Figures 3-6 and 3—7. Figure 3-6 shows the low injection capacitive discharge and Figure 3-7 shows the reverse- recovery when minority carrier injection is present. Figure 3-7 shows that while the bulk of minority carriers are removed in the first two nanoseconds after switching, there is a secondary discharge which lasts 40 x10" 0.10 0 L111 .05 1111 CURRENT (A) 14 11 +111 Llll 'HME(nS) Figure 3—6 Measured reverse-recovery response of the unguarded test diode at room temperature, corresponding to a forward current density of 5.6 X 103 A/cm2 prior to switching. The waveform shows that at this level of forward current density, the discharge is primarily capacitive. 41 111! O O (n 1111 M’— O O CD 1111 / SECONDARY JISCHAREL CURRENT (A) llll -0. 10 \\\/,__/ PRIMARY DISCHARGE llll u N A u w E; HME <4-14> Where, the Auger coefficient g, has a value on the order of 10'31 cm6/S [34]. Trap-assisted recombination is the dominant recombination mechanism in silicon for low to moderate carrier densities. This process can be modeled by the Shockley-Read-Hall theory which is based on a single trap level [34]. The trap-assisted recombination rate, Rt’ is given by; 2 RC - (pn - ni)/[rp(n + ni) + rn(p + ni)] (4-15) 62 where Tp and Tn are the equilibrium hole and electron lifetimes and ni is the intrinsic carrier concentration. The lifetimes associated with this recombination process are on the order of us resulting in diffusion lengthes on the order of mm. Comparing the device dimensions (order of pm) with the diffusion length shows that trap-assisted recombination is not very significant for our analysis. The total recombination rate, R, is the sum of Rt and R A' 4.2.4 Traditional Boundary Conditions Ohmic contact boundary conditions are usually imposed at the n-n+ interface [12,13,14] with the justification that the voltage drop across the n+ region is negligible, due to the low resistivity of the n material, and that the excess carrier storage is inSignificant there. These boundary conditions are P'P and n-n (4-16-a,b) where po and no are the equilibrium hole and electron concentrations. Boundary conditions on current densities, applied at the junction, are that the electron current density at the juction is given by Jn - q (n - no) vn (4'17) where vn is the thermal velocity of electrons. Similarly, Jp - -q (p - p0) vp (4-18) 63 where vp is the thermal velocity of holes. The boundary condition on electron current density was originally introduced in a single carrier analytical solution of the device characteristics [6] and was later extended to holes and used in numerical simulations [4,12,13,14]. Equation 4-17 implies that any conduction band electron at the junction travels to the metal freely and that the average velocity for this process is the carriers' thermal velocity. The remaining two boundary conditions are the values of semiconductor potential at the cathode and at the junction. Namely, the cathode potential is zero and the potential at the junction is given by 45(0) - V - q (Rb ° A(V) ) (4-19) where ob is the barrier height of the junction, AG is the image-force induced barrier lowering, and V is the applied bias. Equation 4-19 is based on the assumption that the semiconductor near the cathode is degenerately doped such that the Fermi energy is approximately at the edge of the conduction band. 4.3 The Effect of Image-Force on Boundary Conditions 4.3.1 Energy Bands Near the Barrier The image-force is an attractive force induced on a charged particle near a metal surface. This force results in lowering of the potential energy for charge carrier emission when an electric field is applied (Schottky effect) [34]. Considering an n-type semiconductor, the effect of image potential on the conduction band, which results in 64 the lowering of the electron barrier height, is widely accepted and used in the literature to analyze Schottky barrier characteristics. Consideration of the corresponding effect on the valence band is due to Inkson [35,36] who noted that the combination of the image potential effect on both bands indicates a collapse of the bandgap very close to metal surface. Although some spectroscopy results have been interpreted as supporting Inkson in a qualitative fashion [37,38,39], this theory applies macroscopic relations to microscopic dimensions and therefore, may not be valid very close to the junction [38,39]. As will be shown later, however, the point of interest where the junction boundary conditions are applied is several atomic layers away from the actual interface and the macroscopic relations are valid. In what follows, the effect of image-force on the bands is considered under low bias before flat-band condition and under high bias beyond flat-band. 4.3.2 Low Bias Condition Under bias conditions below flat-band, the image potential causes a peak in the conduction band near the barrier as shown in Figure 4-1. The position of the peak, xm, is effectively the starting point of the simulation which, as discussed previously, is several atomic layers away from the junction. As a result of the electron image potential, the barrier height of the junction, ob, is reduced by the barrier height lowering A0. The point xm is located close enough to the junction that the conduction band, excluding the effect of the image potential, can be approximated to be linear as shown by the dashed line labeled qu in Figure 4-1. As a result of this approximation, the position of xm coincides with where qu and the energy due to electron 65 METAL l SEMICONDUCTOR l l 1 l l‘ l l‘ l 1 I \\ l HOLE _‘\1 IMAGE POTENTIAL ,5 "m‘ f l v in “—_____ _-_-X-—. i g‘:\\ E ”’ ————————— t—_T.='52— in *11‘;,*\\ ELECTRON i’ ‘ IMAGE POTENTIAL Figure 4-1 Energy band diagram of the device near the metal- semiconductor interface under low bias conditions. Ob is the barrier height excluding the effect of barrier lowering, we is the effective barrier height which includes the effect of barrier lowering, Aw is the barrier lowering potential, and EG bulk is the energy gap of the bulk semiconductor. 66 image potential intersect as shown in the Figure. Using this fact and the symmetry between the electron and hole image potentials, it is concluded that the four energy differentials labeled as AB in Figure 4— l are all equal and have a value equal to qAé/Z. Note that for the valence band, the hole image-potential is positive and the band bends up at the interface. From a quantum mechanical point of view, the distortion in the bands near the interface results because the correlation energy of an electron in the semiconductor changes as one goes toward the metal. Consider an electron in the bulk semiconductor. It repels the other electrons away from it, leaving a hole in the electron sea. The potential gain from this correlation effect is an important part of the potential energy of the electron. Near the interface, however, the metal alters the correlation potential. Inkson has taken this into account in calculating corrected one-electron quantum wave functions. His results support the concept of opposite image potential signs for the conduction and valence bands and a shrinking gap. Referring to Figure 4-1 it can be concluded that the energy difference between the metal Fermi level and the valence band at xm is equal to the difference of the two energy levels at the junction in the absence of image potential. In other words, at equilibrium where the Fermi energy of the metal and the semiconductor line up, E - Ev(xm) = E - qé (4-20) f G bulk b where EC is the energy gap of in the bulk of the semiconductor. By bulk inspection of Figure 4-1 it is also concluded that at equilibrium, 67 Ec(xm) - Ef = qu - qAQ (4-21) and that in general, E (x ) - E - 2 AE - E - q Aw (4-22) C m Gbulk Gbulk From Equation 4-22 it is concluded that the intrinsic carrier concentration at xm, ni(xm), is higher than that of the bulk by a factor of exp(qA¢/2kT). As a consequence of this 'energy gap shrinkage’, nO and po used in Equations 4-17 and 4-18 to obtain boundary conditions on current densities are given by no - Nc exp(—q/kT (@b - Aé) ) (4-23) po - Nv exp(-q/kT (EGbulk - ob) ) - [ni /no] eXp(qA¢/kT) (4-24) where n1 is the bulk intrinsic carrier concentration and Nc and Nv are the conduction and valence band density of states. 4.3.3 High Bias Condition As the applied bias increases beyond the flat-band condition, the sign of the electric field in the depletion region changes and the image potential energy results in a minimum in the valence band at Xm as shown in Figure 4-2. Using an analysis similar to that of the low bias case, at xm as shown in this Figure, 68 IWETRJJ SEMICONDUCTOR l i‘ ' c \ l \\ l \\ l \ \ I \ \ I j)+2 HOLE IMAGE POTENTIAL *f/ f l g X -‘__: :3... .. ..-, r ‘7f ELECTRON IMAGE POTENTIAL qob EC bulk Bf /, . * -,L / QA¢ :5/ I ‘ ’V : +£=AE Figure 4-2 Energy band diagram of the device near the metal- semiconductor interface under high bias conditions (beyond flatband). Qb is the barrier height of the device, AQ is the hole barrier height lowering potential, and E is the G bulk energy 83? 0f the bulk semiconductor. 69 Ec(xm) - Ef = qéb (4-25) metal E - E (x ) - E - qo - qAP (A-26) fmetal V m Gbulk b E (x ) - E - qAQ (4-27) C m Gbulk Consequently, under these conditions, no and po used in Equations 4-17 and 4—18 are given by no - Nc exp(-q¢b/kT) (4'28) po - Nv exp(-q/kT (EGbulk - @b — AQ) ) - [ni /no] exp(qA¢/kT) (4-29) The energy gap shrinkage in this case is identical to that of the low bias condition. The barrier height lowering, however, is a phenomenon related to the valence band and hence, effects the hole injection. It is interesting to note that at Xm’ n >> no under forward bias (see Equation 4-17) while at large forward bias, in contrast, po >> p (see Equation 4-18). Therefore, at large forward bias, the effect of hole barrier height lowering on p0 is far more significant in the hole current density boundary condition than the effect of the low bias electron barrier height lowering on no, in the electron current density boundary condition. Qualitative observations concerning a reversal of band bending and barrier height lowering for holes at high bias has been made by others [13,14,40]. 70 4.4 Effect of Tunneling on Boundary Conditions A source of current flow, in addition to the thermionic emission and diffusion mechanisms considered earlier, is tunneling through the barrier. From Figures 4—1 and 4-2, which correspond to n-type material, it is evident that tunneling of electrons through the conduction band barrier at low bias and that of holes through the valence band barrier at high bias could contribute to the total current. Since the tunneling current is higher for thinner barriers, the electron tunneling current is more significant for devices with higher doping of the semiconductor. The hole tunneling current, on the other hand, is more significant for a device with lower doping levels since the flat-band condition in such a device is reached at a lower value of forward bias. The primary mechanism of forward current flow in moderately doped n—type SBDs is due to thermionic emission and diffusion of electrons. Therefore, the contribution of electron tunneling current is very small compared to the overall electron current. The phenomenon is most significant at very low bias where the barrier is narrow. The thermionic emission and diffusion induced hole current, on the other hand, is small and therefore, under very high bias where the hole barrier is sufficiently narrow, hole tunneling current could play a significant role in the overall hole injection and therefore, should be considered at such bias levels. Analytical expressions for the electron tunneling current have been developed in the literature [41,42]. These treatments are applicable under low to moderate injection levels since they assume that the forward current is proportional to exp(qu/nkT), where V. is the junction voltage, n is the ideality factor and k is Boltzmann’s 7l constant. They use a parabolic approximation for the shape of the barrier which spans the space charge region and, which can be determined from the semiconductor doping density and the applied bias. In this section, an analytical expression for the hole tunneling current is developed. The expression depends on some of the simulation variables and therefore, may be used as a boundary condition in the simulation. As discussed in the previous section, the hole barrier is formed under high bias beyond flat-band. Therefore the shape of the barrier can not be easily determined. To obtain an analytical expression for the hole tunneling current, however, it is desirable to approximate the shape of the barrier with a simple geometry. Triangular and parabolic geometries have been considered for treatment of band-to-band tunneling under high field conditions in the literature [34]. The triangular barrier approximation results in simpler expressions for the tunneling transmission coefficient than the parabolic approximation while the parabolic approximation is used to properly account for momentum transfer in tunneling mechanisms involving a change in carrier momentum. An example of such a process is band-to-band tunneling in indirect gap materials such as silicon. The case under study here involves the tunneling of carriers within the same band over the barrier near the junction. Therefore, there is no change of momentum involved. A triangle as shown in Figure 4-3 is used to model the hole potential barrier. The tunneling transmission coefficient for such a barrier is given by [34] _l/2 T<¢> = exp< <-am* /E> (th - ¢>3/2> (4-3o> 72 9% [qbbh— E(x - xmn 4’fm xm x Figure 4-3 A triangular approximation of the potential barrier for holes at the metal-semiconductor interface under high bias conditions (beyond flatband). @fm is the metal fermi potential, ébh is the hole barrier height, E is the electric field in the semiconductor, and x is the distance from the interface. 73 where E is the electric field near the barrier, ¢ is the hole potential with respect to the potential at the metal Fermi level (note that q x o is the hole energy taking Efm as the zero reference energy), m* is the hole relative effective mass, Qbh is the hole barrier height given by Equation 4-26 and a is given by 1/2 a - 913%— - 6.831 x 107 v"1/2.cm’1 (4.331) where m is the mass of a free electron and h is the reduced Plank's constant. The net hole tunneling current is obtained from the difference between the tunneling current from the metal to the semiconductor and the tunneling current from the semiconductor to metal and is given by ¢ AfgI. bh Jt - k JO Fm<¢> [1 - Fs<¢>1 T<¢> d¢ (4-32) * _AI bh 1" o FS<¢> [1 - Fm<¢>1 T<¢> d¢ where Jt is the net hole tunneling current density, Fm(¢) and Fs(¢) are the metal and semiconductor Fermi-Dirac distribution functions and A* is the effective Richardson's constant [34]. In appendix B, it is shown that using Equation 4—30 for the tunneling transmission coefficient, the hole tunneling current density at xm can be approximated by 74 Q 2 bh Jt - A T a exp<-/3¢bh> JO [exp - P/Po] x (4-33) 1/2 3/2 ] + m; exp[( -am: /E) 53/2 1 } dS * *1/2 E 5 ml eXP[( «ml / ) * * . where 6 - q/kT, ml and mh are the light and heavy hole relative effective masses, A is the Richardson’s constant for a free electron (A - 120 A/KZ), E is the electric field at xm, p is the hole concentration (which varies with x, and therefore S, since x - Xm + S/E), and po is given by Equation 4-29. The tunneling current given by this equation can be added to Equation 4—18 to obtain a more complete boundary condition for the simulation. 4.5 Correction for the Lateral Voltage Drop The one dimensional simulation discussed above assumes the voltage drop between the n+ region and the cathode to be negligible. Under high forward-bias conditions, however, the voltage drop in the parasitic resistance between the cathode and the n+ region, as well as the lateral voltage drop in the n+ region,becomes significant. The lateral voltage drop, which causes the current density in the device to be non- uniform, can be considered by modeling the device as many narrow devices next to each other as shown in Figure 4-4. As shown in this figure, resistor R is the parasitic resistance from the n+ region under the anode area to the cathode. The area under the anode is divided into m elemental diodes and the resistance of the n+ region under each elemental diode is r. Figure 4-5 shows the equivalent circuit for this model. Knowing the doping concentration distribution in the device, 7S ANDDE CATHDDE UX. METAL BX. MET. DX. Figure 4-4 Cross section of the unguarded diode and the parasitic resistances involved, used as a model for the lateral resistance correction to the simulation. 76 29m gill». Figure 4-5 The diode equivalent circuit used to correct the lateral voltage drop in the n+ buried layer. 77 values of R and r have been determined to be 4.2 Q and (6/m) 0 respectively. Using the results of the one-dimensional simulation for the current voltage characteristics of each elemental diode in the equivalent circuit of Fig 4-5, the I-V characteristics of the overall device (Vt , It) can be calculated using the following algorithm. V + rI = V V +r(Il+12)=V 2 3 V + r(I1 + I m_1 + ... + I -v 2 m-l) m Knowing the current density and the corresponding excess carrier storage in each elemental diode, the total amount of stored minority carriers vs. forward current can be calculated as well. As long as the current flow in the area between the boundaries used in the simulation is in a vertical direction (i.e. in the direction shown in Figure 5-4), this model can be used to account for the lateral voltage drop in the n+ region provided that the value of m is large enough. 78 4.6 Method of Approach 4.6.1 Approach of the Previous Work The one dimensional equations stated in section 4.2.1 have previously been solved numerically [4,12,13,14]. In these simulations, carrier generation has been neglected and recombination has been considered to be primarily trap-assisted with a rate given by Equation 4-15. The hole current density boundary condition given by Equation 4- 18 has been used and therefore, tunneling of holes through the barrier at high bias has been neglected. The hole barrier lowering has not been considered by [4,12,13] while [14] considers the phenomenon improperly. The effect of the lateral voltage drop has also not been considered. 4.6.2 Approach of this Work As discussed previously, carrier generation is significant only at very high electric fields corresponding to very high forward bias and therefore, has been neglected. For carrier recombination, the Auger process and the trap-assisted process have both been considered in the simulation. The effects of hole barrier lowering and energy gap shrinkage near the junction on the current density boundary condition have been included as well. The simulation is also corrected for lateral voltage drop in the n+ region. The tunneling of holes through the barrier, as given by Equation 4-32, has not been included in the simulation due to the added complexity to the numerical solution. As previously mentioned, the numerical solutions were performed by C.C. Yu at IBM corporation [4]. The contributions of this thesis to the ’ u.‘ .-.:‘thr 0“ - 79 simulation were the inclusion of effects due to hole barrier height lowering, energy gap shrinkage, Auger recombination, and buried layer lateral voltage drop. The simulation results are to be presented later in Chapter 6 in the context of comparison with experimental results. 4.6.3 Parameter Determination The various parameters in the differential equations and the boundary conditions are related to the material properties as follows; i) Carrier mobilities in the Yu simulation are related to the doping density as well as temperature and the electric field. Empirical functions relating the mobility with the above variables developed by [43] have been used to determine the mobility at each point in the device for a given bias level. ii) Einstein’s relation has been used to relate diffusion coefficients with carrier mobilities. iii) The electron and hole thermal velocities vn and vp are obtained from [34]; * 2 vn - A T /qNC (4-34> * 2 vp - A T /qu (4-35) iv) The image-force induced barrier height lowering, Aw, is given by [34]; V) 80 AT - [qE/anes]l/2 (4-36) where E is the electric field in the semiconductor near the barrier and 63 is the dielectric constant of the semiconductor. Due to the formation of platinum-silicide at the interface during the fabrication of the device, the barrier height of the device depends on the temperatures involved in the fabrication process [34]. Therefore, the value of the barrier height must be experimentally determined for the devices under study. The various measurement techniques and their corresponding results are addressed in the following chapter. CHAPTER FIVE BARRIER HEIGHT DETERMINATION 5.1 Introduction The barrier height of a Schottky diode is an important parameter in the simulation of the device and a variety of methods have been developed for its measurement. These methods include capacitance vs. voltage measurements, photo-electric emission measurements, and current vs. voltage measurements. However, when the Schottky diode test device is a part of an LSI/VLSI integrated test site, one is often limited to current-voltage measurements. This is due to the fact that in such a test structure,- there is no optical access to the device and the parasitic capacitance of the test structure often overwhelms the small junction capacitance of the SBD. Such is the case for the test devices used in this work. The most traditional methods for evaluating the barrier height from I-V data are the activation energy method and the Richardson's 81 82 constant method both of which rely on obtaining the saturation current from the linear portion of a semilog plot of the I-V data where the effect of the parasitic series resistance is negligible. A third method, originally proposed by Norde [44] and later modified by others [45,46,47], has the advantage of tolerating a large resistance in series with the device. These three methods generate results with discrepancies, sometimes on the order of tens of millivolts [47,48]. Considering the fact that small errors in the value of barrier height result in large errors in the theoretical simulation of the device and also, in light of the fact that the value of barrier height for a device depends on the processing involved in its fabrication [5,34], it is desired to have I-V methods which generate reliable and consistent results. This chapter discusses some limitations to each method and develops more general forms for Richardson’s constant method and Norde's method which account for effects due to the barrier lowering phenomenon. The results of each approach are compared for our test devices which, as discussed earlier, are platinum-silicide Schottky barriers on n-type epitaxial silicon. Checking each method for self- consistency shows that for these devices, the modified Norde’s method gives the most accurate results. 5.2 Barrier Height Lowering and the Ideality Factor The ideal Schottky equation based on thermionic emission—diffusion theory, and ignoring the effect of barrier height lowering, is given by [34] 83 I = IS exp(flVj) = Ae A** T2 exp(-fi@b) exp(flVj) (5-1) for Vj > several 5-1 where 5 = q/kT, Ae is the effective area of the *5? junction, A is the modified Richardson’s constant, and Qb is the barrier height. The voltage across the junction, Vj, is given by Vj = V - RI (5-2) where R is the parasitic series resistance of the device. In this chapter, the saturation current term, IS, is generically used as a prefactor in front of the exp(fiVj) term. As additional physical phenomena are considered, the specific expression for Is changes from that in Equation S-l. It is common practice to approximately account for many of the effects by which the diode characteristics deviate from Equation S-l (i.e. non-ideal effects) by a non-rigorously introduced and empirically determined constant called the ideality factor n such that I = C €XP<fiVj/n) (5-3) where C is a constant of proportionality. For forward biased junctions, most of these non-ideal effects are significant at low bias. Low bias non-ideal effects include barrier height lowering, quantum mechanical tunneling of carriers through the junction, and recombination of carriers in the depletion region, all of which result in currents in 84 excess of what is given by Equation S-l. The effects of drift and diffusion of carriers in the space charge layer and minority carrier injection, on the other hand, are significant at very high bias corresponding to large current densities [5]. With the proper choice of C and n, Equation 5-3 can be used to approximately describe the behavior of a given diode. However, when using current voltage data to provide diagnostic information about the barrier, it is necessary to treat this equation with caution since different barrier structures can result in the same value of 0 over a given range of current [49]. Also, for n > 1, interpreting the value of C as the saturation current given by Equation S-l results in a low value of barrier height since C > Is. Figure S-l shows a plot of Equation S-l and a hypOthetical set of observed data with exaggerated non-ideal effects to demonstrate this point. One important 'non-ideal’ effect which is unavoidable is the barrier height lowering, Aw, caused by the image force at the junction. This effect gives rise to an effective barrier height, @e, as below; é V. = T - T V. 5-4 e(J) A <> b Assuming no interfacial layer at the junction, Q is independent of b voltage [5]. However, barrier height lowering, Aé, and therefore 68, are voltage dependent. Correcting Equation 5-1 for barrier lowering RR I = Is exp(fiVj) = AeA T2 exp[-fl ©e(Vj) ] exp(fiVj) (5-5) 8S CURRENT DENSITY (A/sz) .. ‘ S . : . T 1 T 0.0 0.2 0.4 0.6 POTENTIAL (Volts) Figure S—l A hypothetical set of observed data with exaggerated non- ideal effects is shown by X. (a) shows a plot of Equation 5-3 with the best fit to the data (n -l.l). (b) shows the plot of the ideal diode equation (Equation S-l). The excess current due to non-ideal effects is denoted by AI. The non-ideal effects cause the extrapolated current density intercept, C/Ae, to be greater than Js- Is/Ae for Is as given by Equation S-l. 86 In the absence of other non-idealities, Equation 5-5 is an exact relation which, as will be shown, forms the basis of our modified Norde's method. The activation energy method and the Richardson's constant method, on the other hand, require fitting experimental data to an equation with a voltage independent value of Is. For real Schottky diodes, however, Is is voltage dependent as seen from Equation 5-5 and therefore, these methods have to utilize an approximation of Equation 5-5. In some treatments, the effect of barrier lowering on forward I-V characteristics has been folded into the ideality factor n [5,34] such that I = 15 6Xp(flVj/r)) (5-6) ** 2 where IS - Ae A T exp(-fl¢e(0)) (5-7) However, this approach has inherent disadvantages as may be seen from the following discussion. Equation 5-5 can be written as I = A8 A*‘ T2 eXP[-fl ¢e<0>1 exp[ fi> 1 <5-8) where, f(Vj) = ¢e(Vj) - ¢e(0) (5-9) Obviously, 5(Vj - f(Vj)) could be written as fiVj/n if f(Vj) was 1/4 linearly proportional to Vj. However, f(Vj) goes only as Vj and 87 hence, is far less sensitive to changes in junction voltage than a linear relation. In Appendix C, a method is developed to better approximate the voltage dependence of barrier height as below; I I v * A A**T2 o v +AO v v T v * (5 10) =' sexpw j/’7 ) - e eXP{-fi[ e( m) (m). m] GXPW J./77 ] - * O -l and n = [l + A¢(Vm)] (5-ll) where n* is the ideality factor due to barrier lowering, Vm is the mean value of the range of voltage to which the above equation is applied, and A5(Vm) is the first order derivative of AT evaluated at Vm. The barrier lowering A¢(Vj) of an n-type device is given by [5] 1/4 A¢(vj) - {q3ND/8wze: [vC - vj -1/3] ) (5-12) where as is the semiconductor dielectric constant, the equilibrium contact potential, V0, is given by Vc = Qb - (EC - Ef)bulk and ND is the doping concentration. Furthermore, (EC - Ef)bu1k = 1/5 ln(NC/ND) (5-13) 88 where NC is the effective density of states in the conduction band. 3 3 2 l/4 so, A©(Vj) = {q ND/8n es [Qb - Vj- l/fl (l + ln(NC/ND) )]} (5-14) -3/a - 3 2 3 1/4 and, A¢(vj) = -[q ND/32n es] [eb- Vj-l/fi (l+ln(NC/ND)] <5-15) 5.3 The Activation Energy Method The activation energy method is based on Equation 5-7 which assumes that the voltage dependence of barrier height lowering can be accounted for by the ideality factor n. Equation 5-7 can be written as [34] ln(Is/T2) - 1n(Ae A**) - (q/KT) ¢e(0) (5—16) In order to apply this method, values for IS are obtained from the abscissa intercept of the linear portion of the log(I)-V plot of the experimental data at several temperatures. Subsequently, as can be seen from Equation 5-16, the slope of a semilog plot of Is/T2 vs. l/T yields the zero bias effective barrier height ¢e(0). The advantage offered by this method is that knowledge of either the Richardson’s constant A** or the diode's effective area A8 is not necessary [5,34]. However, small but systematic deviations of the 89 experimentally determined value of Is from what is given by Equation 5- 7, caused by the voltage dependence of we and other non-idealities as previously discussed, may lead to appreciable changes in the slope which results in erroneous calculated values for the barrier height. Equation 5-10, which is a better approximation of the voltage dependence of the effective barrier height, may not be used for this method since the mean value of the range of measured voltages, Vm, usually varies with temperature. The temperature dependence of the barrier height may also lead to additional error in the value of the calculated barrier height. Rhoderick [5] has considered the case where we depends on temperature due to the temperature dependence of work functions and shows that to the extent that the effect can be approximated by a linear relation, the activation energy method yields the value of ¢e(0) at zero temperature. 5.4 The Richardson's Constant Method The standard Richardson's constant method is also based on Equation 5-7. However, this approach uses the values of A‘ and Is at a given temperature to calculate @e. A potential disadvantage of this method is ** that the value of A which depends on the electric field, must be ** known. However, A is well known for silicon Schottky diodes [34] and is relatively constant (=llO A/cmzK2 for n-type Si) over the range of .1. electric field present at the contact (see [50] for values of Ax“ for 9O GaAs). Additionally, the value of Qe obtained from Equation 5-7 depends AA - on the logarithm of A and is therefore, insensitive to variations in AA the value of A As has been previously discussed, however, Equation 5-7 is based on the assumption that the barrier lowering effect can be incorporated into a diode ideality factor, a. As shown in section 5.2, a more accurate approach of accounting for the effect of barrier lowering is to use (see Equation 5-10) O V + AT V V = l B In A A T I 5 17 e( m) ( m)' m / ( e / s) ( - ) where again, values of IS are obtained by extrapolating the abscissa intercept of the log(I)-v plot. This forms the basis for obtaining Qb in a modified Richardson's constant method. Since ¢e(Vm) and Aé(Vm) both depend on @b (see Equations 5-4 and 5-14), Equation 5-l7 gives an implicit relation for @b and may be solved iteratively. The accuracy of this method depends on the absence of other non-idealities besides barrier lowering. In other words, the experimentally determined value of n should not be larger than the value of 71x obtained from Equation 5~ll. 5.5 Modified Norde's Method The original method proposed by Norde [44] is based on Equation 5- l. The method calculates the barrier height by plotting the function 9l F(V) = V/2 - l/fl 1n(I/AeA** T2) (5-18) then finding its minimum at (V0 , F(Vo)) and finally calculating the barrier height from ob - F(VO) + vO/z - 1/5 (5-19) This method has been used in the literature as a better alternative to other I-V methods [51,52,53,54]. As originally presented, however, the method did not consider barrier lowering and assumed a unity ideality factor for the device with the justification that non-ideal effects are significant only at low values of current and therefore, can be neglected at the higher bias levels used by the method. Later, Schwartz et. al. [47] modified Equation 5.19 to account for a non-unity ideality factor. Their modification, following the discussion in section 5.2, is expected to underestimate the value of barrier height since it takes C, given by Equation 5-3 to be the saturation current Is as given by Equation 5-l. Lien et. al. [46] have used this method to first find the series resistance R, then subtract series resistance effects from the original I-V data in order to find the barrier height by the Richardson's constant method. Therefore, their method has the same limitations as discussed in section 5.4 for the Richardson's constant method. Chot [45] proposes a method which involves plotting F(V) at several temperatures and obtaining the barrier height by a slope method. Temperature-variable methods for determination of barrier height, however, are compromised by the fact that the barrier height 92 itself is temperature dependent. These modifications do not explicitly consider the barrier height lowering effect. While the assumption of insignificant non-ideal effects at high bias is true for most non-ideal phenomena, in what follows, a more general form of Norde’s method which considers barrier height lowering is developed and shows that the voltage dependence of barrier lowering plays a significant role in barrier height determination by this method. F(V) is more generally defined as AA 2 F(V) - V/a - l/fl ln(I/AeA T ) (5-20) where a is an arbitrary constant > I. In the standard Norde's method, I is expressed as in Equation 5-1. However, in this modification, Equation 5-5 which explicitly accounts for barrier lowering is used. From Equations 5-2, 5-4, and 5-5 F(V) = (l/a - 1)v-+IR + ob - A©(Vj) (5-2l) Under high bias, minority carrier injection into the bulk of the device may be significant and consequently, the parasitic series resistance, R, may be modulated. For bias values below that level, however, R is independent of bias and therefore, dF(V)/dV — (l/a - 1) + RdI/dV - dAo/dv (5-22) 93 This equation is solved for dF/dV = 0 to find the minimum (V0, F(VO)) in Appendix C and results in RIO = l/fl (a - l/S) (5-23.a) and V0 = 1/5 [ln(a - l/S)/5RIS] (5-23.b) where S - l + A§(V. ) jo and IS is given by Equation 5-5. Therefore, from Equation 5-21 a - 1 a8 - l Qb - A¢(Vjo) + F(VO) + ( )Vo - BS (5-24) where using Equation 23.a, _ ._ _ -0 Vjo Vo 1/3 (a l/S) (5 25) Equation 5-24 provides a relation for the barrier height which corrects for the barrier lowering at a specific junction voltage. Also, since A¢(Vj) depends on Qb (see Equation 5-14), Equations 5-24 and 5-25 form an implicit expression for the barrier height and must be solved iteratively. To find the best choice for a, note that (see Appendix C) [sz/dV21VO z A (a - 1)/a3 (5-26) 94 differentiating this with respect to a and setting the result equal to zero yields a - l.5. Therefore, for this value of a, the second derivative of F(V) is maximized and hence, the minimum of the F(V) plot is the sharpest and the best resolution is achieved. If, however, due to the limitations posed by the data, it is desired to have the minimum occur at a particular point, one can use Equation 5-23.b to find the value of a which makes the minimum occur at that point. In that case, an apriori knowledge of R is not necessary to obtain a since by approximating S by 1, from Equation 5-23 b V0012) - V0011) - 1/5 [In (02 - l)/(al - 1)] (5-27) So, by using an arbitrary value of al and finding Vo(a1), one can find the value of a2 which yields the desired value for Vo(a2). This method has several advantages. First, it can be applied to a device with a large series resistance (i.e. the existence of a linear region in the semilog plot of the I-V data is not required). Secondly, it can utilize data at higher bias where the non-ideal effects are negligible and finally, a may be chosen to utilize the data about a desired bias level. A potential disadvantage of the method is the fact that it only uses a few data points about the minimum V0 and therefore, is sensitive to error in that data [46]. 5.6 Results and Discussions The experimental procedure for obtaining the I-V data has previously been discussed in Chapter 3 and the results of the current 95 density vs. voltage measurements at four temperatures are shown in Figure 3-15. Table 5-1 contains the extrapolated current density axis intercept, C/Ae, and ideality factor obtained from the data by a least squares fit over the linear portion. Beyond about 0.7 volts, the current is limited by the series resistance of the epitaxial layer, which is on the order of 20 Ohms. The diode ideality factor, n is approximately 1.04 in the straight line portion of the curves which indicates that barrier lowering is not the only non-ideal effect in play. Typical values of n*, the ideality factor due to barrier lowering alone, are found to be on the order of 1.02. Consequently, as discussed previously, the activation energy method and the Richardson’s constant method underestimate the barrier height. When the values of C/Ae from Table 5-1 are used to obtain the barrier height using the activation energy method, an effective barrier height of 0.888 V was obtained. As discussed in section 5.3, to the first order, this value may be interpreted as the effective barrier height at zero temperature under zero bias. Correcting for barrier lowering results in a value of ¢b(T-0) = 0.918 V. The Richardson's constant method was used to obtain the barrier height both for the traditional method using Equation 5-7 and the modified method introduced in this work using Equation 5-17. Results are shown in Table 5-2 where it is seen that the modified method results in slightly higher values for @b as expected. 96 Table 5-1 Experimentally determined current density axis intercepts and ideality factors. Temp. oc C/Ae (A/cmz) 77 27 8.81x10‘8 1.045 85 3.23x10'5 1.046 100 1.10x10‘“ 1.042 125 7.44x10‘” 1.040 97 Table 5-2 Barrier height values obtained Richardson's constant method using Equation Richardson's constant method using Equation 5-17. Temo. °C from; (a) original 5-7, (b) modified 27 85 100 125 Barrier Height¢b in V a D .866 .871 .856 .858 .853 .856 .897 .849 98 Table 5-3 shows the results obtained by using Norde's method. Column a shows the results obtained using the originally proposed method which neglects the barrier lowering effect. Column b contains the results obtained from the method proposed by Schwartz et. al. to account for an ideality factor [47] and Column c shows the results of the modified method presented in section 5.5 which accounts for the barrier lowering effect. A value of 1.5 was chosen for a for the latter method and Figure 5-2 shows the plots of F(V) for this choice of a. The difference between the various barrier height values listed in tables 5-2 and 5-3 are significant. Noting that all the methods discussed here are fundamentally based on Equation 5-5, to check for self-consistency each of the resulting barrier heights at room temperature are used to plot Equation 5-5. Comparing these plots with the experimental data shows how accurate each method is. Figure 5-3 shows that a barrier height value of 0.881 V, generated by the modified Norde's method (Column C of Table 5-3), gives excellent agreement with the experiment. Furthermore it will be shown in Chapter 6 that when this barrier height value is used in the numerical simulation, the results also match the experimental values. The barrier height values determined by the Richardson’s constant method and the original Norde's method, however, produced considerably different results. Figure 5-3 also confirms that the modified Richardson's constant method is an improvement of the original method. The barrier height is expected to change with temperature because of the temperature dependence of the energy gap, the electron affinity of silicon, and the work function of the metal. Experimental data is available only on the energy gap temperature dependence which has a 99 Table 5-3 Barrier height values obtained from; (a) original Norde's method, (b) Norde's method modified by Schwartz et. al. [47] to account for the ideality factor n, (c) Norde’s method modified to account for barrier lowering A¢, as in this work. Temp. °C Barrier Height (#0 in V a b C 27 .866 .837 .881 85 .852 .827 .869 100 .849 .826 .864 125 .842 .819 .858 100 0.9a— 0.8—— g I 0.7—— —] wwww I] 0.0 0.2 0.4 0.6 0.8 1.0 POTENTIAL (Volts) Figure 5-2 Plots of F(V) as defined by Equation 5-20 for a-1.5 using the experimental data of Figure 3-15. 101 O N l lllllfll Um ... O lllllfll CURRENT DENSITY (A/cmz) l.LllLMd —. Ci —L - _ _ _ L»'T" _ _ _ 1 - _ _ .4 “-1 fl —4 _ __ 0 0.45 0.50 0.55 POTENTIAL (Volts) 0 L14 (1‘ C Figure 5-3 Solid lines show plots of Equation 5-5 at 27°C using the barrier height value of; (a) original Norde's and Richardson's constant method (0.866 V), (b) modified Richardson's constant method (0.871 V), (c) modified Norde’s method (0.881 V). The experimental data is marked with X. As expected, the best agreement between c and experiment is at higher current levels where the non-ideal effects are negligible. 102 linear coefficient equal to 4.7 X 10.4 eV/K [34]. The barrier height obtained by the modified Norde’s method is observed to decrease monotonically with temperature in a relatively linear fashion with a coefficient approximately equal to 2.3 X 10-4 V/K. This may be compared with a barrier height temperature coefficient of 3 X 10'4 V/K reported for photoelectric measurements on Au-Si diodes [5]. Figure 5-4 shows the agreement between Equation 5 using the barrier height values in Column c of Table 5-3 and experiment at 85°C, 100°C, 125°C. The barrier height results in Column b of Table 5-3 are significantly smaller than the values in Column c of that table which, following the discussion made on the ideality factor in section 5.2, is to be expected. This difference is also consistent with the observation made by Schwartz et. al. [47] that their modification of Norde's method resulted in barrier height values which were considerably lower than the values determined by photo response. The 15 to 17 mV difference in the values of Columns a and c in Table 5-3 show the significance of considering the barrier lowering phenomena in the modified Norde’s method. The results in Column b of Table 5-2 are also smaller than those in column c of Table 5—3 due to the error in the modified Richardson's constant method caused by the fact that the measured values of ideality factor (x 1.04) are larger than the values obtained by Equation 11 (z 1.02) (i. e. barrier height lowering is not the only significant non-ideality in this device). If the values obtained for the barrier height (Table 5-3, Column c) are extrapolated to find @b at zero temperature assuming a linear temperature dependence, a value of 0.950 V is obtained. This value is 32 mV higher than what the activation energy method gives using the 103 l02—=r— .2 NE 2 125°C 8 / If 1()_E__. 100 .2 5 85 a .- Z .1 LL] Q 44—: E 1—— Lu : a: -1 Q: — D - L.) -d X X X IIIIITIIIWIIIITETIITTITIIITT] 0.15 0.20 0.25 0.30 0.35 0.40 0.45 POTENTIAL (Volts) Figure 5-4 Comparison of experiment with plots of Equation 5-5 at elevated temperatures using the barrier height values obtained from modified Norde's method and experiment. The experimental data is denoted by X. 104 same linear relation with temperature. This discrepancy is due to the fact that, as discussed in section 5.3, the activation energy method neglects the voltage dependence of the effective barrier height as well as other non-ideal effects. To check for variations in the barrier height values obtained for different devices, the modified Norde's method was applied to data obtained for two other devices. One device showed barrier height values almost identical to the test device used to obtain the values reported here while the other device had room temperature barrier height of 0.903 V. As discussed previously, such variations from device to device are expected since the barrier height of the device depends on the processing involved in its fabrication. 5.7 Chapter Summary and Conclusions Three methods have been compared for calculating the value of the barrier height of an SBD from the forward bias I-V data. The Richardson’s constant method and the Norde's method are modified to account for barrier lowering and the modified Norde's methods is shown to generate accurate results as determined by its self-consistency demonstrated by the agreement between Equation 5-5 and experiment. The barrier height of a platinum-silicide Schottky diode is determined to be 0.881 V at room temperature and to decrease with increasing . .. -4 temperature With a coeff1c1ent of about 2.3x10 V/K. Less accurate are the modified Richardson’s constant method and the activation energy method. While the former method can generate accurate results for devices with barrier lowering as their only non-ideal effect, the 105 latter method can only be used to obtain an estimate of the barrier height at zero temperature. A comparison of the measured ideality factor and the one calculated using Equation 5-11 shows whether or not barrier lowering is the dominant non-ideal effect. Comparing the three methods, it is concluded that the following criteria may be used to choose the proper I-V method to calculate the barrier height. ** i) If the values of Ae, A , Es, and ND are known, then the modified Norde’s method which explicitly accounts for barrier height lowering, is preferred. However, the technique is sensitive to statistical error in the I-V data. *3? ii) If the values of A6, A , ES, and ND are known and the semilog plot of the I-V data has a large enough linear range such that the abscissa intercept can be extrapolated and n can be determined, but, the data is suspected of having non-negligible statistical error, then the modified Richardson’s constant method is preferred. The accuracy of this method depends on how close the measured n is to what is obtained by Equation 5-11. AA iii) If the values of A8 and A are known while either as or ND are not known, then the original Norde's method or the original Richardson's constant method may be used to estimate the barrier height. . ** . . . iv) If the value of A or Ae is not known, then the activation energy method may be used to obtain a rough estimate of the zero temperature barrier height. For the test devices used in this work, the first condition applies. CHAPTER SIX COMPARISON OF SIMULATION AND EXPERIMENT 6.1 Introduction In order to check the validity of the theoretical treatment of current transport in the SBD, which was discussed in Chapter 4, and also to check the significance of various physical phenomena in the device behavior, the results of numerical simulation are compared with experimental data. The comparison is made both for the excess minority carrier storage data and the J-V characteristics in order to provide a comprehensive diagnoses of the device behavior as related to minority carrier injection. To consider the conductivity modulation effect explicitly, it is necessary to extract the J-V characteristics of the bulk from the overall J-V Characteristics of the diode. To obtain the bulk voltage, the junction voltage must be subtracted from the measured diode voltage for every given value of current. Consequently, an accurate relation 106 107 between the junction voltage and the current through the device is required. The ideal diode equation (Equation 2-1) can be used for this purpose for low to moderate injection levels. At high injection, however, the equation is no longer valid and the junction and bulk voltages can not be separated accurately. An alternative to the explicit method discussed above, which eliminates the problem of determining the junction voltage, is simply to consider the overall J-V characteristics which implicitly includes the bulk conductivity effects. Direct comparison of the theoretically and experimentally determined J-V characteristics of the device, provides the insight necessary to check the adequacy of the theory in treating the effects of conductivity modulation. This chapter first examines the correlation between experiment and theory based on the traditional simulation discussed in Section 4.6 1. Subsequently, lateral voltage drop, boundary condition considerations such as hole barrier height lowering and image—force induced energy gap shrinkage, and Auger recombination are considered separately, and the effect of each phenomenon on correlation of simulation and experiment is examined. Throughout the steps outlined above, only room temperature results have been considered while later in the chapter, higher temperatures are examined. 108 6.2 Traditional Simulation 6.2.1 Simulation Method The traditional one dimensional numerical simulation has already been discussed in Section 4.2. In summary, the one dimensional differential equations given in Section 4.2.1 are solved subject to boundary conditions outlined in Section 4.2.4. Carrier generation is assumed negligible, and in this version of the simulation recombination is considered limited only to the trap assisted process described by Equation 4-15. Lateral voltage drop and Auger recombination are neglected in this simulation and the effect of the image—force has only been considered in relation with the conduction band. Therefore, phenomena such as hole barrier height lowering at high injection, band gap shrinkage near the barrier and hole tunneling at high injection have also been neglected. 6.2.2 Current-Voltage Comparison Figure 6-1 shows a comparison between experiment and simulation for a room temperature unguarded SBD for bias up to 1 V. In the low current region, excellent agreement is observed, but above about 103 A/cm2, the simulation predicts more current than what is measured. The good agreement at low currents, where junction characteristics dominate the diode current, primarily indicates the accuracy of the measured barrier height which was obtained from the modified Norde's method. Figure 6-2 shows the simulation results using two barrier height values which are only 22 mV different and demonstrates the sensitivity of the 109 105—— ,a - ’./"" NS 104—'— l/ a j; _ “I; 102—— f 1 5 ——- - -—— Simulated 35; l""'- Measured ‘10-.2 T I T l T I 0.2 0.4 0.6 0.8 1.0 Potential (Volts) Figure 6—1 Comparison between current-voltage characteristics of the experiment and the traditional simulation for bias up to one Volt. 110 Current Density (A/cmz) l l l l l l .2 0.4 0.6 0.8 1.0 Potential (Volts) C) I (A 0 Figure 6-2 Simulation results of the J-V characteristics showing the sensitivity of the simulation on the value of the barrier height, Qb' lll J-V characteristics on the value of barrier height. The discrepancy in Figure 6-1 between experiment and simulation at high currents, where the bulk resistance plays a dominant role, is due to the resistance associated with the buried n+ layer and the n+ contact as will be shown in Section 6.3. Measured J-V characteristics at room temperature extend to slightly beyond 3 V and 4 X 105 A/cm2. Figure 6-3 shows the comparison between simulation and experiment over this extended range using a linear scale to emphasize the high bias region and a large difference is seen for these very high injection conditions. The traditional simulation initially shows more conductivity modulation than is. measured, then a plateau in current (which is not observed experimentally), and eventually the measured current exceeds the simulated current. Clearly, the traditional simulation does not adequately model high current behavior in these test devices. 6.2.3 Stored Minority Carrier Comparison Figure 6-4 shows the room temperature simulation and experimental results for the charge density associated with stored excess minority carriers. Again, good agreement is found for low bias levels. Beyond about 1.4 Volts, or 6 X 104 A/cm2, less stored charge is measured than predicted. The experimental data is limited to maximum current densities of about 105 A/cm2 by the pulse generator, and at this current density, the simulated charge density is about 40% higher than measured. Another interesting behavior of the simulation is a peak in the amount of stored charge at a current density of about 2.6 X 105 A/cm2. 112 x105 -—- - ——- Simulated Current Density (A/cmz) Measured Potential (Volts) Figure 6-3 JoV comparison between the experiment and the traditional simulation for high injection conditions. 113 x10’4 0. B—T €0.4— E a, 0.2— — Simulated .E + Measured O -0 T l 1* I T T l I l l r l 0 l 2 3 x105 Current Density (A/sz) Figure 6-4 Comparison between the experiment and the traditional simulation for charge density associated with minority carrier storage in the unguarded device. The experimental data is obtained by averaging of the data obtained from four devices. 114 The mathematical origin of this peak is the limit on the supply of holes imposed by the hole current density boundary condition used in the traditional simulation (Equation 4-18). The same boundary condition is responsible for the plateau in the J-V characteristics that is predicted by the simulation in Figure 6-3 but not seen experimentally. Therefore, the peak in the charge storage results of the traditional simulation, shown in Figure 6-4, is expected to be an artifact not observable experimentally, had the range of experiment reached this level of current density. 6.3 Simulation Corrected for Lateral Voltage Drop 6.3.1 Simulation Method The method of correcting for the lateral voltage drop was discussed in Section 4.5. Using the algorithm discussed in that section, the current-voltage Characteristics of the device and minority carrier stored-charge vs. current were calculated. The area under the anode was divided into 36 elemental diodes (i.e. m - 36 in the algorithm) since larger values of m gave identical results. The lateral voltage drop causes the current in the device to be non-uniform and therefore, current density is a function of position. For the purpose of presentation, however, the device current for experimental and theoretical results is normalized by the diode area to obtain an average current density, J. 115 6.3.2 Current—Voltage Comparison With this modification of the traditional simulation, the J-V results are now in good agreement with experiment up to 105 A/cm2 as shown by Figures 6-5 and 6-6 which compare the experiment and the simulation at low and high bias respectively. In Figure 6-6, curve b and the data points show the simulation and experiment results. Curve a shows the simulation results without correction, and the large difference between this curve and curve b shows that the lateral voltage drop is highly significant. Curve c in Figure 6-6 shows the expected J-V characteristics in the absence of conductivity modulation. This curve was generated by treating the SBD as a series combination of a diode and a resistor as described by Equations 5-2 and 5-3. A resistance value of 180, which is the resistance of the epitaxial layer in the absence of conductivity modulation, was used in Equation 5-2. Table 5-1 contains the values of the parameters used in Equation 5-3. Comparing curves b and c of Figure 6-6 points to a considerable amount of conductivity modulation in the device. At current densities beyond 105 A/cmz, the lateral voltage drop corrected simulation produces currents less than measured, as shown in Figure 6—7. This indicates the presence of additional physical phenomena not considered by the simulation. 6.3.3 Stored Minority Carrier Comparison As shown in Figure 6-8, the lateral voltage drop correction does not appreciably change the simulated stored minority carrier results since the relationship between forward current density and stored 116 102 Simulated + Measured CURRENT DENSITY (A/sz) O l N I— __L_.. l 0 .5 0 . 6 O . 7 POTENTIAL (VOLTS) O (A O A Figure 6-5 Low bias comparison of the measured J-V characteristics with the simulation corrected for lateral voltage drop. 117 0 U" I | X POTENTIAL (VOLTS) Figure 6-6 Effect of lateral voltage drop correction to the . . . . 5 2 . Simulation for current denSities up to 10 A/cm . Curve a is the traditional simulation, curve b is the simulation corrected for the . + . . lateral voltage drop in the n buried layer, data paints shown by X are the measured results, and curve c corresponds to the expected current with no conductivity modulation. 118 X105 a 3—_ ' A -/----b C NA .- E —I U 32—— >’ d 'H -I .5 _ C Q) Q —1 CD S- "l S. 3 —I U 0 I I I ITTIITIIIITIIIIIIIIlllfirl 0 1 2 3 4 5 Potential (Volts) Figure 6-7 Comparison of the lateral voltage drop corrected simulation and experiment for an extended bias range. (a) Shows the measured results, (b) corresponds to the traditional simulation, and (c) corresponds to the simulation corrected for lateral voltage drop. 119 x10“4 0 . 6—.— N: \ Q 0 . 4—-— ii i? .1; " I/ S ,/ D 0 . 2—— ,/ §I /,/’ -—- - -—— Corrected 2 // —————- Uncorrected u - / 0 ‘ 0 I I I I I I I I I I I I ll 0 I 2 3 x105 Current Density (A/cmz) Figure 6-8 Simulation results for the charge density of stored minority carriers with and without correction for the lateral voltage drop. 120 charge density is close to being linear. Therefore, the average charge density of stored minority carriers vs. the average current density is close to the values calculated by the traditional simulation, which neglects lateral voltage drop. It must be noted, however, that the distribution of the excess stored carriers in the lateral direction is very non-uniform since the current flow in that direction is not uniform. 6.3.4 Additional Remarks Minority carrier injection is sometimes characterized by the injection ratio, 7, defined as the ratio of minority carrier current and the total current. Figure 6-9 shows the simulation results for 7 vs. forward current density. Injection coefficients close to 0.3% are obtained at 105 A/cm2. As a result of the lateral voltage drop, the current density and minority carrier storage vary significantly in the lateral direction. In fact, most of the current and most of the stored charge is due to the last few diodes in the model of Figure 4-5. Consequently, for good high injection performance, the SBD should be designed with a high anode periphery to reduce the lateral drop. A long, narrow SBD will have a more homogeneous current distribution, and presumably better reliability than a square layout. 121 0..0()3 CD :2 _ g .... 5% _ Eé II.0I12 _ 2 —l g: _ E; 0.(JOI : 1 g -I 2: - 0000 TFIIlIIIIILIVIIlIIIIlLFIII‘l 0.00 0.25 0.50 0.75 1.00 1.25 XIID5 CURRENT DENSITY (A/sz) Figure 6-9 Traditional simulation results for the minority carrier injection ratio. 122 6.4 Boundary Condition Corrections 6.4.1 The Simulation Method Further modifications to the simulation arise from the effect of the image-force on the valence band which, as discussed in Chapter 4, results in the shrinkage of the semiconductor band-gap near the metal- semiconductor interface and also leads to hole barrier height lowering and hole tunneling through the barrier at high injection. In the modification of the simulation presented in this section, band-gap shrinkage and hole barrier height lowering effects have been considered. To do so, no and po which are used in the current density boundary conditions (Equations 4-17 and 4—18) have been calculated using Equations 4-23 and 4-24 for bias levels below the flat-band condition and using Equations 4-28 and 4-28 beyond flat-band. Due to the added complexity to the simulation, the effect of hole tunneling at high injection has not been considered. 6.4.2 Current-Voltage Comparison This additional modification of the simulation has an insignificant effect on the low bias region of the current-voltage characteristics where minority carrier injection is negligible, but has an appreciable effect beyond about 105 A/cmz. Figure 6—10 shows the simulated and measured J-V characteristics of the device and shows that the modified simulation remains in excellent agreement with the experiment at low bias as expected. To observe the high injection behavior of the simulation, the J-V results are shown in a linear plot Current Density (A/cmz) —b O l (.14 123 -”- “ — - — Measured Simulated Nun—— U 4:. Potential (Volts) Figure 6-10 Comparison of simulated and measured J-V characteristics with the simulation image-force lowering. including the effects of lateral voltage drop, induced bandgap shrinkage, and hole barrier height 124 in Figure 6-11. As seen in this figure, the new modification extends the region of agreement between simulation and experiment to current densities up to 1.2 X 105 A/cmz. Furthermore, beyond 1.2 X 105 A/cmz, the modification changes the simulation results in the right direction. Figure 6-12 covers even higher values of current density and shows that the plateau in the current values of the previous simulation is no longer observed in the modified simulation. As discussed in the previous section, tunneling of holes through the barrier at high injection was not included in the simulation. The tunneling effect can potentially account for much of the difference between simulated and measured current-voltage characteristics at high injection. Tunneling of holes through the barrier results in additional minority carrier current and a larger excess carrier storage which would, in turn, result in more conductivity modulation and consequently, even higher currents. Impact ionization and shortcomings of the one-dimensional approximation could also account for some of the discrepancy between simulation and experiment at very high injection. 6.4.3 Stored Minority Carrier Comparison Figure 6-13 shows the results of the traditional simulation and the modified simulation. As is evident from this figure, at high injection more minority carrier storage is predicted by the modified simulation and the peak observed in the previous simulation is no longer observed. These observations are consistent with the J-V observations regarding an increase of current and the absence of a plateau at high injection, since the plateau in the J-V characteristics corresponds to the peak in the carrier storage results. It is also 125 x105 Current Density (A/sz) l I Potential (Volts) Figure 6-11 Linear plot of the current-voltage characteristics comparing the measured results (curve a), the simulation corrected for the lateral voltage drop only (curve c), and the simulation corrected for lateral voltage drop as well as the image-force induced bandgap shrinkage and the hole barrier height lowering (curve b). 126 x105 a b 4...... N’: ii ..... c :5 _,-- E? e 2*— Q) D H C OJ L L —I 3 L.) 0 I I 1 T'I I I I I I I I l I I I I‘ III I I l I T I I l 0 l 2 3 4 5 Potential (Volts) Figure 6-12 Plot of the current-voltage characteristics over an extended range and comparing the measured results (curve a), the simulation corrected for the lateral voltage drop only (curve c), and the simulation corrected for lateral voltage drop as well as the image-force induced bandgap shrinkage and the hole barrier height lowering (curve b). 127 x10"3 0. 151—7 ...: j 5: 0.10—— E? - Corrected , 2 _ Simulation a) —'4 C3 .. 0.05—-r E a /" 5 4 I Traditional _ Simulation 0.00 , I T I , I 0 2 4 6 x105 Current Density (A/cmz) Figure 6-13 Comparison of minority carrier charge-storage results between the traditional simulation and the simulation corrected for image-force induced bandgap shrinkage and hole barrier height lowering. 128 evident from Figure 6-13 that this modification of the simulation has a negligible effect in the range of current densities where experimental 5 charge storage data is available (up to 10 A/cmz). 6.5 Consideration of Auger Recombination 6.5.1 The Simulation Method Auger recombination in silicon is significant only at high values of carrier concentration, and therefore has been considered in the literature in simulations of heavily doped materials [55,56], as well as simulations of devices under high injection [57,58,59]. The values reported for the Auger coefficient (parameter g in Equation 4-14), vary 31 31 cm6/sec [34,55,57,S8,60,6l]. in the range of 10' to 7 X 10' To . include Auger recombination in the simulation, the corresponding recombination rate given by Equation 4-14, has been added to the previously considered trap-assisted recombination rate. A value 31 cm6/sec has been used for the Auger coefficient to obtain a of 10' qualitative measure of the effect of the phenomenon. For simplicity, the traditional simulation without the consideration of boundary condition corrections has been used here. 6.5.2 Effect of Auger Recombination on the Simulation Figures 6-14 and 6‘15 show the simulation results of the current- voltage characteristics and the minority carrier stored-charge vs. forward current with and without Auger recombination. Ignoring the peaks in charge storage and the plateaus in J—V results which, as 129 x105 3w.— - Excluding Auger Recombination «t “ Includingmeumom 1cm 8 — /--—’- ‘x 2‘____ / 5 / -I >, +4 _ 3 c d m G a— *2 I—— m g - S. 3 _ c: o I I I I I I I I T I I I I I I I I I 0.5 1.0 1.5 , 2.0 Potential (Volts) Figure 6-14 Current-voltage characteristics resulting from the traditional simulation with and without consideration of Auger recombination. 130 XI 0'4 0 . 6——— NT 8 Q 0 ' 4—— Excluding Auger >, Recombination 3" a 2 Including Auger g Recombination I; 0..2-+- S... It! ..C U -I 0"0 T I I I I I I I I' I T I *T I I 1 2 x105 Current Density (A/cmz) Figure 6—15 Minority carrier stored-charge density results from the traditional simulation with and without consideration of Auger recombination. 131 discussed in section 6.2, are artifacts of the traditional simulation, the Auger recombination is shown to have a small effect at high injection and a negligible effect at lower injection levels. Specifically, Figure 6-15 shows that in the range of current density for which experimental data is available (up to 105 A/cm2), Auger recombination is insignificant in the simulation. 6.5.3 Effect of Auger Recombination on Experiment As discussed in chapter 3, the accuracy of the minority carrier charge storage measurement depends on the ability of the switching circuit to sweep all the excess minority carriers out before they are recombined. In other words, the minority carrier lifetime must be much larger than the time involved in the reverse recovery, or alternatively, the diffusion length of the minority carriers must be much larger than the depth of the bulk. The hole lifetime, rp, and the hole diffusion length, Lp, due to Auger recombination are given by 2 Tp - l/gn (6'1) 1/2 d - 6-2 an Lp [Dprl ( ) where Dp is the hole diffusion coefficient. Tables 6-l.a and 6-l.b show calculated values of hole Auger lifetime and diffusion length for two values of carrier concentration (1018 and 1020 cm 3). Table 6-1.a corresponds to the lower limit of the 31 cm6/s), and Table 6-l.b corresponds to the the 31 Auger coefficient (10- upper limit of the Auger coefficient (7 X 10' cm6/s). As can be seen 132 Table 6-1 Hole Auger lifetimes and Auger diffusion lengths in silicon under various conditions. (a) For Auger coefficient, g - 10'31 cm6/s, (b) for g - 7 x 10'31 cm6/s. n 1018 cm’3 lozocm'3 TD 10,43 1 ns LD 1.01x10'2 cm 0.13;.m (o) n 1018 cm’3 1020 cm’3 TD 1.43/J.S 143 03 L0 3.8x10’3 cm 0.05,.m (b) 133 . l8 -3 from these tables, for an electron concentration of 10 cm , the Auger hole lifetime is on the order of us and the corresponding diffusion length is on the order of lO-3cm. Therefore, compared to a few ns of reverse recovery and a bulk depth on the order of um, Auger recombination is insignificant for this level of electron concentration. For an electron concentration of 1020 cm-B, however, Auger lifetime is a nanosecond or less and the diffusion length is on the order of 0.1 pm. Therefore, Auger recombination is significant at this level of electron concentration. Figure 6-16 shows the simulation results for the minority carrier profile in the device at a forward current density of about 105 A/cmz, which is the upper limit of the range in which experimental data for minority carrier storage is available. This figure points to two important observations. First, at this current level, the highest value of excess carrier concentration in the epitaxial region ( 0 s x s 1 pm) is only about 1.8 X 1018 cm-3. So, following the above discussion, at least up to this current density level, Auger recombination in the epitaxial region is negligible. The second observation from Figure 6-16 is the fact that a significant amount of excess carriers are stored in the n+ region ( x > 1 pm). The doping concentration in this region, as previously shown in Figure 3-2, increases from 1017 cm.3 to beyond 1020 cm- . Therefore, Auger recombination is significant in this region during the reverse recovery measurement and some of the excess carriers stored in the buried n+ region may recombine before being collected by the switching circuit. Figure 6-17 shows the simulation results for total stored-charge and epitaxial-only stored-charge as compared to experiment. As would be expected, the experimental values are between the two simulation 134 O N O ...-Q C _s on NINDRIIY CARRIER DENSITY (cm-3) l I I I 1(316 I I -I Epitaxial Layer I n Layer I I 1014 ITIIIIIIIIIIIIIFIIII 0.00 0.05 0.10 0.15 0.20 XIII'3 DISTANCE FROM JUNCTION (cm) Figure 6-16 Traditional simulation results for minority carrier profile at a forward current density of 1.1 X 105 A/cm2 (from C.C. Yu [4]). 135 x10"5 1.0 E; _ ",7, 0.5 g a g’ 1 0.0 I 0.0 x105 Current Density (A/sz) Figure 6-17 Comparison of minority carrier stored-charge density results of the traditional simulation and experiment. Curve a shows the simulation results considering the epitaxial region only, curve b shows the simulation results for the total device, and the experimental data points are shown by X. 136 - . . + results Since some, but not all, of the excess carriers in the n layer are collected experimentally. 6.6 High Temperature Comparison Figures 6-18 and 6-19 show the simulation results at 27, 85, 100, and 125 °C. The J-V results shown in Figure 6-18 show that the simulation predicts more current as temperature increases, and the minority carrier storage results shown in Figure 6-19 show that the simulation predicts more charge storage for increased temperatures. Therefore the simulation results show the same trend for device behavior vs. temperature as the experiment (see Figure 3-10 and 3-15). The agreement between simulation and experiment at elevated temperatures, however, is not as good as that of room temperature. Figures 6-20, 6-21, and 6-22 show the J-V comparison of simulation and experiment at 85, 100, 125 °C respectively, and Figures 6-23, 6-24, and 6-25 show the minority carrier charge storage comparison at those temperatures. The observed discrepancies between simulation and experiment at elevated temperatures are believed to be due to a shortcoming in the simulation to properly account for temperature dependent phenomena. All of the simulation results presented in this section (Figures 6-18 to 6-25), correspond to the traditional simulation corrected only for the lateral voltage drop since, as previously demonstrated, other corrections to the simulation are significant at current densities beyond 105 A/cm2, and the available experimental data at elevated temperatures do not exceed that level of current density. 137 Current Density (A/cmz) —b O I (A s\ F I.— Potential (Volts) Figure 6-18 Traditional simulation results for the J-V characteris- tics of the device at four temperatures. 138 x10‘3 0.15—4.— l25 0C Charge Density (C/cmz) x105 Potential (Volts) Figure 6-19 Traditional simulation results for the minority carrier stored—charge density at four temperatures. 139 105—1— 3103—— 3” .I E” 1__ Simulation Q) t -—- - -—— Experiment ,0-3 I I L I fiIIIIITIfIrnIIIIIIII 0.0 0.5 1.0 1.5 2.0 Potential (Volts) Figure 6-20 Comparison of the J-V characteristics obtained from the traditional simulation and experiment at 85 °C. 140 Simulation Current Density (A/cmz) d -- - -—— Experiment 1 0“} I I I II I I ’75 I I T *T I I I I I I I I 0.0 0.5 10 1.5 2 0 Potential (Volts) Figure 6-21 Comparison of the J-V characteristics obtained from the traditional simulation and experiment at 100 °C. 141 Simulation —-— - -—— Experiment Current Density (A/sz) Potential (Volts) Figure 6-22 Comparison of the J-V characteristics obtained from the traditional simulation and experiment at 125 °C. 142 x10‘4 02-- e - + + £01—r— + .5 .. + g. ‘ 4_ -——- Simulated 5 - + Measured 0.0 , I , I I I I jI 0.0 0.2 0.4 0.6 0.8 x105 Current Density (A/sz) Figure 6-23 Comparison of the minority carrier stored-charge density obtained from the traditional simulation and experiment at 85 °C. 143 x10‘4 0.2—— .5: ~ + + §D.I——— + g d -F 2; d 4- -——- Simulated _§ _ + Measured u + 0.0 , I , I . I r I I I 0.0 0.2 0.4 0.6 0.8 1.0 x105 Current Density (A/cmz) Figure 6-24 Comparison of the minority carrier stored-charge density obtained from the traditional simulation and experiment at 100 °C. 144 x10'4 0.2—— E - + §D.I—— + E " + g _ ——Simulated .E — + Measured t’ _ + 0-0 . I . I . I . I rI 00 02 0.4 06 08 10 x105 Current Density (A/cmz) Figure 6-25 Comparison of the minority carrier stored-charge density obtained from the traditional simulation and experiment at 125 °C. CHAPTER SEVEN CONCLUDING REMARKS 7.1 Summary of Major Results and Conclusions Steady-state dc minority carrier storage and conductivity modulated J-V characteristics of platinum-silicide Schottky barrier diodes are determined experimentally and cempared with results from a numerical simulation. The experimental method for measuring the minority carrier storage uses a high time resolution switching circuit to measure the reverse-recovery response of the diode. The reverse- recovery current is then integrated to measure the total charge swept out of the device. The total charge is subsequently corrected for parasitic capacitance effects to yield the charge associated with stored minority carriers. The reverse-recovery measurement, as well as the high current density portion of the J-V measurement, is performed 145 146 using a train of pulses with a very low duty cycle to avoid self- heating. The J-V measurement is done using a four terminal technique to avoid errors in voltage measurement, caused by the parasitic resistance of the leads connecting the device to the circuit. The carrier storage results extend to current densities as high as 105 A/cm2 and the J-V characteristics are measured up to 4 X 105 A/cmz. Guarded SBDs show considerably more minority carrier storage than do unguarded 8805. The barrier height of the device is an important input parameter in the simulation of the device and therefore, three methods have been compared for calculating the value of the barrier height from the forward bias I-V data. The Richardson's constant method and Norde's method were modified to account for barrier lowering and the modified Norde’s method was shown to generate accurate results as determined by its self-consistency. The barrier height of a representative platinum- silicide Schottky diode was determined to be 0.881 V at room temperature and to increase with increasing temperature with a coefficient of about 2.3 X 10-4 V/K. Less accurate were the modified Richardson's constant method and the activation energy method. While the former was shown to be able to generate accurate results for devices with barrier lowering as their only non-ideal effect, the latter method is only useful for obtaining an estimate of the barrier height at zero temperature. The device simulation is for the unguarded SBD, and is based on a one dimensional numerical solution of the basic equations governing steady-state carrier transport in the device. Both simulation and experiment show considerable conductivity modulation and charge storage due to minority carrier injection. The one dimensional simulation using traditional boundary conditions shows considerable discrepancy with the 147 measured J-V data at high current densities. However, when corrected for lateral voltage drop, energy gap shrinkage near the barrier, and barrier height lowering for holes, the simulation agrees with experimental current-voltage characteristics for current densities up to 1.2 X 105 A/cmz. At higher bias levels, more current is measured than predicted by the simulation. The major contributor to the discrepancy is believed to be hole tunneling at high injection which is not considered by the simulation. A boundary condition is developed which approximates hole tunneling using a WKB approximation and a triangular barrier. Two dimensional effects beyond the lateral voltage drop, and impact ionization are other potential sources of the high injection discrepancies. The stored minority carrier measurements agree with simulation up to about 6 X 104 A/cmz. Beyond that, Auger recombination in the buried layer prevents some of the stored minority carriers from being measured in the reverse-recovery experiment. The measured stored charge at high injection is found to lie between simulation results for charge storage only in the epitaxial region, and charge storage in the overall device. The fraction of forward current due to minority carriers is small. Simulation results show that the minority carrier injection ratio is about 0.3% at 105 A/cmz. However, this degree of injection causes appreciable conductivity modulation which has a large effect on the I-V characteristics. It also leads to stored charge densities on the order of 10"5 coulombs/cm2 which must be removed from the device on switching from forward to reverse bias. If reverse switching currents are on the order of 104 A/cmz, the time required to remove the minority carriers is on the order of ns. For the reverse-recovery experiments in this study, the majority of stored excess carriers were observed to 148 discharge during the first two ns, but a secondary discharge of minority carriers lasting a few additional ns was observed. For the nearly square SBDs in this study, high injection lateral voltage drops are significant and the current density is highly non- uniform in the lateral direction. In narrow devices, this effect would be reduced. 7.2 Suggestions for Further Investigations The steady-state simulation may be improved in several ways. The tunneling boundary condition, developed in this work for hole tunneling under high injection, may be incorporated in the simulation to achieve better agreement with experiment at high current densities. Also, the lateral voltage drop can be~ considered more properly by a two dimensional simulation instead of the multiple resistor model presented here. As the device area gets much smaller, edge effects become more significant and a three dimensional simulation may be necessary to account for such phenomena. While the steady-state simulation calculates the amount of excess minority carriers stored in the device, no direct information about the transients of switching, such as the primary and secondary discharge observed in this work, is obtained. A transient numerical simulation would provide such information and would prove useful in investigating possible correlations between device geometry and reverse-recovery. While device simulations provide a considerable amount of information about the expected device behavior, the ultimate objective is to develop proper circuit models, which are much simpler to use in aiding device and circuit design. Present available models are based on 149 the traditional simulation and do not account for the corrections developed by this work [13]. Therefore, a better device model may be developed. The model presented here for lateral voltage drop may be useful to that end. As shown in Chapter 6, a significant amount of the stored excess carriers recombine in the n+ buried layer before being collected by the switching circuit in the charge storage measurement. Elimination of this problem requires a significant amount of speed improvement over the already fast switching circuit. Therefore, extending the range of carrier storage data to higher current densities may prove extremely difficult. The J-V data, however, may be extended to a higher level of current density with the use of a better differential measurement set- up. APPENDICIES APPENDIX A DETAILS OF EXPERIMENT A.l Krakauer's Method The circuit used for this measurement is shown in Figure A-l. The primary purpose of this circuit was to excite the test diode with a sinusoidal input. At current levels where minority carrier injection was found to be significant, however, the continuous sine wave damaged several test devices. Therefore, instead of the continuous sine wave, a sinusoidal burst was used to reduce the average power delivered to the test device. The pulse generator shown in Figure A-l (Hewlett-Packard 214), was set to generate a train of pulses with a pulse width of 50 ps and a repetition rate of l KHz. The pulse train, in turn, was taken to the modulation input of the signal generator (Wavetek 2000) and consequently, the output of the signal generator was bursts of 150 lSl Pulse Generator Modulation input Signal Generator Amplifier Test Device Sampling Scope Figure A—l Diagram of the circuit for measurements using Krakauer's method. 152 sinusoidal signal generated every ms and lasting 50ps. The signal generator was set for a frequency of 50 MHz. The sinusoidal signal had to be amplified to generate enough current to be able to drive the test device into high injection. The amplifier used for this purpose was part of the trigger take-off circuitry of a Tektronix llO pulse generator. The output of the amplifier was used to drive the test diode which was loaded with the 500 internal input impedance of the sampling oscilloscope. A Tektronix 661 sampling oscilloscope with type 481 sampling heads was used to observe the current through the test device. A.2 Charge Integration Measurement A.2.l The Circuit The circuit used for the charge integration measurement has been previously shown in Figure 3-4. The pulse generator used in this circuit was a Tektronix 109 model with a rise time of 250 ps. This pulse generator operates by discharging a transmission line (a coaxial cable in this case) using a mechanical mercury reed switch. The pulse amplitude is determined by the voltage to which the delay line is charged , and the pulse width is determined by the length of the delay line as Figure A-2 shows. The pulser can use two delay lines, but since a low noise display on the sampling oscilloscope strongly depends on having identical input pulses and, considering the fact that it is unlikely for two delay lines to be identical, only one of the two delay lines was used. The repetition rate of this pulse generator, for a single delay line, is fixed at about 350 Hz due to limitations posed by 153 Va 100K open circuit tor-nine tlon ( 5 ns. 50 Uhn cable 0 norcury switch 50 L___ «:r—-——-——-lO IWSu————————4:> Figure A-2 A simplified schematic of the pulse generator circuit and the resulting pulse. 154 the reed switch. A coaxial cable, with the length equivalent to 5 ns of wave propagation, was connected to the delay line input to obtain a 10 ns wide pulse. Also, an external dc power supply (Universal Electronics 520A) was used to charge the delay line since the internal supply of the pulse generator was incapable of providing sufficiently high voltages. All of the connectors and attenuators, as well as the bias insertion unit were coaxial General Radio components. Also, coaxial, low loss, low dispersion, RG9 cables were used to connect the circuit components. The length of each cable, in terms of its equivalent wave propagation time, is shown in Figure 3-4. The values of cable length, as discussed in Chapter 3, was properly chosen to obtain the desired timing relation between the oscilloscope trigger input, the diode response, and the reflections due to impedance mismatches in the circuit. A Tektronix 661 sampling oscilloscope with 481 sampling heads was used to observe the diode response. The oscilloscope had a 500 input impedance and a 350 ps risetime which, combined with the risetime of the pulse generator, resulted in a total risetime of 450 ps for the observed pulse. Additionally, the oscilloscope was used in the external trigger mode and was set for 100 samples per horizontal division of display. The analog outputs of the oscilloscope’s horizontal and vertical amplifiers were used as inputs to the analog-to-digital (A/D) converter . 155 A.2.2 Data Acquisition The horizontal and vertical amplifier outputs of the sampling oscilloscope provided 200 mV for every centimeter of displacement on the CRT display. The dc offset adjustment and the horizontal position adjustment on the oscilloscope were used to match the zero level of the amplifier outputs to the desired reference location on the oscilloscope display. These output signals were also observed on a second oscilloscope (Hewlett-Packard l727-A) to ensure proper dc offset adjustment and calibration. The output signals were, in turn, taken to an IBM personal computer equipped with a Data Translation DT2801 A/D converter board for digitization, and subsequently, integration of the vertical signal (corresponding to the diode current) with respect to the horizontal signal (corresponding to time). The time involved in a single sweep of the oscilloscope trace is determined by the repetition rate of the pulse generator and the desired sample density as set on the sampling oscilloscope. In this experiment, each sweep of the trace took about 3 seconds and the A/D converter was set to take 150 samples. Therefore, a sampling frequency of about 50 Hz was used. The A/D board, however, was capable of sampling at much higher frequencies (up to 13.7 KHz). In order to trigger the sampling at the beginning of the sweep of the oscilloscope trace, The A/D board was used in the external triggering mode. The signal by which the A/D conversion was triggered, was taken from the retrace portion of the horizontal raster signal. Figure A-3 shows the circuit which was used to generate the trigger signal. The 0.01 pF input coupling capacitance was used to filter out the slowly varying sweep portion of the raster signal while 156 lOOK —— 0.010F input O———4}\L 2N4401 10K output "-' ...“, 7412l ‘5 SVOI N If— 10K l0 0.001 uF Figure A-3 Diagram of the circuit used to condition the retrace portion of the horizontal sweep raster of the sampling oscilloscope to generate a 7 ps down-going pulse suitable for triggering the A/D converter. 157 transmitting the fast retrace portion of the signal. The retrace signal was subsequently amplified by the transistor circuit and was finally used to trigger a one shot, which generated a down-going 7 us wide pulse suitable for the trigger input of the A/D converter board. The software used to control the A/D board was written in basic and made use of a real-time assembly language software package written by the manufacturer of the board, called PCLAB. A.3 Sample Mounting The initial intent was to use test chips which were mounted on ceramic subtrate using flip-chip technology. A shielded sample mount, large enough for the ceramic substrate, was fabricated so as to provide a gradual impedance change between the 50 0 coaxial lines and the diode. Essentially, this sample mount was a coaxial cavity with an air dielectric, and tapered inner and outer conductors made from brass and copper, with the test diode being a part of the inner conductor. The sample mount was tested in the charge storage measurement circuit under open and short circuit conditions and showed little apparent parasitic capacitance or inductance. However, when a ceramic substrate with the test chip removed was inserted, the open circuit and short circuit conditions showed appreciable values for both parasitic capacitance and inductance, estimated to be on the order of 2 pF and 50 nH, respectively. In order to reduce parasitics, it was decided to use bare chips (i.e. chips which were not mounted on a ceramic substrate). Thermal gold wire bonds were made to the chip solder balls at a temperature of approximately 160 °C using a West Bond wire bonder. A modified General 158 Radio type 874-X 50 0 coaxial sample insertion unit was used, since the bare chips were small enough to fit into it. The modification of the sample mount involved the use of longer center conductors machined from brass rods to minimize the length of the discontinuity of the inner conductor to a value limited by the chip size. Checking this sample holder under open and short conditions showed no significant parasitic effects and the test chip mounted in this sample holder did not reduce the circuit's time resolution. To perform the experiment at elevated temperatures, it was necessary to heat the test chip. To do so, the sample mount was heated up using a hot plate controlled by an Omega 4201 PC digital temperature controller which monitored the air temperature inside the sample mount using an RTD (resistance temperature detector) sensor. As a check, the sample temperature and the air temperature inside the sample holder were once measured using independent sensors to ensure that that the air temperature inside the sample holder does accurately reflect the sample temperature. The dielectric pellets holding the inner conductors in the GR connectors of the sample mount showed some deformity when exposed to high temperature and therefore, were replaced subsequent to every high temperature measurement. A.4 Current-Voltage Measurement Circuits used in the low and high bias current-voltage measurement have previously been shown in Figure 3-14. A Tektronix 577 curve tracer and a Fluke 8060-A digital multimeter were used in the low bias circuit. The multimeter was used in the high input impedance mode, with a value of at least 10,000 MD. 159 A Hewlett-Packard 214-A pulse generator and two Hewlett-Packard 1727A storage oscilloscopes were used in the high bias circuit. All test chips used in current-voltage measurements were mounted on ceramic substrates by the manufacturer (IBM) using fip-chip technology. To perform the experiment at elevated temperatures, the test device was heated in a Blue M oven equipped with a temperature controller. A.5 Test Device Integrity Under stressful conditions including high forward bias, the SBD may suffer degradation or damage [62,63]. occurrence of such damages during a measurement process, therefore, may result in erroneous data. To avoid this problem, all of the test devices used in various measurements were initially tested for damage. Subsequent tests of the device quality were done during various stages of each set of measurements and at the end of all measurements made on each test device.' The data obtained from any device, which did not show good properties during the subsequent quality test, was discarded. The principal method to reduce the occurrence of device damage was found to be the use of low duty cycle pulses or bursts of signal to reduce the average power delivered to the device while achieving the desired high current levels. In spite of these precautions, however, several devices were found by the quality check to be damaged before the desired amount of data was collected The criteria used to check the quality of the test device was the reverse current of the diode under a few volts of reverse bias. A 'good' unguarded device showed a reverse current on the order of one nA while stress related damage increased the reverse current, sometimes as 160 high as hundreds of pA. Efforts to restore the damaged devices by heat treatment, as suggested in the literature [62], were unsuccessful. The guarded devices showed much more robust characteristics as expected. The reverse current of these devices were found to be less than 0.1 nA which was the limit of the measurement equipment and stress related damage was rarely observed. APPENDIX B DERIVATION OF THE HIGH INJECTION HOLE TUNNELING BOUNDARY CONDITION Equation 4-31 can be written as; Q * bh Jt - A qT/k I [Fm<¢) - FS<¢>1 T<¢> d¢ - {1 + exp[ fi<¢ - ¢fm) 1} > l/fi, Fm(¢) and Fs(¢) can be approximated by; Fm<¢> - exp< ~fi¢> (3-4) FS<¢> - exp[ -fl(¢ - ¢fs> 1 3/2>] d¢ which simplifies to * 2 Qbh Jt - A T fl IO [1 - exp<fi¢fs> 1 X (B-8) 1/2 exp[ <-am* /E> (ebb - ¢>3/2 - B¢] d¢ To evaluate the term exp(B¢fs), note that 163 p - Nv expi/kT] (3-9) where p is the hole concentration, Nv is the valence-band density of states, and EV is the energy level of the valence band. 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