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' .' ‘ .74.: x. ~,_\. , ' , v " _ . . .. » - ., ,- , “3.. , .. $135373 , ' T‘ " ' "T ' ‘ {iwnly :(fiiw-«l heats p r "gdilg‘t’fi u,- 93;} x 3 $3.11?) :39?" {33 3T3 237:“ £534. "2“" 2 n, j x , l? . ' 2 l in 11331.1"; fun ‘ 553‘: " 7 ‘3‘: ' " {1‘ 31‘1"“ “3‘ . g ' x 35%; ““3“!“ "my. :1; g? ' . ‘ ,. r. A; ”'2‘. him, w; 2%% @232 w “8‘” , ' ~ ‘ i' :' .r. "'u. 2+ " ‘ WE" ”‘3 5% 3.31.3 .' 4&3: EM Y": “2'1““ ~32? , ' . ’ “r- ~n..:¢..- ¢;.. . 85‘4“? I {AM " A? Tip ‘ [Liam 531$" . ' u ‘ "r" ‘ " . gI ‘ if?) . ‘1", {2: WWW“ . “f; ié'fi ‘3.- ma? ._.;.., 4.5.1:- “" v 4‘ .- 3 ' .ex'vflr-Q‘ 11:; .L'm—I . . 7.5:: THESlS This is to certify that the dissertation entitled A MODULAR DISTRIBUTED MICROCOMPUTER SYSTEM FOR SCIENTIFIC INSTRUMENTATION presented by Bruce Hewitt Newcome has been accepted towards fulfillment of the requirements for Ph.D. degree in (Ibemistrx fléflé D Major professor FM 5: W I fi— MSU is an Affirmative Action/Equal Opportunity Institution 0-12771 MSU LIBRARIES n. RETURNING MATERIALS: Place in book drop to remove this checkout from your record. FINES Will be charged if book is returned after the date stamped below. ’ A MODULAR DISTRIBUTED MICROCOMPUTER SYSTEM FOR SCIENTIFIC INSTRUMENTATION by Bruce Hewitt Newcome A DISSERTATION Submitted to Michigan State University in partial fulfillment of the requirmente for the degree of DOCTOR OF PHILOSOPHY Department of Chemistry 1983 ABSTRACT A MODULAR DISTRIBUTED MICROCOMPUTER SYSTEM FOR SCIENTIFIC INSTRUMENTATION by Bruce Hewitt Newcome A hierircal computer system has been designed to meet the needs of chemical instrumentation. This system consists of a central minicomputer that is connected to several dedicated microcomputer systems. These microprocessor systems perform instrument control and data acquisition and then transfer the data to the host system for further data analysis. This separation of tasks allows each computer system to be specifically tailored to the tasks that it performs. A modular microprocessor system was designed to permit the easy implementation and adaptation of the computer system to the needs of the instrument. A system is assembled from a set of standard single function modules which provided the needed functions for the control system by mounting them on a dual—bus board. This board provides the local bus to interconnect the different modules in the system. Examples of the systems that have been implemented are a laser lab data acquisition system, a diode array Bruce Hewitt Newcome spectrophotometer system, and a time dispersed magnetic sector mass spectrometer. A distributed processing system was developed for instrumentation problems that require more processing power than a single microprocessor can provide. The use of several distributed microprocessors instead of a single larger processor has advantages in the areas of speed, non-interference, and flexibility. Dedicated interprocessor hardware was designed to implement the different modes of interprocessor communication. These modes of communication are block data transfer, task assignment, parameter transfer, and task coordination. A four processor system was built to control a Triple Quadrupole Mass Spectrometer. The four processors in the system are a master processor, an ion path processor, a detection processor , and a reduction processor. The master processor handles' the mass storage, communications with the operator, and controls the other three slave processors. The ion path processor controls the potentials of all of the elements in the ion path. The detection processor performs the data acquisition and the reduction processor performs peak finding in real time on the acquired data. This system is a significant improvement over a similar single processor system. To that old curse ” May you live in interesting times." ii ACKNOWLEDGMENTS I would like to thank Professor Christie Enke for his help and guidance. I am also indebted to him for the support and freedom that he provided for this work. I also thank Professor Stanley Crouch and the other members of my committee, Professor George Leroi and Professor David Fisher, for their contributions. I am also indebted to the many members of the Enke and Crouch groups for their friendship and assistance. The financial support of the Office of Naval Research and Extranuclear, inc. is gratefully acknowledged. I would like to thank my parents for their guidance and support and Professor H. V. Malmstadt and Professor Jim Avery for their initial assistance and direction. I would like to acknowledge the help of the many members of the Chemistry Department Staff that assisted in this work. Finally I acknowledge the help and friendship of my Co—conspirator Carl Myerholtz without whom this would not have been possible. For truly the whole is greater than the sum of the parts. iii TABLE OF CONTENTS LIST OF TABLESIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Vii LIST OF FIGURESIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Viii CHAPTER 1 _ -INTRODUCTIDN-I I I I I I I I I I I I I I I I I I I I I I I 1 COMPUTER IN CHEMICAL ANALYSES .................... 1 SAMPLE PREPARATION.. ........................... l INTERACTION BETWEEN THE SAMPLE AND TRANSDUCER.. 2 RECORDING THE OUTPUT OF THE TRANSDUCER ......... 3 PROCESSING AND REDUCTION OF DATA ............... 5 HISTORICAL PERSPECTIVE ........................... 5 SEPARATION INTO ANALYSIS AND CONTROL SYSTEMS ..... S COMPUTER NETWORKS ................................ 12 LABORATORY MICROCOMPUTER SYSTEM DESIGN GOALS ..... 13 SUMMARY ........... . .............................. 1o CHAPTER 2 - THE SINGLE MICROCOMPUTER SYSTEM ~...... 18 USES OF THE SECOND BUS ........................... 19 THE BACHPLANE ......................... . .......... 22 LOCAL BUS DEFINITION ............................. 24 STANDARD MODULES ................................. 27 PROCESSOR MODULES .............................. 29 MEMORY MODULES ................................. 3O iv SYSTEM SUPPORT MODULES ......................... MASS STORAGE INTERFACE MODULES. .............. .. LSI PERIPHERAL MODULES ......................... ANALOG FUNCTION MODULES .................... .... MISC. MODULES .................................. DUAL HEIGHT MODULES ......... . .................. SUMMARY .......................................... CHAPTER 3 - EXAMPLE MICROCOMPUTER SYSTEMS -........ LASER LAB DATA ACQUISITION SYSTEM ................ LINEAR DIODE ARRAY SPECTROMETER SYSTEM ........... MASS SPECTROMETER CONTROL SYSTEM ................. SUMMARY .......................................... CHAPTER 4 ~ DISTRIBUTED PROCESSING SYSTEMS -....... MULTIPLE PROCESSOR SYSTEMS ....... . ............... TASK COUPLING IN DISTRIBUTED SYSTEMS ............. TASK PARTITIONING ...................... . ......... INTERPROCESSOR TOPOLOGY .......................... INTERPROCESSOR COMMUNICATION MODES ...... . ..... DISTRIBUTED PROCESSOR DESIGN GOALS ............... CHAPTER 5 - INTERPROCESSOR HARDWARE -............. THE INTERPROCESSOR BUS ........................... DIRECT MEMORY TRANSFER PATH ................. ..... COMMAND TRANSFER PATH ............................ STATUS TRANSFER PATH ......................... .... n. u' . u .I ul 0 . 44 4S C’TI E’s. PERFORMANCE ............ ... ....................... CHAPTER 6 - TOMS CONTROL SYSTEM -.................. The TRIPLE QUADRUPOLE MASS SPECTROMETER .......... REQUIREMENTS FOR A TQMS CONTROL SYSTEM ........... THE TQMS CONTROL SYSTEM .......................... MASTER PROCESSOR ............... . ............. .. ION PATH PROCESSOR....... ..................... . DETECTION PROCESSOR ............ . ............... REDUCTION PROCESSOR ............................ DATA ACQUISITION ................................. USER INTERFACE ................................... ENHANCED PERFORMANCE AND CAPABILITIES ............ CHAPTER 7 - SOFTWARE *........................... FORTH LANGUAGE ................................... DISTRIBUTED FORTH ................................ TQMS SOFTWARE .................................... SUMMARY .......................................... CHAPTER 8 _ FUTURE DEVELOPMENTS -I I I I I I I I I I I I I I I I IDEAS FOR THE SINGLE PROCESSOR SYSTEM ........... . INTERPROCESSOR HARDWARE MODULES .................. TQMS CONTROL SYSTEM .............................. REFERENCESIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII vi 1GB 102 1GB 107 11C 112 124 126 128 133 133 137 13B 140 141 143 145 147 LIST OF TABLES PAGE The Design Goals for the Microprocessor System . 15 A List of Standard Modules ..... ....... ......... 29 Advantages of Distributed Processing Systems ... Sb Distributed Microprocessor System Design Goals . o7 Pinout of the Interprocessor Bus Cable ......... 75 Devices in the TQMS to be Controlled ........... 10? Component Modules of the Master Processor ...... 114 Modules in the Ion Path Processor ...... . ...... . 117 Modules in the Detection Processor .... ...... ... 120 Modules in the Reduction Processor ....... ...... 123 Scanning Rates for the TQMS Control System ..... 129 Selected TQMS Control System Commands ...... .... 13S vii LIST OF FIGURES FIGURE PAGE 1-1 A Typical Hierircal Computer System ............ 11 2-1 A Typical Single Microprocessor System ......... BO 2~2 The Foil Side of the Duaerus Board .... ........ 21 2*3 The Trace Side of the Backplane Board ......... . 23 2-4 The Layout of the Local Bus .................... 25 3-1 Block Diagram of the Laser Lab Computer System . 41 3-2 Block Diagram of the Diode Array System ..... ... 46 3-3 Block Diagram of the BTOF Computer System ...... SO 4-1 Distributed System Topologies ..... .... ......... 63 5*1 A Typical Distributed Processing System ........ 73 5-2 Block Diagram of the Bus Controller and Switch . 7S Sm3A Schematic of the Bus Controller .. .............. 81 5-38 Schematic of the Bus Controller ................ 82 S~4A Schematic of the Bus Switch .................... 83 5—48 SChematIC Of the ELIE SWitCh IIIIIIIIIIIIIIIIIII. 84 S~S Block Diagram of the Command Driver and Buffer . SS S-oA Schematic of the Command Driver ................ 89 waB Schematic of the Command Driver ....... . ..... ... SO S~7A Schematic of the Command Buffer ...... ... ....... 91 5*7B Schematic of the Command Buffer ................ 92 viii Block Diagram of the Status Module ....... . ..... 96 Schematic of the Status Module """""""'2' 97 Schematic of the Status Module . ...... .. ........ 98 The TQMS Instrument ........ .......... .. ........ 104 The TQMS Operating Modes .......... ............. IDS Block Diagram of the TQMS Control System .. ..... 111 Block Diagram of the Master Processor .. ........ 113 Block Diagram of the Ion Path Processor ........ 116 Block Diagram of the Detection Processor ....... 119 Block Diagram of the Reduction Processor ....... 122 Diagram of TQMS Data Acquisition ............... 125 CHAPTER 1 -INTRODUCTION- COMPUTER IN CHEMICAL ANALYSES To answer the question of how computers can be used to help the analytical chemist it is useful to examine the general processes that occur during a typical chemical analysis. An analysis can be broken down into four general stages: sample preparation, interaction between the sample and a transducer(s), recording the output of the transducer(s) as a function of other controlled or measured variables, and processing and interpretation of the data. SAMPLE PREPARATION The sample preparation stage involves operations which transform the raw sample into a state where it can effectively interact with the transducer and the elimination of substances in the raw sample that would interfere with the interaction of the transducer and the l-J component of interest. Examples of these operations include extraction, dissolution, vaporization, chemical reaction, irradiation, and gas and liquid chromatography. A computer can be used to assist in several ways with these operations. For routine analyses computer controlled robots could be used to completely automate the sample handling involved in sample preparation. Computer control of GC and LC equipment greatly increases the ease with which temperature and solvent programing can be accomplished. A less obvious way in which computers can simplify the task of sample preparation is that they enable multiple dimensions of information about the sample to be collected. When this information is cross~correlated it permits the desired information about the component of interest to be determined even in the presence of many other components. This added selectivity allows a much less pure sample to be analyzed thus decreasing the amount of sample purification that must be performed(1). INTERACTION BETWEEN THE SAMPLE AND TRANSDUCER The second stage of an analysis is the interaction between the sample and a transducer. The transducer can take many forms such as electric and/or magnetic fields, the various types of electromagnetic radiation, or chemical reactions. It can also be either a single step process, such as the interaction of the sample and electrode in an electochemical analysis or multiple step process, such as a mass spectrometer where the sample is ionized, interacts with an electric and/or magnetic field, and finally is detected by an electron multiplier. One way that computers can assist in this stage of the analysis is by allowing the use of highly nonlinear transducers. These transducers are difficult to employ without computer assisted correction of the transducer s response curve. Another possible way that computers can assist in the interaction of the sample and the transducer is that the computer can vary the conditions of the interaction in a rapid and intelligent fashion to maximize the ”real“ information that is acquired from the sample while minimizing the amount of sample required. This can result in increased precision and sensitivity in the analysis. RECORDING THE OUTPUT OF THE TRANSDUCER Recording the results of the interaction between the sample and the transducer is the third stage of an analysis. The use of a computer for recording the transducer’s output has advantages over conventional techniques in a number of different situations. One of these situations occurs when data are generated by the transducer at high rates. A modern computer system can record data at rates that are much higher that manual techniques. Another situation happens when large amounts of data are generated by the experiment. Computer systems can be very useful in this case because they allow the data from the experiment to be processed in real time, thus greatly reducing the amount of data that must be stored. A final example of a situation where computer acquisition of data is an advantage is when an experiment takes a long time to perform. Unlike most human beings, a computer can take data for days at a time without ever getting bored. Also computers can simultaneously take related or corrective data, such as temperature for a temperaturewsensitive transducer or data from multiple transducers with different selectivity coefficients(2). The computer is also capable of evaluating the quality of data in real time and thus move to the next point when the desired signal—to—noise ratio is reached or if the present datum is not of interest. A further advantage of computer data acquisition systems is that data are recorded in a machine readable form. This allows the computer to assist directly in the further reduction and processing of the data. Ul PROCESSING AND REDUCTION OF DATA A stage of the analysis where computers can have a large impact is the reduction and analysis of the raw data from the experiment. An example of analytical techniques where the use of computers have had a large impact are Fourier transform NMR and IR. The routine use of these techniques depends entirely on the use of computer systems to acquire data and to perform the Fourier transform operation. Other examples of computer assisted analysis of data are the integration of peak area for a number of instrumental methods, the deconvolution of overlapped peaks, and the use of computer searched libraries of standard compounds. A future area that has a great deal of potential is the use of artificial intelligence systems for both data analysis and experiment definitions. These experiment definitions would provide rules for intelligent real time optimization of the experimental parameters. HISTORICAL PERSPECTIVE From an historical perspective the widespread use of computers for chemical instrumentation began with the advent of the minicomputer. These were the first computers that could operate in the laboratory environment and which were directly accessible to the chemist. Minicomputers were, however, still much more expensive than many of the instruments in the laboratory. Thus, the use of a dedicated minicomputer was only justified with large expensive instruments, such as NMR or mass spectrometers, with high data rates. In an attempt to share the cost of the computer among several projects these minicomputer systems were frequently connected to a variety of different instruments(3)(4)(5). Because of the complex and expensive interfaces between the computer and the instruments, the computer frequently had only minor control over the instrument and was normally used just for data acquisition and analysis. Even with these limitations the use of minicomputers greatly increased the quantity and quality of information that could be obtained from an instrument. The next major development in the use of computers for chemical instrumentation was the development of the microprocessor. The low cost of these processors has led to an explosion in the use of computers to control chemical instruments. The use of microprocessors has become so prevalent that most new chemical instruments either come with built—in computers or have them available as options. These systems are usually built from either commercial microprocessor boards or are fully custom systems. These approaches can be justified because of the needs of commercial production. In the research laboratory where existing or custom instruments must be interfaced to computer control systems, several different approaches have been employed(o),(7). The simplest of these approaches is the use of "Personal Computers” to control chemical instruments(8),(9)(1@). This method is attractive when only a few experimental parameters need to be controlled and the resulting data rates and data volumes are small to moderate. The personal computer contains most of the needed components for a control system so only the interfaces to the instrument must be designed. The disadvantage of this approach is the lack of flexibility of the system and the cost of any unused features that are included as part of the basic computer. A second approach is the use of standard industrial computer boards(11).(12) for instrument control systems. This is a more flexible approach than the use of personal computers since a wide variety of different functions are available from different manufacturers. However, many of the available boards contain more than one function due to the fixed board size, which sometimes results in the purchase of unwanted capabilities. A third approach that has been employed in research laboratories that are interested in laboratory automation is the use of microcomputer systems that have been specially designed for laboratory control systems(13),(l4). This approach offers the greatest flexibility in the configuration of the microprocessor system but requires a large investment of time and personnel to design the needed components. This investment of time is offset by the generation of efficient and economical microprocessor systems that are readily tailored to the specific needs of the instrument. SEPARATION INTO ANALYSIS AND CONTROL SYSTEMS From the initial discussion of the use of computers to aid chemical analyses, it can be seen that there are two general areas where computers can be of assistance. These two areas are real time instrument control and data acquisition, and the interactive analysis and reduction of data that result from an xperiment. The two different classes of functions have different requirements from the computer system in terms of response time to external events and in the types of peripherals needed. The real time control applications require a rapid response time from the processor and need dedicated interfaces to the instrument being controlled. The data analysis functions on the other hand require only a moderate response time and utilize peripherals which are capable of storing large amounts of data (e.g. disk and tape drives)or that are useful for presenting data to the operator (e.g. graphics displays, printers and plotters). These differences in requirements suggest that two different computers connected in a hierarchical configuration might best meet the needs of both types of functions. This would allow each of the computers to be tailored to the different requirements of each class of functions. Examples of data analysis functions are reference library searching, correction of the raw data for background effects, transform operations that change the raw data into a more comprehensible form, signal—to-noise enhancement, correlation analysis, interactive graphical analysis of the data, and presentation and tabulation of the experimental results. A minicomputer or one of the new super—microcomputers have several features that are helpful in implementing these data analysis functions. These computers are capable of utilizing large amounts of memory, can be readily interfaced to large disk and tape drives, and can implement multi-user operating systems efficiently. This last feature allows the cost and capabilities of expensive peripherals to be shared by several users. These 1O computer systems are also capable of supporting specialized numeric and array processors which can greatly increase their number crunching ability. Interfaces for graphics displays and plotters are also readily available. Figure 1‘1 shows a typical example of this type of computer that is used as a data analysis system for several different instruments. One final advantage of separating the control and data analysis functions into different processors is that the control system can be used to collect data for a new experiment while another user is analyzing the data from a previous experiment on the data analysis system. Some examples of the types of functions that a control system can perform are the control of instrument parameters, the acquisition of data from the instrument, real time data reduction to eliminate extraneous data values, and rudimentary displays of the acquired data for use in optimization of the instrument parameters and monitoring the course of an experiment. To perform these functions the control system needs a variety of interfaces to the instrument and peripherals capable of supporting a "user friendly“ interface with the operator. Modern microprocessors have several features which make them ideally suited for implementing instrument control system. One feature is high performance at a low cost which allows the microcomputer to be dedicated to a single instrument. TERMINALS 11 OTHER COMPUTER SYSTEMS — GRAPHICS DISPLAY .Dl MINI- COMPUTER DISK DRIVE SYSTEM __l 4 PRINTER C>000 E d FLOPPY DISK , PLOTTER A 1%.]; INSTRUMENT CONTROL hMCRO INSTRUMENT Figure 1*1 l INSTRUMENT CONTROL MICRO INSTRUMENT CONTROL MICRO INSTRUMENT INSTRUMENT A Typical Hierircal Computer System. Another feature that these microprocessors have is a less complex bus structure than the minicomputers which allow simpler interfaces between the instrument and the computer to be constructed. The availability of LSI peripheral circuits, such as USARTs, parallel I/O ports, and microprocessor compatible signal converters (ADCs and DACs), also simplifies the design of new interfaces to the instrument. The programmable nature of many of these LSI peripherals is another advantage because it allows a general purpose interface to be used for a variety of instruments by merely changing the controlling software. The low cost of these peripherals also increases the number of instrument parameters that can be controlled by the computer at a reasonable cost. COMPUTER NETWORKS The advent of separate data analysis systems and instrument control systems has led to the development of a variety of laboratory networks which allow the different instrument control systems to communicate with other ”host" computer systems(15),(1o). These host computer systems provide the ”data analysis” system functions while the satellite systems provide individual instrument control and data acquisition. These heriarchical systems permit the different functions that are involved in an experiment to be performed on the computer that is most suitable for that task. The existence of these networks also assists in the combination of data from different types of instruments to obtain the answers to a single analytical problem. Modern control systems are developing in several directions such as intelligent systems(l7) which employ the results of an experiment to determine the conditions for the next experiment, and the use of distributed processing systems to provide increased capabilities for instrument control. LABORATORY MICROCOMPUTER SYSTEM DESIGN GOALS To meet the needs of our research group for instrument control systems, we decided to design a microcomputer system that would better meet the requirements of a research environment than commercial microprocessor boards or personal computers. This system was designed using experience gained with a microprocessor system designed by Jim AverytlB) and Dan Lovse(19)at the University of Illinois , and a previous microprocessor system designed at 14 Michigan State University by Erik Carlson(20) and Jim Hornshuh(21). To insure that the system would meet the needs of the research environment, a list of design goals was compiled. These goals are given in Table 1-1 and discussed below. The requirement for the hardware to be modular on the single function level arises from the constantly changing nature of most research instruments. This modularity allows the control system to be easily modified as the experimental needs change. The single function nature of the modules permits the addition of just the capabilities that are required without wasting time, money, or board space on functions that are not needed. The design goal of operation with a wide range of configurations arises from the vastly different requirements of different instruments in a research laboratory. Another of the design goals is the need for the computer systems to be able to operate in a hierarchical system with other computers. This allows the microcomputer to be used as a control system with a separate minicomputer acting as a data analysis system. The microcomputers also need to be inexpensive if they are to be dedicated to a large number of different instruments. The availability of graduate student labor permits the assembly of the microcomputers to be labor Table 1-1. The Design Goals for the Microprocessor System. 1. Modular hardware on a single function level. 2. Capable of operating over a wide range of configurations. 3. Should be able to operate in a hierarchical environment. 4. Inexpensive given low cost labor. 5. Elimination of card edge connectors for improved reliability. 6. Provisions for I/O connections on the backplane. 7. Should be able to evolve gracefully from a single processor into a distributed processor system. 16 intensive and still result in an affordable microcomputer. To improve the reliability of the system. the elimination of printed circuit board edge connectors was a design goal. To be reliable these connectors require gold plated fingers on the PC board and accurate PC board routing. Attempts to use edge connectors had resulted in problems in previous systems since neither of these requirements could be easily met with the available in~house equipment. Another design goal that resulted from experience with previous systems was the desire that I/O connections would be made through the system backplane. This allows a board in the system to be easily removed or extended for debugging without dragging a mass of cable with it. A final design goal was the requirement that a single microprocessor system should be upgradable to a distributed processing system without complete redesign of the instrument interfaces. SUMMARY This thesis describes a microcomputer system which meets these goals. The single processor implementation is described in Chapter 2 and several of the various applications to which it has been put are described in 17 Chapter 3. The concept of distributed processing and the advantages that it affords are discussed in chapter 4. Chapter 5 describes the specific hardware that was designed to implement a multiple processor version of this microcomputer system. This multiple processor system was used to implement a control system for an advanced mass spectrometer as described in Chapter 6. A short summary of the software that was written for these systems is presented in Chapter 7. This microcomputer system has been very successful in our department where it has been used to implement more than twelve different instrument control systems. CHAPTER 2 - THE SINGLE MICROCOMPUTER SYSTEM - To meet the design goals stated in Chapter 1 a modular microprocessor system was developed. This system is composed of a series of single function modules which are interconnected to form a computer system by mounting the modules on a dual—bus board. The dual-bus board has two sets of bus traces on it which connect the local processor bus to all of the medules in the system. Up to four of the dual-bus boards can be plugged into a backplane to form a complete microprocessor system as shown in Figure 2~1. The two sets of bus traces on the dual-bus board can be seen in Figure 2~2, which shows the foil side of a dual-bus board. The signal traces on the dual—bus board are connected to the backplane by pin and socket connectors which mount in the holes shown on the left side of Figure 2~2. These connectors were used because of their high reliability compared to conventional edge connectors. As can be seen in Figure 2—2, the lower set of bus traces is directly connected to the pin connector, while the top set of traces is left unattached. The uncommitted nature of the top set of bus traces provides a great deal of flexibility in designing different microprocessor system. 18 19 USES OF THE SECOND BUS On most of the dual-bus boards in a single processor system, the two sets of bus traces are joined by a series of vertical jumpers so that both sets of bus traces are connected to the local processor bus. This allows standard function modules to be mounted on both the top and bottom halves of the dual—bus board, which increases the number of modules that can be mounted on a single dual-bus board. However, the top bus can be used for more novel applications by jumper—connecting the traces to the backplane instead of to the lower bus. This allows the top bus to be used as an interprocessor bus, a hardware controlled peripheral bus, or as the local processor bus of another processor. The use of the top bus as an interprocessor bus is discussed in the second half of this dissertation. The advantages of employing the top bus as a peripheral bus are examined in chapter 3 where a linear diode array spectrophotometer control system is shown as an example. An example of the use of the top bus as the local bus of another processor would be the implementation of an intelligent data base controller. A module that connects to both of the busses would allow requests for information to be transferred to the data base control processor, which Figure 2—1 A Typical Single Microprocessor System. 1I1II Illlllll IIIII III I|l( would then search the data base for the requested information and return it to the main processor.- THE BACKPLANE The backplane board, which is shown in Figure 2-3, is capable of interconnecting up to four dualfbus boards. The backplane has a set of traces along it’s lower edge which connects the local bus between the dual~bus boards and also distributes power. The signals from the connectors on the top half of the backplane are brought out to sets of pads which permits the mounting of different types of cable connectors. The latter are used to connect the computer system to the instrument that is being controlled and to the rest of the real world. Thus, the dual—bus boards can be removed or extended without having to disconnect any cables. Sets of pads are also provided for connecting the local bus to another backplane if more than four dual—bus boards are required to construct the system. .... .... d:— »_'I I<—— |3.8 cm , 5.4 in——> 2|.8 cm, earn—a Figure 2—3 The Trace Side of the Backplane Board. LOCAL BUS DEFINITION The local processor bus used in this system is a fully demultiplexed synchronous bus. The data and address signals are all active high while most of the control signals are active low to reduce problems with noise spikes. Further information on the signals generated by the SO85 and SOSS processors is found in the appropriate Intel manuals(22>,(23). In addition to the normal bus signals, four additional signals have been provided for the use of the interprocessor modules. The layout of the local processor bus is given in Figure 2~4. The definitions of the signals that make up the bus are as follows: DO~D7 Eight bidirectional data lines. AO~A15 The lower sixteen address lines. A16—A19 The four most significant address lines (BOSS system only) ALE The falling edge of Address Latch Enable indicates that a stable address is available to be latched into the address latches. It is also used to indicate the start of a bus cycle. NR\ The active LO write signal is used to strobe data from the data bus into the addressed location. * Shield Gnd SHIELD GND * . * HALT (A19) (A18) P81 * a P82 (A17) (A16) P83 * * PHOLD\ PHLDA * * PWR\ PRD\ * * HOLD\ HLDA * * RESIN\ READY * * RST7.5 (INTO) (INT1) RST6.S * * RST5.5 (TEST\) INTR * * RESET\ CLK\ * * INTA\ IO/M * * 81 RD\ * * NR\ ALE * . ~ * A15 A14 * * A13 A12 * * A11 A10 * * A9 A8 * ' * A0 A1 * * A2 A3 * * A4 A5 * * A6 A7 * * DO DI * * 02 D3 * * D4 DS * a D6 D7 * ANALOG 6ND * -24 * +24 * +5 * DIGITAL GND a Figure Ew4 The Layout of the Local Bus. RD\ The read signal is used to enable a memory or peripheral device to drive the data lines. This signal is active LO. SI This signal gives an advanced indication of the direction of information transfer on the data lines. A HI level indicates data are to be read into the processor. IO/M A HI level on this signal indicates an I/O transfer is to take place while a LO level indicates a memory transfer is to occur. INTA\ An active LO interrupt acknowledge from the processor. CLH\ The inverted processor clock. RESET An active LO reset signal from the processor which is used to initiallize all of the peripherals in the system. INTR An active HI general interrupt input to the processor. It is normally generated by an 8259A interrupt controller. RSTS,5-RST7,5 Three interrupt signals to the SO85 processor which have predefined interrupt vector locations in memory. INTO,INT1 Two bussed inputs to an 8259A interrupt controller in an BOSS system. TEST\ An active LO signal that is tested by the BOSS CPU during the WAIT instruction. READY When this signal is LO the processor enters a wait state until the ready signal returns HI. It is used to slow down the bus cycle for slow peripherals. RESIN\ An active LO reset input to the processor. HLDA A hold acknowledge signal which indicates that the processor has released the local bus when HI. HOLD\ An active LO signal which requests the use of the local bus from the processor. PRD\,PWR\,PHOLD\,PHLDA Four signals used by the interprocessor modules to control the generation of the RD\, WR\, HOLD\, and HLDA signal on systems which have interprocessor modules. PSI—PS3 Peripheral status lines which are used by the BOSS CPU module and the interprocessor modules. HALT\ An indication that the SO85 CPU has executed a halt instruction. STANDARD MODULES More than thirty different standard modules have been designed for use in this system. This wide range of functions greatly reduces the number of custom interfaces that must be designed when a new instrument control system is constructed. Table 2-1 gives a list of the currently available modules. These modules are constructed in two different heights, single height modules that are 3.7 inches high and double height modules which are 7.7 inches high. The modules come in different widths depending on the amount of space that the function needs. The modules can be designed in one inch increments from a minimum of one inch to a maximum of nine inches. This modularity of size combined with the ability to pick up bus signals at multiple locations on the module result in very efficient use of space. PROCESSOR MODULES There are two different processor modules; one uses the Intel BOSS processor and the other uses the Intel BOSS processor. The SO85 CPU module has latches on it which- demultiplex the data-address signals from the processor and triwstate drivers which buffer the data and control signal. This module also contains two switches which allow the processor to be reset and held. There are six LEDs on this module which provide indicators for the following signals, P81,PSZ,PS3,HLDA,HALT,and SOD (serial data out from the SO85). The BOSS processor module combines the functions of Table 2-1. A list of Standard Modules. SO85 CPU 9513 CTC * BOSS CPU 58167A RTC RAM/ROM Octal 12 bit DAC (AD390) 8K RAM Dual 8-bit DAC (AD558) * 8259A Interrupt Controller Dual 12-bit DAC (1230) * Chip Select 12—bit ADC (AD574) * Address Extender Diff. Multiplexer * Wait State Generator Programable Gain Amp. * AC Terminator Diff. Transceiver Active Terminator Softknobs Interface SCSI Interface 8OS7 Adapter 1771 Floppy Disk Controller * 2”,3” Wire Wrap Dual 8251A USART Bus Multiplexer 8255A PIO Graphics Controller (7220) 253-5 CTC Graphics Memory Plane * Modules that were designed by other people in the department. the processor with an interrupt controller, chip select logic, and an active terminator on a single double height module. It was necessary to combine these functions to provide enough space for the processor functions in the same area as an SO85 CPU module, an interrupt controller module, a chip select module, and an active terminator module. In addition to circuits which demultiplex the data and address signals and buffer the data and control signals, the BOSS CPU module provides circuits which control the restart address of the processor and provide for the addition of zero, one, or two wait states for memory locations between XFOOO and XFFFF. This wait state circuitry is necessary for the processor to access the standard LSI peripheral modules. The functions of the interrupt controller , the chip select logic, and the active terminator are the same as those provided by the standard modules. An adapter module has also been designed which allows the 8OS7 numeric coprocessor to be used with the BOSS CPU module. MEMORY MODULES There are two different memory modules that can be used with this system. The first provides up to 8 Kbytes of RAM memory using 2114 (4 x 1K bit) memories. This module has been largely replaced in recent systems by the second memory module. This module, called the RAM/ROM module, has sockets for eight 24—pin JEDEC standard RAM or ROM chips. It can provide a total of B KBytes of memory if 1 or 2 Hbyte chips are used or 16 Hbytes if 2 or 4 Kbyte memory chips are used. SYSTEM SUPPORT MODULES Several modules have been designed to provide system support functions such as interrupt control, chip select logic, wait state generation and bus termination. The interrupt control is provided by a module which employs an Intel 8259A interrupt controller to provide eight vectored interrupts. This module can be used with both the 8085 and BOSS CPU modules. Flip/flops and inverters are provided on this module for use in transforming interrupt signals into the active HI level interrupt signals that the interrupt. controller requires. The address decoding for all the peripheral modules is performed by a separate chip select module. This module decodes 512 addresses in memory space into eight 64 byte unqualified chip selects, and the top unqualified chip select is decoded into eight 8 byte read/write qualified -r m .5 .3 5.. .5. chip selects. The unqualified chip selects are normally used by other LSI peripheral modules in the system while the qualified chip selects are used to control flip/flops and latches. By combining the address decoding onto a single module, the other modules are simplified and duplication of the chip select logic is avoided. To allow the entire 1 megabyte address space of the BOSS to be used, an address extender module was designed which decodes address lines A16 through A19. The address extender module may be used with all the chip select and memory modules. The wait state module is used in an 8OB5 system to stretch the bus cycle by driving READY LO. Its function is provided on the BOSS CPU module because most of the LSI peripherals require a longer bus cycle than the BOSS normally provides. Bus termination is provided by two modules, an active terminator module and an AC terminator. The active terminator module terminates the bus signal with a 1 kilohm resistor to a 2.6 volt source which is formed- from a zener diode and an emitter follower. The 1 kilohm resistance was chosen as a compromise between the need to match the characteristic impedance of the bus traces (approximately 2OO ohms) and the desire to keep the required DC current levels as low as possible. The AC terminator was designed to permit additional termination to be added to a system without increasing the level of DC .l o' drive required. It terminates the bus lines with a 22O ohm resistor and a 10,000 pF capacitor in series. This combination matches the characteristic impedence of the bus traces at the frequencies that the processor uses. MASS STORAGE INTERFACE MODULES Interfaces to mass storage devices are provided by two modules: a floppy disk controller and a SCSI(Small Computer Standard Interface) adapter module. The floppy disk controller was designed using a 1771 floppy disk controller chip and is capable of controlling up to four 8" floppy disk drives. This module was designed by Ralph Thiim(24). The SCSI adapter module can be used to interface the computer to a variety of intelligent disk and tape drive controllers using the industrial standard SCSI bus structure. The use of the SCSI controller greatly simplifies the software since it allows a single driver- program to control both floppy disk and Winchester disks. LSI PERIPHERAL MODULES Serial ports are provided by a dual USART module that has two B251A USARTs. The baud rates are set by jumpers which control a baud rate generator chip. Two USARTs were used so that the baud rate generator and the line driver chips could be shared. A Parallel I/O module using an 8255A PIO chip provides parallel input and output ports for the system. Two different counter/timer modules have been designed for this system. One uses the Intel 8253-5 counter/timer chip while the other uses the Advanced Micro Devices 9513 counter chip. These two circuits differ in their complexity and capabilities. The 8253-5 is the simpler of the two and has 3 sixteen-bit counters and fewer operating modes than the 9513. The 9513, which has 5 sixteen~bit counters, is much more flexible than the 8253-5 and includes such features as an on—chip frequency source and a wide variety of Operating modes. The 9513 module was designed by Gene Ratzlaff(25). A real time clock module has been designed to provide the computer with the time of day. This module, which uses the National 58167A clock/calendar chip provides both time of day and date for the processor. ANALOG FUNCTION MODULES Analog interface functions are provided by a number of different modules. These include three different DAC modules, an ADC module, a programmable gain amplifier, and a differential multiplexer module. The simplest of the DAC modules is a dual 8—bit DAC module which contains two A0558 unipolar DACS. The second DAC module is an octal 12—bit DAC module which uses two A0390 quad DAC chips. This module provides eight 2’s complement bipolar DACs. The third module is the most flexible of the three modules. This module can be configured to use either 8 or 12 bit DACs; either DAC can be independently configured as unipolar or bipolar with a full—scale range of 10.0, 7.5, 5.0, or 2.5 volts. The ADC module uses an A0574 ADC which is a 12—bit 35 microsecond converter. This module also contains a A0583 sample and hold circuit. The differential multiplexer was constructed with a HIl-0507 which is an eight channel differential multiplexer. A Burr~Brown 360686 was used to implement the programable gain amplifier module. This module is software programable for gains between 1 and 1024 in powers of 2. Most of these modules were designed by other people in the department: the differential multiplexer and programable gain amplifier were designed by Lynn Jones(26), the ADC was designed by Gene Ratzlaff(25), the A0558 module was designed by John Stanley(27), and the dual 8/12 bit DAC board was designed by Norm Penix(28). MISC. MODULES To aid in the construction of custom interfaces several. miscellaneous modules have been designed. A differential transceiver module was designed for use when the interfaces to the instrument needed to be physically distant from the computer system. This module allows a subset of the local bus to be differentially driven to a remote location. The ability to place interfaces close to the instrument results in much shorter analog signal paths which leads to better accuracy and greater noise immunity. For use in prototyping interfaces, two wire wrap boards have been designed. These modules come in 2 inch and 3 inch widths with pads provided on the 2 inch module for connections to the local bus. A final miscellaneous module is a softknob interface which can interface up to four quadrature encoded rotary knobs to the computer system. These knobs are very useful in providing a convenient way- of controlling various instrument parameters. DUAL HEIGHT MODULES Several modules have been designed which make special use of the top bus. The first of these is a bus exchanger .... .. '_' module which can switch the two sets of bus traces on a dualmbus board between the local bus and a second bus connected to the top of the backplane. This module is normally used to switch blocks of memory between two different busses. Two gother modules use the top bus as a graphics memory bus. These modules are the graphics controller and the graphics memory plane module. The graphics controller uses a NEC7720 graphics controller chip. This chip controls up to 256K bytes of private graphics memory and can draw points, lines, boxes, and circles. The graphics memory module can use either 16K or 64K DRAM chips which results in a 512 by 512 pixel display if 16H chips are used or a 1024 by 1024 memory plane if 64R memory chips are used. SUMMARY This microcomputer system has been used to construct more than twelve systems in our department with excellent results. These systems have been very reliable with no development of contact problems that plagued previous microcomputer systems in the laboratory environment. The modular nature of this system has also allowed systems with very different functions to be constructed with only minor amounts of custom interface design. Three of the systems that have been built with these modules will be examined in Chapter 3 to illustrate the power and flexibility of this system and the advantages it has for chemical instrumentation. CHAPTER 3 - EXAMPLE MICROCOMPUTER SYSTEMS - The modular microprocessor system described in Chapter 2 has been used to construct over twelve different instrument control systems in our department. As examples of the different types of microprocessor systems that can be built, three of these control systems will be examined in detail. These three systems are a data acquisition system for a laser laboratory, a diode array spectrophotometer that is used for optical rotatory dispersion experiments, and a control system for a time-resolved magnetic dispersion mass spectometer. These three systems will also be used to demonstrate several ways the computer was used to improve the chemical information that is obtained from an experiment. LASER LAB DATA ACQUISITION SYSTEM The first computer system that will be examined is the laser lab data acquisition system (29). The type of experiment this system was designed to control is the 40 investigation of saturation effects on absorption spectra. In these experiments, a sample is optically pumped by one wavelength of laser light and then the absorbance at a different wavelength is measured by a probe beam(26). To perform these experiments, four light intensities must be measured for each laser pulse. These four values are the intensity of the incident pump beam, the intensity of the transmitted pump beam, the intensity of the incident probe beam, and the intensity of the transmitted probe beam. A block diagram that shows the major components of this system is presented in Figure 3-1. The system was constructed on three dual-bus boards using the following standard modules: an 8085 CPU module, two RAM/RUM modules, a dual USART module, an interrupt controller module, an active terminator, a floppy disk controller module, a parallel I/O module, a differential multiplexer module, a programmable gain amplifier module and a 12-bit ADC module. As can be seen in Figure 3-1 one' of the USARTs is used to communicate with a terminal while the other USART is used to communicate with a DEC POP-11/40 which performs advanced data analysis functions. The floppy disk is used to store both system software and acquired data. A ”step through" of the stages involved in data acquisition will best illustrate the system operation. A data acquisition operation is started by the firing of the 41 .Emym>m Lmvjoeou bod memu mcw +0 emtomao xuoam Aim mtjofiu , 34 _ _ ulna“ (5... fl and”... r19 _ (m4 .32 55 ..—u _ _ _ _ 22:23. > i m juosuzégefizvrfll \_I.Z 5% 11 r: u. E 10523 1.102 coupzvfwullllfll - [L m 198%2322. _ \rI] to. m l 4I< < ~56 :— 512.35% es... ... filido 1:05 .325: j ,rlllllll Jar... 1!- i M V 3&0 Nd/YAS laser system, which sends a trigger signal to the microcomputer. The trigger signal is connected~to several digital delay cards where it is used to generate gate and reset signals to a set of four gated integrators. The length of time that the gate is delayed from the trigger and the width of the gate pulse are both programmable through the parallel I/O port that controls the digital delays. The four light beams to be measured are converted to electrical current by four photodiodes, and the resulting signals are integrated by four separate gated integrators. The end of the gate pulse causes an interrupt signal to be sent to the microprocessor. The microprocessor then acquires the four data values by selecting each of the four channels of the differential multiplexer sequentially, setting the programmable gain amplifier to the proper gain for the selected channel, and converting the resulting signals. This process is repeated for ten to one hundred pulses and then the data are displayed along with the transmittance for each of the two beams. The software also displays the mean transmittance, standard deviation of the mean, and the percent error. The laser lab system is an excellent example of how a computer system can greatly increase the amount of chemical information that can be acquired. Before the computer system had been constructed a number of experiments were attempted using an oscilloscope for readout. Polaroid photographs of the oscilloscope screen provided data storage. It was immediately apparent that this approach had serious shortcomings in several areas. The first of these was the task of aligning the optical components in the system. This task was extremely tedious because after every change in the optical path, the ratio of the incident and transmitted signals had to be determined from the oscilloscope display. With each measurement so tedious, the estimation of the error in the measurements was very difficult. Even greater problems were encountered in trying to determine accurate values for the transmittance of the pump and probe beams. Because the use of an oscilloscope allowed only one diode signal to be monitored at a time the transmittance of the two beams could be determined only from average values of the incident and transmitted beams. This was a problem' because the pulse—to-pulse variability of the laser power was quite large (factors of two or more are common). The error in the determination of the average beam intensities was larger than the small changes in probe beam transmittance that the experiment was trying to determine. Using the data system, these problems were easily overcome since the computer could measure all of the signals for each pulse of the laser thus providing a complete transmittance measurement for both beams as well 44 as an accurate measurement of laser power in each beam. The computer system also calculates the error in the measurements which is of great value in trying to align the optical components. LINEAR DIODE ARRAY SPECTROMETER SYSTEM The second control system is a data acquisition system for a linear diode array spectrophotometer(30),(31). This system is used to determine optical rotatory dispersion (ORD) spectra of various compounds. The ORD technique involves the determination of the optical rotation of circularly polarized incident light by optically active compounds as a function of the wavelength of the incident light. The diode array that is used as a detector has 512 diodes arranged in a linear array. In operation, light striking the diodes causes a decrease in the charge that is stored in each diode. After a programmable integration time, the charge on each diode is serially shifted out of the array, and the charge that must be added to return the diode to the original level is measured. This charge is proportional the amount of light that the individual diode received. As can be seen from the block diagram of this system shown in Figure 3—2, the top bus on several of the dual—bus boards is used as a hardware—driven peripheral bus. The reason that this configuration was chosen is that the diode array generates data at a rate faster than can be accommodated by the processor. Normally the data could be stored in memory using a direct memory access (DMA) controller. However, this requires the use of the local bus which inhibits operation of the processor while the DMA transfer is going on. DNA storage was not a viable option in this case because there is insufficient time between blocks of data for the processor to load the integration time and acquisition parameters for the next block of data. These problems were avoided by using a bus exchanger module to switch two blocks of memory alternately between the local bus and the top bus. This allows the data to be stored in memory over the peripheral bus while the processor is loading the next set of acquisition parameters. After several blocks of data have been stored in the memory, the bus exchanger swaps the banks of memory so that the processor can process the data and store it on disk. The computer system was constructed on six dual-bus boards using the following standard modules: an 8085 CPU module, two RAM/ROM modules, two RAM modules, a dual USART 4o .Ememxm >mttq mucus wzs +0 emtamuo goods was wtsuac T Boom >23 , _ 004 I 2.20 32.... _ Ba 6290 H 7 «so .2298“. .\ 3:22.00 k . f , cc. .2300 _somQ _zm mejoeau deem mcp +8 emtomaa xUGHm film wtjoau 5:22.. 3:. ..2 32.25., _ . . . . :28 . :28 55: . 24m: 2:. so :5. 24¢ _ . . commuooza-oo \# :5: fl; 1 smog rmaaxczéo I IIIIII i haazcmpz. [ $883885: M W M w M W M w M W goose o\. o\_ mo&w.r. $43.62.; 3.5; “canto cohowbwo cuaaompzoo _ bozom @cammmucti owyjeutomao Heuuo>e Q l I Tm. wtjoau . x \\\ «to ‘i Lg g r it -\ 74 Table 5—1, and the definition of the signals are given in the following list. 100-107 Eight bidirectional interprocessor data lines that carry the data during a direct memory transfer and carry 8 bits of the command during a command transfer. IAO—IA15 Sixteen interprocessor address lines that carry the address information during a direct memory transfer and the remaining 16 bits of command during a command transfer. IIA16-IA18 The three thh—order interprocessor address lines that carry the number of the processor being accessed during direct memory and command transfers. IRD\ An active LO signal that is used by the communicator to enable the transfer of data during an interprocessor read operation. IWR\ An active LO signal that is used by the communicator to enable the transfer of data during an interprocessor write operation. IIO/M The communicator drives this signal LO during an interprocessor memory transfer. ISI\ This signal is driven by the communicator to indicate the direction of data transfer during a direct memory \J Ul Table 5-1. Pinout of the Interprocessor Bus Cable PIN 1 IP GND PIN 2 STGND 3 STB\ 4 STBEN\ 5 5A3 6 5A2 7 5A1 8 8A0 9 807 10 SD6 11 SD5 2 804 13 803 14 802 15 SDI 16 500 17 IRDY 18 ICMD 19 IA18 2 IAl7 21 1A16 22 ILOCH 23 IWR\ 24 IRD\ 25 IIO/M 26 ISl\ 2 IA15 28 IAl4 29 IA13 30 IA12 31 IA11 32 IA10 33 1A9 34 1A8 35 IA7 36 IA6 37 1A5 38 1A4 39 1A3 40 1A2 41 1A1 42 1A0 43 107 44 106 45 IDS 46 104 47 103 48 102 49 101 50 IDO 76 transfer. A LO level indicates that the data is to be transferred to the communicator. ILOCH A HI level on this line, which is driven by the communicator, indicates that the addressed processor is not to be released at the end of the direct memory transfer operation. IIRDY A LO level on this line keeps the communicator in a wait state during a direct memory transfer until the addressed processor releases its local bus. I (IVE) The coordinator drives this signal HI to strobe the command information into the FIFO buffers on the addressed processor during a command transfer. SEiIl0—SD7 Eight status data lines that carry the status information between all of the processors. s3A0-SA3 Four status address lines that are used to control which byte of status information is being written into the dual-ported memory on all of the processors. These four signals are driven by the coordinator. STE\ 4 L0 level is driven on this line to strobe the data on 800-507 into the dual—ported memory on all of the processors. STEH3V\ This signal is used to establish the timing of the 77 STB\ signal. It is driven LO by the coordinator to enable the STB\ signal. STGND This is a reference ground for the status bus signals. IPGND This is a reference ground for the rest of the interprocessor bus signals. In addition to the signals on the interprocessor bus, the (dual bus board provides several uncommitted traces that are Lised to connect signals between interprocessor modules on tzhe same processor. These signals provide the processor riumber (PNO-PN2), five chip selects (CBl\-CB4\,BCREG), and 11hree hardware status signals (BUFE\, BUFF\, CMDHLD). DIRECT MEMORY TRANSFER PATH The module in each processor that carries out the direct memory transfer path is the bus controller or the bus switch module depending on whether the processor is the (:ommunicator or one of the other processors. The block diagrams of each of these two modules are shown in Figure 5~2. The bus controller module was originally designed to berused with an 8085 CPU. However, it was later modified 78 ‘Inter- processor 0)om -b‘ CONTROLLER L CWW' l——A A AV . TT 0 local A —__________‘p__+, 1}, C y 4. lnter- IS) , processor 2 I s -Decodc ‘ SWITCH Control' ‘ v_v4 VA In“ E 5* Irir ITigure 5w2 Block Diagram of the Bus Controller and Switch. 79 to operate with the 8088 CPU because the 8088 CPU’s increased address space permits more efficient operation of the direct memory transfer path. In the communicator, the top half of its 1 megabyte address space is defined to be interprocessor memory space. Each of the slave processors, which are restricted to 64 Hbytes of memory space, is assigned a unique eighth of the available 512 Hbytes. Any read or write operation to these addresses in the czommunicator initiates an interprocessor memory transfer sand results in an actual read or write in the corresponding tnyte in the slave’s memory. Thus the top half of the czommunicator’s memory is actually the combined memory of tzhe slaves. The main stages in this transfer are: the bus (controller drives the interprocessor bus, the addressed bus 'switch holds the slave processor and takes control of the slave's local bus, the communicator performs a read or write operation to the slaves memory, and the slave processor is released from the hold state. There are two different options which can modify the stages in the basic transfer. The first is that the (:ommunicator can set a latch which then generates the ILOCK sugnal during the next interprocessor transfer. This signal causes the bus switch on the addressed slave system to keep the slave processor in a hold state after the tr‘ansfer is finished. Subsequent transfers to this slave 80 caan then take place at a faster rate because there is no rieed to wait for the processor to finish the current bus czycle and release the local bus. The lock latch is cleared taefore the last transfer to the slave system, which allows ‘t;he slave processor to be released from its hold state. ‘r'his option is useful for batch transfers such as loading t) locks of code or moving blocks of data from the slave. The sssecond type of deviation from the basic transfer takes P) lace when the interprocessor transfer takes longer then a FZIreset time. If this happens, a bus ”timeout error” occurs Laohich immediately terminates the interprocessor transfer ‘Eahd generates an interrupt to the communicator processor. this error can take place if a peripheral controller (DMA Czontroller) in the slave system has control of the local tous and won't release the local bus for the bus switch to L152. The schematic diagrams of the bus controller and the tnus switch are given in Figures 5-3A and 5-3B and Figures ES~4A and 5-4B respectively. These diagrams will be used to Ciiscuss the steps that take place during a typical ititerprocessor transfer between the communicator and a S 1 ayes memory: 0 If the communicator desires to perform a block transfer it sets the LOCK flip/flop. ’51 Qure swim Schematic of the Bus Controller. F:lo'oure 5~3B Schematic of the Bus Controller. WC)- .5 *5 -<:JRDY l t-CIIDCK ) Pl‘LD/D— —‘ j? PItDAD— H PNOD- L--<:llAl6 PNID— —<:JIAI7 —<:)Icm met/D— ' ' I:Jlgure 5*4A Schematic of the Bus Switch. F“”1 gure 5~4o Schematic of the Bus Switch. The communicator addresses a memory location which corresponds to the desired location in the slave processor memory space. Logic on the 8088 cpu module inserts one wait state which gives the interprocessor modules time to respond. The control logic in the bus controller recognizes that a slave address is being addressed by combining A19, ALE, PRD\, PWR\, and PHLDA. The control logic then enables the tri—state drivers which drive the data, address, and control signals onto the interprocessor bus. When the bus switch in the slave processor recognizes that it is being addressed by combining IA16, IA17, IA18, ICMD, IRD\, and IWR\ it drives IRDY LO, which causes RDY on the communicator to be driven LO thus placing the processor into a wait state. It also generates a signal which is combined with HOLD\ in an arbitration circuit to drive PHOLD\ LO. This requests the use of the local bus from the slave processor. After the slave processor has finished any current bus cycle it releases the local bus. The slave processor then informs the bus switch that it may assume control of the bus by driving PHLDA HI. The bus switch then enables a set of tri-state drivers which place the address, data, and control information \ 86 onto the local bus. C) After sufficient setup time has passed the communicator processor is released from the wait state by driving IRDY HI. c: The communicator then completes the read or write operation and disables all of the tri-state drivers. (z) If ILOCK was LO during the transfer then PHOLD\ is driven HI which releases the slave processor from its hold state and permits it to resume execution. If ILOCH was HI during the transfer then PHOLD\ is kept LO and the processor stays in a hold state. 12f the HOLD\ signal on the slave processor was active when t:he transfer starts, the arbitration circuit on the slave Ebrocessor never allows the IRDY signal to return HI. This Faermits a counter on the bus controller to reach terminal czount and set a flip/flop. When this flip/flop is set, it ccauses the RDY signal on the communicator to be driven HI, thich releases the processor from the wait state and qgenerates an interrupt to the processor. 87 COMMAND TRANSFER PATH The command transfer path is implemented by a command driver module on the coordinator and command buffer modules on all of the other processors. A block diagram of these two modules is given in Figure 5—5. These modules use the data and address lines of the interprocessor bus to transfer a 24*bit command to the FIFO buffers on the desired slave system. The FIFO buffers, which are located on the command buffer modules, allow queuing of up to 32 commands for the slave processor. Figures 5~6A and 5-68 are schematics of the command driver and Figures 5~7A and 5-7B are schematics of the command buffer. The stages that take place during a typical transfer are: 0 The coordinator loads the processor number of the slave to which the command is to be sent into the register controlled by chip select CB4\. o The coordinator loads 16 bits of the command into two l-byte latches controlled by chip selects CBl\ and CB2\. o The coordinator then writes the remaining eight bits of the command to a fourth address (CB3\). 0 When CB3\ goes LO the command driver module drives RDY 88 lnlor- processor I DRIVER ‘ (DOC!) | A A g D o a local 0 e 1 '— lntor 3 - —9 4 procouor A 1 T c J l: BUFFER cloor 24*32 FIFO rooot, inter hold. Decode D local A 1 o C t Figure 5~5 Block Diagram of the Command Driver and Buffer. axc>~ I [>0 Figure 5~6A Schematic of the Command Driver. 90 Figure 5~6B Schematic of the Command Driver. 91 Figure 5—7A Schematic of the Command Buffer. Figure 5—7B Schematic of the Command Buffer. LO which places the coordinator in a wait state. It then requests the use of the interprocessor bus from the communicator by placing the communicator in a hold state. The coordinator then waits for a hold acknowledge from the communicator. If the system uses a combined coordinator /communicator, then the hold and the hold acknowledge signals are jumpered to appropriate levels. 0 When the command driver is granted use of the interprocessor bus, it drives the 24 bits of the command and the specified slave number onto the interprocessor bus. After a setup time has passed, a HI pulse on the ICMD signal is generated. o The control logic on the command buffer module loads the command into the FIFO buffers when it recognizes it’s slave number and a HI on ICMD. o The coordinator is then released from its wait state and control of the interprocessor bus is returned to the communicator. The commands are loaded into the FIFO buffers without interfering with the slave processor. The slave processor can check if a command has been sent to it by reading from the address that generates CB4/. If bit 0 is HI, a command is in the FIFO buffers. The slave processor can then read the command by reading from addresses that generate CBlf, CB2/, and CB3/. Reading from CB3/ also causes the next data in the FIFO buffers to become available. In addition to being loaded into the FIFO buffers, four of the bits in the command have immediate functions. The first of these immediate functions enables the coordinator to clear the FIFO buffers on the command buffer module. This allows the coordinator to empty the buffers at startup time or to cancel commands it has already sent to the command buffers. The second immediate function is the ability to reset the slave system. This is accomplished by driving the RESINK signal LO, which allows the coordinator to initialize the entire distributed processing system to a known state by resetting all of the slave processors. The third function is the ability to hold the slave processor by driving the CMDHLD signal HI. This function can be used at startup before code has been down-loaded into the slave to keep the slave from executing random instructions. The final immediate function is the ability to issue an interrupt to the slave; this could be used to cause the slave processor to read the command buffers before the current task is finished. A high priority command could thus be executed before it’s normal turn. STATUS TRANSFER PATH The status module, which is the same for each processor, contains sixteen bytes of dual-ported memory, a one byte software status register, and an octal hardware status driver. A block diagram of the status module is shown in Figure 5-8. One of the ports of the dual ported memory is written into by a hardware driven status bus, which is part of the interprocessor bus, while the other port can be read by the processor using the local bus. A schematic diagram of the status module which implements the status transfer path is shown in Figures 5—9A and 5-9B. Each of the processors is assigned two addresses on the status bus, one for it’s software status byte and one for it’s hardware status byte. A counter, which is on the command driver module, cycles the address lines on the status bus (SAO-SA3) through the addresses that are assigned to the different processors. When a status module recognizes an address that matches one of its status bytes, it drives that byte onto the status data lines 800*807. The status module then waits for STBEN\ to go LO at which time it drives STB\ LO. This causes the information on lines SDO~SD7 to be written into the corresponding address in all 96 .mHZUOZ mjwmum ace +0 emcomao auofim mim wtjoau w .33 S o boson. 33.6 :22 .8250 too .2. 836.6: ocoztom o x o. o M 3839:. u 4 l t. m L25 .5635... 3234‘ Figure 5-9A Schematic of the Status Module. 98 825l|2 825ll2 825l|2 825ll2 Figure 5*9B Schematic of the Status Module. 99 of the dual—ported memories. The hardware that generates the addresses for the status bus can be jumpered so that fewer than sixteen address are generated. This allows the status information to be update more rapidly if there are less than eight processors in the system. When a processor wants to know the status of any processor in the system, all it has to do is read the corresponding byte in it’s dual ported memory Four of the bits in the hardware status byte are available for definition by the user while the other four have been predefined. The four predefined bits are command buffers empty (BUFE\), command buffers full (BUFF\), processor on hold (PHLDA), and local bus controlled by a peripheral controller (HLDA). These signal lines are used mainly by the coordinator and communicator to control the exchange of information between processors. The software status byte is used to synchronize the execution of tasks on the different processors in the system by exchanging information about what task is being executed by each processor. The status module is also equipped with a set of latches and comparators that monitor the status data and address lines. This circuit is capable of generating an interrupt to the local processor in two ways, first if the 100 software status byte of any processor matches the value stored in the latches or second, if the software status byte of a specific processor matches the value stored in the latches. This allows a processor to perform a task while waiting for a specific event on another processor. The status module also has the address decoding logic on it for all of the interprocessor modules. PERFORMANCE The combination of these interprocessor paths allows distributed processing systems to be designed that can effectively implement real time control systems. As an example of the type and complexity of system that can be built with these modules, a control system for an advanced mass spectrometer is examined in the next chapter. This UT system, which uses a MHz 8088 processor as a combined coordinator/communicator, was used to determine the communication rates of the different hardware paths. The direct memory transfer path was capable of transferring 270 Hbytes per second between the master and a slave using the unlocked mode. If the locked mode of communication was employed the transfer rate increased to 345 Kbytes per 101 second. This system used four processors which results in a status transfer latency of 1.6 microseconds. The transfer rate for the command transfer was determined using some high level FORTH routines which could be implemented faster in assembly language. These FORTH routines resulted in a command transfer rate of 3,400 commands per second if the FIFO full bit in the hardware status byte was checked. The communication rate increased to 7,600 commands per second if the check for FIFO full was not performed. These communication rates are sufficient for many real time applications with the status transfer path needing the most improvement due to the amount of time that the interpretation of the status byte needs in software. This improvement might be accomplished by the implementation of a status transfer mode that would allow interrupt signals to be transferred between processors (see the future developments in chapter 8). CHAPTER 6 - TOMS CONTROL SYSTEM - The principal driving force behind the development of the distributed processing system in our laboratory was the need for an instrument control system that would allow the full potential of our Triple Ouadrupole Mass Spectrometer (TOMS) to be utilized. The flexibility and complexity of this instrument requires a control system with capabilities that are greater than those that can be realistically implemented with a single processor control system. To assist in the discussion of this control system, the following section presents a description of the TOMS instrument and its principal operating modes. THE TRIPLE OUADRUPOLE MASS SPECTROMETER The triple quadrupole mass spectrometer is a type of tandem mass spectrometer that was invented in our laboratory by Yost and Enke<44),(45). The TOMS instrument is constructed from two quadrupole mass filters that are separated by a quadrupole collision chamber as shown is 102 103 Figure 6~1. In the TOMS technique, the sample to be analyzed is first ionized in the source region, and the resulting ions are mass analyzed in the first quadrupole mass filter. The selected ions are then fragmented in the collision chamber by collisions with other molecules. The collision chamber consists of an RF-only quadrupole which focuses the scattered ions thus increasing the efficiency of the collision process. The resulting fragment ions are then mass analyzed by the third quadrupole mass filter and detected by a continuous dynode electron multiplier. The use of tandem mass spectrometers has proved to be of great value in the direct analysis of mixtures and the determination of organic structures. When the TOMS is used for mixture analysis, the sample is ionized using “soft ionization” which, results in predominantly molecular ions. These ions can then be selected by the first quadrupole, fragmented in the second quadrupole, and identified by the fragment spectra obtained by scanning the third quadrupole. For structure elucidation, the pure sample is ionized using "hard ionization”, which results in fragmentation of the sample. Each of these parent ion fragments can be selected by the first quadrupole, fragmented in the second, and the resulting daughter ions analyzed by the third quadrupole. The compete fragmentation map is formed by recording all of the parent—daughter fragmentation steps; this map is a .ocmeocomco ozoh och duo ijdau grandma zo. o8 4 20.5.0950 20....0m...um zoFo WIND DC (SCANNING) MOO _."'_. RF DAUGHTER SCAN A—Q D'E B—-) EoF c——> a." DC (SCANNING) _ l RF PARENT SCAN A9 A-l4 a—> o-Ia c——> c-Ie ‘oc l—l B-JS C-IS RF __J DC NEUTRAL LOSS SCAN (SCANNING) The TOMS Operating Modes. 1 RESULT “—30 lg, O 107 between the quad~one mass and the quad—three mass. REQUIREMENTS FOR A TOMS CONTROL SYSTEM One of the characteristics of the TOMS that must be considered by the designer of the control system is the dynamic range of ion current. Because of the two stages of selectivity in the TOMS the ion current has a usable dynamic range of 10ES. To insure adequate time resolution when a BC or other transient sample introduction technique is used, it is desirable that the TOMS be able to scan at a rate of 1000 AMU/sec. At these scan rates, analog current measuring techniques are used, which results in a dynamic range of 10E5 to 10E6. This range is limited by ion statistics at the low end and by detector saturation at the high end. However, if a nontransient sample introduction technique is used, the ion signal can be measured over the full dynamic range by employing pulse counting techniques to measure the ion signal at the low end. Because of the time needed to accurately determine the ion signal pulse counting, this technique can only be used at slower scan rates. This wide dynamic range requires number representations and peak—finding algorithms that work with 108 wide ranges of data values. The large number of devices that must be controlled on the TOMS also presents a challenge for the designer of the control system. These devices are listed in Table 6~1. The control system must also be capable of rapidly switching between the different ionization modes of the TOMS. The three principal ionization modes are electron impact ionization, positive chemical ionization, and negative chemical ionization. When the ionization mode is changed, the settings of all of the devices may have to be changed. This requires that the control system be capable of storing the settings of each device for every ionization mode. The values of several of the ion path devices should 'also change as the mass of the quadrupoles is scanned. This tracking of the ion path with mass greatly increases the number of calculations that the control system must be capable of performing in real time while scanning. To enable the operator to interact with the instrument effectively, the control system needs the following capabilities: the ability to display the raw ion signal in real time, the ability to display the acquired data, utilities to manage the data that the system acquires, and a user friendly interface. A display of the raw ion signal is needed so the Operator can optimize the different 109 Table 6-1. Devices in the TOMS to be controlled. Electron energy Repeller EI ion volume Cl ion volume Extractor lon source lens 1 Ion source lens 2 Ion source lens 3 Interquad lens 1-2 Interquad lens 2-3 Ouad 1 DC rod offset Ouad 2 DC rod offset Ouad 3 0C rod offset Multiplier high voltage Mass selected by quad 1 Ouad 1 delta mass Ouad 1 resolution Mass selected by quad 2 (.4 Mass selected by quad Ouad 3 delta mass Ouad 3 resolution 110 instrument parameters. The display of the acquired data permits the operator to determine if the control system is collecting data properly and is also useful in monitoring the course of an experiment. THE TOMS CONTROL SYSTEM In the distributed control system that was built for the TOMS, the different tasks in the system were partitioned into separate processors using vertical partitioning. This resulted in the four-processor system, shown in Figure 6-3, with one master processor and three slave processors. The three slave processors perform the real time tasks with one processor handling the efferent tasks, a second the afferent tasks, and the third the central partition tasks. The master processor is a combined coordinator/communicator which also handles the communication with the operator, with the disk drives, and with a PDP 11/23, which acts as the data analysis system for the triple quadrupole mass spectrometer. The ion path slave processor performs the efferent tasks of controlling the quadrupole power supplies and the voltages on all of the ion path elements. The detection slave processor 111 .Ewpm>m HULwCOU mZGe wry +0 emtdmao cUOHm file mtjdau .Wmozxtom 722.25., x mmzco - ‘ w , xeo m¥ 55% _W_ 8:. _ i i Max , _ mom cowmmoomccmsz_ . _ MW ,MW IW— zo_._.ow._.m$ _ZO_._.ODom£ _ 1.5». 20. _ intros; H m .l chm—231.52. 220... 112 performs the afferent tasks of ion signal conversion and data formatting. The central partition tasks are performed by the reduction slave processor, which performs the peak finding operations on the data from the other two slave processors. MASTER PROCESSOR A block diagram of the master processor is shown in Figure 6-4. This processor was built on five dual bus boards with the standard modules listed in Table 6-2. The master processor is a 5 MHz 8088 processor with an 8087 numeric coprocessor for increased ”number—crunching‘I ability. The three RAMXROM modules provide 8H of ROM and 40K of RAM memory for the system. The master processor has four serial ports that are used to communicate with a terminal, a printer, a Votrax voice synthesizer, and the POP 11/23 data analysis system. A parallel I/O port is provided to transfer data to the 11/23 system while the serial port to the 11/23 is used for control purposes. An additional interface to the operator is provided by a set of softknobs. These optically encoded knobs are used to provided an enhanced user input. Mass storage for the distributed processing system is provided by an SCSI disk controller, which controls an 8 megabyte Winchester disk 113 [8087 I 8088 I ggflsonxmaij al‘da’é‘u SCSI SCSI 99$? IBK I RAM USART 4 P~ v”’d r A A l STATUS I POP — IVES * aus P W :dcomaouen u, ’ ° :1 come» [3:359:15 CZ: DRIVER l INTERUPT CONTROLLER , ha,- Figure 6-4 Block Diagram of the Master Processor. 114 Table 6-2. Component Modules of the Master Processor. ILII F-J m 8088 CPU Module 8087 Numeric Coprocessor Module Interrupt Controller Module RAM/ROM Modules Chip Select Modules Address Extender Modules AC Terminator Modules Dual USART Modules Parallel I/O Module SCSI Adapter Module Real Time Clock Module Softknob Interface Module Interprocessor Status Module Interprocessor Bus Controller Module Interprocessor Command Driver Module and an 8" floppy disk. The master processor is also provided with a real time clock which allows it to enter the time and date into all experimental records. This processor is a combined coordinator/communicator so it has an interprocessor bus controller, an interprocessor command driver, and an interprocessor status module. ION PATH PROCESSOR The ion path slave processor, which is shown in Figure 6-5, is built from the modules listed in Table 6-3. This processor is an 8 NH: 8088 processor that is supplied with 16K bytes of RAM memory. Since this is a slave processor, the interprocessor modules consist of a status module, a bus switch module, and a command buffer module. The ion source electronics are controlled by an octal DAC module and part of a parallel I/O module. Another port on the parallel I/O module is used to control the vertical gain on an oscilloscope display. A differential transceiver module is used to communicate with a remote RF control box which houses the DACs that are used to control the three quadrupole power supplies and the interquad lenses. There are two special modules on this processor; one is the AMU timer module which is used to determine the scan rate of the quadrupoles, and the other is a link/sync output module 116 l l z ,___w > AMU 4—“ 4—“ l6K TIMER RAM . T . scope v. GAIN I—_‘ R.F. 4—“ DIFE CONTROL —_r‘—J\ PVC TRAN. BOX W W ICIO r—— , r—* i: as “j. M M STATUS ._ T W W M M BUS LR S'YNNKé W SWITCH 311803 OUTPUT W . 4—“ CBOMMAND 4-“ To REDUCTION W UPPER W PROCESSOR Figure 6-5 Block Diagram of the Ion Path Processor. 117 Table 6-3. Modules in the Ion Path Processor. 1 8088 CPU Module 1 RAM/ROM Module 1 AC Terminator Module 1 Parallel I/O Module 1 Octal DAC Module 1 Differential Transceiver Module 1 AMU Timer Module 1 Link/Sync Output Module 1 Interprocessor Status Module 1 Interprocessor Bus Switch Module 1 Interprocessor Command Buffer Module 118 which is used to transfer data to the reduction processor and to synchronize the data acquisition process. This board could be eliminated by a redesign of the status module using recently available integrated circuits. DETECT I ON PROCESSOR Figure 6-6 shows a block diagram of the detection slave processor, which is built from the modules listed in Table 6-4. This processor uses an 8 MHz 8088 CPU and has 16 kbytes of RAM memory. The ion current signal is converted to a voltage signal by a preamp module, which has a transresistance of 2 megohms. This results in a full scale 10 volt output for an input current of 5 microamps, which is the maximum current that should be drawn from the continuous dynode electron multiplier. The signal from the preamp is then sent to a multiamp module which provides five amplifiers with gains of 1, 4, 16, 64, and 256. These five signals are connected to a differential multiplexer module on the detection processor which is used to select one of the channels for conversion by the ADC. The multiamp module also contains a set of comparators and digital logic that produces a digital code to indicate the proper amplifier to use. This code is read by the processor using a parallel I/O port and is then lused to select the z i I__I\ A_I\ A_I\ |6K Pl/O RAM ‘—V W W L____AT MULTI AMP , N_V Mux. W PRE I I AMP ADC A—I\ M W STATUS PROM “ V ‘ ” DETECTOR . M UNIV ,1 x “'4‘ BUS LR SYNC W SWITCH WBUS OUTPUT W 4-“ COMMAND 4-“ TO REDUCTION v-v BUFFER v—v PROCESSOR —— L4— Figure 6-6 Block Diagram of the Detection Processor. 128 Table 6~4. Modules in the Detection Processor. 1 8686 CPU Module 1 RAM/ROM Module 1 AC Terminator Module 1 Parallel I/O Module 1 Differential Multiplexer Module 1 12—Bit ADC Module 1 Link/Sync Output Module 1 Interprocessor Status Module 1 Interprocessor Bus Switch Module 1 Interprocessor Command Buffer Module differential multiplexer channel. The data from the ADC are formatted and sent to the reduction processor via a link/sync output module. Although this processor is currently under~utilized by just operating the ADC, it provides the processing power needed to operate an additional pulse counting interface, which will be provided in the future. REDUCT I ON PROCESSOR The reduction slave processor, which is shown in Figure 6-7, is constructed from the modules listed in Table 6~5. The reduction processor is a 5 MHz BOOB processor with an BOB7 numeric coprocessor. which provides additional "number-crunching” capabilities. Two RAM/ROM modules are used to provide 32 kbytes of RAM memory for the processor. This processor receives data from the ion path processor and the detection processor through two link/sync input modules and then performs peak-finding operations in real time. This processor is also equipped with a graphics controller module and a graphics memory plane populated with 64H—bit DRfiMs. These two modules provide a 1024 by 78B pixel graphics display that is used to display the acquired data. 122 [MONITORJ * {8087 ‘ i A [CDCID «K3-421MDIflD] Figure a~7 l : 8088 l l I S. c F— CRAPHICS’LJ‘ L ' '51:“ MEN—v W L_____I r___ A—"CRAPIIICSM 4—“ l6K W MEMORY W W RAM LINK/ A_l\ SYNC A_J\ A_l\ INPUT w STATUS W W ‘ PROM ION PATH 4 ,. PROCESSOR "—" Selig" W W LINK/ 4—D SYNC INPUT w 4-“ COMMAND 4-“ W BUFFER W PROM DETECTION PROCESSOR L... LR Block Diagram of the Reduction Processor. 123 Table 6-5. Modules in the Reduction Processor. BOBB CPU Module BOB7 Numeric Coprocessor Module RAM/ROM Modules Graphics Controller Module Graphics Memory Plane Module Link/Sync Input Modules Interprocessor Status Module Interprocessor Bus Switch Module Interprocessor Command Buffer Module 124 DATA ACQUISITION The interaction of the three slave processors during data acquisition is illustrated in Figure b-B. These processors execute a set of tightly coupled tasks to acquire and reduce a scan of data from the TOMS. This data record is then transferred to the master processor where it is stored on the disk while the three slave processors are acquiring the next scan of data. To initiate a scan operation, the master processor transfers command and parameter information to each of the three slaves. The ion (lath processor then calculates and sets the first set of ion path values. When these values are stable, the ion path slave passes the X—axis data to the reduction processor, informs the detection processor that it can acquire a data point, and begins to calculate the next set of ion path values. The detection processor then acquires the data point, informs the ion path slave that it can update the ion path values, formats the acquired data point, and checks to see if the reduction processor is ready to accept the new data. When the reduction processor is ready, the detection processor passes it the Y-axis data and waits until the ion path processor indicates that the next data point should be acquired. At the same time the reduction .coupamajuuq meme mzak wJ Emmewe are wtjmfiu (...(o 1b: 20 0232.... van“. gauzum 56.. <53 3:: 2.58“ ERG 5...: 20 $2.02.... yam... Scomcmm 56.. <53 52 25.2 5.25.. (...(O 2.9. US$004 wwadg) :h-fz PM” mu34<> zhdn. zo— zh.+z 9—34-5130 7: 3382... .I @252... $3.. .55.. «:3 .3332... ET: .258 5.359 mu3<> $3.; 55. .3. 5388.. 5: 5m, 32 35:33 12.. :2 126 slave is performing peak finding using the X and Y axis values that were passed to it by the other two processors. This process continues until all of the data points in the scan have been acquired and processed. While all of this is taking place, the master processor is storing the data from the previous scan and is interacting with the Operator to determine the next operation to perform. USER INTERFACE The TQMS control system can interact with the operator tJWrough several different devices. These devices include a CRT terminal, a printer, a graphics monitor, a set of softknobs, and a speech synthesizer, which combine to form an efficient and user friendly interface to the system. Because of the many instrument parameters and operating modes, special attention was focused on the interaction between the operator and the control system. This attention resulted in a set of simple descriptive commands and several interactive screen editors that can be used to modify readily any of the instrument parameters<4é),(47). The control system also provides several aids for the optimization of the different instrument parameters. One of 127 these is the ability to display the raw ion signal on an oscilloscope using either a fast scan command, which scans over a range of masses, or a split screen command, which allows up to five selected mass windows to be displayed next to each other. During these displays the various instrument parameters can be modified by using a set of softknobs. These softknobs are rotary encoders which provide the feel of conventional potentiometers, but have the added advantages of variable resolution, unlimited range of rotation, and computer controlled starting value and clipping to preset limits. The control system is equipped with four of these encoders, which can be assigned to any parameter in the system. A graphics display is provided so that the acquired data can be displayed to determine if the proper instrument parameters were used for data acquisition. The display also permits the course of an experiment to be monitored. A final means of interaction between the Operator and the instrument is provided by a Votrax Type-n-Talk speech synthesizer<48>. This module is used to provided a variety of warning and error messages, which permits the operator to move around the room and still be apprised of any problems with the TQMS instrument. 128 ENHANCED PERFORMANCE AND CAPABILITIES This control system has several advantages over a similar control system that was implemented using only a single 8 NH: 8086 processor. The first of these is an increased scan speed which results in better time resolution when a BC or similar sample introduction technique is used. The scanning rates and the number of data values that are averaged for each data point are shown for the two systems in Table 6—6. As can be seen, the distributed control system is capable of scanning at rates of IOOO and SEE AMU per second which the single processor system cannot perform. At the faster scan rates, which are the more commonly used rates, the distributed system has twice the signal—to~noise ratio of the single processor system. The distributed system is also capable of tracking several of the ion path devices with mass during a scan operation, which improves the resolution and sensitivity of the instrument. The distributed system should be capable of performing this tracking operation even at the fastest scan rates since the limiting factor in the scan rates is the ability of the detection processor to acquire and format a data point. 129 Table 5—6. Scanning Rates for the TOMS Control System. AMU/SEC #AVERABES/PNT #AVERAGES/PNT (1Q points/AMU) single processor distrib. processor 1000 ~-* 1 SOD --- 2 256 1 4 180 4 1o 56 15 :2 L5 32 b4 1% 128 128 5 256 256 2.5 51: 51‘ ...-L ....I. S t-J 4:. I'-’- S |’--J 4:. 130 The increased processing power of this system will also permit new features to be developed such as the use of pulse counting for the detection of low level ion currents and the implementation of intelligent scanning algorithms which scan rapidly where no ion current is found and scan slowly when a peak is found. These features will increase the sensitivity of the instrument and reduce the amount of sample needed for an analysis. Another example of the advantages of separating the tasks into different processors is the use of the softknobs during a split screen or fast scan display. In the single processor system the softknobs task slows the scan display by over 4OZ which causes distortion in the display. In the distributed processor system the softknob task runs on a separate processor from the scan tasks and this results in less than a 5% change in the execution time of the scan tasks when the softknobs are running. The success of the TOMS control system can be further illustrated by discussing the advantages of distributed processing systems that are listed in Table 4-1. The first of the advantages is parallel execution which is demonstrated in the TOMS system during the data collection stage. In the present system the bottleneck in the collection process is the detection processor. However if the present ADC was replaced with a faster ADC the 131 bottleneck would shift to the reduction processor. The bottleneck could even be shifted from the reduction processor to the ion path processor if some specialized signal processing hardware was added to the reduction pnrocessor. The fact that the bottleneck in the data eacquisition operation can be moved between the different fzrrocessors indicates that each processor is executing a rrtajor portion of the overall task in parallel with the c:31:her processors. The experience with this system is that t: fie "overhead” consumes between 8% and 28% of the processor t2..i.me depending on the specific task. This is substantially l (sass than the overhead fraction in the single processor Es-‘;>-’stem. The simpler bus structure and the lower complexity (2"1F: the different modules also allows the easier addition of F1 GEEw interfaces and capabilities to the system as compared i:-t:2 the single Multibus processor system. The advantages of nonrinterference of tasks is 1c3£emonstrated by the Softknobs task mentioned above. The SSeparation of the ion path control tasks and the softknobs driver tasks onto different processors resulted in superior performance because the interference between the two tasks was eliminated. Also eliminated were the task interleaving programs and the priority assignment programs. The simpler modification of tasks can be shown by examining the data acquisition operation. In the distributed processing system A __________A 132 the tasks executing on the reduction processor, for example, could be changed or modified without affecting the tasks running on either the ion path or the detection processors. In the single processor system however, the i:hree tasks are tightly interleaved so any change in one r“outine can easily affect the other tasks. The modulatity of the hardware and the software in the c:i.istributed processing system also greatly facilitates the eaewfihancement of the instrument. If more processing power is l—tleeeded to add a new feature to the instrument another CD tfi—ocessor can be added without major changes to the system “d'i—Iile in the single processor system adding more processing F) (:3wer means starting over with a new processor. The C: :1 stributed processing system is also easier to debug and t:"*‘oubleshoot because of the ease with which a problem can '23‘63 confined to a section of the overall system and also t:’Eecause of the capabilities of the Master processor to EEw-zamine and change any of the slaves memory or peripherals. (As these examples show, the increased processing power of the distributed system permits greatly enhanced control of the TOMS. In the future as the control system is further developed the advantages of the distributed processing system will become even greater. CHAPTER 7 - SOFTWARE - Although the software for the various systems ciescribed in the previous chapters is not part of the t"esearch that this dissertation covers, this chapter will Fzyrovide a short discussion of the software that was written «1: or these systems. This discussion will focus on the I. «anguage that was employed, the modifications that were fr?.é1de to it for use in the distributed processing EE'r‘ivironment, and the resulting commands for the TOMS CZ (:3ntrol system. FORTH LANGUAGE The software for the different control systems was 11mplemented using the polyFORTH version of the FORTH language(49). This version of the FORTH language has several attributes that make it an excellent language for instrument control systems. Some of these advantages are its size, the ability to directly access machine resources, its execution speed, and its extensibility. A complete .' "J 1 ._:..__'a 134 FORTH system that contains the FORTH compiler, an editor, an assembler, and disk and terminal handlers occupies only 8 kbytes of memory. This standard FORTH system contains all of the functions needed for program development and t:herefore does not require the use of cross compilers or sseparate development systems. The standard FORTH system azalso allows direct access to any memory address or I/O port aaaithout the intervening presence of an operating system. _17111s is extremely advantageous in real time control systems vaaffiere much of the software involves interaction with the 1i. rostrument interfaces. This implementation of FORTH can EZIIr-oduce high—level threaded code that executes at BOX to :EE;‘EBZ of the speed of a similar routine written in assembly 3L~«éenguage. This is an excellent speed considering the £5a—‘tzflvantages of writing in a high level interpretive GEPtnvironment. However, if a routine needs maximum speed, the F:?I3RTH system also provides an assembler as an intergal part be the standard system. One of the most useful attributes of FORTH is its extensibility by which new commands and structures can be readily added