IIHWHHIWIHUIHIHHWWHIIHIHHI’HHWII‘IHHI '—I_._. I0); _(/)000 mews This is to certify that the thesis entitled HIGH-PERFORMANCE DATA ACQUISITION FOR REAL-TIME TURBULENCE MEASUREMENTS presented by Pierre Georges Meyer has been accepted towards fulfillment of the requirements for M.S, degreein Electrical Engineering Major professor Date é/éifl 0-7639 OVERDUE FINES: 25¢ per day per item ’ RETURNING LIBRARY MATERIALS: Place in book return to raw charge from circulation rccm HIGH—PERFORMANCE DATA ACQUISITION FOR REAL—TIME TURBULENCE MEASUREMENTS By Pierre Georges Meyer A THESIS Submitted to Michigan State University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE Department of Electrical Engineering and Systems Science 1980 ABSTRACT HIGH-PERFORMANCE DATA ACQUISITION FOR REAL-TIME TURBULENCE MEASUREMENTS By Pierre Georges Meyer A high-performance, computer-controlled, data acquisition system has been designed, constructed and tested. This system, which is based on an LSI-ll microcomputer, collects voltage infermation from up to sixteen hot-wire anemometers located in the cross-section of a wind tunnel. These voltages are later converted to velocities. For ample flexibility, the acquisition unit provides a wide range of sampling rates for any number of channels and offers the advantage of user- definable random channel selection. Moreover, calibration circuits, accessible from the front panel, allow the operator to perfbrm simple tests and make parameter adjustments for any selected channel. Typical sampling rates between 250 Hz and 10 kHz/Channel for eight channels are achieved. And variable gains between two and two hundred are provided to amplify input signals to as large as :_2.5 V before converting them into 12-bit digital data words by means of ultra-high-speed A/D converter. _ 5" .i To my fiancee Midori Shibayama ( K m J; 2’ O ) for her thoughtfulness and love ACKNOWLEDGEMENTS I gratefully acknowledge the technical direction and the constant encouragement I have received from my academic and research advisor Dr. P.D. Fisher throughout this work. Also, I would like to thank Dr. R.E. Falco for his financial support and initiation of the idea for the project and Jeff Piper for his assistance in writing the nec~ essary software programs. In addition, I am indebted to Mike Schuette, Bill Smith and Charles Dorcey for their substantial help in wiring the‘ circuit boards of the data acquisition unit. My particular gratitude also goes to Joanna GrUber, who typed the manuscript with great care and exemplary patience. iii TABLE OF CONTENTS Page LIST OF TABLES vi LIST OF FIGURES vii I. INTRODUCTION 1 II. REQUIREMENTS AND DESIGN ALTERNATIVES 3 2.1 System Requirements 3 2.1.1 General System Description 3 2.1.2 Major Requirements 5 2.1.2.1 Analog 5 2.1.2.2 Digital 7 2.2 Design Alternatives 3 2.2.1 Parallel Conversion and Digital 8 Multiplexing . 2.2.2 Analog Multiplexing and Serial 11 Conversion 2.3 General Description of the Prototype 11 III. ANALOG CONVERSION 15‘ 3.1 General Block Diagram of the Conversion Circuit 15 3.2 Devices of the Conversion Chain and DMA Interface 17 3.2.1 Instrumentation Amplifiers ' 17 3.2.2 Sample-and—Hold Devices 3.2.3 Multiplexer 18 3.2.4 Analog—to-Digital Converter 19 3.2.5 DMA Interface 21 iv 3.3 Front Panel and Calibration Features 3.3.1 General Description 3.3.2 Operation Modes 3 1 Test MOdes 3. . .2 Calibration Modes 03.2. 3 2 3.3.3 Chain Calibration 3.4 Summary IV. HARDWARE ORGANIZATION OF THE MICROCONTROLLER AND THE UTILITY LOGIC 4.1 Hardware Organization of the Utility Logic 4.1.1 Interface 4.1.2 RAM/Delay Circuit 4.2 Hardware Organization of the Microcontroller 4.2.1 The Clock Circuit 4.2.2 Microcontroller Design Considerations 4.2.2.1 Basic Microinstruction Cycle 4.2.2.2 Time Allocation for the Main Tasks 4.2.2.3 Design of the Control Logic ,4.2.2.4 Diagnostics 4.3 Summary V. DEVELOPMENT AND EVALUATION Preliminary Study and Design Construction System Evaluation 01mm MNH 1 General Data Acquisition Procedure . .2 Tests and Results 5.3. 5 3 VI. CONCLUSION APPENDIX Data Acquisition System Photographs REFERENCES Page 22 22 .24 27 27 28 32 34 34 34 36 39 39 42 42 42 46 52 52 S6 56 S6 U57 S7 S7 61 64 72 3.1 4.1 4.2 6.1 LIST OF TABLES Analogsvoltage/digital-code correspondence Sampling rates as a function of the number of channels Microcontroller microcode Evaluation of total cost Page 20 47 53 62 LIST OF FIGURES Block diagram of the overall measurement system Typical anemometer output signal Block diagram of the parallel conversion/digital multiplexing alternative Block diagram of an analog multiplexing/serial conversion circuit General timing diagram of the prototype design Conversion chain and associated circuits Front panel and calibration circuit Calibration switching circuit and measurement apparatus Calibration switching modules on front panel Manual sample and convert features Hardware organization of the utility logic RAM/delay register select logic Block diagram of the microcontroller Function block diagram of the clock circuit Typical microinstruction cycle Microcontroller timing relationships Flow-chart for control logic activities Control logic (part one) vii Page 12 14 16 23 25 26 29 35 37 40 41 43 45 49 SO Page 4.9 Control logic (part two) 51 4.10 Timing diagram for all channels except the last 54 4.11 Timing diagram fer the last channel 55 5.1 Elow-chart of calibration and data acquisition procedure 59 A.l Data acquisition unit with minicomputer system 55 A.2 Close-up view of the front panel 66 A.3 Logic circuit board 1 67 A.4 Logic circuit board 2 68 A.5 Input/output board 69 A.6 Analog-to-digital conversion board 70 A.7 Typical analog board 71 viii CHAPTER I INTRODUCTION The study of turbulent and unsteady flows in wind tunnels has become an important aspect of modern applied rescarch in fluid mechanics (1,2). Randomly occurring coherent motions Within such flows are being investi- gated in order to uncover their physical properties. To examine such three-dimensional flow features, detailed quantitative information about the streamwise and normal velocity fluctuations is required; Hot-wire anemometry is a technique commonly used for this purpose (3). This research effort deals with the design, construction and evaluation of a data acquisition system that is used to sample, digitize, and store réal-time turbulence data derived from an array of anemometers placed in a flow fiehi. This instrument offers a wide range of sampling rates to accomodate an equivalently large series of signal frequency ranges. It collects data from up to sixteen anemometers, since such a number is required to perform measurements with satisfactory spatial resolution. In the long range, the unit is intended to connect to a computer system with powerful storage facilities-- high—density memory or disc. This operation will permit long data streams to be taken. Such streams facilitate the detection of an increased number of coherent motions during a single acquisition experiment. Eventually, the data acquisition syStem will also command the shutter—release of a camera to combine the hot-wire anemonetry measurements with simultaneous flow visualization in order to Obtain a pictural description of the phenomena under investigation. This thesis presents a complete study of the data acquisition system in question. Chapter 2 delinéates the basic requirements for the features to be incorporated in the design. Chapter 3 examines the analog-to-digital conversion chain and its associated calibration circuits. The hardware organization of the microcontroller and the utility logic is treated in Chapter 4. Finally, Chapter 5 summarizes the development phases, includ- ing testing and evaluation of the overall system. CHAPTER II REQUIREMENTS AND DESIGN ALTERNATIVES This chapter establishes the requirements of the data acquisition system and presents the various alternatives. The first section, Section 2.1, introduces the data acquisition unit and its interre- lation with its environment and closely examines its different require- ments. Section 2.2 illustrates the design alternatives with their respective advantages and disadvantages. Finally, the last section, Section 2.3, defines a precise model for the desired data acquisition system. 2.1 System Requirements 2.1.1 General System Description Figure 2.1 gives the block diagram of the overall system in which the data acquisition unit is incorporated. The data acquisition system collects analog information from the transducer and signal conditioning unit. This unit comprises a given number of transducers - anemometers - that deliver the signals to be processed by the data acquisition system. Each transducer generates a signal proportional to the physical variations in the resistance of its probe (4); such variations are induced by equivalent variations of the flow of gas in the wind tunnel. The data acquisition unit then converts the signals from the different anemometers into a digital code that is consecutively sent to the microcomputer through appropriate interface devices. The system uses an LSI-ll (5). This Emumxm unoEoHSmmmE Hawno>o any mo eunmmflw xooflm H.N ohnmfim mamaocmwhom HHfiD HHCD I o use oummpouaH soapfimfisvo< spun mcacoapawcou wou9n5000howz . oocwshoMHom swam Hmcmwm paw Ii T o «\HH u .qu I Hooswmcenh microcomputer performs the following tasks: initialize the data acquisition unit, start the acquisition process, store the converted data temporarily in main memory, transfer blocks of data to disc, execute diagnostic tests, and, finally, retrieve the infbrmation from disc for further processing. This study focuses on the data acquisition unit. Nevertheless, it is essential to understand the characteristics of the computer and its interface as well as those of the transducer and signal condition- ing unit to meet the front and rear-end compatibility criteria; so, these factors, too, will often have to be referred to in later sections and chapters. 2.1.2. Major Requirements The overall system requirements constitute the cornerstone for this study and may be subdivided into two areas: analog and digital. 2.1.2.1. Analog For the analog circuitry the requirements may be enumerated as follows. First, the unit has to process signals through eight dif- ferent channels, a number which should be expandable to sixteen, with channel inputs fully compatible with the transducer outputs. The second requirement regards the conditioning of the anemometer output signals. The signals delivered by the transducers have a dc offset of a few volts on which an ac component of a few tens—of—millivolts is superimposed (see Figure 2.2). Both components are important for the turbulence studies (2). The dc component corresponds to the average velocity of the fluid flow as seen by the transducer. A feature Composite Signa1(V) DC Component (V) AC Component(mV) 2 -r- 1 .- i i > 500 1000 Time (ms) 2 1 .. I I > 1 l 500 1000 Time (ms) 30 20 10 ~10 —20 . l I . 5 V 1 0 Time (ms) Figure 2.2 Typical vanemometcr output signal in the calibration circuit has to be implemented to evaluate its value. In addition, for optimal use of the resources, this dc component must be eliminated during the data acquisition process to save only the information corresponding to the ac component. And this ac component must be amplified by means of an instrumentation amplifier with variable gain. Gains of 2 to 200 must be available. As a third requirement, high stability -4 :_O.S mV/min -- and minimi— zation of the noise have to be given a high priority in the design and construction phases of the analog chain. Finally the calibration procedure and its features on the front panel must be made as simple and attractive as possible to the user. However, for this objective, a compromise will have to be found because simplicity for the user undoubtedly means complexity in the circuitry. But circuit complexity must be balanced with the need for timeliness in the completion of the design objectives. 2.1.2.2 Digital Three main requirements must be considered with the digital circuitry. First, provisions must be made so that analog channels can be accessed either randomly or sequentially. In addition, all channels must be sampled simultaneously and their sampling rate must be made variable and definable under program control. Rates between 500 Hz/channel and 10 kHz/channel must be allowable for eight channels or less. The last requirement concerns the intrinsic characteristics of the A/D converter(s); Since the word length of the computer is sixteen bits, for optimal use of its storage Space the word length of the A/D converter(s) should be at least twelve hits; the remaining four bits must contain the analog channel address. And the choice of the A/D converter(s) must be dictated by such important criteria as accuracy, stability and linearity. For both the analog and digital circuits, additional hardware must be provided for convenient diagnostic tests and easy trouble— shooting. But any increase in hardward renders the system less cost- effective and lengthens system deve10pment time.. Fifteen-thousand dollars was budgeted fer this data acquisition system, and six months were allocated to design, construct, and test it. Therefbre, compromises were imperative for the final design. Having defined all the general requirements, the different design alternatives can now be considered. And this is the purpose of the next section. 2.2 Design Alternatives To fulfill the requirements delineated in-the preceding section, trade-offs must be established between circuit complexity, convenience fer the user, sampling speed and cost. These factors will be examined in the next subsections for the different design alternatives. These can be classified into two main categories depending on the type of conversion-“ parallel or serial-- and the type of multiplexing -—analog or digital-- involved. 2.2.1. Parallel Conversion and Digital Multiplexing Figure 2.3 illustrates the organization of a parallel conversion/ digital multiplexing data acquisition system. The signals from all channels are sampled simultaneously and subsequently converted in “waging :o_uaua_~su can ~ocam one»; poguouucou e o>wumcyoufim mcfixofimwuflss Hmpfiwfiw\:ofimno>coo Hofiamuwm may mo Emhmmflv xoon m.N manna» umuc. x9“ _u _ _ = A — howouoa cam; a"- o» .9 .wwumw my Au ~.:_ _ an a q o : Em IV. 2 .8333. Em A 8:32. .>:OU Hhaum om Q\< .>:OU ukaum m n\< as a, :83 2 .5 Em H Em ., a, 3 .QE<\.um:~ I l I I l I i H .9553”: ooaw aneucn muouososoca 20am 10 parallel. The digital codes are then strobed into their corresponding registers. These registers have tri-state outputs and are enabled in sequence or randomwise. To drive the address lines of the 4-to-16 line decoder, the utility logic may include the following features: A register loaded under program control selects the desired channel before reading in the infermation. With this method, any number of registers may be scanned and in any order, but at an important sacrifice in speed. A 16 x 4 RAM, driven by a 4—bit binary counter, is pre-loaded with any sequence of analog-channels during an initialization cycle. This scheme allows the control logic to access the analog channels randomly by incrementing the RAM counter sixteen times. Such a method, however, may result in the acquisition of a sig- nificant amount of superfluous data if less than sixteen channels are desired. In other words, it may not procure an Optimal use 'of the storage resources of the system. A 4-bit binary counter addresses all Sixteen registers directly and therefbre in a fixed sequence. A gain in speed is achieved over the previous alternative but only sequential access is possible, and the problem of waste of memory space remains unaltered. An improvement in speed and minimization of storage of useless infbrmation can be achieved by using a presettable counter instead. But this method still prohibits random access. Tb keep the attractiveness of random channel selection along with high-speed achievement and a total elimination of wasteful code, a 16 x 5 RAM, driven by a counter, may be used. This 11 memory, when pre-loaded, contains only zeros in the fifth bit except for the last channel. The control logic examines the status of this bit to decide when to terminate the sequence. Also, identical perfbrmances may be achieved with a 16 x 4 RAM driven by a presettable counter. These alternatives, except for the first one, are all suitable fOr very high acquisition rates. The drawback, however, lies in the cost. The A/D converters are the most expensive devices; therefbre, their number should be minimized. The next subsection presents an alternative that takes this factor into account. 2.2.2 Analog Multiplexing and Serial Conversion The block diagram of the typical circuit is given in Figure 2.4. In the case of analog multiplexing and serial conversion, again all channels are sampled simultaneously. Then, during the hold time, they are multiplexed and converted serially in a sequential or random order. All features, outlined in the preceding subsection for the utility logic, are still valid and their relative advantages and disadvantages remain the same. Nevertheless, in a global way, due to serial conver- sion, the performances in speed are drastically degraded. The trade-off, however, is an important upgrading in cost-effectiveness in comparison- with the previous cost. Using the general considerations discussed in this section, the next section describes a prototype of the final design. 2.3 General Description of the Prototype The compromise between speed and cost, when weighted with the 12 pwaoafiu cowmno>coo waaom\wnflxoamfipaaa mofimnm cm mo amummfiv xoon v.m ohsmfim uwzouwu camununwmuu van flocum ucoum uofifiouucoo e oauos sasunuz Tl : n _ Pam I! .3333. — .230 935 I' Sakai—cu o\< _ l a H uoxo~mwuasx uo~a=< a . cu . on zxm as =\m zxm A =\m 2 9325 u I I .. n n .. d 5:2“ muouofigofla 30km comm -uou:~ 13 requirements, suggests the choice of an analog multiplexing and serial conversion type system. Due to the poor implicit Speed performances of such a system, to achieve a 10 kHz/channel sampling rate, the following elements must be considered for speed enhancement. The sample-and-hold devices must be chosen so as to have a short acquisition time; the multiplexer a low settling time; and, finally, the A/D conver— ter a very fast conversion rate. Moreover, the minicomputer must possess the capability of acquiring the digital data in the shortest time pos- sible. Therefore, the unit must make uSe of direct memory access (DMA). Finally, the utility logic must include the following features. To implement a variable sampling rate, a delay counter combined with a delay register loaded under program control during initialization, will have to be introduced. After the successive conversions within each sampling period, the control logic may preset the counter to the value stored in the delay register and decrement it to zero. And, to keep the flexibility of random channel selection, the utility logic will also comprise a 16 x 5 RAM to contain the sequence of the channel addresses with an extra bit for the last channel indication. Figure 2.5 gives the general timing diagram for the data acquisi- tion process and illustrates the sequence of the various tasks of the unit. As shown, for optimal effectiveness the DMA cycle fer a given channel overlaps with the conversion cycle of the next channel. The different tasks are controlled by a microcontroller which is enabled and disabled under program control. Chapter IV will fully describe this microcontroller as well as the utility logic and their associated diagnostic circuits. 14 :mwmov ofipggm 05 mo Enamwfiu 9553 3.850 m.~ 093mg . . . . . . _ _ _ . _ . _ _ .A o u u a ” OHM. “iiimnHU _ . _ _ _ _ _ _ . _ _ _ . . . . _ _ . . _ . _ 05:. U u .D _-..-..--..._U .U . . _ _ . . . . . . . . . . . . . . . . . . . . . 2.: 9.52% W _ U I I I I I I I . D W . 9983332 . . . . . . _ . . . . . . . . . _ . _ . _HHH H . . . . as up: new _ .IIIIIII. _ _ 2. .H m . . _ . . . _ . . . . . . . . . . . _ . _ . . . H0585 . 5:956 .339 _ 3585 . . ”0:526 . "0:526 . «535nm any: . 323$ . 3.3 . _ vacuum . any: . 3:35 oocoscow 2.: an 33 «5358 I e voice «5358 iv CHAPTER III ANALOG CONVERSION The purpose Of this chapter is to give a detailed presentation of the analog-to-digital converSion chain and the calibration features that it uses. Section 3:1 is an introductory paragraph describing the prin- cipal connections between the major building blocks: These blocks and their more elementary components are examined more thoroughly in the subsequent sections. Section 3.2 focuses on the amplification and con— version devices as well as the interface needed for data transfers to the computer. And Section 3T3 concludes the chapter by di5cussing the calibration and front panel circuits and by outlining the theory of the required single-channel chain calibration. 3.1 General Block Diagram of the ConversiOn Circuit Figure 3.1 illustrates the organization of the conversion chain. The given block diagram primarily attempts to emphasize the data flow between all constituent parts. In this perspective, it shows that the outputs of the anemometers connect to the inputs of the instrumentation amplifiers via the front panel and calibration circuit. The outputs of the instrumentation amplifiers drive the inputs of the sample- and—hold devices through a similar path. For circuit simplicity, however, such a scheme has been abandoned for the link between the sample—and-hold devices and the multiple Xer.’ Instead, direct connections are provided. But this restriction finds its compenSation in a special calibration feature that allows theSe lines to be inspected, too, if desired. Any 15 16 :Inalrg uorlezqueg put {curd 3u015 33930 woodwoommm us... 596 53328. 1m onswfim xn~ammv mcuczou gouco>ccu :\< < Leummuoz mzusum coxo~;_-:: uo~::< H E 45:5. Em A 55>on A >28 25% 4 Fr H who>:OU A4 uhflum l 1:. p A _ H” .5 - .5 N— v >—-> o~ v_c: nuuofinscw a~ zwm _ 1_o: -w-o~nanm m ”HM Essa... .2. ¢~ WD+<+m 5.505. 586 IV 5.20: .65 2505 55w k—2~ 723m OI OI 0383131111 we 2 i l '.\ZiO 17 of the multiplexer inputs, when selected by means of the four channel address lines --CAl, CA2, CA4, CA8—-, is steered towards the Output and consecutively connects to the input of the A/D converter via the cali- bration circuit. After eath ConverSion, the digital output code of the A/D converter is strobed into a register and then either displayed on the front panel or transferred to the Computer through a DMA interface. Sampling, channel selection, or converSion initiation are either per- formed manually or under microprogram control. The front panel and calibration circuit is used to control either mode. The front panel and calibration circuit are presented more completely in a later section. The other blocks of the overall converSion circuit are discussed in the next section. ........ This section is devoted to a brief review of the different elements of the conversion chain. Emphasis is placed on their major characteris- tics. The section finally concludes by treating the DMA interface and its properties. 3.2.1 Instrumentation Amplifiers The system uses for all the channels the AM—ZOlC instrumentation amplifier from Datel Systems, Inc. ( 7). This device provides the user with a variable voltage gain -- l to 1000 -- programmable by means of an externally adjustable resistor R G must have a very low tempature Coefficient. The gain is inversely pro- For high stability, this resistor portional to the value Of R and its equation is simply G = 200 K/RG. G For internal offset adjustment, a good quality external trimming 18 potentiometer is required. Additional characteristics of the AM-201C are an excellent common-mode-rejection ratio(CMRR) -- ll4dB --, a worst case input drift of ~251uV/OC, a maximum gain nonlinearity of .01% and a 3 dB bandwidth Of at leaSt 45 kHz for all allowable gainsi' These properties make this component an excellent option for this type of application. 3.2.2 Sample-and-Hold Devices Monolithic integrated circuit sample-and—hold devices SHM-IC-l from Datel Systems haVe been choSen ('7). Their selection was based on such important criteria like short aperture delay --50 ns—- and a low acquisition time. The circuit must include a good quality polystyrene type capacitor of .001 uF to achieve an acquisition time of 5 Us for a 10 V step up to .01% of its final value: The sample-and-hold devices are used in the unity gain noninverting configuration with an external trimming potentiometer for offset cancellation. For optimal operating conditions, their arrangement on the circuit board fellows exactly the scheme of the manufacturer's proposed layout. 3.2.3 Multiplexer The circuit makes use of a 16-channel MX-1606 single-ended CMOS multiplexer from the same company ( 7). It allows channel sampling rates of up to 200 kHz and a transfer accuracy of .01% over i_10V signal swings. Very low source impedances —- under 1 kn -- and an extremely high load impedance -1 above 100 MO -— are needed to achieve Such an accuracy. The first requirement is undoubtedly met because the" output impedance Of the Sample-and—hold devices is typically 0.2 D. 19 But for output compatibility with the low input resistance of the A/D converter -- typically 2 k9 --, a unity gain buffer amplifier is in- serted between the two Stages: In this respect, a CA3140 operational amplifier from RCA is the right choite (:8). Indeed, this device has a typical input resistance of 1.5 T9 in addition to a very low offset and a high bandwidth.' 3.2.4 Analog-toQDigital Converter For ultra-high Speed data conversion, the system makes use of a 4133-22 12-bit A/D converter from Teledyne Philbrick (5)). This device has been selected because of the excellent performance/price compromise it offers. By means of the successive approximation technique, typical conversions are executed in 2.5 us. Two conversion modes are available, unipolar or bipolar, but bipolar is imperative for this application. .For this mode, an extra option is provided. Both offset binary or two's complement codes are offered but for easy data handling, the natural choice is two's complement because this is the number system representation used by the computer. The correspondence between the analog inputs and the digital outputs for this code is shown in Table 3.1. With regard to the transfer characteristics of the A/D converter, the typical nonlinearity, differential nonlinearity and quantizing errors are :1 LSB, 11/2 LSB and :1/2 LSB, respectively. Finally, only two control/status lines are needed. A positive—going pulse with a duration from 35 us up to 200 us on the Start Convert line is required to initiate a conversioni And the high-to-low transition on the Status line Can be Utilized to Strobe the OutpUt code into a register: This line may also be inspected by the microcOntroller to cheek if the" 20 TABLE 3.1 ANALOG-VOLTAGE/DIGITAL‘CODE CORRESPONDENCE Analog Input Input (Volts) Digital output (12 bits) +FS + 5.0000 100...000 +FS - l LSB + 4.9976 100...001 + 3/4 Scale ' + 3.7500 A 101...000 + 1/2 Scale + 2.5000 110...000 o + 1 LSB ’ + 0.0024 111...111 0 + . 0.0000 000...000 0 - l LSB - 0.0024 000...001 - 1/2 Scale - 2.5000 ' 010...000 - 3/4 Scale - 3.7500 011...000 - FS + 1 LSB — 4.9976 011...111 FS = Full Scale LSB = Least Significant Bit 21 conversion time remains within prescribed margins. 3.2.5 DMA Interface The interface is a general pupose direct memory access DRV-llB interface from Digital Equipment Corp. ((5). Transfer rates of up to 250 kwords (16 bits/word) are possible in single cycle mode: The interface contains five registers. These are a word count register -- WCR —-, a bus address register -- BAR --, a control/status register -- CSR --, an input data buffer register and an output data buffer register. As suggested by their denominations, WCR contains the two‘s complement of the number of words to transfer and BAR the address to which an input transfer takes place or from which an output transfer originates. During normal operation, the contents of WCR and BAR are incremented after each tranSfer unless disabled by means of a dedicated bit in the control/status register. When WCR increments to zero, the processor automatically branches to an interrupt routine, provided that the interrupts have been previously enabled. Interrupts and DMA trans- fers are enabled under program control by setting special purpose bits in the CSR register. Once they are enabled, the user's device must_ assert specific control lines to define the desired transfer type -- word or byte, input or output. These lines may just be tied to fixed levels if, for a given interface peripheral, the transfer type is predefined and unique as it is the case for this system. The most important line required to initiate a DMA cycle is CYCLE REQUEST. This line must be conditioned by the microcOntroller at appropriate times. As indicated in Figure 3.1, the system makes use of’a few additional features offered by the DRV—llB interface board, namely;INIT, FCNTl, 22 FCNT2. These lines, asserted under program control, initialize the system, start the data acquisition process and terminate it, respectively. 3.3 Front Panel and Calibration'Features' 3.3.1 General Description Figure 3.2 illustrates a detailed block diagram of the front panel and calibration circuit. The inputs and outputs of the devices from the sixteen channels connect to the meaSurement aparatus via the cali- bration switching circuit and a set of seventeen eight-pole double-throw interlocked switching modules -- SW1, SW2, .., SW17. Each switching module, except SW17, selects a given analog channel and directs its particular devices towards the calibration switching circuit. Inter- locking provides mutually exclusive channel selection. The modules also connect the positive input terminals of the instrumentation ampli- fiers to variable DC voltages which will constantly be referred to as external offsets. These offsets are available from a series of potentio- meters -- TRl, ..., TR16 -- fixed on the front panel and with terminals connected to a very stable voltage reference. Figure 3.2 depicts, as an example, the case in which channel #16 has been selected for calibra- tion. Switching module #17 is not drawn. Its sole purpose is to lock out all other switches at the end of a specific channel inspection. It is important to note that this switch must remain depressed during multi- channel data acquisition in order to keep the entire acquisition chain isolated from the calibration switching circuit. Subsection 3.3.2 presents a complete schematic of this switching circuit.and analyses the Corresponding calibration modes. 23 From fi— Ancmometers I SW1 SW16 Measurement Apparatus SW1 SW16 Calibration Inst./Amp. Vin- I Switching ‘L Circuit L 7 Voltage reference , -s.sv +5. sv I I I I I I I I I I TRl TR16$ 1 2 3 4 s 6 7 8 9 I I - v 1 I I SW1 W16 l I I L P ' ' I I I d b I I SW1 _ I I Inst./Amp. ' SW16 I I + f ' 8L2 - - - - - - A , I Em " ' Inst./Amp. I Display I . ' Outputs N r sm swus I i ‘ i I I I P CONVTEST I I 1 I I I> I I SW1 SWl6 I I I I I S-fi-H . I . Inputs .‘L ' ' S-s-H ; I - I I Outputs I MUXI - MUX4 I I swr izL__g}: " - wm ‘ ¥¥§4I ‘I_, - Imx II Multiplexer ‘ T ’ LED I I Output ’ I I .., H A/D Input ‘ Register [12 Manual S-E-H Output 1’ ,L T and Convert 4. CAI-CA8 (L 1’ Features ‘ I ET ' a. I. Q START Start convert ‘ cox‘y slfi Figure 3.2 Front panel and calibration circuit 24 Besides the aforementioned features, the frOnt panel includes dedicated circuits to select, for a specific application; either manual or microcontrolled sampling, converSion and multiplexer channel speci- fication, as shown in Figure 3.2. In addition hexadecimal LED modules are provided to display, during manual operation, the selected multi- plexer channel and the result of a conversion and to reveal a possible conversion error during the acquisition process; Finally.an extra LED on the front panel is used to inform the user when the microcontroller is in the RUN mode. 3.3.2 Operation Modes Figure 3.3 gives a detailed sketch Of the calibration switching circuit. Three arrangements of multi-pole double-throw interlocked switching modules can be distinguished: These are reproduced in Figure 3.4. The different operation modes are selected with the main switchrack. They can be classified as independent, test or calibration modes accord- ing to the grouping in Figure 3.4. The unique purpose of the external mode is to permit external AC or DC signals to be measured by means of the installed apparatus without having to disconnect it from the calibra— tion circuit; and the non-calibration push-button is just used to lock- out all other switches. The test and calibration modes, exclusively, make use of the two extra switch Sets. The AC/DC switchrack allows the gain adjustment of the instrumentation amplifier to be performed either by an AC source or a DC source. And the Input/Output set (Vin-lvin+’ respectively) is required to link With the desired meaSurement instru- terminals, ment either the input or the output (the Vin— or the vin+’ respectively) of the device being tested or calibrated (the instrumentation 25 msueuwmmm ucoaonnmmos use pwzoufio wcfigouflzm compennwaeu m.m shaman w h o m e m N H a\< x2: 55 cm So CL I 3: Zn _ .3. a A I \M 8 25> < _ 0w 9W! F -5> PI. <50 om . ? zu _ z“ r u up on on 2... \< moml A A H xm _ w o o r 3: “Duo: m. m+ r exm m sentence , exm -: .. . - . Aw C u C aecufim a. Ne «ecuww encumo-uumo youauocou you05u~o> on 13.888 nouoau~o> on yous—83> 8 u< 22.888 Emacs“; u< “9&3 u< mcmueuo>< 26 Input/V. _ Output/V 1n in+ ’/ \ ’1 \ \ .r \ " a"’\ \ V Ou in+ Input tput .. __ AC pg f' '1 r' '1 r' ‘1 t' "‘1 I' '1 l. .J l. .J L... .I ...J .. .I /’ \ ------1:| EO/CHAIN NCAL EXT EO/CHAIN GN 10 S/H A/D Figure 3.4 Calibration switching modules Non-calibration mode ' Independent External measurement External offset/chain calibration Gain adjustment Calibration q Internal offset reduction Sample-and-hold test Test Multiplexer test A/D Converter test on front panel 27 amplifier, respectively). The interdependence among the various switch- ing modules is also illustrated in Figure 3.4, but the role Of these switches finds a better explanation thrOughout the following subsections. 3.3.2.1 Test Modes There are four test modes. During the internal offset mode —- IO --, both inputs of the selected inStrumentation amplifier are connected to the analog ground. DC Voltmeter #1 is directly connected to its output so that it displays the actual internal offset; This offset can then be reduced by means of the aSSOciated trimming potentiometer on the amblifier board. When the S/H or MUX'pushébuttons are depressed, the input of the sample—and-hold device is automatically linked with the variable internal DC reference shown in Figure 3.3. The value of the corresponding voltage can be read on DC voltmeter #1 if the Input switch is set. When switching over to Output, either device presents its output to the same voltmeter, depending upon which mode has been selected. Both modes enable manual sampling and channel selection. To see if the device in question works properly, the sample-and-hold toggle switCh, shown in Figure 3.5, must be activated and the value read from either output must coincide with the value previously measured for the input. Finally, for the A/D mode the internal DC reference is directly con- nected to DC Voltmeter #1 and to the input of the A/D converter. The' conversion toggle switch, represented in Figure 3.5, is then used to start a conversion. The resulting code appears on the display and may be compared to a more detailed verSion of Table 3.1. 3.3.2.2 Calibration Modes During gain calibration —- GN -— the positive input terminal of 28 I Toggle SWitCh D. _. I s 4* 2 N7_-L ‘ fl DO- Monostabl e L__... - __ Debounce I S3 I 54 n S/‘I‘I‘ Toggle Switch “"'1 , 120 ns . V“ I .n. ' ‘DO' Monostable V A/D Start . . I k. Convert Inu— ' ’ Debounce START CONV Figure 3.5 Manual sample and convert features 29 the instrumentation amplifier is tied to the analog ground. The negative terminal is either connected to the internal DC reference or to an external AC generator depending upon the status of the AC/DC switches. For both options,the Input/Output switches allow the in~ spection on the AC or DC voltmeters of both the input and output signals. The ratio between both Signals defines the gain. Due to the high common- mode-rejection ratio of the amplifiers, gain calibration with or without external offset yield the same results. With the AC option; both input and output can be viewed on an oscilloscope. This feature is useful when noise phenomena or possible oscillations at very high gains are to be examined. For the external offset/chain calibration -— EO/CHAIN -- modes, the positive input of the instrumentation amplifier connects directly to the external offSet and the negative input to the internal DC reference. The value of the output is automatically displayed on DC Voltmeter #2. The Input/Output switching modules permit both signals on the input terminals to be checked and have been renamed Vin-lVin+ for this case for obvious reasons. This mode is not only devoted to the adjustment of the external offset but also to perform the evaluation of the overall transfer equation for each individual'channel. This opera- tion is entitled chain calibration and is exposed in the next paragraph. 3.3.3 Chain Calibration Chain calibration is necessary to take care of all inherent errors. Even when minimized, their cumulative effects can be significant. The major errors are the internal offsets of the instrumentation amplifier, the Sample-and~hold device and the buffer amplifier as well as the Offset of the A/D conVerter and its nonlinearity, differential nonlinearity and 30 quantizing errors. Gain and nonlinearity errors of the sample-and-hold device can be considered as.negligeable according to the manufacturer's data sheets. In addition, due to the excellent impedance characteristics of its sources and load, the multiplexer doesnot introduce any transfer error. Taking the main errors into account, the partial transfer equationa are yl = Ag + B for the instrumentation amplifier y2 = y1 + C for the sample—and-hold device ' Y3 = y2 + D for the buffer amplifier Y = 573 + F + G for the A/D converter where: x = vin— ‘ Vin+ A = gain of the instrumentation amplifier B = offset of the amplifier C = offset of the sample-and-hold device D = offset of the buffer amplifier E a gain of the A/D converter F = offset of the A/D converter G = nonlinearity + differential nonlinearity + quantizing errors Y digital code All parameters, except G, are fixed but may vary slightly with temperature. C on the other hand occurs randomly in time with positive and negative excurSions and therefore may be considered as a random variable with zero mean. For that reason, when taking the average of several digital samples‘ for a very stable analog voltage x, the Overall transfer equation is Simply: 31 y = AEx + (EB + BC + ED + F). Thus each channel has a transfer equation of the form: y ='Mx + N This equation may be rewritten in an equivalent form as: y Mz + P where: , = + , z x V1n+ P = N - M; Vin+ M and P are two coefficients to be evaluated. Once their values have been computed, the analog voltage samples are easily recovered from the stream of digital data by applying the following equation: 2.42.111 M To compute M and P, the requesite steps are as follows. First, by means of the gain calibration feature, the gain is adjusted to a desired value that will remain unaltered at least until the overall data acquisi- tion process has been completed. Then with the external offset calibra- tion circuit, the positive input terminal of the instrumentation amplifier is adjusted to the value displayed by the averaging voltmeter. This value represents the DC component of the Signal delivered by the anemOmeter of the given channel. From that point in time, Vin- is adjusted so as to yield a value on DC Voltmeter #2 close to the upper extreme of the full scale of the A/D converter. A series of conversions is then performed under program control and a first couple of values (z ) obtained. The process is finally repeated I’Yl with Viné chosen so as to produce an output voltage On DC Voltmeter #2 near the lower extreme of the full scale. This operation yields a second 32 result (22, y2). M and P are then simply obtained by the formulas: 'y2-y1 . , = z -z bits/Volts ' 2 1 z y —z y . P=—-————2:_1z2 bits ‘2 .1 These coefficients define a precise correspondenCe between the analog voltages and their corresponding digital samples: After each chain—calibration; care must be taken not to alter the external offset or the gain of the amplifiers in order to keep the coefficients unchanged for the overall data acquisition process. 3.4’ Summary The chapter presented a typical data acquisition system with sixteen analog inputs and a 12-bit digital output. The incoming signals can be amplified with gains of two to two-hundred, adjustable with onfboard potentiometers accessible from the front panel. DC components between -5.5 V and +5.5 V can be eliminated by means of external offset voltages. With a gain of two, AC signals with maximum deviations of :_2.5 V can be converted. On the other hand, only peak values not exceeding :_25 mV are measurable for a gain of two hundred. In the optimal case, sampling rates of 10 kHz/channel can be achieved for eight channels. Due to the short duration of the calibration procedure and the data acquisition process, drifts due to temperature are expected to be negligeable. As optimal conditions are rarely met, inherent transfer errors will haVe to be minimized by allowing more acquisition time for the sample-and—hold devices and more Settling time for the multiplexer, i.e, by redUcing the maximum expected 33. sampling rate. The next chapter treats the design of the microcontroller and considers this important factor, when allocating specific time frames to the elementary operations within a data acquisition cycle. All additional inherent errors, namely the internal offsets, are taken care of by the chain calibration of eaCh individual channel. But ‘ special attention must be given to the minimization of noise voltages at the inputs because they yield digital output errors that are pro- portional to the gain. As a reference, with a gain of two, the output error corresponding to an input noise Voltage of i_0.5 mV is 1/2 LSB. This problem must be dealt with during the construction of the circuits. The tests performed to evaluate all the real performances of the system with respect to the previous considerations, and their results will be presented in Chapter 5. CHAPTER IV HARDWARE ORGANIZATION OF THE MICROCONTROLLER AND THE UTILITY LOGIC This chapter presents a more in—depth analysis of the microcontroller and its associated utility logic. The utility logic is described in Section 4.1. As indicated in Chapter 2, its purpose is to store the sequence of the selected channels and the delay required for a variable sampling rate. These uSer-defined functions serve as parameters for the microcontroller; Section 4.2 discusses the hardware organization of the microcontroller and the necessary steps in its design. 4.1 Hardware Organization of the Utility Logic Figure 4.1 illustrates the organization of the utility logic. Two main hardware sections can be distinguished: the interface and the RAM/delay circuit. These are described in detail in the following subsections. 4.1.1 Interface The interface, a general purpose DRV-ll parallel interface board from Digital Equipment Corp. ((5), directly connects to the LSI-ll bus. It is characterized by sixteen diode—clamped data input lines -- INOO- INlS —- and sixteen latched output lines —- OUTOO—OUTlS for input/output data transfers operated under program control. In addition, the inter- face provides the user with four control lines for hand—shaking purposes; These are: NEW DATA RDY, DATA TRANS, REQ A and REQ B. The latter two permit interrupt requests to be generated from the interface peripheral 34 35 oflmoH xuwawp: on» mo :ofiuwNflcmmno ohmswhmm 3000-00.50 N 3. $ng N \ v0 .50 u 00 .50 .2 .50 n 00 .50 45. >a¢ 52. \ .25. IIIA up: 025. an. mum .mmm \ anon came \ _.Jmmwuuuiuoufifiawuwzu \ m c mu m .2. Em :. \ , .b. t .2. 2 j «E58 :5. _ _ noucaou xu~oo _ , ‘ n c , - . <-< v hr mm .30 0 r 7 . zs_msno~ .nr xuoau vzH-czH nuaomocuunav . y x 35.8 E ex=:-~ x3: . ~. .o acnm-ga~u new x < e n E. .25 5.. lthOA ‘ ~ 33352.3 5 H" 2H-mo 2H com Auaumccmaaav mm .» ~ ‘ :ouuom ODBJJBIUI 191 1919:! I I “AUG 36 to the computer. NEW DATA RDY (DATA TRANS, respectively) is a pulse which inferms the user that an output transfer (an input transfer, respectively) is taking place. This particular application makes use of the NEW DATA RDY pulse only. Its pulse width is normally SSOnSLbut can be extended to higher values of up to lSOOns by adding an external capacitor. The trailing edge of NEW DATA RDY may be used to strobe the output data into the user's device.’ Since the data is not stable when the leading edge of the pulse occurs, an Option on the board allows the pulse to be shifted in order to use this leading edge for the same purpose. Finally, two additional lines -; CSRO and CSRl -- are avail- able to control the interface peripheral. They are set and reset under program control by setting or resetting their respective bits in the Control Status Register. Also, an initialization line -- INIT -- is provided for optional interface resetting. 4.1.2 RAM/Delay Circuit As illustrated in Figure 4.1, the DRV-ll interface board, described in the previous section, is used to transfer data to the RAM and to the delay register. Figure 4.2 gives the detailed diagram of the select logic that is used to strobe the data into one terminal or the other. Data transfers only take place when the microcontroller is in the idle mode, i.e., none of the lines controlled by the microcontroller are in their true state. A low level on CSRO (high level, respectively) selects the delay register (the RAM, respectively). To load the RAM, only the five least significant bits are neceSSary. For the register on the other hand, twelVe bits are required for reaSons which beCome obvious in the next section. The CSRl line is used to increment the RAM counter; This 37 ofimoa pomHom Houmfimoh xmfiow\2200 $2.5 Ya 01 3mg 35:00 v.8. 025. n 3 20 uOmoH u: :9. L H 032 v 8 E I . .Sm 02:0 Hm; Vial OCH Homom j l_ 002“ 2: v 8 E E u 3 E Mm. 8E Wu SE HIVSE Em w 8 E 3813 e3: uuucsou H/S+— U o m u k a 003 >—‘ 1.13 'lNHD 1.51 >—— an owvu (— DUI ome— isanbau 2mm {— P901 31904—0 7 SILLVLS l>—-— NnauaAo “—— ANOD .ums *“" lSEIlANOD <-—-—- JEQIDH :90 31904-0 II‘ABG aovgiaiul textured 41 uflzuafio 2030 on» me 52mm? 200.3 5325.2 [Ira E J 1]. .III 95 . name: j :50 c0332?— mvce 00 a} .mocv cu e\_ >m+ £8 :5 E . ouusanuuca we: 0: E: Q: aortas: .. avov 00 a)“ :ov 00 8:: 1... f a L 2:20 ‘lllun hmmmm 25.35 A" 3. 2%: hmofiu #2 3. 033352 0mm Aneumv 2.20". cam >m+ :zH >m+ “unnumv 2.20"— 42 to enable the RAM of the utility logic and to drive an LED circuit on the front panel to inform the user that the system is in the RUN mode. 4.2.2 Microcontroller Design Considerations 4.2.2.1 Basic Microinstruction Cycle ' Figure 4.5 illustrates a typical microinstruction Cycle with the transitions in the ROM circuit. The data on the ROM output is not stable during tpl, therefore tp2 is used to generate most of the com- mands by simply AND-ing this pulse with dedicated output lines of the ROM. Combined with the statuses of LST CHNL BIT and EOD, these commands control most of the state transitions of the control logic. tp and TP 1 are only used for minor state transitions. 4.2.2.2 Time Allocation for the Main Tasks The diagram given in Figure 2.5 serves as a starting point in allocating fixed time intervals for the sampling, settling, conversion and data transfer tasks; To aChieve at least a 10 kHz/channel sampling rate for eight channels, one must try to solve the equation: A + 83 + D = 100 vs, (1) where A = allowed sampling time in us; B = allowed conVersion period for one channel in us; 100 us==samp1ing period corresponding to 10 kHz; D = optional delay in us which Should be kept small when solving this eqUation. ' Equation (1) has three Unknowns. A and B are two degrees of freedom that satisfy the following: 43 | l‘ps I '< >3 tp1 I F'— I th J—L : TP 1 ' j“ ROM Counter Inc 3 1 ROM Counter Reset q - -—- --- ROM Counter Preset ROM address FT 1 A g ROM outputs Figure 4.5 Typical microinstruction cycle 44 A > rated acquisition time Of the sample-and—hold devices B > rated settling time Of the multiplexer + rated analog- toldigital conversion time Moreover, since D, the delay time must be positive, A + 8B :_100 us. Furthermore, for simplicity, it is strongly recommended to take integer numbers for A and B, and D a fortiori, so that all tasks can be performed in an integer number of microinstruction cycles. An Optimal choice for A and B is A = 8 us B 11 us This selection allows enough additional time to perform each task within adequate safety margins. Both rated and allowed time intervals are indicated in Figure 4.6, a more detailed version of Figure 2.5,WhiCh shows the sequence for two channels only. Figure 4.6 also explains how the data acquisition process is initiated. With the values of A and B established previously, any allowable data acquisition sequence can be described by the following more general equation: A+NB+D=T, (2). where I I N = number of channels T = desired sampling period in us D = delay in us that may include a small fixed delay Df and an Optional variable delay Dv stored in the delay register. 4s mafiam:0fiumaoa mafiawp HOHHOHpcooonowz o.v onsmflm < . 2 a m < camp 9 «20¢ m age 0 cemmuo>co u: mam w_AmI u “a m “K G n‘ Ad at Q m o m1.e I'L'l‘ _ HM mam.~ misc mus» quw mus m _Am111 maoccagu ozu you a cannon wcfifiasew . §~ Eagggagr JCI 7 ~‘ uh 2 2 2 2 0229 Ouuxu <20 v03022< beau caumuo>=ou voonH< oequ mewuoom vaso22< oefiu newuflmmscoa vasoHH< LP hmwmm mmhm cunz ———-> START cow fl __J T)— 3 1 __./ tpz -%’wnm3 ”wt- FFZ . D '6 -—> cowvnasr FD "’ C +SV FPS STATUS Clear L—_ MMHERRHET > D FF4 c CYCLE , " _ +5‘L Q 3 REQUEST D Clear Q ——I c awe Clear 2—%"cm>s d} T {>0 2» ..—.-—- M 3.. CMD 6 > OVERRUN J > CMD8 - DC? a» Del-C Load Figure 4.8 Control logic (part one) 51 uemoum pmo~0 ammmm nos» pummv ofiwefi Hopucou m.v OHSMfim 0.005. 20.552 w 0 hmmmz mmkmm+ my umo~0 U 5 9' I A 8.6 nlllllll. 11 a L _ as. _ 0C >m+ H 925. W a as heo~0 .mm020 u 185 0 U 0 o a _ one _ mam. . m3_ng >m+ 000 .2. 2 22:0 Pm.— 52 inverse is used to load the delay counter. Finally a special circuit was necessary to generate a 1.5 us cycle request pulse, as illustrated in Figure 8; Detailed timing diagrams are given in Figure 4.10 and Figure 4.11. For conciseness reasons, identical successive microinstructions have simply been grouped into a single microinstruction. The main state transitions occurring during each cycle are also illustrated. It should be noted that microinstruction x '14' is never entered except at the end of the conversion cycle of the last channel, where it is repeatedly executed until the delay counter decrements to zero. Finally, the complete microcode for the whole sequence is shown in Table 4.2. 4.2.2.4 Diagnostics The circuits of the control logic are tested by means of program— generated clock pulses. These pulses have a lower frequency than the ones delivered by the internal clock circuit. After each elementary transition, the diagnostic program reads in a 16-bit word. This bit- configuration contains the statuses of the most important control lines of the control logic. The resulting sequence, describing the actual fUnctioning of the circuits during the diagnostic tests, is compared to a table that keeps memorized all the steps of the ideal operation (10). Figure 4.3 shows all the lines that are scanned in order to localize any defective device. 4.3 Summary Chapter 3 and Chapter 4 discussed all the circuits, analog and digital, involVed in the data acquisition unit. The next chapter deals with the tests performed on these circuits and the overall system and with the conclusions they suggest. ROM Address (Hexadecimal) 53 TABLE 4.2 MICROCONTROLLER MICROCODE ROM Contents 5 4 m \I O‘ M N H x'OO' x'Ol' x'02 x'03' x'04' x'OS' x'06' x'07' x'08' x'09' x'OA' x'OB' x'OC' x'OD' x'OE' x'OF' x'lO' x'll' x'12' x'13' x'l4' x'lS' x c: c: c: c: c: c: c: c> c: c: C) h‘ c> c> c> c: c: c: c> c: a. a. c: c> c: c> c> c> c> c> c> c: c: c> c> c> c: c: c: c: c: c: c> x h“ c: c: c: c: c: c: c> c: c: c: c> c> c> c><0 <0 <0 <0 <0 <0 x c> _. c: c: c: c> C) c: c: c: c: c: <0 <0 <0 <0 <0 <0 <0 <0 <0 x c> c’ h‘ c> c: c> c: c> c> c> c> c> C) c: c: c> c> c: c: c: c> XOOOHOOOOOOOOOOOOOODOO XOOOOOOHCOOOOOOOOOOOOO N c> c: c> c: c: c> c: c> c> c: c> c> c: hi hi hi hi h! hi #4 hi Sll’ pmmH ecu umooxo .mHoccmso Haw Hem emhmmfiv mcflaflk 0H.v ousmfim fir] JiH .<0.x .mo.x .n~.x .N~.x .-.x .0~.x .00.x ..IFI d. .SO.K cu .<0.x ||_..I IQIL 1:. .20.0" cu .Ho.x .00.x WW emmaama m4u>u 0:2 oz<¢ uomom woman; III! e:— w 020 0 020 m 020 v 020 n 020 >200 Fm Memos N.< ennui 1 .qu u A ~ .-;.1 i 2;": anti. .jfi ‘Lgufid-‘- aware: ’3 67 't board 1 1rcu1 Figure A.3 Logic c 68 \ ’5 h“. Id N canon. ”53.30 ofimoq v.< «Human 69 Figure A.5 Input/output board 70 Ewen 538280 prfimfluéuumofieé o.< 0.33m .4 2. .2. 34.2 .M .. w.m~§,0\< “3-9. m: Wm zgmmaro. wart/gm... LP 71 Ewen “228 3033. 5.4. 0.3mm 33-52 I 5:252 29332353 02. m25m>m m AWE REFERENCES Robert E.-Falco, Coherent MotiOns in the Outer Region Of Turbulent Boundary Layers. The Physics of Fluids, Vol. 20, No. 10, Pt. 11, October 1977. ' ' Robert E.-Fa1co, Combined Simu1taneo 5 Flow Visualization/H0t4Wire ' Anemometrygfor"the Study of Turbulent Flows. A Reprint from Nonsteady Fluid Mechanics, Edited by D.E. Crow and J.A. Miller, 1978. Genevieve Comte-Bellot, Hot—Wire Anemometry, Annual Review of Fluid Mechanics, Vol. 8, 1976; Ecole Centrale de Lyon, 69130 Ecully, France. Anonymous, SSMIO Instruction Manual, Disa Electronics, Franklin Lakes, New Jersey 07417. Anonymous,'Microcomputer ProceSSOrs, Microcomputer Handbook Series, Digital Equipment Corporation, 1978—1979. Anonymous, Memories and Peripherals, Microcomputer Handbook Series, Digital Equipment Corporation, 1978-1979. Anonymous, Datel Engineering Product Handbook, Datel Systems, Inc., 1977-1978. Anonymous, RCA CA 3140, Publication #2M1144, RCA Solid State Products, Somerville, New Jersey, May 1977. Anonymous, Product Guide, Teledyne Philbrick, 1978. Pierre G. Meyer and Jeff Piper, Data Acquisition System User's Manual, Michigan State University, 1980. M’TlTIWQfiJfifllflifllflifltllfilflfll'lilfl”WWIIs 77 4320