\. * Flu-.- .v-v‘--.. i - ’ "k. f LIQFUQRY ' him-Mamet Eta“ ‘ I This is to certify that the dissertation entitled Inverters for Interconnected Random Sources presented by John Michael Miller has been accepted towards fulfillment of the requirements for Ph.D. degreein Elec. Engl". mitt/M Major professor Date /%&'li/f/)/?[P3 MS U i: an Affirmative Action/ Equal Opportunity Institution 0-12771 MSU LIBRARIES n. RETURNING MATERIALS: Place in book drop to remove this checkout from your record. FINES will be charged if book is returned after the date stamped below. INVERTERS FOR INTERCONNECTED RANDOM SOURCES BY John Michael Miller A DISSERTATION Submitted to Michigan State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Department of Electrical Engineering and Systems Science 1983 Copyright by JOHN MICHAEL MILLER 1983 ABSTRACT Inverters For Interconnected Random Sources BY John Michael Miller Techniques of converting the random power available in the wind into utility-compatible electric form are analyzed. A variable speed rotor is capable of extracting more power from a wind resource than a constant speed one. 'To utilize variable—speed generators in a utility-interconnected wind system requires some means of frequency conversion. Both current source and voltage source static frequency changers are investigated and field data obtained on operating units is presented. .An approach which allows control over utility-side reactive power, ease of harmonic filtering, and which provide a continuous (pulsating) current demand on the power source is developed. These three features are shown to be lacking in the performance data obtained from commercial units. A 200 VA cascade converter was built and tested in the laboratory. For the dc voltage link regulator to remain stable with simultaneous random variations on its input and high frequency current pulsations at its output, required the development of a multiple feedback controller. Link John Michael Miller voltage level is used for reactive power control of injected current. Low order harmonics are minimized using a PWM inverter and filter. The necessary high frequency switching was accomplished using bipolar transistors. For Doreen ii ACKNOWLEDGMENTS Special thanks go to my advisor Professor G.L. Park for introducing me to wind energy conversion systems, for his encouragement and guidance. Thanks also to Robert Schlueter, Donald Reinhard, Jes Asmussen, Raoul LePage, Lawrence Giacoletto, John Kreer, and Otto Krauss for their helpful comments and suggestions. I appreciate the laboratory space provided to perform much of the experimental work. Thanks also to Gwen Counseller for doing such a fine job typing this manuscript. iii TABLE OF CONTENTS Page List of Tables , v List of Figures vi Chapter I. INTRODUCTION . . . . . . . . . . . . . . . 1 II. WIND ENERGY CONVERSION: THE VARIABLE SPEED METHOD . . . . . . . . . . . . . . . 6 III. STATIC CONVERTER THEORY . . . . . . . . . 28 IV. POWER ELECTRONIC TECHNIQUES . . . . . . . 49 V. THE CASCADE CONVERTER FOR A VARIABLE SOURCE . . . . . . . . . . . . . . . . . . 101 VI. CONCLUSION . . . . . . . . . . . . . . . . 158 APPENDICES A. ON CONVERTER TERMINOLOGY AND MEASUREMENT RESULTS ON THE CSI INVERTER . . . . . . . 164 B. VSI CONVERTER THEORY AND MEASUREMENT RESULTS . . . . . . . . . . . . . . . . . 189 C. CONTROL CIRCUITS FOR PWM CONVERTER . . . . 202 REFERENCES 0 O O I O O O O O O O O O O O O O O O O 2 3 4 iv LIST OF TABLES Table Page 4.1 Parameter Values for Example 4.1 . . . . . 69 4.2 Transformer Bias Versus PWM Modulation Depth . . . . . . . . . . . . . 84 A.l Conditions for Recorded Data in Figure A09 0 I O O O O O O O O O O O O O O 183 8.1 VSI Converter Circuit Parameter values 0 I O O O O O I O O O 0 O O O O O O 191 Figure 2.1 3.6 3.7 4.6 ‘07 4.8 4.9 List of Figures Two basic converter types . . . . . Generalized switching matrix for a defined input voltage set .. . .. . Generalized switching matrix for a defined input current set . . . . . . Possibility of circulating current . DC to AC current source inverter (CSI) 0 O O O O O I I O O O O O C O 0 CSI converter defined voltages and dependent currents . . . . . . . . . Converter line to line voltage and current 0 O O O O O I O O O I O O I 0 Single phase CSI a) topology and b) waveforms . . . . . . . . . . . . Natural sampling of sinewave with P89 Resulting PWM wave with P89 and K=.7S Functional diagram for natural sampl ing 0 O I O O O O O O O O O O O PWM inverter functional diagram . . . Turn off trajectories of a BJT power transistor 0 O O O O O O O O O O O O GTO Evaluation Circuit . . . . . . . GTO switching waveforms . . . . . . . GTO gate and anode current during turn Off 0 O C O O O O O O O C O O 0 GT0 turn off example . . . . . . . . vi Page 19 29 29 29 35 36 42 42 51 51 52 58 59 64 64 66 70 Figure . Page 4.10 2-Level PWM with passive load a) filtered load current, b) load current spectrum . . . . . . . . . . . . . 75 4.11 Transformer asymmetry due to core bias. . . 79 4.12 Measured magnetizing current with PWM drive, asymmetrical case. Current id is the bridge dc input current .. .. . . 30 4.13 Measured magnetizing current with PWM drive, symmetrical case . . . . . . . . . . 30 4.14 Construction for determination of PWM switChing instants I O O O I O O O O O O O 87 4.15 Phasor diagram for sinusoidal case . . . . 93 4.16 Inverter unfiltered output voltage prm(t) and line voltage V£(t) . . . . . . 93 4.17 Line voltage vgit) and injected current i£(t) . . . . . . . . . . . . . . . 98 5.1 Converter input voltage, current, and power density from Dakota 4kW DC wind generator .... . . . . . . . . . . . .. . 104 5.2 Cascade converter topology . . . . . . . . 106 5.3 Converter inductor current . . . . . . . . 106 5.4 Input regulating converter . . . . . . . . 112 5.5 Converter energy loss components . . . . . 112 5.6 BJT switching waveforms . . . . . . . . . . 115 5.7 Fast recovery diode switching waveforms . . . . . . . . . . . . . . . . . 116 5.8 FRD characteristics defined . . . . . . . . 116 5.9 Converter circuit averaged model . . . . . 119 5.10 Converter response as a function of ' duty ratio . . . . . . . . . . . . . . . . 119 5.11 Regulating range of the converter . . . . . 121 vii Figure _ Page 5.12 Converter operating modes during continuous conduction . . . . . . . . . . . 125 5.13 Converter closed loop configuration . . . . 136 5.14 Regulator audio susceptability with output feedback . . . . . . . . . . . . . . 138 5.15 Multiple feedback regulator controller . . . . . . . . . . . . . . . . 140 5.16 Multiple feedback model . . . . . . . . . . 142 5.17 Duty ratio controller signals . . . . . . . 145 5.18 Audio susceptability of MFB regulator . . . 147 5.19 Line current IQ as a function of a with parameter Vs . . . . . . . . . . . . . 151 5.20 Filter voltage V angle as a function of a wiéh parameter Vs . . . . . . 153 5.21 Phasor diagram for converter voltages and current . . . . . . . .‘. . . . . . . . 153 5.22 Real power P and reactive voltamperes 0 versus a and typical power factor . . . . 155 A41 Single phase synchronous rectification . . . . . . . . . . . . . . . 166 A.2 Description of converter wavetype . . . . . 166 A.3 CSI converter voltage and current time phase relations . . . . . . . . . . . 168 A.4 Voltampere operating locus for phase angle controlled converter . . . . . . . . 172 A.5 Measurement of voltage distortion . . . . . 178 A.6 System configuration for example A.3 . . . 180 A.7 Effect of finite x1 on CSI operation .i. . 181 A08 NOfl‘Ideal CSI converter 0 o o o o o o o o o 182 A.9 Oscillograph of CSI performance . . . . . . 184 viii Figure A. 10 A.11 A.12 B01 8.2 8.3 B.‘ 8.5 EMS C.1 C02 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 Waveforms illustrating non-ideal CSI performance . . . . . . . . . . . . . Plot of equation A.l7 . . . . . . . . Spectrum of id(t) recorded in Figure A.9 . . . . . . . . . . . . . Alternator driven VSI converter . . . Simplified VSI converter . . . . . . Plot of calculated line current for VSI converter 0 O O O O O O O O O O O VSI waveforms at Skw output . . . . . VSI one line diagram during source commutation O O O O O O O O O O O O 0 Spectrum of VSI converter line current I I O O O O O O O I O O O I 0 Functional diagram for natural sampling 0 O I O O O O O 0 O O O O 0 Detail of PLL circuit and functional diagram 0 O O O O O O O O O O O O O O PWM circuit and spectrum of VPWM(t) . PWM switching functions . . . . . . . Commutation margin circuit and waveforms O O O O O O O O O O O O O O PWM driver circuit . . . . . . . . . 3-Level PWM into a resistive load . . 3-Leve1 PWM line connected . . . . . Phase lead circuit . . . . . . . . . Regulator control circuit . . . . . . Duty ratio encoder, resolution 263 ns Duty ratio d(t) step response . . . . ix Page 185 186 187 189 193 196 197 199 200 202 204 207 210 213 214 218 221 223 226 228 230 Figure Page (L13 Limit cycle in d(t) for excessive gain 0 O O O O O O O O O O O O O O O O O O 231 C.14 Error amplifier with compensation . . . . . 232 CHAPTER I INTRODUCTION The need for conservation of conventional fuels has stimulated investigation of alternative electric energy sources. On the scale of the electric power industry some of these sources represent minuscule contributions to capacity while others appear to have the potential of supplying several per cent of capacity. From a functional point of view, alternative energy sources can be considered dispersed storage and generation (DSG) or solar driven. When considering the form of the electrical energy produced by many of these sources the need for power conditioning becomes evident because it is necessary to inject electrical energy into the utility network in controlled AC form. Although the use of power electronic devices is not new to the electric power industry, e.g.: the use of thyristors in high voltage direct current (HVDC) transmission, the integration of inherently direct current sources requires the use of switching semiconductors in increasing numbers. Dispersed storage and generation includes small hydro installations, battery peaking, fuel cells, and supercon- ducting magnetic energy storage (SMES). Even though hydro is not dependent on power electronic switching devices, the f0 desire for more efficient storage and generation may require variable speed pumps. In this case power electronics would be required. As for batteries and SMES of utility capacity there is no choice, both are inherently dc. The DSG class also includes the fuel cell which con- sumes a variety of hydrogen-rich fuels. It is attractive for dispersed generation near large load centers. Again the need to transmit its output over existing power networks requires converting its output to alternating current. The solar category includes most sources that are renewable. These include solar photovoltaic, thermionic and wind. The first two are inherently do in character, the last dependent upon the electrical generator used. This brief introduction illustrates the sources involved. Some are for utility load leveling or fuel—saving only while others serve to augment the capacity of the utility. The topic of this thesis stems from research performed at the Michigan State University wind test site. .Additional data and experience were gained from field tests performed at operating wind generation sites within the state. Unsatisfactory performance of existing wind power condi- tioning devices stimulated this investigation into inverters. Because semiconductor switching devices are bistable, the generation of a sinusoidal waveform relies on their proper switching sequence. The class of non-dissipative static converters produces a sequence of output pulses at a frequency equal to or greater than that of the utility frequency. When switching at the line frequency, the pulse duration and amplitude are chosen to have a fundamental component of some specified character. The fundamental component is separated from this pulse waveform by filtering techniques. By switching at greater than the base frequency this filtering process can be performed more efficiently both in terms of energy and economics. The case where switching is less than some base frequency will not be considered. Power conditioning performed by this class of sampling converters has been extensively researched. The cycloconverter is an example. In the cycloconverter the output frequency is limited to one-third to one-half of the input frequency [448. The trend to higher switching frequency is from converters operating at 60 Hz quasi-square wave to phase- staggered vector summation at 1080 Hz and more, to pulse width modulated converters operating at several kilohertz. The availability and refinement of switching devices con- tinues the upward trend of switching frequency. In Chapter Two a survey of present converter design is given along with the conditioning needed for wind genera- tion. Active waveshaping of current has increased to keep high order harmonics at a minimum on the utility networks to avoid interference and overheating. The multi-converter concept has emerged as one topology capable of meeting this requirement. This research adds to the findings of those working in the photovoltaic conversion area by investigating the cascade topology using a wind turbine as the energy resource. It is shown in Chapter Five that this converter topology produces minimum torque pulsations on the wind generator. Chapter Three and Appendices present background on switching converters and compares ideal and actual con- verter behavior. Actual field measurements confirm this and illustrate the pulsating load inverters can impose upon their source. Chapter Four develops the background for the pulse width modulation technique. Here the concepts of real power flow, reactive voltamperes and distortion voltamperes are defined. This material is essential, even though switching converters operate without magnetic energy storage, because their effect on the utility is similar to an induction generator. The cascade topology represents a viable method of reducing the negative aspects of static converters inter- connected to the utility. By providing a continuous flow of input current, the load presented to any of the inherently dc sources is much easier to characterize. Active current waveshaping reduces the filter requirements and minimizes interference with nearby communication and data processing equipment. This occurs because low psophometric current is produced by higher fidelity current waveforms. Psophometric current is a fictitious current such that if it flows in power conductors, the same level of communication inter- ference results as that actually observed.»~ Magnitude con- trol of an otherwise random source voltage makes it possible to achieve enhanced power factor performance. This is so because the ratio of converter dc port voltage to ac port voltage defines the reactive power requirement. This multi-stage approach is not without disadvantages. The power must be processed twice. Once to achieve regula- tion and input current smoothing and again during inversion to alternating current. The forward converter in the wind turbine application is the analog of the series diodes used in photovoltaic systems to protect the array from power reversal (because of heat dissipation limitations). The conclusions of this research are presented in Chapter Six. Areas open for future research are given. Some practical aspects of interconnected operation are described. These include tolerance to both internal and external faults, capability for soft starting and sequenced disconnect. Utility voltage matching and both frequency and phase matching are required. Finally the inclusion of a 'smart' controller is described. CHAPTER II WIND ENERGY CONVERSION: THE VARIABLE SPEED METHOD 2.1 Why Variable Speeds? The conversion of kinetic energy in wind to electrical power can be accomplished in several ways. When it is desired that converted electrical power meet the frequency and voltage constraints of an electrical distribution net- work for the purpose of offsetting conventional generation, the conversion schemes become limited. .At present, electri- cal power generation from the wind is most economically accomplished by first converting wind energy into mechanical torque. This rotational energy is then converted into elec— trical energy of a form dictated by the character istics of the particular generator used. Thus the conversion of wind energy into electrical form involves at least two separate conversions. First is the conversion to mechanical torque with some energy escaping in the form of heat, turbulence, and sound so that the efficiency is less than 100%. Then conversion of this torque into electrical current is again accompanied by loss mechanisms, mostly heat, so that effi- ciency is again less than 100%. The second conversion stage relies on electrical con- version equipment that has been under development for decades. When horizontal axis wind turbines are used, the advantages of operating the turbine in a variable speed versus a constant speed mode are several [1,2]. In the low wind regimes characteristic of most inland portions of this country, the blade power coefficient Cp, a function of wind speed, can be maximized if the rotor speed is allowed to vary in direct proportion to the wind speed. It is known that propeller-type turbines have a maximum C of .59 only P at one value of 1. This parameter 7. is the ratio of blade tip tangential velocity to the wind stream velocity normal to the blade swept area. It is apparent that since 1. varies with the wind speed, the variation of C is less when P a variable speed rotor is used. A further advantage of variable speed rotors is a smoothing of the electrical power produced because energy in wind gusts can be partly absorbed in accelerating and decelerating the rotor. Also, blade pitch control is not necessary. The disadvantage is that variable speed rotors produce variable frequency electric power unless commutation is used. In [1] tests on both a variable speed alternator (a 3—phase, self excited, field controlled 20 kW unit) and a constant speed induction generator (3-phase, 25 kw unit) both using the same rotor (34'9” diameter) were evaluated. In tests performed on the induction generator, it was found that overall efficiency (including blade CP of about .30) was low in the 11 to 13 MPH wind speed range but improved substantially above that. For the alternator tests it was found that having the generator operate into a battery bank as a means of local energy storage exhibited the lowest overall efficiency. The battery acts to clamp the alter- nator output voltage which, in turn, reduces the rotor rpm range and thus Cp. This technique has the further disadvan- tage that at higher power levels battery overcharging be- comes a problem. Because the battery charge-discharge effi- ciency is low (60%-75%), system efficiency suffers. Reducing the overcharge condition and the attendant gassing may require the incorporation of a charge regulator on the battery bank or some means of battery switching. Operation of the alternator with the battery replaced with a large capacitor for energy storage exhibited greater net effi- ciency; The reason is that Cp is larger due to a wider-rpm range of the rotor. The inverter (synchronous, line commu- tated) input voltage range was greater. A disadvantage of variable speed operation with direct current output is the inclusion of an inverter for operation into the utility network. This represents a third power conversion stage wherein the character istics of the electrical power are modified. 'The term static frequency changer best defines the function of this third conversion process. 2.2 Electromechanical Converters “In [3] the authors present similar arguments in favor of the variable speed technique. Also presented is a clas- sification of present static frequency changers. These techniques will be discussed later. First look at methods allowing the generator to operate directly into the utility. These schemes belong to the class of rotating converters. This class can be partitioned into two subgroups, those having a rotating air gap flux in synchronism with the utility, and those in which the armature slips relative to the rotating air gap flux. The first group contains all synchronous devices in which the torque-producing magnetomotive force tmmf) is stationary with respect to either the stator or rotor. Rotor here refers to the moving portion or armature of the converter which is coupled to the rotor of the wind turbine. The remaining member then has mmf moving with respect to its reference frame whereby electrical energy flows out from its windings in proportion to the input mechanical torque (or vice-versa). Machines in this group are d-c generators, synchronous generators, and alternators--both inductor and permanent magnet types. The second group contains machines in which the mmf has relative motion to both rotor and stator--hence the term slip. In this case electrical energy is supplied to or from both members. Machines belonging to this group are induction and doubly-fed induction machines. The induction type includes the common caged rotor machine, ac- commutator, and multiple rotor devices. The last category of this group is the wound rotor induction generator. A 10 Tm, the rotor angular velocity (u; is less than we so that slip is positive. The electrical input power includes the slip power dissipated in the rotor. ‘When delivering aero- dynamic power to the rotor with 8 negative, the slip power will be dissipated as heat in the generator mode. ‘By pro- viding local VAR support this induction generator will de- liver electrical power to the utility in response to the wind turbine torque input. Because mechanical torque (Tm) is proportional to wind speed (WS) squared and WS is a random process, then Tm is random. More will be said on this later. If the induction machine is of the wound rotor type, this slip energy can be recovered. In [3] a matrix of options between the four basic motor types is given and four basic converter types suited to variable speed operation are noted. The first of these slip energy recovery schemes is from the adjustable speed ac drive field and is the semiconductor implementation of the original 'Kramer' drive. In this scheme (also called the subsynchronous static converter cascade), only slip power is converted so that the converter rating is only a fraction of the machine KVA rating. Its topology is that of a rectifier (uncontrolled), d-c link, and line-commutated inverter interconnected to the utility. By varying the inverter firing angle, the loading on the wound rotor of the double output induction generator can be varied (amounts to controlling the rotor resistance) so that power output is controllable. The power factor of this ll scheme is poor because lagging VARS are needed by both the machine stator and inverter. The second technique also derives from the ac drives field. In this method the uncontrolled rectifier of the Kramer scheme is replaced with a fully controlled converter (cycloconverter). This is the static Scherbius system in which slip power flow is bi-directional. This has the advantage that operation is over both positive and negative values of slip (typically 250% of cos). Again, converter rating is less than the machine rating and is typically 50%. 2.3 Interconnection Considerations It was stated above that wind turbines produce a very random output. Injection of such unpredictable power into a utility presents problems not encountered in the past. These include concerns of system stability, adequate levels of spinning reserve, and unloadable generation. Suppose an array of wind turbines (wind farm) having a total rating that is a significant fraction of system capacity is sub- jected to a large wind speed variation. This would be the case for example during a storm frontal passage. In [4] the authors consider various levels of wind turbine penetration on a utility and how the cycling of conventional generation (steam turbines) can be controlled. One technique calls for coordinated blade pitch control to reduce wind power varia- tions over some interval (1 to 10 minutes). From this a methodology is developed for setting system spinning 12 reserve, and unloadable generation so that load following is not impaired. This is a very serious problem since wind speed during a storm passage may increase at a rate exceeding that of unloadable generation. By simplifying matters greatly this can be viewed as the case of many small time constant generators and a few large time constant generators supplying energy to a common load. What are the limits of stability of such an arrangement? This is typical of the questions arising when variable output alternate energy sources are interconnected with a utility. Characterization of the wind has been done previously. In [5] it is shown that the two parameter Wiebull distribu- tion gives a good fit to short-term wind velocity prob- ability density. In addition to short-term behavior are the cyclic diurnal, seasonal, and annual trends. To adequately define these requires a long-term measurement pro~gram. Stochastic modelling of the wind resource is then of great concern to the system planner in assessing reliability of his system with wind generation. Further assessment of wind turbines of both constant speed and variable speed are given in [6,7,8,9]. The impor- tant effects on performance are several. Although there is no fuel cost, a large capital investment is needed per kW (this is partly due to the need to get the wind turbine rotor area off the ground to heights where the wind is). Below about 300m altitude, wind speed usually obeys a power law increasing with height. Towers are expensive, espe- l3 cially those sturdy enough to support a bulky rotor and gen- erator. The generator output cannot be scheduled and, fur- ther, the power changes are fast.‘ This is illustrated with field data records in [8]. Other than safety issues, the main interconnection concerns are of harmonics, VAR require- ments, and power factor. The term power quality encompasses these concerns. Measurements have been performed on distribution systems [10,11,121 to assess the power quality issue. In [10] the digital simulations of two distribution systems are compared with measurements to determine harmonic content and suggest methods to minimize harmonics. Large installations which generate substantial harmonic currents are power supplies for transit systems, dispersed storage and genera- tion, motor speed controllers, and arc furnaces. The har- monics so generated are specified by frequency, magnitude, and phase angle. The sources can be either voltage or current depending upon commutation technique. That is, a line-commutatedi(commutation VARS supplied by the utility) inverter is a source of current harmonics. Similarly a force-commutated inverter is represented as a source of harmonic voltages behind an impedance. The arc furnace is modeled as a source of harmonic currents. The most preva- lent being the third, fifth, seventh, and ninthf The fifth harmonic rises to 20% of the fundamental current during the melt down phase. It was further shown that the typical distribution system resonance (of low Q) is near the seventh l4 harmonic. An important finding was that the size and loca- tion of capacitor banks had a marked effect on harmonic voltage amplitude. Feeder location between the harmonic source and the capacitor bank appears to be the most sensi— tive arrangement. The main impact of the capacitor bank is a downward shift in system resonance. The KVAR and voltage rating of capacitor banks thus installed are critical since they are shunt paths for harmonic currents, Ihshw V where h is the harmonic number. Filter VA rating must account for system harmonics. One notable addition to the list of distribution system harmonic sources is the static var compensator (SVC). This is a utility size (MVA rated) phase controlled reactor. The SVC includes switched capacitor bank, reactor, and trap filters (series tuned) to hold harmonics below 5%. In oper- ation the phase control of this reactor allows system vol- tage control by sinking or sourcing vars as needed to hold system voltage near nominal. It is also used near arc furnaces (25 to 150 MVA) and rolling mills for var support and minimization of voltage flicker. In EHV systems it provides line compensation. ‘With frequency control the SVC provides damping of power oscillations. 2.4 Effect of Harmonics ‘What are the effects of these harmonics? This question can be answered in two parts. First, the effect on equip- ment and second, on control metering, and protection. In 15 the first case, high harmonic voltages and currents can cause failures of equipment, and produce high losses. Susceptible utility equipment includes capacitor banks as mentioned above, transformers, and switchgear. The most pronounced effect is overheating. In [13] the effect of system voltage harmonics on induction motors is investi- gated. It is found that for total harmonic distortion of the voltage wave (THDV) less than 5%, the increased Joule heating and subsequent temperature rise remains within specified limits. However, since voltage harmonics give rise to large current harmonics it is not known at what THDV level the life of induction motors will be significantly reduced. Considering transformers [14,15], investigation indi- cates that the most severe performance degradation results from operation on an asymmetrical B-H curve. 'When harmonic order and phase is such that system voltage exceeds rated voltage, substantial odd-order harmonic currents are gen- erated. Both system overvoltage and core asymmetry yield harmonic currents. .Although the pulse burst modulation (PBM) technique described in [15] contains only low-order harmonics, radiated interference is negligible as is tele- phone interference. However, the production of even- order harmonic currents is detrimental to not only transformers but induction watthour meters (11]. Also, the current harmonics produced at different loca- tions on the same network can reinforce each other in cer- l6 tain circumstances. In [16] this was shown to be the case for electric vehicle battery chargers. In three phase systems, the phases cannot be perfectly balanced so that even though the delta-connected transformer blocks triplen harmonics, the degree of imbalance determines how much posi- tive and negative sequence third harmonics are passed. Of significance is the presence of a negative sequence fifth harmonic. As for control and metering, the problems are similar: interference with carrier current systems, and ripple con- trol systems must be minimized. It has been found that at 20% fifth harmonic, an electronic watt transducer was more than 10% in error. The problem with telephone interference is now more severe due to use of phone lines as a data transmission medium. In fact, the line current flowing in a distribution system is greater than that current required to deliver the real power of the connected loads. This extra current can be broken into two components. The first is a reactive component due to phase displacement and is at fundamental frequency. The second component, called the psophometric current, represents the distortion components, i.e., the harmonics. It is the psophometric component which interfers with communication and data channels. In [29] the telephone influence factor TIF and weighting function are explained. Psophometric current is defined as that single fre- quency current which would cause the same interference on a l7 neighboring telephone circuit as does the actual harmonic containing line current. 2.5 Classification of Converters The above discussion gives several examples of why the power quality issue is so important--especially when large switching converters are tied to the utility. What are some of the converter circuits now in use and how is the har— monics problem corrected? First, all static converters can be grouped into two broad categories. The terms line- commutated and force-commutated refer to how the d-c port source current is transferred from one path in the inverter to an alternate path such that a reversal of current direc— tion is achieved at the a—c port. The line-commutated (also source or natural) inverter can function only in a utility interconnected configuration. This is necessary with thyristor switching elements because the device can only turn off if its forward current is reduced to zero and held there for a short time. So, the utility must supply the volt-amperes to achieve this by producing an abrupt poten- tial reversal across the thyristor. As a consequence the power factor as seen by the utility is always lagging. In the very early days of power conditioning, the converter harmonic behavior at both its d-c and a-c ports was found to be integrally related to the number of commutations per period of the base ac wave. It was observed that only even harmonics were present at the d-c port. IDepending upon 18 whether the converter input defined quantity is current or voltage determines which types of harmonics (dependent quan— tities) current or voltage are present. A current source inverter has current as the defined input and voltage har- monics are the dependent quantity at the d-c port. The converse holds for the voltage source inverter (Figure 2.1a and b). The number of cycles of ripple in the d-c port depen- dent quantity per base ac wave period was termed the pulse number p. Thus, if h is the harmonic order and n any integer, the d-c port harmonics are given as hanp. At the a-c port only odd harmonics were found to be present with order given as hsnptl. In his book, Direct Current Trans- mission, Vbl. l. ELW. Kimbark gives an excellent discussion on the positive and negative sequence characteristics of these a-c port harmonics. Force-commutated (also self or impulse) inverters can operate in a stand alone mode. As such they find applica- tion for powering static loads, e.g., an uninterrup tible power source (UPS). In this topology, the switching devices are capable of commutating the current independently of any utility interconnection. When thyristors are used as the main switching elements, auxiliary thyristors and passive commutating components are used to provide the commutation energy locally. The main advantage of this converter type is its control over power factor. Further examples of present converter topologies are to be found in [17,18]. 19 L + m Vol tage S; ; Source Il Z a) Current Source Inverter CSI. REACTORS 9T1 d+4 Voltage .4 Source [— b) Voltage Source Inverter VSI. Figure 2.1. Two basic converter types 20 Also presented are techniques of harmonic cancellation or neutralization and filtering. Harmonic cancellation in use at the present is best illustrated by the vector addition method (stepped wave). In this approach multiple-phase-shifted (parallel connected on the d—c port; series connected at the a-c port) converter bridges using specialized magnetics sum the phase-shifted components of the output. The harmonic cancellation takes place in a specially-designed transformer which supports only the voltage harmonics. .As was the case in capacitor bank, VA rating also applies here and the harmonic neutrali- zation transformer rating is 40% of the total converter VA rating. The final vector summation is accomplished at the main utility interface or service transformer bank via wye- delta low side windings. Many variations are possible by paralleling more converters at appropriate phase angles in conjunction with more wye-delta transformer sets. 'Two sig- nificant drawbacks are attributed to this configuration. First, this series connection of transformers at the high side is not prudent at distribution and transmission vol- tages. Second, the VA rating penalty is high. So far the discussion has centered on low frequency converters. The pulse numbers encountered in these methods are the paralleling of 6-pulse units for 12-pulse operation and tripling for lB-pulse. One theme keeps running through this--large magnetics and capacitors are needed. The mag- netics are for both harmonic neutralization and in trans- 21 formers for voltage matching and isolation. Capacitors are used along with magnetics for compensation of power factor and in series tuned shunt filters to divert uncan celled harmonics from the utility. In recent years the trend is to higher speed switching devices and circuits which exploit them. This is possible because semiconductor devices are more economical than capacitors and magnetics. 2.6 The Trend to Higher Operating Frequency Present research in power semiconductors is centered around improving ratings and switching characteristics-- especially voltage withstand capability and switching times [19]. The power MOSFET is rapidly finding application in low-power lightweight converters. .However, operation at high voltage is penalized by large on-state dissipation. Power bipolar transistors are taking over increasing propor- tions of the thyristor domain and gate-turn-off thyristors (GTO) are being improved in their turn-off capability. Pre— sent devices require a gate current pulse of a tenth to one fifth of the rated anode current. Their advantage lies in the fact that gate energy for turn off is much less than anode energy needed in classic auxiliary commutating methods. Recent power semiconductor devices are the static induction transistors--essentially a vertical junction PST. In power converter applications, a drawback arises from the normally ON characteristics of this device. Another recent development is the field controlled thyristor (FCT). This 22 PCT is a minority carrier device in which on-state resis- tance is very low. However, it is also a normally ON device. The pulse width modulated (PWM) technique discussed in this thesis is one method whereby the high switching speed of power semiconductors can be used to achieve dc to ac conversion. The technique is based on principles of modula- tion theory to realize the translation of available power at zero frequency (dc) to some higher frequency (60 Hz). By using this method, the problems of harmonic filtering are reduced because the harmonics are now spaced about multiples of the carrier frequency. When bipolar power transistors are used, this frequency may now be several to perhaps twenty kilohertz. GTO's can achieve still higher powers (because of higher withstand voltage) up to two kilohertz and as high as six kilohertz at lower powers. This PWM technique has been used in the photovoltaic area [20]. Here a single phase bridge topology was designed to interface between a 160V to 240V dc photo-voltaic (PV) array and a 240 Vrms utility at 6 EVA. The power output from PV arrays is predictable in areas with few cloudy days per year [81. Inverter control in the PV appli cation is accomplished using ripple phase sensing to track the array peak power point. Tests on this particular PWM inverter, with a 19 mH series waveshaping filter to the utility, resulted in current harmonics that were less than 5%. A similar PWM inverter is described in [21] using power 23 bipolar transistors for a residential 8 kW rated_PV inverter and a commercial 200 kW rated thyristor inverter. In recent years a further refinement to the PWM tech- nique has been explored. This is the concept of active waveshaping. As explained above, a passive filter is used to provide waveshaping. Reference [22] proposes that one method of achieving current waveshaping for an intercon- nected converter is by use of time-varying gains. In this approach, the dc input current to a parallel inverter (thyristor implementation called a parallel-capacitor- commutated inverter whose operation is described in [41]) is shaped into a half sinusoid. With such half sinusoids of current present in the link inductance, the current zero crossings must coincide exactly with that of the ac voltage wave. Thus a very strict requirement of unity power factor operation is imposed. Actual power distribution systems are inductive so that achieving exact current zero-voltage zero coincidence will be difficult. The control of the link inductor current is accomplished using a buck converter with time varying feedback gains. These gains not only vary at the 60 Hz line frequency rate but their magnitude is a function of the injected current level. This converter was built and tested on a simulator. Control problems encountered were due to an open loop pole at the origin and a right hand plane zero in both the induc- tor current and filter capacitor voltage state equations. The action of time varying gains causes the closed loop 24 poles to move so that system response is time varying and load dependent. Because of this amplitude modulation of the input current, the d-c source will be subjected to a high second harmonic. This itself may present interface problems depending upon the source used. A further refinement of this technique is to use a high- frequency link. A photovoltaic application of this is given in [23]. The scheme developed is a three-stage conversion process. In the first stage, high power bipolar transistors follow a PWM switching function at 10 to 20 KHz. The output of this PWM single-phase bridge is coupled through a high- frequency ferrite-core transformer to a rectifier bridge using fast recovery diodes. The PWM shaped current at the bridge output again is used to feed a d-c link inductor. The inductor further filters the current into half sinusoids. The final stage is a conventional thyristor bridge connected directly to the utility. The PWM stage is controlled such that the shaped current has a natural zero just prior to the voltage wave zero crossing. In this manner thyristor commutation is built in (classified as line-commutated, although the current is artificially quenched). This conceptual design was tested using a computer simulation. Because the current is shaped to a half-sinusoid at the PV array interface, a large input capacitor is needed to source the 10 to 20 KHz current pulses. The array current is again pulsating at 120 Hz. 25 2.7 The Multistage Concept Most recently a further refinement to this concept has been proposed and built [24]. In this paper, the authors describe a photovoltaic dc-ac inversion process using the multiple converter topology. Their approach is to use a double forward converter (parallel buck/boost) realized using power MOSFET transistors. 'This stage has its duty ratio modulated in response to a half-sinusoid current or voltage reference signal. By phase locking to either the utility or an internal clock, either interconnected (current reference) or stand-alone (voltage reference) operation is possible. The system operation is similar to the previous references when current programmed. ‘When voltage programmed it has many aspects presented in this thesis. As the above sequence of papers illustrates, the conver- sion of power from renewable energy sources requires the multi-stage converter concept. The research results pre- sented here commenced at the time (1981) reference [22] was being presented. During the intervening time research of this multistage concept using wind turbine output as its power source has not been published. For the case of wind energy, the source is not as pre- dictable as from a PV array. Thus, the strategy to shape current would be considerably different because, with wind energy, the generator current is a random process. By taking into account other constraints of highly variable power throughput, the need to manage reactive power flow, 26 and to minimize pulse loading of the energy resource, a different topology was needed. The topology chosen is that of an input switching regulator (boost converter) with con- tinuous input current and constant output voltage. There- fore, a dc voltage link is used in place of the aforemen- tioned current link. It is now the line-interfaced stage that is switched at a high frequency rate (PWM) to achieve inversion to ac. Filtering is then used for current wave- shaping at the utility interface. By controlling the inverter phase lead angle, power throughput can be varied. Then by a judicious setting of the regulated voltage, a minimum var flow can be realized. This topology meets the three requirements on power, vars, and waveform set forth previously. What remains is the control of this cascade configura- tion. In [25] a description of two different means of generating PWM switching functions are presented using a microprocessor. One technique is to continuously solve an algorithm for each switching angle given a voltage magnitude of the fundamental desired. The second technique is to pre- compute all the necessary angles and store them (only those for a quarter wave due to symmetry) in a look up table. This second technique is the programmed waveform technique and operates in real time. Either technique is capable of nearly eliminating harmonics up to any desired order [31,32,33,341. 27 The boost converter topology operates as a regulator of the random source input. Its function permits the input d-c voltage to vary through a wide range while stablizing the output voltage at a set level. When a load is connected at this regulator output which has large excursions in its current demand, iua, the PWM inverter, it is found that conventional output feedback fails to stabilize the regula- tor. Others [26,27,281 have investigated similar behavior in switching converters of the buck-boost type. In the technique of current-injected control, the output current is sensed and fed back. This technique has a serious disadvan- tage in that the converter becomes unstable for duty ratio D greater than 50%. After experimental investigation of various control laws, a unique control strategy emerged which is very robust as a stabilizer. Chapter 5 describes its analysis in detail. Essentially the method consists of sensing the regulator input current and processing out all high frequency components due to switching. This function is then summed with the converter high frequency ramp function and compared with a processed sample of the output voltage. The duty ratio obtained is a function of both input current and regulated voltage. High dc gains are now possible so that deviations in the regulated voltage can be kept low. Furthermore, the range of duty ratio is limited only by fundamental loss mechanisms-~not by the controller. CHAPTER III STATIC CONVERTER THEORY 3.1 Generalized Converter Theory In Chapter 2 switching converter schemes were classi- fied. This chapter establishes the fundamental principles upon which all bridge-type converters operate. In general an arbitrary number of sources and loads can be intercon- nected via a generalized switching matrix. This is a two dimensional schematic giving all possible ways of connecting M-sources to N—loads. By proper connections at the nodes through switches, the M-sources can generate at the N-loads wave-waveforms of a predetermined character. In his book [37] Wood denotes the input and output port variables as 'defined' and “dependent" quantities. This terminology will be used here because it is descriptive of actual converter behavior. Consider the switching matrix shown in Fig. 3-1. In this figure any of the M-input voltage sources Vs can be connected through an appropriate switch to any of the N- output lines. The M-independent voltage sources are the defined quantities supplying dependent currents Idl'm'IdM' At the output port the N—defined current sources must be supplied by the M-dependent source currents. Naturally, the 28 29 l 7 / I r “9181‘”de r f r" f” , , I I f ——>Isa'vd3 /’ f' ” f’ I I 7 f '_’I 'v ’1 /, r“ ,F' 82 d2 / / , , '—’Is1'va1 V’ /:V ’7 (fi'l TVBM. . . 18H VBJIS IdH d3 d2 d1 Fig. 3-1. Generalized switching matrix for a defined input voltage set. r] ,1 r", ,[ fisz’IdN ‘ ' -—’v I 9 ,1 r! / r, .3 d3 f -—’ V ’I (3' (5' f_ r”? 82 d2 1 —~>v I 7 7 I‘ / l’ l ,1 "° WI 1.1 WI 8 d 1 am s3 82 31 Van Va; vd2 vdl Fig. 3-2. Generalized switching matrix for a defined input current set. k '7”Isk / “7.\ .4 am 31 Fig. 3-3. Possibility of circulating current. 30 V-I characteristics of the load will dictate the dependent voltages vdl""'VdN response to these N-defined currents Isl to IsN' It can be shown that if all quantities are replaced by their exact electrical dual--voltages with cur- rents, parallel with series, single polarity voltage with unidirectional current--a dual network will be constructed. Note that since the fundamental quantities are voltages and currents, there can be no third dimension to the generalized switching matrix. When duality is applied to the network in Fig. 3-1, Fig. 3-2 results. In Fig. 3-2 the M-defined current sources drive the N-defined voltages. In Chapter 4 the necessary switch realizations are given. From circuit theory it is known that in any electrical network, the voltages and currents must conform with Kirch- hoff's voltage and current laws, RVL and RCL. Application of Kirchhoff‘s voltage law KVL, and current law RCL to Figure 3.1 results in the following two constraints: . Along any input (output) line one or more switches must be ON. If this condition is not satisfied, KCL will not be valid at the output (input) port because defined current source requires a return path. . Along any output (input) line at most one switch can be ON. Disregarding this condition results in violation of RVL at the input (output) port. Here terms in brackets apply to the dual circuit Figure 3.2. For example, suppose all the switches are open or OFF. Define an ON switch as a logical l and an OFF switch as a 31 logical 0. With this definition the KVL description of Figure 3.1 becomes: V 3 P l l' r le W Vsl1 de = H V82 ; yd ‘3 H XS (3.1) V V L dN-l i. 4 ii. 8M4 where H is an NXM matrix, yd the le dependent voltage column vector, and 15 the Mxl defined source voltage vector. Similarly the RCL description of Figure 3.1 is: P '1 P W Idi1 l 181. Idz = P 182 3 la 3 '2 is (3.2) I. I. l 9% l i l 8". where P is an MXN matrix, and Id, Is are column vectors. In order to satisfy the above constraints, 2 - HT. Clearly if H - [0] and if the defined current sources are non-zero, then RCL is violated because all of the dependent currents 1d must also be non-zero. Hence H must have at least one 1 in each column. The second condition is similar. Suppose along output line It the switches to both input lines .f and m are closed, Figure 3.3. Because the attributes (magnitude, phase) of these defined voltage sources V81 and vsm are not identical, a circulating current Icr can flow. XVL is indeed violated at the input port in this case. Thus, there 32 can be, at most, one 1 in each row of matrix H in Figure 3.1. The notation of [37] will be used in which 3 represents the matrix of existence functions for the node switches in the generalized switching matrix. Define the switch exis- tence function as a unit amplitude pulse with period Zfrand duty ratio D, (D51). Each existence function in H can be expanded in a Fourier series as 2 w (sin nnD.. = _ 13 _ hij Dij+n nil n ) cos[n(wt wij)] (3.3) when the time axis is symmetrically located on the existence function with 'I’ - o. The existence function for different values of duty ratio D can be approximated using a complete set of discrete Walsh functions. In this case equation 3.3 would consist of the summation of weighted Walsh functions orthogonal over the fundamental period ZNMw. The Fourier representation has been chosen instead because of its utility in developing expressions for harmonic content. Section 343 outlines other valid techniques. In a completely generalized converter, it is possible to generate at the output port defined quantities of arbitrary waveshape and frequency--strictly dependent on the switching pattern defined by B. Thus H can define switching patterns that represent constant frequency of the 33 output quantities or variable frequency as desired. This property is exploited as described in Chapter 2 where either constant frequency operation, necessary in a utility inter- connected mode, or variable frequency, as for instance in variable speed motor drives, are required of the inverter. We can see that H is unique during any switching interval and, for operation from periodic sources with period Ts' an integer number of switching intervals are concatenated into period Ts' Since the switching function matrix 3 defines the circuit topology during any subinterval of Ts' then the resulting currents exhibit the character of each such topology, drive, and loading conditions. When these cur- rents persist from one subinterval on to the next, the circuit is in the continuous conduction mode. Conduction here refers to the presence of a non-zero switch current. On the other hand, when external conditions and circuit dynamics are such that if any of these currents go to zero within a subinterval of T8, the circuit enters a discon- tinuous conduction mode. Example 3.1: To the switching matrix of Figure 3.2, connect a pair of defined dc current sources Isl and 182 with 182 - 'Isl' This gives M=2. For inversion into an ac defined voltage source N-2,3pu. where N82 defines a single phase configuration, and N83 a three phase configuration and so on. Notice that where N-2, the pair of ac defined voltage sources have the same phase and frequency. In this case both may be combined into a single voltage source. The 34 result is then a single phase bridge configuration. Should a neutral connection exist in Figures 3.1 or 3.2, a class of converters termed midpoint converters results. Let N=3 in this example and refer to Figure 3.4. Using the relations given, Figure 3.4a can be redrawn as shown in Figure 3.4b. With the switches numbered as in Figure 3.4b, we first verify the switching matrix constraints. The re- quirement that along any input line at most one switch can be on, means that only one of switches s1, s3, 85 and one of 82, s4, 86 can be on. If two switches are on in either of these triples, it is easy to verify that the corresponding defined voltage sources are shorted resulting in excessive circulating current. The remaining constraint requires that of switch pairs (sl,s4), (83,86), (85,82) one switch must be on in two of these pairs. To have none on clearly violates KCL at the input port. Furthermore, the case where both switches in a pair are allowed to be on without violating circuit theory will be inadmissable based on the desire to achieve power transfer from the dc to the ac sources. Thus, to simul- taneously satisfy the two network constraints and the one constraint on power transport thinngh the switching matrix reduces the choice of admissable switch pairs to s1 and 32 or 86, 83 and s2 or 84, 85 and s4 or 86. A useful mnemonic aid for switching sequence labeling is to repeat output lines a and b as shown in Figure 3.4b and label the switch 35 W\ \x ,4» 0‘ A 0 39 fim \N v p” C? b) Let v81 . Va, V82 3 V6, V83 3 VC Figure 3.4. DC to AC Current Source Inverter (CSI) 36 .' ‘ .. ,' °' . .' ,' '. I ". .' 0. TL. ? :3. f. .‘- . .f. . a. '7' + .‘g‘ ’7’ .4fiq‘ #3 a) t .‘o.. '0. o '. a. ' ’ ' .' '. .0 ' . i . '0. z W ‘a I W an bn on T1 T2 T3 T4 T5 T6 1 l 3 3 5 5 1 l 3 6 2 2 4 4 6 6 2 2 .11 b) n-l _L nTB _____‘,,‘,‘_n-+1Ts P. --.I.s: ..... , _ % 1 L" wé o 1%; 2r 20’ i b 181 ____ ___. 3-4>60t c) 1c v...‘ Is 0 —' r-fi ———-— .9 wt Figure 3.5. CSI converter defined voltages and dependent ' currents. 37 operations in sequence along the diagonals a-c, b-a, c-b, in an upper left to lower right fashion. Referring to Figure 3.5 the circuit operation is as follows. Let the switch closings occur when the correspon- ding pole voltage phase is 47 radians. In figure 3.4b a pole is defined as the switch pair across the input port 1- 2, e.g., (81, s4), (s3, s6), and (s5, 82). By delaying the switch closings fl’radians the converter will operate at full inversion so that power is transferred from Is to each of the three defined voltage sources yabc. The negative of these pole voltages are shown dotted in Figure 3.5a. The solid curves define the dependent voltage V1_2 at the input port (note that the lower envelope is folded onto the top envelope to yield 6 pulse ripple at the dc port). In Figure 3.5b the switch pairs are given during each of the six subintervals of switching period nTs. By assigning a logic 1 to each location where a given switch is on yields the existence function matrix for each subinterval. Application of equation 3.2 yields: F 1a l '1 o ' 1] IIS 1,, - o o -1 : Id - HTIS : t€Tl (3.4) L 101 L0 1J l ‘ V ' 1a 0 0 1 I8 ; teT2 1b - 1 o -1 L 1c} _0 1y 38 where matrix HT is different from one subinterval to the next in that two rows are exchanged. Figure 3.5c shows the resulting phase currents for the a and b phase. In this example current flows in 120 degree blocks so that the duty ratio D - 1/3 . Substituting this value into equa- tion 3.3, then writing the expression for phase current i a of Figure 3.5c results in ia(t) = (%+% sin % cos[wt-%])IS-(%+% sin % cos[wt-n])x (3.5) 1 1 . n lln ” Is+(6+? Sin 6 cos[wt —E—-)Is+ni3ln cos nwt where the summation indexed by n defines the current harmonics. No even harmonics are present due to waveform odd symmetry. Combining terms in equation 3.5 .5} 2n oo 1a(t) = 5 cos wt + Z I cos nwt n=3 9 (3.6) similarily for the phase b and c currents. . _ 3V3 2n m Zn (3.7) 1b(t) — 757 Is cos (at-1r)+ :3 In cos[n(wt-1r)] . 3J5 2n ” 2n 1 (t) = I cos wt+—— + Z I cos[n(wt+ )] c _ 211 s ( 3 ) n=3 n 3 The defined voltage sources are assumed to have no harmonic components, i.e., 39 Van”) -= vm cos wt you“) - vm cos (wt-2’93) (3.8) 2h‘ «penit1 - Vm cos (wt+ /3) The power delivered to these defined sources can be computed as the product of equations 3.6 and 3:7 with 3.8. To emphasize the delivery of real power, the higher order current terms are neglected. Since switch sl is closed when LEn(t’ is at’w radians the power delivered to this source is: 3/3 pa(t) = van(t)ia(t) = VmIs 75: cos wt cos(wt—n) (3.9) 3/3 3/5 = -VmIs fi— —VmIs F COS Zwt and for the b and c phases the result is the same as equa- tion 3.9 with the addition of the respective phase angle. The total three phase fundamental power is then 3pa(t). The double frequency terms vanish in the total power expression so that power is constant. (3.10) _ 9V3 p(t) - -vas 7F? Equation 3.9 shows that the instantaneous power delivered by the defined source Ua(t) is negative. Therefore, Da(t) absorbs power. This same result applies to the complete voltage source set. If the current harmonic terms had been retained, the expression 3.10 would contain a summation term of voltage and current cross products. These higher order 40 terms will contain no real power and represent distortion voltamperes. This example is for the specific case of the switch closings delayed by¢x.-T’radians from the corres- ponding voltage wave zero crossing. Figure 3.6 illustrates the ac line current and voltage. The following defining relations are used: vab(t) = van(t)-vbn(t) iab(t) = ia(t)-ib(t) (3.11) This example serves to demonstrate how sequential switching achieves inversion from a defined dc source into a defined ac source. The dependent current at the ac port approximates a sinusoid (fundamental component of the stepped wave line current). The extent to which the step approximation deviates from a sinusoid determines the harmonic content. From Figure 3.5a the presence of ripple components on the dc port dependent voltage means that the input power contains harmonics. INo energy storage occurs within the switching matrix. Therefore harmonics must be present in the ac port power. Minimizing harmonic content of converters is necessary. A notable technique is vector summation in which the step size of the current waveform shown in Figure 3.6 is reduced. In general l-converters of the type described in example 3.1 may be combined. If the switching patterns applied to each converter are delayed by 20%;.p, the number of such current steps will be increased to 1Qp where p is the base converter 41 pulse number. {For example, if,i- 2 a twelve pulse converter results in which the second converter switching functions are identical with the first but delayed by‘W76. This technique requires replication of converters and many switches are needed. Twelve pulse converters represent the economical and practical limit at very high power [44,45]. This is due to the limitations of realizable switch elements. Chapter 4 will introduce devices currently available for this application. The effect of switching function timing in relation to the defined so quantity is needed. In the specific example treated here, the phase delay angle at was Wradians. Referring once more to Figure 3.5a, if at is less than 9’, the solid envelope will shift left along the dotted curves and discontinuties will appear in the envelope wave. As at is delayed to ”72, these discontinuties will have maximum amplitude and, further, will be symmetrical with the wt- axis. Consequently, since dc source power is the product of Is (constant) and this voltage envelope, the result averages to zero. The dc side and ac side harmonics are maximum. As «xis delayed into the range ”72 to 0 the effect is the mirror of that just described. 3.2. Assessment of Present Single Phase Conversion Methods - The conversion of dc to ac can be achieved using either of the switching matrices of Figures 3.1 or 3.2. The converter of Figure 3.1 is a voltage source inverter VSI and 42 i 21 ab ' a P I M l A vab )t N“ I, 8 “\ I7 \ \ ,' ‘\ \ —: w t I \\ \ ,’ \ st 7 ‘ \‘l""w/ \ O’ll Figure 3.6. Converter line to line voltage and current. 1. ) a) [ ia : I ,”'%hvs(t) '-- l i-3 a F’”“' O." 1 I 1.... I 0-,. ‘ : 5.. L . l 3 l a . I m 2:: b) *-~-—- Figure 3.7. Single phase CSI a) topology and b) waveforms 43 that shown in Figure 3.2 is a current source inverter CSI. When used in the conversion of electricity produced by wind driven generators each scheme has its advantages. In this section both the CSI and VSI converter are analyzed in the ideal case. Appendix A extends this ideal analysis by considering some practical limitations. Measurement results are presented there. The single phase CSI converter is obtained by removing one pole from the circuit of Figure 3.4b. Because genera- tors are voltage sources, an interface element gives the appearance of a current source to the converter. If the value of L is sufficiently large, the current I8 will be continuous. As the value of L approaches infinity the current IB is smooth dc. Figure 3:7 outlines this circuit. If the assumption is made that L is infinite, then over any complete period of the ac voltage, the average volt-seconds accumulated by L must be zero. The utility is represented as an ideal voltage source LQ(t). Its impedance is negligible relative to that of inductance L. The switches labeled 31' 82, 83 and 34 are unidirec- tional current carrying and bidirectional voltage blocking. They are realized in practice using conventional silicon controlled rectifiers (SCR's). With regard to the con- straints imposed in example 3.1, the dependent current ia(t) 18: ia(t) = fills-H118 ; Eel Ts_<_t 1, the PWM wave tends toward a square wave. Some research has centered on this range of K. In the area of variable speed a-c drives, the harmonic degradation for K slightly greater than one is acceptable. This is not the case when current is supplied to the line. The second characteristic of PWM determined by the circuit of Figure 4.3 is the switching to line frequency ratio P. (4.2) In this work P is constrained to integer values greater than 1. A suitable choice for P depends upon the particular choice of switching devices. A high ratio (P) yields mini— mum weight filters, but efficiency will fall because of the large number of commutations per cycle required of the devices. A low value for P gives improved switching effi- ciency but larger investment in the low pass filter. This research investigated P from 5 to 30. One significant finding is that for odd integer ratios, the phase locked loop (PLL) would lock to the line frequency with an odd number of cycles in one half cycle and an even number in the other half cycle. It will be shown later in this chapter that transformer design is very critical for a PWM waveform, especially the tendency to asymmetrical magnetizing current. This is due to the ampere-turn imbalance applied to the 54 transformer caused by both PWM pulse width and pulse number variation between half cycles. The PWM method is also suited to voltage control as equation 4.1 implies. A later development will give an exact relation useful for voltage level control. The effective range is limited where, for low values of K, more of the energy appears at the carrier (switching) frequency we. Finally at K equal zero, all the energy is at we (and multiples thereof). At intermediate K, energy appears at tom, “)c and as sidebands of we. It is significant that no low order harmonics appear until K exceeds 1 in which case 3rd, 5th, and higher odd harmonics appear. For these reasons and because filter requirements are minimal, the modulation depth is restricted to values less than unity. The PWM bridge circuit was tested using both bipolar and thyristor devices. It is a fact that thyristors dominate the power electronic field where high current and voltage devices are required. However, as switching speeds are increased, the time required to commutate~the thyristor consumes a larger fraction of each switching period. Present state-of-the-art thyristor devices, for example the gate-turn-off (GTO) thyristor, are efficient up to a few kHz. Overlapping this range and extending up to approximately 20 kHz, bipolar junction transistors (BJT) meet most requirements. Where converter weight is of primary concern, the minimization of magnetics requires switching speeds in the hundreds of kilohertz. .Above 20 kHz the power MOSFET 55 has emerged as a strong contender with the BJT and at the higher frequencies clearly excels. A frequency ratio of 30 (1.8 kHz) was chosen in this research because GTO devices could be studied at the higher end of their application range. Because of the large dif- ferences in control terminal drive requirements of these three devices, the driver circuits become more complex. 'The bipolar, a minority carrier device, relies on the continuous injection of base charge of magnitude dictated by the col- lector peak current and saturation current gain hFE‘ The GTO is a latching device which exhibits BJT behavior for anode currents less than its latching current level In and remains in its high conduction state for anode current IT greater than Ih' The thyristor enters the regenerative or latching state at the onset of double injection, ine., injection of holes by the p-anode and electrons by the n- cathode. The advantage of the OTC is the ability of the gate to turn the device off. Where a BJT will always return to its off state upon the removal of base current, a thyristor will remain latched on. Appendix B contains an analysis of the effects a latched thyristor can have in a bridge circuit. During this research, one GTO was destroyed by excessive Izt because of a failure in its gate driving stage. In a VSI circuit, a commutation failure is a par- ticularly catastrophic event. The GTO thyristor is a four layer device in a p-n-p-n structure. A useful circuit model is that of a pnp transistor at the anode interconnected with 56 an npn transistor at the cathode. The outer p+ and n+ are generally heavily doped (102°) and the internal p-base region is more heavily doped (1018) than the adjoining n- region (1014) which is also the widest for voltage blocking capability. The cathode-gate junction is of the shorted emitter structure to improve its reapplied dv/dt withstand ability. Essentially this can be modeled as a low value base to emitter shunt resistance on the npn transistor. As the device turns off, the fast-rising anode voltage induces a displacement current via the junction depletion capaci- tance. This current appears at the npn base as turn-on current. The shorted emitter lowers the emitter efficiency sufficiently so that the device can regain its forward blocking ability. In inverter applications and especially in PWM circuits it is necessary to have fast turn off. Therefore, GTO devices need low minority carrier lifetime in the base regions. The highly doped end regions have low lifetime carriers already. Usual methods of base minority carrier lifetime control are the introduction of recombination cen- ters by impurity (gold) diffusion or by high energy particle irradiation (electron and gamma). Present devices rely on the creation of lattice defects by high energy particle radiation which does not produce the high leakage currents that gold doping does. As a result, the pnp current gain hFEl is low (as a result of the wide n-base) whereas the npn current gain hFEZ is current dependent. 57 Many device parameter tradeoffs are required in thyristor design. The major compromise is between forward voltage drop in the ON state VT and turn off time tq. These parameters are reciprocally related and contemporary devices in the l‘kV GTO class exhibit turn on gains of a few hundred and turn off gain of less than ten, typically five or six. These values were confirmed experimentally. The remaining circuitry of the PWM controller and switch driver circuits are explored in Appendix C. Figure 4.4 is a functional diagram of the complete PWM inverter stage. To minimize switching losses, a collector-to-emitter voltage snubber circuit composed of elements R, C, and D in Figure 4.4 is connected in parallel with the main switch. Figure 4.5 is a plot of measured turn off characteristics for a Motorola 2N5633, 150W switching transistor operating Wi.thin its safe operating area (SOA). Since lead inductance is invariably present, the switch operation remains within tire reverse bias safe operating area (RBSOA) by relying on the snubber circuit to act as a collector clamp. The driver cOnnecting switching functions 31 and HZ to the switch elements supplies both forward and reverse drive. Current 131 in Figure 4.4 is defined as the base turn on current and 132 as the base reverse current drive to speed up base Stored charge removal. The use of turn off drive current 332 reduces the turn off time, tOT' in Figure 4.5. That is the time interval from removal of forward drive until col- lector current has fallen to 10% of peak... 58 i1 ’ a.‘ 1 ,34 S2 9“”- xezm ./ ' I I H%aa PWM *0 H2 comm L H MODULE GE D66Ev6 DISCRETE C 01 ECG 152 'r 02 2N5633 or 2N2150 u _‘.A to Sl-S4 BJT SWITCH ELEMENT Figure 4.4. PWM inverter functional diagram. 59 2N5633 BJT l) C = 0, 182 = O, toT = 35118 2) c = o, 1B2 = .15A, t0r= isus 3) _c = .Oiaf, IBZ = .15A, toT = 3.5us 10. ® \ \\\(:) SOA <:> :Esb %-—--- — -/ .1 _$ 1 Figure 4.5. Turn off trajectories of a BJt power transistor 60 The respective values of Ic peak are 2.5, 2.0, and 1.6 ampere and the final VCE sustaining voltage is 25 volts. The density of points reflects the relative amount of the ~total trajectory time spent at different current levels. Operating curve 1 has the longest turn-off time since the only means of base charge removal is recombination whereas in 2 and 3 reverse drive is applied which aids in charge removal. Operating curves 2 and 3 have an order of magni- tude lower turn- off time than 1 for approximately the same level of collector current. The significant difference is that a higher density of measurement points occur on 3 for low values of VCE. This means that dV/dt limiting of VCE(t) during turn off by a snubber network further improves switching performance because the time on trajectory near the SOA limit b is low. Thus the transistor dissipation is lowest for curve 3 in Figure 4.5. A further reduction of transistor dissipation is pos- sible by the incorporation of anti saturation clamping from collector to base of the npn switch. This technique is termed a Baker clamp. Ref. [47] gives further results for turn on and turn off characteristics for various cases of reverse bias and collector clamping. A key result is that transistor energy absorption Esb increases with increased gate reverse bias provided the collector voltage is clamped. The conclusion at this point is that switching applications using bipolar devices use RC networks to minimize the time at high dissipation levels and preferably have some means of 61 keeping the device at saturation while inhibiting operation in deep saturation. The action of the R,C,D network is similar to that of an external current commutation circuit. When the transis- tor collector to emitter voltage begins to rise, the capaci- tor C limits its rate of increase according to the relation IP/CsSJRJVCE). For case 3 of Figure 4.5, this voltage slew rate is limited to 32V£KS until C charges to VCE off. In order that a large dI/dt resulting from a fully charged capacitor discharging into the collector of the npn at turn on not damage the npn, a diode D is added. This reverse biased diode forces C to discharge through resistor R with a time constant of 3.44s (Rs-68 ohm) with a maximum dI/dt of VC“IF/112C or 0.1 A148. The circuit shown in Figure 4r4 was constructed using bipolar switching devices and in this instance the frequency ratio P of the controller was set to 29. The switch existence functions 81 and 82 were programmed to produce 3- level PWM with a modulation depth setting 103.9. The results of this experimentation are given in Appendix C. The next topic involves the study of thyristors in this application. It has already been noted that thyristors are much more rugged than the BJT but what are the switching characteristics like? Unlike the BJT, a GTO thyristor requires a current source turn-on driver and a voltage source turn-off driver. Although a current pulse IGF will turn a GTO on, provided its duration is sufficient to insure 62 the formation of a plasma beneath the cathode contact and hence entry into the regenerative mode, it is good practice to sustain IGF' Then if anode current IT falls below 1h the device will remain conducting. The requirement for voltage sourced turn-off results from the GTO's physical construction. In a conventional thyristor (SCF), application of reverse potential (VAR) creates an electric field within the thyristor that confines the conducting plasma into a high density current filament at the most remote point from the gate structure» The turn off concept is akin to extinguishing an arc by blowing it out. If the path followed by the high density current filament can be lengthened, the filament will extinguish itself. This is accomplished by placing the gate structure at the thyristor pellet center and then diffusing the p+ anode such that the cathode, which surrounds the gate, overlaps the anode. Now when reverse gate potential is applied, the plasma retreats to the outer perimeter of the cathode where the current filament is swept off the anode» .A second device fabrication step is the diffusion of a high resistivity p- into the p-type gate region between the cathode and gate to inhibit gate to cathode avalanche. The p-type gate region remains with higher conductivity to minimize its lateral resistance» The reverse gate current IGR will resemble a diode reverse recovery current. When this current decays away, the reverse bias VAX due to the voltage source turns 63 the device off. This voltage source magnitude must be less than the gate-cathode breakdown potential. To accomplish this, the BJT driver circuits described in Appendix C were modified to provide IGF current sourcing and IGR voltage turn-off. If in Figure Ck8, the collector resistor on 03 is set to zero and its base resistor reduced to insure peak IGR can be switched, then correct voltage sourced turn-off is achieved. A higher level IGF is provided by reducing the collector load resistor of 02 to about one-fourth. The turn on and turn off performance of a GTO was measured using the circuit shown in Figure 4»6 and the results plotted in Figure 4.7. The value for L has been calculated from the turn-off response of Figure 4.7 since the connecting lead inductance was unknown. When IGR in Figure 4:7 was increased to .52A, the anode current IT storage and fall times remained nearly the same but the pulse width of IGR was reduced 86% to 0'71A5° Analysis of the thyristor switching waveforms can be done by considering the phenomena occurring during each time interval. During the turn on delay interval td, the pulse of gate current IGF causes single injection by the n+ cathode emitter to commence. At approximately one micro- second, these cathode-emitted electrons are swept across the gate region depletion layer and injection of holes by the p+ anode has resulted in the onset of double injection. The next interval tr defines the rise time of anode current IT. 64 hl BTVSB-lOOOR 26V 7.8 ohm 7.5uH .047uF 68 ohm L 1L1 T ‘D :fii 1T1 * D RS I ——9 ‘ VT Iiie— l -1qu ° Figure 4.6. GTO evaluation circuit wovw<~a I _ (A§$ IGF-.l4 “k 3, t . [(5 -32-- ”04+ IQ ‘1» I 4T4 IT=3 S———— 2 L ——§\\\\ - t v fi .45 “'2 1b [ a a t €712. Figure 4.7. GTO switching waveforms. 65 During this interval the npn current gain, being a current dependent parameter, has reached the critical point at which regeneration occurs. A conducting plasma of electrons and holes exists beneath the cathode nearest the gate contact and begins to spread with finite velocity across the cathode. The anode to cathode conductivity increases rapidly and anode to cathode voltage VAX drops rapidly to its ON state value VT' By the end of the current rise time the plasma has become more uniform. In Figure 4:7 the 450 ns delay at gate current zero crossing is due to the switching speed limitation of the gate driver. The storage time ts begins when IG starts negative and extends to the point where IT has dropped by 10%. During this storge time, the large pulse of gate current IGF depletes excess p-base charge so that turn off of anode current can begin. During anode current fall time, the internal electric field due to 'VAK forces the conducting plasma into a high density cur- rent filament. The anode to cathode conductivity decreases and the thyristor begins to support forward voltage. The overshoot of VAR is due to lead inductance and the dI/dt of anode current. It is during this fall time tf, that the large dvIdt of VAX is capable of re-gating the thyristor on. The final dynamics in IT and VAX are due to the action of the snubber circuit. Figure'4»8a and b show the turn off transients with and without this RC damping. The data in Figure 4»8 was obtained using pulse techniques with a duty ratio of less than 4%. In a) the reverse gate current pulse 66 .SA, I 6A a) Without RC damping IGF .4A, IGR T 0.5uS/Cm b) With RC damping 0.5uS/cm Figure 4.8. GTO gate and anode current during turn off. 67 width is 2.2‘8 at the 50% points and the storage time is l»6 «s. In b) the pulse width of IGR is reduced to 1.74s and the GTO storage time to 1.44s. As the detail in Figure 4.8b shows, the undershoot of load current is due to capacitor current IC acting as an external current commutation path. Example 4.1: Investigation of the R-C snubber circuit effect on thyristor turn-off. Figure-4»8a shows that the GTO will turn off the anode current IT quickly, and for the parameters given, yields a 275% peak overshoot in anode voltage VAK' Therefore, in order to best utilize the forward blocking capability of this device near its design limit, VDRM' it is essential that any inductive overvoltage be limited. The most direct method of reducing this voltage overstress is with a shunt capacitor. With this capacitance in parallel with the device, the lead inductance and capacitance form an RLC series resonant circuit. A first approximation to its behavior is to assume that when load current IL has dropped to 90% of its ON state value, the thyristor current IT drops to zero» i»e., the capacitor has commutated the current. The fall time tf of IT will be assumed a step change in this analysis. With the parameter values for this example given in Table~4.l, the initial conditions and response iL(t) can be calculated. ~Using the circuit drawn in Figure 4»6 with initial conditions based on the above approximation of iL(0+)-.91T 68 diL(t) , (4.3) _H?__' 0+ = [VS‘R1L(0+) - VAK(O+)]/L = -1.36 A/uS. The Laplace transform IL(s) S[Vs(s) - [vC(0+)](s)1/L + sz[1L(0+)](5) (4.4) INS) = — 2 s + R/L s + l/LC Substituting the Laplace transforms of the voltages and currents in equation 4.4 results in (VS-VT)/L + s(.9 IT) (4.5) 2 IL(S) = s + R/L S + l/LC The inverse Laplace transform of equation 4.5, with damping constant R/2L less than the undamped natural frequency (LO-1’2, e.g., the damping coefficient zeta is 0.265, yields iL(t) = [VS-VT - 0.9 I: R/Z] exp[-%E]sin Q@%" (%%)2 t \lé- - 122/4 lj 2 + 0.9 IT exp[-§It:]cos\/r1t - (2131:) t ; 0 _<_ t < t1 (4.6) Where t1 is defined as the time at which diode D becomes forward biased. For time t greater than t1 the resistor R8 is switched into the circuit raising the damping coefficient 69 Table Parameter Values 4.1 for Example 4.1 40v 2v 6A 6.7 ohm .047 F 7.5 a 14V measured 70 R,C,and D ---- C onljr .-_-'O‘ Figure 4.9. GTO turn off example. 71 to 2.96. This results in a hyperbolic tail to the current as shown in Figure 4»9 and verified by the actual response in Figure 4»8b lower trace. The diode D switches after its stored charge QRR is removed. Suppose this charge is removed by iL(t) given in equation 4W6 flowing through diode D over the interval to to t1 in Figure 4.9. Then, t1 QRR ‘ aIRtrr = Jfio iL(t)dt (4.7) where IR is the peak value of this reverse current and trr is the diode reverse recovery time. For this diode QRRfJ35qC and ttr-.4,.(s so that 1R31.8A. From equation 4.6 the corresponding value of t1 is l.fi&s. For t>t1 diode D is reverse biased so that the current response becomes . [V -v (t ) + I (R+R )/2] (R+R ) 1L(t) = S C 12 R 5 exp [’ 'TVS (t-t1)]X (R+RS) - L 2 C (4.8) L- R+RS7 11 sin T) " It (t‘tl) (R+Rs) R+RS 2 ‘1 ‘ IR exp ' T (t‘ti) C05“ (‘21-) ' It (t’ti) where the new initial condition on capacitor voltage is computed from 72 t 1 1 . Vc(t1) = CI; 1L(t)dt (4.9) 69.17 V. The result of equation 4»9 is substituted into equation 4»8 and the result is plotted in Figure 4.9 for time greater than t1. This example serves to illustrate the fact that lead inductance in the connecting leads inhibits fast turn-off of circuit current. When a snubber of the type discussed is implemented the current fall time can be very rapid during the underdamped phase and highly damped after the diode D in Figure 4»6 recovers its reverse blocking capability. Thus to minimize anode current oscillation in a switching circuit the lead inductances must be minimum. The inverse diode across the switch element shown in Figure 4.4 has no effect on this phenomena in the case of resistive load. ‘When the bridge supplies current to a reactive load, these antiparal- lel diodes conduct for portions of each cycle during which reactive current flows. 'The case of driving a transformer for isolation will be explored in the next section. 4.2. Analysis and Testing of the 2-Level PWM Converter - A PWM converter is classified as 2-level if the waveform switches between two states. The output of the converter in Figure 4.4 will be 2-level‘when switch pairs 73 (81,32) and (53,84) operate with complementary switching functions H1 and HZ, where H2=l-Hl. In this manner the resulting transformer voltage switches between +V8 and -V8. The case of 3-level PWM is obtained when either pair of switches ($1.83) or (s2,s4) have 50% duty ratio and the remaining 2 switches each have switching functions H1 and H2. In this case the transformer voltage switches between +Vs and ground at the PWM rate and then between --V8 and ground. The process is periodic with period given by the 50% duty ratio switches. The experimental results for 3- level PWM are given in Appendix B. The converter configuration of Figure 4.4 is capable of both voltage control and harmonic elimination. The fre- quency ratio P defines the number of pulses per cycle of the fundamental provided the system operates with modulation depth K41. Recent researchers [31,32] have shown that, using PWM, it is possible to eliminate P-harmonics, and achieve voltage control over the fundamental. However, the method requires the apriori calculation of the individual PWM notch width for each desired voltage level. The method is essentially one of conduction angle modulation (CAM) and differs from.the natural sampling PWM considered here in that the latter achieves harmonic elimination with con- tinuously variable voltage control. A prominent application of voltage controlled inverters is in the variable speed a-c drive field where constant flux motor operation necessitates fixed voltage per hertz ratios. This programmed waveform 74 concept has been further studied in [33] wherein eight structurally related PWM wavetypes are compared using dis tortion factor (see Appendix A) as an objective function to assess harmonic distortion for a given fundamental magnitude» Others [34] have addressed the problem of spectral error due to finite commutation time of switching devices. These finite pulse slopes introduce fine structure to the PWM spectra at harmonics of the output frequency, albeit of insignificant amplitude. With this 2-level PWM inverter operating into a fixed load, the measured performance is shown in Figure 4.10. Here the PWM bridge switches current through the primary of an isolation transformer into a filter network consisting of a series inductor and shunt capacitor. This filter is resistively loaded. 'The measured load current and spectrum are shown in Figure 4.10a and b. This configuration led to several experimental findings. First the transformer magnetizing current introdued asymmetry into the current waveform due to distortion of its output voltage. ‘Transformer VA rating was found to have significant impact on the spectra, chiefly in the introduction of low order even and odd harmonics (Figure 4.10b). Next the filter inductor core, besides having the required high frequency properties, attained using ferrite, Inust be gapped. The presence of an ungapped core caused 75 TI AVG 1 M: 1 600.00 , .. j 1 REAL J i ! ~' 3 sumac 1..M—.—..~-.~- fl ,- f r JAN is . .1 I! an SEC amaze m a) Load Current P=30, K=.75, LF=45mH, CF=SuF. L SPEC 1 #A: 1 an 7 3 if i 3 (v) ‘ LGMAG : J ! x ' 4 V‘ J] 7 v“ (\M l n . 3 “Vi V7”) 4 ‘4 -4ILBMU.4._W--,_H___Pw_llq_m___r_.w.~w_,l_rmi 0.8 HZ 6.0888 K b) Current spectrum recorded and processed on hp5423A. Figure 4.10. Z-Level PWM with passive load a) filtered load current, b) load current spectrum. 76 noticeable audio noise levels due to magnetostriction as well as reduced range of load current. This happens because peak load current beyond the saturation ampere-turns negates filtering. A gapped core alleviates both these phenomena. Figure 4.10b illustrates the strong fundamental component of current at 60 Hz, the presence of several low order harmonics, and harmonic clusters about multiples of the switching frequency, fc=60P=1800 Hz. The result so far shows that sinusoidal current is attainable in a stand-alone mode. In addition the harmonics present are amenable to filtering. Next the source of the low order harmonics can be explored. Restricting magnetizing current harmonics imposes strict limits on transformer VA rating. In addition to core thermal limits set by hysteresis, eddy current, and Joule heating, the peak core flux levels for a given material must not be exceeded. The higher efficiency core materials available include ferrite and amorphous metal. However, because of lower permeability of these materials, core volume must be increased. The relation given in equation 4.10 shows the dependence of flux density B on construction and operating conditions. AB = fi x 104 (Tesla) ”'10) In this expressionvaB represents the change in flux density to application of pulse with magnitude V volts and duration‘T seconds. This pulse is applied across a winding of N turns 77 with an effective area A. For the case of a PWM waveform, the voltseconds (VT) applied to the transformer core increase in proportion to the amplitude of the sinusoidal modulating function. Define the saturation flux density of this core material as 3. Then for a given number of primary turns (N) and effective core area (A), the change in core flux density (AB) must remain within the operating flux limits of 1’5. An increase in VT such that AB exceeds either +3 or -'§ will be accompanied by a large increase in primary current ipfit). This results due to core saturation, the attendent drop in magnetizing inductance, and a dramatic increase in core magnetizing force (8). Consider the case where the average voltseconds (V!) impressed upon the core during alternate half cycles are not equal. This is the case illustrated in Figure 4.11 in which primary turns (N) and core area (A) are constants. The flux 8’, Webers, and flux linkagesl, Weber turns, are used as the ordinate axis labels. The core magnetizing characteristic is drawn in C, showing the locus of core hysteresis curve apices versus increasing magnetic field a. .As shown in.a and b, the voltage V i(t)-idt) with an unbalanced volt- pr second product is supported by an offset of the core mag- netizing characteristic. The nonlinearity of the core flux versus current results in an asymmetrical magnetizing cur- rent. Here the d-c bias current Io-lln no results in the presence of even harmonics in the current superimposed on the odd harmonics produced by the odd symmetry of.fl'versus i. 78 With a PWM waveform, the asymmetry in voltseconds is a result of a distorted line voltage signal and any signal processing asymmetry of the control circuits. Recall also the comments on phase locked loop behavior when P is odd. The following experimental results were obtained with P=29 for which V7+>V¢’ as shown in Figure 4.11a. Carry the above analysis further and assume a sinusoidal voltage wave with positive offset V0. Since flux linkage is the integral of voltage across the N-turn primary, then flux linkages can be expressed as A(t) = XO-Al COS wt (4.11) . ' -1 _ -1 T 1pri(t) = g [A(t)] — g [A ¢Ufll where the function g represents the Rayleigh arc in Figure 4.llc. In [15] an empirical equation is found which gives a close approximation to actual magnetizing current. If ip(t) = A Sinh [BA(t)] (4.12) equation 4.11 is substituted into equation 4.12 and expanded using the trigonometric identity Sinh (A-B)-Sinh A Cosh B- Cosh A Sinh B, an expression for ip(t) is obtained. 1p(t) = ASinhBAOCosthlcoswt — ACoshBAOSinhBAlcoswt (4.13) In Figure 4.12 the measured results are shown for a transformer with ungapped core and asymmetrical primary voltage. The constants in equation 4.13 were empirically determined for this case as A=.00046, 810‘.35, and Ell-9.0. 79 ‘I'-"A ’Mt) vpri(t) Transformer asymmetry due to core bias. Figure 4.11. 80 2ms/DIV ip(t) lA/cm idm lA/cm Figure 4.12. Measured magnetizing current with PWM drive, asymmetrical case. Current id is the bridge dc input current. st/DIV A=.00046 Figure 4.13. Measured magnetizing current with PWM drive, symmetrical case. 81 To remedy this asymmetrical condition, either the PWM drive signal can have any voltsecond unbalance sources removed (accomplished later in this research with the phase lead circuit shown in Appendix C) or neutralized. Figure 4.13 shows the results of neutralizing the core offset effects by using a control winding to apply sufficient ampere-turns of magnetizing force to exactly cancel those due to the V-s imbalance. This was achieved by using a complementary— symmetry current driver stage for bidirectional current sourcing into the control winding of the test transformer. The harmonic content of the magnetizing current envelepe can be obtained by computing the Fourier series for ip(t) given by equation 4.13 as oo . + . \t 1p(t) E [an cos nwt bn Sln nu ] n 1 zip-I where a = 7T .l- ip(wt) cos nwt d(wt) TT (4.14) TT b = if i (cut) sin nwt d(m) n n _n p Substituting equation 4.13 into the Fourier coefficient expressions above yields the following where Io(- ) is the modified Bessel function of index zero and argument 811. Since this argument is less than 12 the series formula may be used to evaluate Iv?!) as (X) _ 1 X ZS+v : ———-<> 5:0 s!(S+v)! 7 (4.15) 82 where \>= 0. Then the coefficient ao in equation 4.14 becomes so = AIO(BAI) Sinh BAG. (4.16) With this coefficient the offset current i of Figure 4.11c O can be calculated as io=ao/2 z 90mA. This bias in mag- netizing force Ho=Nio is neutralized as shown in Figure 4.13 by 'NcIdc ampere—turns. Here, N is the number of c turns in the control winding. A test of this neutralized transformer (Table 4.2) shows that the magnitude of control current had to be increased as the primary peak-to-peak PWM voltage was raised. Also note the column labeled K (the PWM modulation depth) giving the values such that equation 4.10 is satis- fied. This is because the peak magnetizing current iM in Figure 4.11c is held fixed at 2.2A. Table 4.2 lists the empirical results. This data shows that peak-to-peak primary voltage (PWM) had to be increased by approximately the same percentage as modulation depth was reduced. This is consistent with maintaining c0nstant the primary fundamental volts per turn. The core is an ungapped 3C8 ferrite. When a gapped core was used in this same experiment, the same volts per turn was realized for two different values of gap length. The magnetizing current peak value again held constant. The gapped core did require a greater amplitude magnetizing current(due to its increased reluctance) at lower Vpri' 83 The data of Table 4.2 serves to clarify a significant point: transformer rating for PWM application is critical. For voltage control using modulation depth control and a fixed d-c source Vs' where V =2VS, it is necessary that PP transformer maximum volts/turn not be exceeded at the largest value of K. Therefore, in addition to its volt— ampere rating for power through-put, the operating volts/turn must have sufficient margin below its rated value if voltage control is used. Furthermore, a gapped core is much more tolerant of voltsecond imbalance but requires larger magnetizing current. In [11] it is shown that at 1.6 p.u. of rated voltage, the magnetizing current requirement equals the transformer rated current of distribution transformers. At more modest values of overvoltage the transformer current harmonics increase substantially. For 15 to 20 percent voltage overdrive the low order current harmonics--third, fifth, and seventh--exhibit near concurrent peaks. Most notably, the third harmonic can reach 75% of the fundamental. This is an "interconnection effect” which should be monitored by utilities where overvoltages due to distributed sources are likely. The remaining magnetizing current harmonics for the envelope wave of i (t) can be computed. The result will P consist of both even and odd harmonics where the coeffi- cients computed using equations 4.14 will be hyperbolic Bessel functions of corresponding order and argument 811. 84 Table 4.2 Transformer Bias versus PWM Modulation Depth K Vpr'x I dc Modulation Depth Primary Volts (Vp-p) Bias Current (mA) .91 24 80 .86 26 75 .77 28 100 .68 34 100 .59 38 100 .50 44 100 .36 58 130 85 The above analysis explains the presence of low order har- monic load current due to PWM. These harmonics will consist of both even and odd order. The current switching at a PWM rate within this envelope will generate current harmonics about multiples of the switching frequency. Two techniques of evaluating the harmonic content of a PWM waveform are as follows. The first method is to compute the spectrum of individual notch waves for each of M such notches defining the PWM waveform and to use superposition [33]. This technique requires knowledge of exact pulse and notch widths. Voltage control can be realized in a micro- processor controlled PWM inverter by having the switch element firing angles stored in a look up table in memory. This is the programmed waveform method. As such the dis- crete and well-defined time steps inherent in this method yields exact values of the PWM pulse and notch widths. The degree of resolution in output pulse width will depend upon memory capacity and word length. (A second method which analyzes the harmonic content of a PWM waveform for con- tinuous variation (as opposed to discrete step) of pulse and notch width is based on the technique first proposed by Bennett [37,39] in an unpublished report. This technique applies to the cases of uniform and natural sampling. Refer to Figure 4.14. The line with slope 1/P (P is the frequency ratio) intersects the modulating function (cosine curves) at the switching points of the resulting PWM waveform. The range of P is from zero to infinity. Notice 86 what happens as P traverses this range. For Psao the line becomes the abscissa («580) and the output is a pulse pattern with frequencytwb and amplitude 1. As P is increased from zero, P assumes values that are rational, irrational, and integer. At ps0 the line is vertical so that the switching function has degenerated to an impulse. It can be seen that this method accommodates all frequency ratios. The modulating function plotted vertically in Figure 4.14 is :2krr19’72 (l-K coswmt) where k=0,l,2,... and K is the modulation depth 0.7 in Figure 5.10, the right hand side of eq. 5.17 becomes negative. When D>Dc, the converter in its Open 100p mode collapses. 119 s d + DT TV v I,» S .1 l q 0 r q 1 V =V +V o _ _ f vl — (I 1))vO Figure 5.9. Converter circuit averaged model V 15V Vf .8V r .3 ohm r3 .45 ohm 0 measured . A A A A A # v 0 -5 .11). 1 Figure 5.10. Converter response as a function of duty ratio 120 The points along the D-axis labeled a,b, and c repre- sent the critical values of D,Dc at which the slope of the voltage transfer characteristic VS(D) is zero. That is, for a given load RL' operating points on the right of Dc are unstable. In a closed loop feedback controller, this repre- sents the point of zero phase margin. Of course any addi- tional lag introduced by the feedback will cause instability at duty ratios less than Dc' It is well known in converter theory [28] that the analysis technique, state space aver- aging, is not capable of identifying these critical values of D. It is here shown that the application of energy balance to the non-linear converter circuit model does pre- dict this very critical performance limitation. Laboratory measurements agree with the plots shown in Figure 5.10. The goal of this converter is to translate the variable voltage of a stochastic source as shown in Figure 5.1 to a regulated level. In order to achieve a closed loop stable output for a given regulated level Vs' it is necessary that the input voltage V+V not exceed an octave in variation. Then the maximum input voltage VMAX would coincide with the point D-0 and VHIN would be such that D>rc,rp,rq. This yields A u) Z/D’ V A n s/ (s) = = ,(S) (S.£32) V $2+2§wn8+w2 6‘ 11 Here the following derivations have been used. D’RLZ D. 2 S=O rc+0 LC(RL+rC) 2 A _ 1 mm - l/LeC and c - 2R; / re/C . If equation 5.18 is solved for 1/l-D - 1/D' and this, in turn, substituted into the numerator of equation 5.32, it can be seen that at higher boost levels the complementary duty ratio decreases. The corresponding effect on the low pass filter performance is a reduction of the bandwidth and increased damping. Hence, higher frequencies present in the input voltage experience increased attenuation along with enhanced damping--both desirable attributes of a regulator. 134 Using the definitions given in eq. 5432 in eq. 5.31 results in it being reduced to - S - (0n \3 X_2 X1 (7 A 5’ X1 T (5.33) S/d(S) = 12* 1:j[— = Gd($) + S ZCwnS + mm The response of output voltage to a perturbation in duty ratio is again second order. The numerator shows the presence of a right hand plane (RHP) zero, Sz 'wfiC/D’C‘Z/Xl) which is dependent on the state. At zero frequency, the variation in output voltage is related to the duty ratio perturbation by the gain factor Vs/D'. This is consistent with intuition in that low values of D' (high levels of VE) are accompanied by greater ripple in the defined quantity. Also apparent is the non-minimum.phase behavior of output voltage to perturbations in duty ratio. Furthermore, this RHP zero moves in response to the converter input impedance 2 S _ Qn C X2 _ V = RIN z " 15"— XI ‘ ITS" T (5.34) As equation 5434 shows, the converter input time constant determines the zero location. Since, in the ideal converter RIN - D'ZRL, the RHP zero is load dependent. In the unloaded converter this zero is at infinity and moves toward zero as loading is increased. With the PWM.inverter described in Chapter 4 as the load on this input regulator, a step change in lead angle at - g causes this RHP zero to jump. Response tests of duty ratio to a step change 135 in load are given in Appendix C along with various feedback schemes. The closed loop transfer function model for the regulator is given in Figure 5.13. In this figure only small signal behavior about the operating state is shown. Using the development given in Appendix C for the effective feedback gain He(s) using a gain only or single pole roll- off error amplifier, the closed loop performance of Figure 5.13 is A (S) v A 1 CV V615) rm d e s (5.35) where He(s) = -aKmKa. In this expression a is that fraction of the regulated- voltage compared with the reference voltage. ‘Variation of a sets the regulated voltage V6 to a defined level. Parameter Km is the transfer function of the pulse modulator and Ka is the error amplifier low frequency gain. The regulator low pass nature results in a loop bandwidth of eq. 5235 that is quite small. The above description of regulator instability can also be developed using the describing function technique. In the above analysis the pulse modulator hysteresis was neglected. Although itself an approximation, validity of the describing function technique is ensured by the low pass response of the regulator. Using this technique, the pulse modulator phase lag due to hysteresis can be modeled. From this the nonlinear element describing function is developed 136 __ POWER STAGE l"---"-------—b-—7 I I I A 1 _ I V'/‘ (s) I V'+9 ‘f’ I 4 8 V ' 1 x I i v E 1 RI. . I ’ A I _": V : vs/d(s) I I 7 I : . f L ________________ J n+3 He(s Figure 5.13. Converter closed loop configuration 137 using the fundamental terms only of its Fourier representa- tion. This done, any critical frequency (limit cycle period and amplitude) can be identified as the intersection with the plant Nyquist plot by the critical loci (negative recip- rocal of the nonlinear element describing function). The end result, however, will be the same as above. The gain must be low. When the control law shown functionally in Figure 5.13 is used as the boost controller in Figure 5.2 the large deviations of inverter input current id(t) cause this regu- lator to become unstable. The results of experimental variation of gain Ka of equation 5435 showed that to decrease the sensitivity of the regulator to this large ripple current 16' Ra had to be very low. Low gain will effectively offset the advantages of incorporating a regula- tor stage. For now if the input voltage V is random, then similar variations appear in the 'regulated' output Vs“ This has been shown in equation 5432. If the input to output transfer function Gv(s) of equation 5.32 is defined as the audio susceptability, i.e4, the tendency to become an amplifier, then what is needed is for vas) to exhibit high attenuation. Figure 5.14 gives the closed loop audio susceptability for this regulator with output feedback. As gain is increased, audio susceptability improves but the phase slope increases rapidly due to magnitude peaking. If the regula- tor output time constant is reduced, the audio susceptabil- 138 -1eo'.. Figure 5.14. 3O 160* Regulator audio susceptability with output feedback. 139 ity becomes worse for a given gain. ‘The data for Figure 5.14 was obtained by modulating a laboratory power supply with a variable sinusoidal source. This supply fed the boost regulator and load combination. An experimental control circuit was discovered which is capable of stabilizing this boost regulator with a connected PWM.inverter and driven by a random source. Figure 5.15 contains the modifications to Figure 544 needed to implement this multiple feedback controller. The auxiliary generator v is a sinusoidal source for audio susceptability tests and 9 a low frequency noise generator for random input measure- ments. The controller acts as an analog voltage programmer converting the dc supply Vi into a voltage controlled volt- age source (VCVS) of 200 VA capability. The basic boost regulator remains unchanged except that the connected load is now the PWM inverter. The output voltage is sensed via an attenuating network R10 and R11 in conjunction with error amplifier ARl. A current transformer (CT) senses the input current 13' This signal is processed by amplifier AR2 and summed to the ramp and pedestal signal at summer AR3. These feedback signals are compared at comparator AR4. The com- parator contains hysteresis so that the switching instants of D in d(t) - D+d(t) are clean. This duty ratio command d(t) controls the on time of switch element 01 to maintain Vs constant with highly pulsating load current and randomly varying input V . 140 Figure 5.15. Multiple feedback regulator controller. 141 The-analysis of this multiple feedback (MFB) controller follows. With HFB the scalar feedback gain He(s) of equation 5435 becomes a vector feedback gain. Because of multiple control paths to the comparator function (AP4 of Figure 5.15) its transfer function G(s) will appear by itself, as shown in Figure 5.16. The output feedback gain H2(s) c ve/V8(s) is found as follows: -K K .+T S _ dc 01 2 . Vs“) ‘ —_—1+ST2 Vs“) * (““1+tzs)VREF (5.36) _ R where ch — a 8/R9 V a - REF/vso Vso is the nominal value of Vs' K = 1 '1' R8/R9 0V 72 ‘ C2R8 and the tilde symbolav'will be used to distinguish MFB analysis from the output feedback case. Since VREF is fixed, a perturbation in the output results in a change in error voltage of ~ -K _ V ~ ._ dc (5.37) “2(5) ’ e/vs(5) ' 175.; ~ By circuit design the error voltage Ve(t) is constrained to -0.7 5 Ve(t) 5 4.7 volts. The feedback gain H1(s) can be found from Figure 5.15. The current transformer (CT) loaded 50 ohms resistive has a transfer gain of Ka of 0.1 V/A. Its phase shift is negligible over the bandwidth of the signal processing 142 —III"'IIIIDIIII‘II|' II'"'II|I|II'IIII .ILOlVEB-$.T.A§E _-- - - _ --_ I 1 1 I ‘|'l‘l"'|'l'l" 'I" Multiple feedback model. Figure 5.16. 143 circuitry. The effective feedback gain H1(s) = (imp/fem) is determined from R3 {7(5)=._;Q§£é,f x 1+ST1 S (5 38) Vrmp(s) = (1+KOI) Vx(51 - K01 V;mp(s) R where ROI 8 6/R5 11 = ClR3 yields, ... _ ac ~ , Vrmp(5) - mtg 15(5) " K01 Vmp(s) (5.39) R where Kac = (1+KOI)Ka 3/R2. Equation 5.39 can be put into the form of a transfer func- tion H1(s) by recognizing that the periodic time function V'rmp“) s v'rmp(t+Ts’ is very fast with respect to Is(t). That is, the average value of time function Vrm (t) is P modulated by the slowly varying function of time V;(t). V K = I'mp ~ g 3C H1151 /Is (51 T+Srl (5.40) The duty ratio control signal d(t) s D+51t) at the comparator output is g 53 d(t) - .1: [ve(t) - vmp(t)] (5.41) 144 where R'm/Ts is the comparator gain obtained, asdescribed in Appendix C, and Ts is the switching period of 01 in Figure 5.15. The steady state portion of d(t),D is given by the steady state portions of equations 5.36, V8° and VREF' and that of equation 5439, V' The perturbation in duty ratio rmp' d(t) results from the functions given in equations 5.37 and 5.40. In Figure 5.16 the comparator transfer function G(s) neglecting hysteresis is K'm/Ts 8 K”. Figure 5.17a and b illustrate the signals given in equation 5441 for the duration of a single switching period T8. The function G(s) - K'm/Ts - .373 V'1 is obtained from Figure 5.17. The block diagram of Figure 5.16 can be analyzed to obtain the input to output transfer function valid within the low frequency approximations made for the power stage. 125(5) = 1305(5) 17(5) - FOd(S) 5(5) (5.42) d(s) = 6(5) [Ve(s) - Vrmp(s)1 (5.43) With rC in Figure 5.15 neglected‘Vé(s) c §2(s), and since 15(5) - 81(8) then using equations 5.37 and 5.40, equation 5.43 becomes 5(5) = 1.145(5) 3(5) . (5.44) where He(s) = {-GH1(s) 632(8)] and 3T - (21(5) 22m) b) 145 a) d(t) Comparator output d(t) (top) and Vrmp(t) (bottom). Figure 5.17. Duty ratio controller signals. 146 Equation 5.44 shows that the control signal d(t) for the HFB case is a function of the regulator input current and output voltage. Substitution into equation 5.42 results in ‘Vs(s) = Fov(s) 9(5) + 50A(s) Is(s) (5.45) where F0v(5) = 1+FFOEAS(51 od 2 FodGH1(S) F s OA( 1 1+Fodcnz (57 The audio susceptability for the regulator is given as the Fov(s) component. At zero frequency this value is FOV(S) 5+0 = W ’1’ II; (5.46) where 508(s) is the cr(s) of equation 5.32 and Fod(s) is the 66(5) of equation 5.33 with steady state values x2 - Vso and X1 = 180' Using the HFB method the regulator is stable for high values of d-c gain. 'This is very important when the input voltage varies over an octave range or more. Figure 5.18 shows the results of an audio susceptability test for this regulator for two values of duty ratio D'. This figure can be compared with Figure 5.14. In that case, low gains were needed to insure stability with the inverter load. Conse- quently its audio susceptability was marginal to non- existent. The most pronounced difference between these two control methods is the substantial phase lead provided with 147 MAG (dB) +lO.. 1000 -10 4 -201 +45. 1000? F' . igure 5.18. Audio susceptability of HFB regulator. 148 MFB. With input from a wind generator having significant spectral content below 3 Hz, the regulator functions in its region of maximum rejection. The results obtained in Chapter 4 on the PWM inverter confirm the stability provided by the MFB controller. The extension of the ideas presented in the chapter to the multiphase case can be accomplished by proper phasing of the bridge switching functions. Referring to Figure 5.2, a three-phase inverter is realized by incorporating an addi- tional power pole into the bridge» The only modification is to displace the pole switching patterns by 360°/N where N is the number of phases. These changes require no modification to the PWM controller. 5.4. Source Power Tracking Using the Cascade Converter For this inverter to function with variable power input its phase lead u(relative to the utility voltage v‘(t) must be controllable. The bridge controller of Figure 5.2 provides this function by applying a filtered replica of this line voltage having digitally controlled phase lead to a phase locked loop. The amount of phase lead will depend upon the filter inductance. Since this reactor must have a gapped core to accommodate the wide range in injected current anticipated, relatively low values of Q will result. Filter Q is defined here as the ratio of reactance to resistance at the fundamental, typical values obtained in the laboratory range from 3 to 6. 149 The operating policy of a cascade converter in the maximum power tracking mode with a wind generator source is to sample the input voltage and use this information to vary the inverter phase lead. With the lead circuit described in Appendix C, a four bit control word provides 15 discrete steps in power. .A microprocessor controller is best suited to perform this control function. By comparing the input voltage sample with a look up value the processor can output a suitable control word to either raise, lower, or leave unchanged the lead angle . An example will serve to illustrate the means of power transfer that can be achieved using the circuit of Figure 5.2. First consider the simplest case in which the inverter output voltage is assumed sinusoidal. Then case I of Chapter 4 applies so that equation 4.21 can be used to plot real power and reactive voltamperes versus angle using the regulated voltage V8 as a parameter. In order to show the influence of various circuit parameters, the defining rela- tions will be used for V1 and V’ . The current I shown in Figure 5.2 can be found: nKVs/fi eJ (wmt'ta) - Vm/ ermt 12(a,t) = R - ’7 e 'Z'eje (5.47) = II cos [mmt + 6(a) - e] Arms 150 where 2 2 _ , ' (nKVS/fz) + Vm/z . nK\ SVm cos on 11 = 2 R + mm 2L2 nKV:5 . Md)=tmfl[ SUI“ ] nKV cosOt- V s m This relation for line current is plotted in Figure 5.19 for the system parameters given. In this example the conditions are such that up to 10 kW of power can be transferred. Operation into a 240 Vrms utility by the wind driven source having a voltage distribution similar to that in Figure 5.1 requires that Vs be set at 200 VDC' This means the regulator duty ratio need not exceed point a in Figure 5.10. Regulator stability is insured and further, since the power available from the wind turbine is low when the output voltage is low, then power throughput at high duty ratio will also be low. Conversely, when wind turbine output reaches rated power, its voltage rises so that regulator duty ratio decreases and efficiency improves as illustrated in the plot for‘wout of Figure 5.5. Moreover, operation of bipolar transistors at this level of V8 allows the devices to be 50% derated on sustaining voltage and maintain low switching dissipation. This requires reverse bias drive since the circuits are inductive. Therefore reliable operation can be insured. As noted previously, the transformer turns ratio can be kept less than 2 so that transformer losses can be minimized. In this case n-l;7 151 1‘ vm=r’§' 240v s A (DEG) Figure 5.19. Line current I as a function of a with parameter Vs 152 matches the PWM fundamental component to the utility when operating at modulation depth K near unity; Note from Figure 5u19 that line current for alpha zero is a strong function of V8 (hence the ratio of converter d-c port voltage to a-c port voltage). An interesting result is that when Vs drops below its rated value of 200V the resulting plots nearly overlay those for V8 greater than 200V by the same difference. What happens is that the angle (JYN)-9) of this current varies from a lagging to a leading value rela- tive to the utility (taken as a reference phasor in this case). For a given filter 0, the angle 6 is a constant. However, JV“), the angle of the filter voltage'Vz with respect to 2‘, is a function of lead anglecx given Vs' Figure 5.20 illustrates this dependence. Note in particular how rapidly JO?!) approaches 90° as O( is increased for the case vsczoo. When V8 is reduced below its nominal value the angle of V2 is always greater than 90°. The behavior described in both Figures 5.19 and 5.20 can be used to augment Figure 4.15 for additional insight into this type of converter topology behavior. The phasor diagrams of Figure 5421 describe the sequence for V8 less than, equal, and greater than nominal for a given lead angle. As can be seen from these sketches, it is possible to select a value of‘Vs given a value of utility voltage’Yk such that the angle of 11 remains near zero. The control angle O v80 Figure 5.21. Phasor diagram for converter voltages and current 154 point that it would not be prudent to allow Ottobecome a delay angle. If it did, the reactive voltamperes will increase markedly along with a reversal of power flow through the inverter. The regulator is unidirectional in power flow so that the wind turbine would not be allowed to absorb the power reversal. Consequently the regulated volt- age Vs would rise, control of the regulator will be lost, and the wind turbine would run unloaded. The control used for atin this research inhibits this condition from occuring. Rewriting equation 4.21 as S¢48 allows real power flow as well as reactive voltamperes to be assessed. 'The real and imaginary parts of equation 5a48 are plotted in Figure 5.22 as a function of «x. I (nK vs)2 nKVSVm 8(a) = —7T7T—- cos 6 - —7T7T—-cos (n+8) (5.48) (nKVs)2 nKV V )] +j[—2-l-Z-l—' sin 9 ‘ firmSin (0+6 With the same parameters given in the above example, raising the filter quality Q to 5 has the following effect. The real power levels P attainable are reduced for a given lead angletx. The corresponding level of reactive voltamperes Q are increased. Therefore a proportionally higher value of link voltage V8 is required. As this dc voltage is increased the behavior is again_as depicted in Figure 5.22. 155 Q P (kvm)(kw) V5- 4 mhL 3 230 10 - T 210 00 9O 5 4. Lag _§_u_______‘_230 O \ ‘-\ a _-_- [210 a - -:~ ~ -- _________ 200 35 Lead ‘ ~ - - - -.. ...._.. -190 (DEG) -5 A PF 1.0 -----.. AA ___ 1r fi90 100 .5 o O i . . 4 A P 4 + A 0 IO ' 2O ' 3o ' - a or (DEG) Figure 5.22. Real power P and reactive voltamperes Q versus at and typical power factor. 156 Figure 5.22 shows that power factor can be optimized by the correct choice of dc link voltage V8 to ac line voltage Vp. This means that for a very extensive range of power level, the reactive power will remain nearly constant. Thus operation at unity power factor or any desired power factor is possible. In conclusion, this chapter has presented data of an operational DC wind generator showing its highly variable power output over several minutes. The PWM inverter described in Chapter 4 was then cascaded with a boost type d-c converter to regulate the highly variable source voltage such that a-c line reactive voltamperes can be managed. In actual experiments it was found that because of the pulsating load presented to the regulator by this inverter output feedback was insufficient to stabilize it. It was shown that due to internal loss mechanisms the boost converter step-up ratio experiences a load dependent peak beyond which control is not possible. Consequently the control circuitry was modified to include duty ratio range Ilimiting. However, since constraining duty ratio within this range was also insufficient to insure stability a new control scheme was devised which did. Laboratory Ineasurements on this multiple feedback converter show a pronounced phase lead in its audio susceptability relative ‘to the output feedback case. The resulting stability with high loop gain provides a nearly constant regulated output under highly variable input. This chapter concludes with an 157 example to illustrate the capability of the cascade converter to provide power tracking while maintaining a selectable level of reactive voltamperes. CHAPTER VI CONCLUSION A. Rresent Busting This research has explored the conversion of d-c from a highly variable source into utility compatible a-c. The survey presented in Chapter 2 categorized the various con- version schemes. It was found that the availability of high speed power devices has opened the way for high frequency power conditioning methods. The most recent of these being the pulse width modulation (PWM) and high frequency link techniques. Both methods are aimed at active waveshaping of the current. ‘With PWM, a base band filter blocks out the high frequency components. The line injected sinusoidal envelope current appears at this inverter dc port as double frequency sinusoidal current pulses. The merit of this technique is that this current (envelope) is continuous. Field measurements of both the current source (CSI) and voltage source (VSI) converters show that injected current is a high amplitude and short duration (typically one quarter cycle) pulse. Appendices A and B present data showing the high levels of low-order harmonics present in these waveforms. It was found that the CSI outperformed the VSI at higher power because the input current sourcing 158 159 inductor of the CSI converter enables current to flow over a greater portion of the a-c cycle. The high frequency link is essentially the mirror operation. The source current is first shaped into double frequency sinusoidal pulses and then inverted 'unfolded' into the ac utility. Two methods for this waveshaping rely on high frequency switching. The key finding is that power must be processed two to three times. By processed is meant some switching operation involving semiconductor devices. However, a source with the variability of a wind generator has not been considered. Most power conditioning research at present involves dc power from photovoltaics. This means the source voltage is a function of solar insolation, array temperature, and type of cloud cover. The high frequency link concept and its variants, cur— rent band control, and current controlled modulator (MCZ) operate at unity power factor to optimize switching effi- ciency in two of three conversion stages. Being a high frequency process, it requires switching devices capable of handling large amounts of power at frequencies above 10 kHz. This necessitates bipolar technology and fast recovery diodes. The high frequency (current) link is also capable of sinusoidal a-c current injection and continuous input current envelope (is similar in operation to the field modulated generator concept). This research has also investigated different types of semiconductor switching devices. The push to higher fre- 160 quency operation in power conversion demands devices with the ruggedness of a thyristor and the ease of control of a PET. The power transistor and power MOSFET are best suited to high frequency operation. The gate turn off thyristors investigated in the report had problems with reliable turn off when operating at 1800 Hz. The bipolar devices did not. 3- Breathesis The central thesis in this research has been sinusoidal current injection with controllable reactive voltamperes and continuous source current demand. In Chapter 5 the cascade converter was investigated as a candidate for inversion from a variable source. 'The cascade was composed of a boost dc converter and a PWM inverter. It was found that although a boost converter can regulate its output voltage with an input range from 2 to 3:1 into a passive load, it cannot remain stable under large-signal load current. This is exactly the condition presented by a PWM.inverter large current pulsations. To overcome this inherent deficiency in voltage feedback, an input current (a-c feedforward) loop was incorporated. This multiple feedback technique resulted in a very stable regulator. High values of dc gain under large signal load is possible yielding a regulator with minimum output voltage variation for large changes in its input voltage. This new multiple feedback (MFB) technique is well suited for regulation of a random source with a pulsating load current. 161 C. Operation During this research, several interconnected features of the cascade converter were discovered. These involve start up and utility connection. Proper sequencing during start up is essential. With all logic control circuits powered, the dc-side contactor may be closed. If the regulator step up ratio is high at this time, a large dc source surge current will result. If this proves excessive for either the source or regulator devices, the control signal d(t) can be restricted in range to allow a soft d-c connection. Next the inverter must be energized in phase with the utility. The logic signal control provided by the PWM commutation margin circuit realizes on-off control and the phase locked loop provides synchronous operation. With the regulated voltage set for desired reactive voltampere performance, the a-c contactor is then energized. From this point on a power tracking function controls the inverter. The disconnect procedure is essentially the reverse of the above description. If utility voltage sags or surges out of its acceptable range, a check of the level of vm(t) derived from the utility voltage v‘(t) would be used to produce a disconnect command. All these features would be most economically done using the microprocessor controller. That is because thresholds and limits could be easily changed. Improper sequencing can be distructive. since the bridge incorporates inverse diodes and the switch existence 162 functions are complementary, then enabling the ac connection prior to starting PWM operation results in each ON switch and its opposite inverse diode short circuiting the ac supply. This was found to be a problem when using the upper driver memory latch circuit described in Appendix C. It was also verified that because of the unidirectional power flow capability of the regulator, disconnect or failure of the d-c source is isolated from the a-c utility. The regulator inverter voltage link assumes the potential that the full bridge inverse diodes deliver. Therefore no real power interchange occurs. Similarly for an ac fault, the line voltage sense is capable of very rapid disconnect. D. Future Research Several areas for future research are opened up. Evaluation of the audio susceptability on this regulator- inverter scheme show that MFB introduces considerable phase lead in its output to input response. This should be inves- tigated for different dc to ac feedback gain ratios. Simi- larly for the control d(t) to output VS response. This is now more difficult because of multiple paths into d(t). In order to assess the injected power variability in relation to that of the input power, a spectral study of both is required. )An output-input power spectra would define the degree of power smoothing provided by the low pass response of this cascade. 163 Measurements of conversion efficiency were not per- formed during this study. The most meaningful efficiency measurements on this cascade converter would require a unit of several KW rating to be constructed and connected to an operating dc SWECS. Because of high speed switching, the real power component at the input, output of the regulator, and utility injection would require use of an electronic wattmeter. This type of metering is versatile and capable of obtaining the reactive volt-ampere component at the utility connection point. APPENDIX A APPENDIX A ON CONVERTER TERMINOLOGY AND MEASUREMENT RESULTS ON THE CSI INVERTER This appendix provides definitions of the concepts used in the development of the line commutated CSI inverter. Consider the basic synchronous rectifier circuit of Figure A.l. Assume sinusoidal input voltage ggt) and a constant load current Is' Rectification occurs when the thyristor gating signal occurs between the line voltage vl(t) zero crossing and its first peak, i.e., 0$¢¢<"/2. The point whereCK-O is defined as the rectification end stop. At this value of a the thyristors conduct for fi'radians. If this mode of operation is chosen, there is no need for controlled switches; diodes will suffice. However, if control over Va is desired, then the angle4n/2 Figure A.7. Effect of finite x, on CSI operation. Suppose the converter firing angle is set to fire 6 ms into the 60 Hz utility waveform such that O! -= 130° at which point the value of v; (t) is e - 185 V. Then equation A.l6 gives a value of 108 microseconds for the commutation notch width. 2(XS+XC)Id tN = 108 us me At the external load bus which represents all other loads connected to the system at this point, the observed line notching will depend on the ratio of the system and con- verter impedance. This means that for a very stiff system, the generation of line notch-induced voltage harmonics will 182 be the least severe. With the line reactance values given in Figure An6 the voltage notch depth on the load bus is X _ S VD‘TT8=.76€ S C = 141 V The shaded area in Figure AJ7 represents the voltseconds required to commutate between alternate pairs of thyristors for a finite source impedance. The analysis to this point has concentrated on the continuous conduction case. That is, a constant current source was assumed. 'The final modi- fication to Figure A21 is to replace the ideal current source with a real voltage source and a filter inductor. This inductor (L) can be either air core or of ferrous metal construction. The component values given in Figure A.8 are representative of the system considered in example A.3. = r = .7 Ohm T L0 = soonn J L = BuH Th1 .4 Th} Vi = 345 sin wt x Lo 4. E = 160V a C r C = 1700uF ‘37‘ JL. V V1 d G E. a! 1' - Th4 Th2 18 .*__. Figure A.8. Non-Ideal CSI converter. 183 The voltages given in Figure A.9 have been chosen to correspond with values obtained during tests of this inverter. Figure A.9 is the actual oscillograph recording of signals vaa' , vd, id, and is. As shown in Figure A.9, the CSI converter firing angle is 15284° and the current pulse duration is 92°. It should be noted that due to the potential transformer connection the recorded line voltage is Va'a not Vaa' . Also, the noise present on both current waveforms is due to the sampling performed by the oscillo- graph input modules on those particular channels. Table A.1 lists the signal levels during this test. Table A.l Conditions for Recorded Data in Figure A.9 Signal Amplitude vdo -l60 Vac v6 50 vp_p Id 13.1 Apeak Vaa' 345 Vpeak delay angle 152.4° (2.66 radians) conduction angle 92° (1.6 radian) The analysis of Figure A.8 proceeds as follows. The input current is discontinuous (see is in Figure A.9). Thus thyristor commutatiom.is a source commutation occuring when the current through a thyristor pair attempts to reverse. The capacitor C in Figure A.8 provides filtering of the dependent voltage Vd' The effect is that V6 is effectively 184 M3 5.4. m V T I C3 .1 El! . NH ,9 V = 82 V/cm, V d aa' =72.6 V/cm, id=3.42 A/cm, is=2.24 A/cm Honeywell 1858 Visicorder at 80 in/sec. Figure A.9. Oscillograph of CSI performance. 185 clamped to Vdo' the potential across capacitor C during the time intervals in which no thyristors are conducting. This effect is shown in Figure A.lO (note that in Figure A.9, Vd is also inverted to coincide with V3.61. Several important features are apparent from inspection of Figure A.9 and Figure A.lO. First, the steady state volt seconds impressed upon L average to zero. Notice the strong flux bias in L due to is' which causes the incremental inductance of L to vary as the average d-c amp-turns produced by is forces the operating point to move along the magnetization curve as the d-c generation Es varies (not apparent in Figure A.9 because ES and Vdo are slowly varying functions of time). Second, the peak of id(t) occurs exactly at the point when Vaa' (t) I: de' This gives the value of fit at which did(t) -—;:—- a 0. Using Figure A.lO, an analytical expression can be derived for dependent current id(t) injected into the utility. Vd . jf\~ 5;:331 f 4: «rt \/—. 3 Figure A.lO. Waveforms illustrating non-ideal CSI performance. 186 t v.3.1.== [ (vaa,-Vdo)dt; a/w :_t < a/. + tON 01/0.) t a = f (Vm 5111 wt - Vd01dt a/w - d0(t-a/w) + Vm/w(COS O. ' COS cut) (A.17) . _1, 1d(t) - I:\.S.I. V -—%?-(t-a/w) + 5%-(cos a - cos wt) idm id(t) = 2.0 x 104 (t-a/w) + 114.39 (cos a - cos wt) where a/w §_t<:a/w + toN , t in ms. Equation A.l7 is plotted in Figure A.ll for two values of inductor L. The d-c component in equation A.l7 vanishes vaa', id(t) (V) 1 (A) (300740 0 (150)20 - Figure A.ll. Plot of equation A.l7. 187 1653.233 Y:-3.2333 HARMONIC LEEEI 1 IN) 1 as j 7 2 1 i S ————. -m “o w H“ ~“ A...‘ .34...“ ”.- .. w.” -~-u~. .04.... -. ¢fi|b¢~ulnonvu4u ’NM ‘ - m m~.—.-~ ‘1'? '4ILIIU T “I T W I T I IJI HZ (HELD! s 3 KW output from 4 KW rated dc generator Figure A.lZ. Spectrum of id(t) recorded in Figure A.9. 188 due to odd symmetry. The conduction angle tON is a func- tion of thyristor firing angle 0‘ and the ratio of Vdo to Vm. So, if at approaches "radians for a given input source voltage vdo' the peak amplitude of id(t) is reduced. This is a consequence of the non-ideal current source nature of the Es and L network. The spectral content of id(t) is displayed in Figure A.lz. This spectrum was obtained by recording the signal id(t) on a magnetic tape recorder during normal operation of the CSI inverter and then playing the tape back into a lab spectrum analyzer. The results of this spectral analysis show that the total harmonic distortion for current id(t) using harmonics 3 through 9 is: THDI - 1/(.304)2 + (.089)2 + (.040)2 + (.032)2 THDI = 0.32. This is lower than for a square wave .483 and illustrates the current waveshaping provided by inductor L in this application. APPENDIX B APPENDIX B VSI CONVERTER THEORY AND MEASUREMENT RESULTS This appendix reviews the theory and experimental re- sults obtained from an operational 10 kW VSI line-commutated inverter. It will be shown that this configuration gen- erates significant harmonics even as power approaches rated value. The reason can be seen from Figure 8.1 where the wind driven generator (alternator in this case) feeds an uncontrolled bridge rectifier (a three-phase Graetz cir- cuit). The three-phase rectified voltage is filtered by I' 3: £% 2%» ‘V Th1 ‘V’Th3 13W) e 0 1d n 82 r x "J" 11 a a' T (W T- “ 2 e xs v1 8:3 I‘ X ZS 25 V Th4 . VThZ Figure 8.1. Alternator driven VSI converter. 189 190 capacitor C and this filtered voltage Vs' a slowly varying function of time relative to the line voltage period, supplies through a thyristor bridge dependent current id(t) to the utility source V;(t). The situation is that of a voltage source driving another voltage source: so when source potentials do not match, large currents can flow. The dI/dt reactors shown in Figure B.l limit the rate of current rise of the bridge thyristors and have a moderate effect on current waveshaping. It is also necessary that lead and reactor winding resistances be equal since any unbalance will introduce asymmetry between the two bridge poles and consequently generate even harmonics. Since all such converter installations are interfaced to the utility distribution network through transformers, the d-c component of the injected current will bias the transformer core. Should the ampere turns due to this bias be sufficient to cause the normal peak operating flux to exceed the knee of the transformer magnetization curve, substantial current peaking will occur along with an increase in the third harmonic of the line voltage. Reference [14] gives examples of unbalanced ampere-turns on interphase transformers and inverter transformers. The analysis of Figure B.l is done using the operating conditions and parameter values given in Table 8.1. The base quantities are 240 Vrms and 37.5 KVA. The transformer has 3.66% impedance so that 191 2 3 = (.24) x 10 _ Zb 37.5 - 1.536 ohms XS = 3.66 x 1.536 x .01 = .056 ohms L = XS/w = 148.5 pH (8.1) Using an inductance bridge the parameters of the tapped reactors were obtained. The remaining values in Table 8.1 are nameplate or calculated. VSI Converter Operating values Component parameters Table B.l Circuit Parameter Values reactor reactor (5 w t‘ t” IT 198 Vdc l4 Vp-p ‘2 Apeak 232 Vrms 5 kW approx. 148.5411 .9 mH .8 ohm 39004 P Thyristor 125 At rated current _If the assumption is made that for operation at less than rated power the reactors remain linear, then L reactor can be set constant at its measured value. It should be 192 noted that the inductance measurement was made at 1 kHz so that the value given may be somewhat higher at 60 Hz. The analysis using linear theory will give an expres- sion for the line injected current id(t). Given an equation for id(t), valid over a complete cycle, it will then be feasible to make theoretical calculations of the injected current harmonic levels. It is necessary to note that for this converter both input current (to the thyristor bridge) and the line injected current will remain discontinuous. This is an essential departure from the CSI converter in which continuous current operation is a function of the d-c source parameters and the ratio of d-c to a-c line voltages as demonstrated in Appendix A. A further simplification to the circuit of Figure B41 is to replace the generator, rectifier and filter capacitor with its Thevenin equivalent source. Using the operating values of Table B.l the effec- tive output resistance of this network can be determined as AV RT“: "—z'lEE: .37 OhIn d . . (B.2) lam-vs min +RTHld peak= 205v Using the values calculated in equation B.2 the overlap conduction (ice) that will occur during a commutation failure can be found as the response of a series R-L circuit. In this instance the driving function will be a step in voltage of magnitude BTH' 193 . (B.3) Em/Rr [1 - exp(-R.1. t/Ln icchj = where RT = RTH + 2(R0N + Rreactor)‘ After four time con- stants, current icc(t) will have reached 102.5 A. For different Operating conditions higher or lower values will occur. The important point is that current magnitudes capable of exceeding the maximum thermal energy rating (Izt) of the semiconductor devices can be reached rapidly in a fault. An additional feature of VSI converters would be the inclusion of series fuses with each main thyristor. The constraint being that Iztfuse < Ithhyristor° Measurements on the performance of this converter show that the thyristors are gated on an angle1€ ahead of the voltage wave zero crossing. This angle was found to remain very close to 3° (.15 ms). Consider the interval from 76 to wtON during which thyristors Th1 and Th2 are ON. Time tON is the conduction time of these devices. Application of Kirchhoff‘s voltage law to the circuit of Figure B.2 during Figure B.2. Simplified VSI converter. 194 this time interval yields . did(t)/ ETH - v2(t) = (RTH+R1+R2)1d(t) + (L1+L2+LS) dt + V + V (8.4) T(flfl) 'r(na) where VT is the thyristor ON state voltage. Let R = R1 + R2 . 2 R Lr = L1 + L2, and ETH = r reactor' did(t)/ EIH _ Vm sin (wt-B) = (RTH+Rr)id(t) + (LS+LT) dt (B's) Shifting the time axis in equation B.5 by1PAu and taking the Laplace transform yields EIH Vm(w cos B - 8 sin 8) s ‘ 2 2 S +'w = (RTH+Rr)Id(s) + S(Ls+Lr)Id(s) E‘I'H V [5 sin 8 - (1) cos 8] (B.6) I (5) = +1 5+1/ ) + m4 2 2 d SUB r)( T (HSLQ(944”(S*“) Where discontinuous conduction yields id(O+) = 0 and w. 1'1 T==R;EHT'= R; , a partial fraction expansion of equation r B.6 is I (s) = E1“ - E1” - VD. [sin 8 + wt cos a] d RES' R;(S+17T1 R}. (1+w2T2)(S+l/T) (B.7) SVfi(sin 8 + wt cos B) th(wT sin 8 - cos B) + + V RT(l+w2t2)(S2+wz) RT(1+w212)(Sz+w2) The inverse Laplace transform of equation B:7 can be ob- tained to yield the time response id(t) for 0 S t g tON' 195 The current ceases at t - tON because the line voltage source commutates the ON thyristors. This result is plotted in Figure Bh3. Comparison with measured data in Figure Bv‘ verifies this analysis. 1+w T . ’ V ' + ids) = Kim- [1 - exp (- m1] - q” [51“ B 2 ‘5” C05 8] exp (- m) + V1'11 R? I (8.8) 0 V a Sin 8 + or cos B m wT s1n B - cos B . 1+w T where 0 g t 5 tON' The noise present on the two current measurement channels of the oscillograph was due to signal sampling in those parti- cular modules. .All other signals were obtained using high gain differential input modules. As Figures B.3 and B.4 show, the initial current slope did(t)/dt is much more severe than for the CSI topology investigated in Appendix A. For the operating values shown, the initial current slope can be determined by taking the derivative of equation B.8 and evaluating the resultant expression at t - 0+. d1 (t) ’ + V’ V d l8TH m w )1) (wt sin 8 - cos B) ' (8'9) at = —Er_+ '1? t=0+ 1+wztz As equation B.9 demonstrates, the dI/dt stress on incoming thyristors is inversely proportional to the inductance pre- 196 id(t1 (A) u. 60 . Vi ( t) 404. 20. -404, -60 (1 p= 3° 1»:TH .. 205v vm - 323v .72. .975 ms ton = 2.75 ms Figure B.3. Plot of calculated line current for VSI converter. 197 _— UVI‘TI l b ." 3;. 'tIWfrrl1 l -‘ 7+7": , Lr\1~T—r~r1— 3" Vs 32.7 V/cm; id 10.8 A/cm; Vaa' 24.7 V/cm, is Honeywell 1858 Visicorder at 80 in/sec. Figure 8.4. VSI waveforms at 5 kW output. v8 .id 7 as. L. :1 is I). I Q 10 A/cm 198 sent between the d-c voltage source and the utility line. In the limit as LT—DO, the rate of change of thyristor anode current lideT/dt-an. Since some inductance is LT-no present at all utility interconnection points, the thyristor dIT/dt limit may or may not be exceeded. Thus the main purpose of the dI/dt reactors is to limit turn on current slope. As Figures B.3 and B.4 also show, a secondary feature is the introduction of some waveshaping into the current pulse trailing edge. This waveshaping will contribute to a reduction in current harmonics and help to increase the total power factor. Examination of Figure Bv‘ reveals fine structure at the peaks of the voltage waveform vaa' an. This detail con- sists of a step change in voltage vaa' that is a function of thyristor turn off °ITldt and the a-c side inductance. The ringing is due to line and transformer leakage induc- tance resonating with distributed capacitance. The ringing frequency as determined from Figure Bv‘ is approximately 4 KHz. Figure 8.5 is a one line diagram of the converter in Figure B.2 during one half cycle at t - tON' At t a tow the flux change in LI and L8 is not sufficient to force current id(t) into source \k and a source commutation by Y: and ETH forces the conducting thyristor pair off} As soon as thyristor recovery occurs the voltage Vaa' (t) 199 L: 1 TH lell p. at Figure B.S. VSI one line diagram during source commutation. executes a step change in magnitudeovaa. given in equation 8.10. did(t) Avaa.(t) = I.S T (8.10) t=tON Using equation B.9 and tON from Figure B.3, the value of Vaa' in equation B.lO is approximately 3.7 volts. This agrees quite well with the 1.5 mm step at the peak of vaa'(t) in Figure B.4 at each thyristor pair commutation point. One final comment on equation B.8, as the source generation increases, the defined d-c voltage ETH increases propor- tionally resulting in the first term of equation B.8 (which defines the target current during each half cycle) increasing in magnitude. The current slope at turn on increases likewise (equation B.9) with the final result that 200 103.871 7.4).st mm L 95!: 1 lb 1 ll an 18 H2 mm Figure B.6. Spectrum of VSI converter line current. 201 the current conduction interval tON remains relatively fixed. From this development, one would not expect to observe any marked reduction in harmonic content of id(t) as rated power is approached. Such is indeed the case. Figure B.6 is the log spectrum of the time waveform id(t) in Figure B.4. Of particular interest in Figure B.6 is the fact that third and fifth harmonics are comparable in magnitude. This spectral data was obtained from laboratory analysis of a magnetic tape recording of the VSI converter using an FM recorder having flat response from DC to the tenth harmonic. Harmonic data beyond the ninth will not be accurate. Thus the magnitudes of the eleventh and thirteenth harmonic are uncertain. APPENDIX C APPENDIX C CONTROL CIRCUITS FOR PWM CONVERTER This appendix contains the circuit schematics and analysis of the functional blocks contained in Chapters 4 and 5. Figure 4.3 is repeated here as Figure C.l in which the main elements are the phase locked loop (PLL), the dual slope integrator and a comparator. Discussion of the phase lead ( ) circuit will be deferred until the PWM control circuitry has been completed. The PLL circuit is drawn in PT :[ v.‘ _L: vco : It i vam K,P K I Kwh(t) Figure C.l. Functional diagram for natural sampling. 202 203 Figure Ck2. CMOS devices are used because of their wide‘ supply voltage tolerance and low power consumption. The 60 Hz line reference signal is squared by saturating amplifier ARl. Negative excursion at the output is clamped to protect the PLL input (U1). For a frequency ratio P-30, the voltage controlled oscillator (VCO) must lock at me - 1800 Hz. Therefore, with the VCO center frequency chosen at this value the PLL will lock to a 60 Hz reference square wave so long as the frequency error remains within the acquisition bandwidth (on. This acquisition or lock bandwidth must be sufficient to allow for normal VCO drift and 60 Hz line frequency variation (typically less than 11 Hz). The low pass filter (LP) has a cutoff frequency of approximately 34 Hz for loop noise rejection. The divide by P function is realized with a lS-stage twisted ring counter U2, U3, and U4 with coupling via inverters US A, B, and C. Only essential components and connections are shown. The PLL circuit analysis is no more involved than a type I second order control loop. The phase detector (PD) has transfer gain K;:volts/radian, the loop filter, G(s) and the VCO transfer gain, RV radian/volt sec. In Figure C.2b the complete PLL transfer function T(s) can be determined. The VCO transfer function can be obtained asiaé(s) - RV V1(s) - sQ(s) so that 6c(s) - (Xv/s) V1(s). The 'digital phase detector has a phase at lock of ”72 radians and V1 - vDD/2 where VDD is the supply voltage. If the output phase increases, the error voltage V1 is reduced and vice-versa. 204 U2 E? T0 111th I A} ‘F———' VED r'clk m. l n CD4066 '- vm ]_ vc Q5 it 14111 , PD L—‘ , 022 E—— __~”1Ll CD4018' ’ ‘l LP‘ ' ' m L vco 4.1: .11: D. ‘ .1 '0 90k 100k ‘- Q5 “—‘Clk D a) Phase Lock Loop '65 -.L 3 USA U3 U5! U4 -_]i;bUSC b) Functional Diagram Figure C.2. (.31 $21- Detail of PLL circuit and functional diagram. fl 205 In this case K; -= l/qr (VDD - vss) = 4.7 rad/sec... and RV a 818.4 rad/volt sec. Then T(s) is 6 K¢VT T(s) = C (s) = (C.l) Pwnz “51 = 2 2 S +2 CwnS+wn where ‘1’: RC of the LP function and K 1%, p <13 = 1 w 3 1') Equation C.l shows the low pass nature of this PLL. The closed loop 3 dB bandwidth “(1 determines the time to lock. Therefore the response to a step change in phase 9m of vm(t) will have a damping coefficient 1'. For this circuit to respond rapidly and yet have low overshoot, it is necessary for 3’ to be chosen accordingly. A 3 - .7 is a common and suitable choice. Using this value and the defining relations of equation C.l yields an expression for the loop filter capacitance C. P C = -——-2- = .08 DF 4RK¢1§lC (C.2) Therefore a value of C - .lx(f is selected for which I c .64 and the loop lock bandwidth is a)“ - 165 rad/sec so that this circuit will settle to a step in phase in approximately 24 ms. This means that for operation in the utility phase- locked mode, the system can respond to a change in phase in 206 less than 2 cycles. In order to achieve such a low lock bandwidth (fn s 26 Hz, 1.4% of fc) it is necessary that the VCO center frequency remain within +756 Hz of fC. ‘The center frequency in Figure CLZa is set by the .02224f capacitor and a 90 KJ\resistor which is trimmed for fc = 1.8 KHz with P s 30. Figure C.3a is the schematic of the integrator and PWM comparator with parameters P and K. The dual-slope integra- tor consists of amplifier ARl with transfer function A(s), resistors R1, R2, and R3 and capacitors Cl and C2. Resistor R4 is used to minimize input offset voltage by providing a ground path for input bias current from the non-inverting terminal of ARI which equals that on the inverting terminal to ground. R4 - R1 "(R2 + R3) where Rl >> R0 of the pre- vious stage. The RC feedback network on ARl has transfer function be(s) = Ifb/Vc(s) be(s) = s[c1 gR2+R3)++ SC1R3C2R2] . (C.3, V R2+R3 (1+5 CZRZ) ARI ‘Vi—(S)=m WW where R3C2 = 33 ms >> R1C1 = 3.3 ,5 > Z/fc = 1.11 ms (c.4) Equation Ca4 will result in an ideal integration of 111/8 in the limit as c2 +00 with KI - -1/R1c1. That is assuming ARl is an ideal amplifier withoutdynamics A(s)2 .Ao—vfli. In the practical circuit it is sufficient to 207 cl ll 2 “.1123 'A'A'L _LAVA'A' Vim R1 3311:2113? -—MM—_( _ - . Vc(t) 33K '1 1" fc ARl c3 ‘L prmm R4 15K R5 + 2 K, P D1 — T ? Vm(t) KVm(t) 10K 't. J! ‘r 11 c4 iR6 '1? -.- a) Integrator and PWM comparator. b) Spectrum of V WM(t) for K = .95 and P = 30; 60 Hz line at left is 1.5 dB above marker dot on fc. Figure C.3. PWM circuit and spectrum of VPWM(t). 208 select C2>>Cl such that the inequality given in equation CN‘ is satisfied. For the values given in Figure CL3a operating at P-30, results in the given condition being satisfied. The effect of a non-ideal amplifier ARl transfer function A(s) is to modify the denominator term in equation C.4 to VARl ~ KI v. (S) ‘ 1 1 S[1+ /A(s)] (c.5) GB where A(s) = 3:2)— . 3 Hence, for operation at low frequencies (~103 Hz) and with a general purpose ARl having gain bandwidth (GB~10°), the error associated with the non-ideal characteristics can be neglected. The comparator AR2 is a high gain amplifier operating open loop to achieve fast switching at the intersections of Vc(t) and xvifit). Resistors R5 and R6 are bias current return paths for AR2 and diode D1 is a negative voltage clamp for interfacing to the following TZL logic circuits. Capacitors C3 and C4 are necessary because any d-c offsets present at the input to AR2 will cause an asymmetrical PWM wave. This, as noted in Chapter 4, will result in the generation of even harmonics and their adverse effect on transformer operation. One result of this comparator func- tion-is the introduction of pulse jitter in the PWM pulse train. Experimental results show that this PWM jitter is about 548. Figure C.3b shows the PWM spectrum of VPWH(t’° 209 This spectrum verifies the analysis given in Chapter 4: only even spectral lines about the odd carrier multiples and odd spectral lines about even carrier multiples (the 2fc line is at -35 dB relative to the 60 Hz line). Before this PWM pattern can be applied to the bridge driver circuits, a complementary PWM pattern must be gen- erated. In this way the top switch in a bridge pole func- tions during complementary intervals to the lower switch in the same pole. Figure C.4a describes these PWM patterns for the 2-1evel case and Figure C.4b for the 3-leve1 case. As Figure C.4a indicates, the switching function Hl causes switching devices 81 and S2 to turn on at its logic 1 level and off at its logic 0 level. The bridge output waveform Vaadt) will be either +Vs as defined by switching, or existence, function 81 and at -V8 as defined by existence function H2.- This circuit operates between either of two states five and hence generates 2-leve1 PWM. A second varia- tion of the switching pattern is to operate the top switches 81 and $3 at 50% duty ratio and the lower switches 82 and S4 in the PWM pattern. Except for this case, the lower switch existence functions must be |'windowed" by the top existence function of the opposite pole. Figure C.4b illustrates this case of 3-level PWM in which an additional state at 0 Volts is allowed. If the lower switch functions were not selec- tively blanked, either pole or both would form a low imped- ance path across V8 and results exactly the same as for a commutation failure described in Appendix B would follow. 210 l . H1 I 31 52 J31 / S3 O ,_ o a a. 1 (— Vs ~—-() VaafiD-—- H2O ‘ 33,54 2 S4 ' l/ 52 +Vs :. vaa' -vs-—J L. a) 2-Level PWM 1 F———-' 31 o___1 l—___ S3 0 ______ 1 1 S2 0 F"Ll II I I l s4 311 We. m n 11‘ b) S-Level PWM Figure C.4. PWM switching functions. 211 The major advantage of 3-level PWM is that switching losses on half the switches can be reduced because only two commu- tations per half cycle are needed. These definitions of bridge switching functions assume ideal devices. Any practical device requires a finite time to reach its ON state and similarly some finite time to regain the OFF state. Should the existence functions shown in either Figure C.4a or b be applied to a bridge circuit with bipolar or thyristor devices, very large pole currents would occur during the turn on of one device and turn off of the remaining device in each pole. These short circuit currents would be especially destructive of bipolar devices since their base drive may be insufficient to hold the transistor in saturation. The attendant large power dissipation would quickly result in transistor failure. The second concern is that circuit inductance is invariably present and the large dIldt induced voltage transients can easily exceed the bipolar collector to emitter breakdown voltage. If these transients contain sufficient energy, the transistor Esb rating may be exceeded also. The second breakdown that results would then permanently damage the device. The thyristor is much more tolerant of high current surges due to its regenerative characteristics so that power dissipation will not be increased as dramatically. rDuring research on the bridge operation utilizing bi- polar devices, the two transistors in one pole were lost due to second breakdown in which the collector became fused to 212 the emitter as a result of excessive current transients. This resulted because insufficient margin had been allowed for device storage time. Storage time varies with current density and without antisaturation (Baker clamp) circuitry on the transistors, the allowed margin was exceeded. 'The circuit needed to introduce this switching margin is drawn in Figure C.5a for the case of 2-1evel PWM. In the 3-level PWM, additional gating is necessary to realize the blanking of alternate half cycles. The circuit of Figure (LS operates on the output signal VPWM(t) of Figure Ch3a after some logic level translation. The objective is to generate the pair of switching functions HI and HZ shown in Figure C54. These existence functions are labeled according to which switch they enable, i.e., USPl for upper switch pole one, etc. In this circuit, the base PWM wave edges are notched by an amount determined by the RC time constants of 01 A and B. The complementary pair of edge-notched PWM patterns are produced at the output of exclusive OR gates 02. Gate U3 introduces inhibit control over the PWM pattern so that the entire bridge may be shut down by external control. The logic inverter gates of U4 are needed for current drive capability into the intervening device driver stages. The timing diagram of Figure CLSb demonstrates several unique features of this circuit. First, a time lag equal to the RC time constant is intro- duced into the PWM existence functions. This means that the fundamental component will lag the line waveform Y‘(t) 213 J M VP , 74123r 2% 1? 4: U2 V T 1 fine] 3 [ llclr Q| UlB L ‘T— Pwk CNTL a) PWM programmable commutation margin circuit. Y 6 w .l f L1 —_‘ T USPl P2 SP2 LSPl :' ' H l ' lg m : 3 [L ! fl 3! 's I . : t :1 '---" ' l .w—-—- _ _____, ' I I I g I I I I o VP‘WUIA 'mh ,;___' : _ .L..l.__._:_.. I l . I '_ ___.. F——_— vaPUlB 4L— b) PWM complementary existence functions with commutation margin. Figure C.5. Commutation margin circuit and waveforms. 214 +9V 1 - 55k Q 1Q ‘ 2N2905 Ic _L 2.87k:; , C LSPX 1 . 31: A _H Q4 7 "—K$—1 DzTZ 15k 22 —~mr v: 65 10 ~ -9V ta a) Driver circuit with connected BJT switch. 10V Isolated + %22k UlAL 7. 1%; 0113 , T ~{>_ saga: b) Pulse reconstruction. Figure C.6. PWM driver circuit. 215 by RC seconds. Second, the existence functions 81 and 82 mesh with programmable margin on both leading and trailing edges. Therefore, with turn on of sufficient margin, switching rise times and fall times and storage delay can be accommodated. Third, due to unequal propagation times through these devices, the occurrence of 10 ns delay differ- ences are observed in both 81 and 82 at the beginning of the notch. This unavoidable effect can be compensated by increased capacitive loading in the subsequent driver (Figure C.6). The driver stage was designed so that, with minor changes, either bipolar or thyristor devices could be switched. The input is compatible to T2L logic or paral- leled CMOS. Since the inverter bridge can have one side grounded in the transformer coupled case the driver stage couples the logic signal from Figure C.5 directly to the main switches (low side of all poles). That leaves the upper switch driver referenced to a common which switches rapidly between ground and +Vs. This requires to individual isolated supplies. Figure C.6 shows the driver connected to a BJT main switch element. In this case the collector load resistors of both 02 and Q3 are chosen for equal 181 and 132 drive to the Darlington connected switch. 'When the gate turn off (GTO) thyristor was used the necessary current source turn on drive was realized by adjusting the collector load of 02. To provide a voltage source turn off drive the collector 216 load on 03 was reduced to zerOu The supply voltage is below the avalanche potential of the GTO so that gate-cathode breakdown is prevented. A quick analysis of this circuit shows that it has two stable states which are dependent on the logic drive signal. The circuit to the upper switch drivers is complicated by the need for operation isolated from ground. Several methods for sending the PWM switching functions to the isolated drivers are feasible. Three different methods were investigated. The use of both opto-isolators and trans- formers were tried. When using an opto-isolator with PWM it was found that the photo-transistor response was slew lim— ited so that narrow PWM.pulses were distorted. The lamp diode voltage signal retained the input PWM shape. In lieu of this shortcoming a pulse transformer was used. Because it takes a substantial transformer to pass logic level signals undistorted (low droop) the pulse differentiation approach was taken. In this method the PWM logic signal drives the pulse transformer so that a differentiated pulse pattern appears at its secondary. The PWM pattern is then reconstructed at the isolated ground by the Schmitt trigger latch (Figure CLGb). The small core transformer T1 has a 50x10“6 volt-second product, so it cannot pass the widest (50048) PWM pulses. The load Rl on transformer. T1 damps ringing when the core resets after each pulse. By empirical adjustment the best noise immunity was found to occur when the memory hysteresis adjustment R2 was increased to the 217 This is potentially damaging when 01A is such that its corresponding switch must be held OFF. Gating an: OFF device back ON causes bridge overlap conduction to occur. This phenomena was verified by replacing the small pulse transformers with audio quality transformers capable of passing the PWM pattern undistorted. In this case both L, and Cw were higher (Cw ~ .OOBMF) so that the overlap conduction problem was easily induced (a limiting resistor was added between +Vs and the bridge to prevent device damage). By plotting the susceptability to failure (level of V8) versus the ratio of notch margin to oscillation period (To4~v15x(s) it was found that the circuit was relatively immune for odd integer multiples of notch margin to oscillation period. This confirms that the second peak in successive odd periods of the oscillation falls within the notch margin (no bridge conduction). It also means that in this application pulse transformer design is very critical. Performance of the circuit in Figure Cw‘ was next assessed using the existence functions of Figure CL4b. The upper driver circuit was modified to handle the required 50% duty ratio or 8.3 ms ON pulses for 3-leve1 PWM. This change resulted in the circuit of Figure C.6 being replaced with a BF carrier source and an envelope detecting circuit in place of the Schmitt trigger latch. 'The idea was to blank a 350 K82 square wave oscillator, a propagation delay type using coupled monostable multivibrators, at intervals of 8.3 ms 219 and send alternate pulses to switches 81 and 53 by way of the same pulse transformers. The driver was next converted into an envelope detector (circuit of Figure CLGa) by adding 384 pF of capacitance from the collector of 01 to the anode of D1. ‘With a transformer coupling the bridge to a resis- tive load on its secondary, the oscillograph recording of Figure C(7‘was obtained. In this recording waveform Vm(t) is the modulating signal (60 82 reference) and V§(t) is the output voltage across the load resistor (no filtering). Current id(t) is the d—c source current and i;(t) is the .resistor current. The trace for id(t) clearly shows that the transformer magnetizing current occurs at the zero crossings of Vm(t).‘ The current is positive but makes negative excursions (energy returns to Vs) when a reactive load, either lagging or leading, is connected. Both currents id(t) and i1(t) reveal a source of trouble which befell this experiment. The current pulses id(t) are several amperes in magnitude, have large rates of rise and fall, and so are a source of significant levels of interference. With such a source of both conducted and radiated emissions, shielding of the PWM controller became a necessity. Before the results in Figure C57 could be obtained, the entire driver circuit had to be enclosed in a magnetic shield and all low-level signal leads to the driver had to be replaced with shielded twisted pair. It was found experimentally that radiated magnetic fields, even though attenuating at r'3, were the single most significant cause 220 of induced voltage transients. Hence, ferrous metal shielding and the minimization of signal lead loop areas proved to be the most reliable cure. With this knowledge of how a 3-level PWM converter performs, the transformer secondary (rated for 120 Vrms 60 Hz) was connected to the utility 120 V line. This resulted in some interesting findings, as shown in Figure C.8. For the fundamental component of the PWM waveform to be coincident with the line voltages, phase lead had to be introduced ahead of the phase locked loop. This lead circuit is shown in the functional diagram in Figure C.l with inputs from a potential transformer (PT) for the line reference signal and a vector input consisting of the four lines DO,...,D3. The first candidate circuit investigated for this application was straightforward--use a phase-lead circuit. This proved to be an unwise choice. Although it was known that phase lead is very noise and high-frequency susceptible, perhaps an introduction of a lag pole just beyond the lead pole would suppress these undesired effects and still retain an overall phase advance. This idea did work and, in fact, the results shown in Figure C.l4 were obtained using it. However, the line THD levels of some 4% were very effectively magnified at the output of this lead circuit--especially the third and fifth harmonic. The resulting output began to look like a stepped wave approxi- mation to a sinusoid. The following low-pass filter did remove a great deal of this distortion with a consequential 221 H2 for S4 Honeywell 1858 Visicorder at 40 in/sec. Figure C.8. 3-level PWM line connected. 222 reduction in the phase advance. This difficulty was over- come by replacing this design by a two- stage lag plus inversion of the line 60 Hz reference signal. This amounts to a tradeoff between distortion and time. By introducing in excess of 90° of phase lag to the line reference signal, nearly one half of a 60 Hz cycle has gone by (no time is lost because of the 180° inversion). The resulting phase lead circuit is drawn in Figure C.9. The signal labeled H2 is the blanked PWM existence function for switch S4 and is representative of this technique. The line reference is V1(t) at the output of the potential transformer and the lower trace Vs(t) shows the ripple produced on the defined source Vs’ The traces for currents id(t) and il(t) were obtained using wideband torodial current transformers (CT) in the appropriate leads of Figure Ck4. Notice the resemblance between current iL(t) and that for the V81 line commutated converter in Appendix B. The operation is similar. For d-c supply voltage vs greater than the a-c peak, Vm current flows over the full half cycle. The bathtub shape of this current is due to the large potential across the transformer leakage inductance at the line voltage \wt) zero crossings. This illustrates a disadvantage of the 3-level PWM inverter in a utility connected application. The method can be expected to produce similar waveshapes in a motor drive application due to the counter emf of the motor. By operating the PWM inverter at higher frequencies the integrating action of 223 Pfisohfio uaoH omasm .m.o ohdwfih moa<filn nD Anvnu was Anvma nmesmme 2: J :2 onaozsm moHsmo mmmmzéa xwm 224 transformer magnetics would greatly enhance filtering out the 60 Hz component. 1 The remaining experimentation in this research was performed using 2-level PWM1and the results are given in Chapter 4. When using this technique phase lead was provided in digitally encoded steps. Figure (L9 is the circuit used for 15 step (2.9°/Bit) control. The phase advance circuit of Figure (L9 generates the phase angle by which the fundamental component of the PWM waveform leads the line voltage in addition to compensating for internal signal processing delays of the controller. Amplifer ARl buffers the output and increases the voltage level of the RC 90° lag network. The potential transformer polarity is chosen to give a net 180° phase shift to V (t). Amplifiers AR2 and AR3, in conjunction with high speed bidirectional transmission gates 01 and 02, form a binary stepped phase lag circuit. Transfer function G2(s) consists of a 24 step phase lag followed by a complementary gain equalization stage. In applications requiring variable modulation depth the gain of amplifier AR4 can be made adjustable. Amplifier ARS is a unity gain current driver. The regulator 04 biases the substrate of gates 01 and 02 below the maximum negative signal swing to be encountered. The K K . 1 K 61(5) = 1:3?I-= 1;-; where K1 = /T1 and le >> 1 _ "KN 'K2 K2 , _ 4 62(S)-(Wl; TN—‘Fyl-q- ,N-1,2,...,2 225 (33(5) = K3 (C.6) K1K2K3 C(S) = GIGZGS(S) = STT:S?;T LG(jw) = -n/2 - tan-1 wTN LG(jw) — -3n/2 - tan (DIN including PT polarity argument of G(jII) shows that the argument of the overall transfer function lies between -”72 and -2’fl’ radians in N— steps. In this way the necessary phase advance for VSI converter operation has been achieved. Furthermore, this advance angle is now under digital control. The cascade converter described in Chapter 5 can be described as a R-I-W technique where the basic power conditioning techniques [3] are R - regulate, I - inversion, and W - waveshape. The R-I-W topology is chosen so that regulation of the random source is followed by the inversion and waveshape function. The circuits used to reallize this regulation function comprise a closed loop system in which feedback controls the duty ratio D of a pulse modulator. Various feedback schemes have been evaluated in order to assess the converter response. Both oscillograph and chart recorder plots of the time response of duty ratio D have been obtained in the laboratory using electronic encoding of duty ratio. 'This encoding was performed digitally so that the lag present, had analog techniques been applied, could be avoided. These circuits are shown in the figures below. 226 Figure C.10 is a detailed version of Figure 5.4 for the input regulator. In this Figure R5 is used to set the steady state duty ratio D which, in turn, controls vs. V , L FRD j>1 j ‘ _._..._"’3 11° m1 cé f g; , ,,_JMA,__. To 118$ R2 R5 +517 ARl - 4—‘§2 ' - ve "—1 #35 To ‘1 + ‘ ? Encoder "‘ AR} 1 C4 vREF 3R7 Fig.0.ll AR2 I Figure C.10. Regulator control circuit. Automatic voltage control of V8 for reactive voltampere adjustment would constitute another control loop in which R5 is replaced with an element controlled by the a-c line voltage. This can also be accomplished digitally. Amplifier ARl is the main switch driver which is similar to the circuit of Figure C.6a. Amplifier AR3 is the feedback error amplifier and AR2 the'pulse modulator. Resistors R8 and R9 are connected to the emitters of the Wilson active load on the input circuit of comparator AR2. By sampling the driver switching signal, about 200 mv of hysteresis can be obtained. In this manner, the pulse modulator performs 227 clean switching at the intersections of the error signal Vé (t) and the internally generated ramp function Vrmp(tL. The effective feedback gain can be found by analysis of Figure Chlo. A fraction of the defined output voltage V8 is available at the error amplifier AR2 inverting input as avg. At the noninverting terminal, a preset reference voltage level is present for comparison with ave. Thus, the error amplifier transfer function Ga(s) can be determined. ve = -Ka(aVS) + (1+KaWREF (C.7) where a 2 0 and K = R2/R3 a A f = - - A 7 \ + V aKaVS akaVs + (1+Ké) V e e REF (C.8) Taking the small signal component of equation C.8 A V Gas) = 6795(5) = -aKa The effective feedback gain can now be derived as He(S) = “1163(5) = -al(algn (C.9) The circuit used to digitally encode the duty ratio D is shown in Figure C.ll. In this circuit, a high frequency clock signal is gated into an eight stage counter U3. The gating signal is a buffered and inverted replica of d(t) shown in figure C.10. During the low portion of this signal DT8,.the gate IC 02 is enabled. This permits clock pulses buffered by UlB to enter the clock input of counter 03. The clock itself is a CMOS inverter biased into its linear J [3. 579MHz 701 8 Bits Figure C.ll. Duty ratio encoder, resolution 263 ns. region by resistor R1 (to VDD/Z). Resistor R2 limits over- drive of UlA and in this circuit must be less than 22 K so that the Barkhausen condition can be met. At the end of the interval DTs the negative slope of the pulse on Qlls collec- tor triggers a monostable multivibrator U4. The Q output of this IC gates the output of the counter 03 through a series of AND gates U5 into an R-S tristate latch UG. At the completion of the prescribed switching interval T8, the pedestal on Vrm (t) Figure CLlO is routed through level P . shift transistor 02 into the reset pin of U3. In this way, 229 the counter is always cleared prior to the start of the following interval. The previous count remains latched into U6 where it is available on the 8 bit bus for asynchronous decoding using a digital to analog converter (DAC) and buffered for input to a recorder. At the clock frequency given, the resolution of 263 ns is sufficient for 8 bit encoding of the complete interval Ts. T . 28 x 263 x 10'9 - 67’15. Using this circuit in conjunction with the closed loop regulator allows an assessment of the dynamics present in duty ratio to changes in load. Figure C.12a shows the encoded duty ratio of Figure C.10. In Figure C.12b and c the response to a step change in load is shown. Here, the change in damping is apparent as D is increased. For stable closed loop operation, the zeros of the return difference 1 + GdHe(s) must have negative real parts. 1+G H (s) = 52+ ZCw +aK X1/ 8 + w z-aK whz X ' 0 d.e n agn C n afin_fi’ 2 " (C.10) In equation C.10 zeta and omega n are parameters of the power stage. Parameter a is the fraction of the output voltage such that aVB s 2.5 volts. Km is the pulse modula- tor gain in units of per volt. By the Hurwitz criteria, chn + axagn Xl/C > o (C.11a) 230 Trace of D + d(t) for gain only case. D = .4 ' V = 25V, Ka = 25, a = .1 - W ‘——_— -. .— ....- , "7L - H..-“ 4 _.._, .. - .. - .- l v .. -_ ,_. l .V - _ ~ - t- - A- -. _. ’k'f . Fe,” 1 ) ,. '. ‘0‘. I .... I) I I .- - F- _ _ - - . _.. . -. . -_- -- . -2. ,.. .._ -N L. . . .--- _ . ._-. -.-_ . ._ .._.- ,_ . . . - ,- -- -_.--- .-, -. -_. .5 W“. __ - . , , -, - m ___-_-_ -_,__.__._ - . _- a W.“ m. - - _-... --_..- ____l.------___-_-_ ___-, I . \ , _ x - V . I 1 ,. I I o 1' . u 0 n D I I a I 9 I 1 I L I I 9 1 If ','.‘. 4 I ... _ . .' a-~..————»+—A——. ,._,‘,. _-.+-_ - Ib‘h‘fn-fi'mfl V... ,I . -. . 1 1 . I In I I O 4 a $4 I I 1 . 1 I ll} 1.- a. .o I t .I i I Q I I 5 l I I l I 11 1 1 4 . .. __... ‘_ 0 —~ .- .¢..--..-_.-._..._.---,. ..... _.... ,._.._‘..._. 7--~-J._.-v._.r--.1-.._r-.-r_.1-~ 7, ,...--.._. ._.. "1- we _1 Bi-.. .._.l .._. ' _L L l I ”‘71-...u“. N_-- -H...1. i . . . Li--‘ I‘-- at,“ C) D.= .6 Vs 37.5V RL = 23,w,23 100 mm/sec ""t Figure C.12. Duty ratio d(t) step response. 231 2 (LIZ - n . wn aKaKm /D,X2 > 0 (C 11b) Equation C.11a is always satisfied. However equation C.llb implies that the error amplifier gain Ra is constrained to D) K < . , a 3&9? This means that error amplifier gain must be lowered as larger boost ratios are attempted. Figure C.13 illustrates -_....--._ . --4_44_..~..._ -_.¢-. -W— _- —._.-o L _".:t“_"‘.' .... I ‘IJ . i . . I‘ITIHIqIETf‘faaar‘,*tqf.rrrnrfarfff*rr.nrtrfrtnr‘ao.,,, XLSVLFU.Vt1‘IV*U$V$IVV‘I tvivut l I ........................ HA M... ..........-_._ <——t .2V/mm, lOOmm/s fosc=33Hz Figure C.13. Limit cycle in d(t) for excessive gain. the limit cycle behavior of d(t) when equation Chllb is not satisfied. A look at the pole migration for the regulator is shown in Figure C.14a and b. The non-minimum phase nature of 66(5) causes instability problems. The proximity of the open loop poles to the imaginary axis requires Ka to be small. As shown in Figure C.14b, an error amplifier with lag-lead compensation maintains the conjugate poles in the 232 / S-PLANE X _ S-PLAN'E \\ # f a) Gain only b) Lag—Lead compensation R2 31 «Haw—4}— avs A‘A'A' >- :e vREF — + c) Circuit Figure C.14. Error amplifier with compensation. in v LHP. The lag pole, however, is now free to cross into the RHP. A circuit to realize this lag-lead function is shown in Figure C.14c. Its transfer function is: \7 1 j (S) = -8 R2123 . s + /T2 \7 mm 3W T (C.12) s P where q; I C132 < 75 - Cl (R2+R3). Investigation of the return difference for this feed- back scheme shows that the characteristic polynomial is cubic. The necessary stability conditions are: 1 , X1 n T > O P w 2 ““2 X2 12st Tp D’TZ aKmKa > 0 Ka = W This last inequality requires that the error amplifier gain satisfy ‘1’ , '1' , 2 D Z (C 13) K < — , = __ K o 3 TP aNnXZ) Tp a Tests using this feedback scheme again produced limit cycle behavior. This behavior is intuitive since the regulator is essentially a gain element with gain always greater than one. Therefore, additional loop gain in the form of error amplifier gain will only aggravate the situation. The conclusion is that low gains are needed. With a random input to the regulator its output will also exhibit fluctuations. The lack of regulator performance using these methods forced a complete revision of the control structure. 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