LIBRARY Michigan State University This is to certify that the thesis entitled SYNCHRONIZATION OF MULTIPLE CLOCKS IN AN SOC presented by STEPHEN ALLEN ZIEL has been accepted towards fulfillment of the requirements for the MS. degree in Electrical and Computer Engineering M Major Professor’s Signature MN! 3 ) . 7,0 137 I I r Date MSU is an afiinnative-action, equal-opportunity employer I i PLACE IN RETURN BOX to remove this checkout from your record. ' TO AVOID FINES return on or before date due. MAY BE RECALLED with earlier due date if requested. DATE DUE DATE DUE DATE DUE 6/07 p:ICIRC/DateDue.indd-p.1 SYNCHRONIZATION OF MULTIPLE CLOCKS IN AN soc By Stephen Allen Ziel A THESIS Submitted To Michigan State University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE Department of Electrical and Computer Engineering 2007 ABSTRACT SYNCHRONIZATION OF MULTIPLE CLOCKS IN AN SOC By Stephen Allen Ziel There are many applications where the driving signals are oscillatory in nature. An example includes modem digital systems, where a clock signal is used as a timing reference for each digital component. In this case, this reference is sometimes fed into several modules within the overall circuit, with each module using its’ own clock signal. Therefore, the accuracy of the incoming oscillatory (clock) signal is crucial to the correct functionality of the overall chip. Another example is in modem RF designs, where multiple oscillatory signals are fed into the RF circuit for signal processing and analysis. At such high frequencies, wire resistance is beginning to cause enough delay such that different components are operating at different times when they should be operating together. This thesis presents an architecture and method of synchronizing these oscillations, where in both digital and (especially) RF systems unsynchronized components can cause faults, which may lead to failure of the chip. This design includes Digitally Controlled Oscillators (DCO’s) coupled via vector multipliers implemented by (analog) CMOS Gilbert Multipliers. It is scalable to any large number of nodes, the only constraint being the chip area itself, as well as finer feature size technologies. To my parents. iii ACKNOWLEDGEMENTS First and foremost, I would like to thank my friends and family that have been there for me during my time in Graduate school. While the time commitment in Graduate school is certainly heavy, their unwavering support during this time has never ceased. Particularly in my family, my Parents and Grandparents have all been especially there for guidance and support while working on this and other projects, and I appreciate their thoughtfulness very much. Next, I would like to thank Dr. Gregory Wierzba for all of the questions he has answered throughout the years with regards to any circuit structure I have come up with. The insight he has provided has been priceless. I would also like to acknowledge the help of Mr. Pete Semig while working on this and my other projects. His help in pointing me in the right direction within several problems I encountered while trying to complete my thesis work proved to be invaluable. Finally, I would also like to thank my committee members, Dr. Shantanu Chakrabartty and Dr. Donnie Reinhard, as their helpful comments regarding my thesis work have been invaluable. Last but not least, I would like to thank Dr. Fathi Salem for allowing me to work with him and his team even before I entered Graduate school. Without the real world experience I gained while working with him, as well as the advice and direction he provided me in my studies and thesis work, I could not have accomplished this work and gotten where I am today. iv TABLE OF CONTENTS LIST OF TABLES .............................................................................................. vii LIST OF FIGURES ............................................................................................ viii CHAPTER 1 INTRODUCTION AND BACKGROUND .................................... 1 1 .1 Digital Systems ........................................................................... 1 1.2 RF Systems ................................................................................ 2 1.3 Other Work Related to this Thesis .............................................. 4 1.4 Goal and Organization of this Thesis .......................................... 4 CHAPTER 2 THE ENTIRE CIRCUIT ............................................................... 7 CHAPTER 3 THE INDIVIDUAL COMPONENTS .......................................... 10 3.1 Gilbert Multiplier ........................................................................ 10 3.2 Current-to-Voltage Converter .................................................... 13 3.3 Low Pass Filter ......................................................................... 16 3.4 Digitally Controlled Oscillator...................................... .............. 19 3.4.1 Negative Resistance Approach ............................................. 19 3.4.2 Negative Resistance from Cross-Coupled MOSFET’s .......... 23 3.4.3 Designing a MOSFET-based Oscillator ................................. 24 3.4.4 Additional Calculations .......................................................... 25 3.4.5 On-Chip Inductor Using ASITIC ............................................. 27 3.4.6 Simulation Results ................................................................. 28 3.5 Digital Varactors ....................................................................... 29 3.5.1 Theory ................................................................................... 29 3.6 DCO vs. VCO ........................................................................... 30 3.7 . High Pass Filter ........................................................................ 34 3.7.1 Circuit Derivation ................................................................... 34 CHAPTER 4 . OTHER ON-CHIP COMPONENTS .......................................... 38 4.1 3V — 2V Converter .................................................................... 38 4.2 3 - 8 MUX ................................................................................. 39 4.3 Transconductance Amplifier ..................................................... 40 CHAPTER 5 Final Circuit Simulation Results ............................................ 42 CHAPTER 6 Fabricated Circuit and Test Results ...................................... 48 6.1 Gilbert Multiplier ........................................................................ 48 6.2 3V-2V Converter ....................................................................... 49 6.3 Digitally Controlled Oscillator .................................................... 49 CHAPTER 7 Future Considerations ............................................................ 55 7.1 Gilbert Multiplier ........................................................................ 55 7.2 Low Pass Filter ......................................................................... 56 7.3 DCO .......................................................................................... 56 7.4 High Pass Filter ........................................................................ 56 APPENDICES .................................................................................................. 58 BIBLIOGRAPHY ................................................................................................ 77 vi LIST OF TABLES Table 3.1-1: Parameters for the Modified Gilbert Multiplier ................................ 10 Table 4.2-1: 3-8 Decoder Truth Table ................................................................ 40 Table 4.3-1: Transistor Sizes for the Transconductance Amplifier ..................... 41 vii LIST OF FIGURES Figure 1-1: A Digital System Example Showing Time Delay ................................ 2 Figure 1-2: Basic PLL Topology Showing Multiplication of Two Oscillators .......... 3 Figure 2-1: The block diagram of the finished circuit ............................................ 9 Figure 3-1: The Modified Gilbert Multiplier Schematic ........................................ 12 Figure 3-2: The Current-to—Voltage Converter Schematic .................................. 13 Figure 3-3: The Gilbert Multiplier Simulation Results .......................................... 15 Figure 3-4: Typical second order LPF ................................................................ 16 Figure 3-5: Simulated LPF Bode Plot ................................................................. 18 Figure 3-6: DCO architecture and equivalent circuit structure for analysis ......... 19 Figure 3-7: Typical Negative Resistance Oscillator ............................................ 20 Figure 3-8: Equivalent Parallel Resistance Due to the Negative Resistance ...... 22 Figure 3-9: Negative Resistance Schematic ....................................................... 23 Figure 3-10: Large signal analysis of the DCO ................................................... 26 Figure 3-11: Two Port Model from ASITIC ......................................................... 27 Figure 3-12: Simulation Data Showing the DCO Oscillates at ~1.7GHz ............. 28 Figure 3-13: Typical Capacitor Symbol ............. . ................................................. 29 Figure 3-14: PMOS Digital Varactor Schematic .................................................. 29 Figure 3-15: Small Signal Model for a PMOSFET .............................................. 30 Figure 3-16: Voltage vs. Capacitance Characteristics for the PMOSF ET ........... 31 Figure 3-17: MOSFET Varactor Capacitance Values ......................................... 32 Figure 3-18: The High Pass Circuit or Differentiator ........................................... 34 Figure 3-19: PSpice code used for simulating the differentiator ......................... 35 Figure 3.20: PSpice simulation of the differentiator circuit .................................. 37 Figure 4-1: 3V - 2V Converter with Buffer ........................................................... 38 Figure 4-2: Implementation of the Decoder, Converter, and Varactor Bank. ...... 40 Figure 4-3: Transconductance Amplifier Schematic ........................................... 41 Figure 5-1: Original Concept Circuit without the HPF ......................................... 44 Figure 5-2: Simulation corresponding to VBMS = 3V for original concept circuit. .45 viii Figure 5-3: Figure 5-4: Figure 6-1: Figure 6-2: Figure 6-3: Figure 6-4: Figure 6-5: Figure 6-6: Figure 8-1: Figure B-2: Figure F-1: Figure G-1: Original concept circuit simulation (VBIAS = 1.5V). ............................ 46 Simulation corresponding to VBIAS = 3V and identical input phases. 47 The gathered data from the fabricated test circuit. ........................... 48 3V - 2V Converter Fabricated Results .............................................. 49 The Fabricated DCO Results ........................................................... 50 Simulation Results of analogLib Inductor, with 5M ohm Resistance. 51 Simulation of Figure 1 using the NCSU_Anang_Parts Inductor ...... 53 Simulated DCO with Increased Widths Showing Oscillation. ........... 54 Final Circuitry Floor plan .................................................................. 65 Final Circuitry Layout ....................................................................... 66 MOSIS Pin Diagram ......................................................................... 74 26nH On-Chip Inductor Including Orthogonal Poly-Planes .............. 76 ix CHAPTER 1 INTRODUCTION AND BACKGROUND As circuits and systems become more complicated with each generation of technology, and as the efficiency of each successive device improves’ upon the previous device, more and more components are beginning to operate on multiple oscillators or clock signals. Modern examples abound in these areas: 1. 1 Digital Systems Digital systems often feed the same clock signal throughout its circuitry to synchronize components in a circuit. That is, there may be multiple blocks or modules on a chip, with each of these requiring a clock input for control. Thus, in these systems there may exist multiple oscillators, all depending upon an original clock signal that should be as accurate as possible. Furthermore, each generation of technology allows a decrease in size of circuit components, however as sizes of components shrink, each piece of the chip can operate at higher frequencies. In deep submicron technologies, this can become a problem because in these high frequencies, the wire itself is often the time limiting factor (see fig. 1-1). That is, for these small sizes, the time delay that a wire introduces can cause two components on opposite sides of the chip to function at different fractions of time, eventually leading to faults. ln worse case scenarios, these faults can lead to chip failure. It is therefore very important that clock synchronization occur in digital systems, especially when these systems reach the deep submicron technology levels. Digital Digital System A System B L Clock Signal sin(wt) sin(wt + .9) sin(wt) (9 , Figure 1-1: A Digital System Example Showing Time Delay In modern digital system design, this flaw has been recognized and digital synchronizers have been developed to resolve the clock delay problem. [See 18]. These digital synchronizers consist of pass transmission gates that send a digital signal to a latch, which will hold the correct value until it is needed at the output. Unfortunately, as [18] demonstrates, building a perfect synchronizer in this way is impossible! The goal of the circuit designer, therefore, should be to minimize the failure of the component as best as possible. 1.2 RF Systems In RF systems, phase locked Ioop’s (PLL’s) are used to lock two frequencies together, usually an incoming frequency and a local oscillator, or base frequency. In these cases the most basic PLL consists of 3 Gilbert Multiplier, a filter, and some type of controlled oscillator [9] (see fig. 1-2). Traditionally the oscillator has been voltage controlled, which gives rise to the name Voltage Controlled Oscillator (VCO). The type of frequency conversion depends on the mixer (or multiplier), and filter used — a low pass filter will pass the down-converted signal at the lower frequencies, where it is easier to process the signal (usually used in frequency receivers). A high pass filter will pass the up-converted signal at the higher frequencies, where it is normally sent out of the system through an antenna (usually used in frequency transmitters). k>< D <: )VOUT TVLO Figure 1-2: Basic PLL Topology Showing Multiplication of Two Oscillators Recently, efforts have been made to digitize this entire building block [see 11 — 14] in order to reduce analog subcircuits that prevent the designers from taking full advantage of the deep submicron technologies. As just one example, the analog VCO has been replaced with a digital DCO. This has been accomplished by taking advantage of a MOSFET’s internal capacitance and controlling it digitally with a control voltage at the gate input. Therefore, as the gate voltage changes digitally, the capacitance of the device also changes, such that the overall frequency of the oscillator can be controlled in a digital manner. This allows the oscillator to take full advantage of the advanced technologies (again usually geared towards digital design). 1.3 Other Work Related to this Thesis Others have approached oscillator synchronization in a different fashion than that which is described here. For instance, in [17], the authors have shown that synchronization can be achieved through implementing first and second harmonic coupling. They achieve amplitude stabilization — a feature they show to be similar to synchronization - by use of cross-coupled MOSFET’s, which also provides the first harmonic coupling. The second harmonic coupling is achieved through use of a narrow band passive circuit. The end result is an LC oscillator with good quadrature outputs. See [17] for further results. 1.4 Goal and Organization of this Thesis This thesis addresses CMOS implementation of an architecture that improves upon the Digital System section by allowing phase synchronization among multiple oscillators. It also improves upon the RF System section by allowing any number of oscillators, rather than only two as in a PLL, to be synchronized together (again, in phase). Finally, it again improves upon the structure devised in [17], in that many oscillators can be synchronized with each other as opposed to only two. As such, the motivation of this thesis is to provide an architecture which will synchronize any number of oscillators in phase, thereby solving the problems (or improving upon the efficiency) of those given in this introduction. The rest of the thesis is divided as follows: first, chapter two gives a general explanation of how each component in the overall circuit interacts with the other components surrounding it. The modeled equation used for this work is given, along with a brief explanation of it and its parameters. The relationship between the mathematical equation and the overall circuit topology is given as well, tying together what we expect to see in the fabricated results with the given equation. Chapter three gives a full explanation of each individual component in the overall circuit topology. This includes circuit structure, usually aided with extensive circuit analysis, simulations and explanations of simulation results obtained. In some cases, Spice or SKILL programming code is also given, where necessary to aid understanding. Chapter four includes additional circuits used in the final fabricated chip, including proper reasoning behind each subcircuit. When necessary, correct circuit analysis and simulations with explanations are given to aid in understanding. Chapter five gives the final circuit simulations, with full explanations, to several different input possibilities. These different possibilities depend on Gilbert Multiplier biasing, as well as initial phase conditions on the input sinusoidal voltages. Output graphs are obtained - each extensively simulated using the Cadence design tools and plotted with MATLAB, providing 250,000 data points for complete analysis. Chapter six provides the final fabricated circuit results, including test circuits. These test circuits were fabricated to check individual circuit components (LE. Gilbert Multiplier, DCO, LPF, etc) with the simulated results. Screen shots from an oscilloscope are also provided, when needed. Chapter seven provides future considerations for several subcircuits, based upon the observed weaknesses of the current final circuit structure. Using these considerations as guides for future renditions of this chip will enable projects descending from this thesis to greatly outperform the current work presented. References are given when needed, to help provide the reader with background material to a topic external to the main focus of this thesis. Finally, the thesis ends with an appendix which provides material not immediately necessary for understanding of this work, as well as a bibliography, for further references and personal study. CHAPTER 2 THE ENTIRE CIRCUIT The fabricated circuit block diagram can be seen in figure 2-1. Each of these blocks will be discussed further in subsequent chapters and sections. The idea of this circuit is to synchronize three oscillators — again, possibly the same clock used in many locations on chip that has become out of synch with itself. In practice, this concept can be applied to as many oscillators as allowable by area constraints. A mathematical model of this circuit can be shown from [1] to be: . . a j=n Hi—wi=¢i=bi-fi zzwij'005(6i_6j) (1) i j¢i Where 6,- are the phases and a),- are the oscillators’ frequencies. This model is a gradient ascent system with the term within the square brackets considered to be a potential energy function. It is the model that we are trying to replicate, as shown in figure 2-1. In this equation, bi is a strength value (due to biasing), Wij is coupling strength, and the term in the parenthesis is the total coupling of phase differences. We synchronize these oscillators as follows: As the circuit diagram shows, the signals begin by being fed either directly, or through feedback, into the modified Gilbert Multipliers. As each signal is multiplied together, current mirrors provide complementary current outputs to a current-to-voltage converter, which acts as current summation and multiplication. Due to the multiplying of these signals by one another, noise and other unwanted signals are generated, which is partially filtered out at high frequencies by use of a simple second-order low pass filter. This low pass filter also passes the down converted component of the signal that we wish to process for this circuit. The processed signal is then fed as a voltage into a digitally controlled oscillator (DCO), which functions similarly to a voltage controlled oscillator (VCO). As the DCO adjusts to the incoming signal, feedback from the other two outputs (V2 and V3 for the case of V1) further adjust these same properties until each of the three oscillators is in synch with each other. Thus, this circuit is able to perform phase locking among any number of sinusoidal waves, in this case three separate oscillators. “Soto 0335» .2: ho Ewan? x003 och ”TN 239“. m> m> m> N fl 5 X E X N E5 _ ODD CHAPTER 3 THE INDIVIDUAL COMPONENTS 3. 1 Gilbert Multiplier The parameters in table 3.1-1 correspond to the transistors in figures 3—1 and 3-2, respectively. Within the first stage of the modified Gilbert Multiplier, all of the parameters have been sized with respect to a length of 1.5um. The second stage, or the current-to-voltage converter stage, takes the difference between the two currents by feeding each output of the first stage into a leg of one current mirror with a 1:1 ratio. That is, in this stage there should not be any current amplification. Any difference between the currents will be detected through the extra connection to the MOSFET resistors, M31 and M32, which will either sink or source the current depending upon the mismatch present. Transistor (W/L) ratio Transistor (W/L) ratio M1 3.0u/1.5u M11 1511/1511 M2 3.0u/1.5u M12 1511/ 1.5;; M3 5.4g/ 1.5g M13 1.5u/1.5u M4 5.4u/1.5u M14 1.5u/1.5u M5 5.4u/ 1.511 M15 1.5u/1.5u M6 5.4u/ 1.5]; M21 2.7u / 3.45j1 M7 5.4u/ 1.5g M22 2.7u/3.45u M8 5.4p/1.5u M31 1.59/45]; M9 5.4u/ 1.5]; M32 1.5u/4.5u M10 5.4p/ 1.5u Table 3.1-1: Parameters for the Modified Gilbert Multiplier 10 It should be important to note that we have four degrees of freedom (d.f.) per modified Gilbert Multiplier. V2 and V4 have both been connected to 1.5V in this work so that VD% acts as a virtual ground. This configuration allows us to generate a four-quadrant multiplier, which allows the input voltage to oscillate around 1.5 V DC. 11 2522.8 3.35:: :35 .8535. 2: "F...” 2:9". :2 22 22 T 2sz :2 m<_m> a . +1 12 3.2 Current-to- Voltage Converter VDD M21 b——C1 EMZZ I+ M31 1- Vow M32 Figure 3-2: The Current-to—Voltage Converter Schematic It can be seen from the schematic in figure 3-2 that the current mirror acts as current subtraction with IOUT = I+ — I-. IOUT is then fed into active resistors, composed of PMOSFET’s, which produce Vour at the output. The circuit analysis for the active resistors is relatively simple. Due to the source-gate voltage of the PMOS transistors being equivalent to the drain-source voltage, v 1 ID =9mVDs => 03 = (2) ID 9m 13 The result in equation (2) shows that these active resistors have a resistance of —1—, where gm is determined largely by device sizes and the large signal drain 9m current (see equation (34)). The output voltage of the current-to-voltage converter block, simulated in Cadence for multiple values of V1 and V3, can be seen in figure 3-3. VBMS was kept to 1.5 V in these simulations, or VD% . Notice the relatively smooth linear region. This is where we want to operate during (analog) voltage multiplication, and also when we use the multiplier as a phase locking mechanism. 14 e e 00 e 0? 3:50”. cow—2:55 3:323: ton—5 on... "a-” 2:2". F> %%s%%%%e%%%%e%%%% n> .2, w> a0 .0 0 01% 0.0 AA» AV. 0 15 3.3 Low Pass Filter The low pass filter is a crucial component of the overall design due to need to filter out the unwanted spurs resulting from the Gilbert multipliers. These unwanted frequencies can be mathematically stated below, using a common trigonometric property. (Acosamxmcoswzt»="7B-(cos(w1 -w2)t + cosiwi + an (3) Therefore, when mixing two signals together, we will return a low frequency and high frequency component in our output. The low pass filter circuit used to filter out these unwanted (high) frequencies can be seen in figure 3-4 along with the appropriate circuit analysis. Figure 3-4: Typical second order LPF Using Kirchhoff’s laws, we obtain the following equations. 1 —V l R I —l — = O 4 IN + 1 +(1 2) SC ( ) (12—11)i+/2R+12—1—=o (5) SC SC Putting I1 and I2 into matrix form yields: , 1 1 _ R +— —— — VIN = so so ’1 (6) 0 _1_ _(_2_ + R] 12 _ SC SC _ 16 Solving for I2 yields: 1 R+— V SC IN _1- o _.\_/LN_ '" 18C 1 ‘= 2R 301 R (7) R+— —— __ 2 SC SC [SC+R +82C2+SCJ 1 2 — ———+R SC [SC ]_ After rearranging and solving for VOUT in terms of VlN, we get: VIN (8) (sore)2 + S(3CR)+1 VOUT = Simulating this circuit using Cadence and setting R=5OOQ, C=100fF yields the bode plot on the next page. This bode plot closely matches the expected results, with the -3dB roll off point at 1.2 GHz. This is more than adequate enough for our circuit, as the highest frequency we want to keep will have a bandwidth of f1—f2 = 300 MHz, according to simulations. 17 Magnitude vs. Phase Response i 5 ll I g, I ii i i i I :l s 1‘ I a? ‘ i II 1 I i I l l ii i I; i It I , II I; i i i: i I I: I : 1‘ I ll .L I I ill 1' III. . ITT ooooooooo ooooooooooo v-NCOVI'LOCDNQD o NV ooomvcooo Illll ,— IIIIFPFFF I I II (ap) epmlufiew (SOOJDOD) eseud' 18 I H3939 I H3178? 0 H3996 0 H3207 0 ”EVIL 60+3 I171 60+39 I'S 609981 8043919 80+397'Z 80+390'L LO‘BLV'V 1.0+3 I6'l 90+38 I'B 90+3LV'8 90+387'I 9051 I99 90+369'Z 90"391' I 70+306'I7 70+360'Z €0+El I6'8 €0+308'€ €O+389' L 8' l69 1'968 6'93l [89 1688 0 Frequency (Hz) Figure 3-5: Simulated LPF Bode Plot 3.4 Digitally Controlled Oscillator 3.4.1 Negative Resistance Approach VDD T I Mlb—l M2 ’ 7H m u/vj $ MED —] E)M4 _I_ Figure 3-6: DCO architecture and equivalent circuit structure for analysis The analysis of the DCO circuit is very similar to traditional voltage controlled oscillators. Above is a schematic of a typical VCO circuit which mirrors a DCO. ‘ygm —’\/\/\r— C IV /l | L M —’\/\/\r—' _y gm —’\/\/\/— _%gm As in a VCO, the DCO can be thought of as an RLC oscillator circuit. The purpose of the negative resistance is to eliminate the parasitic resistance presented by the non-ideal inductor and capacitance. This is necessary because according to the Van der Pol equations, oscillation occurs if these resistances cancel each other out. That is, the following analysis holds for the circuit in figure 3-7: 19 RP: LE 0:]: 1'1 1R 1}. j - Figure 3-7: Typical Negative Resistance Oscillator Using normal circuit theory, iL+ic+iR+i—=0 (9) dt dt L __ de de_Cd2v I—— 1 1 dt dt dt2 ( ) di iR=_Y__:> RP = 1 E! (12) Rp dt Rp dt diL +dIC + diRp +fl= o (13) dt dt dt dt Substituting equations (1 O) — (12) into (13) yields: 2 . [vi]+ cu + _1_.d_v +fl=0 (14) Finally, we need to solve for the negative resistance component. Van der pol [16] solved this equation with the aid of power series, as follows. Let, x2 x4 v—=v(x)=cos(x)=1——2!—+-I-- (15) Here, Van der pol approximates the power series by rounding down to the first two expressions after the DC component. The DC constant is dropped because there is no DC offset with pure AC signals. Then, 20 3 I— = I(x) = %V(x) = —sin(x) = —x + %— (16) Finally, the ‘x’ is replaced with a voltage ‘v’. Re-evaluating yields: /— = —v + — (17) Solving for%, the missing component in equation (14) above, yields: flzflflpzfl fl[-a1v+a3v3] =fl[_a1+a3v2] (18) dt dt dv dt dv dt Notice that when v = 0 in this equation, — a1 = —7?-1—-, which is where the negative n resistance comes from. Therefore, VL d2v 1 dv dv 3 [—]+ C—— + —— +|:—(—a1v+a3v ”=0 (19) -v—L- +[CSZ]+ —1-S +[S(—a1v+a3v3)] =0 (20) L Rp [034(3)] + H— a1V(s)+ 33V(s)3 + EFVIS))i + [$99] = o (21) V(s) in these equations is the startup voltage. Originally, V(s) is very small, and we can approximate equation (21) by: [cszv(s)] + H- a1V(s)+ #Wsfl] + [LES—l] = o (22) 2032+s[—a1+%]+%=0 (23) 21 3324.3 _—’3. +— 0 LC II 0 A N A v We want this system to be undamped, which according to elementary control theory occurs when the middle term drops out, or: 1 ___P = o (25) Therefore, we need to build a system which will cancel out the positive resistance by some expression a1. This value should be as close as possible to the actual positive resistance, as it is impossible to build a system which will perfectly cancel out another parameter. Equation 25 can be shown graphically by dropping the capacitance and showing that the cancellation of conductances is required for oscillation in the parallel circuit formation of figure eight. R fie » R NEGATIVE Figure 3-8: Equivalent Parallel Resistance Due to the Negative Resistance 22 3.4.2 Negative Resistance from Cross-Coupled MOSFET’s The calculation of the negative resistance, shown in figure 36 is found by first inserting a test current across the drain nodes of the NMOS (or PMOS) transistors, as shown in figure 3-9. [test M 1 1|”.I Figure 3-9: Negative Resistance Schematic Then, using elementary circuit analysis, the input impedance can be calculated. V932 = Vds1 Vgs1 = VdsZ ID = Qngs Vtest = V932 — Vgs1 ’test = ’01 - II32 From equations (26) — (28), I test = 9 m IVgs1 — V982) 1 Vtest = —(" I test) 9 m Therefore, 23 (26) (27) (28) (29) (30) (31) (32) V For this work, the MOSFET’s M1, M2, M3 and M4 in the DCO circuit were kept to a minimum length size. Only M1 and M2 were increased in size, to W = 4.5um, from the initial width of W=1 .5um, for electron and hole mobility matching purposes. As in a VCO circuit, the transconductance gm of each MOSFET is determined by both the large signal drain current ID, and the following relationships: WKp -_-2 ——I 34 9m L 2 D I ) KP =%% (35) These equations should be used when designing a negative resistance MOSFET oscillator, as explained in the next section. 3.4.3 Designing a MOSFET-based Oscillator For this work, the design in figure 3-6 was used. To calculate the value for the negative resistance component needed for oscillation, several parameters must be obtained first. In this case, the frequency of operation, inductance of the on- chip inductor, as well as the inductors estimated Q value are all needed to determine the series resistance of L, as given by the equation below [9]: 24 Using ASITIC (see [5]) as a basis for the optimized inductor, the associated parameters reveal that a) = (ZnXZGHz), L = 26nH , and Q s 2. These values lead to a series resistance of R3 = 8189, meaning that the designed negative resistance needs to be RN = —R3 = -—8189. Setting this value equal to equation 33 above, and using equation 34 to find the transconductance yields the design parameters needed to create the cross-coupled MOSFET oscillator. 3.4.4 Additional Calculations Outside of the negative resistance calculations, this information is still useful because it allows the calculation of information such as the Q of the RLC circuit, C ML .37, Since the Q-factor needs to be as high as possible, it is beneficial to find out what where the Q is given by [11] to be: the limiting factors are in an attempt to improve their performance. To calculate a rough estimate of gm, the DC equivalent model is drawn (see figure 3-10) and the following equations can be obtained. ’01 +102 =103 +lo4 (38) VGS3 = VGS4 = V63 (39) VSG1 = V362 = V86 (40) The following analysis is simplified by ignoring any short channel effects that are inevitably present in the DCO MOSFET’s (see [15]), due to the lengths of the transistors being smaller than == 3pm. 25 VDD T + + V503 V504 — Figure 3-10: Large signal analysis of the DCO Notice that the capacitor acts as an open, while the inductor is a short. Also notice that if the PMOS transistors are matched, and likewise the NMOS transistors are matched, then the equations in (38) — (40) hold. Using the last two relationships, it can become clear that all of the transistors are operating in the saturation region, because VGS — VDS and VSG — VSD. The current equations for this region can then be written as: W . /D_NMOS = -L-K (VDs -VTH)2 (41) W . /D__PMOS = TK (VSD - VTH)2 (42) Typically, in silicon the hole mobility is approximately y3 of the electron mobility, assuming we are not operating in deep submicron technology. Therefore, WpMOS has been set to be approximately 3WNM03 in this circuit for matching purposes. Finally, assuming that all of the PMOS and NMOS transistors are very closely matched, we have: 26 VDD = Vsc + V63 (43) v Vsc = Vcs = VDS = Vso = 0% (44) 2 W . v ’D_NMOS =’D_PMOS AflCf-KPMOS (I D%)-VTH) (45) Finally, plugging equation (45) into equation (34) will give us our estimated value of gm from which we can solve for Q, using equation (37). 3.4.5 On-Chip Inductor Using ASITIC The on-chip inductor was designed and optimized using the ASITIC program (see [5]). The particular inductor chosen is a typical square inductor. This inductor was designed to be 26nH, with a size of 270nm by 270nm. According to ASITIC, the Q value is equal to roughly 2. Furthermore, using the PIX command in ASITIC, the following two port model was found: L R O 0 Cl F; F: C2 Figure 3-1 1: Two Port Model from ASITIC The four grounded parameters provided by this program are C1 =C2=0 fF and R1 =R2=1000 T-ohms. Therefore, the two port model can be viewed as a perfect inductor in series with a perfect resistor. In this model, the inductor has a value of 26nH and the resistor has a value of 48.75 ohms. (To model the worse case 27 scenarios, we will assume the resistance is 50 ohms for the remainder of this thesis). For additional protection, orthogonal poly lines were added below the metal layers in the layout to reduce any parasitics that might arise after fabrication. For completeness, the final inductor layout can be seen in figure G-1 in Appendix G. 3.4.6 Simulation Results Simulation results of the DCO (from figure 3—6) in Cadence are shown on the next page, along with a graph giving the frequency range of oscillation offered by this DCO. Due to the inherent difficulties in simulating oscillators for real wortd conditions, a small current (in the nanoampre range) was set as an initial condition through the inductor, which acted as modeling real world noise that typically starts the oscillation in the circuit. Vout- ’\ N o, b- q. h 3.3 .32.; w. .51.» .599 9999 ,;.\ b5 ,9 .3" .5 gee e N 61‘ I\. %. $9 9. Time (s) Figure 3-12: Simulation Data Showing the DCO Oscillates at ~1JGHz. 28 3. 5 Digital Varactors 3.5.1 Theory IIMITIfiB—[m W ii...€i [— M2 f‘_[M4 M6 _%D_NIN+I O I : )VCTR_1 TR_ Vc 2 ( : )VCTR_3 l B : VCTR_N Figure 3-14: Typical Figure 3-13: PMOS Digital Varactor Schematic Capacitor Symbol N Jl wll> F44 1o As shown in figures 3-14 and 3-13, the capacitor in figure seven represents the equivalent capacitance of the digital varactors, which are made up of voltage sources and MOSFET’s. These voltage sources turn ‘on’ or ‘off’ a MOSFET, which alters the C33 of each transistor, and ultimately the entire ‘capacitor' itself. Here, the drain-source-bulk connections are the ‘ends’ of each digitally controlled capacitor we are incorporating into our design. An analysis of this configuration to ensure it is a variable capacitor can be done as follows. Suppose we take the small signal model of a PMOSFET, shown in figure 3-15, and connect it in the fashion described above. Then, CTOTAL = 036 // Cse // 006 = 036 + 086 + 006 (45) 29 Occasionally, in the literature one might find that the drain and source nodes have been connected together, while connecting the bias voltage to the bulk node. This still acts as a varactor, which can be shown as follows: CDG D CD B O II II— eo—II 6811—? Figure 3-15: Small Signal Model for a PMOSFET 1 1 1 CTOTAL = 036 + [I ]+ [ J] (47) . 003 + 033 006 + 036 For the situation in equation (47), CBG is clearly the dominant factor due to the capacitive dividers in the term on the right. However, the range of capacitance associated with equation (46) is typically higher than that of equation (47), which is why this connection scheme was chosen for this work. 3.6 DCO vs. VCO Due to the technological trend of device shrinking in each new generation of components, it is becoming more and more difficult to achieve adequate results using a VCO. This can be easily explained using the typical capacitance vs. voltage graph, shown in figure 3-16. Traditionally, the capacitance of the 30 oscillator was set using the accumulation mode of the graph. This was due to the lower rate of change (slope) of the depletion to accumulation region of the graph, which allowed engineers to be less precise in their control voltage requirements to achieve the desired capacitance output. However, as technologies shrink, the slope of this portion of the graph has increased, making it difficult to achieve the same capacitance requirements (or same resolution) as before. Additionally, VDD also shrinks as technologies advance further, leaving less room for error. Both of these problems have led engineers to begin using digital varactors, which take advantage of the transition region of the depletion to inversion regions, providing a sort of ‘digital capacitance’ programmable by the engineer. CMOS > VG 4—Accumulation—>§-Depletion—><—Inversion—> Figure 3-16: Voltage vs. Capacitance Characteristics for the PMOSFET For this thesis, the capacitance of each varactor was set up to be binary- weighted such that each successive varactor had approximately twice the capacitance of its predecessor. That is, 31 N— CVaractor _ N = 2CVaractor _(N —1) = '" = 2 1CVaractor _1 (43) Each CVaractor term in the above equation represents the various capacitances of the varactors in the chain respectively. In practice, this was accomplished by increasing the ZX— ratio of each PMOSFET linearly, to achieve approximately twice the capacitance for each successive varactor. Therefore, the first varactor, which represents the smallest capacitance available, has a ¥ ratio equal to N —1 one, while the size of the last (eighth) varactor is equal to LIL—fl == 128. The capacitance values found from the simulated varactors are shown in figure 3-17. Notice that when the digital inputs are low, the smallest capacitance is obtained (591.5 fF), and when the digital inputs are high, the largest capacitance is obtained (975.1 fF). Capacitance (fF) 1200 1000 A 800 I 600 ~--"'E"T 400 200 Capacitance (fF) O I I Il‘lIlllI Ilv.;1.,llllill III I -lIIll III IIIIll.l*Ill| IIIII:..=: 'll‘ I‘IIiIl IIII.‘III' nil. 'IIIIIII . I.:‘I‘il|ll| I IIIIuII, ll‘llIlixlflIli‘l' IIHIIIIIIIII O ‘- O ‘- O ‘- O ‘— O ‘- O ‘— O ‘- O \— ‘- O O ‘— s- O O ‘- s— O O s- O O ‘— C) s— V" O ‘— O O v- O ‘— v- O O O ‘- ‘- s- O O ‘— \— ‘- O O O O ‘- O ‘— O \— ‘— O x— O s- s— O ‘- O O \- v- 0 O ‘— O O ‘- ‘— O ‘- ‘— O O O O ‘- ‘- ‘— O O O O \- ‘- ‘- O O O O O O O ‘— F F v- ‘- ‘- ‘— Digital Input (Binary) Figure 3-17: MOSFET Varactor Capacitance Values 32 This range can be extended, when required, by using voltage converters to convert from 0 volts to roughly VTH (corresponding to the valley in figure 3-16), and 3 volts to the value which achieves the highest capacitive value. If this is done, simulations show that the range can be increased to 456.4 fF (or from 519.1 fF to 975.5 fF). Due to the nonlinear increase in capacitance achieved by this method, some have resorted to using methods such as dithering to fine tune their frequency measurements. Texas Instruments, for example, included the DCO on chip with one of their delta-sigma dithering components, which allowed for much higher precision in determining the oscillator frequency. These methods are discussed further in the literature (see [12] - [14] for example), and were not used in this thesis due to time constraints, but could be considered as an option for improvement in future renditions of the chip. 33 3.7 High Pass Filter I—‘-3 + “NED R v... Figure 3-18: The High Pass Circuit or Differentiator The purpose of this stage is to provide a 90° phase shift to the output of each signal, which is designed to make each phase difference converge as close as possible to zero. 3.7.1 Circuit Derivation Using Kirchhoff’s laws, we get: SC(VIN - Vour )8 = Vour (49) (SRO +1)Vour = VIN(SRC) (50) SRC v = v 51 our IN[SRC+1) ( ) Next, separate into the correct bode forms and plot: ’ i 1 Vour =VIN(S)(RC) s 1 (52) i 1 ]+ ( RC 2 1 Where: = — 53 we RC ( ) 34 Notice that there will be a loss from V». to VOUT. This is reflected in the bode plot. Also note from figure 3-20 that it is desirable for Vour << VIN for a perfect 90° phase shift, however VOUT cannot be made too small because we cannot tolerate a significant loss in gain. With the current DCO parameters and configuration, the simulated circuit is operating at about 1.7 GHz. Therefore, by setting the following parameters: R = 1K (54) c = 8f (55) RC = 8p (56) RC" = 125G (57) We should expect that: non,” = ——1— = (125GXO.159)= 20 GHz (58) RC(27:) The following PSpice code obtains the bode plot on the next page, matching this expectation. DIFFERENTIATOR VS 1 0 AC 1 C1 1 2 BF R1 2 0 1K .AC DEC 120 10 1T .PROBE .END Figure 3-19: PSpice code used for simulating the differentiator Notice the phase shift is still not a perfect 90° as desired, seen in the following graph, but 84° instead. Also notice that the loss in gain will result in an output voltage that is only 1—(1—0 of the output voltage we would expect. These 35 deviations from the ideal high pass filter should be kept in mind when viewingthe results in the output, as they will cause an error which will prevent the results from achieving a perfect 0° phase difference at the output. 36 :32? 55:29:55 9: ho :o_ua_:E_m 339... SN.” 2:9". «0506“ "05.3. H chum hoow .mo Squad _eumo hue—.2695 28>...“ 4 «mac .H ammo." Nmzooa «53 In awn—OH 2.: OH umoa _ (I) 1/ 1C 14 h I n. wvmmfi .Ooo.no~ / / x / r \/ r I: 1Cu 84.: 6.52.8 / \xxx/iL I 1 :L.vm .OoomON _ _ 23>va o 0x m\ 33:- .082: -\ _ . 22a. .0823 / \\I._ . .r _ I./I.\ L n a-.. " /VU\—\ > < A0>fluumv mm; Adv o.hm "ouzunuonfiofi 02.8an h0\m0\vo ":3...— 0.5..mequ MOHKHHZWmHhhHO 37 CHAPTER 4 OTHER ON-CHIP COMPONENTS Several other components were provided on chip for specific operations not related to the proof of concept circuit presented in the block diagram of figure 2-1. This chapter describes these components, their operation, and their simulation results where necessary. 4.1 3V— 2V Converter It was found that while simulating the DCO, a larger range of frequencies was obtained when the control voltage was set at 2V rather than 3V. This was found by completing a FFT simulation in the Cadence Design tools and observing the results. Therefore, an on-chip voltage converter was created to aid in testing and simulating the final chip. The circuit built for this operation is shown below, along with the relevant circuit analysis used to design it. 49’” "CI M1 M2 ——1 M3 M4 M5 M6 V + VIN our Figure 4-1: 3V - 2V Converter with Buffer 38 A buffer was added to this circuit to ensure that the signal entering the converter has a strong voltage (I.E. 3V). Therefore, minimum sizes were used for these transistors to minimize area constraints. That is: W1=W2:W3:W4 zfl:1.5,u (59) L1 L2 L3 L4 L 06,11 A design equation was found (from [11]) to be: 2 fig KP1 _ VDD ’VREF -V702 (60) W2 L1 KP2 VREF - Vss - V701 Where M1 is an NMOS transistor, M2 is a PMOS transistor, and VREF is the desired voltage output. Therefore, 2 flfl—46”=[——3“2"0'8] =27.78). (61) W2 L115,u 2—0—0.8 m-!'l=9.26m (62) W2 I-1 For the circuit in this work, we chose: M1 = Ell = LEE (53) L1 15)) M2 = 52 = 945—41 (64) L2 0.6,u 4.2 3- 8MUX Due to the binary weighted, digital varactors used in this work, decoders were created and inserted on-chip to decrease the amount of pins required to test the “proof of concept” circuit. Through the use of VHDL programming, Cadence was 39 used to create this device layout automatically. For reference, the VHDL code used has been given in Appendix E at the end of this thesis. The truth table in table two shows the implementation of the 3-8 MUX, whose outputs were used as the control voltages for the varactors. 0 0 O 1 O 0 1 0 O O 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 O 0 0 0 1 0 0 0 0 1 0 1 0 0 1 O 0 0 0 0 1 1 0 0 1 O 0 0 0 0 0 1 1 1 1 0 0 O 0 0 0 0 Table 4.2-1: 3-8 Decoder Truth Table A 3V-2V Varactor B Q 7 C 8 Bits Converter 8 Bits Bank Figure 4-2: Implementation of the Decoder, Converter, and Varactor Bank. 4.3 Transconductance Amplifier The need to measure and monitor the activity of internal nodes in the overall circuit, combined with the desire to leave the circuitry unaffected by outside interferences such as scope probes, prompted the creation of a transconductance amplifier to be used as a form of voltage follower. Essentially 40 this amplifier uses a large impedance input (in this case, gates of MOSFET transistors) to draw only a small amount of current from the source it is connected to. This amplifier is then connected in a unity gain feedback formation, similar to an OP-AMP, which produces a voltage-follower like result at the output. The circuit used in this work is shown below, as well as the various transistor sizing characteristics. VOUT Figure 43: Transconductance Amplifier Schematic Transistor Sizes m Lenth M1 311 1.51) M2 311 1.511 M7 5.411 1.511 M8 5.41) 1.51) M9 5.411 1.511 M1 0 5.411 1.511 M11 1 .511 1.511 M12 1.511 1.51I M15 1.511 1.51I Table 4.3-1: Transistor Sizes for the Transconductance Amplifier 41 CHAPTER 5 Final Circuit Simulation Results The following results show transient simulations in the Cadence software suite. Each simulation was run using SKILL programming, and collected approximately 250,000 data points per simulation (see the following graphs). For this project, the code used to simulate is given in Appendix E at the end of this thesis. The goal of these simulations were to predict the final phase difference of each signal, as well as the expected time it should take for each phase difference to come to a constant. Several different scenarios were simulated, based on different bias voltages and sinusoidal phase differences at the input. The first two simulations, in figures 5-2 and 5-3, were based upon the original circuit design which did not contain a high pass filter (differentiator). This high pass filter was added later to shift the phase differences as close to zero as possible. Both of the simulations corresponding to the original concept circuit show that the phase difference is approaching a constant of 2% radians. The only visible difference is that while the first simulation (figure 5-2) connected ngAs to 3V, the second simulation (figure 5-3) connected it to 1.5V. Another difference between the two graphs is obvious — it took a simulation time of 4011s for the circuit with VBIAS = 3V to approach a noticeable constant, while it took 80115 for the circuit in figure 5-3 to approach the same constant. For clarification, the circuit structure used for these first two simulations (and the original concept circuit) can be seen in figure 5-1. 42 The third simulation, shown in figure 5-4, is regarding the final fabricated circuit design shown in figure 2-1 of this thesis. That is, it includes the high pass filter design with shifting the phase differences to zero in mind. Here VBIAS is 3V and the input phase differences are the same. When the phase differences are identical at the input, figure 5-4 shows that the phase difference corresponding to V2 - V1 has approached exactly zero radians, while the phase difference between V3 — V2 has approached 7% radians. This error is most likely due to the nonideal differentiator circuit, as explained before. 43 “E: 65 52:; :35 38:8 .6595 ”E 2:9“. > 9 .9 9 AM a X E X ”EA 1 com ID > ~> ~> 9 H_ 5 X X X ma: 1 com _I > 5 5 5 AM 5 “EA 44 £250 unwocoo _uEmto .8 >m u 25> 2 mEuconmotoo 5:23.25 "N...“ 959". $3 0E5. mm om mm om 2 or m _ _ _ _ _ _ _ v. _ r _ _ _ _ _ V Amcmfimmv 88520 ommga (suegpea) GDUGJSJNO eseud 45 .A>m._‘ u m<_m>v cos—235m 239:0 38:00 _mEmto 56 239.... $3 oEF on on on ov om ON or _ — _ _ _ h _ _ Amcmfimmv 8:985 3ch (SUB!pBu)83U819mC| eseud 46 .mwmmca SE: .3352 new >m n 25> 2 mEuconmwtoo 532385 Jim 9.39". 33 oEF wcmfimm E 88520 $95 (suenpeu) enuejeyro eseud 47 CHAPTER 6 Fabricated Circuit and Test Results Along with the main circuitry component, there were several test circuits fabricated on chip for testing and evaluation. Presented below are the results of these test circuits. 6. 1 Gilbert Multiplier V1 vs. V3 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 +3 V1 Figure 6-1: The gathered data from the fabricated test circuit. The modified Gilbert Multiplier (shown in figures 3-1 and 3-2) can be shown below for comparison with the simulated results in figure 3-3 on page 11. This graph is very similar to the one presented in the simulations, and most importantly it shows the linear region where phase detection will occur, which is the crucial component of this circuit. 48 6.2 3V-2V Converter The test 3V-2V converter built on-chip works exactly as expected, with the results shown in figure 6-2 below. Note that channel one is the VDD input of 3V, while channel two is the output voltage, or 2V. Tek Slo ): 50.0 S/sr 1 Acqs T l I ....'....:....{.... ..... n. ........................... ............................... . . . . 3 . . . . 1 . . . . 2 . . . . ..... s... . . - - - ~ . . - o - . . . . . . . . . . . u..- ,,............ ..... Chi {100‘ VTEEIE 'ifio‘ov Figure 6-2: 3V - 2V Converter Fabricated Results 6.3 Digitally Controlled Oscillator The DCO results are shown on the next p oscillate, but produces an unexpected constant of 1.692 V DC instead! To discover why this is happening, further an simulation. According to the previous DC uses the inductor in the analogLib library in Cadence, oscillation should be age. The fabricated circuit does not alysis was taken on the DCO O simulation (see figure 23-12), which 49 Tek Run: BOOKS/sr Sample L r fir v f fv fir ' ...... a ----- . ..... cu ‘ a u u . u o - c u u o u . u o a a u n - u n a u- .............................. ............................................................ ............... ....... ....:....:....!.... ..... ................ uuuuuuuuuu .................. ......... .uu . u u o u . o n o a u n n n . . n . . . I . a... .............................. v u ‘- u . . - v . _ v - - q _ v v u w ..... ....................... u- a o n o o n a o u o o u a u . - u u c v n I O - un- nu c n u - u u u 0 . u a u u n n - o a o - o o o - no .............................. C3 Mean 1.692 V - . ’ p . . u _ l i u ‘ 1.00V ..... A A - ‘ ‘ ‘M' 3.0.0.“; 662' .r ' ‘ 3an C 13 Figure 6-3: The Fabricated DCO Results occurring. This DCO waveform was produced when given a 26nH inductor with 50 ohm resistance. That is, in the inductor component itself, 50 ohms was inserted into the resistance attribute of the model, denoted as R in figure 3-11. However, it is apparent from the tested results that there is too much positive conductance in the circuit, and not enough negative conductance to cancel it out. Therefore, testing the accuracy of the inductor from the analogLib library proves that the inductor model in this library is inaccurate, due to its inability to model inductor resistance correctly. For instance, if the 50 ohms in the model is replaced with 5M ohms, we still see almost identical waveforms as shown in figure 31. These results continue to be seen in simulations, even when the 50 605333. 250 Sr. 525 «.326:— nfiuoficu no 3.3.06”. cosmic—5 31c 959". A m V arc: caém case c843. c8 _ .l. .3..lly.....1 . 4..... 2. it it n...- -<..u g: g . .... -.~-.1-. . . l mmcoawca WEEmco: 8.“. 51 resistance reaches 1T ohms or higher! This problem can be solved by first using a different inductor model (from the NCSU_Analog_Parts library) and using the two port model found by ASITIC (see figure 3-11). The results of this new simulation are almost identical to those of the fabricated version, providing further proof that the original inductor model was inaccurate (see the simulation in figure 6-5). Notice that the settled transients’ DC value of the simulated and fabricated versions are almost identical, with the simulated version being 1.64 V, and the fabricated version being 1.692 V. Now that we have confirmed the cause of the problem, the next step is to raise the widths of the negative resistance MOSFET’s to increase the negative conductance, which will cancel out the positive conductance and induce oscillation in the circuit. In this way, it was found that by increasing the PMOS transistor widths to 300um and the NMOS transistor widths to 100nm, rail-to-rail oscillation can occur in the simulation (see figure 6-6). This simulation includes the 50 ohm series resistance from the 26nH inductor, using the two port model generated from ASITIC. These results demonstrate that while the fabricated DCO does not oscillate, it was due to an incorrect amount of negative conductance to cancel out the existing positive conductance. By increasing the transistor widths to accommodate for this discrepancy, oscillation is induced and correct performance is once again achieved. 52 00? .2022.— mtmnlaofic15 0 <—15.0 volts PROCESS PARAMETERS N+ P+ POLY PLY2_HR POLYZ Ml MZUNITS Sheet Resistance 80.9 103.6 23.3 1011 41.7 0.09 0.09 ohms/sq Contact Resistance 60.9 150.8 17.6 28.1 0.86 ohms Gate Oxide Thickness 140 angstrom 60 PROCESS PARAMETERS Sheet Resistance Contact Resistance COMMENTS: N\POLY is N-well CAPACITANCE PARAMETERS N+ Area (substrate) 424 Area (N+active) Area (P+active) Area (poly) Area (poly2) Area (metall) Area (meta12) Fringe (substrate) 311 Fringe (poly) Fringe (metall) Fringe (meta12) Overlap (N+active) Overlap (P+active) CIRCUIT PARAMETERS Inverters Vinv Vinv Vol (100 uA) Voh (100 uA) Vinv Gain Ring Oscillator Freq. DIV256 (31—stg,5.0V) D256_WIDE (31-stg,5.0V) Ring Oscillator Power DIV256 (31—stg,5.0V) D256_WIDE (31-stg,5.0V) COMMENTS: SUBMICRON M3 N\PLY 0.05 814 0.80 under polysilicon. P+ POLY 746 87 2470 2366 215 234 309 [\JNNNHH OOOOLDO 61 POLY2 M1 940 ONbONN 90. 145. O 27 36 56 50 49 61 .01 .26 .13 .86 .44 .60 60 76 .47 .99 N_W UNITS 806 ohms/sq ohms M2 M3 N_W UNITS 12 7 37 aF/um“2 16 11 aF/um“2 aF/um“2 15 9 aF/um“2 aF/um“2 31 13 aF/um“2 35 aF/um“2 34 23 aF/um 39 28 aF/um 55 34 aF/um 52 aF/um aF/um aF/um UNITS volts volts volts volts volts MHz MHz uW/MHz/gate uW/MHz/gate T69K SPICE BSIM3 VERSION 3.1 PARAMETERS SPICE 3f5 Level 8, * DATE: NOV 27/06 * LOT: T69K * Temperature_parameters=Default .MODEL CMOSN NMOS ( +VERSION +XJ +K1 +K3B +DVTOW +DVTO +UO +UC +AGS +KETA +RDSW +WR +XL +DWB +CIT +CDSCB +DSUB +PDIBLC2 +PSCBE1 +DELTA +PRT +KT1L +UB1 +WL +WWN +LLN +LWL +CGDO +CJ +CJSW +CJSWG +CF +PK2 * 3.1 1.5E—7 0.875093 -8.5140476 0 = 2.670658 = 452.3081836 llllll lOl—‘LAJLDNOHF—‘O 1.166279E-1l 0.1384489 -3.615287E—3 1.380341E3 1 . .537786E-8 H ["3 \1 .076309 .23243E-3 .619472E8 .01 OOOQNOOOW l \J ON H I? H CD .34E-10 .240724E—4 .007134E-10 .64E-10 0.0283027 .MODEL CMOSP PMOS ( +VERSION +XJ +K1 +K3B +DVTOW +DVTO +U0 +UC +AGS +KETA +RDSW +WR +XL +DWB 3.1 1.5E-7 0.5600277 = -l.0103515 0 2.2199372 220.5729225 -5.76898E-11 0.157364 -2.42686E-3 3E3 l 1E—7 1.629532E-8 WAF: TNOM NCH K2 W0 DVTlW DVTl UA VSAT BO A1 PRWG WINT XW VOFF CDSC ETAO PCLM PDIBLCB PSCBE2 RSH UTE KT2 UCl WLN WWL LW CAPMOD CGSO PB PBSW PBSWG PVTHO WKETA TNOM NCH K2 W0 DVTlW DVTl UA VSAT BO Al PRWG WINT XW VOFF Star—HSPICE Level 49, 9104 27 = 1.7El7 -0.0943223 1.01582E-8 0 0.4282172 3.061716E—13 1.682414E5 2.579158E-6 1.054571E-6 0.0301426 2.594349E-7 0 0 2 2 .4E-4 .332015E-3 2.6209353 -0.0436947 2.968801E-4 80.9 -1.5 0.022 -5.6E—11 1 .34E-10 .9148626 .8 .8 .0526696 0.0191754 IOOOONNOO \] .7E17 .302429E-3 .010628E-8 .5378964 .141811E—9 .342779E5 .735259E-7 .447019E-4 -0.0418484 3.097872E—7 0 —0.0823738 WKDHWOOHKDHN 62 UTMOST Level 8 LEVEL TOX VTHO K3 NLX DVT2W DVT2 UB A0 Bl A2 PRWB LINT DWG NFACTOR CDSCD ETAB PDIBLCl DROUT PVAG MOBMOD KTl UAl AT WW LL LWN XPART CGBO MJ MJSW MJSWG PRDSW LKETA LEVEL TOX VTHO K3 NLX DVT2W DVT2 UB A0 Bl A2 PRWB LINT DWG NFACTOR 49 1.4E-8 0.6656437 25.0562441 1E-9 0 -0.1373089 1.515137E-18 0.6297744 5E-6 0.3379035 0.0106493 7.489566E-8 —9.471353E-9 1.0754804 0 -l.531255E—4 1 1.0300278 9.970995E-3 1 = —0.11 = 4.3lE-9 3.3E4 0 0 1 0.5 1E—9 0.4416777 0.2025106 0.2025106 110.1539295 8.469064E-4) 49 1.4E-8 —0.9633249 7.2192028 5.826683E-8 0 = -0.1158128 1.085892E—21 = 0.9333822 = 5E-6 0.3701317 -0.0212357 1.040878E—7 -l.983686E-8 0.969384 +CIT +CDSCB +DSUB +PDIBLC2 +PSCBE1 +DELTA +PRT +KT1L +UBl +WL +WWN +LLN +LWL +CGDO +CJ +CJSW +CJSWG +CF +PK2 * II II II II II OOOl—ILUP—‘OO .172604E-3 .851867E10 .01 -7.61E-18 .09E-10 .410008E-4 .487127E—10 .4E-11 .73981E-3 CDSC ETAO PCLM PDIBLCB PSCBE2 RSH UTE KT2 UCl WLN WWL LW CAPMOD CGSO PB PBSW PBSWG PVTHO WKETA H 2.4E-4 0.4985496 2.1142057 -0.0511673 1.697939E-9 103.6 -1.5 0.022 —5.6E—11 H .09E-10 .9665307 .99 .99 .98016E—3 .870507E-3 NU'IOOOLAJNOO 63 CDSCD ETAB PDIBLCl DROUT PVAG MOBMOD KTl UAl AT WW LL LWN XPART CGBO MJ MJSW MJSWG PRDSW LKETA 0 —0.0653358 0.0256688 0.1695622 0 1 = -0.11 4.3lE-9 3.3E4 0 0 1 0.5 1E-9 0.4978642 0.3877813 0.3877813 14.8598424 -4.823171E-3) APPENDIX B Final Circuitry Layout and Floor Plan 64 Gilbert Multiglier (current/volt EHMNEE EWHEIE elm “HIE @EEEE E 3V-2V Inductor Inductor Conv Varactors El 3 @ DE Final Circmt El ~ DEG DEC 5I E] 24 DCO Inductor 25 Ill l:l<——| @aaao amass Hl-"F Transconductance Amplifier Figure B-1: Final Circuitry Floor plan 65 Figure B-2: Final Circuitry Layout 66 APPENDIX C Fabricated Chip Pin Assignment 67 VDD to PADS 3-8 Decoder_2_select 0 3-8 Decoder_2_select 1 3-8 Decoder_2_select 2 V3_LPF Out Gilbert Multiplier TEST Vbias Gilbert Multiplier TEST V4 Gilbert Multiplier TEST V3 Gilbert Multiplier TEST V2 10. Gilbert Multiplier TEST V1 11. V00 to Base circuit 12.V1 LPF Out 13.V1 HPF Out 14. Gilbert Multiplier TEST VOUT 15. 3V-2V Converter VOUT 16. V1_OUT 1 7. V3_OUT 18. 3V-2V Converter V.N 19. Vbias 20.GND to PADs 21 . 3-8 Decoder_1_select 0 22. 3-8 Decoder_1_select 1 23. 3-8 Decoder_1_select 2 24.Varactor TEST Out 2 - VDP 25.Varactor TEST Out 1 — VDN 26. DCO TEST OUT2 - V1 DP 27. DCO TEST OUT1 — V1 DN 28.Transconductance Amplifier TEST VOUT 29. Differentiator Test Circuit In 30. Differentiator Test Circuit Out 31.GND to Base Circuit 32.V2 LPF Out 33.V2 HPF Out 34.V2_OUT 35. Transconductance Amplifier TEST Vm- 36.Transconductance Amplifier TEST VIN. 37.V3 HPF Out 38. 3-8 Decoder_3_select 2 393-8 Decoder_3_select 1 40. 3-8 Decoder_3_select 0 599°.‘19’9‘PWNT‘ 68 APPENDIX D OCEAN Script To Collect Data 69 HDUH’9’!!9HH’IH”H’HHH ;Script to gather data ; ; gather.ocn ; ;Stephen Ziel 8/07/06; ’!!I!HH!’1’!!H”’)!’!H!9!H9 openResults("/egr/research/RFlC/zielstep/cadence/simulation/Final_Project_cop y4/spectreS/schematic/psf") selectResults('tran) freq1=frequency( v( "N1 " ) ) freq2=frequency( v( "N2" ) ) freq3=frequency( v( "N3" ) ) w1=2*3.141592654*freq1 w2=2*3.141 592654*freq2 w3=2*3.141 592654*freq3 biglist1=root( deriv( v( "N1" ) )/w1, 0, 0) biglist2=root( deriv( v( "N2" ) )/w2, 0, 0) biglist3=root( deriv( v( "N3" ) )lw3, 0, 0) myport1=outfile("/egr/research/RFIC/zielstepN1data") foreach( element biglist1 fprintf( myport1 "%L\n" element) close(myport1 ) myport2=outfile("/egr/research/RFlC/zielstepNZdata") foreach( element biglist2 fprintf( myport2 "%L\n" element ) close(myport2) myport3=outfile("legr/research/RFlC/zielstepN3data") foreach( element biglist3 fprintf( myport3 "%L\n" element ) ) close(myport3) 70 APPENDIX E 3-8 MUX VHDL Code 71 library IEEE; use lEEE.std_|ogic_1164.all; use lEEE.std_|ogic_unsigned.all; entity DECSTOB is port (SEL: in STD_LOG|C_VECTOR(2 downto 0); DEC_OUT: out STD_LOG|C_VECTOR(7 downto 0)); end DEC3TO8; architecture BEHAV of DEC3TO8 is begin CASE_PRO: process (SEL) begin case SEL is when "000” => DEC_OUT <= ”00000001“; when "001" => DEC_OUT <= "00000010"; when "010" => DEC_OUT <= "00000100"; when "011" => DEC_OUT <= ”00001000"; when "100" => DEC_OUT <= "00010000"; when "101" => DEC_OUT <= ”00100000"; when "110" => DEC_OUT <= "01000000"; when "111" => DEC_OUT <= "10000000"; when others=> DEC_OUT <= "00000000"; end case; end process; -End CASE_PRO end BEHAV; 72 APPENDIX F MOSIS Pin Diagram 73 WEEEEWW I nrlnnm Qty: 5 T69K-A0 P40 (76389) 40 wires; longest is 5300; shortest is 3874 um Minimum pad size: 60 x 60; minimum pad pitch: 111 um MOSIS Die Size: 1684 (+128 / -72) x 1678 (+0 / -72) um Cavity Size: 7874 um x 7874 um ‘I ‘ TOP VIEW 2 1‘40 74 26-SEP-2006 12:30:42 Figure? F-1: MOSIS Pin Diagram 77 APPENDIX G On-Chip Inductor Layout 75 Mlllllflll Figure G-1: 26nH On-Chip Inductor Including Orthogonal Poly-Planes 76 BIBLIOGRAPHY 77 [1] [2] [3] [4] [5] [5] [7] [8] I9] [10] [11] [12] [13] S. Ziel, F. Salem, “Self-SynChronization of an Array of Programmable Oscillators (Clocks)”, Proceedings of the 2006 IEEE lntemational Conference on Mechatronics and Automation, pp. 1537-1542, June, 2006. Gray, Hurst, Lewis and Meyer, “Analysis and Design of Analog Integrated Circuits”, 4th edition. M. Rachedine, D. Kaczman, A. Das, M. Shah, J. Mondal, and C. Shurboff, “Performance Review of Integrated CMOS VCO Circuits for Wireless Communications”, IEEE Radio Frequency Integrated Circuits Symposium, pp. 77-80, 2003. P. Andreani and S. Mattisson, “On the Use of MOS Varactors in RF VCO’s”, IEEE Journal of Solid State Circuits, pp. 905-910, June, 2000. ASITIC Documentation, http:l/rfic.eecs.berkeley.edu/~nikn<flad/asitic.html “Layout of Capacitor”, Wayne State University, http://webpages.eng.wavne.edu/~cadence/ECE6570/cap/Layout of Gaga citor.htm “Layout of Resistor”, Wayne State University, http://webpages.eng.wavne.edul~cadence/ECE6570/res/Lavout of Resist or.htm lnder Bahl, “Lumped Elements for RF and Microwave Circuits”, 2003 Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”, 2nd edition Gregory M. Wierzba, “ECE 832 Lecture Notes”, Fall 2005 R. Staszewski, D. Leipold, C.Hung, P. Balsara, “A First Digitally-Controlled Oscillator in a Deep-Submicron CMOS Process for Multi-GHz Wireless Applications”, IEEE Radio Frequency Integrated Circuits Symposium, pp. 81 - 84, 2003 R. Staszewski, D. Leipold, K. Muhammad, P. Balsara, “Digitally Controlled Oscillator (DCO)—Based Architecture for RF Frequency Synthesis in a Deep-Submicrometer CMOS Process”, IEEE Transactions on Circuits and Systems — II: Analog and Digital Signal Processing, Vol. 50, No. 11, November 2003 R. Staszewski, P. Balsara, “Phase-Domain All-Digital Phase-Locked Loop”, IEEE Transactions on Circuits and Systems — ll: Express Briefs, Vol. 52, No. 3, March 2005 78 [14] [15] [16] [17] [18] K. Waheed, R. Staszewski, “Harmonic Characterization of Mismatches in Deep Submicron Varactors for a Digitally Controlled RF Oscillator” Einspruch, Gildenblat, “Advanced MOS Device Physics”, Vol. 18, pp. 1-37, 1989. J. Groszkowski, “Frequency of Self-Oscillations”, 1964 l. M. Filanovsky, A. Allam, L. B. Oliveira, J. R. Femandes, “Synchronization of Mutually Coupled LC—Oscillators”, ISCAS 2006 J.M. Rabaey, “Digital Integrated Circuits”, 2nd edition, 2003 79 IIIIIIIIIIIIIIIIIIIIIIII