Chip seal is one of the most popular preventive maintenance techniques performed by many DOTs, county road departments and cities. One of the most important parameters affecting performance of a chip seal is the percent aggregate embedment depth into the binder. Depending on the percent embedment of aggregates in chip seals, they may be susceptible to distresses such as aggregate chip loss and bleeding. In this study, a standard test procedure was developed to directly calculate aggregate embedment depth via digital image processing techniques. Two image-based algorithms were developed to calculate embedment depth, and another algorithm was developed to compute the percentage of the aggregate surface coverage area with binder. The statistical analysis results indicated that there is a good correlation between embedment depth obtained from image-based algorithms and sand patch test results. Analyses of chip seal samples collected from limited number of ‘good-performing’ field chip seal sections revealed that the aggregate percent embedment ranged from 50% to 70%, which is the typical desired range to minimize bleeding and chip loss. However, more research is needed to investigate the ‘poor-performing’ field sections. Various laboratory chip seal samples were also prepared to investigate the variation of percent embedment in chip seals made with the minimum and maximum binder and aggregate application rates specified in MDOT’s special provisions. The results revealed that the average percent embedment ranged from 55% to 70%.
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