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LIBRARY
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Unwersity

 

 

 

This is to certify that the
thesis entitled

Digital Low-Level Radio Frequency Control and Microphonics
Mitigation of Superconducting Cavities

presented by

Nathanael Robert Usher

has been accepted towards fulfillment
of the requirements for the

MS. degree in Electrical Engineering

 

 

%P/

Major Professor's Signature

00/32/2 007

Date

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Digital Low-Level Radio Frequency Control and
Microphonics Mitigation of Superconducting Cavities

By

Nathanael Robert Usher

A THESIS

Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

MASTER OF SCIENCE
Department of Electrical and Computer Engineering

2007

ABSTRACT

Digital Low-Level Radio Frequency Control and
Microphonics Mitigation of Superconducting Cavities

By

Nathanael Robert Usher

Superconducting Radio Frequency (SRF) cavities designed for proposed linear reaccel-
erators at the National Superconducting Cyclotron Laboratory (NSCL) have an unloaded
quality factor (Q) on the order of 109. The high Q results in a very narrow bandwidth, so
small perturbations in the cavity’s resonant frequency result in large changes in the mag-
nitude and phase of its electric field for a fixed frequency driving signal. As a result, it is
necessary to use a controller that can compensate for perturbations as they occur.

This project develops a new digital low-level radio frequency (LLRF) controller for
this application, including DSP-based hardware, software algorithms, and a graphical user
interface. The digital LLRF controller provides two types of c0ntrol over cavity pertur-
bations. The LLRF implements a PID control on the cavity driving signal to compensate
for nonlinearities and small random disturbances. Significant cavity detuning caused by
narrow-band vibrations, referred to as “microphonics,” are reduced by the LLRF controller
using a piezoelectric tuner controlled by an adaptive feedforward cancellation algorithm.

The completed prototype is a small, standalone, economically viable, ethemet con-
nected controller. Through a MATLAB interface, it will allow advanced algorithm devel-
opment by control engineers who are not necessarily familiar with the low-level workings

of the controller.

ACKNOWLEDGMENTS

I would like to thank my advisor Dr. Xiaobo Tan and Dr. John Vincent of the National
Superconducting Cyclotron Laboratory (NSCL) for giving me the opportunity to work on
this project. I would also like to thank everyone in the electronics department at the N SCL
for their help. Without help from Mark Davis and John Priller, I would not have been able to
develop the network interface and graphical front-end. Adam Molzahn laid the groundwork
for this project with his digital phase meter and introduced me to the fundamentals of how
the system works. Without Adam’s work to build upon and the help and guidance of the

NSCL staff, I would not have been able to complete this project.

iii

TABLE OF CONTENTS

ABSTRACT ....................................... ii
ACKNOWLEDGMENTS ................................ iii
LIST OF TABLES ................................... vi
LIST OF FIGURES ................................... vii
1 Introduction ..................................... l
2 Signal Digitization and Interlocks .......................... 9
2.1 Collecting Input Samples ........................... 9
2.2 CORDIC Algorithm ..... _ ......................... 12
2.3 DSP Interface ................................. 15
2.4 RF Output Creation .............................. 18
2.5 Interlocks ................................... l9
3 Tasks Performed by the Digital Signal Processor .................. 21
3.1 DSP Peripherals ................................ 21
3.2 Control Program Overview .......................... 22
3.3 Data Received From Host Processor ..................... 23
3.4 Control Thread ................................ 24
3.5 Status Thread ................................. 25
3.6 Software Interrupts .............................. 26
4 Control ........................................ 28
4.1 RF Amplitude and Phase Control ....................... 28
4.2 Cavity Tuning ................................. 29
5 The ZWorld RabbitCore Host Processor and Graphical User Interface ....... 32
5.1 Module Initialization ............................. 32
5.2 User Interface ................................. 33
5.3 Main Screen .................................. 34
5.4 PID Screen .................................. 36
5.5 AFC Screens ................................. 37
5.6 Startup Screen ................................. 40
5.7 Advanced Screen ............................... 40
6 Testing and Performance ............................... 42
6.1 Cavity Simulation Circuit ........................... 42

iv

7 Conclusion and Future Work ............................ 50

7.1 Conclusion .................................. 50
7.2 Required Changes ............................... 51
7.3 Future Hardware Upgrades ................. g ......... 52
7.4 Future Software Upgrades .......................... 53
A FPGA Implementation of a CORDIC Algorithm .................. 55
B DSP Daughter Board Schematics .......................... 59

BIBLIOGRAPHY .................................... 7 l

2.1
2.2
3.1

LIST OF TABLES

CORDIC algorithm example .......................... 15
Description of FPGA memory locations .................... 16
Responses from the DSP are received by the host two words after the com-

mand was transmitted. ............................ 24

1.1

1.2

1.3
1.4
2.1

2.2

2.3

4.1

4.2

5.1
5.2
5.3
5.4

5.5
5.6
6.1

LIST OF FIGURES

Overview of the LLRF controller as it will be connected to an SRF cavity.
The LLRF controller consists of everything inside of the dashed lines. . . .

LLRF controller motherboard. DSP daughter board is attached on the lower
right corner. Host processor board attaches to back side. Front side contains
the reference phase-locked loop and all input signal conditioning compo-
nents. Back side contains the high-speed ADCs and DAC, FPGA, and
output signal conditioning components. ...................

DSP daughter board. DSP is underneath the large black heat sink. .....
ZWorld RabbitCore daughter board. .....................

Sampling a 50 MHz signal at 40 MSPS produces a 10 MHz alias whose
phase is measured relative to the phase of the 10 MHz reference signal.

DAC output spectrum when producing output at 40 MSPS (left) and IF
after 50 MHz band-pass filter (right). ....................

DAC output. spectrum when producing output at 80 MSPS (left) and IF
after 50 MHz band-pass filter (right). ....................

Block diagram of PID control. The cavity behaves linearly when operat-
ing near its resonant frequency, so it can be approximated by the transfer
function, G(s). ................................

Adaptive feedforward cancellation control for the cancellation of a single
sinusoidal disturbance [22]. .........................

Main controller screen. ............................
PID tuning screen. ..............................
AFC screen. .................................

FFI‘ screen shows FFI‘ of cavity output in dBm, cavity magnitude response,
and cavity phase response in degrees. All plots show 0 to 1000 Hz linear
scale. .....................................

Startup screen. ................................
Advanced screen. ...............................

Block diagram of circuit used for cavity simulation. The two transfer func-
tions are replaceable RC networks. .....................

vii

6

ll

41

6.2

Each of the transfer function blocks is made up of a replaceable RC net-

work. ..................................... 44
6.3 Ideal magnitude response (top) and magnitude response calculated by

LLRF controller (bottom). .......................... 46
6.4 Ideal phase response (top) and phase response calculated by LLRF con-

troller (bottom). ............................... 47
6.5 FFT of RF input with 60 Hz sinusoidal disturbance. Because the magnitude

of the disturbance is large, its third harmonic is also present. ........ 49
B.1 System Overview. .............................. 60
B.2 Voltage regulation and clock generation. .................. 61
B.3 DSP power connections. ........................... 62
B.4 DSP bypass capacitors, UTOPIA port, HPI port and reserved pins. ..... 63
B.5 DSP serial connections. ........................... 64
B.6 DSP JTAG emulation port and general purpose port. ............ 65
B.7 DSP external memory interface A. ...................... 66
B.8 External SDRAM. .............................. 67
B.9 DSP external memory interface B. ...................... 68
B. 10 External non-volatile memory and FPGA connection. ........... 69

viii

CHAPTER 1

Introduction

The desire to do further research into particle physics has driven a demand for new high-
energy accelerators. The reduced surface resistances of superconducting cavities make
them capable of supporting high fields with low power losses. The quality factor (Q) of a
cavity of given geometry is an indicator of how high a field it can achieve. While cavities
with high quality factors can achieve higher internal fields, this comes at the expense of
narrower bandwidth. The very narrow bandwidth associated with high Q cavities makes
maintaining amplitude and phase control in the presence of perturbations increasingly dif-
ficult [1].

Feedback control is required to maintain a stable cavity field in the presence of a distur-
bance. One can apply a PID control to maintain the amplitude and phase of the cavity field
at a given set point. As perturbations shift the cavity’s resonant frequency away from the
RF driving frequency, the low-level radio frequency (LLRF) controller measures the error
in the cavity field and compensates. Although this method works well for small perturba—
tions, it will not work for large perturbations, since the required input power to maintain
the cavity field will be too high. Therefore, for high-Q superconducting cavities, it is nec-
essary to have an active tuning mechanism to cancel the disturbances to keep the driving

frequency within the cavity’s bandwidth.

A properly designed continuous wave system will only have limited narrowband si-
nusoidal disturbances due to vibrations (microphonics). Simrock et a1. were the first to
demonstrate using a piezoelectric actuator to cancel these disturbances [2]. Due to the com-
plex transfer functions of multi-cell superconducting cavities, a feedback control would be
exceedingly difficult to implement. However, Kandil et al. demonstrated an adaptive'feed—
forward cancellation (AFC) algorithm capable of canceling narrow-band vibrations in a
multi-cell cavity using a dSpace development board connected to a PC [3]. Although the
AFC algorithm was shown to work, the implementation required a PC and several other
pieces of equipment to control a single cavity. Therefore, it was not practical for use in a
running linear accelerator, which will have many cavities that need to be controlled. The
control needs to be implemented on a low-level radio frequency (LLRF) controller to be
useful, which is the subject of this work. The LLRF controller will use the AFC algorithm
to attenuate cavity detuning from significant narrow-band disturbances, and Use a PID con-
trol to continuously adjust the amplitude and phase of the RF driving signal to compensate
for other disturbances.

Digital LLRF controllers are currently being designed at several accelerator labs to
replace analog controls. Implementing controls in the digital domain reduces the size and
cost of the hardware and allows the implementation of controls that are not feasible on
analog systems [9]. Most of the new LLRF controllers being developed for applications that
do not require a lot of computing power rely on a field programmable gate array (FPGA)
to perform the RF measurements and control algorithms. The controllers being developed
for the Spallation Neutron Source (SNS) accumulator ring [5] and International Linear

\

Collider (ILC) [6] are both based on FPGAs. For applications that require more processing

power, an FPGA with an embedded processor is commonly used [7]. Although some of
the other LLRF controller designs provide a lot of the functionality required for the linear
reaccelerator upgrade to the N SCL and could possibly be adapted if necessary, they do not
meet all of the requirements for the reaccelerator upgrade. The problem with either of these
designs is that upgrading the software for the system requires extensive knowledge of the
LLRF controller and experience with FPGA programming. One of the requirements for the
LLRF controller for the NSCL is that it must be possible for control engineers to update the
software controls using tools they are familiar with, without needing to know the details
about how the hardware is set up. Other requirements are that the LLRF controller must
be completely standalone, requiring only a network connection to communicate with the
EPICS control system [8], it needs to provide tuner outputs for microphonics mitigation,
- and it needs to have a user-friendly interface for setup and monitoring.

Figure 1.1 shows an overview of the LLRF controller developed here, which was in-
spired by the LLRF controller designed by Lawrence Berkeley National Laboratory [9].
The LLRF controller consists of a motherboard (Figure 1.2), a DSP daughter board (Fig-
ure 1.3), and a control host board (Figure 1.4). The input signal conditioning portion of
the motherboard is unchanged from the previous iteration of the project: the digital phase
meter developed by Adam Molzahn [10]. However, there have been major changes to the
digital sections. The biggest change is that a high-performance DSP has been added to the
controller. All of the digital processing is now done by the DSP, so all data is sent from
the FPGA directly to the DSP instead of the host processor. The DSP runs the PID based
amplitude and phase control algorithms and feedforward based microphonics mitigation

algorithms and sends data to the control host processor as necessary. This frees up enough

 

Stable RF Stable RF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Figure 1.1. Overview of the LLRF controller as it will be connected to an SRF cavity. The
LLRF controller consists of everything inside of the dashed lines.

FPGA logic to allow it to perform a 16-bit coordinate rotation digital computer (CORDIC)
algorithm [11] on all incoming channels to obtain their phase and magnitude information.
The parallel nature of the FPGA makes it the ideal place for doing the phase and amplitude
conversions, since it can do all input channels simultaneously without slowing down the
rest of the system. By converting all input channels simultaneously, we guarantee that a
read of all input channels returns amplitude and phase information taken at the same sample
time.

There are five RF inputs on the front of the controller module. One is a reference signal

(10 MHz), used to control the sample clock for the high-speed analog-to-digital converters

 

Figure 1.2. LLRF controller motherboard. DSP daughter board is attached on the lower
right comer. Host processor board attaches to back side. Front side contains the reference
phase-locked loop and all input signal conditioning components. Back side contains the
high-speed ADCs and DAC, FPGA, and output signal conditioning components.

 

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Figure 1.3. DSP daughter board. DSP is underneath the large black heat sink.

 

Figure 1.4. ZWorld RabbitCore daughter board.

(ADCs) used to digitize the inputs and to synchronize multiple modules when they are
implemented together in an accelerator. Three of the RF inputs are the input signals to be
measured (forward power, reflected power, and cavity output). Depending on mixer and
filter parts selection when assembling the modules, the inputs can be between 2 MHz and
1.5 GHz, with power levels from -7 dBm to +33 dBm. However, there are some frequencies
within that range that will not work well due to interactions of the harmonics that may be
present within the intermediate frequency. The final RF input is the local oscillator (LO)
input, which-must be at a frequency 50 MHz higher or lower than the RF input frequency
and phase-locked to the reference signal. The LO signal is mixed with each RF input to
convert them to the 50 MHz interrfiediate frequency (IF) for sampling. The fixed 50 MHz
intermediate frequency is used, because it is easier to digitize a signal with a fixed, known
frequency. An ideal mixer produces frequencies which are the sum and difference of its two
input signals as shown in Equation (1.3). Since the LO signal is chosen 50 MHz higher or
lower than the RF frequency, one of the components of the mixer output is at 50 MHz, and
the other is filtered out using a 50 MHz band pass filter. Also, since the L0 is phase-locked
to the reference signal, 92 is fixed and can be calibrated out. Therefore, phase changes in

the RF input directly affect the phase of the IF signal.

RF=A|sin(u)1t+01) (1.1)
L0 =A2sin(0)2t+02) (1.2)
A1142 A1A

RFai<L0= 2608(((D1—0)2)t+91—92) (1.3)

 

COS(((01+(02)I+91+92)—

 

The remaining front panel connectors are the RF output, a tuner output, RF On/Off
input, reset input, and a fault output. The RF output is produced by creating an output at
the IF, then mixing it with the L0 to produce a signal at the desired frequency. The fast
tuner output is an analog signal that is designed to cancel microphonics up to 1 kHz. A
slow tuner output is provided that can be used to compensate for slow drifts in the resonant

frequency of the cavity. The rest of the signals are digital control signals.

CHAPTER 2

Signal Digitization and Interlocks

The field programmable gate array’s (FPGA) primary task is to collect the data sampled
by the high-speed ADCs and buffer it until it is requested by the DSP. The configurability
and parallel nature of the FPGA makes it ideal for collecting and buffering the sampled RF
signals. The FPGA’s other tasks include setting the digital attenuators on the input channels
and taking care of 'some of the interlock signals. The FPGA used in this project is a Xilinx
Spartan-H XC2S 150. Although it is adequate for this project, future versions will probably

move to a newer, faster FPGA with more available logic.

2.1 Collecting Input Samples

To be able to calculate the amplitude and phase of the signal, we need a vector-based
measurement of the signal with respect to a reference. If the samples are taken at 90°
intervals, then the vector realizations can be equated to the real and imaginary components
of a vector in the complex plane. If the first sample is taken as the real component of the
signal, then the second sample is 90° lagging and is equated to the imaginary component
of the signal. In the absence of a DC sampling error, the third sample is the negative of

the first sample and the fourth sample is the negative of the second sample. The first and

third and second and fourth samples can be averaged to remove any DC sampling error.

Once the real (I) and imaginary (Q) components are known, the phase and magnitude can

be computed using:
Phase = tan—1 (g) (2.1)
Magnitude 2 V12 + Q2 (2.2)

The phase information gathered with this method can be used to tell the relative phase
between inputs, but is not meaningful when using multiple LLRF controllers in a system,
since the first sample is taken at an arbitrary time. Therefore, one of the RF inputs is used
as a reference signal. The phase of the reference signal is subtracted from the phase of
each input to produce phases relative to the reference signal, which allows multiple LLRF
controllers to be synchronized with each other.

In a variable frequency system, it can be difficult to take samples every 90° since the
time delay between samples depends on the signal frequency. However, since all of our
inputs have been mixed to 50 MHz, we have a known frequency, and just need to choose
an appropriate sample rate [10]. To take samples every 90° of the input signal, we need
four samples per period, and therefore, a sample rate of 200 MSPS. ADCs that can sample
at 200 MSPS are expensive, so it is not cost-effective to use them, and it was necessary to
find another way to get the I and Q values. By removing the condition that all four samples
in a measurement must come from the same period of the input signal, we can use a lower
speed, less expensive ADC. Therefore, a sample rate of 40 MSPS was chosen. Sampling at
40 MSPS produces a 10 MHz alias with the same amplitude and phase as the 50 MHz IF

signal (Figure 2.1) and gives us samples taken every 90° as desired.

10

10MH2 from 50MHz sampled at40MHz

 

 

 

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Figure 2.1. Sampling a 50 MHz signal at 40 MSPS produces a 10 MHz alias whose phase
is measured relative to the phase of the 10 MHz reference signal.

11

Each ADC samples its input on the rising edge of the 40 MHz sample clock. The FPGA
reads the 14-bit data output of each ADC on the falling edge of the clock, when the data
becomes valid. The FPGA samples all inputs simultaneously, so the relative phases of
each channel are preserved, even if one or more of the input channels are drifting in phase.
As seen in Figure 2.1, by sampling the intermediate frequency (50 MHz) at 40 MHz, the
system produces samples that are 90° apart, and if the phase of the input is constant, the
input sequence will repeat every four samples. The FPGA passes every input through a 10
MHz first-order digital band-pass filter to try to remove noise that might have been picked
up by the ADC during sampling [12]. Next, each set of samples is saved as either I , Q, —I,
or —Q, depending on the value of a 2-bit counter. The FPGA then averages the I and —I
and Q and —Q pairs and buffers them so they can be accessed by the DSP. The averaging
removes any DC offset from the samples, to give the real and imaginary components of the

vector.

2.2 CORDIC Algorithm

Since most vector calculations done by the DSP need to be done in polar coordinates, it
is necessary to implement an efficient algorithm for conversion between the rectangular
and polar coordinates. In the previous iteration of this project [10], these conversions were
done by the host processor using equations (2.1) and (2.2). However, doing the conver—
sions in the host processor is much too slow to be reused here. One option to speed up
the conversions was to implement the same conversion in the DSP. However, implement-

ing the conversion in the DSP uses a surprisingly large amount of CPU time and would

12

greatly reduce the amount of computing time available for the control algorithms. The best
option is to implement the conversions in the FPGA using the Coordinate Rotation Dig-
ital Computer (CORDIC) algorithm. The CORDIC algorithm was designed in the early
days of digital computers as a way to perform conversions between polar and rectangular
coordinates quickly using a small number of gates. It uses a series of multiplications by
known complex numbers to shift the input vector to 0°, while keeping a running total of the
amount of phase shift it has added. After shifting the input vector to 0°, we know that the
output vector’s real component is the input vector’s magnitude, and the input vector’s phase
is the negative of the total phase shift. By selecting the phase shifts carefully, each step of
the algorithm can be implemented using only right-shifts and addition or subtraction [13].
Another advantage of the CORDIC algorithm is that it does not have to produce its
output in any particular type of unit, so we are not restricted to using radians or degrees to
represent the phase. To speed DSP calculations, the system represents phase as a raw 16-bit
value, with each bit representing $96- degrees. This is advantageous because the DSP no
longer has to check whether its results are between 0° and 360°, since any result that would
normally fall outside this range simply overflows and wraps around to the desired value.
In each stage of the CORDIC algorithm, we check the sign of the Q value todecide
whether to add or subtract phase. The first stage is a 90° shift. If Q is positive, the I and
Q values are swapped and the new Q value is negated to produce a —90° shift, and 90° is
added to the cumulative phase. If Q is negative, the I and Q values are swapped, the new I

value is negated to produce a +90° shift, and 90° is subtracted from the cumulative phase.

(1+Qj)(0+j) = -Q+IJ' (2-3)

13

(1+Qj) (0—1') = Q-lj (2.4)

In subsequent stages, the shifts are performed by multiplying the intermediate vector by a

vector of the form 1 + 2‘" j or 1 — 2‘" j, depending on the sign of Q.

(HQ) (1 452‘" j) = (I—2""Q) + (Q+2“"1) j (2.5)

(1+ Q1) (1 — 2‘" j) = (I+2"‘Q) + (Q— 2*”1) j (2.6)

Since the FPGA stores numbers in binary format, 2‘"I is equal to I shifted to the right
by n bits, and 2“"Q is equal to Q shifted to the right by n bits. The second stage of the
algorithm uses n = 0, and n is increased by l in each subsequent stage. The algorithm gains
approximately 1 bit of resolution in each stage it performs, so it runs 16 stages as set up
in the FPGA. The FPGA performs each stage of the routine on the rising edge of the ADC
sample clock, and it does 16 stages per conversion, so the FPGA is able to convert every
fourth set of I , Q, —I, and —Q values for each channel. This produces phase and magnitude
pairs 2,500,000 times per second, which is much faster than the DSP will request them.
One issue that needs to be taken into account with this algorithm is that after the first
stage, each multiplication changes the magnitude of the vector being converted, not just the
phase. However, the total magnitude scaling is a constant dependent only on the number
of iterations of the algorithm. Therefore, the magnitude scaling inverse can be calculated
ahead of time and can be used to cancel the scaling effect. Table 2.1 shows an example
conversion including the magnitude scaling constant. The cumulative phase converges

toward the actual phase of 538°, and I (divided by the magnitude constant) converges to

14

Table 2.1. CORDIC algorithm example.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Stage I Q Cum. Phase Mag. Constant Next Phase Shift
0 150 205 0° 1 —90°
1 205 -150 90° 1 45°
2 355 55 45° 1.41421 —26.565°
3 382.5 -122.5 71.565° 1.58114 l4.036°
4 413.125 -26.875 57.529° 1.62980 7.125°
5 416.484 24.766 50.404° 1.64248 —3.576°
6 418.032 - 1 .265 53.98° 1.64569 l.790°

 

 

the actual magnitude of 254.02.

In order to produce the high-speed DAC output from the desired phase and magnitude
information, it is necessary to perform the CORDIC algorithm in the reverse direction. The
algorithm is almost identical, except that the FPGA starts with the desired magnitude in I ,
the desired phase in the phase accumulator, and Q = 0. Then, it performs shifts based on
the sign of the phase value until the phase is shifted to 0. Again, there is a scaling factor
in the conversion, so the DSP must multiply the desired magnitude by the scaling factor’s

inverse before sending the phase and magnitude pair to the FPGA.

2.3 DSP Interface

The fastest way to transfer data between the DSP and a peripheral is through one of its two
external memory interfaces (EMIF). To connect the FPGA to the DSP, I set up the FPGA
to appear as a 16—bit asynchronous RAM, then defined memory locations that the DSP can
read or write to send or receive data [14]. Because of the small number of available pins
on the FPGA, I could only set up 32 memory locations, but this is sufficient for the current

system. The memory locations are shown in Table 2.2.

15

Table 2.2. Description of FPGA memory locations.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Add. Description Read/W rite Add. Description Read/W rite
0 Chl - Ref. Phase Read-only l6 Chl I Read-only
1 Chl Amplitude Read-only 17 Chl Q Read-only
2 Ch2 - Ref. Phase Read-only 18 Ch2 I Read-only
3 Ch2 Amplitude Read-only 19 Ch2 Q Read-only
4 Ch3 - Ref. Phase Read-only 20 Ch3 I Read-only
5 Ch3 Amplitude Read—only 21 Ch3 Q Read-only
6 Always Outputs 0 Read-only 22 [Ref I Read-only
7 Ref. Amplitude Read-only 23 Ref Q Read-only
8 Output Phase W 24 Output I Read-only
9 ' Output Amplitude RM 25 Output Q Read-only
10 Error Register Read-only 26 I Input R/W *
11 Digital Attenuator R/W 27 Q Input W
12 Ref. Phase Read-only ' 28 I Input W
13 Unused R/W 29 Q Input W
14 Output (shifted 225°) 1 Read-only 30 Phase Output Read-only
15 Output (shifted 225°) Q Read—only 31 Magnitude Output Read-only

 

 

 

 

 

 

 

 

The phase and magnitude information discussed in the previous section is available to
the DSP in memory locations 0 to 7. When the DSP performs a sequential read of the input
channels, the FPGA temporarily stops updating the data. This guarantees that the data from
each channel was obtained at the same time. The FPGA begins updating the data when the
DSP reads or writes any other location. The phase of each channel is given to the DSP
relative to the reference phase. As a result, the reference phase in register 6 is always 0. In
the event that the absolute phase of the reference signal is desired, it is available in register
12. The I and Q values for each input channel are available in memory locations 16 to 23.

The DSP sets the RF output by writing a desired phase and amplitude to registers 8
and 9. The FPGA automatically runs the new settings through its CORDIC routine and
produces corresponding I and Q values in locations 24 and 25. The I and Q values are sent

to the high-speed DAC to produce the RF output. When producing the output at 80 MSPS,

16

the FPGA uses a total of 8 samples, and therefore needs two sets of I and Q pairs. The
extra pair is produced by adding 225° to the desired output phase before passing it through
the CORDIC routine. The extra I and Q values are available in locations 14 and 15.

Six of the memory locations (26 to 31) are for an additional CORDIC routine. When
the DSP writes a set of I , Q, —I, and —Q values to registers 26 through 29, the FPGA runs
the CORDIC algorithm on the set of input data and produces a phase and magnitude pair in
registers 30 and 31. These registers are used when the DSP is measuring the transfer func-
tion of the cavity, to find the value of the phase shift and magnitude at each measurement
frequency.

The value of the digital attenuators is controlled by register 11. The digital attenuators
have six control bits, so the uppermost ten bits of this register are not used and are read as
0. A value of 0 corresponds to the minimum attenuation, and a value of 63 corresponds to
the maximum attenuation.

Memory location 10 shows the over-voltage status of each ADC and the status of each
interlock. Each ADC has a pin that is set high if the input voltage to the ADC is too high
to produce a valid reading. The over-voltage pins are connected to the 4 least significant
bits of register 10. If the digital attenuators are set up correctly and there is no malfunction
in the module, these bits will read 0. Bits 4 and 5 correspond to the reset signal and on/off
signal, respectively. During normal operation, these bits will both read 0.

There is one unused register, in location 13. It can be read from and written to by the

DSP, but currently does not perform any function in the FPGA.

l7

2.4 RF Output Creation

The input sampling process can be reversed to produce the RF output. Since the DSP
provides the output set points as phase and amplitude pairs, the FPGA first passes the set
points through the CORDIC routine to produce the I and Q values. Since it takes 400 us
for the FPGA to complete a single CORDIC conversion, and the FPGA is set up to con-
tinuously perform conversions on the values stored in the phase and amplitude registers, it
takes between 400 ns and 800 ns before a new setting affects the output. The —I and —Q
values are created by negating the I and Q values. The final step necessary before sending
the values to the output DAC is to convert them into the proper format. The FPGA repre-
sents numbers internally as 16-bit two’s complement numbers (-32768 to 32767), while the
DAC expects 14-bit straight binary numbers (0 to 16383). The FPGA converts each output
sample by complementing the most significant bit to put each sample into l6-bit straight
binary format and ignores the two least significant bits to shrink the number to the required
14 bits.

The FPGA passes the I/Ql—Il—Q values to the output DAC at 40 MSPS to produce
the RF output. The DAC produces a square wave, so the output is not made up of a single
frequency component; the output contains a 10 MHz signal and its odd harmonics (30
MHz, 50 MHz, 70 MHz, etc.) as shown in Figure 2.2. Since we only want the 50 MHz
signal to be present, the DAC output is passed through a 50 MHz filter, which attenuates
the unwanted frequencies.

Increasing the sampling rate of the DAC should provide both a better signal-to-noise

ratio and increase the power of the 50 MHz signal [15]. The output DAC supports sample

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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T
StatOHz Stop 100 iii-i2 StatOHz Stop 100MHz

Figure 2. 2. DAC output spectrum when producing output at 40 MSPS (left) and IF after 50
MHz band-pass filter (right).

rates up to 165 MSPS, but the current RF board design limits the DAC sample rate to
80 MSPS [16]. To create the RF output at 80 MSPS, we need to cycle through eight
samples, taken at 0°, 225°, 90°, 315°, 180°, 45°, 270°, and 135°. Four of these samples
(0°, 90°, 180°, and 270°) correspond to the I/Ql—Il—Q samples used when producing the
output at 40 MSPS. To produce the other four samples, the FPGA adds 225° to the desired
phase value and then sends the new phase and amplitude pair through the CORDIC routine.
Producing the RF output at 80 MSPS yielded an approximately 5.3 dB increase in power at
the intermediate frequency and approximately a 3.0 dB improvement in the signal-to-noise

ratio as shown in Figure 2.3.

2.5 Interlocks

The module has three external connections for safety interlocks: RF enable, fault, and

reset. All of the interlocks are TTL signals that are connected through the FPGA so that

19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

j; um 50.0 MHz mm 50.0 MHz
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sm 0 Hz Stop 100 MHz sun 0 Hz Stop 100 MHz

Figure 2.3. DAC output spectrum when producing output at 80 MSPS (left) and IF after 50
MHz band-pass filter (right). '

their behavior can be reconfigured if necessary. The module’s RF output must be disabled
unless the RF enable interlock is low. This is accomplished by tying the RF enable signal
to the power down pin on the high-speed DAC. The fault interlock is an output, which can
be used to signal the rest of the RF control system. It is currently unused, since the module
is not programmed to detect faults. If the module were to detect a fault, it would disable the
RF output, set the fault signal, and wait for a reset signal. When a rising edge is detected
on the reset input, the module will reset the fault signal, and enable the RF output (if the

RF enable interlock is low).

20

CHAPTER 3

Tasks Performed by the Digital Signal

Processor

The control processing is performed by a Texas Instruments TMS320C6414T fixed-point
DSP. It was chosen because of its high speed and available software tools. In the current
iteration of the module, the DSP is running at 360 MHz, but if more performance is required
in the future, the DSP clock speed can be increased to 1 GHz. Although all of the current
code is written in C and assembly, code can be generated from MATLAB using the Real-
Time Workshop Embedded Coder. This will allow control engineers using the module to

change control algorithms using tools they are familiar with.

3.1 DSP Peripherals

The DSP has two 4 MB flash EEPROM modules connected via the same memory bus
the FPGA uses. The first is an 8-bit wide memory divided into four 1 MB pages and
is used to store the programs. After reset, the DSP checks the status of two of the host
processor output pins to determine which program it should boot. Then, it sets the page

of the program ROM accordingly and loads the program into internal RAM. The second

21

module is 16 bits wide and is divided into two 2 MB pages. It is used as storage for large
lookup tables and any measurements that need to be stored in non-volatile memory, but
need to be accessed quickly. The current program stores a l6-bit sine lookup table and the
measured cavity transfer function in this ROM.

One of the DSP’s serial ports is connected to a Texas Instruments DAC8554 4-output
digital-to-analog converter. The DAC has a maximum sample rate of 200 KSPS on all
outputs [17]. Output A is used to produce driving signal for the cavity’s piezoelectric tuner,
and output B can be used to produce a slow tuning signal, which can be used to compensate
for slow drifts in the resonant frequency of the cavity. The other two outputs are currently
unused and are available for future applications. The cavity tuner signals are connected to
an operational amplifier to amplify their signals.

Although the DSP has 1 MB of internal RAM, an external 16 MB SDRAM is provided
in case future programs need more memory for their calculations. The SDRAM is 32-bits
wide and operates at 125 MHz.

The DSP printed circuit board also includes a temperature sensor to measure the tem-
perature inside the module. It is used as a status indicator to signal if the module is not

getting enough airflow to prevent overheating.

3.2 Control Program Overview

The control program is set up as a multi-threaded program; with each thread being triggered
by a different hardware or software interrupt as necessary. Higher priority interrupts are

allowed to preempt lower priority threads. Receiving a data word from the host processor

22

triggers the highest priority thread. The main control thread has the second highest priority,
and is triggered by a counter, so that it runs at fixed intervals. The final hardware—triggered
thread runs much less frequently than the other two, and does some low-priority status
calculations. The threads triggered by software interrupts are used for routines that take a
long time to perform and need to be done outside the hardware interrupt threads to prevent

them from missing their deadlines.

3.3 Data Received From Host Processor

The serial connection between the DSP and host processor is full duplex and uses the same
clock and synchronization signals for data traveling in both directions [18]. This means‘that
the DSP must have data buffered and ready to transmit back to the host processor when
the next word is received, because data is transmitted simultaneously in both directions
as shown in Table 3.1. If the DSP is unable to respond to a command before the next
command is received, incorrect data could be displayed on the user interface, so the thread
that processes host commands was given the highest possible priority. This guarantees that
the DSP will finish processing the current command and have a response ready for the host
processor before the next command is received.

Each data word sent between the DSP and host processor is 32—bits, and is sent most
significant bit first over the host processor’s SPI port. Each command from the host is
broken into three parts: the first bit is a 0 for a write and 1 for a read (this bit is ignored
for read-only registers), the next 15 bits are a register address, and the last 16 bits are an

optional argument. The exception to this format is when the host is sending a new program

23

Table 3.1. Responses from the DSP are received by the host two words after the command
was transmitted. ~

 

 

 

 

 

 

 

 

 

 

Transmission Word Command to DSP Response to DSP
1 Command 1 Null Response
2 Command 2 Null Response
3 Command 3 Response 1
4 Command 4 Response 2
5 Command 5 Response 3
6 Command 6 Response 4
7 Command 7 Response 5
8 Null Command Response 6
9 Null Command Response 7

 

 

 

 

 

to the DSP. In this case, the host initiates the transfer by writing the program number and
block number to register 0x0102, and then it sends a 64 kB block of the new program to
the DSP. After the block of data is done being programmed, the host processor repeats the
process for the remaining blocks (if necessary).

The DSP response format varies depending on the command it has received. If it re-
ceives a command to update a setting, it echoes back the setting to acknowledge that the
setting has been updated, or in cases where the setting cannot be changed, the DSP replies
with — 1. If the host processor reads a register, the DSP simply sends back the value of that
register in whatever format it uses for calculations; the host must then convert the value to

a meaningful format before sending it to the GUI.

3.4 Control Thread

The control thread has the second-highest priority. It runs at fixed intervals based on one

of the DSP’s internal timers. In the current setup, this thread runs 16,387 times per second,

24

but the timer can be modified to run at virtually any interval. The primary tasks for this
thread are to perform the phase PID, amplitude PID, and adaptive feedforward cancellation
(AFC) algorithms. Additional lower priority tasks are performed by other threads.

The control thread begins by reading the phase and amplitude of each input channel
from the FPGA. It also stores the I and Q values of the cavity output in a buffer so that a
fast Fourier transform (FFT) can be computed. If the FFT buffer is full, this thread posts
the software interrupt that initiates calculation of the FFT. The FFI‘ is used to identify
low frequency (0 to 1000 Hz) sinusoidal disturbances affecting the cavity. Next, if a user
is tuning the PID parameters and has pulsing enabled, the thread takes care of switching
between the two phase or amplitude set points. After this is done, the thread runs the PID,
cavity transfer function measurement, and AFC algorithms (if enabled) and updates the
output phase and amplitude and sets the fast tuner. The cavity transfer function cannot
be calculated correctly if either PID or AFC control is enabled, so logic is implemented
to prevent them from being enabled at the same time. This is because the cavity transfer
function algorithm assumes the cavities RF input has constant amplitude and phase, and it

uses the fast tuner output to shake the cavity.

3.5 Status Thread

The final hardware thread runs much less frequently than the other two, and performs some
low-priority tasks. It is triggered by a read from the ADC connected to the temperature
sensor on the DSP’s circuit board. The read occurs at the maximum possible interval al-

lowed by the DSP’s serial port hardware. This thread calculates the board temperature in

25

Celsius and the average DSP load over the previous interval and stores the values until the

host processor requests them.

3.6 Software Interrupts

There are several threads that are implemented as software interrupts. They are used to
perform tasks that take a long time to run and are not time critical. If any of these tasks were
implemented within the hardware threads that initiate them, the hardware thread would fail
to complete in its allotted time.

The highest priority software thread is the one that computes an FFT on a set of complex
data samples. It is based on the DSP_fft16x32 function included with the DSP program-
ming tools [19]. The function computes an FFT on 32-bit complex data samples and uses
a l6—bit “twiddle factor” look-up table to speed up processing. There are two versions of
this function included with the DSP programming tools. The first is a hand-optimized as-
sembly language version that is extremely fast, but is not interruptible. The second is an
implementation of the same algorithm written in C. Although the C version is not as fast as
the optimized version, it is interruptible. and is therefore the better choice for this system.
The FFT has complex output, but we are only interested in seeing the magnitude response
in the GUI, so as a final step, the FFT thread runs a 32-bit CORDIC routine on the complex
FFT output to find the magnitude for each frequency. The output is saved until the host
processor reads it and initializes the next FFT calculation.

The last two threads are used to program memory into the flash EEPROMs that are

connected to the DSP. One thread programs the measured cavity transfer function into

26

ROM, so it is not lost at reset or power down. The other thread programs a 64 KB block of
the program ROM. Although these threads have almost no calculations in them, they take
the longest to complete. Before programming a ROM, the corresponding memory block
must be erased, which typically takes around 800 ms. Then, each word can be programmed
at a typical rate of approximately 10 ,us [20]. As a result, the time spent in these threads is
mostly spent in an idle loop, polling the ROMS to find out when they are ready for the next

word to be programmed.

27

CHAPTER 4

Control

4.1 RF Amplitude and Phase Control

Cavity control is typically done using a PI controller, so a PID control was implemented to
c0ntrol the RF output, using feedback via the controller’s cavity input. The DSP program
allows separate PII) control of the phase and amplitude of the signal, and some other tools
have been included in the GUI to ease the PID tuning process. When operating at RF
frequencies near a cavity’s resonant frequency, the cavity behaves approximately linearly,
so we can model the relationship between the RF driving signal and the cavity output using
a transfer function. Figure 4.1 shows the closed-loop system. During operation, the RF
frequency is fixed, but the amplitude and phase can be adjusted. Therefore, the system
input and output are complex numbers. Since the system has a pole at s = O, the system. is
type 1 and values can be chosen for kp, ki, and kd to ensure the system response to a step
input has zero steady-state error [21].

The transfer functions of the cavities being controlled vary dependent on the cavity
type and amplifier system used, so the PID parameters must be tuned when equipment is
changed. This tuning has historically been done by manually turning the RF output on

and off, measuring the system response, and adjusting the PID parameters as necessary.

28

complex complex

set point ' kps+kt+kasz output

controller plant

 

 

a}

 

 

 

 

Figure 4.1. Block diagram of PID control. The cavity behaves linearly when operating near
its resonant frequency, so it can be approximated by the transfer function, G(s).

The DSP speeds up this process by automatically stepping between two set points and
displaying the step response in the GUI. As the users change the PID parameters, they can
immediately see the change in thesystem response. The PID loop compensates for small

non-linearities and slowly varying drifts.

4.2 Cavity 'Ihning

We expect that most disturbances, not controlled by the P11) alone, that will affect the
cavities in the reaccelerator will be of the narrowband sinusoidal variety and due to rotating
machinery, such as vacuum pumps. In order to cancel out these disturbances, the adaptive
feedforward control developed by Tarek Kandil [22] was implemented in this module. The
DSP is programmed to cancel disturbances at up to 10 frequencies. A block diagram of
a single-frequency control is shown in Figure 4.2. GT(s) is the transfer function from the
cavity tuner output to the phase error seen in the cavity output signal. The tuner has the
affect of shifting the cavity resonant frequency, which results in an error in amplitude and

phase as seen by the controller. When operating at RF frequencies near the cavity resonant

29

 

 

 

 

(‘os(wt+ 0)

uuuplier Integrator Multiplier

 

Estimated noise signal

 

Figure 4.2. Adaptive feedforward cancellation control for the cancellation of a single sinu-
soidal disturbance [22].

frequency, a given change in tuner output has a relatively large effect on the phase error
compared to its effect on the amplitude error, so the phase error is used for the adaptive
feedforward cancellation algorithm.

The disturbances we expect to encounter are made up of multiple sinusoidal signals:

d = ZAisin (coit +13.) déf 2 aicos (am) + bisin (am) (4.1)
i=1 '—

1—1

Before the adaptive feedforward cancellation algorithm can be applied, we need to know
the frequency of the disturbance to be cancelled and the phase of GT(s) at that frequency.
To calculate the phase of GT(s), we start with the RF amplitude and phase set to fixed
values (PID disabled), and drive the tuner while measuring the cavity response. The tuner is

driven in 1 Hz increments from 1 Hz to 1 kHz, and the magnitude and phase response of the

30

cavity phase error is measured at each frequency. The measured Bode plot is representative
of the system transfer function, GT (3). The plot is stored in non-volatile memory so it is not
necessary to calculate it every time the controller is powered down or reset. The disturbance
filters use this information from the measured Bode plot to stably apply the feed-forward
algorithm. The value of each a),- is determined by performing an FFT on the cavity error
signal \y and looking for the frequencies with the highest magnitudes. However, a,- and b,-
are unknown, and must be estimated. We estimate these two parameters by multiplying the
error signal by a gain factor and two orthogonal signals of known phase and then integrating

the results. The control output is then created from the estimated values as:

def

u = dicos (wit) + 1318i" (Cort) =

IMF-3
M:

l

. Aisin ((0.1 +13.) (4.2)

l

—

As long as the measured phase delay 0 is within 90° of the actual phase delay and 'Y is
chosen sufficiently small, the estimated values 5,- and 13; will converge to the actual values
a,- and bi, as shown in Chapter 3 of [22]. 7 controls the rate at which the estimated param-
eters adapt to changes in the actual values, so increasing 7 can cause the control to also
dampen disturbances that are close in frequency to 0),- [23]. This occurs because the large 7
allows the adaptive parameters to continuously change phase to match the frequency of the

disturbance, even though it is not the exact frequency the algorithm is set up to cancel.

31

CHAPTER 5

The ZWorld RabbitCore Host Processor

and Graphical User Interface

The ZWorld RabbitCore 3200 microprocessor acts as the host processor for the module.
The RabbitCore 3200 was-selected because of the large amount of code already developed
for it for other systems at the NSCL, but any other processor that supports the serial periph-
eral interface (SP1) protocol and has a sufficient number of I/O pins could be used instead.
The host performs initial chip configuration for all the integrated circuits used in the mod-
ule. After configuration is complete, the host processor acts as an interface between the
GUI and the DSP. It forwards commands received via its network interface to the DSP
and passes data received from the DSP over Ethernet back to the GUI. In addition, it also

supplies an interface based on the Modbus protocol to the main EPICS control system [8].

5.1 Module Initialization

After the system powers up, the host processor must initialize all of the other chips in the
module. Most of this is done using the SP1 before data transfer can begin. The high-speed

ADCs must be set from test mode to normal operating mode, and the phase-locked loop

32

must be set to the correct multiplier value. The SPI interface is also used to program the
FPGA. The RabbitCore module contains a large enough flash ROM to hold both its code
and the FPGA’s code in compressed format, so it is not necessary to download the FPGA
code every time the module is powered up.

After the first three initialization steps are completed, the SP1 is used for transmitting
commands and data between the host processor and the DSP. The DSP has its own non-
volatile memory for program storage, so the host processor does not need to send the DSP
its program at startup as it does with the FPGA. The DSP is set up to select between up to .
four programs when it is reset to make testing and debugging easier. When modifications
are made to the DSP program, the new code can be downloaded without erasing the previ-
ous versions. Programmers can then quickly switch between different versions of the code
to verify that bugs in one version are not present in others. In its initial boot stages, the
DSP checks the status of two of the RabbitCore’s output pins to determine which program

to load.

5.2 User Interface

After module initialization is complete, the host processor’s primary task is to act as an
interface between the user and the DSP. It passes user commands to the DSP using its SPI
interface and passes data back to the user. Unlike previous versions of this project, which
used a telnet interface, this version has a graphical user interface. It was written in QT so
that it will compile and run on all major operating systems [24]. The GUI is much easier

to use than the older telnet interface, since the user no longer needs to memorize all of the

33

commands. The GUI also has much more functionality, since it can display graphs of the

input, cavity transfer function, and FFT of the cavity output.

5.3 Main Screen

A screenshot of the main controller screen is shown in Figure 5.1. The top part of the
screen shows the amplitude and phase of each input channel. The phase is shown relative
to the reference channel, and the reference phase is always shown as 0.

Below the input status is the attenuator setting. It accepts values between 0 dB and
63 dB. For maximum measurement accuracy, the attenuator should be set to a value that
allows the inputs to be as close as possible to 2.3 V without going over.

Below the attenuator box are the RF output control settings. In the open-loop mode, I
and Q values are calculated from the phase and amplitude set points and are sent directly
to the high-speed output DAC. In the closed-loop mode, a PID control algorithm is used to
set the cavity output to the desired settings. The phase and amplitude controls can be set to
open-loop or closed-loop independently of each other.

The two graphs on the bottom show the CPU load for the DSP and the ZWorld host
processor. The DSP load should appear fairly constant, with the exception that it will spike
to 100% when calculating an FFT or writing data to a ROM. The spikes are normal and will
not affect the ability of the DSP to run the control algorithms, because the control thread
has higher priority than the other threads and will interrupt them as necessary.

The ZWorld Save button saves the current settings as the defaults to load after a power

up or reset. The settings include all settings on the main screen, PID screen, and AFC

34

   

 

I Rf Momtor and Control (PHCTLR_TEST) - It'll]
fie
Hun (Bum-g uln)44 » ~74. ,. WV. , , ~ W.» ~74.-. .. .,_‘-,_*__

m Flue
...... ___|.........
m... 6.....- I
...... ......___ I
num- (....-. l

 

 

 

 

rSM-Load4444 eme-_iA ,_._
osnnaaz 7|“ 152

l
l
2mm: llllllll " an

 

 

 

Figure 5.1. Main controller screen.

35

 

 

screen, with the exception of the RF On/Off status. The RF is always off by default after
power up. The ZWorld Reload button returns all settings to their defaults without resetting
the system. The ZWorld Reset and DSP Reset buttons allow individual resets of the ZWorld
host processor and DSP. The DSP Reset button also allows the user to select which program
to run on the DSP. The DSP can hold four different programs in separate pages of its
program ROM. This allows new DSP code to be downloaded to the DSP’s program ROM
without overwriting the previous version of the program. If there is a problem with the
new program, the DSP'canbe reset and told to reload the old version without putting the -

module into an unusableivstate. The rest of the buttons open screens discussed below.

5.4 PID Screen

The PID tuning screen was designed to ease tuning of the PID control loops by making
it possible to see the system response in real-time as the control parameters are modified.
The phase and amplitude PID control constants can be tuned independently of each other.
To see the response of the cavity, the user simply has to set a nominal and pulsed value
and click the run button to start stepping between the two set points. The controller will
automatically step between the two set points and the GUI will show the step response.
The stepping frequency can be changed to affect how much of the waveform appears on
the screen at a time. Figure 5.2 shows the amplitude PID being tuned. It is best to turn off
the AFC algorithm when tuning the PH) parameters, because the error signal affects both
the PID and AFC algorithms. Although the DSP code was written to minimize the effect

of the step signal on the AFC algorithm, there is still some ringing produced by the tuner if

36

 

 

 

 

 

 

Juli-4% 44—4 4 4
[. l.___ .. .___ ._ .~_,_ .__._.. -.
1 nap-Inna [hi mm ”b m l
. Ian—I [ 0.0000 an. an E
uni-I- I 0&5 no. In .I
(I; .:f:h+;._'_:nf;_f:Tg,z .3 W“... MW 1
l III-u 2300 a. |

 

3"...77 H
W F 0.5000 mum . , I
Inn—l I“ _ 0.0000 .0.- 1.. l

: nun-nu l 0.0000 9.0.11: 3

 

 

 

 

Figure 5 .2. PID tuning screen.

it is enabled while tuning the PID parameters.

5.5 AFC Screens

There are three main parts of the AFC screens, the FFT magnitude plot, cavity transfer
function, and the AFC cancellation screen. The DSP measures the cavity transfer function
by outputting a sine wave on the cavity tuner and measuring the cavity’s response. The
tuner output is swept from 1 Hz to 1 kHz to produce the graphs shown in the GUI. The

cavity transfer function is also stored in non-volatile memory to prevent it from being lost

37

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5.3. AFC screen.

during a reset. Automatic disturbance detection and cancellation has not been implemented
yet, so it is up to the user to identify the frequencies at which disturbances are occurring.
This is done by finding peaks on the FFT magnitude plot and entering their frequency
into the AFC Cancellation Frequency box. The DSP automatically loads the previously
calculated cavity phase delay for that frequency, and when enabled, outputs a disturbance
cancellation signal at the selected frequency. Up to 10 frequencies can be enabled at a once.
There are master enable and disable buttons for the tuner, which can be used to enable or

disable the tuner without having to manually select every cancellation frequency.

38

 

Figure 5.4. FFI‘ screen shows FFI‘ of cavity output in dBm, cavity magnitude response,
and cavity phase response in degrees. All plots show 0 to 1000 Hz linear scale.

39

 

 

 

 

 

 

 

 

 

 

Figure 5.5. Startup screen.

5.6 Startup Screen

The module has a start—up mode, where its RF output gradually ramps to its set point after
I enabled. The user can specify an initial RF output level, the amount of time to stay at that
level, and a ramp time to the amplitude set point. This feature allows the RF system to
tune-up gradually before going full-scale and removes the initial overshoot that will occur

if the PID parameters are under damped.

5.7 Advanced Screen

The Advanced screen contains features that are not used during normal operation. This
screen contains buttons for downloading a new DSP program and calibrating the input
channels. Program download is done over Ethernet, and can be done without affecting
the program currently running on the controller. The DSP’s program ROM can contain up

to four independent programs, so a new program can be downloaded without overwriting

40

   

I Advanced

192168125131

 

 

 

.22.]

 

 

Figure 5.6. Advanced screen.

the one that is being run. When a program is being sent to the DSP, the GUI screens will
temporarily stop updating, and commands sent via the GUI will be queued, but the module
will continue to run as normal. When the download completes, GUI updates will resume
and any queued commands will be sent to the module.

The channel calibration button will run a software routine that attempts to remove any
constant phase or amplitude measurement errors between the three input channels, when it
is implemented. These errors are primarily caused by slightly mismatched impedances on
the input channels on the PCB, which prevent the amplifiers and attenuators from perform-
ing ideally. These variances cause each of the input channels to have a slightly different
level of gain, which results in a fixed error factor between channels. Similarly, the digital
attenuators do not attenuate in exact 0.5 dB steps, so at different levels of attenuation the
amplitude error may vary. Also, during testing, a very small amount of phase error was

measured depending on the attenuation setting for the digital attenuators.

41

CHAPTER 6

Testing and Performance

6.1 Cavity Simulation Circuit

SRF cavities are rarely available :forttesting purposes, so I built a test circuit to simulate
a cavity with a known transfer function and known disturbances. A block diagram of the
simulation circuit is shown in Figure 6.1. The test circuit has inputs for a disturbance
signal, tuner signal from the LLRF controller, and the RF output from the LLRF controller.
The disturbance signal and tuner signal are added together with a fixed DC voltage offset
after the tuner signal passes through a transfer function block. The transfer function is
designed to simulate a mass-spring model of the tuner arm. The DC offset is necessary to
prevent the simulated disturbance signal from changing signs before it is multiplied with
the RF signal, since a sign change would result in a 180° jump in phase of the output
signal. In a real cavity, the disturbances cause the cavity resonant frequency to shift away
from the driving frequency, in both amplitude and phase error. The phase error is typically
used for disturbance identification, because it is relatively large compared to the amplitude
error. The changes in phase cannot be easily modeled in a test circuit, so the test circuit
simply performs amplitude modulation by multiplying the RF signal with the sum of the

disturbance and tuner signals and the amplitude error is used for disturbance identification.

42

 

 

 

 

 

Figure 6.1. Block diagram of circuit used for cavity simulation. The two transfer functions .
are replaceable RC networks.

After modulation, the RF signal passes through another transfer function block before being -
amplified and sent back to the LLRF controller.

In order for the controller to perform the adaptive feedforward algorithm described in
Section 4.2, it must be able to accurately calculate the phase response of the cavity. To test
this, several different transfer function models were placed in the circuit, and MATLAB
was used to calculate the phase response of the system. Each transfer function module
consists of an RC network as shown in Figure 6.2.

By defining x1 as the voltage across capacitor C1 and x2 as the output voltage, we can
write the circuit’s state equations [25]:

. _ u4x1 x14x2

, _ 6.1
M ClR] C1R2 ( )

 

43

Output

 

 

C2

Figure 6.2. Each of the transfer function blocks is made up of a replaceable RC network.

. x1 412

 

 

_ 6.2
X2 C2R2 ( )
y = x2 (63)
The state model is then:
R “R .1 .21.
x, : C1R1R2 CIR] x+ C1R1 u (6.4)
1 441 0
6R; (3sz
y = [ o 1 ] x (6.5)
This leads to a transfer function of:
l
H (s) (6.6)

: C1C2R1st2 +(C1R1+ C2R1+C2R2)s +1

Using this information, MATLAB can calculate the ideal phase response of the ampli-

tude error of the circuit, which can then be compared to the phase response of the amplitude

A ./.

error as calculated by the LLRF controller. The LLRF controller calculates the phase re-
sponse of the amplitude errorvsignal'by slowly sweeping its fast tuner output from 0 Hz to
1 kHz. For each frequency, it records the incoming RF amplitude at four points, spaced
90 degrees apart, from which it can calculate the phase and magnitude response. During
cavity sweep, there is assumed to be no disturbance and (01 is much smaller than (DRF, so

the Circuit’s output can be approximated as:

VOut = (Arsin (037) Gr (1017‘) + VOffset) ARFSin (GORE) 02 (ijF) (6-7)

Since (07 is much smaller-than amp, the tuner component can be viewed as a scaling con-
stant on the RF signal, and the tuner input will cause a sinusoidal error in the amplitude
of the RF output. Therefore, for the test circuit, C;- (Figure 4.2) can be approximated by
G 1 (s). Figures 6.3 and 6.4 show the ideal amplitude and phase response and the response
calculated by the LLRF controller in the presence of the disturbances it will attempt to
cancel. The phase plots match very closely, with the calculated plot staying within approx-
imately five degrees of the ideal plot for frequencies below 500 Hz and within ten degrees
for frequencies between 500 Hz and 1,000 Hz. The saw tooth pattern seen in the plot cre-
ated by the LLRF controller starting at about 600 Hz is an artifact of algorithm used to
calculate the phase. To speed processing and make sure there were no errors in the original
implementation of the phase calculation algorithm, the algorithm was implemented using
integer intermediate values, instead of floating point variables. Although the phase calcu-
lation is accurate enough for the AFC algorithm to work, it can be made more accurate by

using more precise intermediate results or filtering the output data to produce a smoother

45

 

 

LA

 

106750077500“ 400 566 ’6007700‘360‘0606666
Frequency (Hz)

 

 

 

 

1002003004005006007008009001000
FnequencyO-tz)

Figure 6.3. Ideal magnitude response (top) and magnitude response calculated by LLRF

controller (bottom).

curve; so later versions of the DSP code will be modified to do so.

After verifying that the cavity transfer function calculation was accurate enough to work

with the AFC algorithm, the controller was tested with known disturbances. In testing, the

AFC algorithm was able to reduce the effect of disturbances to the noise floor with an
appropriate value of the adaptation gain 7, regardless of the amplitude of the disturbance.
Increasing the value of 7 improves the effectiveness of the AFC algorithm by allowing the

estimated parameters to converge faster to the actual parameters (Figure 6.5), but setting 7

46

 

Phase (degrees)
8

 

 

1002003004005006007008009001000

quuency (H2)

 

 

Phase (degrees)

 

 

100200300400500600700000'9001000
Frequency(Hz)

Figure 6.4. Ideal phase response (top) and phase response calculated by LLRF controller
(bottom). -

47

too high can cause instability, so its value must be chosen carefully. The spikes seen at 189
Hz, 378 Hz, and 568 Hz are caused by some unterminated digital connections within the

controller. Those connections will be fixed in the next update of the circuit board.

48

 

Magnitude (dBm)

 

60100200 300400 500 600 700 0009001000
Frequency (Hz)
N o disturbance cancellation

 

 

Magnitude (cl Bm)
t:

l'Ile “”1””1.‘ 1lIilI ll]! '11 P"; iluI‘lj il‘IIi’ll ‘11}, iI,

if“ 'lllll lll‘h ll "l_. IIGOJII 11%|.”in
"'100200300400500 0009001000
quencHHZ)

AFC cancellation at 60 Hz, 7 = 0.125. Disturbance power is reduced to T0 of its original level.

_6..

 

Magnitude (dBm)
é:

Uni .1“; .l‘lh.lll‘ IlII: ‘tlr. ,u. III [21.5.11 1‘" 1"", I,

115 [llllllll‘lun‘ ‘1.I l . : lll

100 200 300 400 500 GOOI 700 800 9001000
FrequenCHHZ)

AFC cancellation at 60 Hz, 7: 0.25. Disturbance power is reduced to 313 of its original level.

Figure 6.5. FFT of RF input with 60 Hz sinusoidal disturbance. Because the magnitude of
the disturbance is large. its third harmonic is also present.

49

CHAPTER 7

Conclusion and Future Work

7 .1 Conclusion

A new prototype LLRF controller has been created for use with high-Q superconducting
cavities. In addition to the digital PID amplitude and phase control provided by typical
LLRF controllers, the new prototype implements an adaptive feedforward cancellation al-
gorithm for microphonics mitigation with a piezoelectric tuner, and is the first LLRF con-
troller to do so. Microphonics mitigation is necessary, because the narrow bandwidth of
high-Q cavities allows microphonics to perturb the resonant frequency of the cavity too far
for the PID feedback control alone to Work.

Testing was done to make sure that the AFC control does not conflict with the LLRF
amplitude and phase control, and there were no conflicts during normal operation. How—
ever, during PID tuning the AFC can make it difficult to select the correct parameters.
During PID tuning, the RF output steps between two set points so the system response can
be seen. If the AFC control is enabled when tuning, it also tries to compensate for the
error, since the step function has components at all frequencies. The result is what appears
to be some ringing after each set point transition. Although steps were taken in software to

minimize the effect on the AFC algorithm, it is currently not possible to completely prevent

50

the change in output set point from affecting the AFC algorithm.

7 .2 Required Changes

Although the LLRF controller was shown to work in testing, there are several modifications
that need to be made to the DSP daughter card before the module is ready for production.
The biggest problem with the current version of the circuit board is that it runs very hot.
The DSP and its voltage regulator are both designed to dissipate heat through the circuit
board. However, the circuit board is simply not large enough to get enough airflow for
the heat generated. On the prototype, heat sinks were added to the DSP and the voltage
regulator to attempt to solve the problem. The heat sink on the DSP was able to sufficiently
cool it, but there is not enough surface area on the top of the voltage regulator to add a
sufficiently large heat sink to it. In order to solve the cooling problem, the DSP daughter
card must be increased in area, and the voltage regulator should be moved farther from the
DSP, since those two ICs produce almost all of the heat on the board.

In addition to the cooling problem, there were several minor errors made in the board
schematic that made their way into the board layout. There were three pull-up resistors on
the control lines for the DSP external memory interface that were mistakenly connected
to ground instead of +3.3 V. Also, when programming the EEPROMs, it was found that
it is better to let the software check the status of the EEPROMs during program and erase
than to use the hardware control pins, so the busy pins should be disconnected from the
EEPROMs.

Finally, DIP switches should be added to make it easier to change DSP hardware set-

51

tings. Switches should be added for the following settings: DSP clock multiplier, JTAG

mode, DSP endian mode, DSP boot mode, SDRAM clock select, EEPROM and FPGA

clock select, and default program.

7 .3 Future Hardware Upgrades

During software development, several potential changes to the hardware were identified
that would help improve data flow within the module as well as make sure that parts are
available in the future. The FPGA currently used in the module is a Xilinx Spartan-II,
which is an older model, which is not as fast and does not have as much logic as the newer
Spartan-3 and Spartan-3E FPGAs. The Spartan-H will likely be phased out in the next few
years, so it will be a good idea to migrate to the newer model.

Several signal routing changes could be made to the module to improve device utiliza-
tion. There is an 8-pin DIP switch used to set the device address. In the current version,
it is connected through the FPGA to the host processor. By connecting the DIP switch di-
rectly to the host processor, 16 FPGA I/O pins would be freed. By connecting these pins to
the DSP to change its interface from 16 bits to 32 bits wide, the data throughput would be
doubled. Currently, the DSP and host processor both have a free serial port, which could
be connected to each other. The addition of a second serial connection between the de-
vices would allow the large block data transfers (program download, FFI‘ plot, etc.) and
the control commands to be sent on different serial ports. Doing so would remove the lag

in response to user commands during block transfers, since the host processor would no

longer have to wait until the block transfer finishes to send the command.

52

The pass band of the RF output filter must be chosen based on the operating frequency
range of the module. The current version of the RF circuit board accepts filters in the
YY161 surface-mount package, but for higher frequencies there is not a very good selection
of available filters. As a result, for some applications, it is necessary to add an external filter
on the output to get adequate filtering. By changing the board layout to accept filters in a
more common package, the need for external filters can be eliminated for the whole range

of frequencies the module is designed to work with (2 MHz to 1.5 GHz).

7 .4 Future Software Upgrades

In future versions of the LLRF control, the PID feedback control will be combined with
a feedforward control to improve the system response. This will allow higher gain PID
parameters to be used to improve accuracy without affecting the stability of the system.
In addition, integrator anti-windup will be implemented to prevent the system output from

saturating.

53

APPENDICES

54

APPENDIX A

FPGA Implementation of a CORDIC

Algorithm

/*******************************************************************t/

/* CORDIC section (written in Verilog) */
/* */
/* A 16—bit CORDIC routine is used to convert sampled I/Q values */
/* for each input channel to phase/magnitude (’A' registers). A */
/* second implementation operates in the reverse direction to */
/* convert the desired output phase and magnitude to I/Q (’O' */
/* registers). */

/********************************************************************/

// Counter to keep track of stage of routine
reg [3:0] ctr;

// Phase look—up table

// Each bit is 360 / 65536 degrees

wire [14:0] lut;

wire [15:0] lutn; // Negative of look—up table
assign lutn = -lut;

ROM16X1 #(.INIT(16’h8000)) lut14 (.O(lut[141), .A0(ctr[O]),
.A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3]));

ROM16X1 #(.INIT(16’hOOOl)) lut13 (.O(lut[13]), .A0(ctr[0]),
.A1(ctr[1]), .A2(ctr[2]), .A3(ctr[3]));

ROM16X1 #(.INIT(16’h0002)) lut12 (.O(lut[12]), .A0(ctr[0]),
.A1(ctr[l]), .A2(ctr[2]), .A3(ctr[3]));

ROM16X1 #(.INIT(16'hOOO4)) lutll (.O(lut[ll]), .AO(ctr[O]),

55

.Al(ctr[1]), .A2(ctr[2]),

ROM16X1 #(.INIT(16’h0008)) lutIO (.O(lut[10]),

.Al(ctr[1]), .A2(ctr[2]),

.A3(ctr[3]));

.A3(ctr[3]));

ROM16X1 #(.INIT(16'h0012)) lut9 (.O(lut[91),

.Al(ctr[1]),‘.A2(ctr[2]),
ROM16X1 #(.INIT(16’h002C))
.Al(ctr[1]), .A2(ctr[2]),
ROM16X1 #(.INIT(16’h0056))
.Al(ctr[1]), .A2(ctr[2]),
ROM16X1 #(.INIT(16’hOOA6))
.Al(ctr[1]), .A2(ctr[2]),
ROM16X1 #(.INIT(16’h0146))
.Al(ctr[1]), .A2(ctr[2]),
ROM16X1 #(.INIT(16’h028C))
.Al(ctr[1]), .A2(ctr[2]),
ROM16X1 #(.INIT(16’h0514))
.Al(ctr[1]), .A2(ctr[2]),
ROM16X1 #(.INIT(16’hOA22))
.Al(ctr[1]), .A2(ctr[2]),
ROM16X1 #(.INIT(16’h1474))
.Al(ctr[1]), .A2(ctr[2]),
ROM16X1 #(.INIT(16'h79DC))

.A3(ctr[3]));
lut8 (.O(lut[81),
.A3(ctr[3]));
lUt7 (-O(lUt[7])I
.A3(ctr[3]));
1Ut6 (.O(lUtl6])I
.A3(ctr[3]));
lut5 (.O(lut[5llr
.A3(ctr[3]));
lut4 (.O(lut[41),
.A3(ctr[3]));
lut3 (.O(lut[31),
.A3(ctr[3]));
lut2 (.O(lut[21),
.A3(ctr[3]));
lutl (.O(lutllllr
.A3(ctr[3]));
lutO (.O(lut[01),

.AO(Ctr[O]),

.AO(ctr[O]),

.A0(ctr[0]),

.A0(Ctr[0]),

.AO(ctr[O]),

.A0(Ctr[0]),

.A0(ctr[0]),

.A0(Ctr[0]),

.A0(ctr[0]),

.AO(ctr[0]),

.A0(ctr[0]),

.Al(ctr[1]), .A2(Ctr[2]), .A3(ctr[3]));
// Input I and Q read from high-speed ADC
reg [15:0] AI, AQ;

// Input registers written by DSP
reg [15:0] Op, Oa; // Output phase and amplitude

// CORDIC outputs
reg [15:0] Ap, Aa;
reg [13:0] OI, OQ;

// Input phase and amplitude
// Output I and Q

// Intermediate values

reg [15:0] AI2;

reg signed [15:0] AQZ;

reg [15:0] Ap2;

reg signed [15:0] 012, 002;
reg [15:0] Op2;

// Possible values for first stage of CORDIC routines
wire [15:0] All;

wire signed [15:0] AQl;

wire signed [15:0] 001;

56

// Possible values for stages 2-16 of CORDIC routines
wire [15:0] AI3;

wire signed [15:0] A03;

wire signed [15:0] 013, 003;

// First stage depends on the sign of the input Q value
assign A11 = AQ[15] ? -AQ : AQ;
assign AQl = AQ[15] ? AI : —A1;

// First stage depends on the sign of the input phase
assign 001 = 0p[15] ? —0a : 0a;

// Stages 2-16 depend on the sign of the intermediate Q value
assign A13 = AQZ[15] ? (A12 - (A02 >>> ctr))

(A12 + (AQ2 >>> ctr));
assign A03 = AQZ[15] ? (A02 + (A12 >> ctr)) : (A02 - (A12 >> ctr));

// Stages 2— 16 depend on the sign of the intermediate phase value
assign 013=0p2[15] ? (012 + (OQ2 >>> ctr))

(012 - (002 >>> ctr));
assign 003 = 0p2[15] ? (OQ2 — (012 >>> ctr))

(002 + (012 >>> ctr));

always @(posedge clk400ut)
begin
ctr <= ctr + 1;

// First stage: shift input +90 or -90 degrees
// First stage occurs when counter = -1
if (&Ctr)
begin 6
A12 <= A11;
AQZ <= AQl;
Ap2 <= AQ[15] ? lutn : lut;
OIZ <= l6’h0000;
OQ2 <= 001;
Op2 <= Op[15] ? (Op + lut) : (Op + lutn);

// Store completed conversion values from last clock cycle
Ap <= Ap2;
Aa <= A12;

// Store completed conversion values from last clock cycle
01 <= 012;

57

00 <= 002;
end

// stage 2—16: perform shift and update intermediate registers
else
begin

A12 <= AI3;

A02 <= A03;

Ap2 <= A02[15] ? (Ap2 + lutn) : (Ap2 + lut);

012 <= 013;
002 <= 003;
Op2 <= Op2[15] ? (Op2 + lut) : (Op2 + lutn);
end I
end

58

APPENDIX B
DSP Daughter Board Schematics

59

Jl

 

 

 

 

 

 

 

 

 

 

ROM/FPGA Interface
Sheet4.SchDoc

 

 

BAI

 

8A2

 

8A3

 

BA4

 

BAS

 

R/~W

 

BDO

 

BDl

 

BD2

 

 

 

 

 

BD3

 

BD4

 

BDS

 

BD6

 

BD7

 

BD8

 

 

 

 

 

BD9 BOOT_PAGEO

 

 

C
8010 BOOT_PAGEI C
C

 

BDl l PROG_PAGE

 

 

BDlZ

 

BDl3

 

BDl4

 

BDlS

 

~BCEO

 

 

 

l O ~RESET

 

 

 

 

 

 

 

 

 

 

Power/Clocks

~ Sheet] .SchDoc

5 NM]
~RESETAECLKIN D

 

 

 

 

”S 1

SW-

SPS'li‘
DSP GPIO/Serial
Sheet3.SchDoc

 

 

 

 

....____..._._1

 

 

D scum PROG_PAGE D—
on BOOT_PAGEI

 

 

 

 

 

 

 

 

 

 

 

 

:> DRO BOOT_PAGEO
D DSPEN

:) CLK40

 

 

 

 

DSPGPlv

 

 

DSPGP2

 

DSPGP3

 

DSPGP4 _
FASTI'UNE [

 

 

 

 

 

 

 

 

:> LOCKED SLOWTUNE __

 

 

Figure B. 1. System Overview.

60

DSP Power
Sheet2.SchDoc
_ _ ___ ,,._1
SDRAM
Sheet5.SchDoc
AECLKIN
EL__
l
—' 2
—_> 3
1F—' 4
Beader4

 

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L;
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n52 SE 8

 

     

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l 3.: 75:0 ,
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3
m N .l a: men.
32.2» v c .wmmnw nzo T J :0
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m l £39 25
I $5255 25 _ 1 a: use
on>n 22.2 v :AS _ So as
E 23 , _ _
NNN . .
l. 303 NW?

 

Figure B.2. Voltage regulation and clock generation.

61

 

 

 

TMSSZOCC

 

 

 

 

 

 

DVDD
IAL_
A2 1 DSPGND
A25 A
31 AI3 6””
314 33 GND GND
GND GND
B26 313
37 324 GND GND
33 oz GND GND
310 04 GND 6"”
317 C23 GND GND
319 (:25 GND CM)
320 33 GND GND
33 35 GND GND
GND GND
F9 D22
312 324 GND GND
F15 34 GND GND
F18 36 GND 6””
GS 39 GND GND
022 E18 0”” GND
GND GND
115 321
1122 323 GND ON”
121 F5 GND GND
l6 F8 GND 0"”
K22 310 GND GND
L5 311 GND GND
M5 F13 GND GND
GND GND
M6 F14
M21 F16 GND GND
N2 F17 0”” GND
GND GND
P25 F19
GND GND
35 F22 ND
321 G9 G GND
T5 (112 GND GND
us 015 GND 0"”
U22 GIS GND GND
V6 111 GND GND
v21 H6 0"” GND
GND GND
ws 1121
W22 H26 GND 0"”
Y5 15 GND Gm)
v22 GND GND
17
GND GND
AA9 :20
AA1 12 GND GND
M1 K21 GND GND
. GND GND
AA1 .1 L6
GND GND
A37 1.21
GND GND
A38 M7
A31 M20 GND GND
GND GND
A31 N6
GND GND
A319 N21
GND GND
A320 N25
A31 32 GND GND
AEI3 vv G ,, "D _ 7 G "D
A326 TMS320€6414T
AF2
AF25
1414mm TMSS20C6414TGLZ

Figure B.3. DSP power connections.

62

 

i=3.

 

11.11...
1T.
1T...
1:1,:
3.?

 

C66
T.luF

J.

C65
T1113

J.

lOOuF

C8

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’1‘

C7

l

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noour’l‘

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v

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T

UlE

C5

 

_L
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1
c4
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I

 

 

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’F1

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‘7

 

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{4
{l

 

 

 

 

M

 

5
J

 

M

 

 

 

mmmmmmmmmmmc

 

“Em.

flay
V
I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DSP HPI / RSV(PCI)

 

UlD

~HINT
HCNTL l
HCN'I'LO

RSV (PCI

 

63

10K

 

 

 

 

 

 

 

 

 

 

Figure B.4. DSP bypass capacitors, UTOPIA port, HPI port and reserved pins.

 

TMS320C6414TGLZ

.E
Awlf...

.mU
.08
.58

 

n
66939.: ".....Lraé 1
_L.|IL F.
...... v z? n a .H

02 ..
m>+ .

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1..“ H1

50> 1 959

NS

361.1
H

8m» H e ".553
:2 as "E. _ ".2: _.
2... God! 80”.“

1 H
83

Q20 .
E

Figure B.5. DSP serial connections.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dpr
UIG _‘ 12 , ,7
DSPJTAG
1 2 1—
TMS 43119 3 4
'I'DO __. 5 6 l—
AF18
TDI 1 AFI6 ‘ 7 8
TCK fl 9 10
~TRST m— 11 12
EMU“ Tfil-S- —1 l3 l4 —
EMUIO
AE18 JTAGl-Ieader
EMU9
ACI7
EMU8
AF17
EMU7
ADI7
EMU6
AE17 0R”
EMUS ‘:
AC16 lK
EMU4
ADI6
EMU3
AE16
EMUZ ——
ACIS
EMUI AFlS
EMUO
W‘s’szocmmrotz .;Rll
:‘lK

 

 

 

  
 
 
 
    

 

Ufl,, ,77
DSP GPlO

GPO GP15

om GPI4

GP2 (1313

GP3 0312

GP“

 

 

R27 , 7 7 7 7 7
———~w———l, MJAQED
33 ‘
R28 77 ,7 ,
—33-—{ 8970T7PAG739>

R29 7,, , 77,
jam—i XRQQflQE>

 

 

 

 

 

 

 

 

G3

F2

34
__.3

,2 ,:R24 ,:R25 ,:R26
:03 :‘lOK 1’10K :‘lOK
AE4

Figure B.6. DSP JTAG emulation port and general purpose port.

65

Ull AF24

    

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

“D63 DSP 3MIFA
AFB A3362
AED61
A3360
A3359
A3358
fig} A3357
:AC2I . A3356
Am A3355 AECLKOU’I‘Z
A320 A3354
A520 A3353
AC20 A3352
M20 A3351
AC19 A3350
—"AD19 . A3349
“/24 A3348
w23 A3347
Y26 A3346
Y23 ' A3345
Y25 22g:
Y24
M26 531332 AECLKOUTI
mg: A3340
M24 A3339
A326 AED38
A324 A3337
A325 A3336
ACZS A3335
3.26 13::
53—26 A3332
A331 0 A, 8 ..6
32330 "1 '1 326 AED“
XW'WA" 1 325 “D30
A328 : V" 1 325 “in”
— AA A3328
5327 _. "" 4 324_ A3327
5326 . A, . 321 “D26
A325 5 I}, . 324 A3325
5323 1 “AV,“ 1 323 AED23
5321m—Ivv»—‘ G24 A3321
5320 . A, : GZS A3320
5319 . 3:, 4 623 “D19
A)I8 . G26
K3177 *‘N‘ . 1123 £33
5316 _1_,,,," 1124 A3316
A31“ 11," 319 A3315
A3141 III 319 A3314
A31: """ 1 A20 A3313
A31: . ...... i 320 A3312
531 ‘ :*:* ‘ 320 A3311
£3910: vl‘v‘r: g? A3310
‘ AN» ‘ A339
A38 1 ”A 321
vvv AED8

 

 

 

fifsnoéaindfz " ’

Figure B.7. DSP external memory interface A.

66

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

   

 

 

7375—4 ~cs vvo —
m ~WE VDD *3
W ~CAS VD” ‘1
m “3 VD” —
m DQM3 “390 —
m DOW VDDQ —__
m 901‘“ “’90 *1
m DQMO VDDQ '7'.
W17— CL“ VDDQ ‘1'

4 c1<3 vagg ——:=

—— NC —‘

.6 1
$311) :7 DQ“ VDDQ —:i1
—A329 1 — DQ30 NC —‘=—
A328 3 _ D029 NC —:'—AA1
—AD27 ;— DQ28 BAl - AA‘
M6 ; — DQ27 BAO AA ;
A325 2 — 3Q26 A11 ‘ AA
A324 2 ‘ DQ25 A") 1 AA:
AD23 A _ DQ24 A9 ‘ 1111
A322 2 “ DQ23 A8 2 AA
A321 ‘ ‘3sz A7 ‘ A111
A320 —1 3Q21 A6 : M
AD19 73— ‘3on A5 1121
A318 31— DQ19 A4 60 mfi'
A317 3— ”Q's A3 :‘7 A1E'
A316 1 D0” A2 1 AN
A315 85 m“ A' : Am

14 15 A0 ‘ ~

A313 82 DQl4 NC —. —
A312 80 DQ13 NC —.-—
A311 79 DQ” NC "17—
A310 77 DQll vsso —-.
A39 76— Dow vsso —
Am 74 DQ9 vsso —:
AD7 1 DQ8 vsso —‘
Am 1— DQ7 vsso —‘
A35 1— 3Q6 vsso H
A34 — 305 VSSQ F1
AD3 , 3Q4 vsso —‘
A32 ‘ 3Q3 vss —;
A31 4— DQ2 vss --:
A30 ,— DQI vss

‘ DQO vss

 

 

MT48L01M3232TG-6

Figure B.8. External SDRAM.

67

 

ommm

 

 

 

 

 

 

 

 

 

 

 

 

 

 
 

 

      

3am

5mm 2mm
3mm Qmm
8mm v<mm
5mm 3mm
3mm 3mm
3mm 2mm
5mm 3mm
3mm 3mm ,
8mm 2<mm
29mm :<mm
:Qmm S<mm
ammm 2<mm
29mm 2.4mm
39mm 2<mm
29mm £<mm
m3<mz S<mm
mo<mz £<mm
Cram 2.4mm
mmOmmz 02mm
32m? 80m:
ommmbmm Eomz
Em .2me 30mm: 881
Em 2m v «aflommz 80m:
-<m 2m v E5503 Emma
Em EEO «Bofiomm 8mm:
2m 2m v 550% 5mm;

                           
                        

Figure 3.9. DSP external memory interface B.

68

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HMmm—Mz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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2 _ 00> mm> _ N N _ mm> BE: _ t.
. 2203 mm> . 02 00> .
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NE «N N 8m 8m .N N N<m
N< 3 n . _ 2 1
Em MN 2.“ Em Em z. N «.5
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2m .1N mm Nam Nam mm NN firm
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3m _N 2 8m 8m mm "N 2m
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3m 2 8 8m 8m 8 a Em
b< Q .I c b< .
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3 N a N 3 .
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, .2 N n . . N .2 .
2% N on Nam 8 N 2<m
_ 2.3. a o? .
23 6 NM 25 NM 6 :«m
:< S _ 2 a :< _
2<m m 3 Sam ...m m NZm
NE : a _ : a N2 _
E<m w 3 :mm on v 2<m
N? N_ a _ - N_ a N2
2<m N on Nam 3 N 32m
3< 2 a _ 2 G <2. I
2<m N 3 23m :6 N 92m
W? :on . I. Eon m2 _
SE a £< oz 2..le Sam 96 4 3503 2< _ _ £<m
NZm N6 2 23m 2 N6 2%
:< 32 z B: :< _
. 62m 2 oz 01 : -3 a i 02 N2 _ 2 N35
89$ 58/ ONE 2 02 m2 ImNIIII mo<mz N 3 m2 a? _ S 2<m
\ a 6.4 Eomz Nmomz N a 85
/ z r 1 N<
S N:

Figure B.lO. External non-volatile memory and FPGA connection.

69

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7O

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72