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DESIGN AND EVALUATION OF AN AUTOMATED TEST PLATFORM FOR
LARGE—SCALE ANALOG FLOATING GATE ARRAY PROGRAMMING

By

Paul R. Kucher IV

A THESIS

Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of

MASTER OF SCIENCE
Electrical and Computer Engineering

2007

ABSTRACT

DESIGN AND EVALUATION OF AN AUTOMATED TEST PLATFORM FOR
LARGE-SCALE ANALOG FLOATING GATE ARRAY PROGRAMMING

By

Paul R. Kucher IV

Due to advances in microfabrication technology, modern digital systems can pro-
cess large data sets using discrete algorithms with high precision. However, due to
the increasing clock frequencies required to operate on data in real-time applications,
analog circuit topologies have become attractive for computation. Such computa—
tional blocks require an analog data store that can achieve at least eight bits of
accuracy for coarse classification. This work creates an automatic means of program-
ming subthreshold floating gate circuits used as analog storage elements. The system
consists of a test platform designed with a flexible configuration for both topology
and process—neutral large-scale floating gate array programming. A system-on-chip
with analog floating gates has been fabricated in a standard 0.5pm CMOS process
and is used to validate the performance of the test platform. A novel algorithm for
floating gate programming has been developed based on experimental observation
and the test unit is capable of programming analog floating gate arrays to within

0.5% accuracy.

ACKNOWLEDGMENTS

I would like to begin by thanking my advisor, Dr. Shantanu Chakrabartty. I feel
honored to have worked under his direction for the past two years, and have gained
significant insight into designing mixed-signal VLSI systems for machine learning
applications. He has provided me with the opportunity to pursue the areas of research
I find most intellectually stimulating and has always guided me in accomplishing my
goals. I look forward to continued collaboration and wish him the best in his own
research endeavors.

I thank my committee members, Dr. Greg Wierzba and Dr. Andrew Mason, for
taking time out of their busy schedules to be a part of my project. I also credit
Dr. Mason with introducing me to research through working in his lab during my
undergraduate career. I thank him for this opportunity and his thoughtful review
of my thesis work. I thank Dr. Greg Wierzba for his advice and inspiration. I have
enjoyed our many discussions and the advice he has given extending back to my
undergraduate years. His courses have taught me many of the skills I needed to
complete this work and I thank him for giving me these tools.

I thank my friend, Arthur Matteson, who helped in populating the test platform
printed circuit board. I am impressed with his ability to work with fine-pitch, surface
mount components and am grateful of being able to learn his technique. I also thank
Arthur for his constant input and review of my thesis.

Finally, I thank my parents, Paul and Elaine Kucher, who have done their absolute
best in raising and guiding me. They have always supported my interests and have

never failed to help in time of need.

iii

LIST OF TABLES .............................. viii
LIST OF FIGURES ............................. ix
1 Introduction ................................ 1
1.1 Previous Work .............................. 2
1.1.1 Field-Programmable Analog Arrays ............... 2

1.1.2 Support Vector Machine ..................... 4

1.1.3 Imagers and Adaptive Sensors .................. 6

1.2 Motivation: Rapid Configuration of Analog Memories ......... 7
1.3 EEPROMS for Analog Parameter Storage ................ 8
1.4 Floating Gate Test Station Design .................... 8
1.5 Floating Gate Test Station Control ................... 8
1.6 Testing and Results ............................ 9
1.7 Conclusions ................................ 9

2 EEPROMs for Analog Parameter Storage .............. 10
2.1 History ................................... 10
2.1.1 PROM ............................... 10

2.1.2 EPROM .............................. 11

2.1.3 EEPROM ............................. 11

2.1.4 Flash Memory ........................... 12

2.2 Floating Gate Transistors ........................ 12
2.3 Fowler-Nordheim Tunneling ....................... 13
2.4 Hot-Electron Injection .......................... 15
2.5 Analog Floating-Gate Programming Procedure ............. 16
2.6 Programming Precision .......................... 18
2.7 Charge Retention Characteristics .................... 19
2.8 Temperature Dependency ........................ 20
2.9 Summary ................................. 22

3 Floating Gate Test Station Design .................. 23
3.1 Noise and Shielding Considerations ................... 23
3.1.1 Shared Current Paths ...................... 24

3.1.2 Shielding Techniques ....................... 25

3.2 System Architecture ........................... 26
3.3 Power Circuits ............................... 28
3.3.1 Voltage Regulation ........................ 28

TABLE OF CONTENTS

iv

3.3.2 Fowler-Nordheim Tunneling Supply and Control ........ 29

3.3.3 Hot-electron Injection Supply and Control ........... 32
3.4 Voltage Digital-to-Analog Conversion .................. 33
3.5 Voltage Analog-to-Digital Conversion .................. 34
3.6 Multi-channel Current Digital-to—Analog Conversion .......... 36
3.7 Multi-channel Current A / D Conversion ................. 38
3.8 Testing Considerations .......................... 42
3.9 Summary ................................. 43
Floating Gate Test Station Control .................. 45
4.1 Instruction Decoding and Execution ................... 45

4.1.1 Instruction Set .......................... 48
4.2 Digital Input / Output ........................... 49
4.3 Digital Potentiometer Control ...................... 50
4.4 Current Analog-to-Digital Conversion .................. 52
4.5 Injection Control ............................. 54
4.6 Memory I/O ................................ 55
4.7 Memory Multiplexer ........................... 57
4.8 Memory Transfer Control ........................ 57
4.9 Voltage Digital-to—Analog Conversion .................. 59
4.10 Serial I/O ................................. 61
4.11 Serial Multiplexer ............................. 64
4.12 Serial Shifter ............................... 64
4.13 Seven Segment Display .......................... 66
4.14 Signal Generator ............................. 67
4.15 Voltage Analog-to—Digital Conversion .................. 69
4.16 Voltage DAC Multiplexer ......................... 71
4.17 Digital Clock Manager .......................... 71
Testing and Results ........................... 74
5.1 Test Station Validation .......................... 74

5.1.1 Fowler-Nordheim Tunneling Pulse Response .......... 74

5.1.2 Hot-Electron Injection Pulse Response ............. 75

5.1.3 VoltageMode ADC Linearity .................. 76

5.1.4 Signal Generator ......................... 80
5.2 Overview of the Test Chip ........................ 84
5.3 Floating Gate Testing Results ...................... 86

5.3.1 Floating Gate Current Equalization ............... 86

5.3.2 Adaptive Injection Characteristics ................ 87

5.3.3 Effects of Injection on Threshold Voltage ............ 90

5.3.4 Programmable Current Lookup Tables ............. 92

6 Conclusions ................................ 94

6.1 Accomplishments ............................. 94
6.2 Suggestions For Future Work ...................... 95
6.2.1 Floating Gate Architectures ................... 95

6.2.2 Board-Level Modifications .................... 96

6.2.3 Microcontroller-Based Test Station ............... 97
APPENDICES ................................ 100
A Support Vector Machine SoC ..................... 100
A1 Layout ................................... 100
A2 Pad Frame ................................. 103

B Test Station Design Documentation .................. 105
El Test Station Parts List .......................... 105

C Test Station VHDL ........................... 127
C.1 Digital Clock Manager: dcm.vhd .................... 127
C2 Instruction Decoder and System Controller: decode.vhd ........ 129
C3 Multi-channel Digital Input/ Output: digital_io.vhd .......... 135
C4 Digital Potentiometer Control: digital_pots.vhd ............ 138
C5 Current ADC Control: iadc.vhd ..................... 140
C6 Floating-Gate Transistor Injection: injectionvhd ............ 144
C7 Memory Transfer Control: memory_block_transfer.vhd ......... 145
C8 Memory Controller: memory_io.vhd ................... 147
C9 Memory Multiplexer: memory.mux.vhd ................. 149
C10 Voltage DAC Controller: program_dacs.vhd .............. 150
CH RS-232 Serial Controller: serial_io.vhd ................. 152
C.12 Serial I / O Multiplexer: serial_mux.vhd ................. 157
C.13 Serial Shifting Controller: serial_shifter.vhd ............... 158
CM Seven Segment Display: seven.segment.vhd ............... 160
C.15 Signal Generator: signal_gen.vhd .................... 162
C.16 Voltage ADC Controller: vadc.vhd ................... 164
C.17 Voltage DAC Multiplexer: vdac_mux.vhd ................ 167
C.18 Top Module: top.vhd ........................... 168
C.19 Implementation Constraints File: top.ucf ................ 177

D MATLAB Toolbox Overview ...................... 179
E Test Station MATLAB Functions ................... 181
El FPGAInit.m ................................ 181
E2 FPGALoopback.m ............................ 182

vi

E.3 FPGADigitalIO.m ............................ 182

EA FPGAInjectPulse.m ........................... 183
E5 FPGATunnel.m .............................. 184
E6 FPGASetBias.m ............................. 184
E7 FPGASetBiasCurrent.m ......................... 185
E8 FPGAReadVoltage.m ........................... 185
E9 FPGAReadCurrent.m .......................... 187
E10 FPGAEstimateCurrent.m ........................ 188
E11 FPGAReadMemory.m .......................... 189
E12 FPGAReadMemoryBlockm ....................... 189
E.13 FPGAWriteMemory.m .......................... 190
E14 F PGAWriteMemoryBlock.m ....................... 191
E.15 FPGAWriteMemoryVector.m ....................... 192
E16 FPGASerialShift.m ............................ 192
E17 FPGAthctionGenerator.m ....................... 193
E.18 FPGASignalGen.m ............................ 195
F Floating Gate Testing Code ...................... 196
El KeithleyInit.m ............................... 196
F2 KeithleyGetCurrent.m .......................... 196
F3 KeithleySetVoltage.m ........................... 197
FA SVM2Init.m ................................ 197
F5 SVM2SelectCell.m ............................ 198
F6 SVM2GetCurrent.m ........................... 199
F7 SVM2GetCurrents.m ........................... 199
F8 SVM2SetCurrent.m ............................ 199
F9 SVMZSetCurrents.m ........................... 201
FIG SVM2InputSweep.m ........................... 201
FM SVM2CurrentRampTest.m ........................ 201
BIBLIOGRAPHY .............................. 203

vii

LIST OF TABLES

3.1 Jumper Descriptions ........................... 42
4.1 System Instruction Set .......................... 48
AI Fabricated Prototype Pin Descriptions ................. 104
B] Test Station Parts List .......................... 109

viii

2.1
2.2
2.3
2.4
2.5

3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17

4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13

LIST OF FIGURES

Crossection of a Floating Gate nMOS Transistor ............ 12
Energy band of a structure influenced by Fowler-Nordheim tunneling 13
Floating Gate Cell Schematic ...................... 16
Floating Gate Transistor Equalization Procedure ........... 17
Floating Gate Current Mirror ...................... 21
Circuits with Ground Loops ....................... 24
Local Return Paths Only ......................... 24
Block Diagram of the Mixed-Signal Test Station ............ 27
Voltage Regulation ............................ 28
Tunneling Control Circuit Schematic .................. 29
MAX762 Simplified Schematic Diagram ................. 30
Injection Comparator Circuit ...................... 32
LTC2600 Block Diagram ......................... 34
16—Channel Voltage ADC ......................... 35
Precision Current Source ......................... 36
AD7376 Digital Potentiometer SPICE Model Schematic and Code . . 37
Precision Current Source DC Response ................. 38
Precision Current Source Transient Startup Response ......... 39
Current Measurement Circuit ...................... 40
Current ADC I—V Converter DC Response ............... 41
Current ADC I—V Converter Transient Response ............ 41
Mixed-Signal Test Station Populated Printed Circuit Board ...... 44
System Controller Block Diagram .................... 46
The Instruction Decoding and Execution VHDL Module ....... 47
Digital I/ O VHDL Module ........................ 50
Digital Potentiometer VHDL Module .................. 51
Digital Potentiometer Serial Peripheral Interface ............ 51
Current ADC VHDL Module ...................... 52
Current Channel Multiplexer 12C Interface ............... 52
Current ADC Serial Peripheral Interface ................ 53
Hot-Electron Injection VHDL Module .................. 55
Memory I/ O VHDL Module ....................... 56
Memory Multiplexer VHDL Module ................... 57
Memory Transfer VHDL Module .................... 58
Voltage DAC VHDL Module ....................... 60

4.14 Serial I/ O VHDL Module ........................ 61

4.15 RS-232 Signal Timing Diagram ..................... 62
4.16 Serial Multiplexer VHDL Module .................... 64
4.17 Serial Shifter VHDL Module ....................... 65
4.18 Seven Segment Display VHDL Module ................. 66
4.19 Signal Generator VHDL Module ..................... 67
4.20 Voltage ADC VHDL Module ....................... 69
4.21 Voltage ADC Serial Peripheral Interface ................ 70
4.22 Voltage DAC Multiplexer VHDL Module ................ 72
4.23 Digital Clock Manager Module ...................... 73
5.1 Tunneling Pulse .............................. 75
5.2 Minimum Injection Width ........................ 76
5.3 Injection Widths ............................. 77
5.4 Voltage ADC Linearity at 2 MHz .................... 78
5.5 Voltage ADC Linearity at 1 MHz .................... 78
5.6 Voltage ADC Linearity at 400 kHz ................... 79
5.7 Voltage ADC Linearity at 153600 Hz .................. 79
5.8 Signal Generator Sine Wave at 1 kHz .................. 81
5.9 Signal Generator Triangle Wave at 1 kHz ................ 81
5.10 Signal Generator Sawtooth Wave at 1 kHz ............... 82
5.11 Signal Generator Square Wave at 1 kHz ................ 82
5.12 Floating Gate Programming Test Setup ................. 83
5.13 Analog SVM Chip Photomicrograph .................. 83
5.14 Support Vector Simplified Schematic .................. 84
5.15 Floating Gate Cell Schematic ...................... 85
5.16 Unequalized Array of Floating Gates .................. 87
5.17 Equalized Array of Floating Gates .................... 88
5.18 Floating Gate Equalization Accuracy Histogram ............ 88
5.19 Equalized Array of Floating Gates at VCG = 2.2 V .......... 89
5.20 Floating Gate Equalization Accuracy Histogram at VCG = 2.2 V . . 89
5.21 Adaptive Programming used for Hot-Electron Injection ........ 90
5.22 pMOS Input Stage V-I characteristics .................. 91
5.23 Floating Gate MOS Threshold Voltage Modulation .......... 91
5.24 Floating Gate Current Ramp ...................... 93
5.25 Floating Gate Current Sine Wave .................... 93
A.1 Floating-Gate Transistor Layout ..................... 100
A2 Integrator Layout ............................. 101
A3 Shift Register Layout ........................... 101
AA Support Vector Layout .......................... 101

A.5 Output Stage Layout with Floating Gates and Shift Register ..... 101

A6 Support Vector Machine Layout ..................... 102
A7 Fabricated Prototype Pin Bonding Diagram .............. 103
El Gerber Output: Motherboard Top Silkscreen .............. 110
B2 Gerber Output: Motherboard Top Solder Mask ............ 111
B3 Gerber Output: Motherboard Top Layer ................ 112
B4 Gerber Output: Motherboard Middle Layer 1 ............. 113
B5 Gerber Output: Motherboard Middle Layer 2 ............. 114
B6 Gerber Output: Motherboard Bottom Layer .............. 115
B7 Gerber Output: Motherboard Bottom Solder Mask .......... 116
B8 Motherboard NC Drill Output ...................... 117
3.9 Gerber Output: Daughterboard Top Silkscreen ............. 118
3.10 Gerber Output: Daughterboard Top Solder Mask ........... 118
8.11 Gerber Output: Daughterboard Top Layer ............... 119
B.12 Gerber Output: Daughterboard Bottom Layer ............. 119
BB Gerber Output: Daughterboard Bottom Solder Mask ......... 120
RM Daughterboard NC Drill Output ..................... 120
B.15 Test Station Connectors ......................... 121
3.16 Test Station Power Circuits ....................... 122
B.17 Test Station Voltage Digital-to—Analog Converters ........... 123
B.18 Test Station Current Digital-to—Analog Converters ........... 124
3.19 Test Station Analog-to—Digital Converters ............... 125
B.20 Test Station Daughterboard ....................... 126

xi

CHAPTER 1

Introduction

Analog VLSI computational methods become an attractive alternative to compara-
ble digital VLSI techniques when systems demand high computational density and do
not require high precision [1]. The former is the case in any application whose data
depends on multi—dimensional datasets, and generally takes the form of a matrix-
vector multiplication (dot product) [2]. These two requirements are the case in many
machine learning applications where the output is represented as the confidence of a
decision-making algorithm. In the case of digital systems, these algorithms are gen-
erally sequential in their execution, and require computationally-intensive operations
such as the above mentioned matrix-vector multiplication as well as implementing
polynomial functions [3].

Creating ultra-low-power signal processors often requires a substantial portion of
the architecture implemented in the analog domain [4]. Additionally, when the input
has a resolution of around 10 bits or less, analog computation can have significant
advantages when compared to an architecture implemented in the digital domain.
For example, there are many application circuits that are both very elegant in their
implementation and scalability as well as their power consumption. An example of
such a circuit is the winner-takeall or maximum circuit [5]. What appears to be an
O(n) problem in a computer science context becomes a parallel operation in analog.

Creating a parallel architecture requires a parallel data store that can allow trained

templates to be directly accessed by analog hardware. In the past, such parameters
were implemented as external potentiometers that had to be tuned by hand. Further-
more, this method also used a significant number of external I / O channels, increasing
package size and reducing the number of available diagnostic pins [6]. One increas-
ingly popular method involves the use floating gates to store bias currents on-chip.
These circuits have the advantage of eliminating off-chip, configurable biases such
as DACs or potentiometers, and of implementing them directly in the signal path,
eliminating the need for transmission gate multiplexers to share these sources. Addi-
tionally, because these circuits are simple in their architecture, they may be densely

integrated.

1 .1 Previous Work

Floating gate devices are traditionally divided into three primary areas: as analog
memory elements; as adaptive circuit elements; and as capacitive circuit elements [7].
This section provides an overview of previous work in important selected applica-
tions incorporating these three primary uses for floating gate devices. Interestingly,
however, many applications fully realize the potential of floating gates. For example,
field-programmable analog arrays incorporate both analog memory and trimming el-
ements, as well as capacitive elements. Likewise, SVMs incorporate floating gates as

analog memories and as adaptive circuit elements.

1.1.1 Field-Programmable Analog Arrays

Analog integrated circuit (IC) design often requires substantial expertise in the field
to design, fabricate, and test a system successfully. Additionally, such work sometimes
requires several design iterations, and is therefore expensive and time consuming. The
digital design flow includes several tools for the designer, such as hardware descrip-

tion languages, synthesis tools, and field-programmable gate arrays (FPGAs) to test

designs before they are synthesized on-chip for fabrication. However, such tools for
the analog designer do not exist, making it difficult to study non-ideal effects such as
noise and mismatch.

Modeling and simulation provide a first principle approach for sub-system imple-
mentation. Yet, testing will ultimately be required, and for some large-scale designs,
is the only means of verifying the entire design. Field-programmable analog arrays
(FPAA) have been proposed [8, 9, 10] to alleviate some of these design challenges to
allow rapid prototyping of analog designs using reconfigurable hardware.

Reconfigurable analog hardware may sound like an attractive alternative to tra-
ditional analog VLSI. However, it has the disadvantage of requiring a larger die area
to achieve similar functionality, a problem shared by FPGAs. Additionally, FPAAs
have additional parasitics due to switch matrices necessary to route signal paths.
These shortcomings lead to higher power consumption and reduced bandwidth, mak-
ing them impractical for some designs.

Floating gates are attractive for FPAAs because they may be used as switches
in the configuration network and may be used directly as analog elements [11]. The
impedance of a floating gate is inversely proportional to the number of electrons on
the floating node. Thus, the quality of the switch is determined by its finite on
and off impedances. FPAAs are comprised of computational analog blocks (CAB),
which are analogous to slices in FPGA terminology. The use of floating gates as
in-circuit elements leads to a dense architecture, reducing the size of these CABS.
This is possible by eliminating the need for on—chip resistors that consume significant
area. Additionally, without fixed-value resistors, signal routing complexity is further
reduced as a floating gate may act as a variable resistor.

Basic analog building-blocks such as current summation and subtraction, integra-
tion, differentiation, amplification, and thresholding may be integrated into a single

CAB with few transistors. These CABS include floating gates combined with op—

erational transconductance amplifiers to perform these tasks. Furthermore, floating
gates have been used directly in operational amplifiers for offset cancellation through
on—chip trimming circuits [12, 13, 35].

Matrix vector multipliers have also been included on FPAAs [14]. The charge
on the floating gate can act as a weight and its control gate can act as the input.
Signed numbers are represented using a differential pair configuration and if cascaded
together across multiple CABS, a matrix vector multiplier may be realized.

Since matrix vector multiplication (MVM) provides the foundation for many ma-
chine learning-related operations, specialized hardware for this task has been devel-
oped to exceed the performance of a general purpose FPAA hardware. One realization

of this approach is in the form of a support vector machine.

1.1.2 Support Vector Machine

A support vector machine (SVM) is a type of supervised learning method for creat-
ing functions based on a set of labeled training data. These functions could be for
classification or generalized regression [15]. For machine learning applications, SVMs
are applied to the classification task, and have been used extensively for recognition
with image [16, 17], acoustic [18, 19, 20], olfaction [21, 22], temperature [23], acceler-
ation or vibration [24], and even biomedical signature [25] front-ends. However, these
applications have largely been confined to software implementations and on digital
signal processors, where speed and storage capabilities are not the limiting factor as
on a system-on-chip.

SVMs have only recently been mapped onto analog structures [28], which are
becoming viable alternatives to digital signal processors as a means of implementing
SVMs in hardware. Utilizing parallel architectures, it is possible to compute the deci-
sion score as a single operation, based on the DC response of the system. Furthermore,

where speed is not critical, it is possible to bias these circuits in the subthreshold re-

gion at reduced voltage headroom to dramatically reduce power consumption beyond
that of digital implementations.

Floating gates become very important template storage elements for analog SVMs
since they may be placed directly in the signal path for continuous time classification.
Since SVM parameters are represented as floating-point values, they may be directly
mapped onto analog hardware as configurable current sources. Additionally, SVM
performance may be controlled directly through the bias of the global control gate
voltage, which capacitively couples with the floating node to set bias current.

However, before realizing an SVM using analog structures, it is important to un-
derstand the training methods used and how they affect chip architecture and floating
gate programming. SVM training involves finding the maximum margin between data
classes, which means that the classifier attempts to maximize the distance between
data points of different classes along the decision boundary (hyperplane), which in
turn minimizes error when classifying incoming data points. This topic, along with
soft-margin regularization theory, are important when developing the training algo—
rithm [26].

Furthermore, these topics are critical for the designer as they have implications
on any hardware implementations, which have both limited resolution and linear-
ity, as well as device imperfections. For example, noise robustness and temperature
sensitivity at the circuit-level can affect the generalized performance of an SVM by
corrupting SVM parameters through capacitive coupling or temperature-dependent
offsets. This often leads to deterioration of the equal error rate, a common figure of
merit for SVM performance.

Analog SVMs may also implement a modified variant of the general SVM formula—
tion. One such implementation involves working in the log domain where floating gate
parameters are not stored as linear mappings of their floating point representations

[27]. Here, the decision surface becomes warped due to circuit topology, resulting

in a need for floating gate support vector compensation. The log domain SVM also
has the unique advantage of simplifying the hardware implementation by not having
to implement the SVM formulation directly and has no inherent temperature de-
pendency. However, it still relies on floating gates for parameter storage, leading to
nonlinear noise and temperature dependency.

Analog SVMs are an ideal application for large-scale floating gate programming
due to the high demand for accurate and high-density parameter storage to achieve
performance on par with digital SVM implementations. However, the need for a
large number of support vectors has lead to increasing requirements on die area. In
addition, increasing density can also result in reducing the size of the floating gate
capacitors, which has implications on resolution, and is discussed in Section 2.6.

In the design of neuromorphic systems [29], SVMs have broad applications. Con-
sequently, analog SVMs are of direct interest to this work, which will be validated
through the testing of an analog SVM’s floating gate array. Further details on the

test chip are given in Section 5.2.

1.1.3 Imagers and Adaptive Sensors

Floating gates also have applications in the feature front—end space of neuromorphic
systems. One such application is in active pixel sensors (APS), where traditional
machine vision systems separate the image acquisition and processing modules. In-
spired from biology, a vision chip that can integrate adaptive elements directly on the
imager has the advantage of higher speed and parallelism, and higher integration.
Bandyopadhyay et al. proposed a CMOS transform imager [30] with on-chip float-
ing gates capable of programmable matrix operations and filtering. Here, the floating
gates store arbitrary analog waveforms for image transforms and nulling mismatch
during matrix Operations. These basis function bias generators are stored in a ma—

trix and are multiplexed to the active row of the imager. I-V converters are used to

provide voltage-mode output.

In addition to on-chip filtering, mismatch cancellation is another area of interest
in designing APS imagers. Process variation can create undesirable artifacts in the
image from a phenomenon called fixed pattern noise (FPN). This leads to random,
deterministic spacial noise across the pixel array. FPN has traditionally been elimi-
nated through the use of correlated double sampling, but Wong et a1. has proposed a
current-mode imager with self-adapting mismatch reduction [31]. Here, floating gates
were added at the pixel level. During a calibration step, uniform light was shown on
the imager and the pixel output voltages were read. Each pixel was adapted through
hot-electron injection to produce a desired constant output voltage under these con-

ditions.

1.2 Motivation: Rapid Configuration of Analog Memories

Due to the proliferation of analog floating gate technology and its applications, it
becomes increasingly important to have a generalized framework for precision pro-
gramming of floating gate arrays. As will be discussed in Chapter 2, both circuit
topology and process technology will determine programming methods. Thus, a con-
figurable programming interface is necessary to accommodate different mixed-mode
designs.

This work aims to provide a testing platform for mixed-signal systems incorporat-
ing analog floating gates. This system will implement a generic interface that is easy
to use for rapid testing, and is both modular and customizable in its software and
firmware interfaces. Finally, the work will validate the performance of the system on
a mixed-mode system—on-chip in the form of an analog support vector machine. This

thesis will cover the following topics in detail.

1.3 EEPROMS for Analog Parameter Storage

This chapter covers the background of non-volatile semiconductor memory technology,
how it has been used in the past in the digital domain and the evolutionary steps
that have led to the use of floating gates as analog memory elements. The theory of
these devices are discussed, including the important hot-electron injection and Fowler-
N ordheim tunneling programming and global erasure methods, as well as previous

work in the area of floating gate characterization and device limitations.

1.4 Floating Gate Test Station Design

This chapter covers the design considerations and implementation of the testing plat-
form required for floating gate programming. Noise and shielding considerations are
discussed, as well as the circuits required on the periphery of a mixed-mode design
incorporating floating gates. Important topics include the design of a precision cur-
rent measurement system, a tunneling and injection supply and associated control
schemes, a voltage-mode digital-to—analog converter bank for bias and signal genera-

tion, and digital interfaces to mixed-signal designs.

1.5 Floating Gate Test Station Control

Chapter 4 covers the design of a hardware-based controller using the Xilinx Spartan-3
XC3S2OO FPGA. This controller is responsible for providing all serial interfaces to
the sub-modules of the test station, as well as instruction interfacing with a PC—based
host. All logic has been written using the VHSIC Hardware Description Language

(VHDL) and was optimized to minimize slice utilization.

1.6 Testing and Results

This chapter begins with the validation of the mixed-mode test platform. Such tests
are necessary for calibration of the measurement circuits acting on the periphery of
the floating gate chip. Next, the test chip is discussed, outlining the programming
methods and some architectural considerations in the testing process. Finally, floating

gate results are provided, demonstrating functionality of the complete system.

1 .7 Conclusions

This thesis concludes with an overview of the work accomplished and some suggestions
for future work. Also, further resources are available in the appendices, including
layouts from the fabricated test chip, schematics and component lists for the test
station, all code used in the hardware controller and PC-based interfaces, as well as
testing scripts for the floating gate experiments. A brief tutorial is given on using the

software interface.

CHAPTER 2

EEPROMS for Analog Parameter Storage

An Electrically Erasable Programmable Read-Only Memory (EEPROM) is a non-
volatile storage medium typically used to store configuration parameters. EEPROMs
have been used for many years in digital systems but have only recently made their
way into the field of analog computation. Additionally, EEPROMs have the advan-
tage of data retention for prolonged periods of time, typically ten years or more. This
chapter covers the history of PROM technologies through the first digital EEPROM
devices, as well as the theory of floating gate transistors and their limitations. This
basis will then be used to design an interface for a floating gate programming test

platform.

2.1 History

2.1.1 PROM

One of the earliest forms of programmable memory is the Programmable Read-Only
Memory (PROM), invented in 1956 by Wen Tsing Chow at the American Bosch Arma
Corporation for the US Air Force’s Atlas ICBM. This memory device utilizes fuses
and anti-fuses to either establish an open or short circuit connection, respectively,
effectively writing a one or zero permanently to that cell of the device.

For example, if the PROM initially contained all cells programmed to logic zero,

10

burning an anti-fuse would bridge a connection between the output of the given
cell and the chip’s supply voltage, establishing a digital high or ‘1’ at the output
node. A fuse will likewise produce the opposite effect. It is important to remember
that the breakthrough of PROM technology meant that configuration data could
be stored onto the integrated circuit post-fabrication for the first time. PROM’s
greatest advantage is therefore its permanent data retention capability. However,
what became PROM’s greatest advantage is also its greatest limitation, which lead

to the development of erasable non-volatile memories.

2.1.2 EPROM

Next came the Erasable Programmable Read-Only Memory (EPROM), invented by
Dr. Dov Frohman in 1971. EPROM technology utilizes floating gate transistors,
which are described in greater detail in Section 2.2. EPROMs are erased by exposing
the die to an ultra-violet light source. This is accomplished by penetrating light with
a typical wavelength of 235 run through a quartz erasing window in the packaging.
Many EPROM chips are mounted inside a plastic rather than ceramic package
to reduce costs. These types of EPROM-based circuits are OTP or One-Time-

Programmable in that they do not include a quartz window.

2.1.3 EEPROM

EEPROM technology is similar to EPROM technology, but does not require an ultra-
violet light source for erasure. The methods required for writing and erasing these
types of memory cells include injection and tunneling, which are discussed in greater

detail in Sections 2.3 and 2.4.

11

Control Gate Floating Gate

  

Figure 2.1. Crossection of a Floating Gate nMOS Transistor

2.1.4 Flash Memory

Flash memory has become standard in many consumer electronic devices that re-
quire large non—volatile data stores. Flash memory utilizes the same technology of
EEPROMs, except they allow erasure of all cells simultaneously. This differs from
regular EEPROMs that may program and erase each cell individually. By this defi-
nition, analog floating gates with a single erase may be termed analog flash memory,

as the tunneling operation is a global function of the programming process.

2.2 Floating Gate ’Il'ansistors

Figure 2.1 illustrates the crossectional structure of a floating gate transistor. Float-
ing gate transistors are constructed using a traditional MOSFET with an additional
gate layer (ELEC in the AMI 0.5 pm fabrication technology). Thus, a floating gate
is a polysilicon layer encapsulated by silicon dioxide. Charge may then be stored
on the polysilicon gate indefinitely, provided that no charge may leak through the

surrounding insulator.

12

 

_EC
_EV

 

Figure 2.2. Energy band of a structure influenced by Fowler-Nordheim tunneling

The voltage of the floating gate is determined by the capacitively coupled input
voltage, called the control gate voltage. The amount of charge on the floating gate
determines the potential difference between the floating node and the control gate
voltage. By increasing the amount of charge on the floating node, the potential
across the POLYl-POLY2 capacitor increases, thus decreasing the voltage of the
floating node with respect to ground, and increasing the current in a floating gate
pMOS device and decreasing current in a floating gate nMOS device. Increasing the
charge of the floating node is achieved through a process called hot-electron injection.

Charge is removed through a process called Fowler-Nordheim tunneling.

2.3 Fowler-Nordheim Tunneling

Fowler-Nordheim (F N) tunneling is a field-assisted electron tunneling method used
to remove negative charge from the floating node [32]. When a large potential is
applied across a polysilicon-silicon dioxide-silicon structure, typically implemented
as a MOS-capacitor, its band structure will be modified as shown schematically in
Figure 2.2.

In the presence of a high electric field, electrons in the conduction band of the
floating gate electrode will see a triangular energy barrier whose width is a function

of the applied electric field. Adequately high electric fields will cause the barrier

13

to become small enough for electrons to tunnel through the barrier and into the
8102 conduction band. Equation (2.1) gives the Fowler-Nordheim tunneling current
density where h is Planck’s constant, it = h / 27r, (15;, is the energy barrier at the Si-Si02
interface (3.2 eV), ET is the electric field at the tunneling interface, q is the charge
of an electron (1.6 x 10‘19 C), m is the mass of a free electron (9.1 x 10'31 kg), and

m“ is the effective mass of an electron in the band gap of Si02 (0.42 - m).

 

 

/—.¢
J: q3 Ln—E2ezrp —4 2m 3%? (2.1)
87rh¢bm* T ET

The tunneling mechanism is independent of temperature. However, the number
of electrons available for tunneling in the conduction band of the polysilicon gate is
dependent on temperature. In addition, the Fowler-Nordheim tunnel current density
is exponentially dependent on the applied electric field.

Using Equation (2.1), it is possible to calculate the current density in the AMI
C5N process, which has a 13.5 nm gate oxide thickness [33]. Equation (2.2) shows a
numerical expression of the tunneling current density with respect to applied tunnel-
ing voltage (VT). For 15 V applied at the tunneling pin (and 0 V at the floating gate),
it is expected that the Fowler-Nordheim tunneling current density will be 176.2 A / m2
or 176.2 pA/umz, which translates to 158.6 pA through the 1.5um/0.6pm MOS ca-

pacitor.

 

J[A/m2] = 1.147-10-6 [WIT] [fir [117/7:] exp [{3;;:?;/[ill] (2.2)

Although the tunneling current may be estimated by multiplying the current den-
sity by the area of the MOS capacitor, this assumes that the current density is uniform
across the interface. In fabricated devices, however, this is an unlikely scenario due

to fringe fields and device mismatch.

14

2.4 Hot-Electron Injection

Hot-electron injection is a process by which electrons are put onto the floating node
by gaining enough energy to surmount the SiOg barrier. When the minority carriers
that flow through the channel of a MOS device are in the presence of a large source-
to—drain bias (for a pMOS transistor), the carriers are heated by this large electric
field and their energy distribution is increased. This leads to impact ionization at the
drain of the device, generating both majority and minority carriers. The minority
carriers are collected at the drain, and can overcome the 8102 barrier if they gain
sufficient energy. This process moves these carriers from the drain and onto the gate,
a process commonly called the hot-electron injection gate current.

It is important to note that with hot—electron injection, it is only feasible to move
electrons onto the floating node and they cannot be removed by the same means.
A mechanism called hot-hole injection has been demonstrated as a complementary
operation to neutralize the negatively charged gate, but is not widely used due to its
low hot-hole injection gate current.

There are several models that have been used to characterize the hot-electron in-
jection current such as the lucky, eflective electron temperature, and other physical
models. However, unlike Fowler-Nordheim tunneling, there is no closed form expres-
sion for the gate current and therefore these models are simply quantitative. An
empirical model that can be used for programming floating gate arrays was proposed

by Bandyopadhyay et a1. [34] and is given in Equation (2.3).

A I I initial 2 I initial
ln — == K2 (V03) ln -—-—— + K1(VDS)ln — + K0 (Vps) (2.3)
ISO [so 150

Here, K2, K1, and K0 are unitless functions of the source-to-drain voltage and
[so is a bias current. This expression has been used to accurately model the best

source-to—drain voltage at the injection node during programming to minimize the

15

TUNNEL

Vdd KER.
l: T is...

M1
INJECT

 

 

Figure 2.3. Floating Gate Cell Schematic

number of injection pulses.

Figure 2.3 shows the schematic representation of a floating gate cell. Hot-electron
injection is achieved by pulsing the drain of transistor M1. Transistor M2 is the MOS
capacitor discussed in the Fowler-Nordheim tunneling section. The TUNNEL pin is
a global erase, meaning it is tied to all floating gates in the array. In this example,
the injection pin is also the cell output current. The REF pin is the control gate
voltage which capacitively couples with the floating node to set the gate voltage of
the device. The capacitance C is a parallel plate capacitor (shown in layout in Section
A.1). It is comprised of a parallel plate (POLYl-POLY2) capacitor separated by an

SiOg dielectric layer.

2.5 Analog Floating-Gate Programming Procedure

An algorithm to initialize floating gate arrays is given in Figure 2.4. First, the array
characteristics must be determined to equalize the floating gate cells to a constant
current. This is done by measuring the output source current of each floating gate cell.
An initial control gate voltage is chosen such that all floating gates are conducting a
measurable current. The maximum cell current in the array is then programmed to
every floating gate.

Next, the control gate voltage is increased until the floating gate cells output a

16

 

Initialize variables
moquead = 0
Select first EEPROM cell

 

 

 

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sanctum

 

lnItIaIIze variables

 

SelectfirstEEPROMcoll

 

 

 

 

 

 

 

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EEPROM Col

 

 

 

 

 

 

Madman: Current Found
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EEPROM Col V

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2.4. Floating Gate Transistor Equalization Procedure

minimally resolvable current. Due to mismatch, not all cells will maintain the initial
targeted current during control gate voltage scaling. Thus, the equalization procedure
must be repeated. This process continues until the array is equalized at less than
10 nA at an unspecified control gate voltage. Finally, the array is programmed to

its targeted current levels specified by the application using the previously discussed

hot-electron injection methodology.

17

2.6 Programming Precision

It has been shown that floating gates can reliably achieve an equivalent accuracy of
greater than 13 bits of resolution [6]. The accuracy of floating gate programming
is highly dependent on the measurement Circuit’s ability to resolve drain current
changes between injection pulses, as well as the minimum charge transfer possible
using hot-electron injection. Srinivasan et al. [35] defined a figure of merit (F OM)
given in Equation (2.4) and showed that programming accuracy was constant in the

subthreshold region and improves in strong inversion.

FOM = —log2 <~AI—I) (2.4)

Here, AI is the minimum change in drain current possible for a given I, or the
existing bias current of the floating gate transistor. Essentially, the FOM shows the
resolution of an injection pulse, which for the 0.5 pm process is between 3.2-4.6 bits
up to 1 pA of current and increases quadratically beyond this limit. This increase is
due to a modified AI / I relationship as the drain current equation for strong inversion
contains an overdrive term that depends on the initial floating gate voltage. Thus, to
attain high accuracy, higher floating gate currents are required.

The precision is theoretically limited to the ability to inject a single electron onto
the floating gate. In addition, resolution is also determined by the floating gate
capacitance (CFC). Since AVFG = AQ/Cpg, the change in charge will produce a
larger change in potential across the floating gate if capacitance is decreased. Thus,
larger floating gate capacitors will increase resolution.

With a CFO of 1 pF, [35] showed it is theoretically possible to achieve 17.82 bits
of accuracy with a charge transfer of one electron in weak inversion and 20.09 bits in
strong inversion. However, due to the probabilistic nature of hot-electron injection,

it is difficult to achieve transfer of a single electron to the floating gate.

18

 

2.7 Charge Retention Characteristics

Due to the high quality SiOg insulator surrounding the floating node, floating gates
have the ability to store charge for long periods of time. Charge retention is limited
only by defect densities, which increase under stress such as a high-temperature bake
during PCB population or from a high number of injection/tunneling cycles [32].
Following an initial programming cycle, a slight drift in the floating gate current
results from interface trap site settling. This loss of charge from the Sl02 is when
backtunneling to the silicon bands occurs. Interface trap density may be reduced
substantially, however, through a hydrogen annealing step during device fabrication.
Unfortunately, however, this step is not present in a standard digital CMOS process.

Thermionic emission is responsible for long-term charge loss in floating gate tran-
sistors and is a function of temperature and time. This phenomenon results when
electrons are emitted over the energy barrier toward the control gate or substrate.
Equation (2.5) expresses the fraction of charge lost where Q(t) is the floating gate
charge at time t, Q(0) is the initial charge, k is Boltzmann’s constant (1.38-10'23J/ K),
T is temperature in Kelvin, V is the relaxation frequency of electrons in polysilicon,

and (233 is the Si—Si02 barrier potential.

% = exp [—tu - exp (3135)] (2-5)

It can be seen that thermionic emission increases with temperature. Therefore,
retention tests typically use a series of accelerated conditions, such as storing the
device at temperatures up to 350°C. From these experiments, the relaxation frequency
and Si-Si02 barrier potential may be extracted. Srinivasan et a1. [35] found a 433 of
0.9 eV and V of 60 Hz for the 0.5 pm process by plotting Q(t)/Q(0) for temperatures
between 250°C and 350°C and applying the data to the above model. Thus, over the

course of ten years, a charge loss of 1.14 - 10‘3% is expected at room temperature

19

(25°C). Even in extreme environments where device temperatures can reach 100°C,
charge retention is still 98.5% over the same period of time. Consequently, floating

gates are very attractive as long-term analog storage elements.

2.8 Temperature Dependency

Floating gates suffer from the same temperature dependency as a standard MOS
device. The carrier mobility and threshold voltage are the predominant temperature-
dependent parameters. These are evident in the source current equations for a pMOS

transistor in both weak (2.6) and strong (2.7) inversion regions [36].

 

Q, W VDD - VCG + VFG

IS — L [00623]) ( n(kT/q) ) (2.6)
,W V

IS = K I [(VDD — VCG + VpG — VT) — —:’3] VSD (2.7)

In subthreshold, I Do is a process-dependent preexponential constant dependent
on VT and n is the subthreshold slope factor, which typically 1 < n < 3. Note that
Equation (2.6) does not model the moderate inversion transition region. In strong
inversion, K’ is a process parameter that is dependent on the mobility and capacitance
of the gate oxide layer. It can be seen in these equations that the pMOS transistor
source current is directly proportional to temperature.

Various topologies have been used to offset temperature dependency in current
references. However, these circuits traditionally involve fixing the operating point
through fixed—width transistors. One proposed method [37] uses a floating gate as
a trirnmable element in a temperature-insensitive current source. However, such
references will require current mirrors to bias the control gate voltage, and due to
device mismatch, mirrors can suffer from offset errors. Figure 2.5 shows a floating

gatebased topology for offset removal and was proposed in [38]. Here, 01 and Cg act

20

Vdd Vdd
01 02
., l>—l w H .2
IIN l l IOUT
Figure 2.5. Floating Gate Current Mirror

as programmable multiplicative factors of the mirror. An ideal mirror can be realized
by calibrating the floating gates such that both devices have the same threshold
voltages.

Using a current reference instead of a fixed voltage bias for the control gate has
an additional advantage of being supply voltage invariant, and thus increases the
supply rejection capability of the floating gate cell. This is on account of the control
gate reference VCG tracking the source-to-gate voltage of a diode-connected pMOS
transistor. Consequently, a direct relationship (neglecting mismatch) may be derived
between the fixed reference current and the floating gate output current, scaled by

the floating gate voltage V02 as given in Equation (2.8) below.

IOUT = ea: (V02 - V01) (2.8)

[m nkT/ q
Equation (2.8) gives the output current scaling factor for weak inversion and is
based on the difference in charge stored on the floating gate cell and the floating gate
reference. Furthermore, it is possible to decrease floating gate currents in relation to
the reference current through increasing the charge on Cl, which may be useful if the
sink current I m is significantly large.
This analysis has shown that techniques exist to compensate for device and tem—
perature variations in floating gate elements. Although these topologies solve some

operational deficiencies, they create new problems such as increased circuit com-

21

plexity, which leads to calibration and testing challenges. Also, these circuits offer
reduced flexibility as the temperature—independent biases must be designed around a
target current or a specific region of operation. Furthermore, such bias circuits add
to the overall power budget of the chip and must be designed to meet the targeted

specifications.

2.9 Summary

In this chapter, the fundamentals of erasable programmable solid-state memories were
described. The history of non-volatile semiconductor memories was discussed, laying
the foundation for an analog memory storage element. Floating gate devices have the
ability to replace fixed current sources and sinks in analog integrated circuits. Their
flexibility in reprogrammability allows them to be used for not only calibration and
trimming, but as template storage, opening up the possibility for on-chip learning.
Next, the mixed-signal test station with automatic floating gate cell programming
support will be described. It can be seen that mixed-signal systems-on-chip with
floating gate cells require extensive peripheral circuitry. This work aims to provide

this support in a modular fashion for rapid design evaluation and validation.

22

CHAPTER 3

Floating Gate Test Station Design

The need for a test station to automatically calibrate floating gate transistors and the
difficulty in setting precision current sources for analog computation was outlined in
Chapters 1 and 2. The system required to perform the operations of hot-electron in-
jection and tunneling, as well as performing data acquisition for the forward-feedback
process of floating gate programming has been carefully designed to meet the targeted
specifications. In addition, this system must also be a fully-functional mixed-signal
test station, and be able to set the bias conditions for the device under test and pro-
vide digital control interfaces. This chapter discusses the design of each subsystem

and its targeted performance.

3.1 Noise and Shielding Considerations

When designing analog and mixed-signal systems, noise becomes an increasingly ap—
parent limitation when trying to resolve signals in the millivolt and sub—millivolt
range. Additionally, noise may not only be a random phenomenon, as detector sys-

tems can pick up correlated, spurious signals as well.

23

 

 

Circuit A Circuit A

l J L—F—J
X »— Y Ground Plane Ground Plane
J. [ .1. .J_ _J_

J " 7 Fri T

Circuit B Circuit 8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3.1. Circuits with Ground L00ps Figure 3.2. Local Return Paths Only

3.1.1 Shared Current Paths

The most common type of unwanted signal transfer is caused by ground loops, also
known as shared signal paths [39]. Figure 3.1 illustrates shared current paths for two
independent circuits. Circuits A and B both have their own dedicated current return
paths. However, because current will target the path of least resistance, it will flow
through the ground plane. Large currents between nodes X and Y cause a potential
difference across the ground plane, inducing an additional voltage at node X.

Figure 3.2 shows an improved layout of circuits A and B that limits current flow
in the ground plane to currents entering or leaving circuits A and B only. Each circuit
has its own dedicated current return path, so no shared DC path exists, thus limiting
any transient spikes on circuit A to affect circuit B.

However, paths need not exist explicitly for ground loops to form. In time-varying
signals, parasitic capacitances may exist between these nodes and the ground plane.
Thus, spurious voltages are formed on the critical node as a result of AC coupling
and charge injection with the ground plane. Furthermore, induction can cause charge
injection onto critical nodes as well if they exist between time-varying signals and the
return path. Therefore, it is essential to tightly route the signal and its return path,
minimizing induction through field cancellation.

Shared current paths have been minimized in layout by connecting all ground and

24

power pins for each circuit to centralized nets [40]. These nets are connected to the
power planes though single or concentrated vias. Furthermore, AC coupling through
parasitic capacitance has been reduced by routing time-varying signals away from

sensitive DC signals as well as through shielding techniques.

3.1.2 Shielding Techniques

One method to reduce the effects of electromagnetic interference is to use contiguous
shielding. A contiguous shield is one that completely surrounds sensitive signals, thus
attenuating and reflecting the majority of any incident wave. The fraction of the wave

that is reflected is given by Equation (3.1).

Z3 ie
E0, = E0 (1 —— —§——‘i) (3.1)

0

Reflection is high because the impedance of free space (Z0) is approximately 377 Q
and the impedance of the conductor is much lower, thus E0, z E0. Additionally, the
signal is attenuated because any absorbed wave produces a local current whose mag-
netic field opposes the incident electromagnetic wave. The total current in the shield
decreases as the wave penetrates deeper into the material, and the wave penetration
depth (6) may be calculated by the equation given in (3.2) where f is the frequency
of the incident electromagnetic wave, p, is the permeability and p is the resistivity of

the conductor.

 

 

6: 2.110_4[ cm-s—l] ”ff (3.2)

Thus, if a shield is adequately thick, has a high enough conductivity and low
permeability, the majority of the incident electromagnetic interference will be isolated
from the inside of the enclosure. Therefore, during testing, a contiguous shield will

be placed over the test setup to reduce the effects of light and RF pickup.

25

In addition to contiguous shielding, additional internal shielding methods are em-
ployed to prevent capacitive coupling from transferring interference onto sensitive
nodes. The technique employed is called field line pinning and works by placing a
conductor between the interfering source and the critical node, thus absorbing the
field lines and shielding the node.

This is implemented by placing all digital signals on the bottom layer and analog
signals on the top layer. Two inner layers act as ground and supply planes, providing
the intermediate conductor. The dielectric material between the outer signal layers
and inner planes is fiberglass with a dielectric constant of approximately 4—4.9 and
a thickness of 12 mils [41]. Furthermore, the inner planes are separated by a 28 mil
core of laminate. Thus, a high capacitance exists between the interference node and
the intermediate node, allowing the ground plane to absorb the field lines of noisy

digital signals.

3.2 System Architecture

Figure 3.3 shows a block diagram of the mixed—signal floating gate test station and
its interface with external digital control via a field-programmable gate array. All
voltage-mode channels are passed through a lOO—pin connector to an adjacent board
that houses the device under test. Current-mode circuits interface through BNC
connectors that provide contiguous shielding for noise reduction.

The main digital bus runs vertically on the underside of the board and is responsi-
ble for controlling all sub-circuits. In addition, 13 channels of digital I / O are reserved
for the 100-pin header, and connect to the daughterboard. Each sub-circuit is dis-
cussed in the remaining sections. The FPGA-based controller is discussed in detail

in Chapter 4.

26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Figure 3.3. Block Diagram of the Mixed-Signal Test Station

27

 

 

 

 

 

T IN OUT ‘
R
C ADJ 1$ —— Ca

 

 

 

 

 

Figure 3.4. Voltage Regulation

3.3 Power Circuits

Proper supply regulation is important because it provides a stable voltage to sensitive
analog circuits whose output may become distorted if the power supply rejection ratio
is low. Furthermore, it is important to have separate supplies for both analog and
digital signals, since Section 3.1 showed that digital switching can cause considerable
noise on the supply rail. The board contains three linear voltage regulators and three
DC / DC converters. A 15 V boost converter is required for Fowler-Nordheim tunneling
in the AMI C5N 0.5 pm CMOS process. Additionally, the digital potentiometers and
operational amplifiers in the current ADC and DAC circuits require a -5 V VSS supply
rail. The hot-electron injection circuit requires a -2 V VSS supply rail. These are

provided by two switched-capacitor voltage converters.

3.3.1 Voltage Regulation

The board is powered by three LM1086 1.5 A low dropout positive voltage regulators
[42] using the adjustable topology shown in Figure 3.4. The voltage VU is provided
by a 9 V nominal unregulated power adapter with an open circuit voltage measured
at 13 V. Capacitors Cl, Oz, and 03 are 10 uF tantalums rated for 16 V. Additionally,
resistors R1 and R2 make up a voltage divider that allows adjustment of the regulated

voltage.

28

 

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33uF L "
I LBI Lx bier .N 500
T J;— REF MAX762 V+ voo our OUT
SHDN _ ucca7322
I T GND
' _J__ -_- __l_ AVDD3.3

Figure 3.5. Tunneling Control Circuit Schematic

Tuning the regulators becomes important when it comes to precision measurement
because it determines the supply rails and reference voltages of the ADCs and DACs.
Any small fluctuations will directly aflect the scaling of any digital input /output
codes.

The three voltage regulation circuits are shown in Appendix B.16. U0 is calibrated
to 5 V and can provide power directly to the FPGA development board, eliminating
the need for the board’s own regulated 5 V supply. U1 also provides 5 V, but is used
to supply the test station’s own circuits. U2 provides 3.3 V to the test chip, as well

as to the Fowler-Nordheim tunneling circuit for the idle voltage.

3.3.2 Fowler-Nordheim Tunneling Supply and Control

The tunneling supply is provided by the Maxim MAX762 15 V step-up switching
regulator [43], which is capable of providing 150 mA of output current at an effi-
ciency greater than 80%. Figure 3.5 shows the configuration of the tunneling supply
connected to its control logic via the UCC37322 gate driver [44].

The input voltage range for the MAX762 is 2 V to 16.5 V. To reduce the load on the
5 V regulators, the unregulated supply is connected directly to the boost converter,
which also increases the efliciency of the converter by reducing the switching frequency

and increasing the gate-to-source voltage of the internal MOSFET. The device is

29

-------------------------------------------------

 

 

   

 

o TRIG —<)<]T _

ONE-SHOT

LCD—s

 

 

 

 

 

 

 

 

ii
E

 

 

 

 

 

 

 

TRIG Q’
ONE-SHOT

 

 

 

 

r--------_--¢--—-----—--—--—------—

Figure 3.6. MAX762 Simplified Schematic Diagram

operated in the bootstrapped mode, meaning its supply current is drawn through the
output node.

Figure 3.6 shows a block diagram of the MAX762’s internals, simplified from the
datasheet’s own diagram to emphasize the features used in the circuit given in Fig-
ure 3.5. The basic theory of operation of the device is as follows. The regulated
output voltage is set by charging up the 33 ”F output filter capacitor. This is accom-
plished by pulse-frequency modulating the LX line. First, LX is pulled to ground,
causing current to ramp up inside the inductor. Next, LX is released and becomes
a high-impedance node. Since current cannot change instantaneously inside an in-
ductor, the current is forced through the Schottky barrier diode and charges up the
output capacitor.

A closer look at Figure 3.6 reveals that there are two primary functions of the
MAX762: to detect undervoltages as well as to limit the current flowing through the

inductor. Resistors R1 and R2 act as a voltage divider and connect to the undervoltage

30

comparator. This output is fed to an S—R latch as well as a one-shot monostable
timer. The purpose of the latch is to determine whether the internal N-channel
power MOSF ET M1 should be turned on.

When enabled, the power MOSFET allows the increased current in the inductor
to flow through R3. When the voltage across this resistor exceeds V2, the peak current
comparator output goes high. This causes the S—R latch’s reset to go high and sets
the output Q to low, turning off the power MOSF ET. This prevents the chip from
sinking more than its 1 A peak current limit.

In addition to a current limit, the MAX762 also limits the “on” pulse width
through the one-shot monostable multivibrator at the output of the undervoltage
comparator. When the comparator detects a low voltage at V+, the output of the
timer goes low for 8 as. This sets the maximum time at which the LX pin is enabled
through M1. If the peak current is exceeded, the reset on the S-R latch is still tripped
via the current comparator.

A minimum delay between pulses is controlled by the second one-shot monostable
connected to the output of the S-R latch through an inverter. This disables the S
input on the latch for a duration of 1.3 us. After this minimum time, M1 either
remains off if the output is in regulation, otherwise the cycle repeats if the output is
out of regulation.

The output of the MAX762 acts as the power supply to the Texas Instruments
UCC37322 high-speed, low-side MOSFET driver. The UCC37322 provides an output
of either 0 V or 15 V based on input logic issued from the F PGA. The output of this
MOSFET driver is connected to a resistor and Schottky barrier diode in series. When
the output of the driver is 0 V, the diode prevents the ‘OUT’ node in Figure 3.5 from
falling below one diode drop less than the output of the 3.3 V regulator. The resistor
provides a low current path back to the grounded output of the UCC37322.

When the output of the MOSFET driver is 15 V, the diode does not conduct

31

Idle Voltage

 

 

 

 

Inject Bias (DAC #39 = 3V)
(DAC #37 = 2V) °
Inject
(FPGA 05) °
V
Threshold
MAX1681 __ (DAC #38 = 1.5V)

 

 

,...\ 1uF

 

 

 

 

 

 

;:1UF '— I
tuF

 

 

 

 

 

 

 

 

Figure 3.7. Injection Comparator Circuit

and the ‘OUT’ node is set directly to the output of the driver. Because the global
tunneling pin is a high-impedance node and tunneling currents are on the order of
picoamperes, the voltage drop across the resistor is primarily due to the reverse bias

leakage of the Schottky barrier diode, which can be in excess of 1 mA.

3.3.3 Hot-electron Injection Supply and Control

Hot-electron injection is the method used to add charge to the floating gate. Figure 3.7
shows the schematic of a comparator circuit to switch the global injection pin from a
user-set idle voltage and the -2 V injection voltage.

The MAX1681 [45] is a frequency-selectable, switched-capacitor voltage converter
that inverts a 2 V input voltage to -2 V for the VSS supply rail on the OPA2743 [46]
op-amp comparator. Since the injection current is proportional to the drain-to-source
voltage drop across a floating gate transistor, the inverted voltage of the MAX1681
may be adjusted during runtime to modulate the amount of injection current. Thus,
both amplitude modulation and pulse-width modulation programming methods are
supported. However, the minimum input voltage is 2 V, therefore only larger injection

currents are supported.

32

Since transistors can break down at 8 V in the AMI C5N process, it is not‘rec-
ommended to exceed a 4 V positive voltage input. This is prevented by the 4.096 V
precision reference used in the voltage DAC, which is used to set the positive voltage
supply of the MAX1681.

The OPA2743 is a high speed, rail-to-rail operational amplifier. The device has a
slew rate of 10 V/ps, allowing injection pulse widths as small as 1 us. The positive
supply rail is connected to voltage DAC channel #39, and is initialized to 3.3 V
during test station startup. The negative supply rail is connected to the output of
the MAX1681 and is controlled by DAC channel #37. The threshold voltage for
the comparator is set by DAC channel #38 and is configured at startup to 1.5 V, a
midpoint for FPGA logic signals.

The injection pulse is provided by the FPGA and uses negative logic. Therefore,
when the negative terminal of the op—amp is set to low, no injection occurs and the
‘Inject Out’ node shown in Figure 3.7 is set to the positive, idle voltage. Likewise,
a logic high on the negative input terminal produces the negative, injection bias as

output.

3.4 Voltage Digital-to—Analog Conversion

Five LTC2600 octal 16-bit voltage-output DACS [47] are used to provide 40 channels
of voltage digital-to—analog conversion. A block diagram of the LTC2600 is shown in
Figure 3.8.

The LTC2600 is programmed in a straightforward manner using a serial periph-
eral interface that is described in detail in Section 4.9. After receiving the update
instruction in the 32-bit shift register, a decoder updates the DAC register associated
with the selected channel. The ideal output voltage is given by the following transfer

function:

33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

01: GND voo I°
I I
' DAC 7 Input 4 A Input DAC :
or DAC 0 Re ister Register Re ister Re ister :9 DAC 7 To
* T % 0%C I
OL D AC 1 (:3 DAC ::I Input It Input LtIDA I: D AC 6 Jo
. Register Re ister Register Re ifter I
I + r I
I , I
I DAC Input Input DC I
. DAC 2 3:] Register . ister ¢ $I Rgiister Re ister DAC 5 To
I I
' DAC 3 7 Input Input EDIDA '
o-I- DAC 3 Re ister Re ister ¢ :9 Re ister Re iscfer :5 DAC 4 -I-o
I .. I
oI REF CLR’ Io
I Control Decoder I
I ' {F o I

 

 

 

 

 

it

 

 

I— 32-bit Shift Register

 

§DI :0
0
Figure 3.8. LT C2600 Block Diagram
:t:
VOUT = (213) ‘VREF (33)

where a; is the input code given in 24—bit binary and VREF is the reference voltage set
via the REF pin.

The REF pin is connected to an LT1461 precision voltage reference [48] set to
4.096 V, which sets the maximum voltage output of each DAC channel. In addition,
each channel is capable of sinking or sourcing up to 15 mA, making it an ideal supply

for the hot-electron injection circuit.

3.5 Voltage Analog-to—Digital Conversion

Sixteen channels of ADC input are made available through the use of the Linear
Technology LTC2418 24-bit delta-sigma converter [49]. Figure 3.9 shows a block
diagram of the LTC2418’s internals, as well as its configuration on the board.

The LTC2418 is a 3rd order A2 ADC, which is an advantageous ADC architec-

34

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I- -I ---------------------------- 1
I VD“ LTC2418 I ' ......... .
CH1 . r Oscillator +IF0 < I
83% 0' B ROI-I- : : g :
°——- . . I I
' ° 1x? DIfferentIaI Decimating Serial Iiggk I: i
' z 5% T” 3rd0rder T” FIR T” Interface Joisoo I" E
CH15 o'— 3 AZ Modulator —I0: 08’ I
owe .L__ 2 R 1 l ----------
2.5V Leno i i

 

 

Figure 3.9. 16—Channel Voltage ADC

ture due to its high resolution and linearity, which is critical for precision measure-
ment. Also, unlike traditional A2 ADCs, this part has zero latency, meaning data is
available before beginning the next conversion cycle. The ADC is capable of handling
differential input, however, an LT1461 precision voltage reference of 2.5 V connects to
the common terminal for single-ended input. Therefore, each of the sixteen channels

has a rail-to-rail input voltage range as is given by the following constraint equation:

— 0.5 - VREp g VIN g 0.5 - Vppp (3.4)

where (REE. — REF.) = VREF and is equal to 5 V and VIN = IN+ - 2.5. Addi-
tionally, the digital output code monotonically increases with input voltage, meaning
the output code is not represented in two’s complement. Equation (3.5) translates

the received binary code into an equivalent analog voltage between 0 and 5 V.

35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+§V IN OUT A
REF192

4.7uF == GND 1uF £2, 4 w R

3 {T +5V

OPA2743

B + VL

-5V
Rt

Figure 3.10. Precision Current Source

3.6 Multi-channel Current Digital-to-Analog Conversion

Figure 3.10 shows the schematic for a single channel precision current reference [50].
Eight channels have been included for providing input bias currents for nMOS-based
input current sinks.

The basic circuit operation is as follows. The REF192 precision voltage reference
[51] maintains a constant 2.5 V between nodes A and B, and is bypassed by a 1 [IF
tantalum capacitor. An AD7376 digital potentiometer [52] acts as a voltage divider
by setting the value of the wiper at node W. The op—amp is in a negative feedback
loop, forcing the positive and negative input terminals to a virtual ground. This
causes nodes VL and W to be set to the same voltage if ignoring the offset of the
amplifier.

Therefore, by setting the value of the wiper resistance in the digital potentiometer,
the voltage across the resistor R is fixed by the voltage divider, and Ohm’s Law
determines the current flowing through the resistor and into the load. Also, since
the current range is determined by the value of the resistor, the value of R has been

spaced exponentially across channels to give the highest range.

36

* AD7376 Model

* A W B

.SUBCKT POT10K 1 2 3 7 8

ERA 1 6 VALUE = {V(7,8)*1OK*I(V81)}

V31 6 5 0

RS 5 2 1

ERB 5 4 VALUE = {(1-V(7,8))*1OK*I(V32)}
V82 4 3 0

.ENDS

Figure 3.11. AD7376 Digital Potentiometer SPICE Model Schematic and Code

 

The output voltage range at VL is from -5 to 2.4 V. The AD7376 digital poten-
tiometer has a VSS of -5 V, making its wiper voltage swing capable of i5 V. The
OPA2743 has a rail-to-rail input voltage swing, allowing VL to drop to the negative
supply. If VL exceeds 2.4 V, the precision voltage reference will decrease its output
voltage if VAW is set to 2.5 V, since the supply range requires a minimum of 2.6 V.

Figure 3.12 shows a SPICE simulation of the current DAC’s DC response. The
macromodels for the REF192 and OPA2743 were used during simulation. However,
the AD7 376 was modeled separately as two voltage-controlled voltage sources in series
with two independent DC sources set to 0 V. The digital potentiometer is modeled
in Figure 3.11. The voltage across the ERA dependent source is proportional to the
resistance of the potentiometer multiplied by the current through the V51 independent
source and the value of an external source (V733, which sets the wiper ratio). The other
dependent source is set in a similar manner, but its voltage is set according to the
remaining fraction of the wiper.

The value of R in Figure 3.10 was set to 2.2 MG, which is the value of R9, R11,
R13, and R15 on the test station. These correspond to the first four DAC channels.
Channels #5 and #6 are set to 100 k9 and the remaining two channels are set to
10 k9, providing a larger source range. It can be seen from simulation that the current
DAC is linear across its entire range and is inversely proportional to the code set in

the potentiometer’s internal register.

37

 

Current DAC Simulated DC Response

I I I 1

Output Current (uA)
O .0
O) on

.0
.5

0.2 '

 

 

 

 

120 100 80 60 40 20 0
Digital Potentiometer Input Code

Figure 3.12. Precision Current Source DC Response

Figure 3.13 shows the step response of the current DAC, which tests the stability
of the circuit. Although there is a slight overshoot and ringing, the circuit settles
in under 3 us. This ringing may be eliminated by changing to a lower bandwidth
op-amp such as the TLC2252 as used in the current ADC; however, this will result

in a longer settling time.

3.7 Multi-channel Current A / D Conversion

Precision current measurement is accomplished through the use of a I-V converter as
shown in Figure 3.14. The ADG715 [53] contains eight channels of serially-controlled,
single pole, single throw switches that are used to multiplex input currents. The
TLC2252 [54] that is in a negative feedback configuration allows I-V conversion across
the AD7376 digital potentiometer. Additionally, the output voltage of the op-amp is
sampled by the 24—bit, LTC2415—1 A2 ADC [55].

38

 

Current DAC Simulated Transient Response

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5C 9 9
2
3
’5
t
3
o
E
o I
3 4 5
3’ MI ' I III/MN
E 0.4 -
§
0
15 0.2
o (Ir—I 4 . ‘
0 1 2 3 4 5
Time (us)

Figure 3.13. Precision Current Source Transient Startup Response

Not shown in the figure for simplicity is a unity gain buffer between the output
of the I-V converter and the input of the ADC. This buffer isolates the switched-
capacitor front-end of the ADC from the I-V circuit. The LTC2415-1 has a dynamic
input current that is set by this switched capacitor network at a frequency of half the
conversion clock rate (see Section 4.4) and is dependent on the source impedance and
input capacitance of the external circuit.

Analog-to—digital conversion involves turning on a single switch in the ADG715
and calibrating the gain of the I-V by setting the wiper on the digital potentiometer.

The I-V output is given by Equation (3.6).

1m = (VA — VW) /RAW (3-6)

The reference VA % VRE F - VA M p_0 F FS ET and VA M p_0 17 p3 ET is the amplifier input

offset, which is sampled during an initial calibration step. VREp is an adjustable offset

39

IZC Interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

___________ I |
I- T- ? meas A AD7376 3
cm SCL SDA JIN— —°
CI-I2 0—
CH3 0— Vdd
CH4 0— W Vdd SPI
CH5 0_ ADG71 5 _ —r- .93 55391
CH6 0— I
cmo— “m“ LTC2415 . i
cm 0— GND 0— + 2.5V 0— IN- 24-bit ADC I
REF I I
-J_— (DAc #40) _ GND L _____ i
_ - I

Figure 3.14. Current Measurement Circuit

and is set by the 40th channel of the voltage DACS. Its default value is set to 1 V
during system startup. The value of RAW is iteratively chosen to maximize the poten-
tial across VAW, which helps to minimize the measurement error caused by the series
resistance RW internal to the potentiometer. The output Vw is measured directly by
the ADC and the current computed in Equation (3.6) is handled in software.

Figure 3.15 shows the DC response of the I-V converter. For the simulation, the
AD7376 was replaced with a 2.2 M52 resistor, enabling resolution of sub—nanoampere
currents, a modification that has also been made to the board for testing the floating
gate transistors.

Figure 3.16 shows the stability of the current ADC’s I-V converter by simulating
its step response. This I-V circuit was initially designed with the OPA2743 that was
used previously in the injection and current DAC circuit, but was shown to cause
stability problems both in testing and in simulation. A beta network analysis also
reveals the OPA2743 to be marginally stable in this configuration.

Due to small source currents, the input impedance is very large, and fl approaches
one as given by the following equation where R1 is the input impedance to the I-V

converter and R2 is the feedback resistance.

40

Current ADC I-V Simulated DC Response

 

_5
0|

.5
I

Output Voltage (V)

0.5

 

 

Mr

 

 

0
Input Current (nA)

Figure 3.15. Current ADC I-V Converter DC Response

 

Current ADC I-V Simulated Transient Response

15 .

_s
O

I I

 

 

Input Current (M)
01

 

 

 

 

 

 

 

0 u
-5 l L l l
o 10 20 30 40 50
1.03 . .
a 1.02 r -
*3 l
> 1.01
'5
a t -
o
O.” a 4 e a
”0 10 20 30 40 50
Time (us)

Figure 3.16. Current ADC I-V Converter Transient Response

41

1
R1 [IN

[3: R1+R2 = T};+2.2Mn

 

 

(3.7)

As IIN is small, 6 ——» 1. A plot of the open loop gain and phase versus frequency
in the OPA2743 datasheet shows that the phase margin is less than 20° when the
open loop gain crosses unity. Although marginally stable, a SPICE simulation of the
step response showed oscillations. However, the TLC2252 has approximately a 30°
phase margin at the unity gain crossover frequency and is shown to be stable with a

settling time of approximately 6 us.

3.8 Testing Considerations

Each of the previously described circuits are globally enabled through a series of
jumpers, which are described in Table 3.1. These jumpers aid in the initial population
and testing phase, and act as power-on resets during control logic testing. These

jumpers also enable supply current measurement for each sub-circuit.

 

Designator Description
JPO DGND to AGND Inductor Bypass
JPl Unregulated Supply
JP2 F PGA Supply
JP3 5 V Regulator Output
JP4 3.3 V Regulator Output
JP5 Current ADC Supply
JP6 Current DAC Supply
J P7 -5 V DC / DC Converter Input Supply
J P8 Boost Converter Input Supply

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3.1. Jumper Descriptions

42

3.9 Summary

This chapter covered the design and implementation of the floating gate mixed-signal
test station. To obtain high precision, both noise and shielding issues have been ad-
dressed through layout and part selection. Additionally, reference calibration through
manual potentiometer adjustment and offset sampling techniques have been imple-
mented to improve converter accuracy. These details will become apparent when
trying to resolve sub-nanoampere currents during the floating gate programming pro—

cedure. Figure 3.17 shows a picture of the completed test station motherboard.

43

 

Figure 3.17. Mixed—Signal Test Station Populated Printed Circuit Board

44

CHAPTER 4

Floating Gate Test Station Control

Now that the system architecture and circuits have been well-defined in the previous
chapter, a control logic is necessary to handle high-speed digital communication with
the motherboard. The test station is controlled via a Xilinx XC3S200 Spartan-3 [56]
field-programmable gate array. A commercially-available development board [57] for
this FPGA is directly connected to the floating gate test station motherboard. The
control logic has been written in VHDL and synthesized for direct representation of

the FPGA’s firmware as a bitstream file and is stored on an adjacent EEPROM chip.

4.1 Instruction Decoding and Execution

The test station’s main controller is shown in block diagram form in Figure 4.2.
This main module is responsible for handling system startup as well as enabling
and disabling each sub-module based on the incoming instruction. Each instruction
is sent serially over the RS-232 interface as a 16—bit packet and is stored in the
currentjnstr'uctz'on variable. A global instruction pointer is then incremented, which
allows the module’s state machine to recognize incoming instructions.

As new instructions arrive, they are immediately decoded and executed. There is
no FIFO queue for instructions, so the main controller must complete execution of the

previous instruction before beginning the next instruction. Although a limitation of

45

 

i

Digital Clock Manager

 

 

rxd

txd

Serial l/O

 

 

serial_out
serial_clt

Serial Shifter

 

Walk
damned

I

dummy

 

Digital Pots

 

 

 

dIQItILIOI

E
_I_ 1111 :1: 11,1.

Digital I/O I

 

domed
aIgIt.vuI

_‘I_L

Seven Segment
Display

 

 

Intact C—I Injection I

 

 

 

Voltage DACs

80k.“ .—
“m ._ Voltage DAC
Mm” ._ MultIpIexer

 

 

I Serial Mux

 

 

9 Execution Control

 

Memory Xfr

 

 

 

Memory I/O

HIIHHHI

 

 

 

Memory Mux

 

 

 

Current ADC

IIIIH

 

 

 

 

 

Signal Generator

 

Voltage ADC

HUI

 

 

Figure 4.1. System Controller Block Diagram

46

Iadc_elt
Iadc_sck
iadc_oe_bor
ladc_ado
Iadc_sda
iadc_ecl

adc_clk
adc_sok
adc_cs_bar
adc_adl
adc__edo

 

clk .— -. program_dac
vdac_uloct .— —. dac_programmed
sig_gen_enable .— —. dac_lnsh‘ucflon
sig.gen_oomplete .— _. adc_oonv_modo
serial_ooroct .— '. ‘°°—'°°'°“
txd_ready .— —. adc_data_ready
txd_oomplete .— _. adc_data_collect
rxd_complete ._ —. ladc_data_ready
parallothd .— —. iadc_data_oollect
paralloerd .— —. injechulse
“”3”” '— Execution Control '" “be—“‘9“
shift_end_flag .— —. lnbcflonm_vfldth
lads .— -. tunnel _pulse
lod_datn .- -. lo_lnstructlon
from_addms .- —D lo_update
to_addross ._ —. lo_updated
read_block .— _. lo_output
write_block .— _. dlgltaLpoLnumbor
mom_dau_ln '- —. dlgltaLpoLvalue
xfr_op_completed .— ~—. digital _pot_update
modulo_uloct h —. digital _pot_updated

 

 

 

Figure 4.2. The Instruction Decoding and Execution VHDL Module

47

 

the instruction decoding architecture, this does not pose a great risk to the operation
of the system due to low overhead and latency of instruction execution. Additionally,
the PC—based software interface always waits for an acknowledgment packet before
sending additional instructions.

During the idle state, each module is disabled and the three system multiplexers
are put in their neutral states. Upon receiving a new instruction, the instruction
pointer increments, which is identified in the idle state and instruction decoding

begins.

4.1.1 Instruction Set

The system uses the four most significant bits of the first packet to decode the in-

struction. Table 4.1 details the instructions available and their basic function.

 

Code Description
0000 Loopback
0001 Memory Transfer
0010 Voltage Digital-to—Analog Conversion
0011 Voltage Analog-to-Digital Conversion
0100 Current Digital-to—Analog Conversion
0101 Current Analog-to—Digital Conversion
0110 Floating-Gate Transistor Injection
0111 Floating-Gate Transistor Tunneling
1000 Digital I/O
1001 Signal Generation
1010 Serial Shifter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4.1. System Instruction Set

The system then jumps to the appropriate state based on the properly decoded
instructions. Any illegal instruction is ignored and the controller enters the idle state
on the rising edge of the next clock pulse.

Some instructions are longer than one, 16-bit word and require subsequent packets

to be sent and decoded. An example of this is any operation that requires memory

48

access. The FPGA development board includes 512 kB of SRAM available through
an external chip. These memory addresses are 19 bits wide and block memory trans-
fers require two addresses to be sent: one for the starting address and one for the
ending address. Additionally, if data is to be written to the on—board memory, an
additional packet is required. This structure is handled automatically by the internal
states of the system controller. Since the instruction packet is incremented whenever
a new instruction arrives, the system controller expects additional packets whenever
a multi-packet instruction is decoded. Additionally, during each of these states, the
inst.pointer.last variable is updated in order to distinguish changes on the main in-
struction pointer.

After an instruction is executed, an acknowledgment word is sent back to the PC
so it may resume its own script execution. This is handled by sending the controller
into the loopback state (state 3). The data stored in the current_instruction variable
is transferred to the serial I/O module for data transfer. This variable is reset to zero
prior to this operation to ensure data integrity.

Next the system controller returns to the idle state and sets the instruction pointer
and its comparison register inst.poz'nter_last to zero. This is necessary to prevent
the instruction pointer register from rolling over after receiving a large number of
instructions. Since the controller can only execute one instruction at a time, the

value of the instruction pointer does not have any effect on future instructions.

4.2 Digital Input/ Output

The board includes a 13-channel digital I / 0 interface between the PC and the device
under test. Figure 4.3 shows the block diagram of this module.

The signal digital_ios is a 13-bit wide input / output bus that connects directly to
the FPGA’S I/O pins. All other signals are connected to the instruction execution

module. The instruction signal is a 6—bit wide bus that contains the channel to update

49

 

clk
io_update
io_updated Digital I [O F. dlgitaLlos

instruction

output

HHT

 

 

 

Figure 4.3. Digital I/O VHDL Module

(stored in the four least-significant bits) as well as the direction of the data flow and
any data that must be written to the digital line.

Two internal state machines control the current state of the module and the
state of the digital_ios signal. During system startup, all channels are set to a high
impedance state. Next, the module sits in an idle state and waits to receive the
update flag when the io_update signal is high on the rising edge of the FPGA clock.
Then, the channel to update is decoded from the instruction signal and it is set to a
high impedance state for one clock cycle. If the most-significant bit of the instruction
signal is high, the channel enters the writing state, otherwise it enters the reading
state. If the channel enters the reading state, its data is latched to the output signal’s
register where it remains until it is overwritten during the idle state. Finally, the
io-updated flag is set to high for a duration of one clock pulse for the system controller
to acknowledge that the I/O operation has completed. The module then returns to

the idle state and resets the acknowledgment flag.

4.3 Digital Potentiometer Control

The board contains nine digital potentiometers that are daisy-chained together for
control via a three-wire serial peripheral interface. Each potentiometer is seven-bits,

which implies a 63-bit serial chain to program all potentiometers simultaneously.

50

 

clk
dlgltal-pot_numbor
dlgltaLpoLvaluo
digital_poLupdate
digital_poLupdated

—. digital_poLclk
—. digital _pot_sdi
l" digital_poLcs_bar
—. digital _pot_shdn_bar

Digital Pots

HHT

 

 

 

Figure 4.4. Digital Potentiometer VHDL Module

cs*\ .. r—+

 

Figure 4.5. Digital Potentiometer Serial Peripheral Interface

Figure 4.4 shows the signal assignments for the digital potentiometer controller. The
input signals from the execution controller include the number of the device in the
daisy chain, the value to store in the device, and an update flag for when these registers
are ready to be sampled. The clock, serial data input, chip select, and shutdown lines
connect directly to the digital potentiometer.

Upon receiving the update flag, the module decodes the device number and goes
into serial shifting mode. During the shifting operation, the serial chain is rotated
in a 63—bit register to retain the values previously updated in the other devices. The
shifting operation occurs at 390 kHz, allowing an update frequency of 6.2 kHz. After
the shifting operation completes, an acknowledgment flag is set to high for one clock
pulse before returning to the idle state.

Since the digital potentiometers are used for both the current analog-to-digital
converter as well as the current digital-to—analog converter, the update process is

controlled globally by the execution controller. This eliminates the requirement of an

51

 

—. iadc_clk
—. iadc_sck
clk .— —. iadc_cs_bar
—. iadc_sdo
iadc_data_collect .— -. iadc_sda
iadc_data_ready .— Current ADC r. iadc_scl
ladc_address .— —. read_control
iadc_starLaddross .— —. write_control
iadc_end_addross .— —C mem_op_completed
—. address
—. memory_data_wrlte

 

 

 

Figure 4.6. Current ADC VHDL Module

scL W
sm W0 A1 A0 rvw sameacameieim
Start Stop

Condltlon‘— “an“ BY“ —’ 0'“ BY“ —* condition

 

Figure 4.7. Current Channel Multiplexer 12C Interface

additional multiplexer for the potentiometer control signals from both the execution

controller and the current ADC.

4.4 Current Analog-to-Digital Conversion

The board incorporates a 24-bit delta-sigma voltage mode analog-to—digital converter
in conjunction with a 128-position digital potentiometer, an eight-channel analog
multiplexer and operational amplifier to make up the current ADC module. This
FPGA module controls the three interfaces between the ADC, potentiometer, and
multiplexer to resolve currents in the nanoampere range.

From a data acquisition perspective, the channel number, gain and number of

52

53130292827262524

3m>—\n_ 5:°° 0'" 9'6 CEEE®H®®®®®®W

Convmlon Result E

CS

 

 

 

 

1:; "

r
r
I
I
u
Octal/O M:

Figure 4.8. Current ADC Serial Peripheral Interface

samples are specified. These are provided by four, 16-bit packets to the execution
controller, which then slices them into the starting address, ending address, channel
address, and gain. The memory addresses are required because the data is first stored
into the FPGA board’s RAM modules before being transferred over the communica-
tion bus, acting as a buffer to allow real-time data acquisition. Data is ultimately
transferred over the serial line via the block memory transfer module. The three
most-significant bits of the memory addresses as well as the ADC channel number
are obtained from the first instruction packet.

The gain update is provided by the seven least-significant bits of the fourth in-
struction packet. Gain update only occurs when the most-significant bit of this packet
is set to ‘1’, otherwise no gain update occurs. This reduces the overhead and improves
the performance of the ADC module.

During startup, the module initializes all of the internal variables and external SP1
and 12C signals, and waits in the idle state until the iadc_data-collect signal is high.
Next, it initializes the multiplexer serial chain and enters shifting mode to update the
analog multiplexer. The analog multiplexer uses an 12C interface, however only the
writing mode of the protocol has been implemented.

After the multiplexer is updated, the single-channel, 24—bit ADC is reinitialized
by shifting out the previous conversion. This is completed since the ADC begins

conversion immediately following the last bit during the serial shifting operation,

53

thus the existing data in the ADC is from a previous data collection and should be
ignored.

After shifting out the previous conversion, the ADC goes into a waiting state for
the serial output line to transition from high to low. This transition signifies data
conversion is complete. The data is shifted into a 32-bit register where it is sliced
into two 16-bit words for storage into two sequential memory cells in the FPGA
development board’s RAM. After writing to the memory, the current memory address
is incremented and the process repeats for however many samples are specified.

The data may be stored anywhere in memory thanks to the iadc_start.address and
iadc_end.address input signals. This allows the flexibility of filling the entire memory
with samples if necessary or allowing space for other modules.

After reaching the ending addresses, the module sets the iadc_data_ready flag to

high for one clock cycle and then returns to the idle state.

4.5 Injection Control

The floating gate transistors are written to using the hot-electron injection process
discussed in Chapter 2. The circuit that controls this process requires one digital
output from the FPGA to enable/disable injection. However, the injection control
module uses a logarithmic-based injection scheme to achieve very small injection
pulses on the order of tens of nanoseconds to approximately ten seconds.

This is achieved by the use two 30—bit registers. First, a comparison register is set
to all zeros with its least significant bit set to ‘1’. The signal injecti0n_pulse_width
shown in Figure 4.9 is provided by the execution controller and is an 8-bit integer

representing the pulse width given by the following equation

y = 20 - 10‘9 - 2x (4.1)

where y represents the output pulse in seconds and :1: represents the value given

54

 

clk .—

in]ectlon_pulse_width .— . . , ,

__ Injection —- unlect
Inject_pulse .—

pulse_injected .—

 

 

 

Figure 4.9. Hot-Electron Injection VHDL Module

by injectiompulsewidth. After initializing the comparison register, it is rotated left a:
number of times. Although a: can take values from 0—255, the number is practically
limited to 29, since there are 30 bits in the comparison register. Any values greater
than 30 will simply cause the comparison register to make a complete rotation, keeping
the injection pulse width at a maximum of 10.73 seconds.

After setup of the comparison register, the injection pulse goes high and the
module enters a counting mode where it increments the 30—bit injectionfegister' vari-
able once per clock cycle until it exceeds the value of the comparison register. Thus,
2010g(229) or approximately 174.5 dB of dynamic range is achieved using this method.

Following the injection pulse, an acknowledgment flag is set high for the duration
of one clock cycle to allow the execution controller to resume operation and return

to the idle state.

4.6 Memory I/O

The system uses the FPGA development board’s SRAM chips to buffer all data
acquired from the test platform, as well as configuration data for the serial shifting
module and signal generator. It is therefore essential to have a robust interface to the
physical memory cells. The Memory I/O controller shown in Figure 4.10 interfaces
with the physical control pins on the two RAM modules as well as a 5:1 memory

multiplexer to allow multiple modules direct access to the memory without passing

55

 

-. cet

-. ubt

clk .— -. Ib1

—. ce2

read_control .—4 —. ub2

write_control .— Memory I/O —D Ib2

mem_op_completed .— ---D 06

address .— —. we

memory_dsta_wflts .— —. mem_sddress

rnsmory_dsta_resd C: -. mem_dstat
-. mn_dsts2

 

 

 

Figure 4.10. Memory I/O VHDL Module

data through the execution controller.

During the idle state, the two input control flags read_control and writecontrol
determine how the RAM cells are enabled. The read mode always has a higher
precedence than the write mode. Thus, if both signals are high, the memory controller
will read the data from the current address and latch it to memory.data-read. During
the read mode, the active low write enable signal is set to high and the output enable
signal is low. The dual is true during the write mode. The RAM chips themselves are
each 256 kB and thus have an 18-bit addressing scheme. Internally, however, these
two chips are addressed in a 19-bit addressing scheme where the 19th bit acts as the
upper and lower byte enable as well as the chip enable.

Each RAM chip shares the same address bus, but has separate data buses. The
data buses are bidirectional, meaning they must be set to a high impedance state when
not in use. When both input control flags are set to logic low, the memory address
is set to zero, both output and write control flags are disabled, and the memories are

disabled.

After receiving a transition on one of the two input control flags, the internal

56

 

modulsJoloct
F. read_oontroLout

r—D write_control_out

i-v. “armpit

—. my_dsu_\vms_ou

read_contnLln
writs_control_ln
m In

nunory_dsts_wrls_ln

Memory Mux

”HT

 

 

 

Figure 4.11. Memory Multiplexer VHDL Module

state machine goes into the read or write state. In the read state, the data latched
onto the memory_data-read signal by the two data buses is determined by the most-
significant bit of the memory address. Likewise, during the write state, this bit also
determines the data put onto the bus from the memor‘y_data_write register. Finally,
the mem-op_completed acknowledgment flag is enabled to return control to the parent

module before returning to the idle state.

4.7 Memory Multiplexer

The Memory I / 0 controller discussed in Section 4.6 interfaces with a 5:1 multiplexer
to allow the memory transfer, current ADC, voltage ADC, signal generator, and
serial shifter to gain direct access to memory without passing data indirectly through
the execution controller. Figure 4.11 shows the signals passed through the memory

multiplexer.

4.8 Memory Transfer Control

Although the Memory I/O controller handles low-level access to the RAM, all data
transferred to and from the board is handled by the Memory Transfer Control module.
It also interfaces directly with the serial I / O module for direct outbound data transfer.

Figure 4.12 shows a block diagram of this module and its associated pins, where all

57

 

—. p-uIlsthd
r—D txd_ready
clk .— -. txd_complete
lrom_sddrsss .— —. read_control
mam ._ Memory Transfer _. “mom
read_block .— —C mem_op_completed
write_block .— —. dams
“In .— —. mmory_dsmm
op_completed .— —. mem_dutdmssd

 

 

 

Figure 4.12. Memory Tiansfer VHDL Module

pins on the left-hand side connect to the execution controller.

This module contains two internal state machines, one for block memory reads
and the other for writes. The memory transfer control module is also connected to
the memory multiplexer. Therefore, the execution controller must select the second
input channel, otherwise the Memory Transfer Controller will never receive an update
acknowledgment from the Memory I / O module.

Just as the read.c0ntrol and writecontrol flags initiate the memory I/O con-
troller to complete an operation, the Memory Transfer module uses the read_block
and writablock control flags to begin a block memory transfer. These signals can
never be high simultaneously, otherwise both state machines will break out of their
idle states and will attempt to access the same memory signals at the same time.
This condition is prevented by the execution controller, which ensures both signals
are logic low during the idle state and only go high based on the 6th most-significant
bit of a memory transfer instruction packet.

On the execution controller side, the first instruction packet contains the read or
write operation flag, as well as the three most-significant bits of the address registers.
Two additional states collect the starting and ending addresses for reading or writing.

If a writing operation is required, a fourth packet is sent. The fourth data packet may

58

be written to one address or a range of addresses. This is used to initialize memory
cells, or for verification purposes as seen in the system initialization script.

Initially, there were two instructions to handle memory transfer. However, since
a block data transfer mode was required, a more elegant solution was to include one
extra instruction packet for every transfer, providing an address range. If the transfer
included a single read or write, both addresses would be the same. The expectation,
however, is that most data transfers will be block transfers, which is the case for
analog-to—digital conversion and serial shift chain verification. This approach reduces
the need for additional overhead in the FPGA to handle single address reads and
writes, as well as reduces the need for an additional op code in the instruction set.

When either of the two state machines break out of the idle state, they iterate
through the range of addresses provided by the from_address and to-address signals.
It uses a temporary currenLaddress variable for comparison and increments after each
read or write. During a memory read operation, the module may access the serial
I/O directly given the execution controller has enabled the serial I/O multiplexer
accordingly. Upon completion of a block data transfer, the 0p-completed signal is set

to logic high for one clock pulse before returning to the idle state.

4.9 Voltage Digital-to-Analog Conversion

The voltage DACS consist of five, eight-channel daisy-chained devices programmed
using a serial peripheral interface at a frequency of 25 MHz. Each device contains
a 312-bit register used to store a command op code, DAC channel, and 16—bit value
representing the voltage output. Thus, the module requires an internal 160-bit serial
chain for device configuration. Figure 4.13 shows a block diagram of the DAC control
module.

Upon DAC update, the execution controller receives two packets from the se-

rial communications interface. The first packet contains the upper 12 bits of the

59

 

—C clk
program_dac .— —. clr_bar
dac_programmed .— Voltage DACS h. cs__bar
dac_lnstructlon '— —. sdi
—. sck

 

 

 

Figure 4.13. Voltage DAC VHDL Module

dac_instruction signal and the second packet contains the remaining 16 bits. The
upper four bits of this signal contain the device address, which is parsed after the
program_dac signal becomes a logic high and initiates a DAC update. The device ad-
dress determines which 32 bits in the internal 160—bit shift chain register are updated
prior to the shifting operation. The remaining 24 bits in the dac-instruction register
are written directly to the shift chain register based on the device address. Further-
more, the upper eight bits of the instruction register contain four bits representing
the DAC command code followed by four bits representing the DAC channel.

The command code has multiple configurations, but only the write and update
feature is used. For example, the DAC channels may have their internal registers
written to, but not their outputs updated, or may have their outputs disabled en-
tirely. This feature may be useful, for instance, if all channels need to be updated
simultaneously. Given that the dac_instruction is passed directly from the software
interface, such behavior is user configurable.

After updating the serial chain, the module enters the shifting mode. Since this
module updates only one device per serial shift cycle, all other devices receive a
command code of no operation (OxF). Finally, the dac_programmed signal is set to
logic high to acknowledge the DAC operation is complete before returning to the idle

state.

60

 

txd__ready .—
txd_complete .— —C clk
rxd_complete .— Serial I [O —I rxd
paralleerd .— —. txd
parallethd .—

 

 

 

Figure 4.14. Serial I/O VHDL Module

4.10 Serial 1/0

The serial communications module allows data transfer between the PC—controlled
software interface and the FPGA development board. The protocol used is the stan-
dard asynchronous serial communications found in typical RS-232 implementations.
The hardware used is the minimal 3—wire RS-232, which contains only transmission,
receive, and ground connections. Figure 4.14 shows the Serial I/O module and its
associated pins.

Figure 4.15 shows one byte of asynchronous data using RS—232 signal levels. From
this figure, it can be seen that the signal levels use a negative logic. There is a voltage
translator that resides between the interface cable and the FPGA to convert between
these signal levels and 0—3.3 V levels, as well as converting the signals to positive
logic.

The line sits idle at the mark voltage level. There is an undefined region between
positive and negative 3 V to eliminate invalid start bit detection, particularly when
the cable is unplugged. When a transition from high to low occurs (positive logic),
the start bit is sent, followed by eight data bits and a specified number of parity
and stop bits. The figure also illustrates mark parity and two stop bits, which has

been defined for this system. Additional packets may be sent on the next clock cycle

61

Packet

    
   

+15V

   
   
    
 

LSB MSB
10100100001E111

Space (0)
+3V
Undet. 0V
-3V
Mark (1) - - .. _

-15V Stop Bits

sum an Parity Bit

Figure 4.15. RS-232 Signal Timing Diagram

following the last stop bit.

This transceiver contains two registers for storing both received data and data to -
transmit, pamllethd and paralleLrttd. It also has acknowledgment signals for these
two modes whenever a serial to parallel or parallel to serial conversion is complete.
Finally, in the transmit mode, the transceiver has an additional control flag whenever
data stored in the parallel_t:cd register is ready to be sent serially.

The module operates at a baud rate of 115200 bps, which is the maximum sus-
tainable frequency of the data terminal equipment (DTE). To set the baud clock, the
FPGA’s 50 MHz external clock is divided using a counter. There are two baud rate
generators depending on the direction of data being transferred. The transmission
baud rate generator may run continuously because it is the responsibility of the DTE
to detect the start bit and to synchronize its own baud rate clock. However, during
receiving, the baud rate clock is synchronized during start bit detection, and is set to
a logic low otherwise.

A standard packet size is typically eight bits (although seven bits is often found
in legacy devices) for this type of serial communications. However, due to the 16—bit
word widths of the RAM chips and data from the voltage DACS, it became natural to

implement a 16-bit packet structure for serial communications. This is accomplished

62

by sending two, 8-bit packets sequentially and then reconstructing the data as a
single 16—bit word following transmission on both ends. A state machine handles
each bit transmitted as well as the start, stop, and parity bits. During each state of
the transmit operation, another state machine handles the shifting of the parallethd
register.

On the receive side, the input signal is buffered to prevent glitches. This is ac-
complished by incrementing or decrementing a counter based on the current sample
of the input signal. The counter is initially set to 50 and the output is set to logic
‘1’, which also corresponds to the idle state of the serial protocol. If the input signal
goes low, the counter will begin to decrement until it reaches zero for every ‘0’ it
samples per clock cycle or will increment its value by one for every ‘1’ it samples.
After at least fifty ‘0’ samples, the output is set to logic ‘0’. Therefore, by utilizing
this method, any spurious logic highs during which time the input should be logic
low will be avoided. This specifically prevents false triggering of the start bit.

As in the transmit mode, the receiver has its own state machine to iterate through
the received bits during the serial to parallel conversion. This state machine is syn-
chronized on the start bit, which is accomplished by oversampling the filtered serial
receiver input. Once a high to low transition is detected, a counter increments until it
reaches half of the desired clock cycle length. A flag then instructs the receiver state
machine to begin collecting each data bit. The baud rate generator counts 434 clock
cycles per bit and sets the get_nert_bit signal high for one clock cycle before resetting
the counter. After receiving the last data bit of the second packet, the receiver state
machine returns to the idle state.

Since mark parity and two stop bits are used, the next three bits following the
data bits during serial transmission are logic ‘1’, or the same as the RXD line’s idle
state. This is designed to give the data terminal equipment extra time between

packets. However, in the receiver, only one stop bit and no parity bits are recognized.

63

 

module__sslect .—

S _ l M —. txd_ready_out
txd_readan .— ena UX —. parallel_txd_out

parallel_brd_ln .—

 

 

 

Figure 4.16. Serial Multiplexer VHDL Module

Therefore, higher transmission rates may be achieved by configuring the data terminal

equipment accordingly.

4.11 Serial Multiplexer

Two modules require access to the serial I / O module, the execution controller and the
memory transfer module. Figure 4.16 shows the serial multiplexer that allows each
of these modules to gain control of the paralleLtrrd and txd.ready signals. This multi-
plexer may also directly disable serial I / O transmission by setting the moduleselect

signal to zero.

4.12 Serial Shifter

A general-purpose serial shift chain controller has been included for the purpose of
testing mixed-signal designs with D flip-flop—based shift registers. Such shift registers
are used to enable and disable portions of the chip to aid in the testing process.
However, the length of these chains can vary depending on design and application,
but they all have the same basic structure and control pins.

Figure 4.17 shows the block diagram for the serial shift chain VHDL module.
Three external pins are needed for serial shifting: serial_clk, serial_in, and serial_out.
The other signals and buses are required for handshaking and for loading and storing

data from the memory.

64

 

—. serial_in
--. serial_out
clk .—
-D serial_clk
add —. read_oontrol
starL rsss .— . .
v—D write_control
”d_mm Serial Shifter
—. mem_op_completed
shithtarLflag .—
—. address
shift_end_flag .—
—. memory_data_wrtte
—. memory_data_read

 

 

 

Figure 4.17. Serial Shifter VHDL Module

The controller works by reading the bitstream from sequential memory locations
and shifting the data out one bit per serial clock cycle. Additionally, the controller
will read the data output from the opposite end of the serial shift chain if available,
and will store it in subsequent memory locations.

Setup requires writing ‘1’s and ‘0’s to the least-significant bits of sequential mem-
ory cells in any portion of the SRAM. This is accomplished by using the memory
transfer module and writing ‘1’s and ‘0’s to each address. The addresses which this
data spans is given by the start.address and end_address registers.

During the idle state, the end shifting flag and serial out pin are cleared. During
a shifting operation, the execution controller configures the memory multiplexer to
allow the serial shifter module direct access to the SRAM. Three packets are received
from the PC-based host containing the instruction op code and the start and end
memory locations where the serial chain data is configured. I

The current address is set to the start address and the cell count is determined
by subtracting the start address from the end address. The host controller ensures
that the end address is always greater than the start address, and that the selected
memory cells are not less than cechount locations away from the end of memory.

Such a condition will cause the data written back as read from serial_in to overflow

65

 

—C clk
-D digit_sel
—. dlgit_val

Seven Segment
Display

lad_data .—

 

 

 

Figure 4.18. Seven Segment Display VHDL Module

the memory space.

The controller then iterates through each memory location until the current ad-
dress is greater than the end address. Next, the shift_end_flag is set for one clock
cycle and the controller returns to the idle state.

Data read from the serial_in pin will be written to the next memory location
following the last cell containing data to add to the serial chain. Thus, if memory cells
1—500 contain data for shifting, the data written back will be contained in memory
cells 501—1000.

4.13 Seven Segment Display

A seven segment display decoder is used for debugging purposes to view the internal
states of the F PGA. It is set by default to display the value of the current_instmction
register. Figure 4.18 shows the block diagram for the control module.

The theory for updating the seven segment display is as follows. Each display
module has a parallel interface to control which of the seven LEDs are enabled.
Additionally, each module has its own enable pin, making a four-bit address bus to
control which display module is to be updated. Only one seven-segment module may
be enabled at a time. The controller iterates through the four display modules and
turns each on individually to set the display segments. Although one digit is on at
any given time, the human eye perceives the update of the display as continuous.

This module uses four internal processes. A clock divider is used to reduce the

66

 

—. cs_bar
—D sdi
clk .— r—D sck
sig_gen_enab|e .— —. read_control
Mmmm ._ Signal Generator _. my,“
starLaddress .— —C mem_op_completed
end_address .— —. m
_.
r-C

 

 

 

Figure 4.19. Signal Generator VHDL Module

update frequency of the display to 250 kHz. An LED selection state machine decodes
an integer-based selection to one that enables only one seven segment module at a
time. A process to convert the value of a four-bit register into the enable signals
for the seven segments is needed to display the characters properly. Finally, the
main process deconstructs a 16—bit hexadecimal number and sets the other processes

accordingly to enable the correct seven segment module and its enabled segments.

4.14 Signal Generator

A signal generator module combines the functionality of the voltage digital-to-analog
conversion module with the memory transfer module to create a multi-channel wave-
form generator that may be used for testing mixed-signal designs. A block diagram
of this module is given in Figure 4.19.

A review of Section 4.9 shows that the DACS are controlled with a SPI through a
160—bit serial shift chain register. By storing 16-bit codes in memory, the DACS may
be programmed by reading these memory locations sequentially and updating their
outputs accordingly. Therefore, by computing a vector of digital inputs, an analog
waveform may be realized at any frequency, offset, amplitude, and phase within the

constraints of the digitally programmable interface and output range.

67

The execution controller initializes the DAC multiplexer and memory I/ O multi-
plexer while waiting for the second instruction packet. The second and third instruc-
tion packets contain the start and end addresses for the memory locations containing
the DAC codes. The first five memory locations in the specified memory range con-
tain the channel addresses of the five DAC ICs. Therefore, for multi-channel signal
generation, up to five channels may be specified with one channel per DAC chip.

This behavior is due to the l60-bit serial chain updating the five chips concurrently.
Since only one channel per chip may be updated at a time, only one channel is
allowed per chip during multi-channel signal generation. Additionally, since the last
four channels of the fifth DAC chip provide biases to the injection and current ADC
circuits, these channels may not be specified in the fifth memory location in the
address range due to their required stability as a bias.

After receiving the ending address, the module sets the sig_gen_enable flag and
and enters a waiting state until a termination packet is received. This termination
packet is a single instruction packet and is implemented by the host controller using
the loopback command. This is the only means of disabling signal generation and
returning the execution controller to the idle state.

During the idle state, the DAC serial chain register is initialized to the no oper-
ation state for all five devices. Upon receiving the sig_gen_enable flag, the controller
initializes the channel addresses for the five chips by reading the first five memory
locations specified in the address range. Next, the data is loaded from the remaining
addresses sequentially and is stored into the DAC serial chain register.

This processes occurs in blocks of five memory addresses per shift cycle. After
loading the data into the serial shift chain register, the data is output via the serial
peripheral interface at a frequency of 25 MHz. The module then reads the next five
locations and stores them into the serial shift chain and repeats the process. This

occurs until the end address is reached, after which the current address is reset to

68

 

—. adc_clk
clk .— —. adc_sck
—. adc_cs_bar
adc_data_collect H H adc_sdi
adc_data_ready .— —. adc_sdo
sdc_conv_mode .— VOltage ADC —D read_control
sdc_sddress .— -. write_control
sdc_start_address .- —C mem_op_completed
adc_end_sddress h -. address
r-D memory_dsts_wrlte

 

 

 

Figure 4.20. Voltage ADC VHDL Module

the beginning of the data loadable addresses. It is also during this state that the
controller determines if the sig_gen-enable flag has been cleared, meaning that the
termination packet has been received. The sig.gen.complete acknowledgment signal
is set for one clock pulse and the module enters the idle state.

Thus, to construct multi-channel signal generation, the data for a single channel
is stored in every fifth memory location. Routines have been devised in software to
generate these data structures and store them in memory. An example function is

given in Section B.17.

4.15 Voltage Analog-to-Digital Conversion

The board includes a 16—channel, 24-bit delta-sigma voltage mode analog-to-digital
converter for data acquisition. This module controls the SP1 communication protocol
that both configures and receives the conversion result, as well as stores the received
data in the FPGA board’s SRAM.

Figure 4.20 shows the configuration of the voltage ADC VHDL module. The
signals on the left-hand side connect to the execution controller whereas the other

signals connect to the memory I/O module and external pins for the SP1 and conver-

69

31302928272625246543210

 

 

 

 

 

-— Input Address *7 t Don’t Care ——>

 

7—K
L_

lio

 

 

t Datallo

Viv

 

 

Figure 4.21. Voltage ADC Serial Peripheral Interface

sion clock.

During data acquisition, the channel number, number of samples, and conversion
mode are specified. These are provided by three 16-bit packets to the execution
controller, and are latched to the adc_c0nv_mode, adc_address, adc_start_address, and
adc_end.address registers. As in the current ADC case, the memory addresses allow
the data to be stored into the FPGA board’s SRAM before being transferred over the
communication bus, acting as a buffer to allow continuous data acquisition. Data is
then transferred over the serial line via the block memory transfer module. The three
most-significant bits of the memory addresses as well as the ADC channel number
are obtained from the first instruction packet.

During the idle state, the module initializes all of the internal variables and exter-
nal SPI signals and waits until the adc_data-collect flag is set. Next, it initializes the
ADC’s serial data input by setting the adc_chain register, which specifies the ADC
channel address and the conversion clock mode for the next conversion.

The conversion clock mode specifies the speed and accuracy of the data converter.
Four modes are selectable based on bits 6—7 of the first instruction packet. The
implications of each of these modes is discussed further in Chapter 5, during the
testing and validation of the test station’s performance.

The module then shifts 32-bit data to and from the ADC, as shown in Figure 4.21.

70

The serial output read from the ADC corresponds to the previous conversion cycle;
therefore, the first conversion after initiating analog-to—digital conversion is ignored.
The ADC then goes into a waiting state for the serial output line to transition from
high to low. This transition indicates the conversion is complete. The data is shifted
into a 32—bit register where it is sliced into two 16—bit words for storage into two
sequential memory cells in the FPGA development board’s RAM. After writing to
the memory, the current memory address is incremented and the process repeats for
however many samples are specified.

The conversion clock rate is determined by the adc-clk signal. This ADC is capable
of a conversion clock rate of 2 MHz, producing an output rate of over 97 samples per
second. As in the current ADC module, the data may be stored anywhere in memory
due to the use of specified address ranges at the input of the module. This allows the
flexibility of filling the entire memory with samples if necessary or allowing space for
other modules.

After reaching the ending addresses, the module sets the adc_data-ready flag to

high for one clock cycle and then returns to the idle state.

4.16 Voltage DAC Multiplexer

The voltage digital-to-analog converters are shared between two modules, the single-
channel, single update voltage DAC controller and the signal generator. The voltage
DAC multiplexer allows multi-module access to the SPI. Figure 4.22 shows the pin

configuration of this 2:1 multiplexer.

4.17 Digital Clock Manager

The Digital Clock Manager (DCM) module allows synthesis of a new clock frequency

along with duty cycle and phase correction of existing clock sources [58]. Additionally,

71

 

module_select .—

chn H Voltage DAC

deIn .- Multiplexer
cs_bar_ln .—

—. sck_out
—D sdi_out
—. cs_bar__out

 

 

 

Figure 4.22. Voltage DAC Multiplexer VHDL Module

DCMs help to eliminate clock skew, thus improving performance of the overall system.
Figure 4.23 shows the DCM module implemented on F PGA hardware.

The FPGA development board includes a 50 MHz external crystal oscillator that
acts as input to the DCM. The DCM can be synthesized for a number of modes,
but only buffering and duty cycle correction are used to improve fanout perfor-
mance. Additionally, a PLL can multiply the clock to frequencies up to 280 MHz
for the XC3S200FT256-4 and faster for parts with better speed grades. The DCM
shown in Figure 4.23 has three outputs. Signal clk0.0ut shares the same frequency
as clkin_in, but is buffered and has duty cycle correction. It also acts as the global
clock to all other modules. Signal clkfx.0ut is realized as a 250 MHz clock source and
clkin_ibufg_0ut is a buffered version of clkin_in.

The DCM is also capable of producing 90, 180, and 270 degree phase-shifted
clock sources based on the source frequency and 180-degree phase-shifted sources of
a doubled source frequency and the freely synthesizable (fx) frequency. Furthermore,
it is possible to divide the clock. The DCM is preferable to using traditional clock
dividers made with counters and comparators since these structures occupy slices
whereas a DCM is a separate module existing in the periphery of the FPGA. This
particular device contains eight DCMs.

Utilizing the PLL of the DCM module, it is possible to improve the speed of the
overall system, thus reducing the baud rate error in the asynchronous serial communi-

cations and doubling the speed of the voltage DACS to their maximum SPI frequency

72

 

—. clk0_out

clkian .— Digital Clock Manager —- cIktx_out
—. clkin_ibufg_out

 

 

 

Figure 4.23. Digital Clock Manager Module

of 50 MHz. However, this would require adjusting all internal timing and counter
sizes, which is not possible with existing slice utilization. A larger device such as
the XC3SlOOO would be required for any future expansion of the FPGA’s synthesized

functionality.

73

CHAPTER 5

Testing and Results

Before floating gate transistors may be programmed to currents in the nanoampere
range, it is essential to test and calibrate the measurement circuits of the mixed-
signal test station. This chapter validates the functionality of the voltage-mode ADCs
and DACS, current-mode circuits, and floating-gate programming circuits. Next, the
floating-gates are tested through a series of programming experiments detailed in
Section 5.3.

The system controller detailed in Chapter 4 has been tested throughout its design
and will not be discussed. Furthermore, it acts as the framework for the following

experiments, which would not be possible without a robust digital interface.

5.1 Test Station Validation

5.1.1 Fowler-Nordheim Tunneling Pulse Response

Figure 5.1 shows the transient response of the gate driver output of the Fowler-
Nordheim tunneling circuit. Since tunneling is either enabled or disabled by the least-
significant bit of the corresponding instruction packet, the period of the tunneling
pulse is defined by the speed of the host software to disable tunneling, which includes
the overhead of making the tunneling function call and constructing the packet for

serial transfer. A minimum tunneling pulse width of 139 [is is possible by sending

74

 

Tunneling Gate-Driver Output
1 6 T I i I T l T

L A; ‘L J A ‘_.LL_‘_

 

.s .5 .5
o N «5

Output Voltage (V)
on

 

 

 

 

 

J l j l l

‘20 30 4o 50 so 70 so 90 100
Time (ms)

 

 

Figure 5.1. Tunneling Pulse

two instruction packets back-to-back.

5.1.2 Hot-Electron Injection Pulse Response

Figure 5.2 shows the minimum pulse width of the injection circuit for different biases
of DAC channel #37. Unlike tunneling, which is a relatively slow process on the order
of seconds (at 15 V), large injection currents can be generated with pulse widths
on the order of microseconds. Thus, a logarithmic pulse scaling method has been
implemented as discussed in Section 4.5. The OPA2743, which acts as a rail-to-rail
comparator, has a slew rate of 10 V/us and sets the minimum resolvable pulse width.
Thus, the variable :1: in Equation (4.1) can be set to a minimum of six. Furthermore,
it can be seen that the output of the MAX1681 does not have a direct negative
correspondence to its input.

Figure 5.3 illustrates the logarithmic scaling of the injection pulse F PGA module

for different values of :1: at a fixed input of 2 V to the MAX1681 voltage inverter. This

75

Minimum Injection Rate vs. Injection Voltage

f

A
_,

Output Voltage (V)

 

 

 

 

 

 

<OIO
N
N
<

224v

 

 

—4 l I L
2 3
Time (us)

Figure 5.2. Minimum Injection Width

experiment also illustrates that the injection voltage has a slight settling and drift to

its targeted amplitude.

5.1.3 Voltage-Mode ADC Linearity

The LTC2415-1 and LTC2418 have near identical performance specifications. The
LT C2418, however, includes a front-end multiplexer for 16-channel data acquisition.
Calibrating the LTC2415—1 will be especially important for accurate current measure
ment, which is essential for floating gate programming. These data converters have
an external conversion clock source input F0 that determines the conversion time. A
maximum frequency of 2 MHz produces 97.5 samples per second.

Figure 5.4 shows the linearity of the data converter operating in the 2 MHz con-
version clock mode. For this experiment, one channel of the voltage—mode DAC is
connected to the first channel of the LTC2418. The DAC is a 16—bit converter and is

guaranteed monotonic across its range of 0 to 4.096 V. First, the DAC’s internal reg-

76

Injection Pulse Widths

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 1
8
3
>
3 0r- " + 0 v
O
-1.
v x=6
‘2 O X=7 ‘
I x=8
O X=9
—3 l l 1
O 5 10 15 20

Time (us)

Figure 5.3. Injection Widths

ister is cleared, producing O V output, which is then sampled by the ADC. The DAC’s
register is incremented and this process is repeated spanning the entire resolution of
the DAC. The deviation from ideal is plotted in millivolts.

Given that these are 24-bit data converters, a minimum of 16 bits is expected
as the experiment is limited by the resolution of the digital-to—analog converters.
However, Figure 5.4 shows a resolution of less than 8 bits. The DACS have a settling
time of 2 us, however the time between configuration of the DAC and the ADC sample
is a minimum of 555.6 [1.8 (for serial communications) without including setup time
by the host. Therefore, this error is not due to any transients.

The LTC2418 datasheet shows that resolution is inversely proportional to sam-
pling speed. In addition, the resolution deteriorates rapidly after 25 samples per
second. Figures 5.5 and 5.6 show experimental results for 1 MHz and 400 kHz, re-

spectively.

77

Voltage ADC Nonlinearlty (at 2 MHz)

 

 

 

8C 1 s
60 1
40 q
S‘
E 20 ,
i
= O
5
2
-20
.40
4593.5 i 175 é 2:5 5 3.5

Input Voltage

Figure 5.4. Voltage ADC Linearity at 2 MHz

Voltage ADC Nonlinearity (at 1 MHz)
1 . . . .

 

 

 

 

 

0.5
S‘
5. o
i
E -o.5
Z

_‘| I-

-1.g e s s s 1
6.5 1 15 2 as 3 3.5
Input Voltage

Figure 5.5. Voltage ADC Linearity at 1 MHz

78

Voltage ADC Nonlineerity (at 400 kHz)

 

0.8

0.6

0.4

0.2

0

—0.2

Nonlinearlty (mV)

—o.4

-O.6

—0.8

"5.5

l l

1 1 .5 2 2.5
Input Voltage

 

Figure 5.6. Voltage ADC Linearity at 400 kHz

Voltage ADC Nonlineerity (at 153600 Hz)

 

0.5 '

Nonlineaer (mV)

 

T

1" l‘

I\ I‘

 

 

— Runi
— Run2

 

 

I f , .

 

it
I

 

 

1 1 .5 2 2.5
Input Voltage

Figure 5.7. Voltage ADC Linearity at 153600 Hz

79

The converter has a notch filter designed to reject 60 Hz noise at its internal clock
frequency when the F0 pin is driven to logic low and rejects 50 Hz noise at logic high.
The filter may be adjusted to a center frequency of F0 / 2560 if provided an external
conversion clock. This corresponds to an clock rate of 153.6 kHz for 60 Hz noise.

Figure 5.7 shows the best case performance metric for the LT2418 at 6.2 samples / sec.

5.1.4 Signal Generator

The multi-channel signal generator module discussed in Section 4.14 has been tested
through the example function generator script of Section EU in the appendices.
Figures 5.8 through 5.11 show a 1 kHz waveform for the standard sine, triangle,
sawtooth, and square waves with no offset or phase shift at two amplitudes: 1 and

0.5.

80

DAC-based Signal Generator (Sine Wave)

:3A A
:: V V f

 

Output Voltage (V)
N 0)

d

 

 

 

 

 

 

 

O
"0'50 0.5 1 1.5 2 2.5 3
“me (ms)
Figure 5.8. Signal Generator Sine Wave at 1 kHz
DAC-based Signal Generator (Triangle Wave)
4.5
4 In
3.5 '-
3%
S
g 2.5r
i
> 2 '
S
g- 1.5 " t
O
1 P
0.5 -
0 d
’0'50 0.5 1 1.5 2 2.5 3

Time (ms)

Figure 5.9. Signal Generator Triangle Wave at 1 kHz

81

 

 

Output Voltage (V)

 

 

 

‘7

DAC-based Signal Generator (Sawtooth Wave)

 

 

 

0 0.5 1 .5
Time (ms)

2.5 3

Figure 5.10. Signal Generator Sawtooth Wave at 1 kHz

DAC-based Signal Generator (Square Wave)

 

..(— m“—

3.r‘——"‘ (“u--

N
01

Output Voltage (V)
a m

0.5 '

 

 

 

 

 

or s
—.u

l
l

Fm

 

 

 

 

 

1.5
Time (ms)

Figure 5.11. Signal Generator Square Wave at 1 kHz

82

 

Figure 5.12. Floating Gate Programming Test Setup

I I

, " .//./""
s‘v‘s‘sb be s l-/

'0

,"s
~s
4.
.e
9.
A
,s
s

Figure 5.13. Analog SVM Chip Photomicrograph

83

L

\l \‘x V \

OII/o'

 

 

 

L------d

 

 

 

 

——

 

'e
3
_:1

r-------1>---------------

Figure 5.14. Support Vector Simplified Schematic

5.2 Overview of the Test Chip

An analog support vector machine (SVM) has been designed and fabricated using the
AMI C5N process teclmology. This chip contains a 14-dimensional input space and
28 support vectors, which corresponds to 392 floating gates in the first stage of the
SVM. The second phase of the algorithm contains an output stage with an additional
56 floating gate cells.

Without going into great detail on the SVM hardware, it is important to look at
the transistor-level structure of the SVM for floating gate programming. The output
currents from these cells will pass through the SVM to a common output node that
is measured with the current ADC.

Figure 5.14 shows a simplified schematic of a training vector in the SVM’s first
stage. The floating gate cells are represented by independent current sources Y0 and
Y1. X0 and X1 are represented as diode-connected transistors. The support vector

output is given by Z.

84

Vdd

 

 

 

 

 

 

 

 

INJECT 0 our

Figure 5.15. Floating Gate Cell Schematic

All ground connections meet at a common node that is separate from digital
ground used for cell selection. This allows each cell to be individually selected to
test the output current of individual floating gates or the performance of individual
support vectors. The fabricated prototype includes cell selection transistors at the
output of the X and Y inputs, above M1 and M2, and above the 7 constant current
sink.

Floating gate readout involves disabling the sourcing capability on the Xn tran-
sistors and passing all current through M1. All other cells are disabled, including Mz
as well as M, for all support vectors. Additionally, this architecture requires the gate
of the M1 transistor to be charged, otherwise it will not act as a switch and will limit
the current flowing through the drain of the floating gate.

During every current readout or injection cycle, the M2 transistor is enabled to
charge the parasitic gate capacitance of M1 so it is completely enabled. M2 must then
be disabled, otherwise current may flow from adjacent cells, corrupting the reading.
Additionally, the cascoded biasing transistor at the output of the floating gate cell is

fully enabled to minimize effects of the early voltage.

85

Figure 5.15 shows the floating gate cell schematic as implemented on-chip. This
basic topology was discussed in Chapter 2; however, note that M1 through M4 have
been laid out as 6um/3um to minimize mismatch between the injection and readout
transistors.

Cells are selected through a shift register controlled by the interface described in
Section 4.12. The shift chain consists of 515 selection bits in the following order: 392
first stage cells, 28 output stage cells, six test cells, the remaining 28 output stage
cells, five cells for an on-chip integrator controller, and 56 M7 and M2 selection cells.
It is important to note that not every shift register stage contains a corresponding
floating gate cell. Consequently, all experiments have been carried out on the first

stage cells.

5.3 Floating Gate Testing Results

Figure 5.16 shows an array of 300 unequalized floating gate cells in their natural,
post-fabrication state. With a 2 V control gate voltage, they vary from approximately
21 nA to 34.5 nA. Since the nearest integer to the maximum current read in the array

is 35 nA, all cells will be equalized to this current.

5.3.1 Floating Gate Current Equalization

Figure 5.17 shows the same floating gate array programmed to 35 nA. Since the
programming algorithm stops injecting once the cell current exceeds the targeted
current, it can be seen that the average current slightly exceeds the targeted current.
A histogram of the equalized floating gate currents is shown in Figure 5.18.

Next, the control gate voltage is increased to 2.2 V. This reduces the current in the
floating gate cells by reducing the source-to-gate voltage of these capacitively-coupled
pMOS transistors. Figures 5.19 and 5.20 show the measured currents in the floating

gate cells and their histogram, respectively.

86

Unequalized Floating-Gate Currents (VCG = 2V)
35 I t 1 1 s

 

 

 

 

 

 

 

 

 

 

 

30 - .
g |
E
O

25

2 I l l l l

(50 100 150 200 250 300 350
Floating-Gate Cell

Figure 5.16. Unequalized Array of Floating Gates

5.3.2 Adaptive Injection Characteristics

Figure 5.21 shows the hot-electron injection characteristics for seven different targeted
currents starting from the equalized array current of 35 nA. The algorithm used for
this experiment is given in Section F.8.

Since injection current is a function of the initial current, the pulse width must be
decreased as the initial current increases. The algorithm thus includes an injection
width modifier that is incremented for different current ranges. The modifier is then
subtracted from the default pulse width. The default pulse width is determined by
the AI change between the previous injection cycle and targeted currents. As the
measured current comes within a specified range of the targeted current, the injection
pulse width is divided by two. This process is repeated until the current is within
250 pA of the targeted current.

87

O

Equalized Floating-Gate Currents (VCG = 2V)

 

eU

35.25

Current (M)
82
a

'3: __...- .. ...| .. .-
W

 

 

 

34.8 ‘ ‘

 

 

— Measured Current
------ Average Current 1
- - Targeted Current

 

 

l.1| ..
||

 

 

 

0 50 100

150
Floating-Gate Cell

200 250 300

Figure 5.17. Equalized Array of Floating Gates

—/'A
l

45
4o " /

235 Vi

861‘
\1

 

 

 

 

 

 

 

 

 

1

 

 

 

 

Equalized Floating-Gate Currents (VCG = 2V)

 

 

 

34.5

35
Current (nA)

Figure 5.18. Floating Gate Equalization Accuracy Histogram

88

Equalized Floating-Gate Currents (VCG = 2.2V)

;— Measured Current
------ Average Current

 

4.4

 

 

 

 

4.35 '-

4.3 '

4.25

 

 

 

Current (nA)

 

 

 

 

 

 

3. I I I I
950 50 100 1 50 200

Floating-Gate Cell

Figure 5.19. Equalized Array of Floating Gates at VCG = 2.2 V

 

Equalized Floating-Gate Currents (VCG = 2.2V)

I“ I U

: ‘l

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 /
7, 40 _
U
‘6
b
.8 30'
E
3
z

20 "

10

I i I
(3.8 3.9 4 4.1 4.2 4.3 4.4 4.5

Current (nA)

Figure 5.20. Floating Gate Equalization Accuracy Histogram at VCG = 2.2 V

89

Adaptive Programming
70 i r , T 7 7
-9- 40nA —. '
-I- 45nA
-+— 50nA
-6- 550A .,
65f -e- BOnA r
+ 65nA

sol ‘7' 70nA

 

 

 

 

 

 

Current (nA)
\

 

 

1)
C)
C
O
(
(

 

 

Pulses

Figure 5.21. Adaptive Programming used for Hot-Electron Injection

It can be seen that the targeted current can be programmed within 2% accuracy
in fewer than 16 pulses. Extrapolating this figure shows a worst case of 26 pulses for
less than 0.5% accuracy. As compared to the state of the art injection algorithms
that require accurate modeling of injection currents [34], this empirical model requires

approximately twice as many pulses to achieve similar accuracy.

5.3.3 Effects of Injection on Threshold Voltage

Figure 5.22 shows the voltage to current characteristic for the standard pMOS tran-
sistor represented by Xn in Figure 5.15. These transistors have a width to length ratio
of 6/ 3. This characteristic may be compared to that of the floating gate as shown in
Figure 5.23. Here, the control gate voltage was set to 2 V and an array of floating

gates was programmed in increments of 50 nA, starting at 50 nA.

90

Current (nA)

§

Current (nA)

§

Standard pMOS vsc vs. IS (WIL = 513)
SW I I I I I I

‘

§

§

 

 

 

 

2.6 2.55 2.5 2.45 2.4 2.35 2.3 2.25
GateVoltage

Figure 5.22. pMOS Input Stage V-I characteristics

2.2

 

Floating-Gate Source Current vs. VCG
2m 7 V I I i V

I’

180

160

_s
N
o

8 8

 

I I I I

3.6

2.3 2.2 2.1 2
Control Gate Voltage

2.5 2.4 1.9 1.8

 

1.7

Figure 5.23. Floating Gate MOS Threshold Voltage Modulation

91

By sweeping the control gate voltage, the threshold voltages of the programmed
floating gates may be observed. As more electrons are injected onto the floating
node, the threshold voltage decreases. Furthermore, it can be seen that the voltage
to current response of the floating gate is different from that of a standard pMOS
transistor. This is due to different source-to-drain voltages across both transistors,

as the floating gate cell includes an additional cascoded stage biased at 1.5 V.

5.3.4 Programmable Current Lookup Tables

Figures 5.24 and 5.25 demonstrate the ability to program a current-mode lookup table
on-chip. The first figure illustrates a current ramp from the initial equalized current
of 35 nA to 74 nA with a slope of 1 nA per cell. Figure 5.25 demonstrates a sine wave
with an offset of 62 nA and an amplitude of 14 nA—pp. These offsets and amplitudes
were chosen due to the initial state of the array, which had been equalized to 55 nA

prior to programming.

92

75

Programmable Current Ramp

 

 

 

Measured
— Ideal

 

 

70'

$

Current (nA)
%

 

P

t

I

 

 

10

15

20

25

Floating-Gate Cell

30

Figure 5.24. Floating Gate Current Ramp

Programmable Current Sine Wave

35

 

O)
N

Current (nA)

 

52'

 

Measured

 

 

 

— Ideal

T

I

 

 

 

5

1O

15
Floating-Gate Cell

20

25

Figure 5.25. Floating Gate Current Sine Wave

93

30

CHAPTER 6

Conclusions

6.1 Accomplishments

Through this work, an automatic test unit (ATU) for topology and process-neutral
analog floating gate programming and mixed-signal design testing has been fabricated
and verified on a system-on-chip. This incorporated the design of a board-level system
framework for precision voltage and current measurement and analog output, as well
as high slew-rate injection and tunneling outputs. The system required the design
of a high-speed controller realized in VHDL and synthesized on a Xilinx XC3S200.
Furthermore, a software interface has been developed to provide a customizable API
for future floating gate testing for analog computation in SoCs.

For the validation phase of this work, an analog support vector machine complete
with floating gate transistors was designed and fabricated to test the accuracy of the
AT U for performing hot-electron injection and tunneling functions, as well as off-chip
current analog-to-digital conversion. Additionally, a novel floating gate programming
algorithm has been developed through experimental observation, and has been used

to successfully program floating gate cells to within 0.5% accuracy.

94

6.2 Suggestions For Future Work

This work is an ongoing effort to develop a rapid prototyping and verification system
for mixed-signal ICs. Future iterations will improve on the features introduced in
this work and further refine the methods developed herein. Several drawbacks to the
existing system were identified during system validation and these items are discussed

below.

6.2.1 Floating Gate Architectures

This work explored only one floating gate architecture that used a separate MOS
device for prograrmning and current output. A more efficient design would incorporate
these two functions using the same floating gate MOS device. This ensures that both
the injection and readout nodes have the same current sourcing characteristics. This
is important for accurate modeling of the injection rate based on the existing control
gate voltage and the charge stored on the floating node. Since mismatch between the
injection and readout transistors is likely to occur, the AI / At where t represents the
injection pulse period will not be constant across different cells given their output
currents are equalized. Furthermore, any charge trapping that occurs in the gate
oxide layer of the injection transistor will have a further effect on injection modeling,
making it more difficult to characterize the current output transistor.

However, although it would appear this method would require less area per floating
gate cell by eliminating the additional injection transistor, it would occupy a greater
footprint due to two required multiplexing transistors. Furthermore, two additional
multiplexing transistors should be added to the existing architecture in order to bypass
the support vector machine for direct current measurements. The existing topology
requires the floating gate current to pass through the support vector cells to the
ground terminal. This creates testing complications since this current cannot be

measured directly, or requires the SVM to be configured in an unstable state.

95

6.2.2 Board-Level Modifications

The floating gate test station was designed for the AMI C5N process, which requires
a minimum of 15 V for Fowler-Nordheim tunneling and allows hot-electron injection
between 4 V and 6.5 V. The tunneling and injection supplies were therefore designed
for these voltages without giving consideration to more sophisticated fabrication pro-
cesses.

A 0.25 pm process, for example, uses a 10 V tunneling voltage and 3.8 V VDS for
hot-electron injection. Although the amplitude of the injection output can be adjusted
through the configuration of voltage DAC channel #37, it cannot be reduced beyond
a certain threshold without the MAX1681 inverting DC-DC converter exceeding its
input range. One solution is to modulate the test chip’s supply voltage using one
of the voltage DAC channels. Since each DAC channel is capable of sourcing up to
15 mA of current, these channels may be used directly to decrease the supply for
injection at a lower VDs-

Furthermore, digital potentiometers could be used at the output of the tunnel-
ing and injection supply nets to divide their output voltages. This method may be
preferable for two reasons. First, as demonstrated in Chapter 5, there is not a di-
rect correspondence between the output of the DAC channel and the injection supply
output. Since the digital potentiometers are guaranteed to be monotonic regardless
of their nominal values, the output may be accurately calculated based on a fixed
output voltage. Second, the potentiometer would provide an additional load for these
DC—DC converters, thus improving their efficiency.

Another potential improvement could come from modifying the topology of the
current DAC to provide sinking as well as sourcing. This would allow current biasing
from pMOS-based structures. One possible implementation could include inverting
some of the channels to sink rather than source current. This may be done by using an

inverting regulator that maintains a negative potential across the digital potentiome-

96

ter in the existing topology. Both implementations may be combined by connecting
both regulators to the same common ground path and using a switch to reverse the

voltage polarity across the digital potentiometer.

6.2.3 Microcontroller—Based Test Station

The merits of an FPGA-based versus a microcontroller-based test station include
high speed through parallel processing and access to off-chip RAM for data storage
in real-time data acquisition experiments. Such performance cannot be matched by
a general purpose microcontroller unit such as the PIC18F or dsPIC30/ 33 families
by Microchip or the MSP430 family by TI due to limited I/ O ports and peripheral
speed. Even the hardware SP1 and 12C modules in these devices are only capable up
to 2 Mbps whereas the FPGA is capable up to 125 Mbps when using the PLL module
of the FPGA’s digital clock manager.

However, these devices offer the advantage of being easily integrated onto the
existing test station PCB through package availability such as DIP and SOIC, which
stands in stark contrast to BGA and TQFP of modern FPGA devices. Additionally,
some performance bottlenecks can be reduced by incorporating demultiplexers on the
output of the part for chip selection in a SPI-only environment. This would allow
individual part selection, eliminating daisy-chained configurations and reducing the
number of shift cycles during serial communication with these devices.

The FPGA development board can accommodate a large number of parallel de-
vices such as external SRAM due to high density packaging. Chips up to 2 MB are
common as of 2007 and the current system integrates 512 kB of SRAM through two
256 kB devices. This cannot be matched directly by a microcontroller unit whose
options for external memory include serial EEPROMs or parallel SRAM. In the case
of SRAM, due to large data and address bus widths, multiplexers and latches would

be required to interface with the microcontroller using a minimum number of pins,

97

a partial speed penalty that makes real—time data acquisition more challenging. Ad-
ditionally, microcontrollers have at most 30 kB of data RAM, which would limit the
data buffer size before serially transferring the data for post processing.

An alternative to this problem would be to use the PIC18F2550/4550 family
of USB microcontrollers capable of 12 million instructions per second (MIPS) [59].
USB can alleviate communication bottlenecks by providing up to 12 Mbps for full
speed devices. Utilizing interrupt transfers, latency can be guaranteed [60], thus real-
time data acquisition may occur through immediate transfer with very small buffers.
Also, unlike the similar isochronous transfer mode, interrupt transfers include error
checking, thus ensuring data transmission accuracy. Furthermore, the bus can supply
power directly to the test station with up to 500 mA of current, well above the power
requirements of the existing test station (70 mA) and thus eliminating the need for
external power adapters.

In conclusion, one outcome of this work has been to create a modular test station.
Through this, it is possible to make a single demo platform that combines both
the functionality of the motherboard and daughter card containing the SoC under
test. Taking into account the lessons learned in this design and the recommendations
outlined above, it is now possible to make a completely integrated system which does

not require external test and measurement equipment for chip testing.

98

APPENDICES

99

APPENDIX A

Support Vector Machine SoC

A.1 Layout

 

Figure A.1. Floating-Gate Transistor Layout

100

 

Integrator Layout

2

A

igure

F

44
a; ”In/M .-

1,21%

 

AAA Arse: .A
é_7.1%4J/,%m41”,
twil- II
_////7/ Z7/Az//// // I z/lA/V
7M).-—

//////./7//mfla m WV/ m
/%J j 51%“
V [II tit;
./ II

 

 

ur

(liver/Irv! mwaaa mlm
I...‘

 

can 51 o :1 51341211]

, .

.72~V///u
ll/

////flm”./

 
 

Shift Register Layout

3

A

igure

F

 

Figure A.4. Support Vector Layout

5
,o
.n
x...
o
_n
y.
.4
.a
7.
.o

l’l‘drirla‘f;

 

'1'. '10: I. ’1-21'4'; QI'I'.‘

Output Stage Layout with Floating Gates and Shift Register

5

A

igure

F

101

 

Layout

Support Vector Machine

.6.

A

Figure

102

A22%dfimm

 

 

 

 

3 § § :5 a a '- E
'5' E E E E ’2' E E E 5
E E E E E E E E E
lameness? E "user
INTEGPULSE E E ass
SERIALTEST E oouuou
senIAm E can
samuour E van
CLK E E x43,
mrsamvaus E x42,
man” :41,
GAIN“ E E x40,
EEPBOIBIAS E m
manna EEEEE
gm: mm:

Figure A.7. Fabricated Prototype Pin Bonding Diagram

103

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name Type Description
1 VDD Jumper Supply
2 GND Jumper Ground
3 COMMON Analog I/O Aux Ground / Measurement
4 REF Analog I / O EEPROM Control Gate Reference
5 INJECT Analog I/O EEPROM Injection
6 TUNNEL Analog I / O EEPROM Tunneling
7 INTEGCALIBRATION Analog I / O Integrator Calibration Current
8 INTEGVPBl Bias Integrator Transconductor Bias
9 INTEGVPB2 Bias Integrator Transconductor Bias
10 INTEGVN B1 Bias Integrator Transconductor Bias
11 INTEGVN B2 Bias Integrator Transconductor Bias
12 IN TEGVREF Bias Integrator Reference Voltage
13 INTEGVCMP Bias Integrator Comparator Threshold
14 INTEGREFCURRENT Bias Integrator Input Sink
15 INTEGMEAS Digital In Integrator Measurement Control
16 INTEGRESET Digital In Integration Capacitor Reset
17 INTEGPULSE Digital Out Integrator Output Pulse
18 SERIALTEST Digital Out Shift Chain Cell #424 Out
19 SERIALIN Digital In Serial Shift Chain In
20 SERIALOUT Digital Out Serial Shift Chain Out
21 CLK Digital In Input Clock
22 INTEGINVBIAS Bias Integrator Output Inverter Bias
23 GAMMAl Bias Gamma #1 Bias
24 GAMMA2 Bias Gamma #2 Bias
25 EEPROMBIAS Bias EEPROM Cascode Bias
26 CELLBIAS Bias SVM Cell Bias
27 X<O> Analog I/O Input Dimension #1
28 X<1> Analog I/O Input Dimension #2
29 X<2> Analog I / 0 Input Dimension #3
30 X<3> Analog I / 0 Input Dimension #4
31 X<4> Analog I / 0 Input Dimension #5
32 X<5> Analog I / 0 Input Dimension #6
33 X<6> Analog I/O Input Dimension #7
34 X<7> Analog I / 0 Input Dimension #8
35 X<8> Analog I/O Input Dimension #9
36 X<9> ' Analog I / 0 Input Dimension #10
37 X< 10> Analog I / 0 Input Dimension #11
38 X<11> Analog I/O Input Dimension #12
39 X<12> Analog I / 0 Input Dimension #13
40 X<13> Analog I/O Input Dimension #14

 

 

 

 

Table A.1. Fabricated Prototype Pin Descriptions

104

 

APPENDIX B

Test Station Design Documentation

B.1 Test Station Parts List

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Designator Description Manufacturer Part
A1 CONN HDR BRKWAY .100 80POS RT/ A 4—103326—0
A2 CONN HDR BRKWAY .100 80POS RT/A 4-103326—0
A3 CONN RECEPT R/A lOOPOS 1.27MM FX2-100$4.27DS(71)
ADC] IC ADC 16CH 24BIT DIFINPUT28$SOP LTC2418CGN#PBF
ADC2 IC ADC 24BIT DIFFINPUT/REFIGSSOP LTC2415-1CGN#PBF
ADC #1 CONN JACK BNC VERT SOOHM PCB 227699-1
ADC #2 CONN JACK BNC VERT 5OOHM PCB 227699-1
ADC #3 CONN JACK BNC VERT 5OOHM PCB 227699-1
ADC #4 CONN JACK BNC VERT 5OOHM PCB 2276991
ADC #5 CONN JACK BNC VERT 5OOHM PCB 227699-1
ADC #6 CONN JACK BNC VERT 5OOHM PCB 227699-1
ADC #7 CONN JACK BNC VERT 5OOHM PCB 227699—1
ADC #8 CONN JACK BNC VERT 5OOHM PCB 227699-1
AMPO IC OPAMP RRIO DUAL 12V 8—SOIC OPA2743UAG4
AMP1 IC DUAL R-TO-R OP AMP 8-SOIC TLC2252IDG4
AMP2 IC OPAMP RRIO DUAL 12V 8—DIP OPA2743PAG4
AMP3 IC OPAMP RRIO DUAL 12V 8-DIP OPA2743PAG4
AMP4 IC OPAMP RRIO DUAL 12V 8—DIP OPA2743PAG4
AMP5 IC OPAMP RRIO DUAL 12V 8—DIP OPA2743PAG4
C0 CAP TANTALUM 22UF 16V 20% SMD F931C226MCC
C1 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
C2 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
C3 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
C4 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
C5 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB10105K

 

105

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Designator Description Manufacturer Part
C6 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
C7 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
C8 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
C9 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
C10 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
Cll CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
C12 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
C13 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
C14 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
C15 CAP TANTALUM 1UF 16V 20% SMD F 931C105MAA
C16 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA
C17 CAP TANTALUM 1UF 16V 20% SMD F9310105MAA
C18 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA
C19 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA
C20 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA
CADCl CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CB1 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CB2 CAP 4.7UF 25V CERAMIC F 1206 ECJ—3FF1E475Z
CB3 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CB4 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CB5 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CB6 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CB7 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CBS CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CB9 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CDACl CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CDAC2 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CDAC3 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CDAC4 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CDAC5 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CDAC6 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CDAC7 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CDAC8 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CDAC9 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CDAClO CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CIDO CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CIDl CAP TANTALUM 1UF 16V 20% SMD F931C105MAA
CID2 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CID3 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA
CID4 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CID5 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA

 

106

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Designator Description Manufacturer Part
CID6 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CID7 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA
CID8 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CID9 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA

CID10 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CID11 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA
CID12 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E47SZ
CID13 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA
CID14 CAP 4.7UF 25V CERAMIC F 1206 ECJ-3FF1E475Z
CID15 CAP TANTALUM 1UF 16V 20% SMD F931C105MAA
CR1 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
CR2 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
CR3 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
CR4 CAP TANTALUM 10UF 16V 20% SMD F931C106MBA
CR5 CAP 1UF 16V CERAMIC X7R 1206 ECJ-3YB1C105K
CTl CAP 33UF 25V ELECT MZA SMD EMZA25OADA330MF61G
CT2 CAP 33UF 25V ELECT MZA SMD EMZA25OADA330MF61G
D0 LED RED CLEAR 1206 SMD LTST-C150CKT
D1 LED RED CLEAR 1206 SMD LTST-C150CKT
D2 LED RED CLEAR 1206 SMD LTST-C15OCKT
D3 LED RED CLEAR 1206 SMD LTST-C15OCKT
D4 DIODE SCHOTTKY 30V 1.5A NMP 2P MA2Q70500L
D5 DIODE SCHOTTKY 30V 1.5A NMP 2P MA2Q70500L
DACl IC DAC OCTAL R—R 16BIT 16SSOP LTC2600CGN#PBF
DAC2 IC DAC OCTAL R—R 16BIT 16SSOP LTC2600CGN#PBF
DAC3 IC DAC OCTAL R—R 16BIT 16SSOP LTC2600CGN#PBF
DAC4 IC DAC OCTAL R—R 16BIT 16SSOP LTC2600CGN#PBF
DAC5 IC DAC OCTAL R—R 16BIT 16SSOP LTC2600CGN#PBF
DAC #1 CONN JACK BNC VERT 500HM PCB 227699-1
DAC #2 CONN JACK BNC VERT 500HM PCB 227699-1
DAC #3 CONN JACK BNC VERT 500HM PCB 227699-1
DAC #4 CONN JACK BNC VERT 500HM PCB 227699-1
DAC #5 CONN JACK BNC VERT 500HM PCB 227699-1
DAC #6 CONN JACK BNC VERT 500HM PCB 227699-1
DAC #7 CONN JACK BNC VERT 500HM PCB 227699-1
DAC #8 CONN JACK BNC VERT 500HM PCB 227699-1
JPO SHORTING JUMPER GLD/NICKEL BLUE 929955-06-ND
JPl SHORTING JUMPER GLD/ NICKEL BLUE 929955-06-ND
JP2 SHORTIN G JUMPER GLD/ NICKEL BLUE 929955-06-ND
JP3 SHORTING JUMPER GLD/ NICKEL BLUE 929955—06—ND
JP4 SHORTING JUMPER GLD/ NICKEL BLUE 929955—06—ND

 

107

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Designator Description Manufacturer Part
JP5 SHORTING JUMPER GLD/NICKEL BLUE 929955-06—ND
JP6 SHORTING JUMPER GLD/ NICKEL BLUE 929955—06—ND
JP7 SHORTING JUMPER GLD/NICKEL BLUE 929955—06—ND
JP8 SHORTING JUMPER GLD/NICKEL BLUE 929955—06—ND

JPW CONN POWERJACK MINI .1” R/ A PCMT SC237-ND
L1 FERRITE CHIP 1000 OHM 200MA 0805 BLM21AG102SN1D
L2 POWER INDUCTOR 1.0mH 0.18A SMD CDRH74NP-102MC
MUXl IC SW OCTAL SER 2.7/5.5V 24TSSOP ADG715BRUZND
POTl IC POT DIGITAL 128POS 14-TSSOP AD7376ARUZIOO
POT2 IC POT DIGITAL 128POS 14-TSSOP AD7376ARU10
POT3 IC POT DIGITAL 128POS 14-TSSOP AD7376ARU10
POT4 IC POT DIGITAL 128POS 14»TSSOP AD7376ARU10
POT5 IC POT DIGITAL 128POS 14-TSSOP AD7376ARU10
POT6 IC POT DIGITAL 128POS 14-TSSOP AD7376ARU10
POT7 IC POT DIGITAL 128POS l4-TSSOP AD7376ARU10
POT8 IC POT DIGITAL 128POS 14-TSSOP AD7376ARU10
POT 9 IC POT DIGITAL 128POS 14-TSSOP AD7376ARU10
R0 RES 1.00K OHM 1/4W 1% 1206 SMD ERJ-8ENF1001V
R1 RES 511 OHM 1/4W 1% 1206 SMD ERJ-8ENF5110V
R2 TRIMPOT 2K OHM 4MM TOP ADJ SMD 3224W-1-202E
R3 RES 511 OHM 1/4W 1% 1206 SMD ERJ-8ENF5110V
R4 RES 511 OHM 1/4W 1% 1206 SMD ERJ-8ENF5110V
R5 TRIMPOT 2K OHM 4MM TOP ADJ SMD 3224W-1-202E
R6 RES 511 OHM 1/4W 1% 1206 SMD ERJ-8ENF5110V
R7 RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF2201
R8 RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF2201
R9 RES 2.20M OHM 1 / 8W 1% 0805 SMD MCRlOEZHF2204
R10 RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF2201
R11 RES 2.20M OHM 1 / 8W 1% 0805 SMD MCRlOEZHF2204
R12 RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF2201
R13 RES 2.20M OHM 1/8W 1% 0805 SMD MCRlOEZHF2204
R14 RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF2201
R15 RES 2.20M OHM 1 / 8W 1% 0805 SMD MCRlOEZHF2204
R16 RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF2201
R17 RES 2.20M OHM 1/8W 1% 0805 SMD MCRlOEZHF2204
R18 RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF2201
R19 RES 2.20M OHM 1/8W 1% 0805 SMD MCRlOEZHF2204
R20 RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF 2201
R21 RES 2.20M OHM 1/8W 1% 0805 SMD MCRlOEZHF2204
R22 RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF 2201
R23 RES 2.20M OHM 1/8W 1% 0805 SMD MCRlOEZHF2204

 

 

 

108

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Designator Description Manufacturer Part
R24 RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF2201
R25 RES 511 OHM 1/4W 1% 1206 SMD ERJ—8ENF5110V
RADCl RES 2.20K OHM 1/8W 1% 0805 SMD MCRlOEZHF2201

RR1 RES 511 OHM 1/4W 1% 1206 SMD ERJ-8ENF5110V

RR2 T RIMPOT 2K OHM 4MM TOP ADJ SMD 3224W-1-202E

RR3 RES 511 OHM 1/4W 1% 1206 SMD ERJ—8ENF5110V

TUNNEL IC MOSFET DRVR SGL HS 9A 8—DIP UCC37322P

U0 IC REG POSITIVE 1.5A LDO TO-263 LM1086CS—ADJ/NOPB
U1 IC REG POSITIVE 1.5A LDO TO-263 LM1086CS-ADJ/NOPB
U2 IC REG POSITIVE 1.5A LDO TO-263 LM1086CSADJ/NOPB
U3 IC PREC REF LDO 4.096V 8-SOIC LT1461AC38—4#PBF
U4 IC REF LDO MICROPWR 2.5V 8SOIC LT1461AC38-2.5
U5 IC SW-CAP VOLT CONV 8-SOIC MAX1681ESA
U7 IC SW—CAP VOLT CONV 8-SOIC MAX1681ESA
U8 IC DC-DC CONV HI EFF 8-DIP MAX762CPA+

U10 IC VOLT REFERENCE LDO 2.5V 8801C REF192FSZ

U11 IC VOLT REFERENCE LDO 2.5V SSOIC REF192FSZ

U12 IC VOLT REFERENCE LDO 2.5V SSOIC REF192FSZ

U13 IC VOLT REFERENCE LDO 2.5V 8801C REF192FSZ

U14 IC VOLT REFERENCE LDO 2.5V 8SOIC REF192FSZ

U15 IC VOLT REFERENCE LDO 2.5V 8801C REF192FSZ

U16 IC VOLT REFERENCE LDO 2.5V 8SOIC REF192FSZ

U17 IC VOLT REFERENCE LDO 2.5V SSOIC REF192FSZ

 

 

 

Table B.1. Test Station Parts List

109

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RIO ‘
l:|
R12
III
914
I:
R18
|:|
R20
III
R22
C3
R24
|:l

W‘
nixed-Sumo! 1c Testing Board v1 1 O

as

40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

mEn—Em _l_ 2 3 4. 5 6 7 B 9
m] at 2 m: mDmD mDmD MDWD mDmD

3m mmwfl MENU MENU mmwfl a.
WUUEm MD; 2 . mnu m: mD m MD mu

3 ENE a .L .s m0 U D E 5D
WUUE MSW u n .m FE ”mm m mam a
EEW “mm u 4% E mu. E mu. a mu a mu.
MUUHWEUEU E m r. E mm mm mm mm
mmflmm Eufififi “WEE mm EE

3.. E3 Dub] m%

 

 

. mCUEm m kggm KEm

R92
v—fi
.._I

 

 

Figure B.1. Gerber Output: Motherboard Top Silkscreen
110

 

 

II .II .II .II .II .II 11:"
E EI-H-II-H-H-I ° E E ’ '
II II II ~Il ~II %II II II C O O O
. .55.. -= = " II o 0 O O
I— —I- I: = -II 0 O
=§,§== 'l =Fh1’ 3| I O O O 0
III Ill" 0 O O o
=I-- "I. I I I 'ml 0 .
-- I I I o o o o
I... I. O... OOOI
IIII II n. "u = o o o 0
I'll Il'l; . .
_ o o o o

 

 

. C C .
=I== ” = =' 5 5 = = II... "I
- - - -. 0 °.
_ _ o o _ _ I . O C
III. II ' ' 0". oII
IIII u '° ' ' ' ’
II II II III. II o
C O C C
= -. : : - - .I... 'I'
- - - I
= = 0 0 = 1:. I. . .
’ ' 0". oll
.0 C C C C
III II II II IIII II '-
=I== I. _ -. : : _ _ -..O‘l 0'. . . . .
- - - - ’
= = o o = =0 .0. O 0
I'll III ° ' 'l'l oll
IIII n " ' ' ' ’
II II II I'll II o
C C C .
:-- = : : = - .m
II = = o o = =' .0 O O
I. ' ' 0"". all
.. .0 O O C C
0 :: '
. 0.000000000000000... 3.000000000000000... .
IOOOOOOOOOOOOOOOOOOO oooooooooooooooooooo

Figure B.2. Gerber Output: Motherboard TOp Solder Mask

111

 

 

 

Figure 3.4. Gerber Output: Motherboard Middle Layer 1

113

 

Figure B.5. Gerber Output: Motherboard Middle Layer 2

114

 

 

 

 

II . I . I . I . I . I E: II
0 O
,:,::,::.::,::, '2- O O
I II II II II II II I O O O O
-. ,-. 0. s o.
!' O O O O
O .°.
. IO! . .
O
O
. o- . .3 O O O O
. OO;O’
. a: O O O O
‘3 ° C O
O O O O
000- ooon .
' ' ' . O O O O
0000 0000 . .
o
O O O O
I
o
. o. o o o .000 .
O
. I. .I . .0. . . . . .
o O 0 °
0 o ' 0 " Q Q
C . . Q...) .
. . . .- 0 O O O
O. O O O O... .
O
.- g .0, . . . . .
o o -
o o ' ' " O O
. . 0.0.: .
.- O O O O
O. O O O O... O.
O
.I o ,0, . C O C O
o o o
o o 0 0 ’ O O
. . . . ..' o
O
. .- O O O O
O. O O .00... .
Q
.g . ,0, . O O O O
o . . ' .0
0 O ' ' O O
I. ° ’ '.'.' -
C. °‘ 0 0 C 0
I O
o
. 00000000000000.0000. Iooooooooooooooooooo .
looooooooooooooooooo oooooooooooooooooooo

Figure 3.7. Gerber Output: Motherboard Bottom Solder Mask

116

O O O O
. O 0
O O O O
O O O O
0
° 00
o O O
o. o
.0...
00.0
to... 00 O O O O
0000
no... 0
.000 o
.0...
O O O O
o
O
o. O O
O
. O.
O 0 O O
o
0000 00..
O
O
’ ' o o o o
O
O... O...
' o o
o. o
00...
o.
0000. O O O O
.000
00000 o
0.00
to... o
O. O O O O...
. o
. O O O 0
oo o 0 °
0 o
O O O
o 0 ° ° 0 O
. o o . ,'
O O O O
O o O
o. o o o 0000
o
O
. O O O O
o o ,
. O
.0 O O
000.. . .
0000 O O O O
.0... .
.000 O O . .
IO... '
.00.
00000 I O O O
O. O O O 0... 0
° 0
o O O O O
0. g g .
O O
o O O
o o ' ° 0 o
O
. . . . '-
0 O O O
O
O. O O 00....
O
o
. o o o o
o o
o
O O
O O I
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Figure B.8. Motherboard NC Drill Output

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Figure B.9. Gerber Output: Daughterboard Top Silkscreen

 

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Figure B.10. Gerber Output: Daughterboard Top Solder Mask

118

    

 

 

 

 

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Figure B.11. Gerber Output: Daughterboard Top Layer

Figure 3.12. Gerber Output: Daughterboard Bottom Layer
119

 

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Figure B.13. Gerber Output: Daughterboard Bottom Solder Mask

Figure B.14. Daughterboard NC Drill Output

120

   

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126

APPENDIX C

Test Station VHDL

C.1 Digital Clock Manager: dcm.vhd

 

 

1

2 —— Author: Paul R. Kucher

3 —- Module Name: clkmgr — Behavioral
4 — Modified: 2007—09—13

5 — Description: The digital clock manager for :rc3s200—ft256—4.
6

7 library IEEE;

8 use IEEE.STD_LUGIC_1164.ALL;

9 use IEEE.STD_LOGIC_ARITH.ALL;

10 use IEEE.STD_LOGIC_UNSIGNED.ALL;

11 use IEEE.NUHERIC_STD.ALL;

12

13 library UNISIH;

14 use UNISIH.Vcomponents.ALL;

15

16 entity clkmgr is

17 Port(

18 c1kin_in: in std_logic;
19 c1kfx-out: out std_logic;
20 c1k1n_ibufg_out: out std_logic;
21 c1k0-out: out std_logic
22 );

23 end clkmgr;

24

25 architecture Behavioral of clkmgr is
26 signal CLKFB_IN: std_logic;

27 signal CLKFX_BUF: std_logic;

28 signal CLKIN_IBUFG: std_logic;

29 signal CLKO_BUF: std_logic;

30 signal c1k0_out1: std_logic;

31 signal GND_BIT: std_logic;

32 component BUFG

33 port ( I : in std_logic;

34 0 : out std_1ogic);

35 end component;

36

37 component IBUFG

38 port ( I : in std_logic;

39 0 : out std_10gic);

127

40 end component ;

41

42 —— Period Jitter (unit interval) for block DCMJNST= 0.15 U]
43 -—— Period Jitter (PMak—to—Fwak) for block DCWLJNST‘='0.61 ns
44 component DC)!

45 generic( CLK_FEEDBACK : string :=I "111";

46 CLKDV_DIVIDE : real 1- 2.0;

47 CLKFX_DIVIDE : integer :3 1;

48 CLKFX_HULTIPLY : integer :- 4;

49 CLKIN_DIVIDB_BY_2 : boolean :- FALSE;
50 CLKIN_PERIOD : real :- 10.0;

51 CLKOUT_PHASE_SHIFT : string :- "NONE”;
52 DESKEU-ADJUST : string :- "SYSTEM-SYNCHRONOUS";
53 DFS_FREQUENCY_HODE : string :- ”LOW";
54 DLL_FREQUENCY_HODE : string :- "LOW”;
55 DUTY_CYCLE-CORRECTION : boolean :- TRUE;
56 FACTORY_JF : bit_vector :- x”C080';
57 PHASE_SHIFT : integer :- O;

58 STARTUP_HAIT : boolean :- FALSE;

59 DSS-HODE : string :- ”NONE');

60 port ( CLKIN : in std_logic;

61 CLKFB : in 8td_logic;

62 RST : in std_logic;

63 PSEN : in std_logic;

64 PSINCDEC : in std_logic;

65 PSCLK : in std-logic;

66 DSSEN : in std_logic;

67 CLKO : out std_logic;

68 CLK90 : out std_logic;

69 CLK18O : out std_logic;

7o CLK27O : out std_logic;

71 CLKDV : out std_logic;

72 CLK2X : out std_logic;

73 CLK21180 : out std_logic;

74 CLKFX : out std_logic;

75 CLKFX18O : out std-logic;

76 STATUS : out std_logic_vector (7 dounno 0);
77 LOCKED : out 6td_logic;

78 PSDONE : out std_logic);

79 end component;

80

81 begin

82 GND_BIT <- ’0’;

83 c1kin_ibufg_out <- CLKIN_IBUFG;

84 c1k0_out <- CLKFB-IN;

85 CLKFX-BUFG_INST : BUFG

86 port map (I->CLKFX_BUF ,

87 0->c1kfx_out);

88

89 CLKIN_IBUFG-INST : IBUFG

90 port map (I->c1kin_in.

91 0->CLKIN_IBUFG);

92

93 CLKO_BUFG-INST : BUFG

94 port map (I->CLKO_BUF,

95 0->CLKFB_IN);

96

97 CLKO_BUFG_INST1 : BUFG

93 port map (I=>CLKO_BUF,

99 0->c1k0_out1);

100

101 DCM_INST : DCM

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0.2 Instruction Decoder and System Controller:

«30043101591».—

uNHHudHHHuHHt-o
Hoomqamawuwo

generic map( CLK-FEEDBACK => "1X",

CLKDV-DIVIDE -> 2.0,
CLKFX_DIVIDE -> 1,
CLKFX_HULTIPLY 8) 5,

CLKIN_DIVIDE_BY_2 -> FALSE,

CLKIN_PERIOD 8) 20.000
CLKOUT_PHASE-SHIFT .)

"NONE",

DESKEU-ADJUST I) "SYSTEH_SYNCHRONOUS",

DFS_FREQUENCY-HODE ->
DLL_FREQUENCY_HODE I)

"HIGH",
"LOW",

DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF -> x”8080“,
PHASE_SHIFT -> 0,
STARTUP-HAIT -> FALSE)
portrnqp (CLKFB->CLKFB_IN,
CLKIN->CLKIN_IBUFG,
DSSEN->GND_BIT,
PSCLK->GND_BIT,
PSEN->GND_BIT,
PSINCDEC->GND-BIT,
RST->GND_BIT,
CLKDV->open,
CLKFx->CLKFX-BUP,
CLKFX180->open,
CLKO->CLKO_BUF,
CLK2x—>open,
CLK2X180->open,
CLK90->open,
CLK180->open,
CLK270->open,
LOCKED->open,
PSDONE->open,
STATUS->open);

end Behavioral ;

decode.vhd

 

Paul R. Kucher
— Alodule Name: decode — Behavioral
—— Alodflied: 2007—09-13

—— Author:

Description: This nunn.rnodule controls the entire systeni. It
for decoding individual instructions coming from 125—232
communications and enables the appropriate sub—modules

—— to complete a given task.

is responsible

 

library IEEE;

use IEEE.STD_LOGIC_1164MALL;

use IEEE.STD_LOGIC_ARITHLALL;
use IEEE.STD_LOGIC_UNSIGNEDMALL;

entity decode is

generic(
width: integer :=16;
addr: integer :818;
depth: integer :=8

)3

Port(

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clk:

seria1-select:
txd_ready:
txd_conplete:
rxd-conplete:
parallel-txd:
parallel_rxd:

shift_start-f1ag:
shift_end_flag:

leds:
led_data:

fron_address:
to-address:
read_block:
urite_block:
men_data_in:
xfr_op_conp1eted:
nodule_se1ect:

vdac_select:
sig_gen_enable:
sig_gen-conplete:

program_dac:
dac-prograIned:
dac-instruction:

adc-conv-mode:
adc_address:
adc_data_ready:
adc_data_collect:

iadc-data_ready:
iadc_data_c011ect:

inject_pulse:
pulse_injected:
injection_pulse_width:

tunnel_pulse:

io_instruction:
io_update:
io_updated:
io_output:

digit-pot_nunber:

digit_pot_value:

digit_pot_update:

digit_pot_updated:
);

end decode;
architecture Behavioral of
begin

leds(7) <- ’0’; leds(6) <=

out

out
out

out
out
out
out
out
in

out

out
out
in

out
in
out

out
out
in

out

out

out
in
out

out

out
out
in

out
out
out
in

std_logic;

integer range 0 to 2;
std_logic;

std_logic;

std-logic;

std_10gic_vector(15 downno 0);
std_logic_vector(15 downno 0);

std_logic;
std_logic;

std_logic_vector( 7 downno 0);
std_logic_vector(15 dounno O);

std_logic_vector(addr dovnno 0);
std_logic_vector(addr dounno 0);
std_logic;

std_logic;

std_logic_vector(15 dounmo 0);
std_10gic;

integer range 0 to 5;

integer range 0 to 2;
std_logic;
std_logic;

std_logic;
std_logic;
std_logic_vector(27 downno 0);

std_logic_vector(1 downno 0);
std_logic_vector (3 downto 0);
std_logic;
std_logic;

std_logic;
std_10gic;

std-logic;
3td_logic;
std_logic_vector (7 downto 0);

std_logic;

std_logic_vector(5 downno 0);
std_1ogic;
std_logic;
std_logic;

std_logic_vector (4 downto 1);
std_logic_vector(7 dovnno 1);
std_logic;

std_logic

decode i3

’0’;

1963(5) <= ’0’; led8(4) <= ’0’;

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leds(3) <- ’0’; 1eds(2) <- ’0’; leds(1) (a ’0’; leds(0) <- ’0’;

- TVUs is the instruction fetch and decode process. It takes in 16—bit
— data from the RS’232 bus and then decides whether to write to memory.
—— send data to the chip, read froniinenuny. or send data back to the [71
decode_and_execute: process( clk )
variable current_instruction: std_logic_vector(15 downto 0)

:- ”0000000000000000";
variable execute_state: integer range 0 to 50 :- 0;
variable inst_pointer, inst_pointer_1ast: integer range 0 to 100 :- 0;
variable msb_addr, nsb_addr2: std_logic_vector(2 downto 0) := "000";
variable read_or_vrite_block, new_instruction: std_logic :- ’0’;
variable dac_command: std_logic-vector(11 downto 0);

begin
if clk’event and clk - ’1’ then

if rxd_complete - ’1’ then —— fetch instruction
led-data <- std_logic_vector( parallel_rxd );
current_instruction :- para11e1-rxd;
inst-pointer :- inst-pointer + 1;

end if;

if inst-pointer > inst-pointer-1ast then
inst-pointer_last :8 inst-pointer;
nev_instruction :- ’1’;

else
new_instruction :- ’0’;

end if;

case execute_statI is
when 0 -> —- Idle State
if nev_instruction - ’1’ then
execute_state :- 1;

end if;

txd_ready <- ’0’;
urite-block <- ’0’;
read_block <- ’0’;
program_dac <- ’0’;
io_update <- ’0’;

adc_data-collect <- ’0’;
iadc_data_collect <- ’0’;
digit_pot_update <- ’0’;
shift_start_f1ag <- ’0’;

module_select <- 0;

serial_select <- 1;

vdac_select <- 1;

when 1 -> —— Decode Instruction

if current-instruction(15 donnno 11) = "0000" then
execute_state :- 3; —- Loopback

elsif current_instruction(15 dounno 12) = "0001" then
execute_state :- 5; -— hhmnny Transfer

elsif current_instruction(15 dounno 12) a “0010” then
execute_state :- 9;-—— VoHage DflC

elsif current_instruction(15 douwno 12) - "0011" then
execute_state ;. 11; —— lfifltage.ADC

elsif current_instruction(15 dounno 12) 3 "0100" then
execute_state :- 14; -— Churent.DAC

elsif current_instruction(15 downno 12) - "0101" then
execute_state :- 16; —— Churent.ADC

elsif current_instruction(15 dounno 12) - "0110" then
execute_state :- 21; —- EEPRCM! Injection

131

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elsif current-instruction(15 dounno 12) - ”0111” then

execute_state :- 23; —- EFPROM Tunneling

elsif current_instruction(15 dounno 12) - "1000" then
execute_state :- 24; -—- Digital 10

elsif current_instruction(15 dounno 12) - "1001' then
execute_state :- 26; -—- Signal (3eneration

elsif current_instruction(15 dounno 12) - "1010" then
execute_state :- 30;-—— Serial Shift Chant

else execute_state :- 2;

end if;

when 2 -> — Reset Instruction Pointer

inst_pointer_1ast := O;
inst_pointer :- 0;
execute_state :- 0;
‘when 3 ->-—— Yransfer data in current instruction over RS—232
parallel_txd <- current_instruction;
txd_ready <- ’1’;
execute_state :- 4;
when 4 -> — Transfer data continued
txd-ready <- ’0’;
if txd_conplete - ’1’ then
execute_state :- 2;
end if;
when 6 I) —— Memory Transfer (Block/Single Read ('4 W’rite)
nodule_select <- 2;
serial_select <- 2;
if neu-instruction - ’1’ then ——-1Receive Starting .4ddress
tron_address <- Isb-addr & current_instruction;
Ixecute_state :- 6;

else
nsb_addr :- current-instruction(2 dounno 0); —— 17—19th bits of
Isb_addr2 :-I current-instruction(5 dounno 3);-—— Address Reg.
read_or-urite-block :- currInt_instruction(10);
end if;
‘when 6 ->
if nev_instruction - ’1’ then — Receive Ending Address

to-address <- Isb_addr2 & current_instruction;
execute_state :- 7;
end if;
‘when 7 ->
if read-or_urite_block - ’1’ and nev-instruction - ’1’ then
vrite_block <8 ’1’; '
nem_data_in <- current_instruction;
execute_state :- 8;
elsif read_or_vrito-block - ’0’ then
read_block <- ’1’;
execute_state :- 8;
end if;
udmm 8 ->
urite_block <- ’0’;
read-block <- ’0’;
if xtr_op_completed - ’1’ then execute_state := 2;
end if;
when 9 -> — Voltage DAC
if new-instruction 8 ’1’ then
dac-inetruction (8 dac_command I current_instruction;
program_dac <- ’1’;
execute_state :- 10;
else
dac_connand :- current_instruction(11 dounno 0);
end if;
when 10 ->

132

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209
210

260

program_dac (I ’0’;
1f dac_programmed I ’1’ then execute_state :I 3; end if;

when 11 I) —- Voltage ADC
module_select <I 3;
if neu_instruction I ’1’ then ——- Receive Starting z4ddress

fron-address <I msb_addr & current_instruction;
execute_state :I 12;

else
nsb_addr :I current_instruction(2 dounno 0); -— 17—19th bits of
nsb_addr2 :I current_instruction(5 dounno 3); ——-;4ddress Reg.

adc-address <I current_instruction(11 dounno 8);
adc_conv_node <I current_instruction(7 downmo 6);
end if;
vflunnl2 I)
if new_instruction I ’1’ then-—— Receive Endfiu714ddress
to_address <I nsb_addr2 & current_instruction;
adc_data_collect <- ’1’;
execute_state :I 13;
end if;
when 13 I)
adc_data_colloct <- ’0’;
if adc_data-ready I ’1’ then
current-instruction :I "0000000000000000";
execute_stato :I 3;
end if;
when 14 I) -- Current DAC
digit_pot_number <- current-instruction(11 domnno 8);
digit_pot_va1uo <I current-1nstruction(6 dounno 0);
digit_pot_update <I ’1’;
oxecute_state :I 15;
‘when 15 ->
digit_pot_update <- ’0’;
if digit-pot-updated I ’1’ then
current_instruction :I "0000000000000000";
execute_state :I 3;
end if;
when 16 -> —- Current ADC
modu10_select (I 4;
if new_instruction I ’1’ then ——— Receive Starting 14ddress
from_address <I msb-addr & current_instruction;
execute_state :I 17;

else
msb_addr :I current-instruction(2 dounno O); -— 17—19th bits of
nsb_addr2 :I current_1nstruction(5 do‘nno 3); ——-‘4ddress Reg.
adc_address <I current-1nstruction(11 dounno 8);
end if;
“dam 17 I)
if new_1nstruction I ’1’ then —— Receive Ending Address

to_address <I nsb_nddr2 t current_instruction;
execute_state :I 18;
end if;
when 18 ->
if new_instruction I ’1’ then-—— Receive Gabi Update
digit_pot-number <I "0000"; '
digit_pot_va1ue <I current-instruction(6 downno 0);
if current_instruction(15) I ’1’ then —— (Duh; Update on [tequest
digit_pot-updata (I ’1’;
execute_state :I 19;
else
iadc_data-collect <= ’1’;
execute_stata :I 20;
end if;

133

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287
288

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end if;
when 19 I>
digit_pot_updato (- ’0’;
if digit-pot_updated I ’1’ then
iadc_data_collect (- ’1’;
execute_state :I 20;
end if;
*when 20 I)
iadc_data_collect (I ’0’;
if iadc_data_ready I ’1’ then
current-1nstruction :I "0000000000000000';
oxecute_state :I 3;
end if;
when 21 I) —— EEPROM Injection
injection_pulse_vidth <= current_instruction(7 domnno 0);
1nject-pulse (I ’1’;
execute_stato :I 22;
“men 22 I)
inject-pulse (I ’0’;
current_1nstruction :I "0000000000000000";
if pulse_injected I ’1’ then execute_state :I 3; end if;
when 23 I) —— EEPROM Tunneling
tunnel_pulse (- current-instruction(0);
current_instruction :I "0000000000000000";
execute_state :- 3;
when 24 I> —— Digital I/O
io_instruction (I current_instruction(11 domnno 10) &
current_instruction(3 downto 0);
io_update <I ’1’;
executo_stato :I 25;
‘When 25 I)
io_update (I ’0’;
if io-updated I ’1’ then
current_1nstruction :I "000000000000000" & io-output;
exocute-state :I 3;
end if;
when 26 I) —— Signal Generation
vdac_select (I 2;
nodule_select (I 5;
if new_instruction I ’1’ then —-.Receive Starting i4ddress
from_address (I nsb-addr & current_instruction;
execute_state :I 27;

else
msb_addr :I current_instruction(2 dounno O); —— 17—19th bits of
msb_addr2 :I current_instruction(5 downto 3); — Address Reg.
end if;
\Nhen 27 I)
If neu-instruction I ’1’ then ——-.Receive Ehuhng zdddress

to_address (I msb_addr2 & current_instruction;
sig-gen-enablo (- ’1’;
oxecute_state :I 28;
end if;
wdmm 28 I)
if nev-instruction I ’1’ then-— Receive Stop Cbndinon
sig_gen_enable (- ’0’;
execute_state :I 29;
end if;
'when 29 I)
if sig_gen_comp1ete = ’1’ then
current_instruction :I "0000000000000000";
oxecute_stato :I 3;
end if;

134

C.3 Multi-channel Digital Input / Output:

OOQGMAWNH

NMNNQNDNNNwwav—nu—Hi—nw
omeamawnwoemqamemnuo

when 30 I> —— Program Serial Chain
modulo_select (I 1;
if nev-instruction I ’1’ then —— lieceuwz Starting l1ddTC$S
from_address (I msb_addr t current_instruction;
execute_state :I 31;

else
nsb_addr :I current_instruction(2 downto 0); — 17—19th
nsb-addr2 :I current_instruction(5 dounno 3);-—— Address
end if;
‘when 31 I)
lf nov_instruction I ’1’ then —— Receive Ending Address

to_address (I nsb_addr2 l current-instruction;
shift_start_flag (I ’1’;
execute_state :I 32;
end if;
‘Nhen 32 I)
shift_start_flag (- ’0’;
if shift_end-f1ag I ’1’ then
current_instruction :I "0000000000000000";
oxecute_state :I 3;
end if;
when others I) execute_state :I 0;
end case;
end if;
end process;

end Behavioral;

bits of

Reg.

digital_io.vhd

 

-— Author: Paul R. Kucher
— Module Name: digital_io — Behavioral
—— Modified: 2007-09— 05

-—— Description: This module allows easy access to the FPGA’s I/Os from the
-—— remaining pins on the FPGA development board. From. Matlab.
— the direction of each pin may be set and data may be read

— or written to each of these ports.

—— If the main decoder unit is modified to accommodate additional
— functionality utilizing one of these l/Os, be sure remove the

—— pins from the UCF file accordingly.

—— Pins are currently assigned as follows:
— digital-io(0) H’GA Pin MIO
—— digital_io(1) FPCfl [Rn A7
-— digital_io (2) FPGA Pin 1117
— digital_io(3) FPGA Pin A13
— digital_io (4) FPGA Pin A9
—— digital_io(5) FPGA Pin AID
—- digital_io(6) FPGA Pin BM
—— digital-io(7) FPCK th A8
— digital-io(8) FPGA Pin 81]
—— digital_io(9) FTKLQ Pu: BIZ
- digital_io(10) FPGA Pin .412
—— digital-io(ll) FPGA Ffin BIO
—- digital_io(12) FPGA Ffin 813

 

library IEEE;

135

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use IEEE.STD_LOGIC-1164.ALL;
use IEEE.STD_LDGIC_ARITHLALL;
use IEEE.STD_L0GIC_UNSIGNEDLALL;

entity digital_io is

Port(
clk: in std_logic; —— FPGA clock
digital_ios: inout std_logic_vector(12 downto 0); — FPGA I/O Pins
instruction: in std_logic_vector(5 downto 0);
io-update: in std_logic; -— Flag to read instruction
io_updated: out std-logic; —— Flag indicating instruct-ion executed
output: out std_logic — Output Data (If Applicable)
);

end digital_io;

architecture Behavioral of digital_io is
begin

state_nachins: process( clk )

variable io-stato: integer range 0 to 7 :I 0;

variable io_set: integer range 0 to 40 :I 0;
begin

if clk’ovent and clk I ’1’ then
case io_state is
when 0 I) -— Initialization State
digital_ios (I (digita1-ios’range I) ’Z’);
io-state :I 1;
when 1 I) -— Idle State
if io_update I ’1’ then
io_state :I 2;
end if;
io_sot :I 0;
io_updated (I ’0’;
when 2 I) —— Make High Impedance
if instruction (3 downto 0) I "0000' then io_set 'I 1;
elsif instruction (3 downto 0) I "0001" then io-set :I 2;
elsif instruction (3 downto 0) I "0010" then io_set :I 3;
elslf instruction (3 downto 0) I "0011" then io_set -I 4;
elsif instruction (3 downto 0) I "0100' then io_set :I 5;
elsif instruction(3 downto 0) - "0101" then io_set :I 6;
elsif instruction (3 downto 0) I "0110" then io_set :I 7;
elsif instruction (3 downto 0) I "0111' then io_set :I 8;
elslf instruction (3 downto 0) I “1000' then io-sst :I 9;
elsif instruction (3 downto 0) I "1001” then io_sst :- 10;
elsif instruction (3 downto 0) I "1010" then io_set :I 11;
elsif instruction(3 downto 0) I "1011' then io_set :I 12;
elslf instruction (3 downto 0) I "1100" then io_set -- 13;
end if;
io_stato :I 3;
when 3 I) —— Decode
lf instruction (5) I ’1’ then —— Set 1/0
if instruction (3 downto 0) I "0000' then io_set :I 14;
elslf instruction (3 downto 0) "0001" then io_set :I 15;
elsif instruction (3 downto 0) “0010” then io_set :I 16;
elsif instruction (3 downto 0) "0011' then io_set :I 17;
elsif instruction (3 downto 0) "0100” then io_set :I 18;
elsif instruction (3 downto O) "0101" then io_set :- 19;
elsif instruction (3 downto 0) "0110" then io_set :I 20;
elslf instruction (3 downto 0) "0111" then io_set :I 21;
elsif instruction (3 downto 0) "1000" then io_set :I 22;

136

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elslf
elsif
elsif
elsif
end if

instruction(3
instruction(3
instruction(3
instruction(3

downto
downh:
downto
downto

output (I instruction(4);

else —-
if
elsif
elsif
elsif
elsif
elsif
elsif
elslf
elsif
elsif
elslf
elslf
elsif
end if
end if;
io_state
1Nhen 4 I)

io_updated (I

io_state

Read I/O

instruction(3
instruction(3
instruction(3
instruction(3
instruction(3
instruction(3
instruction(3
instruction(3
instruction(3
instruction(3
instruction(3
instruction(3
instruction(3

3
:I 4;

’1’;

:I 1;

when others I) io_state

end case;

case io_sst is

downto
downuo
dounno
downto
dounno
downto
domnno
dounno
dounno
dounno
dounflo
dounflo
domnno

when 0 I) output (I instruction (4);
when 1 I) digital_ios (0) (I ’2’;
when 2 I) digital_ios (1) (I ’2’;
when 3 I) digital_ios (2) (I ’2’;
when 4 I) digital_ios (3) (I ’2’;
when 5 I) digital_ios (4) (I ’2’;
'when 6 I) digital_ios(5) (I ’2’;
when 7 I) digital_ios (6) (I ’2’;
‘when 8 I) digital_ios(7) (- ’2’;
‘when 9 I) digital_ios(8) (I ’2’;
‘when 10 I) digital_ios(9) (I ’2’;
when 11 I) digital_ios(10) (- ’2’;
‘when 12 I) digital_ios(11) (I ’2’;
when 13 I) digita1-ios(12) (I ’2’;
when 14 I) digital_ios (0) (I

when 15 I) digital_ios (1) (I

when 16 I) digita1-ios (2) (I

when 17 I) digital_ios (3) (I

when 18 I> digital_ios (4) (I

‘when 19 I) digital_ios(5) (I

when 20 I) digital_ios (6) (I

when 21 I) digital_ios (7) <-

when 22 I) digital_ios (8) (I

when 23 I) digita1-ios (9) (I

when 24 I) digita1-ios (10) (I

when 25 I) digital_ios (11) (I

when 26 I> digital_ios (12) (I

when 27 I) output (I digita1-ios (0);
'when 28 I) output (I digita1-ios(1);
when 29 I) output (I digital_ios (2);
when 30 I) output (I digital_ios (3);

0)
0)
0)
0)

0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)
0)

"1001”
"1010”
"1011"
"1100”

"0000"
"0001'
”0010”
"0011"
"0100'
”0101"
“0110”
"0111"
"1000"
"1001”
"1010"
"1011"
"1100"

then
then
then
then

then
then
then
then
then
then
then
then
then
then
then
then
then

instruction(4);

instruction(4);
instruction(4);
instruction(4);
instruction(4);
instruction(4);
instruction(4);
instruction(4);
instruction(4);
instruction(4);
instruction(4);
instruction(4);
instruction(4);

137

io_set
io_set
io_set
io-set

I 23;

24;
25;
26;

27;
28;
29;
30;
31;
32;
33;
34;
35;
36;
37;
38;
39;

154 when 31 I) output (I digital_ios (4);

155 when 32 I) output (I digital_ios (5);
156 when 33 I) output (I digital_ios (6);
157 when 34 I) output (I digital_ios (7);
158 when 35 I) output (I digita1-ios (8);
159 when 36 I) output (I digital_ios (9);
160 when 37 I) output (I digital_ios(10);
161 when 38 I) output (I digital_ios(11);
162 when 39 I) output (I digital_ios(12);
163 when others I) null;

164 end case;

165 end if;

166 end process;

167

168 end Behavioral;

0.4 Digital Potentiometer Control: digital_pots.vhd

 

 

1

2 —- Author: Paul R. Kucher

3 —- Module Name: digital_pots — Behavioral

4 —— Modified: 2007—07—13

5 — Description: This module controls the nine digital potentiometers on the
6 — mixed—signal test board. It takes in the value and channel
7 — number and updates the chain accordingly

8

9 library IEEE;

10 use IEEE.STD_LOGIC_1164.ALL;

11 use IEEE.STD_LOGIC_ARITH.ALL;

12 use IEEE.STD_LOGIC_UNSIGNED.ALL;

13

14 entity digital_pots is

15 Port(

16 clk: in std_logic; — FPGA Clock

17 digit-pot_c1k: out std_logic; —— Potentiometer Serial Clock

18 digit_pot_sdi: out std_logic; —— Potentiometer Serial Data Input
19 digit-pot_cs_bar: out std_logic; — Shift Enable

2o digit_pot-shdn-bar: out std_logic; -- Shutdown Signal

21

22 digit-pot_nunbar: in std_logic_vector(4 downto 1); —— Pot Number

23 digit_pot_va1us: in std_logic_vector(7 downto 1); —— 7—bit Pot Value
24 digit_pot-update: in std_logic; —— Potentiometer Update Flag

25 digit_pot_updated: out std_logic ~— Digital Potentiometer Updated Flag
26 );

27 end digital_pots;

28

29 architecture Behavioral of digital_pots is

30

31 begin

32

33 program_pots: process( clk )

34 variable count: integer range 0 to 127 := 0;

as variable shift_count: integer range 0 to 70 :I 0;

36 variable pot__stato: integer range 0 to 2 :I 0;

3? variable pot_chain: std_logic_vector(63 downto 1)

38 :I "100000010000001000000100000010000001000000100000010000001000000";
39 begin

4O

41 if clk’svent and clk I ’1’ then

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if count ) 64 then digit_pot_c1k <- ’1’;
else digit_pot_c1k <I ’0’;
end if;

case pot_etate is

‘when 0 I) —— Idle Slate
digit_pot_cs_bar (I ’1’;
digit-pot_sdi <- ’0’;
digit-pot_ahdn_bar (I ’1’;
digit_pot-updated (I ’0’;
ahift_count :I 0;
count :I O;
pot_stata :I 1;

'when 1 I)
if digit_pot_update I ’1’ then
if digit_pot_nunbar I ”0000" then —— IAIN? Potentunneter

pot-chain( 7 dounno 1) :I digit-pot-va1ue;
elsif digit_pot_nunber I “0001' then —— H140 Channel-#1
pot_chain(14 donnno 8) :I digit_pot_va1ue;
elsif digit_pot_nunber I "0010" then -— [DAC Channel #2
pot_chain(21 downno 15) :I digit_pot_va1ua;
elsif d1git_pot_nunber I "0011” then —— H140 CWannel;#3
pot_chain(28 donnflo 22) :I digit_pot_va1ua;
elsif digit_pot_nunbar I "0100“ then —— H140 Cmannel #4
pot-chain(36 donnno 29) :I digit_pot_va1ue;
elsif d1git_pot_nunber I "0101" then —— HZ4C’CWannel #5
pot_chain(42 dounno 36) :I digit_pot_va1ue;
elsif digit_pot_nunbar I "0110” then — [DAC Channel #6
pot-chain(49 donnno 43) :I digit_pot_va1uo;
elsif digit_pot_nunbar I "0111" then —— [DAC Channel #7
pot_chain(66 dounno 50) :I digit-pot_va1ua;
elsif digit_pot-nunbar I "1000" then —— Ul4C’Channel #8
pot-chain(63 dounno 67) :I digit_pot_va1ua;
end if;
pot_atate :I 2;
end if;
when 2 I)
if ahift_count < 1 then
digit-pot-adi <I ’0’;
digit-pot_cs_bar <I ’0’;
elsif ahift_count < 64 then
digit-pot-sdi <I pot_cha1n(63);
elsif ahift_count < 65 then
digit_pot_ad1 <I ’0’;
digit-pot_ca_bar <I '1’;
else
d1git_pot_updated (I ’1’;
shift_count :I 0;
pot_atate :I 0;
end if;

count :I count + 1;
if count I 127 then

count :I 0;
if shift_count < 64 and shift_count > 0 then

pot-cha1n (63 downto 1) :I pot_chain (62 downto 1) & pot_chain (63);

end if;
shift_count :I shift_count + 1;
end if;
*when others I) pot_state :I O;

139

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109

end case;
end if;

end process;

end Behavioral ;

C.5 Current ADC Control: iadc.vhd

DGQOCflfiuNW

maaaaatbaavbwwwwwrwwwwsnuNunwnnguwr—uwunu—H
090‘! 0‘ “DWOQQNQO‘ “MD-‘0 madmawnw (DU‘IOUIbGNi-‘O

 

—— Author: Paul R. Kucher

—- Module Name: iadc — Behavioral

— Modified : 2007— 09—07

—- Description: This module controls the 8 channel current ADC. It controls

—- the single channel LTC 2415 ADC as well as the ADC 715
———- analog multiplexer.

 

library IEEE;

use IEEE.STD_LOGIC_1164MALL;

use IEEE.STD_LOGIC-ARITHMALL;
use IEEE.STD_LOGIC_UNSIGNEDMALL;

entity iadc is

generic(
width: integer :I 16;
addr: integer :I 18;
depth: integer :I 8

)3

Port(
clk: in std_logic; -—-— FPGA clock
iadc_clk: out std_logic; —— Conversion Clock (f0)
iadc_sck: out std_logic; —- Serial Clock for ADC
iadc_cs-bar: out std_logic; —— Serial Transfer Enable
iadc_sdo: in std_logic; —— Serial Data Out (of ADC}
iadc-sc1: out std_logic; —— Serial Clock for Multiplexer
iadc_sda: inout std_logic; —— Serial I/O for Multiplexer
iadc_address: in std_logic_vector(3 downto 0); —— Channel Address
iadc_start_address: in std_logic_vector(addr downto O); — St. Data Store
iadc_end_address: in std_logic_vector(addr downto O); — End Data Store
iadc_data_ready: out std_logic; —- Data Conversion Complete Flag
iadc_data-collect: in std_logic; --— Control flag to initiate sampling
read_control: out std_logic; —— Instruct module to read data
urite_control: out stdglogic; —- Instruct module to write data
mem_op_completed: in std_logic; —- Flag if memory operation completed
address: out std_logic_vector(addr downto O); —— Address to R/W
nemory_data_vrite: out std_logic,vector(width-1 downto O) — Data to write
);

end iadc;

architecture Behavioral of iadc is

signal address_register: std_logic_vector (7 downto 0);
signal sdo_fi1tered: std-1ogic :I ’0’;

signal sdo-sync: std_10gic_vector(1 downto 0) :I "00";
begin

address_encode: process( iadc_address )

140

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63

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begin
case iadc_address is
'when "0000" I) address_register (I "00000001";
when "0001" I) address_register (I "00000010";
when "0010" I) address_register (I ”00000100";
'when ”0011” I) address_register (- ”00001000”;
when "0100" I) address_register (I "00010000";
‘when "0101” I) address_register (I "00100000";
when "0110" I) address_register (I "01000000";
'when ”0111" I) address_register (I "10000000”;
‘when others I) address_register (I "00000000";
and case;
end process;

sdo_sync_input: process( clk )
begin
if clk’event and clk I ’1’ then
sdo_sync (I sdo-sync(0) & iadc_sdo;
end if;
end process;

—- FWlter the inconfing data for any glitches.

sdo_filter-input: process( clk )

variable count : integer range 0 to 7 :I 5;

begin

if clk’evant and clk I ’1’ then

if sdo_sync(1) I ’1’ and count < 5 then count :I count + 1;
elsif sdo_sync(1) I ’0’ and count > 0 then count :I count - 1;
end if;

if count I 5 then sdo_fi1tered (I ’1’;
elsif count I 0 then sdo_filtered (I ’0’;
end if;
end if;
end process;

state_nachine: process( clk )

variable iadc_state: integer range 0 to 9 :I 0;

variable count, start_count: integer range 0 to 500 :I 0;
variable pause_count: integer range 0 to 60001 :I 0;
variable adc_clk_count: integer range 0 to 100 :I 0;
variable sdo_parallel: std_logic_vector(31 douano 0);
variable nux_chain: std_logic_vector(17 downto 0);
variable nux_count: integer range 0 to 127 :I 0;

variable current_address: std_logic_vector(addr dounno 0);
variable shift_count: integer range 0 to 40 :I 0;
variable nux_shift_count: integer range 0 to 20 :I 0;
variable convarsion_complete: std_logic :I ’0’;

——variable startup-count: integer range 0 to 15 := 0;
variable startup-complete: std_logic :I ’0’;
begin

if clk’event and clk I ’1’ then

—— if startup_count < 10 then

—— startup_count := startup_count + I;
.—— startup-covnplete :=- ’0’:

——- else

—— startup-cornplete :=: ’1’;

—— end if:

if adc_c1k_count ) 50 then iadc_clk (I ’1’;
else iadc-clk (I ’0’;

141

113 end if;

114

115 if adc_clk_count I 100 then adc_c1k_count :I 0;
116 else adc_c1k_count :I adc_c1k_count + 1;

117 end if;

118

119 if count > 200 then iadc_sck (I ’1’;

120 else iadc_sck (I ’0’;

121 end if;

122

123 if (nux_count ( 32 or nux_count ) 96) and iadc_state I 2 then
124 iadc_scl (I ’0’;

125 elsif start_count > 20 and iadc-state I 1 then iadc_scl (I ’0’;
126 else iadc_scl (I ’1’;

127 end if;

128

129 if pause_count ( 50000 then

130 pause_count :I pause_count + 1;

131 end if;

132

133 if count I 400 or iadc_state /I 4 then count :I 0;
134 else count :I count + 1;

135 end if;

136

137 if nux-count I 127 or iadc_state /I 2 then mux_count :I 0;
138 else nux_count :I mux_count + 1;

139 end if;

140

141 case iadc_state is

142 when 0 I) -— Idle state

143 read_control (I ’0’;

144 urite_control (I ’0’;

145 iadc_cs_bar (I ’1’;

146 shift__count :I 0;

147 nux_shift_count :I 0;

148 iadc_sda (I ’1’;

149 iadc-data_ready (I ’0’;

150 conversion_conplete :I ’0’;

151 current_address :I iadc_start_address;

152 if iadc_data_collect I ’1’ and startup_conplete I ’1’ then
153 aux_chain :I ”100100000" & address_register & "O";
154 start-count :I 0;

155 iadc_sda (I ’0’;

156 iadc_state :I 1;

157 end if;

158 when 1 I) — Multiplexer Write Start Condition
159 if start_count ) 45 then

160 start_count :I 0;

161 iadc_state :I 2;

162 else

163 start_count :- start_count + 1;

164 end if;

165 when 2 I) —— Update Multiplexer

166 if nux_shift_count ( 18 then

167 if nux_count I 1 then

168 iadc_sda (— nux_chain(17);

169 elsif nux_count I 127 then

170 nux_chain(17 downto 1) :I nux_chain(16 downto 0);
171 nux_shift-count :I nux_shift_count + 1;
172 end if;

173 else

174 iadc-sda (- ’0’;

142

175
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177

180

190

194

209

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23 1
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iadc_cs_bar <= ’0’;
iadc_state :I 3;

end if;

‘when 3 I)

if start_count > 45 then
iadc_sda (I ’1’;
start_count :I 0;
iadc_state :I 4;

else
start_count :I start_count + 1;

end if;

when 4 I) —— Shift Out ADC Data

if shift_count ( 32 then

if count I 200 then
sdo_parallel :I sdo_parallel(30 dounno O) & sdo_filtered;
elsif count I 390 then
shift-count :I shift-count + 1;

end if;

else
pause_count :I 0;
iadc_state :I 5;

end if;
when 5 I) — Conversion Waiting Period
shift-count :I 0;
if sdo_111tered I ’0’ and pause_count I 50000 then — Conv. Complete

if conversion_complete I ’0’ then
conversion_conplete :I ’1’;
iadc_state :I 4;
else -—— At least one conversion completed
address (I current-address;
nemory_data_vrite (I sdo_parallel(31 dounno 16);
vrite_control (I ’1’;
iadc_state :I 6;
end if;
end if;
udmm.6 I)
vrite_control (I ’0’;
current_address :I current_address + 1;
iadc_state :I 7;
“dun 7 I)
if mem_op_completed I ’1’ then
address (I current_address;
memory_data_write (I sdo_parallel(15 dounflo 0);
vrite_control (I ’1’;
iadc_state :I 8;
end if;
\when 8 I)
vrite-control (- ’0’;
current_address :I current_address + 1;
iadc_state :I 9;
\Nhen 9 I)
if mem_op_completed I ’1’ then
if current_address > iadc_end-address then
iadc_data_ready (I ’1’;
conversion_conplete :I ’0’;
iadc_state :I 0;
else
iadc_state :I 4;
end if;
end if;
when others I) iadc_state :2 0;
end case;

143

237

238 if startup_comp1ete I ’0’ then
239 startup_complete :I ’1’;

240 end if;

241 end if;

242 end process;

243

244 end Behavioral;

C.6 Floating-Gate Transistor Injection: injection.vhd

 

 

1

2 — Author: Paul R. Kucher

3 — Module Name: injection —- Behavioral

4 — Modified: 2007-07—29

5 — Description: Hot electron injection is accomplished by providing a large
6 —— source to drain pulse to a PMOS transistor. This module

7 — controls the pulse width that drives the external injection
8 —— circuit.

9

10 library IEEE;

11 use IEEE.STD_LOGIC_1164.ALL;

12 use IEEE.STD_LOGIC_ARITH.ALL;

13 use IEEE.STD_LOGIC_UNSIGNED.ALL;

14

15 entity injection is

16 Port(

17 clk: in std_logic; -— FPGA clock

18 inject: out std_logic; —— Injection pulse

19

20 inject-pulse: in std_logic; —— Inject pulse control bit

21 pulse-injected: out std_logic; —— Pulse operation completed flag
22 injection-pulse_vidth: in std_logic_vector(7 downto 0) —-— P/W register
23 );

24 end injection;

25

26 architecture Behavioral of injection is

27

28 begin

29

30 injection_pulse: process( clk )

31

32 variable injection-state: integer range 0 to 2 :I O;

33 variable injection_pulse_count: std-logic_vector (7 downto 0);

34 variable injection_register , injection_conpare: std_logic_vector(29 downto 0);
35

36 begin

37 if clk’event and clk I ’1’ then

38 case injection_state is — injection pulse state machine

39 when 0 I) —— idle state

40 pulse_injected (I ’0’;

41 inject (I ’0’;

42 injection_register :3 "00000000OOOOOOOOOOOOOOOOOOOOOO";

43 injection-compare :I "OO0000000000000000000000000001";

44 injection_pulse_count :I "00000001";

45 if inject_pulse I ’1’ then injection-state :I 1; end if;

46 when 1 I) — pulse width setup

47 if injection_pu1se_width ( injection_pulse_count then

48 injection_state :I 2;

144

49 else

50 injection_conpare :I injection_conpare(28 dounno 0) t
51 injection_conpare(29);

52 injection_pu18e_count :I injection_pulse_count + "00000001";
53 end if;

54 when 2 I) -— injection state

55 if injection_register < injection-conpare then

56 inject (I ’1’;

57 injection_register :I injection_register +

58 "000000000000000000000000000001";

59 else —— return to idle state

60 inject <I ’0’;

61 pu18e_injected <I ’1’;

62 injection-state :I 0;

63 end if;

64 “men others I) injection_state :- 0;

65 and case;

66 end if;

67 end process;

68

69 end Behavioral;

C.7 Memory Transfer Control: memory_block.transfer.vhd

 

—— Author: Paul R. Kucher
— Module Name: memory-block-transfer - Behavioral
— Modified: 2007-09—13
Description: This module facilitates block memory transfers and indirectly

— controls data to and from the memory by external sources.

 

library IEEE;

use IEEE.STD_LOGIC-1164.Aflla
10 use IEEE.STD-LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNEDMALL;

OQQGOIAODDH

...
he

13 entity nemory_block_transfer is
14 generic(

15 width: integer :I 16;

16 addr: integer :I 18;

17 depth: integer :8 8

18 );

19 Port(

20 clk: in std_logic; ——-FTK}1 clock

21

22 1ron_address: in std_logic_vector(addr doumno 0);.-— Start Address
23 to_address: in std_logic_vector(addr dounno 0);-— End.Address
24 read-block: in std_logic; -—- Read block flag

25 write-b10ck: in std_logic; —— lVrfie block flag

26 data_in: in std_logic_vector(15 dowwmo 0);-—— Data to unite
27 op-comp1eted: out std_logic; —- Ahmuny operation conuflete flag

28

29 txd_complete: in std_logic; ——— Serial transfer conuflete flag

30 txd_ready: out std_logic; -—- Serial data ready flag

31 para11e1_txd: out std_logic_vector(15 downto 0); -— Data for serial
32

33 read-control: out std_logic; —— Instruct inodule to read data

34 urite-control: out std_logic; -— Instruct nunhde to unite data

35 mem_op_completed: in std_logic; —— FVag if numuny operation conufleted

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);

address: out std_logic_vector(addr downto 0); ~— R/W Address
nenory_data_vrite: out std_logic-vector(vidth-1 dounno O); -— lVrue Ihna
nenory_data_read: in std-logic_vector(vidth-1 dounno 0)-—— Read Dan:

end nenory-block_transter;

architecture Behavioral of memory_block_transfer is

begin

memory_block: process( clk )

variable read_block_state: integer range 0 to 7 :I 0;
variable write_block_state: integer range 0 to 3 :I 0;
variable current-address: std_logic_vector(addr downto 0);

begin

if clk’event and clk I ’1’ then

if read_block_state I 0 and urite_block_state I 0 then
op_conpleted <I ’0’;
read-control (I ’0’;
erite-contr01 (I ’0’;
txd_ready <I ’0’;

end if;
case read_block_state is —- [Hock Read State Ahuhdne
‘dmm 0 I)

if read_block I ’1’ then
current_address :I fron_address;
read_block_state :I 1;
end if;
inhen 1 I)
if to_addresa < current_address then
op_conp1eted <I ’1’;
read_block_state :I 0;
else
address <I current_address;
read_control <I ’1’;
read_block-state :I 2;
end if;
‘when 2 I)
read_control (I ’0’;
read-block_state :I 3;

‘when 3 I)
if mem_op_completed I ’1’ then
read-block-state := 4;
end if;
vdmm 4 I)

parallel_txd <I memory_data_read;
txd_ready (I ’1’;
read_block_state :I 5;
vflux15 I>
txd-ready (I ’0’;
read-block_state :I 6;
‘when 6 I)
if txd_complete I ’1’ then
current_address :I cnrrent_address + "0000000000000000001";
read_block_state :I 1;
end if;
when others I) read_block_state :I 0;
end case;

146

98

99 case vrite_block_state is —— Block Write State Machine
100 when 0 ->

101 if write_block I ’1’ then

102 current_address :I fron_address;

103 write_block_state :I 1;

104 end if;

105 when 1 ->

106 if to_address < current_address then

107 txd_ready <I ’1’;

108 op_comp1eted (I ’1’;

109 write_block-state :I O;

110 else

111 nenory_data_erite <I data_in;

112 address <I current_address;

113 erite-control (I ’1’;

114 para11e1-txd <I data_in;

115 erite_block_state :I 2;

116 end if;

117 when 2 I)

118 write_contr01 <I ’0’;

119 if mem_op_completed I ’1’ then erite,block_state :I 3; end if;
120 when 3 I>

121 current_address :I current_address + "0000000000000000001";
122 vrite_block_state :I 1;

123 when others I) erite-block_state :I 0;

124 end case;

125 end if;

126 end process;

127

128 end Behavioral;

C.8 Memory Controller: memory.io.vhd

 

 

1

2 —— Author: Paul R. Kucher

3 —— Module Name: memory-io — Behavioral

4 — Modified .' 2007—09—13

5 — Description: This module is responsible for controlling the FPGA development
6 —- board’s SRAM chips. This module controls both. chips by adding
7 —— a 19th address bit to select each 10.

8

9 library IEEE;

10 use IEEE.STD_LOGIC_1164.ALL;

11 use IEEE.STD_LOGIC_ARITH.ALL;

12 use IEEE.STD_LOGIC_UNSIGNED.ALL;

13

14 entity memory-io is
15 generic(

16 width: integer :I 16;

17 addr: integer :I 18;

18 depth: integer :8 8

19 )3

20 Port(

21 clk: in std_logic; —— FPGA clock

22 cal: out std_logic; —— Chip enable #1

23 ub1: out std_logic; —— Upper byte enable #1
24 11:1: out std_logic; -— Lower byte enable #1
25 ce2: out std_logic; —— Chip enable #2

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ub2: out std_logic; -—- Upper byte enable #2
Ib2: out std_logic; —— Loner byte enable #2
06: out std_logic; —— (MHput enable
we: out std_logic; -—- White enable
men-address: out std_logic_vector(addr-1 downto 0); —— Addr. Bus
nen_data1: inout std-logic_vector(width-1 dowuno 0);-—— Data Bus 1
mem_data2: inout std_logic_vector(width-1 downno 0); —- Lhna Bus 2
read_control: in std_logic; —— Instruct nuuhde to read data
erite_control: in std_logic; —— Instruct nunhde to unite data
mem_op_completed: out std_logic; -— FVag if nwnuny operation connfleted
address: in std_logic,vector(addr downto 0); —- Addr. to R/W
nenory-data_write: in std_logic_vector(width-1 downno O); —— lVrue LNMa
nenory_data_read: out std_logic_vector(width-1 downno 0)-I— Read Data
):
end nenory_io;

architecture Behavioral of nemory_io is

begin

—- 7VHs process controls uflnnher the address is‘fixnn the read
—— or unite operation and sets the address bus accordingly.

-- It also sets the control signals from the memory and moves
— data from the internal registers to the external memory and
—— vice versa.

nenory_data: process( clk )

variable nenory_state: integer range 0 to 3 :I 0;
variable enable_nen1, enable-nen2: std_logic;

begin
if clk’event and clk I ’1’ then
case nenory_state is
wdmm 0 I>

if read_control I ’1’ then
mem_address (I address( addr-1 dounno 0 );
we <I ’1’;
0e (I ’0’;
enable-nen1 :I address(addr);
enable-nen2 :I not address(addr);
nenory_state :I 1;

elsif write_control I ’1’ then
mem_address <I address( addr-i dounno 0 );
we <I ’0’;
ca <I ’1’;
enable_nen1 :I address(addr);
enab1e_nen2 :I not address(addr);
nemory_state :I 2;

else
nemory_state :I O;
mem_datai <I (mem_data1’range I) ’2’);
mem_data2 <I (mem_data2’range I) ’Z’);
nen-address <I "000000000000000000";
oe <I ’1’;
we <I ’1’;
enable_nen1 := ’1’;
enab1e_nen2 :I ’1’;

end if;
nen-0p_conp1eted <I ’0’;
when 1 I) — read state

if address(addr) I ’0’ then

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menory_data_read <I mem_datal;
else
nenory_data_read <I mem_data2;
end if;
nem-op-conpleted (I ’1’;
nenory_state :I 0;
when 2 I) —— write state
if address(addr) I ’0’ then
mem_data1 <I nemery_data_write;
else
nen_data2 <I nemory_data_write;
end if;
nen-op-conpleted <I ’1’;
nenory-state :I 0;
*when others I) nenory_state :I 0;
end case;

cei (I enable_nen1;
ubi <I enable-men1;
lb1 <I enable-nen1;

ce2 <I enable-nen2;
ub2 <I enab1e_nen2;
Ib2 <I enab1e_nen2;
end if;
end process;

end Behavioral;

0.9 Memory Multiplexer: memory_mux.vhd

OOQOiOIAUNI-I

NNNNNNNNNIIHHHu-IHHHHH
DNQMfiwNHOOQQOfiU‘O-UNHO

 

— Author: Paul R. Kucher

—— Module Name: memorymmr — Behavioral

—- Modified: 2007-09—13

— Description: This module multiplexes the input signals to the memory-io

— module. This is necessary since multiple modules need
—— access to the memory buses. This module is controlled via
—— the instruction executuni controUer.

 

library IEEE;

use IEEE.STD_LOGIC_1164LALL;

use IEEE.STD_LUGIC_ARITHMALL;
use IEEE.STD_L0GIC-UNSIGNEDMALL;

entity nemery_mux is

generic (
width: integer :I 16;
addr: integer :- 18;
depth: integer := 8

);

Port(
nodule-se1ect: in integer range 0 to 5;-—— Select
read-control_in: in std_logic_vector(4 dounflo 0); -— Read IVag
write_control_in: in std_logic_vector(4 downno 0); —— lVrfle Flag
address-in: in std_logic_vector(((addr+1)I5-1) domaflo O);

nenory_data_write_in: in std_logic_vector((width*5)-1 dovnno O);

149

29 read_control_out: out std_logic; —— Read Flag

30 write_control-out: out std_logic; —— Write Flag

31 address_out: out std_logic_vector(addr downto 0); —— Address
32 memory_data_write-out: out std_logic_vector(vidth-1 downto O) —— Data
33 );

34 end nemory_mux;

35

36 architecture Behavioral of memory_mux is

37

38 begin

39

4o multiplexer: process( module_select , read_control-in, write-control-in,

41 address_in, nemory_data_urite_in )

42

43 begin

44

45 case module_select is

46 when 1 ->

47 read-control_out <- read-control-1n(0);

48 write_control_out <- write_control-in(0);

49 address-out <- address_in(addr downto 0);

50 menory-data_write_out <- nemory_data-vr1te_in(width-1 downto 0);

51 when 2 ->

52 read_control_out <- read_control_1n(1);

53 write_control_out <- urite_control_in(1);

54 address_out <- address_in(((addr+1)*2)-1 downto addr+1);

55 neuory_data_vrite_out <- memory-data_write_in(widtht2-1 downto width);
56 when 3 ->

57 read_control_out <- read_control_1n(2);

58 write-control_out <- write_control_in(2);

59 address-out <- address-in(((addr+1)#3)-1 downto (addr+1)*2);

60 neuory_data-vrite_out <- nelory_data_urite_in(vidtht3-1 downto widtht2);
61 when 4 ->

62 read_control_out <- read_control_in(3);

63 write-control_out <- write_control_in(3);

64 address_out <- address_in(((addr+1)*4)'1 downto (addr+1)*3);

65 memory-data_write-out <. nemery_data_vrite_in(widtht4-1 downto widtht3);
66 when 5 ->

67 read_control-out <- read_control_in(4);

68 write_control_out <- write_control_in(4);

69 address-out <= address_in(((addr+1)*5)-1 downto (addr+1)t4);

7o memory_data_write-out <- memory-data_write_in(vidthts-l downto widthfll);
71 when others ->

72 read_control_out <- ’0’;

73 urite-control_out <= ’0’;

74 address_out <- "0000000000000000000";

75 nemory_data_vrite_out <-I "0000000000000000";

76 end case;

77

78 end process;

79

80 end Behavioral;

C.10 Voltage DAC Controller: program_dacs.vhd

 

1

2 — Author: Paul R. Kucher

3 — Module Name: program_dacs — Behavioral
4 — Modified: 2007—09—13

150

OGQQO'

— Description: Update one LTC2600 I6—bit digital-to—analog converter
—— on the inothcrboard using the provided [WUT instruction.

 

library IEEE;

use IEEE.STD_LOGIC_1164aALL;

use IEEE.STD_LOGIC_ARITHaALL;
use IEEE.STD_LOGIC_UNSIGNEDMALL;

entity program_dacs is

Port(
clk: in std_logic; —— FPGA clock
clr_bar: out std_logic; —— CmfiLRAR DAC’pin
cs_bar: out std_logic; ——- CS_BAR DAC pin
sdi: out std_logic; ___ Serial Data In DHC'pin
sck: out std_logic; —— Serial CHock.DAC pfil
program_dac: in std_logic; -- Program DAC control flag
dac_programmed: out std_logic; —- Fhognnnnnng conufleted control flag
dac-instruction: in std_logic_vector(27 donnno 0) —— DACYinstruction
);

end program_dacs;
architecture Behavioral of program_dacs is
begin

program_dacs: process( clk )

variable count: integer range 0 to 15 z- 0;

variable program_state: std_logic_vector(1 doumno 0) :- "00”;
variable dac_nun: std_logic_vector (3 downto 0);

variable dac_chain: std_logic_vector(159 downto 0);

variable shift-count: integer range 0 to 180 :- O;

begin

clr-bar <- ’1’;
if ( clk’event AND elk-’1’ ) then

if count > 0 then sck <- ’1’;
else sck <3 ’0’;
end if;

case program_state is

vdmm "00” a)

if program_dac - ’1’ then
program_state :- "01”;

end if;
cs_bar <- ’1’;
dac_programmed <= ’0’;

when "01" ->
dac_num :- dac_instruction(27 dounno 24);
program_state := "10";

when "10" ->
dac_chain :-
"00000000111100000000000000000000"
"00000000111100000000000000000000"
"00000000111100000000000000000000"
'00000000111100000000000000000000"
"00000000111100000000000000000000";
if dac-nun = "0001" then

dac_chain(23 dounno 0) :- dac_instruction(23 dounno 0);

elsif dac_nun - ”0010" then

"RR"

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dac_chain(55 dounno 32) :- dac-instruction(23 dounno O);
elsif dac_num - "0011" then

dac-chain (87 downto 64) :- dac_instruction(23 downto 0);
elsif dac_num - "0100" then

dac_chain(119 dounflo 96) :- dac_inatruction(23 dounno 0);
elsif dac-nun - "0101" then

dac_chain(151 dounno 128) :- dac-instruction(23 dounno 0);

end if;

program_state :- "11';
*when ”11“ ->

if shift-count < 160 then
dac_chain(159);

sdi <-

cs_bar
else

sdi <-

cs_bar

(-

’0
(-

’0’;

,0
8

’1’;

dac_programmed <- ’1’;
shift_count :- 0;
progran-state :- "00";

end if;

if count I 1 then
shift_count :- ah11t_count + 1;
dac_chain(159 downto 1) :- dac_chain(158 downto 0);

end if;

*when others -> program_state :- "00";

end case;

if count - 1 or program_state /= "11“ then count :- 0;
else count :- count + 1;

end if;

end if;
end process;

end Behavioral;

C.11 RS—232 Serial Controller: serial-io.vhd

QWNIGUIAWUH

NHHO—IHHHHHHH
ommdomeuuiwo

 

Author:
Module Name:
Alodified:
ZDescription:

Paul R. Kucher

serial-io —- Behavioral

2007—08—06

This module is responsible for controlling the serial
connnunicafions between the FWCM and the.PC. It generates
the appropriate baud rate and handles turning zoarallel into
serial data for transmission and serial into parallel data
for receiving. This module is currently configured for

a 115200 bps baud rate. but num be adjusted by changing the
counters in the baud clock generators.

 

library IEEE;
use IEEE.STD_LOGIC_1164MALL;
use IEEE.STD_LOGIC_ARITHLALL;
use IEEE.STD_LUGIC_UNSIGNEDLALL;

entity serial_io
Port(

clk:

is

in std_logic; - FPGA clock

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rxd: in std_logic; —— Physical receiver pin

txd: out std_logic; -— Physical transmitter pin

txd_ready: in std_logic; — Data ready on parallel-t:cd to send
txd_complete: out std_logic; —— Transmitted word control flag
rxd_complete: out std_logic; —— Received word control flag
paralle1_txd: in std_logic_vector(1$ downto 0); — Transmit register
parallel_rxd: out std_logic_vector(15 downto 0) —— Received register
);

end serial-io;
architecture Behavioral of serial_io is

signal baud_sanple: std_logic;

signal rxd-state: std_logic_vector(4 downto 0) :I "00000";
signal txd_state: std_logic_vector(4 downto 0) :I "00100";
signal rxd_filtered, txd-tenp: std_logic :I ’1’;

signal rxd-sync: std_logic,vector(1 downto 0) :I "11";
signal get_next_,bit: std_logic :I ’0’;

begin

— This process divides the global clock down to the baud
—— rate for use in the RS232 serial communications.
— 115200 bps (specifically 115207.373 bps) is the current baud rate.
haud-rate_set: process( clk )
variable count: integer range 0 to 500 :I 0;
begin

if clk’event and clk I ’1’ then

count :I count + 1;

if count > 434 then count :I 0;
end if;

if count I 1 then baud_samp1e <- ’1’;
else baud_sanple (I ’0’;
end if;
end if;
end process;

—- This process is what controls 128232 communications with Matlab. It will
— read 16 bit data from the paralleLtrd signal and sends it to Matlab
—— in two chunks of 8 bits each. 115200 band is used as well as mark parity
— and 2 stop bits.
txd_state_nachine: process( clk )
begun
if clk’event and c1]: I ’1’ then
case txd_state is
when ”00100" I> if txd-ready I ’1’ then
txd-state <I "00000"; end if; —-— idle state
when "00000” I) if baud_sanple I ’1’ then
txd-state <I "01000"; end if; — send start bit
when “01000" I) if baud_sample I ’1’ then
txd_state <- "01001"; end if; —— bit 0
when "01001” I) if baud_sanple = ’1’ then
txd_state <I "01010"; end if; — bit I
when ”01010" I) if baud_sample I ’1’ then
txd_state (I "01011"; end if; — bit 2
when "01011" I> if baud-sample I ’1’ then
txd_state <I "01100"; end if; —- bit 3
when "01100" I> if baud_sanple I ’1’ then
txd_state <= "01101"; end if; — hit 4

153

83 when "01101" I) if baud_sample I ’1’ then

84 txd_state (- "01110"; end if; — bit 5

85 when "01110" I) if baud_sample I ’1’ then

86 txd_state (I ”01111"; end if; —- bit 6

87 when ”01111" I) if haud_sanp1e I ’1’ then

88 txd_state <I “00001”; end if; -— bit 7

89 when "00001“ I) if baud_sanple I ’1’ then

90 txd-state <I "00010"; end if; —-— parity bit
91 when "00010” I) if baud_sanple I ’1’ then

92 txd_state (I ”00011"; end if; — stop bit #1
93 when ”00011" I) if baud_samp1e I ’1’ then

94 txd_state (I ”10000"; end if; —— stop bit #2
95 when "10000" I) if baud_sample I ’1’ then

96 txd_state <I "11000"; end if; —— send 2nd start bit
97 when ”11000” I) if baud-sample I ’1’ then

98 txd_state (I ”11001"; end if; — bit 8

99 when "11001" I> if baud_samp1e I ’1’ then

100 txd_state (I ”11010"; end if; — bit 9

101 when "11010" I) if baud_sanple I ’1’ then

102 txd-state <I "11011'; end if; — bit 10

103 when "11011" I) if baud_sanple I ’1’ then

104 txd_state (I "11100"; end if; — bit 11

105 when "11100” I) if baud_sanple I ’1’ then

106 txd_state (I "11101"; end if; — bit 12

107 when "11101" I) if baud_sample I ’1’ then

108 txd_state (I "11110"; end if; — bit 13

109 when ”11110” I) if baud_sanple I ’1’ then

110 txd-state (I "11111"; and if; — bit 14

111 when ”11111" I) if baud_sanple I ’1’ then

112 txd-state (I "10001“; end if; — bit 15

113 when "10001" I) if baud_sanple I ’1’ then

114 txd_state (I “10010”; end if; — parity bit
115 when "10010" I) if baud_sanple I ’1’ then

116 txd_state (I "10011"; end if; —— stop bit #1
117 when "10011” I) if baud-sanple I ’1’ then

118 txd_state <I "00100"; end if; — stop bit #2
119 when others -) txd_state <- "00100";

120 end case;

121 end if;

122 end process;

123

124 — This process handles the parallel to serial conversion of the data in the
125 —— input register named ’parallel-t:rd ’.

126 txd_shift: process( clk )
127 variable parallel_data : std_logic_vector(15 downto 0) :I "0000000000000000";

128 begin

129 if clk’event and clk I ’1’ then

130 if baud-sample I ’1’ then

131 if txd_atate (3 downto 0) I "0000" then

132 txd_temp <I ’0’; — start bit

133 if txd_state (4) I ’0’ then —— load data

134 parallel_data :I parallel_txd;

135 end if;

136 elsif txd_state (3) I ’1’ then —— send data bits
137 txd_temp <I parallel_data(0);

138 parallel_data(14 downto 0) :I parallel_data(15 downto 1);
139 else

140 txd_temp (I ’1’; —— idle is always high

141 end if;

142

143 if txd-state = ”10011" then

144 txd_complete <I ’1’; —— send ack. bit

154

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200

end if;
else
txd_complete (I ’0’;
end if;
end if;
end process;

txd <- txd_tenp;

-—— Synchronize the receiver pin unth the FPGfi clock.
rxd_sync_input: process( clk )
begin
if clk’ovent and clk I ’1’ then
rxd-sync <I rxd_sync(0) & rxd;
end if;
end process;

—- FWlter the inconnng data for any glitches.

rxd_tilter_input: process( clk )

variable count: integer range 0 to 60 :I 60;

begin

if clk’event and clk I ’1’ then

if rxd_sync(1) I ’1’ and count < 50 then count :I count + 1;
elsif rxd_sync(1) I ’0’ and count > 0 then count :I count - 1;
end if;

if count I 50 then rxd_filtered (I ’1’;
elslf count I 0 then rxd-filterod (I ’0’;
end if;
end if;
end process;

—- Baud rate generator for receiving.
rxd-next-bit: process( clk )
variable count: integer range 0 to 1000 :I 0;
begin
if clk’event and clk I ’1’ then
if rxd-state(3 downno 0) I "0000" then
if rxd_filtered I ’0’ then count :I count + 1;
else count :I 0;
end if;

if count I 200 then
get-next_bit <= ’1’;
count :I 0;
else
get_next-bit <I ’0’;
end if;
elsif count I 434 then
get_next-b1t (I ’1’;
count :I 0;
else
get_next_bit <= ’0’;
count :I count + 1;
end if;
end if;
end process;

——- This process 1nanages the inconnng connnand structure to the $7131
-— over RS232 conununicauons.

rs232_receive_sm: process( clk )

begin

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23 l
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24 2
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if clk’evont and clk I ’1’ then
case rxd_state is

when ”00000" I> if get_next_bit
rxd_stato <I "01000”; end if;
‘when "01000" I> if get_next_bit
rxd_state <I "01001"; end if;
'when ”01001" I> if get_next_bit
rxd-state <I "01010"; end if;
when “01010" I> if get-next-b1t
rxd_state <I "01011"; end if;
when "01011" -> if get_next_b1t
rxd_stato <I "01100“; and if;
‘when "01100" I) if get_noxt_bit
rxd-state <I ”01101”; end if;
when "01101” I) if get_next_bit
rxd_state <I "01110”; end if;
when "01110” I> if get_noxt_b1t
rxd-stato <I "01111"; end if;
when "01111" I) if get_next_bit
rxd_state (I "00001"; end if;
when "00001" I) if get-next_bit
rxd_state <I "10000"; end if;
‘when "10000” I) if get_next_bit
rxd_state (I ”11000"; end if;
when "11000" I) if get_next_bit
rxd-state <I "11001"; end if;
vflxni"11001' I> if get-next_bit
rxd_state <I "11010"; end if;
‘when "11010" I> if got-next_b1t
rxd_stato (I "11011"; end if;
when "11011" I> if gst_next_b:i.t
rxd-stato <I "11100"; end if;
‘when ”11100" I> if get-ncxt_bit
rxd_state <I ”11101"; end if;

I ’1’ then
—— start bit found?
I ’1’ then
—— bit 0

I ’1’ then
—— bit 1

I ’1’ then
—— bit 2

I ’1’ then
—— bit 3

I ’1’ then
—— bit 4

I ’1’ then
—— bit 5

I ’1’ then
—— bit 6

I ’1’ then
—— bit 7

I ’1’ then
—— stop bit
I ’1’ then
—— 2nd start bit found?
I ’1’ then
—— bit 8

I ’1’ then
—— bit 9

I ’1’ then
—— bit 10
I ’1’ then
—- bit 11
I ’1’ then
——- bit 12

when ”11101” I) if get_next_b1t I ’1’ then

rxd_stato <I "11110"; end if; —— bit 13
when "11110" I) if get_next_bit I ’1’ then
rxd_state <I "11111”; end if; —— bit 14
when "11111" I> if get_next_bit I ’1’ then
rxd-state (I "10001"; end if; —— bit 15
“dun "10001" I) if get-next_bit I ’1’ then
rxd_state (I ”00000"; end if; —— stop bit
‘when others I) rxd_state (I "00000";
end case;
end if;

end process;

- This process shifts in the [ti-bit instruction / data from the PC and makes
-— it available on the signal
r8232_shitt-in: process( clk )
variable packet1 , packet2 std_logic_vector(7 downto 0);
begin
if clk’event and clk I ’1’ then
if get_next-bit I ’1’ and rxd_state(3) I ’1’ then
if rxd_stato(4) I ’0’ then —— shift data
packet1 :I rxd_filtered & packet1(7 dounno 1);
elsif rxd-state(4) I ’1’ then —— shift data
packet2 :I rxd_filtered & packet2(7 donnno 1);
end if;
end if;

'parallel-r$d ’ when ’rzd-complete ' is high.

if rxd_state I "10001" and get_next_bit I ’1’ then

156

269 parallel_rxd <= packet2 & packetl;

27o rxd_complete (I ’1’;
271 else

272 rxd-comp1ete (I ’0’;
273 end if;

274 end if;

275 end process;

276

277 end Behavioral;

C.12 Serial I/O Multiplexer: serial_mux.vhd

 

 

1

2 —— Author: Paul R. Kucher

3 — Module Name: serial_mur - Behavioral

4 — Modified: 2007—09-13

5 -— Description: This module multiplexes the input signals to the serial_io
6 — module to allow direct communications back to the PC without
7 — having to pass data through the instruction decode and execute
8 -— unit.

9

10 library IEEE;

11 use IEEE.STD_LOGIC_1164.ALL;

12 use IEEE.STD_LOGIC_ARITH.AIL;

13 use IEEE.STD_LOGIC_UNSIGNED.ALL;

14

15 entity serial_mux is

16 Port(

17 nodule_select: in integer range 0 to 2; —- Select Line

18 txd_ready_in: in std_logic_vector(2 downto 1); —— TXD Flag In
19 parallel-txd_in: in std_logic_vector(32 downto 1); —- 7X0 Reg. In
20

21 txd-ready-out: out std_logic; — TXD Flag Out

22 parallel_txd_out: out std_logic_vector(16 downto 1) — TXD Reg. Out
23 )3

24 end serial_nux;

25

26 architecture Behavioral of serial_nux is

27

28 begin

29

30 multiplexer: process( module_select , txd_ready_in, parallel_txd-in )

31

32 begin

33

34 case nodule_select is

35 when 1 I)

36 txd_ready_out (I txd_ready_in(1);

37 para11e1_txd_out <I para11e1_txd_in(16 downto 1);

38 when 2 ->

39 txd_ready_out <I txd_ready-in(2);

4o parallel-txd_out <- para11e1_txd_in(32 downto 17);

41 when others I)

42 txd_ready_out <I ’0’;

43 parallel_txd_out (I ”OOOOOOOOOOOOOOOO";

44 end case;

45

46 end process;

47

157

48

end Behavioral;

0.13 Serial Shifting Controller: serial_shifter.vhd

004010135919.—

mummmuaaenobeeeewwwwwwwwwwunnwwnnnnni-wui—p—Hui-.—
O!lb“NHOQOQQCF‘WDHOOa)flGO‘hWND-‘OVOOQGmfiuuflowmflfimfiwND-‘O

 

— Author: Paul R. Kucher

— Module Name: serial_shifter - Behavioral

—— Modified: 2007—09—05

— Description: This unit enables and disables the states of a generic serial

—— shift register. The starting and stopping addresses specify
— where in memory the serial shifting states are stored and
—— this module will then read the least significant bit

— from sequential memory locations and output them on the

— ’serial-out ’ line.

 

library IEEE;

use IEEE.STD_LOGIC_1164MALL;

use IEEB.STD_LOGIC_ARITHuALL;
use IEEE.STD_LOGIC_UNSIGNEDMALL;

entity serial_shifter is

generic(
width: integer :I 16;
addr: integer :3 18;
depth: integer :I 8

)3

Port(
clk: in std_logic; —— FPGA Clock (Pin T9)
serial_clk: out std-logic; ——- Serial Clock (FPGA Pin A9)
serial-in: out std_logic; —— Serial Data To Chip (FPGA Pin 86)
serial_out: in std-logic; — Serial Data From Chip (FPGA Pin D5)
shift_start_flag: in std_logic; —-— Shifting operation begin flag
shift_ond-11ag: out std_logic; — Shifting operation complete flag
start_address: in std_logic_vector(addr downto 0); —— St. Address
end_address: in std_logic_vector(addr downto 0); —— Ending Address
read_control: out std_logic; — Instruct module to read data
write-control: out std_10gic; —— Instruct module to write data
lem_op_comploted: in std_logic; — Flag if memory operation completed
address: out std_logic_vector(addr downto 0); -— Address to It/W
memory_data_vrite: out std_logic_vector(vidth-1 downto 0); —— Write Data
nonory_data_read: in std_logic —- Read Data

):

end serial_shifter;

architecture Behavioral of serial_shifter is
begin

serial_shift: process( clk )

variable shift_state: integer range 0 to 7 :I 0;
variable read_next: std_logic :-- ’0’;

variable startup_conplete: std_logic :8 ’0’;
variable shift_out_period: integer range 0 to 200;

variable current_address , ce11_count: std_logic_vector(addr downto 0);

begin

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112
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1 14
115
116
117

if clk’event and clk I ’1’ then

case shitt_state is
\Nhen 0 I>
shi£t_end_flag (I ’0’;
serial_in <I ’0’;
read_control (I ’0’;
urite-control <I ’0’;
nemory_data_vrite <I "1111111111111111";
address <I '0000000000000000000”;
if shitt_start_flag I ’1’ then
current_address :I end_address;
call-count :I end_address - start_address + 1;
shift-state :I 1;
end if;
“dam 1 I)
if current_address < start-address then
shift_end_flag (I ’1’;
shitt_stato :I 0;
elsif read_next I ’1’ then
address <I current_address;
read_control (I ’1’;
shi£t_state :I 2;
end if;
‘when 2 I)
read_control <I ’0’;
shift_state :I 3;
‘when 3 I>
if mem_op_completed I ’1’ then
shift_stato :I 4;
end if;
‘when 4 I> —— Read serial data back for verification
serial_in <I nenory_data_read;
address <I current_address + cell_count;
nonory_data_vrito <I “000000000000000' & serial_out;
vrite-control <I ’1’;
shift_state :I 5;
“dun 6 I)
vrite_control <= ’0’;
shift_state :I 6;

\Nhen 6 I)
if nem-op_completed I ’1’ then
current_address :I current_address - 1;
shift_stato :I 7;
end if;
inhen 7 I>

if shift_out_period I 0 then
shitt_state :I 1;
end if;
when others I) shift_state :I 0;
end case;

if shift_out_period I 50 then read_next :I ’1’;
else read_next :I ’0’;
end if;

if shift_out_period > 199 or shift_state I 0 then shift_out_period

else shift_out_period :I shift_out_period + 1;
end if;

if shift_out_period > 100 then serial_clk (I ’0’;
else serial_clk <I ’1’;

159

:I 0;

118
119
120

121 ‘

122

end if;
end if;
end process;

end Behavioral ;

C.14 Seven Segment Display: seven_segment.vhd

@OQGOI#OONH

Ola-bases5.5-hAassume:wwuguwwwgngnnuwwuNHHHHHHi—HHH
Hocmqamnwu—owmaau what—o m mméuuwocmqocnbwuwo

 

— Author: Paul R. Kucher

—— Module Name: seven-segment — Behavioral

— Modified: 2007—08-06

— Description: This module controls the seven segment display on the FPGA

-— development board.

 

library IEEE;

use IEEE.STD_LOGIC_1164MALL;

use IEEE.STD_LOGIC_ARITHMALL;
use IEEE.STD_LOGIC_UNSIGNEDMALL;

entity seven_segment is

Port(
clk: in std_logic; -— FPGA clock
dig1t_sel: out std_logic_vector(3 downto 0); — Digit selection
digit-va1: out std_logic__vector(6 downto 0); —— Digit value
1ed_data: in std_logic_vector(16 downto O) —— Data for display
)3

end seven_segment;
architecture Behavioral of seven_segment is

— LED Timing

signal 1ed_c1k: std_logic;

signal 1ed_index: integer range 1 to 4;

signal led_number: std_logic_vector(3 downto 0);

begin

— Divide the clock for the 7—segment LED display.
1ed_t1ming: process( clk )
variable count_leds: integer range 0 to 200 :I O;
begin
if ( clk’event AND elk-’1’ ) then
if count_1eds < 100 then
led_c1k (I ’0’;
else
led_c1k (I ’1’;
end if;

if count_1eds > 199 then count_1eds :I 0;
else count_1eds :8 count_1eds + 1;
end if;

end if;

end process;

—— This process selects the digit to update.

digit_se1ect: process( 1ed_index )
begin

160

52 case 1ed_index is

53 when 1 I> digit_se1 <- "1110";

54 when 2 I) digit_sel (I "1101";

55 when 3 I> digit_se1 (I "1011";

56 'when 4 I) digit_se1 <I "0111";

57 when others I) null;

58 end case;

59 end process;

60

61 — For LED display write ucf file (a,b,c.d,e.f,g for 7 segments)
62 — Map the 7—bit code of the LED display to a 4—bit code O—F
63 digit_va1ue: process( 1ed_nunber )

64 begin

65 case 1ed_nunber is

66 when "0000" I) digit_va1 <I "0000001";
67 ‘when "0001” I) digit_va1 <I “1001111";
68 ‘when "0010" I) digit_va1 <I "0010010”;
69 when ”0011” I> digit_va1 <I “0000110”;
70 when "0100" I> dig1t_va1 (I "1001100";
71 when ~0101" -> digit-va1 <- "0100100-;
72 when "0110” I> digit_va.1 <I ”0100000”;
73 'when "0111” I> dig1t_va1 (I "0001111";
74 when "1000” I) digit_va1 <- "0000000";
75 when "1001" I) digit_va1 <- "0000100";
76 Winn "1010" I) digit_va1 (I "0001000";
77 when ”1011' I) digit_val (I "1100000";
78 when "1100" I> digit-va1 <- "0110001";
79 when "1101" I) digit_val <I "1000010";
80 ‘when ”1110" I) digit_va1 <I "0110000";
81 vflnn|"1111" I> dig1t_va1 <I "0111000";
82 when others -> null;

83 end case;

34 end process;

85

so — Set the value of the selected digit.

87 set_digit: process( 1ed_c1k )
as variable count: integer range 0 to 5 :I O;

89 begin

90 if 1ed_clk’event and 1ed_c1k I ’1’ then
91 count :I count + 1;

92 if count I 5 then count :I 0;

93 end if;

94

95 case count is

96 when 1 ->

97 led_nunber <- 1ed_data(3 downto 0);
9s 1ed_index <I 1;

99 when 2 =>

100 led_number <= 1ed_data(7 downto 4);
101 led-index <- 2;

102 when 3 ->

103 1ed_number <= 1ed_data(11 downto 8);
104 1ed_index <I 3;

105 when 4 I)

106 1ed_nunber <I led_data(15 downto 12);
107 led_index <I 4;

103 when others I)

109 null;

110 end case;

111 end if;

112 end process;

113

161

114

end Behavioral;

C.15 Signal Generator: signal_gen.vhd

OGQOSUIfiwwi-fi

uumumgahhenooebawwwwwfiwwwwunnuuunwuuuuwwuu—u—ww
mawuw coonflaicnawto—‘oroanqcno‘ wwwoomqomhuuwoomqmuowuwo

 

— Author: Paul R. Kucher

—— Module Name: signal-gen — Behavioral

— Modified: 2007—09—13

— Description: This module controls high—speed digital—to—analog conversion

— for function/signal generation. It reads the values of the
—- 16—bit DACS from. memory and loads them into the 160—bit serial
--- shift chain.

 

library IEEE;

use IEEE.STD_LOGIC_1164MALL;

use IEEE.STD_LOGIC_ARITHLALL;
use IEEE.STD_LOGIC_UNSIGNEDuALL;

entity signa1_gen is

generic(
width: integer :I 16;
addr: integer :I 18;
depth: integer :I 8
);
Port(
clk: in std_logic; —— FPGA clock
cs_bar: out std_logic; — 08.8.4}? DAC pin
sdi: out std_logic; — Serial Data In DAC pin
sck: out std_logic; — Serial Clock DAC pin
sig_gen_enable: in std_logic;

sig_gen_conplete: out std_logic;

start_address: in std_logic_vector(addr downto 0); — St. Data Store
end_address: in std_logic_vector(addr downto 0); —— End Data Store
read_control: out std-logic; — Instruct module to read data
vrite_control: out std_logic; —— Instruct module to write data
mem_op_completed: in std_logic; — Flag if memory operation completed
address: out std_logic_vector(addr downto 0); — address to RM
memory_data_vrite: out std_logic_vector(vidth-1 downto 0); — Write Data
nemory_data_read: in std_logic_vector(vidth-1 downto 0) —— Read Data

)3
end signa1_gen;

architecture Behavioral of signa1_gen is
begin

generate_signa1s: process( clk )

variable count: integer range 0 to 15 :I 0;

variable program_state: integer range 0 to 5;

variable dac_chain: std_logic_vector(159 downto 0);

variable shift-count: integer range 0 to 180 :I 0;

variable current_address , true_start: std-logic_vector(addr downto 0);
variable next_sequence: std_logic_vector(addr downto 0);

begin

if ( clk’event AND clkI’l’ ) then

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117

if count > 0 then sck (I ’1’;
else sck <I ’0’;
end if;

if count I 1 or program_state /I 5 then count :I 0;
else count :I count + 1;
end if;

case program_state is
\Nhen 0 I)-—— Idle State
cs_bar <I ’1’;
sdi <- ’0’;
read_control (I ’0’;
vrite_control <I ’0’;
sig_gen_complete (I ’0’;
nemory_data_vrite <I "OOOOOOOOOOOOOOOO";
dac_chain :-
"00000000111100000000000000000000" &
'00000000111100000000000000000000” &
"00000000111100000000000000000000' &
"00000000111100000000000000000000" &
”00000000111100000000000000000000";
if sig_gen_enab1e I ’1’ then
program_state :I 1;
current-address :I start_address;
true_start :I start_address + 5;
end if;
when 1 I) — Setup Channels
if current_address < true_start then
address <I current_address;
read_control <I ’1’;
progran-state :I 2;
else
current_address :I true_start;
next-sequence :I true_start + 5;
program_state :I 3;
end if;
‘when 2 ->
read_control (I ’0’;
if mem_op_completed I ’1’ then
current-address :I current_address + 1;
dac_chain :I dac_chain(127 dounno 0) & “000000000011" &
nemory_data_read(3 dounno O) 2 ”0000000000000000";
program_state :I 1;
end if;
when 3 I) — Start Loading Data Sequence (DAC3 #1 — #5)
if current_address < next_sequence then
address <I current_address;
read_control (I ’1’;
program_state :I 4;
else
program_state :I 5;
end if;
when 4 I) -— Load Data Into Shift Chain
read_control (I ’0’;
if mem_op_completed I ’1’ then
current_address :I current_address + 1;
dac_chain :I dac_chain(127 dounflo 0) &
dac_chain(159 dounno 144) I memory_data_read;
program_state :I 3;
end if;

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when 5 I> -— Shift Out Data

if shift_count < 160 then
sdi (I dac_chain(159);
cs_bar (I ’0’;

else
sdi (I ’0’;
cs-bar (I ’1’;
shift_count :I 0;
if current_address > end_address then

current_address :I true_start;

next_sequence :I true_start + 5;
else

next_sequence := next-sequence + 5;
end if;

if sig_gen_enab1e I ’1’ then
program_state :I 3;
else
sig_gen_conplete (I ’1’;
program_state :I 0;
end if;
end if;

if count I 1 then
shift_count :I shitt_count + 1;
dac_chain :I dac_chain(158 domnno O) & dac_chain(159);
end if;
when others I> progran-state :I 0;
end case;
end if;
end process;

end Behavioral;

C.16 Voltage ADC Controller: vadc.vhd

@QQfithNv-I

”SNMHHHHHHHHHH
on HOGWQOO‘AUNHO

 

— Author: Paul R. Kucher
-— Module Name: vadc — Behavioral
—— AIodUied: 2007—08—23

— Description: This module controls the 16 channel. 224-bit Sigma Delta
— Analog—to—Digital converters used for voltage measurement.

 

library IEEE;

use IEEE.STD_LOGIC_1164MALL;

use IEEE.STD_LOGIC_ARITH“ALL;
use IEEE.STD_LOGIC_UNSIGNEDMALL;

entity vadc is

generic (
width: integer :I 16;
addr: integer :I 18;
depth: integer :I 8
) ;
Port(
clk: in std_logic; —- FTth clock
adc_c1k: out std_logic; —- (Tonversion (Hock (f0)
adc_sck: out std_logic; -—— Serial (Hock
adc_cs_bar: out std_logic;-—— Serial Transfer Enabh?

164

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adc-sdi: out std_logic; —- Serial.Data In (to ALXU

adc_sdo: in std_logic; —— Strial Data Out (ofim0C)
adc_conv_mode: in std_logic_vector(1 dounno O); —- f0 hhde
adc-address: in std_logic_vector(3 dounflo O);-w— Channel.Address
adc_start-address: in std_logic_vector(addr dounno 0); —— St. Data Store
adc_end_address: in std_logic_vector(addr donnno 0); -— End Lhna Store
adc_data_ready: out std_logic; —-— Data Conversion Complete Flag
adc_data-collect: in std_logic; —— (Sontrol flag to initiate sanufling
read_control: out std_logic; —— Instruct inoduurto read data
vrite-control: out std_logic; —- Instruct nunhde to unite data
mem_op_completed: in std_logic; -— FYag if nwmuny operation conufleted
address: out std_logic_vector(addr downno 0);-—— Address to H/H’
nemory_data_vrite: out std_logic_vector(vidth-1 doundo O) —— inue [hue
)3

end vadc;

architecture Behavioral of vadc is

begin

state_nachine: process( clk )

variable
variable
variable
variable
variable
variable
variable

variable
variable
variable
variable
begin

if clk’

vadc_state: integer range 0 to 7 :I 0;
count: integer range 0 to 50 :I 0;
pause-count: integer range 0 to 50000 : O;
adc_c1k_count: integer range 0 to 350 :I 0;
adc_clk-period: integer range 0 to 350 :I 24;
adc_c1k-high: integer range 0 to 165 :I 12;

adc_chain, sdo_parallel: std_10gic_vector(31 dounno 0)
:I "01001111111111111111111111111111";
current_address: std_logic-vector(addr dounflo O);
shift_count: integer range 0 to 40 :I O;
conversion_conplete: std_logic :I ’0’;
startup-conp1ete: std_logic :I ’0’;

event and clk I ’1’ then

if adc_clk_count > adc_clk_high then adc-c1k (I ’1’;

else

adc_c1k (I ’0’;

end if;

if adc-clk-count I adc-clk_period then adc_clk_count :- 0;

else

adc_clk_count :I adc_clk_count + 1;

end if;

if count > 12 and vadc_state I 1 then adc_sck (I ’1’;

else

adc_sck <= ’0’;

end if;

if pause_count < 50000 then
pause_count :I pause_count + 1;

end if;

if count I 25 or vadc_state /= 1 then count :I 0;

else

count :I count + 1;

end if;

0888

vadc_state is

when 0 I> —— Idle State
read_control <- ’0’;
vrite_control <- ’0’;

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adc_cs_bar <I ’0’;
adc_sdi (I ’0’;
shift_count :I 0;
adc_data_ready (I ’0’;
conversion_conp1ete :I ’0’;
current_address :I adc_start_address;
if adc_data_collect I ’1’ and startup-conp1ete I ’1’ then
adc_chain :I "1011" & adc_address(0) t adc_address(3 dounno 1) &
”000000000000000000000000”;
if adc_conv_node I '00" then —— 153600 H2 f0 w/60Ut freq. rej.
adc_clk_high :I 162;
adc_c1k_period :I 325;
elsif adc_conv_node I ”01' then —— 2 Aflh f0
adc_c1k_high :I 12;
adc_c1k_period :I 24;
elsif adc_conv_node I "10" then —— I hflh f0
adc_c1k_high :I 25;
adc_clk_period :I 49;
else —— 400 kHz f0
adc_c1k_high :I 75;
adc-c1k_period :I 124;
end if;
vadc_state :I 1;
——adc-cs-bar«<= ’0’:
end if;
when 1 I) —- Shift In/Out State
if shift_count < 32 then
if count I 1 then
adc_sdi (- adc_chain(31);
elsif count I 14 then
sdo_parallel :I sdo-parallel(30 dounno O) & adc_sdo;
elsif count I 25 then
adc_chain (31 downto 1) :I adc-chain (30 downto O);
shift_count :I shift_count + 1;
end if;
else
pause_count :I 0;
vadc_state :I 2;

end if;
when 2 I) — Conversion Waiting Period
shift_count :I 0;
if adc_sdo I ’0’ and pause_count > 49999 then —— (Souversnni Cbnqflete

adc_chain :I “1011” & adc_address(0) t adc_address(3 dounno 1) &
"000000000000000000000000";
if conversion_conplete I ’0’ then
conversion_conplete :I ’1’;
vadc_state :I 1;
else —- At least one conversion completed
address (I current_address;
nemory_data_vrite <I sdo_parallel(31 dounno 16);
vrite_control (I ’1’;
vadc_state :I 3;
end if;
end if;
*when 3 I)
vrite_control <- ’0’;
current_address :I current_address + 1;
vadc_state :I 4;
\vhen 4 I)
if mem_0p_completed I ’1’ then
address (I current_address;
nemory_data_vrite (- sdo_parallel(15 dounno 0);

166

148 write_control (=- ’1’,

149 vadc_state := 5;

150 end if;

151 when 5 ->

152 write_control (I ’0’;

153 current_address :I current_address + 1;
154 vadc_state :-I 6;

155 when 6 ->

156 if mem_op_completed I ’1’ then
157 if current_address > adc_end_address then
158 adc_data_ready (I ’1’;

159 conversion-conplete :I ’0’;
160 vadc_state :I 0;

161 else

162 vadc_state :I 1;

163 end if;

164 end if;

165 when others I) vadc_state :I 0;
166 end case;

167

168 if startup_complete I ’0’ then

169 startup_comp1ete :I ’1’;

170 end if;

171 end if;

172 end process;

173

174 end Behavioral;

C.17 Voltage DAC Multiplexer:

vdac_mux.vhd

 

 

l

2 — Author: Paul R. Kucher

3 — Module Name: vdaCJnua: — Behavioral

4 — Modified: 2007—07—15

5 —— Description: This module multiplexes the output signals to the serial
6 — interface to the LT02600 voltage digital—to—analog converters.
7 —— Two separate modules control the DACS. An all—channel bias
8 — controller and a high—speed signal generation module.

9

10 library IEEE;

11 use IEEE.STD_LOGIC_1164.ALL;

12 use IEEE.STD_LOGIC_ARITH.ALL;

13 use IEEE.STD_LOGIC_UNSIGNED.ALL;

14

15 entity vdac_nux is

16 Port(

17 module-select: in integer range 0 to 2;

18

19 sck_in: in std_logic_vector(2 downto 1);

20 sd1_in: in std_logic_vector(2 downto 1);

21 cs-bar_in: in std_logic_vector(2 downto 1);

22

23 sck_out: out std_logic;

24 sdi_out: out std_logic;

25 cs_bar-out: out std_logic

26 );

27 end vdac_mux;

28

29 architecture Behavioral of vdac_mux is

167

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C.18

OOQGUhWNi-I

wwNESNMNNNNNHI-Hwt—HHHHH
H060) amnwwr—oomqmo‘awnwo

begin

multiplexer:

begin

case nodu1e_select is

*when 1 I) ——
sck_out
sd1_out

cs_bar_out

‘when 2 I> ——
sck_out
sd1_out
cs_bar-out (I

Bias

process( module_select,

ControHer
(I sck_in(1);
(I sdi_in(1);

sck_in, sdi_in, cs_bar-in )

(I cs_bar_in(1);
Signal Generation

(I sck-in(2);
sdi_in(2);
cs-bar_1n(2);

(-

when others I)

sck_out
adi_out
cs_bar-out (I

end case;

end process;

end Behavioral;

<-
(:-

’0’;
’0’;
’1’;

Top Module: top.vhd

 

.Author:

Module Name:
biodified:
I)escription:

Paul R. Kucher

top —

Vflflm code.

Behavioral
2007-09—13

Top module for the
is responsible for

Mixed—Signal Test Station. This module
connecting the smaller components of

 

library IEEE;

use IEEE.STD_LUGIC_1164~ALL;

use IEEE.STD_LDGIC_ARITHLALL;
use IEEE.STD_LOGIC_UNSIGNED.AflIfi

entity tap is

generic(
width:
addr:
depth:

);

Port(
clksrc:

ser1a1-c1k:

serial_in:

serial_out:

inject:
tunnel:
leds:

rxd:

txd:
digit_se1:
d1git_val:

integer :I
integer :8
integer :-

out
out
in

out
out
out
in

out
out
out

16;
18;

8

std_logic; —— FPGA [Mn 79
std_logic; —— FPGM [fin BIO
std_logic; —— FPO” Ifin A9
std_logic; —— FPGA fun 813
std_logic; —— FPGA Ffin C5
std_logic; —— FPCfl fun E6
std_logic_vector (7 downto 0);
std_logic; —— FPCH Ffin 7V3
std_logic; —— FPGH [fin R13

std_logic_vector(3
std_logic_vector(6

168

dounno 0);
dounno 0);

32
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ce1: out std_logic; -— FPGA Ffin P7
ub1: out std_logic; —— FPGA Fun 71
lbl: out std_logic; ~— FPCM an P6
ce2: out std_logic; —— FPGA Pin N5
ub2: out std_logic; —— FROM [fin R4
Ib2: out std_logic; —— FPGA Pin P5
as: out std_logic; -— FPGA Pin K4
we: out std_logic; — FPGA Pin 03
mem_address: out std_logic_vector(addr-1 downto 0); —— L5 — L3
mem_data1: inout std_logic_vector(vidth-1 downto 0); -— N7 — R1
mem_data2: inout std_logic_vector(vidth-1 downto 0); — P2 — N1
digital_ios: inout std_logic-vector(12 downto 0); — FPGA I/O Pins
clr_bar: out std_logic; — Unmapped
cs_bar: out std_logic; —— FPGA Pin B4
sdi: out std_logic; -— FPGA Pin D10
sck: out std_logic; -— FPGA Pin .44
adc_clk: out std_logic; — FPGA Pin B6
adc_sck: out std_logic; —— FPGA Pin B7
adc_cs_bar: out std_logic; — FPGA Pin A5
adc_sdi: out std_logic; —— FPGM [fin B8
adc-sdo: in std_logic; — FPGA Pin 85
iadc_clk: out std_logic; — FPGA Pin 07
iadc_sck: out std_10gic; — FPGA Pin D6
iadc_cs_bar: out std_logic; — FPGA Pin D5
iadc_sdo: in std_logic; - FPGA Pin 06
iadc-sc1: out std_logic; — FPGA Pin D8
iadc_sda: inout std_logic; — FPGA Pin A3
digit_pot_clk: out std_logic; — FPGA Pin E7
digit_pot_sdi: out std_logic; —-- FPGA Pin D7
digit-pot_cs_bar: out std_logic; —— FPGA Pin 08
digit_pot_ahdn_bar: out std_logic —— FPGA Pin C9
)3
end top;

architecture netlist of 1:0}: is

component cllnngr is

Port(
c1kin-in: in std_logic;
c1k11_out: out std_logic;
clkin_ibufg_out: out std-logic;
clk0_out: out std_logic
);

end component ;

component digital_io is

Port(
clk: in std_logic;
digital_ios: lnout std_logic_vector(12 downto 0)
instruction: in std_logic_vector(5 downto 0);
io_update: in std_logic;
io_updated: out std_logic;
output: out std_logic
):

end component ;

component serial_io is

Port(
clk: in std_logic;
rxd: in std_logic;
txd: out std_logic;
txd_ready: in std_logic;

169

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155

txd_conplete:

rxd_complete:

parallel_txd:

paralle1_rxd:
)3

end component ;

component ser ial _mux
Port(
module-select:
txd-ready_in:
parallel_tzd_in:
txd_ready_out:

out
out
in

out

in
in
in
out

paralle1_txd_out: out

) 3
end component ;

std_logic;

std_logic;

std_logic_vector(15 dounno 0);
std_logic_vector (15 downto 0)

integer range 0 to 2;
std_logic_vector(2 downto 1);
std_logic_vector(32 downto 1);
std_logic;

std_logic_vector(16 downto 1)

component nenory_block_transf er is

generic (
width:
addr:
depth:

) 3

Port(
clk:

from_address:
to_address:
read-block:
write-block:
data_in:
op_conpleted:
txd_conplete:
txd_ready:
parallel_txd:
read_control:
write_control:

men-op_completed:

address:

nemory_data_erite:
memory_data_read:

)3

end component ;

component memory_i o
generic (
width:
addr:
depth:
)3
Port(
clk:
ce1:
ub1:
1b1:
ce2:
ub2:
lb2:
oe:
ve:
mem_address:
mem_datai:
nen-data2:

is

integer :I 16;
integer :I 18;

integer :I 8

in std_logic;

in std_logic_vector(addr downto O);
in std_logic_vector(addr downto 0);
in std_logic;

in std_logic;

in std_logic_vector(15 downto 0);
out std_logic;

in std-logic
out std_logic

out std_logic_vector(16 downto 0);

out std-logic;

out std_logic;

in std_logic;

out std_logic_vector(addr downto 0);
out std_logic_vector(width-1 dounno 0);
in std_logic_vector(width-1 dounmo 0)

integer :I 16;

integer :I 18;
integer :I 8

out
out
out
out
out
out
out
out
out
inout
inout

std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic_vector(addr-1 dounno 0);
std_logic_vector(width-1 downno 0);
std_logic_vector(width-1 dounno 0);

170

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read_control:

vrite-control:

mem_op_completed:

address:

nemory_data_write

nenory_data_read:
)3

end component ;

component nenory_nux

generic (
vidth:
addr:
depth:

)3

Port(
nodule_select:
read-control_in:
vrite_control_in:
address_in:
nenory_data_vrite
read_control_out:
write_control_out
address_out:
memory_data_vrite

)3

end component;

in std_logic;

in std_logic;
out std_logic;
in std_logic_vector(addr downto 0);
: in std_logic_vector(width-1 dounno 0);

out std_IOgic_vector(vidth-1 dounno 0)

integer :I 16;

integer :I 18;
integer :I 8

_1n: in

: out
out
_out: out

component seven_segnent is

Port (
clk: in st

d_logic;

integer range 0 to 5;

std_logic_vector(4 dounflo 0);
std_logic_vector(4 domnmo 0);
std_logic_vector(((addr+1)I6-1) dounno 0);
std_logic_vector((width'5)-1 dounno 0);
std_logic;

std,logic;

std_logic_vector (addr downto 0);
std_logic_vector(width-1 downno 0)

digit_sel: out std-logic_vector(3 dounflo 0);
digit_val: out std-logic_vector(6 downno 0);
1ed_data: in std_logic_vector(15 downto 0)

) 3
end component ;

component program_dac
Port (
clk:
clr_bar:
cs_bar:
sdi:
sck:
prOgran_dac:
dac_programmed:
dac_instruction:
) 3
end component ;

component 3 ignal -gen
generic (
width:
addr:
depth:
)3
Port(
clk:
cs_bar:
sdi:
sck:
sig_gen_enab1e:

in std_logic;
out std-logic;
out std_logic;
out std_logic;
out std_logic;
in std_logic;
out std_logic;
in std_logic_vector(27 dounno 0)

integer
integer
integer

in std_logic;
out std_logic;
out std_logic;
out std_logic;
in std_logic;

171

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219
220
22 1
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223
224

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227
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235

264

sig-gen_conp1ete:
start_address:
end_address:
read_control:
write_control:
mem_op_completed:
address:
nemery-data_write:
nenory-data_read:

) 3

end component;

component vdac .1111: is
Port (
nodule_se1ect: in

sck-in: in
sdi_in: in
cs_bar_in: in
sck_out: out
sdi-out: out
cs_bar-out: out
)3

end component ;

component vadc is

generic(
width:
addr:
depth:

)3

Port(
clk:
adc_clk:
adc_sck:
adc_cs_bar:
adc_sdi:
adc_sdo:
adc_conv-node:
adc_address:
adc_start_address:
adc_end_address:
adc_data_ready:
adc-data_collect:
read_control:
write_control:
mem_op_completed:
address:
nemory-data_write:
)3

end component ;

component iadc is
generic (
width:
addr:
depth:
)3
Port(
clk:
iadc_clk:

out
in
in
out
out
in
out
out
in

std_logic;

std_logic_vector(addr dounno 0);
std_logic-vector(addr downto 0);
std-logic;

std_logic;

std_logic;

std_logic_vector(addr downto 0);
std_logic_vector(vidth-1 donnno 0);
std_logic_vector(width-1 downno 0)

integer range 0 to 2;

std_logic_vector (2 downto 1) ;
std_logic_vector(2 dovnno 1);
std_logic_vector(2 downno 1);

std_

logic;

std-logic;

std-

logic

integer :I 16;

integer :- 18;

integer :I 8

in
out
out
out
out
in
in
in
in
in
out
in
out
out

out
out

std_logic;

std_logic;

std_logic;

std_logic;

std_logic;

std_logic;

std_logic_vector (1 downto 0);
std_logic_vector(3 dounno 0);
std_logic_vector(addr donnno 0);
std_logic_vector(addr dounno 0);
std_logic;

std_logic;

std_logic;

std_logic;

std_logic;

std_logic_vector(addr dounno 0);
std_logic_vector(width-1 downflo 0)

integer :I 16;

integer :- 18;

integer 3"I 8

in

out

std_logic;
std_logic;

172

280
28 1
282
283
284

286
287

298

311

335

iadc_sck:
iadc-cs_bar:
iadc_sdo:
iadc_scl:
iadc_sda:
iadc_address:

iadc_start_address:

iadc-end_address:
iadc-data_ready:
iadc_data_collect:
read_control:
write_control:
mem_op_completed:
address:
nenory_data-write:

)3

end component ;

component digital -pots
Port(

clk:
digit_pot-clk:
digit_pot_sdi:
digit_pot_cs_bar:

digit-pot_shdn_bar:

digit_pot_nunber:
digit-pot-va1ue:
digit_pot_update:
digit_pot_updated:
)3

end component;

component injection is
Port(

)3

clk:

inject:
inject_pulse:
pulse-injected:

out
out
in

out

inout

in
in
in
out
in
out
out
in
out
out

9
18

in
out
out
out
out
in
in
in
out

injection_pulse_width:

end component ;

component serial_shifter is
generic(

)3

width:
addr:
depth:

Port (

clk:

serial_clk:
serial_in:
serial_out:
shift_start_flag:
shift_end_flag:
start-address:
end_address:
read_control:
write_control:
mem_op_completed:
address:
memory_data_write:

inte
inte
inte

in
out
out
in
in
out
in
in
out
out
in
out
out

std_logic;

std_logic;

std_logic;

std_logic;

std_logic;

std_logic_vector(3 dounno 0);
std_logic-vector(addr downuo 0);
std_logic_vector(addr douuno 0);
std_logic;

std_logic;

std_logic;

std_logic;

std_logic;

std_logic_vector(addr downno 0);
std_logic_vector(width-1 domnno 0)

std_logic;
std_logic;
std_logic;
std_logic;
std_logic;

st
St

d_logic_vector (4 downto 1);
d_logic_vector(7 downto 1);

std_logic;
std_logic

in
out
in
out
in

ger
ger
ger

std
std
std
std
std
std
std
std
std
std
std
std
std

std-logic;
std_logic;
std_logic;
std_logic;
std_logic_vector(7 donnno 0)

:I 16;
:I 18;
:I 8

_logic;
_logic;
_10gic;
_logic;
_logic;
_logic;

_logic_vect or (addr downto 0);
_logic_vector(addr downno 0);

-logic;
-logic;
_logic;

_logic_vector (addr downto 0);
_logic_vector(width-1 domnno 0);

173

342 nemory_data_read: in std_logic

343 ) 3
344 end component;
345

346 component decode is
347 generic(

348 width: integer :I 16;

349 addr: integer :I 18;

350 depth: integer :I 8

351 );

352 Port(

353 clk: in std_logic;

3.54 serial_select: out integer range 0 to 2;

355 txd_ready: out std_logic;

356 txd-conplete: in std_logic;

357 rxd_complete: in std_logic;

358 parallel_txd: out std_logic_vector(15 downto O);
359 paralle1-rxd: in std_logic_vector(15 downto 0);
360 shitt_start-flag: out std_logic;

361 shift_end-11ag: in std_logic;

362 leds: out std_logic_vector( 7 downto 0 );
363 1ed_data: out std_logic_vector(15 downto 0);
364 fron_address: out std_logic_vector(addr downto 0);
365 to-address: out std_logic_vector(addr downto 0);
366 read_block: out std_logic;

367 write_block: out std_logic;

368 nen-data_in: out std_logic_vector(15 downto 0);
369 xfr_0p_conpleted: in std_logic;

37o nodu1e_select: out integer range 0 to 5;

371 vdac_select: out integer range 0 to 2;

372 sig_gen_enable: out std_logic;

373 sig_gen_conplete: in std_logic;

374 program_dac: out std_logic ;

375 dac_programmed: in std_logic;

376 dac_instruction: out std-logic_vector (27 downto 0);
377 adc_conv_node: out std_logic_vector(1 downto 0);
378 adc_address: out std_logic_vector (3 downto 0);
379 adc_data_ready: in std_logic;

380 adc-data-collect: out std_logic;

381 iadc_data_ready: in std_logic;

382 iadc-data_collect: out std-logic;

383 1nject_pulse: out std_logic;

384 pulse_1njected: in std_logic;

385 injection_pulse_width: out std-logic_vector(7 downto 0);
386 tunnel_pulse: out std_logic;

387 io_instruction: out std_logic_vector(5 downto 0);
388 io_update: out std_logic;

389 io_updated: in std_logic;

390 io_output: in std_logic;

391 digit_pot_number: out std_logic_vector(4 downto 1);
392 digit_pot_va1ue: out std_logic_vector (7 downto 1);
393 digit_pot_update: out std-logic;

394 digit_pot_updated: in std_logic

395 );

396 end component;

397

398 signal parallel_txd_in: std_logic-vector(32 downto 1);

399 signal txd_ready_in: std_logic_vector (2 downto 1);

400 signal serial_select: integer range 0 to 2;

401 signal txd_ready_out, txd_conplete, rxd_complete: std_logic;

402 signal parallel_txd_out , parallel_rxd: std_logic_vector(15 downto 0);
403

174

404
405
406
407
408
409
410
411
412
413
414
415
416
417

422

448

450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465

signal led_data: std_logic_vector(15 downto 0);

signal 1ron-address , to_address: std_logic-vector(addr downto 0);

signal read_block, write_block, xfr_op_completed, nem_op-conpleted: std_logic;
signal nem_data_in: std_logic_vector(15 downto 0);

signal nenory_data_read: std_logic_vector(width-1 downto 0);

signal module_select: integer range 0 to 5;

signal read-control_in, write_control_in: std_logic_vector(4 downto 0);
signal address-in: std_logic_vector(((addr+1)I6-1) downto 0);

signal nemory_data_write_in: std_logic-vector((width*S)-1 downto 0);
signal read-control_out, write_control_out: std_logic;

signal address_out: std_logic_vector(addr downto 0);

signal nemory_data_write_out: std_logic_vector(width-1 downto 0);

signal program_dac, dac_programmed: std_logic;
signal dac_instruction: std_logic_vector (27 downto 0);

signal adc_conv_node: std_logic_vector(1 downto 0);
signal adc_address: std_logic_vector(3 downto 0);
signal adc-data_ready , adc_data_collect: std_logic;

signal iadc,data-ready, iadc_data_collect: std_logic;

signal inject_pulse, pulse_injected: std_logic;
signal injection_pulse_width: std_logic,vector(7 downto 0);

signal io_instruction: std_logic_vector(5 downto 0);
signal io_update, io_updated, io_output: std_logic;

signal shift_start_11ag, shift-end_flag: std_logic;

signal digit_pot_number: std_logic_vector(4 downto 1);
signal digit_pot_va1ue: std_logic_vector (7 downto 1);
signal digit_pot_update . digit-pot_updated: std_logic;

signal vdac_select: integer range 0 to 2;
signal vdac-sck_in, vdac-sdi-in, vdac-cs-bar_in: std,logic_vector(2 downto 1);
signal sig_gen_enab1e , sig_gen-conp1ete: std_logic;

signal clkin-ibufg-out, c1k0_out: std_logic;
signal clkfx_out. clk: std_logic;

begin
clkmanager: clkmgr port map( clksrc, clkfx_out, c1kin_ibufg_out , clk );

serial: serial_io port map( clk, rxd, txd, txd_ready_out, txd_complete,
rxd_complete, parallel_txd-out, paralle1_rxd );

ser_nux: serial_nux port map( serial_select, txd_ready_in,
parallel_txd-in, txd_ready_out, parallel-txd-out );

nemory_xfr: nemory_block_transfer port map( clk, fron_address, to_address,
read-block , write_block . mem_data_in , xfr_op-conpleted , txd_conplete ,
txd-ready_in(2), parallel-txd_in(32 downto 17), read-control_in(1),
write_control_in(1) , nem-op_completed ,
address_in (((addr+1)*2)-1 downto addr+1) .
nenory_data_write_in(widthI2-1 downto width), nemory_data_read )3

memory: memory-io port map( clk, ce1, ub1, lb1, ce2. ub2, Ib2, 06, we,
mem_address, mem_datal, mem_data2, read_control_out , write_control_out ,

175

466 mem_op_completed, address_out, nenory_data_write_out , menory_data-read );
467

468 mem_nux: nenory_nux port map( nodule_select , read_control_in, write_control_in.
469 address_in, nemory_data_write_in , read_control_out , write_control-out ,

470 address_out, nemery_data_write_out );

471

472 display: seven_segnent port map( clh, digit_sel, digit-val, led_data );
473
474 v-dac: program_dacs port map( clk. c1r-bar, vdac-cs-bar-in(1), vdac_sdi_in(1),

475 vdac_sck_in (1) , program_dac , dac_programmed , dac_instruction )3

476

477 sig_gen: signa1_gen port map( clk, vdac_cs_bar_in(2), vdac-sdi_in (2),

478 vdac_sck_in (2) , sig_gen_enable , sig_gen_conplete , fron_address ,

479 to_address , read_control_in(4) , write_control-in(4) , men-op_conpleted ,
480 address-in (((addr+1)*5)'1 downto (addr+1)t4) .

481 memory_data_write_in(widthIS-1 downto widthI4), nemery-data_read );
482

483 v_dac_nux: vdac_nux port n‘np( vdac_select , vdac_8ck_in, vdac_sdi_in,

484 vdac_cs_bar_,in, sck, sdi, cs_bar );

485

486 v_adc: vadc port mw( clk, adc_c1k, adc_sck, adc_cs_bar, adc_sdi, adc_sdo,
487 adc_conv_mode , adc_address , fron_address , to_address . adc-data_ready ,
488 adc-data_collect , read_control_in(2) , write_control_in(2) .

489 mem_op_completed , address-in(((addr+1)‘3)-1 downto (addr+1)*2),

490 nenory_data-write_in(width93-1 downto widtht2) );

491

492 i_adc: iadc port map( clk, iadc_clk, iadc-sck, iadc-cs_bar, iadc_sdo,

493 iadc-scl, iadc_sda, adc_address , fron_address , to_address ,

494 iadc_data_ready . iadc_data_collect , read_control_in (3) .

495 write_control_in(3) . mem_op_completed ,

496 address-in(((addr+1)*4)-1 downto (addr+1)#3).

497 nenory_data_write-in(widthI4-1 downto widthIS) )3

498

499 pots: digital_pots port mep( clk, digit_pot_c1k, digit_pot_sdi ,

500 digit_pot_cs_bar , digit_pot_shdn_bar , digit_pot_nunber ,

501 digit_pot_va1ue , digit_pot_update, digit_pot_updated );

502

503 injection_control: injection port inap( clk, inject, inject_pulse,

504 pulse_injected, injection_pulse_width )3

505

506 input_output: digital_io port map( clh, digital_ios, io_instruction,

507 io_update, io_updated, io_output );

508

509 shifter: serial_shifter port map( clk, serial_clk, seria1-in. serial_out,
510 shift_start_flag , shift_end_flag , fron_address , to_address ,

511 read_control_in(O) , write_control_in(0) , mem_op_completed ,

512 address_in(addr downto O), nenory_data_write_in(width-1 downto 0),
513 memory-data_read(0) );

514

515 main: decode port map( clk, serial_select, txd_ready_in(1), txd_complete,
516 rxd_complete , parallel_txd_in(16 downto 1), parallel_rxd,

517 ahift_start_flag , shift_end_flag , leds, led_data, fron_address ,

518 to_address , read_block, write_block , mem_data_in, xfr_op_completed ,
519 nodule_select , vdac_select , sig_gen_enable , sig_gen_complete ,

52o program_dac , dac_programmed , dac_instruction , adc_conv-1node , adc_address ,
521 adc_data_ready , adc-data_collect , iadc_data_ready , iadc_data_collect ,
522 inject_pulse , pulse_injected , injection_pulse_width , tunnel ,

523 io_instruction , io_update , io_updated , io-output , digit_pot_nunber ,
524 digit_pot_va1ue, digit_pot_update, digit_pot-updated );

525

526 end netlist;

176

C.19 Implementation Constraints File: top.ucf

1 # Implementation Constraints File

2 # Assignment of FPGA Pins

3 # Modified: 2007—09—13

4 NET ”clksrc" LDC I "T9" ;
5 NET "mem_address<0>" LDC I ”L5" ;
6 NET "mem_address<1>' LDC I "N3" ;
7 NET "mem_address<2>" LDC I ”M4" ;
8 NET ”mem_address<3>" LDC I "H3" ;
9 NET "mem_address<4>" LDC I "L4" ;
10 NET "mem_address<5>" LDC I "G4" ;
11 NET ”mem_address<6>" LDC I ”F3" ;
12 NET "mem-address<7>" LDC I "F4" ;
13 NET "mem_address<8>" LDC I "E3" ;
14 NET ”mem-address<9>" LDC I "E4" ;
15 NET "mem_address(10>" LDC I "GS” ;
16 NET "mem_address<11>" LDC I "H3" ;
17 NET 'mem_address(12>" LDC I "H4" ;
18 NET “mem_address<13>' LDC I "J4" ;
19 NET "mem_address<14>" LDC I "J3" ;
20 NET "mem_address<15>" LDC I "K3" ;
21 NET 'mem_address<16>" LDC I "K5" ;
22 NET 'mem_address<17>" LDC I “L3" ;
23 NET ”mem_data1<0>" LDC I “N?“ ;
24 NET "mem_dat81<1)" LDC I ”T8" ;
25 NET "mem_datal<2>" LDC I "R6" ;
26 NET ”mem_datal<3>" LDC I "T5" ;
27 NET ”mem_data1<4>" LDC I "R5” ;
28 NET "mem_data1<5>" LDC I "C2" ;
29 NET "mem_datai(6>" LDC I "C1" ;
30 NET ”mem_datal(7>" LDC I ”B1" ;
31 NET ”mem_datal<8>“ LDC I ”D3" ;
32 NET ”mem_data1<9>" LDC I "P8" ;
33 NET 'mem_datai<10>“ LDC I ”F2" ;
34 NET "mem_datai<11>" LDC I "Hi" ;
35 NET ”mem_data1<12>" LDC I ”J2" ;
36 NET "mem_data1<13>" LDC I "L2" ;
37 NET "mem_datal<14>" LDC I "P1" ;
38 NET "mem_datai<15>" LDC I "R1" ;
39 NET "mem_data2<0>" LOC I "P2" ;
40 NET "mem_data2<1>" LDC I "N2" ;
41 NET "mem-data2<2>" LOC I "M2" ;
42 NET ”mem_data2<3>” LDC I "K1” ;
43 NET "mem_data2<4>" LDC I "J1" ;
44 NET "mem_data2(5>" LDC I "G?" ;
45 NET "mem_data2<6>” LDC I "E1" ;
46 NET ”mem_data2<7>" LDC I "DI” ;
47 NET "mem_data2<8>" LDC I "D2" ;
48 NET ”mem_data2<9>" LDC I "E2" ;
49 NET "mem_data2<10>" LDC = ”C1" ;
50 NET "mem_data2<11>" LDC I ”F5” ;
51 NET "mem_data2<12>" LDC I "C3" ;
52 NET "mem_data2<13>" LDC I "K2" ;
53 NET ”mem_data2<14>" LDC I "Hi" ;
54 NET "mem_data2<15>" LDC I “N1" ;
55 NET "ce1" LOC I "P?” ;
56 NET "ce2" LDC I "N5" ;
57 NET "1b1" LDC I "P6" ;
58 NET "Ib2" LDC I ”P5" ;

177

59
60
61
62
63

65
66
67
68
69
70
7 1
72
73
74
75
76
77
78
79
80
8 1
82
83

833

86
87
88
89

91
92
93

95

97

98

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119

NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET

"ub1"
"ub2"
woe"
"we"
”digit_val<0>"
'digit-va1<1>"
"digit_val<2>"
"digit_val<3)"
”digit_va1<4)"
“digit_val<5>"
"digit_val<6>”
”digit_se1(0)"
"digit_sel<1)"
”digit_sel<2>"
"digit_sel<3>”
"1eds(0>"
"leds<1>"
“leds<2>"
"leds<3>"
"leds<4>"
"leds<5>"
"leds(6>"
"leds<7)"

"txd"

'rxd'
”serial_clk"
"serial_in"
"serial_out'
"inject"
”tunnel”
”digital_ios<0>"
"digital_ios<1>"
'digital_ios<2)”
”digital_ios<3>"

fiflfifl'”digihfl-ios<4>”

NET
NET
NET
NET
NET
NET

"digital-ios<5>"
'digital-ios<6>"
"digital-ios<7>"
"digital_ios<8>"
"digital_ios<9>”
“digital_ios<10>"

#fi$fl‘”diginfl-ios<11>”
#NET "digital_ios <12)”

NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET

'digit_pot_clk"
"digit_pot_sdi"
"digit_pot_cs_bar"

"digit_pot_shdn_bar"

"cs_bar"
”sck"

"sdi"
"adc_c1k"
"ado-cs_bar"
"adc_sck"
"adc_sdi"
"adc_sdo"
"iadc_clk"
"iadc_cs_bar"
"iadc_sck”
"iadc_sdo"
"iadc_scl"
”iadc_sda"

LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC

LCK7=

LDC
LDC
LDC
LDC
LDC
LDC
£1X3
LCX?
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC
LDC

"T4"
"R4"
"K4"
"G3"
"N16"
"F13"
"R16"
”915"
"N15"
"613"
"£14"
”D14"
"614"
”F14"
"513"
"K12”
"P14"
"L12“
"N14"
“p13"
"N12"
"p12"
“911"
"313"
"113"
"810"
.Agu
"313"
"C5 M
"£6:
”H10"
"A73
"M7"
”A13"
”A9”
"110"
"314"
"13"
"311"
"312"
"112'
”310”
#813"
"E7"
.07"
"ca"
"C9"
"B4"
"A4"
"010"
"B6"
"A5"
"B7"
"B8"
"35"
"C7"
"cs"
”D6"
"05"
"A3"
"D8"

178

APPENDIX D

MATLAB Toolbox Overview

Appendix E provides source listings for all MATLAB functions that control the test
station. Each script is documented and syntax descriptions are available in the com-
ments. Additionally, these descriptions are available in MATLAB via the help func-
tion in the form help (function name).

These functions will only be visible in MATLAB if the toolbox has been properly
added to the directory search path. This is accomplished by adding the full directory
path in the File —> Set Path dialog or by directly using the path function. In
addition, ADC calibration data is stored in the same directory, and this path must
be set in FPGAInit .m.

The board is controlled via the instructions described in Table 4.1, and all
hardware-level communication is handled through the built-in file I / 0 functions such
as fopen, fwrite, fread, and fclose. Serial objects are created with the serial
function, which requires the COM port number as its argument. Consequently, this
parameter must be modified for every installation. All other configuration options are
set through this object and are given in Section E.1. Also, MATLAB writes to the
serial port using an array of unsigned, 8-bit integers. Because the FPGA uses a 16-bit
data word internally, MATLAB must read and write two 8~bit packets sequentially

and reconstruct received data as a 16-bit unsigned integer.

179

The F PGA is initialized by calling FPGAInit. This function cannot be called
a second time unless the serial port object is released by calling fclose(s). The
initialization script runs a sanity check on the F PGA to ensure that the memory
transfer and loopback commands are working properly before initializing the test
station. Also, the working directory is changed to the location of the toolbox. All
other functions may be called following successful initialization. However, failure
may result if the FPGA is not in its idle state or if the JTAG program bit stream is
corrupted. Thus, ensuring that the FPGA has been reset prior to initialization will
prevent either the FPGA or initialization scripts from entering a locked state.

Appendix F may act as an example toolbox for chip testing. These scripts were
used in the floating gate experiments of Chapter 5. Here, SVM2Init acts as the system
initialization routine and calls both FPGAInit as well as configures all of the on—chip

biases and serial interface.

180

APPENDIX E

Test Station MATLAB Functions

E.1 FPGAInit.m

DQ4QM§WNH

wwwwwwuwwwwnwuunnunupump—pupa..-
COOQOU‘uthI-‘OQOQOIOwaHOOOQGthNI-IO

70 This script initializes the FPGA for data acquisition. It opens the

% serial port for data transfer as well as runs some sanity checks on the.
%FPGA’s modules to ensure everything is working properly.

% Cheates serial port object ’3’ at the desired settings.

cd(’c:\Documents and Settings\Pau1 R. Kucher\Desktop\Matlab\FPGA Tools’)
eval( sprintf([’load VADCCalibrationData’]) ); % lflfltage ALK7(7aHbration [NHa

global a;

a I seria1(’COM2’); % Set to whatever (29M port you are using.

s.Tineout I 5;

s.InputBufferSize I 600000; %A value greater than the maximum memory size
3.0utputBufferSize I 600000;

set(s,’BaudRate’,115200,’Parity’,’none’, ’StopBits’, 1);

fiopen(s);

random_nunber I round(rand(1)*1000);
FPGAWriteMemoryBlock(1,100,randon-nunber);
read_data I FPGAReadHenoryBlock(1.100);
sun-of_zeros I ann(mnn(read_data,1),2);

init_test I FPGALoopback(5);
init_test2 I FPGALoopback(0);

if init_test 'I 5 II init_test2 'I 0 ll sum_of_zeros ~- randon_numbert100,
fprlntf(’Sanity Check Failed! Check Setup.\n’);

else
fprintf(’Initialization Successful!\n’);

end;

% Initialize Potentiometers
FPGASetBiasCurrent( 0, 127 );
for channel-1:8,

FPGASetBiasCurrentC channel, 127 );
end;

% Initialize Injection Circuit

FPGASetBias (37. 2); % Injection Voltage
FPGASetBias (38, 1.5); % Threshold

181

40
41
42
43

FPGASetBias(39,

% Initialize
FPGASetBias(40,

3.3); %

Current ADC
1);

Idle

E.2 FPGALOOpback.m

OWQGUhWNt-i

HHHHHHHHI—IH
omqmuawuuo

lflfltage

function output I FPGALoopbackC intval );

§t§3§i§i§2§i§i

global

This function

Loopback Tcst (sanity check).
it to the P7114, decodes
read.

it,

intval I uint8( intval );

fwrite (e ,

while a . BytesAvailable <2 ,

end;

date I
output

fread(e, 2);
I data(1,:);

E.3 FPGADigitalIO.m

cocoqascnauiou—

NNNNDNNNi—HHwHi—Hi—i—u
ammawuwoomqaubwuwo

function output =

.%

Takes

and then
is useful
the FPGA and you want to verify that
decoded properly and the

if you

instruction

Syntax: output = FPGALoopbaek( intval )

in a value 0—255 and sends

serializes it back to hiauab to be
are uniting a new instruction for
the previous instruction has been
fetch / decode process is at idle.

[intval hex2dec(’00’)].’synC’);

FPGADigitalIO( pin_name, direction, value)
% Syntax: output = FPGADigitalIO( pin-name.

direction, value)

% Generic digital l/O control of the FPGA’s remaining 1/0 pins.

% Up to twelve channels are available
% overridden in the FPGA’s

global

if nargin < 3,
value I 0;

end;

if
elseif
elseif
elseif
elself
elseif
elseif
elseif
elseif
elseif
elseif
elseif
elseif
end;

strcmp(pin_nane ,
strcmp(pin_name ,
strcmp(pin-name ,
strcmp(pin_name ,
strcmp(pin_name ,
strcmp(pin_name ,
strcmp(pin_nane ,
strcmp(pin_name ,
strcmp<p1n-name ,
strcmp(pin_name ,
strcmp(pin_name ,
strcmp(p1n-name ,
etrcmp(pin_name ,

’MlO’).
)A'rl),
)H7I)’
’A13’).
JAgl)’
’A10’).
'314'),
’A8,)o
’811’),
'312’),
’A12’),
’810’),
’813’).

channel
channel
channel
channel
channel
channel
channel
channel
channel
channel
channel
channel
channel

if they have not been
internal controller.

III I
i-bHHtomleicn-thI-bo
”Hen-unveuev-veuubowo-a

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if strcmp(direction, ’out’).
dir_nun I 8;
elseif strcmp(direction, ’in’).
dir_nun I 0;
else
fprintf(’You must specify the direction of data flow.’);
return;
end;

instruction I bitor( dir_num, bitshift( value, 2) );
instruction I bitor( hex2dec(’80’), instruction );

try , fwrite (s , [channel instruction] , ’ sync ’ );
catch , fwrite (s , [channel instruction], ’ sync ’ );
end;

while e.ByteeAvailable < 2,
end;

data I fread(s,2);
output I bitehifthata(2,1),8) + data(1,1);

E.4 FPGAInjectPulse.m

@QNIOU‘AQNH

0369096303QNNMNNNMNNHF‘F‘HHHF‘HHH
lbwNHOOQQOiUwaHOOQQGU‘fiUND-IO

function time I FPGAInjectPulse( width );

95 Syntax: time = FPGAInjectPulse( width )

%

% Produce a pulse of —2V to the floating—gate transistor injection pin.

% The value of 'width’ corresponds to the time the injection pulse is set.
% in the fawn tnne = (l/50e6)*2‘(uddth+l) umere 'tfine' is the return value
95 in seconds.

global e;

nax_pulee I hex2dec(’FF’);
if width > max-pulse,
width I max_address;
elseif width < 0,
width I 0;
end;
try, fwrite(s, [width hex2dec(’60’)], ’sync’);
catch. fundte(e, [width hex2dec('60’)],’sync’);
end;
injection_width I 1/5066’2-(Hidth+1);
fprintf ( ’Injection width: 21.6f seconds.\n’, injection_width );

pause( injection_width+1/57600#20);

while e.BytesAvailahle < 2,
end;

freed (e , . ByteeAvailable);

time I injection_width;

183

E.5 FPGATunnel.m

OQNGMJIUUH

HHHHHHI—l
¢U§WNHO

function FPGATunnelC state )3

% Syntax: FTML47vnnd( state )

.%

% Fowler-Nordheim Tunneling enable/disable function. The variable ’state
% is specified as I if the tunneling voltage is desired and 0 if the 3.3V
% regulator supply is desired.

9

global s;

intval I uint8( state );
fwrite(e, [intval hex2dec(’70’)l , ’sync’);

while 3 . Byteshvailable <2 ,
end;

data I fread(s, 2);

E.6 FPGASetBias.m

OWQGUwar-t

Macaw““UMMNNNNNNNNHHHHHHHMHH
GUIACJNHOCDOqa’mfiwwh‘oom‘la’mfiwwfio

function status I FPGASetBias( channe1_number , dac_value );

% Syntax: status = PIML4Seufias( channeLJuunber. dac_value );

.%

% FPGASetBias sets a specific analog DC bias to one of the motherboard's
% five on—board DAC3. The first paranuner is the channel nunflmr (1—40) and
% the second is the specific voltage that the DAC unll be set to (0 to 4.096t7.

global s;

dac-num I floor((channel_number-1)/8) + 1;
channe1_nun I channel_number - (dac_num - 1)I8;

supp1y_range I 4.098;
dacbits I 16;

if (dac_num > 0) & (dac-num < 6) & (channe1_num > 0) & (channel_num < 9)

if dac_value > supply_range
fprintf( [’Given DAC value = (X1.4f) has exceeded the higher ’...
’limit of 4.098V.\nDAC Value is corrected and assigned ’...
’with maximum supply range.\n’], dac_value );
dac_value = supp1y_range;
end;

range_value I bitand(uint32((dac_va1ue/supply_range)I((2‘dacbits)-1))....
hex2dec(’FFFF’));

value-msbs I bitshift( bitand( range_value, hex2dec(’FF00’) ), -8);
value-lsbs I bitand( range_value, hex2dec(’00FF’) );

comm_msbs I bitor( hex2dec(’20’), dac_num);
comm_lsbe I bitor( hex2dec(’30’), channel_nun-1);

try, fwwite(s, [comm_lsbs comm_msbs value_lsbs value_msbs],’sync’);

catch, fwufite(s, [comm-lsbs comm_msbs value_lsbs value_msbs],’sync’);
end;

184

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while s . BytesAvailable <2 ,
end;
fread(s,2);
status I 1;
else
fprintf( [’Either DAC number ( > 5) or channel number (
’ has exceeded the limits’J);
status I 0;
end;

E.7 FPGASetBiasCurrent.m

OOQGG‘CADF

NMHHHHHHHHH
ocwqamawuwo

functkn: FPGASetBiasCurrent( channel, value );
% Syntax: FPGASetBiasCurrent( channel, value );

> 8)’...

%

% Bias current generator. The eight channels have a range of 0—7 (with the
% exclusion of the current ADC potentiometer. 1—8 otherwise) and have an
96 integer ’value’ from 0—127, representing the digital code of the

% potentiometer that controls the current amplitude.

global s;

value I uint8( value );

command I bitor(hex2dec(’40’). channel);
fwrite (s , [value command] , ’ sync ’ );

while s . BytesAvailable <2 ,
end;

data I fread(s, 2);
output I data(1,:);

E.8 FPGAReadVoltage.m

OWQOUBWMH

U-lb-‘HHD-IHHHI-‘I-I
mmqmuawaiwo

function output I FPGAReadVoltage( channel , start_address , samples , clk_mode );
95 Syntax: output 2 FPGAReadVoltage( channel, start-address .

ssnssnnsssnsnasss

samples, clk-m0de ):

FPGAReadVoltage allows voltage analog—to—digital conversion via
the LTC2/18 I6—channel, 24—bit Delta—Sigma ADC. Channels are numbered

1-16 and are specified on the daughter board. The 'start-address

7

parameter sets the first address to begin storing the conversion
result in memory. The variable ’samples ' specifies the number of samples

to be taken during the experiment.

’clkJnode ’ specifies the frequency of the ABC’s conversion.

clock. It

defaults to BMHZ when this optional parameter is unspecified. Other valid

rates are ’internal ’ which provides the best accuracy and

a 60 H: notch

filter to help reject light pickup noise, '400kllz’ and ’IMHz’ modes are

provided as a best compromise between speed and accuracy.

Accuracy

deteriorates rapidly after [MHz as detailed in the LTC2418 datasheet.

The output is a two—dimensional array that contains the channel from
which the conversion result was obtained as well as the result itself.

185

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%'
96 Last modified: 2007—09—13

global s titted;

if nargin < 4,
conv_clk-mode I 1;

elseif strcmp(c1k-mode,’internal’) II 1,
conv-c1k_mode I O;

elseif strcmp(clk_aode,’QOOkHz’) II 1,
conv_c1k_mods I 3;

elseif strcmp(clk_mode,’1HHz’) II 1,
conv_c1k_mode I 2;

else % 2 MHz Conversion Clock
conv-c1k-mode I 1;

end;
channel I channel - 1;
end_address I start_address + 2Isamp1es - 1;

data_total I end_address - start_address + 1;
start_address_read I start_address;
end_address_read I end-address;

max-address I hex2dec(’7FFFF’):

if start_address > end_address,

fprintf(’The ending address must be greater than the starting address!\n’);

return;
elseif (max_addrsss - end_address) < ( end_address - start_address + 1),
fprintf(’The ending address is too close to the last address in RAM!\n’);

return;

elseif channel < 0 II channel > 15,
fprintf(’The specified channel number is invalid!\n’);
return;

end;

three_msbsl I bitand( bitshift(start-address,-16), 7);
three_msbs2 I bitand( bitshift(end_address,-16), 7);

msbs I bitshift(conv_clk_mode,6) + bitshift(three_msbs2,3) + three_msbs1;

96 Just set the address to allow a maximum number of bits.
start_address I uint16( bitand(start-address, 65535 ) );
end-address I uint16( bitand(end_address, 65535 ) );

packetil I bitand( start_address, hex2dec(’00FF’) );
packet21 I bitshift( bitand( start_address, hex2dec('FF00’) ), -8);

packet12 I bitand( end_address, hex2dec(’00FF’) );
packet22 I bitshift( bitand( end_address, hex2dec(’FFOO’) ), -8);

command I bitand(hex2dec(’3F’).bitor(hex2dec(’FO’).channel));

try, fwnfite(s, [msbs command packetil packet21 packet12 packet22],’sync’);
catch, fundte(s, [msbs command packetll packet21 packet12 packet22],’sync’);
end;

while s . BytesAvailable <2 .

end;

fread(s,2);
data I FPGAReadHemoryBlock(start_address-read, end_address_read);

186

82
83 reference I 2.501;

84 supply I 5.0209;

85

86 jIl;

87 for 1I1:2:data_tota1,

88 data_temp I bitor(bitshift(data(i).16).data(i+1));

89 channe1_returned I bitor(bitand(14,data_temp),

90 bitshitt(bitand(16,data-temp),-4));

91 code I bitshift(bitand(536870848,data_temp),-6);

92 measured_voltage I (bitget(data_temp,29))*bitget(data_temp,30)*supply
93 + (1-bitget(data_temp,29))*bitget(data_temp.30) *

94 (code/(2‘23)Isupply+reference) ...

95 + (1-bitget(data_temp,30))*bitget(data_temp.29) #

96 (reference-(1-code/(2‘23))Isupply);

97 output(j,1) I channe1_returned + 1;

98 output (3' ,2) I measured_voltage; % - polyval (fitted , measured_voltage)+3e—3;
99 j I j + 1;

um end;

E.9 FPGAReadCurrent.m

functhon output I FPGAReadCurrentC channel, start_address, samples, gain );
Syntax: output = FTMLAReadCunwnt( channel, start-address, sanufles, gain );

Returns the voltage read by the L7YEM15—1 data converter when doing l—V
conversion. This function is called in FPGAEstimateCurrent, but gives
better control over the conversion procedure such as udnch addresses to
store conversion results and gain control.

«inadequate»...
Efiifiifiifiifiifi

gLobal s;
10
11 update I 0;
12 if nargin < 4,
13 update I O;
14 gain I 0;
15 else
16 update I 8;
17 end;
18
19 channel I channel - 1;
2o
21 end_address I start-address + 2*samples - 1;
22
23 data-tota1 I end_address - start_address + 1;
24 start-address_read I start_address;
25 end_address_read I end_address;
26
27 max-address I hex2dec(’7FFFF’);
28
29 if start-address > end_address,
30 fprintf(’The ending address must be greater than the starting address!\n’);
31 return;
32 elseif (max_address - end_address) < ( end_address - start_address + 1),
33 fprintf(’The ending address is too close to the last address in RAH!\n’);
34 return;
35 elseif channel < 0 ll channel > 15.
36 fprintf(’The specified channel number is invalid!\n’);
37 return;

187

38 end;

39

4o three_msbsl I bitand( bitshift(start_address ,-16), 7);

41 three-msbs2 I bitand( bitshift(end_address ,-16), 7);

42

43 msbs I bitshift (three_msbs2 ,3) + three_msb81;

44

45 % Just set the address to allow a maximum number of bits.

46 start-address I uint16( bitand(start_address, 65535 ) );

47 end_address I uint16( bitand(end_address, 65535 ) );

48

49 packet11 I bitand( start_address, hex2dec(’00FF’) );

50 packet21 I bitshift( bitand( start_address, hex2dec(’FI-‘OO’) ), -8);
51

52 packet12 I bitand( end-address. hex2dec(’00FF’) );

53 packet22 - bitshift< bitand( end-address, hex2dec(’FF00’) ), -8);

55 command I bitand (hex2dec( ’ 5F ’) . bitor (hex2dec( ’ F0 ’ ) , channel D;
56
57 try , fwrite (s , [msbs command packet11 packet21 packet12 . . .

58 packet22 update gain] , ’ sync ’ );

59 catch , fwrite (s , [msbs command packet11 packet21 packet12
60 packet22 update gain], ’ sync ’ );

61 end;

62 while s.BytesAvailable <2,

63 end;

64

65 fread(s,2);

66

67 data I FPGAReadHemoryBlock(start-address-read,end_address-read);
68

69 jIl;

7o

71 for 1I1:2:data_tota1 ,

72 data_temp I bitor (bitshift (data(i) .16) ,data(i+1) );
73 value I bitshift (bitand (1073741760 , data_temp) , -6);
74 output(j) I 2*5.04*va1ue/16777216-2.5;

75 j - j + 1;

76 end;

E.10 FPGAEstimateCurrent.m

1 function output I FPGAEstimateCurrent( channel, samples );

2 % Syntax: output = FPGAEstimateCurrent( channel. samples );

3 %

4 9’6 Calculate the measured current from the voltage—mode output of the
5 % current ADC circuit. The variable ”reference” should be recalibrated
6 % upon startup for accurate current measure-ment.

7

8 global s currentadcoffset;

9

10 reference I 1.0258;

11 %reference = FPGAReadCurrent( 9.1.samples ); % Read from

12

13 measured I mean( FPGAReadCurrent( channel, 1, samples ) ); % Measure current
14

15 output I ( currentadcoffset - measured ) / 2.195596;

16

17 fprintf ( ’Measured Current: 7.1.6an\n’, outputtleQ );

188

E.11 FPGAReadMemory.m

OQQOIU‘éQDr-i

Aaaaanuuwwwwwwwwununnunnwwwwr—wawwwu—
maunnoomq0:0!s-wuuoomqmuawuwoomqmo‘Awwa-o

function output I FPGAReadHemory( address );

96 Syntax: output = FPGAReadMemory( address )

%

% Read from the FPGA data RAM by specifying a 19—bit address 'address ' and
95 return the value as 'output ’

global s;
max_address I hex2dec(’7FFFF’);

if address > max-address, % 19—bit addresses
address I max-address;
end;

addressl I address;
address2 I address;

addresses I address2 -address1 +1;

three_msbsl I bitand( bitshift(addressi ,-16) , 7);
three_msb82 I bitand( bitshift (address2 ,-16) , 7);

msbs I bitshift(three_msbs2,3) + three_msbs1;

96 Just set the address to allow a maximum number of bits.
addressi I uint16( bitand(addressl, 65535 ) );
addres32 I uint16( b1tand(address2, 65535 ) );

packet11 I bitand( addressl, hex2dec(’00FF’) );
packet21 I b1tshift( bitand( address1, hex2dec(’FF00’) ), -8);

packet12 I bitand( address2, hex2dec(’00FF’) );
packet22 I bitshift( bitand( address2, hex2dec(’FF00’) ), -8);

try , fwrite (s , [msbs hex2dec ( ’ 10 ’) packet11 packet21 . . .
packet12 packet22] , ’ sync ’ );

catch , fwrite (s , [msbs hex2dec( ’ 10 ’) packet11 packet21
packet12 packet22] , ’ sync ’ );

end;

while s.BytesAvailable < 2,
end;

data I fread(s,2);
output I bitshift(data(2,1),8) + data(1,1);

E.12 FPGAReadMemoryBlock.m

NOMwas-I

function output I FPGAReadHemoryBlock( addressi, address2 );

70 Syntax: output = FPGAReadMemoryBlock( address} , addressi! )

%

70 Read a block of the FPGA's memory by specifying two IQ—bit addresses
% where address] <= address2. The result is stored in the array ’output '

global s;

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max_address I hex2dec(’7FFFF’);

if addressl > max_address, %§19—bit addresses
addressl I max_address;

end;

if address2 > max_address ll address2 < addressi, %'19—bit addresses
address2 I addressl;

end;

addresses I address2-address1+1;
hytes_to-read I 2*(addresses);

three_msbs1 I b1tand( bitshift(addressI,-16), 7);
three_msh32 I hitand( bitsh11t(address2,-16), 7);

msbs I bitshift(three_msbs2,3) + three_msbs1;

96 Just set the address to allow a maximum number of bits.
address1 I uint16( bitand(address1, 65535 ) );
address2 I uint16( bitand(address2, 65535 ) );

packet11 I bitand( addressl, hex2dec(’00FF’) );
packet21 I h1tsh11t( bitand( addressl, hex2dec(’FF00’) ), -8);

packet12 I bitand( address2, hex2dec(’OOFF’) );
packet22 I bitshift( hitand( address2, hex2dec(’FF00’) ), -8);

try, fundte(s, [msbs hex2dec(’10’) packetll packet21
packet12 packet22],’sync’);

catch, fundte(s, [msbs hex2dec(’10’) packet11 packet21
packet12 packet22],’sync’);

end;

while s.BytesAva11able < bytes_to_read,
end;

data I fread(s,hytes_to_read);

addr_1ndex I 1;

J ' 1;

while j <- bytes_to-read,
output(addr_index) I bitshift(data(j+1,1),8) + data(j,1);
j ' 3+2:
addr_index I addr-index + 1;

end;

E.13 FPGAWriteMemory.m

omqambwn—

function FPGAWriteMemory( address , value );
% Syntax: FPGA WriteMemory( address . value )
%

% TWis function alhows the value specified in ’value’ to be undtten to the
70FI’GA’s on-board memory at the specified address given in ’address ’.

global s;

max_address I hex2dec(’7FFFF’);

190

 

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if address > max_address, %§19—bit addresses
address I max-address;
end;

addressl I address;
address2 I address;

value I uint16(va1ue);
addresses I address2-addressl+1;

three_msbs1 I bitand( bitshift(address1,-16), 7);
three_mshs2 I hitand( bitshift(address2,-16), 7);

msbs I bitsh11t(three_msbs2,3) + three_nsbs1;

% Just set the address to allow a maximum number of bits.
address1 I uint16( b1tand(addressl, 65636 ) );
address2 I uint16( bitand(address2, 65535 ) );

packet11 I bitand( address1, hex2dec(’00FF’) );
packet21 I bitshift( hitand( address1, hex2dec(’FF00’) ), -8);

packet12 I bitand< address2, hex2dec(’00FF’) );
packet22 I hitshift( hitand( address2, hex2dec(’FF00’) ), -8);

packet3 I b1tand( value, hex2dec(’00FF’) );
packet4 I bitshi£t( bitand( value, hex2dec(’FF00’) ), -8);

try, fundte(s, [msbs hex2dec(’1F’) packet11 packet21 ...
packet12 packet22 packet3 packet4],’sync’);

catch, fundte(s, [msbs hex2dec(’1F’) packet11 packet21
packet12 packet22 packet3 packet4],’sync’);

end;

while s . BytesAvailable <2 ,

end;

data I fread(s,2);
output a bitshift(data(2,1),8) + data(1,1);

E.14 FPGAWriteMemoryBlock.m

@OQQUIAODNH

HHHHHHH
Oiuthb-IO

functhon output I FPGAUriteMemoryBlock( addressl, address2, value );

% Syntax: output = FPGAWriteMemoryBlock( address]. address2. value )

9E

% Write a block of data to the FPO/1's Memory by specifying two IQ—bit addresses
% where address] <= address2, and the value to write.

global s;

max_address I hex2dec(’7FFFF’);

if address1 > max_address, 5% HL—bit addresses
address1 I max_address;

end;

if address2 > max_address ll address2 < address1, % 19—bit addresses
address2 I addressi;

191

"mm _‘ ‘m‘

17 end;

18

19 value I uint16(va1ue);

20

21 addresses I address2-address1+1;
22

23 three_mshs1 I hitand( bitshift(addressl,-16), 7);
24 three_mshs2 I bitand( b1tshift(address2,-16), 7);

26 msbs I bitshift(three-msbs2 ,3) + three_msbs1;
28 % Just set the address to allow a maximum number of bits.
29 address1 I uint16( bitand(address1, 65535 ) );
30 address2 I uint16( bitand(address2, 65535 ) );

32 packet11 I bitand( addressi, hex2dec(’00FI-") );
33 packet21 I hitshift( hitand( address1, hex2dec(’FFOO’) ), -8);

35 packet12 I hitand( address2, hex2dec(’00Fl'-") );
36 packet22 I hitshift( hitand( address2, hex2dec(’FF00’) ), -8);

38 packet?) I b1tand( value, hex2dec(’00FI-") );
39 packet4 I hitshift( b1tand( value, hex2dec(’FF00’) ), -8);

4o

41 try , {write (s , [msbs hex2dec ( ’ 1F ’) packet11 packet21 . . .
42 packet12 packet22 packet3 packet4] , ’ sync ’ );

43 catch , fwrlte (s , [msbs hex2dec( ’ 1F ’) packet11 packet21 . . .
44 packet12 packet22 packet3 packet4] , ’ sync ’ );

45 end;

46 while 3 . BytesAvailable <2 ,

47 end;

48

49 data I fread(s,2);
50 output I b1tsh1ft(data(2.1).8) + data(1,1);

E.15 FPGAWriteMemoryVector.m

function FPGAHriteHemoryVector(addresses , values)
% Syntax: FPGA WriteMemoryVectofladdresses. values)
’ to the addresses
in vector ’addresses ’. Note that both ’valucs’ and

% 'addresses ’ must have the same length.

’70 Write the values in the vector ’values

if length( addresses ) "I length(va1ues),

OOQOMQ-WNH

fprintf(’Vectors "addresses” and ”va1ues” are not of equal 1ength!\n’);
10 return;
11 end;
12
13 tota1_va1ues I length( addresses );
14
15 for 1I1:tota1_values,
16 FPGAWriteMemory(addresses(i),va1ues(i))
17 end ;

E.16 FPGASerialShift.m

192

 

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8 S 3 8 3 m S 3 a 3 3 3 S 3 8 8 fl 8 8 K 8 S 8 8 8 m 3 8 8 2 3 S 8 8 S 3 Z 8 a n E 5 Z 8
BGEQé'iERBQSQéQeQSQéQéSBQSQoVeWBQ

function FPGASerialShift( start_address, end_address );
Syntax: FPG/lSerialSh-ift( starLaddress, end_address );

This function acts as a generic. variable—width, high—speed serial shift

register interface. By storing Is and Os into sequential memory addresses,
this function will instruct the FPGA to load the least—significant bit of
each memory location and put it onto the serial data line.

the start and end addresses away from the last memory location in RAM.
This is because the serial data shifted out from the chip (if present)
will be shifted back into the FPGA and stored in the subsequent memory
locations following the end address. Thus. the total amount of memory
required for this module is 2t(end_address — start-address + 1).

You may then read the appropriate memory locations to check that the
desired serial chain operation is present.

global s;
max_address I hex2dec( ’ 7FFFF ’ );

if start_address > end_address,
fprintf('The ending address must be greater than the starting address!\n’);
return;

elseif (mar_address - end_address) < ( end_address - start_address + 1),
fprintf(’The ending address is too close to the last address in RAM!\n’);
return;

end;

three_msbsl I bitand( b1tshift(start_address ,-16), 7);
three_mshs2 I bitand( bitshift(end-address,-16). 7);

msbs I hitshift(three_msbs2 ,3) + three_msb31;

% Just set the address to allow a maximum number of bits.
start_address I uint16( bitand(start_address , 65535 ) );
end_address I uint16( bitand(end_address, 65535 ) );

packet11 I bitand( start_address, hex2dec(’00FF’) );
packet21 I bitshift( b1tand( start_address, hex2dec(’FF00’) ), -8);

packet12 I hitand( end_address, hex2dec(’00FF’) );
packet22 I bitshi£t( hitand( end_address. hex2dec(’FF00’) ), -8);

try, fwrite(s, [msbs hex2dec(’A0’) packet11 packet21
packet12 packet22] , ’ sync ’ );

catch, fwrite(s, [msbs bex2dec(’A0’) packet11 packet21
packet12 packet22] , ’sync ’ );

end;

while s.BytesAva11ab1e <2,

end;

data I fread(s,2):

E.17 FPGAFunctionGenerator.m

1
2
3

function FPGAFunctionGenerator( channel , type , frequency , gain , offset );
% Syntax: FPGAFunctionGenerato-r( channel, type , frequency, gain , offset );
%

193

Note: The ’end_address ’ cannot be positioned less than the difference between

E
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a
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I4-

 

woodman

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This command sets up the waveforms necessary for function generation. The
parameters may contain the following values:

%

%

%

% channel: 1—4. 9—12. 17—20. 25—28. 33—36 are valid.

%' type: ’sine fl 'square ’ 'sauflooth ’ and ’triangle ’ are valid.
% frequency: < 5kH2 gives acceptable penfinvnance.

% gain: 0 < gain < 1

%' offset: —25 < offset < .5

global s signa1_data;

if gain > 1,
gain I 1;
elseif gain < 0;
gain I 0;

end;

if offset > 0.5,
offset I 0.5;
elseif offset < -0.5,
offset I -O.5;

end;

% Compute the number of cycles to generate desired frequency
cycles I round((frequency‘-1)/((20e-9)*21 + 160t2I20e-9))

dac_num I floor((channe1-1)/8) + 1;
channel_num I channel - (dac_num - 1)I8;

if channel-num > 5,
fprintf(’The channel number (per DAC) cannot exceed 5!\n’);
return;

end;

if strcmp(type, ’sine’),
waveform I uint16(65535*(0.5 + offset) +
65535Igaint(0.5*sin(2*pi*[1:cycles]/cyc1es)));
elseif strcmp(type, ’ square ’) ,
vaveform([1:floor(cyc1es/2)])I uint16(65535*(0.5 + offset) +
65535Igain*0.5*(ones(size([1:f100r(cycles/2)]))));
waveform([(floor(cyc1es/2)+1):cyclesl) I uint16(65535*(0.5 + offset) -
655359gain90.5I(ones(size([(floor(cycles/2)+1):cycles]))));
elseif strcmp(type, ’sawtooth ’) ,
waveform I uint16( 65536IgainI[1:cyclesllcycles +
0.5I65535*(1-gain) + offsett65535 );
elseif strcmp(type, ’triangle ’) ,
waveform([1:floor(cycles/2)]) I
65535Igaint[1:floor(cyc1es/2)]/floor(cycles/2) +
0.5I65535*(1-gain) + 65535*offset;
waveform([(floor(cyc1es/2)+1):cycles]) I
65535Igaint[cycles-floor(cyc1es/2):-1:1]/floor(cyc1es/2) +
0.5I65535I(1-gain) + 65535Ioffset;
else
fprintf(’Invalid waveform type. Setting values to zero.\n’);
waveform I zeros(1,cycles);
end;

FPGAWriteMemory( dac_num, channel_num-1 );

FPGAWriteMemoryVector([6-dac_num+5:5:(Stcycles+5)]. waveform );
FPGASignalGen(1,SIcycles+5);

194

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E.18 FPGASignalGen.m

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function FPGASignalGen( start_address , end_address );

% Syntax: FPGASignalG’en( start-address. end-address );

.%

% This function initiates multi—channel function generation.
95 It will send the start and end addresses where the waveforms
% are stored in memory and will enable the state machine

% in the FPGA that controls continuous reading of these memory
% locations.

global s;

max_address I hex2dec( ’7FFFF ’ );

if start_address > end_address,
fprintf(’The ending address must be greater than the starting address!\n’);

return;

elseif (max_address - end_address) < ( end_address - start-address + 1).
fprintf(’The ending address is too close to the last address in RAM!\n’);
return;

end;

three_msbs1 I bitand( bitshift(start_address ,-16). 7);
three_msbs2 I bitand( bitshift(end_address ,-16), 7);

msbs I hitshift(three-msbs2 ,3) + three-msbs1;

% Just set the address to allow a maximum number of bits.
start-address I uint16( hitand(start_address , 65535 ) )3
end_address I uint16( hitand(end_address, 65535 ) )3

packet11 I hitand( start-address, hex2dec(’00FF’) );
packet21 I bitshift( bitand( start_address , hex2dec(’FF00’) ), -8)3

packet12 I bitand( end-address, hex2dec(’00FF’) );
packet22 I bitshift( hitand( end_address, hex2dec(’FF00’) ), -8)3

try , fwrite (s , [msbs hex2dec ( ’ 90 ’) packet11 packet21
packet12 packet22] , ’ sync ’ );

catch , fwrite (s , [msbs hex2dec ( ’ 90 ’) packet11 packet21
packet 12 packet22] , ’ sync ’ );

end;

195

 

 

APPENDIX F

Floating Gate Testing Code

F.1 KeithleyInit.m

@GQOM‘WBH

HHHrAHHo—H
4¢€8thHO

% Setup the Ketthley 2400 SourceMeter for measurement.
% Cheates serial port object ’s2’ at the desired settings.

global s2;

:2 I seria1(’COH6’);
s2.Tineout I 5;
32.1nputBufferSize I 500000;
32.0utput8uffer8120 I 500000;

set(s2,’BaudRate’,57600,’Parity’,’none’, ’StopBits’, 1, ’Terminator’,’CR’);

fiopen(32);

fprintf(s2, ’UUTP ON’);
fprlntf(82, ’:SENS:FUNC ”CURR"’);

if s2.BytesAvailab1e > 0,
fread(s2,s2.BytesAvailable);
end;

F.2 KeithleyGetCurrent.m

comaauawuu

HI-II-II—l-IHH
amhwnuo

functton output I KeithleyGetCurrent( samples );
% Syntax: output = KeithleyGetCurrenH samples )_:
%

% Return the measured current as floating point value in units of Amperes.
global 32;

for iIlzsanples,
try, fprintf(s2, ’:READ?’);
catch, fprintf(s2. ’:READ?’);
end;
while s2.BytesAvailable < 70,
end;

temp I fecanf(s2);
output(i) I str2num( temp(15:27) );

196

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17

end;

F.3 KeithleySetVoltage.m

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function output I KeithleySetVoltage(voltage)3
% Syntax: output = KeithleySetVoltage(voltage);
%

% Set the voltage of the Sourcehhder.

global 82;
try, fprlntf(s2, [’:SOUR:VOLT:LEV:IHM:AMPL ’ num2str(voltage)])3

catch, fprintf(s2, [’:SOUR:VOLT:LEV:IHM:AMPL ' num2str<voltage)])3
end;

F.4 SVM21nit.m

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uncomqaacn w noomqou-bwnu-o

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000)
coon

%S'VM Chip Version 2 Initialization Script
%
% Last modified: 2007—09—13

gLobal ref integvpbl intengb2 integvnb1 integvnb2 integvref integvcnp;
gLobal integrefcurrent integinvbias gannal ganna2 eeprombias cellbias;
global 1111;

global currentadcoff set;

%Input and Bias Initial lfiflues

ref I 2.0;
%ref = 2.2;
integvpbi I 2.0;
1ntegvpb2 = 1.4;
integvnbl I 1.1;
integvnb2 I 1.7;
integvref I 0.7;
%integvref = 0;
integvcmp I 1. ;
integrefcurrent I 0.65;
integinvbias I 1;
gammal I 0.6;
gamma2 I 0.2;
eeprombias I 1.5;
cellbias I 1.5;
xin I 3.3tones(1,14);

% Ififint the current state of the biases

fprlntf ( ’REF = Z1.4f\n’, ref )3

fprlntf ( ’INTEGVPBI = Z1.4f\n’, integvpbi );
fprintf ( ’INTEGVPB2 . 7.1.4f\n’, integvpr );
fprlntf ( ’INTEGVNBI = Zl.4f\n’, integvnbi )3
fprlntf( ’INTEGVN82 = '/.1.4f\n’, integvnb2 );
fprlntf ( ’INTEGVREF = 7.1.4f\n’, integvref );
fprlntf ( ’INTEGVCMP = Zl.4f\n’, integvcmp );
fprlntf ( ’INTEGREFCURRENT = Z1.4f\n’, integrefcurrent )3
fprintf ( ’INTEGINVBIAS = Z1.4f\n’, integinvbias )3

197

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c.
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fprlntf ( ’GAMHAI = Z1.4£\n’, gamma1 );

fprintf ( ’GAMMA2 I 7.1.4f\n’, gamma2 )3
fprlntf ( ’EEPROMBIAS = 7.1.4f\n’, eeprombias )3
fprintf ( ’CELLBIAS = Z1.4f\n', cellbias );
FPGAInit;

FPGADigitalIO( ’H10’, ’out’, 1); % Integrator Measure
FPGADigita1I0( ’A7’, ’out’, 1); % Integrator Reset

FPGAHriteHenoryBlock(1,5000,0);
%Keithley1nit;

FPGASetBias (33 , integrefcurrent ); % INTEGREI"CURHENT (Pin 14)

FPGASetBias (32 , integvcmp )3 % INTEGVCMP (Pin 13)
FPGASetBias (31 , integvref )3 % INTEGVREF (Pin .12)
FPGASetBias (30 , integvnb2 ); % IN'I'EGVNBZ (Pin 1 1)
”ensues“ (29 . integvnbl ); % [NTEGVNBI (Pin 10)
FPGASetBias (28 , integvpb2 )3 96 IN'I'EGVPBB (Pin 9)
FPGASetBias (27 , integvpbl ); 96 INTEGVPBI (Pin 8)
FPGASetBias (26 , ref ); % REF (Pin 4)
FPGASetBias (18 , integinvbias); % INTEGINVBIAS (Pin 22)
FPGASetBias (17 , gannal )3 % CALHWU (Pin 23)
FPGASetBias (16 , gamma2); % GAMMA2 (Pin 24)
FPGASetBias (15 , eeprombias ); % EEPROMBIAS (Pin 25)
FPGASetBias (14 , cellbias ); % CELLBIAS (Pin 26)

96 Initialize Input Vectors

FPGASetBias(13, xin( 1)); % Pin 27
FPGASetBias(12, xin( 2)); % Pin 28
FPGASetBiasUl, xin( 3))3 % Pin 29
FPGASetBias(10, xin( 4)); %'F5n 30
PPGASetBias( 9, xin( 5)); 96 Pin 31
FPGASetBias( 8. xin( 6)); "a Pin 32
FPGASetBias( 7, xin( 7)); 95 Pin 33
FPGASetBias( 6, xin( 8)); % Pin 34
FPGASetBias( 5. xin( 9)); % Pin 35
FPGASetBias( 4, xin(10))3 % Pin :36
FPGASetBias( 3, xin(11)); % Pin 37
FPGASetBias( 2, xin(12))3 % Pin 38
FPGASetBias( 1, xin(13))3 % Pin 39
FPGASetBias( 1, xin(14))3 % Pin. 40

FPGAReadCurrent(1,1,10)3
currentadcoffset I nunn(FPGAReadCurrent(9,1,20))3
FPGAReadCurrent(1,1,20)3

-F.5 SVM2$electCele

(34:30!wa—

function SVM2SelectCe11( cell )
95 Syntax: SVMZSelectCelH cell )
% Select one of the internal .515 floating—gate cells.

FPGAUriteHemoryBlock(13515.0);

FPGAWriteMemory(cell,1);
VaFPGAWriteMemory(floor((cell -1)/14) + 488.1);

198

 

 

9
10
ll

FPGASerialShift(1,515)3
%FPGASermlS/zift (I .515):
pause(.5)

F.6 SVM2GetCurrent.m

Qwflfiufiwwfi

NNNUNSDNi-IHI—i—wuwi—Hu
~305me Hocmqouewn—o

function output I SVM2GetCurrent(ce11)
Syntax: output 2 SVM2GetCurrent(cell)

Read the (mirrent front a floating-—gate cell and retain: it iii 'output’
while using the on—board current ADC.

J§i§3§3§2§2§

Last modified : 2007-09—13

global eepronbias cellbias;

eepronbias I 3.3;

cellbias I 3.3;

FPGASetBias(15,00prombia3)3 % EEPRONHNHS (Fun 25)
FPGASetBias (14, cellbias ); % CELLBIAS (Pin 26)

FPGAUriteHenoryBlock(1,5000,0)3

SVM2SelectCell( cell )3
pause(.5)
output I FPGAEstimateCurrent(1.20);

eepronbias I 1.5;

cellbias I 1.5;

FPGASetBias(15,eepronbias); % EERROAHHAS (Inn 25)
FPGASetBias (14 , cellbias )3 % CELLBIAS (Pin 26)

F.7 SVM2GetCurrents.m

omflaacnawnon—

nuns-a—
AGND-O

% Yvns script acquires floating-—gate cell currents and stores thflnl'fil the
% variable ’data’

global cellbias;
for i-1:100,

SVM2SelectCe11(i)3
cellbias I 0;

FPGASetBias(14,ce11b1as); % CELLBLdS (Phi 26)
cellbias I 3.3;
FPGASetBias(14,ce11bias); % CELLBLdS (Phi 26)

data(i) I FPGAEstimateCurrent(1,20);
%data(i) = mean(KeithleyGetCurrent (5));
end;

F.8 SVMZSetCurrent.m

199

 

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woomqamawNpaoomqaio-awuwo

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functhon injectionrate I SVM2SetCurrent( cell, value );

% Syntax: injectionrate = SVM2SetC-ur1'ent( cell, value )3
%
% Set the specifunl cell to the targeted current where ’value’ is

9'5 given in Amperes.
global eeprombias cellbias s 32;

cellbias I 0;

FPGASetBias(14,cellbias)3 % CELLBLAS (PHI 26)
cellbias I 3.3;
FPGASetBiaa(14,ce11bias)3 % CELLBDH3(I%n 26)

SVH2SelectCe11(cell)3

injnod I 0;

pulses I 0;

current I nunn(KeithleyGetCurrent(5))

if current < 700-9,
injnod I 0;

elseif current < 1000-9.
injnod I 1;

elseif current < 150e-9,
injnod I 2;

else
injnod I 4;

end;

%Determine injection pulse width modifier

injectionrate(pulses+1,1) I current;
1njectionrate(Pulses+1,2) I 0;

if current < value,
while value > current ,

if current < value - 10e-9,

 

pulsevidth I FPGAInjectPulse(22 - injnod);
elseif current < value - 7e-9,

pulseuidth I FPGAInjectPulse(21 - injuod);
elself current < value - 6e-9,

pulsevidth I PPGAInjectPulse(20 injnod);
elseif current < value - 2e-9,

pulsevidth I PPGAInjectPulse(19 injuod);
elself current < value - 1e-9,

pulsevidth I FPGAInjectPulse(18 injnod);
elself current < value - .5e-9,

pulsevidth I FPGAInjectPulse(17 injnod);
elseif current < value - .25e-9

pulsevidth I FPGAInjectPulse(16 injmod);

else FPGAInjectPulse(15 - injmod);
end;
pulses I pulses + 1;
current I KeithleyGetCurrentCl);
injectionrate(pulses+1,1) I current;
injectionrate(pulses+1,2) I pulseuidth;
If current < 60e-9,
injmod I 0;
elseif current < 100e-9,
injnod I 1;
elseif current < 1506-9,
injnod I 2;
else
injmod I 4;
end;
end;

200

63

65

end;

fprlntf( ’Programmed current in '/.i pulses: '/.1.6f nA.\n’,

pulses, currentt199 )3
pause(0.5)3

F.9 SVMZSetCurrents.m

NOUDUN"

% Script used to equalize an array of floating gates.

value I 35e-9;

for iI3013392,
SVM2SetCurrent(i,value)3
end;

F.10 SVMZInputSweep.m

QQ‘IGUI#WNH

H
O

11

% Last modified: 2007—09—05

global eepronbias cellbias;

eepronbias I 3.3;
cellbias I 3.3;
ganna1 I 2;

FPGASetBias(15,0epronbias);
%FPG/lSetBias (14, cellbias );
%FPGASetBias (l7,gamma1);
SVM2SelectCell(1);

3'1:

for 1-3.3:-.01:1.75,
FPGASetBias(14,0)3
FPGASetBia8(14,3.3);
FPGASetBias(13,i)3

% EEPROMBIAS (Pm 25)
% CELLBIAS (Pm 26)

% CELLBDH;(IHn 26)
95 CELLBIAS (Pin 26)

sveepdata5(j) I nunn(KeithleyGetCurrent(5));

J-J+1:
end;
eeprombias I 1.5;
FPGASetBias(15,eeprombias)3

F.11 SVMZCurrentRampTest.m

wmqmmawwv—

H
O

% Script to set a targeted

set of currents across the array specified in

% 'i’ using the SVMBSetCurrent function. This script has also been used to

% configure other arbitrary
global a 32;

for i-91:100,
%SVM2SetCurrent(i , sin ({

waveforms on— chip.

(i)—90)/10* pi )I.56—9+60€—9).‘

SVH2SetCurrent(i,i*1e-9)3

end;

201

BIBLIOGRAPHY

202

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

BIBLIOGRAPHY

C. Mead and M. Ismail, Analog VLSI Implementation of Neural Systems, Springer,
1989.

A. H. Kramer, “Array-Based Analog Computation,” IEEE Micro, Vol. 16, No. 5,
Oct. 1996, pp. 4049.

R. Genov, G. Cauwenberghs “Charge-Mode Parallel Architecture for Matrix-
Vector Multiplication,” IEEE T. Circuits and Systems II, vol. 48 (10), pp. 930-936,
2001.

R. Sarpeshkar, C. Salthouse, J. Sit, M. W. Baker, S. M. Zhak, T. K. Lu, L.
Turicchia, and S. Balster, “An Ultra-Low-Power Programmable Analog Bionic

Ear Processor,” IEEE Transactions on Biomedical Engineering, Vol. 52, No. 4,
Apr. 2005, pp. 711-727.

J. P. Lazzaro, S. Ryckebusch, M. A. Mahowald, and C. A. Mead, “Winner-Take-
All Networks of O(N) Complexity,” Caltech Computer Science Department Tech-
nical Report, Caltech-CS—TR—21-88, 1989.

R. R. Harrison, J. A. Bragg, P. Hasler, B. A. Minch, and S. P. Deweerth, “A CMOS
Programmable Analog Memory-Cell Array Using Floating-Gate Circuits,” IEEE

Transactions on Circuits and Systems II: Analog and Digital Signal Processing,
Vol. 48, No. 1, Jan. 2001.

P. Hasler “Overview of F loating—Gate Devices, Circuits, and Systems,” IEEE
Transactions on Circuits and Systems II: Analog and Digital Signal Processing,
Vol. 48, No. 1, Jan. 2001.

T. S. Hall, C. M. T wigg, J. D. Gray, P. Hasler, D. V. Anderson, “LargeScale Field-
Programmable Analog Arrays for Analog Signal Processing,” IEEE Transactions
on Circuits and Systems I: Regular Papers, Vol. 52, No. 11, Nov. 2005.

E. Lee and PG. Gulak, “A CMOS Field Programmable Analog Array,” IEEE
Journal of Solid State Circuits, Vol. 26, No. 12, Dec. 1991, pp. 1860-1867.

[10] V. Gaudet and P. G. Gulak, “Implementation Issues for High-Bandwidth Field-

Programmable Analog Arrays,” Journal of Circuits, Systems, and Computers Spe-
cial Issue on Analog and Digital Arrays, World Scientific Publishing, Vol. 8, No.
5—6, 1998, pp. 541-558.

203

[11] M. Kucic, P. Hasler, J. Dugger, and D. V. Anderson, “Programmable and adap-
tive analog filters using arrays of floating-gate circuits,” Proc. of 2001 Conference
on Advanced Research in VLSI, Mar. 2001, pp. 148-162.

[12] LR. Carley, “Trimming Analog Circuits Using Floating-Gate Analog MOS Mem-
ory,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 6, Dec. 1989, pp. 1569—
1575.

[13] Y. L. Wong, M. H. Cohen, and P. A. Abshire, “A Floating-Gate Comparator
With Automatic Offset Adaptation for 10-bit Data Conversion,” IEEE Transac-
tions on Circuits and Systems 1: Regular Papers, Vol. 52, No. 7, Jul. 2005, pp.
1316-1326.

[14] T. S. Hall, P. Hasler, D. V. Anderson, “Field-Programmable Analog Arrays: A
Floating-gate Approach,” 12th International Conference on Field Programmable
Logic and Applications. Montpellier, France. Sept. 2002.

[15] C. J. C. Burgas, “A Tutorial on Support Vector Machines for Pattern Recog-
nition,” Data Mining and Knowledge Discovery, Vol. 2, No. 2, Jun. 1998, pp.
121-167.

[16] E. Osuna, R. Freund, and F. Girosi, “Training Support Vector Machines: An Ap—
plication To Face Dectection,” Proc. Computer Vision and Pattern Recognition,
1997, pp. 130-136.

[17] A. K. Jain, Fundamentals of Digital Image Processing, Englewood, Cliffs, NJ:
Prentice-Hall, 1989.

[18] A. Ganapathiraju, J. E. Hamaker, and J. Picone, “Applications of Support Vec-
tor Machines to Speech Recognition,” IEEE Transactions on Signal Proc., Vol.
52, No. 8, Aug. 2004, pp. 2348-2355.

[19] V. Venkataramani, S. Chakrabartty, and W. Byrne, “Gini—Support Vector Ma-
chines for Segmental Minimum Bayes Risk Decoding of Continuous Speech,” Com-
puter Speech and Language, Vol. 21, No. 3, Jul. 2007, pp. 423—442.

[20] V. Wan and S. Renals, “Speaker Verication Using Sequence Discriminant Sup-
port Vector Machines,” IEEE Tmnsactions on Speech and Audio Processing, Vol.
13, No. 2, Mar. 2005, pp. 203-210.

[21] L. Wang, Support Vector Machines: Theory And Applications, Springer, 2005,
pp.370.

[22] C. E. Priebe, “Olfactory Classification via Interpoint Distance Analysis,” IEEE
Transactions on Pattern Analysis and Machine Intelligence, Vol. 23, No. 4, Apr.
2001, pp. 404-413.

204

[23] G. Xu, W. Tian, Z. Jin, and L. Qian, “Temperature Drift Modelling and Compen-
sation for a Dynamically Tuned Gyroscope by Combining WT and SVM Method,”
Measurement Science and Technology, 18 (2007), IOP Publishing Ltd, pp. 1425-
1432.

[24] P. C. Moster, “Gear Fault Detection and Classification Using Learning Ma-
chines,” Sound and Vibration Magazine, Mar. 2004.

[25] X. Chen, R. Harrison, and Y. Zhang, “Genetic Fuzzy Fusion of SVM Classifiers
for Biomedical Data,” IEEE Congress on Evolutionary Computation, Sept. 2005,
Vol. 1, pp. 654-659.

[26] B. Boser, I. Guyon, and V. Vapnik, “A training algorithm for optimal margin
classifier,” in Proc. 5th Annu. ACM Workshop Computational Learning Theory,
1992, pp. 144-52.

[27] P. Kucher and S. Chakrabartty, “An Energy-Scalable Margin Propagation-Based
Analog VLSI Support Vector Machine,” IEEE International Symposium on Cir-
cuits and Systems, 2007, 27—30 May 2007, pp. 1289-1292.

[28] S. Chakrabartty and G. Cauwenberghs, “Sub-Microwatt Analog VLSI Support
Vector Machine for Pattern Classification and Sequence Estimation,” Adv. Neural
Information Processing Systems (NIPS’2004), Cambridge: MIT Press, 17, 2005.

[29] C. Mead, “Neuromorphic Electronic Systems,” Proceedings of the IEEE, Vol.
78, No. 10, Oct. 1990, pp. 1629-1636.

[30] A. Bandyopadhyay, P. Hasler, and D. Anderson, “A CMOS F loating-Gate Matrix
Transform Imager,” IEEE Sensors Journal, Vol. 5, No. 3, Jun. 2005, pp. 455-462.

[31] Y. L. Wong and P. A. Abshire, “A 144x144 Current-Mode Image Sensor with
Self-Adapting Mismatch Reduction,” IEEE Transactions on Circuits and Systems
I, Vol. 54, No. 8, Aug. 2007, pp. 1687-1697.

[32] W. D. Brown and J. E. Brewer, Nonvolatile Semiconductor Memory Technology,
IEEE Press, 1998.

[33] AMI Semiconductor, “Process Specification Sheet: Process Technology 0.5um,”
2003.

[34] A. Bandyopadhyay, G. J. Serrano, and P. Hasler, “Adaptive Algorithm Using
Hot-Electron Injecton for Programming Analog Computational Memory Elements
Within 0.2% of Accuracy Over 3.5 Decades,” IEEE Journal of Solid-State Circuits,
Vol. 41, No. 9, Sept. 2006, pp. 2107-2114.

205

[35] V. Srinivasan, G. J. Serrano, J. Gray, and P. Hasler, “A Precision CMOS Am-
plifier Using Floating-Gate Transistors for Offset Cancellation,” IEEE Journal of
Solid-State Circuits, Vol. 42, No. 2, Feb. 2007, pp. 280-291.

[36] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Second Edition,
Oxford University Press, New York, 2002.

[37] S. Shah and S. Collins, “A Model for Temperature Insensitive Trimmable MOS-
FET Current Sources,” IEEE Transactions on Circuits and Systems II: Express
Briefs, 2007.

[38] F. Adil, G. Serrano, and P. Hasler, “Offset Removal Using Floating-Gate Circuits
for Mixed-Signal Systems,” Proc. IEEE Southwest Symp. Mixed-Signal Design,
Las Vegas, NV, Feb. 2003, pp. 190195.

[39] H. Spieler, “Radiation Detectors and Signal Processing - VII. Why Things Don’t
Work,” University of Heidelberg, Oct. 2001.

[40] D. L. Jones, “PCB Design Tutorial,” Rev. A, 29 Jun. 2004, pp. 17—18.
[41] Sunstone Circuits, “Material Specifications,” Online, Accessed 4 Oct. 2007.

[42] National Semiconductor Corp, “LM1086 1.5A Low Dropout Positive Regula-
tors,” D3100948, Jun. 2005.

[43] Maxim, “MAX761/MAX762: 12V/ 15V or Adjustable, High-Efficiency, Low Iq,
Step-Up DC-DC Converters,” 19-0201, Rev 0, Nov. 1993.

[44] Texas Instruments, Inc., “UCC27321, UCC27322, UCC37321, UCC37322 Single
9—A High Speed Low-Side MOSFET Driver with Enable,” SLUS504C, Sept. 2002.

[45] Maxim, “MAX1680/ MAX1681: 125mA, Frequency-Selectable, Switched-
Capacitor Voltage Converters,” 19—1247, Rev 0, Jul. 1997.

[46] Texas Instruments, Inc., “OPA743, OPA2743, OPA4743: 12V, 7MHz, CMOS,
Rail-to-Rail I/ O Operational Amplifiers,” SBOS201, May 2001.

[47] Linear Technology Corporation, “LTC2600/LTC2610/LTC2620 Octal 16—/14-
/12-Bit Rail-to—Rail DACS in l6—Lead SSOP,” 2600fa, LT/TP 1103 1K Rev A,
2003.

[48] Linear Technology Corporation, “LT1461 Micropower Precision Low Dropout
Series Voltage Reference Family,” 1461f LT/LCG 0800 4K, 1999.

[49] Linear Technology Corporation, “LTC2414/LTC2418 8-/16-Channe1 24-Bit No
Latency A2 ADCs,” 241418fa, LT1105 Rev. A, 2005.

206

if“ new

 

[50] P. Khairolomour, G. Leung, A. Li, “Precision Programmable Current Sources
Use Digital Pots,” Electronic Design, #9944, 31 Mar. 2005.

[51] Analog Devices, Inc., “REF 19x Series: Precision Micropower, Low Dropout Volt-
age References,” C00371-0—10/ 06(1), Rev I, 2006.

[52] Analog Devices, Inc., “AD7376: +30 V/:l:15 V Operation 128-Position Digital
Potentiometer,” Rev. B, Mar. 2007.

[53] Analog Devices, Inc., “ADG714/ADG715: CMOS, Low Voltage Serially Con-
trolled, Octal SPST Switches,” Rev. B, 2002.

[54] Texas Instruments, Inc., “TLC225x, TLC225xA Advanced LinCMOS Rail-to-
Rail Very Low-Power Operational Amplifiers,” SLOSl76D, Mar. 2001.

[55] Linear Technology Corporation, “LTC2415/LTC2415—1 24—Bit No Latency A2
ADCs with Differential Input and Differential Reference,” sn2415 sn24151fs,
LT/TP 0202 2K, 2001.

[56] Xilinx, Inc., “Spartan-3 FPGA Family: Complete Data Sheet,” D8099 (v2.2),
25 May 2007.

[57] Xilinx, Inc., “Spartan-3 Starter Kit Board User Guide,” UG130 (v1.1), 13 May
2005.

[58] Xilinx, Inc., “Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs,”
XAPP462 (v1.1), 5 Jan. 2006.

[59] Microchip Technology, Inc., “PIC18F2455/2550/4455/4550 Data Sheet,”
DS39632D, 30 Jan. 2007.

[60] Axelson, Jan, USB Complete, Third Edition, Lakeview Research LLC, pp. 28—29,
2005.

207

 

   

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