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IMPEDANCE EXTRACTION MICROSYSTEM FOR
NANOSTRUCTURED ELECTROCHEMICAL SENSOR
ARRAYS

presented by

CHAO YANG

has been accepted towards fulﬁllment
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IMPEDANCE EXTRACTION MICROSYSTEM FOR NANOSTRUCTURED
ELECTROCHEMICAL SENSOR ARRAYS

By

Chao Yang

A DISSERTATION

Submitted to
Michigan State University
in partial fulﬁllment of the requirements
for the degree of

DOCTOR OF PHILOSOPHY
Department of Electrical Engineering

2008

ABSTRACT

IMPEDANCE EXTRACTION MICROSYSTEM FOR NANOSTRUCTURED
ELECTROCHEMICAL SENSOR ARRAYS

BY
CHAO YANG

Electrochemical biosensors transform biochemical reactions into electrical
information through various electrode transducers. With their high sensitivity and
speciﬁcity, electrochemical biosensors are ideal agents to detect many inorganic and
organic substances. Recently, the microfabrication of biosensors has matured to the point
where high density arrays can be generated. A microsystem comprised of such arrays and
an integrated circuit (IC) suitable for sensor interrogation and information extraction
enables the capabilities of electrochemical sensors to be employed in applications that
require miniaturization, including point of care medical diagnostics and distributed safety
and security monitoring. In such a microsystem, the interrogation IC must provide
extremely high sensitivity, to read the weak response from the miniaturized sensors, and
be capable of multi-channel simultaneous readout, to support high density (~100
elements) arrays. This dissertation focuses on overcoming the challenges and limitations
in electronics that impede the development of electrochemical microsystems. Speciﬁcally,
this research targets electrochemical impedance spectroscopy, an essential assay
technique for many sensor interfaces. Several possible architectures for multichannel
impedance spectroscopy were explored in this dissertation. The key functional blocks,
identiﬁed as an impedance extractor and digitizer and a wide frequency range quadrature

signal generator, were designed, tested, and implemented within a prototype biosensor

array system to validate the design. The results of this research pave the way for further
development of ICs for electrochemical sensors and lay a solid foundation for future

implementations of fully integrated electrochemical impedance microsystems.

ACKNOWLEDGEMENTS

Though only my name appears on the cover of this dissertation, a great many
people have contributed to its production. I owe my gratitude to all those people who
have made this dissertation possible and because of whom my graduate experience has

been one that I will cherish forever.

First of all, I would like to thank my advisor, Professor Andrew Mason, for his
support and mentor in my dissertation work. I am grateﬁil for his encouraging to explore
my own during this research. He also gave me tremendous support and understanding for

my family. It was a great experience with Prof. Andrew Mason.

I thank Prof. F ahi Salem, Prof. Shantanu Chakrabartty and Prof. Mark Worden for
serving on my committee, and I appreciate their directions, idea sharing and answering

my questions.

My family always give me unlimited support all the time. My wife, Zhan Fu,
sacriﬁced 3 lot for our family. My parents and parents-in-law also supported me with

their love and aids in many ways. This dissertation is dedicated to them.

Advanced Microsystems and Circuits lab (AMSAC), leaded by Prof. Mason, is a
fantastic team exploring the cutting-edge research. I am proud to be part of it. I am
grateful to Jichun Zhang, Junwei Zhou, William Kun, Yue Huang, Daniel Rairigh,
Xiaowen Liu, Awais Kamboh and other members for their help. It is my pleasure to

know and work with them.

iv

Table of Contents

LIST OF TABLES ............................................................................................................ vii
LIST OF FIGURES ......................................................................................................... viii
1 Introduction ................................................................................................................ 1
l . 1 Motivation ..................................................................................................... I
1.2 Background ................................................................................................... 4
1.3 Research objective and approaches ............................................................ 14
1.4 Thesis outline .............................................................................................. l6
2 Electrochemical Interrogation Methods ................................................................... 17
2. l Potentiostat .................................................................................................. 1 8
2.2 Voltammetric techniques ............................................................................ 19
2.3 Impedance spectroscopy ............................................................................. 20
2.4 Prototype potentiostat microsystem ............................................................ 24
3 System Approaches for a Impedance Spectroscopy Microsystem .......................... 34
3.1 Electrical features of a miniaturized tBLM biosensor ................................ 34
3.2 Techniques to realize on-chip EIS .............................................................. 37
3.3 Proposed biosensor array based EIS microsystem ...................................... 44
3.4 VLSI implementation for the multi-channel EIS system ............................ 58
4 Compact On-chip Impedance Spectroscopy ............................................................ 61
4.1 Integrator design ......................................................................................... 64
4.2 Analog-to-digital convertor ........................................................................ 67
4.3 Analog multiplication for EIS applications ................................................ 68
4.4 Lock-in ADC .............................................................................................. 74
4.5 Synchronization of signals from two clock domains .................................. 79
4.6 Circuit realization ........................................................................................ 80
4.7 Conclusion .................................................................................................. 88
5 Integrated Quadrature Sinusoid Signal Generator ................................................... 90
5.1 Approaches for the sinusoid signal generator ............................................. 90
5.2 Hybrid quadrature sinusoid signal generator .............................................. 95
5.3 Circuit realization ...................................................................................... 106
5.4 Conclusion ................................................................................................ 1 l7
6 Experimental Results ............................................................................................. l 18
6.1 Measurement of the compact IS circuit .................................................... 118
6.2 Measurements of the quadrature sinusoid signal generator ...................... 126
6.3 Biosensor measurement ............................................................................ 132
6.4 Conclusion ................................................................................................ 138
7 Summary and Future Work .................................................................................... 139

V

7.1 Summary of the contributions ................................................................... 139

7.2 Future work ............................................................................................... 140
Appendix. Response of the tBLM biosensor to frequency change ................................. 144
Bibliography ................................................................................................................... 147

vi

LIST OF TABLES

TABLE 3.1. RANGE OF FREQUENCY AND CURRENT RESPONSE ...................... 36

TABLE 5.1, CONFIGURATION OF THE FILTER FOR DIFFERENT OUTPUT
FREQUENCY RANGES ............................................................................................... 101

TABLE 5.2. INPUT SINGAL FREQUENCY SETTINGS FOR DIFFERENT RANGES
OF OUTPUT FREQUENCIES ....................................................................................... 104

TABLE 5.3. THE PARAMETERS FOR THE FILTER DESIGN ................................. 108

TABLE 5.4. THE CLOCK DIVIDER SETTINGS FOR DIFFERENT FREQUENCY

OUTPUTS ....................................................................................................................... 116
TABLE 6.1. PERFORMANCE SUMMARY OF THE LOCK-IN ADC ....................... 126
TABLE 6.2. THE PERFORMANCE SUMMARY OF THE QSSG ............................. 132

vii

LIST OF FIGURES

Figure 1.1. Concept diagram of the biosensor array microsystem, the miniaturized

biosensor array is built on top of the integrated circuit die ................................................. 3
Figure 1.2. Integrated biosensor microsystem. ................................................................... 4
Figure 1.3. Integrated biosensor microsystem. ................................................................... 5
Figure 1.4. Biosensor platform with soluble protein immobilized. .................................... 8

Figure 1.5. Diagram of varieties of proteins that is embedded into or attached with the

cell membrane, source: Wikipedia (without copyright control). ...................................... 10
Figure 1.6. Manmade membrane tethered to the solid surface, protein is embedded ....... 11
Figure 1.7. Electronic system of the impedance spectroscopy. ........................................ 15

Figure 2.1. Simpliﬁed schematic of a typical electrochemical potentiostat system.
Normally three electrodes are employed: a working electrode, a reference electrode and a
counter electrode. .............................................................................................................. 18

Figure 2.2. (a) typical stimulus potential for cyclic voltammetry, (b)cyclic voltammogram.
........................................................................................................................................... 20

Figure 2.3. (a) the input sinusoid waveform and the electrochemical response of a
potentiostat system. The output waveform is still a sinusoid, but multiplied by K with a
phase delay of Ad), (b) bode plot of the system response. ................................................ 21

Figure 2.4. Example of the Nyquist plot of the admittance for a biochemical potentiostat.
........................................................................................................................................... 23

Figure 2.5. An amperometric microsystem comprised of a switched capaitor
amperometric readout block, an electrode potential drive block, and a current switching

matrix (mux). .................................................................................................................... 25
Figure 2.6. Schematic of the two stage ampliﬁer. ............................................................ 28
Figure 2.7. Schematic of the folded cascode OTA. .......................................................... 29

viii

Figure 2.8. Die photograph of the 2.3x2.2mm CMOS chip with surface electrodes and
circuit blocks labeled. ....................................................................................................... 30

Figure 2.9. The testing setup for the biosensor microarray based on-chip platform. ....... 31

Figure 2.10. Cyclic voltammogram of secondary alcohol dehydrogenase modiﬁed
electrodes in 5, 15 and 25 mM 2-propanol in 0.1M PBS, at 25 ° C and lOOmVs'l scan rate,
vs. Ag/AgCl reference electrode. ...................................................................................... 32

Figure 2.11. Oxidation peak values VS. 2-propanol concentration levels ........................ 32
Figure 3.1. (a) structure of the tBLM biosensors and (b) their equivalent circuit mdoel. 34

Figure 3.2. The EIS output of tBLM biosensor with an area of 0.1cm2, with two sets of
RM’s mimicking sensing the analyte with different concentration. (a) shows the output on
a Bode plot, (b) shows the EIS output on a Nyquist plot with RM=500KQ , (c) shows the
EIS output on a Nyquist plot with RM=50KQ. The Bode plot shows that the frequency
range of interest is at low frequencies ............................................................................... 37

Figure 3.3. The principle block diagram of F F T based EIS system. ................................ 38

Figure 3.4. Block diagram of frequency response analyzer based impedance.
Spectroscopy. .................................................................................................................... 40

Figure 3.5. Equivalent circuit model for tBLM biosensor. ............................................... 46
Figure 3.6. The DC and double frequency AC interference in the integrator output. ...... 47

Figure 3.7. The principle block diagram of the fast interrogation EIS system: (a) the
conﬁguration to produce the real portion of the admittance, (b) the conﬁguration to
produce the imaginary portion of the admittance. ............................................................ 48

Figure 3.8. The principle block diagram of the fast EIS microsystem. ............................ 49

Figure 3.9. Output relative error versus the different levels of mismatch in amplitude and
phase of two identical biosensors, and the equivalent resolution in terms of digital
presentation. ...................................................................................................................... 50

Figure 3.10. Magnitude and phase changes due to a change of up to 20% in component
values found in the tBLM biosensor circuit model. The base values for the components
are Rm=50KOhms, Cm=0.5uF and Cdl=5uF. .................................................................. 51

ix

Figure 3.11.The principle block diagram of the multi-channel EIS microsystem ............ 56
Figure 3.12. A plot of the real and imaginary admittance of a tBLM biosensor model... 57

Figure 4.1. The lock-in ADCs extract and digitize the impedance information of a

biosensor. .......................................................................................................................... 61
Figure 4.2. Block diagram of the biosensor array based microsystem. ............................ 63
Figure 4.3. Functional block diagram of the proposed EIS system. ................................. 64
Figure 4.4. Simple integrator circuit. ................................................................................ 65
Figure 4.5. The mixed mode integrator diagram. ............................................................. 66

Figure 4.6. The subthrehold multiplier: (a) Gilbert subthreshold CMOS analog multiplier,
(b) CMOS translinear principle based multiplier .............................................................. 69

Figure 4.7. A simpliﬁed chopping circuit, Y is a current input, X is large square-wave

signal. ................................................................................................................................ 71
Figure 4.8. Multiplication integrator ................................................................................. 73
Figure 4.9. Block diagram of the lock-in ADC based IS system ...................................... 74

Figure 4.10. Waveform of the compensation current control signal (D and D* in Figure
4.9), for D and D* are low on the ﬂipping of the capacitor .............................................. 77

Figure 4.11. Block diagram of the control block, which generates the updating clock and
the chopping control signal. An XOR gate is used to generate a pulse covering the edge
of the chopping clock. This pulse will block the change on the updating clock through
gating the clock of DFF4 and therefore avoiding conﬂict between the chopping signal
and the updating clock. ..................................................................................................... 80

Figure 4.12. Folded cascade op-amp circuit designed for the lock-in ADC system. ....... 81

Figure 4.13. AC simulation of the ampliﬁer in Figure 4.12. ............................................ 82
Figure 4.14. Circuit schematic of a dual-level comparator. .............................................. 83
Figure 4.15. The input voltage DC sweep of the dual level comparator. ......................... 83

Figure 4.16. Schematic of the new up/down counter with shift register capability .......... 85

Figure 4.17. Waveform of the control signals for the proposed bidirectional

counter/shifter. .................................................................................................................. 85
Figure 4.18. Block diagram of the scalable up/down counter. ......................................... 87
Figure 4.19. The layout of the lock-in ADC (600nm X IOOpm). .................................... 87

Figure 4.20. The simulation waveforms of some signals in the lock-in ADC system. The
input sinusoid stimulus frequency is lkHz. ...................................................................... 88

Figure 5.1.The block diagram of the variable clock based digital domain signal generator.
........................................................................................................................................... 91

Figure 5.2. The block diagram of the direct digital synthesis based signal generator. ..... 92

Figure 5.3. The principles of a triangle-to-sine signal generator: (a) transformation from
triangle waveform to sine waveform, (b) a typical circuit to perform the transformation.
........................................................................................................................................... 94

Figure 5.4. The principle structure for the proposed quadrature signal generator. ........... 96

Figure 5.5. Example of a resistor chain based DAC working as sinusoid signal generator
(oversampling ratio is 14), (a) the sampling points in a sinusoid waveform; (b) the
structure of a DAC with an unevenly tapped resistor chain. ............................................ 97

Figure 5.6. Architecture of a resistor chain DAC based qudrature sinusoid signal
generator. .......................................................................................................................... 97

Figure 5.7. The spectrum of an R-chain DAC. The envelop is a rectiﬁed sinc function, the
frequency is normalized to the sampling frequency, and the output amplitude is

normalized to the signal strength. ..................................................................................... 98
Figure 5.8. Linearity versus oversampling ratio for the DAC’s output. ......................... 100
Figure 5.9. Concept of sub-sampling techniques. ........................................................... 104
Figure 5.10. The block diagram of a sub-sampling system. ........................................... 104
Figure 5.11. A circuit for an R-chain DAC for a signal generator. ................................ 106

xi

Figure 5.12. Schematic of the gm-C biquadratic ﬁlter. ................................................... 108

Figure 5.13. OTA with a small gm (two level tunable). The signal S selects the gm level.
......................................................................................................................................... 109

Figure 5.14. OTA with a small gm. ................................................................................. 111

Figure 5.15. (a) transfer function and (b) the linearity of the variable ﬁlter with cut-off
frequency of 200KH2 ...................................................................................................... 112

Figure 5.16. (a) Transfer function and (b) linearity of the variable ﬁlter with a cut-off
frequency of ZOKHz ........................................................................................................ 112

Figure 5.17. (a) Transfer function and (b) the linearity of the variable ﬁlter with a cut-off
frequency of 2KHz .......................................................................................................... 113

Figure 5.18. (a) Transfer function and (b) the linearity of the variable ﬁlter with a cut-off

frequency of 250Hz ......................................................................................................... 113
Figure 5.19. Circuit of the sub-sampling quadrature sinusoid signal generator. ............ 114
Figure 5.20. The clock divider circuit ............................................................................. 115

Figure 5.21. The original signal leaks out to the output through the tracking window. . 115
Figure 5.22. The token ring based switch network’s control signal generator. .............. 116
Figure 5.23. The layout of the quadrature sinusoid signal generator. Its size is lmm2.. 117
Figure 6.1. Die of two lock-in ADCs .............................................................................. 118
Figure 6.2. Experiment setup for the lock-in ADC ......................................................... 119

Figure 6.3. Phase vs. output with an input sinusoid of (a) 30nA amplitude @IKHz and (b)
1.4nA@101-Iz. ................................................................................................................. 121

Figure 6.4. The lock-in ADC’s amplitude transfer performance with respect to 8—bit
digitization: (a) DNL, (b) IN L. ....................................................................................... 123

Figure 6.5. Amplitude conversion characterization for the zero phase sinewave input. The
lock-in ADC is conﬁgured to accommodate a wide range of input signals. .................. 124

xii

Figure 6.6. Experiment setup for verifying impedance extraction. ................................ 125

Figure 6.7. The real and irnagineary coefﬁcients of current response from the setup in
Figure 6.6. The test result and theoritical expectitations are given for comparision. ..... 125

Figure 6.8. Die photo of the quadrature sinusoid signal generator. ................................ 126
Figure 6.9. Experiment setup for the ﬁlter testing. ......................................................... 127
Figure 6.10. Experiment setup for the signal generator testing. ..................................... 128

Figure 6.11. Measured frequency response of the ﬁlters on the signal generator chip. . 129

Figure 6.12. Output spectrum for a lOOHz sine input with a 450mV amplitude for (a) a
tunable ﬁlter and (b) a ﬁxed ﬁlter. .................................................................................. 129

Figure 6.13. Waveform of quadrature sinusoid output at two extreme frequencies, (a)

lmHz and (b) lOKHz. ..................................................................................................... 130
Figure 6.14. The phase mismatch between the output quadature signals. ...................... 131
Figure 6.15. The amplitude mismatch between the output quadature signals. ............... 131

Figure 6.16. Spurious free dynamic range (SF DR) of the output (450mV amplitude). . 131
Figure 6.17. The experiment setup for the real biosensor impedance extraction. .......... 133
Figure 6.18. Impedance of monolayer and tBLM: (a) magnitude, (b) phase. ................ 135

Figure 6.19. Impedance of monolayer, tBLM and gramicidin modiﬁed tBLM, (a)
magnitude, (b) phase. ...................................................................................................... 137

Figure 7.1. Proposed electronic system for the impedance spectroscopy biosensor array
based microsystem. ......................................................................................................... 142

xiii

1 Introduction

1.1 Motivation

Electrochemical biosensors [l] are composed of biological element and a sensing
element (transducer). They transfer biochemical reaction information into electrical
information through the coupling of their two elements. Electrochemical biosensors could
be glucose, deoxyribonucleic acid (DNA), proteins, hormones, or even micro-organisms.
With their high sensitivity and sensing target speciﬁcity, electrochemical biosensors are
ideal agents to detect many varieties of inorganic or organic substances [2]. A wide range

of applications can be found based on the assay of inorganic or organic substances.

A personal blood glucose monitoring device is a very successful and practical
application of biosensors. Blood glucose biosensors beneﬁt 20 million diabetes patients
[3] in the US. Biosensors can also be used to diagnose diseases. For example, Wang [4]
has developed electrochemical biosensors that quantify the degree of HIV infection. It
was estimated that medical biosensor-related products would reach 7 billion US dollars in
2004, and grow at a rate of 9.7% until 2008 [5]. Biosensor arrays provide a very efﬁcient
way to perform drug screening in pharmacology research[6, 7]. In security, biosensors
are useful to sense bio-toxins and biological warfare agents[8]. In environmental related
areas, biosensors can be used for on-site monitoring of water, air, waste processing and
soil[9, 10]. Furthermore, biosensors can speed up food testing and greatly promote public

food safety in the food industry.

To date, the microfabrication of biosensors is maturing to the point where high

density arrays are being, or will soon be, generated. These arrays provide tremendous

advantages. 1) The miniaturized elements increase the detection sensitivity and require
smaller amounts of reagents for the analysis, which leads to lower costs. 2) By having
large numbers of detection sites and integrating various functionalities, biosensors arrays
provide massively parallel sensing capability. 3) The miniaturized biosensor array
provides more ﬂexibility in real application due to its small physical size. Traditional
expensive and bulky bench-top instruments limit the capability and performance of
sensor arrays because long electrical cabling introduces a signiﬁcant amount noise and

interference on the small signals generated from miniaturized biosensors.

To maximize the beneﬁt of the miniaturized biosensor arrays, a microsystem built
with these arrays and their interrogation integrated circuit is necessary. Following
Moore’s Law [11] for more than 30 years, integrated circuit technology can provide
powerful information acquisition and signal processing capability within a tiny silicon die.
Its low cost and small size leverage the advantages of a biosensor array. With the rapid
progress in CMOS circuit compatible biosensor fabrication techniques [12-14], these
arrays can be put directly on top of a silicon integrated circuit to form a fully integrated
biosensor microsystem. A conceptual structure for such a system is shown in Figure 1.1.
This microsystem can be applied in many areas, such as medical diagnostics [5],
pharmacology research [6], security enhancement [8], environmental protection [10], and

others.

In order to exploit these advantages, some technical challenges must be overcome.
These challenges span over a broad range of disciplines, including the microfabrication
of the biosensor, electrode construction and electronics design. For the electrical system,

it is not just the miniaturized copies of the bench-top instruments. In conventional

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Figure 1.1. Concept diagram of the biosensor array microsystem, the miniaturized
biosensor array is built on top of the integrated circuit die.

biological analysis platform, the highest performance instruments are always used,
ensuring that the measurement is not limited by the detection system. The performance of
the integrated electronics in the biosensor microsystem is limited by the available
hardware resource on the silicon die. Moreover, the lower response level of the
nano/micro-scale biosensors requires the interface electronics to be more sensitive than
bench-top instruments. The electrical system level innovation is also necessary to support
the in-parallel interrogation of the large biosensor array. Overcoming the challenges and
limitations on the electronics for the microsystem will make a powerful propellant for the

adventures leading to the fully integrated electrochemical biosensor microsystem.

This dissertation presents the realization of the integrated electrical system for the
biosensor microsystem based on the understanding of the features of biosensor arrays and

their electrical interface needs. The focus is the impedance spectroscopy (IS)

interrogation based electrical systems for biosensor array readout. To overcome all above

mentioned challenges, creation is needed at both circuit and system level.

1.2 Background

1.2.1 Integrated biosensor microsystems

To date, the microfabrication of biosensors is maturing to the point where high
density arrays are, or will soon be, available. Research on miniaturization of biosensors
started in the 1990’s with a microarray on a glass chip for DNA sequencing [15]. During
the same time period, on-silicon chip microelectrode design also made progress[12, 14].
In recent years, some label-free and reusable biomimetic biosensors have been built for
electrochemical applications [16-18]. As stated in the motivation section, these
miniaturized biosensor arrays provide tremendous advantages. To fully realize these
advantages, a microsystem that combines the biosensor microarray and miniaturized
interrogation instruments is desired. The conceptual block diagram of such a system is

shown in Figure 1.4. Biological recognition element inside the microsystem gathers the

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Figure 1.2. Integrated biosensor microsystem.

bio-related information through various reactions with testing environment, and the
instrument (transducer) translates inside bio-information into a meaningful forms for end
users. Optical analysis based biosensor integration systems are currently in widespread
use[l9, 20], but they require extensive external equipment. Electrochemical biosensors
are considered to be one of the most promising technologies for the next generation of
high-performance biosensors because of their inherent scalability and their cost-

efﬁciency in terms of fabrication and detection reagents.

Practically, an integrated electrochemical biosensor microsystem consists of
biosensor arrays, interface electrodes, and electrical circuits for interfacing and post
signal processing. To increase the reliability of the system and minimize the interference
from outside and among different elements, biosensor arrays and electrodes should be
built on the top of the silicon chips where the electrical circuit system is built. Figure 1.3
shows a conceptual structure for the microsystem. Some CMOS fabrication compatible

processes have been developed for this purpose[12]. Electrodes are always built with

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solid metal, like aluminum or gold. They provide the bases for the formation of the
biosensors and bridge between the electrochemical biosensor and electrical circuitry.
Electrode size determines the biosensor size. Accordingly, smaller electrode arrays are
required to match the miniaturized biosensor array elements. The dimension of a
miniaturized electrode could reach 50um[13]. In some situations, multi-analytes and
samples need to appear at different sensor elements, so microﬂuidic channels are needed
to conduct analytes to individual biosensors[l2]. The electrical circuit in the integrated
biosensor microsystem plays several roles. First, it supports the potentiostat system for
each biosensor elements. Second, it generates and applies the proper stimulus signal for
different interrogation methods. Third, it processes the potentiostat results. Normally the

potentiostat response is conditioned ﬁrst [21].

1.2.2 Label-free and reversible electrochemical biosensors

To provide background information for this dissertation research, some potential
biosensor elements that are compatible with goals of this research are discussed.
Biosensors [l] are devices utilizing biological reactions or binding events to
quantitatively or semi-quantitatively identify biological-relevant analytes. There are two
fundamental elements in biosensor devices: biological recognition elements (abbreviated
as BRE), which are biochemical probes, and transducers, which transfer the biochemical
information from the BRE to measurable information, such as electrical signals, optical
signals, acoustic waveforms or other forms. Electrical information is preferable to others
because it is easier to interface to a computer for processing. Electrochemical
procedures[22-25] are involved in the conversion of the biological information to

electrical information.

Some biosensors need preprocessing to label the analytic species before sensing.
Those labels turn out to be the real detecting target after binding happens. The sensing
procedure for some biosensors is non-reversible, which means the sensors need to be
replaced frequently. For a biosensor array, these labels and non-reversibility will result in
the waste of the unused and reusable sensor elements. These limitations even make the
sensing impossible in some situations, such as implanted sensing devices, battle ﬁeld

sensing devices and portable ﬁeld biosensor devices.

DNA-based biosensors are popular biosensors available for a real application. DNA
biosensors use afﬁnity mechanisms to bind the targeted molecules. This kind of biosensor
needs preparation of the analytes to attach the ﬂorescent or electrochemical labels for the
optical[26] or electrochemical[27-29] readout. Also, the sensing procedure is irreversible
because once the DNA couples are formed between sensing elements and target
molecules this binding can not be broken without destroying the DNA sequence.
Antibodies[30-33] can serve as the immunoassay based BRE too. They also rely on the
afﬁnity mechanism between antibodies and antigens. Each antibody recognizes a unique
antigen [34]. In the human body, this precise binding (afﬁnity) mechanism allows an
antibody to label a microbe or an infected cell to initiate an attack by the other parts of
the immune system, or to directly neutralize its target (i.e. by blocking a part of a microbe
that is essential for its invasion and survival). However, during this attachment process,
the binding between the antibody and antigen is so tight that antibody can not come off in
a time frame that allows reuse. Therefore, antibody biosensors are also irreversible

SCI'ISOI' S.

Some protein BREs provide very efficient, speciﬁc and selective recognition with
good stability and reversibility and without pre-tagging of target species, i.e., label-ﬂee.
Based on the natural state of these proteins in living organisms, they are categorized as
soluble protein and membrane protein. Soluble proteins are dissolved in the liquid

cytoplasm of cells. Membrane proteins are attached to, or associated with, the membrane

. Aqerus
: , - Enviomment
protein

"‘ ~1nm

       

  

1“ tethering Y
i Q... I I ‘ molecule p .,

“i ., 3, ,. .»golq;electr0de‘i'.-~_,

(*0
Enzyme
2e-
@ ‘ Cofactor
2e

 

[ Gold electrode l

 

(b)

Figure 1.4. Biosensor platform with soluble protein immobilized.

of a cell or an organelle.

1.2.2.1 Soluble protein based biosensors

Many enzymes ﬂow within the liquid environment inside cells. They catalyze (i.e.
accelerate) chemical reactions. Like as other catalysts, enzymes are not consumed by the
reactions they catalyze. Enzymes are much more speciﬁc than other catalysts, making
well suited as biosensors. Enzymes can detect the existence and concentration of speciﬁc
molecules by using a transducer to monitor the reaction rate. Because enzymes are not
consumed during the reaction, enzyme-based biosensors are re-usable and can provide
reproducible results. As a result, enzymes[35-38] are the most commonly used BREs in

protein based biosensors.

Soluble proteins are commonly made immobilized on the electrochemical
biosensors. As shown in Figure 1.4(a), some tethering/linking molecules are employed to
anchor the soluble protein to the electrode [39]. Enzymes are always involved in charge
transformation, and linking molecules (Figure 1.4. (b)) can be used to transfer this charge
onto an electrode. Thus, enzyme activities can be monitored by reading the electrical

current on the electrode.

1.2.2.2 Membrane proteins

In contrast to the soluble proteins, membrane proteins are attached to, or embedded
in, the cell membrane or attached to the surface of it. Cell membranes are composed
primarily of a bilayer lipid membrane (BLM), which provides several nanometer-thick

insulating barrier between cellular compartments. A diverse set of membrane proteins

impart speciﬁc functionalities to precisely control molecular—level transport and signaling.

Figure 1.5 shows a conceptual diagram of the cell membrane and a diverse set of proteins.

Because many membrane processes either have an electrochemical basis or can be
coupled to electrochemical processes, an electrochemical platform is ideally suited to
both measure and control membrane phenomena. It is possible to build electrochemical
biosensors with membrane proteins[40]. Some techniques only manipulate single cells
and test the electrochemical features of the cell membrane[41]. However, the complicated
cell manipulation process makes it hard to use, and availability of the cell membrane
protein limits the variety of the protein types. Alternatively, membrane proteins can be
embedded into artiﬁcial membranes to form a bio-mimetic interface[42]. The membrane
protein based biosensor could be built by attaching the artiﬁcial membrane to the

biosensor platform, as shown in Figure 1.6.

Protein channel Extracellular Fluid
. sport protein) .

    

Phospholipld
bilayer

Cytoplasm

Figure 1.5. Diagram of varieties of proteins that is embedded into or attached with the
cell membrane, source: Wikipedia (without copyright control).

aqueous samples ,

"o ”Li~oo¢§¥

aanana. \Anhﬂn
95000000000000... “Wd
. Totem bilayer

r9ooccoooooooooogc

1;; . c». ..

1
“
i

I/ 1.3.1; I. "arenﬁ’ (I; i binding
7 I I {1” "T" I Kr, [ layer
solid support electrode (WE) .

Figure 1.6. Manmade membrane tethered to the solid surface, protein is embedded.

1.2.2.3 Nanostructured bio-interface

The nanostructured biomimetic interfaces can be thought to be an artiﬁcial cell
membrane. Living cells carry out many vital processes using cell membranes that consist
mainly of lipid bilayer and membrane proteins. These functions can be reproduced in the
laboratory using biomimetic interfaces, whose structure mimics that of a cell membrane.
Since the thickness of lipid bilayers and proteins is about 5mm, research on biomimetic
interfaces represents an integration of Biotechnology and Nanotechnology. The
nanostructured biomimetic interfaces provide pseudo-natural environments for the
membrane proteins. Comparing with the real cell membrane, the synthetic interface can
be embedded with more types of protein. With is thickness in the same dimension as
proteins, these interface make is possible to study the properties of single protein. This
interface features fast response and high sensitivity and therefore are good biosensor
candidature. Furthermore, they are feasible to be integrated for multiparameter biosensor
array valuable for healthcare, biomedical research, environmental monitoring, etc. They

are the prototype biosensors for this dissertation works. Chapter 3 will detail their

11

characterization. The nanostructured biomimetic interfaces have high sensitivity but their
response signal is very weak. The interrogation electronics muust provide very high

sensitivity level in order to extract the biomimetic interface information from a weak

signal.

1.2.3 Electronic interrogation systems

Traditional bench-top instruments limit the capability of biosensor arrays. They
support only one biosensor elements at a time and can not provide a low cost solution for
array based multi-channel measurement. Further more, complicated setup of these
instruments limits their application for biosensor arrays outside laboratories. Thus, with
the miniaturization of biosensors and electrodes, compact interrogation electronics have
to be developed. Early efforts in this area have yielded an ion-sensitive ﬁeld effect
transistor (ISF ET) arrays in CMOS compatible processes [43, 44], where the biochemical
activities of biosensor controls the gate potential of F ET transistor and convert the bio-
inforrnation to electric channel current change. A hybrid microsystems that combine the
traditional optical based method and electrical systems [45] was developed by bridging
the optical information and electric one with CCD sensors. Potentiostat, which bridges
the electrochemical sensors with electric interrogation system, is a necessity for a real
electrochemical biosensor interrogation system, and on—chip potentiostats have been
developed [46, 47] for compact electrochemical instruments to interface with biosensor
array [13, 48], record neural signal [49]. Miniaturized front end electrodes and circuits
that digitize results have been integrated with a potentiostat [50] to promote the
integration level of the microsystem. However, all of the above only constructed a basic

interface for the biosensors; the responses of the sensors were analyzed outside of the

12

microsystem. They have limitations for the interrogation of a large array of biosensors,
especially for an impedance spectroscopy system, where a signiﬁcant amount of raw data
is generated from every sensor element. Thus, a high throughput data path and lot of
hardware resources are required to send out this raw information. These solutions are
nearly impossible for interrogation on an entire array in parallel. Some impedance
spectroscopy systems were also built for biomedical and biochemical measurements [51-
53] but do not include integrated circuits. Therefore, they are not suitable for an array
based application. At the time of writing, no publications on stand-alone impedance

spectroscopy microsystems supporting sensor array can be found.

1.2.4 Challenges of the biosensor microsystems

As a hybrid system, there are many challenges in different aspects, like the
microfabrication of biosensors, electrode building and electrical system design. The focus
of this thesis is the electrical system of the integrated biosensor array microsystem. In
conventional biological analysis platforms, the highest performance instruments are
always used, ensuring that the measurement is not limited by the detection system.
Unlike these conventional systems, in miniaturized platforms the performance could be

limited by the integrated instruments —- namely, an on chip electrical circuit system.

As the biosensor elements in the array scale down, their sensitivity will increase,
but their response signal level also becomes smaller. The on-chip electronics in the
microsystem should be able be capture these weak response signals from a biosensor. The
most important feature of the integrated biosensor array is the large amount of sensing
elements. Parallel interrogation is expected in order to exploit this advantage. These

parallel operations for the large sensor array require a large amount of signal processing

13

tasks, especially for an electrochemical impedance spectroscopy (EIS) system where
complicated signal processing is needed to extract the impedance information. In the
traditional method, the potentiostat result is processed by some device with powerful
computation capability, such as a digital signal processor (DSP) or computer. It is
impossible to instantiate computational devices for each channel due to its physical size.
It is also hard to process the sensor array result by a centralized computational device;
even a high performance digital signal process can not handle this heavy work load for
the large sensor array. The throughput capability of the data channel transferring the
original data out could also be a problem for the large sensor array. The solution to this
problem is distributing the computation into an individual channel with a compact size
analog circuit. How to design such a compact size analog circuit to realize the required
computation with the expected performance is a challenge for the electrical system. To
enhance the ﬂexibility and lower the measurement cost, the stimulus generator is
expected to be integrated to provide a standalone system. Different interrogation
techniques need different types of stimulus. Thus, a compact size stimulus generating

circuit with ﬂexible waveform is another challenge.

1.3 Research objective and approaches

In this research, an electrical system for a miniaturized, tagless and reusable
biosensor array microsystem was developed. The focused interrogation method is
impedance spectroscopy. The proposed electrical system includes a sinusoid stimulus
generator, impedance spectroscopy circuit and a digitization circuit to provide digital
output to facilitate data transmission for parallel interrogation. Conceptually, the

electrical system for an EIS microsystem is shown in Figure 1.7. Currently, there are no

14

biosensor$

IIIIIIIIIIIIIIIIIIII
O

Signal ’\/V‘ |__iS'N Impedance 'ma X0
Generator Spectroscopy reagl((Xo))

electrical system

 

 

 

 

Figure 1.7. Electronic system of the impedance spectroscopy.

publications regarding the realization of channel level signal processing for multi-channel
EIS systems. For an EIS application, the sinusoid stimulus signal is needed over a wide
frequency range (lmHz to lOkHz). Again, there are no publications reporting a sinusoid

signal generator for such a wide frequency range.

This research will ﬁrst develop a feasible electrical system solution for the
biosensor microsystem. Based on this system-level solution, the signal generator and
impedance spectroscopy blocks will be designed and fabricated with individual integrated
circuits to verify the feasibility of the VLSI realization of this electric system. For the
prototype design, a tethered bilayer lipid membrane protein biosensor [42] was selected
to deﬁne the speciﬁcations for the electrical system. All the individual functional circuit
blocks will be tested with a fabricated chip. Furthermore, the impedance spectroscopy

circuit will also be tested with the real biosensor or biomaterial.

Biosensor microsystem design is complicated and multi-disciplinary work,
involving research on integrated electrical systems, microfabrication of electrodes and the
development of miniaturized biosensors. Thus, the fully integrated biosensor array

microsystem is outside the scope of this thesis. The research in this dissertation will

15

provide a solid knowledge and technology basis for the future development of a fully

integrated microsystem.

1.4 Thesis outline

Chapter 2 describes popular electrochemical interrogation methods and prototype
microsystem realization. Chapter 3 discusses the requirements for the biosensor array
impedance spectroscopy (IS) microsystem and some feasible system level approaches for
the electrical portion. Based on the conclusion of the system approach in Chapter 3,
Chapter 4 describes the development and VLSI realization of a channel level compact
impedance spectroscopy circuit (an impedance digitizer). In Chapter 5, a wide frequency
range quadrature sinusoid signal generator, which covers frequencies from 1 mHz to
lOkHz, is developed and implemented in VLSI. The testing results for the many VLSI
realizations required for a multi-channel EIS system are provided and discussed in
Chapter 6. In the ﬁnal chapter, both the summary of this dissertation work and

suggestions for future research in this area are provided.

16

2 Electrochemical Interrogation Methods

In the biosensor, while BREs actually capture biological information, transducers
are required to convert the biological information into measurable form so that further
processing on the information can be performed. This measurable information can
include electrical signals, optical signals, acoustic waveforms and other forms. Electrical
information is preferable to others because it is easier to interface with and be processed
by the computer. Electrochemical procedures[22-25] are ideal to produce the electrical
result. Basically, all sensing procedures in electrical biosensors have the following
generalized steps. 1) The analytic species appears in the reaction chamber (normally a
speciﬁc buffer solution) and collides with the BREs. 2) The targeted analyte and the
probe form bio-chemical bonds, which change certain electrochemical properties of the
biosensor. 3) The transducer translates this electrochemical property change and
translates this to observable quantities electrochemically. To sense the electrochemical
feature change, an electronic signal is required to stimulate the biosensor. The electrical
response from the biosensor carries electrochemical property information. A potentiostat
works as the bridge between the electronic system and the biological system during this
procedure. Some electrochemical measurement techniques are developed on top of the
potentiostat to extract different information with a speciﬁc stimulus. The potentiostat
system and popular electrochemical interrogation methods will be studied in this chapter.
In addition, a prototype voltammetry microsystem built to study the electronics systems

for the microsystem will be discussed.

l7

2.1 Potentiostat

While there are many electrochemical interrogation methods, they are all based on
the potentiostat. In amperometric operation, the potentiostat applies a voltage with a
predeﬁned shape to a biosensor and monitors the current response. A typical potentiostat
in the electrochemical domain is illustrated in Figure 2.1. Electrodes are solid contacts
built with metal or semiconductor. They provide the interface between chemical reaction
and electrical system. According to the function of the electrodes, they are classiﬁed as
working electrode (WE), reference electrode (RE) and counter electrode (CE). The
potentiostat measures the voltage-to-current (VI) response. We can apply the voltage
between two electrodes (i.e. WE and RE in Figure 1.3) and monitor the current ﬂow
between them. Normally, three electrode potentiostats are widely used with the RE put as
close as possible to the WE. With the feedback system built with an ampliﬁer connecting

RE and CE, the potential of RE is ﬁxed to the reference (analog ground) potential. RE

 

 

WE: Working Electrode

   

 

RE: Reference Electrod

 

Vohage

Source CE: Counter Electrode

 

 

 

 

 

Figure 2.1. Simpliﬁed schematic of a typical electrochemical potentiostat system.
Normally three electrodes are employed: a working electrode, a reference electrode and a
counter electrode.

18

does not draw current because of the very high input impedance of the ampliﬁer.
Therefore, the potential in the solution around the CE is the same as the RE and ﬁxed to
the reference potential. A three electrode potentiostat system has several advantages over
its two electrode counterpart. First, it provides very accurate potential control between the
WE and the surrounding solution where electrochemical reactions occur on the interface
in response to the potential difference. Secondly, in-series solution resistance can be
minimized to the point of becoming negligible through placing the RE very close to the
WE. In real applications, some systems have more than three electrodes. Their principles

are the same as that for the three electrode system.

With the potentiostat system, a wide range of techniques have been developed to
qualitatively and quantitatively determine the kinetics and thermodynamics of
electrochemical reactions. Several techniques that are often used for biosensors are

introduced in this chapter.

2.2 Voltammetric techniques

Voltammetric techniques study the response of a biosensor over time by applying a
time—varying stimulus. They study the relationship among stimulus potential (E),
responding current (1), and time (t).There are several variations on these techniques[54].

Cyclic voltametry is the most widely used votametric method.

Cyclic voltammetry (CV) has become an important and widely used
electroanalytical technique in many areas of biochemistry. It is widely used to study
reduction-oxidation (redox) processes, reaction intermediates, and the stability of reaction
products. This technique is based on varying the applied potential at WE in both the

forward and reverse directions (at some scan rate) and monitoring the current. A typical

l9

 

 

current(uA)

0.2 ' 15
:5 °' 1
3 -O.2 - 0.5-
% . .
L3 '0'4 , 41.7 4.5
o
> -O.6

'0-8 I i I T I

 

 

 

0 3 6 9 12

Time (Second) Input Stimulus potential (Volts)

(a) (b)

Figure 2.2. (a) typical stimulus potential for cyclic voltammetry, (b)cyclic
voltammogram.

stimulus potential waveform is shown in Figure 2.2(a). It is a triangle wave with a certain
slope and amplitude. The timing information of this sweep is contained within the slope
of the triangle waves. The result of the cyclic voltammetry can be shown visibly by
plotting the instant responding current against the instant stimulus potential (Figure

2.2(b)). This plot is called a cyclic voltammogram.

2.3 Impedance spectroscopy

Instead of studying the relationship between the stimulus potential, response current
and time, impedance spectroscopy (IS) studies the relationship between the stimulus
potential, response current and frequency of stimulus. IS monitors the transfer function of
the biochemical system to a sinusoid stimulus at individual frequency points and plots the
ratio against the frequency. In some situations, several interrogation techniques can have
comparable effectiveness. However, when complex heterogeneous reactions interact with

mass transport, a frequency analysis is more efﬁcient [55].

20

2.3.1 Bode plot

If a sinusoid signal is fed in as the stimulus, assuming that the electrochemical

 

D

Amplitude

 

 

 

 

 

 

 

 

 

 

(a)
gain
Y >
A ACD log(freq)
0
90
180-
>
log(freq)
(b)

Figure 2.3. (a) the input sinusoid waveform and the electrochemical response of a
potentiostat system. The output waveform is still a sinusoid, but multiplied by K with

a phase delay of Ad), (b) bode plot of the system response.

21

system is linear (which is true for small signals), the response of the electrochemical
system is also a sinusoid of the same frequency but with differences in phase and
amplitude (Figure 2.3). If a phase shift is involved, we can not use a single resister or
conductor to represent the transfer ﬁmction. Instead, impedance (or admittance) are
needed to represent both the amplitude and phase changes. To characterize the transfer
function of the system, we can extract the amplitude gain (K) and phase shift (Acp) by
comparing the response and the stimulus of the biosensor. Then (K, Alp) pairs for the
frequency range of interest is acquired and plotted as in Figure 2.3(b). This kind of plot is

called a Bode plot.

2.3.2 Nyquist plot
Alternatively, we can rewrite the sinusoid signal of a certain known frequency as an

in-phase component and quadrature phase component, as given by

a sin(0)t + (1)) = a sin(¢) cos(0)t) + a cos(¢) sin((r)t) (2.1)

At a known frequency, we can just use the coefﬁcients of these two components to
represent this signal. With the help of complex notation, the amplitude of the in-phase
component and the quadrature phase component are represented as the real and imaginary
parts of a complex number (A +jB). Thus the transfer function of the system can be easily
represented mathematically by

Z— Ao+JBo

— , (2.2)
Ain + .IBin

22

By mathematical derivation in the complex domain, we can derive Z, which is also
a complex number. By plotting the real portion versus the imaginary portion of Z over the
frequency range of interest, a plot shown in Figure 2.4 is achieved. This kind of
imaginary part versus real part plot is called a Nyquist plot. A Nyquist plot does not
present the frequency information directly, but the shape of the curve in it already gives

enough information.

2.3.3 Linearity of electrochemical systems

In the above discussion, a fundamental assumption is that the system under study is
linear. For a biosensor based electrochemical system, this is not always true [56]. In order
to apply the IS method introduced above, a small signal analysis for non linear systems
concept is used to linearize the system. This concept states that, for a nonlinear system, if
a stimulus signal is small enough, it can be viewed as a linear system at that point with
very good accuracy. In the potentiostat for an electrochemical biosensor system, a large
DC voltage is applied to set the proper state of the system, and a small AC stimulus is

applied. Finally, the output AC signal is monitored and compared with the input AC

k

KAN)

imaginary portion

 

 

(AN)
real portion 7

Figure 2.4. Example of the Nyquist plot of the admittance for a biochemical
potentiostat.

23

signal to extract the impedance information.

2.3.4 Electrical circuit models for electrochemical systems

For IS, the electrochemical systems on the surface of a solid electrode are always
modeled as electrical circuit networks. The components used in the circuit model and
their values embody certain electrochemical processes and phenomena involved in
electrochemical reactions. By analyzing the IS result, either with a Bode plot or a Nyquist
plot, we can ﬁgure out the component parameters of interest in the equivalent circuit
model. Eventually, the electrochemical reactions can be studied quantitatively from the
component values of the circuit model. There are many different circuit models for

different types of electrochemical processes [56].

2.4 Prototype potentiostat microsystem

To better understand electrochemical microsystems and explore the practical issues
of real VLSI realization of such microsystems, an amperometric microsystem that
support the electrochemical biosensor array has been developed based on the previous
works of our group [46, 57]. This microsystem can perform the voltammetry

interrogation techniques for a biosensor microarray.

24

2.4.1 Architecture of the microsystem

The system view of the amperometric microsystem is shown in Figure 2.5. A
miniaturized electrode array was formed on top of the silicon chip, in which the interface
circuits are built. A variety of biosensors will be deposited onto the corresponding

electrodes with a CMOS compatible process. A reference electrode (RE), a counter

WE array~~ - -
CD 3
sg a
E e 3 RE
to 8 :
ale 3
‘8 ‘D : ‘
CE
1 electrode potentia/drive -
. RE
“mg“ , L—~—~-—--—- Amp2 Potential
- --~' Amplf 2;; R2 , --—)
(I) _,1lw l1; 1
E ’9 l VSTC
k
... hi2 phlt
a p- . E - ‘   clock ..(CLK
'5 cm] _ Cf pm generator
9 . i l; ., phi1 phi2
C , 1 t 1 v
0 -- _ , phl1 C'"; , phi1
OTA ' L- i- ' Vout
+ .’ : 1 _ . ' ’
- phiZ 1 1+OTA' ‘ S/H toA/D
l-V ' ' PGA current readout

Figure 2.5. An amperometric microsystem comprised of a switched capaitor
amperometric readout block, an electrode potential drive block, and a current switching
matrix (mux).

25

electrode (CE), and a multi-parameter array of working electrodes (WE) were patterned
on the surface of an electrochemical interface circuit using post-CMOS fabrication. The
interface circuit drives a three-electrode system of an on-chip biochemical sensor array. It
also provides amperometric readout for the biosensor array’s current response. To cater
to the diversity and explore the high sensitivity of biochemical sensors, this interface

circuit must deal with a wide range of input current with a low noise feature.

In the electrode potential drive block of Figure 2.5, control signal Vsrc sets the
potential applied across the electrochemical cell, and either a constant voltage or a
sweeping signal (for CV measurements) can be applied. Amp2 is conﬁgured as a unity
gain buffer to sense the RE potential without loading RE. Amp] and Amp2 form a
feedback circuit to control the RE potential through the CE to establish a potential
difference between the RE and the chosen WE. Notice that the RE can not sink/source
electrical current, so all current measured at the WE comes from the CE, which helps

maintain the stability of the RE electrochemical potential.

In the current readout block [58], a switched capacitor (SC) charge integrator
converts the sensor output current into a voltage, which then goes through a
programmable gain ampliﬁer (PGA) that has auto-zero compensation. The output voltage
is then sampled, held, and fed to an A/D converter. The entire readout chain utilizes
correlated double sampling (CDS) [59] to reduce the kT/C noise as well as ampliﬁer

offset. The output of the current readout block, Vout, is given by [58]:

V _ IW _ C111
out — C f C
int 3 f

 

(2.3.)

26

where, 1% is the frequency of phi1, [w is the sensor current from the working electrode,
C int is the integrator capacitor, Cin is the binary weighted programmable capacitor at the

PGA input, and Cf is the feedback capacitor of the PGA.

The response sensitivity of bio-interfaces applied to the WE array can vary widely,
resulting in a broad range of currents to be measured by the readout circuit. The current
generated by the transducer is also directly proportional to the area of the WE. To support
these variable current levels, which are not set until after the electrochemical interface
circuit is fabricated, it is vital that the current readout block operate over a wide range of
input currents. As shown by (2.3), the overall readout circuit gain (Vout/Iw) is determined
by the clock frequency, the PGA gain (Cin/Cj), and the value of the integrator capacitor.
Thus, by using on-chip programmable capacitors for Cint and Cin and adjusting the clock
frequency, the readout circuit can be adapted to a large input current span. The capacitor
values and operational frequency were designed to support input currents ranging from

10 pA to 10 11A.

2.4.2 VLSI realization

Two kinds of ampliﬁers are employed for the electronic interface, depending on
their loading characteristics. The ampliﬁers used in the potentiostat drive block in Figure
2.5 drive the biosensors, which could have complicated impedance characteristics over a
wide value range. In order to minimize the effects of varying loading on the stability of
the system, a two-stage ampliﬁer is designed because its dominant pole is located inside
the ampliﬁer and is independent of the loading characters. For the ampliﬁers in the
current readout block, their loadings are purely capacitive with known value. Thus,

cascode single stage ampliﬁers are employed here to save hardware area by eliminating

27

the Miller compensation components. With the dominant pole located at the output node,

the purely capacitive loading will only improve the phase margin.

The schematic of the two-stage ampliﬁer used in the electrode potential drive stage
is plotted in Figure 2.6. With Miller compensation, the internal pole at the node “a” and
the output pole are split away from each other, while the internal pole becomes the
dominant pole. Simulation shows this ampliﬁer has 110dB DC gain and at least 3.5MHz
unit gain bandwidth with varying loading conditions. For a bioelectrochemical
application, the frequency of the stimulus is always in a very low frequency range, i.e.
less than lOOHz. The DC gain and the bandwidth are high enough to make sure the

electrode potential driving stage can transfer the stimulus to the sensors accurately.

An operational transconductance ampliﬁer (OTA) conﬁguration has been chosen

for the switched capacitor (SC) current readout block. The two main design

vdd

 

 

 

 

 

 

 

Vbn2 "a
and

Figure 2.6. Schematic of the two stage ampliﬁer.

28

vdd

M3 bMdEIm
Msjb—qwm [M6

 

 

 

 

 

vim-1 M1 M2 Fm. M7JF—M‘IEM8
Vbn2._1 M11 M9ﬂl—_I|__]M1O

gnd

 

 

 

Figure 2.7. Schematic of the folded cascode OTA.

considerations for this OTA are high gain, to ensure precision operation, and rapid
settling time, to ensure that the output settles within half of the clock period. Figure 2.7
shows the schematic of an OTA. MN] and MN2 form the input differential pair, MNll
acts as the tail current source pair, MP5 and MP6 are cascode transistors to the input
differential pair, MP3 and MP4 form the PMOS current source and MN7, MN 8, MN9,
MNIO form a wide swing cascoded NMOS current source. Because the load is purely
capacitive in SC circuits, an op amp with a single high impedance output node is suitable.
A cascode gain stage is selected for the high gain and immunity to the Miller effect at
high frequencies. The ampliﬁer output is shorted to the input during the ﬁrst phase of SC
operation. Therefore, a folded topology, which allows the input and output voltages to be
at the DC same level, is necessary. Due to the higher mobility of NMOS devices, NMOS
transistors are chosen for the differential input stage to provide a higher transconductance,
gain, and bandwidth than their PMOS counterparts. The simulated performance of this
circuit shows a DC gain of 79dB, unity gain bandwidth of 24MHz with a 60 degree phase

margin, 49 V-sec'l slew rate and 33 nsec settling time, an input/output range of 0.8 V to 3

29

V, CMRR of 107 dB (DC) and PSRR of 80 dB. In 0.5).rm CMOS with a 3.3V supply and

3pF load, the circuit, including the bias stage, dissipates 1.1mW.

2.4.3 Electrochemical experiment

The circuit was fabricated with a 0.5 pm CMOS process. Figure 2.8 shows the
3X3mm die with circuit blocks labeled and surface electrodes illustrated. This version of
the chip implements a 4X4 array of 100 11an working electrodes, but the circuit and post-
CMOS process can be scaled to a much higher density, covering the entire surface of the
chip. Array density is ultimately limited by ﬂuid handling constraints to approximately

100 electrodes per chip with our existing equipment.

To perform initial electrochemical testing with the system, a prototype electrode

array built on a glass chip is employed. As both silicon chip and glass are made of silicon,

“a;

' Potentiostat & ' 1
Current Readout 2. ‘

.. I
s ....r. .1 2:“ r . a. .1:

Switch network for
on-chip electrodes
( 44 arav)

 

(01“ " ‘-
“mil-Vt",

I
Figure 2.8. Die photograph of th
circuit blocks labeled.

    

        

 

at Leisure“ :15":"- "-

Computer running Labview K Chipmo ned on the Test sloution
and connected to a DAQ 1303 test bench in the beaker

Figure 2.9. The testing setup for the biosensor microarray based on-chip platform.

they have very similar physical features. Thus, a glass chip can mimic a CMOS chip very
well. The same micro-fabrication procedures of electrode formation and biosensor
deposition, are performed for the prototype electrode array. The whole testing setup for
the biosensor array platform, including the prototype biosensor array, is shown in Figure

2.9.

To verify the on-chip electrochemical interface circuit properly performs cyclic
voltammetry measurements, a cyclic voltammogram of secondary alcohol dehydrogenase
modiﬁed electrodes (working electrodes) is performed. They are in the 0.1M PBS with 2-
propanol of concentration 5, 15 and 25mM. The temperature is at 25 ° C and the scan
rate is set to 100 mV 5". The reference electrode is a Ag/AgCl electrode. A 530 mV
peak-to-peak triangle wave was generated and applied between CE and WE, sweeping
from -100 mV to 430 mV (with respect to the RE potential) at 2 Volts. The on-chip
amperometric readout circuit was clocked at 100 kHz, and the cyclic voltammogram
shown in Figure 2.10 was captured. The typical shape of this curve veriﬁes the on-chip
potentiostat operates as expected and can perform cyclic voltammetry. The oxidization

peak values, which are the bottom peaks in Figure 2.10, are also plotted against the

31

Cyclic Voltammetry

 

    

 

 

 

.12
O
2.
O
r'f’ l a
‘31,. ' _ _J‘1b—25mM g
l
1 _______ 15mM “1.6
. ~--~--~5mM 1
1 , , . . 1.4
2.2 2.1 2 1.9 1.8 1.7 1.6

Stimulus (Volts)

Figure 2.10. Cyclic voltammogram of secondary alcohol dehydrogenase modiﬁed
electrodes in 5, 15 and 25 mM 2-propanol in 0.1M PBS, at 25 ° C and lOOmVs'l scan rate,
vs. Ag/AgCl reference electrode.

1.7 1 -- - .
E o 1.669

A 1.65 i

£1

0

a 1.6 ., I

a f 91.576.

5 1.55 l ‘ I

Q 1 ’ .

8 l .. i .

a: "5 “ trues.

1.45 — —.——— “L _- ,___. ._. .._. _;_'

o 5 1o 15 20 25 30

2-propanol Concentration (mM)

Figure 2.11. Oxidation peak values VS. 2-propanol concentration levels.

concentration levels of the 2-propanol in Figure 2.11. The high linearity of their

relationship is convincing of good performance of this on-chip potentiostat platform.

2.4.4 Conclusion
A single-chip amperometric readout circuit and electrode array system suitable for

bioelectrochemical measurements has been designed and implemented. The on-chip

32

circuitry features an electrode potential control block and a current readout block that
serves as an electrochemical potentiostat capable of performing chronoamperometery and

cyclic voltammetry.

33

3 System Approaches for a Impedance Spectroscopy

Microsystem

In this chapter we will propose an impedance spectroscopy system targeted for on-
chip biosensor arrays, speciﬁcally the miniaturized on-chip protein embedded tethered
bilayer lipid membrane (tBLM) [42] biosensor array. The electrical features and circuit
models of the tBLM biosensor array will be discussed ﬁrst. The system level approach
for impedance spectroscopy will also be discussed. Feasible approaches are given at the

end of this chapter.

3.1 Electrical features of a miniaturized tBLM biosensor

The structure of a tBLM biosensor is illustrated in Figure 3.1. Protein is embedded

into the artiﬁcial lipid bilayers to mimic the function of ion channels in the cell

 
 
  
  

Protein ion

Solution
channel

Lipid Bilayer

 

 

 

 

 

with ion CM
channel
Metal
Solution llll Ii Cd
- L—__l
Interface electrode 1 I
(a) (b)

Figure 3.1. (a) structure of the tBLM biosensors and (b) their equivalent circuit mdoel.

34

membrane. Some ion channels are very speciﬁc and selective to certain types of ions in
the bulk solution. Once the corresponding ions are present in the bulk solution, these ion
channels will open and conduct current when the proper potential drop across the lipid
bilayers is applied. The tBLM’s conductivity (real portion of the admittance) carries the
information of existence and concentration of certain ion in the solution. This
conductivity information is modeled in the equivalent circuit as a resister (RM in Figure

3.1(b)), which is the sensing parameter of interest.

In this structure (Figure 3.1(a)), other phenomena couple electrochemically with the
ion channel activities and prevent direct resistance measurement of RM. At the surface of
the electrode, the accumulation of ions near the electrode form a metal-solution double
layer capacitance, which is modeled as C,” in Figure 3.1(b). This capacitor prevents DC
resistance measurement techniques to be applied for RM. Two surfaces of the artiﬁcial
lipid bilayers also form a capacitor, which is called the membrane capacitor and is in
parallel with RM. The bulk solution surrounding the tBLM shows resistance to ions and
thus affects the electrochemical system as a resistor (modeled as Rs in Figure 3.1(b)). Its
effect is normally ignored because its value, which is in the hundreds of ohms range, is

much smaller than the impedance of the other components in the circuit models. Typical

values for other components in the equivalent circuit in Figure 3.lf(b) are Cm = 0.59
uF/cmz, Cd] = 3.9 uF/cmz, and Rm = 46 KQcm2(would vary according to target analyte

concentration)[60].

In order to measure the RM with the coexistence of the other components in Figure

3.1(b), electrochemical impedance spectroscopy (EIS) is employed. Through analyzing

35

the response of the system over frequency, RM can be deduced. Figure 3.2 shows the EIS
response of a tBLM biosensor with area of 0.10m2 corresponding to two different analyte

concentration levels. Both a Bode plot and a Nyquist plot are shown.

In Figure 3.2 , impedance value in the ﬂat region of the impedance plots can be
approximated as the ion opening resistance (RM in Figure 3.1(b)). The frequency range
corresponding to the ﬂat region of impedance plot could range from several mHz to tens
of KHz [61]. This frequency range is not related to the size of the tBLM biosensor
because the featuring frequency is determined by the ratio of those components in the
circuit model and the scaling is proportional for all components. We can also ﬁgure out
the range of the response current. It is obvious that the current response is directly
proportional to the area of the tBLM biosensors. Also the current is proportional to the
stimulus signal strength. As discussed in Chapter 1, in order to linearize a tBLM
biosensor electreochemical system, only small excitation is allowed. Assuming it is 5mV,
the strength of the current response between the 10 mHz to 10 KHz is about lnA/cm2 ~
lOuA/cm2. The size of the miniaturized tBLM sensor can be changed from sub-mm range
to sub-cm range. In order to design an EIS system with compatibility for more general

purpose applications, we summarize the electrical interface as in Table.3.1

TABLE 3.1. RANGE OF FREQUENCY AND CURRENT RESPONSE

 

Interested frequency Range lmHz ~ lOKHz

 

Sinusoid current response strength 0.001nA ~ lOOnA

 

 

 

 

36

 

 

 

 

 

 

 

1.19.071 —— H - -,
RM=500KQ
1.E+06...-. R"=5°KQ
1.5+05... ......
1.E+04« -»
9.9T “
3’, -70
N .....
.C
n. .50
ac e 3”” ,
0.1 1 10 100
Freqency
(a)
500- Img(Z) (K0) R 500K!) 40- Img(Z) (Ko)
1 u: I
400. « RM=50KQ
3001 “’— 1
. so.
200.
100. ‘
o . - - . . A .20 - - - L - -
o 100 200 300 400 soo 600 o 10 20 so 40 so so
Real (2) (K0) Real (2) (K0)
0)) (C)

Figure 3.2. The EIS output of tBLM biosensor with an area of 0.1cm2, with two sets of
RM’s mimicking sensing the analyte with different concentration. (a) shows the output
on a Bode plot, (b) shows the EIS output on a Nyquist plot with RAF—5001“), (c)
shows the EIS output on a Nyquist plot with RM=50KQ. The Bode plot shows that the

frequency range of interest is at low frequencies.
3.2 Techniques to realize on-chip EIS
Several techniques are used to perform impedance spectroscopy. They can be sorted

into two categories: the fast Fourier transform (FFT)-based IS and the frequency response

analyzer (FRA) based IS.

3.2.1 FF T based methods

37

A Fourier transform is a mathematical method used to transfer a time domain signal
(x(t)) into the frequency domain (F (co)), shown in (3.1). F (to) shows the frequency
content of x(t). F (m) is a complex number and can be expressed as amplitude and phase,

or real part and imaginary part.

_ 1 —i(1)t
F(w)—E_1:ox(t)e dt (3.1)

The F F T is an efﬁcient algorithm to compute the discrete Fourier transform (DF T),
and is very suitable to digital signal processing. A general block diagram of FFT based
impedance spectroscopy system is shown in Figure 3.3. A white noise source produces
the perturbation excitations to the biosensors. An A/D converter converts the biosensor
response to a digital signal, and the discrete-time Fourier transform (F F T) is performed in

the digital domain with the help of the digital signal processor (DSP).

The most important advantage of the FF T is that the F F T method can work out the
frequency response at all interested frequencies at the same time. To gain this beneﬁt, the
small stimulus excitation source needs to produce all the interested frequency
components simultaneously. There are multiple ways to generate a pseudo white
bandwidth source that contains as many frequency components as possible[51]. White

noise contains many frequency components, which means that it can serve as the source

 

 

  

biosensor
(X0)

 
 

 

Bode Plot

/

l
I Nyquist Plo

 

 

Synthesized
Source

Figure 3.3. The principle block diagram of FFT based EIS system.

38

here. Computers can be used to generate a pseudo random digital sequence as the white
noise source. The edges of the square pulse have many frequency components, so we can
also use periodic square pulses or random square pulses as stimuli. All above mentioned
methods have the random spectrum and thus result in more or less variation due to the
uneven strength of frequency components in the spectrum. Instead, a synthesized source
with a limited number of frequency points with the same strength can be generated with

the help of the computer.

The FFT block plays a key role in the FFT based solution. Complicated
computation is needed to perform the discrete Fourier transform even if the efﬁcient fast
Fourier transform or some other techniques [62] are employed. Large memory is also
needed to store the intermediate results and the input/output digital sequence. These

factors prevent the analog realization. DSP or a computer is always involved in the FFT.

The composite signal source and the computation intensive Fourier transform force
the F F T based solution to require systems with powerful digital computation and control
capability, such as a personal computer or a DSP system. Although some practice was
done to realize the FFT with an analog circuit [63], it is far from practical due to the poor
accuracy and preprocessing/pre-storing of the input data set. The size and power of the
intensive digital circuit of the FFT method prohibits it from being implemented for low-

power compact integrated biosensor interrogation systems.

3.2.2 FRA based method
Unlike the FFT based method, which works out the response at all interested

frequencies at the same time, frequency response analyzer (F RA) based methods process

39

 

 

 

Imago
SIN *
Quadrature W l Potentiostat
Signal (X0)
Generator COS

 

   

 

 

 

real(Xl

 

 

Figure 3.4. Block diagram of frequency response analyzer based impedance.
Spectroscopy.

the response at single frequency points one at a time. Its principle block diagram is shown

in Figure 3.4. It consists of a quadrature signal generator, multipliers and integrators.

A quadrature signal generator produces a pair of sinusoid signals with the same
amplitude and frequency, but with a 90° phase shift. It produces signals at a single
frequency one at a time and is capable of sweeping over the entire frequency range of
interest. A couple of multipliers are employed to perform the needed signal processing.
As its input and output are all analog signals, the multipliers are realized with an analog
circuit. In the end, integrators remove the interference and produce the constant DC

signals which represent the real and imaginary parts of the admittance of the biosensors.

Assume that the signal generator produces the sine and cosine signal with zero
initial phase at a frequency of (I). The response of the biosensor (at node B) can be
expressed as Asin(cot+rp). The pair (A, (0) represents the impedance information of the

biosensors. The signal at node B can also be expressed as:

A sin(u)t + (p) = A cos((p) sin(u)t) + A sin((p) cos(u)t) (3.2)

40

The coefﬁcients in (3.2), i.e., Acos(¢) and Asin(rp), represent the real part and
imaginary part of the admittance of the biosensors. The system in Figure 3.4 calculates
Acos(rp) and Asin(¢), at each frequency point of interest. The outputs of the multipliers

are

SCl = A sin((ut + (p) sin(cot) = %[cos(¢) — cos(2cl)t + (p)] (3.3)

SC2 = A sin((r)t + (p) cos((ot) = %[sin((p) + sin(2(l)t + (p)] (3.4)

Both (3.3) and (3.4) have the DC components and AC components located at twice
the stimulus frequency. The DC components are the real part and imaginary part of the
admittance with a scaling factor of 0.5. With the help of the integrator, the components at

twice the stimulus frequency are suppressed, and the DC components are ampliﬁed.

 

SDI = % LT %[cos(¢) - 005(20)t + (P)ldt
(3.5)
= %COS((1)) — 4$(1l)[sin(20)t+ (p) - sin((P)]

5m :71: LT%[Sin((p)-l- sin(20)t + <p)]dt
A (3.6)
[cos(2(0t + (p) — cos((p)]
4T0)

 

A .
= —— +
2 srn((p)

To suppress the components at double the stimulus frequency (interference
components), we either integrate over a long enough time or make the duration of the
time to be exactly the half period of the stimulus signal. At high frequencies, the former

method is always used because it is hard to control the duration of integration to be

41

exactly half of the period. As the relative error is small to set the duration of integration
to be half cycle at low frequencies, latter method is chosen for low frequency

interrogation and minimizes interrogation time.

In addition to a high feasibility of realization as an integrated circuit, this
architecture is inunune to the DC offset of the multiplier. If there are input referred DC

offsets at the inputs of the multiplier, its transfer function is

z=(x+a)(y+b)=xy+ax+ay+ab (3.7)

where a and b are the DC offsets, and x and y are sinusoid signals of the same frequency.
The ﬁrst term in (3.7) will generate the desired DC output. The last term is another DC
term that can be cancelled through calibration. It will not ruin the DC output. The ﬁrst
term will also generate AC interference at the double frequency point. This, along with
the 2nd and 3rd terms in (3.7), will be suppressed by the integrators in Figure 3.4. As a

result, only the desired DC signal is presented at the output.

This architecture is also immune to the multiplier’s odd order nonlinearities. These
nonlinearities only introduce the harmonics at multiples of the stimulus frequency and the
integrators in Figure 3.4 can suppressed them. However, the even order nonlinearities of
the multipliers will generate interference DC signals and affect the resolution of this FRA
based system. 3rd order and 4th order nonlinearities are the most signiﬁcant non-ideal
effects in an analog multiplier. Their effects on the accuracy of the F RA based system are

discussed below.

Assuming the multiplier in Figure 3.4 has 3rd order and 4th order nonlinearities, its

transfer function can be expressed as,

42

z=xy

+1<31X‘7'y+1<32xy2 +k33x3 +k34y3 (3.8)

3 2y2 3

+k4lxy +k42X +k43X y+k44X4+k45y4

where x and y are sine signals with the same frequency. The ﬁrst line shows the wanted
multiplication function, and the 2nd and 3rd lines represent the unwanted nonlinear
transfer function. All of the 3rd order nonlinearities (terms in the 2nd line of (3.8)) only
generate non-DC harmonics, which can be suppressed by the integrators. Thus, the
system is robust against 3rd order nonlinearities. This conclusion is also true for all other
odd order nonlinearities. In (3.8), only xy and xzyz terms generate DC components at the
output. By substituting x and y with Asin(wt+rp) and sin(wt) and only including xy and

xzy‘? terms, we get,

2 = xy + k42x2y2 = A sin((r)t+ ¢)+ k42 sin2((ot +¢)sin2(mt)

2 3.9
2cos (2(1))+1+F ( )

 

= 1—:-COS((1))‘I" k42A

where F represents the non-DC terms, and will be suppressed by the integrators. The ﬁrst
DC term in (3.9)’s result is the real part information of input signal (see (3.2)). The
second DC term is a product of the 4th order nonlinearity (xzyz). We can see that the
output is accurate as long as k4; is much smaller than the ﬁrst DC term. Higher even
order nonlinearities also produce a DC term in (3.9), but their effect should be much
smaller than 4th order one. To keep these nonlinear terms at DC in (3.9) small enough, the

even order harmonics of multiplier should be controlled.

For the analog multiplier circuit, it is hard to achieve very high linearity. However,

with some balanced structures, it is easy to suppress the even order nonlinearities to the

43

point where they can be ignored. Normally, for a balanced analog multiplier structure,
odd order harmonics dominate the linearity performance. That kind of non-linearity does
not affect the accuracy of the result because the integrators employed in an FRA based

system illuminate their effects.

3.3 Proposed biosensor array based EIS microsystem

Considering the above discussion on FFT-based and FRA-based 1S systems, we
have obvious reasons to choose the F RA-based IS system as the architecture for our EIS
system. As shown in Figure 3.4, a quadrature sinusoid signal generator is necessary for a
stand-alone EIS system based on the FRA structure. For the tBLM biosensor, the
frequency range of interest is from lmHz to 10kHz (TABLE 3.1). Thus an on-chip
quadrature sinusoid signal generator is developed to cover this range. Two possible
interrogation systems will be proposed based on the FRA architecture in Figure 3.4. One
system targets the rapid interrogation for low frequencies measurement. Normal F RA
methods require a long interrogation time at low stimulus frequencies (sub Hz or lower)
because the integrator in Figure 3.4 requires at least half of a stimulus cycle to eliminate
the AC interference. The proposed method tries to avoid the use of this integrator in AC
interference elimination. A second system is based on a compact IS circuit to support the
multichannel, high accuracy EIS system. The performance and feasibilities of these two
systems will be studied, but in the end, only one of them was chosen as the prototype

electrical system for the biosensor array microsystem.

3.3.1 Rapid response IS systems

3.3.1.1 Delay in EIS systems

In an F RA based EIS system, the total response time of the system is decided by
two factors. One is the delay of the biosensor; the other is the delay from the
interrogation system. These will both be analyzed to determine where the bottleneck

OCCUI‘S .

Potentiostat systems interface with biosensors and translate their electrochemical
response into electrical information. For a frequency range of less than lOkHz, the
electronics introduce only a negligible delay. The potentiostat delay is mainly due to the
biosensor delay. For an EIS system, we need to vary stimulus frequencies to sweep across
all of the interested frequency points. The biosensor delay determines the settling time of
the ﬁequency transition. We will take the tBLM biosensor as an example to study these
delays. Its circuit model is redrawn with a sinusoid voltage source in Figure 3.5.
Assuming that the sinusoid voltage source frequency changes from too to (01 at t=0, then

we can get the current response as

1

A R (c +C )t -
1(1) = ——5—e M 1 2 + A- srn(c01t+ (p) 3.10
(Ceca ( )

 

where A5 is a constant determined by (no and (01, and A, (p are the amplitude and phase of
the response current. For the detailed derivation of (3.10) please see Appendix. (3.10)
shows that in addition to a stable response signal at frequency (01 (second term), there is
also a term(ﬁrst term) embodying the transition effects. The ﬁrst term will die out
eventually with a time constant of RM(C 1+C z)- The settling time of a frequency change is

proportional to this time constant. For typical values of the tBLM biosensor [60], this

45

+V-

 

 

CM

Re __i l"— C‘"

 

 

 

 

 

—::I—
RM

Figure 3.5. Equivalent circuit model for tBLM biosensor.

time constant is about 0.25 see. So, there is up to a several seconds waiting time for the

EIS system to read a stable output after a frequency change.

For the F RA based IS system (Figure 3.4), the integrator takes times to suppress the
double frequency AC interference. As shown in Figure 3.6, the averaged DC components
remain constant regardless of the integration time. However, the AC interference dies out
exponentially as integration duration increases. Because the AC component crosses over
the zero point at multiples of half a period of the stimulus frequency, we can minimize
the interrogation response time by tightly controlling the integration duration to be half of
a period of the stimulus. However, the delay is still large for very low frequency
measurement. For example, if lmHz is the frequency of interest, the minimum
integration duration is 500 seconds (about 11min). Compared with the several second

delay of a typical tBLM biosensor in frequency transition, the delay of the EIS

46

A Amplitude

 

———- DC component
............. Asymptotic line forAC

AC components
................ @ doubled frequency

 

 

2T
Integration Time (seconds)

Figure 3.6. The DC and double frequency AC interference in the integrator output.

interrogation system is dominant. It becomes worse if multiple low frequencies are
selected and the large scale biosensor array is interrogated. To overcome this problem, a

fast EIS architecture is proposed.

3.3.1.2 Rapid EIS systems

As discussed in the previous section, the integrator is the bottleneck causing the
long delay for low frequency EIS interrogation with a conventional F RA based system.
Thus, to improve the interrogation speed, a new architecture eliminating the integrator for
AC interference suppression is proposed. The principle block diagram of this system is
shown in Figure 3.7. Instead of interrogating single elements, as in a conventional FRA
based EIS system, this new method interrogates two identical biosensor elements
simultaneously with in-phase and quadrature phase sinusoid stimuli of the same
frequency. Then, complex domain (dealing with signals having real and imaginary parts)
signal processing is done to extract the real and imaginary part of the biosensors’

admittance. No integrator is required in this new system.

To explain this system mathematically, assume that we have two identical biosensor
elements. For the conﬁguration in Figure 3.7(a), the summation operation at the output is

expressed as

47

, 0 ' Bsin(cot+q>)
p ' B 1+ 0 °
sIn(to (p) 9

.'k 0 k

9 . \
. A t .
9Aﬂn(mt)\8ioscnsor D__4 Acos(¢) 8mm ) Brosensor D__* Acos((p)

a X

0 0¢
. O Bcos(wt+tp)
Acos cot)

(a) (b)

Figure 3.7. The principle block diagram of the fast interrogation EIS system: (a) the
conﬁguration to produce the real portion of the admittance, (b) the conﬁguration to
produce the imaginary portion of the admittance.

 

 

 

m
m

 

 

 

 

 

 

 

A sin((p)B sin((r)t + (p) + A cos((r)t)B cos((r)t + (p) = AB cos((p) (3.11)

This result is the real part of the admittance. Similarly, for the conﬁguration in Figure

3.7(b), the subtraction at the output is expressed as

A cos((p)B sin(u)t + (p) — A sin(tp)B cos(u)t + (p) = AB sin((p) (3.12)

which is exactly the imaginary part of the admittance.

(3.11) and (3.12) show that the stable outputs are presented at the output of the EIS
system as long as the biosensors’ responses are stable. Thus, only the biosensors’ delays
appear in the frequency transition. The elimination of the integrators greatly improves the
interrogation speed for low frequencies. Due to this dramatic improvement in the
interrogation speed, this system can scan the whole biosensor array sequentially in a
reasonable time. We can use just one this system and use multiplexer to access all the
array elements. The system level block diagram for the rapid EIS based biosensor array
microsystem is shown in Figure 3.8. The signal generator provides the sinusoid stimulus

for the biosensors and the reference signal for the IS circuit. A multiplexer is employed to

48

 

   

Sllleon chip for biosensor array
biosensor

.NIIII-III..-IIICIIIIIIIIIIIIIIIIIII..
O
O

%% @* @3-
@ﬁ.

8 0 [888

   
   
  

t
t
a

 

X
E: 3 Ra id
%% ”@T ﬂ, 2 IS) __o)utput
'lCircuit

AQ.IIIIIIIIIIIIIIIII'I..

t
e
t

.
O
U
U
.0
..IIIIIII‘ IIIIIIIIII III-II...- III-III.

 

 

 

 

 

 

 

 

 

buadrature sinusoid generator I

 

 

 

 

Figure 3.8. The principle block diagram of the fast EIS microsystem.

pick up the desired sensor element pairs for the EIS circuit. All electrical components can

be integrated on a single silicon die.

3.3.1.3 Accuracy limitation due to non-ideal effects

(3.11) and (3.12) show that the AC interference can be completely canceled.
However, this is based on the assumption that all components are ideal. The mismatches
between the biosensor and the readout circuit (analog multiplier) will result in the leakage

of AC interference at the output and affect the accuracy.

Error due to biosensor mismatch

This rapid EIS system requires two identical sensor elements. In reality, mismatch
between sensor elements is unavoidable, and it will limit the accuracy. For a sensor pair
with a certain admittance mismatch, the effect of sensor mismatch can be studied by
comparing the mismatch and the value of the biosensor admittance. Relative error is

deﬁned as the ratio,

49

. _ 1Y1 ” 21
Relative error—————- (3.13)
1 II
where Y) and Y; are the admittance of two biosensors. The admittance can be expressed
with a magnitude and phase pair (A,rp).The relationship between relative error and
mismatch is plotted in Figure 3.9. Output signals are always digitized before further
processing. In order to relate the relative error to the resolution of the digital signal, the
vertical axis on the right reveals how many bits of resolution we can achieve. Speciﬁcally,
it shows that the mismatching error could be 15% of the base impedance values with a 5°

phase mismatch and 20% magnitude mismatch in admittance.

By relating the mismatch of the components in the circuit model of an

electrochemical biosensor to that of the magnitude and phase of the biosensor, we can

 

ES :

1 I5 .9
12 t E!
O O

o In

.2 2

.9 E g
g; .—

“ '5

.2

.46 ‘6

 

 

   

Figure 3.9. Output relative error versus the different levels of mismatch in amplitude
and phase of two identical biosensors, and the equivalent resolution in terms of digital
presentation.

50

have more of a sense of the degree of mismatch for the real biosensors. Again, we take
the tBLM biosensor as an example. The phase and magnitude changes due to changes in
the individual circuit model components are studied by changing every component’s
value up to 20%. The admittances at a frequency of interest (1H2, where Rm shows up in

the model) are taken. The result is plotted in Figure 3.10. Several conclusions are drawn:

0 Cdl and Cm have limited effects on the magnitude change. There is a less than 5%

change with a 20% change in Cdl or Cm.

0 Rm has a dominant effect on the magnitude change. A 20% change in Rm results

in nearly a 14% change in magnitude.

With tBLM biosensors, a good match between the Cdl components (electrode and
solution double layer capacitor) of different biosensors can be easily achieved. This is
because Cdl depends on the area of the solid electrode, which can be accurately
controlled during manufacturing. In addition, Cm contributes less than a 1% effect with a

20% mismatch. As a result, a mismatch of Cdl and Cm results in a relatively low error for

 

 

 

 

 

 

12 I/’ A 4 Cdl
A 10 ' ’I’ Rm 0 g 3 1
0 i 8 I /” g, 3’ 0....Rm
Bi 0 6 u
E U 5 v 2 1
5 ’3'" 0 g - ° Cm
o g, z g
3% g 5 a 1 .
E .5 2 .E .
o 0.05 0.1 0.15 0.2 0 0:05 07 0:15 0-2
change (normalized to nominals value) changes (normalized to nominate value)

Figure 3.10. Magnitude and phase changes due to a change of up to 20% in component
values found in the tBLM biosensor circuit model. The base values for the components
are Rm=50KOhms, Cm=0.5uF and Cdl=5uF.

51

tBLM biosensors at a frequency of interest. The mismatch of the Rm component
dominants the admittance mismatch. However, a 20% base value mismatch is tolerable
during measurement because amplitude always changes several decades at a frequency of

interest[6 l ].

Due to this mismatch effect, the fast interrogation method can not achieve a high
resolution. However, with the above analysis, moderate accuracy (around six bits) is
feasible. For some qualitative interrogation situation, for example, detecting whether or
not certain elements is present, three bits of resolution can give enough information. Thus,

this method can also be applied for a badly matched sensor pair in these situations.

Error due to circuit mismatch

The gain mismatch and the input referred offset of the multipliers will affect how
effectively AC interference can be eliminated. To study the effects of both the gain
mismatch and the input referred offset,, we will rewrite equation (3.11) for the system

diagram in Figure 3.7, including the offset and gain mismatch of the multiplier. It is,

[AsﬂutHVcﬂIBsirﬂd+¢)+V(B12]+(l+a)[Ams(01)+V$21][Boos(ut+¢)+Vm22
=ABOOS(¢)+1<AB

](3.14)

where Vosij represents the input referred offset of the ith input of the jth multiplier, and 0.

represents the gain mismatch of the multipliers. On the right side of (3.14), the ﬁrst term
is the wanted result. The second term is the error due to mismatch and the offset of the

multipliers. k is a parameter determined by the multiplier’s mismatch and is expressed as

52

V0311"0312 + (1 + 00‘,052 1V0S22

k=orcost0tcoscot+ +
( ) ( 11) AB

v
JAE sin((r)t + 1;) +

v V V (3.15)
+ —OBSI—2 sin(0)t) + (1+ 001%; cos(0)t) + 42% cos(0)t + (b))

k shows the relative error due to the multipliers’ mismatch compared with the wanted
output, or the ﬁrst term in (3.14). The expression for k in (3.15) illustrates that k is
determined by the multiplier gain mismatch and the relative input referred offset
compared with the amplitude of the input signal. Because there are so many terms in
(3.15), even a very small gain mismatch and offset results in a signiﬁcant error. More
than 30% relative error (k) is observed when only a 5% gain mismatch and a 5% relative
input offset is applied on (3.15). We should observe the same error level if we rewrite

(3.12) with the gain mismatch and offset of the multiplier.

This observation almost excludes the analog solutions for the multipliers. The large
gain mismatching (more than 5%) of two analog multipliers [64-71] is expected.
Furthermore, an input referred offset of more than lOmV is very common for analog
multipliers. In order to provide enough dynamic range of the input signal, we can not
keep the input signal very large. Thus, the relative input referred offset can not be small.
The solution is to perform the multiplication in the digital domain, where the multiplier
gain mismatch and offset can be minimized to zero. At the system level, the sensor’s
response should be digitized with an ADC, and all other signal processing performed in

the digital domain with the help of a DSP.

3.3.1.4 Summary of the rapid response EIS system

53

A new EIS system was developed to signiﬁcantly improve the interrogation speed
at low ﬁ'equencies (sub-Hertz or lower). It eliminates the AC interference suppression
integrators used in a conventional F RA based IS system to improve the speed. The new
system suppresses the AC interference by coupling two biosensors’ responses. The
measurement accuracy of the new system is strongly affected by the matching of the
biosensor and readout channels. Digital domain signal processing is recommended to
achieve the readout channel matching. As a biological system, biosensors always have
poor matching. However, the biosensor mismatch for some type of sensors, e.g. tBLM
protein biosensor, is tolerable. We can extract the desired impedance information with a
moderate level of accuracy from these biosensors. If the matching of biosensors can be
improved signiﬁcantly in related research, this method can work for wider range of
biosensors. In this dissertation, we would not realize this system due to its limited

accuracy.

3.3.2 Multi-channel compact high accuracy EIS systems

Although integrators in F RA-based IS systems (Figure 3.4) introduced large delays
for low frequency interrogation, the system provides the high accuracy result with the
circuit non-idealities. Section 3.2.2 has discussed the non—ideality tolerance in detail.
Analog and mixed-signal ICs can realize the F RA-based IS system with a very compact
size. Just as any analog circuit system, this realization will have many circuit level non-
idealities. The integrators in this system will suppress these effects signiﬁcantly and help
to guarantee high accuracy. Based on this understanding, an EIS system featuring multi-

channel parallel interrogation was developed. For biosensor array screening, the long

54

interrogation delay for low frequencies can be alleviated by simultaneous in-parallel

interrogation.

3.3.2.1 Electrical system of the multi-channel high accuracy EIS

Figure 3.11 shows the electrical system of the multi-channel EIS, in which the
compact IS circuit is built and instantiated for every biosensor element in the array. A
quadrature sinusoid signal generator is also employed in this system to provide the
sinusoid stimulus for the biosensor and the reference signal for the IS circuit. With
advances in the development and microfabrication of the biosensors, the scale of the
biosensor microarray can reach hundreds or even thousands of elements. Due to the
limited number of PADS on the silicon die, it is not feasible to reserve dedicated pads for
every unit readout channel to send out the interrogation result. Thus, the unit IS circuit
needs not only to extract the impedance information from the biosensor, but also to
digitize the extracted impedance information. The digitized results can be put into a
global shifter bank so that the impedance information of all the active channels can be

read out through the same serial data interface PADs.

55

 

Silicon chip for biosensor array
biosensor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REEE’
HERM—
ease

inane ..
'5’" Li [it Li
sane.

aria
MERE

 

 

 

 

-))

 

 

O
C
.1.-
'U
C
-.-

l Quadrature sinusoid generator

 

 

 

 

Figure 3.11.The principle block diagram of the multi-channel EIS microsystem.

3.3.2.2 Rapid interrogation of tBLM biosensors

For tBLM biosensors, shown in Figure 3.1, the impedance value is dominated by
Rm (the sensing parameter) at low frequencies. Thus, low frequency IS is conducted to
extract the value of Rm. The FRA structure based compact EIS system will have a long
interrogation time at low frequencies. A new method that extracts the value of Rm of
tBLM biosensors with high frequency IS is developed so that the rapid interrogation can

also be achieved with this compact EIS system for tBLM biosensors.

For the circuit model in Figure 2.1(b), the admittance of the tBLM biosensors is

 

1
+1
2 2 2 2 2 2
+c0C +(0C 6°C 1
Y(0))= 1 = gM M M M d' 2 (3.16)

1 1 2
. +. g (0C 1
gM+jcoCM ijd1 [——————2 M2 2 J +[ 2 M 2 +
gM'H’) CM g

8M 1 (”CM
g

 

 

At frequencies where gM<<wCM, (3.16) this becomes,

56

10‘; ' '

 

' —*— Real, Rm=50K
-6. . Imag,Rm=50K
10 :' —.— Real@ high freq

 

 

 

 

 

 

 

10 a 1 Lilla-1 L . .JLllan . 1 . .141”
-1
10 10° 101 1o2
Freq
Figure 3.12. A plot of the real and imaginary admittance of a tBLM biosensor model.
'coC
2 C (3.17)

C 1+ _M
1 + ——M- C

d] dl

For a given tBLM sensor, CM and Cd; are constant. Thus, the real portion of
admittance, which is proportional to gM, is independent of frequency. A plot is shown in
Figure 3.12 for a 1mm x 1mm tBLM biosensor (the typical parameters are

RM=50~SOOKOhms/CM2, CM=500nF.CM2 and Cd,=5uF.CM2).

In Figure 3.12, the dotted black line represents . The real portion of the admittance
approaches this dotted line after about lOHz. Thus we can measure the real portion of
admittance above lOHz, and deduce the gM. Although higher frequencies may also be

picked, the accuracy will be less at those frequencies because both the imaginary portion

57

and the admittance increase with frequency. Extracting the small real portion from the

much larger admittance reduces accuracy.

3.3.2.3 Summary of multi-channel high accuracy EIS systems

The compact, high accuracy EIS systems provide a multi-channel 18 solution for
biosensor array microsystems. Its structure is based on the FRA. The analog/ mixed-
signal IC realization of this system can provide the compact size. The internal integrator
makes the system robust against the real analog circuit non-idealities and guarantees
accurate results. Further, this system does not impose any matching constraints on
biosensors as rapid EIS system does. It works for all kinds of miniaturized biosensors.
Although it still has a long interrogation time for low frequencies, simultaneous in-
parallel multi-channel interrogation alleviates the issue signiﬁcantly for whole array

impedance scanning.

3.4 VLSI implementation for the multi-channel EIS system

Two possible system solutions for the biosensor microarray interrogation EIS
system have been discussed in this chapter. Our conclusion is that a compact, multi-
channel, high accuracy EIS system is a better choice for an EIS biosensor array
microsystem because it can support a wider range of biosensor types and provide
accurate results in spite of circuit non-ideality. For an on-chip electronic system, this is a
very important feature because we lose the freedom in choosing the best performance
electronics that exists with bench-top instruments. Limited choices for on-chip
electronics always meant more circuit non-ideality. Thus, robustness to circuit non-

ideality becomes very critical for an on-chip electronic system.

58

In the rest of this dissertation, the feasibility of a VLSI realization of a multi-
channel EIS system will be explored. The main challenge in a VLSI realization is to
provide all the required functions and performance within a limited physical size budget.
Two key functional blocks will be studied: a channel-wise impedance extraction and the

digitization circuit cell, and a wide frequency range quadrature sinusoid signal generator.

3.4.1 Compact impedance extracting and digitizing circuit

In the multi-channel EIS system, the impedance extraction and digitization circuit
cell is instantiated for every sensor element in the array to provide massively parallel
interrogation capability. With most of the chip area on top of the die populated by
biosensor elements, the circuit cell must be compact enough to be ﬁt into the space
budget underneath every sensor element. With the increasing scale of the array, this
physical area budget could be very tight. As discussed earlier in this chapter, this circuit
cell not only provides the impedance extraction function, but also needs to digitize the
extracted impedance information. Further, it needs to provide a shift register bank to
stream out the interrogation result of the entire array with limited I/O pad resources.
Chapter 4 will study this readout channel in detail and present a compact solution

meeting the requirements that was developed and fabricated.

3.4.2 Quadrature sinusoid signal generator

For a stand alone FRA-based IS microsystem, a quadrature sinusoid signal
generator is necessary. It needs to produce a pair of sinusoid outputs with the same
frequency and amplitude, but with a 90° phase shift (in-phase & qudrature-phase signal or
1&Q signals) over 7 orders of frequency range (lmHz ~10KHz) with good frequency

accuracy. Furthermore, good matching between the I & Q signals is also very important

59

for accurate results. So far, there have not been any publications that achieved sinusoid
generation with accurate frequency control over such a wide frequency range. Although
its physical size budget is not as tight as that of the channel-wise unit impedance readout
circuit cell, the limited available chip real estate excludes some realization options and
puts forth more challenges for implementatoin. A hybrid structure and VLSI realization
of a prototype quadrature sinusoid signal generator is described in Chapter 5. It inherently
guarantees good I&Q matching. Moreover, it is completely controlled by digital signals

to achieve high frequency resolution and permit easy interface with a computer.

60

4 Compact On-chip Impedance Spectroscopy

In this chapter, a very compact impedance spectroscopy (IS) system and circuit will
be developed and built. Its working frequency range is from lmHz to 10kHz. It provides
digitized information of a sensor’s impedance response. A new analog-to-digital (ADC)
circuit structure is proposed to build this compact IS circuit. In contrast to a traditional
ADC, which converts an instantaneous analog value into a digital value, this ADC
converts the phase and amplitude information of a sinusoid input into the digital domain.
We will refer to this circuit as a “lock-in ADC” because it needs a reference clock to
extract impedance information in a manner that is similar to a lock-in ampliﬁer [72]. The
principle operation of the lock-in ADC is shown in Figure 4.1. Its input (Ix) is a sinusoid

current, which is the current response of a biosensor to a sinusoid voltage stimulus

Simw|x=Asin(wt+0)=a-cos(wt)+b-sin(wt)

   
 

MUM

 

 

3.. Ix cllk cllk
’w lock- In ADC an” lock-In ADC b"
reference reference

 

 

 

 

cos(wt)-|>0-|>o—' sin(wt) -|>o-|>o—
l I W _J_LJ‘1

Figure 4.1. The lock-in ADCs extract and digitize the impedance information of a
biosensor.

61

(sin(a)t) ). The amplitude (A) and phase (8) of 1x carry the sensor’s impedance

information. Ix can also be represented as the sum of cosine and sine components.
Asin(cot+6)=a-c0s(a)t)+b-sin(wt) (4 1)

The coefﬁcients in (4.1) represent the imaginary and real parts of the biosensor’s
admittance (the reciprocal of impedance), respectively. The relationship between these

coefﬁcients and the amplitude (A) and phase (0) information is

{a=Asin(9) (4 2)

b=Acos(9)

As shown in Figure 4.1, the lock-in ADC digitizes the sensors’ admittance information,
i.e. aorb in (4.1). It needs a square wave reference signal that is either in phase with the
sine component or in phase with the cosine component. If the reference signal is in phase
with the sine component, the digital output is the coefﬁcient of the input current’s sine
component. In the other case, the digital output is the coefﬁcient of its cosine component.
Digital counters are employed inside the lock-in ADC. These counters can be

reconﬁgured to work as a shifter to perform the serial readout.

This compact IS circuit is set to be instantiated for each miniaturized element of the
biosensor array microsystem. A principle block diagram for the electrical part of the
micosystem is illustrated in Figure 4.2. Every biosensor has its own IS readout circuit cell.
Due to limited pad resources in the integrated circuit package, it is impossible for every
readout channel of a large scale biosensor array (around lOOelements or more) to have a
dedicated pad to output the extracted impedance information. Thus, a shift register is

built within each IS circuit. The shift registers within each cell are connected together to

62

 

Silicon chip for biosensor orroy
biosensor

 

 

 

 

 

 

 

 

 

 

 

 

 

0 9.
Sensor
Stimulus OUIPUI

Figure 4.2. Block diagram of the biosensor array based microsystem.

form one large shifter such that the result of each IS circuit cell can then be accessed

through a single set of serial data pads.

To ﬁt the IS circuit cell with the area of each miniaturized biosensor element, a
compact BIS system was developed. As shown in Figure 4.3, this EIS system
incorporates an analog signal processing function, performing the F RA analysis, and the
result quantization function, converting the output into digital domain and storing it. A
new circuit architecture is proposed that permits the required functions to share hardware
resources such that the layout size is minimized to ﬁt to the individual sensor’s size. Also,
this new architecture eliminates non-ideal circuit effects, such as leakage, offset, and

nonlinearity, to achieve high accuracy for low frequency interrogation.

The proposed compact architecture was built with a switched capacitor circuit. All

other functions (digitization, integration, multiplication) are realized around it. Starting

63

s=1
COS(wt)or\/—V\D.-Dui'n—\o—
SlN(wt) W J U '\o_

S=O

’-I ----------------

 

 

 

’x Lock-in ADC .
[Potentiostat Xo o’ X m :im89(X0)(S=1)
(Biosensor) s“ : Real(Xo) (8:0)
s‘ I

‘-------------------I

Figure 4.3. Functional block diagram of the proposed EIS system.

with the realization of the integrator, we will show the architecture step by step as it

moves toward a ﬁrlly integrated IS structure.

4.1 Integrator design

As discussed in Chapter 3, the integrator in an FRA removes the AC harmonics
from the output of the multiplier. The inputs of the multiplier are two sinusoids of the
same frequency. The frequencies of the harmonics at the multiplier’s output occur at
multiples of the input sinusoid frequency. By integrating the multiplier’s output over one

or more periods of the sinusoid signal, these harmonics can be suppressed completely.

An typical integrator for an FRA circuit would be composed of an op-amp and a
capacitor in a feedback loop as shown in Figure 4.4. However, this structure is not
suitable for an IS application because the range of signals that can be integrated is limited
by the supply voltage. For a long integration time required for low frequency 1318
interrogation (sub-Hertz or lower) or a large input current, the voltage on the capacitor
could reach IKV if the supply voltage were not limited. This is unrealistic for
microelectronic components. In order to provide a wide output range with the analog

integrator, current mode operation has been adopted in some literature [73, 74]. With a

64

‘ Reset—1

—||—
f/

Figure 4.4. Simple integrator circuit.

 

 

 

 

current mode integrator, the integration result is actually stored on a capacitor as a
voltage, which drives the gate of a MOSF ET and converts the stored voltage information
into the transistor’s drain current. Although these current mode integrators provide a
much wider output range compared to the one in Figure 4.4, they become problematic
with a long integration time because 1) the charge on the storing capacitor will slowly
leak, and this leakage becomes very signiﬁcant for a long integration duration; 2) the
output signal range could still be limited by the physical size of the output MOSF ET; and

3) the power consumption budget also limits the current output range.

In this dissertation, a mixed-signal method is proposed to remove the limitations on
the output range. The principle diagram of the new method is illustrated in Figure 4.5. It
is based on the integrator in Figure 4.4. However, instead of storing the integration result
solely on the capacitor as in Figure 4.4, this new method stores the result in both the
digital and analog domains. It can provide a large output range because the digital

representation (binary number) is very ﬂexible with regard to range expansion.

In Figure 4.5, the capacitor and two counters are initially reset. During the
integration, the input current is continuously fed into the integrator and charges

65

 

 

 

 

-Vth 0—

 

 

Figure 4.5. The mixed mode integrator diagram.

(discharges) the integrating capacitor. There are two comparators to set the lower
boundary (- Vth) and upper boundary (Vth) of the integrator’s output. Once the output is

6619’

above this range the comparator outputs . The clock signal samples the 1’s and feeds
the proper reference current in at the input in order to subtract the absolute value of the

voltage drop on the capacitor by a ﬁxed amount in one clock cycle. The voltage change

(A V) due to the reference compensation current is:

AV ___ Iref 'Tclk

C (4.3)

where T C”, is the period of the clock. Meanwhile, two synchronized counters count the

‘61,,

clocked output of the comparators. For example, if D becomes at a clock edge, the
counter (P) counts 1 and a A V is subtracted from the simple integrator’s result.
Alternatively, if D‘=l, the counter (N) counts 1 and a AV is added to the simple
integrator’s result. At the end of the integration, we have three values stored in the system:

the simple integrator’s analog output, and the two counters’ outputs in the digital domain.

Counter (P) and counter (N) store the number of D=1’s and D*=l’s respectively.

66

Applying the charge conservation theory for the integration process, we can recover the

integration result expressed by

% LT ImdtereS +AVZDi—AVZD’i" = res +Av(2Di_ZD’;) (4.4)

where V,“ is the simple integrator’s analog output at the end of integration, and 2Di and

2D: are the value of counter (P) and counter (N).

As this integrator is targeted for the long integration duration, the counter could
overﬂow. In order to decrease the count for D and D*, Vth is set large and A V is chosen
very close to Vth such that consecutive l’s at D and D* are minimized. Thus, this
integrator can work with a very long integration duration (tens of seconds and greater)
with a reasonably sized counter. Leakage could be a problem with the long integration
time. However, in this proposed EIS solution, leakage is cancelled automatically and

does not deteriorate the result. This will be detailed later in this chapter.

4.2 Analog-to-digitalconvertor
The proposed integrator already partially digitizes the result. If A V is taken as the

reference unit, the digital output results of the new integrator represent the integer part of
the digital output, which is the difference of the counter (P) and the counter (N) as shown
in (4.4). The residue value at the simple integrator output represents the decimal part of
the result if AV> V,;,. With an increase in integration time, i.e. more than one stimulus
cycle, Vm becomes insigniﬁcant in (4.4). Thus, the counter (N) and the counter (P)
already provide enough resolution, and we can ignore the residue analog output (Vres).

The output of the ADC is just the difference of counter (P) and counter (N). In an E18

67

application, a long integration time is always required due to the low frequency
interrogations. For a high stimulus frequency, the integration can be performed for
several consecutive stimulus cycles in order to extend the integration time. Thus, the
analog to digital conversion is realized without any additional hardware other than the

new proposed integrator itself.

4.3 Analog multiplication for E18 applications
The multiplier is employed in EIS system to extract the real part or imaginary part

of the response. Its function is summarized in equations (3.3) and (3.4). The integrators
that follow the multiplier pick out the DC components and suppress the AC interference
(Figure 3.4). As long as the multiplier is a balanced structure, its linearity and offset are
not critical in an FRA-based IS system because the integrator will suppress all AC
interference that they introduce. For an unbalanced structure, the odd order harmonics
will introduce error in the DC information (see the discussion in section 3.2.2). The
consumption of both power and silicon area is very important because this IS circuit will
be instantiated for every miniaturized biosensor element in an array. There are several
options for an integrated CMOS analog multiplier. These options will be studied in this

section, and a solution for the proposed EIS system will be proposed.

The most commonly used analog multipliers are ones built with CMOS transistors
working within a strong inversion region [67-70]. These multipliers, based on the large
signal models of CMOS transistors in a linear or saturation region, provide good linearity
for large signals. Their offset is also small because transistors operating above threshold
possess better matching performance. They achieve good performance with high power,

which limits their application in a multichannel EIS system.

68

Because multiplier linearity and offset are not critical for an FRA-based EIS
solution, analog multipliers working in the sub-threshold region, which have large
nonlinearity and offset but consume small area and power, are better options. Figure 4.6(a)
shows a Gilbert analog multiplier realized with CMOS in the sub-threshold region [75]. It
is a balanced structure and works with a small bias current. Rairigh [76] proposed an EIS
system with a similar sub-threshold CMOS analog multiplier. Another kind of sub-
threshold CMOS analog multiplier is the CMOS translinear principle based multiplier
[65]. One example of this multiplier is shown in Figure 4.6 (b). Its output can be
expressed as,

I I
Iout = 41; (4.5)
3

where 11, 12, and 13 are the current sources shown in Figure 4.6(b). The problem with this

structure is that it is not balanced and therefore it is not suitable for EIS applications.

Modulation based analog multipliers provide very good linearity and accuracy[66].

ICT+ h3-

X+ X+

 

Vb

 

(a) (b)

Figure 4.6. The subthrehold multiplier: (a) Gilbert subthreshold CMOS analog
multiplier, (b) CMOS translinear principle based multiplier.

69

They convert one input of the multiplier into time domain information (sequence of
pulses) and modulate this with the other input. The penalty is the complicated hardware.

Thus, they are not good solutions for an EIS system.

All of the above multiplier solutions provide multiplication between two analog
inputs. As discussed in Chapter 3, for the F RA-based solution, the non-ideal effects of the
analog multiplier are not a problem as long as the multiplier has a balanced topology.
Thus, the chopping circuit in Figure 4.7, which has a balanced structure, could be a good
choice. One of its inputs is a digital signal (X) that controls the two switches in Figure 4.7.
At the differential output, the analog input signal (Y) is modulated by X. There are many
frequency components at the differential output, but the component representing to the
product of the two signals (X and Y) is located at DC. All of the other components are
located at other frequencies and would be suppressed by the integrator in the overall EIS

system. The principle is explained below.

Assume an integrator is used to integrate the differential output current in Figure

4.7. Let Y be the response of the biosensor in a BIS interrogation,

Y = B sin((1)t + (p) (4.6)
Let X be a square wave with a 50% duty cycle. Its ﬁ'equency is also (1) and it is in
phase with sin(a)t) such that

1, nT s t<nT+ T/2

4.7
-1, nT+T/2 St<(n+I)T ( )

X = sgn(sin(wt)) = {

where T is the period of the stimulus signal. If the integration time is set to the period of
the stimulus, the result of the integration is:

70

Figure 4.7. A simpliﬁed chopping circuit, Y is a current input, X is large square-wave
signal.

T
__ l T _ 1 3 . l T .
[out - ¥ I) Yth — T I) bsm((r)t + (p)dt "IT [gbsrnwot + (p)dt (4.8)

Solving this integral, we get

I out = %[cos(wT + (p) — 2 cos ((DTT + (p) + cos((p)] (4.9)

Substituting wT with 27: in (4.8), 10m becomes

b
IOUI = 1:; COS((p) (4.10)

which is the scaled real part of the response current. Similarly, if the square-wave signal
is in phase with cos(mt), X is given by
1, nT S t<nT+T/4
X =sgn(c0s(a)t))= -l, nT+T/4St<(nT+4T/3) (4.11)
1, nT+4T/3 S t<(n+I)T

Thus, the integration result is

1 T 2
I =— Yth=-bsin 4.12
out T L 1t ((1)) ( )

71

which is proportional to the imaginary part of the response.

(4.6)-(4.12) show that the desired impedance information can be extracted through
multiplying the analog response signal with a digital reference signal using a chopping
ampliﬁer. However, the chopping technique changes the direction of the signals (Y in
Figure 4.7). For a compact IS system, the input signal is a sensor’s current response to a
sinusoid stimulus, and thus the direction of the sensor’s response current can not be
reversed directly. Although this current could be mirrored to generate a copy in the
reverse-direction, resolution would be lost due to mirroring mismatch. Instead of building
a dedicated chopping circuit for the multiplication ﬁinction, the chopping multiplication
function is incorporated into the analog integrator in this dissertation. The new integrator
is shown in Figure 4.8. Instead of reversing the input current direction at the clock edge,
the polarity of the integrator itself is reversed by ﬂipping the integrating capacitor.
During an integration cycle, the capacitor connects in one direction for the ﬁrst half cycle
and its direction is changed for the second half cycle. In terms of the charge on the
capacitor, this ﬂipping operation changes the direction of the input current. In short, this
system (shown in Figure 4.8) changes the sign of the integrator instead of the direction

of the input signal.

cpl in Figure 4.8 represents the reference square wave. At time 0, the integrator is
reset. The multiplication integrator works from time 0 to time T, which is the period of

the reference signal. Assuming cpl is in phase with sin(cot) , as shown in waveform (a) in
Figure 4.8, and [in is Asin(a)t‘|6) , then Vout at time T+ (+ sign means after the rising

edge oftpl) is

72

Reset «)1 in phasle_I with sin(wt)

 

 

 

 

 

_/__
«11 «p1
_/ _ 7:
«,7 w (a)
Iin "/ "‘ (p1 in phase with cos(wt)
._-1_\
o Vout

 

 

 

'7.
\

(b)

Figure 4.8. Multiplication integrator.
T / 2 T

Vout: —1-CJ‘Iindt—i [IindtzZ—[Acosﬂﬂ (4.13)

0 T/2

The result is proportional to real part of the input current signal. Similarly, if cpl is in

phase with cos(a)t) , shown in waveform (b) in Figure 4.8, then Vout at time T+ is

1 TM 3T/4 T 2r
Vout:E [ Iindt— [ Iindt+ [ Iindt =—EAsin(e) (4)4)
0 T/4 3T/4 7’

The result is proportional to the imaginary part of the input current signal.

Saving chip area, this multipling integrator realized the multiplication function
without any dedicated hardware for an analog multiplier. Another advantage of this
circuit is that it is immune to the integrator’s leakage. For a general analog integrator, the
leakage current at the op-amp’s negative input node will steal charge from the integrating
capacitor, which results in a loss of information for periods of long integration. In the
multipling integrator, the capacitor is ﬂipped back and forth according to the square wave,

and the leakage current steals charge from both plates of the integrator. Because the

73

voltage at the op-amp’s negative input is ﬁxed by the feedback loop, the leakage current
is constant. With the 50% duty cycle square wave, this constant leakage current will steal
the same amount of charge from both plates of capacitor, and its affect is canceled at the

end of the integration.

4.4 Lock-in ADC

The realization of chopping techniques on a simple capacitor integrator (Figure 4.8)
could also migrate to the proposed mixed—mode integrator to expand its output range and
digitize its result, as shown in Figure 4.9. This block diagram shows the detailed system

of the lock-in ADC shown in Figure 4.3. It is the core of the compact IS system.

(p1 in Figure 4.9 represents the reference square wave. The left portion of the circuit
is the multipling integrator. The rest of the circuit is the digitizer. Similar to the mixed-
mode integrator presented in Figure 4.5, two comparators and two reference currents

(Irefl or Iref2 ) are used to digitize the integrator’s output and keep it within the pre-

 

 

 

Reset
.__/—__ ‘

«31 $1

0T / 4

W W

I' lref1 '-
'."-» _ D
lrefz 4. Mom 0"

 

oun er E
+/-/shifter =

N)—

   

 

   

CLK—

 
 

Figure 4.9. Block diagram of the lock-in ADC based IS system.

74

deﬁned range. The system in Figure 4.9 requires two bidirectional counters to count the
events on two comparator’s outputs. Their counting mode (up/down counting) is
controlled by (01. If (p1 is high, the counter is conﬁgured as an up counter; if (pl is low, it
is in down counting mode. At the end of a measurement, the contents of these two

counters show the digitization result. The procedure will be detailed below.

There are two clock domains in this system, i.e, the updating clock (clk in Figure
4.9) and the chopping clock ((p in Figure 4.9). The former is a ﬁxed frequency clock. The
latter’s frequency is equal to the stimulus frequency, which is variable. In some

situations, this could result in error, and a method to deal with it will be discussed later.

To simplify the explanation of the operation of the lock-in ADC system, let’s
assume that at any (01’s transition edge, both D and D* are low. The general case will be
considered later. Suppose (01 is in phase with sin(wt) , as the waveform (a) in Figure 4.8.
After resetting the counters and integrating capacitor at time 0, the integrator starts its
work. (p1 is 1 from time 0 to T/2. At time T/2 (before the (pl ’8 edge), based on the charge

conservation theory for the input node, we have

T / 2 N N *
[ Iindt = CUVresl — IreflUTOZ Di+ IrefZUTOZ Di (4.15)

O 1 l

where er is the residue value at the integrator output, To is the updating clock period,
and N is the number of clock cycles from time 0 to T/2. During this period, counters are
set to up counting mode because (01 is high. The counters are reset at time 0. At time T/2,
the counter (P)’s content is the summation of the D.- ’s and that of counter (N) is the

summation of the D: ’5. Both of the summations are included in (4.15).

75

At time T/2, the integrator capacitor is ﬂipped. Immediately following, the

integrator’s output becomes ('Vresl). From time T/2 to T - (before the (pl’s rising edge),

the following equation holds

T 2N 2N
I Iindt = C (Vresl + VresZ) — [ref 1T0 Z Di-i- Iref2TO 2 Di (4.16)
T / 2 N+1 N-i-l

where Vrcs2 represents the integrator’s output voltage at time T (before the (01’s rising

edge). (VmiJerz) represents the voltage change from time T/2 to T. After (pI’s rising

edge at time T, the integrator capacitor is ﬂipped back, and integrator’s output becomes

N N
(-sz ). During this half cycle, the counters initial values are 29, and 21): ,
1 1

respectively; and both counters are set to down counting mode because (p1 is low. At the

N 2N
end (time T), counter (P)’s content is [2 Di- 2: Di] and that of counter (N) is
l N+l

N 2N
[2 D: - 2 D:]. To show the result over the entire cycle, we must subtract (4.16) from
1 N+l

(4.15), which gives ,

T/2 T/Z
J‘ Iindt- [ Iindt
0 0
N 2N N 2N
=-CVresl—IreflTO(ZDi- Z Di]+lref2TO[ZD:— 2 Dr] (417)
l 2N+1 1 2N+i

N 2N N * 2N a
z—IreflTO ZDi— 2 Di +Iref2T0 Di 2 Di

1 2N+l l 2N+l

76

From (4.13) we know that the left side of (4.17) is proportional to the coefﬁcient of the
real portion of the input signal. The right hand side of (4.17) shows that the result is

composed of the residue value on integrator and the contents in the two counters.

Because we chose the parameters such that lCVrcsl

 

<%maX(1rcflT0.Ircf2T0) , we can ignore

the analog residue portion and treat it as noise. Thus, the real portion information is
presented digitally by two counters. The digitalized real portion coefﬁcient can be

recovered by

A=Counter (N)-k1 *Counter(P) (4.18)

,where k] counts for the mismatching of two reference currents (Irefl and Ire/2).
Calibration is needed to ﬁnd k1 for an accurate readout. The calibration method will be

discussed later in the dissertation.

Similarly, if (01 is in phase with cos(a)t) , the counter’s results carry the digitized

imaginary coefﬁcient information of the input signal.

We assumed that both D and D* were low at the transition edge of (01. Now we will

 

 

 

 

 

 

//\ 4" Vth
c ‘ /
Vout \ / \ // o
\/ ,\ \( Vth
o1 \
D

 

 

ﬂ

 

rLrLiLuu T 1111er

Figure 4.10. Waveform of the compensation current control signal (D and D* in
Figure 4.9), for D and D* are low on the ﬂipping of the capacitor.

 

 

 

 

 

 

 

 

S J/IMT\ \\
E [\W

 

 

 

 

77

discuss the case where D or D* is high at the transition edge of (01. When either of them
is high, they require a ﬁxed amount of compensating charge to draw the integrator’s
voltage output back into the range during a clock cycle by controlling the reference
currents. If the integrator capacitor’s polarity is changed due to (01’s edge during the
process, the polarity of this charge should have also been reversed accordingly.
Otherwise, it would result in an error up to one digitized step. To take care of this issue,
multiplexing switches at the inputs and outputs of the D-ﬂip ﬂops are inserted as shown
in Figure 4.9. If D is high when (pl’s rising edge comes, these switches will provide the
waveforms shown in Figure 4.10. When (pl’s edge arrives, D is high. It charges the
integrator with 1,4,. After (pl ’3 edge, D goes low and D* becomes high, which will
charge the integrator with Ire/2. 1,41 and 1,312 are set to be equal. This switching between
Ire/1 and 1“,); changes the polarity of the charge to match that of the integrator capacitor
because the two currents have the same values but different polarities. The waveform of
the integrator’s output is also plotted in Figure 4.10. Practically, there is still a mismatch
between these two currents, but it can be easily controlled to within 1%. As a result, this

feature suppresses the error to be much smaller than one digitized step.

k] in (4.15) represents the mismatch between 1,41 and 1,612. We need to extract k]
for the real circuit to accurately recover the impedance information based on (4.15). If
only a DC current is injected into the system in Figure 4.9, it will charge two plates of the
integrating capacitor equally because every plate is connected to the input for 50% of the
conversion process. As a result, its effect is canceled completely for any frequency of (01.

Thus, the counters result should give a zero with (4.18) and kl is found by

k1=Counter(N)/Counter(P) (4.19)

78

4.5 Synchronization of signals from two clock domains

As mentioned earlier in this chapter, the chopping signal and the updating clock are
independent, but it is possible for both signals to transition at the same time. This edge
coincidence should be avoided for proper operation of the system. The control signal
generator block generates all the control and clocks needed for the IS system, and
eliminates the edge coincidence. The principle block diagram of the control generator is

shown in Figure 4.11.

Although the chopping signal and the updating clock are in different clock domains,
we can synchronize them with a clock that is much higher frequency than either signal.
The error introduced due to this synchronization is negligible if the synchronizing clock
frequency is high enough. In Figure 4.11, the input sinusoid is converted to a square wave
by two digital inverters. DF F 1~DF F3 are used to synchronize this square wave and
produce three copies of it, each with a slightly different delay. The output of DFF2 is
used as the internal chopping control signal. The outputs of DF F 1 and DF F 3 form a pulse
through an XOR gate, and the edges of the chopping signal occur within the center of the
pulse. The updating clock is derived from the main clock of IOMHz by dividing by 100.
DFF4 is used to resynchronize the updating clock. The clock input of DFF4 is gate-
controlled by the pulse, which blocks the events of the updating clock within the pulse
duration. Because the pulse spans the chopping clock edge, it protects the chopping clock

against any potential change from the updating clock.

The synchronization of the two signals from different clock domains to avoid any
edge coincidence introduces some error. In the derivation of the chopping techniques for

real/imaginary part extraction, it is assumed that the chopping signal and the sinusoid

79

chopping clock

 

Sin
updaﬁng
clock

   

Main Clock
(1OMHz)

 

Figure 4.11. Block diagram of the control block, which generates the updating clock and
the chopping control signal. An XOR gate is used to generate a pulse covering the edge
of the chopping clock. This pulse will block the change on the updating clock through
gating the clock of DF F4 and therefore avoiding conﬂict between the chopping signal and
the updating clock.

should be in phase. For the chopping signals in Figure 4.11, the synchronization method
described above introduces a delay of up to two IOMHz clock cycles compared to the
sinusoid. However, since the frequency of the sinusoid is much lower than lOMHz
(lOkHz maximum), these delays only introduce negligible error. At the same time, when
the pulse suppresses changes from the updating clock, it changes the period of frequency
update by two consecutive lOMHz clock cycles surrounding the pulse. However, this

error can also be neglected due to the relative high frequency of the main clock.

4.6 Circuit realization

Three major circuits are employed by the lock-in ADC in Figure 4.9. They are an
op-amp, a comparator and a bidirectional counter/shifter. These blocks are realized with

the AMI 0.5um CMOS process.

4.6.1 Op-arnp
Figure 4.12 shows the op-amp circuit. A folded cascode structure is implemented
because it provides sufﬁcient DC gain within a single stage. Because there is only one

dominant pole in this structure and its load is only a capacitor, no extra hardware is

80

vddr
250nAl [250m

W4 41%] 500nA jF—‘ji:
W41: JIH- 3'”

jP—M—I

vb2

 

 

 

 

 

 

 

vout

 

 

 

 

 

nd

Figure 4.12. Folded cascade op—amp circuit designed for the lock-in ADC system.

required for stability compensation. With a total current consumption of luA, this circuit
works in the sub-threshold region. The simulation results in Figure 4.13 show that it can
provide 76dB DC gain with a unit gain bandwidth of 870kHz. A lpF capacitor is used as
a load in the simulation because the designed integrator capacitor in Figure 4.9 is lpF.
For a targeted lO-bit resolution and lOOkHz clock, this ampliﬁer provides enough DC

gain and bandwidth.

4.6.2 Comparator

Two comparators are employed in Figure 4.9. In order to save silicon area, a circuit
that combines these functions into one dual level comparator was designed and is shown
in Figure 4.14. This is an ampliﬁer-based comparator, and its output logic is deﬁned in
Figure 4.14. A DC sweep simulation was performed on the input voltage to check its

functionality, and the result is plotted in Figure 4.15.

81

0.00

DC gain=76dB

Phase marge=86 -2a.o
Condition: 1pF Cap A
en
a -4a.a 2
'O O)
v -619 (D
C 'O
'5 v
0) 410.0 3
2
400 a.

-120

1 10 1K 10K 1 10M

 

Frequency (Hz)

Figure 4.13. AC simulation of the ampliﬁer in Figure 4.12.

4.6.3 Bidirectional counter/shifter

Two bidirectional counters are employed to count D’s and D*’s during the
conversion process. Due to the limited number of chip I/O pads and the potential need for
a large number of counters (up to 100) within a multi-channel microsystem, it would be a
signiﬁcant advantage if the outputs of multiple EIS cells could to be read out through a
serial data link. Thus, a shift register based counter structure was selected[77, 78]. As
speed is not critical in this microsystem with up to a lOOkHz clock, an asynchronous
counter was chosen to avoid unnecessary dynamic power for unchanging bits. In [29], a
very compact size counter/shifting register is designed. It achieves hardware efﬁciency
through sharing most of the hardware between the asynchronous counter and shift
register. The counter in [29] was conﬁgured as a up counter, and it is also feasible to
conﬁgure it to function as a down counter. However, to build a bidirectional counter,
more complicated control logic is normally required to enable dynamic switching
between the two working modes. The scale of such control logic increases exponentially

as the number of bits increases. In this biosensor microsystem application, the counter’s

82

vdd

4d 1446
_D- Dhi
m"? 3p... 3p... DH”

 

 

 

 

 

 

[E -Vin<V|o : Dhi=0, D|o=0
|_]_| Ll -Vlo<Vin<Vhi : 010:1, Dhi=0
L3 E] 9,, -Vin>Vhi :Dhi=1, Dlo=1

Figure 4.14. Circuit schematic of a dual-level comparator.

 

 

 

 

 

 

 

4.0 .

 

3.0 . i

Volts
9
o

|
2.0 . j
I
I
I

 

P
0.0 A-4, #14444“HAJHA_. --;A .....................

 

Vin
Vhi (1 .5Volts)

   
  
 
  

  

 

Volts

 

Vio (1 .1Volts)

      

1 4 1.6 2.0

Vin (Volts)
Figure 4.15. The input voltage DC sweep of the dual level comparator.
number of bits is set to twenty to support a wide range of sensor responses. Thus, the size
(and power) of conventional up/down counter structures and their control circuitry
present a limitation that must be addressed by designing a new ultra compact

bidirectional counter/shifter circuit. The new counter is based on the up counter proposed

83

in [49], but an algorithrn-based, down counting method was developed so that it can reuse

the up counting circuits with some minor modiﬁcations.

The counters in the Figure 4.9 count down (minus 1) many times when (pl is low.
With a 4-bit counter taken as an example, if a countdown by n were to happen during a

period where (pl was low,, the counter result could be expressed as

33323130 — n (4.20)

where a,a,ala0 is the initial value of the counter. It can also be rewritten as

a3812211810 - n = -(-a3azarao + n) (4.21)

In two’s complement representation, the negative operation can be performed by a bit

inversion plus ‘ l ’

‘33323130 = a331241310 +1 (422)
Thus, (4.20) can be rewritten as

33323130 —n
= -(-a3azalao + n)

= —((a3a2a1a0 +1)+n) *

=-(5§£5§E+n)-1 (4.23)

 

=((333231—3_(;+n)+1)—1 *

 

= (a3a2a1a0 +n)

Steps with a (*) mean that the two’s compliment representation for the negative sign

operation was performed. The beginning of (4.23) represents the counting down by n, and

84

latch A latch B

outp

31—— . ——IE
_ a a

”LI I I LIE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M1 M2
sh ift_ph_1_| _I |_ | I_ I3" "1-th
E. 9 I; 9 9
cnt_en:
inv_ph1:
inv_ph2A

 

Figure 4.16. Schematic of the new up/down counter with shift register capability.

up bit down bit ready
counting inversion counting inversion for
output

 

 

cnt_en

inv_ph1 |—] [_l

inv_ph2 m n
shift_p_h1 "JUL
shift_ph2 [ULH

Figure 4.17. Waveform of the control signals for the proposed bidirectional
counter/ shifter.

 

 

 

 

 

 

 

 

 

 

 

the end of (4.23) shows that only bit inversion and up counting by n is performed. Thus,
we see that the counting down can be achieved by simply counting up with a bit-
inversions at the start and end of counting down operation. This concept can be applied to
generate an up/down counter using an up counting circuit and minimal additional

hardware.

85

To realize this idea, an up counter/shifter circuit cell with the bit inversion
capability was designed and is shown in Figure 4.16. It is based on the up
counter/shifting register in [49]. Two NMOS transistors (M1 and M2) and related control
signals are inserted to provide the bit inversion capability. This circuit has two latches
built with two back to back connected inverters. Both its input and output are in
differential form. In counting mode, both shift-p111 and shift _ph2 are set to be low and
cnt_en is set to be high. In shifting mode, cnt_en is low, and the non-overlapping signals
shift _phl and shift _ph2 shift the input to the output. In bit inversion mode, both cnt_en
and shifting control signals (shiftth and shift _ph2) are kept low. The non-overlapping
square pulses on inv_phI and inv_ph2 force the ﬂip-ﬂop to invert its state. The pulse of
inv_ph] comes ﬁrst and inverts latch A. Then the pulse of inv_ph2 causes latch B to
invert too. According to (4.23), for proper operation it is important to make sure that the
bit inversions are performed both before and alter any consecutive down counting cycle.
The waveforms of the control signals for proper operation are summarized in Figure 4.17.
This bidirectional counter/shifter contains only 24 transistors, which is less than the D
ﬂip-ﬂop standard cell (28 transistors) developed by Tanner[79]. Because most of the
transistors in Figure 4.17 are NMOS, it is easier to achieve higher hardware efﬁciency
than a D ﬂip-ﬂop, which has the same number of both NMOS and PMOS transistors.
With this compact cell circuit in Figure 4.16, a multi-bit bidirectional counter can be built
as shown in Figure 4.18. Two 20-bit bidirectional counters/shifters are employed for the

lock-in ADC in Figure 4.9.

86

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

_ mp outp— inp outp— — inp outp—0L”
In —1nn outn—inn outn— —inn outn—
m m m I” m m
5'5'3'2'. S'S'S‘Z 5533
I< l<|§|=a g '< |<|5I=1 g I< l< 5': g
o-o- r-o- ] o-e-
3 33?. lo 3 Egg lo 3 3312's
inv_phvllllll lllll _l
iﬁvr£m 51 I I I I I I I I
shjﬁ. l I l l l I ..
sﬁyﬂi 252 l l I I
cnlzsn L l

 

 

 

Figure 4.18. Block diagram of the scalable up/down counter.

   
 

 
 

s»: “I :11] III 1111151131.-..“ it . '
Chopping“ Mi. Comp. III
integrators;E nPair Ii ESSESEﬁEEh 1- 1117:.“31 1'11 -----

/7 "1
&/ éﬁm (“E-E- "‘E Jif‘

I“.

 

'I

1 sun“ i.1;: L's-'4‘ ..1.» __11__-“ attain-"1. 11: _'__1"-11““

 

 

 

{I i=- .l—Hz'sJi' Ht... lunl~1 ianiiodulao .35 I_ _'__liréoi "ii"

_Qmﬁ‘lu‘

 

Figure 4.19. The layout of the lock-in ADC (600um X lOOum).

4.6.4 System integration

Using the compact VLSI realization of functional blocks described above, the

integrated lock-in ADC in Figure 4.9 was constructed, and the layout of this cell is shown

in Figure 4.19. The whole circuit occupies an area of only 0.06mm2. With this size, a

3mm by 3mm die can integrate more than lOOcells, which is enough for current and

anticipated microsystem needs. A system level transient simulation was performed to

verify its functionality. For this ﬁrnction veriﬁcation simulation, a lkHz sinusoid input

was chosen and simulation was continued for just one cycle to cut down simulation time.

In real operation, with a lOOkHz clock, there are only 10 clock cycles within one cycle of

the lOkHz stimulus. In order to obtain high resolution, it needs to run for at least 100

stimulus cycles for a lOkHz frequency point.
critical signals are plotted in Figure 4.20. Comparing the simulation result in Figure 4.20

with the waveform in Figure 4.10, we can conclude that it functions as expected.

87

The simulated waveforms of several

(Volt)

(Volt)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

: onecycle :
1.5[ Vth
I
. .- ........0
III \th
I- . .
‘ 1—
0I . . j . i “’1
‘iL
. III- [I II - III II II II I o:
4
.1 II - III II II II III - II - o.
4 ' 1 1-111 11 11‘11 . 1 1 " -?1'1 "1
05:1..IIIII11I1II1III1I1I.1II1=II:IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIllIII|||II|1IIII|IIIIII::II|1|I|IIIIIIIIIIIIIIIIIII 6'11
0.00 200u 400 5'71 z 1 11 1.00111 1.20m
lime(s)
capf'lipping
; (Vout
13 v 0
1:1 \/ ; w -vm
‘ an
or 1 j
4 ' 0*
(1F 1 ﬂ 1 _ .
4
. D
4- ;
o-I‘Iﬂl—Iﬂﬂl‘lﬂﬂﬂI—Iﬂﬂﬂﬂﬂﬂﬂﬂﬂlﬁi

 

50011 540u 580u 620u 66011 70011

limei(s)

Figure 4.20. The simulation waveforms of some signals in the lock-in ADC system.
The input sinusoid stimulus frequency is lkHz.

4.7 Conclusion

electrochemical impedance spectroscopy system in this chapter. It performs not only the
impedance information extraction, but also impedance information digitization. With the
help of this structure, the signal processing load of a biosensor array based EIS system
can be distributed to each channel. The result of this chapter proves the feasibility of the
multi-channel on-chip IS microsystem proposed in Chapter 3. Utilizing the AMI 0.5um

CMOS technology, a compact VLSI circuit realization is also achieved. A new super

A new structure is developed for a compact readout channel for an on-chip

88

compact bidirectional counter/shifter circuit is designed to signiﬁcantly improve

hardware efﬁciency. The test results of this circuit will be described in Chapter 6.

89

5 Integrated Quadrature Sinusoid Signal Generator

A qudrature sinusoid signal generator is a signal generator that can produce a sine
wave (in-phase) and a cosine wave (qudrature phase) at the same frequency
simultaneously. This function is necessary for the proposed on-chip EIS system. As
discussed in Chapter 3, the frequency range of the output signal is expected to be lmHz
to lOkHz. The matching between the in-phase output and qudrature phase output is very
critical. The target spurious free dynamic range (SFDR) of the sinusoid output is above
48dB. In this chapter, an on-chip qudrature sinusoid signal generator is developed to meet
the requirements of the on-chip EIS system. A new hybrid structure is developed to
achieve the required frequency range while keeping good in-phase qudrature-phase

matching (IQ matching).

5.1 Approaches for the sinusoid signal generator

In commercial products and research papers, many solutions for a sinusoid signal
generator are implemented. Generally speaking, they can be categorized in to three
groups: digital signal processing (DSP) based solutions, oscillator based solutions and

non linear circuit based solutions.

5.1.] Digital signal processing based sinusoid generator

DSP based solutions generate the sinusoid signal through digital means [80, 81].
They consist of a digital memory bank, digital signal processor, digital to analog
converter, and analog output circuits. As these methods operate in the digital domain and
employs mature technologies, they provide very reliable performance and are therefore

widely used in industry. There are two main architectures used to generate the sinusoid

90

with the DSP. One is a variable-clock-based method, while the other is a direct digital

synthesis (DDS) based method.

Figure 5.1 shows the block diagram of the variable-clock-based method. A memory
block is used to store all of the digitized samples of a periodic waveform over an entire
period. A clocked address decoder enumerates all memory contents sequentially. The
output of the memory reconstructs the periodic waveform in the digital domain. The
frequency of the waveform is determined by the frequency of the updating clock. Finally,
the digital to analog convertor translates the waveform to the analog domain. At the

output of the generator, an analog ﬁlter smoothes the output and produces a clear image.

Similarly, a DDS based solution also employs a waveform memory block, which is
enumerated by a clock. However, the frequency of the clock is ﬁxed, as shown in Figure
5.2. The phase increment (delta phase) is tunable to control the frequency of the output
waveform. Instead of sweeping across the entire waveform memory contents one by one,
in DDS based systems the address decoder bypasses a certain number of memory
addresses between two ﬁxed-clock readings. The number of memory elements bypassed
is controlled by the delta phase. The higher the delta phase, the more memory cells are

bypassed, and therefore the higher the frequency of the output signal.

The digital signal processing based method is very ﬂexible and can produce nearly

Variable Waveform 9339's: OUTPUT
Clock Memory output

Figure 5.1.The block diagram of the variable clock based digital domain signal
generator.

 

 

 

91

 

 

 

Waveform » éi'litae'fg OUTPUT
Mammy output

Figure 5.2. The block diagram of the direct digital synthesis based signal generator.

 

 

 

 

 

 

all shapes of waveforms. It can generate any periodic pattern as long as it has been saved
in the waveform memory. For qudrature sinusoid outputs, it can also maintain good IQ
matching with a preloaded waveform memory. The main drawback of this system is that
it requires a very large memory, and thus large chip area, to generate low frequency
signals. In order to relax the design requirements of the analog ﬁlter, the replicas in the
DAC output should be distanced from the signal. Thus, the update clock frequency can
not be very low. With a relatively high update clock frequency, a large oversampling
ratio is expected for low frequency signals. As a result, a large memory space is needed
due to the large number of samples. The physical size of large memory limits its
application in an on-chip EIS system, where a lot of area is dedicated to on-chip
biosensors. For only a high frequency sinusoid generator, a DSP based method is
overqualiﬁed because it can generate any kind of periodic signal. The required ﬂexibility
in waveforms is achieved through generalizing the generator’s structures. This results in

complicated hardware that can then be optimized for only sinusoid generation.

5.1.2 The oscillator based sinusoid signal generator

92

An oscillator is the most widely used circuit to generate pure sine waves. There are
many ways to build an oscillator, such as LC tank oscillators[82], RC oscillators[83] and
transconductance (gm)-C oscillators[84]. Qudrature oscillators are designed to generate
qudrature signals[85-88]. In all oscillator based sinusoid signal generators, the frequency
is controlled by the circuit components through factors such as the inductance, resistance,
capacitance and transconductance. Frequency tuning is realized with the control of these
parameters. In order to maintain a good accuracy in frequency, a feedback loop (which is
always a phase locked loop) is used to track the output frequency with respect to a
reference. The problem with these oscillator based signal generators is that it is hard to
cover a wide frequency range because the component values, which control the frequency,
can not change over a very wide range (7~8 orders of magnitude are desired). ,A
subthreshold, widely tunable, CMOS transconductance providing a frequency tuning
range over 7 decades has been presented [89], but accurate frequency control is difﬁcult

because it is impractical to exactly tune the transconductance over that range.

5.1.3 Nonlinear transfer function based signal generator.

In nonlinear transfer function based methods, a triangle wave is generated ﬁrst.
Then a nonlinear transformation is performed on the triangle wave to approximate the
sine waveform, as shown in Figure 5.3 (a). The tank ﬁmction is a good transformation for
a sine wave output. Bipolar transistors can be used to realize the tanh function, which is
explicit in Figure 5 .3 (b) [90]. A diode and a MOS transistor can also be used to realize a

nonlinear function that is suitable for synthesizing a sine wave[9l, 92].

93

Although this nonlinear transfer function based method makes the realization of the
sinusoid signal generator easy due to the ease of generating a triangle wave; its main
drawback is its linearity. It depends on the tanh function to approximate half a sine wave.
It is important to pick the right range of the nonlinear transfer function to make a good
approximation. A nonlinearity of 0.2% is reported in[92] Thus, the peak value and the
common mode bias voltage of the triangle wave are very critical. For a board-level
design, it is feasible to tune the triangle wave generator to match the nonlinear transfer
function circuit. However, for on-chip applications, the nonlinear transfer function is
largely affected by the process and temperature variation of the device. This makes it
hard to control its quality in terms of linearity. Furthermore, if this type of generator is
employed for quadrature output, two identical nonlinear transfer functions are required.

The mismatching between them will directly contribute the IQ mismatch.

Transformation

Function I/

 

 

 

 

 

 

 

 

Output Sine Wave
Vin+ Vin-
Input
Triangle
waveform
v
(a) (b)

Figure 5.3. The principles of a triangle-to-sine signal generator: (a) transformation
from triangle waveform to sine waveform, (b) a typical circuit to perform the
transformation.

94

5.2 Hybrid quadrature sinusoid signal generator

All above mentioned solutions have some limitations for realizing an on-chip
quadrature sinusoid generator with good linearity and IQ matching in addition to accurate
frequency control over wide range (lmHz to lOkHz). A new architecture was developed
to meet these requirements. It is built with a hybrid structure, where different principles
are applied for the low frequency output and the high frequency output such that a wide
range of the frequencies are covered. For high frequencies (above lOOHz), an unevenly
tapped resistor chain with a tunable updating clock is employed. In the low frequency
range, a subsampling concept is utilized through a sample and hold circuit. It also
inherently keeps a good matching between in—phase and quadrature phase outputs
because two outputs are generated from the same resistor chain. The principle block
diagram illustrating the structure is shown in Figure 5.4. The proposed signal generator is
purely controlled by digital signals and its output frequency is set with respect to the
main input digital clock. Therefore high frequency accuracy is easily achieved. The

detailed design for each block will be addressed in the following.

5.2.1 Principles of an R-chain based quadrature sinusoid signal generator

With a DSP based signal generator, the waveform is stored in the memory block. A
tunable clock reads this memory block and then sends the results to a digital-to-analog
convertor (DAC) to produce the corresponding analog output. This system can generate
many varieties of periodic waveforms because the memory contents can be changed
according to the desired output waveform. If the output is only a sinusoid, the contents of
the memory are ﬁxed. In order to save hardware, the memory block can be eliminated

and the waveform information can be stored as analog signals in a resistor chain DAC.

95

R-Chain IQ SIN Gen for lOOHz ~ IOKHz

I‘d

 

 

 

_:D_s;u

analog
MUX

I COS

R-Chain DAC

 

 

I-d Inn-II... h-

L-.-----------------------------

r
I
I
I
I
!

 

 

 

 

--- II. -------------------

i

I

I

:

SI I
Sub-sampling :
DAC :
COc l

I

I

I

I

 

 

 

 

L—
lOMHz Clk [M
_’ Divider

111—1

 

 

 

 

 

 

 

a 7
. Subsampling IQ SIN Gen for lmHz ~ lOOHz

I-----------------------------------------

Figure 5.4. The principle structure for the proposed quadrature signal generator.

This principle is shown in Figure 5.5, where the data points of the sine wave are
stored in analog form with an oversampling ratio of fourteen. The top and bottom
voltages of the resistor chain in Figure 5.5 (b) are set to the peak and valley of the sine
wave. The resistor values are chosen such that each tapped point has a voltage equal to
the corresponding point in the sinusoid waveform (Figure 5.5 (a)).At any given time, only
one switch is tuned on. The main clock controls these switches to pick the correct tap in
the chain. The sequence of turning on the switches is l-2-34-5-6-7-8-7-6-5-4-3-2. By
repeating this sequence a sinusoid waveform is generated. In order to have a continuous
output, a ﬁlter is used to smooth the output waveform and ﬁlter out any replicas present

in the output.

5.2.2 The architecture of an R-chain based signal generator
As shown in Figure 5.6, in this design the same resistor chain is used for both the

sine wave output and cosine wave output. At each tapping point of the resistor chain,

96

there are two switches, one for the sine wave and the other for the cosine. A token ring

controls the two sets of switches. Two identical ﬁlters are used to smooth the each output.

5.2.3 R-Chain DAC design
An R-chain DAC is used to generate a quadrature sinusoid signal of lOOHz and

above. The most important parameter of the DAC is the number of taps along the resistor

Time
S<1>
V1 —
S<2>
V2 —
S<3>
V3 _

Vout

88>

CLK chh S<k8>
Control

 

 

(a) (b)

Figure 5.5. Example of a resistor chain based DAC working as sinusoid signal
generator (oversampling ratio is 14), (a) the sampling points in a sinusoid waveform;
(b) the structure of a DAC with an unevenly tapped resistor chain.

    
   
 

 

 
 
 
 

 

 

 

 

 

. SIN
Filter
00c" “ken RChain _Sl’lr variable
Rlng DAC COS CI Digitalpart
—/_ F'l
COS l:| Analogpart

Figure 5.6. Architecture of a resistor chain DAC based qudrature sinusoid signal
generator.

97

chain. This is decided by the oversampling ratio of the output sinusoid. Although more
taps correspond to better linearity, they also require more silicon area for the switches
and routing metal. Also, more taps complicate the switching control logic circuit because
more switches need to be controlled. In this section, the effect of the oversampling ratio
on the linearity of the DAC’s output is studied, and an optimized oversampling ratio is

selected.

The typical spectrum of the DAC’s output for a sinusoid waveform is shown in
Figure 5.7. The strengths of the fundamental signal and its replicas are enveloped by a
rectiﬁed sinc function, which results from the sample and hold feature of the output
waveform. The points of intersection between the rectiﬁed sinc ﬁmction and the

horizontal axis are located at multiples of the sampling frequency. The linearity is

9 .0
¢ 10 a
,/ >~

P
N

P
o

999
NU.»
'1
{0"
\
I

0
d
.\\\
//
\

/

 

amplitude(normalized to signal amplltude)
0
0|

 

1 V1 1 )A/ 1 ‘ q/l J
0.5 1 15 2 2.5 3 3.5
Frequency (normalized to sampling frequency)

 

O

 

0

Figure 5.7. The spectrum of an R-chain DAC. The envelop is a rectiﬁed sinc function,
the frequency is normalized to the sampling frequency, and the output amplitude is
normalized to the signal strength.

98

analyzed by studying the spurious free dynamic range (SF DR), which is deﬁned as,

SFDR = Strengh offundamental szgnal

 

Strengh 0f the total replicas

Due to the asymptotic decrease in the amplitude of the sine function, only the ﬁrst
replica has signiﬁcant effect. So, the relationship between the oversampling ratio and the

ﬁrst replica’s dominant SF DR is studied.

The strength of the fundamental frequency component in Figure 5.7 is,

 

 

 

 

 

 

 

 

 

 

 

 

 

sin [21: 31—]
2 S
A0 = f (5.1)
2“ i
2fs
where f0 is the output sinusoid frequency, fs is the updating frequency and
E=0ver sampling ratio (5.2)
S
Similarly, the strength of the ﬁrst replica is
K _ \ 7- r \2
sin 2n f3 f0 sin 21: f5 + f0
A 2fS + 2fS
= 5.3
1 l 2,,fs_—:Q_ mm ‘ >
\ 2fS J K 2fS )

and the ﬁrst replica’s dominant SFDR is

99

. A
SFDR = 2030g[A—(1)] (54)

Combining (5.1) - (5.4), the relationship between linearity and oversampling ratio is
developed, which is then plotted in Figure 5.8. It indicates that if the oversampling ratio
is greater than 512, a linearity of 50dB can be achieved directly. However, that
oversampling ratio is unrealistic in practice. The number of taps is roughly half of the
oversampling ratio. An oversampling ratio of 512 would correspond to 256 taps, which
will result in a very large amount of routing metal and taps, in addition to very
complicated digital control logic for switch control. Thus, it is preferable to lower the
oversampling ratio and employ a low pass ﬁlter (LPF) to further suppress any replicas.
Also, the oversampling ratio can not be too low. The oversampling ratio determines the
distance between the fundamental signal and its replicas. A very low oversampling ratio

tightens the performance requirements for the LPF. Thus, a tradeoff is made between the

 

60

 

U1
0

 

 

.b
O

 

 

SRDR (as)
2:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20
l
10 i
I
I
I
o . E
4 3 16 32 64 123 256 512 1024

Oversampling Ratio

Figure 5.8. Linearity versus oversampling ratio for the DAC’s output.

100

complexity of the LPF and that of the R-chain DAC. Therfore, an oversampling ratio of
64 was chosen. Only 33 taps are needed for this ratio, which is reasonable and feasible
for both hardware area and switch control logic complexity. With a 64x oversampling
ratio, the SFDR of the DAC’s sinusoid output is 33dB. The proceeding LPF should
provide at least l7dB suppression of replicas at a frequency of roughly 64x the signal

frequency.

In Figure 5.4, the main clock of lOMHz is divided to generate an updating clock for
the R-chain DAC. The highest output frequency of 156kHz is achieved by directly
employing the main clock as the updating clock. The low frequency of the R-chain based

signal generator is set to lOOHz to loosen the requirement on the ﬁlter.

5.2.4 Filter design for an R-chain based sinusoid signal generator

It is not difﬁcult to design a ﬁlter that suppresses the replicas 64x away from signals
by l7dB for a ﬁxed sampling frequency. However, in the R-chain based signal generator,
the sampling frequency is changing from MHz range to kHz range to cover a wide output
frequency range. In order to overcome this challenge, a reconﬁgurable LPF was
developed. The ﬁlter is a 2nd order Butterworth ﬁlter with three optional cutoff

frequencies. The conﬁgurations of the ﬁlter according to the output frequency is shown in

101

TABLE 5.1, CONFIGURATION OF THE FILTER FOR DIFFERENT OUTPUT
FREQUENCY RANGES

 

 

 

 

 

Output Cut off frequency of the 2nd Worst case ﬁrst replicas
Frequency Range order Butterworth LPF suppression
lOOHz— lKHz 2K -21dB @ lOOHz
lKHz — lOKHz 20K -21dB @ lKHz
Above lOKHz 200K -21dB @ lOKHz

 

 

 

 

5.2.5 Sub-sampling based quadrature sinusoid signal generator.

The R-chain DAC based signal generator is not suitable for low frequency sinusoid
output because the updating clock will scale down proportionally with the output
frequency and make it hard for the ﬁlter to suppress the replicas close to the desired
signals. Thus, for frequencies of lOOHz and lower, a sub-sampling based sinusoid signal
generator is proposed. It can provide good linearity for a sinusoid signal of very low
frequency with a high oversampling ratio, which loosens the requirements for the low

pass ﬁlter design.

Sub-sampling is also referred to as down-sampling. It is a signal sampling technique.
In contrast to Nyquist sampling techniques, the sub-sampling technique uses a sampling
frequency much lower than twice the signal frequency. The ﬁrst replicas of the sampling
output will be located near DC. As the replicas carry the same information as the sampled
fundamental signal, the ﬁrst replicas are used to store the information in a sub-sampling
technique. This is often used in communication systems to down convert the information
from an RF band to a low intermediate frequency band to facilitate further signal

processing [82, 93].

102

In this research, this technique is employed to produce a low frequency sinusoid
waveform through sampling a high ﬁequency sinusoid signal. The sequence of the

sampling result of a sinusoid input is given by
. f0
f(n) = Sln 21m f— (5.5)
s

wherefo is the signal frequency and f, is the sampling frequency. Assuming that f0 is very

close to f, then Af=f0-f,, and (5.5) can be expressed as

 

f(n) = sin[21tn f5 :Af] = sin(21m + 21mg]: sin[21m?—f] (5.6)

S S S

which shows that the sampled output is also a sinusoid but has frequency of Af. This sub-
sampling technique is graphically shown in Figure 5.9. A sinusoid input (solid line) is
sampled by a frequency very close to it and another sinusoid at output (dotted line) is
formed. The principle block diagram of this kind of signal generator is shown in Figure

5.10.

103

To have a constant sinusoid output from sub-sampling it is very critical to keep a
constant relationship between sampling frequency and input signal frequency. This is
easily achieved with the proposed structure. The sub-sampling signal generator is realized
by sampling the R-chain signal generator’s output with a clock derived from the same
main clock. For the R-chain based signal generator, the output frequency is exactly
controlled by and related to the main clock. The sampling frequency for the sub-sampling
signal generator is also generated from the main clock, and thus the frequency difference
between the sampling frequency and the output frequency of the R-chain signal generator
will be constant and can be tightly controlled. The output frequency range of the sub-
sampling signal generator and the corresponding frequency of the R-chain based signal

generator output are listed in

— input sine wave --------- output sine wave 0 sampling point

tlm

Figure 5.9. Concept of sub-sampling techniques.

 

 

 

SIN,f0 SIN
Clock, f1

 

 

Figure 5.10. The block diagram of a sub-sampling system.

104

5.2.6 Filter design for a sub-sampling signal generator
The over sampling ratio (OSR) for the S/H in a sub-sampling circuit is roughly

equal to the frequency ratio of the input signal and the output signal.

shows that the smallest OSR is about 100. Furthermore, the sampling frequency
does not change too much because it only varies by a small amount around the input

signal frequency. Therefore, it is not difﬁcult to design a ﬁlter to smooth the output.

A 2“d order Butterworth ﬁlter with a 250Hz cutoff frequency is employed to smooth
the output. With the minimum OSR of 100, the SF DR is about 37dB based on the plots in
Figure 5.8. This ﬁlter will provide replica suppression of at least 24dB for 0.1Hz to 10Hz
and at least 64dB for 10 Hz to lOOHz, which is enough to achieve a total SF DR of at least
50dB. For the output frequency of 1 mHz -0.1Hz, replicas exist within the pass band of
the ﬁlter. Thus, the ﬁlter does not provide any suppression for these replicas. However, in
this range the S/H itself already provides good SFDR of more than 50dB because the

OSR is over 1000.

TABLE 5.2. INPUT SINGAL FREQUENCY SETTINGS FOR DIFFERENT
RANGES OF OUTPUT FREQUENCIES

 

 

 

 

Output frequency Input signal frequency
range (M is the divider ratio for an R-chain DAC updating clock)
lmHz — 0.1Hz 99.968 Hz (M=1563)
0.1Hz — 10Hz 1001.6Hz (M=156)
10Hz — lOOHz 9765.5Hz (M=l6)

 

 

 

 

105

5.3 Circuit realization

5.3.1 The R-Chain DAC

The R-chain DAC is built with many resistors in series. 33 taps, including two ends
of the chain, are needed for an OSR of 64. As the chain is unevenly tapped, the values of
the resistors between any two consecutive taps could be different. For good linearity of
the DAC, proportional matching of these resistors is very important. As matching
between different sized resistors is worse than that between resistors of the same size, the
resistor chain is composed of 1000 resistors of the same size. The 33 tapping points are
mapped into points between 0 and 1000. Theoretically, the method can provide a linearity
of 10 bits (60dB), which meets the requirement of 50dB linearity. The circuit of the

resistor chain is shown in Figure 5.11.

At each tap, two switches are added for the sine and cosine signals. Instead of a
CMOS switch, only an NMOS transistor is used for the switch. This saves silicon area

and simpliﬁes the control logic design.

5.3.2 Low pass ﬁlter design
Both the RCDAC signal generator’s output and the sub-sampling signal generator’s

output need a ﬁlter to suppress the replicas and switching noise. These ﬁlter’s

 

OSIN

    

Figure 5.11. A circuit for an R-chain DAC for a signal generator.

106

characteristics and requirements have been discussed earlier in this chapter. In this

section, their circuit realization will be discussed.

5.3.2.1 Structure of the ﬁlter

A gm-C structure was adopted to design the ﬁlters. For a 2nd order Butterworth LPF,
its gm-C realization is shown in Figure 5.12. It is a gm-C structure that can be used to
synthesize different biquadratic LPFs [94]. By setting the gm and capacitors values, we
can realize the 2nd order Butterworth ﬁlter. The ratio of C1 to C2 is set to 2, so thatthe Q
is ﬁxed at 0.707, which provides maximum pass-band ﬂatness for the pass band. All the

parameters are summarized in TABLE 5.3 for the two kinds of ﬁlters used in the system.

Instead of using a metal-insulator-metal (MIM) capacitor, the NMOS gate
capacitance is used. Because the gm is also built with the NMOS transistors, the NMOS
gate capacitance will track the process variation of gm. Although this tracking can not
cancel out the process variation of the cut-off frequency very well, it narrows down the

process variation range.

For conﬁgurable ﬁlters, the gm values and the capacitance values have two level
settings. Combining them, ﬁlters with three different cutoff frequencies are provided.
Two sets of capacitor values are achieved by putting two individual capacitors in parallel
and using one of them to tune the capacitance value. For the transconductance, a circuit

structure is developed to provide two gm values.

107

With the ﬁxed ﬁlter, the gm and capacitance values are ﬁxed. Because the cutoff
frequency is very low, with a reasonable capacitor value (feasible within the silicon area),
the gm is inevitably small, as shown in TABLE 5.3. A new structure that provides a very

small gm was designed to meet this need.

5.3.2.2 OT A with two transconductance levels

The ﬁlter capacitor can not be too large such that it will not ﬁt within the on-chip
system. This indicates that the gm values need to be small. There are several ways to
design an OTA with a small gm. They are 1) OTA with current division [95] and source

degeneration [96], 2) ﬂoating gate OTA [97, 98] and 3) bulk driven OTA [99, 100]. The

 

 

 

 

 

 

 

¢ MOS CAP

TABLE 5.3. THE PARAMETERS FOR THE FILTER DESIGN.

Figure 5.12. Schematic of the gm-C biquadratic ﬁlter.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Conﬁgurable Filter Fixed Filter
Gm C1 C2 F c Q gm C1 C2 F c Q
60n 5p 2.5p 2k 0.707
600n 5p 2.5p 20k 0.707 9n 7.5p 3.7p 250 0.707
600n 0.5p 0.25p 200k 0.707

 

108

 

OTA with current division and source degeneration was adopted because it consumes less

power, is easier to control, and provides relatively good performance [101].

The schematic of the designed OTA is shown in Figure 5.13. It combines the
current division and source degeneration techniques. [101] also built an OTA by
combining these two techniques. In Figure 5.13, the combination is realized in a different
way. The current division is realized with the mirror structure (Mnl&Mn2, Mn3&Mn4).
The internal feedback loops involving the input pair will control the gate of the current
mirrors including Mn] and Mn3, respectively. Because the current of the input pairs is
ﬁxed, this structure will give better linearity performance. PMOS transistors in the triode
region working as MOS-resistors are used as the source degeneration resistor. The gm of

the OTA is

vdd

 

 

 

 

1
It...

 

 

 

 

 

 

Vin—i
:II—vbn

 

 

 

 

 

 

 

 

 

 

gnd
Figure 5.13. OTA with a small gm (two level tunable). The signal S selects the gm level.

109

gm = K— (5.7)

 

I W
gOI,2 = 2\/l-1COX 3%?) (5.8)
Mpl,2

where K is the ratio of the current division (controlled by S in the Figure 5.13 circuit) and
15 , as shown in Figure 5.13, is the bias current for the source degeneration MOS-resistor.
Thus we can tune the transconductance (gm) with the size of the MOS-R and its bias
currents. In order to keep. the circuit working properly, the overall current direction
within the MOS-R can not be changed. Thus the minimum of 13 should be larger than the
maximum AC current within a margin of tolerance, which improves the linearity of this

circuit.

5.3.2.3 OTA with small transconductance levels

For the ﬁlters used at the output of the sub-sampling signal generator, TABLE 5.3
shows the transconductance-is only 9nS. The same circuit topology in Figure 5.13 is used
for a small gm OTA too. The circuit for the OTA with a small transconductance is shown
in Figure 5.14. The current division switch is removed, and the division ratio is ﬁxed at
10. A smaller drain current and longer length of MOS-R in (5.8) are used to generate a

small go.

110

vdd

 

 

 

 

W

 

 

 

win—i

I 1:10

 

 

 

Mn1

 

 

 

 

 

 

v

gnd
Figure 5.14. OTA with a small gm.

5. 3. 2. 4 Filter characteristics

The transfer functions and the linearity of the ﬁlters were veriﬁed with simulation.
The transfer function and linearity performance of the variable frequency ﬁlter with a
cutoff frequency of 200kHz, 20kHz and 2kHz are shown in Figure 5.15, Figure 5.16, .and
Figure 5.17, respectively. The transfer ﬁmction and linearity performance of the ﬁxed
cutoff frequency (250Hz) ﬁlter are shown in Figure 5.18. These results show that the

ﬁlter meets the design requirements and can provide a dynamic range of more than 57dB.

111

Spectrum of Output Signal

 

 

 

Filter Charateristics 1
0.0
_m :_ SFDR:58dB
6 E A 500mV@100KHz
3-29 L m
o E 3
3 -33 ; o
g : 2nd order Butterworth 1;
3 -49 } Cutoff frequency: 200KHz 3;
a: : E
'5 -5e :- E
E E <
LL '60 E
-7o F
1 to we 1K 1 00K 1 1
Frequency ) Frequency x 16
(a) (b)

Figure 5.15. (a) transfer function and (b) the linearity of the variable ﬁlter with cut-off
frequency of 200KHz.

Spectrum of Output Signal
Filter Charateristics

 

 

 

. SFDR:57dB

A ‘1' '- ... 500mV OKl-lz
m in
3 -2e . 1:
0 ~—
"° 3
3' '4' 2nd order Butterworth g
51’ -5. _ Cutoftfrequency: 20KHz g
g 40- < o
“' -7I .

4'1 1o III 1K m can i tell 4

Frequency Frequency x 10
(a) (b)

Figure 5.16. (a) Transfer function and (b) linearity of the variable ﬁlter with a cut-off
frequency of 20KHz.

5.3.3 Sub-sampling quadrature sinusoid signal generators
The circuit of a sub-sampling signal generator is shown in Figure 5.19. A simple
capacitor track and hold (T/H) circuit is followed by a 2“d order Butterworth ﬁlter with a

cutoff frequency of 250 Hz.

CMOS transmission gates are used as the sampling switch. For the I and Q channels,

the middle switch is the real switch, and the two switches on each end are half size

112

Spectrum of Output Signal

SFDR:seee
500mV KHz

Filter Charateristics 1

 

   
 

2nd order Butterworth
-5. _ Cutoff frequency: 2KHz

   

Amplitude (dB)
to A a) m

0

Filter Response (d8)
e .I

 

4'1 II III 1K IIK III»: I IN -
Frequency Frequency x 16

(a) (b)

Figure 5.17. (a) Transfer function and (b) the linearity of the variable ﬁlter with a cut-off
frequency of 2KHz.

Spectrum of Output Signal

 

     
 

 

 

10
Filter Charateristics _
i SFDR.74dB

-Ie . a ’ 500mV@100Hz
63‘ u
E... r
3 ' '0
C a
o a
8'4. 2nd order Butterworth :
g Cutoff frequency: 250Hz 2'
2-70 . <
it

-9. . I”... - _-_ u __

1 10 1” 1K 10K 1.0K ill
Frequency Frequency x 16
(a) (b)

Figure 5.18. (a) Transfer ﬁinction and (b) the linearity of the variable ﬁlter with a cut-off
frequency of 250Hz.

dummy switches to compensate for the charge injection of the switch operation. This

cancellation is beneﬁcial for a moderate linearity level (50dB).

During the system analysis, the relationship between OSR and SF DR was based on
an ideal S/H circuit. This assumption is important for a sub-sampling signal generator. If

a normal 50% duty cycle T/H circuit is used for a sub-sampling signal generator instead

113

of an S/H circuit, a lot of the energy of the original signal will leak through to the output
in the tracking windows and deteriorate the low frequency output, as shown in Figure
5.21. Thus, a 50% duty cycle clock, providing a wide sampling window, results in
leakage energy around the updating frequency. This leakage will badly deteriorate the
SFDR. To overcome this problem with a simple T/H circuit, the duty cycle of the T/H
clock was changed so that it only tracks the input within a very narrow window, which
not only limits the original signal leakage power but also moves the leaked energy to
higher frequencies where a simple ﬁlter can effectively screen this leakage out. The
digital control block will generate the narrow width square pulse (low duty cycle square

wave) with a width of 0. l usec.

The leakage of the sampling capacitor could be a serious problem with a very low
frequency output because the sampling ﬁequency is only about lOOHz. In order to
suppress it, minimum sized NMOS transistors were used and the capacitor was set to 1pF.

Because the stored value only changes a small amount for two consecutive samplings, the

SlNin Ea“

_LCs V
grpF

I_r
1"
s
S _
jl—‘L @
COSin -
_L Cs Cl

 

 

 

 

 

 

 

Figure 5.19. Circuit of the sub-sampling quadrature sinusoid signal generator.

114

Original

 

 

Signal Leakage of
orignal signal
Sampled
Output
CHock

 

 

 

 

 

 

 

 

Figure 5.21. The original signal leaks out to the output through the tracking window.

minimum size NMOS transistors do not affect the sampling speed at all.
5.3.4 Digital control circuit

5.3.4.1 Clock divider

Two clock dividers are used in the circuit to provide a clock for the R-chain DAC
and sub-sampling circuit. The divider circuit is shown in Figure 5.20. An asynchronous
counter is used to reduce power consumption. The divider ratio is set by a memory
register value. To generate the clock for the R-chain DAC, the counter and register have
11 bits. For the subcsampling clock, the counter and register have 17 bits. The values of

registers and their corresponding output frequencies are summarized in TABLE 5.4.

 
 
    

 

 

 

 

 

 

 

‘ n-1
D 0— D Q
DFF --- DFF

-IkRnQ son: It

 

 

 

 

 

 

 

 

 

 

Q<12n>+‘ f
Digital Comparator

Figure 5.20. The clock divider circuit.

 

Clk

 

 

115

TABLE 5.4. THE CLOCK DIV IDER SETTINGS FOR DIFFERENT FREQUENCY
OUTPUTS.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Frequency Register M (11 Frequency output of Register N
Range Bits) DAC (17 bits)
100-78K Hz 71B’h~002’h 100-78K Hz N/A
10-100 Hz 10’B 9765.6 Hz 401 ’h - 40B’h
0.1-10 Hz 9C’h 1001.6Hz 2701’h—2765’h
lm-0.1 Hz 61B’h 99.968Hz l86Cl’h-l97lA’h
Q<1z63> 1 2 3 62 63 64
—-o c. o c o o- -O O ‘D o ‘D 0-
OFF DFF DFF - - - DFF DFF DFF

 

 

 

 

 

 

 

 

 

 

Clk rClk nQ— rCIK nQ—[Flk nQ— ECIK "Q r0", "Q If” no-

Q<1264>7‘-‘ Combination S°°5<1=33>
logic Ssin<1z33>

 

 

 

 

 

Figure 5.22. The token ring based switch network’s control signal generator.

5.3.4.2 Switch control for the R-chain DAC signal generator

A token ring is used to generate the correct switch controls for the tap switch
network of the sine and cosine outputs. As shown in Figure 5.22, there are 64 elements in
the ring corresponding to an OSR of 64. At any time, only one “1” is in the ring. An all
zero detector veriﬁes this single “1” rule and pulls the ring back from any other incorrect
states. Each switch in the R-chain DAC corresponds to two elements in the ring. A
combination logic block generates the switch control signals by providing a mapping
describing this relationship. As both the sine and cosine control signals are generated

from the same token ring, their phase relationship can be well-maintained.

5.3.5 System integration
Using the above designed fundamental building blocks, the overall integrated

quadrature sinusoid signal generator was implemented with the AMI 0.5um CMOS

116

 

Figure 5.23. The layout of the quadrature sinusoid signal generator. Its size is 1mm2.

process. The layout of this signal generator is plotted in Figure 5.23. Its silicon area is
1mm2. This circuit is very large compared with the size (0.06mm2) of the channel-wise
compact IS readout circuit developed in Chapter 4. However, we only need one signal
generator for the entire microsystem. Thus, this size is acceptable for an integrated

impedance spectroscopy microsystem.

5.4 Conclusion

A wide frequency range quadrature sinusoid signal generator was presented in this
chapter. With its hybrid structure, it can provide good phase and amplitude matching for
the quadrature sinusoid signal from lmHz and IOkHz. It inherently guarantees frequency
tuning accuracy because it is purely digitally controlled. The prototype of this design has
been fabricated with a 0.5um CMOS process. With a size of lmmz, it can serve as the
stimulus generator for an integrated IS microsystem. Testing results will be given in

Chapter 6.

117

6 Experimental Results

The a compact on-chip impedance spectroscopy circuit (Chapter 4) and wide
frequency range quadrature sinusoid signal generator circuit (Chapter 5) were developed
to demonstrate the feasibility of a multi-charmel impedance spectroscopy microsystem
and to explore the relevant analog/mixed signal IC design methodology for such a
system, Both circuits were fabricated with the AMI 0.5um CMOS technology using 3
3V power supply. This chapter presents the experimental test results of the fabricated
chips. In addition, test results for a prototype electrochemical biosensor system using the

designed circuits are presented to verify the application potential of this thesis research.

6.1 Measurement of the compact IS circuit
The die photo of the prototype IS lock-in ADC is shown in Figure 6.1 with the main

functional blocks labeled. The size of each lock-in ADC cell is lOOum by 600nm, and

two of these cells are on the prototype chip. Due to the compact size of this circuit, which

 

Figure 6.1. Die of two lock-in ADCs.

118

was a rigorously maintained design goal, more than 100 copies of this circuit can be
instantiated on a typical 3mm by 3mm silicon chip. This is sufﬁcient for both existing
and near future IS based biosensor array microsystems. The lock-in ADC cell consumes
2uA of current in the working mode. To measure the Circuit’s performance and verify its
functionality, two sets of experiments are performed to characterize the lock—in ADC, and

demonstrate its practical impedance information extraction capability.

6.1.1 Experiment setup

A data acquisition card (DAQ E2530A) from Agilent Technologies (Santa Clara,
CA, USA) was used to interface the lock—in ADC with a PC running software to
conﬁgure and control the chip. The setup is shown in Figure 6.2. The DAQ E2530A can
generate both analog and digital patterns and read analog or digital signals. It generates
the sinusoid voltage signals for a sensor model that mimics the function of the biosensors.
The current response of the sensor model due to the sinusoid stimulus is sent to the lock-
in ADC. The DAQ E2530A also generates all of the digital control signals for the lock-in
ADC. The digitized results from the chip are also read out serially by the DAQ E2530A

so they can be displaced and stored on the PC.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

sensor
,IIII IIIIII IIIIIIIII IIIIIIIIIII I IIIII I IIIIIII III-II. mOdel
l isinusoidWW
5 D Estimulus ‘
E 3 A édigital control
" "— Agilent ESerial data path
5 ° 53630A [S 5

I
I
IIIII IIIII II IIIII IIIIIIIIIIIIII IIIIIIIIIIIIIIIIII I.

.0

Figure 6.2. Experiment setup for the lock-in ADC.

119

Two sensor model circuits were designed to characterize the performance of the
lock-in ADC. To characterize the amplitude and phase transfer function of the lock-in
ADC, a pure capacitor is used for the sensor model. For a voltage sinusoid stimulus
strength of several hundreds of mV, which is large enough to surpass the noise effects of
the DAQ card, an off-the-shelf capacitor can generate a current response range from
several hundreds of nA to sub-pA. By setting the capacitor to different values and
sweeping the amplitude of the sinusoid voltage stimulus, the lock-in ADC can be tested
over a wide input current amplitude range. The phase relationship between the capacitor
response current and the voltage stimulus is ﬁxed at 90°. Thus we can sweep the phase
delay of the sinusoid voltage stimulus to sweep the phase of the response current. The
second sensor model circuit is the model for the tBLM biosensor [42], described in 6.1.3.

This circuit model is used to verify the impedance extraction capability and accuracy.

6.1.2 Characteristics of conversion
The lock-in ADC extracts the phase and amplitude information of an input sinusoid
current. The phase and amplitude transfer characteristics were studied individually in the

experiments.

120

Sinusoid current signals with constant amplitude were fed into the lock-in ADC.
Their phase with respect to the reference clock was then changed. The observed phase vs.
the normalized output is plotted in Figure 6.3. The results are normalized to the peak
value. Two sets of sinusoid signals were tested: one is 10Hz with an amplitude of 30nA
and the other is lkHz with an amplitude of l.4nA. The lock-in ADC was conﬁgured to
measure the imaginary coefﬁcient only. The real coefﬁcient can be found through

shiﬁing the curve in Figure 6.3 by 90 degrees. Theoretically, as shown in (4.2), with a

1.2
Normalized 1
Response 0 8

phase shift

-225 "’3-135-90 45 90 135 180 225
it measurement

theory curve
RMS error 0.027 ' '1

(a)

1.2
Normalized 1

response 08 ,2"

0.6 » y” s

0.4

0.2 ,2" "(phase shift
0 ’=-

-225 "ix-135 -90 '03-’70 45 90 135 180 225
9 measurement

.. theoretical curve
RMS error 0.012 ' '1

(b)

Figure 6.3. Phase vs. output with an input sinusoid of (a) 30nA amplitude @IKHz and (b)
l.4nA@10Hz.

121

constant amplitude and frequency, the relationship between the phase shift and the
imaginary coefﬁcient is a sine wave. Figure 6.3 also plots the theoretical prediction. We
can see that the measured results match the theoretical curve very well. The RMS error

for 30nA lKHz sine input is 0.027 and that for 1.4nA 10Hz sine input is 0.012.

To examine the amplitude transfer ﬁmction, a 100 Hz sinusoid signal with 0 initial
phase was supplied and its real portion coefﬁcient was extracted by the lock-in ADC. The
amplitude of the sinusoid signal was swept and the lock-in ADC output was observed.
The relationship between the input signal’s amplitude and the digital output (digitized
real portion) is linear for a constant phase and frequency. Thus, the ADC’s benchmarks,
integrated non-linearity (INL) and differential non-linearity (DNL) plots, are used to
show the lock-in ADC’s amplitude conversion accuracy. With the input amplitude
changing from 0 to 100nA, the 1024 points of INL and DNL are plotted in Figure 6.4.
The results show that the circuit can provide more than 50dB dynamic range for an input

range of 100nA.

122

O~1 0 A 10

 

 

Amplitude [nA]
(a)

0~100nA 10Hz
,4, m

 

 

‘90 I I I I I I
O 20 40 60 80 100
Amplitude [till]
0))

Figure 6.4. The lock-in ADC’s amplitude transfer performance with respect to 8-bit
digitization: (a) DNL, (b) INL.

The lock—in ADC can be conﬁgured to accommodate a wide range of input signal
strengths by changing the magnitude of the two reference currents and the updating clock.

Figure 6.5 plots the amplitude conversion characteristics of the lock-in ADC for the

123

105

 

 

 

 

 

 

 

 

 

 

 

 

f
100nA
104-
o
1:
o
O
3 103
E ‘A
1:
102 0.4nA
x
78fA
10
1f 1p 100p Ian 1}:

Amplitude of input sinusoid waveform (A)

Figure 6.5. Amplitude conversion characterization for the zero phase sinewave input. The
lock-in ADC is conﬁgured to accommodate a wide range of input signals.

largest signal range and the smallest signal range. Figure 6.5 shows that the achievable

sensitivity is better than 100fA.

6.1.3 Impedance information extraction

The experiment setup in Figure 6.6 was used to verify the function of the lock-in
ADC as an 18 system. A sensor model circuit and component values were chosen to
mimic a real IS-based biosensor[102]. A sinusoid voltage stimulus was applied and the
current response was analyzed by the lock-in ADC. The real and imaginary current
response was recovered from the digital output of the chip. The results are plotted in
Figure 6.7. The calculated impedance for a given set of component values in the sensor
circuit model in Figure 6.6 are also plotted for comparison. Plots in Figure 6.7 show that
the chip’s measured results follow the theoretical prediction very well. The maximum

absolute error observed is 0.6nA, and the RMS absolute error is 0.1nA. Compared with

124

biosensor model JUUUHHHHI 100KHZ
I

 

    

         

. 50m: 43an '0 clk
.VIn = IOCk'in ADC
(s|n(wt)) ; 3 reference

 

it... 40pF ,

 

sin(wt)

/cos(wt) _ﬂJ—l

Figure 6.6. Experiment setup for verifying impedance extraction.

 

 

 

2.55-03 ERROR “ﬁgs“,ﬁﬂs mes-cs
absolute 0.6nA 0.1-EA MAX f"
2508 relative to . , , > *~- .
‘_ 1.5E-08 .1"
5' 1:2:
§ 1E’08 ', a}: . v ‘4 x x I" / -"
S I. _ .
U 55-09 _
0.1 1 10 100
Frequency(Hz)
Tested Real Portion Tested Imaginary Portion
............. Calculated real portion .. - - - Calculated imaginary portion

Figure 6.7. The real and imagineary coefﬁcients of current response from the setup in
Figure 6.6. The test result and theoritical expectitations are given for comparision.

the maximum result of 23.5nA, the relative maximum error is 0.025 and the RMS error is

0.004.

6.1.4 Discussion

The above experiments prove that the lock-in ADC can extract and digitize the

impedance information with good accuracy. Its low power and compact size meet the

125

requirements of an IS-based biosensor array microsystem. The performance is

summarized in TABLE 6.1.

TABLE 6.1.

  

6.2 Measurements of the quadrature sinusoid signal generator

A die photo of the prototype quadrature sinusoid signal generator is shown in

Figure 6.8. The circuit occupies 1mm by 1mm. With a 3V supply, the entire circuit draws

 

 

 

 

Figure 6.8. Die photo of the quadrature sinusoid signal generator.
126

only 6011A of current during operation. Several experiments were performed to test the
quality of the output sinusoid in terms of the dynamic range and matching between the
in-phase and quadrature-phase outputs. As the ﬁlter’s performance is critical for the

signal quality, the ﬁlters used in the system were also characterized through experiments.

6.2.1 Experiment setup

Two sets of experiments were conducted to test the transfer function of the ﬁlters
and the output signal of the signal generator individually. A spectrum analyzer (E4395A)
from Agilent Technologies (Santa Clara, CA, USA) and a power supply were employed
to test the ﬁlters. This setup is shown in Figure 6.9. The spectrum analyzer was set to the
NB response testing mode. A small signal was generated at the RF out port and was then
fed back to the spectrum analyzer at port B as the input reference signal. It was also fed
to the input of the ﬁlters. The DC value of the RF output is always zero, and the ﬁlter

input’s DC bias is 1.1 volts. A capacitor and resistor were used, as in Figure 6.9, to set

 

 

A/B

 

SpectrumAnalyzer RF 0m 8 6‘
Agilent E4395A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10pF .
__l l_ Filters
| for the signal generator
1M!)
Power su I
pp y 1.1 Volt

 

 

Figure 6.9. Experiment setup for the ﬁlter testing.

127

the proper working point for RF out signal being input to the ﬁlter. The ﬁlter’s response
output was connected to the A port of the spectrum analyzer. The frequency sweep range

and the signal power were set through the spectrum analyzer.

To test the overall signal generator, a data acquisition card (DAQ E3630A) from
Agilent Technologies (Santa Clara, CA, USA) was employed, as shown in Figure 6.10.
The DAQ generates the digital control signals for the signal generator and receives the
sine and cosine output ﬁ'om the test chip at two of its analog input channels. The

spectrum analysis of these input signals was performed with a computer.

6.2.2 Analog ﬁlter characterization

Two kinds of ﬁlters are employed by this design. Both of them are 2nd order
Butterworth ﬁlters, and the same gm-C structure (Figure 5.12) was selected for both of
them. One has three optional cutoff frequencies; the other has a ﬁxed cutoff frequency.
Experiments were performed to check their AC transfer characteristics and large signal

linearity, both of which are important for good quality sinusoid output.

Figure 6.11 shows the measured transfer function of the ﬁlters. All curves are put

into one plot for easier comparison. Due to process variations, the cutoff frequencies are

.CCIIIIIIIIIIIII-IIIIIICC-III-IIIIIIIOIIIIIIIIIIIII.

- - Signal sin
m generator

9

 

 

 

 

 

 

 

 

 

 

 

    

 

 

 

 

 

 

, E3630A

  

 

A 5 control cos
6" gAnalog input
ﬂ Agilent §Analog input

9

.lIIIII.IIIIOIIIIIIIIIIIIIIIIIIIIIIOI IIIIIIIII III-I.

Figure 6.10. Experiment setup for the signal generator testing.

128

 

20 I
tunable filter 121 kHz

 

 

 

 

ﬁxed ﬁlter (-

 

galn(dB)
XI ' x
/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-80
1 2 3 4 5 6
log(frequency)
Figure 6.11. Measured frequency response of the ﬁlters on the signal generator chip.
0-
e: '2“ e
E 40- 70dB E
g 450' E
(O (I)
E -80. ........ g
1L TM a.
-100-
-120- .120
IIIIIIIIIIIIIIIIIIIrﬁIﬁ—I IIIIIllll'IIll'Illl.IlIl|
0 100 200 300 400 500 O 100 200 300 400 500
Frequency (Hz) Frequency (Hz)
(a) (b)

Figure 6.12. Output spectrum for a 100Hz sine input with a 450mV amplitude for (a) a
tunable ﬁlter and (b) a ﬁxed ﬁlter.

shiﬁed for some of the curves, compared with the simulation results in Chapter 5.
However, since the designed 2"d Butterworth ﬁlter can provide more than enough

suppression of the harmonics, this process variation does not interfere with performance.

Figure 6.12 shows the linearity plot for each ﬁlter. Only one plot is given for the
tunable ﬁlter because the main nonlinearity contributors, Mp1 and Mp2 in Figure 5.13,
are the same for all three cutoff frequencies. Both ﬁlters can provide more than 50dB of
linearity with an input strength of 450mV, which is enough for the 48dB output linearity

of the signal generator.

129

6.2.3 Quadrature sinusoid output

Several output frequency points were generated ranging from lmHz to lOkHz. The
waveforms of two extreme output frequencies are plotted in Figure 6.13. Figure 6.14
shows the observed phase mismatch, which is the variation from the expected 90 degree
phase between the sine and cosine outputs. Figure 6.15 shows the amplitude mismatch
between sine and cosine output. The spurious free dynamic range (SFDR) of the output

(450mV amplitude) is plotted in Figure 6.16. The linearity in Figure 6.16 represents the

 

 

 

 

g 1.
1.
2' sine
0 1
1: - .
:3 ........ cosme
‘5.
E o.
0' I T I I j T T I I I I
0 200400600800 1k 1.2k1.4k1.6k1.8k 2k
Time (Second)
(a)
2—
1.8-
1.6-
sine

........ cosine

    

08 \‘O ‘-O

0 50u 1dOu 15'0u 20'0u
Time (Second)

0))

Figure 6.13. Waveform of quadrature sinusoid output at two extreme frequencies, (a)
lmHz and (b) lOKHz.

 

130

signal strength difference between the desired frequency and the largest secondary spike

in the output signal spectrum.

phase mismatch (°)

 

 

-3 -2 —l 0 1 2 3 4

 

 

 

Log frequency (Hz)

Figure 6.14. The phase mismatch between the output quadature signals.

A 4.0 -

°>°« 3 o

g 3.0 0'\2‘.5 2 5

as v t

E: 2.0 «

E

8 1.0 .

.é’

'5 0.0 r .

§ -3 -2 -1

 

Log frequency (Hz)

Figure 6.15. The amplitude mismatch between the output quadature signals.

     

 

0.6

0.6 0.6
0.5

   

0.5

 

-2 -l 0 l 2 3 4
Log frequency (Hz)

Figure 6.16. Spurious free dynamic range (SFDR) of the output (450mV amplitude).

131

6.2.4 Discussion

The results show that the signal generator developed for this dissertation can
provide a quadrature sinusoid output over the expected frequency range with good phase
(< 1°) and amplitude matching (< 3%) between sine and cosine output. Figure 6.13(a)
shows a DC offset difference between sine and cosine outputs for a lmHz output. This is
due to the offset of the ﬁlters. It is constant for all the frequency points generated with the
sub-sampling circuit (lmHz ~ lOOHz), so it is easy to be corrected through calibration.
The frequency accuracy is guaranteed inherently due to the digital clock control. The

measured linearity is above 44dB. Overall, its performance is summarized in TABLE 6.2.

6.3 Biosensor measurement

6.3.1 Experimental setup

To test the designed IS circuit under real conditions, a prototype electrochemical
biosensor system was developed utilizing a miniaturized biosensor fabricated on a glass
chip. The test setup for this prototype system is shown in Figure 6.17. The DAQ was
employed to generate the stimulus and control signal and to read the lock-in ADC’s
output. Eight miniaturized gold electrodes were patterned on the glass chip, and then
biosensor interfaces (described below) were self assembled onto the electrode. The bulk

metal around the round electrode serves as the counter electrode, where the 5mV sinusoid

TABLE 6.2. THE PERFORMANCE SUMMARY OF THE QSSG

T 0.5um CM 3volts
Die area 1mm
Power ' 60uA
F 1m Hz ~ 10K Hz

Phase ' ' <0.8°
. . . (3%
>44dB

 

132

stimulus signal is applied. The lock-in ADC extracts the response from one electrode on

the array at a time.

With the assistance of collaborators from Chemical Engineering, tBLM sensor
interfaces were fabricated onto the gold electrodes. Brieﬂy, a self assembled monolayer
(SAM) of 1,2-dipalrnitoyl-sn-glycero-phosphothioethanol (DPPTE) tether lipid was
formed on a clean gold electrode by placing the array in a lmM ethanolic solution of
DPPTE for 24 hrs. A tethering lipid DPPTE has a terminal thiol group that forms a
covalent bond with a gold surface and creates an organized SAM. The SAM modiﬁed
gold was washed in ethanol to remove unabsorbed lipid molecules and dried under
nitrogen. The upper leaﬂet of the bilayer was deposited by ﬁrsion of vesicles made of 1,2-
dioleoyl-sn-glycero-phosphocholine (DOPC) mobile lipids. Excess liposomes were

replaced with ﬁesh electrolyte solution after the tethered bilayer lipid membrane (tBLM)

Serial data path

 

 

 

+ digital control

ﬂ

 

 

 

 

 

  

 

 

 
 

Agilent
E3630A "'7

 

 

 

  

 

 

    

sinusoid
stimulus

 

 

  

 

 

 

Figure 6.17. The experiment setup for the real biosensor impedance extraction.
133

formation. Impedance measurements were conducted in a 100mM sodium chloride

solution over the frequency range of 10 mHz to 100 Hz.

6.3.2 Experimental results

Prior experiments have shown that it is useful to monitor the quality of the
biosensor interface during its formation on the electrode. Thus, this procedure was chosen
as the subject of experiments to characterize the lock-in ADC. Figure 6.18 shows the
impedance changes of the tBLM after the upper leaﬂet of the bilayer was deposited by
the fusion of vesicles (DOPC). 0 hours result means the base impedance of the SAM.
These plots show that the impedance increases over time as the upper layer forms, as
expected. The impedance data were ﬁtted to the modiﬁed Randles’s equivalent circuit
shown in Figure 3.1(b) using Z-view software (Scribner Associates, Inc., Southern Pines,
NC). The equivalent circuit is a combination of a resistor and capacitors that can be
related to the physical characteristics of the biointerface. The membrane capacitance (Cm)
and the membrane resistance (Rm) are modeled in a parallel arrangement as they
represent the properties of the bilayer membrane. For a DPPTE monolayer, the Cm and
RH, values were found to be 0.635 uF/cm2 and 20 Kﬂcmz, respectively. For the tBLM, Cm
and Rm values of 0.505 [IF/cm2 and 425 Kﬂcm2 were observed. The capacitance value
for the tBLM is in good agreement with the reported values for high quality BLMs on an
interface[60]. However, a slightly lower value was obtained for membrane resistance
suggesting there may have been some pinhole defects in tBLM. One possible reason is
that the defects were mainly at the edges of the electrode where SAM formation was not
perfect. The molecules at the edges have a smaller number of molecules surrounding

them, resulting in less hydrophobic interactions and disordered arrangement of lipids.

134

Even so, we were able to obtain the electrochemical parameters of a tBLM in the

frequency range under study.

 

1 ‘ -o-Ohr
' +2hrs
+4hrs
—a—6hrs
. -a-8hrs
. .244- +10 hrs
‘ é . ﬁ-12hrs
1 : y —-—14hrs
‘ 1 ; --16hrs
“ ‘ +24hrs

 

Log(impedance) (0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

‘2 -1 0 1 2
Log(frequency) (Hz)

 

 

 

+0hr

+2 hrs
+4 hrs
-a—6 hrs
-a-8hrs
‘ +10hrs
-ﬁ-12 hrs
—-—14 hrs
--16hrs
+24hrs

 

 

phase

 

 

 

 

 

0 1
Log(frequency) (Hz)

(b)
Figure 6.18. Impedance of monolayer and tBLM: (a) magnitude, (b) phase.

135

After the tBLM measurements, a 1 11M concentration of gramicidin ion channel
protein was introduced to the electrolyte solution. Gramicidin exists as a dimer that is
known to incorporate itself almost spontaneously in a pre-formed tBLM. The monomers
get partitioned in lower as well as upper leaﬂets of the tBLM and are able to move freely
within each monolayer. The ﬂuid nature of the tBLM allows for the free movement of
these gramicidin monomers within the sensor. The alignment of these monomers creates
a channel that allows the passage of ions through the tBLM. Gramicidin ion channels

selectively transport alkali metal ions through the cell membrane.

The impedance of monolayer (DPPTE), pure tBLM and gramicidin modiﬁed tBLM
are plotted in Figure 6.19 for comparison. Incorporation of gramicidin in the tBLM
decreased the membrane resistance from 425 to 59 kﬂcm2 due to the passage of sodium
ions through tBLM. These results show that the gramicidin ion channels respond to alkali

metal ions in the solution through a signiﬁcant change of membrane impedance.

136

—-—Gramicidin modified}

    

. tBLM
‘3‘ 7 é—O—DPPTE
o .
3 6
II
'°
a
.§ 9
D) 5";
o
-‘
4 . . , .
-2 -1 0 1 2
Log frequency (Hz)
(a)

9°:

 

-2 -1 0 1 2
Log frequency (Hz)

(b)

Figure 6.19. Impedance of monolayer, tBLM and gramicidin modiﬁed tBLM, (a)
magnitude, (b) phase.

6.3.3 Discussion
The measurement of gramicidin activity demonstrates that the circuit developed in

this dissertation can be similarly used to measure the activity of different proteins based

137

biomimetic interfaces using a platform that is small enough to support a large array of
such sensors with (or on top of) a single microelectronic chip. Using an array of compact
lock-in ADC cells, multiple measurements can be done at the same time, allowing for

simultaneous address and monitoring of molecular events by each electrode on the chip.

6.4 Conclusion

The feasibility of the VLSI realization of the compact quadrature sinusoid signal
generator and compact impedance extractor and digitizer is critical for the success of
multi-channel EIS biosensor array microsystem. In this chapter, the silicon realization of
these two critical blocks was characterized and veriﬁed with a series of experiments. The
quadrature signal generator can produce quadrature sinusoid waveforms with good IQ
matching over seven orders of frequency range (lmHz to lOkHz). The lock-in ADC can
extract the impedance information with a sensitivity of up to 0.1pA of amplitude and has
successﬁrlly extracted and digitized the impedance information for the gramicidin
modiﬁed tBLM biosensor. These results show that the designed signal generator and
impedance extracting/digitizing circuit function as they were designed to and can support
impedance extraction in the biosensor microsystems. The circuits developed in this thesis

research enable a chip-scale realization of an EIS sensor array microsystem.

138

7 Summary and Future Work

7.1 Summary of the contributions

Microsystems that integrate a miniaturized biosensor array atop a silicon chip and
interrogate each sensor element electrochemically using integrated electronics within the
chip have a tremendous advantage over existing alternatives. This dissertation developed
the electrical systems and circuits for an impedance spectroscopy-based biosensor array
microsystem to address the special issues related to a large scale miniaturized biosensor
array. Two system level approaches for the electronics of the microsystem were
developed. For one of these systems, prototype ﬁrnctional blocks were developed and
fabricated, and veriﬁed. The results of this research provide a solid basis for future

research on all aspects of biosensor microsystems.

7.1.1 Proposed two architectures for the IS biosensor microsystem

Two new options for the interface electronics of a biosensor array based impedance
spectroscopy microsystem have been designed. Both of them are based on a frequency
response analyzer (F RA), which enables the compact IC realization of a full IS system.
One signiﬁcantly decreases the interrogation time at low frequencies (sub-hertz or lower)
through eliminating the integrators used in a conventional F RA based structure and
performing its function with complex signal processing in the analog domain. The other
one features high accuracy and compact size so that it can provide multi-channel in-
parallel interrogation for every sensor element. The VLSI realization of the key
functional blocks for the second one was also developed in this dissertation because it

provides higher accuracy and can support a wider range of sensor types.

139

7.1.2 The smallest known impedance extractor and digitizer circuit

In this dissertation, a novel compact IS readout circuit was developed and fabricated
with the AMI 0.5um CMOS technology. Its physical size is only 0.06mm2. A 3mm by
3mm silicon die it can integrate more than 100 of these IS circuits, which is enough for
anticipated microsystem needs. This lock-in ADC circuit not only extracts the impedance
information of the biosensors but also digitizes this information locally so that the results
for the whole array can be read with a serial interface to conserve pad resources.
Incorporating several innovative circuit blocks and methodologies, the new lock-in ADC
provides all of the features of a traditional IS measurement system within an ultra
compact integrated circuit that is many orders of magnitude smaller than all reported

alternatives.

7.1.3 The widest frequency range quadrature sinusoid signal generator

An on—chip stimulus sinusoid generator is a necessary component for a stand-alone
1S microsystem. Many biosensors are measured with low frequency stimulus, i.e. from
lmHz to lOkHz. At the integrated circuit level, there are no known options to cover this
wide frequency range of seven orders of magnitude. Thus, a novel hybrid signal
generator structure was developed and silicon-veriﬁed with the AMI 0.5um CMOS
technology. It generates a quadrature sinusoid signal (both sine and cosine signals)
covering the above mentioned frequency range with inherently guaranteed matching
between the signals. The performance of the new signal generator is outstanding for
many sensor applications and the very small size (~lmm2) makes it ideally suited for use

in integrated microsystems.

7.2 Future work

140

Based on the results of this dissertation, the following suggestions for future

research are made.

7.2.1 Fully integrated IS microsystem

The channel-wise compact IS circuit and the compact wide frequency range
quadrature sinusoid signal generator represent two hardware hurdles for the fully
integrated multi-channel IS microsystem. These hurdles have been overcome during this
dissertation, in which those two blocks have been designed and their performances have
been veriﬁed with real chip experiments. The results validate the concept of the
integrated IS microsystem proposed in Chapter 3. Thus, the next step is to develop the

fully integrated electronic system for this IS microsystem.

A conceptual system diagram for a fully integrated IS microsystem is proposed in
Figure 7.1. This system employs one quadrature sinusoid signal generator that generates
the stimulus for all of the biosensor elements in the array. For each biosensor element,
one dedicated compact IS readout circuit is used to extract and digitize the impedance
information. To provide a more generic interface, a three electrode system is adopted for
each biosensor. A half-ampliﬁer is used to support the three electrode system for each
biosensor. All the half-ampliﬁers within the same column share a common second half
ampliﬁer. This half-ampliﬁer concept was developed for an infrared imaging system[103,
104] and a potentiostat circuit[105]. This half-ampliﬁer can save hardware area. Different
elements in the array may have different DC bias settings. This can be achieved by
setting the WE potential individually through conﬁguring the DC point of the lock-in

ADC’s input. A block that sets every element’s WE potential according to the input

141

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142

7.2.2 Extension to cyclic voltammetry measurement

In cyclic voltammeter measurement, a triangle wave with a certain pattern is
applied as the stimulus to a potentiostat and the current response of the sensor system is
measured. The proposed system is easily reconﬁgured for cyclic voltammetry
applications, and the proposed integrator can be easily reconﬁgured as the current mode
continuous time (CT) Sigma-Delta ADC. A triangle waveform generator might also be

required to generate the stimulus for cyclic voltammetry interrogation

143

Appendix. Response of the tBLM biosensor to

frequency change

Let the frequency change happens at t=0+. We can express the source as:

V(t) = sin(coOt)-sin((r)0t)-u(t)+sin((1)]t)-u(t) (A.1)

where u(t) is the step function. The ﬁrst term in (4.1) is ignored because it represents a

stable periodic signal and is easy to be added back in a linear system, like the tBLM
circuit model. We will add its response later in the result directly. To facilitate this
derivation, the analysis is performed in S domain, where only the signals after time 0+

are studied. By ignoring the ﬁrst term, (A. 1) become (A.2),

V10) =-Sin(03()t)'u(t)+3in(wrt)'u(t) (A. 2)

Its Laplace transformation is

 

030 (”I
V (s) = + A.3
1 32 +0002 s2 +n)]2 ( )

The transfer function of equivalent circuit in F igure.3.1 is

 

Z(s) _ 1 l

— + A.4
gm+s-Cl s-Cz ( )

So the current response of the circuit is

144

_ we + mi
=X_Vl(s)_ 52+(002 s2+co,2

 

 

 

Is — —
0 2 2(3) ___1__+ 1
gm+S'C1 S'C2
= mi .(gm+S'C1)'S'C2_ (00 (gm+S'C1)-s-C2 (A.5)
s2+0112 gm+S'(C1+C2) 32+o)02 gm+5'(Cr+C2)
A1+A2+A3+A4+ A5

 

 

—S+.iwr s-jwi s+iwo s-iwo gm+s-(C1+C2)

where,.4(l = (s—jw1)-I(s)| , A2 = (s +jwi)-1(S)|

s=jw1 s=—j0)]

A3=(S—jmo)'1(8)l A4=(S+j(°0)'l(5)|

s=jm0’ s=—jm0

A5 = (g... +s - (C1 + C2» 1(s)|,=_ gm
C1+C2

( \

2
_ ('00 _ (”1 gm 'CZ
(h'FCb

2 2
gut ) 4_ 2 [ gut :] 2
-—-- we —-— +04
\[CI+C2 C1+C2 )

(5) can also be expressed as:

 

 

(A1+A2)+(A2 -Ar)jwr +<43+A4)+(A4 -A3)on , A5 (A6)

I(S)=
s2+rol2 sz+c03 gm+S'(C1+C2)

 

 

Transforming (6) into time domain, we get,

_ 8m
1(1) = ——A5 e CI+Cz
(C1+ C 2)
+(A3 '1' A4 ) COS((.00I) '1' (A4 - A3 ) sin(o)0t) (A7)
+(A1+ A2)cos(0)1t) + (A2— A1)sin(o)]t)

 

145

ln (7), ﬁrst term present the transition effect; the terms in second line present the stable

response for —Sin(0)0t); and 3rd line terms present the stable response for sin((olt).

(7) shows the time domain response for (2), now we can easily derive the time
domain response for (1). As the ﬁrst term in (1) present a stable stimulus, the response to
it should also be stable. Also the stable response to the second term in (1) should cancel
that of the ﬁrst term in (l), as the ﬁrst two term will cancel each other after t=0+. At

stable response of (1), we should not see any response to sin(u)0t). Assuming that a

frequency change happens at t=0, the response of the (l) is

 

_ gm
I(t)= A5 e C1+C2 +(A1+A2)cos(w1t)+(AZ—A1)sin(m1t)
(C1+C2)
1 (A.8)
A5 — Rm(Ci¥C2)t -
= e +(A +A )cos(o) t)+(A —A )sm((o t)
(C1+C2) 1 2 1 2 1 1
(A.8) can be represented as
___L_t
1()=——AS——e Rm<C1+C2> +A-sin((olt+(p) (A.9)
(C1+C2)

where second term represents the sensor’s stable response, and ﬁrst term will die out

eventually.

146

[1]
[2]

[3]
[4]

[5]

[61

[7]

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[9]

[10]

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