. .2 t . .4“ 1.4....” '9! mW... ‘ ,fimm n a . N um: 31 Q p k ‘ a . “Ff; m55......wqfi 33m tn I!!!" x l ‘D V www‘uufi . . vdunu mu ‘11! 53.03. _.J>.._,Q«tonu , .. . fig. ._ .mé . : 4 .. .03 41":73M s . u. .u { figfigfig . fiamgflgmnasgg mam LIBRARY a L Michigan State Abel _ Hniversity This is to certify that the dissertation entitled DESIGN OF HIGH-DIMENSIONAL OVERSAMPLING DATA CONVERTERS WITH ON-CHIP LEARNING: THEORY, ALGORITHM AND HARDWARE REALIZATION presented by AMIT SATISH GORE has been accepted towards fulfillment of the requirements for the Ph.D. degree in ELECTRICAL ENGINEERING [ Dr. Slamm) Major Professor’s Signature 1 13/0 21/ 2008 Date MSU is an Affirmative Action/Equal Opportunity Employer PLACE IN RETURN BOX to remove this checkout from your record. TO AVOID FINES return on or before date due. MAY BE RECALLED with earlier due date if requested. DATE DUE DATE DUE DATE DUE M. a: a 2mm 5/08 K:lProlecc&PrelelRC/DateDue.indd DESIGN OF HIGH-DIMENSIONAL OVERSAMPLIN G DATA CONVERTERS WITH ON -CHIP LEARNING: THEORY, ALGORITHM AND HARDWARE REALIZATION By Amit Satish Gore A DISSERTATION Submitted to Michigan State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Electrical Engineering 2008 ABSTRACT DESIGN OF HIGH-DIMENSIONAL OVERSAMPLING DATA CONVERTERS WII'H ON-CHIP LEARNING: THEORY, ALGORITHM AND HARDWARE REALIZATION By Amit Satish Gore Advances in miniaturization have enabled the integration of high density recording and recognition elements within a single device with applications ranging from biomedical engineering to surveillance sensors. One of the challenges of high density sensing is the acquisition of high dimensional analog signals within a given power budget at a specified resolution. The underlying success of high dimensional sensing depends upon the tracking of low dimensional information manifolds embedded in a high dimensional signal space. The objective of this work is to develop theory, algorithm and hardware for an adaptive high—dimensional mixed signal analog to digital interface that can learn to determine the salient information embedded in a high dimensional analog signal space. This dissertation presents a framework for constructing a high dimensional oversam- pling 2A (Sigma-Delta) learning algorithm and hardware that can identify and track the low—dimensional manifolds embedded in a high-dimensional analog signal space. At the core of the proposed approach is a min-max stochastic optimization of a regularized cost function that combines the machine learning principle with EA modulation. As a result, the algorithm not only produces a quantized sequence of transformed analog signals but also a quantized representation of transform itself. Thus, this algorithm naturally yields a high dimensional Spatiotemporal EA Learner (Abbrev: STL) system. This STL framework is generic and can be extended to higher-order modulators with different signal transformations. In this work, learning is demonstrated to identify the linear compression manifolds which can eliminate redundant analog-to-digital conversion (ADC) paths. This improves the energy efficiency of the proposed architecture compared to a conventional multi-channel data acquisition system. One of the salient features of this architecture is its self-calibration property in the presence of computational artifacts of mismatch, offset and nonlinearity. The proposed STL system is realized on chip as a proof of concept. The system is mapped to a mixed signal design that consists of an analog matrix vector multiplier de- signed with dynamic biasing technique for manifold learning and digitized interface for spatiotemporal data conversion and manifold storage. Measured results from the four- dimensional STL system fabricated in a 0.5 pm CMOS process demonstrate the real-time adaptation and self-calibration capabilities that are consistent with theoretical and simula- tion results. This adaptation and self-calibrating capability of STL system make it suitable for implementing practical high-dimensional analog-to-digital converter. The SA learning of designed prototype has been successfully applied for source localization and bearing an- gle estimation using miniaturized microphone arrays. The proposed architecture is generic and can be applied to wide range of applications which include brain machine interfaces (BMI), ”smart” hearing aids, high-density MEMS sensors, electro-chemical, bio-molecular sensor arrays and miniaturized RF antenna arrays. ACKNOWLEDGNIENTS I would like to take this opportunity to express my deepest gratitude to Dr. Shantanu Chakrabartty for his advice during my graduate studies. As an academic advisor, he was always approachable and ready to help in every possible way to make sure I was always at ease while working on my research. He always made me feel his friend while maintaining the professional distance required for my graduate studies. My special thanks to him for his help in some of my difficult times. I wish him well for all his future endeavors and would be happy to work with him in future. I would like to thank Dr. Michael Shanblatt, Dr. Andrew Mason and Dr. Evangelyn Alocilja for being on my PhD dissertation committee and guiding me through their vari- ous feedbacks, suggestions and queries. I really enjoyed my opportunities to work with all of them through one or more collaborated projects. I would like to thank my lab mates Paul Kucher, Arnin Fazel and Yang Liu with whom I shared my research as well as per- sonal space and I had a great time with them during my graduate studies. I would like to thank Brian Wright and Roxanne Peacock who helped me with their prompt services of lab equipments and inventory required for my research work. My special thanks go to my wife Prajaktaa for her un-wavered support throughout my graduate studies and her calming influence. I owe my deepest regards and gratitude to my parents (Satish Gore and Smita Gore) and brother Anamay Gore for their well wishes and sacrifices in every possible way to get me going through my academic years. I would like to dedicate my dissertation to my parents, grandparents and my wife for keeping faith in me all these years of graduate school. iv TABLE OF CONTENTS LIST OF TABLES .................................. viii LIST OF FIGURES .................................. ix 1 Introduction .................................... l 1.1 Milestones of Oversampling EA Converters ................. 1 1.2 Motivation for Spatiotemporal EA Learner (S TL) System ......... 5 1.3 Spatiotemporal 2A Learner (STL) System ................. 10 1.4 Applications of Spatiotemporal 2A Learner (STL) System ......... 13 1.4.1 Micro-electrode Sensor Arrays in Neural Prosthetic Devices . . . . 13 1.4.2 Acoustic Sensor Arrays for Source Localization ........... 15 1.5 Scientific Contributions ........................... 16 1.6 Dissertation Organization .......................... 17 I Theory and Algorithm 19 2 Regularization Framework for Designing 23A Converters ........... 20 2.1 Fundamentals of Over-sampling Data Converters .............. 20 2.2 Theory of 23A Converters ........................... 25 2.2.1 First Order 53A Converter ...................... 25 2.2.2 Second Order EA Converter ..................... 28 2.3 Regularization ................................. 31 2.3.1 Introduction to the Regularization .................. 31 2.3.2 Regularization Theory of Multi-channel 23A Converters ...... 32 3 Hysteretic 23A Converter ............................. 36 3.1 Motivation for the Hysteretic EA Converter ................. 36 3.2 Mathematical Modeling of Hysteretic 2A Converter ............ 38 4 The Spatiotemporal 2A Learner (STL) Algorithm .............. 42 4.1 Regularization Theory of Spatiotemporal Learner (STL) System ...... 43 4.2 Online Adaptation and Compression ..................... 45 4.3 First Order Spatiotemporal 2A Learner (STL) system ........... 48 4.4 Second order Spatiotemporal EA Learner (STL) system .......... 52 4.5 Hysteretic Spatiotemporal 2A Learner (STL) system ............ 55 4.6 Higher-order Spatiotemporal 2A Learner System .............. 59 5 Simulation and Verification Results of the Spatiotemporal 2A Learner (STL) Algorithm ..................................... 62 5.1 Behavioral Simulations of the STL System ................. 63 5.2 Parametric Performance of the STL System ................. 67 5.2.1 Over-sampling Ratio (OS R) of the EA Converter ......... 69 5.2.2 Resolution of the Signal Transformation Matrix A ......... 70 5.2.3 Component Mismatch and Offset .................. 71 5.2.4 Integrator Leakage of the EA Converter ............... 72 5.2.5 Component Non-linearity of the STL System ............ 74 5.2.6 STL System Dimensionality M and the Signal Statistics ...... 76 5.2.7 Order of the 2A Converter ...................... 77 5.3 Neural Signal Processing with the STL Algorithm ............. 81 II Hardware Realization 84 6 Hardware Circuit Design ............................. 85 6.1 Hardware Realization of the STL System .................. 85 6.2 4-Dimensional STL System ......................... 88 6.3 Circuit Design ................................. 89 6.3.1 Linear Transformation Module .................... 90 6.3.2 Up—Down Counter/Shifter ...................... 91 6.3.3 Transconductor ............................ 92 6.3.4 Current DAC ............................. 93 6.3.5 First Order 2A Converter ...................... 95 6.3.6 Third Order EA Converter ...................... 97 6.4 ST L System: Circuit Simulation Results ................... 101 6.5 STL System: Power Estimation ....................... 103 7 Hardware Results ................................. 106 7.] Hardware Design Test Setup ......................... 106 7.2 Characterization of the Hysteretic First Order 2A Converter ........ 108 7.3 Characterization of 2 x 4 Channel 3"d Order Spatiotemporal EA Learner (STL) System ................................. 114 7.3.1 Characterization of System Components ............... 114 7.3.2 System Adaptation .......................... 118 7.3.3 Signal Decorrelation ......................... 126 7.3.4 Signal Reconstruction ........................ 127 8 STL System Application: Acoustic Source Localization ............ 129 8.1 Far Field Acoustic Modeling ......................... 131 8.2 Measurement Results ............................. I36 vi 8.2.1 Bearing Angle Estimation of Miniaturized Microphone Array . . . 136 8.2.2 Bearing Angle Estimation of Miniaturized Microphone Array with Common Mode Suppression ..................... 137 9 Concluding Remarks and Future Directions .................. 143 9.1 Summery and Concluding Remarks ..................... 143 9.2 Future Directions ............................... 144 9.2.1 Freedom of Hardware Realization .................. 144 9.2.2 Power Optimization and Resolution Enhancement ......... 145 APPENDICES ..................................... 147 A Derivation of Mathematical Models of the STL Systems ........... 147 Al Optimization Framework of the STL System ................ 147 A2 Mathematical Modeling of the First Order STL System ........... 150 A3 Mathematical Modeling of the Second Order STL System ......... 155 A.4 Mathematical Modeling of the Hysteretic STL System ........... 160 B Noise Analysis ................................... 166 3.1 Noise Contribution of the Transconductor Network ............. 166 B.2 Noise Contribution of the Current References ................ 167 B3 Noise contribution of the Integrator of the First Stage of the EA Modulator 168 BIBLIOGRAPHY ................................... 172 vii 6.1 6.2 7.1 7.2 7.3 7.4 7.5 LIST OF TABLES The loop parameters of the third order single loop single bit EA modulator 98 Capacitor sizes used for the 2A modulators ................. 100 Measured specifications of the multichannel hysteretic 2A converter array 112 Comparison of the hysteretic 2A converter with other Potentiostats and ADCs ..................................... 112 Measured power dissipation of the STL system components ........ 113 Measured channel power of the 4-dimensional STL system ......... 114 Measured specifications of the 4-dimensional STL system ......... 118 viii 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 2.1 2.2 2.3 2.4 Discrete time model of the first order 2A converter ............. LIST OF FIGURES Milestones of EA converters ......................... The SA converters are driven by the bit rate and the power consumption specified by their applications. ........................ Sensor miniaturization has enabled the high density sensing where the di- mensionality of the system plays equally important role along with the bit rate and the power consumption. ....................... The high density sensing applications are inseparably constrained by the dimensionality, bit rate and the power dissipation ............... The electrical activity of neuronal population of the cerebral cortex [18] (2006) obtained by 1024 micro—electrode array. ............... The change in spatial position of the speaker is slow compared to its speech signals ..................................... Operational principle of the STL system is to track the slowly varying spatial information from the correlated high density signals ......... The conceptual diagram of the S TL system ................. The architecture of the spatiotemporal 2A learner (STL) system ..... Functional architecture of the cortically implanted neural prosthesis illus- trating the interface of the data converter with micro-electrode arrays and signal processing module ........................... Acoustic source localization used in the surveillance system ........ (a) Model of the quantization as an additive noise (b) Quantization error distribution under white noise approximation (c) 2-bit Quantizer ...... Block diagram of the feedback modulator used in an oversampling data converter ................................... Noise shaping of the EA converter: Attenuation of the quantization noise in the signal band increases with increase in the order of the EA converter 2 3 4 5 6 7 7 8 13 21 25 25 2.5 2.6 2.7 2.8 2.9 3.1 3.2 3.3 3.4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Z - model of the first order EA converter .................. 27 Discrete time model of the second order EA converter ........... 28 Z - model of the second order 2A converter ................. 30 Line search contours of the gradient descent method that approaches the optimum solution 211* ............................. 33 The multichannel 2A converter array is modeled by minimizing fimction flw) within regularization framework ..................... 35 Architectures of (a) time-encoded modulation (TEM) machine (b) continu— ous time 23A converter and (c) semi-synchronous hysteretic EA converter . 36 Comparison of integrator outputs when (a) hysteresis level, A = 0 and (b) hysteresis level, A = 0.05 .......................... 37 Discrete time model of the semi-synchronous (hysteretic) 2A converter . . 38 Illustration of compensation steps for the semi-synchronous hysteretic 2A conversion. The residue at the end of synchronous conversion is discharged (charged) with a reference current up to a fixed potential A to get extended bits. ...................................... 41 Mathematical model of the S TL system ................... 45 First order STL system that consists of the first order 2A converter array and the first order adaptation module .................... 49 Mathematical model of the 2-dimensional first order STL system ...... 50 Second order STL system that consists of the second order EA converter array and the second order adaptation module ................ 53 Mathematical model of 2-dimensional second order STL system ...... 54 Hysteretic STL system that consists of hysteretic 23A converter array with hysteretic adaptation module ......................... 57 Illustration of EA dynamics for (a) first-order modulator with :c = 0, (b) modulator with :1: > 0, (c) higher-order modulators (bold lines indicate higher velocity), (d) effect of reducing the magnitude of x .......... 60 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Functional verification of the first order ST L system using artificially gen- erated multi-channel data: (a) Analog input signals presented to the 8- dimensional STL system (b) The digital output data representing the trans- formed input signals (c) The reconstructed signals using the digital output data and the signal transformation coefficient obtained from matrix A of the STL system (d) Adaptation of the STL system is shown by N orm(A) that converges to a stable value after learning the signal statistics ..... Functional verification of the second order STL system using artificially generated multi-channel data: (a) Analog input signals presented to the 8- dimensional STL system (b) The digital output data representing the trans- formed input signals (c) The reconstructed signals using the digital output data and the signal transformation coefficient obtained from matrix A of the STL system (d) Adaptation of the STL system is shown by N orm(A) that converges to a stable value after learning the signal statistics ..... Functional verification of the STL system using synthetic multi-channel data: Plots (a)-(d) show the FF T of the 4 input signals presented to the 4-dimensional learner: (c) and (d) are the mixture of signal shown in (a) and (b). Plots (e)-(h) show the FF T of the output data. The output plots (g) and (h) show that the redundancy in channel 3 and 4 is removed by the learner system Plots (i)-(l) show the reconstructed signals from the un- correlated output data ( e H h ) and the transformation coefficients of A. The reconstructed plots show that the signal transformation is a linear process. The signal reconstruction accuracy of STL system is shown using the mean square error (MSE). The reduction in MSE implies better adaptation of the STL system by improved learning of signal statistics ............. Increase in the order of the EA converter framework of the STL system decreases the reconstruction error which is attributed to the improved noise shaping of higher order EA converter .................... The effect of OSR of the EA converter army on the performance of the STL system ................................. The effect of the resolution of a signal transformation matrix A on the per- formance of the STL system ......................... The component mismatch effect on the performance of STL system The effect of integrator leakage on the performance of STL system xi 63 66 67 68 70 71 72 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.]7 5.18 5.19 The response of a sigmoid function that is used to model the nonlinearity of S TL system components .......................... 73 The non linear effects of used components on the performance of STL system ..................................... 74 The effect of system dimension and signal statistics on the performance of STL system .................................. 75 Comparison of the first order and the second order STL system perfor- mances .................................... 76 Comparison of the first order and the second order STL system perfor- mance with respect to the resolution of a linear transformation matrix A . . 77 Comparison of the first order and the second order STL system perfor- mance with respect to the component mismatch in the system ........ 78 Comparison of the first order and the second order STL system perfor- mance with respect to the component leakage in the system ......... 79 Comparison of the first order and the second order STL system perfor- mance with respect to the component non-linearity of the system ...... 80 Comparison of the first order and the second order S TL system perfor- mance with varying system dimensionality .................. 81 Functional verification of the STL system for the multi-channel neural data: (a) Original multichannel input signals (b) Digital output produced by the STL system, and (c) The reconstructed signals from the multi- channel output data streams of the STL system and the signal transfor- mation matrix A ............................... 82 5.20 Adaptation of the STL system is shown by the signal transformation matrix 6.1 6.2 6.3 6.4 A that converges to a stable value after learning the correlation of neural signals .................................... 82 The block diagram of 4-dimensional STL system .............. 86 The schematic diagram of 2-dimensional (2-Input 2-0utput) S TL system . 89 Schematic: I bit up-down counter/shifter ................... 91 Schematic: I] bit up-down counter/shifter .................. 92 xii 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 7.] Schematic: Transconductor with bump circuit for improving the linear op- erating range. ................................. 93 Circuit simulation response of the transconductor .............. 94 The schematic I 0-bit current DAC that provides a reference current for the transconductor network of signal transformation module ........... 95 The output response of the IO—bit current DAC is plotted by integrating the DAC current output for a fixed interval of 20ps. ............... 96 Schematic of the hysteretic first order 2A converter ............ 97 Schematic diagram of the hysteretic comparator of the 2A converter. The hysteresis level in the comparator is changed by adjusted the bias values VPB and VNB of the comparator: ...................... 97 Third order single loop single bit 2A modulator. .............. 98 The schematic of the first stage integrator of the third order hybrid 2A converter. ................................... 99 The schematic of the second and the third stage stage integrators of the third order hybrid 2A converter. ........................ 99 Schematic of the folded cascode op-amp .................... 100 2-Channel STL system response to DC inputs during the initial period of 100us. The digital outputs d1 and d2 represent a digital pulse width data equivalent to input signal X 1 and X2 respectively. VOU T1 and VOU T2 are the integrator outputs of the 2A converter array used in the 2-dimensional STL system .......................... 102 2-Channel STL system response to DC inputs during the final simulation period of 100us. The STL system adapts such that the digital output d2 represents the transformed signal of X2 that is un-correlated from signal X1. The reference signal X 1 is represented by the digital output d1 and VOU T 1 shows the unchanged integrator response. ............. 103 Convergence plot of the non-diagonal element A( 2,] ) for different DC input signals with respect to fixed reference signal of 40mV ............ 104 The response of signal transform matrix that shows the adaptation of ST L system with respect to the non-linearity of the current DAC ......... 105 Block diagram of the test setup used for the mixed signal design verification 107 xiii 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 Setup showing the interface of PC, Xilinx Spartan-III and NI data acquisi- tion card with home grown motherboard to test the designed chips ..... 107 Micrograph of the 42 channel hysteretic EA converter array. By disabling the hysteresis, the shown architecture acts as a 42 channel first order 2A converter array. ............................... 108 ADC output response where current is varied from -100nA to +1 0071A in 1024 steps .................................. 109 Measured DNL plot of the hysteretic EA converter that shows the 10-bit accuracy ................................... 1 10 Demonstration of the 2A converter that measures the sub-threshold char- acteristics of a PMOS transistor whose drain current is reduced as low as 50 fA. ..................................... 111 Comparison of power dissipation with respect to sampling frequency shows that the hysteretic EA converter is more power efficient compared to the conventional EA converter ......................... 111 Micmphotograph of the 3rd order 2x4 dimensional ST L system. ...... 113 Power spectrum of the first channel ( 1 kHz input signal) of the 3rd order STL system. ................................. 115 Digitized response of the transconductor of the diagonal cell with respect to the reference bias current. ......................... 116 Mismatch behavior of all diagonal cells of the 4-dimensional STL system. The worst case mismatch variations are within 4% of the largest diagonal cell output. .................................. 116 The non-linearity of current DAC of the non-diagonal cell of the signal transformation module ............................ 117 Running average of the modulator output of the second channel over 1024 cycles ..................................... 1 19 Discrete time behavior of the decorrelation coefficient a21 ......... 120 Adapted value of am after 10000 cycles for DC input signals ........ 120 The adopted value of the de-correlation coefficient (121 as the phase is var- iedfiom 0° to 360° .............................. 121 xiv 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 8.1 8.2 8.3 8.4 8.5 8.6 8.7 The adopted value of the decorrelation coefficient am as the magnitude and the phase of the second signal 232 are varied ............... 122 The residual power left on the second channel as the phase difierence (cor- relation) between the two signals is varied from 0° to 180° ......... 123 Characterization of the 3rd channel is performed by 3 sinusoidal signals :51, 2:2 and 2:3. The phase difference (on) PH I (1, 2) between signals x1 and 3:2 is kept constant and the phase difference ((151 3) PH I (1, 3) between signals 1:1 and :1:3 is varied ........................... 123 The ratio of decorrelation coefficients a31 and egg with respect to the phase difference between signals X1 and X3 .................... 124 The residual power left on the 37" channel with respect to the phase differ- ence between signals X1 and X3 ....................... 125 Signal power in each channel before and after adaptation .......... 125 Reconstruction signal power of the 2nd signal with the help of signal trans- formation matrix A and the digitized modulator output of the first channel. 127 Reconstructed signal power of the 3rd signal with the help of signal trans- formation matrix A and the modulator outputs of first two channels. . . . . 128 Far field recording of miniaturized microphone array ............ 130 2-D projection of far field acoustic signal on miniaturized microphone ar- ray ...................................... 130 4x4 surface mount MEMS SiSonic microphone (Knowles Inc.) array. Each microphone is separated by a distance of] cm. ............... 135 10° resolution obtained from the 4x4 Microphone array .......... 135 The schematic of the pie-processing circuit used to separate the common mode and differential mode signal of each microphone ........... 137 (a) A 4-microphone array/grid consists electret condenser microphone placed at a distance of 1 cm from the center of the microphone array. (b) The test setup shows the tonal source located at a distance of 1 m from the microphone array ................................ 138 Coefficient on tracks the bearing angle 0 of the sound source ....... 139 XV 8.8 4° resolution is achieved by eliminating the common mode signal from all microphones. The pre-processing technique achieves the total dynamic range of 90° angular movement of the speaker: ............... 139 8.9 For small dynamic range of 34°, a resolution of 2° is achieved with the help of common mode suppression technique ................... 140 8.10 The common mode suppression and the mismatch compensation of micro- phone responses improve the bearing angle response. The non-linearity is suppressed for the given input dynamic range of 90° at the resolution of 4°. 140 8.11 The common mode suppression and the mismatch compensation of micro- phone responses improve the input dynamic range to 50° at the achievable resolution of 2° ................................. 141 xvi CHAPTER 1 Introduction Advances in miniaturization are enabling sensors that integrate high-density of record- ing and recognition elements within a single device, promising an unprecedented break- throughs across disciplines ranging from life-sciences to communications. However, these advances have led to new challenges in the area of robust and energy efficient signal pro-— cessing, a topic that has been attracting increased interest in the circuits and systems com- munity. The objective of this research is to develop theory and algorithm for an adaptive high dimensional oversampling analog to digital interface and to investigate its hardware realization. 1.1 Milestones of Oversampling 23A Converters The emerging techniques of oversampling EA converters have found wide range of appli- cations ranging from biomedical to RF designs. This is possible because of the underneath robust architecture which is relatively insensitive to device imperfections making them suit- able for high resolution interfaces. The higher resolution of 2A converters comes from the oversampling therefore they run at much higher speed compared to Nyquist rate analog to digital converters. The oversampling of signal spreads the noise over wider bandwidth and thus attenuates the noise in the signal band. In addition to oversampling, the EA converters use negative feedback that performs the high pass filtering of the quantization noise thus ] _ Hybrid _‘ Multi-bit . MAASH” ' I Z A Single loop Higher order ' 9 Parallel I Modulators I Modulatorsl Spl'rlt 2A l I I i I I I 7 1950 1960 1970 1980 1990 2000 2010 Figure 1.1. Milestones of 2A converters provide more attenuation of in-band noise. Therefore, the EA converters are also called the noise shaping converters due to modified response to the quantization noise. This noise shaping behavior improves the Signal-to-Noise Ratio (S NR) of the 2A converter in the signal band that leads to a higher resolution. The details about the noise shaping character- istics of the EA modulators are discussed in chapter 2. The SA converters have evolved over the last six decades and their milestones are shown in Fig. 1.1. Although the 2A converter is a classical example of a mixed signal circuit design, the interesting fact is that they are originated from the field of communica- tion back in 1954 when this technique was applied for signal tracking and data transmis- sion [1, 2]. The use of 2A modulators was limited to communication until early 19608 when it was realized that the modulation principle naturally yields a method for binary encoding or tracking of analog signals. The concept was first realized on the board level architecture in early 19605 and it got its integrated form in 19703. In the early stages, the single loop 2A modulator [3] was designed for analog to digital conversion. By that time the audio applications were driving the technology therefore a high resolution and wide dynamic range were the key requirements. 80 in the 19805, researchers came up with higher order 23A modulators [4, 5, 6, 7, 8] that improved the dynamic range of single loop modulators at the cost of less stable structures. The stability of higher order modulators was improved by cascading of stable lower or- P 10*1 OWern/V) 10-2 Figure 1.2. The SA converters are driven by the bit rate and the power consumption specified by their applications. der (1“ or 2nd order) EA modulators to achieve higher order modulation. These cascade or MASH [9] structures have the dynamic range of the higher order single loop mod- ulators as well as the stability of the lower order modulators. The in-band quantization noise was further reduced by employing the multi-bit quantizer [10, 11] to improve the Signal-to-Noise Ratio (SN R). Despite the advancements in SA modulators, the area that still remains unsolved to date is the underlying theory that governs their stability and long term behavior. The underlying non-linear and sometimes chaotic dynamic behavior are still active areas of research today. Even though several approximation techniques were developed, the most notable theory showed the noise shaping behavior [12] which is the fundamental principle of oversampling EA converter. The quantization noise generated in an oversampling EA converter is assumed to be white i.e. the quantization noise is assumed to be random, an approximation which is not seen in a real hardware therefore the correlated quantization noise degrades the perfor- mance of 2A converter. In order to randomize the quantization noise, special split 2A Dimension Figure 1.3. Sensor miniaturization has enabled the high density sensing where the dimensionality of the system plays equally important role along with the bit rate and the power consumption. conversion [14, 13] architectures were proposed. In split EA converter [15, 13], the quan- tization noise is de-correlated by splitting the input signal across parallel multichannel 2A modulators. It is shown that the M -dimensional 2A modulators with oversampling ratio N achieves the performance of a single modulator with an oversampling ratio of M x N. This method reduces the constraints on oversampling ratio to achieve the desired perfor- mance at lower speed. For high speed applications, hybrid 2A modulator [16] is designed that combines the continuous time and discrete time modulators to form a higher order modulator. The continuous time integrators used in these modulators relaxes the band- width constraints on the op-amp where as the subsequent discrete time modulators offer the accuracy of switched capacitor circuits. The higher resolution and the robust architecture of 2A converter find many high den- sity sensing applications in the fields of biomedical, audio and RF systems. In high density sensors, thousands of sensors are integrated on a single device. Therefore, the constraints of data bandwidth, sensor area and power dissipation can severely limit the use of multi- Dimensionality Bit Rate g . ._...> Power Figure 1.4. The high density sensing applications are inseparably constrained by the dimensional- ity, bit rate and the power dissipation. channel 23A converters. Such critical requirements of high density sensing motivates new smart techniques required for designing multi-channel EA converters. The presented re- search on multi—channel 2A converter processes the signals in space and time to satisfy some of the constraints to give a special architecture of STL system. 1.2 Motivation for Spatiotemporal EA Learner (STL) System Advancements in the EA converters have found wide applications from biomedical, audio to RF systems. The domain of these applications is mainly quantified by the bit rate and the power dissipation which is shown in Fig. 1.2. For example, the biomedical applications such as pacemakers can work with low bit rate but they have strict power dissipation con- straints. To avoid the burning and damaging of neighboring tissues, one can not exceed the power density of 80mw/cm2 [43]. The audio applications have moderate bit rate but they require a very high resolution where as RF systems on the other hand require high bit rate which leads to more power dissipation compared to other applications. The sensor miniaturization has enabled the integration of large number of sensors within a single device to increase the dimensionality of high density sensing. The dimen- sionality of high density sensors is a relative quantity with respect to the application. For example, a 4 mm2 micro-electrode array [17] employed for brain machine interface con- Figure 1.5. The electrical activity of neuronal population of the cerebral cortex [18] ( 2006) ob- tained by 1024 micro-electrode array. sists of 1024 electrodes where as for the same dimension, a 3 x 3 microphone array [48] with 250nm separation are designed for acoustic sensing. In RF systems, a state of the art 4 x 4 antenna array [64] has shown the separation distance of 100nm on a single die. Therefore, as shown in Fig. 1.3, the number of active sensors or the dimensionality of high density sensing plays equally important role along with bit rate and power dissipation. The dependency of dimensionality, bit rate and power dissipation in Fig. 1.4 shows that these constraints are inseparable. For example, the maximum tolerable power density of 80mW/cm2 [43] in human tissues limit the density of micro-electrode arrays used in neu- ral signal processing or limit the output bit rate like in pacemakers. Therefore, to match the specified constraints of bit rate, power dissipation and number of electrodes, some special techniques are required. The miniaturized high density sensors show that the signals generated at the sensor interface are highly correlated. Therefore, the digitized output data at the sensor inter- face show significant amount of redundancy across the channels. For example, as shown in Fig. 1.5, signal correlation is seen across the recordings of the electrical activity of neuronal population in the cerebral cortex [1 8] obtained by the 1024 micro-electrode ar- ngl" Frequency Temporal Features Low Frequency Spatial Features Figure 1.7. Operational principle of the STL system is to track the slowly varying spatial infor- mation from the correlated high density signals ray [17]. Similar observations are also made about the signals obtained from miniaturized microphone arrays and RF antenna arrays. In miniaturized microphone arrays, where the microphones are placed within a sub-wavelength distance, speech signals are separated by a very small phase, therefore. these microphone recordings show significant amount of correlation across signals. The degree of correlation is a useful parameter which gives the spatial information of signals. There are applications which are interested in specific form of spatial information like the signal correlation rather than the redundant temporal signals. For example, the high dimensional neural recordings of brain machine interface (BM I) l l - High Density . I l , . Sensors ‘ gi .— u‘ " p $(t)3,Hig‘h' Dimensional Signals 2A Learner“ ‘ "" e Figure 1.8. The conceptual diagram of the STL system are used to find the position or the velocity information of prosthetics which lies in lower diluensional space compared to their entire signal space. Similarly, consider the acoustic sOlll‘ce localization shown in Fig. 1.6 where the objective is to find the spatial location or the angular position 0 of the speaker in a room with the help of speech recordings obtained from the microphone array. As the speaker moves in the room, the speech signals received at tlle sensor interface are modulated by the movement of speaker. This spatial modula- tiotl of speech signals is slower compared to the speech signals or the frequency bandwidth of the modulation is smaller compared to that of the speech signals. For acoustic source localization, the objective is to track the spatial modulation of speech signals rather than SPQeCh signals themselves. This shows that we are interested in information which lie in the Subspace of speech signals. The examples of neural signals (Fig. 1.5) and acoustic signals (Fig. 1.6) discussed be- fore show (Fig. 1.7) that we are interested in the slowly moving or the relatively low fre- cl‘lency spatial information manifold and not the signals themselves. This low frequency spatial information lie within a signal subspace which is modeled as Y(t) = A(t) S(t) (1.1) where signals S (t) are the multi-dimensional correlated high frequency temporal source signals that are modulated by the slowly moving or the low frequency spatial modulation or the manifold parameter A (t) to give the multi-dimensional output Y (t). Since the change in spatial information A(t) is very slow compared to source signals S (1‘), therefore A(t) is assumed relatively constant which yields Y(t) = A S(t) (1.2) We are interested in spatial modulation or the manifold information A and not the temporal behavior signals Y(t). When such high density sensor signals are interfaced with conven- tional/traditional multi-channel analog to digital interface, each signal is treated separately to get the multi-channel digitized data. The spatial information is extracted from these dig- itized multi-channel data streams with the help of advanced digital processing. Therefore, the conventional multi-channel systems fail to exploit the inherent correlation of signals. They produce digitized output sequence Y(t) that shows significant amount of redundancy aCross all channels. Therefore, the hardware resources are over-utilized in order to extract SUCh spatial information. Contrary to the conventional multi-channel approach, in this dissertation a novel multi- challure] STL architecture is presented that directly gives us the spatial manifold informa- tioh (A) of the source along with the modulated temporal signals. The presented work inhel‘its some of the properties of compressive sensing [19] that performs the dimensional- ity I‘eduction. It exploits the inherent sparsity of the spatial information of signals which is a fundamental principle of the analog to information converters [20, 21]. This architecture de‘correlates the signals at the sensor interface and represents them with lower dimensional data. The conceptual model of the presented architecture is shown in Fig. 1.8 which shows “lat we are interested in a system that gives us two digitized output data streams. One data stream represents the multidimensional un-correlated transformed signals Y and the other data stream represents the spatial manifold information (A) of source signals. The presented spatiotemporal 23A learner employs such technique of digitized representation of spatial modulation and the modulated output of the source signals. 1.3 Spatiotemporal 23A Learner (STL) System The STL shown in Fig. 1.8 requires a system level approach that performs the spatial sensing of signals along with analog to digital conversion. In this work, a min-max opti- mization [22] approach is designed that models the signal de-correlation and analog to dig- ital conversion within a single cost function. The gradient descent algorithm is employed to minimize the cost function with respect to the internal state of the system that yields a multi-channel EA modulation as a natural choice for analog to digital conversion. The gradient ascent algorithm maximizes the cost function with respect to the signal transforma- tion that learns the spatial distribution of the source signals. The learning embedded within the algorithm naturally yields a Gramm-Schmidt orthogonalization that de-correlates the input signals. This learning is shown to be robust to the computational artifacts of mis- match, offsets and non-linearity and is shown to adapt and compensate these errors without external monitoring. This unsupervised learning [23, 24, 25, 26, 27, 28, 29] and online cOtljpensation are shown to improve the signal de-correlation performance. The unsuper- Vi Sed learning within the 2A framework is similar to the learning mechanism shown in neLII‘ons [30] where the firing of neuron is modeled as a first order EA converter with a p“EECision of 2 to 3 bits. When thousands of neurons act in tandem, they improve the preci- Siol‘l of signals up to 8 — 9 bits [31]. Neuronal computational units (for example synapses or neurons) suffer from artifacts similar to the system non-ideality but when they work in mu"Idem, they deliver the performance unmatched by any artificial systems [31, 30]. Simi- ‘al‘ly, the multi-channel EA converters can work in tandem with the learning mechanism of ‘he system. This online learning and adaptation embedded within a BA converter frame- 10 Transform Pa ra meters D(A) Transformed Output D(Y) Figure 1.9. The architecture of the spatiotemporal 2A learner (STL) system work gives us the novel STL architecture which is shown in Fig. 1.9. This architecture is not designed for any specific form of EA converter but it is shown in this work that it is compatible not only with the higher order 2A converters but also with a novel design of hysteretic 2A converters. The STL algorithm is realized in hardware to show the proof of concept. This algo- rithm can be realized in many ways but the particular mixed signal design presented here is Chosen because it saves the area and the power dissipation of the system. In the designed hal”Chrtrare system, to eliminate the quantization effects, signals are processed in analog do- main before digitization of the analog to digital interface. The analog signal processing (AS P) ensures that the spatial information is directly sampled like we see in analog to in- fc’I‘Itl'lation converters (AI C) [20, 21]. Several reasons are considered for processing signals in analog domain. The basic principles of device physics are used for carrying out the fun- dalnental operations such as addition, subtraction and multiplication which are key func- tiOHS of signal processing. The subthreshold circuits designed for analog signal processing offer better energy efficiency compared to their digital counterparts [32, 33, 34, 35, 36, 37]. The Use of fundamental techniques of signal processing reduce the complexity of analog building blocks and therefore save the chip area compared to their digital realization. The redlllced complexity of analog circuits work at higher speeds because of their abstract de- Vice forms and small driving load. Analog devices operated in the linear region eliminate the Quantization errors seen in the digital domain. Despite all these advantages, analog sig- nal processing techniques are not widespread because they are limited by the device errors of mismatch, offsets and non-linearity of analog circuits. The inherent learning embedded within the algorithm of STL system compensates for these device errors. The learning of spatial information of signals is enabled by the single bit feedback obtained from the outputs of multi-channel EA modulators. The single bit feedback significantly reduce the complexity of the digital hardware which saves the area and power dissipation. The feed- back in Fig. 1.9 is shown to be stable because of the presence of robust EA modulators within the loop. This stability of global feedback network of the STL system is not lim- ited to single bit modulators. The single bit digital feedback simplifies the digital updates of the required signal transformation (spatial modulation parameter) A whereas the sig- nal transformations are performed in analog domain therefore the STL system gives the de-correlation parameters in digital form along with the temporal digitized output of the transformed (modulated) signals at the sensor interface. The signal transformation unit that performs the signal de-correlation is designed with a Current mode transconductor network that offers the compact analog processing unit for the given algorithm. The transconductor network carries out multiply-accumulate (M AC) func tion required for the signal transformation. This signal transformation is carried out by finding the weight vectors of the multiply-accumulate units (M ACs) therefore in order ‘0 de—correlate signals, weight vectors need to be updated with changing input signals. In the STL system, the weight vectors are adjusted with the help of new dynamic biasing technique [46, 47] that modulates the reference currents and improves the power efficiency of the system. Such dynamic biasing of the transconductor network is achieved with the help of feedback obtained from the single bit 2A modulator outputs of the STL system. The Single bit feedback simplifies the digital logic, saves the chip area and therefore helps in accommodating more channels on a single die. In the next section, the applications of spatiotemporal 2A learner (8 TL) system are b1"‘lefly introduced. The inherent key features of these high density sensing applications 12 are discussed. A brief discussion is presented about how spatiotemporal EA learner can exploit some of these features to its advantage in the data acquisition process. 1.4 Applications of Spatiotemporal 2A Learner (STL) System The STL system finds a wide variety of applications ranging from life sciences to high speed communication where high density sensors are deployed for data acquisition. These applications range fiom high speed antenna arrays [65, 66, 67, 68], microphone arrays for high resolution acoustic source localization to low power high density micro—electrode arrays for neural sensing. This research will focus on two applications namely the neural signal processing and the acoustic source localization which are discussed below. 1.4.1 Micro-electrode Sensor Arrays in Neural Prosthetic Devices ....... Prosthetic l Controller Transmission Channel 1024 Channel Microelectrode Array Figure 1.10. Functional architecture of the cortically implanted neural prosthesis illustrating the lute Uace of the data converter with micro-electrode arrays and signal processing module Design of cortically implanted neural prosthetic sensors (CI N PS) is an active area of regcatch in the rapidly emerging field of Brain Machine Interface (BM I) [38, 39]. The core technology used in these sensors is micro-electrode arrays (M E As) that facilitate real—time 13 recording from thousands of neurons simultaneously. These recordings are then actively processed at the sensor interface (shown in Fig. 1.10) and transmitted to an off-scalp neural processor which controls the movement of a prosthetic device [38]. A key challenge to designing implanted integrated circuits (1C) for CI N PS is to efficiently process the high- dimensional signals generated at the interface of micro-electrode arrays [40, 41]. Sensor arrays consisting of more than 1000 recording elements are common [17, 42] which sig- nificantly increase the transmission bandwidth at the sensor interface. A simple strategy of recording with parallel data conversion and transmitting the recorded neural signals ( at a sampling rate of 10 kHz) can easily exceed the power density limit of 80mW/cm2 de- termined by the local heating of biological tissue [43]. In addition to the increased power dissipation, a high-transmission rate adversely affects the real-time control of a neural pros- thesi s [40]. One of the solutions that has been proposed by researchers is to perform compres- SiOn of neural signals directly at the sensor interface, reduce its wireless transmission rate and so its power dissipation [44, 45]. It has been shown that the neural cross-talk and Common-mode effects introduce unwanted redundancy at the output of micro-electrode aTray [41]. As a result, neural signals typically occupy only a small sub-space within a higl'l-dimensional signal space spanned by the micro-electrode signals. An optimal strat- egy for designing the multi-channel analog-to-digital converter is to identify and operate witllin the sub—space spanned by the neural signals and in the process eliminate the cross- channel redundancy. In this research, a novel approach is presented that directly performs the signal decorrelation and redundancy elimination at the analog to digital interface. By ertlI>loying the STL system, the M EA based sensors can adapt to the slow variations of the cross-channel correlation, observed due to relative motion of micro-electrodes with re- spect to signal sources. Thus, the proposed spatiotemporal 23A learner (STL) system can alleviate the cross-channel redundancy across electrodes and therefore, can perform the data—compression directly at the analog to digital interface. 14 1.4.2 Acoustic Sensor Arrays for Source Localization Acoustic Sensor Array _ ”3%. Video , — \ ..... f ,« Surveillance leer-Mulflehahne'r i) AooustlcSource?" Analogto Digital , _ . . ~ ' Conversions: ”when“ .. Figure 1.11. Acoustic source localization used in the surveillance system Acoustics has spanned over wide applications ranging from conventional audio to Sul’Veillance systems. Miniaturized microphone array based source localization and separa- fiOn are widely attracting numerous speech processing applications including smart hearing aids (e.g. Siemens Triano CIC BT'E- 16 channel Digital Hearing Aid) and remote surveil- lance system for homeland security. The generic block diagram diagram of such remote sul'Veillance system is shown in Fig. 1.11. The underlying principle of source localiza— fioh and separation is to accurately identify the spatial location of the desired signal source alohg with other sources of interferences and then beam-steer the response of the array Such that only desired source is enhanced while other interfering sources are attenuated. Researchers have come up with various source localizing techniques which use differ- ent Characteristics of acoustic source signals. For example, in [49], an energy—based acous- tic Source localization technique has been used in an open—terrain acoustic sensor field. The property of intensity/energy attenuation of an acoustic signal as a function of distance from the source is used in a DS P based maximum likelihood (ML) estimation method for locating the source signal [50]. Phase correlation is one of the approaches that does not cause the spreading of the peak of a correlation function. Therefore, the cross-correlation functions derived from various microphone pairs are simultaneously maximized over a set of potential delay combinations to locate the acoustic source [51]. The phase difference measured at the receiving sensors has been used by [52, 53, 54] to localize the coherent, narrow band source with the direction of its arrival. Time delay of arrival (TDOA) is shown to be suitable for broadband acoustic source localization [55, 56, 57] but these estimates degrade with increase in the shrinkage of the sensor aperture dimensions [58, 59]. [60, 61, 62] have developed a low cost low power on-chip acoustic sensors that act as an autonomous node in a sensor network. Such an autonomous node can be used for acoustic source localization but poses real challenges with reduced sensor distance. The wavelengths of all speech signals are in the range of 17.2m (20H 2) to 4.3m (8kHz). So when acoustic sensors are placed within a sub-wavelength distance of signal source, the magnitude and phase separation among all acoustic sensors are extremely small. Such Small changes in signals are shown to get resolved with the help of oversampling and aver- aging techniques [95]. This gives the motivation for using the EA converters which show the noise shaping characteristics in addition to the oversampling that could help in resolv- ing such small signal changes. The proposed STL system with embedded 2A modulators directly performs the spatial signal decorrelation at the analog to digital interface and lo- cfillizes the source with the help of digitized spatial manifold coefficients. Validity of these cl aims is shown and discussed in more details in Chapter 8. 1-5 Scientific Contributions me presented research integrates the concepts from machine learning with EA modulation that leads to the following innovations in algorithm and hardware: 16 1. Optimization framework for generating spatiotemporal 23A learner (STL) sys- tem: This research is based on a min-max optimization of a regularized cost function which directly combines the EA conversion with signal de-correlation. This gener- alized method is shown to be helpful in designing novel modulator topologies which includes semi-synchronous hysteretic EA modulators. 2. Real-time tracking and de-correlation of high-dimensional input signals: The spatiotemporal 2A learner (S TL) system not only produces the digitized represen- tation of the de-correlated input signals but also gives the digitized representation of signal transformation coefficients. This algorithm tracks the spatial statistics of input signals in real-time, thus providing a framework for designing a mixed-signal system with on-chip learning. 3. Compensation method for analog circuit artifacts: By embedding analog signal computing in a BA feedback loop, analog artifacts such as mismatch, non-linearity, distortion and offsets are compensated. Also, an on-line learning technique enables the architecture to be robust to variations in environmental conditions. 4. Dynamic biasing technique of analog interface circuitry: The proposed algorithm also provides a framework for adapting the biasing condition of analog computing circuits such that it consumes optimal power based on the input signal statistics. 1.6 Dissertation Organization TThe dissertation is organized as follows: The theory of 2A converters is presented in chap- ter 2. It concisely introduces the concepts of quantization, order of 2A converter, and file effect of device imperfections on the performance of a EA converter. Based on these fundamental concepts, an optimization framework for the multichannel parallel EA con- Verter is shown that models the 2A conversion within the context of machine learning. 17 This framework is shown to yield a novel hysteretic 2A conversion algorithm whose prop- erties are presented in chapter 4.5. The optimization framework is then extended to the STL architecture which is presented in chapter 4. A min-max optimization framework is presented that yields an outer-product based on-line signal de-correlation algorithm. The performance of the STL system is evaluated with MATLAB simulations which are shown in chapter 6.1. The simulation results are shown to demonstrate that by embedding analog computation in the feedback loop of a BA conversion, the presented topology becomes robust to analog artifacts. In addition to performance evaluation, the STL algorithm is shown to work with real life neural signals. The encouraging simulation results give us the confidence and handle over the hardware realization of the system. The circuit design and the circuit level simulations are shown in chapter 6. Two hardware prototypes are designed, one with the first order and the other with the third order EA converter framework. The performance of the current mode first order 2A converter that also forms the core com- ponent of the third order STL system is evaluated in 7. The benefits of novel hysteresis mechanism embedded within the first order EA converter is verified with hardware results. Prototypes of the first order and the third order STL systems are fabricated. For brevity, hardware results of the third order STL system are reported. Test results of acoustic source localization with the help of third order spatiotemporal EA learner system are presented as a proof of concept in chapter 8. Concluding remarks and the future directions for the presented work are discussed in chapter 9. 18 Part 1 Theory and Algorithm 19 CHAPTER 2 Regularization Framework for Designing EA Converters This chapter introduces the fundamental concepts of EA conversion and the mathemat- ical notations which will be used in the regularization framework for modeling the 2A modulation. 2.1 Fundamentals of Over-sampling Data Converters Analog to digital conversion is traditionally described in terms of two separate operations: the uniform sampling and the quantization in amplitude [70]. The quantization as shown in Fig. 2.1(c) is a process where infinite number of analog input values are mapped to a finite number of output amplitude values [70]. The N — bit ADC has a 2N quantization values. For an N — bit quantizer, the separation between output levels of the quantizer is given by _ Q —2N—1 where Q is the maximum output range. If the full scale input range is I‘ then the separation between the input levels (7) is given by _I‘ “aw A quantization error is defined as the difference between the quantizer output and the input as shown in Fig. 2.1(a). When the input signal exceeds the full scale input range then the 20 'D D q...— Figure 2.1. (a) Model of the quantization as an additive noise (b) Quantization error distribution under white noise approximation (c) 2-bit Quantizer quantizer is said to be overloaded. The spectral density of a quantization error approaches to uniformly distributed additive white noise when 0 The input signal does not exceed the input range of the quantizer o The input signal is active across many quantizer levels 0 The probability density function of the error process is uniform over the range of quantizer error 0 The random variables of the error process are uncorrelated The quantizer error probability density function under white noise approximation is shown in Fig. 2.1(c). The power in the quantization error a? is given by 5 2 __ 1 if 2 d 06 —— '3 —6 6Q CQ ‘2‘ 2 _ 52 06 — E In a sampling process, a continuous time signal is sampled at the uniformly spaced interval. A continuous time signal x(t) is represented by uniform samples :I:[n] = 276%) where f3 i s the sampling frequency. In the Nyquist rate data converters, the sampling frequency f3 is chosen to be twice the input signal bandwidth f B. Therefore when a signal is sampled at the N yquist rate, the residual energy left above the signal bandwidth f B can be filtered 21 out using anti-aliasing filter. In a N yquist rate converter, the input signal is periodically repeated at frequencies f 3: 2 f B, therefore a very sharp cutoff anti-aliasing filter is required. The power spectral density NQ( f) due to quantization noise is given by 62 1 = 5*}: (2.1) NQU) Eqn. (2.1) shows that the power spectral density due to quantization noise is reduced by in- creasing the sampling frequency ( f s) and spreading the noise power over a wider frequency band. The dynamic range of a quantizer is defined as the power of a full scale input sinusoid divided by the input referred quantization error power where the signal power is defined as the mean squared value of the signal [71]. The power of a full scale sinusoid input signal S 3 is S=—=— r S 8 8 *( ) If G is the gain of the quantizer then the input referred quantization noise power SQ is given by 62 ,2 SQ = __,- = 7— 1202 12 Therefore, the dynamic range (DR) of an N-bit quantizer is DR = figi = 52221") SQ 2 i.e. the dynamic range of an N -bit quantizer is DR = (1.76 + 6.02N)dB The dynamic range of an ideal Nyquist rate data converter is equal to the dynamic range of the quantizer [71]. In an over-sampling data converters, the sampling is done at a much higher rate com- pared to the Nyquist rate ( f N) with a course quantization embedded within a feedback loop 22 in order to reduce the amount of quantization noise in the signal band [71]. The down sam- pling using digital filter at the quantizer output gives equivalent digital representation of the input signal. By increasing the sampling frequency (f3), the cut-off constraints on the anti-aliasing filter are relaxed. The over-sampling rate (OSR) of the over-sampling data converters is given by fs OSR = — fN where f3 is the over-sampling fiequency and f N is the Nyquist frequency. The over- sampling ratio (OSR) reduces the baseband noise by the factor of OSR. Therefore, the dynamic range of an over-sampling data converter is improved and is given by _ OSR*SS __ 3 DR _ * OSR * (2”) (2.2) SQ 2 Eqn. (2.2) shows that in order to increase the resolution by one bit, the oversampling ratio OSR needs to be doubled. A EA converter is a special class of an over-sampling data H(z) Quantizer F(z) DAC Figure 2.2. Block diagram of the feedback modulator used in an oversampling data converter converter that alters the spectrum of quantization noise such that the noise is attenuated in the signal band and amplified out of the signal band. Because of the high pass filter- ing of the quantization noise, the 2A converter is also called the noise shaping converter Which improves the signal to noise ratio (SN R) in the signal band. The fundamental block diagram of the 2A converter is shown in Fig. 2.2 where the number of feedback loops defines the order of a 2A converter. As shown in Fig. 2.2, A(z) and F (2) are the discrete time filters that adjusts the loop gain to stabilize the feedback modulator. Quantization is 23 achieved by uniformly spaced decision levels with the help of analog to digital converter (ADC). The feedback is obtained by converting the digital output of the ADC in to ana- log signal with the help of digital to analog converter (DAC). The accuracy of the DAC determines the quantization noise in the signal band. For a high resolution requirements, a very high linearity is expected from the DAC which may become bottleneck for the sys- tem performance. A simple form of quantizer in the EA modulators is a 1 — bit quantizer. A 1 — bit quantizer has only two output levels therefore quantizer may introduce offset and gain errors rather than nonlinearity [72]. With such a 1 — bit quantizer, only 2-level DAC is required which is easy to implement. Although 2-level DAC is linear, the noise error introduced by such quantizer is very large in the signal band Because of the noise shaping characteristics of the 2A converter, the introduced quantization noise is attenuated and moved out of the signal band. The attenuation of the quantization noise in the signal band increases with increase in the order of a BA converter, therefore the dynamic range (DR) improves with increase in the order of a 2A converter. The dynamic range DR L of the Lth order EA converter is given by 2L 1 DRL = % (Tr—2}) OSR2L+1 (2.3) The rrns noise power p L of the Lth' order EA converter is given by aerL 2f0 L4"; ”L _ x/2L+1 (73—) (2'4) The noise shaping characteristics plotted in Fig. 2.3 shows that the noise power reduces in the signal band and amplifies outsides the signal band with increase in the order of a EA converter. This noise shaping property of a 2A converter relaxes the precision of hardware components used in SA converter. A 2A converter is shown to be a very robust structure that has inherent compensation properties to any device irregularities [71]. The theory of 2A converter in the next section shows the data conversion procedure and a noise shaping characterization of a 2A converter in more details. 24 Noise shaping characteristics of sigma delta converter — Order (L) = 3 ----- Order (L) = 2 - - -Order (L) =1 .9 or .0 .p. .......................................................................... O N r 2. (a 3 2’... t i Magnitude spectrum O 00 ' : : \ : E a i f . i 1 fi ‘ I i I ' ' 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency normalized to sampling frequency (fs) Figure 2.3. Noise shaping of the EA converter: Attenuation of the quantization noise in the signal band increases with increase in the order of the 2A converter 2.2 Theory of EA Converters 2.2.1 First Order 2A Converter ‘ A X _ + w[n] :l—T—[E d[n] Figure 2.4. Discrete time model of the first order EA converter The order of a 23A converter is decided by the number of integrators in the feedback loop that accumulate the error signal. In a first order EA converter, the integrator accumu- lates the error signal which is a difference between the input signal a:[N] and the modulator output signal d[N] at its output w[n] [71]. The Eqn. (2.38) is a recursion equation of an 25 integrator used in a first order 2A converter shown in Fig. 2.4. For the first order 23A converter, the recursion after N cycles is given by w[N] = w[N — 1] + a:[N] — d[N — 1] (2.5) where d[N — 1] == sgn(w[N — 1]). The recursion given by 2.6 is expanded as w[0] = 0 w[1] = w[0] + :I:[1] — d[O] ru[2] = w[1] + x[2] - d[l] After N cycles, w(N) is given by w[N] = w[N — 1] —l— :1:[N] — d[N — 1] (2.6) By adding recursion terms up to N cycles, the closed form of w(N) is obtained N N —1 w[N] = 2.1)[0] + 2 mp] — Z d[z’] (2.7) i=1 '=0 where w[N] is the residual value left after N cycles. In oversampling data converters, the input a: is assumed constant for the oversampling period of N cycles. Therefore, dividing both sides of Eqn. (2.7), we get 1 1 N '1 N1L?[N] = 1r — Tv’ :1 d[z] (2.8) 1,: As N —> oo, 7%w[N] —> 0. Therefore 1 N—l a: = N Z; d[i] (2.9) 26 Q(z) Y(z) Figure 2.5. Z - model of the first order 2A converter As given in Eqn. (2.9), the input signal x is represented by averaging the modulator output over N cycles. The z-domain model of the first order 2A converter is shown in Fig. 2.5. The quantization noise is assumed to be white and it is represented by an additive factor Q(z). The integrator of a EA converter is represented by H (z). The output Y(z) is written as W) = — z*1Y(z))H 0. Therefore, N—12—1 —2 221121 + 1:30 d[i] (2.26) 2'— 0j=0 The second order topology is also formed by removing the feedback from the second mod- ulator. By removing the feedback signal d[N - 1] from the second integrator (Eqn. (2.18)), the recursion for w[N] at any instant N is given as w[N] = w[N — 11 + u[N — 11 (2.27) 29 With modified w[N] as shown in Eqn. (2.27), the equivalent digital output of input :1: is given by the second order 2A converter as 1 N—l 2—1 x = E Z de (2.28) i=0 j=0 The z-domain model of the second order EA converter is shown in Fig. 2.7. The quanti- C1(2) 4. ~ v H1(Z) 1(2). H2(Z) V2(z) 6 Y(z_). 1 Figure 2.7. 2 - model of the second order 2A converter zation noise is assumed to be white noise and it is represented by an additive factor Q(z). Two integrators u[N] and v[N] that are used in discrete time analysis are represented by H1(z) and H2(z) in the z-domain model of the second order EA converter. The output Y(z) is written as Y(z) = V2(2) + 62(3) 12(2) = (v1(z>+ 2'1Y(z))H2(z) V1(Z) = (X(Z) + Z_1Y(Z))H1(Z) Solving for Y(z) using V1(z) and V2(z), we get H1(3)H2(Z) ~ 1 X(") + 1+ 2‘1H2(z)(H1(2) + 1) YR) : 1+ z—1H2(z)(H1(z) + 1) Q(Z) (2-29) H1(z) and H2(z) are assumed to be ideal integrators whose response is given by H1(Z) = H2(Z) = (2.30) l—z—1 30 Substituting the value of H1(z) and H2(2) in Eqn. (2.29), we get Y(z) = X(z) + (1 — z-l)‘-’Q(z) (2.31) Eqn. (2.31) shows that the attenuation of quantization noise in the signal band by the sec- ond order 2A converter is more compared to the first order EA converter as given by Eqn. (2.13). Therefore the second order filter (1 — 2‘1)2 improves the signal to noise ratio (SN R) compared to the first order filter (1 — 2‘1). The improvement in the attenuation of the quantization noise due to the second order filter is shown in Fig. 2.3. “With leakage factors (11 and (12 of integrators 2i and 21) respectively, the output response of the second order 2A converter is given as Y(z) = X(z)+ (1— (1 — urn—1X1 —— (1— a2)z‘1)Q(z) (2.32) Having briefly introduced to the noise shaping behavior of the EA converter, the next section will show you the regularization framework that introduces the optimization prob- lem. In this problem, a constrained cost function is minimized by the gradient descent algorithm. Mth change in the input state and the internal state of the function, the gradi- ent descent algorithm takes gradient steps that minimizes the cost function. It is shown in the next section that these gradient steps naturally yield the modulation steps of the multi- channel ZA converter. In chapter 4, the constrained cost function is modified that yields the STL system. 2.3 Regularization 2.3.1 Introduction to the Regularization Regularization is one of the common scalarization methods that is used to solve the bi- criterion problem [22]. The generic formulation of bi-criterion problem consists of two objective functions where one of the objective functions is minimized and the other is maximized for a given constraint functions. The objective of the regularization is to smooth 31 out errors caused by the bi-criterion problem by adding the differentiation terms. The differential operator in the bi-criten'on problem represents the measure of the variations or the smoothness of a function. For example, the reconstruction of signals is considered as a regularization problem where the signal noise is a regularization parameter. Therefore, the reconstruction of signals is considered as a convex optimization problem. In simple tenns, the regularization is a curve/function fitting under given constraint functions. The most common form of regularization is based on the minimization using the Eu- clidean norm that results in a convex optimization problem. The function to be minimized can be defined using any norm but L1 and L2 norms are comparatively simple to eval- uate compared to some of the other norms. Each norms comes with certain tradeoffs in evaluating the function. The L2 norm puts more emphasis on large errors than the small errors caused in regularization therefore they have modest residual errors in the regular- ization function [22]. The Regularization using L1 norm is more robust compared to L2 norm because L1 puts larger emphasis on small residuals (errors) compared to L2 norm. The effect of larger residuals (errors) is reduced with an L1 norm compared to that with L2 norm while approaching the optimized solution of a bi-criterion problem. Therefore, the regularization with an L1 norm can also be used as a heuristic for finding the sparse solution. The difference in the relative weighting for a small and large residual errors due to L1 norm helps to have a smaller deviations that are within a smaller error constraints of a closed form optimized solution. These small deviations due to L1 norm and the gradient steps taken to correct those errors lead to the 2A converter which will be shown in the next section. 2.3.2 Regularization Theory of Multi-channel 2A Converters In this section an optimization framework for deriving the multichannel 2A converters is introduced. For the sake of simplicity it is assumed that the multichannel 2A converter input is an M dimensional vector x 6 ”RM where each dimension represents a single 32 Oscillatory behavior around 0 ntimal solution w* = 0 --' ." Trajectories of gradient descent algorithm 4‘:‘ Figure 2.8. Line search contours of the gradient descent method that appmaches the optimum solution 20* channel of the multi-channel array. It is also assumed that the vector :1: is stationary with respect to the discrete time instance N which is a valid assumption for an over-sampling data converter. The validity and the limitation of this assumption is explained briefly at the end of this section. Denote a regression weight vector w 6 RM. Consider the following optimization problem “1,1“ f(w) (2.33) where f(w) = |w|T1 — wa (2.34) and 1 represents a column vector whose elements are unity. The cost function (Eqn. (2.34)) consists of two factors: the first factor is the L1 regularizer which constrains the norm of vector w and the second factor that maximizes the correlation between vector w and an input vector x to minimize the function f (w). The L1 regularizer is chosen to define the cost function in Eqn. (2.34) because the solution obtained by updating the to with the gradient steps at any instant of time perfectly fits with the modulation of a BA converter. To ensure that the optimization problem in Eqn. (2.33) is well defined, the norm of input vector IIXIIoo S 1 is assumed to be bounded. The closed form solution to the optimization 33 problem in Eqn. (2.33) is found to be w* = 0 as shown in Fig. 2.8. Given an initial estimate of the state vector w[0] , the online gradient descent step for minimizing the Eqn. (2.33) after N iterations is given by W[N] = Wm _ 11 — 17% (N 1) (2.35) where n > 0 is defined as the learning rate. The choice of L1 norm in Eqn. (2.33) ensures that for n > 0, the iteration (2.35) exhibits an oscillatory behavior around the solution w*. Combining Eqn. (2.35) with Eqn. (2.34), the recursion Eqn. (2.36) is obtained: w[N] = w[N — 11 + 27(x — d[N — 11) (2.36) where d[N] = sgn(w[N — 11) (2.37) and sgn(w) denotes an element-wise signrnn operation such that d[N] 6 {+1, —1}M represents a digital time-series. The iterative steps in Eqn. (2.36) lead towards the solution of the optimization problem in Eqn. (2.33). This iterative step in Eqn. (2.36) has the same form as that of a recursion of the first order EA converter in Eqn. (2.6). For M dimensional system, the recursion in Eqn. (2.35) represents the recursion step for M first-order 2A converters [72]. Therefore, the recursion in Eqn. (2.36) represents a parallel multichannel 2A converters as shown in Fig. 2.9. In the given architecture, every single channel from the multichannel 2A converter system has a independent dedicated input. Following N update steps, the recursion given by Eqn. (2.36) yields 1 N 1 x —— N Z d[n] = W(W[N] — W101) (2.38) 22:1 By using the bounded property of w that asymptotically leads to 1 N N 21 d[n] _i x (2.39) 34 2A Converter Array Figure 2.9. The multichannel 2A converter array is modeled by minimizing fimction f(w) within regularization framework as N —-> 00. It can also be shown that N update steps yields a digital representation which is logg(N) bits accurate. L1 norm in the optimization function shown in Eqn. (2.33) ensures that for n > 0, and the iteration Eqn. (2.35) exhibits an oscillatory behavior around the solution w*. The L1 norm decreases the magnitude of errors around the optimal solution w* but increases the frequency of oscillations. Therefore, the multi-channel EA converter show increased switching of the comparator output given by Eqn. (2.37). The increased switching of a 2A converter leads to increase in the power dissipation. Therefore, in order to reduce the frequency of oscillations of a multichannel EA converter using an L1 regularizer, a novel technique of hysteretic 2A converter is introduced. By adding the hysteresis in the comparison operation given by Eqn. (2.37), the frequency of oscillations is reduced. The hysteresis introduced at any time instant N in Eqn. (2.37) is given by d[N] = sgn(w[N — 1] + d[N — 1]A) (2.40) A hysteretic EA converter is a special technique applied within a BA converter where the frequency of switching is reduced especially for very small signals. The reduced fre- quency of switching and the oscillations save the power dissipated by the multichannel 23A converter and hence provide the advantages in designing a low power EA converter. The theory and the simulation results of a hysteretic 2A converter are given in chapter 4.5. 35 CHAPTER 3 Hysteretic 2A Converter 3.1 Motivation for the Hysteretic 2A Converter ] - Integrator Comparatorl ]‘ w (a) Integrator Comparator / - Integrator Comparator I] (C) / I l (b) Figure 3.1. Architectures of ( a ) time-encoded modulation (TEM) machine (b) continuous time EA converter and (c) semi-synchronous hysteretic 2A converter Low power applications such as remote sensing and neural sensing have signals in the range of uV to mV. For small signals, the signal noise becomes a comparable factor that leads to increased spurious transitions. Therefore, the power dissipation due zero cross switching [47] increases. The zero cross switching is significant in a 2A converter for small signals which leads to increase in the power dissipation. Therefore, in order to reduce the total number of switching cycles of a comparator in a BA converter, a new hysteretic EA converter is presented. 36 The novel hysteretic EA converter augments the continuous time 2A converter output with a pulse width modulation to reduce the switching activities as shown in Fig. 3.1(c). The hysteretic EA converter is compared with a TEM [Fig. 3.1(a)] and a continuous time 2A converter (Fig. 3.1(b)). The TEM topology uses an integrator and a hysteretic com- parator in the feedback configuration (Fig. 3.1(a)) to produce a pulse width modulated (PWM) digital sequence whose duty cycle is proportional to the input signal. In [78], a sampling stage was added outside the TEM feedback loop which led to an asynchronous 2A converter architecture. Continuous time (CT) 2A converter technique as shown in Fig. 3.1(b) uses a non-hysteretic comparator and a sampling stage inside the feedback loop. The continuous time (CT) 23A converter topology is shown to measure up to pi- coarnperes of current [82]. The hysteretic 2A converter (Fig. 3.1(c)) combines the TEM and the continuous time (CT) 2A techniques by using the hysteretic comparator and the sampling stage in the feedback loop. The addition of hysteresis in the comparator reduces the switching cycles when operating with a small magnitude of signals. (a) (b) g 0.1 01 ............. ....... . ..... ............. 8 0.05 - - -'- - -' - - 5- :95 ° 0 (0 83-0'05 ‘. Z l" '- -. -- - -. 9 _0_1L ............. _01, E HystereSIs level = 0 i ' Hysteresis level > 0 g 0 20 40 60 0 20 40 60 Clock Cycles Clock Cycles Figure 3.2. Comparison of integrator outputs when (a) hysteresis level, A = O and (b) hysteresis level, A = 0.05 Fig. 3.2 shows the effect of hysteretic 2A converter in reducing the comparator switch- ing. It shows that the integrator output exhibits a significantly higher comparator switching (see Fig. 3.2(a)) as compared to the converter operating with a hysteresis value, A _>_ 0.(see Fig. 3.2(b)). With the hysteresis level ( A = 0), the hysteretic 2A converter acts as a first 37 order 2A converter. The hysteretic 2A converter improves the resolution of a EA con- verter by adding the hysteresis in a comparator. Due to the hysteresis of a comparator, the residue left on the integrator is proportional to the input signal. By digitizing the residue left on the integrator, the resolution of a hysteretic 2A converter is increased. The resolu- tion enhancement of the hysteretic 23A converter is performed by the two step operation, a continuous time synchronous conversion followed by the asynchronous compensation step. Therefore, it is also named as a semi-synchronous EA converter. Details about the syn- chronous and asynchronous conversion steps of the hysteretic 2A converter are described with the help of mathematical model in the next section. 3.2 Mathematical Modeling of Hysteretic 2A Converter Figure 3.3. Discrete time model of the semi-synchronous (hysteretic) 2A converter Similar to the analysis of the first order 2A converter given in 2.2.1, the bandwidth of the input signal a: is assumed to be much smaller compared to that of the sampling frequency. By adding the hysteresis to the comparator of the first order EA converter given in Eqn (5.2), the recursion equation for the hysteretic EA converter at any clock cycle N becomes w[N] = w[N — 1] + :1:[N] — d[N — 1] + (d[N — 1] — d[N — 2])A (3.1) where the hysteretic comparator output d[N — 1] is given by d[N — 1] = sgn(w[N — 1] + d[N — 2]A) (3.2) 38 The recursion given by Eqn. (3.1) is expanded as 11101 = 0 26111 = w[0] + :r:[1] — d[O] w[2] = 211111 + :1:[2] — d[l] + (d[l] — d[O])A Recursion after N cycles is written as, w[N] = w[N — 11+ :r:[N] — d[N —1]+(d[N —. 11 — d[N — 2])A Solving the recursion for w[N], we get N N—l w[N] = (1101 + Zeb] — Z d[i’] + (d[N — 11 — d[0])A (3.3) i=1 i=1 where w[N] is the residual value left after N cycles. In an oversampling data converter, the input .2: is assumed to be constant for an oversampling period of N cycles. There- fore,dividing both sides of Eqn. (3.3) with N, we get 11N—l Fn,r[N1——n101+ a: - — NZ dlz‘l +—1,(le — ll— lel)A . (3-4) w[N] and w[0] are finite residues therefore as N —> oo, fierV] ——> 0 and imam] —> 0. Therefore 1 N— = N 221121 +% — 11 — d[O])A (3.5) i=1 The Eqn. (3.5) is broken into two parts, a synchronous conversion given by D N and the hysteretic residue H N- A synchronous conversion is given by 1 N —1 _ EV Z d[z'] (3.6) 2:1 The hysteretic residue H N left on the integrator after synchronous conversion is given by HN = %(d[N — 11 — d[0])A 39 The digital output (1 [N] of a BA converter takes values d[n] 6 {+1, —1} therefore H N takes bounded values (—-2A < H N < 2A). The residue H N left on the integrator after N synchronous conversion cycles is proportional to the input signal 2:. Therefore, the digitiza- tion of the residue H N after synchronous conversion gives additional bit information about the input signal 2:. To extract additional information from the residue H N, an asynchronous digital conversion needs to be done. Asynchronous conversion is performed by disconnect- ing input signal from the EA converter and running the modulator only with its reference signals that has fixed charging and discharging rate V. In an asynchronous conversion, the number of clock cycles [Next] are measured till the integrator value 211* [Next] reaches to a preassigned state. The asynchronous recursion steps are given by 221*[Nwt] = 211* [Next - 1] -- (1* [Next — 1]l/ where the initial value stored on the integrator is w" [0] = H N- The hysteretic EA converter is run for extended cycles Next till the residue H N reaches the preassigned state stored at the start of the synchronous conversion. The maximum number of required extended conversion cycles Next are given by 2A Next = '— V The asynchronous conversion uses extended counting technique [73] to enhance the resolu- tion of a 2A converter. Let k be the number of cycles required by the extended conversion to reach a preassigned state. Therefore, the digital output of an extended conversion is given by k D; = Z d*[i] (3.7) i=1 Therefore, the input signal a: is represented by combining the digital outputs obtained from the synchronous and the asynchronous conversion of the hysteretic 2A converter. There- fore, the digital output of signal :1: is given by 1 N—l 1 k a: = N Z; d[z] + Next gal [7] (3.8) 40 The digital output D N in Eqn. (3.6) is correlated with digital outputs at previous clock cycles and is controlled by the hysteresis level A of a comparator as shown in Fig. 3.2. Fig. 3.4 shows the working principle of a hysteretic 2A converter. During the synchronous Integrator plot Sigmafdelta conhersion cylcles {Extendéd counting cycles 4 ‘ ‘ o 1 -. - -- - :‘f. . --- -- '- ----- -- --- 1.. -~- --- .- --I-I- ----- -'- -a -- -'-~ -- I r . . . . 0 l rm i ' l , , [Wn]:Residues left after ,. : i . , sig 2 : 0.05_...'.l-y” . . t“. . ............ ......... ........... q Integrator output 0 -o.os - « * "1 : E X2 1“ p +X3 —o-1 -~-----------‘ ----.-..---. H‘bééfifibfl . --------Io.-- X4 ; ; . . ; + X5 1 l l L V l 200 400 600 800 1 000 1 200 1 400 1 600 Clock cycles Figure 3.4. Illustration of compensation steps for the semi-synchronous hysteretic 2A conversion. The residue at the end of synchronous conversion is discharged (charged) with a reference current up to a fixed potential A to get extended bits. conversion, the hysteresis level A is set to 0.1. The equivalent digital output from the synchronous conversion is obtained after N = 1024 cycles. The residue left on the in- tegrator Wn = H N is proportional to the input signal 22,-. The asynchronous conversion is performed with Eqn. (3.7) to enhance the resolution of a 2A converter. In the extended conversion, input :3 is disconnected and the converter is run till Wn reaches a a preassigned value of 0.1. The additional bits obtained from the extended counting method improves the resolution of a hysteretic 23A converter. The benefits of using a hysteretic 2A converter are shown with the hardware results in chapter 7. 41 CHAPTER 4 The Spatiotemporal EA Learner (STL) Algorithm Chapter 2 has shown the framework for a non-interacting multichannel 2A converter. In chapter 2, a function f (w) of internal states to of the multichannel 2A converter system is minimized such that the energy of the internal states 212 of the multichannel 2A system is reduced. It should be noted that the system is in the most stable state when the energy state of the system is minimum. All channels in the multichannel 2A converter system act as a separate unit and process the data at each channel independently. Therefore, any common mode signal is represented through multiple channels. The common mode signals increase the signal correlation among signals which in turn increase the output data redundancy of the multichannel EA converter. The signals generated by the high density micro-electrodes and microphone arrays show significant amount of correlation which appear as a common mode signal across all channels. Therefore, in order to decrease the data redundancy, signals need to be de- correlated before they are digitized. In order to de-correlate signals, a function f (w) given in chapter 2 is modified such that the energy of the internal state to is minimized and the de—correlation of signals is maximized. This is achieved by transforming the signals before digitization. The modified function f (w, A) needs to be optimized with respect to the inter- nal state w and the signal transformation coefficients A. The aim of optimizing the function 42 f (w, A) is to reduce the energy of the internal states 21) of the multichannel EA converter and to increase the signal de-correlation with the help of signal transformation function A. Similar to the minimization of f (w), the gradient steps taken to optimize function f (w, A) lead to the STL system. In the next section, the theory and the algorithm of an optimization framework that lead to the STL system are shown. 4.1 Regularization Theory of Spatiotemporal Learner (STL) System For a M dimensional STL 23A learner, the input is a M dimensional vector x 6 RM where each dimension represents a single channel in the multi-channel array. It is also assumed that the vector x is stationary with respect to the discrete time instances N which is a valid assumption for an over-sampling data converter. The validity and limitation of this assumption is explained in chapter 2. Also denote a linear transformation matrix A 6 RM XM and a regression weight vector w 6 RM . Consider the following optimization problem glee-623111511 f (w, A)) (4.1) where f(w, A) = |w|T1 — WTAX (4.2) and 1 represents a column vector whose elements are unity. The cost function in Eqn. (4.2) consists of two factors: the first factor is an L1 regularizer which constrains the norm of the vector w and the second factor that maximizes the correlation between vector w and the input vector x transformed using a linear projection denoted by matrix A. The choice of L1 norm and the form of cost function in Eqn. (4.2) will become clear when the corresponding gradient update rule is presented. To ensure that the optimization problem in Eqn. (4.1) is well defined, the norm of the input vector ||x||c>0 g 1 will be assumed to be bounded. The closed form solution to the optimization problem in Eqn. (4.1) is found to be w* = O as 43 shown in Fig. 2.8. From the perspective of analog to digital conversion, the iterative steps leading towards the solution of the optimization problem in Eqn. (4.1) are more important than the final solution itself. Given an initial estimate of the state vector w[0] the online gradient descent step for minimizing the Eqn. 4.1 at iteration N is given by Wm] = w[N _ 11 _ ngwf. (N I) (4.3) where r) > 0 is defined as the learning rate. The choice of L1 norm in the optimization function in Eqn. (4.1) ensures that for 2) > 0, the iteration Eqn. (4.3) exhibits an oscillatory behavior around the solution w*. Combining Eqn. (4.3) with Eqn. (4.2), the recursion Eqn. (4.4) is obtained as follows: w[N] = w[N — 11 + 27(Ax — d[N]) (4.4) where d[N] = sgn(w[N — 11) (4.5) and sgn(w) denotes an element—wise signurn operation such that d[N] E {+1, —1}M rep- resents a digital time-series. Iterations in Eqn. (4.3) represents the recursion step for M first-order 23A converters [72] where inputs :1: are transformed by the linear transform A. If A is a identity matrix then the recursion in Eqn. (4.4) represents a multichannel EA converter arranged in parallel channels as shown in Fig. 2.9 in chapter 2. In the given architecture, every single channel from the multichannel 2A converter system has inde- pendent dedicated input. If we assume that the norm of matrix ||A||oo S 1 is bounded, it can be shown that llwooll < 1 + r). \Vrth such a linear matrix A, the multichannel 2A con- verter system would be of the form shown in Fig. 4.1 such that consistent with the theory of 2A conversion [72], the moving average of the digital output vector sequence D[N] con- verges to the transformed input vector y = Ax as the number of update steps N increases. Following the update steps N, the recursion given by the Eqn. (4.4) yields 1 N 1 y —- N )3 din] -—— n—N(wlNl — wt)» (46) 12:1 44 Figure 4.1. Mathematical model of the STL system N Ax— 1%,ng = n—fiv-(wiNi —w(01) (4.7) By using the bounded property of w, Eqn. (4.7) asymptotically leads to 1 N N n; d[n] —+ Ax (4.8) as N ——> 00. 4.2 Online Adaptation and Compression The next step is to determine the form of matrix A which denotes the family of linear transformations spanning the signal space. The aim of optimizing for A is to find a multi- channel signal configuration that is maximally separated from each other. For this purpose, one channel or dimension is denoted as a reference dimension relative to which all dis- tances/correlations are measured. This is unlike the scenario for independent component analysis (ICA) [75] where the objective is to search for a maximally independent signal space including the reference channel. Even though several forms of matrix A = [aij] can be chosen, in this particular case, the matrix A is chosen to be a lower triangular matrix such that aij = 0;2' < j and (1,5 2 1;i = j. Thus, the first channel is unaffected by the proposed transform A and will be used as a reference channel. Therefore, the signal com— pression or the redundancy elimination is to optimize the cross-elements aij such that the 45 cross-correlation terms in the optimization function (Eqn. (4.1)) are minimized. This can be written as a min-max optimization criterion where one of the operations performs the analog to digital conversion, where as the other operation adapts the linear transformation matrix A so as to maximize the margin of separation in the respective signal space. This is denoted by the following equation: max (min f (w, A)) (4.9) aijiiéj w In conjunction with the gradient descent steps in Eqn. (4.4), the update rule for the elements of A follows a gradient ascent step given by 61,-j [n] = a1]- [n — 1] — {ui[n.]$j;V2 > 3' (4.10) where g is a learning rate parameter. The update rule in Eqn. (4.10) can be made amenable to digital hardware implementation by considering only the sign of the regression vector w[n] and the input vector x as aiflrV] = aij [N — 1] — {di[1’\"].sgn(xj);\7’i > j. (4.11) The update rule in Eqn. (4.11) bears a strong resemblance to online update rules used in independent component analysis (ICA) [75, 77]. The difference with the presented technique however is the integrated data conversion coupled with spatial de-correlation and signal compression. The output of the STL is a digital stream whose pulse density is proportional to the transformed input data vector as 1 N N Z d[n] _. A[n]x (4.12) n=1 By construction, the STL produces a digital stream whose pulse—density contains only a non-redundant information. To achieve the compression, some of the digital channels can be discarded based on their relative energy criterion and can also be shut down to save power. The power savings of the system is not discussed in this dissertation but is left 46 for the future directions of this research. The original signals are reconstructed from the compressed digital stream by applying an inverse transformation A‘1 as 1 N e = NAM—R: d[n1). (4.13) n=1 The advantage of using a lower triangular form for the linear transformation matrix A with its diagonal elements as unity, is the existence of a well defined matrix inverse. Therefore, the signal reconstruction using the multichannel 23A converter output is also always well defined. Since the transformation matrix A is being updated continuously, the information related to the linear transform also needs to be periodically transmitted to ensure faithful reconstruction. However, in many naturally occurring signals, the underlying statistics of multi-dimensional signals change slowly as compared to the signals themselves. Therefore, the transmission of a matrix A needs to be performed at a relatively slower rate than the transmission rate of the input signals. Similar to the conventional EA conversion [72], the framework for the STL can be extended to time-varying input vector under the assumption of a high oversampling crite- rion [72]. For the STL, the oversampling ratio (OSR) is defined by the ratio of the update frequency f3 to the maximum Nyquist rate amongst all elements of the input signal vec- tor x[n]. The resolution of a STL is determined by the OSR as log2(OS’R). During the oversampling period the input signal vector can be assumed to be approximately stationary. For time-varying input vector x[n] = {my-[12]}, j = 1, .., M the matrix update equation in Eqn. (4.11) can be generalized after N steps as N 1 1 . . j—V-az-j [N] = {N E di[n]sgn(:1:j[n]);V2 > ]. (4.14) n=1 Thus if the norm of the matrix A is bounded under asymptotic condition N —> 00, then the Eqn. (4.14) implies the decrease in cross-channel correlation between the digital output and the sign of the input signal. This is similar to a de-correlation framework in ICA where the higher-order correlations are generated using a non—linear mapping of random variables [75]. 47 In the following subsections 4.3 - 4.5, the mathematical model of the STL architecture for a 2-dimensional system is shown. All the assumptions and necessary conditions used for the 2—dimensional system are valid for M -dimensional STL system. Therefore, based on the 2-dimensional model, a generalized expressions for the M dimensional STL system are given. The STL system is shown employing the first order 2A converter. It is also shown that the STL system can be implemented with the higher order 2A converters and the novel hysteretic 2A converter. The expressions for the digital data representation and the conditions for the signal de-correlation are given for the 2-dimensional system. The expressions for the M -dimensional STL system are stated by extrapolating the the 2-dimensional model. The complete derivations for the M -dimensional system are given in A. For deriving the 2-dimensional S TL architecture, the minimization function given by the Eqn. (4.1) is written as f = |w|T.1 — wAcc (4-15) where the 2-dimensional linear transform matrix A is of the form A=(a11 0 ) (4.16) 0'21 a22 Input signal a: and the internal state 21) are given as a: = ( (1:1 ) and “”2 (4.17) w=('w1 2122) For the 2-dimensional system, the function f in Eqn. (A6) is simplified and written as f = lel + |wg| — (201231 + (121212221 + 211222) (4.18) 4.3 First Order Spatiotemporal EA Learner (STL) system The min-max optimization criterion given in the Eqn. (4.9) shows that the inner optimiza- tion performs the analog to digital conversion (proved in Chapter 2), where as the outer 48 Figure 4.2. First order STL system that consists of the first order 2A converter array and the first order adaptation module loop adapts the linear transformation matrix A so as to maximize the margin of separation between respective signal space. A first order STL system is shown in Fig. 4.2 where the inner optimization is performed by the first order 2A converter. The adaptation of a linear transform matrix A is performed using the gradient ascent nrle whereas the internal state 21) is updated using the gradient descent rule under the first order approximation in an optimization framework. Therefore, the internal state 211 is given by 4017.1 = w[n— 11— %( _1) (4.19) The 2-dimensional first order STL system is shown in Fig. 4.3. The states wl and 202 are given by the Eqn. (4.20) and Eqn. (4.21) respectively. The Eqn (4.20) is a first order EA converter equation where the input is yl and the output is d1. Eqn (4.21) is also a first order EA converter equation where the input y2 is a linear transformation of inputs 2:1 and $2. w1[ri] = w1[n — 1] — (d1[n —— 1] — 3:1[71 — 1]) (4.20) w2[n] = w2[n — 1] — (d2[n — 1] - a21[n — 1]21[n — 1] — $2[n — 1]) (4.21) 49 d2[n] EA ADC Channel I d1[n] Figure 4.3. Mathematical model of the 2-dimensional first order STL system The transformed signals m and y2 are shown in Fig. 4.3 and are given by 1111”] = 0511”] (4.22) 312 [71] = 0211711501171] + 162171] (4.23) The gradient ascent steps are taken to update the elements of a linear transformation matrix A so as to maximize the de—correlation between two input channels :31 and $2. The gradient ascent steps for the update of the elements of A are given by aiflN] = (113-[N — 1] + kg- 3043‘ (4.24) (N -1) For the 2-dimensional system, the closed form output of the non-diagonal element (121 of a linear transform matrix A following the recursion Eqn. (4.24) is given by N —2 0.2111), — 11 = — Z §d21i1sgn(e1[i]) (4.25) 2: As N —+ co, the recursion (Eqn. (4.21)) of the first order 2A converter gives N N i~1 N 2322121 — 52326121 2 d2U]sgn(x1 hi) = Z 4218 (4.26) i=0 '=0 j=0 i=0 The 2-dimensional STL architecture is extended to an M -dimensional STL architecture with all valid assumptions and initial conditions of the 2-dimensional STL system. For an 50 M -dirnensional STL system, the linear transformation matrix is of the form all 0 . . 0 A : £121 (122 . . 0 (4.27) arml am2 . . amm The M -dimensional inputs :1: and the internal states to of the STL system are given by ( j: ) a: = . and K , } (4.28) 13m w = ( 2111 202 . . wm ) Therefore, for an M -dimensional system, the Eqn. (4.26) is extended to a generalized form as shown below. N m—l N i—l N Ewen—£2: Zeb] 24(31ngan =delzi (4.29) i=0 1:1 2:0 j=0 i=0 Let the expected value of signal sum over N cycles be N arm) = meh] 220 therefore, the Eqn. (4.29) is simplified as m—l —§=: 5(711)azm=zdmlil (4.30) i=0 where am is the non-diagonal element of a linear transformation matrix A. The coefficient alm is given by —-1 =5 2 dmLilsgnCrrLil) (4.31) '20 Since dm [2] 6 {+1, —1}, the signal mm is said to be de-correlated from the rest of the lower dimensional (m. —- 1) channels when 221:0 dm [2'] = 0. Therefore, the de-correlation condition is given by E(a:m)= Z E(:r:l) a)”, (4.32) 51 The Eqn. (4.32) shows that the signal mm is completely represented by the lower dimen- sional digital data outputs d1 ..... dm_1 of the M -dimensional STL system when the signal CL‘m is completely completely correlated with the lower dimensional M — 1 signals. There- fore, the Eqn. (4.30) gives the digital output rim of the non-redundant signal information of the signal at the M th channel. 4.4 Second order Spatiotemporal 2A Learner (STL) system The first order STL architecture shown in the section 4.3 can be extended to a higher order system. A second order STL system is shown in Fig. 4.4 that employs the sec- ond order 2A converter framework. The ruin-max function in Eqn. (4.9) is optimized using the Eqn. (4.15). For the 2-dimensional STL architecture, the function f is given by Eqn. (4.18). In the second order STL system, the internal state (D[N] of the STL system is updated with a second order approximation of the gradient descent rule. Therefore, the general form of w[n] is given by (D[N] = ”(r-'[N — 1] — 31]; (N 1) + w[N — 1] — w[N — 2] (4.33) For the 2-dimensional STL system, the states ml and 202 are given by Eqn. (4.34) and Eqn. (4.35) respectively. Eqn. (4.34) is a second order 2A converter where the output d1 is the output of the second order 2A converter output and the input is 2:1. Eqn. (4.35) is a second order 2A converter equation where the output d2 tracks the input which is a linear transformation of input signals 2:1 and .232. For the 2—dimensional STL system, the input signal transformations are given by Eqn. (4.22) and Eqn. (4.23). 2111 [N] = w1[N — 11 — (d1 [N — 11— x1[N — 11) + 2111 [N — 11 — 2U2[N — 21 (4.34) with = new —11—(42(N — 11— (a211N — 1m (N - 11+ :an - 11)) (4.35) +2131 [N — 1] — w2[N — 2] The update rule for the elements of linear transformation matrix follows the gradient ascent steps. The adaptation of the linear transformation matrix A can also be done using the first 52 Figure 4.4. Second order STL system that consists of the second order 2A converter array and the second order adaptation module order approximation as given in Eqn. (4.24) but it would be slower compared to the second order update of the internal state 21). Therefore, to improve the adaptation speed of the linear transformation, a second order update is applied. The gradient ascent steps of adaptation with second order approximation for the element (61,-j) of the linear transformation matrix A is given by aiflN] = (113-[N — 1] + 165% (N )+ aiflN —- 1] -— 02'le — 2] (4.36) 1 —1 For the 2-dimensional system, the closed form output of the non diagonal element (121 of the linear transformation matrix A following the recursion Eqn. (4.36) is given by N i—l 021 [N 1 = —E Z Z d2U139n($1171) (4-37) i=0 j=0 As N -r 00, the second order EA recursion Eqn. (4.35) after substituting the value of a21 gives N-l N—l 2—1 j-l [v-1 2 r2121 -6 Z 41111 Z Zdzlkisgnmlki) = Z 012111 (4.38) i=0 i=0 j=0 k=0 ' 2:0 53 d2[n] EA ADC Channel 1_ d1[n] Figure 4.5. Mathematical model of 2-dimensional second order STL system Like the first order STL system, the 2-dimensional second order STL architecture is ex- tended to the M -dimensiona1 architecture. For the M dimensional STL system, the linear transformation matrix A is given by Eqn. (4.27). The M—dimensional input signal vec- tor and the internal state vector of the STL system are given by Eqn. (4.28). Therefore, Eqn. (4.38) is extended to an M -dimensional second order STL system whose general form is given by N—1 m—l N—l i—l j—l N—l 2 22mm — 6 Z Z xiii] Z Z dmikisgnmlki) = Z danlil (439) 2:0 l=1 i=0 j =0 12:0 i=0 Let the expected value of signal 22m over N cycles be N E(:rm) = Z :cm[2'] i=0 therefore, the Eqn. (4.39) is simplified as m—l N Eon.) — Z Eonazm = 2412'] (4.40) l=1 i=0 where am is the non-diagonal element of a linear transformation matrix. Element aim of the linear transformation matrix A is given by N—lj—l arm =6 2 Z dmlkisgnmlki) (4.41) j=0 k=0 54 Since dm[2'] 6 {+1, —-1}, the signal mm is said to be de-correlated from the rest of the lower dimensional (M — 1) channels when 2&0 dm [2] = 0. The Eqn. (4.40) gives the digital output dm that represents the non-redundant or un-correlated signal in am. If the input signal mm is completely correlated with the lower dimensional (M — 1) signal, then the right hand side of Eqn. (4.40) goes to zero. Therefore, the de-correlation condition for the signal at channel M from the rest of the lower dimensional (M - 1) signals is obtained when m—l E(a:m) = Z E(:r:))alm (4.42) l =1 is satisfied. It should be noted that the de-correlation condition given by Eqn. (4.42) is the same as the one given by the first order STL system in Eqn. (4.32) but the update rule for the non-diagonal elements of a linear transform matrix A changes the performance of the second order 8 TL system as will be seen in chapter 6.1. 4.5 Hysteretic Spatiotemporal 23A Learner (STL) system In this section it is shown that the first order STL architecture shown in section 4.3 is extended to the novel hysteretic 2A converter. The recursion equation of the hysteretic first order 2A converter is given by w[N] = w[N — 1] + E (Ax — d[N]) (4.43) and d[N] 2' sgn(w[N -— 1] + d[N — 1]A) (4.44) where A is a hysteresis level of a comparator. The hysteretic STL system is shown in Fig. 4.6 that uses the hysteretic 23A converter. In the hysteretic STL system, the internal state w[N] of a STL system is updated using the gradient descent rule that makes use of hysteresis in updating the value of w[N]. By 55 adding the hysteresis in the update rule, the general form of w[N] is given by w[N] = w[N — 1] — gig (N—1)+ A(sgn(2u[N — 1]) — sgn(w[N — 2])) (4.45) where A(sgn(w[N -— 1]) - sgn(w[N —- 2])) is the hysteretic term added to update w[N]. The min-max function in Eqn. (4.9) is optimized using Eqn. (4.15). For the 2- dimensional STL system, Eqn. (4.18) defines the function f for the hysteretic STL system. For the 2-dimensional hysteretic STL system ,the states ml and 2122 at any instance N are given by Eqn. (4.46) and Eqn. (4.47) respectively. 211M = as (N — 11 — (41 (N — 11 — $1 (N — 11) (4 46) + Asgn(-wl [N — 1]) — Asgri(2ul [N — 2]) 1021M = ”412 [N - 1] - (d2 [N - 1] - (a2ilN - 11501 [N - 1] + leN - 1])) (4.47) + Asgn(2u2 [N — 1]) — Asgn(w2[N — 2]) Eqn. (4.46) is a recursion of a hysteretic EA converter where the output 611 represents the input signal 11:1. Eqn. (4.47) is also a recursion equation of a hysteretic EA converter where the output d2 represents the signal which is a linear transformation of input signals 2:1 and 11:2. For the 2-dimensional system, the signal transformations are given by Eqn. (4.22) and Eqn. (4.23). The update rule for the elements of a linear transform matrix A follows the gradient ascent steps as given by the first order STL system. But to improve the speed of adaptation, the adaptation of a linear transformation matrix A is done by the first order hysteretic approximation as given in Eqn. (4.48). The gradient ascent steps for updating the elements (aij) of a linear transformation matrix A using the hysteretic approximation at any instance N is given by 8 Gig-[1V] = a,j[N — 1] + k—f Bar]- + A(aiJW " 11 ‘ aiJ'1N - 2]) (4.48) (N -1) Therefore, for a 2-dimensional system, the closed form output of the non-diagonal element (221 of a linear transformation matrix A following the recursion Eqn. (4.48) is given by N—1 N—l 2—1 am [N] = —£ 2 d2[2']sgn(:r:1[i]) —€ 2 AN"i :d2[j]sgn(:1:1[j]) (4.49) 2:0 2:0 j=0 56 Figure 4.6. Hysteretic STL system that consists of hysteretic EA converter array with hysteretic adaptation module As N —> co, the recursion of the hysteretic EA converter (Eqn. (4.47)) after substituting the value of £1.21 from Eqn. (4.49) gives N—i N—1 Z (1211] = Z 932111 2:0 2:0 N—l i—r . _j-1 (4.50) -E Z xiii Z (121713974161 1.71) + AF] 2 d2lk189n($1lkl) i=0 j=0 2:0 The 2—dimensional hysteretic STL system is extended to an M -dimensional hysteretic STL system. For an M -dimensional STL system, the linear transformation matrix A is given by Eqn. (4.27). The m-dimensional input signal vector and the internal state vector of ST L system are given by Eqn. (4.28). The 2-dimensional balanced Eqn. (4.50) is ex- tended for an M -dimensional system that gives the M -dimensional balanced equation as 57 shown below N —1 N —1 2 22,121 .-= Z r... [2'] 2:0 2:0 m—l N—l i—l j—l (4'51) -—€ 2 Z 42121 E: dmLilnglei’l) + AM 2 imitcisgnmiki) 1:1 2:0 j=0 k=0 Let the expected value of signal 5cm over N cycles be N E(:rm) = 2: cm 111 2:0 therefore, the Eqn. (4.51) is simplified as m—l N E(.2:m) — 2 Demo)", = 22,421 (4.52) [21 i=0 where am, the non-diagonal element of a linear transformation matrix A, is given by 2—1 . .j -1 arm = t Z dmtilsgnccrlii) + A"? Z dmlkisgnmlkl) (4.53) j=0 k=0 The Eqn. (4.52) gives the digital output dm that represents the non-redundant or un- correlated signal of channel M. If the input signal mm is completely correlated with the lower dimensional (M — 1) signals, then the average of 211:0 d,n[2'] in Eqn. (4.52) goes to zero and the signal at M1th channel is completely represented by the lower dimensional dig- ital data outputs d1 ..... dm_1 of the M-dimensional hysteretic STL system thus eliminating the redundant signal information from the M th channel. Therefore, the de-correlation con- dition of the M th signal from the rest of the lower dimensional (M - 1) signals is obtained when m—l E(a:m) = Z E(:cl)a)m (4.54) 1 =1 is satisfied. It should be noted here that the hysteretic STL system can be made to work as a first order STL system when hysteresis level (A = O). This is evident equation as when (A = 0), the de—correlation equations Eqn. (4.51), Eqn. (4.52) and the update rule for linear transformation Eqn. (4.53) matches with those given by Eqn. (4.29), Eqn. (4.30) and Eqn. (4.31) of a first order STL system respectively. 58 4.6 Higher-order Spatiotemporal EA Learner System The convergence of the stochastic gradient step in Eqn. (4.3) can be improved by adding the momentum terms according to 8f(w, A) w[ ] w[ ] + 6w N-1 (4.55) +MN—H—wW—fl w[N] =w[N — 1] + (A[N — l]x[N — 1] — /\d[N]) (4.56) +MN—H—wW—fl Momentum terms have extensively been used in optimization theory and neural net- works for improving the convergence speed of the learning algorithms [22, 74]. Even though Hessian-based formulations have also been proposed for improving the perfor- mance of neural network algorithms, they are not suitable for optimizing piece-wise cost function Eqn. (4.1). Recursion Eqn. (4.56) will generate the quantized vector sequences d[N] whose first order expectation as well as second order expectation converge asymptot- ically according to SMfihh §&JAM#MB ash &d&JMMH-= §&dAMkmn. use The proof of convergence for the expressions Eqn. (4.57 — 4.58) is given in appendix A. The update in Eqn. (4.56) is equivalent to the second-order EA modulator [72], thus linking the momentum based gradient descent steps to a second-order EA modulation. Similar to the Eqn. (4.13), the reconstruction formula based on Eqn. (4.58) is expressed in terms of asymptotic value of the linear transform A00 as 811817?” m AA;01£n{£n{d[n]}} (4-59) 59 -_ NJ..- -- 2 w t 3 I w t (a) (D) f f ’7 / V I W t w w : l (C) (d) Figure 4.7. Illustration of EA dynamics for (a ) first-order modulator with :1: = 0, (b) modulator with :L' > 0, (c) higher-order modulators (bold lines indicate higher velocity), (d) efi‘ect of reducing the magnitude of ac Eqn. (4.55) is also generalized to incorporate the Lth order momentum terms according to w[N] = w[N — 11+ gig—M + ATI;(w[N — 11) (4.60) N—l where A,I;(.) denotes an L1th order difference. In case of L = 1, Eqn. (4.60) is equiva- lent to a second order modulation shown in Eqn. (4.55). Higher-order momentum terms have also been used in neural networks [76] to accelerate the dynamics of gradient descent iterations especially where the optimization contours are flat. The optimization approach using the momentum terms are also used to visualize and understand the dynamics of EA modulators. Fig. 4.7(a)-(d) illustrates this dynamics using the one-dimensional cost function f (w) = |2u| — tux with |x| < 1. Fig. 4.7(a) corresponds to a: = 0, therefore the stochastic gradient iterations corresponding to the first-order EA modulation exhibits limit cycles symmetri- cal about the minima w = 0. Fig. 4.7(b) shows the equivalent dynamics corresponding to x > 0, therefore the resulting limit cycles spend more time in the region w > 0. fig. 4.7(c) shows the dynamics of the higher-order modulator, where the momentum factor accelerates the marker towards the minima. The overshoot beyond the minima is proportional to the net velocity at the minima. For higher-order modulators, the acceleration and hence the ve- 60 locity of approach could be large enough so that the magnitude of lirrrit cycles can become unbounded. Therefore, similar to several proposed solutions to improve the stability of the higher—order EA modulators [72], either the magnitude of the state variable 21) needs to be constrained, which implies reducing the velocity of approach towards the rrrinima or the slope of the optimization function be reduced by constraining the magnitude of the input 2:. In this chapter, the theory of the spatiotemporal EA learner is presented. The next chapter shows the simulation results of the algorithm tested under various performance pa- rameters. The simulation results show that the algorithm of the spatiotemporal EA learner works with higher order modulators. The algorithm is shown to be self adaptive and there- fore proves its robustness to hardware artifacts. 61 CHAPTER 5 Simulation and Verification Results of the Spatiotemporal EA Learner (STL) Algorithm In this chapter, the STL algorithm is verified with the help of system level simulations. These simulations help in designing the realistic circuit level architecture for the S TL sys- tem. The hardware realization takes into account various factors that affect the STL system performance. For example, the device mismatch of the system components introduces the offsets across the channels where as the system level factors like the oversampling ratio (OSR) of the EA converter changes the signal to noise ratio (SN R) of the STL system. In this chapter, the robustness of the STL system is verified with the help of mathematical model that takes into account various system level as well as hardware component level factors. The various factors that are considered for the system evaluation are obtained from the reported literature and through expected signal properties. The data samples used for the tests emulate the signals of the high density sensor arrays. The worst case parametric conditions of the hardware artifacts such as mismatch, offsets, leakage and the non-linearity are obtained from the previously published literature. The mathematical models developed in chapter 4 are simulated in M ATLAB. In this chapter, the parametric simulation results are presented for the first order and the second order 3 TL systems. 62 (a) Input Signals (b) System Output ANwhmmflm Channel 0 A N o: J:- 01 O) ‘1 CD Channel 1000 2000 0 1000 500 1000 1500 2000 Samples Samples (c) Reconstructed Signal (d) Adaptation O 0.25 IIAII WM 0.2 ,( Channel ANOD-bO'IODNm W 0.15’ WWW . r 1 0.1 . . 500 1000 1500 2000 0 2 4 Samples Samples x 105 D Figure 5.1. Functional verification of the first order STL system using artificially generated multi- channel data: (a) Analog input signals presented to the 8-dimensional STL system (b) The digital output data representing the transformed input signals (c) The reconstructed signals using the digi- tal output data and the signal transformation coefficient obtained from matrix A of the STL system (d) Adaptation of the STL system is shown by N orm(A) that converges to a stable value after learning the signal statistics 5.1 Behavioral Simulations of the STL System Fig. 5.1 shows the working principle of an 8-channel first order STL system. Fig. 5.1(a) shows the input signals of the STL system. For clarity of the STL algorithm, only 2 fun- damental signals (Channel 1 and 2) are used. They are randomly mixed to generate 8 input signal vector such that rest of the 6 channels (Channel 3-8) are correlated with fundamental signals at channel 1 and 2. It can be seen in Fig. 5.1(b) that after initial adaptation pe- riod, the output streams of the STL system at channels 1 and 2 represent the equivalent digital data corresponding to fundamental signals present at channels 1 and 2. The corre- 63 (a) Input Signals (b) System Output WWW WWW/“WM! Channel awwbmmuoo Channel ANOJ-RUIQNQ WNW/WW MNWVWNVVWNNWV 500 1000 1500 2000 500 1000 1500 2000 Samples Samples (c) Reconstructed Signal (d) Adaptation O O 0.25 WWW/WWW 0.2 , WNW/WWW f h MMWNMMMMMMMW 0.15* Channel IIAII ANOO-hU'lCDNm WWWWWWWWWWWVW * 0.1 500 1000 15100 2000 0 a £1 Samples Samples x 105 0 Figure 5.2. Functional verification of the second order STL system using artificially generated multi-channel data: (a) Analog input signals presented to the 8-dimensional STL system (b) The digital output data representing the transformed input signals (c) The reconstructed signals using the digital output data and the signal transformation coefficient obtained from matrix A of the STL system (d) Adaptation of the STL system is shown by N orm(A) that converges to a stable value after learning the signal statistics lated signals from the rest of the 6 channels (3-8) are removed and they are represented by the digital output streams showing the decrease in the residual energy. The adaptation of a linear transformation matrix A is shown by norm(A) in Fig. 5.1(d) where the adap- tation period is defined as the number of cycles required by N orm(A) to lie within :l:2% of its stabilized value. This simple experiment demonstrates the functionality of STL sys- tem that de-correlates the input signals and eliminates the cross-channel redundancy from the output digital data. The STL system also removes any common mode signal present across all channels. Fig. 5.1(c) shows that the STL system reconstructs the original signals by using the digital output data streams of the fundamental channels of the STL system and the linear transformation matrix as given in Eqn. (4.13). The STL system therefore reduces the digital output data bandwidth. This reduction in the output digital data band- width effectively reduce the power dissipation of the data processing and the transmission. In chapter 4, the STL system is shown to work with higher order 2A converter. Fig. 5.2 shows the simulation results of the second order STL system that employs the second or- der EA converter array. Like the first order STL system, the second order STL system performs the signal de-correlation and eliminates the output data redundancy. The second order STL system in Fig. 5.2 shows that the STL system algorithm is robust to accommo- date higher order EA modulators. The signal de-correlation performed by the system is also be seen by observing the fre- quency response of the system at individual channels. The frequency responses of the 4 channels (14) of the second order system are shown in Fig. 5.3. In this experiment, two sinusoidal signals with distinct normalized frequencies are chosen. These signals are then mixed together in random linear proportions to generate synthetic signals. Fig. 5.3(a)-(d) shows the input signals presented of the 4—channels of the STL system. For the given ex- ample, even though the dimensionality of the input signals is 4, the rank of the input signal space is 2. Plots in Fig. 5.3 (e)-(h) show the FFT responses of the output of all 4 chan- nels. The output plots show that the STL system correctly reduces the dimensionality of the output signals, where the signal power of the first two channels (1 and 2) is retained as shown in Fig. 5.3(e) and (f) whereas the power of the rest of the channels (Fig. 5.3(g) and (h)) reduces by approximately 60dB. Thus, this reduction in the signal power of redun- dant channels shows the signal de-correlation performed by the STL system. The signal are reconstructed like they are shown in Fig. 5.2(d) with the help of stabilized and con- verged de-mixing matrix A00 and the outputs of the STL system. The FFT plot of the reconstructed signals are shown in Fig. 5.3(e)-(h) which shows that the there are no har- monics seen in the reconstructed plots. This experiment shows that the operation of signal 65 Figure 5.3. Functional verification of the STL system using synthetic multi-channel data: Plots (a)-(d) show the FFT of the 4 input signals presented to the 4-dimensional learner: (c) and (d) are the mixture of signal shown in (a) and (b). Plots (e)-(h) show the FFT of the output data. The output plots (g) and (h) show that the redundancy in channel 3 and 4 is removed by the learner system Plots ( i H 1) show the reconstructed signals from the un-correlated output data ( e)-( h) and the transformation coefi'icients of A. The reconstructed plots show that the signal trang'ormation is a linear process. reconstruction is linear process. The reconstructed signals are verified with the help of mean square error (M SE). M SE is defined as the square of the difference between the input signal and the recon- structed signal. M SE shows how good the signal reconstruction is done by the STL system. Fig. 5.4(a) and (b) show the M SE of the first and the second order STL system. As seen in both plots, the M SE gradually decreases with increase in the number of sam- ples. This decrease in the M SE is seen due to gradually improved learning and online adaptation of signal transformation matrix A. The improvement in the learning is seen by the decaying M S E in Fig. 5.4. The higher order 23A converter improves the signal to noise 66 (a) (b) o" ......... —e— Order = 1,0SR = 32 0.. ,,,,,,,,, —e— Order = 2,0SR = 32 .l —e— Order = 1,0SR = 64 l, —e—Order = 2,0SR = 64 A _10)“ .. —>— Order =1.OSR =128 A _1l“ ,,,,,,,, —>—Order = 2,0SR =128 a l\ ——r— Order = 1,0SR = 256 g; klfi —r— Order = 2,0SR = 256 2-20 ............. ' ....... _ 2-20 . t‘ ..................... ........ a) 0 ° 93 h ‘::::::::::::::::=::=:a 2 ' 0 “0 ‘3 ‘30 ,55'3":::::::::::::::::::::¢:o ‘3 '30 " g " ° 3 8 .. fl 2 """ C C sin:::::::::::::::::::::::::: 8 _40. _. 8 -40? ................................................ 2 2 ::::::::::::::::::::::::::::::> -50 - -50 ............................................... . 0 500 1000 1 500 0 500 1000 1 500 Moving window samples Moving window samples Figure 5.4. The signal reconstruction accuracy of STL system is shown using the mean square error (MSE). The reduction in MSE implies better adaptation of the STL system by improved learning of signal statistics. S N R, therefore the M SE decreases with increase in the order of the 2A converter which is seen in Fig. 5.5. 5.2 Parametric Performance of the STL System In this section, the parametric performance of the STL system is shown. The STL system performs the signal de-correlation with the help of online learning technique and eliminates the output data redundancy. Therefore, the most important features that are considered for the performance evaluations are adaptation period, residual power left on the output data streams and the reconstruction error of the STL system. The residual power left on the output data streams indicates how well the data redundancy is removed by the STL system. The reconstruction error accounts for the accuracy of the EA converter of the STL system, the accuracy of adaptation and the precision of input signal transformation to make signals uncorrelated. 67 Moving average of mean square error 0 l T —e—Order=1 +Order=2 A_10()..._.... . .. ............ m E 8 t— _ .................................................................... _ a, 20 2 n (U “ 3 (I) _30- ................................................................ .. C “r. as «P m 0 E -40 ..... \, ............................................................... 1 \\¢===:==:=::===::::===::========3 ¢¢€::¢¢:::¢:¢:::¢:¢¢:¢:¢¢¢¢¢::¢9 _50 i L i 0 500 1000 1500 Moving window samples Figure 5.5. Increase in the order of the EA converter framework of the STL system decreases the reconstruction error which is attributed to the improved noise shaping of higher order 2A converter The STL system is evaluated based on factors that are classified into 3 categories namely the hardware resources, device artifacts and the dimensional statistics. The hard- ware resources are the system level factors such as the oversampling ratio (OSR), order of the 2A converter and the resolution of the signal transformation. The system level factors that affect the STL system performance are the over-sampling ratio (OS R) of the EA con- verter, the resolution of a linear transformation matrix A, and the order of a BA converter. Since the ultimate goal is to realize the STL system in hardware, it is imperative to consider the device artifacts of the hardware. The hardware factors that are of real concern are mis- match, offset, non-linearity, leakage and the noise. The quantization noise in the system is determined by the order of the EA converter that realize the STL framework. The inherent noise shaping associated with the order of the 2A converter (shown in Fig. 2.3) improves the signal to noise ratio SN R of the system in the signal band. This improvement in the 68 -20 --------------------- _ .............................. 800 A 10 8 A m T.) m -40 ......................... .3 6 z s E e c 600 '5 _ ........................... III a . - E '8 (U CU ._ .. .l 2 400% 80 g *5 '3 8 2. Ct -100 51'; 200 -120 3 0 i if -140 —60 i 0 1 00 200 0 0 1 00 200 OSR Figure 5.6. The ejfect of OSR of the 2A converter array on the performance of the STL system SNR comes at the cost of decreased modulator stability. Dimensional statistics plays an important role in the learning process which varies with the system dimension M and the total number of independent signals of the system. In the following subsections, the STL system is evaluated for various factors of all 3 categories. 5.2.1 Over-sampling Ratio (05' R) of the 2A Converter The simulated results of the STL system with change in the over-sampling ratio OSR of a 2A converter that forms the STL framework is shown in Fig. 5.6. The accuracy of the STL system depends on the resolution a 2A converter and the accuracy of a linear transformation matrix A. The dynamic range of the 2A converter is directly proportional to the over-sampling ratio (OSR) as shown in Eqn. (2.2). With increase in the OSR, the quantization noise is spread over a wider bandwidth, therefore the noise in the signal band is attenuated and the signal to noise ratio (SN R) is improved. The improvement in the SN R decreases the residual power left on the redundant channel outputs. As a 69 x10 . i 0 0 r 10 _10 ........................ .A-1ow % 3 3. . . i % -20 -- . g j T) t t _20 ............................. 8 (D -30 ........................... . LlJ c 6' ‘ g g A J .o a- _40 L d ._ -30 ........................... a _ '5 a s a _8 4 ' ' g (g .40 ........................... < 0 8 0: ‘ a) 2 t. . [K _50 ...... 4 0 i i -80 i i -60 i L 10 12 10 12 10 12 Transform Resolution Transform Resolution Transform Resolution Figure 5.7. The efiect of the resolution of a signal transformation matrix A on the performance of the S TL system result, the reconstruction error reduces and the precision of a signal reconstruction given by Eqn. (4.13) improves. For a given set of signals, the total number of clock cycles (N) required for the signal de-correlation and the adaptation are constant therefore with increase in the oversampling ratio (OS R) the number of adaptation cycles (AdaptationCycles = 0%?) decreases. 5.2.2 Resolution of the Signal Transformation Matrix A The update rule for the non diagonal element of a linear transform matrix A of the first order STL system is given by Eqn. (4.31). The learning rate of A is given by 6 which is a function of the resolution of a linear transformation matrix A. The resolution of a linear transform matrix decides the step size for the update rule given in Eqn. (4.31). Therefore, the number of adaptation cycles required by the first order STL system increases with increase in the the resolution of a linear transformation matrix A as shown in Fig. 5.7. The increase in the resolution improves the accuracy of the signal transformation. The improved accuracy of 70 9900 7 o : 0 y c i -20 .............. ...................... ......... 9800 A g 10 E a, m -40» -~ v g 32 3 '5 _. o .............. g .............. g a “'60 . .......................... l: 2 E o 9700 3 L: . .5 0C: ‘80 ..,_C_> -30 ............. E 9600 E S i a 3 -100~- '- *5 3 < m -120 ........................... 8 9500 (K -50 .............. § ............. _140CW . , G G r.) r 9400 i -160 i -60 i 0 0.1 0.2 O 0.1 0.2 0 0.1 0.2 Mismatch Factor Mismatch Factor Mismatch Factor Figure 5.8. The component mismatch effect on the performance of S TL system signal transformation decreases the residual power left on the redundant channels as well as the reconstruction error. 5.2.3 Component Mismatch and Offset The device artifacts can severely degrade the performance of the realized hardware. These artifacts are component mismatch, offsets, leakage and the component non-linearity. The component mismatches and offsets are found in SA converters and the elements of linear transform matrix A. Eqn. (4.31) shows that any component mismatch in the STL system directly affects the linear transformation matrix. Therefore, all component mismatches are lumped together with the update rule given by Eqn. (4.31) for the elements am, of a linear transformation matrix with a mismatch factor 6. Therefore, the update rule with mismatch factor 6 is given as N—l at... = 6 r2 dmlr'lsgn(lejl) + ,\ (5.1) j=0 71 c 9800 .. A a E8. 0 I. 5‘ 9600 g .6 a 3'3? '5 3 9400 - 3:5 2 % E . b . . 9000 ‘ ‘ ‘ 0 0.1 0.2 0 0.1 0.2 0 0.1 0.2 Leakage factor Leakage factor Leakage factor Figure 5.9. The effect of integrator leakage on the performance of STL system where /\ is the Offset in the component mismatch. The performance of the ST L system with mismatch is shown in Fig. 5.8. The number of adaptation cycles change with re- spect to mismatches along the column of the linear transformation matrix that performs the signal de-correlation operation given by Eqn. (4.29). The channel residual power and the reconstruction error show that the online system adaptation is robust to the component mismatch and the offsets. The residual power left on the channel varies by 1.5 % and the reconstruction error varies by 1.7 % when mismatches in the components are up to 20 %. 5.2.4 Integrator Leakage of the 2A Converter The S TL system algorithm is developed in a EA converter framework. The SA converters use capacitive elements to implement integrators that performs the recursion Eqn. (5.2). All electronic energy storing elements are associated with leakage. The increase in the leakage is associated with increase in the noise in the signal band therefore, the leakage degrades the signal to noise ratio (S N R) of the system. The performance of the STL system with respect to the integrator leakage is shown in Fig. 5.9. With leakage factor or, the recursion 72 Sigmoid Function Response —*—Beta =1 —v—Beta = 2 —e—Beta = 3 0.5 +Beta = 4 —9— Beta = 5 Sigmoid Function Output 0 0.5 1 Input Figure 5.10. The response of a sigmoid fiinction that is used to model the nonlinearity of STL system components of the first order 2A converter is written as w[N] = orw[N — 1] + :1:[N — 1] — d[N — 1] (5.2) Therefore, the input a: is represented by the first order EA converter as 1 a N—l V __ — Z ,- —'-1 a: — N i_1 d[r]orl ' (5.3) Using the first order 2A converter output with leakage a and the Eqn. (4.30), the digital output of the M th channel in the STL system is given as N m—l N 1 _ a (“it”) ‘ Z Ewan.) = Edmli] (5.4) i=0 l=1 where aim is given by the single summation function (Eqn. (4.31)) which is proportional to the input signal as; and the digital output dm of the M th channel. The adaptation is said to be done when the condition in Eqn. (5.4) is satisfied therefore, the total number of 73 x10 4 0 0 3.5 . E S a 3... _. z»: ‘2 a .g o. a e < 32 2 4 1.5 -160 -60 0 5 0 5 0 5 NonLinear Factor NonLinear Factor NonLinear Factor Figure 5.11. The non linear effects of used components on the performance of STL system adaptation cycles required decreases. The decimation filtering of the digital output the EA converter can not get rid off of the in band noise due to leakage factor a, so the residual power left on the channel increases with increase in the leakage a. The elements aim of the linear transformation matrix are updated by the digital output dm which tracks the leaky integrator output. Therefore, the accuracy of the update of a linear transformation matrix A using Eqn. (4.31) reduces. This reduction in the accuracy of the signal transformation with increase in the leakage a, increases the reconstruction error. These simulation results show that the integrator leakage needs to be reduced in the system by designing the high DC gain amplifiers. 5.2.5 Component Non-linearity of the STL System The component non-linearity of the system adds harmonics and therefore affects the sig- nal to noise ratio (S N R) of the system. In this simulation, the components of the signal transformation are assumed to have linearity poorer than that of the 2A converter used in the system therefore the non-linear effects of the signal transformation are considered. In 74 2.05X10 7 7 0 7 7 0 7 7 7 7 7 7 _10L .......... ............. 7... 2“ ~ '20" ‘ 8 2 a (D at; §_207. ........ ........... 1... 6 1’ -40+ g _ i i , C I I g, (E -60 . 3% -40 .......... ............ £9. .. .3 : : g 1.9 .5 - _. ‘ %_50 ........ 7_ ........... ..7..4 185 a: §-60 ..... ......L... - _100 ............................ 0: -70 .......... 7 ........... 7.... 1.8 i # -120 i 4 -80 . . 6 8 6 8 6 8 System Channels System Channels System Channels Figure 5.12. The effect of system dimension and signal statistics on the performance of STL system this setup, all components are directly linked with the elements of a linear transformation matrix A. Therefore, the non-linear effects of all components are lumped together with the elements of a linear transformation matrix A and is denoted by Beta(fi). Fig. 6.7 shows the simulation results of the non-linearity in the preliminary circuit design which is modeled as a sigmoid function which is given by 1 It is seen in Fig. 5.10 that the non-linearity of the sigmoid function increases with increase in the value of 6. Therefore, the STL system is evaluated by modeling the response of a linear transformation matrix as a sigmoid function. The update rule for the elements of a linear transformation matrix A of the first order STL system given by Eqn. (4.31) is now modified to N — 1 a... = e 2 dm msgnmun + A 1 j=0 1 + 8‘3 (5.6) The response of the STL system to non-linear factor [3 is shown in Fig. 5.11. The first order STL system implements Eqn. (4.30) where the element a)", is updated by using 75 1000 r r 0 0 a . ; —e—Order=1 ; 7 7. -20 —e—Order=2 w 800.. ' ‘ $-10 777777777777777777777 6 a ’40" “8 0 h '60 .......................... t c 600 d) LIJ .2 5 c E o. -80 .9 Q 1 : _ ‘5 '8 400 g g < ' E -100 a) ...: (I) C a. a 2 s 8 200 -140 0 i 5 -160 i i -60 L 4 0 100 200 0 100 200 0 100 200 OSR OSR OSR Figure 5.13. Comparison of the first order and the second order STL system performances Eqn. (5.6). Therefore, the number of adaptation cycles depends on the ratio of rm to the 1:11 223,-. Fig. 5.11 shows that the STL system learns about the non-linearity and adapts itself without degrading the performance. This is seen with the help of the residual power left on the channel and the reconstruction error plots of Fig. 5.11. The worst case change in the residual power and the reconstruction error are 2.9 % and 3.2 % respectively. 5.2.6 STL System Dimensionality M and the Signal Statistics The performance of the STL system is dependent on the dimensionality (total number of channels) M of the system and the signal correlation or the (signal statistics). Eqn (4.30) shows that for an M dimensional system, the the digital output dm (22:0 dm[i] —> 0) goes to zero at a faster rate if the number of correlated channels increases. As shown in Eqn. (4.30), the signal mm of the STL system is represented by its lower dimensional (M — 1) channels. This shows that the correlated information is shared across M channels for digital representation, therefore Fig. 5.12 shows that the number of adaptation cycles 76 12 7 f 0 . E -20 ......................... a 6‘ 7‘5” _ v C o t. t > 0 g “c1 c O o .9 ”7 Q. .8 E a a O. 3 .. < 33 $33 . m -80 ........................... 0 ’- . —100 e i -100 4 . 10 12 10 12 10 12 Transform Resolution Transform Resolution Transform Resolution Figure 5.14. Comparison of the first order and the second order STL system performance with respect to the resolution of a linear transformation matrix A required decreases with increase in the number of correlated channels. The residual power is a function of the signal correlation therefore conclusions cane not be drawn from observ- ing the residual signals left on the channels. Fig. 5.12 shows that the worst case variations in the reconstruction error goes up to 3.5% which shows that the reconstruction error is not affected by the number of channels. 5.2.7 Order of the 2A Converter The noise shaping characteristics and the dynamic range of a STL system depends on the order of the 2A converter employed in the system. As given by Eqn. (2.3) and Eqn. (2.4), the dynamic range and the attenuation of the noise in the signal band improve with the in- crease in order (L) of a a 2A converter which is seen in Fig. 2.3. As given by Eqn. (4.55), the second order STL system works with the second order difference of the signals, there- fore the error correction of the second order system is better compared to the first order system. Therefore, Fig. 5.13 shows that with increase in the order L and the OSR of the 77 d —6— Order = 1 9800 ‘20 + Order = 2 A -10. ......................... m w E -40 ......................... . 3 .3 970° 3 § -20 ............................. > L -60 ....................... . h g 9600 23'; "é .9 o- ..80 .......................... .. .12) —30 35 9500» a 8. d )3 -100 ........................ . 4% 'D 9400 g 8 _40< ....... A ...... G ...... O ...... 2 p < cit-120» 7% g c A x ., 0: ‘.’ ...... V. ....... 9300 _ 7 7 -50 .............. E P . 9200 1 -160 ’1 -60 ‘ 0 0.1 0.2 0 0.1 0.2 0 0.1 0.2 Mismatch Factor Mismatch Factor Mismatch Factor Figure 5.15. Comparison of the first order and the second order STL system performance with respect to the component mismatch in the system STL system, the system performance improves. The residual power left on the correlated channels and the reconstruction error both decrease with increase in the order L of the STL system. As shown in section 5.2.2, the increase in the resolution of a linear transformation matrix improves the precision of signal transformation. Therefore, the residual power and the reconstruction error decrease with increase in the resolution of a signal transformation. The resolution and therefore the accuracy of the output data increases with increase in the order of the 2A converter used in the STL system. Therefore, with increase in the order L of the STL system for the specified resolution of a signal transformation, the residual power left on the correlated channel and the reconstruction error decrease which is shown in Fig. 5.14. Fig. 5.15 shows that the number of adaptation cycles required by the second order STL system is smaller compared to those required by the first order STL system. This is attributed to the faster adaptation rate of the second order STL system (Eqn. (4.41)) com- 78 1.2 l v 1.1L- ............ ........... . V Reconstruction error (dB) Adaptation cycles Residual power (dB) 09% -140 ......... ........... 0.9 4 ' ' o 0.1 0.2 o o 1 0.2 o o 1 0.2 Leakage factor Leakage factor Leakage factor Figure 5.16. Comparison. of the first order and the second order STL system performance with respect to the component leakage in the system pared to the first order adaptation rate Oiqn. (4.31)). Like the first order STL system, the second order STL system does not get affected by the mismatch in the system. The resid- ual power and the reconstruction error of the second order STL system show variations up to 2% and 1% compared to 1.5% and 1.7% of the first order STL system. Higher varia- tions in the residual power of the second order STL system due mismatch are attributed to the increased number of components and their dynamics in the system. Despite higher variations in the residual power, the variations in the reconstruction error of the second order STL system are less compared to the first order STL system. These decreased varia- tions are attributed to better noise shaping characteristics of the second order EA converter framework of the STL system. The Eqn. (4.40) shows the output characteristic equation of the Mth channel of the second order STL system output with no leakage effects. VVIth leakage or in the system, Eqn. (4.40) is written as N m—l N W (Ecl'm) — Z E($1)azm) = gdmli] (5.7) [=1 79 4 0 —6— Order = 1 0 ~20 —<>— Order = 2 ------- 35 ...... . ........ . . . . . . A to CD 2 B 2. 3 _. ....................... . a, g 3 o o a 55 g 25 ....... _ ...... . ....... . "a (I) < :2 2 . - . > 1.5 i -160 -60 0 5 0 5 0 5 Non-linearity factor Non-linearity factor Non-linearity factor Figure 5.17. Comparison of the first order and the second order STL system performance with respect to the component non-linearity of the system where the coefficient aim is given by Eqn. (4.41). The higher dynamic range of am and the signal amplification due to (17:35 increase the number of adaptation cycles of the second order STL system as shown in Fig. 5.16. Like the first order STL system, the perfor- mance of the second order STL system degrades with increase in the integrator leakage of the STL system. This is exemplified in Fig. 5.16 where the residual power and the reconstruction error increase with increase in the leakage of the STL system. Fig. 5.17 shows that the non-linearity in the system components has very little effect on the second order STL system. It is evident from Fig. 5.17 that due to a better noise shaping of the second order 2A converter, the performance of the second order STL system is bet- ter compared to the first order counterpart. Fig. 5.18 shows that the number of independent channels added in the STL system has lesser effect with increase in the order of the STL system. The adaptation rate of the second order STL system (given by Eqn. (4.41)) is higher than the adaptation rate (given by Eqn. (4.31)) of the first order STL system. There- fore, the number of adaptation cycles decreases with increase in the number of correlated 80 . . o r . 2'05 § § 0 —e—Order=1 g g g -20 —9-Order=2 i" g g 2 A I l g _20 ........... .............. . w 0,3 1: 2 2 r g g a m a _ ........... :- .............. "c’ E "S 40 s : .9 1.9 ‘ O. -- g g : ,_, _ 9W (0 ... ; 1.8 _ ........... ,_ .................. ' -140...” ............. ’ 1.75 i 9 -160 i ; -100 I. 2. 6 8 6 8 6 8 System Channels System Channels System Channels Figure 5.18. Comparison of the first order and the second order STL system performance with varying system dimensionality channels in the second order STL system. The deviations in the reconstruction error is less than 1 % in the second order STL system compared to 3.5 % in the first order STL system. 5.3 Neural Signal Processing with the STL Algorithm The STL algorithm is verified with the real life multi-channel neural data. The multi- channel experiments were performed with an 8-channel neural data recorded from the dor- sal cochlear nucleus of adult guinea pigs. The data was recorded at a sampling rate of 20K H z and at a resolution of 16-bits. Fig. 5.19(a) shows highlighted areas which exhibits high degree of cross-channel correlation. Fig. 5.19(b) shows that the STL system removes this spatial redundancy across all channels and keeps the un—correlated information of each channel. Fig. 5.19(c) shows that the data reconstructed with the help of digital output data streams of the STL system and the signal transformation matrix A. An interesting observation in this experiment is that even though the statistics of the input signals were varying in time as shown in Fig. 5.19(a), the transfonnation matrix 81 _ (a) (b). (c) . 8 WVNMaA‘MWW'Vfl 8 8 {'15 MMMWN‘V‘I " 7 swat? v"‘v‘v‘ “MHWWW 7 7 WV‘WWMM 6 MWMMWWM 6 6 WRMMWF‘ 5 “WVWNNWWM 6 5 Ms - “w M 4 WW 4 4 W 3 WW 3 3 WW 2 MW 2 2 WW 0 0.5 1 1.5 o 0.5 1 1.6 0 0.5 1 1.5 Time (ms) Time (ms) Time (ms) Figure 5.19. Functional verification of the STL system for the multi-channel neural data: (a) Original multichannel input signals (b) Digital output produced by the STL system, and (c) The reconstmcted signals from the multi-channel output data streams of the STL system and the signal transformation matrix A 3.5 ' 1' J 3 2.5‘ I H A ””2 l Bounds l a 1-5 Adaptation Pefiod 1 7 t . n 0 0.5 1 1.5 Time (ms) Figure 5.20. Adaptation of the STL system is shown by the signal transformation matrix A that converges to a stable value after learning the correlation of neural signals 82 A remained relatively stationary during the duration of the conversion. This is illustrated through the reconstruction error graph in Fig. 5.20. This validates the principle of operation of the S TL system where the multi-channel neural recording lie in a low-dimensional space whose parameters are relatively stationary with respect to the signal statistics. The simulation results shown are encouraging to realize the STL hardware system. The worst case hardware parameters considered here are obtained from the advanced liter- ature on hardware therefore the simulation results show that the system is realizable despite hardware irregularities such as component mismatch, offsets and non-linearity. The gen- eralized algorithm of the STL system finds many ways to realize this circuit in hardware therefore the challenging part of the hardware realization is to deal with the complexity of many aspects of the design topology, dimensionality, area and power budget specifications. In part II, the STL algorithm is realized with a specific form of hardware as a proof of concept. The mixed signal circuit design and simulations are shown. The AM I C5N 0.5p process is used to realize the hardware on a chip and the hardware results are shown to ver- ify the functionality of the algorithm in the hardware. This chip is further shown to work with real life data and is used for acoustic source localization. 83 Part II Hardware Realization 84 CHAPTER 6 Hardware Circuit Design 6.1 Hardware Realization of the STL System The simulation results in Chapter have shown that STL system is realizable in hardware. The simulations are performed with some of the worst cases of hardware parameters such as mismatch, offsets and non-linearity. The satisfactory performance under such constraints has provided the fair degree of confidence in realizing this system in hardware. The STL system is designed in a mixed signal circuit design environment. This algorithm can be designed in many ways but the design presented here has the particular advantages of area and power savings. 1 The STL system is designed with the help of 2A converter framework as described in 4. The architecture as shown in Fig. 1.9, consists of mainly 3 modules namely the signal transformation module, 2A converter array ( 23A modulators and decimation filters) and the adaptation (learning) module. The learning and the signal decorrelation are performed with the help of adaptation and the signal transformation modules. The adaptation module uses the feedback from the digital signals of the 2A modulators to generate the digital control signals. These digital control signals drive the transconductor network of the signal transformation module which performs the current mode matrix vector multiplication to decorrelate input signals. The 23A converter array digitizes the uncorrelated analog signals obtained from the signal transformation module to give the temporal information of the 85 X1 X2 X3 X4 2A d1 : Modulat APU (311) O'- A 2A d2 Modulat APU APU (321) (322) APU (331) APU (341) Figure 6.1. The block diagram of 4-dimensional STL system. signals. The adaptation and the signal transformation module are designed considering the com- putational complexities of analog and digital designs and the interface specifications of the system. The adaptation module is designed in with a digital logic circuits that generates the control signals am, for each signal 1 in the M th channel of the STL system as given by Eqn. (4.31). The most important feature of the adaptation module is the 1-bit control signal that updates the coefficient am at every oversampling clock cycle to carry out the signal transformation. The l-bit digital control signals are coarse signals but are shown to be very effective in precise decorrelation of input signals. The hardware complexity of the 86 adaptation module is reduced by l-bit control signals of the adaptation module. The signal. transformation module learns the signal statistics and eliminates the redun- dancy across the signals. In addition to that it adapts and compensates for component irregularities such as mismatch, leakage and non-linearity in the system. The decorrela- tion coefficients that are stored digitally, show the spatial modulation parameters (A) of the source signals whereas the modulated signal transformation is performed in analog domain with the help of current mode circuits. The digital decorrelation coefficients dynamically adjusts the gain of the weight vectors of the matrix vector multiplier performing the current mode computations. The gains of all uncorrelated signals are maximized whereas they are attenuated for all correlated signals to adjust the dynamic range of the transformed signals. The gain control or the adjustment of weight vectors is performed by dynamically bias- ing [47] the reference current of individual cells of the transconductor network. Such gain control and the dynamic biasing optimize the power dissipation of the analog circuits as well as relax the dynamic range requirements of the system [46]. In the STL system, the 2A converter array digitizes the uncorrelated signals from each channel which is a major source of power dissipation of the system. The ideal state of the art 10-bit ADC's consume power of the order of 13.7 mW/MHz [69]. To match such strict power budgets, a novel approach is required to operate the multi-channel 2A converter array. In the STL system, the signal decorrelation attenuates the correlated signals after Signal transformation which are comparable with the system noise. Therefore, the noise increases the zero crossing switching of the EA converters and so the power dissipation of the system [47]. Therefore, a novel approach that adds the hysteresis to the comparator of the 2A converter is introduced. The hysteresis reduces the zero-crossing switching of the comparator and thus decreases the power dissipation of the 2A converter. The output of the STL system consists of two digital streams, the uncorrelated output data streams of the 2A converter array and the signal transformation coefficients/operands aij that are stored digitally in the adaptation module. The signals are reconstructed from the 87 signal transformation matrix A and the non-redundant low bandwidth digitized channel information. In the next section, the design of the 4-dimensional STL system is shown along with the individual components. The design issues and specifications are discussed for each component of the STL system. In the next sections, the test procedures and simulation results are presented for the designed mixed signal circuit of the STL system. 6.2 4-Dimensional STL System A block diagram of 4-dimensional STL system is shown in Fig. 6.1 where the modulator outputs di,i = 1, 2, 3,4 are the digitized representation of transformed signals yi,i = 1, 2,3, 4. The signal transformation coefficients org-J = 1..4, j 5 2' stores the digitized spatial modulation information of signals 25,-,2' = 1.4. The transformed signals y,,i = 1, 2, 3, 4 are given by i 31:“ = Z aij-Tj (6.1) j=1 where xj is the jth system input and aij are the de-correlation coefficients of the trans- formation matrix A given in Eqn. (4.11). The aij are the analog signal processing units (APUs) that perform the signal transformation in analog domain and stores the transfor- mation coefficients in a digital form given by Eqn. (4.11). As discussed in section 4.1, A is chosen to be a lower triangular matrix such that all the diagonal coefficient elements a,,-,i = 1.4 are unity elements. The non-diagonal coefficient elements aijn' 75 j are the adaptive elements that modulates the weight vectors to cancel out correlated signals. The digital data stored in the non-diagonal elements aij,i # j gives the de-correlation coef- ficient of signal x,- with respect to signal 553-. Therefore, the summation Eqn. (6.1) gives signal y,- such that signal 1:,- is maximally uncorrelated with the lower dimensional signals 55,-, j < i. This minimization step leads to a resultant signal y,- = 0 when all input signals 88 :23,- are correlated. The SA modulator of each channel converts the analog signal y,- into a 1-bit modulated output given by d,. The system shown in Fig. 6.1 can be implemented in a voltage mode or a current mode design. The voltage mode summations require capacitive elements to store charge where as the same summations can be performed with a single transistor using the Kirchoff’s current law. Therefore, the current mode computation can save the significant area of the chip for a given dimensionality. The analog processing units (APU) are designed using current mode circuits. Therefore, the current mode output signals 3;,- require the first stage of the EA converters to be a current mode. In case of higher order 2A converters, hybrid modulators are used where the first stage is the current mode and the subsequent stages are the voltage mode modulations. For the given 4-channe1 system, the first order and the third order 2A converter are designed. The first order EA converter employs the hysteretic comparator. The hybrid mixed mode third order 2A uses the integrator block of the first order modulator. For simplicity of understanding, the circuit design and the simulation results of the system are discussed with the help of 2-dimensional model in the next section. 6.3 Circuit Design IREF IDAC = a21 * IREF x1.._+ T Y1=Irr 2A , d1 11 F‘" VREF _ .-/l MOdUlator X1: Up-down d2 Countle:(a21) Current DAC (IDAC) Vim—y Modulator Figure 6.2. The schematic diagram of 2-dimensional ( 2-Input 2- Output) STL system 89 A current mode 2-dimensional STL system as shown in Fig. 6.2 is designed to show the validity of the algorithm discussed in chapter 4. An analog transconductor network performs the matrix vector multiplication for signal transformation and digitally stores the weight vectors. Additions are performed using the Kirchoff’s current law, where as multi- plications are performed by modulating the transconductor bias current. A 2—dimensional STL system shown in Fig. 6.2 has 2 inputs ( X1 and X2 ) and 2 outputs ( (11 and d2 ). Transconductors Tij correspond to the elements aij of the linear signal transfonnation ma- trix A. Since all diagonal elements of the lower-triangular signal transformation matrix A are unity elements, the transconductors Ti, ( T11 and T22 in Fig. 6.2 ) are biased by a con- stant reference current I REF. The non-diagonal transconductor T,- ', i < j ( T21 in Fig. 6.2 ) is biased by the digitally programmable 10 — bit current DAC. The output currents of transconductors are proportional to the input signal X (2') and the bias current generated by the current DAC. The SA modulators digitize the output currents of the transconductor network. The adaptation of the non-diagonal elements aij is implemented using an incre- mental/decremental counter where count mode (increment/decrement) is triggered by an X N OR function that compares the phases of the 112(3) [72] and the digital output d, (j < i) of the 2A modulators. 6.3.1 Linear Titansformation Module The linear transformation module of an M -dimensional STL system has the M - dimensional weight vector that performs the matrix vector multiplication. The linear trans- formation matrix A is configured as a lower triangular matrix so that matrix inversion is always possible for signal reconstruction i.e. to avoid the transformation matrix to get into run-away state(singular matrix). The other advantage of lower triangular structure is the reduction in the hardware complexity and so the power dissipation of the system. All di- agonal elements of a linear transformation matrix are implemented using a transconductor having a constant maximum reference bias current used in the system. The non-diagonal 9O elements are implemented using a transconductors whose reference currents are modulated by a 10 — bit current DAC. The output current of the 10 — bit current DAC is controlled by an 11 —— bit up-down counter where the M SB or the 11th bit acts as a SIGN operator for changing the direction of the transconductor output current. 6.3.2 Up-Down Counter/Shifter r SH . — MU \ R__. D__2X1 DIN Q D—V s—~ DFF c T CLK CLK 6 U 0” rr_‘_’.:_‘.:_‘:.---_-__-..-..........-....-----_---___-_..____..:::- Vdd Vdd CLK LK CLK Io—Cl-K * 4% IV I-I ii Figure 6.3. Schematic: I bit up-down counter/shifter The schematic of a single stage incremental/decremental counter is shown in Fig. 6.3. The core of a single bit up-down counter cell is implemented with an inverter based D flip-flop with minimized transistor count. Therefore, this reduction in the cell size helps to enhance the resolution of adaptation and to accommodate more number of channels for a given die area. The circuit is also configured as a serial shift register to get the access of 91 E R 1bit Counter 1- —— ............ —— R 1b'rt Counter T R 1bit Counter 1- — S Shifter V _ ............ _. S Shifter V 8 Shutter V _ Q Q Q SH_IN— SH '_ g ——l ------------ — SH |_ g * SH x g 5 d ‘5 5 d 6 i 5 o' 6 _1 Do 09 SIGN CNT CLK UPDN Figure 6.4. Schematic: 11 bit up-down counter/shifter the internal states of the counter. The M S B of the counter is used for signed operation that controls the direction of the transconductor output current (see Fig. 6.5). The adaptation of the non-diagonal elements aij ( (121 in Fig. 6.2 ) is based on Eqn. (4.] 1) and is implemented using an ll-bit incremental/decremental counter as shown in Fig. 6.4. The increment or the decrement of the counter is triggered by an X N OR function that computes the binary phase difference between input signal cry-[n] and the digital output of the EA converter d,[n]. In the 2-dimensional system shown in Fig. 6.2, the only non-diagonal element 0.21 is updated using the modulator output of the 2""l channel d2 and the input signal X1. The up-down counter stores the decorrelation coefficient aij of the transformation matrix A and drives the 10-bit current DAC shown in Fig. 6.7. 6.3.3 Transconductor Fig. 6.5 shows the schematic of a transconductor employed for analog processing network of the STL system. The output current of the transconductor is directly proportional to the differential input signals and the bias current of the transconductor. Precise current summation at the output of the transconductor is achieved by employing the cascode struc- tures that enhance the output impedance of the transconductor. The input range of the STL system is limited by the linear input range of the transconductor. Therefore, in order to increase the input range, a wide range transconductor topology needs to be selected. Many 92 Vdd R1 VIP Hm?" Magi} VTPBIAS - 4" M6 SIGN ‘——E' M51 <1 M32 Maj: VREF Figure 6.5. Schematic: Transconductor with bump circuit for improving the linear operating range. topologies are reviewed in [79] to improve the linearity of a transconductor. But due to a limited area constraints, the transconductor with a bump circuit proposed in [79] gives the wide input range as shown in Fig. 6.5 for the limited number of transistors. A bump circuit ( transistors M B 1 — M B4 ) used in the transconductor acts a current steering element, therefore reduces the gm and improves the linear range. The direction of the output current is digitally controlled by the SIGN bit of the up-down counter. The parametric analysis of the DC response of the transconductor is shown in Fig. 6.6 where the reference bias current is varied from 20nA to 200nA. The plot shows that the designed transconductor has more than iISOmV of linear input range. The output current range can vary from few femtoamperes to microamperes for the given input range. 6.3.4 Current DAC The schematic of a 10-bit current DAC is shown in Fig. 6.7. The output of the current DAC modulates the bias current of the non-diagonal transconductors. The current DAC’ 93 x 10‘7 Transconductor: DC Analysis r l r l : i i + 2011A 1.5 ............ ...... , ............... _ ......... ........ ..........._ ..... .. ............. e 40nA : : : : : + 6011A : L + BOHA 1.. ................... ........ ....................... ...................... ............... 100M : l i " —+—-120nA )5- ................................................................................. +140nA ; I : :\ ; ; “ 160M . . 3 -\\ 5 ; +180nA 0_,_ ......... , ........ i ..................... ? ......... \. i 3 ..................... —e—200nA 3.5... T .......................... - _1_ ............... ............................................................................................ 1.5_ .............. ............................................................ .................................. ...... i 1 l r i 1.5 1.55 1.6 1.65 1.7 1.75 1.8 Input Voltage (V) Figure 6.6. Circuit simulation response of the transconductor circuit is based on the standard MOS resistive network whose functionality has been demonstrated over several orders of magnitude [80] with reported current as low as few femtoamperes. The architecture given in [80] is modified to make it binary current DAC. Digital inputs of the current DAC are driven by the output of an up-down counter/shifter shown in Fig. 6.3. All current supplying transistors have to be operated in saturation region in order to make perfect current division at each stage. As the resolution of the current DAC is increased, the voltage headroom to operate each transistor in saturation decreases. As a result, with the increased resolution of current DAC gets more transistors come out of saturation and therefore the non-linear current response is expected. In Chapter 6.1 the STL algorithm is shown to be robust to the non-linearity of the system therefore, therefore despite the non-linear current response the current DAC shown in Fig. 6.7 is used for its 94 ............. p— 4 Li] A IBYPASS __________ - ID— A 09 D8 DO 'DAC Figure 6.7. The schematic IO-bit current DAC that provides a reference current for the transcon- ductor network of signal transformation module. small compact size compared to other capacitive current DACs. Fig. 6.8 shows the transconductor output current as the current DAC is driven by the 11 — bit up-down counter. This response is plotted by stimulating the non-diagonal cell (am-J aé j of the signal transformation matrix A. The transconductor output current is plotted as the 11 — bit up-down counter/shifter is varied. The reference bias current of the transconductor is driven by the 10 — bit current DAC’. For the given value of the up-down counter, the input signal is varied within the linear range of the transconductor. The output current of the transconductor is integrated for a fixed period of time. This integrated output voltage is directly proportional to the output current generated by the current DAC. Thus, the integrated output voltage is used to characterize the current DAC. The DAC response in Fig. 6.8 shows that the response is monotonic but non-linear with respect to the counter data bits. Despite this non-linearity, it is shown later in the circuit simulations, that the STL system adapts and compensates this any non-linearity. 6.3.5 First Order EA Converter Fig. 6.9 shows the schematic of a current mode hysteretic EA converter. It consists of cascoded transistors T2 — T5 for generating current references i138 f. Multiplication of 95 2.4 .............. .................................................. 1 9 :2.2 .................................................................... 8 N 2 .................................................................... a) '2' 1.8l’ .................................................................. 5' 9 1.6 ................................................................. 3 O 'O 1.4 ...................................................................... .9 (U 512 .................................................................... .9. E. 1 ...................................................................... 0 500 1000 1500 2000 DAC Input (SIGN + 10 Bit) Figure 6.8. The output response of the 10-bit current DAC is plotted by integrating the DAC current output for a fixed interval of 20us. reference current I Re f by digital bit Dn is implemented using switches T1, T6 connected to the source of cascoded transistors. Switching at the source as opposed to switching at the drain [81] reduces the channel charge injection and the clock feed-through at the integration node VINT- A standard folded cascode op-amp shown in Fig. 6.14 is used to implement the integrator that provides 60dB open loop gain. As opposed to cascoded inverter based implementation [82], the differential amplifier based implementation can achieve a symmetrical and larger integration range V; NT about the reference potential. A digitally programmable capacitor bank has been used for the implementation that allows the adjustable integration gain. The hysteretic comparator shown in Fig. 6.10 is imple- mented using a basic differential pair with current starved inverters. The positive hysteresis level +A and the negative hysteresis level —A are programmed based on the input current range and the ambient noise level of the integrator. The hysteretic 2A converter acts as a conventional EA converter by setting the hysteresis level A = 0V. 96 d_c| Hysteretic Reset Comparator it VPB1 I I d +1 VOUTT VPBZ-d l I V—HREF * - I '9' C Counter! = o : IN_| - Un Shifter V'N VN32 ‘ Serial Datal t -1 VNB—1"| XEEE-o/ I -A Hi I _.| Q 17 (1 Figure 6.9. Schematic of the hysteretic first order 2A converter T 31 waaq‘] ID——Q— *4 vour VREEd '3le l— Ll VBIAs—l VNB—l 3 Figure 6.10. Schematic diagram of the hysteretic comparator of the EA converter: The hysteresis level in the comparator is changed by adjusted the bias values VPB and VNB of the comparator: 6.3.6 Third Order 2A Converter The linear range of the transconductor is limited to i150 mV therefore the noise shap- ing performed by the first order or the hysteretic 2A modulator is not sufficient to obtain a good SN R for the given input range. Therefore, the third order single loop single bit modulator is designed to improve the S N R of the modulator. This third order hybrid 2A converter consists of current mode integrator as the first stage followed by the subsequent voltage mode modulators. The higher SN R of the third order 2A comes at the cost of less loop stability due to a high gain of the noise transfer function (N TF) at high frequencies. Therefore, the loop instability is compensated by the reduced input range of the modula- tor. The third order 2A converter is designed and simulated in M atlab to get the precise 97 Figure 6.11. Third order single loop single bit EA modulator. Table 6.1. The loop parameters of the third order single loop single bit EA modulator C! Q loop parameters. The current mode output y,- of the transconductor network of the signal transformation module requires the current mode first stage 2A modulator. The hybrid 23A modulators [16] have shown the advantages of the continuous time as well as discrete time modulators. Amplifier unity gain frequency and the power requirements are relaxed in the continuous time modulators where as the discrete time modulators offers the scalability. Therefore, a 3rd order single loop single bit mixed mode hybrid EA modulator is selected after area, power, input range and the stability considerations as shown in Fig. 6.11. Ta- ble 6.1 shows the simulated gain parameters of the 3rd order mixed mode 2A modulators that maintain the stability of the STL system. The current summation Eqn. (6.1) acts as a input to the 3rd order mixed mode single loop single bit 2A converter (Fig. 6.11) ar- ray. The first stage of the modulator is a continuous time current mode integrator shown in Fig. 6.12 where the reference currents are tuned to accommodate the maximum input current (yj = I j, j = 4) given by the current summation Eqn. (6.1) to avoid the over- load condition. The multiplication between the digital bit d and the reference current is implemented by switching (on/off) the cascoded current sources (sink) at the source (see 98 d —‘1 M01 RESET VPBIAS1| M9 40—— VPBlASZ It —<1 M10 Cm VNBIASZ I M11 .29? + VNBIAS1 —1 M12 d _ —-| M02 ' Figure 6.12. The schematic of the first stage integrator of the third order hybrid EA converter: Fig. 6.12). Switching at the source as opposed to switching at the drain has several ad- vantages [81] as it reduces the channel charge injection [81] and the clock feed-through at the integration node. The integrating capacitor (CINT) of the first stage modulator is cho- ___ RESET —0’ s C SZD T I, VIN c1 52 92 o a); \I _ 310° II ] ”‘2 vour $10 7:01 $1 + c 2r d*v* + d’*V :IA _E—‘fig Figure 6.13. The schematic of the second and the third stage stage integrators of the third order hybrid 2A converter. sen such that the integrated output voltage lie within the accepted maximum input range (VL I M) of the second stage modulator where 2pA maximum cumulative current input is 99 Table 6.2. Capacitor sizes used for the 2A modulators C I NT 4. 136 pF Cl 5 l .7 fF C 2 5 1 7 fF allowed. The size of the integrating capacitor (C 1 NT) is given by I REF * TCLK VLIM C I NT = (6.2) The second and the third stage modulators are switched capacitor modulators whose single ended version is shown in Fig. 6.13. The capacitor ratios are set based on the values shown in table 6.1. The absolute values of capacitors are shown in Table 6.2. For all integra- Vdd T @4de 4,—1M21 CI M22 - vpsz e'Erm VIP | M13 JFVIN VOUT M14 N82 M17 V II‘ I IL. 1 M18 VNB1 ”'— M15 I I 1 M16 Figure 6.14. Schematic of the folded cascade op-amp. tors, a standard folded cascode op-amp as shown in Fig. 6.14 is used. Since the op-amp drives only capacitive load, a folded cascode op—amp becomes the natural choice com- pared to the telescopic or two-stage Op-amps. The folded cascode op-amp has better output voltage swing compared to the telescopic op—amp and better speed compared to two-stage op-amps for the given gain. The folded cascode op-amp is designed to have a open loop DC gain of 60dB. This gain is greater than twice the over-sampling ratio of the converter to reduce the errors caused by leakage in the integrator. As opposed to cascoded inverter based implementation [82], the differential amplifier based implementation can achieve a 100 symmetrical and larger integration range V; NT about the reference potential. The modu- lator uses hysteretic comparator shown in Fig. 6.10. The hysteretic comparator shown in Fig. 6.10 is implemented using a basic differential pair with current starved inverters. For the third order modulator, the comparator hysteresis is disabled by setting the hysteresis level A = 0V. 6.4 STL System: Circuit Simulation Results A 2-dimensional STL system shown in Fig. 6.2 is simulated with DC input signals and sinusoidal inputs to verify the functionality. For the transient analysis of STL system, simulations are run for 2 ms at a 250 kHz clock frequency (500 clock cycles). The recorded data of the first and the last 25 cycles spanning 100us each are shown to demonstrate the adaptation of the STL system. Fig. 6.15 and Fig. 6.16 show the STL system performance during the first and the last 25 cycles spanning 100us. DC input signals are applied where input X 1 is +40mV and input X2 is —30mV. The digital outputs of two EA converters d1 and d2 are plotted along with the integrator outputs VOU T 1 and VOU T2 respectively. For the 2-dimensional STL system, channel 1 is a fixed reference channel therefore output d1 is an equivalent digital output of signal X 1. As can be seen by the integrator plot, VOU T 1 in Fig. 6.15 and Fig. 6.16, the integrator output response VOU T1 of channel 1 is unchanged during the initial and the final 10011.3 simulation period. The average value of the digital output d1 is the same (0.8697) during the initial and the final 100113 simulation period. The adaptation of the STL system is evident when the digital output d2 of the second 2A converter channel changes in the final 100us simulation period. The gradual change in the integrator output VOU T2 of the second channel is seen from Fig. 6.15 and Fig. 6.16. When the STL system de-correlates the two channels then the average value of the digital output d2 of the second channel go towards the equivalent zero input signal. The average value of the digital output d2 changes from 0.098 to 0.335 in the initial and the final 100113 simulation periods. Thus, it is seen that the STL system tracks the spatial 101 I .0 Z i 0 h i 20 40 60 ETHH 0 80 100 .—1 _2_, ° lIllIlllllllllllllllllllllllll 0 20 40 60 80 100 1.8 r . T r N : s ; 2 O E 3 E 2 >16- ...... . ....... ................ l ................ ............ ..1 .............. .. 0 20 40 60 80 100 1-8 1 ¥ :' 1 51.7- .............. g ....... . ........ ............. g .............. ........ _ ..... _ o ‘ ' r >1.6 ----- . . _ 0 20 40 60 80 100 Time(us) Figure 6.15. 2-Channel S TL system response to DC inputs during the initial period of 100us. The digital outputs d1 and d2 represent a digital pulse width data equivalent to input signal X 1 and X2 respectively. VOU T 1 and VOU T2 are the integrator outputs of the 2A converter array used in the 2-dimensional STL system. correlation of between two signals. For the 2-channel STL system, the only non-diagonal element T21 of a linear transfor- mation matrix A is shown in Fig. 6.2. The counter value of the non-diagonal element of the linear transformation matrix A is proportional to the magnitude and the phase differ- ence of input signals. Fig. 6.17 shows the steady state counter value of the non-diagonal element of a linear transformation matrix when parametric analysis is performed using the reference signal X1 is +40mV and the signal X2 is varied in steps of 5mV. The steady state adaptation response is shown in Fig. 6.17. The steady state counter value of the non- diagonal element of a linear transform matrix A is proportional to the input signal X2 as the reference input signal X 1 is kept fixed as shown in Fig. 6.18: This response shows that 102 T l I I 1 .......... . . . . . . . . . . . . . . . . 0-- . ' 9» ~.- ~ 1920 1940 1960 1980 i 2000 1 I .1 B e 1920 1940 1960 1980 2000 $17 ..... I . ...‘ I 3 : b ' _ 916.. .............. ............... ............. .. 1920 1940 1960 1980 2000 1:1] ....... . ....... ............... .............. ............... ............... D ' ' , 1920 1940 1960 1980 2000 Time (us) Figure 6.16. 2-Channel STL system response to DC inputs during the final simulation period of 100us. The STL system adapts such that the digital output d2 represents the transformed signal of X2 that is un-correlated from signal X 1. The reference signal X1 is represented by the digital output d1 and VOU T 1 shows the unchanged integrator response. the STL system compensates for the non-linearity of the current DAC by adjusting the counter value that controls the bias current of the transconductor through current DAC‘. With the monotonic response of the current DAC, the STL system adapts to such non- linearity which are shown by the steady state adapted values of the 2-dimensional STL system for DC input signals. 6.5 STL System: Power Estimation The design of STL system deals with the important aspect of power dissipation. In or- der to maintain low power dissipation budgets, each component is carefully designed so as to reduce the power dissipation. The signal transformation module is designed in ana- 103 Convergence of Non-diagonal Element of Linear Transform Matrix 2000 1800 531600 8 93 c: 81200 01000 I a - . . . . . 1 8 9.1,- 1+ 5mV or 8009- < an, 99-9; 9.- 9.9—. 9—9— 9- .9- .9.-.I>_-.9-.9 9.- 9 99:99 .9 >98va l—9—10mV ‘1’ 600- 9. r: ‘°~ .7...Y.7.7.777V'.Y.Y7.77187???9'17??? S ' it‘ll. “69 +15mv Z \‘Eru ~o—o-o--e we-o-o-o-o-e-e-H-o—o-o-o-e 400- ................... .._’....>n‘ .......................................................... _e._ 20mv rock“ a a -n ; -.,. ‘D-D-B-a-a-n-a-D-a-a-a-n-+25mv 200 . ................... ............. ‘i;.~ ... .................... . ...................... ; i 1 ‘41-'99. t-IIr-e-u-o- 30mV 0 0.5 1 1.5 2 Time (sec) x 10-3 Figure 6.17. Convergence plot of the non-diagonal element A(2,1) for different DC input signals with respect to fixed reference signal of 40mV log domain that consumes less power compared to its digital counterpart. The SA mod- ulators are designed with low power techniques of subthreshold circuits and comparator hysteresis. For the designed STL system, the linear transformation matrix A consists of transconductor network with diagonal and non-diagonal cells. The transconductor and the current reference circuit constitute the diagonal cell. The non-diagonal cell consists of a transconductor, a current reference circuit, a 10 — bit current DAC and an 11 — bit up-down counter/shifter. Therefore, the power dissipation of the signal transformation is dominated by the non-diagonal cell. For the M -channel STL system, the total estimated power PEST is given by M * M —1 PEST = (PADC * M + PNondiagA * ( ) (2 ) + PDiagA * M ) (6.3) 104 Response: Non-diagonal Element of Linear Transform Matrix 2000_ ............ . ..... ._ ...... _ .......... ................... ......... . ......... ................. _ 1800* ............... .......... . ..... ...... ....... , ...... ............... .............. _ 1600* ........ ..... . .......... ................... ................. .................. .............. _ (U _ . . . Q1400- ............ , ..... 5 ............... ............... ............ .......... .5 ................ .J E). i : : E : §1200- — o 2 s O . 8’ 5 800- ..................................................................................................... _ is Z 600- ........................................................................................................ _ 400- ........... .t 200* _ l i 1 i l -%0 -20 -10 0 10 20 30 DClnput(mV) Figure 6.18. The response of signal transform matrix that shows the adaptation of STL system with respect to the non-linearity of the current DAC where PA DC is the power consumed by the EA converter, PNondiag A and PDiag A are the power dissipations of the non-diagonal and the diagonal cells of the linear transformation matrix A respectively. As shown by Eqn. (6.3), the power dissipation of all non-diagonal cells can be comparable to that of 2A modulator array for higher values of dimensionality M. This is attributed mainly to quadratic increase in the non-diagonal cells. Similarly, the power dissipation increases with increase in the order of the 2A converter as well as the Operational frequency of the system. In the next chapter (Chapter 7), the power dissipation results of the STL system will all its subcomponents is reported. 105 CHAPTER 7 Hardware Results 7 .1 Hardware Design Test Setup The test setup environment shown in Fig. 7.1 is designed for stimulation and acquisition of mixed signal circuits. An FPGA offers the flexibility of building the desired state machine for digital IO (input/output) interface where as the National Instruments’ data acquisition card is used for the analog interface of the chip. A universal test board or the motherboard shown in Fig. 7.2 is designed that offers the 40 analog output ports where each port is associated with 16 — bit DAC. The analog output ports are digitally programmed either by FPGA or by PC interfaced through M atl ab. A custom made add-on daughter card offers the flexibility to interface the mixed signal design with any package configuration of up to 84 pins. The details of motherboard of the test setup are given in [86]. X z'l inn: Spartan — I I I FPGA board is used for digital stimulation and data collection. This FPGA board offers the J TAG clock rate of 50 M H z for digital state machines. The internal clock generator can go up to 200 M H 2. For running different tests, the FPGA offers the flexibility of programming desired state machines to stimulate the design under test (DU T) and collects the data. Analog signals are acquired by the analog ports of the NI DAC card. The data collected from the FPGA and the DAC card are sent to M atlob over serial (RS232) and parallel ports respectively. A K eithley source meter is used that can generate currents as low as few picoampe-res (pA). This source meter is interfaced 106 Figure 7.1. Block diagram of the test setup used for the mixed signal design ven'fication . } » Test Chip Daughter Card ‘ FPGA Board Motherboard Figure 7.2. Setup showing the interface of PC, Xilinx Spartan-III and NI data acquisition card with home grown motherboard to test the designed chips 107 Single Channel Figure 7.3. Micrograph of the 42 channel hysteretic EA converter array. By disabling the hystere- sis. the shown architecture acts as a 42 channel first order 2A converter array. with M atlab using a GPI B bus interface. The data collected from the FPGA, DAC card and the K eithley source meter is post-processed, analyzed and verified in M atlab. Two hardware prototypes of the STL algorithm are realized with the hysteretic first order and the third order hybrid EA converter framework. The hardware results of the core components of the signal transformation module common to both prototypes are reported using the first order STL system prototype. The design of the hysteretic 2A converter is tested for characterizing the current mode integrator of the first order modulator. This integrator also forms the first stage of the third order STL system. The test results of the first order hysteretic 2A converter are reported. The test results that verify the STL algorithm are reported with the hardware prototype of third order STL system. The third order STL system prototype is shown to perform the acoustic source localization with the hardware results reported in Chapeter 8. 7.2 Characterization of the Hysteretic First Order 2A Converter A hysteretic current mode EA converter as shown in Fig. 6.12 is designed with the hys- teretic comparator. The first stage of the EA modulator of any order plays a critical role 108 .09 on 0: Digital Code N '01 1.5 Current (A) X 10'7 Figure 7.4. ADC output response where current is varied from -100nA to +100nA in I 024 steps in the overall performance of the system. The errors introduced by the subsequent stages of higher order 2A modulators are noise-shaped out of the signal band. Therefore, the characterization of the first stage of the EA modulator is important. A prototype consisting of an array of 42-channel hysteretic first order 2A converter has been fabricated in a 0.5pm CM OS process. The size of the prototype is 3mm x 3mm and its microphotograph is shown in Fig. 7.3. The active area occupied by the single hysteretic EA converter is 0.085mm2 which makes it one of the most area efficient design reported in the literature. The hysteretic first order EA converter is operated as a conventional first order EA converter by disabling the hysteresis of the comparator (A = 0V). Table 7.5 summarizes the specifications of this multi-channel 2A converter array. The reference currents for the current mode hysteretic EA converter are calibrated us- ing the digital output of the modulator. Balanced reference currents for the hysteretic 2A converter are set through external analog biases to maximize the input dynamic range. Ex- ternal reference current biases provide a wide input current range from picoamperes (pA) to 1.09 0.5 ‘ - i , ' l- l . 90 i 1'1 i' ii ' I ’5 1.1! 1‘“ 'll -0.5 - .3............ g . ’4 '3 -2 -1 0 1 2 3 4 Input Current (A) x1 0‘8 Figure 7.5. Measured DNL plot of the hysteretic 2A converter that shows the IO-bit accuracy microamperes (11A). The first set of experiments characterized the hysteretic EA converter. A current source meter ( K eithl eyI nstruments ) was used to generate very low (pA— nA) current inputs. Source current was varied from -100nA to +100nA in 1024 steps to charac- terize the DN L (Dynamic Non—linearity) of the current mode hysteretic EA converter. For this experiment, the hysteresis level of the comparator was fixed to A = IOOmV. A simple 24 — bit counter is used to decirnate the modulator output. This decimated output (digital code) of the modulator was acquired through an FPGA interface. The response of the current mode hysteretic 2A converter is shown in Fig. 7.4 that verifies the monotonicity of the modulator. The differential non-linearity test (DN L) is carried to measure the linearity i.e. uniformity of the output transfer function with respect to change in unit step size. The measured DN L plot in Fig. 7.5 shows the accuracy of 10 bits. The sensitivity measurements (the minimum detectable current) were performed using the on-chip PM 05' transistor with adjustable gate-to-source voltage. [83] has shown that by controlling the gate-to-source voltage (V93), a PM OS transistor is operated in the subthreshold region to generate current in the femtoampere ( f A) range. The use of an internal current source avoids the coupling from the external noise sources, which is critical 110 +nA - pA Current Bias - tA Current Bias logt 0(Digltal Code) 50 fA 2.5 2.6 2.7 2.8 2.9 3 3.1 Current Reference Gate Voltage (V) Figure 7.6. Demonstration of the 2A converter that measures the sub-threshold characteristics of a PMOS transistor whose drain current is reduced as low as 50 fit. -5 2.5 X 10 .1 I t {_T fir —B—Non—hysteretic Converter ;; : : : : : :2: —e— Hysteretic Converter Power Dissipation (W) a: N A 1 0.5 l IIIILIIi l ILLIIIIII 103 1o4 05 8 1 10 Frequency (Hz) Figure 7.7. Comparison of power dissipation with respect to sampling frequency shows that the hysteretic 2A converter is more power efficient compared to the conventional 2A converter 111 Table 7.1. Measured specifications of the multichannel hysteretic 2A converter array Parameters . Values t utlon nsrt1v1 581 on at on Active Area 0.085 mm 1 channel Table 7.2. Comparison of the hysteretic EA converter with other Potentiostats and ADCs m Active mm 0.086 0.45 N/A 0.053 for ultra-small current measurements. Fig. 7 .6 shows the log linear plot of the digitized output produced by the current mode 23A converter, when the gate-to-source voltage (V93) of the on-chip PM OS transistor is varied. In the subthreshold region, the drain current is exponentially proportional to the gate-to-source voltage (V93) of a transistor therefore the log linear plot of the output of an ADC is linear with the gate-to-source voltage (V95) of the current generating PM OS transistor. The landmark gate voltages indicated in the graph were mapped to current values using an external picoammeter. Fig.7.6 shows that the designed current mode 2A converter has the sensitivity to measure the sub-threshold currents as low as 50 f A. Fig. 7.7 compares the power dissipated by the current mode hysteretic 2A converter with the conventional first order EA converter. The average power dissipation is propor- tional to the operational frequency of the 2A converter. For small current measurements in the range of femtoamperes ( f A) to picoamperes (pA), the hysteretic 2A converter reduces the power dissipation by reducing the zero crossing switching of the comparator. The plot 112 'f 4 Channel an Order 2A Array Unit Figure 7.8. Microphotograph of the 3” order 2x4 dimensional STL system. shows that the hysteretic EA converter saves the power by more than 50% compared to the conventional EA converter at 250kHz sampling frequency. Fig. 7.7 also shows that the power efficiency of the hysteretic 2A converter improves as the sampling frequency increases. This improvement is attributed to reduced switching cycles which are controlled by the hysteresis level of the comparator. For the sampling rate of 250kHz, the conven- tional first order 2A converter’s power dissipation is 23p.W. For the same operating fre- quency, the power dissipation of a single hysteretic EA converter channel is 11 pW which accounts for 8pW consumed by the digital components and 3pW consumed by the analog components. The performance of the hysteretic 2A converter is compared with the latest reported data converters as shown in table 7.2. It can be seen that the performance of the hysteretic 2A converter is comparable with other reported ADCs. Table 7.3. Measured power dissipation of the STL system components order mixed mode 231 113 Table 7.4. Measured channel power of the 4-dimensional STL system 7 .3 Characterization of 2 x 4 Channel 3” Order Spatiotemporal 2A Learner (STL) System 7.3.1 Characterization of System Components A prototype consisting of a 2 x 4 —— dimensional STL system has been fabricated in a 0.5,um CM OS process. The size of the prototype is 3mm x 3mm and its micrograph is shown in Fig. 7.8. The active area occupied by the 4 — channel system is 2.175mm2. The input range of the system is limited to 300mV which comes from the linear range of the transconductor used for analog signal processing. The input frequency bandwidth is designed for the speech signal of 4kHz. The oversampling ratio (OSR) of the system is 32 and the system runs at a sampling frequency of 250kHz. The total power dissipation of the system at 250kHz is 1.5mW for the 4 — channel system. The power dissipation of individual components of the STL system are given in table 7.3. For an M -channel system, the power dissipation of the M th channel is given as PMod + P00 + (M - 1)(PNDC + PCNTMW (7.1) The power dissipation of each channel is summarized in table 7.4. The characterization of the 3rd order single loop single bit mixed mode 2A modulator of the STL system is not possible therefore the performance of the first channel is reported. The first channel consists of a single diagonal transconductor cell followed by the 3rd order 2A modulator. Therefore, the characterization of the modulator reflects the effect of transconductor on the input of a modulator. Fig. 7.9 shows the measured power spectral density spectrum for a 114 PSD (dB) -100 2 522223;; .= 35322213 .f 22:21.25 10 10 10 Frequency (Hz) Figure 7.9. Power spectrum of the first channel ( 1 kHz input signal) of the 3rd order STL system. lkH z sinusoidal input signal. The slope of the shaped noise in range of 4kHz to 8kHz shows the third order noise shaping. The spurious tone at the 500Hz has come from the signal source therefore the signal power of this tone is neglected from the performance calculations. The peak SN R, SN DR and the SFDR of the modulator are 53.81dB, 52.68dB and 60.72dB respectively. Table 7.5 summarizes the specification of the 3rd order ST L chip. The transconductor network performs the analog signal processing that converters the input voltage signals into currents before they are processed. In the non-diagonal cells, the reference current of the transconductor is modulated by the current DAC output to perform analog multiplication adj *xj whereas in the diagonal cell, the signal transformation is per- formed using a fixed reference current. Therefore, the transconductor is the key component of the system that may limit the system performance assuming the performance of the 2A modulator is better than that of the transconductors. In this case, the linear (constant gm) range of the transconductor defines the input range of the system. 115 1000i VBIA3=0.86V .............. ......... ...... + VBIAS=0.87V ' : - 300. +VB'AS=0-33V . ..................................... *5 -*- VBIAS=0.89V .9 2 2 3 __‘3 600 8 '9 3 2 i E i 8, 400... .............. ..;... ...... .......... ..; ..... .- O ' ; . Z 200 ........ - 0 3. i 1 r -0.2 -01 0 01 0.2 ' Diagonal cell input ' Figure 7.10. Digitized response of the transconductor of the diagonal cell with respect to the reference bias current. 1000 " —e— Diagonal cell 1 —e— Diagonal cell 2 800i + Diagonal Ge" 3 .................... *5 —*— Diagonal cell 4 D. t : . ., . . ‘5 3 3 3 z 3 g 600.. ............ .......... .............. 1.... a) i I 9 ’ Z I o . E o 400 O) .9 D 3 7' : f f 200-_%. ...... ; fuf ............. ..E ............... E ................ 3.9 0 . 1 l -0 2 -0 1 0 0 1 0 2 Diagonal cell input Figure 7.11. Mismatch behavior of all diagonal cells of the 4-dimensional STL system. The worst case mismatch variations are within 4% of the largest diagonal cell output. 116 600 A . ................. ................. 400- . ‘ ........... ......... , ....... Digitized DAC Output 200 o 500 1000 1500 2000 DAC input Figure 7.12. The non-linearity of current DAC of the non-diagonal cell of the signal transformation module Fig. 7.10 shows the characteristics of the transconductor of the diagonal cell of a trans- formation matrix A. The linear range of the transconductor is 300mV which limits the input range of the STL system. Fig. 7.11 shows the mismatch characteristics of the diag- onal cells of the 4 — channel system. The worst case mismatch seen in the diagonal cells of the 4 — channel system is 4% which is much lower than the worst case mismatch of 20% considered in the algorithmic simulations in Chapter 6.1. Similar mismatch behavior is observed in transconductors of the non-diagonal cells. The non-diagonal cells also suffer from the non-linearity of the current DAC. The designed current DAC (Fig. 6.7) is one of the simplest structures that consists of current divider network. The lack of voltage headroom to keep all transistors in saturation leads to the non-linearity in the output current as shown in Fig. 7.12. De- spite this non-linearity, this particular choice of current DAC requires a very small area (36.15amX 132nm) and consumes 0.22% of total active area which helps in accommodat- 117 Table 7.5. Measured specifications of the 4-dimensional STL system Parameters Values mmx mm X - 0 1 to 110186 ratio [0 norse 120111011 ['3th ran SSl OI] VC area a S V6 area 0 a stem ing more number of channels in a given die area. It will be shown in the next section that the reduced area at the cost of the non-linearity, offsets and mismatch are compensated by the adaptation and learning embedded within the STL system. The next section shows the system functionality of signal compression, adaptation with respect to device artifacts in the system and the reconstruction of signals using the low bandwidth digitized output data of the STL system. 7.3.2 System Adaptation DC RESPONSE OF THE 2nd CHANNEL The DC response of the 2""l Channel is used to show the working principle of the STL system adaptation and learning. For the DC response, only first 2 channels from Fig. 6.1 are used. The reference channel 1 is applied with constant 200mV DC input at X1 and the DC input of the second channel X 2 is varied in steps of 5mV for the total range from —200mV to +200mV. For this 2-dimensional system, the 2-dimensional transformation matrix A has only one non-diagonal element on as shown in Fig. 6.1. All 11-bits of the non-diagonal element 021 are assigned to 1 (Digital value = 2047) to have a uniform 118 ................................... -*-X2=-25mv +X2=25mv ->-X2=—50mv +X2=75mv ; . i -A-X2=-75mv ...... +X2=100mV .. i i : -v-x2=-100mv : f 3 +X2=125mV 350 ....... i-O-X2=—125mv ' i - -I—x2=150mv -l-X2=-150mV —o—X2=175mv _ . , -o-X2=-175mv 2 4 6 8 10 Channel 2 Samples Channel 2 digial output A O Figure 7.13. Running average of the modulator output of the second channel over 1024 cycles initialized condition. The system is run for 20000 clock cycles and the data is recorded. The system learning is shown with the help of modulator output of the second channel and the adapted value of a21. Fig. 7.13 shows the running average of the 2nd channel modulator output averaged over 1024 cycles. As the system adapts, the average value of the modulator output of the 2nd channel goes to zero that shows the signal de-correlation and the removal of signal redun- dancy from the second channel. The non-diagonal matrix element am of the 2-dimensional transformation matrix A stores the de-correlation coefficient. The discrete time adaptation process given in Eqn. (4.14) of the non-diagonal element on to de-correlates signals is shown in Fig. 7.14 for varying DC inputs. The a21 starts with initialized preload condition and then settles down to a value that completely removes the redundancy from the second channel signal. The stabilized value of the de-correlation coefficient am after 10000 adaptation cycles for the given DC inputs are plotted in Fig. 7.15. This response shows that the system learns 119 200 ‘ ............ ' ............... X i=2oomv | x2: 25mv ' ‘ I -¢—X2=50mV .‘3 +X2=75mV % 1500 +X2=100mv 2.} +X2=125mV S -I-X2=150mV § 1000L :0 . —O—X2=175mV a ' ‘0- 'o - - =- g narrate-s: - xz 25'“ g) :‘0-09-0-0'6-0-0'0-0' ' -I-X2=-50mV =5 XV“? V+V 7-7-V' vw- _ - Q- X2=-75mV Ic #A-AqA-AA-A-A AqA- _ o 500 ........ ......W -7-x2--100mv Z * ‘+"‘+“ ' . ‘ .. ** ** - - ' -X2--125mV i **.'*‘**'*‘ . -<-x2=—150mv ‘ : 3-*-X2=-175mV 5 10 15 20 Figure 7.14. Discrete time behavior of the decorrelation coefficient a21 2000 . 1 Channel 1 input = 0.2V g I 1500 - 1000 500 Non-diagonal Adapted ooeffient -8.2 -0.1 0 0.1 0.2 Channel 2 input (V) Figure 7.15. Adapted value of am after 10000 cycles for DC input signals 120 Non-diagonal demixing coefficient i o 1. o 0 i 400. Cd ....... ......... Z ........... _ 200 0 50 100 150 200 250 300 350 Phase shift Figure 7.16. The adopted value of the ale-correlation coefficient on as the phase is varied from 00 to 360° the non-linearity of the DAC shown in Fig. 7.12. The adapted value of the decon'elation coefficient am also accounts for the mismatch and the offsets in the two channels which are seen through the modulator output shown in Fig. 7.13. The average value of the modulator output of the second channel always goes to zero irrespective of the mismatch, non-linearity and the offset in the system which confirms the stability of the STL system under worst case saturation conditions of the 2A modulator used in the STL system. AC RESPONSE OF THE 2” CHANNEL The AC response of the system shows the learning and adaptation with respect to the mag- nitude and phase of the input signals. The AC response of the 2-dimensional system is shown in Fig. 6.1. The signal X1 at channel 1 is treated as the reference signal and the signal X 2 is varied in phase as well as magnitude. The correlation between signals X1 and X 2 is changed by varying the phase difference between the two signals. In the experimental setup, the phase of the second signal X2 is varied in steps of 100 :t 2". The error of i2” 121 2000 f . a E 9 'I'X2=0.8*X1 .. J’s § 3 -o-x2=o.9*X1 c I ‘ . . Q) ‘ . I ; ; a S \ ; E1500 .......... .s‘""§ ................................................. a as o S‘ .8 ‘ I j 31000 .................... ........ ‘A‘. ................ ............ '0 ~ fi. . < r 1‘ 3 E I f ‘ f (U f I . S. 5 ~ \9.‘__ .§ _ i ’0- o . . 1 0 50 100 150 Phaseshift Figure 7.17. The adapted value of the decorrelation coefficient 0.21 as the magnitude and the phase of the second signal 932 are varied comes from the cumulative effect of phase measurements performed on the oscilloscope. Fig. 7.16 shows the adapted value of the de-correlation coefficient am of 2 — dimensional transformation matrix A as the phase is varied from 0° to 360°. The AC response shows that the system adapts with the non-linearity of the current DAC. It also shows the symmetry of operation and thus poses no limitation on the maximum tolerable phase. The adapted value of am is plotted in Fig. 7.17 as the magnitude of the second chan- nel is varied. This adaptation also reflects the learning of offsets and mismatch observed in 2 channels. In vector space analysis, the adapted value of de-correlation coefficient 0.21 is consid- ered as the projection of vector X 2 on vector X1. Therefore, two signals are considered correlated if they are completed in phase (0°) or out of phase (180°). In these 2 cases, the residual power left on the second channel is the minimum which is seen in Fig. 7.18. The signal power is reduced by more than 50dB when 2 signals are correlated. As the phase difference between two signals is increased, the uncorrelated signal of the second channel 122 V O 0'0" ? §.$I+,3.:&‘~é 60 ...... f! ....... ' E .......... ‘....\ ..... A f -I-X2=O.8*X1 § I, 3 I -o-x2=o.9*x1 i. b so“! ............. .......... s \l 8. to i i 'c i ‘ i 0 ' ' ' l 30 .................... . ................. . .......... g 20 ; i 5. 2 0 50 100 150 Phaseshift Figure 7.18. The residual power left on the second channel as the phase difi’erence (correlation) between the two signals is varied from 0° to 180° Input signal (mV) ~150 Time (s) Figure 7.19. Characterization of the 3” channel is performed by 3 sinusoidal signals :31, m2 and 933. The phase difi’erence ($12) PH I (1, 2) between signals 2:1 and 2:2 is kept constant and the phase difi’erence (4513) PH I (1, 3) between signals 9:1 and x3 is varied. 123 - u - PHI(1,2)=20 -o- PHI(1,2)=1O 1.5 ........ ...... Coefficient ratio 0.5 0 50 100 150 PHI(1,3) Figure 7 .20. The ratio of decorrelation coefficients am and (132 with respect to the phase difiference between signals X1 and X3 is shown with the increased residual power left on the second channel. AC RESPONSE OF THE 3rd CHANNEL To understand the multidimensional response in more details, the 3-dimensional structure from Fig. 6.1 is tested. As shown in Fig. 7.19, the parametric response of the 3rd channel is obtained by keeping the phase difference ( 4512 also noted as PI-II(1,2) ) between X1 and X 2 constant and varying the phase difference ( $13 also noted as PI-II(1,3) ) between Signals of the first channel X1 and the third channel X3. Fig. 7.20 Shows the ratio of adapted values of non-diagonal elements am and a32 which correspond to de-correlation of signal X3 with respect to Signal X1 and X 2 respectively. For the given PH I (1, 2)or12. The drops in the signal power of the third 124 60 3 . 350 .............. 3 i g) - 43- - PHI(1,2) = 10 DC: —6— PHI(1,2) = 20 ('0' 40... .. ............................ I l 0 30.. .. b a - . 20 L i l O 50 100 150 PHI(1,3) Figure 7.21. The residual power left on the 3” channel with respect to the phase dtfi'erence between signals X1 and X3 (a) (b) (c) 0 ' 0 Iszzszzz : 0 ; :::":° 5: E a E B E o o o E -50 ......... g)- _50 ................. g _50 ....... .- N <0 5 33 5 Frequency (Hz) Frequency (Hz) Frequency (Hz) (d) (e) (f) O O O a a; a o E o (é) -50 g)- _50 8 -50 .............. ‘- N (0 ES 5 5 -100 33333333 ; _100 ......... . _100 ......... ; 1o2 104 102 10“ 102 104 Frequency (Hz) Frequency (Hz) Frequency (Hz) Figure 7.22. Signal power in each channel before and after adaptation 125 channel at points (a) and (b) Show that the signal of the third channel gets maximally de- correlated from the signals :51 and $2. The phase values of (a) and (b) vary based on the correlation between signals 3:1 and 222 which is Shown by PH I (1,2) in Fig. 7.21. The un-correlated signal of the third channel appears as a residual signal which increases with increase phase difference PH I (1, 3) between Signals x1 and 3:3. The attenuation of the correlated Signals shown in Fig. 7.21 is also verified with the frequency response of the STL system which is discussed in the next section. 7.3.3 Signal Decorrelation The signal de-correlation performed by the system is shown with the help of the frequency response of the STL system. The FFT plots of the digital outputs of 3 channels of the S TL systems are used to Show this result. A single sinusoidal input is applied to all chan- nels and the output is observed before and after adaptation. Plots (a),(b) and (c) in Fig. 7.22 Show the power spectral density of all 3 channels before learning and adaptation. In this configuration, only diagonal elements are enabled therefore the digital outputs d,- of the EA modulators represent signals 3;,- = 2:,- at the respective channels. Plots in Fig. 7.22(d), (e) and (f) Show the system response of 3 channels after leam- ing and adaptation. System learning and adaptation with respect to signals and device artifacts (mismatch, offset and non-linearity) are performed through non-diagonal cells of the system which store the adapted decorrelation coefficients aij in the digital form. The modulator output d,- represents the digitized output of the signals given by Eqn. (6.1). The signal de-correlation is seen in the 2nd and the 3rd channel where power spectral densities of those channels are reduced by 50dB. Therefore, it is seen that the STL system removes the cross—channel redundancy from all modulator outputs dis. The Signals are reconstructed by using the non-redundant digital outputs from the lower dimensional signals and the signal transformation matrix A which will be discussed in more details in sub-section 7.3.4. In this example, the redundant channels 2 and 3 can be 126 A70 ............... ............ “3 <>o—o°~e-9-9'°‘°‘°'?'°-6-o-e-o-e-oo 60- ...................................................................... O 50 100 1 50 Phase shift Figure 7.23. Reconstruction signal power of the 2'” signal with the help of signal transformation matrix A and the digitized modulator output of the first channel. neglected for signal reconstruction. This reduces the output data bandwidth and the signal processing bandwidth of the system. The original signals shown in Fig. 7.22 are recon- structed using the modulator output of the first channel d1 and the signal transformation matrix A. By using the output of the first channel, the output data bandwidth and the sig- nal processing bandwidth are reduced by 75%. Similarly, by selectively shutting down the modulators, the power savings up to 40% is obtained. The power saving techniques for the given framework is not discussed in this work and will be explored in the future direc- tions of this work. So far, we have seen the signal de-correlation and the data compression, performed by the system. In the next section, signal reconstruction with the help of only non-redundant channel information and the de-correlation coefficients is discussed. 7 .3.4 Signal Reconstruction The STL system is configured either as the conventional multichannel 2A converter array with no adaptation or the STL system with adaptation. While switching between these two modes, the temporal phase-magnitude information is lost therefore the reconstruction error 127 (D O [—-— Phase(x1f,X2)=O] ............. ........................................................................ N 00 O r ..................................................................... O l N O .................................................................... Reconstructed signal power(dB) OD g 01 0') ..n O ................................................................... O 0 50 100 1 50 Phase shift Figure 7.24. Reconstructed signal power of the 3” signal with the help of signal transformation matrix A and the modulator outputs of first two channels. is not used to characterize the signal reconstruction. The fidelity of the signal is measured by measuring the peak power and the temporal information of the signal. The reconstruc- tion of the 2nd and the 3rd channel are shown in Fig. 7.23 and Fig. 7.24 respectively. For the 2nd channel, the signal reconstruction is performed by using the de-correlation coeffi- cient (L21 and the modulator output of the first channel d1 while that of the third channel is performed by using the de-correlation coefficients 031, 0.32 and the lower dimensional modulator outputs d1 and d2. Fig. 7.23 and Fig. 7.24 Show that the reconstructed signals maintains the signal power within 3dB error thus emphasizing the compensation of device artifacts and Si gnal decorrelation. In the next chapter (Chapter 8), acoustic source localization with the STL system is shown. The designed system has the resolution of 4° for the dynamic range of 90° and for the sub-dynamic range of 50°, the bearing angle resolution of 2° is achieved. 128 CHAPTER 8 STL System Application: Acoustic Source Localization Acoustic sensing is one of the areas where micro/nano scale sensors are integrated with promising breakthroughs. Microphone arrays (3 x 3) of the order of 100nm [48] are now available for speech recordings. Such compact acoustic sensor arrays are deployed in net- works [87] for source localization which finds many applications in security, surveillance and law enforcement [88]. The source localization based on such micro/nano scale micro- phone arrays pose significant challenges and difficulties due to fundamental limitations im- posed by the physics of sound wave propagation [89]. The acoustic signals (100 — 20kH z) have the minimum wavelength of S 3.4cm, therefore the miniaturized arrays having sub- wavelength placement of microphones suffer from far field effects [90]. Therefore, the small phase difference along with the signal dispersion across the miniaturized sensory array make received signals highly correlated. The source localization of correlated signals has been reported by several groups [91, 92] based on the coherent as well as the non-coherent methods. The non-coherent methods such as closest point of approach (CPA) [92] are not sensitive to synchronization but suf— fers from from the sensor mismatch and the sensor response due to a distance between the source and the sensor. In contrast to non-coherent methods, the coherent methods poses stringent constraints on synchronization as they are based on the arrival time differences 129 --.-.n-.--.-...-..--..-p Figure 8.1. Far field recording of miniaturized microphone array Figure 8.2. 2-D projection of far field acoustic signal on miniaturized microphone array 130 of the acoustic signal to sensors. The coherent methods make use of signal correlation in estimating the bearing of the sound source with respect to miniaturized microphone array. Several algorithms based on cross correlation (CA) [93] - [94], cross correlation deriva- tive (CDA) [95], stereausis network [96] and spatial gradient algorithm [97] are proposed. The Spatial gradient algorithm is shown to give the best accuracy and its implementation requires a sampled analog architecture. Recently it is shown to implement the least mean square (LMS) method for resolving acute differences in the analog acoustic signals. How— ever, the approach is not scalable to larger arrays as it requires direct measurement of higher-order gradients. The SA modulators have robust architecture which make them one of the most accurate analog to digital converters. The proposed STL system learns to decorrelate input signals and employs 2A modulators for digitization. Therefore the STL can offer the accuracy requirements of source localization. The hardware test results in Chapter 7 have shown that the coefficients of signal transformation matrix track the phase difference between signals. This phase tracking property of the proposed STL system is employed for coherent acoustic source localization. In the next Section 8.1, the far field acoustic model is described. 8.1 Far Field Acoustic Modeling In literature far-field acoustics is extensively Studied within the context of array processing with plenacoustic models [90]. A simplistic model is described here which has been used for miniaturized microphone array. For modeling purposes, consider a sensor array shown in Fig. 8.1 that consists of four recording elements. The inter-element distance (2d) is much less than the wavelength of the acoustic signal of interest (audio range of 100Hz — 20kHz). Such recorded signals of the microphone array can be approximated using far field model [90]. For the miniature sensor array, the distance D ( Refer 2-dimensional model in Fig. 8.2) to the source from the center G of the array is assumed to be much larger than the inter—element distance (2d << D). Therefore, the acoustic Signal wavefront 131 is considered planar as it reaches the microphone array. AS shown in Fig. 8.1, the signal $(pj, t) recorded at the jth microphone located in 3 -- D position vector, pj = (2:, y, z), with respect to the origin (center G of the array) as the source S located in the far-field with a azimuth angle of 0. The signal at the center G of the array is assumed s(t), therefore the signal :5 j (p j, t) at microphone pj of microphone array is written as mflpjat) = 0(Pj)s(t — T(Pj)) ' (8.1) where a(pj) and 7(pj) denotes the attenuation and delay for the source s(t) respectively, measured relative to the center of the microphone array. Eqn. (8.1) is expanded using Taylor’s series as cap,» 0., 2 up], t)=a(Pj)Z—— (t) (8.) Under far-field conditions, it is assumed that a(pj) z a is constant across all the rnicro- phones and the wavefront delay r(pj) is approximately linear in the projection of p j on unit vector u pointing towards the source 7(pj) = —u .pj (8.3) where c is the speed of sound wave propagation. Ignoring the higher-order terms of Taylor series expansion, Eqn. (8.2) is expressed as :L‘(pj, t) % as(t) — ar(pj).S(t). (8.4) The 2 — D view in Fig. 8.2 of the microphone array setup (Fig. 8.1) Shows the received signal S at each microphone Mi, (2' = 1, 2, 3,4) with delay Tpi. The Signal at the center of the microphone G is assumed as a reference signal s(t), therefore a signal xpi, (i = 132 1, 2, 3, 4) received at microphone M,- is written as mp1 2 a s(t — Tpl) = a (3(t) — s'(t)%i cos 6) d £13132 2 s()t—Tp2 )=a(s(t )---s(t) Csind) $133 = :as(t+rp3)=a(s() +s' (t)—cos€) 33124 = s(t + rp4)- — a s(t )+ s’( t.()— sin 6) (8.5) The signals 3:12,, (i = 1, 2, 3, 4) are visualized as :1: p,- = 330 M + zed,- (8.6) where signals $p2', (2' = 1, 2, 3, 4) Show the common mode signal 1120 M = 3(t) and the differential Signal ed,- at each microphone Mi. Therefore, signals received at microphone array Show significant amount of correlation due to common mode signal 1:0 M = s(t). The decorrelation condition of STL system performs the Signal transformation Y = AX such that residual signal 3),; left on channel 2' is uncorrelated with respect to rest of the sensor signals xj, j 75 2'. The differential Signals ted,- obtained by eliminating common mode signal 1230 M from signals mp, improves the resolution range of STL system. Therefore, with differential input signals 3rd,, the output signals after Signal transformation are given as - y} - - 1 0 0 0 . - (Edi - .112 = 021 1 0 0 Ivdz (8.7) 313 031 a32 1 0 W3 _y4‘ [041 0420431] _md4_ where y, represents the transformed signals and the lower triangular matrix A stores the signal transformation coefficients. The residual energy of redundant channels minimizes with signal transformation and ideally goes to zero. Solving for the decorrelation condition 133 y,- = 0, we get = arctan (M) (8.8) Eqn. 8.8 shows that coefficients of signal transformation A give us the bearing angle 6 of sound source with respect to microphone array. The bearing estimation in Eqn. 8.8 assumes a perfect cancelation of common mode signal (330 M = s(t)) from all signals which is hard to achieve in real prototype. Due to mismatch in the sensor placement and the microphone responses, the ideal center of microphone array Shifts away from the physical center G shown in Fig. 8.2 which adds the mismatched signal As(t) to the common mode signal s(t) assumed at center G. Therefore, with additional mismatch offset As(t), the signals 2:12,, (i = 1, 2, 3, 4) received by the microphones are given by xpl = a (s(t) — 3'05); cos (9 + As(t)) .1in = a (3(t) — s'(t)C—: Sin9 + As(t)) '13p3 = a (s(t) + 3,00% 0056 + As(t)) $94 = a (s(t) + s'(t)-g sin0 + As(t)) (8.9) Applying the signal transform of Eqn. (8.7), and solving for decorrelation condition, the bearing angle is given by — 2 — a — 1 6 2 8mm ((131 a21031 21032 ) (8.10) am + (121032 + 1 The estimated bearing angle 0 in Eqn. 8.10 compensates the component mismatch re- sponses of the microphone array. This compensation technique shows that only three microphones are sufficient for bearing angle estimation used in source localization. The theoretical formulation of bearing angle estimation is proved with hardware results shown in the next Section 8.2. 134 Figure 8.3. 4x4 surface mount MEMS SiSonic microphone (Knowles Inc.) array. Each microphone is separated by a distance of] cm. ) ; : fl .9 C C I I s s O O U U “524i. .......... ‘5 035 .9 .9 ‘6 *6 Cr : n: , : ’V 1 02¢ i ‘0 so 100 ' $60 200 240 Angle Angle Figure 8.4. 10° resolution obtained from the 4x4 Microphone array 135 8.2 Measurement Results In this hardware result section, the theoretical results in Section 8.1 are shown with hard- ware prototype of STL system. Two sets of experiments are conducted with two different sets of microphone array. The first microphone array directly captures the signals without suppression of any common mode signals where as the second microphone array is de- signed with common mode suppression circuit so signals obtained from these microphones gives us the differential signal from each microphone with respect to the averaged common mode signal of all microphones before they are processed by STL system. 8.2.1 Bearing Angle Estimation of Miniaturized Microphone Array The first set of experiments are canied out to Show that the STL system tracks the bearing angle of source signal by capturing the signals 22p,- received by microphone array without elimination of common mode Signal $CM- These experiments are carried out with mi- crophone array Shown in Fig. 8.3 which deploys surface mount omnidirectional M EM S S iSonz'c microphones (K nowlesSPOlOBBE3). It has the sensitivity of —22dB at lkHz and the Signal to Noise Ratio (SN R) of 55dB. These microphones form a 4X4 grid with a separation distance of 1 cm. The tonal source used for the experiment is placed at a distance of 1772. from the microphone array. The microphone array is kept fixed and the acoustic source is moved in steps of desired angle. The signals obtained from microphones are filtered with second order Sollen-Key low pass filter before they are sent to STL system. Three microphones of microphone grid are selected for STL system inputs. The de-correlation coefficients of the 3rd channel am and cm are recorded and their ratio is plotted as the source moves in steps of 10° angle. The 10°-resolution plot using these M EM S microphone array is shown in Fig. 8.4. With 10° resolution, the localization is seen to be performed in 2 regions which gives the dynamic range for this setup of 200°. 136 C T, Cr, C T3 ET, ' v f Figure 8.5. The schematic of the pre-processing circuit used to separate the common mode and drferential mode signal of each microphone 8.2.2 Bearing Angle Estimation of Miniaturized Microphone Array with Common Mode Suppression The Signal transformation in Eqn. (8.7) takes the differential Signal xd,,i = 1, 2, 3, 4 of the microphone array which requires an attenuation of common mode signal 2:0 M from the received signals mpi. Fig. 8.5 Shows the model of the condenser based microphone with a diaphragm input M I C, that drives the FET transistor T,. The circuit presented in Fig. 8.5 attenuates the common mode signal from all sensor signals of microphone array to give differential Signals V,- as Vi = -9m—T,-(VMICt — VCM)R/i (8.11) where VC M is the common mode signal across all microphones. This common mode signal is obtained by equating the current drawn from R5 and currents drawn from R1....R4. 4 Vdd - VREF E :Qm—Tz-(VMICz’ — VCM) = R5 (8.12) i=1 Therefore, the common mode voltage VG M is given by 4 ‘_ V. ,' V —V , VCM= 22.1 MIC: + dd REF (8.13) 137 Figure 8.6. (a) A 4—micmphone array/grid consists electret condenser microphone placed at a distance of] cm from the center of the microphone array. (b) The test setup shows the tonal source located at a distance of] m from the microphone array. where gm. is the average lransconductance of transistors T,. This pre-processing circuit shown in Fig. 8.5 gives the differential Signal V;- (atdi) by eliminating the common mode signal VCM (530M) from the sensor output. These differential signals V, are applied to STL system which follows Eqn. (8.7). For source localization with common mode suppression, the microphone array is formed with the omnidirectional electret condenser microphones (Knowles Inc). This condenser microphone has the sensitivity of —42dB at lkHz and a Signal to Noise Ratio (SN R) of 55dB. The 4-microphone array is designed with each condenser microphone is placed at a distance of 1 cm from the center as shown in Fig. 8.6(a). The far field effect is generated by keeping the acoustic source at a distance of 1m from the microphone array. In all experiments, the microphone array position is kept fixed and the speaker is moved in steps of desired angle. The source localization is carried out with three microphones which are shown to be sufficient in Eqn. 8.10 to compensate mismatch response of the micro- phones. For bearing angle estimation 0 of sound source, the decorrelation coefficients (121, (131 and a32 are required therefore only 2 channels (channel 2and 3) are run while others are shut down. 138 1500 7 1400 ' 1300 a 1200 1100 1000 900 800 , ; . _ p 700,. + . 6000 2‘0 410 61) so Source Angle (0°) Coefficient a Figure 8.7. Coefficient 021 tracks the bearing angle 0 of the sound source 00 ‘1 r O) -h 01 Bearing Estimation Output 0) C I.- s: 3" h i: i r 0 20 40 60 80 Source Angle (9°) Figure 8.8. 4° resolution is achieved by eliminating the common mode signal from all microphones. The pre-processing technique achieves the total dynamic range of 90° angular movement of the speaker. 139 Bearing Estimation Output 1 I I I l I I O 5 10 1 5 20 25 30 35 Source Angle (9°) Figure 8.9. For small dynamic range of 34°, a resolution of 2° is achieved with the help of common mode suppression technique 1" 00 NNN N«bO) Bearing Estimation Output N 1.8 1.6 ' 1.4 ' C 0 20 40 60 80 Source Angle (9°) Figure 8.10. The common mode suppression and the mismatch compensation of microphone re- sponses improve the bearing angle response. The non-linearity is suppressed for the given input dynamic range of 90° at the resolution of 4°. 140 1 I" or I N & I I ...............................v.................. .... .. ............... Bearing Estimation Output N is: A N v r l _s m 0 10 20 30 40 50 Source Angle (0°) Figure 8.11. The common mode suppression and the mismatch compensation of microphone re- sponses improve the input dynamic range to 50° at the achievable resolution of 2°. The tracking of the bearing angle 0 of the sound source given in Eqn. (8.8) is validated with the help of designed S TL system. It is shown that the signal transformation coefficient 021 tracks the bearing angle of the sound source. This is verified by recording the non- diagonal coefficient (121 of signal transformation A as the signal source is varied in steps of 4°. The recorded coefficient 021 is plotted in Fig. 8.7. This plot shows that the response of 0.21 resembles the tan function although the response has the lower and the upper bounds because of the finite resolution of up-down counter. Similarly, the tracking of the bearing angle is estimated using the coefficients c131 and 032 of the third channel of STL system as shown in Eqn. (8.8). The monotonic response in Fig. 8.8 shows the tracking of source angle with coefficients 0.31 and 0.32 of the third channel. This phase tracking response of Eqn. (8.8) with coefficients 031 and 032 shows 7.3% lesser deviation from the plotted mean values compared to the response obtained from 021. This smoothing is possible because of the first order differentiation of mismatched signal As(t) in addition to the suppression of common mode signal s(t). With the bearing angle tracking Shown in Eqn. (8.8), Fig. 8.9 141 shows that the STL system has the bearing angle resolution of 2° for the input dynamic range of 34°. The next set of experiment Shows that with the help of only two out of four chan- nels of the 4-dimensional system, the signal transformation coefficients 021, 031 and 032 can compensate for the average mismatch As(t) of the microphone response in addition to suppression of common mode signal s(t). Fig. 8.10 shows the improved response of the bearing angle estimation given by Eqn. (8.10) compared to one given by Eqn. (8.8). Fig. 8.10 shows that Eqn. (8.10) suppresses the weights of individual coefficients to re- duce the nonlinearity of the estimation response. This claim is also supported by the fact that the standard deviation of the estimation output Shown in Fig. 8.10 is reduced by 73% in Fig. 8.10. The monotonic response in Fig. 8.11 shows that with the compensation technique given in Eqn. (8.10), the dynamic range of the bearing angle estimation of the STL system is improved from 34° (Fig. 8.9) to 50° at the achievable resolution of 2°. Thus, this novel EA learning of STL system can track the bearing angle of the sound source. Such bearing angle estimation finds applications in defense, security and surveillance system where the objective is to find the angular position of the subject of interest. Similarly, in miniaturized hearing aids, this system can be used for adequate beamforming for improving the quality of source signal buried in the noise. 142 CHAPTER 9 Concluding Remarks and Future Directions 9.1 Summery and Concluding Remarks In this work, a system level approach that combines the machine learning algorithm with oversampling analog to digital converter is presented. This approach forms a min-max opti- mization framework that integrates the manifold learning with multichannel EA converter to give a spatiotemporal EA learner (STL) system. This algorithm is designed for high density sensor signals which are found highly correlated. The manifold learning embedded within the algorithm is shown to decorrelate signals and eliminate the signal redundancy across the channels. Therefore, STL system achieves the signal de-correlation along with data conversion at lower digital data bandwidth unlike the conventional multi-channel data acquisition approach of analog to digital conversion followed by data processing. The STL system produces two digitized Streams that consist of spatial manifold information (signal decorrelation coefficients) and the uncorrelated multichannel data, thus eliminates the need of additional digital signal processing for information extraction. Thus, the presented ar- chitecture directly samples the desired spatial information similar to analog to information converters. The beauty of S TL algorithm is the robustness and the inherent Stability which make it very attractive to realize in hardware. The algorithm and the hardware prototype are Shown to adapt and compensate for device artifacts of mismatch, offset and non-linearity. 143 These errors are compensated in analog domain which employs dynamic biasing technique for analog matrix vector multiplication for manifold learning through signal transforma- tion. The hardware results of STL system realized with the third order EA modulator framework Show that the framework is generic and can be extended to stable higher order oversampling modulators. The spatial manifold learning of STL system is successfully ap- plied for neural signal processing in brain machine interface and bearing angle estimation of source localization. The designed hardware prototype interfaced with the miniaturized microphone array shows the angular resolution 2° for the dynamic range of 50° of angular movement of acoustic source. The presented architecture is generic and can be applied to wide range of applications such as ”smart” hearing aids, high-density MEMS sensors, electro-chemical, bio—molecular sensor arrays and miniaturized RF antenna arrays. 9.2 Future Directions 9.2.1 Freedom of Hardware Realization The architecture presented here is one of the solutions to design hardware for the given algorithm as a proof of concept. Primary source of constraint that is driving this design is the computational simplicity in analog domain, therefore the current mode analog ma- trix vector multiplication is designed. This current mode design is shown to reduce the component size to increase the dimensionality for the given die area. This increase in the dimensionality comes at the cost of limited dynamic range and S N R of the current mode design. These limitations can be overcome with voltage mode circuit design at the cost of reduced dimensionality for the given die area. Similarly, increase in the order of the 2A modulator framework improves the S N R and so the resolution of the system at the cost of degraded system stability, input range and increased die size. In this work, the hardware realization of the STL algorithm is realized with single loop single bit modulators but it must be noted that the algorithm is compatible with higher order modulator frameworks 144 such as cascade, MASH with single bit or multi—bit quantizer. Therefore, the designer is given the flexibility to choose the STL framework that suites the given specifications. 9.2.2 Power Optimization and Resolution Enhancement We have seen that the STL system decreases the residual Signal left on channels with correlated signals. This residual signal left on the redundant channel is also a function of resolution of a BA converter of STL system. With increase in the signal correlation, the residual signal left on the channel reduces below the quantization range of a single LSB value. Therefore after initial adaptation, the system resources are spent on unresolvable residual Signals which decreases the power and resolution efficiency of the system. The power optimization of STL system is an interesting problem which needs to be investigated in order to cater to ultra-low power requirements. Selective shut down of redundant channels would save the power dissipation of system without loss of information. For example, in 4 — channel STL system having highly correlated input signals, power savings of 75% can be achieved from the 2A converter array. Although such selective shut down of modulators of redundant channels looks attractive, its effect on the overall stability of the system and the adaptation process needs system evaluation. The unresolvable residual signal can be further resolved by employing the sub-ranging technique after initial adaptation. The sub-ranging of reference signals of EA modulators increases the dynamic range of the system. This improvement in the dynamic range is as- sociated with the resolution enhancement and therefore more precise signal decorrelation. This sub-ranging technique is associated with increased adaptation time and stricter global stability constraints. The sub-ranging of reference signal after successive adaptation steps also make the signal reconstruction process a piecewise function. Therefore, even though the sub-ranging technique looks attractive, its suitability requires further investigation. 1 45 APPENDICES 146 APPENDIX A Derivation of Mathematical Models of the 8 TL Systems A.1 Optimization Framework of the STL System An optimization framework for deriving the S TL system with EA converters is introduced in chapter 4. It is assumed that the inputs of the STL system are M dimensional vector x 6 RM where each dimension represents a single channel of a multi-channel 2A converter array. It is also assumed that the vector x is stationary with respect to discrete time instance n which is a valid assumption for an over-sampling data converter. A linear transformation matrix and a regression weight vector are represented by A 6 RM XM and w 6 RM respectively. Consider the following optimization problem mvin f(w, A) (A.1) The aim of minimization in A.1 is to determine the form of matrix A which denotes the family of linear transformations spanning the signal Space. The aim of optimizing for A is to a find multi-channel signal configuration that is maximally separated from each other i.e. to obtain a maximally de-correlated multi-channel signals. Even though several forms of matrix A = [cu-j] can be chosen, in this particular case, the matrix A is chosen to be a lower triangular matrix such that 0,-3- = 0;i < j and (1,-j = 1;1’ = 3'. By making the transformation matrix A to be a lower triangular, it is made sure that A is invertible in order to reconstruct 147 the signals. The lower triangular signal transformation doesn’t affect the first channel and therefore it is used as a reference channel. The minimization function given by A.l leads to finding of cross-correlation coefficient terms aij that eliminates the redundancy across the signals. This can be written as a min-max optimization where an inner optimization performs the analog-to-digital conversion, where as the outer loop adapts to find the linear transformation matrix A so as to maximize the margin of separation between the respective Si gnal space. This can be denoted by the following equation: max (min f(w, A)) (A2) 02-31%] W The expression A.2 implies that the function A.2 consists of 2 simultaneous processes. The first process minimizes the total energy of the function f and the second process maximizes the de-correlation of input signals through linear transformation matrix A. The min-max optimization function given in A2 when solved using a specific form of regularizer to reach the solution leads to the architecture proposed for the STL system. In the proposed STL system, the L1 regularizer is used because the recursive steps required to reach the solution perfectly fits with the modulation steps of the 2A converter. Therefore, the optimization function A.2 using L1 regularizer is written as f(w, A) = leTl — wTAx (A3) 1 represents a column vector whose elements are unity. The cost function in Eqn. (A.3) consists of two factors: the first factor is an L1 regularizer which constrains the norm of vector w and the second factor that maximizes the correlation between vector w and input vector x transformed by the linear transformation matrix A. To ensure that the optimization problem in Eqn. (A.l) is well defined, the norm of the input vector ||x||<>0 g 1 will be assumed to be bounded. The closed form solution to the optimization problem in Eqn. (A. 1) can be found to be w* = 0 as shown in Fig. 2.8. In the following three section, a 2- dimensional model of the S TL system is developed using the first order, second order and the hysteretic EA converter. The previous assumptions and necessary conditions used for 148 deve10ping the 2-dimensional model of the S TL system are also true for the M—dimensional STL system. Therefore, the model expressions for the M—dimensional STL system are derived by extending the model expressions obtained by the 2-dimensional system. For the 2-dimensional STL system, a linear transformation matrix A is given by A=(a'11 0 ) (A.4) 0'21 (122 A 2-dimensional input vector x and a regression weight vector w are represented by a: = ( $1 ) and “32 (A5) to: ( wl 1122 ) Therefore the function f (w, A) given in A3 for a 2-dimensional space is written as f = |w1| + lwzl - (101331 + 02171125131 + 102232) (A6) 149 A.2 Mathematical Modeling of the First Order STL System The min-max optimization criterion given in Eqn. (A.3) Shows that the inner optimization performs the analog-to-digital conversion (proved in 2), where as the outer loop adapts the linear transformation matrix A so as to maximize the margin of separation among signal spaces. A first order STL system is shown in Fig. 4.2 where the inner optimization is performed by the first order 2A converter. The adaptation of a linear transform matrix A is performed using the gradient ascent rule to maximize the signal separation whereas the internal state to is updated using the gradient descent rule to minimize the energy for stabilizing the system. The internal state w is updated using the gradient descent rule with the first order approximation in an optimization framework. The update rule for internal state in is given by w[n] = w[n — 11— nif— (A.7) 0w (N—l) Gradients with respect to tal and 102 are given as 5f m —- 3971014) — 1171 5f (Tin—'1 - d1 — $171 0 a—f- = 3971002) — (021331 + 392) mg 3 8f =d2—a21931—1‘2 ”wz where sgn(’wm) is represented by the digital bit dm. ”Therefore, the gradient updates for tal and 102 are given as 2L11[N] = w1[N — 1] — (d1[N — 1] — $1[r’V]) (A.8) 102 [N] = 1ng — 1] — (d2 [N — 1] — 0.21 [N _ 11931 [N] — x2lNl) (A9) A 2-dimensional first order ST L system is shown in Fig. 4.3. The recursion Eqn. (A8) and Eqn. (A.9) using the gradient descent rule give the states of an [N] and 11:2[N] at the 150 time instant N. Eqn. (A8) is a recursion equation of a first order 2A converter where input Signal is $1 and the digital output is (11. By adding the recursion terms of Eqn. A.8 up to N cycles, the closed form for wl (N) is obtained as follows N N—l wl[N] = 101 [0] + Zen] — Z d[i] (A.lO) i=1 i=1 101(0) = 0 be the initial value stored on wl and w1(N) is the finite residue left on the integrator 101 of a 2A converter after N cycles. Therefore .131 is given as N N—l lelz'l = Z dllil (A.ll) i=1 i=0 In over-sampling data converters, the input :1: is assumed constant for an over-sampling ratio of N, therefore the input at is represented by the average of digital output of the first order 23A converter which is given by 1 N—l 1'1: N .23 d1[z'] (A.12) The digital output d2 of the first order 2A converter in Eqn. (A9) is obtained when input is a linear transformation of input signals x1 and 1172. Elements of linear transformation matrix A are updated using the gradient ascent rule that maximize the de-correlation between two input channels x1 and :52. The update rule for elements of A follows a gradient ascent step given by aijLN] = atj [N — 1] + k5); (Iv—1) (A.l3) where h is the step Size constant. Egg—1 = —’lU2:El (A.l4) Therefore, for element 021 of the linear transform matrix A, the gradient ascent rule is given as 3f 8021 (N—l) 0.21[N] = (121 [N — 1] + k 151 3f 8021 (N_1) 0.21 [N] = 021[N — 1] — kw2[N — 1];L‘1[N —— 1] (121 [IV] = 0.21[N - 1.] + k Let k'wle T111311N T 1] = €89G(w2[N T 11189710131 [N _ 1]) where k- and 5 are step size constants. szlN _ 1151311N T 1] = €61le _ 1135171073111v _ 1]) where sgn(u’2 [N — 1]) = d2[N -— 1]. Therefore, recursion Eqn. (A.l3) is written as G211N1 = GzrlN _ 1] _ 661le T 11397141111N T 1]) G211N _ 1] = G21[N _ 2] T €01le T 21897111611N T 2]) G211N T 2] = G21[N T 3] T €61le T 3139749311N T 3]) G21111 = G21101 T €d21018971($1[01) Solving for 021 [N — 1], we get N—3 G21 [N _ 1] = T Z €d21i139n($11i1) T €(d21N T 21189710311N T 2]) i=1 N—2 G211N — 11 = — 2 56121089710310) (A15) i=1 Recursion given by A9 is expanded as w2[0] = 0 10211] = “12101 T ((12101 T G21[01$1[01 T 502101) 102121 = G211] T ((12111 T G21111~T1111 T 932111) 111211)] = wle T 11 T (dle T 11 T 61211N T l]xrlN T 1] T 2?le T 1]) 152 Solving for 1112 [N], we get w[N] = 10210] T 1:1 dzl’il T 1&1021121931111 T I: 1132121 2'20 Dividing both sides by N, we get 1 1 N—1 . N—l . . N—1 . Noemi = r w2101— 2: can — Z G21121$1 121 — 2 2:212] 120 i=0 i=0 —102[N1T21d2[i1+ :20 (1211315171121 + 2113211] 1112 [N] is a finite internal residual value of channel 2 after N cycles. Therefore, as N -—> oo, firwflN] —> 0 and we get 2 3:2[2'] + Z 021[z’] 2:1[1' :2 (12(2) (A.l6) Substituting the value of (1.21, the recursion of the first order EA converter A.9 after N cycles, is written as N N i—l N Z 1272 [1'] — g: 2:1[2'] Z d2[j]sgn(171 L71) = 2 d2 [1'] (A. 17) 1:0 i=0 j=0 i=0 For the M-dimensional STL system, the linear transformation matrix has the form all 0 . . 0 A = 021 (122 . . 0 (A. 18) am] 0mg . . 0mm The M-dimensional inputs and the internal states of the STL system are given by ( $1 ) $2 :1: = . and K m l w = ( 1111 2.02 . . wyn ) (A. 19) 153 Therefore, for the M-dimensional system, Eqn. (A.l7) is extended to give a generalized form for the mth channel as N N m—l i—l N Zena-:2 2x112] Xenophon» =§jdm121 (A20) i=0 l=1 i=0 j=0 i=0 Since dm[1‘] 6 {+1, —1}, therefore the condition for complete signal de-correlation is given by 2,111.0 dm [1'] = 0 which implies N m—l N i—l Zarmlil = t 2 2x111] delilsgn(fvzlil) (A.21) i=0 l=1 ‘=0 j=0 Eqn. (A20) is a generalized equation for the M-dimensional (M > 0) first order STL system that completely describes the 1Wh channel output The uncorrelated signal in the M th channel is represented by the equivalent digitized output dm of the M th channel of the STL system as given in Eqn. (A20). The Eqn. (A.21) shows that if the input signal mm is completely correlated with lower dimensional (m — 1) signals, then the signal mm is completely represented by the lower dimensional digital data outputs d1 ..... dm._1 of the M- dimensional STL system. Therefore, the redundant signal information is eliminated from the M M channel. Eqn. (A.20) gives the digital output dm that represents the non-redundant signal information of the M th’ channel. 154 A.3 Mathematical Modeling of the Second Order STL System The optimization of function A.2 gave the first order STL system when internal state 112 and elements 0,5 of the linear transformation matrix A are updated using the first order approximation of the gradient update algorithm as given in Eqn. (A7) and Eqn. (A.l3) respectively. By adding the higher order momentum terms to the gradient update algorithm, a higher order S TL system is formed. For example, a second order STL system is obtained if the differential values of w and elements aij of the linear transformation matrix A are updated with the gradient update algorithm with first order momentum terms. A second order S T L system is shown in Fig. 4.4. Using the L1 regularizer, the min-max function A.2 is written as Eqn. (A.3). For a 2-dimensional STL system, the Eqn. (A.3) is~ written as Eqn. (A.6). In a second order STL system, the internal state to is optimized using the gradient descent rule with addition of first order momentum term. to is given by w[N] = w[N — 1] — 176—)— + w[N — 1] -— w[N — 2] (A.22) 8"“ (N—l) 3f- = 8971010) T 561 81111 0f at): — d1 _ $1 8 a—f = 8971002) T ((121131 + $2) w2 , 5f 3172 — (12 T (G21-771 + 1112) where sgn(wm) iS represented by a digital bit dm. w1[N] = 1121 [N — 1] — (d1 [N — 1] — 51:1 [N — 1]) + 101 [N — 1] — u;2[N — 2] (A.23) w2lN] = 102le T1] _ (d21N T 1] T (G21 [N T 11331 [N T 1] + $21N _ 1])) (A24) +w1[N — 1] - w2[N — 2] A 2-dimensional ST L system is shown in Fig. 4.5. Eqn. (A23) and Eqn. (A.24) give the States of 11.11 [N] and 1122 [N] at sampling instant N. Eqn. (A23) is a recursion equation 155 of a second order EA converter with input signal 2:1 and the digital output data stream d1. Eqn. (A24) is also a recursion equation of a second order EA converter where the digital output stream d2 is the representation of a linear transformation of input signals $1 and 51:2. The update rule for the elements of linear transform matrix A follows the gradient ascent method. If the adaptation of a linear u'ansformation matrix A is performed using an Eqn. (A. 13) then it would be slower compared to the change in internal state 111. Therefore, to improve the adaptation Speed of a linear transformation, a second order approximation Eqn. (A25) is applied. The second order gradient ascent rule of adaptation for the elements ((1,-j) of a linear transformation matrix A is given by aij[N]=aij[N—1]+kaaf +aij[N—1]—a,-j[N—2] “it (N—l) ('9 (rm-[N] -- a.,j[N —1]_—. 02‘le — 1] - (LU-[N -- 2] + 1980'}... (N ) u —1 Let Cij[N] = aiflN] — aijIN _11 3f q-[N] = c,'[N — 1] + k7— ] j ' (9041' (N—1) Gf 8020' (N—l) For a 2-dimensional system, element (121 [N] is written as = —w,-[N — 1]:cj[N — 1] . , a GzrlM T612110 T11: @11wa 11 T G21[N _2] + k8 f 021 (N—l) -kw2[N __ l]xrlN - 1] = -€sgn('w2[N T 108971071 [N _ 1]) where k and f are constants that hold the equality given above. Let y[N — 1] = —kwg[N — 1]:1:1[N — 1] : —§d2[N - 1]sgn(l‘1[N — 11) 156 (A25) (A26) af 8021 (N—l) €21[N] = 621[N — 1] + y[N — 1] (A27) C21W] = C2111" T 11 + k the recursion Eqn. (A27) is expanded as 021[0] = 0 62111] = 62110] + y[0] = 3110] 021121 = C2111] + 1111] = 910] + 3111] 62113] = 62112] + 1112] = 1110] + 3111] + 3112] 021 [N] = €21[N — 11+ y[N — 1] = y[0] + y[1] + y[2] ........ + y[N — 1] Solving for c21 [N], we get N—l CzrlNl = Z yl’il .___0 The generalized expression for on [N] is given as N —l 621 [N] = —E 2 (12111397201er (A.28) i=0 With the given substitution of Eqn. (A26) for 021 [N], recursion A26 is written as a21[0] = C21[0] = 0 021111 = 62111] + 612110] = C2111] + 621101 G21[2] = C2112] + G21[1] = C2112] + 02111] + C2110] G21131 = C2113] + 021121 = 021131 + C2112] + 621111 + 02110] G21 [N] = C211N1 + 021 [N T 1] = C211N1 + + 021111 + 021101 N G211N] = E 021111 .20 157 N i—l G21[N] = T€ Z 2 6121713971061 17]) (A29) i=0j=0 Recursion equation Eqn. (A24) is written as w2101 = 0 w211] T W210] = 11210] T (d2[0] T G21101$1101 T G7210]) w212] T 11211] = w2111 T ”(0210] T ((12111 T G21111$1111 T G3211]) G213] T “"2121 = G212] _ wzlll T (61212] _ 02112117112] T $2121) 102W] T ’wle T 1] =IU21N T 1] T 102W T 2] T (G21N T 1] T G21[N T llxrlN T11T$21N T11) Solving the recursion for 102 and dividing both sides by N, we get is (usiNi — werN — 11) = 1 . 1 N—l N —1 N T1 N 1112 [0] — Z d2[i] _ 2 0211113311” — Z 33212.] i=0 i=0 i=0 % (rs2 [N] — w2[N — 1]) = 1 N —1 N —1 N—l N T Z G211] + 2: (1211033110 + Z 1172121 1 i=0 i=0 i=0 1112 [N] is an internal residual value of channel 2 after N cycles. This 1112 [N] is finite there- fore, as N —+ 00, 7%(1112[N] — w2[N —1])-—r 0 and we get N—l N—l N—1 Z 11:2[1'] + Z a21[i]2:1[i] = Z d2[’i] . (A.30) i=0 i=0 i=0 Substituting the value of 021, we get 2 lj— —1 N—l 1:11:21]_€ :1 11:1 [1] (: Zdfik] sgn (2:1[k])) = Z d2[i] (A.31) =0k= _0 £20 The M-dimensional STL system is extended by using the result obtained from the 2- dimensional STL system. For an M-dimensional STL system, the linear transformation 158 matrix A is given by A.l8. Tire M-dimensional input signal and the internal state of the STL system are given by A.l9. Eqn. (A31) is extended to the M-dimensional system whose general form is given by 1n— —1 i— -1j— —1 .N—l 1: Gm 121 T6 12: Z 11121 Z Z: dmlklsgnm [16]) = Z d«mlil (A32) j=0k= —0 i=0 Since dm[i] e {+1, —1}, therefore the de-correlation condition is given by 25:0 dm[i] = 0. The Eqn. (A.32) gives the digital output dm that represents the non-redundant or un- correlated signal of channel M with respect to the lower dimensional (M — 1) signals. If the input signal mm is completely correlated with the lower dimensional (M — 1) signal, then the right hand side of Eqn. (A.32) goes to digital data representing the zero input Signal. Therefore, the de-correlation condition of channel M from the rest of the lower dimensional (M — 1) channels is obtained when de-correlation condition given in A33 is satisfied. nr—l i— lj— —1 :1 $m[i]— — E a 212:)[2'] Z de [k]sgn( (x)[h]) (A.33) j=0k=0 159 A.4 Mathematical Modeling of the Hysteretic STL System The optimization of function A.2 gave the first order STL system when the internal state 212 and elements aij of the linear transformation matrix A are updated using the first order gradient update algorithm as given in Eqn. (A.7) and Eqn. (A.13) respectively. By adding the hysteretic momentum terms to the first order gradient update algorithm, a hysteretic S TL system is obtained. Hysteretic gradient update rules are obtained by adding hysteretic momentum terms to the first order gradient update rules of w and elements aij of the linear transformation matrix A. Using the L1 regularizer, the min—max function Eqn. (A.2) is written as Eqn. (A.3). For the 2-dimensional STL system, Eqn. (A.3) is written as Eqn. (A.6). In a hysteretic STL system, the internal state w is optimized using the gradient descent rule with hysteresis. Therefore, w is of the form given by w[N] = w[N — 1] — 71?]: + A(sgn(w[N —— 1]) — sgn(w[N — 2])) (A.34) (9U) (IV—1) fl- : 8971(w1) - $1 8101 Of _ as; — d1 “ “’1 0 5i = 897K102) — (021$1 + 932) 102 8 '51:- : d2 - (021331 + $2) W2 where sgn(wm) is represented by a digital bit dm ual-N] =w1[N —1]—(d1[N — 1] - $1lN — 1]) (A.35) + Asgn(wl [N — 1]) — Asgn(w1 [N — 2]) wg[N] 211:2[N — 1] — (d2[N — 1] — (a21[N — l]x1[N — 1] + 2:2[N — 1])) (A36) + Asgn(w2[N — 1]) — Asgn(w2[N — 2]) where A is the hysteresis level of the 2A converter. The digital output of the 2A converter at the it" sampling cycle is given by dm[z'] = sgn(wm [2] + Adm[z' — 1]) 160 For the 2-dimensional hysteretic STL system, the states ml and 102 at the sampling instant N are given by Eqn. (A.35) and Eqn. (A.36). Eqn. (A.35) is the recursion equation of the hysteretic EA converter where the digital output stream d1 digitizes the signal 3:1. Eqn. (A36) is also a recursion equation of the hysteretic 2A converter where the digital output stream d2 represents the linear transformation of input signals :51 and 11:2. The update rule for the elements of the linear transformation matrix A follows the gradient ascent rule. The adaptation of a linear transformation matrix A is performed using a hysteretic momentum term as given in Eqn. (A.37) to match the adaptation speed of a linear transform matrix A. The gradient ascent rule for the adaptation of elements ((22-3) of the linear transformation matrix A is given by 5f 5%“ (N—l) (LU-[N] = adj-[N — 1] + k + A(aiflN — 1] — aijUV — 2]) aij[N] — AaijUV — 1] = aij]N — 1] — AaiflN — 2] + 16 6f 5023' (N—l) Ciij [17V] 2 adj-[N] — Aaij [1N -- 1] 8 WW] 2 “AN _ 11+ kaa; (N 1) 8f = —w,-[N — 1]$j]N — 1] Baij (N—l) For the 2-dimensional system, the coefficient (121 [N] is written as a21[N] — AazrlN — 1] = 021W - 1] — Aa21[N — 2] + k—af— 6021 (N_1) ——kw2[N — 1]:r:1[N — 1] = —€sgn(w2[N — 1])sgn(:c1 [N — 1]) where k and g are constants that hold the equality given above. Therefore, y[N — 1] = — w[N — 1]:r:1 [N — 1] = — §d2[N — 1]sgn(:r:1[N — 11) 161 (A.37) (A.38) C21lNl = 621le - 1] + k13— (9am (N_1) mm = C21[N - 1] + le - 1] (A39) Recursion Eqn. (A39) is expanded as C21[01 = 0 C2111] = 02110] + ylol = 910] C21[21 = C21[1]+ vi” = ylol + 31111 C21[3] = 621M + W] = 910] + y[1]+ yl2] C21[N] = C21[N — 1] + WV — 1] 2 gm] + 3A1] + y[2] ........ + MN _ 1] N—l C21[N] = Z W] i=0 Solving for c21 (N), we get N—l CNN] = —5 2 d2 [2']sgn(:c1 [1]) (A40) i=0 where (12121 = sgn(‘w2[i] + Ad2li - 1]) With the given assumption A.38, the recursion for am is written as 02110] = C2110] = 0 (1.21 [1] = 021111 + Aa21[0] = C21 [1] + AC21[0] a21[2] = C21[2] + 1302111] = C219] + A(C21[1] + A621101) a2113] = C21[31 + 02112] = C21[3] + A(62112] + AC21[1] + A2621101) a21W] = C21[N] + a21W - 11 = 621[N] + A (max _ 11...+ AN-2C21 [1] + AN -1cm[01) 162 N a'211N1 = C211N1 + Z A11.102111 i=0 Solving for (121 [N], we get N-l -1 (L21 [N] = —5 Z d2[z']sg-n(:c1[z]) —§ NZ: AN i ngU]sgn(x1[j]) (A.41) i=0 i: —0 Substituting the value of am, the recursion equation of mg is written as 102 [0] = 0 w2111 - A89711102 101) = w2101 - (d2 [01 — a21101561101 - cl32101) w2121 - A«‘v‘gn(w2[11) = 102111 - A8971(102101) - ((12111 - a21111331111 - $2111) 102131 As9n(w2[21) — ‘7-w2121 A8971(102111) - (012121- 0211215131121 - $2121) 1L’2]N] - Asgn(wg [N — 1]) = u12[N — 1] — Asgn('wg[N — 2]) — (cw — 11 — a21[N — 1mm — 11- $le — 11) Solving the recursion equation of w2[N] — Asgn(w2[N — 1]), we get u21’V1 A89Tl(89n(w2[’V—11))W[01-(::::0 012121— :1 a21115101121 — 2 01332121) 2122 [N] is the internal residual value of the second channel after N cycles. 1122 [N] is finite, therefore, as N —> 00, 7170112 [N] — Asgn(w2[N — 1])) —> 0 and we get .1. (211le _ Asgn(w2 [N — 1])) = 717212le N 1 N—l N—l N—l — N (2 can — Z a21121x1m— Z x2121] i=0 i=0 i=0 —1 1%(11121N1 — Asgn) =$ (JV 2 c1211] + 2 «22111231121 + 2: 01322111] 2: As N —+ 00, 7%(w2[N] — Asgn( w2[N -— 1]) ) —+ 0, we get N—l N—l N—l Z 162111 + 2 021111331111 = Z d21‘i1 (A42) “120 i=0 i=0 163 Substituting the value of (121 from Eqn. (A.41), we get N—l N—1 X (12111 = Z 132121 i=0 i=0 N—l i—l j—l (A43) - 5 Z 231171 2 d2 1718971601 U1) + NH 2 d21k189n(l‘1[k1) i=0 j=0 k=0 The 2-dimensional model of the STL system is extended to an M-dimensional STL system where the linear transformation matrix A is given by Eqn. (A. 18). The M-dimensional input signal vector and the internal state vector of the STL system are given by Eqn. (A.19). Eqn. (A.43) is extended to an M-dirnensional system and the general form is given by N — 1 N —1 2 dm. [21 = 2 mm [21 i=0 i=0 m—l N—l i—l . .j—1 —5 Z (2: mm 2 (de189n($1171) +AH detklsgn(xz[k1) [:1 i=0 j=0 k=0 (A.44) The digital output dm in Eqn. (A.44) represents the un-correlated signal at channel M. If the input signal :13", is completely correlated with the lower dimensional (M -— 1) signals, then 2:11:61 dm[i.] -—> 0. Therefore, the de-correlation condition of channel M with respect to the lower dimensional (M — 1) channels is obtained when N-l Z :L'm[z'] = i=0 m—l N—l i—l . .311 (A45) 6 Z Emil Z deSQ’IWBlUD+Az—Jde1k189n(xz[k]) (:1 i=0 j=0 1,20 is satisfied. It should be noted here that when the hysteresis level of the hysteretic 2A converter is set to zero then the hysteretic STL system behaves as a first order STL system. If the hysteresis level is zero then Eqn. (A.43),Eqn. (A.44) and Eqn. (A.45) get the form of Eqn. (A.l7), Eqn. (A20) and Eqn. (A.21) respectively. Therefore, the hysteretic STL system can be converted to the first order STL system by adjusting the hysteresis level 164 in the STL system. This technique is useful in applications where the input signals show wide dynamic range. For a small dynamic range signals, the given hysteretic STL system is useful to reduce the zero cross switching as shown in section 4.5 and for a large dynamic range signals, the hysteretic STL system is configured as the first order STL system by adjusting the hysteresis in the system. 165 APPENDIX B Noise Analysis The algorithm designed for the STL system does not have any dimensional limitations but there are some factors that limit the dimensionality of the system in real hardware. Some of these factors are noise, power dissipation and the die area. The noise generated by the system component is the dominant factor that severely limits the maximum number of channels being accommodated by the system. In the designed STL system the SN R is limited by the noise generated by the current summing transconductor network and the first stage of the 3rd order EA modulator used in the system. The noise generated by the second and the third stages is shaped out of the signal band and is negligible compared to the first stage when referred back to the input of the EA modulator, therefore is not considered for the analysis. The noise sources that limit the performance of the system are the transconductor network, the current references of the current mode modulators and the operational amplifiers used in the integrators. We will look at these factors individually to see how they affect the system. B.1 Noise Contribution of the Transconductor Network The transconductor network plays an important part in determining the S N R of the system where the S N R is inversely proportional to the dimensionality of the transconductor net- work. The transconductor topology used the network is shown in Fig. 6.5. The dominant 166 noise contributing devices in this transconductor are M1 — M4. The noise contribution of cascode devices is very small compared to noise contribution from devices M 1 — M4 when referred back to input therefore devices M 1 — M4 are considered for noise analysis. The total input referred thermal noise of devices M 1 — M4 is given by 8K T 8K T . 8K T 8K T V3, (TC) ___ + 2ng + 2.9m3 + 29m4 (3.1) 39ml 39m1 39m1 39ml The total input referred flicker noise due to devices Ml —~ M4 of the transconductor is given by K1 K2 92 2 V2 TC .-= + m fC( ) ”/ILICoxf W2L2Coxf 93,11 2 2 (B.2) + K 3 9m3 K 4 9,7,4 ”/3L3Corf 9,2711 W4L4coxf 93,11 Therefore, the total noise contribution due to a single transconductor is given as V2 = V2 (TC) + V2 (TO) (B 3) n1 tn f c . B.2 Noise Contribution of the Current References The reference current sources of the first stage of the 2A modulator is the second dominant noise source of the channel. These current sources are shown in Fig. 6.12 where devices Mg and M 12 are the dominant sources of noise. The noise generated in the cascode devices Mlg — M11 is very small compared to Mg and M12 and therefore it is not considered here for noise analysis. The thermal noise generated by Mg and Mn is given by 1 8Kng+ 2 Ifh