TRANSISTOR LARGE SIGNAL ANALYSIS Thesis for the Degree of Ph. D MICHIGAN STATE UNEVERSITY HELMY HASSAN E 1964 LIBRARY " Michiga. 3mm University H nmomc av HMS 8 SflNS'. '. 300K BINDERY WT LIRRARY HIN Di “. TRANSISTOR LARGE SIGNAL ANALYSIS BY Helmy Has san EISherif AN ABSTRACT Submitted to Michigan State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Department of Electrical Engineering 1964 Appr ove d by Abstract by Helmy H. EISherif A problem of major concern in recent years is a description of the transistor from the point of interest of the circuit designer. This thesis devises an equivalent circuit that is a modification of the charge control model of the transistor. The equation describing the base emitter junction is modified to include the effects of the base resistance and the variation of the saturation current with the collector to emitter voltage. Also a partially saturated region of operation is introduced to more accurately predict the base control charge. The relative importance of the different charge control model capacitances in predicting the circuit Operation is investigated and curves are presented showing the significance of each. A computer program is developed which reduces the transistor model to a form which can be treated independent of the circuit in which it is connected. This reduced representation is in the linear graph form. COPYRIGHT BY HELMY HASSAN ELSHERIF 1964 TRANSISTOR LARGE SIGNAL ANALYSIS BY Helmy Has san ElSherif A THESIS Submitted to Michigan State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Department of Electrical Engineering 1964 T O MY MOTHER AND TO A FRIEND ACKNOWLEDGMENTS The author wishes to eXpress his sincere appreciation to Dr. R. J. Reid for his guidance; to Drs. L. J. Giacoletto, H. E. Koenig and L. W. Von Tersch for their continued help; to the staff of the Computer Center of Michigan State University and to Messrs. W. Wohlfort, J. Wyckoff, F. Ordemann, G. Mohoney and W. Weeks of the Memory Circuits Division of International Business Machines for their assistance and encouragement. ii TABLE OF CONTENTS Page ACKNOWLEDGMENTS ................................. ii LIST OF APPENDICES ................................. v LIST OF SYMBOLS .................................... vi CHAPTER I. INTRODUCTION ....................................... 1 II. TRANSISTOR LARGE SIGNAL EQUIVALENT CIRCUIT . . . . 4 III . IV. NNNNNNN \JO‘UTQUJNH . 8 Transistor Large Signal Performance ............... 4 Cut Off Region .................................... 5 Normal Active Region ............................. 6 Partially Saturated Region ......................... 11 Totally Saturated Region . . . . . . . . . . . ............... 15 Inverse Active Region ............................. 15 Characteristics of the Base Emitter Junction in a Transistor ....................................... 16 Summary ........................................ 19 TRANSISTOR STATE MODEL AND ITS APPLICATION IN A COMPUTER ANALYSIS PROGRAM .............. 20 3. 1 Capabilities of MISTAP ........................... 20 3. 2 Mode of Operation ................................ 21 3. 3 Subroutine MSTAP 1 .............................. Z4 3. 4 Subroutine MSTAP Z .............................. 28 3. 5 Subroutine MSTAP 3 .............................. 32 3. 6 Subroutine MSTAP 4 .............................. 35 3. 7 Subroutine CAP .................................. 38 3. 8 Subroutine CURRENT ............................. 38 3. 9 Subroutine TBW .................................. 38 EXPERIMENTAL CORROLATIONS . . . . . ................ 41 4. 1 Base Emitter Junction and Stray Capacitances are the only ones Included ............................ 45 4. 2 Base Emitter Capacitances and Collector Emitter Stray Capacitances .............................. 5 1 iii iv 4. 3 Base Emitter Capacitance, Collector Emitter Capacitances and Base Collector Junction Capacitances . . I'M“? omits Discus sion . . CONCLUSION . . . . . . All Capacitances . Additional Test Circuits . . 57 63 75 76 .80 LIST OF APPENDICES Appendix I. Solution of Current Through a P-N Junction when the Voltage is Specified .................................. 81 II. Solution of Voltage Across a P-N Junction when Current is Specified ................................. 85 III. Input and Output Information for MISTAP ............... 88 BASCUR C CBE CBEX CBC CBCX CCEX COLCUR D n D I = XIBE H II XIBC LIST OF SYMBOLS Current through base lead Capacitance Base emitter junction capacitance Stray capacitance between base and emitter leads Base collector junction capacitance Stray capacitance between base and collector leads Stray capacitance between emitter and collector leads Current through collector lead Electrons diffusion length The derivative w.r.t. time, d/dt Current through a P-N junction Saturation current of a P-N junction The current through base emitter diode Base current Collector current Current that would flow through base collector diode Boltzmann's constant Diffusion length of electrons Diffusion length of holes Concentration of acceptors C oncentration of donor 5 vi RBB RCC T = TEMP 1-1 ll TE TB r-l ll VBE VBEIN VBB VCC VIN VCE XIBX XIB XIC IN XIBIN Vii Base control charge Electronic charge Storage charge in the base region Resistance of base semiconductor material Resistance of collector semiconductor material Temperature of junction Emitter time constant Base time constant Collector time constant Contact potential of a P-N junction Effective voltage across junction Applied voltage across junction Voltage between base and emitter leads Voltage across base emitter junction Base emitter bias voltage Collector emitter bias voltage Input signal between base and emitter leads Collector emitter voltage Component of base emitter current that contributes to the build up of the storage charge in the base QS Component of base emitter current that contributes to the build up of the base charge QB Internal collector current Internal base current Width of the base region Normal common base current gain Common emitter current gain CHAPTER I INTRODUCTION The transistor is one of the most important components of today. It is being used extensively in all areas of electronics. There . l are a number of equivalent circuits that describe the tran51stor,( ) however, they are limited to small signal conditions. The dc current equation for a p-n junction is given by; 31’ 1:100:kT - 1) (1.1) The small signal equivalent circuits make the assumption that . . . . kT the voltage applied to the junction V is much less than ? and hence equation (1. 1) can be approximated by I qV qV o : — -l = — 1.2 I Io(1+ kT ) kT ( ) The advancement of the computer industry, the development of micro electronic circuitry and the fact that the transistor is very often driven beyond the small signal region of operation, make equation (1. 2.) a poor approximation of the actual Operation. This has brought about the necessity to develop an equivalent circuit for the transistor that can describe the large signal behavior as well as the small signal behavior. In 1957, Beauffoy and Sparkes(z) developed a charge control model for the transistor. They represented the device in saturation -2- (3) saturation the same way as Ebers and Moll , as two transistors in parallel, one operating normally and the other in reverse (collector operating as emitter and emitter as collector). Though satisfactory for devices of symmetric geometric construction, it is not adequate for asymmetric ones of more complicated geometry. 4) The existence of system analysis programs, that made use of linear graph techniques makes it desirable to have the tran- sistor model in a reducable representation as in Fig. (1.1). Fig. (1.1) Linear Graph Representation of the Transistor One variable associated with each group element will be Specified and the other must be obtained. The material that follows fulfills this requirement and can be divided into three major sections. Chapter 2. discusses the modification and description of the charge control equivalent circuit devised by Beauffoy and Sparkes(2) and discusses the different nonlinear elements and their mode of variation. -3- Chapter 3 presents the details of a digital computer program that performs the required analysis based on the results of Chapter 2. It also gives the state model of the transistor in the four different modes of operation. Chapter 4 shows a comparison between the experimental and calculated re sults . CHAPTER II TRANSISTOR LARGE SIGNAL EQUIVALENT CIRCUIT Z. l Transistor Large Signal Performance The transistor is a three terminal device. It is either a PNP or an NPN with the N region or the P region respectively being the base. Anyone of the two P regions or the two N regions can act as an emitter and the other as a collector. When the terminal designated by the manufacturer to be the emitter is used as an emitter, the transistor is said to be operating under normal conditions. When the terminal designated as collector is used as an emitter, the transistor is said to be operating under inverse conditions. In either case, the performance of a transistor under large signal conditions can be divided into four separate regions: a. Cut-Off Region In this region both junctions are reverse biased. b. Normal Active Region Here, the emitter-base junction is forward biased, while the base-collector junction is reverse biased. c. Partial Saturation Region In this case of operation, both junctions are forward biased, yet the voltage across the base-collector junction will permit a current flow in the forward direction that is much less that the base current, in magnitude. -4- -5- d. Complete Saturation Region Both junctions are forward biased, and the voltage across the base-collector junction will permit a current flow in the forward direction, of the same order of magnitude as the base current. The discussion from now on will be restricted to NPN transis- tors, but the analysis will be equally valid for PNP transistors provided suitable substitutions of sign are made. Fig. (2.1) shows the charge distributions of both holes and electrons in the base region for the four cases of operation. The gradients are approximately linear and are proportional to the net current flowing from the emitter to the collector. 2 L. J. Giacoletto,(1 ) showed that the base region is not an equipotential. The total charge in the base region (which changes parabolically with distance) can be approximated as shown in Fig. (2. l) which holds during both turn on time and turn off time for the greatest majority of cases. 2. 2 Cut -Off Region In the cut-off region only, an equilibrium concentration of electrons and holes exists and the base charge can, for all practical purposes be taken as equal to zero. 2. 3 Normal Active Region (2) It has been shown that the base charge Qb, of electrons (and of holes in excess of the number of impurity atoms) is given by: WZI E = —_ 2. QB 2D,, ( 1) -.--D- m ’1 Chewy: Dansi c Base ‘chaon 'M 5:87) ' I ”1] q Dis lance. C : < O; < O ase a Vbe Vbc ' > ' < Case b. Vbe O, VbC 0 Case c: Vbe > O; Vbc > 0, the difference between Cl and c show the storage charge in this case. Case d: Vbe > O; Vbc > > 0, thedifference between Cl and d is saturation charge. Fig. (2. 1) Charge Distribution in the Base of an NPN Transistor 2 Z (The dimension of — is c_r_n___ = sec) 2D n cm /sec Defining now, three time constants QB a. TE, the emitter time constant = -i—- E QB b. T , the base time constant: — B I B QB c. TC, the collector time constant = -I-— C Equation 2. 1 can be rewritten in the form: ~2 WI Q:T.I: E B E13713"— n The base current is given by 13 = (1 -ocN). IE (1-0 1 o (2.13) > B BC is the criterion for partial saturation. Fig. (2. 4) shows the equivalent circuit for the partially saturated transistor, which is also the same for the totally saturated case . -14.. I fl BC I ' ___- mun--.) [— ( ’/ .4— R85 ' Jco 1 Rec 3 C fiwh - - QIIL I VA'H C «0 § CBC t i" igli ('3 s 0 95 )9 C -_ E 8!") r ‘ G 1., ~71 l E Fig. (2. 4) Equivalent Circuit of a Transistor in Saturation 050(6); Control/0L 6] Em,-’&c, Bulk] Y) P If P-Y) fwncttow T 4T yes Jr TE Om (yo/s a 5 f. I ‘9 85¢ Em’lér Jumbo» w Emitter trough» £930.“ Base Col/ectov‘ function-J Transition 1330') ’1 ' J Colkcfu Balk flebbncc %l C 7"; Cent vols Fig. (2. 5) Schematic Diagram Showing the Different Regions in a. Transistor -15- The voltage level diagram, shown in Fig. (2. 5) shows how the total voltage, Vt’ across the junction, is related to the built in contact potential, V0, and the applied voltage Vap° 2. 5 Totally Saturated Case In this case, both junctions are forward biased and the bias on the collector base junction is such that: I QB/TB)/Z > o (2.14) > - BC (IBE This excess current (I - QB/TB), will not contribute to an increase BE of the base control charge Q but will only contribute to the build B' up of the storage charge QS, and the presence of this storage charge will introduce delays that will be discussed in a later portion. Fig. (2. 4) gives the equivalent circuit of the totally saturated transistor and Equation (2. 14) is the criterion for total saturation. The diode shown between the base and collector represents the base collector junction. 2. 6 Inverse Active Region In this case, the discussion and equivalent circuit are the same as those of the normal active region with the exception that the collector is now acting as an emitter and the emitter is acting as a collector. Fig. (2. 5) shows a schematic diagram for the transistor showing how the different components are distributed. -16- 2. 7 Characteristics of the Base Emitter Diode Junction in a Transistor Chih Tang Sah(6) showed that the current flowing through a semiconductor junction may be divided into four components according to the location of the recombination and generation of electrons and holes. These are: 1. Bulk recombination generation current. 2. Bulk recombination and generation current in the transition region. 3. Surface recombination and generation current. 4. Surface channel current. The current through a p-n junction is thus the combination of these four components and is given by the following equation: (qumkm 1) (2.15) I = I o where, V is the voltage directly across the junction. Due to the presence of the base lead resistance and the resistance of the base semiconductor material, V is related to VBE' the voltage applied between the base and emitter leads, by the following equation: = .. . 2.16 V VBE IBE RBB ( ) -17.. Figure (2. 6) shows the variation of the base emitter current, IBE as a function of V with the collector emitter voltage as a para- BE' meter, for a Texas Instruments, 2N744 NPN epitaxial double diffused high Speed mesa selicon transistor. 3 :03 a greater ,3) .o. (1 1 l) - VCE , O. ”I. I i . ( 1 3 - ( 1 Z .. / _ 0 0.7. 0‘! 0.6 0.3 YE (YO/0 I . Z. O a 0 Fig ( 6) Variation of IBE With VBE A.\.v| I\ l...‘ .| \ n ‘i\\. Lao (.1043 Arr) 0.1, -18- —9— YCE’ (V0 If: 1 Fig. (2. 7) Variation of IBEO With VCE It was founthhat. Equation (2. 15) describes the curves in Fig. (2. 6) to a very close approximation, with IC) being a function of V the CE’ collector emitter voltage. This relation is shown in Fig. (2. 7). For the previous transistor the equation governing the base emitter current is 3.3 -2.24 I :1 “(5 VBE 8 I ) . -1 0 BE BEO BE )Amp (Lin where, IBEO' is the saturation component of IBE' and is shown in Fig. (2. 7) as a function of V . CE * * A study done by the author at International Business Machines -19- The dashed curves in Fig. (2. 6) show IBE as calculated from Equation (2.17) and Fig. (2. 7). 2 . 8 Summary In this chapter, the transistor model was introduced, the partial saturation region has been defined, and an equation describing the current through the base emitter junction as a function of the collector emitter junction voltage was introduced. In the following chapter, the state model of the transistor will be obtained and adapted to a computer analysis program. ' CHAPTER III TRANSISTOR STATE MODEL AND ITS ADAPTATION IN A COMPUTER ANALYSIS PROGRAM A major contribution of this thesis is a computer program MISTAP (MIchigan State Transistor Analysis PrOgram). MISTAP gives a linear graph representation of the transistor through the use of the transistor state model. Presuming that the characteristics of the device have already been stored in the computer, the user has to supply one set of input parameters and one set of output parameters, and MISTAP will supply the remaining two parameters. The results obtained through the use of MISTAP are sometimes within 1: 3% and generally within 10% deviation. To the knowledge of the author, MISTAP is the first program of its kind and handles the transistor from a completely general point of view. 3. l Capabilities of MISTAP 1 - MISTAP can handle up to 50 different transistors. Z - MISTAP can handle up to 20 different types of transistors. (The capabilities supplied in l and 2 can be increased by increasing the size of the dimension statements.) -20- -21- 3 - MISTAP supplies to the user, a set of differential equations (derivatives of four different variables for each transistor), and gives the user the freedom to use any method he likes for their solution. 4 - The solution is accomplished in the shortest possible time, because at times when a fast transistor is operating in a slow circuit, most of the differential equations are replaced by linear and nonlinear algebraic equations, which are generally much faster to solve than the differential equations, (the algebraic solution is usually for time increments much longer than that required for integrating the differential equation). 5 - If under any conditions, some of the devices are operating under inverse conditions, (the collector acting as an emitter and the emitter acting as a collector), MISTAP will handle them in the same way, provided that their inverse characteristics are supplied. 3. 2 Mode of Operation First, the subroutine starts by comparing the circuit time con- stant to the transistor time constant (RBB. CBE), if the circuit time increment is greater than three times the device time constant, the solution is totally or partially by the use of nonlinear algebraic equations, otherwise it is accomplished through the use of differential equations. Secondly, MISTAP will find the mode of operation of each device, transfers the inputs to those applicable to NPN devices and after the solu- tion is completed it is transformed back to the correct conditions. -22.. In solving for the necessary variables, MISTAP makes use of another four subroutines, MSTAPl, MSTAPZ, MSTAP3, and MSTAP4. Before returning to the calling program, it compares its results with those obtained in a previous iteration, if the difference is less than a predetermined error, it will return to the calling program, otherwise it will call another subroutine, VAL, which has to be written by the circuit analyst and which will use the results of MISTAP to determine a more accurate set of inputs. Fig. (3. 1) gives the block diagram of MISTAP. When the voltage is specified and the current is the variable to be solved for algebraically the solution is by the use of the Newton Raphson Methodul), (Appendix I). When the current is the Specified variable and the voltage is to be solved for algebraically this is done by the direct solution of the nonlinear algebraic equation (Appendix II). In the following section, the different subroutines used in conjunction with MISTAP are discussed. -23- $892 Ocmusoandm mo 8235 xoonm :i .mE GS. .5230: u§ I .5an Cg IShk R5. OE i Ems-2; «52:18 I «B 2315.0 .1: 230.5 "83.5.3 0 - 53a n 5300 a I 2.300 I €300 Sting n 5239.9 A! keen - ”Bingo DJ won I :Zocn n3... n R . _- 8. g ‘ tying; I Cu! 11‘s: II Ii MB>| IE3“) ~n> - 5 ~23: Bran 832E g?) n 53:: ~u> I IBESE; 82:: . E .33- .§ . E E S: enslave u 9.03.3.3 nun-Ethel. - 933.5 0.13»:— R 3:26 «Is-on - «53.0 S»: 3-! n 3155 A! 23:0 « 3 5:5- Qviigau 3.2.355 A5 3- a 3 Elk €15.35 ICE-.325 A £315th I Reina}. a it «on u 3‘ I60 aha-on I Qei‘n 65.31:: s 533:! Sun: I at: 32:33 p 2:31: 3.3395 n 55.- 9. a whiz.!§-L.5unu . 35:3 .85 .3!- - is: . . 89:; E... 5.38: 32E?» 85:; 5237898: an a! I: u»: . .c 235 an .5139: n .5280... 5:3: n Sui 8 25. - Eu: H LJQQIQ. as 32.3} {nu-as it 3 m6 ed -24.. 3. 3 Subroutine MSTAP l This subroutine expects to be supplied VBE and VCE and supplies back to MISTAP enough information to determine XIBIN and XICIN. Evaluation of Differential Equations With reference to the transistor equivalent circuit shown in Fig. (3.2), mica) -->- VBE '- - - -t*--."i VCEIN/I) i (Ream VB ”(D E ”WSW -Rccen _ _ A 1 XIBINCQ g 03“” ‘ new (11 a .\ /-*s 9 is .2 = a it CBEUIT'g1 31 3 F1 51 Fig. (3. 2) Equivalent Circuit of Transistor I VBE = VBEIN(I) + XIBIN(I) . RBB(I) VCE = VCEIN(I) + XICIN(I) . RCC(I) XIBIN(I) = XIBE(I) + (CBE(I)+CBC(I)) . DVBEIN(I) - CBC(I) . DVCEIN(I) XICIN(I) = QB(I)/TC(I) - CBC(I) . (DVBEIN(I) - DVC EIN(I)) VCE (3.1) (3.2) (3.3) (3.4) -25- Substituting Equations (3. 3 and 3. 4) in Equations (3.1 and 3. 2) and simplifying we get DVBEIN(I) = [VBE-VBEIN(I)-XIBE(I).RBB(I) + (RBB(I)/RCC(I)).(VCE- VCEIN(I) - (013(1) .RCC(I))/TC(I)] / CBE(I).RBB(I) (3.5) DVCEIN(I) = [VCE-VCEINU) - (QB(I) .RCC(I)/TC(I)) + (RCC(I) .CBC(I)- (VBE-VBEIN(I)-XIBE(I) .RBB(I))/ RBB(I) . (CBE(I)+CBC(I))] / [CBC(I) car-(1) .RCC(I)/(CBE(I)+CBC(I))] (3.6) DQB(I) = x113 - QB(I)/TB(I) (3.7) DQS(I) = XIBX - QS(I)/TS(I) (3- 8) Derivatives Supplied to MISTAP DVBEIN(I) = DVBEIN(I) (3.9) DVCE1N(I) = DVCEIN(I) (3.10) DQB1(I) = DQB(I) (3.11) DQSl(I) = DQS(I) (3.12) (the terms on the left hand side of the equations 3. 9, 10, ll, 12““ are the terms that are integrated. Their solutions are: VBEIN(I), VCE1N(I), QB1(I), and QSl(I)). Solution is by the use of Nonlinear Algebraic Equations Here, the set of nonlinear algebraic equations to be solved are: 05(1) = XIBX . TS(I) (3.13) -26.. QB(I) = XIB. TB(I) (3.14) XIBIN(I) = XIBE(I) (3. 15) XICIN(I) = QB(I)/TC(I) (3.16) XIBE(I) is Obtained through the solution of: XIBE(I) = XIBEO(I). EXP(VBE-XIBE(I).RBB(I) ). Q/XMBE.XK.TEMP(I) ) - l (3. 17) The solution of Equation (3. 17) is performed by Newton Raphson method, for numerical solution of nonlinear algebraic equations, as shown in the block diagram Fig. (3. 3). Also, the integrating program will have these values of derivatives available; DQSl(I) = 0. 0 DQBl(I) = 0.00 DVBEIN(I) = O. 00 DVCEIN(I) = 0. 00 The state model in this case is: Fig. (3. 3) gives the block diagram of subroutine MSTAP l. r - — RBB QB VBE-VBEIN-IBE'RBB+R (VCE-VCEIN-T—‘Rcd DV cc c BEIN R c BB“ BE Q R .c B cc BC v -v -—.R +—(v -v -1 .R ) CE CE + DV IN TC cc RBB(CBE CBC) BE BEIN BE BB CEIN = cBCcBE. R +C ' CBE BC cc Q B DO 1 - _ B B T B Q 5 DQS IBx ’ T— s L 1 _ -27- : I = 2. [— < 30mm VBEIN’I’WBEIN (D3 VCEWm=V¢0~m r “135 g IVI‘INBtI)! A Qsm :- QBHn J 05(11- 951(1) i Y 4 . h - F'I . 97 (A 131 F80. VBEIN/1‘) - VCEIN (I) l or, . .7 m u, ) L Y Y I CALL cums-N7- l | new). xxzee- FI/DF/ J i —: ‘0 urn-om 7° (N " e Wilma...) (1:5. Fuse. meg] I [ CALL 78w L“) <0 XIBC (I) . XIB :68! (1:) ”5X8 0 3O 4. m r 1 (TN Yet 1: Ban-Qumran)! V 4 >0 N r 20 (IQ: <0) Leora-1 a o. xtexs XIBC?!) 3597(11c I XIB =XIB¢(-D-XIK(D V [ Qam . mama-ram] Y '7 4 fi X33. Qua/1'00) xrax- XIDICU- X1. 13‘7'61‘): 9- J 2! < —@ It In: 1165041110“ - 008; (1:) - oaacn q 1&1) 0031(1): 0615(1) (’38) DVBEIN(I) aovanth) 6:) (3.5) DvCl‘lNlr)= oven-u (I) a) (3-6) 32. _ Nautrmfi a?) V Q50) = US 07-8 (:1 man = max - 'r'sa) mama): nanny xtcrwmg @643) I 1:: (1) v awn: vs -_x:um . ROM!) V Elk/(1’): VC- -a (JD/Tear), .80“: ”61(1):- DQSNJMD 8‘IN(¢)= new: 1 _- r servant J T Fm 1 _l A Fig. (3. 3) Block Diagram of Subroutine MSTAP l -28- 3. 4 Subroutine MSTAP 2 This subroutine expects to be supplied with VBE and XICIN(I) and it returns to MISTAP enough information to determine VCE and XIBIN(I). Evaluation of Differential Equations Referring to Fig. (3. 2), and substituting Equation (3. 3) in Equation (3. l), we get VBE = VBEIN(I)+ [XIBE(I)+(CBE(I)+CBC(I)) . DBVEIN(I)-CBC(I) . DVCEIN(I)] . RBB(I) (3.18) Solvinngquation (3. 4) and Equation (3. 18) for DVBEIN(I) and DVCEIN(I), we get DVBEIN(I) = [VBE-VBEIN(I)-XIBE(I) . RBB(I)+XICIN(I) . RBB(I)- (QB(I) .RBB(1))/Tc(1)] / RBB(I) . CBE(I) , (3. 19) DVCEIN(I) = XICIN(I)-(QB(I))/TC(I)+ [CBC(I) . (VBE-VBEIN(I)- XIBE(I) .RBB(I)]/[RBB(I) . (CBE(I)+CBC(I))] / [ CBC(I).CBE(I)/(CBC(1)+CBE(1))] (3.20) together with DQB(I) = XIB - QB(I)/TB(I) (3. 21) DQS(I) = XIBX - QS(I)/TS(I) (3. 22) -29- Derivatives supplied to MISTAP DQBl(I) = DQB(I) DQSl(I) = DQS(I) DVBEIN(I) = DVBEIN(I) DVCEIN(I) = DVCEIN(I) Solution is by the use of Nonlinear Algebraic Equations In this case, we cannot solve for VCEIN algebraically, since its variation does not vary with any of the known quantities only and it is a function of the junction capacitances as well. Thus, in this case, VCEIN(I) has to be solved for by the use of the integration while the rest of the variables can be solved for algebraically. The following are the set of algebraic and differential equations supplied back to MISTAP QS(I) = XIBX . TS(I) (3.23) QB(I) = XIB . TB(I) (3.24) XIBIN(I) = XIBE(I) This is obtained by the same way as in MSTAPl, together with DQBl(I) = 0. 00 DQSl(I) = 0. 00 DVBE1N(I) = O. 00 DVCEIN(I) = DVCEIN(I) State model in this case is: DVB EIN DVC EIN DQ DQ -30.. Q U) Fig. 3. 4 gives the block diagram of subroutine MSTAP 2 B .. .. . + , -— VBE VIBEIN IBE RBB ICIN RBB TC RBB RBB.CBE Q C B BC I - + [V -v -I .R ] CIN TC RBB(CBE+CBC) BE BEIN BE BB C:BC.CBE + c:BC CBE I -32 B T B I -38. BX T -31- < sauvr r h v I VBEIN(I): vacuum 5 (33(1) :03! (I) VCEIN(I): mama.) i 6.561):le (I) Wag: veczurn- vcnucn J VCEIN(I) = WEIN (I) “1850:! = Ivnulml Y r F! = £9 (NB) OF! 3 :9 (Alt) CALL CUREN'T v [ XIBE(I) = XXIB'E- FI/DFI V 1 <0 1’0 >0 W VCEIN(I) xxraz = maul!) XIBC (I): E J .h. I CALL TBW >0_ A 3° mm <° mm: o " XXYY=IXIBELI)- nun/73(1):! ISATCID=O <0 7‘ )0 <“‘ BCCD' a» XIB: awn—mm gm -Tt(' may: nacct) QBCD ! ”m 1’ ISATCI): l f V ’ as = eam ITBII um: XIBE(I)-XI 191:2. manna ._-. nanm e164!) em = yuan-am 005! m =-~ 005(1 =9 0.22) 503 :. nun-5a) amass mew ”:3“ was: “22.2.. - '7 ‘3‘”) Pagan E VBE-XIBINGLRDBU) can an =oam m = DVBEIN(I): Q ”*r RETURN Y r saw I 1 i Fig. (3. 4) Block Diagram of Subroutine MSTAP 2 -32- 3. 5 Subroutine MSTAP 3 This subroutine expects to be given XIBIN(I) and VCE and supplies back enough information to determine VBE and XICIN(I). Evaluation of Differential Equations Referring to Fig. (3. 2.) and substituting Equation (3. 4) in Equation (3. Z), we get VCE = VCEIN(I)+(QB(I)/TC(I)-CBC(I) . DVBEIN(I)+CBC(I) . DVCEIN(I)) . RCC(I) (3. 2.6) Solving Equation (3. 26) and Equation (3. 3) for DVBEIN(I) and DVCEIN(I). we get [ QB(I). Room] DVBEIN(I) = XIBIN(I)-XIBE(I)+ VCE-VCEIN(I)- TC(I) J /RCC(I) CBE(I) (3. 27) DVCEIN(I) = [VCE-VCEIN(I) -QB(I,1),(°:I(‘IC;C(I) ”'Céggnggggg (XIBIN(I) - XIBE(I)] /CBC(I) . CBE(I) .RCC(I)/(CBE(I)+CBC(I)) (3. 28) together with equations (3. 21 and 3. 22). Derivatives Supplied to MISTAP DQBl(I) = DQB(I) DQSl(I) = DQS(I) DVBEIN(I) = DVBEIN(I) DVCEIN(I) = DVCEIN(I) Solution is by the use of Nonlinear Algebraic Equations Here the set of equations yielding a solution are: QB(I) = XIB . TB(I) QS(I) = XIBX . TS(I) VBE : XMBE(I) . XK . TEMP(I) C2 and XICIN(I) = QB(I)/TC(I) -33- XIBIN(I)+XIBEO(I) XIBEO(I) .1n + XIBIN(I) . RBB(I) (3.29) The following differential equations are also supplied to the integrating subroutine DQBl(I) = 0.0 DQSl(I) = 0. 0 DVBEIN(I) = 0. 0 DVCEIN(I) = O. 0 In this case the state model is: r- - r- r .,R I -I-[V -V -QB CC]_1._ DV BIN BE CE CEIN T R BEIN C CC BE V -v _QB'RCC+CBC'Rcc [I _I ] CE CEIN DV TC CBE+CBC BIN BE CEIN RCC.CBC.CBE +c CBE BC C) B DO I - — B B TB Q _ 5 DQS 1BX T_ ... J _. S Fig. (3. 5) gives the block diagram of subroutine MSTAP 3 -34- vs EIN (I) VCEIN(I) = VBEIN (1); 05(1):..— 08! = VCEIN(DJasm.-.anw XIBE (I) : XIBIN(I) fir V6 E = veer» (xx : VBE - XIBIN(I). R58! 3 I VK : VBEIN (.D - VCEINCEJ | CALL CURENT J | CALL “TI 8W éO/I\ >0 QS(I) \/ 7' <0 7 o > 0 <0 186m / r *7 - / ‘DGS I XIBE(I) - .. m": 0 WWW. Imam cam Inmllzj 1M7”!!! = O — o “WA—l m: mama. 11m $18!: 11.6!!! v ISITCU I i I -1 . r m V as = Dam/‘1’ XIII : warm-m 15AM!) :. 2. I j E com (n = Dona) “l (3.2.!) 08m = as .‘ratn 065! u: : noun < 332’ = 3131.75 (11 DVBEIN(I): DVGEIN (I) (3.21) 35%?“ = 968:9). lxlcchtxl. tcetx) ova-mm; avc an! (B (31-23) caeun .o'asun=okum- owl-emerge RETUR N r E N a Fig. (3. 5) Block Diagram of Subroutine MSTAP 3 -35- 3. 6 Subroutine MSTAP 4 This subroutine expects to be supplied with XIBIN(I) and XICIN(I) and returns back enough information to determine VBE and VCE. Evaluation of Differential Equations Solving Equations (3. 3 and 3. 4) for DVBEIN(I) and DVCEIN(I). we get: DVBEIN(I) = (XIBIN(I)-XIBE(I)+XICIN(I)-QB(I)/TC(I))/CBE(I) (3. 30) DVCEIN(I) =[XICIN(I) - QB(I)/TC(I)+(CBC(I) . (XIBIN(I)-XIBE(I))/ [CBEUHCBCUH]/ [CBC(I) .CBE(I)/(CBC(I)+CBE(I))] (3.31) Together with Equations (3.21 and 3. 22) Derivatives Supplied to MISTAP DQBl(I) = DQB(I) DQSl(I) = DQS(I) DVBEIN(I) = DVBEIN(I) DVCElN = DVCEIN(I) Solution is Partially by the use of Algebraic Equations Again, here as in MSTAP 2, VCE has to be obtained through the solution of the differential equation describing VCEIN(I). The set of equations yielding the solution are QB(I) = XIB . TB(I) QS(I) = XIBX . TS(I) VBE is given by Equation (3. 29) -36- together with the following set of differential equations: DQBl(I) = 0.00 DQSl(I) = O. 00 DVBEIN(I) = O. 00 DVCEIN(I) = DVCEIN(I) In this case the state model is: P- _I —- -'l I - I + I - Eli BIN BE CIN T DV C BEIN (3 BE (3 I -Ei§-+ 38C: [1 - I CIN TC cBE+cBC BIN BE] DV , CEIN C c BE ' Bc CBB + CBc DQB 1B - QB/TB . DQS EBX ‘ Qs/Ts Fig. (3. 6) gives the block diagram of subroutine MSTAP 4 JG '- Ele i 05 (D :QSI (I) -37- XIBE(I) : XIBIN(I) i m ' 1 VBC : vscnvm -vca~m ] Y [v CALL concur CALL TBW Y r .fi SO A Q5 (1) V 7/9 VBE = VBEIN(I):VBE - XIBIN (ILRBBm ‘ _1 >0 >7 <0 4 /0 005(1) <0 XIBCII) XIB : XIBE(I) XIBX = O 1.51"“) = O r I mm = IXIBECI) -oBm/Tsa)l/i] ——j——‘ us; AIBELD 415cm am 1) = xmum .Tcfl XIBX = {I and.) Y ISA‘I’CB - l ‘ X18 : GEL!) / TB(I) ) XIBX : unzln .. x1: ' rum) = 2. ‘n r DQBl(I) :: 058(1) 0351(1) = 1305(1) ovasmm = DVBEIN(I) DVCEIN(I): D VCEIN an Fig. (3.6) (32!) (a 22) (3.30) (3.3!) t [ RETUR N t r END . /i\ W l QB(I) : XIB .Tth) QS(I) : XIBt (TS(I) DVCEIMcn : 13w: UNI!) 96mm 3 msaln : DvaaN(I)=o J. l J Block Diagram of Subroutine MSTAP 4 -38- 3. 7 SUBROUTINE CAP This subroutine calculates the value of the junction capacitances of transistor 1, first by finding the type of transistor I, i. e. , L = ITYP(I) CBC(I) = XKBC(L) . (VO(L) - VBC)XBC(L) (3. 32) CBE(I) = XKBE(L) . (VO(L) - VBEIN(I) )XBEU‘) (3. 33) 3. 8 SUBROUTINE CURRENT This subroutine calculates the value of the current through the junction by first knowing the type of the transistor. L = ITYP(I) XIBE(I) = XIBEO(L) . (EXP(Q.VBEIN(I)/MBE(L).K . TEMP(I) )-1) (3.34) XIBC(L) = XIBCO(L).(EXP(Q . VBC/MBC(L) .K . TEMP(I) )-1) (3.35) 3. 9 SUBROUTINE TBW As has been mentioned before, TC varies with the collector to emitter voltage VCE, and Beta, the common emitter current gain varies With XICIN, the collector current, and finally TS, the saturation time constant varies with the collector current saturation level. Each of the previous variations is represented by one curve as shown in Fig. (3.7, 3. 8 and 3. 9). These curves are stored as curves with ten points representing each. Subroutine TBW performs the necessary interpolation to find TC(I), TS(I) and TB(I). Fig. (3.10) shows the block diagram of sub routine TBW . -39- A "room iVCEch (K) . Vc: F' . 3.7 Va't' fT ‘th 1g ( ) ria ion 0 C W1 VCE t1 - 35300 ! lLXICTIflK) —+ Io Fig. (3.8) Variation of TS with Collector Current :5 . u: £[77A00 Q r—..—. l XJCBE‘T ( K) 1c Fig. (3. 9) Variation of Beta with the Collector Current -40.. i L . a rrvp'ai I MI: aorL—n +1 K = MI > J °®~ <0 _. T (K) — - 01's xzcrsrm- xxcrsr/r-IS 725m: TasLK-I) +(xrc1~ <1) .- xIcrsm—n) ~D'rs F K in: j ' ’° «aw» <0 OTC :- T’CCCK‘ -TCC(K-l) VCETCM') - VCETC(K-I) TC(I) = chm- I) -r (VCE- VCETc(K-n) - DTC l K=MI E}; Y ’° «@143» <0 ' mum - BET AIK- m - x BETMD: BETAAm-n + (xzcmm - XICBE TM-l” .0357! l - - TB(I) = BETA an .Tcm J v ' RETURN [ENDJ Fig. (3.10) Block Diagram of Subroutine TBW CHAPTER IV EXPERIMENTAL C ORR ELATIONS In this part, discussion is limited to relating the suggested model to the actual device by comparing the predicted results obtained by the aid of this model and the digital computer, to those measured in the laboratory. There are five capacitances in the combined test circuit and equivalent circuit of the transistor, Fig. (4. 1). 'These are] a b Base emitter junction capacitance, CBE - Base collector junction capacitance, CBC Base emitter stray capacitance, (capacitance between base emitter leads and base emitter socket terminals), CBEX. - Collector emitter stray capacitance, (capacitance between collector emitter leads and corresponding socket terminals), CBCX. - Collector emitter stray capacitance, (capacitance between collector emitter leads and corresponding socket terminals), CBEX. The mathematical prediction starts with the base emitter junction and stray capacitances, CBE and CBEX, being the only ones existing. The other three are included individually afterwards and the effect of each is then discussed. -41- -42- The necessary differential and algebraic equations are first developed. The solution of the differential equations is by the Runga-Kutta method of numerical integration. The symbols used are in the same form of those used in the FORTRAN program so as to make it easy for anyone who wants to go through the steps in detail. CEX,/.9P,‘. H —u— II I )(Vcc,6. v. ww I AAA A'A'A'A r J“ WA 365:1“ 2:3“ I 1 l h u; l . “l ) l - a _ —-—i > 642 ~-_: ' _ “‘- 4:> 01; m l O ‘0‘; 3‘: Q h 0 l 0.1}! I |_ _ _ _ V ‘03 —.-— J...— —..—E —_:— 1E- Fig. (4.1) Complete Test Circuit and Transistor Equivalent Circuit (inside dashed lines) -43- The following tests are performed with the test circuit shown in Fig. (4. l). The transistor used is a Texas Instrument, 2N744 Epitaxial Diffused High Speed Mesa Selicon Transistor. The charge measurements were performed by the device characterization group of International Business Machines Corporation, according to the (9). method suggested by Cornell Hegedus The characteristics of the transistor are as follows: 1 - Base emitter diode junction characteristic, as given by Equation (2.17) and Fig. (2. 7). Z - Base collector diode junction characteristic is given by: IBC = o. 22x 10'“). (ezngC -1) (4.1) where, VBC is the voltage across the base collector junction. 3 - Variation of TC, the collector time constant, with VCE' the collector emitter voltage, is shown in Fig. (4. 2). 4 - The variation of TS with the collector current during saturation is shown in Fig. (4.3). 5 - The variation of beta, the common emitter current gain with IC' the collector current is shown in Fig. (4.4). The values of TC and T8 for the particular voltage level or current levelare obtained by interpolation through the use of Fig. (4. 2) and Fig. (4. 3) respectively. The value of beta is obtained by interpolation through the use of Fig. (5. 4). TB is hence obtained from: TB = B - TC (4.2) 6 - R =50hms,R =80hms,C =C =3.5p.f. CC BB BC BE -44- 3 w) 0.2, .- OJ“ \ OJ ._ m‘ ‘ O 3 1 n n l l J o r 2 3 4 5' 6 7 —» VCE (Va/b) Fig. (4. 2) Variation of TC With VCE , for ZN744 ., 1 5 4 3 )- 2 _. I _ o 1 L 1 l I n J o la 20 30 Thu” Fig. (4. 3) Variation of TS with Ic, for ZN744 g1... 0°). 60.. (,0. 30- O i 1 5 _B 0 ID ’20 W + Lew-M Fig. (4. 4) Variation of Beta with IC' for 2N744 -45.. 4. 1 Base Emitter Junction and Stray Capacitances are the only Capacitance 3 Fig. (4. 5) shows the essential equivalent and test circuits with the elements under the dashed box representing the elements of the transistor equivalent circuit under consideration. In the development that follows, the letter D before any quantity will have the following meaning: DXY -.- d(XY)/dt van/v ' VIN RE I R88 :35 RCC RC O—-vwv- +—- my)? HEN ”(l—IN— ) COLCUR flat 5'3 CBEopyfith Fig. (4. 5) Essential Test and Equivalent Circuit with Base Emitter Capacitances Being the Only Ones Included. -46- Evaluatiqn of Differential Equations where I From Fig. (4.5) C OLC UR = XICIN BASCUR = XIBIN + CBEX . DVBE XIBIN XIBE + CBE . DVBEIN VIN VBE + BASCUR . RB VBE + (XIBIN + CBEX . DVBE) . RB DVBE = (VIN - VBE - XIBIN . RB)/RB . CBEX VBE = VBEIN + XIBIN . RBB = VBEIN + (XIBE + CBE . DVBEIN) . RB DVBEIN = (VBE - VBEIN - XIBE . RBB)/RBB . CBE DQB = XIB - QB/TB DQS = XIBX - QS/TS XIB = component of XIBE, current through base emitter junction,contributing to the build up of the base charge QB. XIBX = component of XIBE contributing to the build up of the storage charge 05. XICIN '= QB/TC VCE = VCC - COLCUR . RC VCEIN = VCE - XICIN . RCC XIBE = XIBEO . [EXP(Q . VBEIN/MBE . XK . TEMP) - l] (4. (4. (4. (4 (4. (4. (4. (4. (4. (4. (4. (4. 3) 4) 5) .o) 7) 8) 9) 10) 11) 12) 13) 14) -47- Two different tests have been taken, one with a larger base drive than the other. Table I gives a summary of these results while Figs. (4.6 and 4. 7) show a comparison between the collector emitter voltage obtained mathematically and experimentally, for these two cases. The following results require the introduction of some defini- tions which are introduced below: Turn on Delay This is the time that elapses between the time the input signal is applied and the time the output signal reaches 10% of its final steady state value. Rise Time This is the time that it takes the output signal to rise from 10% to 90% of its final steady state maximum value. Fall Time This is the time required by the output signal to drop from 90% to 10% of its maximum steady state value. Saturation Time, or Storage Time This is the time that elapses between the instant the input signal drops to 90% of its final steady state maximum value and the instant that the output signal drops to 90% of its own maximum steady state value. -48- Vcsg V55 ( Vol/3) 5.0. 40- 3.0 .. 2.0 .. (.0. 40 80 IZO I (0 771»: (M) --r-v Fig. (4. 6) Base Emitter Junction and Stray Capacitances (Heavy Saturation) -49- —* ~ Vc‘¢ Vin (Va/[J \ l 5. - I) \\ _ . VCE ‘\ W EKPCYIMGVD‘ 40 )- \ \ \ \ \ 5. . \ \ \ \ \ 2. . \ \ \ \ _‘ I r- \\ \ \ \\¥ {- _ _ _ _.~ ,v (L I l A 1! [yo 80 7'2“ (nan) Fig. (4. 7) Base Emitter Junction and Stray Capacitance (Light Saturation) -50- TABLE I Comparison Between Predicted and Experimental Results When Base Emitter Capacitances are the Only Ones Included Heavy Drive Light Drive Turn on delay, n. s. predicted tdp 10 16 experiment tde 12 23 difference -2 -7 % error -l6. 7% -30. 3% Rise Time, n. s. predicted t 2. 5 5 rp experiment tre ll 36 difference -8. 5 -3O % error -77% -83. 5% Fall Time, n. s. redicted, t 12 12 P fp experiment, tfe 21 22 difference -9 -10 % error -43% -45. 5% Saturation Time, n. s. predicted, t 12 5 5P experiment, tse 16 11 difference -4 -6 % error -25% -54. 5% -5 1- To sum up the results given in Table I, although the percentage differences are rather large, the two curves (experimental and predicted) have the same form. The addition of the collector emitter capacitance should increase the delay and reduce the errors. The predicted base cur- rent will be mentioned and discussed later. 4.2 Base Emitter Junction Capacitance, Base Emitter Stray Capacitance and Collector Emitter Stray Capacitance are the Ones being Considered Fig. (4. 8) shows the test circuit and the transistor equivalent circuit with the capacitances mentioned above are the only one included. Evaluation of Differential Equations Referring to Fig. (4. 8), with symbols adjacent to nodes being names of voltages and symbols next to arrows being names of currents BASCUR = XIBIN + CBEX . DVBE (4. 15) COLCUR = XICIN + CCEX . DVCE (4. 16) XIBIN = XIBE + CBE . DVBEIN (4.17) XICIN = QB/TC (4.18) VIN = VBE + BASCUR . RB = VBE + (XIBIN + CBEX . DVBE) . RB -52- Thus, DVBE = (VIN - VBE - XIBIN . RB)/RB . CBEX (4.19) VCC = VCE + COLCUR . RC = VCE . (XICIN + CCEX . DVCE) . RC V V - Kc Vcc [N Br I Va EIN Var EIN ' v“ . A A A . . / J\ ' A A v vvv : VV‘VV _ ’T-_ VY 5 ‘IA aAscun XIUIN p me u COLCUR o 0 ¥ § 9 3 i \ in Q I Q L <,, <\ O ‘0 L c w r’ “ a __ . 8 _)__~ :— I eat). I“! ccEx Fig. (4. 8) Essential elements of the test circuit and transistor equivalent circuit. Collector emitter stray capacitance and the two base emitter capacitances are the only ones. 01', DVBEIN = (VBE - VBEIN - XIBE . RBB)/RBB . CBE (4.20) DQB = XIB - QB/TB (4.21) DQS = XIBX — QS/TS (4.22) -53- XIB and XIBX are as defined in part 5. l XICIN = QB/TC (4. 23) VCEIN = VCE - XICIN . RCC (4. 24) and XIBE = XIBEO . (EXP(Q . VBEIN/MBE .XK. TEMP) - l) (4.25) With the same set of input signals used in part 5. l the predicted outputs as compared to the experimental ones are shown in Figs. (5. 9 and 5.10). Table II summarizes these results. -54- Wt -(-Volta) a % ér'x \ )_ I 5 | I I : Pndo'dcd ’I Vc: I Enfcrimcnt I 4 - I I l‘. i | s- z 1 | | 9 2 _ ) ‘ I l | l ' I I ( \ 7 I - ‘ .I "J— ‘ \ \ ~~~~~ —._____ i 0 . . ‘7‘.” . (5 4o so ‘ «no (we 7739'") Fig. (4.9) Base Emitter Junction and Stray Capacitances and Collector Emitter Stray Capacitance are the ones considered under Heavy Drive Conditions Vc; (v. m) -55- o 30 8° ’10 I“ 75"»: pea) Fig. (4. 10) Base Emitter Junction and Stray Capacitances and Collector Emitter Capacitance are the ones included under Light Drive Conditions -56- TABLE II Comparison Between Predicted and Experimental Results for the Case When Base Emitter Junction and Stray Capacitance, in Addition to the Collector Capacitance are the only one Included Heavy Drive Light Drive Turn on Delay, n. s. - Predicted, t 12 20 dp ' 2 Experiment, tde l 2. 23 Difference O -3 % error 0 - 13% Rise Time, 11. 5. Predicted, t 2. 6 11. 5 rp Experiment, t 11 36 re Difference -8. 4 -24. 5 % error -76% -66% Fall Time, n. 3. Predicted, t 14 15 £9 Experiment, tfe 21 22 Difference -7 -7 % error -33. 3% -31. 8% Saturation Time, n. 5. Predicted, t 12. 5 5.5 5P Experiment, t 16 11 se Difference -3. 5 -5. 5 % error -21. 8% -50% -57- Thus, we see that the collector emitter stray capacitance, as expected introduced more delay in the output signal. As can be seen from Table II, the differences between the experimental and predicted results have decreased. 4. 3 Base Emitter Junction Capacitance, Base Emitter Stray Capacitance Stray Capacitance, Collector Emitter Stray Capacitance and Base Collector Junction Capacitance . Fig. (4. 11) shows the transistor equivalent circuit and the com- ponents of the test circuit with the capacitances named above being the ones considered. !_ ________ ....._-____-___._-- *4 DVOEINy DYC‘J’N) _...... . 2:»... ... ,7; "mu-13%.. “:1" L.- “(Hm _ m _,_ . __ move ' E e ‘ p g lac-3| COLCUR ii = ‘1 ii 3‘ = - 3 0}me I :3 i534: GI I #Iaccn s i T ) i ‘1 l ! T Fig. (4. 11) Equivalent Circuit of Transistor and Test Circuit with Base Collector Stray Capacitance being the only one Missing. -53- Evaluation of Necessary Differential Equations COLCUR = XICIN + CCEX . DVCE (4. 26) BASCUR = XIBIN + CBEX . DVBE (4.27) XICIN = QB/TC — CBC . (DVBEIN - DVCEIN) (4.28) XIBIN = XIBE + CBE . DVBEIN + CBC . (DVBEIN-DVCEIN) XIBE + (CBE + CBC) . DVBEIN-CBC . DVCEIN (4.29) VIN = VBE + BASCUR . RB = VBE + (XIBIN + CBEX . DVBE) . RB or DVBE = (VIN - VBE - XIBIN . RB)/RB . CBEX (4. 30) VCC = VCE + COLCUR . RC = VCE + (XICIN + CCEX . DVCE) . RC or , DVCE (VCC - VCE - XICIN . RC)/RC . CCEX (4. 31) VBE = VBEIN + XIBIN . RBB = VBEIN + (XIBE + (CBE + CBC). DVBEIN-CBC. DVCEIN).RCC = VBEIN+XIBE.RBB + (CBE + CBC) .RBB . DVBEIN-RBB. CBC. DVCEIN (4.32) VCE = VCEIN+ XICIN . RCC = VCEIN +(QB/TC -CBC. DVBEIN+CBC. DVCEIN) . RCC = VCEIN + (QB/TC). RCC -RCC. CBC. DVBEIN+RCC. CBC. DVCEIN (4. 33) From Equation (4. 33) DVCEIN = (VCE-VCEIN-(QB/TC). RCC+RCC. CBC. DVBEIN/RCC. CBC (4. 34) -59- Substituting (4. 34) in (4. 32) and simplifying, we get: DVBEIN = (VBE-VBEIN- XIBE. RBB+(RBB/RCC). (VCC -VCEIN-(QB/TC). RCC) RBB. CBE (4.35) From Equation (4.32), we get: DVBEIN = (VBE-VBEIN-XIBE. RBB+RBB. CBC. DVCEIN)/RBB. (CBE+CBC) (4.36) Substituting (4. 36) in (4. 33) and simplifying, we get: DVCEIN = (VCE-VCEIN-(QB/TC).RCC-(RCC.CBC/RBB(CBE+CBC) ). (VBE-VBEIN-XIBE. RBB) )/RCC. CBC. CB E/(CBE+CBC) (4. 37) DOB = XIB - QB/TB (4.38) DQS = XIBX - QS/TS (4. 39) and XIBE = XIBEO. (EXP(Q. VBEIN/MBE. XK. TEMP)‘-l) (4.40) where XIB and XIBX are as defined previously. Comparing Equation (4. 30) to Equation (4. 17), we notice that they are the same. However, when comparing Equation (4. 35) to Equation (4. 20) we notice that DVBEIN is increased by: (VCC - VCEIN - (QB/TC) . RCC)/RCC . CBE This quantity is negative during turn on and positive during turn off, i. e. , DVBEIN is reduced during turn on and is increased during turn off. This means more delay for VBEIN, referring to Equation (4. 40), this means more delay to XIBE, the current that builds up the charge QB in the base. Equation (4. 37) now replaces Equation (4. 24) which implies that VCEIN does not change instantaneously any longer, but is delayed. -60- 13 i V ~f 3’. 6 tr") 5 - 1’ .. 3 L. 2 h— l I 1 l \ It" \ _-_.1_ \ ‘L \ “ __________ _\-’ 1 L J l o 40 to M0 “:0 M Fig. (4.12) Base Emitter, Collector Emitter and Base Collector Junction Capacitances with Heavy Base Drive -61- § § u: g 6. VCE Experiment. 4. 3. 2. I. \ \‘ .- ~~—— — -——-\_,l 0. I i l J o 40 80 I20 I60 WIN-J Fig. (4.13) Base Emitter, Collector Emitter and Base Collector Junction Capacitances with Light Base Drive -62- From Table III, it is seen that the consideration of the Base Collector Junction Capacitance brought the errors close to 10% margin. The delays were increased as was eXpected from the differential equations. TABLE III Comparison between Predicted and EXperimental Results when Base Collector Stray Capacitance is the only one Omitted. Turn on Delay, n. s. Heavy Drive Light Drive Predicted, t 12.5 20. 5 dp Experiment, tde 12 23 Difference +0. 5 -2. 5 % error 4.15% -10. 9% Rise Time, n. 5. Predicted, t 8 29 rp Experiment, t 11 36 re Difference -3 -7 070 error -Z7. 3‘70 -19. 50/0 Fall Time, n. 5. Predicted, t 18. 5 20 fp Experiment tfe 21 22 Difference -2. 5 -2 % error -11. 5 -9. 1% Saturation Time, 11. 3. Predicted, t 14. 5 6. 5 5P Experiment, tse 15. 5 10 Difference -1 -3. 5 % error -6.65% -35% -63- 4 . 4 A11 Capacitances are Included Fig. (4. 14) shows the total equivalent circuit with all the capacitances (junction and stray) being included. cwwvaz- pvt-e) Jl —F If I'_' ' ' ' ' éac(pvaém—-5Wu-7-'_I JL M MW at; ' call W . m: f ”9 I has VBEIN ”’VBC T \ I R“ I I M I - _ _ _ PT _ _ _ . my; 1:: . 1717' 73:? Wk g) Ililfilii 51"” ”Ga 5 -> <> item 11 4)— Fig. (4. 14) Essential Elements of Test Circuit and Transistor Equivalent Circuit Including all Capacitances Evaluation of Necessary Differential Equations Referring to Fig. (4.14), we can write: COLCUR = XICIN + CCEX . DVCE - CBCX . (DVBE - DVCE) = XICIN + (CCEX + CBCX) . DVCE - CBCX . DVBE ' (4.41) ~64- BASCUR .-. XIBIN + CBEX . DVBE + CBCX . (DVBE - DVCE) = XIBIN + (CBEX + CBCX) . DVBE - CBCX . DVCE (4.42) XICIN = QB/TC - CBC . (DVBEIN - DVCEIN) (4.43) XIBIN = XIBE + CBE . DVBEIN + CBC . (DVBEIN - DVCEIN) = XIBE + (CBE + CBC) . DVBEIN - CBC . DVCEIN (4.44) VIN = VBE + (XIBIN+(CBEX+CBCX).DVBE-CBCX. DVCE).RB = VBE+XIBIN. RB+(CBEX+CBCX). RB. DVBE-RB. CBCX. DVCE (4.45) VCC = VCE + COLCUR. RC VCE + (XICIN+(CCEX+CBCX). DVCE-CBCX. DVBE). RC VCE+XICIN. RC +(CCEX+CBCX). RC . DVCE-CBCX. RC . DVBE (4. 46) From Equation (4. 46) DVCE = (VCC -VCE-XICIN. RC +CBCX. RC . DVBE) /RC(CCEX+CBCX) (4. 47) Substituting Equation (4. 47) in Equation (4. 45) and simplifying, we get: DVCE =[v1N-VBE-XIBIN.RB+RB.CBCX.(VCC-VCE-XICIN.RC)] / RC. (CBCX+CCEX) [RB. (CBEX + CBCX.CCEX) (4.48) CBCX+CCEX From Equation (4.45), we get DVBE = (VIN-VBE-XIBIN.RB+RB.CBCX.DVCE)/RB.(CBEX+CBCX) (4.49) Substituting Equation (4. 49) in Equation (4. 46) and simplifying, we get: -65- VCC—VCE-XICIN. RC + RC. CBCX. (VlN-VBE-XIBIN. RB) RB. (CBEX + CBCX) DVCE: - RC. [CCEX + CBEX.CBCX CBEX+CBCX (4.50) VBE -_- VBEIN + XIBIN . RBB = VBEIN + (XIBE + (CBE + CBC) + DVBEIN - CBC.DVCEIN).RBB = VBEIN + XIBE.RBB + RBB. (CBE + CBC).DVBEIN-RBB.CBC.DVCEIN (4.51) VCE = VCEIN + XICIN . RCC VCEIN + (QB/TC -CBC . DVBEIN+CBC . DVCEIN). RCC VCEIN + (QB/TC).RCC + CBC.RCC. DVCEIN - CBC.RCC.DVBEIN (4. 52) Solving Equation (4. 51) and Equation (4. 52) for DVBEIN and DVCEIN, we get: (VBE-VBEIN—XIBE. RBB+RBB. (VCC -VCEIN-(QB/TC). RCC)/RCC) DVB EIN = RBB . CBE (4. 53) and, VCC-VCEIN-(QB/TC). RCC + RCC. CBC. (VBE-VBEIN-XIBE. RBB) DVCEIN = RBB. (CBE + CBC) RCC . CBC.CBE/(CBE + CBC) (4. 54) In addition, we have: DQB = XIB - QB/TB (4. 55) DQS = XIBX - QS/TS (4. 56) XIBE = XIBEO.(EXP(Q.VBEIN/MBE.XK.TEMP) - 1) (4.57) -66- Equations (4. 53 and 4. 54) are the same as Equations (4. 35 and 4. 37) while Equation (4. 30) is now replaced by Equation (4. 48) and Equation (4. 37) is replaced by Equation (4. 50). This shows that the effect of the base collector stray capacitance is to increase the delay of the output signal by increasing the delay of VBE and VCE, while the junction capacitance CBC increases the delay of the output signal by increasing the delay of VBEIN and VCEIN. Figures (4. 15 and 4. 16) show the eXperimental and predicted curves for this case and Table IV summarizes the results. From Table IV, we see that the differences are within 10% which are reasonable considering the errors made in reading and plotting the results and also in measuring the parameters. -67 .. VCE ( Volt: ——U- VCE Evcvimnc 6 ( I / ‘ ' Pvedicbd | _ J 4 )- i, 3 .. 0 2 . I . "‘~*----~.7 O L 1 l 1 o 40 so 120 "9 mum Fig. (4.15) Base Emitter, Collector Emitter and Base Collector Junction Capacitances under Heavy Drive Conditions -63- 77“ ems.) Fig. (4.16) Base Emitter, Collector Emitter and Base Collector Junction Capacitances under Light Drive Conditions ~69- TABLE IV Comparison Between Experimental and Predictable Results with all Capacitance Included Turn on Delay, n. s. Predicted, t 12. 25 22.5 dp ' 2 Experiment, tde 12 3 Difference 0. 25 0.5 % Error 2. 08 -2. 18% Rise Time, n. s. Predicted, t 10 37. 5 rp EXperiment, t 11 36 re Difference -l 1. 5 % Error -9. 1% 4.15% Fall Time, 11. s. Predicted, t 22. 5 23 fp Experiment, tfe 21 22 Difference 1. 5 l % Error 4. 15% 4. 55% Saturation Time, n. s. Predicted, t 16 9 3? Experiment, tse 15. 5 10 Difference 0. 5 -1 % Error 3. 22% -10% -70.. Summing up, Fig. (4.17) shows the outputs of cases 5.1, 2, 3, and 4, as compared to the experimental output; under light drive conditions. Defining the TURN OFF DELAY as the time elapsed between the moment when the input signal falls to 90% of its final steady state value, and the moment when the output signal falls to 50% of its maximum steady state value. Table V gives a comparison of the turn off delay time for each of the four previous cases. TABLE V Effect of Difference Junction and Stray Capacitance on the Turn Off Delay Time Experiment Predicted Difference %error Heavy Driving Conditions Case a 25 15 -10 -40% Case b 25 16 —9 -36% Case c 25 22 -3 -12% Case d 25 24 -1 - 4% Light Driving C onditions Case a 16.5 8 - 8.5 -51.5% Case b 16.5 10 - 6.5 -39.4% Case C 16.5 13 - 3.5 -21.2% Case (1 16.5 15.5 - l - 6.1% VCE ( ”It” -71- 5 - ‘_ vs: . M . 1‘ Ever/men . // ./ ‘ 11 // x" 5' .. ( ./ 1'I '(1 // g 1 11 ~’ 1 .1 j 1 . ‘1 Bl! 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Figures (4.18) and 4.19) Show the predicted base currents for the case when the base emitter capacitances are the only ones included, and the case when all capacitances are included, together with the eXperimental result. In the case of heavy drive condition, the error in the maximum steady state magnitudes is 0. 25/4. = 6. 25%, and in the case of light drive it is 7%. This error could be due to an error in reading the bias voltage, as a very small error in reading this quantity will result in a relatively large error in the base current, which depends greatly on VBEIN, and this voltage is the eXponent of the exponential term in Equation (4. 57). -75- 4. 5 Additional Test Circuits The test circuit shown in Figure (4. 20) was used in testing the transistor model with a sine wave input and a triangular wave input with a resistive load and an inductive load. VIN I66 .3 2” 7“ o——-M 1169.541 Fig. (4. 20) Test circuit used with sine and triangular wave inputs. In the following discussion, Cases a, b and c will refer to the following: Case a, repetitive triangular wave form input, 100 n. 8. cycle duration time, with resistive load, L = 0 Case b, repetitive triangular wave form input. 100 n. 8. cycle duration time, with inductive load, L = 2).).H Case c, repetitive sine wave input, 100 n. 8. cycle duration time, with resistive load, L = 0. -76 - Figures (4. 21, 4. 22, and 4. 23) show the predicted and experimental input and output wave forms in these three cases. 4. 6 Discussion In this chapter the suggested equivalent circuit of the transistor was tested. Three different circuits were used, capacitive, resistive and inductive. The correlations between the experimental and predicted results were very good with resistive and capacitive circuits. However, with inductive circuits the correlations were not quite as good. Although the difference in case of the inductive load was comparatively high, the predicted wave forms have almost the same shape. The main error in case of inductive loading is in the rise and fall times, however, the turn on delay and storage time are fairly accurate. .m ammo cm mfismom Couofiuonm new fiducofimuomfim Goosfion mcomumfiouuou :N .wv .mfm an...» def. 2.6 «EFF I'll. t ad 3 3 QR O 8 ow 0* 3.x 0 m - d a 0 q _ q . \x‘/ 1 I l o ‘thotisdnxxu CS, /.- . . . was}. - -77- «.0 9.0 we 0.x 1 m. $93.1dtk T \ngseammfl — 35 J q. l «— ( $1,011) 2191 WA “WM)JQI Cnéyotfir 1 an -78- -3fi§if§m um.- 35%....- .n ommU 5 mafia-mom 630:6on Una fiausoemnomxm Coos-$03 mcofimfiounou ANN .vv .wmh 2.5 232.. (SI/04 229M191 «.0 ed «.0 o< N< 3 0.x +— mflfi) 30A -79... _\ VCE(Vb//5) Expewmcrfa/ / Pfedl‘c. teaL 1.2 _ .\ 1 0.8 . o.“ - 1. O 1. (1- 1. VIN‘VRLT Vol.6) O ‘ 20 Ila 6.0 so __ . .. lo a —’ ‘Timc (in-So) I 1.- VIN ' ' P. 1.1 /._..__..--__.._.__~‘ ech {VBE / \ .\ £xpew'menbl . 77:10:66) 0 1 1 w 2.0 40 _..] _ Fig. (4. 23) Correlations between Predicted and Experimental Results in Case c. CHAPTER V CONCLUSION The previous study has shown that the suggested transistor model is capable of giving a good approximation to the actual device performance, at least in most of the cases tested. The incorporation of the defined partial saturation region was significant in predicting collector saturation voltage levels close to the actual ones. The computer analysis program allows the use of the transis- tor in all possible modes of interconnection. When the circuit time constant is large compared to the time increment required to solve the state model, MISTAP has the advantage of reducing the solution time to a minimum through the use of numerical techniques to solve nonlinear algebraic equations. In cases when the collector emitter is selected as a branch, the solution must be achieved through the use of differential equations, independent of the time constant of the external network, since there is no direct relation between the base control charge OB, and the collector emitter voltage. Future work should include investigation of the validity of the suggested model in describing different transistors and in its use in different types of circuits. The effects of inductive loading on rise and fall times should be investigated. Also, work should be done in order to make possible the use of algebraic equations alone to solve cases when the collector emitter is selected as a branch, and the time constant of the external network is much greater than that of the transistor. -30- APPENDIX I SOLUTION FOR THE CURRENT THROUGH A P-N JUNCTION WHEN THE VOLTAGE‘IS SPECIFIED BY NEWTON RAPHSON METHOD Consider Fig. (A-1) and assume that the current through the p-n junction is given by KV _ D ID _ 10 (e -1) (Al) R Wfi r In -—..—E Y0 SE Fig. (A-l) P-N Junction in Series with a Resistance KV D = - .. 2 Let F ID Io(e 1) (A ) KVD : d - dF ID KIOe dVD (A3) we want F so that F + dF = 0 KVD KVD or (HD - KIOe dVD = - ID + Io(e - 1) (A4) E - V now ID =—-—R'—D- (A5) dV _ D or (HD — -T_ (A6) -31... -32- Substituting (A6) in (A4), we get D 0 WI“ KVD KVD -[ dV +KI e dVD]=-1D+Io(e -1) KV l D ‘. dVD = [”113 + K1 -1)] (A7) KV 0e D1] [ +1D -10(e In order that the effect of the external circuit on dV be neglected D KVD < < KIOe as KID 211'“ K as 40 for IDzlmA 1 3 §<<40x10- or R > > 25 ohms IfID=10mA Il{<<40x10- or R > > 2. 5 ohms So, in general, the change in dV should be considered. However, the following discussion will show that the effect of including the varia- tion in dV is only to slow the convergence and will not affect the final answer. Referring to Fig. (A2), for any voltage VD, there will always exist a current ID, hence during solution, the voltage and currents will oscillate between two finite limits. At these limiting points dV =-x dI (A8) where: x > 0 -33- 10 -—-—~ Fig. (A2) Diode Characteristics Substituting (A8) in (A3), we get 2» KV D dF — (dID + KX Io e dID) (A9) a: (1 + KX ID). dID dF d—I-I3=1+KXID and hence the iteration formula is I =1 - A10 D1 D0 1+KXI ( 1 if the variation in dV is not included I :1 -F(I D D0 D0) (Al 1) -34- From Equations (A10) and'(A11), it is obvious that the effect of including the variation in dV is simply to prolong the iteration time. If X in Equation (A10) is such that = -1 KXIDO a solution cannot be obtained although it exists. Thus, in order to avoid problems and to get faster iteration, the effect of dV is neglected. In MISTAP, the base current was described by = . K VBE .. . .. 12 1B IBO (EXPF( 1 IB RBB) ) 1) (A ) F = IBO.(EXPF(K(VBE - IB.RBB) ) - 1) - 13 (A13) DF = - K.RBB.IBOEXPF(K(VBE - IB.RBB) ) - 1) (A14) and the iteration formula is F(IBO) 13 = 130 - W) (A15) APPENDIX 11 SOLUTION FOR THE VOLTAGE ACROSS A P-N JUNCTION WHEN THE CURRENT IS THE SPECIFIED VARIABLE Referring to Equation (A1) for any current ID ) -IDO there will always be a unique voltage VD. Rewritting Equation (A1) KV D ID - ID0(e - 1) ID + IDO KVD or _I—_ : e DO V - 1- ln ID + IDO D K IDO ' I +1 F .11., 1.. _DI__22_ -VD (11., D0 1 ID0 dF=—.-——-——-——.dI ~dV (A17) K ID + IDO D D it is again required to have dF such that F+dF=O l IDO dI dV - 11n IDHDO +v + "" __ D K ID.IDO D D K IDO Referring to Fig. (Al) and substituting Equation (A6) in Equation (A1 7), we get 1 E ' I :3: +9» dID= -— 1n ———D1 D0 +vD (A18) D D0 D0 -86- in order that the effect of the external circuit be neglected. I I R<