OVERDUE FINES ARE 25¢ PER DAY PER ITEM Return to book drop to remove this checkout from your record. A NWV SYNCHRONIZED DIGITAL CLOCK By David Alan Cooper A THESIS Submitted to Michigan State University in partia] fulfiiiment of the requirements for the degree of MASTER OF SCIENCE Department of Electricai Engineering and System Science 1979 ABSTRACT A wwv SYNCHRONIZED DIGITAL CLOCK by David Alan Cooper This work contains the details of the design of a wwv synchronized digital clock. The microprocessor-based digital clock automatically sets itself to the correct time using the encoded time information in the 10 MHz wwv transmissions. (wwv is a station operated by the National Bureau of Standards dedicated to the continuous transmission of time information and radio wave propagation conditions.) Once the digital clock has set itself it will frequently update the displayed time in order that it never varies from the correct time.‘ The WNV synchronized digital clock described in this work differs from previous ones in that it is a consumer-oriented and inexpensive device. ACKNOWLEDGEMENTS I wish to express my gratitude to Dr. Marvin Siegel for his review of the manuscript. In addition, I wish to thank Dr. Lawrence J. Giacoletto for encouraging me to undertake this project. ii II. III. IV. TABLE OF CONTENTS Page INTRODUCTION ....................... 1 1.1 Background ..................... 1 1.2 NWV Time Code .................... 3 SYSTEM ORGANIZATION ................... 6 2.1 Introduction .................... 6 2.2 Clock Subsystem ................... 6 2.3 Receiver and Signal Conditioning Subsystem ..... 8 2.4 Microprocessor Subsystem .............. 8 HARDWARE ORGANIZATION .................. 10 3.1 Analog Hardware Implementation ........... 10 3.1.1 Receiver ................... 10 3.1.2 Filters ................... 12 3.1.3 ‘Tone Decoders ................ 16 3.2 Digital Hardware Implementation ........... 21 3.2.1 Microprocessor ................ 21 3.2.2 Clock .................... 26 SOFTWARE ORGANIZATION .................. 33 4.1 Introduction .................... 33 4.2 Seconds Set Routine ................. 33 4.3 Interrupt Routine .................. 35 4.4 Coder Routine . . . . . . . . . . . ......... 40 CONCLUSIONS ....................... 42 APPENDIX -- ASSEMBLY LANGUAGE PROGRAM LISTING ...... 44 LIST OF REFERENCES .................... 48 iii LIST OF TABLES Table Page 1 Time Zone Setting .................... 9 2 Pulse Type Decoding Method ............... 36 iv LIST OF FIGURES Figure £353; 1 NNV Time Code ...................... 4 2 Example of NNV Time Code ................ 5 3 System Block Diagram .................. 7 4 Receiver Block Diagram ................. 11 5 Receiver Schematic ................... 13 6 Sallen and Key Lowpass Filter .............. 15 7 Filter Circuit Diagram _ ................. 17 8 567 Tone Decoder .................... 18 , 9 Fast Response, Narrow Band Tone Decoder ......... 20 10 Dual Tone Decoder Detection Bandwidth .......... 20 11 Tone Decoder Circuit Diagram .............. 22 12 CDP1802 Pin-Out ............. , ........ 24 13 Microprocessor Circuit Diagram ............. 25 14 Clock Block Diagram ................... 27 15 Frequency Divider Circuit Diagram ............ 28 16 Clock Circuit Diagram .................. 3O 17 Multiplexer Circuit Diagram ............... 31 18 Display Circuit Diagram ................. 32 19 Seconds Set Routine ................... 34 20 Bit-Packing of Record .................. 36 21 Interrupt Routine .................... 37 22 Interrupt Routine (Continued) .............. 38 23 Interrupt Routine (Continued) .............. 39 24 Coder Routine ...................... 41 CHAPTER I INTRODUCTION 1.1 Background Devising an accurate timepiece is a problem man has been endeavoring to solve for thousands of years. In the past, sundials, hourglasses, and mechanical timepieces were used to keep time. These devices are very inaccurate, by today's standards, because of the inher— ent inaccuracy of their timing sources (sun, sand, pendulum, spring, etc.). Today, most timepieces derive their timing signals from either a quartz crystal oscillator or the 60 Hz power line frequency. A fine quartz timepiece has very good short term accuracy (about 1 part in 108) but because of frequency drift by the oscillator it will gain or lose about 30 seconds a year. On the other hand, a clock with a 60 Hz line frequency time base has poor short term accuracy (about 1 part in 104) but for the long term it will normally vary less than 2 seconds from the correct time. Of course, the time on any clock dependent solely on the power from an electric utility company can greatly vary from the true time if a power outage should occur. The National Bureau of Standards (NBS) in Boulder, Colorado, operate a cesium beam clock which is used as the world time standard. The frequency of the cesium beam controlled oscillator in the clock is one of the stablest frequencies in existence (stable to 1 part in 1012).(1) The standard time maintained by NBS is called Coordinated Universal Time (UTC). NBS broadcasts coded UTC on the shortwave fre- quencies of 2.5, 5, 10, 15, and 20 MHz from their station NWV located in Fort Collins, Colorado. The objective of this thesis is the design of a clock that will interpret the coded UTC transmissions from wwv and display that infor- mation. Ideally, this clock will have the short term accuracy of a quartz crystal oscillator and a long term accuracy better than the 60 Hz line frequency. If the power to the clock is interrupted for any period of time, when it resumes the clock will automatically set itself. While clocks that derive their time from NBS already exist com- mercially, they differ from the one described in this thesis in two important aspects.(2) First, the commercial models are made to be used in a scientific research establishment and therefore are relatively expensive instruments (greater than $2500). The clock described in this thesis is aimed at the consumer and will be much less expensive. Secondly, most of the commercial models use the 60 KHz NHVB transmission which requires the use of a bulky antenna that must be mounted exter- nally of any structure. The 10 MHz wwv broadcast, the clock described herein uses, can be received on a telescoping whip antenna thus enabling the clock to be made into a self-contained unit. Because of the daily periodic changes in the ionosphere, only the shortwave frequencies above approximately 10 MHz will propagate over long distances during the day and only the frequencies below about 11 MHz will propagate over long distances at night. Based on the above fact the 10 MHz HNV frequency was chosen for the clock because it is the only wwv frequency that can be received during both the day and night. 1.2 NNV Time Code The coded UTC information is transmitted continuously by NNV. NBS has employed a method of encoding the time of the day and day of the year that requires an entire minute to transmit.(1) Figure 1 shows the envelope used to modulate a 100 Hz subcarrier of NNV. A pulse occurs once each second except the zeroth second of the minute. The leading edge of every pulse coincides with the start of the second and the pulse width determines whether it is a coded zero, one or marker. The pulse width of a coded zero, one and marker is 0.2, 0.5 and 0.8 seconds respectively. Each minute is divided into six ten-second segments called frames. A marker occurs every tenth second marking the end of the frame. The fifth second of each frame is always a coded zero. Thus only eight seconds of a frame remain to carry coded time information. The eight bits of data contained in these eight seconds will henceforth be re- ferred to as a record. The first record of the minute always consists entirely of zeros. The second record contains the minute information in binary coded decimal (BCD). Note that the first four bits of the record are the units and the last four are the tens of the coded number in binary. The third record contains the hour information encoded the same as the minutes. The remaining three records contain day of the year and time correction data not used by this device. Figure 2 exem- plifies the NWV time code, showing the relevant part of the code that would be transmitted beginning at 21:39:00. NNV broadcasts contain additional information along with the en- coded time. Of major interest is a 1 KHz tone burst that occurs at the start of each minute and has a duration of 0.8 seconds. C) \O auoo asp» >3: -- H a2=m_E C ‘ LO 1 L: [: C E E E I: Cl: C: C: O H om sigma..- mums—o5: oq . ,. i a _, _ u. : : c : c c g; 2L .T .... oe weak --m»ao-- move: om . l . q- q _ _ .- - a _ _- q .l . a- . a- _ _ a a a a c a a a a ..| .I .l .I .l .I .i .l om mcmh Timezozun mic: ow . ,- a _, H d i 4 d _ . _ .. . _ _ _ _l_ E .NL LL. C Eul— ZJI— .N; Lul— .| .l .l .l .l .I om mew» T. 3:52.... 3.25 oH . .T d — q ii 4 a i q «T q i q _ u - _ _. _l_ .w; .NHI_ .HL __ .w.r|_ .e .mul_ Lul— .l _I .I .T .I .I .u .m A I p E. E3... L: :H aeHH umuou >33 to mHasmxm -- N arsmHE om . , om . —IIII— #I— —I_ fit u o o H o H u o o o H ON oH ll rrlllll , Fl u. Jfl o H 1Imul m u H o o H oH w H m m - e m N H o F T HI . oonmmHHN p50; $5 pm 95...— CHAPTER II SYSTEM ORGANIZATION 2.1 Introduction A block diagram of the self-setting clock is illustrated in Figure 3. The system is divided into three main parts: the clock, the microprocessor (DP), and the receiver and signal conditioning section. 2.2 Clock Subsystem The Clock consists of a divider, six counters, a multiplexer, and a display. The counters are connected to count in the typical hours- minutes-seconds fashion. The outputs from the counters are time multi— plexed using timing control signals from the divider. The display decodes the multiplexed counter outputs and displays the time informa- tion on six multiplexed LED digits. Time is kept by the clock essentially independent of the rest of the system. A 1 Hz pulse train needed to drive the seconds counters of the clock is obtained by dividing down the signal from a high frequency crystal oscillator. The short term accuracy of this 1 Hz signal is sufficient to keep the clock reasonably precise during intervals when the transmission from WWV is not received. There are three inputs to the clock that are under.uP control: the seconds set, the minutes and hours reset, and the minutes clock. The seconds set allows the DP to set the seconds to one. With the minutes and hours reset input the DP can zero the minutes and hours counters. mam mmmcco< Emcmmwo xoopm Emumzm I- m mesmwm puma: .2: a .cHz Hz . zwmumm -- e «Laure zap: plullo 3:: owu=< mmmaZoH u, Louompma Lopmppwomo Hmumxgu All! 22:33 EH mewz HHaurHu coca» LOHCHHQE< é 12 and the 9.545 MHz signal from the crystal oscillator are mixed to pro- duce the sum and difference frequencies of 19.454 MHz and 455 KHz respectively. The IF amplifier amplifies and bandpass filters the 455 KHz signal. It provides the signal with approximately 60 db of gain within the 3 KHz passband. The 455 KHz signal is finally envelope de- tected, lowpass filtered and presented at the audio output. The receiver schematic is shown in Figure 5. The three transistors are idential n-channel JFET's. 01 is the RF amplifier. 02 and Y1 form the crystal oscillator. 03 perfbrms as the mixer. The heart of the re- ceiver is the commercially available, prepackaged IF strip which pro- vides most of the gain and filtering to the signal. A diode detector and lowpass filter are contained on the IF strip. The inductor L1 is 30 turns of #26 wire on a 8 inch fbrm tapped at 15 turns. The antenna is a 51 inch telescoping whip type. The IF transformer and IF module together form J. W. Miller part 8902-B. 3.1.2 Filters The requirements of the lowpass filters are that they must pass the desired tone frequency (f0) and sufficiently attenuate its harmonics (2f0, 3f0, etc.). Consider the lowpass transfer function K T (S)= LP SZ+wCS+ — w 0 c where we = erfo. The normalized log magnitude of this transfer func- tion is given by: 13 ovumsmcom 333mm E. m 953“. muwomm gmppwz mzmx ucm mpsuoz mm mHoom am: no u:w.~o .Ho a ~22 mvm.m > x omm > Nfi+ .i -uaH ;.uaom ugoem Haapao oHu=< 14 T (.iw) wz LM[—l:£-K—-—]= 20109((1-F)2+(:J;)2 )5 C Q is choosen to be one so that the filter will not ring and cause spurious outputs from the tone decoder. With 0 equal to one the log magnitude can be evaluated at w = (”c and w = Zw‘:. When this is done it is found that the log magnitude of the transfer function at 2tfi: is approximately 8 db down from In which was experimentally fbund c to be a sufficient attenuation. The Sallen and Key lowpass filter in Figure 6 has the transfer function k - RIRZEIEZ Tv“) 52+S(1+1+I-k)+ 1 R1C1 R2‘31 chz R1R2c1c2 r where k = 1 --;g.(5) Comparing Tv to TLP the design equations are 1 found to be w =( 1 )l5 0 = wc K= k C I{17526162 1 + 1 + FF Rleclcz Choosing C1 = C2 = 1 and R1 = R2 and substituting into the design equations yields - -._1._ = -_1_ = _._1_ Rl—szc k 3 Q r2 r1(2 Q) The highpass filter was devised by first designing a Sallen and Key lowpass filter with the desired cutoff frequency (fc = 90 Hz) and then making a lowpass to highpass transformation. This transformation 15 pao cmupmm mmmaon aux can coppmm .. o ocammm UNJI |\ + \u/ -_T_- 16 is made by replacing the resistors in the lowpass circuit by capacitors of value 1/Rug: and replacing the capacitors in the lowpass circuit by resistors! of value 1/C wc where u) = 21rfc. The highpass filter ob- c tained by this transformation has the same cutoff frequency and rolloff characteristics as its lowpass counterpart. After determining the nominal element values from the design equa- tions, impedance scaling is used to obtain practical element values. Using this method, an impedance scaling factor is. choosen; all of the nominal resistor values are multiplied by this factor and all of the nominal capacitor values are divided by this factor to get the final element values. The circuit for the filter section is illustrated in Figure 7. The overall gain of the section is adjusted by varying R4 to obtain the optimum signal level to drive the tone decoders. The cutoff frequency of the first lowpass filter is 1 KHz and fc = 100 Hz for the second one. The large resistor values, which would be unacceptable for use with 741 op amps, can be used with the CA3140 op amps because of their extremely high input impedance (1.5 teraohms). 3.1.3 Tone Decoders A block diagram of a 567 10 tone decoder is illustrated in Figure 8. The 567 consists of a current controlled oscillator (CCO), a phase detector, and a quadrature phase detector (QPD). The CCO and phase de- tector are connected in a typical phase locked loop (PLL) configuration. When a tone within the PLL's bandwidth (capture range) is present at the input the PLL will go into lock and output a 90 degree phase shifted version of the tone to the QPD. The QPD multiplies the input signal with the output of the PLL and produces a DC voltage which drives the 17 Emgmmmq uwsocwu cmppwm .. n ocamwo _ x oH x OH 41 . . cmuoooo wcop NI ooH op _ 5. .32 x omH x omH Hr) .— LH E . EH .. .. cwuoomo 2.8. II |.. h. 5. H B 1:1! V. 9: TIoHHacH g H . . oHu3< x o... 25 o “.5 m .V . ~_ ‘— x own)<. 18 567 Input Phase .———9— Detector ‘ 1C1 Loop -:[;Lowpass Filter - -1 R0 CCO I ~ , +5V Co H. QPD Output "“ C2 Output I Filter Figure 8 -- 567 Tone Decoder 19 output transistor into saturation. If the tone at that input is out- side the PLL's bandwidth the QPD will multiply the input with the CCO's center frequency and produce an AC voltage which is effectively shorted to ground by the output filter capacitor and keeps the output transistor in the off state. When the transistor is off no current flows through RL and the output is at a logical high voltage. A saturated transistor has approximately a 0.2 volt drop across it bringing the output down to a logical low voltage. The CCO's center frequency is set by choosing appropriate values for R0 and C0. The value of Cl, the loop lowpass filter capacitor, determines the bandwidth of the PLL. An important design trade-off exists in choosing the value of C1. Increasing the value of C1 de- creases the bandwidth of the PLL which is highly desirable but it also increases the amount of time required to lock on to the signal. Since the leading edge of each of the tone bursts signify the start of a second, the lock-up time should be as short as possible to enable the uP to accurately set the seconds. Another design trade-off appears in determining the value of C2 the output filter capacitor. Increasing the value of C2 increases the ability of the tone decoder to reject noise and close out-of-band signals but also increases the turn-off time. The turn-off time is critical when measuring the length of the tone bursts and therefore should be made as short as possible. A method of obtaining a fast response, narrow band tone decoder is shown in Figure 9.(3) This method utilizes two 567 tone decoders each of which has a wide bandwidth and therefore a fast response. One 567 has a center frequency a little above and the other a little below the desired tone to be detected. The two outputs are OR'ed (logically 20 567 Input OUT Output 1F-—-Tr—-————- In Unit 1 567 Out In Unit 2 Figure 9 -- Fast Response, Narrow Band Tone Decoder Total Detection Bandwidth «I r- Unit 1 Detection BW Unit 2 Detection BW I f1 Figure 10 -- Dual Tone Decoder Detection Bandwidth fi- f O 21 AND'ed) to produce a tone decoder with a bandwidth equal to the overlap of the individual 567's bandwidths (Figure 10). Note that the 0R func- tion is used because of the negative logic outputs of the 567's (i.e. a tone present equals a logic zero). One small problem with this design is that the bandwidth of the 567's decrease as the signal level decrease below 200 mV. If this should occur there may be no overlap of the two bandwidths causing the desired tone to be rejected. So effort must be made to keep the signal level above this threshold. Two of these fast response, narrow band tone decoders are used in this system: one to decode the 100 Hz tone and the other for the 1 KHz tone. Each decoder uses an XR 2567 IC which contains two independent 567's. The schematic of the tone decoding section of the system with appropriate component values is illustrated in Figure 11. 3.2 Digital Hardware Implementation CMOS digital logic is utilized throughout the digital portion of the system because of its low power consumption and wider variety of logic functions available on IC's in comparison with other logic fami- lies. Although most CMOS logic can operate anywhere in the range from 3 to 18 volts, one 10, namely the E-PROM, requires 5 volts; therefore, to conserve on the number of power supplies, all the logic operates off of 5 volts. 3.2.1 Microprocessor The uP used in this system is the RCA CDP1802 COSMAC microproces- sor.(6) The CDP1802 was selected for the following reasons: CMOS 22 Emcmmwo uwsucwu Lmuoomo mach -- HH mcamwo I Home“ Sex allocH 5. H H H Vs “3H law—ma 23H _ - >m+ m . . 0H m u. ..H.. m 2 III HHH W... 33 h mun .... >m+ H >m+ >m+ H sow—NHL “EH “—1“.on E. 3.8 IS NI 2: Nb oh new» god >m+ -iI' on >m+ 23 logic, powerful instruction set, and single power supply. A pin-out of the CDP1802 is provided in Figure 12. The speed of the uP is deter- mined by the frequency of the crystal connected between the CLOCK and YTAE inputs. This frequency was choosen to be 2.097152 MHz (221 Hz) because it is easily divided down to provide a 1 Hz signal for the clock. Figure 13 shows the circuit for the microprocessor section of the system. Connected to the bi-directional data bus are: a 1024 by 8 bit E-PROM, a 32 by 8 bit RAM, and an interfaced set of switches. Ad- dresses 0000 to 03FF access the E-PROM and 040016 to 041F16 access 16 16 the RAM. When addressing memory the DP puts the upper 8 bits of the address on the address lines first. The 4042 4 bit latch is used to decode the upper part of the address. The three upper address bits needed for this memory structure are latched in the 4042 by the trail- ing edge of TPA (a timing signal from the uP). The state of the switches is read when the uP executes an INP 4 instruction. The execution of this instruction causes the N2 line to go high which disables the memory and turns on the 4066 bilateral switches. With the bilateral switches on, the switches 51 to 58 are connected to the data bus. Because of the pull-up resistors on the data bus, when a switch is "off" the data line will be a logical high level. A switch being "on" shorts the data line to ground and puts it at a logical zero level. The connection of C and R to the CIEAR control line causes the 1 1 uP to reset when power is applied to the system. 24 Figure 12 CDP1802 Pin-Out CDP1802 CLOCK I 1 40 vaa CONTROL {, WATT 2 39 'YTKF CEEAR’ l 3 38 ORA—TR ‘ Q 4 37 DMTOTJT' STATE ' $01 5 36 TRTERRUFT CODES )_ SCO 6 35 ERR MITD' 7 34 TPA I TIMING r BUS 7 8 33 TPB ; PULSES BUS 5 9 32 MA7 BUS 5 10 31 MA6 DATA laus 4 11 30 MA5 BUS I BUS 3 12 29 MA4 MEMORY BUS 2 13 28 MA3 ADDRESS BUS 1 14 27 MA2 \BUS 0 15 26 MAI Vcc 16 25 MAO J ”0 N2 17 24 E_F_1_ L COMMANDS N1 18 23 i .552 I/O N0 19 22 ; EF3 FLAGS V55 20 21 j EF4 ) 25 Ain Bin Cin Din Control Contro Ain Bin Cin Din Figure 13 -— MicroproceSsor Circuit Diagram 26 3.2.2 Clock The block diagram (Figure 14) shows that the clock basically con- sists of a frequency divider, six counters, a multiplexer, and a display. Two pairs of counters are used to count-by-sixty fbr the seconds and minutes. The other pair count-by-twenty-four for the hours. Each pair of counters outputs its count onto eight lines in 800 format, four lines for the binary coded "units" digit and four lines for the binary coded "tens" digit. The twenty-four lines, four lines for each of the six digits, from the counters are time multiplexed down to four data lines and three control lines. These seven lines go to the display where the BCD information on the four data lines is converted to seven- segment code which is needed to drive the six multiplexed LED digits. TPB is a timing pulse output by the uP. The frequency of TPB is 262.144 KHz (218 Hz) which is 1/8 the crystal oscillator frequency. TPB is divided down by a 18 stage binary ripple counter to produce the 1 Hz pulse train that clocks the counter and interrupts the uP. The frequency divider circuit (Figure 15) is composed of two 4020's and a 4047. The 4020's are 14 stage binary ripple counters which are connected to produce a 18 stage counter. A pulse from the N0 output of the DP will reset the counter to zero. The 4047 is a monostable/astable multivibrator which is programmed (hard wired) to perform as a one-shot with an output pulse width of 250 microseconds. The one-shot is trig- gered by the trailing edge of the 18th stage output of the counter. The 0 output Of the one-shot clocks the seconds counter and the 0 output goes to the INTERRURT input on the uP. The 4th, 5th, and 6th stage outputs from the ripple counter are used as the control signals by the multiplexer. 27 .PnDKKMFZHuA- Ampampo Louoooo om+ acoEmmm u o» com p. m.\H. e mempa . -wupsz Emcumwo Huon xuoHu -- 3H aramHE 111111 .ITH mah.. t’ 92.. mHN Ha LauH>Ha n.o \\ ¢\ meme mgmyczou meso: \ m H: c N u. 3 ‘ 3.85 852; .L\ HV\ 22. mcmucaou mmpacwz \xx GHch .. H e Hammm .2: H.:HL- z 3.88 2.52sz \\ ¢\ mag. mcmpczou mucoomm ex much e x. . .- xooHQ mucoomm now $2830 oz 28 Emcmmwo szocwu cmuw>mo zocozcmcu u- mH ocamwu uaH..hu H , 3.2 m EEEEH. R HNH um I oH onhu O'D' n¢o¢ croowm >m+ mmcwH Hocucou cmxmpawpraz 49 HH omoe oH LO'U' 0‘ m‘ <‘ «Ho;|||1 drIIILTo oz A. u ofi mm» omoe x 29 The three 4518's in the clock circuit (Figure 16) are dual decade counters. 04A is connected to Enable B for each of the 4518's so the B counter will increment every time the A counter cycles from 9 to 0. The ANDing of 028 and 03B resets both the A and B counters of the seconds and minutes 4518's and clocks the following 4518 to produce the count by sixty function. The ANDing of 038 and 02B resets both the A and B counters of the hours 4518 to produce the count by twenty-four function. A pulse on the N0 line from the DP will first reset the seconds counters then on the trailing edge increments the seconds A counter to one. The NO line and 53B are ANDed to clock the minutes A t“ and 59th sec- counter when the seconds set pulse occurs between the 40 0nd. Pulses on the 0 line from the uP will also clock the minutes. A pulse on the uP's N1 line will reset both the hours and the minutes. Four 4051 8 to 1 multiplexers compose the multiplexer circuit (Figure 17). Only six of the eight lines are used on each of the 4051's. The three control lines come from the frequency divider cir- cuit. The BCD information on the four lines from the multiplexers is converted to seven segment code by the 4511 in the display circuit (Figure 18). The outputs of the 4511 go through current limiting re- sistors then on to segment inputs of the multiplexed common-cathode LED display. The 4028 BCD to decimal decoder is used to decode the three control lines. The outputs of the 4028 sequentially turn the transistors on and off and hence the LED digits. 30 51A 52A 53A 54A 518 528 S38 S48 M1A M2A M3A M4A M18 M28 M38 M48 H1A H2A H3A H4A H18 H28 H38 H48 Figure 16 -- Clock Circuit Diagram SIA SlB M1A MlB HlA H18 52A 528 MZA M28 H2A H28 S3A S38 M3A M38 H3A H38 54A 548 M4A M48 H4A H48 31 Figure 17 -- Multiplexer Circuit Diagram 32 Saguaro uwaocwu xmpamwo I- mH oczmwu w. i m NH 39m; G m “mmmzm H 3H < S ( Start M I Reset Hours, inutes, & Seconds 1 KHz tone oresent Yes Increment Tone Count 1 (TCl) Is KHz ton: No -resent ? _:l__ Increment Second Count LSC) No Increment Tone Count 2 (TC2) Yes No Yes Is C2 >25mS ? Yes 0 Figure 19 -- Seconds Set Routine O Set Seconds ' I Wait for Interrupt . 35 seconds after entering the loop the DP will set the seconds of the clock to one immediately after the next 100 Hz tone is detected. If the above conditions are not met the DP goes back and waits for the next 1 KHz tone to occur. After setting the seconds the DP idles, waiting for an interrupt. 4.3 Interrupt Routine The interrupt routine measures the length of the 100 Hz tone bursts, thus determining if they are coded zeros, ones or markers and stores this information in RAM for future use by the coder routine. The interrupt pulses from the divider circuit, which was synchronized to WWV in the seconds set routine, occurs at the start of each second. Every time an interrupt pulse occurs when the DP is waiting for an interrupt the interrupt routine is executed. The logic flow of the interrupt routine is illustrated in Figures 21 through 23. The three pieces of information used to ascertain the pulse type are determined by the three timing loops. These three pieces of information are: how long the 100 Hz tone was present during the intervals 0.0 to 0.2 seconds (ZC), 0.2 to 0.5 seconds (0C), and 0.5 to 0.8 seconds (MC). Table 2 illustrates how the pulse type is determined by the three variables. Once the pulse type is ascertained the remainder of the routine is devoted to decoding the time information. The data contained in the first three frames of the time code are stored in the three words recordl, record2 , and record 3 as shown in Figure 20. The fifth pulse of the frame, which is always transmitted as a coded zero, is used as an error checking, control element. If the fifth pulse is not a coded 36 Table 2 -- Pulse Type Decoding Method 0.0 s< ZC575 ms , 0.0 s-<.0C:5'0.3 s 0.0 5‘: MC:5C0.3 5 error 75 ms< ZCS 0.2 S 9 0.0 5" 0C:S§0.1 S 0.0 s< MC$0.15 ZERO 75 ms< 205 0.2 S a 0.1 s< 0C5 0.3 s 0.0 S‘=IM3=5(L1.S ONE 75 ms< ZCS 0.2 5 a 0.1 5‘: OCSS 0.3 s 0.1 5‘: MC:E 0.3 S MARKER 75 ms<¢ ZC1‘s 0.2 S s 0.0 s< OCS 0.1 S 0.1 s‘: MC:E 0.3 5 error Figure 20 Bit-Packing of Record RECORD l 9 8 7 6 5 4 .14.”.th No. of pulse in frame No. of bit in 2 1 word 37 ( Interrupt) Increment Zero Counter (20) Increment Second Counter (SC) Increment One Control (OC) Increment Second CoUnter (SC) Figure 21 -- Interrupt Routine 38 Increment Marker ‘ Counter (MC) Increment Seconds Counter (SC) No Is Tone Presen Yes Yes No Is 5th Pulse Yes 'nFra - ? No Is this a marker 7 NO Shift (Record) Right One Bit Yes A» Figure 22 -- Interrupt Routine (Continued) 39 Is MC > . lsec Yes D ? No Add 100000002 to (Record) '1‘ Wait for Interrupt Figure 23 -- Interrupt Routine (Continued) 4O zero the uP goes back to the seconds set routine and waits for the start of the next minute. Because all the pertinent information is obtained in the first thirty seconds of the minute when the third marker is encountered the MP ignores the rest of the time code and executes the coder routine. 4.4 Coder Routine The coder routine sets the hours and minutes with the time infor- mation obtained by the interrupt routine. Figure 24 illustrates the logic flow Of the coder routine. The BCO time information in record2 and record3 is converted to straight binary and checked to see if it makes sense. The time is corrected for the difference in time zone and finally the clock is set with this information. 41 Convert (Record2) from BCD to Binary D NO Convert (Record3) from BCD to Binary Input Time Zone Number (TZN) 1 (Record3) = (Record3)-TZN I . N = 60x Reset (Record3) Hours and + (Record2) Minutes Figure 24 -- Coder Routine Set Q3 Reset Q N Times CHAPTER V CONCLUSIONS The purpose of this thesis was the design and construction of an inexpensive, self-contained digital clock that would automatically set itself to the correct time using the WWV transmissions. This objective was attained. The clock was constructed and tested by the author. The clock has one major problem, it will set the hours and minutes only in the hours between sunset and sunrise. There are two reasons for this problem. Firstly, and most importantly, the receiver is not very sensitive. Dur- ing the testing of the receiver it was found that one of the transistors in the prepackaged IF module was bad and had to be replaced. There was no cross-reference for the original transistor, so the replacement tran- sistor may not be a very close match and could reduce the gain and sel- ectivity of the IF module. An improvement in the receiver performance may result if the IF module is replaced by a new one. Secondly, the MUF (maximum usable frequency) may not be as high as 10 MHz during the day when this unit was tested (April 1979). Another section Of the clock that could use improvement is the tone decoders. They are too sensitive to variations in the input signal volt- age. A receiver with a good AGC (automatic gain control) circuit could remedy this problem. Perhaps a better solution to this problem would be to replace the filters and tone decoders by an analog microprocessor. The analog microprocessor could digitize the analog signal from the 42 ’43 receiver, perfbrm some digital bandpass filtering, and output digital signals indicating if either the 1 KHz or 100 Hz tones are present. At night, while the clock would reset the seconds almost every minute, the hours and minutes would only set on the average of once every 15 to 20 minutes. This average was improved to once every 5 to 10 minutes when a Hewlett Packard amplifier with a gain of 26 db was in- serted between the antenna and the receiver. About once every 20 times the clock set the hours and minutes it would set them to the wrong time. During the day (if the clock had set the previous night) the crystal oscillator kept the clock accurate to the second. While the prototype of the clock cost about $150 in parts, a number of design changes could easily put the cost below $100. The whole clock section could be replaced by a single clock integrated circuit. The E-PROM, which is the most expensive IC in the device, could be replaced by a much less expensive mask-programmed ROM. It is the author's belief that a unit similar to this one could be manufactured and sold at the price of a moderately price clock radio. APPENDIX ASSEMBLY LANGUAGE PROGRAM LISTING FL LOC 0000 F 0002 0004 F 0005 0007 0008 0009 F 000‘ 000C F 0000 000F 0010 0012 0013 0014 0015' 0016 0017 0018 0019 0018 001C 001E 001F 0021 0022 F 0023 0025 F 0026 0028 0029 002A 0028 002E 0030 0032 0034 0036 0038 0039 0038 0030 003F 0040 0041 0042 0044 F 0045 0047 0048 0049 0048 004C 0040 004F 0050 0051 0053 0054 0055 0056 COSMAC CODE 7100 F800 91 F800 A1 63 C4 F900 52 F800 A2 LNNO (aooqo- 11.0410" 44 SOURCE LINE START: ONEK: LOOPI: 0K1: 0K2: 0K3: 0K4: RESET: LOOP2: CODER: CORI: 0150 L01 PHI L01 pLO OUT \OP L01 0“! L01 PLO L01 STR PHI pL0 PHI PLO PHI pLO L01 PLO L01 PLO 8N1 INC INC BN2 INC 8R GHI GHI GHI $01 82 CHI $01 52 81 BR GHI SDI BL BN2 SEX OUT NOP RET. 10L L01 PLO LDXA PNZ GLO PLO L01 AND PLO L01 AND SHR STR GLO 1'50. A.1(INT) RI A.0(1NT) R1 3 A.1(REC) R2 A.0(REC) R5 yoggo R7 X'03' R8 LCOPI R4 R3 X'OO' A.0(REC) R2 ..DISABLE INTERRUPTS. ..LOAD ADDRESS OF ..INTERRUPT ROUTINE. ..RCSE' HROHINO‘ND SEC. ..LOAD ADDRESS OF ..OATA RECORD INTO ..THE X REGISTER. ooCLERR SECOND COUNT. ooCLEAR TONE RECEIVED ooCOUNIo o.CLEAR 100 HZ RECEIVED OOCOUNTO ooLOAO BIT COUNTER. ..LOAO MARKER COUNTER. ..HAIT FOR 1 KHZ TONE. ..CHECK FOR MINIMUM ..TONE RECEIVED COUNT. ..CHECK TO SEE IF A ..SECONO HAS GONE BY. ..NO TONE RECEIVED. ..UAIT FOR 100HZ TONE. ..RESET SECONDS. ..ENABLE INTERRUPTS. ..HAIT FOR INTERRUPT. ..CHECK FOR ZERO FIRST ..RECORO. ..GET LOWER 4 BITS OF ..RECORD. ..GET UPPER 4 BITS OF ..RECORD. 0057 0058 0059 005A 0059 005C 0050 005E OOSF 0060 0061 0062 0064 0066 0067 0068 006A 006C 0060 006F 0071 0072 0073 0074 0075 0077 0079 007A 007C 007E 007F 0080 0081 0082 0083 0085 0086 3087 0089 008A 008C 0080 008E 008F 0091 0093 0094 0096 0097 0098 009A 0098 0090 009E 009F 00A0 00A1 00A2 00A3 00A4 00A5 45 ADD PLO LOX SHP SHR SHR STR GLO ADC PLO SDI 5L IR! GLO GLO 83E GLO L01 L01 pHI SEP LDI PLO L01 0H1 PLO PHI PLO PHI PLO PHI DL0 DEC RA R2 RA RA sq ONEK ..IF MINUTES > 59 TRY ..AGAIu. 92 A.0(REC)92 CDRI RA 23 ONLK ..IF HOURS > 23 Go HACK. 2 ..RESET HRS AND MINE. 4 ..SET TIME ZONE. CDR4 A.O(INT01 R0 A.1(IN10) R0 R0 A.0(INT) R3 ..CLEAR SECOND COUNT. R4 ..CLEAR ZERO COUNT. R5 ..CLEAR ONE COUNT. P6 ..CLEAR MARKER COUNT. R7 ..DECREMENT BIT COUNTER. 00A6 00A7 00A8 00A9 00A8 00AC 00AE 0080 0082 0084 0085 0086 0087 0089 008A 008C 006E 00C0 00C2 00C3 00C4 00FE 0100 0104 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 INTI: INT2: INT3: INT4: INT5: INT6: INT7: INTR: INTq: INTA: END: 46 INC INC GLO SDI GMT 9381 HZ 82 INC INC GLO SDI CHI $081 52 SEX ..INCREMENT ZERO COUNT. ..INCREMENT SECOND COUNT ..BRMNCH IF SC 3 .2 SEC. ..BRANCH IF 100 HZ. ..SIGNAL NOT PRESENT. ..INCREMENT ONE COUNT. ..INCREMENT SECOND COUNT ..BRANCH IF SC 3 .5 SEC- ..BRRNCH IF IOO HZ. ..SIGNAL NOT PRESENT. ..INCRENENT NRRKER COUNT ..INCREMENT SECOND COUNT ..BRANCH IF SC = .8 SEC. ..BRANCH IF 100 HZ. ..SIGNAL NOT PRESENT. ..DO NOT SHIFT IF BIT 5. ..SHIFT RECORD RIGHT ..ONE BIT. ..CHECK FOR MINIMUM ZERO ..CDUNT. ..CHECK FOR MINIMUM ONE ..COUNT. ..CHECK FOR "INIHUH ..HARKER COUNT. ..START OVER IF BIT 5 ..IS NOT ZERO. ..CHECK FOR MINIMUM ..MARKER COUNT. ..ADD ONE TO RECORD. ..8RANCH IF LAST MARKER ..START A NEH RECORD. ..LOAD 811 COUNTER. 47 0105 7000 135 RET. xooco ..ENAbLE INTERRUPTS. 0107 00 186 IDL ..aAIT FOR INTERRUPT. oaoc 197 ORG x'oaoo' 0.00 CD 188 REC: Dc xvcov 2401 189 5‘0 02:44:39 05/08/79 SL86101 1°C LINES PRINT. 6 PAGES PRINT. COST AT RG3 I REFERENCES REFERENCES Reference for Radio Engineers, 6th edition, Howard W. Sams & Co., Inc.: Indianapolis, Indiana, 1975, pp. 1.27-1.34. Datametrics, "WWVB Time Synchronizer," Bulletin SP-465, Pamphlet published by manufacturer. Signetics, Digital, Linear and M05 Applications, Signetics Corp.: Sunnyvale, California, 1974, pp. 6.1-6.49. ' 73 Magazine Staff, "Build a Useful HF Receiver," 73 Magazine, December 1977. Gobind Daryanani, Principles of Active Network Synthesis and Design, Wyley: New York, New YorR, 1976, pp. 269-276. RCA, User Manual for the CDP1802 COSMAC Micrgprocessor, MPM-201, RCA Solid State Division: Somerville, New Jersey, 1976. RCA, Timesharing Manual for the RCA CDP1802 COSMAC Microprocessor, MPM-202, RCA Solid State Division: Somerville, New Jersey, 1976. 48 "IIIIIIIIIIIIATIIES