NUMERICAL ANALYSIS OF MAXIMUM MICROWAVE POWER FROM A TUNNEL-DIODE OSCILLATOR Thesis for the Degree of Ph. D.‘ MICHIGAN STATE UNIVERSITY CHANDRAKANT BHAILALBHAI PATEL 1969 Vise-m 54.” . .- , up: 3-4:” antral.” :5; III "IIIII“IIIIIIIIIII L I “‘ V;‘\.l! , L 'I USA;VCISit 1 1- ) r j _ This is to certify that the thesis entitled NUMERICAL ANALYSIS OF MAXIMUM MICROWAVE POWER FROM A TUNNEL-DIODE OSCILLATOR presented by Chand rakant B . Patel has been accepted towards fulfillment of the requirements for Ph D degree in F- E y Date May 15. 1969 ajor professor 0-169 amomc ay IIOAG & SIIIIS' l : BOOK BRIBERY INC; LIBRARY BINDERS M. I ABSTRACT NUMERICAL ANALYSIS OF MAXIMUM MICROWAVE POWER FROM A TUNNEL-DIODE OSCILLATOR BY Chandrakant B. Patel The available literature on negative-resistance oscillators contains abundant information on small-signal analysis of tunnel-diode oscillators. Little consideration, however, has been given to large-signal analysis. Those analyses which are available are based on 1. low-frequency circuit operation; and 2. assumption of a single-frequency sinusoidal voltage at the tunnel diode terminals. In this thesis, the large-signal operation of a tunnel—diode oscillator circuit is examined with the ob- ject of delivering maximum fundamental power to the load. The exact analysis of the circuit operation results in a highly nonlinear, third-order and second-degree differen- tial equation. The circuit can also be described by means of a set of first-order, nonlinear differential equations-- its mathematical model.* Using a digital computer, this set of equations is numerically integrated in the time- domain using a fourth-order Runge-Kutta scheme. The Chandrakant B. Patel time-domain solution retains all significant harmonics, and frequency-domain analysis can then be used to evaluate the harmonic content. This method of solution can be easily extended to study the effects of voltage-dependent elements such as the tunnel-diode junction capacitance. The set of equations describing the tunnel-diode oscillator operation, with the circuit designed for the dc: operating point in the negative—conductance region, is numerically integrated until the digital computer cyclic solution corresponds to the steady-state operation of the circuit as determined when the harmonic components of two consecutive periods of the diode voltage are identi- cal within specified limits. The fundamental power de- livered to the load is next evaluated. This procedure, as outlined, is repeated for a number of different bias values and a number of different load resistances. These results indicate an Optimum bias and an optimum load re- sistance for maximum fundamental power. The optimum bias is closer to the diode valley point than to the peak point; the flatter the diode valley characteristic, the closer will be the optimum bias to the valley point. The ratios, (V V - Vopt are 0.382 and 0.345. The actual fundamental frequency of )/(VV - VP), for the two diodes analyzed here operation obtained from the time-domain analysis of the circuit is slightly lower than the frequency calculated from small-signal analysis. Chandrakant B. Patel Circuit Operation corresponding to optimum load resistance cannot be obtained by small-signal build-up from the bias point. Rather, this limit-cycle must be obtained by a large-signal perturbation, as for instance by external triggering. The power delivered to the load is reduced when the operating frequency is increased. Analysis of circuit operation with a voltage-dependent junction capacitance indicates somewhat higher maximum power delivered to the load and slightly lower Operating frequency than with the same circuit and a constant junction capacitance. Two specific configurations of load circuit were used for most of the computer analysis work. Of greater interest would be the synthesis of an optimum circuit configuration for obtaining maximum fundamental power from a specific diode. A few simple computations were made in connection with this synthesis problem. The re- sults of these simple calculations are consistent with the analytic results, but are not of sufficient generality to produce a fully-synthesized circuit. NUMERICAL ANALYSIS OF MAXIMUM MICROWAVE POWER FROM A TUNNEL-DIODE OSCILLATOR BY Chandrakant Bhailalbhai Patel A THESIS Submitted to Michigan State University in partial fulfillment of the requirements for the degree of DOCTOR OF PHILOSOPHY Department of Electrical Engineering and System Science 1969 ACKNOWLEDGMENT The author wishes to express, first of all, his deep gratitude to Dr. L. J. Giacoletto for suggesting the problem area and providing excellent direction to the research reported in this thesis. The author is also thankful to Dr. H. E. Koenig for his interest in the author's doctoral studies in the capacity of chair— man of the department. Sincere thanks are due to Dr. John D. Ryder, Dr. Bong Ho and Dr. D. J. Montgomery for their guidance and willing participation in the author's guidance committee. Sincere thanks are also due to Dr. Y. Tokad for his useful suggestions. I would also like to thank my wife, Nancy, for her help in typing and correcting notes. ii TABLE OF CONTENTS Chapter Page 1 INTRODUCTION 0 O O O O O O O O O O O O O O O l 1.1 Background . . . . . . . . . . . . 1 1. 2 Survey of the Literature and the the Problem Area . . . . . . . . . . 2 1.3 Thesis Summary . . . . . . . . . . . . 4 2 THE TUNNEL DIODE AND ITS EQUIVALENT CIRCUIT O O O O O O O O O O O O O O O O O 6 2.1 Tunnellhs. . . . . . . . . . . . . . . . 6 2.2 Schroedinger's Wave Equation . . . . . 6 2.3 Qualitative Explanation of the Tunnel- Diode Action . . . . . . . . 11 2.4 Direct and Indirect Tunneling . . . . 15 2.5 Approximating the V-I Characteristic . 15 2.6 Equivalent Circuit . . . . . . . . . . 21 3 THE TUNNEL-DIODE OSCILLATOR . . . . . . . . 24 3.1 Introduction . . . . . . . . . . . . . 24 3.2 Stability Criterion for the Tunnel- Diode Circuits . . . . . . . . . . . 24 3.3 Operating Frequency and Circuit . . . . 31 3.4 Oscillator Circuit . . . . . . . . . . 35 4 THE TUNNEL-DIODE OSCILLATOR CIRCUIT: ITS ANALYSIS AND SOLUTION . . . . . . . 45 4.1 Introduction . . . . . . . . . . . . . 45 4.2 Solution by Coerver and Sterzer . . . . 46 4.3 Large- Signal Tunnel-Diode Oscillator Circuit . . . . . . . . . . . . 49 4.4 System-Model of the Oscillator Circuit . . . . . . . . . . . . . 54 4.5 Numerical Solution of the System- Model . . . . . . . . . . . . . . . 61 4.6 Examples . . . . . . . . . . . . . . . 65 4.7 Effects of Varying Circuit Parameters . . . . . . . . . . . . . 77 iii Chapter 5 APPENDIX APPENDIX APPENDIX APPENDIX HYBRID APPROACH FOR MAXIMIZING LOAD POWER O O O O O O O O O O O O O O O O O .1 Introduction . . . . . . . . . . . . 2 Criterion for the Maximum Fundamental Power from the Intrinsic Diode . . .3 Circuit Design for the Maximum POwer from the Intrinsic Diode . . . . . 5.4 Examples . . . . . . . . . . . . . . CONCLUSIONS O O O O O O O O O O O O O O O A Approximation to Tunnel-Diode Static Current-Voltage Characteristic Equation O O O O O O O O O O O O O B Stability of a Linear Active SyStem O O O O O O O O O O O O O O C Circuit Synthesis Based on Two-Frequency Admittance Specification . . . . . . . . . . D Logic Diagram of the Computer Program, GREAT . . . . . . . . . . iv Page 82 82 83 85 88 97 99 104 109 116 CHAPTER 1 INTRODUCTION 1.1 Background A negative-resistance device is of considerable interest as a signal—generating device. The tunnel diode, a two-terminal negative-resistance semiconductor device, Opened up entirely new fields for circuit and solid-state device engineers. The significant pr0perties of the tunnel diode were first observed by Leo Esaki while ex- perimenting on degenerately doped p-n junction. Esaki's results were first published in an historic paper [1] in early 1958. The tunnel diode differs in the basic physical mechanism of its operation from the common rectifying diode. Quantum-mechanical tunneling, from which the name "tunnel diode" is derived, is uniquely exploited in this active device to produce a negative resistance when it is prOperly biased. The immediate applications of the device were seen as amplification and generation of signals, possibly at millimeter-wave frequencies; as detector, mixer, fast computer memory, and logic element. As re- search continued and related technology advanced, the device was better understood and now has a fairly well established place in modern semiconductor technology. This device may find even greater usage as an element in integrated electronic circuits. An important use of the tunnel diode is as a negative-resistance element in an oscillator circuit to generate high—frequency power. 1.2 Survey of the Literature and the Problem Area The basic problem of this thesis is part of the problem of an exact analysis of a tunnel-diode oscillator circuit. This thesis will concentrate on 1. high-frequency operation, 2. design of a circuit to maximize the fundamental power delivered to the load, and 3. synthesis of a circuit for high-frequency operation. The highly nonlinear characteristic of the tunnel diode requires extensive use of a digital computer for a detailed analysis of circuit Operation. It is fitting at this stage to review briefly the literature in the area of negative-resistance oscillators. Van der Pol [22,28] first studied the nonlinear theory of electrical oscillations. Subsequently, two-terminal negative- resistance "black boxes" were devised using tetrodes, transistors, diodes and resistors [35,36,37]; various negative—resistance oscillators and amplifiers were designed [29,30,31,32]. The tunnel diode as a two-terminal negative— resistance element was analyzed by Kim and Brandli [4], Chow [5], G. Dermit [20] and others [2,7,14]. Their analysis considered 1. small-signal operation of the device, and 2. a simplified third-degree polynomial approximating the current-voltage (I-V) characteristic for the tunnel diode. I II IP """ . ‘ ”'. I I b a I l I 9max Lfl/// : ; I . . I I I I I I IV """"""""""""""" g E J_V VP Vv VFP Figure 1.1. Tunnel diode I-V characteristics (a) Actual (b) Third-degree polynomial approximation The circuit operating point was generally chosen as the point of maximum negative-conductance on the curve. K. Tarnay [6,7] and Coerver [8] considered better approximations (see Section 2.5) to the I-V characteristic. They analyzed low-frequency operation_(below self-resonant frequency, see Chapter 3) by assuming a pure sinusoidal signal. Gartner-Schuller's [17] computer results are like- wise for low-frequency operation. Sterzer [9] in his com- puter calculations used a highly exact approximation for I-V characteristic (tenth-degree polynomial) but he assumed a single-frequency operation. It should be noted that in all these publications the voltage dependency of the junc- tion capacitance is neglected, and the capacitance is assumed to be constant. The above survey of the literature reveals that large-signal analyses of the tunnel-diode oscillator cir- cuits for high-frequency Operation have not been very exact. Better solutions of the problem continue to be of great importance. The improved solutions should consider higher harmonic content of the signals and should include junction capacitance as a voltage-dependent element. It was through the realization of the overall significance of the problem that the author was motivated to carry out further research in the area of high-frequency power in tunnel-diode oscillators. 1.3 Thesis Summary The phenomenon of quantum-mechanical tunneling and the qualitative explanation of the tunnel diode action are covered in Chapter 2. There follows a development of the tunnel-diode equivalent circuit. This equivalent cir- cuit is applicable for analysis from dc through gigahertz frequencies. Also described are the various analytical methods for approximating the I-V characteristic of a tunnel diode. . The small-signal oscillator circuit, its design and its small-signal stability are considered in Chapter 3. Large-signal operation of the tunnel-diode oscillator circuit is analyzed in Chapter 4. Applicable equations are formulated, and their numerical solutions by a digital computer are studied in detail. Examples of maximum power delivered to a useful load are given for two types of tunnel diodes. Effects of voltage dependency of the junc- tion capacitance are examined and illustrated. A hybrid approach for optimizing the fundamental power generated by the intrinsic tunnel diode is given in Chapter 5. Circuit synthesis is considered to implement the hybrid—approach solutions. A summary of the overall work and conclusions is given in the final Chapter 6. CHAPTER 2 THE TUNNEL DIODE AND ITS EQUIVALENT CIRCUIT This chapter first describes the tunneling phenome- non to which the specific property of the device is attributed. Then the equivalent circuit of the device, depending on the tunneling property and other physical characteristics, is developed. 2.1 Tunneling Classical physics predicts that a particle of total energy, E, cannot penetrate a potential barrier greater than its own energy. The phenomenon known as quantum-mechanical tunneling predicts that a particle of total energy, E, can penetrate the potential barrier of a height greater than B and be found beyond the bar- rier.- The probability of finding the particle on the other side of the barrier decreases with the height and the width of the barrier. These results can be demon- strated by solving Schroedinger's wave equation in a simple, one-dimensional problem. 2.2 Schroedinger's Wave Equation The time-dependent, one-dimensional Schroedinger wave equation [10] for a particle is 6 2 2 - 1‘— —-2—3 “XI“ + V(x,t)‘Hx,t) = jh ——¢——3‘“’~‘- t) (2.1) 2m 3x at where T(x,t) = wave function defining motion of the parti- cle, V(x,t) = potential energy function, h = §%-where h = Planck's constant = 6.6252 x 10-34 joule-sec., m = mass of the particle, and j = /:I. The time-independent Schroedinger wave equation can be Obtained by separating time and position variables as V(x,t) = w(x) ¢(t) provided V(x,t) = V(x) only. Substituting these in (2.1) and separating vari- ables we get: 2 2 ° 1 j Ld tux). + V(xWx, = 41211122., (2.2) W(x) 2m dx ¢(t) dt Since the left-hand side is a function of x only and the right-hand side is a function of t only, and since x and t are independent variables, we must have 2 2 l —f‘—9——‘Lz‘i)-+vw 0) is applied, more electrons tunnel from the n-side into the empty states in the p-type material than in the reverse direction. This 12 E II E II , r—WV-fi é ; Ecp Ecn ;: Ef r-~-~:—----—: -------- i /’T* Ev I I p Ev I : : 'n : 5 n : I p (a) Lightly doped (b) Heavily doped Figure 2.2. Band structure of a p-n semiconductor junction EC: conduction-band edge energy : Valence-band edge energy E E; Fermi energy E II E + n Cp EC n ' EV ' P . + E i P Vn E Figure 2.3. Band structure of a p-n junction when tunnel- ing is almost zero. 13 asymmetry results in a steep rise in the forward current. This rise in forward current with forward bias continues until the empty states in the p-type semiconductor, at the same level as the filled states in the n-type semi- conductor, begin to decrease. An increase in forward bias (VB > V see Figure 2.4) at this stage results in a de- P’ crease in forward current. This decrease in forward cur- rent continues until finally there are no empty states in the p-type material Opposite the filled states in the n-type material at the same level. The tunneling current is zero, (VB > Vv). At this point the conduction-band edge is at the same level as the valence-band edge (Figure 2.3). Simultaneously the ordinary p-n junction injection current--mainly diffusion current-~is flowing, so the net current does not quite go to zero. The behavior of the tunnel diode for higher forward-bias voltages (VB > VV) is similar to that of an ordinary p-n junction. When a small reverse-bias voltage, (VB < 0), is applied,the number of empty states in the n-type semicon- ductor at the same energy level as the filled states in the p-type semiconductor is greatly increased. Also the reverse bias enhances the electron flow from the p-side to the n-side. As a result, the reverse current increases sharply with reverse bias. As deduced from the above ex- planation the current-voltage plot of a tunnel diode will be as shown in Figure 2.4. l4 ------__-------- 'U Figure 2.4. I-V plot of a tunnel diode OR: Increasing tunneling current due to small forward bias. Tunneling decreases but resultant tunnel- ing current still increases. Peak point Tunneling and tunneling—current component decreases to almost zero. Total current starts increasing due to ordinary diode injection current, OSF. Tunneling current due to reverse bias. 15 2.4 Direct and Indirect Tunneling The laws of conservation of energy and momentum apply throughout the process of tunneling. The change in momentum before and after tunneling involves some exchange of momentum with the crystal lattice. The case where electron momentum is equal before and after tunneling is called direct tunneling. The processes described in Sec- tiom62.2 and 2.3 are of direct tunneling. If the electron' momentum is different before and after tunneling, the pro- cess is called indirect tunneling. The probability of- indirect tunneling is much lower than that of direct tun- neling, owing to the added requirement of the conservation of momentum. Observing the energy-band-momentum diagram of germanium and silicon (Figure 2.5) we can see that direct tunneling is possible in the case of germanium only. For the silicon junction the peak tunneling current will be] very small, since here a momentum of‘hk'c in addition to energy is required for tunneling. Another semiconductor suitable for direct tunnel- ing is gallium arsenide. Therefore most of the tunnel diodes are of germanium or of gallium arsenide. 2.5 Approximating the I-V Characteristic The static current-voltage characteristic of a tunnel diode was indicated in Sections 2.3 and 2.4 to be as shown in Figure 2.6. An expression approximating 16 Ge Conduction band Z///’AH\\\\XVa1ence band k c (a) Si EI F (b) band Conduction V Figure 2.5. Energy band-momentum diagram (a) Germanium, (b) Silicon. IA P" . I I I I I I I IV _---% ............ VP Figure 2.6. Static current-voltage characteristic of a tunnel diode. IP: Peak current VP: Peak voltage vFP: I : V V : V Forward peak voltage Valley current Valley voltage 17 this current-voltage characteristic is required for any analysis or computing purposes. The I-V characteristic can be approximately through various methods: (a) Polynomial approximation 2 N . I(V) = + 31" + a2V + --- + anN 520 ajvJ (2.13) 3: a0 The coefficients aj, j = 0,1,2,---,N are evaluated in accordance with the desired polynomial fit. The least— square fit is most commonly used. The degree of poly- nomial, N, depends on the desired accuracy of the fit. For a more accurate fit in a given region the data associated with the region can be given additional weight [38]. (b) Considering g(V) = dI(V)/dV, and noticing the flat valley region, Narud and Meyer [13] suggested the fol- lowing approximation: g(V) = K(V-VP) (v-vV)3 (2.14) Equation (2.15) is obtained by integrating (2.14) by parts and using peak-point and valley-point voltage and current values. I(V) =fg(V)dV -I = IV P [5(V-VP)(V-V.V)4 ‘ (V-VV)5] + C (VPv-VV‘) (2.1s) 18 Figure 2.7. Tunnel-diode conductance vs. voltage Il(V) I2(V) V Figure 2.8, Tunnel~diode static characteristic: Ferendici and Ko's approximation. 19 From valley point (Iv, Vv),.the constant of integration, C = IV, is obtained. I(V) = O for V = 0 is obtained only for certain rat1os of IP/IV and VV/VP [13]. (c) Using the equation (2.15) for g(V) Scanlan [14] suggested evaluation using gmax' d (V) _ At gmax' 1%V_—‘- 0' and 99-m- = (v-vV)3 + 3(V—VV)2(V-VP) = o dV gives v _ VV + 3VP 4 . Hence substituting for V into (2.14): - - — 27 (VV-VP) (V -V )3K 9max 64 I V P ° Hence 3 256 (V-VP)(V-VV) 27 (VV-VP) and I(V) =fg(V)dV 4 3 2 4v —5(3v +v )V + 20V (V +V )V V P V P--V 256 g max I = 4 V 2 3 + K ° 540 (VV-VP) -10VV (3VP+VV)V + ZOVV VP ( .17) The constant of integration, KC can be evaluated from the choice of axes. 20 (d) K. Tarnay[12] suggested still another approxi- mation considering: (a) the field-emission current due to electrons passing from valence band to conduction band and (b) the current due to electrons tunneling from conduction band to valence band. His expression is as follows: I(V) = a(Vv-V)2tanh(qV/2kT) + gVV , (2.18) where - g V I a = I; V V , and gV = §!» . (VV-VP) tanh(qV?/2kT) V This expression gives a poor approximation to ex- perimental curves, especially in the negative-conductance region. (e) Two-term exponential approximation: Observation of tunneling current and direct-injec- tion diode current components, led A. Ferendici and W. H. KO [11] to suggest a simple two-term approximation Of the static current-voltage characteristic of a tunnel diode. Il(V) = Tunneling-current component (Figure 2.8). 12(V) = Ordinary diode injection current component. I(V) = I1(V) + 12(V) = AVe'aV + 3(ebV-1) . (2.19) This two-term fit generally gives 15% accuracy over the entire curve. The accuracy can be increased over 21 any desired region by selecting the pilot points from that region for evaluation of constants A, a, B and b. (see Appendix A.) 2.6 Equivalent Circuit The current-voltage characteristic of a tunnel diode junction is explained in Section 2.3. This current flows through a p-n junction which is essentially depleted of mobile carriers. Owing to the existing voltage across this depletion layer, there are flux lines and a related capacitance associated with the junction. Therefore the tunneling junction is represented by a varying conductance shunted by a varying capacitance. The junction capacitance, Cd(VD)' is a function of junction voltage, VD [15,16]. For a step junction, which is the case for the tunnel junction, the junction capacitance, Cd, is prOportional to (VD-Vc)-1/2. c «(V -v )"l/2 for v < V (2 20) d c D D V ' where Vb = junction voltage and VC = contact potential, (n with respect to p) H + 0.6 volts for Ge, and 22 + 1.1 volts for GaAs. The electrons traversing the tunnel junction travel through the semiconductor bulk material. The electron col- lisions with the crystal lattice give rise to a resistance rS termed 'spreading' or 'series resistance.’ The value of 22 T a (‘fi —£ V'D Cd (VD) 7‘ 1.2 gd (V ) Figure 2.9. Equivalent circuit for a tunneling junction. r L s s *———~——ANN-*—JMMM¥* ‘ .4 CdIVD) C74; \, Figure 2.10. Equivalent circuit of a tunnel diode. 23 this series resistance depends upon the doping level and the geometry of the diode. The physical length of the lead from the semiconductor to external terminals gives rise to a series inductance, LS, of the order of a few nanohenries. The series resistance, rs, and the series inductance, LS, are represented in series with the tunnel- junction. The resulting equivalent circuit Of the tunnel diode is as shown in Figure 2.10. The validity of this equivalent circuit was verified by Gartner and Schuller's [17] experiments. Computer calculations herein will use this equiva- The effect of considering DO Cd as a function of VD will also be examined. lent circuit with Cd(VD) = C CHAPTER 3 THE TUNNEL-DIODE OSCILLATOR 3.1 Introduction A tunnel diode can be used in negative-resistance amplifiers [18,19] and in negative-resistance oscillators [5,14]. It can also be used as a detector or as a mixer, in which,case the variation of negative resistance with the signal level is essential. In all these cases the diode must be biased in the negative—resistance region. A tunnel diode can be biased to produce three different potential conditions: (1) bistable, (2) monostable, and (3) astable. These are shown in Figure 3.1. In its negative-resistance region, a tunnel diode can be biased two ways, viz., bistable and astable. In bistable biasing the two stable points are a anc c. This type of biasing is used in switching type circuits [5]. The astable biasing is used in amplifiers, oscillators, etc. The tunnel diode used as an oscillator circuit ele- ment is considered here. 3.2 Stability Criterion for the Tunnel-Diode Circuits In a tunnel—diode oscillator circuit, the tunnel diode is biased in the negative conductance region. The 24 25 O Figure 3.1 Biasing a tunnel diode: (l) bistable, (2) monostable and (3) astable. Figure 3.2 Small—signal equivalent circuit of a tunnel diode. 26 circuit is designed to be unstable so small-signal oscilla- tions will start due to circuit noise or transient effect and grow. The circuit stability is in part determined by small-signal analysis. The small-signal equivalentscircuit for the tunnel diode is shown in Figure 3.2. Here —gD is the value of negative conductance at the dc bias point, VD. The loop impedance of the circuit of Figure 3.3 is Zc(s) + ZD(s), whereZD(s) is-the impedance of a two- terminal active device and Zc(s) is the passive network impedance. As shown in Appendix B, the circuit is stable if Zd(s) + ZD(s) = 0 has no solution in the closed right- half s-plane, viz., Re(s) > 0 [2]. The above definition of stability is derived from the small-signal, that is, linear analysis of the device. The follOwing example of a small-signal analysis of tunnel-diode oscillator circuit, Figure 3.4, gives a procedure to ob- tain (G, C) parameter values so that Zc(s) + ZD(s) = 0 has a root in the right-half s-plane. Consider the tunnel-diode equivalent circuit shunted with a parallel G-C circuit as shown in Figure 3.4. For this circuit _l__. G + Cs ’ Zc(s) (3.1a) 1 :7__-———' I g + CD8 ZD(s) = r8 + Lss + (3.1b) 27 Q ZC(S) ZD(S) A V Figure 3.3 Circuit showing connection of circuit with impedance, ZC(s) to the diode with impedance, Z (s). D G 7R; ““ _" 7T -9 = QJVD) R Figure 3.4 Small-signal equivalent circuit of the tunnel diode with a parallel G-C network. 28 Where -g is the negative conductance of the intrinsic tunnel diode at the dc bias point, V The loop impedance D. is (-g+CDs) + (rS+LSs)(G+Cs)(-g+CDs) + (G+Cs) Zc(s) + 20‘s) = IT (OTCs)(-gIE;§) ‘ (3.2) For stability [3], examine the characteristic equation, 3 2 Zc(s) + ZD(s) = 0 = as + bs + cs + d, (3.3) where a = CDCL > 0 , b = -gCLS + cD(rsc + GLS) , c = -g(rSC + GL5) + rsGCD + CD + C and d G - g — rSGg : to determimawhether all roots are in.the left-half plane, (LHP). If all the coefficients of the characteristic equation are positive then all the roots will be in LHP. Therefore, for d > 0 implies (G + r1 > g . (3.4) s This result constitutes the condition for do stability. Since Equation (3.3) has real coefficients, the complex roots must be a conjugate pair. The necessary condition, according to Routh's algorithm, for the complex rootstof(3.3) to be in LHP is (bc-da)<<0. Introducing the 29 values of the coefficients, bc - da = A1G2 + AZG + A3 = F(G,C) , (3.5) where _ 2 _ 2 Al - rsLsCD chLs ’ _ _ 2 2 2 2 2 A2 — gCDrSCLS + rs cD c + LSCD + g CLS , A = r C2C (l-gr ) + r CC2 + gCZL (gr -1) 3 s D s s D s s ' Consider first a pair (Go, Co) of circuit values such that the complex roots.are on the imaginary axis. Thus 3 = ijwo with mo as the desired operating frequency. Substituting 3 =jwo into (3.3) and using Re[ZC(3wo) + ZD(jwo)] = 0 , (3.6) and Im[ZC(jmo) + ZD(jwo)] = 0 , the following equations are obtained: 2 _ Go(rSCD - gLS) + Co(1 - grS - CDsto) - 0 , - (3.7) 2 = _ Go(1 - grs - CDLSwo) + Co(gLS - rSCD) - 0 . Next, the value of GO (and/or Co) are altered such that (3.3) has a complex conjugate root, so = 00 r jw o with co > 0. The correct direction of change to Go is de- 3F(G,C) —.—» I . If the derivative (some) termined by evaluating G 30 is positive, Go is increased,otherwise Go is decreased to get co > 0. dF(G,C) _ _ 2 2 2 2 2 T —. 2<:.L$cD(r$cD gLS) + LsCD + C(r 3CD +9 Ls .) - 2rSgLSCDC . (3 o 8) Thus in the small-signal analysis of the tunnel- diode oscillator (Figure 3.4), there must be a root, S0 = 00 + jwo, of the loop impedance, with Go > 0. If so, then over a period of a small-signal oscillation, the energy generated by the negative conductance of the tunnel diode is more than the energy dissipated by the lossy elements. Once the oscillations start and grow in amplitude, the small-signal conductance, -g, no longer applies because it it constant only over a very small region around the bias point. For large-signal oscillations the voltage-dependent diode conductance, gd = d i(vD)/d VD, must be used. In the large-signal Operation, the diode will operate part of the time in the region where the diode small-signal conductance is positive. Additional losses are produced. These addi- tional losses together with the nonlinear characteristic of the diode establish a steady-state operation. For steady—state operation, the average power generated by the diode is equal to the average power dissipated by the lossy elements of the circuit. 31 3.3 Operating Frequency and Circuit The type of circuit used depends in part on the operating frequency, £0. The terminal impedance of the tunnel diode shown in Figure 3.2 is r . ' gD . CD rS - 2 + (wC;§-+ jw L - 90 ID ZD(jw) .- d Re(ZD) + j Im(ZD). (a) Resistive cut-off frequency, fR, The resistive cut-off frequency, f = wR/Zfl is the R value of w for which Re(ZD) = 0. Equating Re(ZD) = 0 gives gD + (wRCD) RI _ 1 D _ 2 “R _ E- E' 99 . (3.10b) n s Re[ZD(wo)] < 0 . (3.10c) For mo > OR, the terminal resistance is no longer negative, and the tunnel diode cannot be used as an oscillator for frequencies greater than the resistive cut-Off frequency. 32 (b) Self-resonant frequency, f sO The self-resonant angular frequency, ms = 2rfs, is the value of w for which Im(ZD) = 0. m C Im(Z ) = w L — S D = o . (3.11a) D S s g + (m C )2 D S D Solving for ms, C l ‘/ D 2 S CD Ls D If mo < ms, Im[ZD(wO)] < 0, (3.11c) and if we > ms, Im[ZD(wO)] > 0. (3.11d) With present technology, tunnel diodes with resis- tive cut-off frequencies up to 30 GHz can be produced. Generally the resistive cut-off frequency is found to be greater than the self-resonant frequency, £8. The tunnel-diode small-signal equivalent circuit with a load circuit of terminal impedance, ZL(N), forming an oscillator, is shown in Figure 3.5. Here -gD is the incremental conductance of the tunnel diode at the bias point; rs, Ls and C are diode parameters explained in D Section 2.6. 33 With the small-signal operating frequency, F0, the fol- lowing conditions must be satisfied for a steady—state solution: [ZL(“b)+ ZD(ub)]I = 0, (3.12a) or Re[ZL(ub) + ZD(ub)] - 0 , (3j.12b) and Im[ZL(wo)+ ZD(q§] - O . (3.12c) From Equations (3.10c) and (3.11d) for fo < fs, InKZD(wo)) <0, a capacitive reactance, and for fo > £3, InKZD(wo)) >0, an inductive reactance. For the circuit operating as an oscillator and for fo < fS, Im(ZL(wo)) > 0, an inductive load, and for fo > fS’ Im(ZL(wO)) < 0, a capacitive load. Thus, selection of an operating frequency dictates the nature of the load-circuit necessary for oscillation. Here the aim is to concentrate on high-frequency operation, fo > £8; only capacitive-load circuits of the type shown in Figures 3.6b and 3.6c will be used. The oscillator circuit with the operating frequency fo < fs, load circuit inductive, was analyzed on a small-signal basis by Chow [5]. The large-signal analysis with certain assumptions was carried out by Kim and Brandli [4], Coerver [8], and others [7,9,14,17]. 34 LOAD CIRCUIT Figure 3.5 Tunnel—diode oscillator circuit. I b o < m o >l I < w (a w I trdhtr—RMMLnr o \I Jlon a) o I (a) fo < fS (b) fo > fs (c) f Figure 3.6 Load circuits for the tunnel-diode oscillator (a) inductive, (b) capacitive, (c) inductive or capacitive load depending on f0. VBB is the dc bias voltage. 35 3.4 Oscillator Circuit The tunnel-diode oscillator circuit with an operat- ing frequency, f0, which is greater than the self—resonant frequency, f but less than the resistive cut-off frequency, 8! f < fo < fR.is shown in Figure 3.7. fR' S In the circuit of Figure 3.7b,-the load circuit l I must be capacitive, viz., eroCC. - (l/21rfoLc ) > 0. Param- l I eters L.C and Cc can be calculated from the values of CC I and f considering C = kC , k > 1. o C c (a) Selection of an Operating Bias-point, VD. The tunnel diode as an oscillator circuit element must be biased in the negative-conductance region. The bias point, V , must lie between peak point, V , and val- P ley point, VV, i.e.,VP < VD < VV. It should be noticed from the V-I characteristic of the tunnel diodes that the D valley region is flat compared to the peak region. This phenomenon is more pronounced in gallium-arsenide tunnel diodes than in germanium tunnel diodes (Figure 3.8). This indicates that the region with the higher negative resis- tance is flatter near the valley region than near the peak region. The power generated by the diode depends on the voltage swing about the bias point and the incremental negative resistance of the tunnel diode. Since the higher negative-resistance region is flatter near the valley point, the bias point for maximum fundamental power should 36 r L s s e : MI) I ‘ ' LC V. ;:h\ C ‘4—' D GC V Cd(VD) 2/[\ gd(VD) BB Il'r . ~ - (a) rs LS . I Lo . VD ____C G ____ /7~\ c c Cd(vD)/1h\ ngVD) —‘-—l— VBB - . + . - (b) Figure 3.7 Tunnel-diode oscillator circuits with an operating frequency fo > fS. 37 Figure 3.8 Current-voltage characteristics of (1) Germanium tunnel diode, and (2) Gallium-Arsenide tunnel diode. r L 1 *"1 1D (VD) - wi—o—JIIITIRIL * I + 4 G __ v. E c /I\ CC CD 75' D "I'*—Y(w) VBB I 1 I4}; I I . : l «va Figure 3.9 Tunnel-diode oscillator circuit. gd(vD) 38 be closer to the valley p01nt, 1.e., (VV - VD) < (VD - VP). Sterzer [9] has shown in his computer calculations using vD(t) = V + Vo sin(2nt/T) that the optimum bias voltage, D V for the maximum power generation is very close to the DI valley point. His results also show that the flatter the valley region, the closer will be the Operating bias point, V to the valley point, V . Similar results will be de- D' V rived in Chapter 5. (b) Load Parameters: Gc’ Cc and VBB' The discussion of the stability of the tunnel-diode circuits in Section 3.2 pointed out that small-signal in- stability is essential for an oscillator circuit. The circuit parameters, Gc and Cc' are designed accordingly. The bias supply, V , can be determined from the Operating BB bias point, V and from rS and Gc' D! V =V 1 c A tunnel-diode oscillator circuit is shown in Figure 3.9. Here g(VD) and CD are the negative conductance and the junction capacitance respectively, at the quies- cent point, Vb. Initially CD is assumed constant. To the I left of terminals l-l , the admittance is Y(w), a function of frequency. Node admittance for the circuit is YNode(w) = Y(w) + g(VD) . 39 The conditions for an oscillator with an Operating fre- quency, f0, are (see Appendix B, equations (B.11a) and (B.11b)): (a) for the operating frequency of the oscillator to be f0, Im[YNode(wo)] = Im[Y(wO)] = 0 , (3.13a) and (b) for the oscillationtx>start (due to the circuit noise) and grow, Re[Y(wo)] < LgJVD)I . (3.13b) Let _ G R ‘ rs + 2 C .12 , (3.14a) G + (to C ) c o c wocc o o s 2 ’ G0 + (woCC) then, R wox o R2+ (m X)2 o D R2 + (m X)2 o o Im[Y(wo)] = 0, implies wox m C - ' = 0 . (3.16) 40 Solving, This implies wox must be positive. From (3.14b), = w L when C = 0. Let m X = kw L , k < 1, o s c o o s kw L R =J——9—§ - kzsz2 . m C o s o D For R to be real, kL s 2 2 2 . . . l —E—- k woLS > 0. Th1s implies k ('77_—_" D m L C o s D Hence, . 1 k s min 1, -§————-= kmax . wOLsCD Rewriting Equations (3.14a) and (3.14b) as: GC G + (m C ) C CO and CC L-X=X= I 2’ 2 GC + (moCc) and solving them simultaneously for GC and CC: R G = u + (wox C I R2 )2 (3.17a) (3.17b) (3.18) (3.19b) (3.19b) (3.20a) 41 and c = )LA . (3.20b) c R2 + (“0X12 Thus for a different value of k a different set of values (GC,CC) for a given operating frequency, fo > fS is obtained. The condition (3.13b) for growing oscillations can be used to give a lower limit for the parameter, k._ Using Remw )1 = R < -9 (v ) a g . (3.21) 0 R2 + (mox)2 d D D substituting for R, from (3.17a), writing X = kLS, and simplifying, gives: c D 2 2 2 kLS < (99 + woCD) . (3.22a) or c /L k > D S = k . . (3.22b) 2 2 2 m1n 9D + woLs Thus, the bounds for parameter k are: CD/LS . l km1n = 2 ”2 2< k < m1n 1’ -2_-__' = kmax ' 9D + “0L8 woLSCD (3.23) The set of values (Gcm'ccm) evaluated for k = kmin means that Re[Y(wo)] Gc ICC = gD. According to small-signal 42 analysis, this circuit is on the verge of instability and the oscillations may not grow or will grow very slowly. In computer calculations (see Chapter 4) exactly the same result is obtained. However, it should be kept in mind that the small-signal analysis is only a means to obtain for an oscilla- suitable load parameters, G , CC and V 33' tor circuit. The circuit with Gc' Cc values evaluated C for k < k . m in means it is a small-signal stable circuit. Large-signal analysis of the same circuit may nevertheless show instability as corresponding to oscillations as will be shown in Chapter 4. As mentioned in Section 3.2, the circuit must be do stable. That is, the diode biased in the negative-re- sistance region should have a unique dc Operating point on its I-V characteristic, as indicated by Equation (3.24) and shown in Figure 3.10. (G + J.) > |- | (3 24) c rs gD ° ' Thus the algorithm for designing a tunnel-diode small-signal oscillator circuit is as follows: (a) Obtain tunnel-diode parameters CD, rs and Ls from the specification sheet of the diode. (b) Obtain a static I-V characteristic for the tunnel diode. (c) Calculate the static I-V characteristic for the intrinsic tunnel-diode junction from step (b). Next evaluate parameters A, a, B, 43 do load line SIOpe - (GC+ l/rs) ac load line (small signal Figure 3.10. I-V characteristic of the intrinsic tunnel diode with do and (small signal) ac load line for an oscillator circuit of Figure 3.9. (d) (e) (f) (g) 44 and b approximating this curve as outlined in Appendix A. Select an Operating dc bias point, V , (VP < VD < Vy) and calculate (VD). Equa- tion (2.19) and g(V) = dI/dV g1ves: bVD _ -aVD _ gfivn) - Ae (1 aVD) + Bbe (3.25) Calculate two cutoff frequencies, f and f , and select an operating frequency, Io, suc that fS < fo < f Calculate kmax and kmin’ R' Evaluate the load conductance, GC, and the load capacitance, Cc, for a value of k such that k . < k < k . m1n max Check for do stability according to (3.24). Finally, calculate _ l VBB - VD 4' (rs 'l' 5;) ID (VD) , This completes the design of a small-signal oscil- lator with an operating frequence, f0. CHAPTER 4 THE TUNNEL-DIODE OSCILLATOR CIRCUIT: ITS ANALYSIS AND SOLUTION 4.1 Introduction The small—signal equivalent circuit of the tunnel diode developed in Chapter 2 gives very satisfactory re- sults for the gain, bandwidth, etc., of.a tunnel-diode amplifier or the cut-off frequencies of a small-signal oscillator [5,20]. However, this model fails to give satisfactory answers to the typical large-signal nonlinear problems such as the determination of the output waveform, harmonic content, etc., in a tunnel-diode circuit. To perform large-signal analysis of the tunnel- diode oscillator circuit by analytical methods, the characteristic of the negative-resistance element, the intrinsic tunnel diode, must be simplified considerably. Kim and Brandli [4] approximated the I-V characteristic of the intrinsic tunnel diode by a third-degree polynomial about the operating bias point [4,5,22], as 3 i(v) = -gDv+ hv , (4.1a) where 3AI . -gD= - EK—~= conductance at the dc bias (4.1b) point, 45 46 I” ‘1 Ip ""‘7 ()1 r , ; I I l I I l I, | i = v I ; Cubic AI : \ ,‘1”‘approx. : \“ ’I I \‘- [I ’ 5 i l I I ' : | , I .---_L__L ___________ V t : : VP VD VV 1,: AV __.+ Figure 4.1. I-V characteristic of the tunnel diode and the cubic approximation (i-v) used by Kim and Brandli. 47 h = ——3- ' (401(3) (AV) The analysis by Kim and Brandli assumes v = V cos (wt), a perfect sinusoidal voltage about the dc bias point, VD' at the intrinsic tunnel-diode terminals. Despite the poor approx- imation to the I-V characteristic (Figure 4.1) and the pure sinusoidal voltage assumption, meaningful qualitative results were obtained. 4.2 Solution by Coerver and Sterzer Coerver [8] carried out an analysis of a tunnel- diode oscillator using a fifth degree polynomial similar to Equation (2.17)[l4], to approximate the intrinsic tunnel-diode static I-V characteristic. He simplified the oscillator circuit by neglecting harmonics, i.e., assuming single-frequency operation (Figure 4.2). Also he assumed a circuit operating frequency, fo < fs. Coerver's calculations show that the dc bias point, V for the maxi— DI mum fundamental power should be such that (Vv - VD)/(Vv - VP) = 0.4 . Sterzer [9] used a tenth degree polynomial to approximate the static I-V characteristic of the intrinsic tunnel diode. His computer calculations show that the dc bias point for generating the maximum rf power should be 48 1D (V) FF CD (a) (b) Figure 4.2. (a) Coerver's tunnel-diode oscillator circuit (b) Equivalent circuit of (a) at a frequency fo - wo/Zw < f5 where GL is load conductance and GD is to account for diode and cavity losses and L is the equivalent shunt inductance. 49 closer to the valley region. Another important result is that the maximum power generated by diodes with flat val- leys is greater than the power from diodes with narrow valleys. For an accurate solution a good approximation to the nonlinear I-V characteristic is needed, but addi- tionally, the effect of higher harmonics must be con- sidered. A better approach is to formulate the solution of the oscillator circuit in the time domain. If a steady-state time-domain solution is available, harmonic analysis can be employed to determine harmonic content. Because of the nonlinearity of the device, numerical methods of analysis must be used. The time-domain solution of the large-signal oscillator circuit is given in the remainder of this chapter. A Fourier analysis of vD(t) as constituting a frequency-domain signal of the form, vD (t) = VD + kgiysk sinwO t + Vc ck coswot], K > 2 is carried out in Chapter 5. 4.3 Large-Signal Tunnel-Diode Oscillator Circuit The complete large-signal oscillator circuit with operating frequency fO ) f i.e., capacitive load circuit, 8! is shown in Figure 4.3. The following set of equations describes the tunnel-diode section of the circuit. 50 Gc 2): CC v Cf”? gd (VD) v o VBB D diD(vD) , a: r av” A Figure 4.3. Complete large-signal tunnel-diode oscillator circuit with parallel G - Cc load, for Operat- ing frequency fo > £8“ 51 Let i = i(t), v = V(t) and v = vD(t) . Next, D l applying Kirchoff's law at terminal A-A : dvD iD(VD) + Cd 1? = i . (402) The voltage drop across the extrinsic elements, v r and L is: s s . ...____. .‘F ._ . ._ I di ._ _ L8 35 + rsi — v v . (4.3) The solution of (4.3) with i(t = 0) = i(O) is: r r "fit t it. S | l L ' i(t) - 1(0) = e L f [V(t ) - vD(t )]e 3 dt . s o (4.4) Substituting for i(t) from (4.2) and using the notations, dv d2v v = ——2- and v = -——g- , D dt D dt results in r "JEt :Et' . _ . e S t I I LS I CdvD + 1D(VD) — 1(0) + L ‘l. [V(t )-VD(t )]e dt . S 0 (4.5) Differentiating equation (4.5) with respect to time: r r . s s u .' - rs I-fgt t ' '. fgt u chD + iD(vD)vD = -;I e [V(t )-vD(t )]e dt 3 0 v-v + L D , (4.6a) 3 rs ‘ Ver = -f,— [I(t) " 1(0)] + L p (4.613) s s r v-v _ - S s 0 -0 D — f8— [1D(vD) + cdvD 1(0)] + 18— , (4.60) where .' _ d . _ 1D(VD) - a]; (1D(VD))— 9d(vD) . Rearranging Equation (4.6c): CDVD + -———-v + -———————.+ g (v )+rst . rSiD(vD) VD v+i(o)rs d D s s 5 Equation (4.7) completely describes the operation of the tunnel diode in the circuit of Figure 4.2. I The load circuit to the left of terminals A-A in Figure 4.3 is described by the following set of equations: iGC(t) = i(t) + ccé , (4.8a) _ l -. ° V(t) — VBB - a; [i(t) + Ccv] , (4.8b) _ _ l . . — VBB 5— [lD(VD) + Cdv + c061. (4.80) c D From Equation (4.3), v = 3%(v(t)) is ‘- .F IflJfi; '1'.“ 1.1! . IA 53 2. . v = Ls d I(t) + r QilEL + VD dt 5 dt . ll .2 . I " ... - LS 1D(VD)VD + lD(VD)_VD + CdVD (4.9) ' O .. .0. + rS 1D(vD)vD + CdvD + VD di(t) d2i(t) where -3Ef—- and are derived from Equation (4.2). dt Substituting Equation (4.9) into (4.8c) and the resulting expression for v into Equation (4.7), produces a single nonlinear differential equation in v The ex- DC pression for iD(vD) can be selected as any one of the following expressions, (repeated from Section 2.5): 2 a + a v + a v + --- + a v . _ N 1D(VD)_o 11) 2D ND'N?1’ or I -I . _ P V _ _ 4 _ _ S 1D(VD) — 5 [5(vD VP)(vD Vv) (vD VV) + Iv , (Vv-V) P or . 2 qvD 1D(vD) — a(Vv-vD) tanh 2ET'+‘9VVD , or -av bv . _ D D_ 1D(vD) — AvDe + B e l) . The complete equation describing the oscillator circuit shown in Figure 4.3 is obtained by substituting for v, iD(vD) and 15(VD) (from Equation (4.10)) into (4.7). The resulting equation is a thirdaorder, second-degree nonlinear differential equation in v Analytical solutions D. 54 are not known, and straightforward analytical approxima- tions quickly become complex and require numerical approximations. A feasible method of solving specific numerical cases is to use a digital computer to form time- domain solutions on an incremental time basis. 4.4 System Model of the Oscillator Circuit The primary purpose of the system approach is to develop a set of first-order differential equations des- cribing the oscillator circuit of Figures 3.7a and 3.7b. Also, this approach permits the study of the effects of voltage dependency of junction capacitance, Cd(vD), without any difficulty. The large—signal oscillator circuit shown in Figure 3.7a is redrawn as Figure 4.4a for convenience. The system graph of Figure 4.4 is shown in Figure 4.4b. The notations, lettering, and the direction of the arrows are the same as described in reference [21]. The circuit tree is shown in heavy lines. The system model for the oscillator circuit is derived as follows: (1) The set of equations describing the circuit elements, capacitors Cc’ Cd and inductor Ls’ is F- F- “1 r- -( v 7 -l- o o i 1 CC 1 d _ l . E v2 ‘ ° c—d' ° 12 - (4.11) . l 1 0 0 —— v 3 L 3 L _ L a L - 55 3v .nmmumlfimumhm Anv .owumEmnom Amy uflsouflo nonmaawomo mGOHolaoccau HmcmHmlmmqu 23 .v.v musmflm “If r G m. (2) 56 Writing the circuit and the cut-set equations [21] from the system-graph of Figure 4.4b: "V4+V1+V7"V2 - i 3rs + v + V 1 BB V2 0 Writing (4.12) in matrix notation, 0 -iD( )/Cd l/Cd 1l -Gc 12 = 0 v3 1 L- L. (3) El 0 6T C 0 El 0 d 1 o o ——- L. La. -Gc/CC o o 1/LS -1/LS ) l -r S d -l/cj -rS/LS #— .13] l V — :v—i l BB —4 F F" Substituting Equation (4.13) into (4.11) 'i 0 (4.12a) (4.12b) (4.12c) (4.13) (4.14) 57 In this set of differential equations, v can be substituted for v1 and vD for v2. This substitution re- sults in the following set of equations: F- -r --G - r - F -‘ _ __C_ —_l. v Cc 0 cc V1 0 d i ( ) - a; v0 = o - g a}. vD + o . (4.15) d d 1 .1 _._l -32 1 :22 3 LS LS L:3 3i Ls ._ ._ ._ _J _. ._ _( This describes the large-signal oscillator of Figure 4.4. Solving this set of equations on a digital computer is relatively easy compared to solving the higher-order differential equation, Equation (4.7). For initial conditions, the values of v(t), vD(t) and i3(t) for t = 0, must be specified. The bias voltage, VBB is obtained from V = V + ID(VD)[rs + l/Gc] where BB D VD is the intrinsic diode dc bias point. If vD(t = 0)= VD' then a trivial solution of Equation (4.15) is obtained because 6D.= v'= i3 5 0. In an actual oscillator, the electrical noise in the circuit may start the oscillations, which in turn begin to grow in amplitude due to small- signal instability.. In computer simulation the initial perturbation is provided by selecting vD(t = 0) not equal to the do his point, VD‘ A satisfactory choice of initial Aconditions is: 58 at t = 0 vD(0) = VB(#VD) , then i (0) = i (V ) 3 D B ’ (4.16) and v(0) = VB~+ iD(VB)rS , = VBB ' iD(VB)/GC ' These initial conditions will give non-zero values to VD noise excitation in an actual oscillator circuit. , v and i3. The ratio, VB/VD # l,is equivalent to A similar set of first-order differential equations, describing the second form of the oscillator circuit shown in Figure 3.7b, will be derived next. The large-signal oscillator circuit shown in Figure 3.7b is redrawn as Figure 4.5a for convenience. It is an equivalent to the circuit considered in the preceding section. Its system graph is shown in Figure 4.5b. Now to derive the state model of the oscillator circuit, write the set of equations describing the Cc’ Cd' LS and LC circuit elements as follows: 1 F. i, -r F 1 F V1 E:— 0 0 11 c l . vD 0 C— 0 0 12 d — d (4 17) 3E' ‘ 1 , ' 13 O 0 f; 0 V3 . 1 l7 0 0 0 i:— V7 . J L C] _ J‘ 59 Figure 4.5. Complete large-signal tunnel-diode oscillator (a) Equivalent circuit, and (b) its System- graph. 60 Writing the circuit and the cut-set equations, similar to (4.12) and putting them in the matrix form: P. " "" H F '1. " '- 11 -GO 0 -l l 0 12 0 -1D( ) l l VD 0 = + . (4.18) v3 1 -1 -r5 0 13 0 v7 -1 0 0 0 171 v8 4_ .4 ._ .. __ _. _ .. Substituting Equation (4.18) into (4.17), multi- plying the matrices, and substituting v for v1 and VBB for v8, the resulting set of equations is: T "I — 1 (- — (— "'1‘ F G 1 1 v -C—°- o 5— o— v o C C C 1 ( ) D 1 d 3? = + . (4.19) r . l 1 s 13 r; i; ‘1‘; ° 13 0 v i -—1— o o o i —B—B.- . 7 LC 7 Lc ._ .J .1— ...J - _ m— J This is the system model for the oscillator shoWn in Figure 4.5a. lance again a suitable initial condition for vD(t) must be specified.- If the dc bias point for the intrinsic tunnel diode is VD, (VP < VD < VV), then VBB = VD + ID(VD)rS. For“ (t = 0) = V the solution of (4.16) will be trivial since V D D 61 then {7(0) = {5(0) = 13(0) and 17(0) =._= 0. Accordingly suit- able initial conditions are: at t = 0 , VD(0) = VB(# VD) . Then,- i3(0) = iD(VB) , (4.20) v(O) = VB + iD(VB)rS , i7(0) = iD(VB) + [VB + iD(VB)rs]Gc . In both sets of equations the expression for iD(vD) can be any one of those given in (4.10). For any reasonably accurate expression for iD(vD), the set of equations given in (4.15) or (4.19) cannot easily be solved by analytical “methods.. They_were solved on.a digital computer. At the same time solving them numerically on.a digital computer allows freedom to: (a) choose any form for iD(vD) without making the solution any more complicated; (b) study the effect of the junction capacitance, Cd' as a voltage dependent element, C = C d d(VD). 4.5 Numerical Solution of the System-Model The system models developed in (4.15) and (4.19) for the large-signal tunnel-diode oscillator circuits of Figures 4.4 and 4.5 respectively, were solved on a CDC 3600 digital computer using Fortran IV language. The load-circuit parameters are'Gc and Cc' For studying large-signal analysis, the starting point, 62 vD(t = 0), is chosen to be the peak point voltage, VP' This choice permits steady-state solutions which cannot be obtained by small perturbation of a circuit which is ac small-signal stable. Vd(t = 0) = V is equivalent to P the shock excitation of the circuit. The set of first-order differential equations can be solved by either the Runge-Kutta method or by the Adam- Moulton method with the Runge-Kutta starter [23,33]. The computer program used for this is an expansion of the method suggested by Hildebrand [23] for a system of two first-order differential equations. The Adam—Moulton method is referred to as one of the closed types of pre- dictor-corrector formulas. A Fortran subroutine, RKAMSUB [24], based on this was used to solve Equations (4.15) and (4.19). This subroutine integrates the set of equations for the specified time-step, AT, using fourth-order Runge- Kutta method. The time-step size, AT, with which RKAMSUB inte- grates the system of differential equations, should be small enough to yield a reasonably accurate solution and at the same time large enough to yield the solution in a reasonably short time. With the expected operating fre- quency,fo, the expected time period will be T = l/fo. So AT ~ T/100 should be sufficient, considering the non- linearity involved. Fig inf (01 The num Ope is men‘ as: wher and 63 The system model of the circuit of Figure 4.4 (or Figure 4.5) is solved starting at time t = 0 with the initial conditions on vD(t), v(t) and i3(t) given by (4.16), (or (4.20)). As mentioned before The set of equations (4.15), (or (4.19)) is integrated numerically until vD(t) corresponds to the steady-state operation of the circuit. To ascertain when steady-state is reached, vD(t) is Fourier-analyzed [34] and its funda- mental, second and third harmonic components are obtained as: P=3 vD(t) = VD + 2 Vd sin (2“ t + Vd cos 313-t O p=l sp T cp T P=3 1(2—"3t-4) =v + E v e T P (4.21) D D ’ . 0 p=1 p where, I T = the new time-period of oscillation Vd = p Eh harmonic sine component SP Vd = p Eh harmonic cosine component CP _1 2 "2 _ . V — V + V - p th harmonic component D 2' d d — P SP cP and ¢ = arctan -Vd /Vd . If the harmonic 9 cp Sp 64 components VDl' V and VD3 of two consecutive periods of D2 vD(t) differ by less than 1, 2 and 4 per cent respectively, it is assumed that the solution corresponds to the steady- state operation. The resultant period of oscillation, T', not being equal to the assumed period of oscillation, T = l/fo, is not a surprising result. The period, T, is based on small- signal analysis, while the actual period of oscillation, T', is the result of a large-signal analysis of the non- linear problem. It should be noticed that T. is always greater than T. In other words, the resultant fundamental frequency of oscillation, f; = 1/T', is less than the assumed Operating frequency, f0. Using the solution corresponding to the steady- state operation of the circuit, iD(t) = iD(vD(t)) is evaluated point by point for one period of vD(t). Then v(t) and iD(t) are Fourier analyzed in the form: \ P=3 iD(t) = Id + 2 Id sin £1gt) + Id cos ZEB-t),(4.22) o p=l sp T cp T and P=3 2 2 v(t) = V + Z V sin —Eg»t + V cos —l$-t . (4.23) O p=l Sp T cp T The average power generated by the intrinsic tunnel diode at the pEE harmonic is: p = 0.5(v Id + v . (4.24) D d d Id ) 9 sp sp GP G? 65 The average power delivered to the load conductance, Gc' at the fundamental frequency, f0, will be _ 2 2 PG — 0.5 vsl + vcl) cc , (4.25a) cl and at the pEE harmonic p = o 5 v2 + v2. G (4 25b) ch ° sp cp c ' ' The logic diagram of a typical computer program based on the aforesaid procedure is given in Figure 4.6. 4.6 Examples For a given tunnel diode, the procedure stated in Section 4.5 is repeated for different dc operating points between (VP + VV)/2 and VV. For each operating point,.sets of load circuit elements (Gc'cc)' are obtained for values k . _ max - m1n (Ak), 0.8kmin where Ak -- 10 (see Section 3.4). The circuit elements (GC,CC) evaluated for of k = k max’ the parameter k < kmin indicate small-signal stable circuits. As.shown in the output curves to follow, the maximum powerv is actually obtained when circuit elements correspond to k < kmin' For each set of (GC,CC), the oscillator circuit of Figure 4.3 is solved as described in Section 4.5. From the results, a plot is obtained for the power,-PGCl delivered to the load vs. the load conductance, Go. This procedure is followed for two tunnel diodes-- one a narrow valley germanium tunnel diode and the other r¥es_ Check for a.c. stability 66 V READ ‘ \\\A(l),....A(4) 73:145th: VC / I. { __ ,READ /:——~—4Compute kmax} VD, @gnj/ L__L i Compute CC :CC 1(Lc)9VBB Compute Initial r conditions: VB=VP 231 = l/lOOfo { Integrate System- model for 400 F———- «4 ASP steps _.__j >x1’ Integrate for one period L. Fourier analyze vd(t) L_ Fourier analyze id(t) and det) T Integrate for -——a>‘one peaiod with Runge-Jutta way! I 1 NO A: s_j/,/’§teady- L state soiu.? ./ unge-Kutta method? ] Compute & Print. Pout PGcl’PGCZ’PGcfi Compute idCt) i Yes from det) No 1.4 /: Fig. 4.6. Legic Diagram of the Computer Program for Analyzing Tunnel Diode Oscillator Circuit 67 a flat valley gallium-arsenide tunnel diode. The pertinent specifications for these two diodes are listed in Table 4.1. The parameters A, a, B and b in the specifications are the same as described in Appendix A for approximating the static current-voltage characteristic of the intrinsic tunnel diode. The current-voltage plots for both diodes are shown in Figure 4.7. l. GaAs Tunnel Diode ZJ61-22, Calculations From the specifications: valley point voltage, V = 670 mV V. peak point voltage, V 120 mV. P The dc operating points attempted were vD = 0.44, 0.46, 0.48, 0.50, and 0.52 volts. 9 9 For vD = 0.44, ms = 2.27 x 10 , 0R = 4.80 x 10 . For v = 0 52 w = 2 49 x 109 w = 3 65 x 109 D . I S O ' R . . 9 So select mo = 2.77 x 10 radians/sec. The load-circuit elements, Gc'Cc' calculated for the bias point, VD = 0.48 volts, and for several values of k < km are plotted in Figure 4.8. The set (Gc ’Cc ) m m is marked by a star (*). ax corresponding to k = kmin The complete oscillator circuit of Figure 4.3 is solved as described in Section 4.5 for VD = 0.43, (0.02), 0.53 and for different circuit parameters, Gc'Cc' In this 68 TABLE 4.1 Tunnel-Diode Specifications ' ZJ61-22 1N2941 Parameter GaAs Ge rS ohms 2 1 LS nh 6 5 Cd pf 25 20 A 0.51554 0.44 a 8.6207 16.8 B 1.6114 x 10'5 5.4 x 10‘ b 6.4694 15.4 VP mV 120 60 IP mA 22.01 9.64 Vv mV 670 400 Iv mA _ 2.01 0.47 gmax mhos -0.0693 -0.0595 at V volt 0.23 0.12 69 .mmnOHo Henna» namcauuefi mo o.a m.c w.o h.o one meow no moaumfinouomuuno mmmuao>nucouuso h.¢ ousmwh muao> o> .ommuao> w.c m.o v.0 m.o ~.o H.o em PI 'aueJJna pfarad C Load Capacitance, C 70. - 0.48 volts — 2.77 x 109 rad/sec 0.06 .07 .08 .09 .10 .11 .12 .13 Load Conductance, Gc mhos ‘ Figure 4.8 Variation of load capacitance and conductance for constant operating frequency. 71 case maximum fundamental power is delivered to the load conductance, Gc' when VD = 0.48 volts. Table 4.2 shows the complete set of calculations for the oscillator cir- cuit when VD = 0.48 volts. Similar tables are prepared for each dc operating point. The plots of the funda- mental power delivered to the load conductance, Gc vs. Go for various dc operating points are shown in Figure 4.9. Figure 4.10 shows a similar plot for the second and third harmonic power delivered to Gc' 2. Germanium Tunnel Diode, lN2941, Calculations From the specifications: VP = 0.06 volts, VV = 0.40 volts. The dc operating points attempted were V = 0.25, 0.26, 0.27, 0.28 and 0.29 volts. D _ _ 9 __ 9 For VD — 0.25, ms — 2.99 x 10 , and 01R - 7.12 x 10 . For v=029 w =310x109 andw =552xlo9 D O ' s O I R O 0 So select (00 = 3.25 x 109 radians/sec. Calculations similar to those described for the gallium-arsenide diode were performed. A The optimum dc operating point is found to be VD = 0.27 volts. The curves of the fundamental power delivered to G c vs. Go for various dc operating points are shown in Figure 4.11. The results of the maximum power delivered to load conductance, Gc' for the two diodes are summarized in Table 4.3. 72 0’ iv. .u EEC .ooauaaom ouououmoooum oz mo omoo.o oomm.o e noom¢.H hoo.o mmv.o oom.o mm.H = : m.mv mmmo.o mmmm.o SMmoeJ mace on.a moo; ewe...” .. .. age «mace mmm.o «+2 on.a mmo.o mmm.o HH.H mh.H = = m.mv waoa.o Hmm.o “HHHHM.H mo.o (Namnb mHflfitfi (hmb.H a)» E m.Hm‘ mvoH.o Iomm.o mfipaom.a oa.o mom.o mumH.H mm.a moa x o>.~ e.mm whoa.o +mmm.o thHHN.H Ho.o mom.o hma.a om.H = = h.mm HHHH.o +h~m.o .w mH.H vao.o om.o mma.a mum.a .. .. m.mm mvHH.o nomm.o e moa.a mmao.o mm.o mmo.a . vmm.a = = ¢.Ho mHH.o +mmm.o _w mmo.H mao.o mom.o nmo.a mm.H = = mo mama.o emm.o oo.H moo.o meo.o wmo.a wmm.a moa x mn.~ mm mvma.o mmm.o n.5mem.o no.0 mo.o Nnm.o mm.H = = «h mhma.o +-m.o new «mm.o Hma.o hma.o Hom.o ~m.a = = o.om mNH.o |-m.o WTLNNm.o moH.o mma.o www.o h>.H = = m.mm mmmma.o (Nmm.o Wuflh~>.o mho.o mma.o m>.o H5.H .. .. m.mm hma.o vmmm.o 11s hmo.o no.0 H.o vam.o mm.a .. .. m.mOH mmmHH.o mvmm.o emwamm.o o.mm moo.o ovm.o hm.H = : >.HHH memHH.o mwm.o w.mam.o «No.q mmo.o mmv.o om.a = ch.m «.maa mmmoa.o mm.o 1.5mm.o hmo.o ohm.o mnm.o mm.H moa x no.m v.mmH mummo.o mm.o no 3: 3: 38 38 oom\omu omummm none muHo> _ I_ owcofiumm oec05umm HousoEoocsm mooflo an me o 0 mm ouane ocooom “m3 poo unouHsomm o o > vaom owumnocoo Hmcmflm ow on um3om stom (HHmEm mm ~>>coo n Go .oomxoou ooa x ak.~ u o3 .muao> mo.o n o> Amooao maooc e.v onsmam Mo muflsouflu nonmaawomo mo muasmmm Housmfiou Hmcmfimnmmumq N.v mqmda 73- " “riff-Ir! 1. .94“ .mmmMHn macaw ucmumc. amflw How mocmuoacnoo Umoa .m> Hm3om cmoa HmucmEmocsm monfi ow .mucmuoaonou omoq mH.o . ma.o , Ha.o oa.o 0 .3. fluowm\vmu ca x on.a u m - m‘mooafigm¢aw ._. L..+-_ L. - m Em... 2032mm m.q musmfim mo.o om. -. mm. m u m m e U 3. P o.a I n1 O E D. d m mo.H m d 9 D T— oa.a M111 mH.H uW 02 c3 and PG Second and Third Harmonic Power, PG -74 0.4 0.3 GaAs Diode VD = 0.48 volts 2nd Harmonic Power 0.2 wé = 2.70 x 10 rad/sec 3rd Harmonic Power 0.1 .09 .10 .11 .12 .13 Load Conductance, Gc mhos Second and third harmoniC'load power vs. load Figure 4.10 conductance. 75 .mmmmwn obofl©.ucwumMMHn How mocmuosocoo UMOH .m> Hmzom cmoa HmucmEmvcsm Ha.v ousmfim nose ow .wocwuonucou ccoq me.o mm.o mm.o Hm.o hmno m~.o ma.o .mH.o _ OH x o~.m n my . mcofla 00H»- 00m fl..." \@ m -L~.. ye; mH.o m~.o l‘ N O am.o m m o O V mm.o .m¢.o 95 ’IBMOd p901 {easemepung '[0 mm Values for an Optimum Circuit and Related 76 TABLE 4.3 Performance‘pata # Tunnel Diode Parameter GaAs Ge Units Gc 0.1078 0.20 mhos Cc 53.35 40.9 pfarad VBB 0.5284 0.2778 volts mo designed 2.77 x 109 3.25 x 109 rad/sec I mo resultant 2.70 x 109 3.2057 x 109 rad/sec Pout by diode 1.8328 0.518 mW PGcl Fundamental 1.1375 0.402 mW PGC2 2nd Harm. 0.27 0.354 “W PGc3 3rd Harm. 0.10 0.001 uW Re[Y(wb)] a 1.261 1.284 l-gDT 'V - V V" _ V°Pt 0.345 0.382 V P 'Vb, 0.7680 0.479 volts max ‘VD 0.0726 0.037 volts 77 As mentioned earlier it should be noted that the I operating angular frequency, mg, is slightly less than designed mo for both diodes. According to (3.13b), Re [Y(wo)]» F = i-gDT < 1 , is required for the oscillations to grow. For both diodes this ratio is much greater than 1. So for these cases, {gamma V vD(t = 0) value close to V will result in decaying oscil- D lations such that vD(t+w) = VD. By choosing vD(t = 0) = VP = the peak voltage, the diodes are perturbed sufficiently that sustained large-signal oscillations are obtained. 4.7 Effects of Varying Circuit Parameters (a) Oscillator Circuit with G-L-C Load Circuit The equivalent GC - Lc - Cc circuit of the equ. equ. Gc — Cc load circuit considered in the preceding section is shown in Figure 4.5. The circuit elements Cc = nC equ. and L = l/[(n-1)w2C ], n > 2 are computed to keep the Cequ. o c . Operating frequency constant. The above calculations were repeated for n = 3. In general it is observed that the average fundamental power delivered to the load conductance, Gc' is increased by about 10 per cent. But at the same time, the Operating angular frequency of oscillation, mg, decreases significantly. Table 4.4 summarizes the calcula- tions which are similar to those for Table 4.2 but for the 78 f t 1*.Ifffld: 07“”! th.o Hm.m vm.a ab.a = mm.H hm.H v.v~H vuwwo.o moo.o m¢.v mN.H mm.H = wom.a hm.a m.~va ~ommo.o mno.o mm.m m~.H mm.a = mm.H N.H m.awa mmwoa.o mao.o on.~ on.a hm.a = mom.a mo.a m.m>H ~oaa.o «Ho.o Nv.m ham.a mm.H = mnm.a wwm.o m.oo~ mmmmH.o moo.o Ham.o th.H hm.a = hmo.~ vmn.o ~.mv~ mvmma.o moo.o wmv.o mom.a vm.a = mwo.m vmm.o a.mm~ wwwma.o moo.o mmo.o wo.H on.a = mvo.~ mmm.o H.mmm mvNHH.o moo.o .mho.o pah.o ow.a mod x mwo.~ mmv.o m.mmm mhmoo.o oom\pmu a: panama one cacoaumm vacoaumm HmucmEmocom mOOflo 03 o o o cum cam use . q o w Scum unopanmom ow pmoq on Hmzom uHDUHHU coon muao> mv.o umm> .Umnmmm A>>V©U u no .omm\omu ca x hn.~ u 03 .muao> mv.o n 0> m Amwoflo mmmov m.v onsmwm mo muflsoufiu HoumHHfiomo mo muasmom Hopsmfioo Hmcmflmlmmumq v.v mqmda 79 equivalent circuit of Figure 4.4. The tunnel diode under consideration is ZJ61-22 and the Operating point is VD = 0.48 volts. The conclusions with regard to an increase in fundamental power and a decrease in the resultant operating frequency, are evident when the data of Tables 4.2 and 4.4 are compared. ' (b) Oscillator Circuit with Junction Capacitance I as a Junction-Voltage Dependent Element. 1 The oscillator circuit considered in Section 4.6 is solved again, but this time the junction capacitance, CD, it considered to be a junction-voltage dependent element: -1/2 CdOCWC VD) for VD < Vv , and Cd = Cd(VV) for VD), VV , where V _ c contact potential. The specified value of Cd is used for VD = VV: _ Cd(VVLV:c - lV . Cd(VD) - chfT— (4.26) The calculations show that the average fundamental power delivered to G c when the junction capacitance is con- sidered a voltage-dependent element, Cd = Cd(vb) , is always higher than the same power delivered to G c when the junction 80 capacitance is considered voltage-independent, viz., Cd = Cd(VD). Figure 4.12 shows the graphs of the power output for the two cases for the GaAs tunnel diode and the dc operating point equal to 0.48 volts. (c) Effect of Varying Operating Frequency As the Operating frequency approaches the resis- tive cut-off frequency, wR, the Gc element value de- creases sharply. Soon the value of Gc decreases enough to violate dc stability condition (3.24) and we get 1 +— — (Gc rs) < I gDI When a circuit with component values causing dc instability was simulated on the computer, oscillation could not be sustained. For the circuits satisfying dc stability (3.24) the power delivered to load Gc decreased rapidly as the operating frequency was increased. 1; J.-'-_mnn.s.1 ~ ‘ l 81 .ucmocmmmo oomuao> mocmuflommoo .cowuoczn Any .ucmumcoo mocmuflommmo cowuosan “my mocmuooocoo OOOH .m> Hmzom omoa HmucmEmocsm moss ow .mocmuosccou omoq ma.o ma.o Ha.o oa.c _om-_ 1 103;. mm muao> m¢.o "no acoflo made Hfiwwfi .1 4 . A _ . =7 . I w: a . . , 1.1 . a“- omm\omu Am? OH x m oom\cun ca x mo.~ m on m:o«umaa,om in...__-._._.:_._....._.__. ~H.v museum mo.o om.o O In C 61 H o In O to ‘ '4 9d ’IGMOd peoq {equemepuna O H H MU! mH.H CHAPTER 5 HYBRID APPROACH FOR MAXIMIZING LOAD POWER 5.1 Introduction The intrinsic tunnel diode is the device element [54-3—1511— T ‘w F’ which due to its dynamic‘negative-resistance property converts dc power into signal ac power. Hence, an attrac- tive approach to maximize the load power is to determine the optimum voltage vD(t) at the intrinsic-diode terminals that will produce maximum fundamental power, P1, where T _ l - and vD1(t) and iD1(t) are the fundamental frequency com- ponents of vD(t) and iD(t), respectively. Next a circuit, D included, that will sustain vD(t) at the intrinsic-diode terminals must be with the diode elements rs, LS and C synthesized. The determination of the optimum voltage vD(t) cannot be carried out analytically by conventional variational Calculus techniques due to the highly non- linear nature of the intrinsic diode.. Rather, extensive computer calculations were used. With the Optimum vD(t) determined a suitable circuit can be designed following’ 82 83 usual circuit synthesis procedure. This approach is called a hybrid approach. 5.2 Criterion for the Maximum Fundamental Power from the Intrinsic Diode The circuit designed must be such that current- voltage matching exists at the intrinsic-diode terminals, -B (Figure 5.1). The A -B terminal admittance of the l 1 circuit is determined by the harmonic components of vD(t) A g r‘-—t-r-r-T w and the resulting iD(t). To determine Optimum components of VD(t), consider the Fourier analysis of VD(t): N V . 2n 2n v (t) = V + 2 V Sin -— t + V cos ——-t) , D do k=1 dSk (T ] dCk ( T ] (5.2) where V d and Vd are k513- harmonic sine and cosine com- sk dk ponents, respectively. Consider 360 equally spaced values per period of vD(t) . Performing point-by-point calcula- tions 360 equally spaced values per period of iD(t) = jT)(vD(t)) can be obtained using one of the expressions from tiuase given in (4.10). The Fourier analysis of iD(t) is: N I . . 2n 2n 1 (t) = I + I Sin —— t + I cos —— t . (5.3) From this, the k2 harmonic component of the power produced at: the intrinsic tunnel diode is: 84 EdEflme may now UHSUHHO .Hm3om can can OOOHU amass» camcauucH .H.m mudmflm 308 o we may no Amman fits owmcfluucH mucoamam Ofluwmmumm ufldouflo omoq w ............. A w ................... J n u m m n _ . . _ _ . _ u _ " Ao3v _ . . . _ _ .AQ>vU _ v” /L\\©U “ EN _ n a . llll _ .H. _ . > . u N xuozumz " _ u m m . u n + u - BSA in, H - oLTm m. u f n as n ma luluUIItIIuL 85 P = 0.5 V Id + Vd sk sk d . (5.4) dk ck ck d Pd1 is to be maximized with respect to the (2k + l) harmonic components of vD(t), Vdo’ Vdsk' Vde; k = 1,2,...NV. It should be noted that Pd1.will be a negative quantity as corresponding to positive power being delivered to the load. 5.3 Circuit Design for the Maximum Power from the Intrinsic For the passive-circuit to the left of terminals, Al-B, (Figure 5.1), the voltage and the current are VD(t) and -iD(t), respectively. For current-voltage matching at the common terminals, A -B, the circuit admittance at the l fundamental frequency, mo, should be V + jV Y(w)=-:SI idC1=Y(w)+'Y(w) (55) c 0 -Id - j d R o 3 I 0 ° ' sl cl th Similarly at the k——-harmonic, the circuit admittance should be: Yc(kwo) = -Id _ de . (5.6) sk ck These equations provide admittance requirements for the circuit design after the Operating frequency, w , O is selected. 86 Consider the case where only fundamental frequency components are assumed. Following the analysis as indi- cated above, the required admittance at the Al-B terminals is Yc(wo) = YR(wO) + jYIKwO) . (5.7) At the A2-B terminals the admittance required is YR(wO) + j(YI(wo) - woCD) . (5.3) Then, 2(wo) = YR(wo) ;j<¥1(wo) - woCD> 2 ’ (YR(wov '+ [YI(wo) - woCD) = Re[Z(wo)] + jIm[Z(wo)] . (5.9) is the impedance required at the Az-B terminals. Similarly at terminals, A3-B ZT(wo) = [Re[Z(wo)] - rs] + lem[Z(wo)] - woLs] = Re[zT(wO)] + jImIZT(wO)] (5.10) is required. When “0 = ”max' then RelZT(mo)] = 0 as then all the power produced by the intrinsic tunnel diode is dissipated in the series resistance, rs. When the operat- ing angular frequency ”0' is equal to w , the reactive S (component of ZT(wo), is equal to zero as corresponding to the definition of ms. For ”0 > ms, Im[ZT(wO)] is negative 87 corresponding to a capacitive load circuit. For mo < ms, Im[ZT(wo)] is positive corresponding to an inductive load- circuit requirement. To determine w = w max m’ Y (m ) Re[ZT(wm)] = 2 R m 2 - rS = 0 . [YR(wm)1 + [YI(wm> - meD] Then Y (m ) R m 2 _ 2 _ 2 2 ——E;——- YR(wm) — YI(wm) 2meDYI(wm) + meD , or (5.11) Y (m ) 2 2 2 2 R m _ (DmCD zmeI (wm)CD + YI (mm) + YR(wm) " T — 0 o (5.12) Hence Y (m ) \/Y (w’) _ I m R m _ 2 1 3 D This expression for w is identical to the expression in max (3.10b) for the resistive cut-off frequency when YI(wm) = 0 and YR(wm) = gD Similarly, the solution of Im[ZT(gm)] = 0 (for Oh- taining an expression for ms) results in the following cubic equation: -fifi’si’xe‘ig... L L S s s 2 2 2 3 2 YR(wS) + wSYI(wS) - 2w..YI(wS)CD + wSCD . (5.14) 88 When,as is usually the case YI(wS) << YR(wS), the equation yields w = l _ YR(wS) (5 15) S LsCD C2 ' ' D This is identical to the equation (3.11b) for the self- resonant frequency if YR(wS) = gD. Thus, when mo < wmax' the load circuit of Figure 5.1 should be designed such that the admittance to the left of terminals Al-B is Yc(wo). Upon completion of the design the dc stability requirements, according to (3.13), must also be met for proper functioning of the oscillator circuit. In Appendix C it is shown that any two frequency admittance specifications, such as: YT(wo) = YR1(wO) + jYIl(wo) (5.16a) YT(2wO) = YR2(2wo) + jYIZ(2wo) (5.16b) can always be realized if YRl(wo) and YR2(wo) are pOSitive. 5.4 Examples The procedure mentioned in Sections 5.2 and 5.3 was carried out for the two diodes analyzed in Section 4.6. The most difficult part of the hybrid approach is that of obtaining the Optimum harmonic components of vD(t), viz., V Vcl’ V Vc2(as for Nv = 2). Several do' Vsl' 52' attempts were made to find these analytically. Finally a 89 computer program, namely, GREAT--Generalized Random, Extremum Analysis Technique--, (Appendix D) was used for numerical evaluation. This program finds the minimum value of a function of several variables. The initial value of each variable is selected at random from within the specified limits. Evaluating the direction cosines with respect to each variable, the variables are increased or decreased to minimize the functional value. For a gallium-arsenide tunnel diode, considering the fundamental sine-cosine components only, the optimum bias point is found to be about 0.465 f 0.004 volts and the corresponding maximum fundamental power, P x' gene- ma rated is about 1.947 mW. When second harmonic components are also introduced, the optimum bias point shifts to 0.405 t 0.004 volts and the maximum fundamental power out- put increases to about 2.264 mW, a 16.3 per cent increase. Similarly for a germanium tunnel diode, considering the fundamental sine-cosine components only, the optimum bias point of about 0.27 i 0.004 volts is obtained, and maximum fundamental power output is about 0.530 mW. When second harmonic components are also considered, the opti- mum bias point of about 0.23 i 0.004 volts and Pmax about 0.633 mW results. Introducing third harmonic components gives optimum bias point between 0.24 and 0.28 volts and P x about 0.67 mW. Inclusion of higher harmonic components ma results in larger output power, but computer time required 90 to find the optimum voltage components increases con- siderably. As might be expected higher harmonics produce progressively smaller changes in Pmax' Table 5.1 gives typical starting and final values of harmonic components of diode voltage, vD(t) = Vdo + VSl Sinwot + VCl coswot + V82 s1n2wot + V cosZw t , (5.17) c o 2 and the power output from a gallium-arsenide tunnel diode, As mentioned in Section 5.3, the diode current iD(t) = I + Id Sinwot + I do coswot sl dcl +II sinZth + I cosZwot , (5.18) d c2 32 d is calculated from vD(t). The harmonic components of iD(t) for the two cases listed in Table 5.1 are given in Table 5.2. When only fundamental components are considered, the circuit admittance required for the gallium-arsenide diode is according to Equation (5.5): Yc(wo) = 2.4387 x 10‘2 - j 5.6915 x 10'10 . Then, w = 4.3079 x 109, and w z -9 . max 2.3 x 10 radians/sec. S With gd(VdO) = -2.65 x 10‘2 mhos, rS = 2 ohms and mo > ms , 91 TABLE 5.1 VD (t) Harmonic Components when Fundamental Power is Maximum (GaAs Diode) Initial Value Component (Monte-Carlo Method) Final Value lst case: Fundamental Component only Vdo Volts 0.41695 0.46425 V61 " 0.06931 0.31349 VCl " -0.23125 -0.24794 Pout mW -1.2624 -l.9480 2nd case: Fundamental and Second Harmonic Components Vdo Volts 0.46802 0.41067 V81 " 0.12911 0.43022 Vc1 " -0.04920 -0.04584 V82 " 0.123 -0.02570 ch " -0.06229 -0.11747 Pout mW -1.3033 -2.26293 TABLE 5.2 iD (t) Harmonic Components when Fundamental Power is Maximum (GaAs Diode) Component lst Case 2nd Case Ido ma 9.7076 12.953 Id ma -7.6451 -10.401 sl Id ma 6.0465 1.108 c1 I ma -3.7962 - 0.229 dsz 92 the dc stability condition requires the load conductance Gc to be greater than 0.025 mhos. The circuit elements--GC,Cc--for mo = 2.4 x 109, (108), 4.2 x 109 radians/sec are calculated according to Equations (5.7) through (5.10). These are plotted in Figure 5.2. The results from the exact analysis (dis- cussed in Chapter 4) for different wo's are tabulated in Table 5.3. The fundamental power generated by the gallium- arsenide diode is 1.948 mW in each case. In the table 0 I w , Gc and Cc are from Figure 5.2. mo is the resultant (fundamental) frequency of oscillation; P is the power out generated by the diode; and P is the power delivered to Gc the load, Gc' It is evident that the power output from the diode, Pout' and the power delivered to the load, Gc' at the fundamental frequency reduces rapidly when the higher funda- mental frequencies are considered.5 The optimum circuit performance obtained in Chap- ter 4 is also listed in Table 5.3. VD for this case was 0.48 volts. A comparison of this with the data of set no. 2, Table 5.3 shows that the fundamental P and Po ob- G ut c1 tained in Chapter 4 are higher: PG by 7 per cent and cl the power transfer efficiency, PG /P by 5 percent. c1 out However, the small-signal analysis for the circuit elements (obtained by hybrid approach) listed in Table 5.3 93 mhma.a mm.H moa x Non.~ «.mm m.noa moa x hh.m muao> mv.o u o> .¢ Hmummcu mo uwsouflo Edfiflumo vv.mm ma.m~ e o~.m m muflsouflo muoumaawomOIcoz mm.mv mm.~m e oa.m w mm.o onw.a e mm.~ ¢.hm mm.on = om.~ m mmo.a vvm.a e mo>.m m.mo o.oma e mn.~ m hom.a Nam.a moa x v¢.m mm.mm m.~m~ moa x om.m H 3E SE oom\omn omummm mossle omm\omu .02 Ho moowo Eoum ucmuasmmm o o 03 umm Om Doom: 03 O O - peeouflo econ 069.5 6.468 mflmocucmm Canaan Mom mama mocmEHOMHmm omumamm can mosam> uflsouflo m.m mandfi 94 ‘eoueqonpuoa peoq °9 soqm .OOOHO Hmccsu camcwnuca mdmw Scum Mason HancoEMOCSM EOEmeE How .hucmsqwuu mcflpmuomo .m> mocmuosocoo OMOH can wocmuflommmo omen OH x owm\omn 03 .mucmnuoum mcwumnmmo o.v . m.m . m.m o.m n.~ m we. wanmumep .o.o mo. NH. wH. om. «N. mm. J~.m magmas e.~ e ea T m on n. 3 E d E 3 em 3 D. u D a eeea d T: D. I w on em on 95 indicates that the factor F = Re[Yc(wo]/|-gDI is equal to 0.926--1ess.than l, unlike the value of factor F for the Optimum case obtained in Chapter 4. Factor F = 0.926 indicates that the circuits are very close to ac small- signal stability. Consequently, the circuits should al- ways be shock excited. When analyzed numerically, the oscillations could not be generated when vD(t = 0) was selected close to Vdo 0.46 volts. The results listed in Table 5.3 are obtained by considering vD(t = 0) = VP = 0.12 volts. The last two sets in Table 5.3 resulted in non-oscillatory circuits when analyzed numerically. This is due to dc instability. But small-signal analysis indicates dc instability for data of set no. 5 only, while set no. 4 is very close to it. In the second case of Table 5.1, the voltage at the intrinsic-diode terminals, vD(t), up to and including second harmonic components, is considered. Table 5.1 lists one set of several optimum voltage components, Vdo' Vsl' Vcl' Vs2' VC2 producing same fundamental power. The circuit admittance, matching at the intrinsic-diode termi- nals, is calculated for this set according to Equations (5.5) and (5.6). The resulting admittances at the funda- mental and the second harmonics are: Yc(wo) = 2.418 x 10"2 + j 1.135 x 10'6 and 6 3 - j 7.353 x 10' . Yc(2wo) = -8.955 x 10 96 Note that Re[YC(2wo)] is negative. Several dif- ferent Optimized sets were attempted. But for each case Rech(2wo)] was found to be negative. Similar results were obtained for the germanium tunnel diode. Consequently, in the case of these two tunnel diodes a circuit could not be designed that could provide the required current- voltage matching for the second harmonic. This need not be true for tunnel diodes in general. Designing a circuit with Yc(wo) only, and neglecting the mismatch at the second harmonic, resulted in greatly reduced power output when analyzed numerically as outlined in Chapter 4. CHAPTER 6 CONCLUSIONS In this thesis a computer algorithm has been developed for evaluating the fundamental power delivered to the load of a tunnel-diode oscillator circuit. This algorithm has been successfully used to determine changes in fundamental power with changes in circuit parameters. Specifically it was found that simple Operating circuits could be optimized to produce maximum fundamental power. When the optimized circuit is used, tunnel-diode voltage and current are rich in harmonic content. Large-signal analyses that assume perfect sinusoidal signals are not adequate to evaluate Optimum performance. From an in-depth computer evaluation of a germanium and a gallium-arsenide tunnel-diode oscillator circuit it was found that (1) Optimum tunnel-diode bias voltage is closer to the valley voltage than to the peak voltage. (2) The optimum tunnel-diode bias voltage approaches closer to the valley voltage as the valley region of the diode flattens out. (3) Fundamental power delivered to the load de- creases as the operating frequency increases. 97 98 (4) The operating frequency was somewhat lower than the frequency indicated by small-signal analysis. (5) Maximum power output was-found to occur with a circuit which was small—signal stable. This mode of operation would be feasible only if provisions were made for shock exciting the circuit. (6) Somewhat greater fundamental power can be obtained by the use of a voltage-dependent junction capacitance in comparison with circuit operation in which the junction capacitance is constant. (7) For maximum power output the conversion efficiency was about 23.7 per cent. (8) Contrary to some reports in the literature, at no time was it found that the circuit would oscillate at a frequency greater than the resistive cut-off frequency. Although the findings listed above were verified for only the two diodes examined, they are believed to be generally valid. From the work completed, it is con- sidered feasible to use the algorithm developed to design simple circuits for Optimum Operating conditions. At ultra-high frequencies the circuits become more complex and it is not certain whether the algorithm can be modi- fied to include the added complexities. This area, parti- cularly as it relates to transmission-line analysis, could be the subject of further investigation. APPENDICES APPENDIX A APPROXIMATION TO TUNNEL-DIODE STATIC CURRENT-VOLTAGE CHARACTERISTIC EQUATION A useful two-term approximation of the tunnel- diode I-V characteristic was first suggested by Ferendici and Ko [11] as ' "av ' bV A V e T + B (e T IT (VT) = T - l) (A.1) where IT(VT) is the terminal current and VT is the termi- nal voltage. The Id- d characteristic of the intrinsic tunnel diode at terminals a-a' (see Figure A.1), is ob- tained as discussed below. The equivalent circuit of the tunnel diode is as shown in Figure A.1. For static characteristic as ob- tained at low frequency, the effects of series inductance, L and junction capacitance, Cd(Vd), can be neglected. S! Then (A.2) Id(Vd) = IT(VT - Vrg where Vrs= IT(VT)rS Thus point-by-point calculations will give the characteris- tic of the intrinsic tunnel diode. This characteristic can similarly be approximated by 99 100 A IT(VT) rs Ls Id(vd) a VT Cd ;& 9,, (Va) V ' d O _ a I Equivalent circuit of a tunnel diode Figure A.1. Static current-voltage characteristics at l Tunnel diode, terminals A-A Figure A.2. Intrinsic tunnel diode, terminals a-a (a) (b) 101 -an bV AV e + B(e _ d d" d Id(V - l) (A.3) The parameters A, a, B, and b can be evaluated as follows: Suitable pilot points are chosen according to the fit desired. Herein, a closer fit is desired in the nega- tive-conductance region and near the valley and peak points. Suitable pilot points are: (a) peak point, (VP, IP) (b) valley point, (VV, IV) (c) point of maximum negative conductance, or a point(Vc, Ic) near it, and (d) a point between (V , IV) and (V IP) or FP' (VFP, IP). The contribution of the diode-injection cur- rent (2nd term of Equation A.3) is considered negligible for Vd < Vc' Cons1der dId(Vd) _ _ _ d gd(Vd) "' —-a-V-d—' - A(l an)e for Vd < VC . (A.4) Using gd(VP) = 0 in (A.4) gives a = 1/VP. For the point _ -aV (V0, 10), IC - AVCe C. Knowing the coefficient a, the coefficient I exp(V /V ) A = C v c P , (A.5) C can be determined. At the valley point the tunneling current component (lst term of Equation A.3) is 102 -aVV It(VV) = AVVe , (A.6) and the diode injection current component, ID(Vd), at valley point will be ID(VV) = Id(Vv) - It(VV) (A.7) bV - _ FP VFP , It(VFP) ~ 0 , so ID(VFP) — B(e Near V - 1). Consider the ratio 1 (v ) bVFP ID(VV) ebVV - 1 In (A.9) the only unknown is b, but due to the involved exponentials it must be solved numerically, as follows: First guess, b = 1n(ry(VFP - Vv) . 0 ' < < Since VV VFP' b b0. b V e l FP _ 1 Consider b = 0.98b , and evaluate r = _ . l 0 l b V e 1 V - 1 If r1 < r, consider b2 = 0.99b0 and evaluate r2; if r2 < r, consider h3 = 0.995b0 and evaluate r3. Continue the pro- cess until rn < r. Then bn-l < b < bn. Then, try bn+1 = (b -l + bn)/2 and calculate r n n+1“ Continuing this procedure find bk giving rk, as close to the ratio, r, as desired. Finally, knowing b, evaluate ID(VFP) B = W— (A.9) 103 Thus, parameters A, a, B and b are determined for the intrinsic tunnel-diode junction characteristic. APPENDIX B STABILITY OF A LINEAR ACTIVE SYSTEM B.1 In this appendix the stability of an active linear network, Nd’ connected to a passive linear network, N, as shown in Figure B.1 is considered. Since the networks, N and Nd' are linear and their parameters are constant, the pertinent differential equations relating v(t) with i(t) and vD(t) with iD(t) will be linear with constant coefficients [25] as P(a%)i d Y(s) Yd(S) Figure 3.2. System of Figure B.1 with their terminal impedances and admittances. 106 — d d— _. 7 ' 1 P a-E- "'Q a-t- I(t) 0 = . (3.4) d d, Pd arE 0.: 31 LV‘t’_ LOJ Solutions of (3.4) will contain terms of the form AeSt where s = c + jw, a complex number [25]. i(t) = I(s)eSt , (13.5) st v(t) = V(s)e , is a solution. However, the general solution [25] will be: ? skt (S) e I k=1Ak i(t) (3.6) m s t X Bk(s)e k . k=1 v(t) For studying the stability of the system shown in Figure B.1 it is sufficient to substitute (B.S) into (3.4) and check whether the resulting characteristic polynomial is a Hurwitz polynomial, viz., a polynomial having all its roots with a negative real part. Substituting (3.5) into st (3.4) and canceling e , the set of equations obtained is: Ms) -Q(s)’ Ms) 0 . (3.7) Pa“) ode.) V(s) o 107 The characteristic polynomial, As, of the set of equations (B.7) is: As = P(s) Qd(s) + Pd(s)Q(s) . (B.8) For system stability, As = 0 should not have any root with a positive real part. The natural frequencies of the sys- tem are the roots of the characteristic equation. Consider A(s) P(s) Pd(s) (maniac) = éTTs + Tod s V(s) Vd(s) = He) + Id(s) (13.9) = 2(5) + Zd(s) = ZLoop(S) ' Similarly, MS) _ _. P(s)Pd(§Y - Y(s) + Yd(s) - YNode(s) . (B.10) ZLoop(S) and YNode(S) are the loop impedance and the node admittance respectively, for the system shown in Figure 3.2. 2(5) + Zd(s) is the input impedance for termi- I nals, A-A ; Y(s) + Yd(s) is the input admittance for I terminals, B-B . The natural frequencies of a network can also be obtained from Z (s) = 0 and Y Loop = 0. In general, Node(s) the natural frequencies obtained from these will be dif- ferent. If no independent voltage or current source is 108 connected in the network, or if Z op(s) and Y (s) Lo Node are obtained by considering all the voltage sources shorted and current sources open, then the natural frequencies ob- tained on either the impedance basis or the admittance basis will be unique [26]. The tunnel-diode oscillator circuit analyzed in Chapters 3 and 4 can be analyzed on either basis. The input impedance (admittance) of a stable net- work is positive real. A positive real function, G(s), must satisfy [27]: Re[G(s)] 2 o for Re(s): Re(o + jw) = o > o . (3.11) If the input impedance, ZLOOp(s)' (admittance, YNode(S))' is such that: Re[ZLoop(Sfl < 0 Re[YNode(s)] < 0 for Rds)= 0, Viz., s = 3w . (B.12a) Then the corresponding network will be unstable and any oscillation initiated will grow in amplitude. Since the os- cillations are of angular frequency, too, as given by either Im[Z (3)] = 0 Loop or Im[ = 0 with s = jw . (B.12b) YNode(S)] APPENDIX C CIRCUIT SYNTHESIS BASED ON TWO-FREQUENCY ADMITTANCE SPECIFICATION In this Appendix it will be shown that a suitable -w ‘l‘. M circuit can be synthesized to have a given admittance at 1‘ two frequencies provided the conductances of the two ad- mittances are positive. Let the admittances at the two frequencies be: Y(wl) = YR(wl) + 3YI(wl) , and Y(wz) YR(w2) + jYI(w2) . (C-l) The imaginary parts of an admittance specified at two frequencies can always be realized by a three-element Foster network. In a degenerate case, a two-element Fos- ter network will be sufficient. This will be obvious from the following sketches: Figure C.1: for situations where Im[Y(wl)] > 0 and Im[Y(w2)] < 0 , Figure C.2: for situations where Im[Y(wl)] < 0 and Im[Y(w2)] < 0 , and Im[Y(w1)] > 0 and Im[Y(w2)] < 0 . 109 . m3 V we . e v filmeeuiee . e v .1MeewieH rev 3 v a . e A .1 sculeH . e v .1 svwlsH .on.lnv.xmc mcflow>oum mxuo3umc Houmom mo mowumwumuomumso mocmcvoum .m.o wnowflm A3 A3 3“ 23 3“ 110 ——-—-—up——————— ——-—c—-—r——--———— _-——--—--1. L 1 HstH 1_»_eH 1_mlsH .ma v as . Axle v filmeveieH eem 1.1e A llflsceleH mcHOH>oum mxuosumc Hmumom on» How mowumflumuomnmno mocmsvmum .H.U mnsmflm 3 A 3 n 3 ( _ ‘ _»_EH ”SLEH HMHEH ~>HSH 111 Thus the form of the Foster network realizing the imaginary parts of two admittances will be: ks‘s2 + mg) kts2 + mi) or .2..{ .42..3 ' ‘QZ’ or in a degenerate case, like Figure C.1(a) and C.2(a): ks k‘s2 + mi) -2———§' or S . (C.3) S + (1)1 The real parts of the admittances must be realized first. In doing so, the imaginary parts will be altered, but they can always be realized as shown in Figures C.l and C.2. For realizing the real parts of the admittance either of the two general forms of networks shown in Figure C.3 should be adequate. Consider the network of Figure C.3a. Let G = fii and R = Then —l-. 1 2 Gz C613 1 Y‘S’= W+m' LCG s2 + (RZCG 1 l + C)s + G1 (G1 + Cs)(§2 + Ls) ' (s2 + l/LC) + (Rz/L + Rl/L)s ‘ G1 G R ’ G1 R2 ' (C°4) + )s 2 l 2 3 +175— “5+7. f1 xi... ‘1": n. a... r=:. m 112 or F—O e , - ~11 (a) (b) )1 Figure C.3. Networks to realize the real parts of an admittance specified at two frequencies. (1N AD VV \JV 70) :11) (a) (b) Figure C.4. Numerator and denominator of Equation (C.7). 113 The function defined in equation (C.4) cannot be negative on the jw axis because it is a positive real function. Consider the quantity, (C.5) With the substitution of S = jw, only even-power terms in s will effect the real part of the admittance. Odd-power terms in s will effect only imaginary parts of the admittance. With odd-power terms drOpped (C.5) becomes R G G R 2 l 2 2H1 1 l 2 2 (S + f6) (3 + '_Lc ) " r‘Ri + R2’(-5 + T)3 Gl 2 2 2 R291 G1 R2) 3 + - — 4- Tc— ) c ‘1: Substituting jw for s in (C.6) and simplifying gives: (1)4 +w2(R2 + R R )/L2 + R G /L2C2 2 1 2 2 l _ N G - - 0 (C07) 1 . 2 2 2 D . J-w + RzGl/LC) + (GI/C + Rz/LN This real part of the desired network, (C.7), must be positive real. Also any real zeros in w2 must be double; there are no real zeros on the jw-axis. Thus the numerator, N, will be of the form.shown in Figure C.4(a) and the 114 RelY¢w)] YR (.02) Q( T YR(‘°1) .' * I ' I ' . l I : u . l w w 1 2 Figure C.5a. Real parts of the admittance function at the frequencies ml and ”2' Re [If (00)] \ Figure C.5b. Real part of admittance function Yl(w). 115 denominator, D, will be of the form shown in Figure C.4(b). The ratio, N/D, can be almost any positive number. Example: Let YR(wl) < YR(w2). Design a four element G-C, R-L network (like Figure C.3a) of terminal admittance function Y1(w) such that Re[Y1(wl)] = YR(wl). This network will partially realize YR(w2) since Re[Y1(w2)] # YR(w2) in general. Let “Tu-fl Re[Y1(w2)] = Yé(w2). This is shown in Figure C.5b. Now by scaling the element values, a zero is created at oz by reducing YR(w2) by the amount YR(w2)-Yg(w2). Scaling the element values will not affect the zero designed at ml. When this is completed, YR(w1) and YR(w2) are realized. With this result, the modified imaginary parts to be realized can be calculated and the design is completed with a prOperly designed Foster network. 'i'IilI-IIIIIIP .IlIl-l 116 APPENDIX D / . ‘x ' STAR” 2 \ -11-J T >initialize Lindices __I_____ i O {renormalize L- weights Wm... . END ‘3 Print i output -_-.-_-.._-_{--_-- i i arrange I increment ,extremum index I'/ ,o . . --._.. -. ._ w. . —_.....--.———«._.1..___.. ..—.. a”. -. .— //’ §function E . 1 I E data 3 ‘ r ’ 3 r J (increment "T::!“"‘W econdary ‘inl'ldllzel i search L_weights . 1 index _} -..-_._._T_._.___ l 1 ‘. /1\ find i r . ‘secondary ___.;L_-li; ; I search ( generate ! i point ; 2 initial . g "1 ‘4 ) search ; g r- 1 ; j point ; ' utilize ‘ ...___._J 9 1 ( 4 1 52nd order ; 5 d‘ t g 1 3 function i 9 a US ,. I .- 3 I wegrbts ’b‘ : apprOXi' ; l o“ l ) a , : __¢_m__mm_4 : mation g 1 T L J i __-__1._--- .____1_---- E ‘ 1 i 1 3 I ; )generate ( perform ‘ g i search [contracting ) ) vector i search 3 i 3 t i )\ .[ . ! i // | 3 ; ‘///' is -\ No ; perform 3 \\ " o t 3 search vector,;»~——-'~expanding ; . -/ l 9 null? search : A l 3 ,Yes 1 . ' z I I ‘. [ 2 I ' L ( No A /’/. is . 3 \ , _ _~<— termination \yz Yes“ required? 3 I/ 1 store extremum ) point Logic Diagram of the Computer Program "Generalized Random Extremum Analysis Technique" (Courtesy of Instrument Division, Lear Siegler, Inc., ~ Grand Rapids, Michigan) ..—n . “-0..”- wmoJ n-l . REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] REFERENCES Esaki, Leo, "New Phenomenon in narrow Germanium p—n junctions," Phys. Rev;, vol. 109, no. 2, Jan., 1958, pp. 603-604. ' Smilen, L. I. and Youla, D. C., "Stability Criteria 7” for Tunnel Diodes," Proc. I.R.E., vol. 49, July, 1] 1961, pp. 1206-1207. 1 ii Davidson, L. A., "Optimum Stability Criterion for Tunnel Diodes Shunted by Resistance and Capacitance," Proc. I.E.E.E., vol. 51, Sept., 1961, p. 1233. Kim, C. S. and Brandli, A., "High Frequency, High Power Operation of'Tunnel Diodes," I.R.E. Trans. on Circuit Theory, vol. 8, Dec., 1961, pp. 416- 425. Chow, W. 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Mag., vol. 2, 1926, pp. 978-992. Riddle, R. L. and Ristenbatt, M. P., Transistor Physics and Circuits, Prentice-Hall, Inc., EngIewood Cliffs, N.J., 1968, pp. 332-347. Ryder, John D., Electronics Fundamentalsgnd Appli: cations, Third EditiOn, Prentice-Hall, Inc., N.J., T9 4, p . 438-439. Seely, Samuel, Electron Tube Circuits, Second Edi— tion, McGraw Hill, N.Y., 1958, pp. 421-425. Edson, W. A., Vacuum Tube Oscillators, John Wiley & Sons, Inc., N.Y.,v1953, ch. 4. Henrici, Peter, Lecture Notes on Elementary Numeri- cal Analysis, J6hn Wiley & Sons, Inc., N.Y., 1962, ch. 10. Hsu, Hwei P., Outline of Fourier Analysis, Unitech DiViSj-on' N.Y., 1967' pp. 18-19, p0 3330 Nagata, M., "A Simple Negative—Impedance Circuit with No Internal Bias Supplies and Good Linearity," I.E.E.E. Trans. on Circuit Theory, vol. 12, Sept., 1965, pp. 433-434. Martinelli, G., "Realization of a Short-Circuit Stable Negative-Resistance Circuit with No Inter- nal Bias Supplies," Electronics Letters, vol. 2, no. 8, August, 1966, pp, 308-309. Ramanan, K. V. and Varshney, R. C., "New Short-Circuit Stable Negative-Resistance Circuit with No Internal Bias Supplies," Electronics Letters, vol. 3, no. 5, May, 1967, pp. 186-188. Ralston, Anthony, A First Course in Numerical Analy- sis, McGraw Hill, N.Y., 1965, CH. 6. "llllflfllllllfllllli“