DESIGN AND IMPLEMENTATION OF INTEGRATED SELF-POWERED SENSORS,
CIRCUITS AND SYSTEMS
By
Chenling Huang

A DISSERTATION
Submitted to
Michigan State University
in partial fulﬁllment of the requirements
for the degree of
DOCTOR OF PHILOSOPHY
Electrical Engineering
2011

ABSTRACT
DESIGN AND IMPLEMENTATION OF INTEGRATED SELF-POWERED SENSORS,
CIRCUITS AND SYSTEMS
By
Chenling Huang
Wireless sensor systems have been widely used for both industrial and civil applications. With the
development of circuit design and fabrication technique, sensor nodes now can be implemented
with small scale at low cost, which is promising for ubiquitous sensing. However, with more
functions integrated, the conﬂict between power consumption and expected lifetime became critical. Sensor nodes powered with batteries are generally compromised by extra physical size and
periodic battery replacement. Therefore, energy harvesting techniques are intensively involved in
sensor design where environmental signal acts as auxiliary energy source.
A typical energy harvesting sensor consists of four parts: energy harvester, energy storage,
power management and sensor subsystem. Energy harvester scavenges power from environmental
signal which is then transferred into energy storage. Since the output power is usually not in appropriate form, power management is used to provide a usable supply voltage/current for sensor
subsystem. The limitation of energy harvesting sensor is determined by the power consumption of
sensor subsystem, the efﬁciency of energy conversion and the available energy level from environment.
In this dissertation, a novel solution referred as “self-powered sensor” is proposed to extend the
limitation of energy harvesting sensor. The proposed sensor can directly harvest energy from input
signal being sensed. Therefore the usage of energy storage and power management is eliminated,
which achieves higher energy efﬁciency.
To demonstrate proposed solution, the system and circuit design of a self-powered sensor are

presented for long-term ambient vibration monitoring. Constrained by its application, the sensor can only scavenge energy from input strain signal itself, in which scenario all existing energy
harvesting techniques fail. The greatest design challenge is to achieve both ultra-low power computation and non-volatile storage. In this dissertation, a novel technique based on ﬂoating-gate
transistor is presented. By exploiting controllable hot electron injection procedure, speciﬁc computation can be performed according to the characteristic of input signal. In addition, ﬂoating-gates
can also retain computation results with no power consumption.
For autonomous sensing, a hybrid energy harvesting topology is proposed on system level.
The sensor is designed with two different operation modes. In self-powered sensing mode, it can
perform continuous monitoring, computation and data storage which is powered by input strain
signal. In data interrogating mode, additional functions such as data sampling and wireless communication can be enabled once a certain reading device is provided.
The dissertation is organized as follows. In chapter 1, the history of wireless sensor system
is reviewed. The motivation of self-powered sensor and the contributions of this dissertation are
presented. Existing energy harvesting techniques are evaluated in chapter 2. In chapter 3, the case
of long-term ambient vibration monitoring is studied and the hybrid energy harvesting topology is
proposed for self-powered sensor system. In chapter 4, the principle of ultra-low power computation and non-volatile storage is explored based on controllable injection procedure on ﬂoating-gate
transistor. To veriﬁed proposed solution, a sensor prototype was fabricated in 0.5-µm standard
CMOS process. The details of circuit design and evaluation are presented in chapter 5, including
analog signal processor, analog-to-digital converter, radio frequency front-end, digital baseband,
etc. Chapter 6 shows an extension of ultrasonic powering and communication system based on
preliminary work and chapter 7 draws ﬁnal remarks.

I dedicate this dissertation to my parents, for their love and support.

iv

ACKNOWLEDGMENT

I would like to take this opportunity to acknowledge several people who have been particularly
inspiring and helpful to my research work.
Professor Shantanu Chakrabartty has been totally supportive to this project. I appreciate the
opportunity he granted me for my Ph.D. program. I appreciate all his guidance in the past few
years for sharing great ideas and discussing problems with me. I am also grateful for all his efforts
to help me edit papers and debug chips. Without his help, I could have ﬁnished my work in a much
harder way.
I am also very thankful to my other committee members, Professor Lawrence Drzal, Professor
Donnie Reinhard and Professor Fathi Salem. I appreciate your advices for my work in the defense
and thank you for reviewing my dissertation.
To my labmates, thank you for the time we have spent together. In particular, I want to say thank
you to Amit Gore, Yang Liu, Amin Fazel and Ravi Krishna. Thank you for all those discussions
we have gone through which have been a great input for my work.
And to my friends, Chang Liu, Shaowen Ji, Guanqun Zhang, Xiaowen Liu, Faisal Abu-Nimeh
and many of others whose names I cannot list here, thank you for making my life much enjoyable
besides the research work.
Finally, my most gratitude goes to my ﬁancee, Yang Yang. She has always been loving, supporting and understanding. She makes all my efforts meaningful and my life would become totally
different without her. Thank you for always being there for me.

v

TABLE OF CONTENTS

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ix

List of Figures
1

2

Introduction of Self-Powered Sensor System
1.1 Wireless sensor system . . . . . . . . . .
1.2 Energy harvesting sensor . . . . . . . . .
1.3 Motivation of self-powered sensor . . . .
1.4 Contributions in this dissertation . . . . .

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1
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7
9
10

Evaluation for Energy Harvesting Technique
2.1 Solar energy harvesting . . . . . . . . . .
2.2 Thermoelectric conversion . . . . . . . .
2.3 Vibration excitation . . . . . . . . . . . .
2.3.1 electromagnetic . . . . . . . . . .
2.3.2 electrostatic . . . . . . . . . . . .
2.3.3 piezoelectric . . . . . . . . . . .
2.3.4 comparison and remark . . . . . .
2.4 Radio frequency radiation . . . . . . . . .

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12
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17
20
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22
24
28
28

3

Challenge for Self-Powered Sensor
32
3.1 Energy analysis for self-powered sensing . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Long-term fatigue prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3 Hybrid energy harvesting topology . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4

Ultra-Low Power Computation and Non-Volatile Storage
4.1 Floating-gate based analog signal processor . . . . . .
4.1.1 ﬂoating-gate transistor . . . . . . . . . . . . .
4.1.2 piezoelectricity driven hot electron injection . .
4.1.3 controllable injection procedure . . . . . . . .
4.2 Linear ﬂoating-gate injection circuit . . . . . . . . . .
4.2.1 circuit topology for linear injection . . . . . .
4.2.2 programming range . . . . . . . . . . . . . . .
4.2.3 injection rate control . . . . . . . . . . . . . .
4.2.4 injection resolution . . . . . . . . . . . . . . .
4.2.5 remark . . . . . . . . . . . . . . . . . . . . .
vi

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44
44
45
47
55
57
58
63
64
67
68

5

Design and Implementation for Self-Powered Sensor
5.1 System level architecture . . . . . . . . . . . . . . .
5.2 13.56MHz RF front-end . . . . . . . . . . . . . . .
5.2.1 Schottky diode based voltage multiplier . . .
5.2.2 ﬂoating-gate based voltage multiplier . . . .
5.2.3 clock data recovery . . . . . . . . . . . . . .
5.2.4 load modulation . . . . . . . . . . . . . . .
5.3 Floating-gate injector array . . . . . . . . . . . . . .
5.3.1 implementation of strain level monitoring . .
5.3.2 implementation of strain rate monitoring . .
5.3.3 linear injection array . . . . . . . . . . . . .
5.4 Analog-to-digital converter . . . . . . . . . . . . . .
5.4.1 readout mechanism . . . . . . . . . . . . . .
5.4.2 single-slope analog-to-digital converter . . .
5.4.3 fully differential opamp . . . . . . . . . . .
5.5 High voltage generator . . . . . . . . . . . . . . . .
5.6 Digital baseband . . . . . . . . . . . . . . . . . . .
5.6.1 ring oscillator . . . . . . . . . . . . . . . . .
5.6.2 control logic . . . . . . . . . . . . . . . . .
5.7 Evaluation for proposed self-powered sensor system .
5.7.1 long-term ambient vibration monitoring . . .
5.7.2 wireless telemetry . . . . . . . . . . . . . .

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69
69
71
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115
115
116
119
119
122

6

Ultrasonic Powering and Communication
127
6.1 RF versus ultrasonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.2 Model for ultrasonic powering and communication . . . . . . . . . . . . . . . . . 129

7

Conclusions
138
7.1 Summary of contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.2 Future directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

143

LIST OF TABLES

1.1

Speciﬁcation summary for a selection of sensor nodes: MCU. . . . . . . . . . . . .

5

1.2

Speciﬁcation summary for a selection of sensor nodes: 2.4GHz RF transceiver. . .

5

1.3

Speciﬁcation summary for a selection of sensor nodes: others. . . . . . . . . . . .

5

1.4

Energy harvesting sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

2.1

Comparison for efﬁciency for thermal harvesting circuits. . . . . . . . . . . . . . . 20

2.2

Comparison for efﬁciency for piezoelectric harvesting circuit. . . . . . . . . . . . . 27

2.3

Comparison of three vibration energy harvesting techniques. . . . . . . . . . . . . 28

2.4

Implementation examples for RF powering sensor system. . . . . . . . . . . . . . 31

3.1

Strain of median nerve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2

Power and energy budgets reported in literature for low power operations. . . . . . 38

6.1

Material properties and geometric parameters used for simulation. . . . . . . . . . 133

7.1

Main Speciﬁcations for self-powered sensor. . . . . . . . . . . . . . . . . . . . . . 139

viii

LIST OF FIGURES

1.1

Numerous applications for wireless sensor system. . . . . . . . . . . . . . . . . .

2

1.2

Comparison of manufacture cost. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3

1.3

Conventional architecture for wireless sensor node. . . . . . . . . . . . . . . . . .

4

1.4

Performances of various batteries: (a) Ragone chart; (b) power density versus lifetime for batteries from [8]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

1.5

Architecture of energy harvesting sensor. . . . . . . . . . . . . . . . . . . . . . . .

9

1.6

Comparison between (a) conventional sensor, (b) energy harvesting sensor and (c)
self-powered sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

Detail architecture for energy harvesting technique. . . . . . . . . . . . . . . . . . 13

2.2

Output characteristics: (a) equivalent electrical module of solar cell [18]; (b) output
characteristics from an implementation example of solar energy harvester [19]. . . 14

2.3

System diagram of a solar energy harvester implementation [20]. . . . . . . . . . . 15

2.4

Efﬁciency of solar harvesting technique. . . . . . . . . . . . . . . . . . . . . . . . 16

2.5

(a) basic structure of a semiconductor thermoelectric couple; (b) output power
characteristic from a TEG [14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6

Circuit model for thermal harvester. . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7

(a) principle of electromagnetic energy harvester; (b) cross-section of an implementation (not in scale) [34]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.8

Electrostatic energy harvester: (a) in-plane overlap (top view); (b) in-plane gap
closing (top view); (c) out-of-plane gap closing (side view) [36]. . . . . . . . . . . 23
ix

2.9

(a) equivalent circuit model for piezoelectric energy harvester; (b) general architecture of piezoelectric harvesting circuit [39]. . . . . . . . . . . . . . . . . . . . . 25

2.10 Harvester circuit: (a) doubler; (b) diode bridge; (c) SSHI. . . . . . . . . . . . . . . 26
2.11 DC/DC conversion: (a) buck; (b) buck-boost [12]. . . . . . . . . . . . . . . . . . . 26
2.12 (a) Piezoelectric pushbutton; (b) an implementation of an RF transmission sensor
powered by a piezoelectric igniter [47]. . . . . . . . . . . . . . . . . . . . . . . . 27
2.13 Path loss for RF signal at (a) 915MHz; (b) 2.45GHz. . . . . . . . . . . . . . . . . 30
3.1

Thermoelectric conversion efﬁciency: (a) versus temperature gradient [28]; (b)
versus size [55]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2

RF conversion efﬁciency versus input level and frequency [56]. . . . . . . . . . . . 35

3.3

Output energy from piezoelectric transducer versus frequency [57]. . . . . . . . . . 35

3.4

(a) theoretical vibration energy for various structures and loading conditions; (b)
energy harvested from a piezoelectric bimorph from the energy sources in (a) [58].

37

3.5

Power budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.6

Fatigue monitoring: (a) S-N curve; (b) loading history of strain signal [69]. . . . . 40

3.7

Comparison between (a) MCU based sensor and (b) self-powered sensor. . . . . . 42

3.8

Proposed hybrid energy harvesting approach: (a) self-powered sensing mode (powered by ambient vibration signal being sensed; (b) data interrogating mode (powered by RF signal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.1

Layout structure for a pMOS ﬂoating-gate transistor with tunneling port. . . . . . . 45

4.2

(a) illustration of IHEI process in a pMOS FG transistor; (b) illustration of IHEI
using an energy band diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3

(a) schematic of a piezoelectricity driven ﬂoating-gate injector; (b) equivalent circuit model of (a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
x

4.4

Responses of hot electron injection: (a) theoretical and measured response of the
FG injector plotted on a logarithmic scale and on a linear scale (inset); (b) responses measured at various source current; (c) responses measured for using 8
prototypes fabricated in various runs; (d) responses measured under different temperature conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.5

Illustration of ultra-low power signal processing using multiple FG injectors to
achieve level crossing algorithm (not in scale). . . . . . . . . . . . . . . . . . . . . 56

4.6

Proposed linear injection technique: (a) circuit architecture; (b) programming
mode when Sp is open; (c) biasing mode when Sp is closed. . . . . . . . . . . . . 59

4.7

Measured injection current when the source voltage is varied. . . . . . . . . . . . . 61

4.8

Programming setup for linear injection architecture. . . . . . . . . . . . . . . . . . 62

4.9

Measured response showing (a) output range for linear injection; and (b) measured
resolution of proposed linear injection circuit. . . . . . . . . . . . . . . . . . . . . 63

4.10 Measured linear injection responses when: (a) Iref is varied while Vref = 4.9V;
and (b) Vref is varied while Iref = 50nA. . . . . . . . . . . . . . . . . . . . . . . 65
4.11 Measured injection rate when Vref and Iref are varied. . . . . . . . . . . . . . . . 66
4.12 Measured INL and DNL for Vref = 5.11V showing 13.3-bit programming resolution over a range of 4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.13 Measured INL and DNL for Vref = 5.25V showing 12.1-bit programming resolution over a range of 4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.1

System level architecture for the proposed self-powered sensor system. . . . . . . . 70

5.2

Structure of voltage multiplier and cross view of Schottky diode’s layout. . . . . . 72

5.3

(a) layout of Schottky diodes with different ﬁngers; (b) measured characteristics of
Schottky diodes implemented in a 0.5-µm standard CMOS process. . . . . . . . . 73

5.4

(a) Measured output voltage response for Voltage multiplier1; (b) measured output
response for Voltage multiplier2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
xi

5.5

A ﬂoating-gate diode: (a) cross view; (b) circuit model with parasitic diodes; (c)
the diode with auxiliary programming transistor for adjusting ∆V . . . . . . . . . . 76

5.6

(a) I-V characteristics of ﬂoating-gate diode with programmable threshold voltage;
(b) output response for a 5-stage voltage multiplier based on proposed FG diode. . 79

5.7

Schematics of envelope recovery and PWM demodulator. . . . . . . . . . . . . . . 81

5.8

Principle of load modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.9

(a) Load modulation with R; (b) load modulation with C. . . . . . . . . . . . . . . 84

5.10 Different approaches for load modulation. . . . . . . . . . . . . . . . . . . . . . . 85
5.11 Simpliﬁed schematics for self-powered strain level monitoring array. . . . . . . . . 86
5.12 Simulation results for level crossing implementation: (a) Vsw1 -Vsw3 ; (b) sourceto-drain current for each channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.13 Measurement results for level crossing implementation: (a) Vs1 –Vs3 ; (b) total current consumption for ﬂoating-gate array with voltage/current reference. . . . . . . 90
5.14 Measurement results for different level of Vdd : (a) Vdd = 5V; (b) Vdd = 6V; (c)
Vdd = 7V; (d) Vdd = 8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.15 Measurement results to calculate the resolution for event counting: (a) various
counting results for voltage pulses with different duty cycles; (b) different responses measured for α = 240/256 and α = 248/256 with the reference being the
response corresponding to α = 256/256. . . . . . . . . . . . . . . . . . . . . . . . 94
5.16 Simpliﬁed schematics for self-powered strain rate monitoring array. . . . . . . . . 96
5.17 Measurement results of step responses for 3 channels. . . . . . . . . . . . . . . . . 99
5.18 Measurement results for impact rate monitoring. . . . . . . . . . . . . . . . . . . . 100
5.19 Measurement results of linear injection circuit for (a) short-term monitoring and
(b) long-term monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.20 Measurement results for strain level monitoring with linear injector. . . . . . . . . 104
xii

5.21 The proposed level shift readout method. . . . . . . . . . . . . . . . . . . . . . . . 107
5.22 Schematics of fully differential analog-to-digital converter. . . . . . . . . . . . . . 109
5.23 Fully differential opamp used in single slope ADC. . . . . . . . . . . . . . . . . . 111
5.24 Schematic of all-pMOS low voltage charge pump. . . . . . . . . . . . . . . . . . . 113
5.25 Schematic of clock generator for 4 phase low voltage charge pump. . . . . . . . . 114
5.26 Schematic of ring oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.27 Finite state machine for control logic. . . . . . . . . . . . . . . . . . . . . . . . . 117
5.28 Schematics of channel selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.29 Setup for real-time experiment: (a) equivalent circuit model for piezoelectric transducer and FG array; (b) MTS setup used for real-time evaluation of the selfpowered sensor interfacing with a PVDF transducer. . . . . . . . . . . . . . . . . . 120
5.30 Output responses measured for real-time experiments when the sensor is interfaced
with a PVDF transducer and subjected to controlled cyclic strain levels with magnitude (a) 2100µε and (b) 2500µε. . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.31 Experiment setup for wireless telemetry. . . . . . . . . . . . . . . . . . . . . . . . 123
5.32 Impedance matching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.33 Measurement results for wireless telemetry between reader device and sensor: (a)
enable/disable injection; (b) enable tunneling; (c) single channel sampling; (d)
continuous sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.1

Efﬁciency as the function of receiver’s diameter: (a) at 1cm distance; (b) at 10cm
distance [82]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

6.2

Efﬁciency as the function of source-receiver distance: (a) for 10mm diameter; (b)
for 5mm diameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6.3

Ultrasonic powering and communication system using Mason’s model: (a) system
diagram; (b) equivalent circuit model based on Mason’s model [84]. . . . . . . . . 131
xiii

6.4

Mason’s model with labels for calculations. . . . . . . . . . . . . . . . . . . . . . 133

6.5

Simulated energy conversion efﬁciency versus distance. . . . . . . . . . . . . . . . 136

6.6

Ultrasonic communication model. (a) simpliﬁed circuit model for load modulation; (b) simulated result for normalized modulated voltage. . . . . . . . . . . . . . 137

xiv

Chapter 1
Introduction of Self-Powered Sensor System
Firstly motivated by military applications, the research of wireless sensor system has been growing
dramatically in past decades for industrial and civil applications. In this chapter, a brief introduction of wireless sensor system is presented. The conﬂict between power consumption and expected
lifetime is discussed. Finally, the motivation of self-powered senor is explained, followed by the
scientiﬁc contributions in this dissertation.

1.1

Wireless sensor system

Wireless sensor system, also known as Wireless Sensor Network (WSN), is a network formed by
numerous spatially distributed autonomous sensor devices which can be used to monitor, process
and transfer physical or environmental signals cooperatively. For various applications, the signal
of interest can be vibration, temperature, pressure, humidity, motion, etc. As illustrated in Fig. 1.1,
each sensor device (called node/mote) is able to detect ambient signal and share information among
the whole network. Data detected by any node can be processed locally or be transmitted to
external reading device/receiver.
1

Figure 1.1: Numerous applications for wireless sensor system.

Like many other technologies, military applications had become one major driving force for
the research of wireless sensor system in its early stage. During the Cold War, a system of acoustic
sensors, SOund SUrveillance System (SOSUS), had already been deployed on ocean bottom for
submarine surveillance. The same system is now in service for monitoring other events in ocean
such as seismic and animal activities [1]. Another military application during the Cold War is an air
defense system developed to guard the continental United States and Canada with aerostats as sensors [2]. Limited by technologies at that time, the sensor nodes used for these military applications
were not as functional as today’s devices, and human operation was also highly involved.
Later around 1980, the research of wireless sensor system was started with Distributed Sensor
Network (DSN) program of Defense Advanced Research Projects Agency (DARPA). The program’s objective was to design a system where many spatially distributed low cost sensing nodes
could collaborate with each other but operate autonomously. In 1978, the technology components
for DSN program were revealed which included sensors (acoustic), communication, processing
2

techniques, algorithms and distributed software. From system level, the proposed architecture contained all major parts of a modern sensor node’s. However, the mobile node for collecting data in
DSN program was implemented as large as a truck whose volume was limited by the manufacture
and fabrication technology.
With the development of Complementary Metal-Oxide Semiconductor (CMOS) and Micro
Electro-Mechanical Systems (MEMS) fabrication, people started to think about implementing
sensor node in a much smaller scale. In Fig. 1.2, the manufacture cost of 1 million transistors
is compared with those of other materials’ according to the data from U.S. Geological Survey.
From the cost point of view, it has already been economically feasible to build CMOS circuit for
autonomous sensing. By using these modern techniques, it became possible to design a sensor
node in the scale of several cm3 .
The architecture of a wireless senor node at system level is illustrated in Fig. 1.3. The sensor consists of four major blocks: sensing block, signal processing block, communication block

106

transistor (106)
steel (lb)
aluminum (lb)
carbon fiber (lb)
titanium (lb)

Cost ($)

104

102

100

10−2

10−4
1970

1980

1990

2000

2010

Year

Figure 1.2: Comparison of manufacture cost.
3

RF transceiver

Power
source

Analog-to-digital
converter

Micro-controller

Sensor
transducer

Memory

Figure 1.3: Conventional architecture for wireless sensor node.

and power block. For sensing block, a transducer is used to convert physical signal of interest
into electrical form. Generally, the sensed signal is in analog form after conversion and therefore
an Analog-to-Digital Converter (ADC) is usually required for data sampling. The signal processing block consists of Micro-Controller Unit (MCU) and memory cell [Random-Access Memory (RAM)/Flash/Electrically Erasable Programmable Read-Only Memory (EEPROM)] to compute and store sampled data. When data communication is activated, communication block [RadioFrequency (RF) transceiver in Fig. 1.3] is used to exchange data among sensor network. Finally,
power block delivers essential working energy for all circuits.
For comparison, Table 1.1–1.3 summarize several sensor node implementations after year
2000 [3, 4]. Table 1.1 lists main speciﬁcations for the MCU employed for each platform. The
clock speed, memory and bus-width are founded to vary widely among platforms due to different
applications. Note that all selected Central Processing Units (CPUs) are ultra-low power in order
to extend the lifetime of sensor node. From Table 1.2, the power consumptions of RF transceiver
in different modes are listed which indicates much more power is required for communication than
that for sleep mode. The peak current of communication block easily exceeds 10mA in Tx/Rx
and thus communication can only be enabled for a small fraction of operation time. Table 1.3 lists
4

Table 1.1: Speciﬁcation summary for a selection of sensor nodes: MCU.
Platform

CPU

Clock

RAM/Flash/EEPROM

Bus

TelosB

TI MSP430F1611 [5]

8MHz

10K/48K/1M

16-bit

MicaZ

Atmel ATmega 128L [6]

8MHz

4K/128K/512K

8-bit

SHIMMER

TI MSP430F1611

4/8MHz

10K/48K/None

16-bit

IRIS

Atmel ATmega 128L

8MHz

8K/640K/4K

8-bit

Sun SPOT

Atmel AT91FR40162S [7]

75MHz

512K/4M/None

32-bit

Table 1.2: Speciﬁcation summary for a selection of sensor nodes: 2.4GHz RF transceiver.
Platform

RF transceiver

Sleep power

Rx power(mA)

Tx power(mA)

TelosB

Chipcon CC2420

0.02µ–426µA

18.8

17.4

MicaZ

Chipcon CC2420

0.02µ–426µA

18.8

17.4

SHIMMER

WML-C46A BT

50µ–1.4mA

40

60

IRIS

Atmel AT86RF230

20nA

15.5

16.5

Sun SPOT

Chipcon CC2420

0.02µ–426µA

18.8

17.4

Table 1.3: Speciﬁcation summary for a selection of sensor nodes: others.
Platform

Dimension(in)

Weight with/no battery(g)

Price

Year

TelosB

1.26×2.58×0.26

63.05/14.93

US139

2005

MicaZ

1.25×2.25×0.25

63.82/15.70

US99

2004

SHIMMER

0.80×1.75×0.50

10.36/4.87

EUR199

2006

IRIS

1.25×2.25×0.25

69.40/21.29

US115

2007

Sun SPOT

2.50×1.50×1.00

58.08/33.49

US750

2005

physical dimension, weight and cost for each sensor node. A battery is included for all platforms
to deliver power which becomes a constraint for both dimensional size and weight. Also, the cost
listed in Table 1.3 indicates a price cut is necessary, especially for applications requiring hundreds
or thousands of sensor nodes.
5

Energy density (Wh/kg)

10

3

Alkaline
10

Lithium-ion

2

NiMH
Lead-acid
Supercapacitor
101
1
10

10

2

10

3

10

Power density (W/kg)

4

(a)
103

2

>ŝƚŚŝƵŵ
10

10

1

0

10

EŝD,

Power ( µW)

10

-1
0

ŝŶĐͲĂŝƌ
ůŬĂůŝŶĞ

ƌĞĐŚĂƌŐĞĂďůĞ >ŝƚŚŝƵŵ

1

2

3

4

5

Year

(b)
Figure 1.4: Performances of various batteries: (a) Ragone chart; (b) power density versus lifetime
for batteries from [8].

With the development of signal processing techniques and micro fabrications, advanced functions can be integrated into sensor node shown in Fig. 1.3. It makes wireless sensor system applica6

ble to ubiquitous applications such as industrial sensing, environmental/habitat monitoring, trafﬁc
control, medical health care and so on [2]. However, the usage of battery poses serious drawbacks
for sensor node. The drawbacks are two-folded: (1) battery is usually space/weight consuming; (2)
battery has limited lifetime. From Table 1.3, the weight of battery has been found to be more than
half of the total weight of sensor node’s. Moreover, the physical size of battery is much larger than
other commercial chips used on sensor platform. Therefore, the inclusion of battery compromises
the requirement of light weight and small scale.
An even worse inﬂuence of using battery is caused by its limited lifetime. The Ragone chart of
various batteries available for wireless sensor applications is plotted in Fig. 1.4(a), where vertical
axis describes the total energy available per kilogram and horizontal axis shows how fast the energy
can be delivered. Assuming the average power consumption of sensor node is about 100µW, the
theoretical lifetime is calculated to be less than 3 years when a 10g Alkaline battery is used. The
expected lifetime is not sufﬁcient for most long-term autonomous sensing applications (expected
lifetime of more than 10 years). For comparison, the average power available from various batteries
per cm3 versus lifetime is also plotted in Fig. 1.4(b) where both of drain and leakage current are
considered [8]. Due to ﬁnite lifetime, battery has to be replaced periodically to guarantee proper
function of sensor node. However, such replacement can be difﬁcult or even impossible when an
extremely large number of nodes have been deployed or the nodes cannot be accessed physically.

1.2

Energy harvesting sensor

To get rid of battery, there is another solution to design wireless sensor node where sensor can
harvest energy from different environmental signals. The history of human to scavenge energy
from nature can be dated back to the usage of windmills. However, by given the volume constraint
7

of several cm3 , energy harvested from environment is not sufﬁcient to power any circuits for quite
a long time. Thanks to the development of low power CMOS circuit, it became possible to design
energy harvesting sensors in small scale. In [9, 10], an extensive list of potential energy sources is
presented which can be used for small scale unmanned devices. As shown in Table 1.4, there are
four groups of energy sources to power autonomous sensor system: radiant, mechanical, thermal
and magnetic, all of which can provide a few µW energy level. It has been validated that such
energy source is competent to activate ultra-low power wireless senor in the scale of cm3 [11].
Figure 1.5 presents the standard architecture of energy harvesting sensor node. Depending on
applications, a speciﬁc energy harvester functions as the power source in Fig. 1.3. Expect for
the energy harvester, the design considerations for energy harvesting senor are similar to those of
conventional sensor nodes’. As shown in Fig. 1.5, only sensor transducer and ADC are required
for continuous operation while those power-hungry building blocks (MCU and RF transceiver)
must remain in low duty cycle to save energy [16]. Energy scalable computation and low energy
software are also necessary for signal processing [17].
More details of energy harvesting technique will be discussed in chapter 2 where different
technique is evaluated based on its performance and limitation. The greatest design challenge
is to choose an appropriate environmental signal as the energy source. When available energy
Table 1.4: Energy harvesting sources.
Type

Energy sources

Power density

solar (outdoor)

photovoltaic

15,000µW/cm3 [12]

solar (indoor)

photovoltaic

150µW/cm3 [12]

mechanical

electromagnetic, electrostatic, piezoelectric

3.89µ–830µW/cm3 [13]

thermal

pyroelectric, thermoelectric

2,000µW/cm2 @12o C gradient [14]

magnetic

electromagnetic

0.01µ–0.3µW/cm2 [15]

8

Environment

RF transceiver

Energy
harvester

Micro-controller

Analog-to-digital
converter

Sensor
transducer

Memory

Figure 1.5: Architecture of energy harvesting sensor.
level becomes low, the power consumption of sensor subsystem and total conversion efﬁciency
determine the limitation of energy harvesting technique.

1.3

Motivation of self-powered sensor

As shown in Fig. 1.5, data sampling and signal processing performed by ADC, MCU and memory
require a minimal amount of energy level for continuous operations. When there is no sufﬁcient
auxiliary environmental signal provided, the energy harvesting technique fails. However, for many
industrial and civil applications, sensor nodes have to stay functional even with weak/no auxiliary
energy source. So far, there is no solution to address the problem and that is the reason to propose
a new architecture of sensor node – “self-powered sensor.”
Figure 1.6 illustrates and compares the general difference among three types of wireless sensor
nodes. Different from energy harvesting sensor, self-powered sensor does not require any auxiliary
energy sources from environment to maintain functional. Instead, the only signal can be used as
energy is the input signal being sensed. When input signal is sensed, sensor node can start up to
sample and process the signal, and store results before input signal vanishes. When there is no
input signal, sensor node can stay inactive which achieves a highly energy efﬁcient manner.
9

power

(a)

energy
storage

optical

(b)

Sensor

power
RF

Sensor

sense

sense

Environment

Environment

acoustic

(c)

Sensor

sense
power

Environment

Figure 1.6: Comparison between (a) conventional sensor, (b) energy harvesting sensor and (c)
self-powered sensor.
For typical applications, the input signal of interest is unpredictable and in burst mode. The
available energy/power is usually below the minimal energy level to power MCU based architecture shown in Fig. 1.3 and Fig. 1.5. Due to the extremely tight budget, a different system architecture is essential for self-powered sensor to achieve ultra-low power consumption and non-volatile
storage. The design challenges and details will be discussed in chapter 3.

1.4

Contributions in this dissertation

This dissertation will discuss the system and circuit design of self-powered sensor for long-term
ambient vibration monitoring. The reason to choose this study case is because self-powered technique is proved to be the only solution for such application. The sensor node can be widely used for
Structural Health Monitoring (SHM) or Bio-mechanical Implant Monitoring (BIM) for long-term
autonomous sensing. The major contributions in this dissertation includes:
1. An analog signal processing technique is proposed for self-powered sensor system based on
10

controllable Hot Electron Injection (HEI) on Floating-Gate (FG) transistor. Proposed technique
can achieve both ultra-low power signal processing and non-volatile data storage. When interfaced
with piezoelectric transducer for vibration monitoring, the processor can sense, compute and record
different attributes of input signal for fatigue monitoring.
2. Two different FG injection circuit are designed. The ﬁrst FG injector is presented as the
basic computation cell for analog processor which has log-linear response for HEI procedure. The
injector shows good robustness to temperature, process and biasing variations. The second FG
injector introduces a feedback loop to eliminate nonlinear parameters during HEI procedure which
provides a stable and precise control for ultra-low power signal processing.
3. A hybrid energy harvesting topology is proposed for self-powered sensor in the replacement
of MCU based architecture. With new architecture, the sensor node can perform continuous selfpowered sensing during long-term ambient vibration monitoring, while more functions such as
data sampling and communication can be activated once a reading device is provided for data
interrogating.
4. The design and implementation of proposed self-powered sensor system are described with
both simulation and implementation results. Besides FG based analog processor, circuit design for
other building blocks are evaluated such as ADC, on-chip high voltage generator, RF front-end,
digital baseband, etc. The fully functional autonomous senor shows good performances for both
real time self-powered monitoring and wireless telemetry.

11

Chapter 2
Evaluation for Energy Harvesting
Technique
As mentioned in chapter 1, there are four types of environmental signals generally used as auxiliary
energy sources: sunlight, temperature gradient, ambient vibration and RF radiation. Figure 1.5 are
replotted here in Fig. 2.1 to show the details of energy harvesting circuit. As shown in Fig. 2.1,
energy harvesting sensor usually consists of four building blocks: energy harvester, energy storage,
power management and sensor subsystem. Depending on speciﬁc energy source, certain transducer
is selected for harvester circuit to convert environmental signal into electricity form. The output
power is then transferred into energy storage. In most cases, even with sufﬁcient energy level, the
output energy cannot directly power the sensor subsystem. Therefore, power management with
DC/DC conversion is used to generate appropriate supply voltage/current. Power management
might also include matching or tracking mechanism for energy harvester to maximize the output
power from transducer. In this chapter, the details of energy harvesting technique are discussed
with implementation examples where both advantages and disadvantages are evaluated.
12

environment

energy
harvester

energy
storage

sensor
subsystem

power management

Figure 2.1: Detail architecture for energy harvesting technique.

2.1

Solar energy harvesting

Solar energy harvesting technique is one of the most mature and commercially established solutions for power scavenging. Typically, a solar or PhotoVoltaic (PV) cell is used to convert solar
energy into electricity by photovoltaic effect [18]. The equivalent circuit model of a common solar
cell is depicted in Fig. 2.2(a) where the cell is formed by a current source IL in parallel with a
diode, a shunt resistor RSH and a series resistor RS [18]. The output I-V characteristic can be
expressed as

I = IL − I0 · exp

V + I · RS
q · (V + I · RS )
−1 −
,
n·k·T
RSH

(2.1)

where IL is photo-generated current, I0 is reverse saturation current of diode, q is elementary
charge, n is diode ideality factor (1 for an ideal diode), k is Boltzmann’s constant and T is absolute temperature. According to equation (2.1), the typical output characteristics of a solar cell
are plotted in Fig. 2.2(b): dashed line indicates the I-V characteristic and solid line indicates the
corresponding output power for different loading conditions [19]. The solar cell can operate over
a large range of output voltage/current among which Maximum Power Point (MPP) indicates the
optimum loading condition. From Fig. 2.2(b), output power becomes null in both short-circuit and
13

RS
ID

ISH

IL

I
V

RSH

(a)
15

2

10

1

5

Power (mW)

Current (mA)

3

Power
Current
0
0

2

4
6
Voltage (V)

8

0
10

(b)
Figure 2.2: Output characteristics: (a) equivalent electrical module of solar cell [18]; (b) output
characteristics from an implementation example of solar energy harvester [19].

open-circuit extremes. Since available power is the main concern for energy harvesting system,
loading condition should be optimized to MPP to achieve the highest efﬁciency.
The basic architecture of a solar energy harvesting is presented in Fig. 2.3 with the implementation example from [20]. The power management is formed by MPP tracker at Input stage and
DC/DC converter at Output stage. The Input stage consists of a PV cell panel and a power converter (formed by Cin , M , D and L) to adjust cell’s loading condition. In order to optimize output
efﬁciency, Maximum power point tracker is included which consists of a pilot cell (manufactured
14

Max Power Point Tracker
FOC
algorithm VMPP
Pilot
cell

Hysteresis
comparator

Solar
cell

M
Cin

L

Super
capacitor

D

Energy
buffer

Input stage

DC/DC
converter

Vout

Output
stage

Figure 2.3: System diagram of a solar energy harvester implementation [20].

with same technology as the PV cell), a Fractional Open-Circuit (FOC) block and a hysteresis
comparator. Pilot cell is exposed to the same sunlight radiant as PV cell and generates reference
open-circuit voltage VOC . The FOC block is used to calculate MPP for the optimum loading conditions. Sophisticated algorithm using digital signal processing is one option to ﬁnd VMPP when
power budget is efﬁcient [21]. Instead, a linear approximation of VMPP is usually employed for
low power consumption where VMPP can be expressed as

VMPP = KFOC · VOC ,

(2.2)

where KFOC is a constant from 0.71 to 0.78 depending on irradiance condition. Afterward, VMPP
is compared with the actual output condition of PV cell and a hysteresis comparator controls the
switching of transistor M which keeps loading condition at MPP. For battery-less scenario, the
15

100
90

Efficiency (%)

80
70
60
50
40
30
20
10

[22]
[23]
[24]
[25]

0
0.1

1

10

100

Input solar power (mW)

Figure 2.4: Efﬁciency of solar harvesting technique.
output energy can be stored in Energy buffer on an electrochemical double layer capacitor which
is also known as supercapacitor. If output voltage level is not appropriate to power sensor circuits,
a standard DC/DC converter can be added for voltage level adjustment.
According to Table 1.4, solar energy harvesting is the most efﬁcient approach compared with
other harvesting techniques. However, a great challenge of solar energy harvester is tracking VMPP
when the irradiance of light is varying. The MPP tracker in Fig. 2.3 cannot consume too much
power which otherwise reduces conversion efﬁciency. Figure 2.4 summarizes several recent research works for solar energy harvesting circuit where the conversion efﬁciency is compared for
input solar power ranging from µW to mW [22, 23, 24, 25]. As shown in Fig. 2.4, the efﬁciency is
usually reduced with the decrease of input energy level. With optimization, solar energy harvester
can provide sufﬁcient energy for sensor subsystem. However, the drawback is that the availability
of sunlight cannot always be guaranteed. Large capacitor is usually required to store energy for
weak/no light exposure situations.
16

2.2

Thermoelectric conversion

The history of ThermoElectric Generator (TEG) effect can be dated back to the discovery of Seebeck effect [14]. For basic thermoelectric circuit, two different conductors are jointed together at
one junction with temperature THJ . At the other end, the loop is open with temperature TCJ . Due
to the temperature gradient between two ends, an open-circuit voltage VOC can be generated from
Seebeck effect, which is given by

VOC = αab · (THJ − TCJ ),

(2.3)

where αab = αa − αb is Seebeck coefﬁcient difference between two conductors. When an electrical load is connected between the outputs, temperature gradient can be converted to electricity
power and such device is called thermocouple. For general thermoelectric devices, thermocouples
are made of p- and n-type semiconductor materials instead of metal conductors, whose structure
is shown in Fig. 2.5(a). For p-type semiconductor, the Seebeck coefﬁcient αp is positive while
for n-type semiconductor, the Seebeck coefﬁcient αn is negative. Both legs of semiconductors are
jointed at top surface by a metal conductor and a loading resistance RL is connected between two
legs at bottom surface. Assuming heat ﬂow is in the direction from QH to QC , an output current
IL ﬂowing through RL can be generated as

IL =

αpn · THJ − TCJ
,
Rin + RL

(2.4)

where αpn is Seebeck coefﬁcient difference between n- and p-type materials and Rin is the internal
electrical resistance of thermocouple which is given by
17

18
Figure 2.5: (a) basic structure of a semiconductor thermoelectric couple; (b) output power characteristic from a TEG [14].
(b)
RL (Ω)
0
0

5

10

15

20

25

30

Model with thermal resistor
5

Power (mW)

10
15
20
25

(a)
RL
QC

TC
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

TTEG

000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

TCJ
T

p
THJ

Cold junction

n

000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

Hot junction

TH
QH

difference ∆TTEG across two legs is lower than the gradient ∆T as shown in Fig. 2.5(a) [14]. For
respectively. Due to the ﬁnite thermal conductance of top and bottom plates, the temperature
where ρ is electrical resistivity, h and Aleg are the height and contact area of thermocouple leg
2·ρ·h
,
Rin =
Aleg

(2.5)

a single thermocouple, the output power at particular temperature ∆TTEG with loading resistor
RL can be expressed as
2
2
PL = αpn · ∆TTEG ·

RL
.
Rin + RL 2

(2.6)

The output power characteristic of a TEG implementation is plotted in Fig. 2.5(b) from [14].
Due to relatively small value of Rin , the optimum/maximal output power is found when RL is
around 5–10Ω. The standard structure of thermal harvesting circuit is presented in Fig. 2.6. Generally thermoelectric conversion can be modeled as a DC source as long as there is constant temperature gradient across TEG. In order to maximize conversion efﬁciency, load impedance is required
to match Rin . When temperature gradient is not large, the output from TEG becomes very low
although the available current might have values up to 100mA [14]. Therefore speciﬁc circuit technique can be used in Fig. 2.6 to increase output voltage for operating sensor circuits. But the loss in
DC/DC converter will reduce the total energy conversion efﬁciency for thermal harvesting circuit.
Table 2.1 summarizes the performance of several recent implementations for thermal harvesting
circuit. As indicated by Table 2.1, TEG technology can be a good choice for continuous operations
used for applications where a large temperature difference always exists, such as space-craft power
harvesting [26] or power recycling from exhaust waste steam. In addition, any warm-blooded an-

thermal
harvester
storage

Vin
DC/DC

pulse
load
matching
Figure 2.6: Circuit model for thermal harvester.
19

Vout

Table 2.1: Comparison for efﬁciency for thermal harvesting circuits.
Parameter

[28]

[29]

[30]

[31]

[32]

Process

0.35µm

0.35µm

0.13µm

0.35µm

0.18µm

Minimal input voltage

1V

600mV

20mV

25mV (35mV to startup)

200mV

Output voltage

1.75–4.3V

2V

1V regulated

1.8V regulated

1.2–1.5V

Peak efﬁciency

50%

70%

52%

58%

36%

imals can be the heat source respected to environmental temperature when a TEG is attached to
skin surface. In [27], the wristwatch is mentioned to be the ﬁrst practical application of TEG for
daily life.

2.3

Vibration excitation

Ambient vibration is one of main auxiliary energy sources and a large number of energy harvesters
based on vibrational excitation have been proposed or demonstrated at micro scale. Vibration powered generators are typically, although not exclusively, inertial spring and mass systems [33], where
an inertial mass is supported on a suspension and the vibration will cause a relative displacement
of the mass. With a suitable electromechanical transducer implemented, the relative displacement
can be transferred into electricity energy. In this section, three sub-types of the vibration system
with different mechanisms are introduced and compared.

2.3.1

electromagnetic

In conventional/macro scale engineering, electrical generators are overwhelmingly based on the
electromagnetic transduction which was ﬁrst discovered by Faraday in 1831. Using same principle,
a micro scale vibration based energy harvester can be designed whose mechanism is shown in
20

Fig. 2.7(a) [34]. A magnetic ﬁeld, B, is generated by a magnet close to the coil in ﬁeld. Assuming
the coil or the magnet is attached to an inertial mass, a relative displacement z(t) is generated when
ambient vibration occurs, which causes a change of ﬂux across the coil. Such phenomenon will
induce a voltage v(t) in the coil and thus drive a current of i(t) for load resistor R.
Figure 2.7(b) presents an implementation example of electromagnetic energy harvesting technique from [34]. The harvester consists of mass-spring on the top and pickup coil on the bottom.
A vertically polarized permanent magnet is attached to top membrane, which functions as both
magnetic source and inertial mass. The membrane is designed to resonant with ambient vibration
which generates a displacement for the magnet. Due to the planar gold coil attached on the bottom,
varying ﬂux volume is converted to electricity energy. In the implementation example, the dimension of harvester is around 5mm×5mm×1mm and measurement results indicate that the system
is capable of generating 0.3µW at an excitation frequency of 4MHz. For another implementation
example in [35], a DC/DC boost converter is added to electromagnetic harvester to increase conversion efﬁciency. By using a mini shaker vibrating at 40Hz, the maximal output power is measure
to be 35mW.
There are several design challenges for sensor nodes with electromagnetic energy harvesting

B

i(t)

m
2.5mm
150µm

m

R

v(t)

550µm

z(t)

planar Au coil

(a)

(b)

Figure 2.7: (a) principle of electromagnetic energy harvester; (b) cross-section of an implementation (not in scale) [34].
21

technique. First, a rapid change of magnetic ﬂux is essential to induce an observable output voltage.
Second, total variation of magnetic ﬂux is constrained by the dimension of sensor which results in
a low output voltage. Third, a permanent magnet or ferromagnetic materials are usually required
to generate magnetic ﬁeld, which is not compatible with standard CMOS or MEMS fabrication
process.

2.3.2

electrostatic

The principle of electrostatic energy harvesting technique can be explained with parallel-plate
capacitor. The parallel-plate capacitor is typically formed by two plates of conductors isolated by
an insulator. The relationship between voltage V and storage charge Q across the plates can be
expressed as
Q = C · V,

(2.7)

where C is capacitance in farads which depends on physical dimension properties as

C =ε·

A
,
d

(2.8)

where ε is the permittivity of material between plates, A is overlap area and d is the separation
distance between plates. The total energy stored in parallel-plate capacitor then becomes

E=

1
ε·A
d
·Q·V =
·V2 =
· Q2 .
2
2·d
2·ε·A

(2.9)

When voltage V , or initial charge Q, is hold constant and effective capacitance C is varied (due
to the change of d or A), the energy stored in capacitor will be changed according to equation (2.9),
which results in the energy conversion from mechanical movement to electricity. Generally, elec22

trostatic energy harvesters can be classiﬁed into three types according to different approaches to
change physical properties: (a) in-plane overlap; (b) in-plane gap closing; (c) out-of-plane gap
closing [36], whose basic topologies are shown in Fig. 2.8. The dark regions are ﬁxed by anchors
to the substrate, while the rest areas are released structures which are free to move. Plus, arrows
indicate the direction of vibration.
The architecture in Fig. 2.8(a) is referred as an in-plane overlap converter. When ambient vibration causes the gray area to move vertically, the total overlap area A from all interdigitated ﬁngers
is varied which leads to the variation of effective capacitance based on equation (2.8). Similarly
in Fig. 2.8(b), when vibration is horizontal, the equivalent separation distance d for all ﬁngers is
varied which also results in a changing capacitance. In Fig. 2.8(c), vibration direction is out of
the planar plate and effective capacitance can be modiﬁed by distance d. Due to equation (2.9),
changing geometry parameters generate electrical power from vibration signal.
Compared with electromagnetic harvester, electrostatic energy harvesting system is more compatible with CMOS or MEMS fabrication since there is no requirement for special component like
magnet or coil. However, additional power has to be provided for harvester circuit to initialize and
maintain voltage V or charge Q [in equation (2.9)] across the capacitor. In [37], an electrostatic

5-10 mm

5-10 mm

100 µm

(a)

2µm

(b)

(c)

Figure 2.8: Electrostatic energy harvester: (a) in-plane overlap (top view); (b) in-plane gap closing
(top view); (c) out-of-plane gap closing (side view) [36].
23

energy harvester is designed to generate 1.6µW output power when a constant 200Hz vibration
is provided. The energy gain is measured to be 6.9nJ/cycle when an average of 1.7nJ/cycle energy is provided to maintain the operation. In [38], the maximal energy gain is reported to be
2.869nJ/cycle when a 4.2V battery is used. The requirement of extra energy source becomes a
great challenge for energy harvesting sensor node because such energy is usually unavailable.
Electrostatic energy harvester might also have stability issue. When the vibration is too strong,
the plates can be stuck together and cannot move anymore. Finally, the harvester cannot deliver a
large amount of current while only a relatively high voltage (≥10V) can be generated. This leads
to additional circuit inserted to optimize the output power [33].

2.3.3

piezoelectric

The ﬁrst demonstration of piezoelectric effect was in 1880 by brothers Pierre Curie and Jacques
Curie [33]. When piezoelectric materials were subjected to mechanical strain, they would become
electrically polarized and the degree of polarization was proportional to applied strain. Such materials are widely available in several forms among single crystal, thin ﬁlm and polymeric material.
In energy harvesting system, the usage of piezoelectric material is not a recent idea but the piezoelectric electrical generators can only ﬁt into very low power applications, which is in mW level or
even lower. With the progress of the ultra-low power circuit design, it becomes feasible to apply
piezoelectric energy harvesting technique to wireless sensor system.
An equivalent circuit model for piezoelectric energy source is shown in Fig. 2.9(a) [39]. σin is
input mechanical strain signal, Lm represents the mass or inertia of material, Rb represents mechanical damping and Ck represents mechanical stiffness, n is the equivalent turn-ratio of transformation from mechanical side to electrical side, Cb is the output capacitor of piezoelectric material,
24

i is output current and V is output voltage. The amplitude of output voltage depends on material’s characteristics which can easily exceed 10V. However, the capability of current driving is
weak for piezoelectric material. The characteristics will also shift with age and temperature. Figure 2.9(b) demonstrates the interface circuit for an energy harvester using piezoelectric transducer.
The harvesting circuit consists of two stages. Block harvester can ﬁrst optimize the output from
piezoelectric transducer and perform AC/DC transformation. The generated energy can be stored
on capacitor. After that, a DC/DC converter is used to further adjust output voltage level to operate
sensor circuits.
The standard harvester circuit is plotted in Fig. 2.10. The piezoelectric transducer has been
model as an differential voltage source with capacitive coupling. In Fig. 2.10(a), a simple voltage
doubler is used to charge loading capacitor. In Fig. 2.10(b), a diode bridge is used to decouple the
ground connection between transducer and sensor circuits. In Fig. 2.10(c), a switching inductor
is added across transducer as the Synchronized Switch Harvesting on Inductor (SSHI) topology.
When the inductor is switched on/off properly, the output from transducer can be increased which
achieves a higher efﬁciency for harvester circuit.
After energy has been converted and stored on loading capacitor, the DC/DC converter in
Fig. 2.9 is used to generate a usable supply voltage/current. Depending on the initial voltage level

Lm

Rb

Ck

i

n

n
σin

Cb

mechanical

V

harvester
Cb

DC/DC
converter

electrical

(a)

(b)

Figure 2.9: (a) equivalent circuit model for piezoelectric energy harvester; (b) general architecture
of piezoelectric harvesting circuit [39].
25

on loading capacitor, either buck (step down), boost (step up) or buck-boost (step up/step down)
structure can be used. Typical DC/DC buck converter with a pMOS switch is shown in Fig. 2.11(a).
By controlling the duty cycle of Vctrl , an optimized Vout can be achieved with maximal conversion
efﬁciency. The buck-boost DC/DC converter shown in Fig. 2.11(b) works for both cases when Vrec
is lower or higher than Vout . By controlling Vctrl , an equivalent impedance can be achieved after
input terminal which generates a reasonable DC output. A buck-boost converter is suitable for low
excitation level and high efﬁciency applications.
Speciﬁcations of several implementation examples for piezoelectric harvesting circuit are listed
in Table 2.2. Note that for all implementations, a steady vibration signal is provided to transducer
at its resonant frequency. The conversion efﬁciency will drop dramatically when the vibration
source is unsteady or is not at the resonant frequency.
As an implementation example for short-term vibration, Fig. 2.12 presents an energy harvesting system powered by a piezoelectric igniter [47]. The igniter in Fig. 2.12(a) is widely used in

(a)

(b)

(c)

Figure 2.10: Harvester circuit: (a) doubler; (b) diode bridge; (c) SSHI.

I rec
Vrec

Iout

I rec

Vout

Vctrl

Vrec

(a)

I out
Vout

Vctrl
(b)

Figure 2.11: DC/DC conversion: (a) buck; (b) buck-boost [12].
26

Table 2.2: Comparison for efﬁciency for piezoelectric harvesting circuit.
source

method

resonant frequency

efﬁciency

maximal output power

[40]

DSSH

105.3Hz

40%

5.5mW

[41]

SSHI

1kHz

20.2%

<400µW

[42]

bias ﬂip

225Hz

87.5%

<70µW

[43]

synchronous bridge rectiﬁer

125Hz

50–70%

8µW

[44]

rectiﬁer

301Hz

64%

25µW

[45]

switched-inductor

100Hz

41.7%

30µW

[46]

adaptive feedback

250Hz

60%

300µW

Piezoelectric
pushbutton
Igniter

Ground wire

RF transmitter
@ 433MHz

Positive live wire
Pushbutton

Full-wave
recfiter
50mm

Storage
capacitor
HT-12E
MAX666
12-bit address/data cncoder
linear regulator

(a)

(b)

Figure 2.12: (a) Piezoelectric pushbutton; (b) an implementation of an RF transmission sensor
powered by a piezoelectric igniter [47].
experiments to generate high voltage with very low input mechanical strain. When the piezoelectric pushbutton is pressed, output electrical energy is used for RF transmission. As shown in
Fig. 2.12(b), the whole transmitter system is mounted on a Printed Circuit Board (PCB) with the
total area of 2,500mm2 . The experiment results indicate that 67.61nJ electrical energy can be scavenged when the button is pushed and it is sufﬁcient to transmit two complete 12-bit digital word
frame data through RF front-end. To maintain continuous operation, the energy from piezoelectric
27

Table 2.3: Comparison of three vibration energy harvesting techniques.
Type

Advantage

Disadvantage
• bulky size: magnetic and pickup coil

Electromagnetic

• no external voltage source

• difﬁcult to integrate with CMOS/MEMS
• low generated voltage

• no need for smart material

• mechanical constrains limited
• capacitive output with limited current

• no external voltage source

• brittle material

• sufﬁcient high output voltage

• charge leakage

• compatible with CMOS/MEMS

Piezoelectric

• compatible with CMOS/MEMS
• sufﬁcient high output voltage

Electrostatic

• external voltage or charge source

• poor coupling in piezo-ﬁlm

pushbutton must guaranteed.

2.3.4

comparison and remark

Three most popular energy harvest techniques based on vibration energy source are introduced
with principles and implementation examples. Table 2.3 summarizes both advantages and disadvantages for three approaches for comparison. More details can be found in [48]. From Table 2.3,
piezoelectric approach is more suitable for energy harvesting sensor system because (a) it is compatible with CMOS or MEMS fabrication and (b) it does not require additional energy/setup for
initialization. However, a continuous vibration source is always required to power continuous
operation.

2.4

Radio frequency radiation

Under normal conditions, the typical power density of ambient RF signal is measured to be less
than 1µW/cm2 as listed in Table 1.4. Considering low conversion efﬁciency, it is difﬁcult to power
28

any electronic circuits, especially with small scale antenna. Therefore, a certain level of power is
usually delivered to sensor intentionally in RF energy harvesting system. Such technique is widely
used in applications of Radio Frequency Identiﬁcation (RFID) and WSN. In this section, several
design issues for RF powered system are discussed.
In Ultra High Frequency (UHF) or microwave RFID system, reading distance is limited by the
available energy at transponder (sensor) from reader, which is usually greater than 1m. These systems can be operated at different frequency as 868MHz/2.5GHz in Europe and 915MHz/5.8GHz
in USA. In order to evaluate the energy available from reader to sensor, the free space path loss αF
respect to reading distance d is ﬁrst calculated as

αF (dB) = 10 · log10 (

4·π·d·f 2
)
c

4·π
),
= 20 · log10 (d) + 20 · log10 (f ) + 20 · log10 (
c

(2.10)

where f is the frequency of RF carrier signal and c is the speed of light. After applying numerical
values into equation (2.10) and considering GR and GT as the antenna’s gains of reader and sensor,
the total path loss can be expressed as

αF (dB) = −147.6 + 20 · log10 (d) + 20 · log10 (f ) − 10 · log10 (GR ) − 10 · log10 (GT ). (2.11)

Since the maximum transmitted power allowed by Federal Communications Commission (FCC)
for 915MHz and 2.45GHz band is 36dBm (4W) EIRP [49], the theoretical energy available to sensor is plotted in Fig. 2.13, where the gain of antenna is assumed to be 1.64 (dipole) for sensor and
1 (isotropic emitter) for reader. At the distance of 10m, the available power is shown to drop dramatically to −13dBm (50µW) at the frequency of 915MHz, and even as low as −22dBm (6µW)
for 2.45GHz. When transmission occurs in lossier environments, the attenuation of RF signal
29

becomes even serious which poses signiﬁcant limitation of RF energy harvesting technique.
Another important issue for RF powered system is the design of antenna. As the interface

30
25
20

Power (dBm)

15
10
5
0
−5
−10
−15
−20
−25
0

2

4

6

8

10

8

10

Reading distance (m)

(a)
30
25
20

Power (dBm)

15
10
5
0
−5
−10
−15
−20
−25
0

2

4

6

Reading distance (m)

(b)
Figure 2.13: Path loss for RF signal at (a) 915MHz; (b) 2.45GHz.
30

Table 2.4: Implementation examples for RF powering sensor system.
source

[50]

[51]

[52]

[53]

[54]

process

0.25µm

0.30µm

0.35µm

0.5µm

0.25µm

maximal efﬁciency

60%

33%

24%

28%

11%

minimal power consumption

5.5µW

40µW

100µW

16.7µW

60µW

distance

15m

2m

4.3m

4.5m

1.7m

with air, the structure, material and size of antenna will greatly affect the energy scavenged from
ambient RF energy source. Dipole or meander antenna is among the most general structures to pick
up RF energy, which usually has comparable size with the wavelength of RF carrier signal. The
normal size of antenna is half or quarter of the wavelength, which results in 3–6cm for 2.45GHz
signal or 8–16cm for 915MHz signal.
For small scale energy harvesting sensor, antenna will take most part of area compared with
sensor circuits. Therefore, the trade off between power scavenged and sensor’s dimension can be
found in Fig. 2.13. If a higher frequency is used for RF carrier, the size of antenna can be made
smaller due to smaller wavelength. However, path loss will be more serious which reduces the
available power delivered to sensor. Otherwise, if a lower frequency is used, attenuation will be
reduced at the cost of larger antenna scale. A few implementation examples of wireless sensors
powered by RF signal are listed in Table 2.4 with their main speciﬁcations and efﬁciency. Similar
to piezoelectric energy harvesting technique, continuous operation can be achieved as long as
auxiliary RF energy source can be guaranteed.

31

Chapter 3
Challenge for Self-Powered Sensor
The performances of different energy harvesting techniques have been evaluated in last chapter.
When auxiliary energy source is sufﬁcient, each harvesting technique can easily activate sensor
subsystem. In this chapter, the limitation of energy harvesting sensor is discussed by the case study
of long-term ambient vibration monitoring. For this speciﬁc application, none of those auxiliary
energy sources is sufﬁcient and the only signal can be scavenged from is input strain signal itself.
After analyzing available energy level and power/energy budget, it is readily to show that conventional MCU based architecture cannot be directly employed with self-powered sensor. Therefore a
hybrid topology is proposed for long-term autonomous monitoring.

3.1

Energy analysis for self-powered sensing

In order to demonstrate the system and circuit design for self-powered sensor, a speciﬁc application
of long-term ambient vibration monitoring is discussed in this section. It is a typical example to
address the challenges for self-powered sensing because all other solutions are not applicable.
For vibration monitoring, sensor is usually deployed or attached together with certain structure to
32

record the strain history applied to it. Such sensor can be used for fatigue prediction for SHM
and BIM. The requirements of the long-term vibration monitoring poses signiﬁcant challenges in
energy harvesting:
1. In SHM or BIM applications, sensor nodes are always embedded within structure. Therefore
there is no chance for sensor to be exposed under sunlight. Solar energy harvesting is not an option.
2. The output power from thermal harvesting circuit is limited by small scale sensor. The general rules of thermoelectric conversion follow the trends shown in Fig. 3.1. Data in Fig. 3.1(a) are
measured from sintered bismuth telluride powder thermoelements which indicate the typical output characteristic versus temperature difference [28]. The output power of a 1cm2 Bi2 Te3 –Sb2 Te3
thermoelectric generator is also plotted in Fig. 3.1(b) as the function of its physical size [55]. From
Fig. 3.1, it is readily to show that small scale sensor node results in low output power as well as
small temperature gradient which further reduced available power.
3. For RF harvesting circuit, voltage multiplier or rectiﬁer is usually used to convert auxiliary
RF signal into a reasonable DC level to activate sensor system [56]. However, for long-term
monitoring, no steady RF energy source can be always provided to the embedded sensor. Ambient
RF source could be one option, but as shown in Fig. 3.2, the efﬁciency of rectiﬁer is greatly
dependent on input energy level and frequency [56]. When ambient RF energy is very weak, the
output from harvesting circuit is quite limited.
4. Similar to RF energy harvesting, there is also no steady vibration source around the embedded sensor for long-term monitoring. The only available vibration is the input strain signal
itself. However, such vibration is unpredictable whose frequency is within infrasonic region from
DC to 20Hz. When vibration source is not in steady case, the available output energy level from
piezoelectric transducer can be reduced dramatically. Figure 3.3 shows measured results from a
33

piezoelectric disk shaking at various frequency [57]. It is demonstrated that transducer can only
deliver reasonable energy when steady vibration is at resonance frequency. Therefore, when vibra-

9

Output power (mW)

8
7
6
5
4
3
2
1
0
0

20

40

60

80

100

6

8

10

o

∆T ( C)

(a)
22
20

Output power (µW)

18
16
14
12
10
8
6
4
2
0
0

2

4

Thermoelectric leg length (mm)

(b)
Figure 3.1: Thermoelectric conversion efﬁciency: (a) versus temperature gradient [28]; (b) versus
size [55].
34

tion is coming from unpredictable ambient vibration in the case of long-term monitoring, output
energy could become very weak which poses a great challenge of energy harvesting.
Therefore the only available energy source for long-term SHM and BIM is the vibration sig45

RF to DC Efficiency (%)

40

9dBm = 7.94mW
-3dBm = 0.50mW

35
30
25
20
15
10
5
0
100

101

102

103

Frequency (MHz)

Figure 3.2: RF conversion efﬁciency versus input level and frequency [56].
40

Output power (µW)

35
30
25
20
15
10
5
0
0

500

1000

1500

Frequency (Hz)

Figure 3.3: Output energy from piezoelectric transducer versus frequency [57].
35

nal being sensed itself. The energy level from ambient vibration is ﬁrst analyzed. In Fig. 3.4,
three general loading types in SHM are compared, which are earthquake, wind and trafﬁc. The
earthquake data are quoted from 32 different earthquake activities and the data for wind and trafﬁc
are obtained from literatures [58]. Maximal theoretical harvestable energy is plotted in Fig. 3.4(a)
where the results are categorized by different structure types under various loading conditions [58].
The energy level plotted is the theoretical value from a 5cm3 vibration scavenger where all available kinetic energy is assumed to be converted into electrical energy. It should be noted that several
points of earthquake column are for those tremendous earthquake events which are not helpful for
any energy harvesting. Also, total energy instead of average power is plotted which implies that
no continuous energy is provided. For wind-loading cases, the energy is calculated for a period of
30s; for earthquake and trafﬁc loading cases, the loading durations range from 30 to 60s.
In [58], actual energy can be harvested from vibration sources in Fig. 3.4(a) is also analyzed.
A piezoelectric bimorph (the volume is 5cm3 ) is used as the energy scavenger whose resonant frequency is approximately 7Hz. However, dynamic loadings for most civil structure have extensive
vibration component at around 1Hz. Thus the converted energy as shown in Fig. 3.4(b) becomes
much lower than theoretical value in Fig. 3.4(a) [58]. The natural frequency of many mediumspan bridges is around 5Hz which is close to bimorph’s resonant frequency, thus about 10 times
less energy can be scavenged than the theoretical values. For cases of tall buildings, whose resonant frequency is under 0.5Hz, very little energy can be coupled from structure to scavenger which
results in approximately 104 times less energy to be harvested. For earthquake cases, converted
electrical energy is about 30 times smaller on average since the dominant excitation frequency of
earthquake ranges from 0.2Hz to 10Hz.
For situations of in-vivo bio-mechanical implants, the strain levels of median nerve are listed as
36

100

Earthquake
Wind
Traffic

Energy (mJ)

10

1

0.1

Bridges

Tall buildings

Earthquakes

(a)
10
10

Energy (mJ)

10
10

2
1

Eathquake
Wind
Traffic

0

-1

10
10
10

-2
-3
-4

10-5

Bridges

Tall buildings

Earthquakes

(b)
Figure 3.4: (a) theoretical vibration energy for various structures and loading conditions; (b) energy
harvested from a piezoelectric bimorph from the energy sources in (a) [58].

an example in Table 3.1 [59]. For different motions of joint, strain levels in percent are measured.
Typically, the strain levels for in-vivo bio-mechanical structures are in the order of 100–100µε (the
strain producing a deformation of one part per million), which can be converted to electrical energy
37

Table 3.1: Strain of median nerve.
Motion of joint

Strain at wrist

Strain at elbow

Fingers

19%

10.3%

Wrist

3.8%

3.3%

Forearm

2.1%

1.0%

Elbow

3.7%

N/A

Shoulder

7.5%

13.3%

Table 3.2: Power and energy budgets reported in literature for low power operations.
Operation

Budget

1-bit analog-digital (A/D) conversion

50fJ[60]

Write 1 bit to non-volatile memory

25pJ[61]

Digital signal processing

100µW@100MHz[62]

1024-point 16-bit FFT

90nW@164Hz[63]

70nm serial multiplier

20µW@100kHz[64]

Sleep mode

1µW[65]

Pin leakage

2.2nW[66]

in the level of µW. From Fig. 3.4 and Table 3.1, the power/energy budget from ambient vibration
or motion is as low as a couple of µW in SHM or BIM.
Several standard operations for signal processing or data sampling are listed in Table 3.2 with
its up-to-date power consumption. In Fig. 3.5, the power/energy budget is compared with the
energy scavenged from all the implementations presented in chapter 2. No matter which energy
harvesting technique is used, the scavenged energy is reduced with the decrease of input power
level. For solar, thermal and RF energy harvesting, output power level will eventually fall to zero
for long-term monitoring. For piezoelectric harvesting with input power level as low as a few µW,
scavenged energy is not sufﬁcient to power any of operations listed in Fig. 3.5. Therefore, conven38

Output power level (mW)

10

2
Solar
Thermal
Piezoelectric
RF

101

10

0

10-1

digital signal processing
serial multiplier

10-2

MCU active mode
analog-to-digital converter

decrease to zero

10

MCU sleep mode

-3
10

-3

10

10-1

-2

100

10

1

102

Input power level (mW)

Figure 3.5: Power budget.
tional MCU based architecture for senor subsystem is not applicable to self-powered sensing and
a different system architecture is required.

3.2

Long-term fatigue prediction

The idea to power sensor with input strain signal has been veriﬁed by two implementations reported
recently. In [67], an autonomous sensor is designed to measure trafﬁc ﬂow where the sensor is
powered by short duration vibration generated from moving vehicles. Once an automobile passes
over the sensor, an RF pulse can be transmitted for event counting. In [68], another sensor node
has been designed to be powered by moving vehicles. The energy harvesting circuit can power
the sensor to record temperature history. In both cases, the function of sensor has been simpliﬁed
due to limited energy budget. In the rest of this dissertation, a more sophisticated sensor system is
proposed by different architecture for long-term fatigue monitoring.
39

Fatigue is the progressive and localized structural damage that occurs when a material is subjected to cyclic loading [69]. For most civilian building structures under their daily vibration
loading (wind or trafﬁc), the lack of fatigue monitoring might lead to serious problems such as
the collapse of I-35W bridge in 2007. Likewise for bio-mechanical implants (knee- or hip- implants) monitoring, the lack of fatigue prediction results in an unnecessary replacement surgery
or an unexpected failure of implants. By 2030, the cases of primary hip arthroplasty in USA are
expected to double to 0.5 million and the cases of knee arthroplasty will grow by about 7 fold to
3.5 million [70]. Therefore, the usage of fatigue monitoring can bring much convenience and cost
saving.
For long-term (high cycle) fatigue prediction, material performance is commonly characterized
by an S-N curve which is plotted with the magnitude of strain level (si ) against total cycles to
failure (Ni ) in Fig. 3.6(a) [69]. The S-N curve is generated based on tests for each sample of
material where a regular sinusoidal strain signal is applied by a testing machine and the number of
cycles for the material to fail is counted. Intuitively, material can sustain more loading cycles before
failure for strain signal with smaller magnitude. To predict the fatigue procedure for material under

s1
Strain

Stain

(s1,N 1)
(s2,N2)

s2
s3

(s3,N3)

Life (cycle)

Time

(a)

(b)

Figure 3.6: Fatigue monitoring: (a) S-N curve; (b) loading history of strain signal [69].
40

various loading conditions, Miner’s rule, also known as Palmgren-Miner linear damage hypothesis,
is widely used which can be expressed as
k
i=1

ni
= C,
Ni

(3.1)

where C is experimentally found between 0.7 and 2.2 (usually assumed to be 1), k is the number
of magnitude levels for strain signal (k = 3 as shown in Fig. 3.6), Ni is the number of cycles to
failure for each level from Fig. 3.6(a) and ni is the actual number of cycles when strain signal
exceeds the particular level, which is circled in Fig. 3.6(b). For prediction, accumulated ni of each
level is recorded and the material is considered to fail when equation (3.1) is satisﬁed. For fatigue
monitoring, sensor node is required to record the accumulative cycles for each strain level.

3.3

Hybrid energy harvesting topology

In order to achieve long-term fatigue monitoring by using self-powered topology, a novel hybrid
energy harvesting technique is introduced in this section.
Assuming the available energy from environment is in several µW level, it has been already
pointed out that such energy level is not sufﬁcient to activate data sampling and signal processing operations in Fig. 3.7(a). Therefore, self-powered sensor is proposed with a hybrid topology
plotted in Fig. 3.7(b), where MCU based architecture is replaced by analog signal processor.
The sensor has been divided into two parts, each of which can be powered under different operation mode. For long-term continuous operation, the sensor is working in self-powered sensing
mode as shown in Fig. 3.8(a). The sensor is powered with µW ambient vibration signal being
monitored from the surface and only the analog signal processor in Fig. 3.7(b) is activated. Once
41

vibration occurs, the sensor should recover from sleep mode and perform required operations before strain signal vanishes. For example, the sensor should record accumulative period for strain
signal exceeding particular level based on equation (3.1), and keep current results until next vibration cycle arrives. The processor is required to be ultra-low power and non-volatile (details
provided in chapter 4).
During data interrogating mode shown in Fig. 3.8(b), an auxiliary RF signal is provided by
an external reading device to activate other circuit blocks within the sensor such as ADC, digital
baseband and RF transceiver in Fig. 3.7(b). With additional power, the sensor should response to

ʅt

ŶǀŝƌŽŶŵĞŶƚ



Dh
DĞŵŽƌǇ

Z& ƚƌĂŶƐĐĞŝǀĞƌ

ƚƌĂŶƐĚƵĐĞƌ

ŶĞƌŐǇ ŚĂƌǀĞƐƚĞƌͬƐƚŽƌĂŐĞ

(a)



ŶĞƌŐǇ ŚĂƌǀĞƐƚĞƌ

ŶĂůŽŐ ƐŝŐŶĂů
ƉƌŽĐĞƐƐŽƌ

Z& ƚƌĂŶƐĐĞŝǀĞƌ

ƚƌĂŶƐĚƵĐĞƌ

ʅt

(b)
Figure 3.7: Comparison between (a) MCU based sensor and (b) self-powered sensor.
42

RF signal

strain signal

monitor
Embedded
sensor
propagate
from surface

uplink
&
power

power

(a)

downlink
Embedded
sensor

(b)

Figure 3.8: Proposed hybrid energy harvesting approach: (a) self-powered sensing mode (powered
by ambient vibration signal being sensed; (b) data interrogating mode (powered by RF signal).
interrogations from reader, sample the data stored in analog processor and transmit results back
through RF link. Since data interrogating is not required to be continuous, all power-hungry operations can be located in the right half of sensor [Fig. 3.7(b)] to reduce power consumption during
self-powered sensing mode. By using proposed hybrid energy harvesting topology, a self-powered
sensing system can be achieved for both long-term ambient vibration monitoring and wireless data
accessing.

43

Chapter 4
Ultra-Low Power Computation and
Non-Volatile Storage
The applications for long-term ambient vibration monitoring pose great challenges on the design
of self-powered sensor system. As the replacement of ADC, MCU and memory, analog signal
processor should sample, compute and record signal within limited power/energy budget from environmental vibration. In this chapter, an ultra-low power signal processing approach is proposed
based on a controllable hot electron injection on FG transistor when interfaced with the piezoelectric transducer. Plus, a modiﬁed FG injection circuit is proposed to eliminate nonlinear effects,
which achieves a well-controlled injection rate.

4.1

Floating-gate based analog signal processor

The proposed signal processing and storage unit is based on hot electron injection procedure on a
FG transistor. The basic knowledge of FG transistor is given in this section and the principle of
piezoelectric induced HEI procedure is explained. Finally, a general architecture for a controllable
44

injection procedure is proposed for detecting, computing and recording different characteristics of
input strain signal.

4.1.1

ﬂoating-gate transistor

Firstly introduced in digital memory blocks such as EEPROM, ﬂoating-gate technique is increasingly adopted in analog circuit design recently [71, 72, 73]. A ﬂoating-gate transistor is a MetalOxide-Semiconductor Field Effect Transistor (MOSFET) whose layout structure is presented in
Fig. 4.1 (pMOS as an example). The polysilicon gate, node Vfg , is formed by layer poly1 which
is completely surrounded by silicon-dioxide (SiO2 ) in a standard CMOS fabrication process. Capacitor Cfg is formed by poly1-SiO2 -poly2 which makes gate node “ﬂoating.” Due to the high
quality insulation of SiO2 , any charge on node Vfg can be retained for a long interval of time (>8
years) [74]. The charge on Vfg can be modiﬁed with two different approaches which are FowlerNordheim (FN) tunneling and hot electron injection. As shown in Fig. 4.1, a small capacitor Ctun
is formed by the overlap between layer n+ and poly1. In order to remove electrons, a high voltage (>15V) can be applied to Vtun to activate quantum mechanism where a tunneling current ﬂow
Vfg
Cfg
Vs

Vd

Ctun

Vcg

Vtun

poly1

p+

n-well

poly2

n+

cc

Figure 4.1: Layout structure for a pMOS ﬂoating-gate transistor with tunneling port.
45

Control-gate

hot
electrons

3.2eV

EC-Si

Floating-gate

SiO2

EV-Si

electron

Source

hole

E C-SiO 2

Drain

Depletion

SiO2

Si

n-well
EV-SiO 2
Gate

(a)

t ox

Drain

(b)

Figure 4.2: (a) illustration of IHEI process in a pMOS FG transistor; (b) illustration of IHEI using
an energy band diagram.
will be generated to let electrons escape from FG node.
For ﬂoating-gate transistors, impact-ionized hot electron injection can be used to add electrons
onto FG node. Figure 4.2(a) shows the cross section of a pMOS FG transistor which is used to
illustrate the mechanism of HEI. Hot electron injection on a pMOS FG transistor occurs when a
high electric ﬁeld is formed at drain-to-channel depletion region. Due to the high electric ﬁeld
between Vs and Vd , the holes, which are the primary carriers in pMOS transistor, gain signiﬁcant
energy to dislodge electrons by impact ionization [see Fig. 4.2(a)]. The released hot electrons can
be accelerated toward channel region to gain kinetic energy. When their kinetic energy exceeds
silicon and silicon-dioxide barrier (>3.2eV), and if the momentum vector is correctly oriented
towards the Si-SiO2 barrier, hot electrons can be successfully injected into the oxide. The injection
procedure is also shown by using an energy band diagram in Fig. 4.2(b). As more electrons are
injected onto ﬂoating-gate node, voltage Vfg decreases.

46

4.1.2

piezoelectricity driven hot electron injection

One disadvantage of using hot electron injection as a computational medium is that it requires a
large voltage for operation. For example, in a 0.5-µm standard CMOS process, a drain-to-source
voltage greater than 4.1V is required to trigger HEI for a pMOS transistor. In normal circuit design,
such high voltage usually results in high power consumption. However, for long-term self-powered
strain monitoring, it is convenient to generate a high voltage with the piezoelectric transducer for
energy harvesting. As mentioned in chapter 2, piezoelectric materials are capable of generating
large voltage (>10V), though with limited current driving capability(<1µA). Fortunately, limited
current driving capability is not a problem for HEI since it has been shown that when FG pMOS
transistor is biased in weak inversion region, the injection efﬁciency (ratio of injection current and
source/drain current) is practically constant for different values of source current [75]. This implies
hot electron injection can be operated at ultra-low current where even piezoelectric transducers can
be used to drive the procedure.
The principle of piezoelectricity driven HEI is shown in Fig. 4.3(a), where a piezoelectric transducer converts mechanical energy into electrical form. The generated energy is then used to drive
a constant current source Is and the ﬂoating-gate pMOS transistor. Is is used to control injection
procedure which turns out to be a positive feedback process otherwise. During injection, Vfg keeps
decreasing when more electrons (e− ) are injected onto ﬂoating-gate, which further increases the
source-to-drain current through pMOS transistor. The increment of current also increases the probability of impact ionization and then increases hot electron injection current. If left uncontrolled,
HEI will lead to the breakdown of pMOS transistor.
As shown in Fig. 4.3(a), the ﬂoating-gate voltage, denoted by Vfg , is determined by control-gate
voltage Vcg and tunneling voltage Vtun through capacitive coupling. For Cfg , the respective plates
47

+

Vpiezo

Is
Cfg

e−

Mechanical
load

Cgs

Piezoelectric
transducer

Vcg
Vtun

Is

Vs

Vcg

Vfg

Vtun

C fg

I inj

(a)

ro

Ctun
Vfg

Ctun

Id

−
Vd (Vpiezo)

(b)

Figure 4.3: (a) schematic of a piezoelectricity driven ﬂoating-gate injector; (b) equivalent circuit
model of (a).

of capacitor are formed by polysilicon layers, whereas Ctun is implemented using the overlap between ploysilicon and active region (shown in Fig. 4.1). For analysis presented in this section,
both Vcg and Vtun are assumed to be constant and drain-to-source voltage of pMOS transistor is
assumed to be properly initialized to a predetermined value Vs0 for activating hot electron injection. Under these conditions, current source Is drives the source node of pMOS transistor such that
it creates a sufﬁciently high electric ﬁeld at drain-to-channel region to trigger injection process. As
hot electrons are injected onto the ﬂoating-gate node, potential of Vfg decreases resulting in the
decrease of source voltage. To understand the dynamics of circuit, an empirical model for injection procedure is combined with the circuit model of pMOS transistor and the equivalent circuit is
shown in Fig. 4.3(b). In Fig. 4.3(b), Is denotes source current, Id is drain current, Iinj is injection
current, ro is the output resistance of pMOS transistor, Vs,d is source and drain voltage, Cfg is
ﬂoating-gate capacitance, Ctun is tunneling capacitance and Cgs is gate-to-source (bulk) capacitance. It is important to note that the values of currents, ro and Cgs are dependent on biasing
conditions and should not be confused with those of small signal models. A simpliﬁed injection
48

current model [75] is used for this analysis which is given by

Iinj = β · Is · exp

Vs − Vd
Vinj

(4.1)

,

where β and Vinj are injection parameters depending on transistor size and process. The current
source Is in Fig. 4.3(b) also ensures that the ﬂoating-gate transistor is biased in weak inversion
region. For source-to-drain voltage Vds > 200mV, Ids can be expressed as [76]
Vfg
Ids = I0 · exp −
n · UT

Vs
UT

exp

,

(4.2)

where I0 is characteristic current, Vfg and Vs are ﬂoating-gate voltage and source voltage respectively, n is slope factor [76] and UT is thermal voltage (26mV at 300K). To derive the response of
Vs , all Nodal equations for the equivalent circuit in Fig. 4.3(b) are ﬁrst evaluated. If Vfg is properly
initialized, the total charge Qfg on ﬂoating-gate node can be expressed as

Qfg = Cfg · Vfg − Vcg + Ctun · Vfg − Vtun + Cgs · Vfg − Vs .

(4.3)

Assuming the drain is connected to ground for pMOS transistor and applying equation (4.1),
injection current Iinj modiﬁes the total charge according to

Iinj =

∂Qfg
∂t

= β · Is ·

Vs
Vinj

,

(4.4)

which is connected to equation (4.3) by
∂Qfg
∂t

= Ctot ·

∂Vfg
∂t
49

− Cgs ·

∂Vs
,
∂t

(4.5)

where Ctot = Cfg + Ctun + Cgs . Also applying current conservation at node Vs in Fig. 4.3(b)
will lead to
∂Vfg
Vs
∂Vs
Is = Iinj + Id +
+ Cgs ·
− Cgs ·
,
ro
∂t
∂t

(4.6)

where drain current Id is given by equation (4.2).
Equations (4.2)–(4.6) form a set of coupled differential equations whose closed-form solution
is difﬁcult to obtain. For simpliﬁcation, identity Is ≈ Id is assumed for following derivations,
which is reasonable since Iinj and the current changing across Cgs is only a small fraction of
Is . Because Is is ﬁxed by the current source, the expression of ﬂoating-gate voltage with other
parameters can be obtained from equation (4.2) as

Vfg = n · Vs − n · UT · ln

Is
I0

(4.7)

.

The combination of equations (4.4), (4.5) and (4.7) will lead to
∂Vs
Iinj = − n · Ctot − Cgs ·
.
∂t

(4.8)

Equating equation (4.8) with (4.1), the following equation is obtained

β · Is · exp

Vs
Vinj

= − n · Ctot − Cgs ·

∂Vs
.
∂t

(4.9)

The above equation can be further simpliﬁed as
∂Vs
= −K1 · exp (K2 · Vs ) ,
∂t
50

(4.10)

with
K1 =

β · Is
1
, K2 =
.
n · Ctot − Cgs
Vinj

Solving this ﬁrst-order differential equation leads to the following expression of Vs

Vs (t) = −

1
· ln K1 · K2 · t + exp −K2 · Vs0
K2

,

(4.11)

where Vs0 is the initial source voltage and t represents the total duration for hot electron injection
process. The plot of Vs as predicted by equation (4.11) is shown in Fig. 4.4(a) which also shows
the measured results obtained from a prototype fabricated in a 0.5-µm standard CMOS process.
The ﬁgure indicates that the mathematical model is in close agreement with measured results. In
particular, it can be seen in Fig. 4.4(a) that the response of hot electron injection consists of two
distinct regions of operation. The ﬁrst region is linear region [see inset in Fig. 4.4(a)] which occurs
under the condition t

exp(−K2 · Vs0 )/(K1 · K2 ) and equation (4.11) can be simpliﬁed as

Vs (t) = Vs0 − K1 · exp(K2 · Vs0 ) · t,

(4.12)

where the approximation ln(1 + x) ≈ x is used in derivation. Since Vs (t) is a linear function of
the injection duration t, the linear region is useful for monitoring short-term events (with an accumulative injection period less than 100s). However, for long-term fatigue prediction, the second
region of operation called “log-linear” region is of more importance.
Under the condition t

exp(−K2 · Vs0 )/(K1 · K2 ), equation (4.11) can be simpliﬁed to

Vs (t) = −

1
· ln(K1 · K2 · t),
K2
51

(4.13)

4.55

Linear

Output Voltage (V)

4.5

4.5
4.45

4.4

Log-linear

4.4

4.3
4.35

2

4

6

8
8

10
10

12
12x10

4

Measured
4.3

Model (K = 0.202× 10-22, K2 = 8.873)
1

100

10

104

2

Time (s)

(a)

Output Voltage (V)

4.55

4.5

4.45

4.4

4.35

I = 17n, K = 10.0604
2
I = 13n, K2 = 10.1420
I = 10n, K2 = 8.787
I = 8n, K = 9.2166
2

4.3
0
10

101

102

10

Time (s)

3

10

4

105

(b)
Figure 4.4: Responses of hot electron injection: (a) theoretical and measured response of the FG
injector plotted on a logarithmic scale and on a linear scale (inset); (b) responses measured at
various source current; (c) responses measured for using 8 prototypes fabricated in various runs;
(d) responses measured under different temperature conditions.
52

which shows that source voltage is a logarithmic function of total injection duration. The response
is illustrated in Fig. 4.4(a) using both measured and empirical models where the model is shown
to be valid for large durations (t > 103 s). In fact, the log-linear model is valid even beyond 105 s
Figure 4.4 (cont’d)
4.7
4.65

K2

10
4.55

8
4.5

6
2

Output Voltage (V)

4.6

4.45

4

4.4

2

4.35

0

4.3
100

1

2

3 4 5 6 7
Chip number (n)

101

102

8
103

Time (s)

10

4

(c)
4.7
4.65

10

4.55
9

4.5

8

2

Output Voltage (V)

4.6

4.45
4.4

6

4.35

5

K2 = 0.0108× T + 8.52
K2

7

Measured K2
Model

4.3
100

-10

0
10
20
30
o
Temperature ( C)

101

Increase T
40

102
Time (s)

(d)

53

103

104

where the injection current is as low as one single electron per second. This can be readily veriﬁed
from the measured response in Fig. 4.4(a) where the voltage change observed on ﬂoating-gate
node (with capacitor Cfg of 100fF) over a duration of 104 s is 20mV. Another interesting result that
can be seen from equation (4.13) is that the effect of Vs0 can be neglected when t is sufﬁciently
large, where Vs is only dependent on two constants, K1 and K2 . The slope of log-linear response
is, therefore, completely determined by the value of 1/K2 while K1 only introduces an offset. This
offset captures all the artifacts arising from biasing conditions, ambient temperature and fabrication
parameters. Thus, equation (4.13) also provides a model for compensating these artifacts using
a simple differential offset cancellation technique, where equation (4.13) can be written in its
differential form as
∆Vs (∆t) =

1
· ln
K2

t0
t0 + ∆t

,

(4.14)

where t0 denotes a reference injection time with respect to when the differential time interval ∆t is
measured. It can be readily seen from equation (4.14) that the differential operation is independent
of parameter K1 . However, for (4.14) to be useful, the robustness of parameter K2 still needs to
be addressed.
Several experiments have been conducted to quantify the robustness of parameter K2 to different biasing and mismatch conditions whose results are presented in Fig. 4.4(b)–(d). Figure 4.4(b)
shows the responses obtained from multiple injectors on the same chip that were biased with different current source Is . The mismatch in parameter K2 was calculated to be less than 10% for
a biasing current with variation greater than 100%. The result is encouraging since it implies that
the precision of current source is not critical for the operation of ﬂoating-gate injector.
Figure 4.4(c) shows the responses obtained from eight ﬂoating-gate injectors, where three of
them were measured from different prototypes fabricated in the same run and ﬁve of them were
54

measured from prototypes in different run. For these measurement, the mismatch in parameter K2
was calculated to be 4.3%. The results demonstrate that the response of injector is also robust to
fabricated related mismatch.
Figure 4.4(d) shows the responses of the injector measured over a temperature range from
−10o C to 40o C. Measured results show that K2 linearly varied with the temperature whose temperature coefﬁcient was measured to be 0.01V−1 K−1 . Parameter K2 , therefore, varies by 1V−1
for a temperature range of 100o C, showing that the injector’s response is robust to temperature
variations. Thus, the measured results summarized in Fig. 4.4(b)–(d) demonstrate that K2 is robust to variations in biasing/ambient conditions.

4.1.3

controllable injection procedure

The response for ﬂoating-gate hot electron injection has been evaluated in last subsection where a
log-linear relationship has been valuated between source voltage and accumulative injection duration. When HEI is controlled by a particular attribute of the signal of interest, the resultant source
voltage is able to reﬂect the corresponding characteristic. Moreover, the value of source voltage
remains constant due to the non-volatile FG transistor. Based on this principle, the analog processor for computation and storage for long-term self-powered sensing is described in this subsection
with the implementation example of level crossing algorithm.
As shown in Fig. 4.5, multiple FG transistors (M1-3 ) form the computation and storage block
which share same control-gate voltage Vcg . Compared with the injector in Fig. 4.3(a), switches
S1-3 are added to trigger the onset of hot electron injection procedure. The control signal is
generated according to different attributes of strain signal (strain level in this illustration). When
the switch is closed, a constant current Is is ﬂowing through FG pMOS transistor which activates
55

Vpiezo
Is
S1
Is1
Vcg

Is
S2

Vs1

Attribute
extractor

S3

Is2

M1

Is

Vs2

Is3

M2

Piezoelectric
transducer

Vs3
M3

L1
L2
L3

Vpiezo
t1
Is1
Vs1

t2

Vs1

t3

Is2
Vs2
Is3

Vs2
t4

t5

Vs3

Vs3

Figure 4.5: Illustration of ultra-low power signal processing using multiple FG injectors to achieve
level crossing algorithm (not in scale).

hot electron injection (assuming the initial source voltage of each transistor, Vs1-3 , have been
calibrated properly). To implement a level crossing algorithm introduced in section 3.2, the switch
for each injection channel is controlled according to input strain level. As shown in Fig. 4.5, switch
S1 is closed once the magnitude from Vpiezo exceeds L1 ; switch S2 is closed from L2 ; switch
S3 is closed from L3 . An illustrated input strain signal is generated from transducer as shown
in Fig. 4.5 and the corresponding source-to-drain currents Is1-3 are plotted. The currents start to
ﬂow at each circled time and remain zero otherwise. According to subsection 4.1.2, hot electron
injection occurs only in the highlighted period of time which can be expressed from equation (4.14)
56

as
1
∆V1 =
· ln
K2
1
∆V2 =
· ln
K2

t0
t0 + t1

1
∆V3 =
· ln
K2

t0
t0 + t4 + t5

t0
t0 + t2 + t3

(4.15)

Recall the Miner’s rule for fatigue monitoring in equation (3.1), the accumulative injection time
t1 , t2 + t3 and t4 + t5 can be mapped to ni respectively. Therefore, the source voltage drop on
each FG injector represents total number of cycles when input strain signal exceeds the particular level. When ﬂoating-gate injection channels are interfaced with piezoelectric transducer, the
voltage drops can record the statistics information for fatigue monitoring under Palmgren-Miner
linear damage hypothesis. Thus, an ultra-low power approach for self-powered strain monitoring
is achieve by controllable hot electron injection procedure.
The function of FG injection array can be further extended when another attribute extractor
is used. For example, the array can be used to record signal with different strain rate as long as
the switches are controlled based on the speed of signal, which is also of great importance for
fatigue prediction. The circuit design and implementation of the computation and storage block
are presented in chapter 5.

4.2

Linear ﬂoating-gate injection circuit

Hot electron injection is a nonlinear procedure to add electrons onto ﬂoating-gate node. When
properly biased in sub-threshold region, nonlinear effects result in the log-linear response which
has been discussed in previous section. Although log-linear response is important for long-term
57

application, a linear injection procedure can give more precise result for fatigue prediction. In this
section, a new circuit topology is invented by introducing a feedback loop into injection procedure
to eliminate nonlinearity.

4.2.1

circuit topology for linear injection

As a more general case of equation (4.1), the hot electron injection current, Iinj , can be expressed
as a function of transistor source current Is , source-to-drain voltage Vsd and gate-to-drain voltage
Vgd across the transistor. The expression can be generalized as

(4.16)

Iinj = f Is , Vsd , Vgd ,

where f (·) is an arbitrary function. To our knowledge, the exact form of the mathematical function f (·) is unknown and in literature many empirical models have been proposed to approximate
f (·). For example, the following model has been shown to be valid for all operating regions of a
transistor (weak, moderate and strong inversion) [77]:

Iinj = α · Is · exp

λ · Vsd
Vinj

· exp −

β
,
(Vgd + δ)2

(4.17)

where α, λ, β, δ and Vinj are parameters estimated from measured data. For the proposed linear
injection circuit, all voltage/current variables in equation (4.17) such as Is , Vsd and Vgd can be
held constant so that injection current Iinj can also remain constant according to equation (4.16).
The circuit topology is presented in Fig. 4.6(a) and its operational principle is explained with
Fig. 4.6(b)–(c).
In order to start injection procedure, switch Sp is open as shown in Fig. 4.6(b) which gener58

ates a negative feedback loop formed by opamp A and ﬂoating-gate transistor Mfg . The source
current is held constant at Iref which ensures that source-to-gate voltage Vsg remains constant
during injection. Opamp A ensures that source-to-drain voltage Vsd is held as the same as Vref
by appropriately adjusting control-gate voltage Vcg . Thus, according to equation (4.16), the injection current will stay constant when electrons are added onto ﬂoating-gate node. In order to stop
injection procedure, switch Sp is closed as shown in Fig. 4.6(c) which connects control-gate to
a reference potential (ground in this case). Similar to circuit in Fig. 4.3(a), the feedback loop is
disabled and injection result can be accessed at source terminal. The value of Vprog depends on
the ﬂoating-gate voltage Vfg which is determined by the injected charge and capacitor Cfg . The
formal analysis of the linear injection circuit is now presented by taking into account the effect of
opamp with ﬁnite gain and small signal parameters derived from the measurement results.
According to equation (4.16), injection current Iinj in Fig. 4.6(b) is given by

(4.18)

Iinj = f (Iref , Vs , Vfg ),

0
which can be linearized at injection current Iinj with small incremental source voltage ∆Vs and

I ref

I ref
Vprog

Vref

A
Sp
(a)

C fg

M fg Vref

A

Vcg Vfg
C fg
(b)

Iref
Vprog
e−
M fg Vref

∆V

A

C fg

Vprog
M fg

(c)

Figure 4.6: Proposed linear injection technique: (a) circuit architecture; (b) programming mode
when Sp is open; (c) biasing mode when Sp is closed.
59

small incremental ﬂoating-gate voltage ∆Vfg :
0
Iinj = Iinj + Gs · ∆Vs + Gfg · ∆Vfg ,

(4.19)

where Gs = δIinj /δVs denotes the injection transconductance parameter with respect to source
terminal and Gfg = δIinj /δVfg denotes the injection transconductance parameter with respect to
ﬂoating-gate terminal. Assuming the reference current is always held constant, the small signal
analysis of the pMOS current leads to

∆Iref = (gm + gd ) · ∆Vs − gm · ∆Vfg = 0,

(4.20)

where gm = δIref /δVg and gd = δIref /δVd are the transconductance small signal parameters
with respect to gate and drain terminals. Then ∆Vs ≈ ∆Vfg by given gm

gd for the pMOS

transistor in saturation region. Let the gain of opamp to be Av , the modiﬁed charge on FG node to
be ∆Q and the control-gate capacitance to be Cfg . Due to the feedback loop,

∆Vcg +

∆Q
∆Q
= −Av · ∆Vs +
= ∆Vfg ≈ ∆Vs ,
Cfg
Cfg

(4.21)

∆Q
,
Cfg · (1 + Av )

(4.22)

Thus,
∆Vs =

where Vs remains constant for inﬁnite Av . The charge variation ∆Q in (4.22) can be expressed as

∆Q = −Iinj · ∆t.

60

(4.23)

where ∆t is injection duration. Applying equations (4.21)–(4.23) into (4.19) and letting ∆t → 0,
the following ﬁrst-order differential equation is obtained:
dIinj
Gs + Gfg
+
· I = 0,
dt
Cfg · (1 + Av ) inj

(4.24)

(Gs + Gfg ) · t
0
Iinj = Iinj · exp −
.
Cfg · (1 + Av )

(4.25)

which leads to

Equation (4.25) shows that the ﬁnite gain of opamp will introduce temporal dependency in the
injection current which will generate an error during injection procedure. Given the duration of
injection procedure to be tp , the programming error can be computed as
∆Vfg
∆Iinj
(Gs + Gfg ) · tp
=
= exp −
.
Vfg
Iinj
Cfg · (1 + Av )

100

(4.26)

I

ref = 45nA
I
ref = 90nA

10-1

I

inj

(fA)

Fitting

10-2
4.6

4.65

4.7

4.75

4.8

4.85

4.9

4.95

5

V (V)
s

Figure 4.7: Measured injection current when the source voltage is varied.
61

Figure 4.7 shows the measured injection current when source voltage Vref was varied and all
the other parameters were held constant. Based on the measured data, the small signal parameter
Gs , Gfg can be estimated to range from 0.149fS to 2.316fS when reference current Iref is changed
between 45nA and 90nA. Hence, based on equation (4.26), an opamp with a small signal gain
of 40dB should be enough to achieve a linear injection resolution greater than 16-bit. However,
the accuracy will also be affected by the thermal noise while injecting electrons onto ﬂoatinggate capacitor. This error is approximately given by Vn ≈

K · T /CT , where CT is the total

capacitance (including parasitics) at ﬂoating-gate node. Cfg has been implemented to be 100fF
which leads to Vn ≈ 200µV. The measured results presented later indicate that thermal noise is
indeed the limiting factor to determine the accuracy of proposed linear injection circuit.
In order to evaluate the performance of the proposed circuit, a group of experiments were performed with the setup demonstrated in Fig. 4.8. According to equation (4.18) and (4.23), there
are three variables which can be used to control injection procedure: biasing current Iref is implemented with an tunable current reference, biasing voltage Vref is provided externally to set source
voltage for injection, and injection duration tp is precisely controlled by Field-Programmable Gate
Array (FPGA). Note that tunneling terminal Vtun is used for initialization. The injection result is

buffer
C fg
Iref

V ref
FPGA

A
Sp

Vs
M fg

Ctun
Vtun

Figure 4.8: Programming setup for linear injection architecture.
62

indicated by source voltage which can be measured through buffer at Vs .

4.2.2

programming range

The ﬁrst set of experiment is to measure the output range of linear injection circuit. Before the
injection, supply voltage Vdd was ramped up to 6.5V to guarantee there was sufﬁcient output
range for source voltage Vs . Switch Sp in Fig. 4.8 was ﬁrst closed and Vs was set to a voltage
greater than 4.1V by using FN tunneling. The linear injection rate can be controlled digitally by
4.5
Ideal linear model
Measured results

4

Measured Vs (V)

3.5
3
2.5
2
1.5
1
0.5
0
0

0.5

1

1.5

2

2.5

3

4

Programming cycles (x10 )

LSB (mV)

(a)
0.2
0.1
0
−0.1
−0.2
0

0.5

1

1.5

2

2.5

3

4

Programming cycles (x10 )

(b)
Figure 4.9: Measured response showing (a) output range for linear injection; and (b) measured
resolution of proposed linear injection circuit.
63

Sp , or by using different combinations of Vref and Iref . In order to reduce the injection error
from equation (4.26), Sp was open for only 50ms during each cycle to add electrons onto FG
node. After each injection cycle, Sp was closed to connect control-gate to ground and Vs was
measured using an off-chip ADC. Figure. 4.9(a) shows the measured result when Vref = 4.9V and
Iref = 50nA. The result shows a close agreement with an ideal linear model. The response veriﬁes
our hypothesis in previous subsection that constant injection rate can be obtained by regulating
the nonlinear parameters of a pMOS transistor according to equation (4.17). The deviation from
ideal linear model occurs at right bottom corner is due to the ﬁnite operating range of opamp A.
The deviation at left top corner is because the starting source voltage is larger than 4.1V and thus
injection is still occurring when Sp is closed.
Figure 4.9(b) indicates the calculated resolution within the 4V output range from 4.1V to 0.1V.
The Least Signiﬁcant Bit (LSB) voltage for Differential Non-Linearity (DNL) was measured to be
less than 0.4mV, which is limited by injection noise. An equivalent resolution is indicated to be
more than 13.4-bit from Fig. 4.9(b).

4.2.3

injection rate control

Based on the injection model expressed by equation (4.17), the injection current, also known as
the injection rate for linear case, is determined by either Vref or Iref . The next set of experiments
investigated the effect of changing Vref and Iref on linear injection rate. For the ﬁrst experiment,
Vref was held constant and different Iref were used. Figure 4.10(a) shows the measured results
when Vref = 4.9V and Iref was varied from 100nA to 30nA in steps of 10nA. For each biasing
current, 1,000 programming cycles were applied to the FG element and the voltage reduction after
each cycle was recorded. As shown in Fig. 4.10(a), all the programming response are linear and
64

the injection rate decreases monotonically with the reduction in Iref . It conforms to the previously
reported results for IHE observed in pMOS transistors [75].

0

Voltage reduction (V)

−0.02
−0.04
Iref= 30nA
Iref= 40nA

−0.06
−0.08

Iref= 50nA
Iref= 60nA

−0.1

Iref= 70nA
Iref= 80nA

−0.12
−0.14
0

Iref= 90nA
Iref=100nA
200

400

600

800

1000

Programming cycles (n)

(a)
0
Vref= 4.65V
Vref= 4.70V

Voltage reduction (V)

−0.02

Vref= 4.75V
Vref= 4.80V

−0.04
−0.06

Vref= 4.85V

−0.08

Vref= 4.90V

−0.1
Vref= 4.95V

−0.12
−0.14
−0.16
0

Vref= 5.00V
200

400

600

800

1000

Programming cycles (n)

(b)
Figure 4.10: Measured linear injection responses when: (a) Iref is varied while Vref = 4.9V; and
(b) Vref is varied while Iref = 50nA.
65

For the next experiment, Iref was held constant and different Vref were used during injection
procedure. Figure 4.10(b) shows the measured results for the case when Iref = 50nA and Vref was
varied from 5V to 4.65V in the step of 50mV. Again, the programming response is linear and the
injection rate decreases monotonically with the reduction in Vref .
For both experiments, the average injection rate can be calculated using a linear regression
over the measured data. It can be readily shown in Fig. 4.11 that a slower injection rate, or a ﬁner
resolution, can be achieved with smaller Vref or Iref , however, at the cost of longer injection time.
From the experiments, the smallest injection rate was found to be 6.9µV/cycle when Vref = 4.6V
and Iref = 30nA. The largest linear injection rate that can be achieved was 250µV/cycle when
Vref = 5V and Iref = 100nA. Also note that increasing capacitor Cfg in Fig. 4.8 should increase
the programming accuracy, but still compromises the programming speed.

300

Injection rate (µV/cycle)

Fitting
Calculated injection rate

Vref=5.00V

250

200

Vref=4.95V

150

Vref=4.90V
Vref=4.85V

100

Vref=4.80V
Vref=4.75V

50

Vref=4.70V
Vref=4.65V

0
30

Vref=4.60V
40

50

60

70

80

90

100

Iref (nA)

Figure 4.11: Measured injection rate when Vref and Iref are varied.
66

4.2.4

injection resolution

The next set of experiments investigated the programming resolution of proposed linear injection
circuit. The output source voltage in Fig. 4.8 was ﬁrst set between 3V–4V using FN tunneling.
Iref was set to 50nA, tp was set to 50ms, and the injection rate was controlled by only adjusting
Vref . For different Vref , the source voltage was recorded after each injection cycle till total voltage
decrease reached 1V. A large ﬁltering capacitor was used at the output of buffer to eliminate the
effect of measurement noise. Figure 4.12 shows the Integral Non-Linearity (INL) and differential
nonlinearity of the programming method which demonstrated a programming resolution of 13.4bit. Figure 4.13 shows the INL and DNL of the programming procedure when a higher Vref (a
higher injection rate) was chosen. In this case the injection accuracy was measured to be 12.1-bit,
however, at a faster programming speed. Note that the INL is determined by the linearity of the
buffer and opamp, which can be reduced using a pre-calibration procedure. In all DNL measure-

INL (mV)

3
2
1
0
−1
0

500

1000

1500

2000

Programming cycles (n)
DNL (mV)

0.4
0.2
0
−0.2
−0.4
0

500

1000

1500

2000

Programming cycles (n)

Figure 4.12: Measured INL and DNL for Vref = 5.11V showing 13.3-bit programming resolution
over a range of 4V.
67

INL (mV)

3
2
1
0
−1
0

200

400

600

800

1000

Programming cycles (n)
DNL (mV)

0.4
0.2
0
−0.2
−0.4
0

200

400

600

800

1000

Programming cycles (n)

Figure 4.13: Measured INL and DNL for Vref = 5.25V showing 12.1-bit programming resolution
over a range of 4V.
ments, it is readily to show that the minimal voltage resolution is approximately 200µV. From our
calculation in previous subsection, the LSB resolution arises from thermal noise artifacts during
the hot electron injection process. Thus, our linear injection approach can achieve fundamental
limits of ﬂoating-gate programming as dictated by thermal noise.

4.2.5

remark

As the modiﬁcation from basic injection circuit, linear injection cell can also be used for ultralow power signal processing with the structure in Fig. 4.5. By setting Iref and Vref appropriately,
injection rate can be easily tuned for both short-term or long-term applications. However, the offset
among each injection channel will generate mismatch of injection rate, which is different from the
case of basic injection cell. Calibration or gain correction is required for linear injection array.
More design details can be found in chapter 5.

68

Chapter 5
Design and Implementation for
Self-Powered Sensor
Exploiting the controllable hot electron injection interfaced with piezoelectric transducer, an ultralow power computation and non-volatile storage block is designed which can be powered by input
strain signal from transducer. Based on the hybrid energy harvesting architecture, more operations
such as data sampling and wireless communication can be activated when an auxiliary reading
device is provided. In addition, FG based analog processor must be initialized properly which
requires high voltage generation to perform FN tunneling and control logic to enable HEI. In this
chapter, the system and circuit level design are presented for the hybrid self-powered sensor.

5.1

System level architecture

The system level architecture for proposed self-powered sensor system is described in Fig. 5.1.
The highlighted Floating-gate based analog processor is design with the concept of controllable
hot electron injection introduced in chapter 4. As the hybrid energy harvesting system, only the
69

analog processor is required to operate continuously for detecting, computing and recording strain
signal of interest, which scavenges energy from Piezoelectric transducer. As shown in Fig. 5.1,
the energy from transducer is used to power the FG based analog processor which is essentially
the ﬂoating-gate injector array. The array can be formed with basic or linear injection circuit cell
which generates different responses according to input strain signal.
During data interrogating mode, an external reader is used for accessing data within sensor. In
our implementation, a 13.56MHz RF source is provided to activate all the circuit blocks for data
sampling, FG transistor programming and wireless communication. As shown in Fig. 5.1, Coil antenna is used for picking up RF energy based on inductive coupling. Voltage multiplier1 performs

Piezoelectric
transducer
Coil antenna

Voltage
multiplier 1
Voltage
multiplier 2

Envelop
recovery

High voltage
generator

SOF detector
& decoder

Tunneling
controller

Power on
reset

Finite state
machine

Injection
controller

Ring
oscillator

8-bit counter

Selection
controller

Backscatter
modulator

Manchester
encoder

Floating-gate
based analog
processor

Demodulator

Digital baseband

MUX

Analog-to-digital
converter

Figure 5.1: System level architecture for the proposed self-powered sensor system.
70

RF/DC conversion and generates the supply voltage for FG transistor array and ADC. Voltage multiplier2 generates a separate supply voltage for other baseband modules to eliminate noise coupling
to the analog processor. In the uplink of wireless telemetry, Pulse Width Modulation (PWM) is
used for transmitting commands from reader to sensor. When a command is received, the signal
frame is ﬁrst restored through Envelop recovery and Demodulator, and then decrypted by SOF
detector & decoder. Once valid command is conﬁrmed, Finite State Machine (FSM) generates
different control signal for data sampling or FG transistor programming. To initialize FG injector
array, hot electron injection can be triggered by Injection controller while FN tunneling can be performed by enabling High voltage generator. When the voltage information stored in one particular
injection channel is acquired, the channel is ﬁrst selected by Selection controller and then routed
to Analog-to-digital converter through MUX. In our implementation, an single-slop (integrating)
ADC is adopted to convert output source voltage into an 8-bit digital form. In the downlink, the
sampled data are converted into series Manchester code and modulated onto RF envelope with
load modulation. Ring oscillator and Power on reset blocks generate clock and global reset signal
for Digital baseband. More details of each circuit block in Fig. 5.1 will be presented in following
subsections.

5.2
5.2.1

13.56MHz RF front-end
Schottky diode based voltage multiplier

For most RF energy harvesting techniques, a voltage multiplier with the structure shown in Fig. 5.2
is used to convert weak RF signal from antenna into a sufﬁcient high supply voltage to power sensor
system. Assuming a sinusoid RF signal Vrf is picked, the charge stored on all C1 can be transferred
71

metal

Vrf

Schottky diode
C1

C1

C1

n+

n+

n-well
Von

C2

C2

CL

p-sub

Figure 5.2: Structure of voltage multiplier and cross view of Schottky diode’s layout.

onto C2 when Vrf is positive. Otherwise when Vrf is negative, all C1 can be charged by Vrf while
the charge on C2 is only discharged by leakage current of diodes. Due to different characteristics
in different phase, the output voltage throughout each stage can be raised. The output voltage for
the multiplier can be expressed as

Vout = α · N · Vrf − Von ,

(5.1)

where N is stage number, α depends on loading conditions and Von is the forward voltage drop
across diode. From equation (5.1), the output voltage can be increased with smaller Von . In
standard CMOS process, the diode is usually implemented with a diode-connected transistor whose
Von is equal to its threshold voltage (0.7–0.9V). In order to reduce the voltage drop, the Schottky
diode is implemented in standard process to increase the efﬁciency of voltage multiplier. As shown
in Fig. 5.2, a Schottky diode is formed with the junction between metal and nwell. Since the barrier
between metal and semiconductor is much less than the threshold voltage of CMOS transistor, a
diode with much smaller Von can be fabricated.
In the implementation, the effect of interdigitated ﬁngers of the Schottky diode is also evaluated. There are totally three types of Schottky diodes with different number of ﬁngers implemented
in a 0.5-µm standard CMOS process, whose top view layout is simpliﬁed in Fig. 5.3(a). The total
72

contact area between metal1 and nwell were same for all diodes and the I-V characteristics were
measured which are presented in Fig. 5.3(b). Compared with diodes formed by CMOS transistor,
the Schottky diodes have smaller Von of around 300mV. For the diode with more ﬁngers, Von was
measured to be slightly smaller since the parallel ﬁngers reduce conductive resistance. However,

1-finger

10-finger

nwell
metal1
20-finger

(a)
1-finger
10-finger
20-finger

100

Current ( µA)

80

0
-0.2

60
-0.4

40

-0.5

-0.4

-0.3

-0.2

-0.1

0

20

0
-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

Voltage (V)

(b)
Figure 5.3: (a) layout of Schottky diodes with different ﬁngers; (b) measured characteristics of
Schottky diodes implemented in a 0.5-µm standard CMOS process.
73

9
8

Output voltage (V)

7
6
5
4
3
2
1
0
0

5

10

15

20

25

30

35

40

45

35

40

45

Loading current (µA)

(a)
9
8

Output voltage (V)

7
6
5
4
3
2
1
0
0

5

10

15

20

25

30

Loading current (µA)

(b)
Figure 5.4: (a) Measured output voltage response for Voltage multiplier1; (b) measured output
response for Voltage multiplier2.

the reduction of Von is at the cost of larger reverse leakage current. As shown in the inset of
Fig. 5.3(b), diode with 20-ﬁnger has the largest leakage current which will reduce the efﬁciency
74

of voltage multiplier. Finally, the Schottky diode with 1-ﬁnger is used in the design of voltage
multipliers of the sensor.
For Voltage multiplier1, a 16-stage structure is used to generate the power supply for analog
circuits including FG array and ADC. For Voltage multiplier2, a similar 12-stage structure is used
to power all digital circuits. In the design, C1 is twice as large as C2 to increase voltage increment
per stage. For the measurement, a 1Vpp 13.56MHz RF signal was applied to both multipliers and
the output voltage was measured under different loading conditions, whose results are plotted in
Fig. 5.4. For multiplier1, the loading condition is pointed in Fig. 5.4(a) where the output voltage
should be above 6V@10µA. The higher supply voltage is used to leave sufﬁcient injection range
for analog processor. Multiplier1 is also used to power ADC (more details in following subsections). For multiplier2, the loading condition is pointed out in Fig. 5.4(b) where the output voltage
is above 2.5V@40µA. The maximal power consumption occurs when the on-chip high voltage
generator is activated for FN tunneling programming (above 15V).
By comparing the measurement results in Fig. 5.4, voltage multiplier with more stages can
generate a higher output voltage when the loading current is relatively small. However, when the
loading current is increased, the output voltage drops faster for the multiplier with more stages
because more energy is wasted on charging/discharging all the internal nodes. Thus, the number
of stages must be optimized according to loading condition to achieve high RF/DC conversion
efﬁciency.

5.2.2

ﬂoating-gate based voltage multiplier

Another design approach for voltage multiplier has been carried out in our implementation by
using the diode formed by ﬂoating-gate transistor. The proposed structure of FG diode for voltage
75

Vfg
Vs
Control-gate
Floating-gate
Source

Drain

d

C

s
D1

D2
D2

n-well

(a)

MP

P

Vd

N
MD

(b)

(c)

Figure 5.5: A ﬂoating-gate diode: (a) cross view; (b) circuit model with parasitic diodes; (c) the
diode with auxiliary programming transistor for adjusting ∆V .

multiplier is shown in Fig. 5.5 where Fig. 5.5(a) illustrates the cross view of layout and Fig. 5.5(b)
shows the circuit model with parasitic diodes. Parasitic diode D1 is formed between drain region
and nwell for pMOS transistor and D2 is formed between nwell and substrate (which is always
connected to ground). Another parasitic diode formed between source and nwell is omitted because
its source is connected to bulk. When a voltage potential is applied across drain to source, the total
current ﬂowing through can be expressed as

(5.2)

Itot = Ids + ID1 ,

where Ids is drain-to-source current and ID1 is the forward current through diode D1 . The reverse
current for D2 is neglected compared with the total current. For RF powered applications, the
input voltage level of multiplier is relatively low, thus the FG diode is assume to operate in weak
inversion region where Ids can be expressed as [76]
Vfg
Ids = S · I0 · exp −
n · UT

· exp
76

Vd
UT

− exp

Vs
UT

,

(5.3)

where I0 is the characteristic current, S is aspect ratio, n is slope factor and all voltage potentials
are referred to the bulk of pMOS transistor. Current ID1 in equation (5.2) can be expressed as

ID1 = Is · exp

Vds
UT

(5.4)

−1 ,

where Is is the characteristic current for diode.
Apply equation (5.3) and (5.4) to (5.2) and the total current for the FG diode is given by

Itot = S · I0 · exp
= S · I0 · exp
= Ieff · exp

∆V
n · UT
∆V
n · UT
Vds
UT

V
− 1 + Is · exp − ds
UT
Vds
+ Is · exp
−1
UT

· exp

Vds
UT

−1
(5.5)

−1 ,

where ∆V represents the programmable voltage drop depending on the charge stored on FG node.
From equation (5.5), the forward current can be considered as a diode with an equivalent characteristic current of Ieff which can be modiﬁed by ∆V . Thus the equivalent forward voltage drop
Von can be reduced after programming the FG diode with large ∆V .
As mentioned in chapter 4, HEI and FN tunneling can be used to modiﬁed the charge stored
on FG node, which requires extra programming voltages. In conventional programming approach,
multiple switches are essential to disconnect FG transistor from the rest of circuit for programming and to switch it back for normal usage. However, when switches are used for each stage
of voltage multiplier, more parasitic resistance and capacitance will be added for internal nodes,
which greatly deteriorates energy conversion efﬁciency. Therefore the indirect programming for
ﬂoating-gate transistor is adopt to eliminate such parasitic effect where the FG diode with auxiliary
programming circuits is plotted in Fig. 5.5(c) [78]. The capacitive coupling terminals of control77

gate and tunneling are not included in the ﬁgure and an auxiliary transistor MP shares the same
ﬂoating-gate node with MD . With this topology, both HEI and FN tunneling can be applied to
MP instead of MD directly, and thus no switch is required for disconnecting MD from the rest of
circuits. The variation of FG node can be measured at Vfg through a unit gain buffer.
The proposed FG diode was implemented in a 0.5-µm standard CMOS process and both simulation and measured results are plotted in Fig. 5.6(a) for forward voltage drop modiﬁcation. The
I-V characteristic is shown for different ∆V between source and gate which were measured using
the buffer. It is readily to ﬁnd that the equivalent Von of FG diode can be programmed to be as low
as 50mV. Also, measured results demonstrate the indirect programming provides a good control
on adjusting the charge on FG node.
A 5-stage voltage multiplier based on the proposed FG diode was prototyped in a standard 0.5µm CMOS process with same structure shown in Fig. 5.2 (the Schottky diode is replaced with FG
diode). Figure 5.6(b) shows the output response for voltage multiplier when RF input is 300mV.
The normal threshold voltage of pMOS transistor was measured to be −0.9V in fabrication process
which means voltage multiplier with diode-connected pMOS transistor cannot harvest any power
from such low level RF input. The frequency of input signal was swept from 0.1MHz to 11MHz
and output DC voltage was measured under no-load condition. The voltage multiplier provides a
gain of around 2 which matches the theoretical performance of a 5-stage multiplier with α = 0.5
in equation (5.1) (the ideal output gain is 2.5 for the 5-stage voltage multiplier). It is believed that
the DC output is determined by the forward charging current and reverse leakage current of FG
diodes. Since the leakage current is considered to be constant, more charge can be stored onto
loading capacitors when the frequency of input signal is increased. However, forward charging
current will stop increasing due to the limited response speed of ﬂoating-gate diodes which results
78

in the gain drop beyond 2MHz as shown in Figure 5.6(b).

20

Ids (µA)

15

10

Simulation: ∆V=550mV
Simulation: ∆V=650mV
Simulation: ∆V=750mV
Simulation: ∆V=850mV
Measured: Vfg=500mV
Measured: Vfg=400mV
Measured: Vfg=300mV
Measured: Vfg=200mV

5

0
−0.5 −0.4 −0.3 −0.2 −0.1

0

V

ds

0.1

0.2

0.3

0.4

0.5

(V)

(a)
2.2
DC output gain
2.1

Voltage Gain

2
1.9
1.8
1.7
1.6
1.5
1.4
0

2

4

6

8

10

Frequency (MHz)

(b)
Figure 5.6: (a) I-V characteristics of ﬂoating-gate diode with programmable threshold voltage; (b)
output response for a 5-stage voltage multiplier based on proposed FG diode.
79

5.2.3

clock data recovery

In the uplink of wireless telemetry from external reading device to sensor, series command is sent
with pulse width modulation where Data 1 contains wider positive pulse width and Data 0 contains
narrower positive pulse width. The command is sent by Amplitude Shift Keying (ASK) modulation. For PWM, the clock information is considered to be transmitted along with data because
there is always a negative edge within each data bit. Based on the architecture shown in Fig. 5.1,
envelope recovery and PWM demodulator are designed to recover both data and synchronized
clock from the variation of RF envelope.
The principle of clock data recovery is described in Fig. 5.7 which includes the schematic and
transient responses of internal voltage nodes. Due to the low voltage level of input signal, Vrf is
ﬁrst doubled in magnitude before its envelope is extracted, denoted as V1 in Fig. 5.7. In order
to amplify the variation of envelope, a comparator is used to compare V1 and V2 , where V2 is
considered to be the average value of V1 through a passive low pass ﬁlter in Fig. 5.7. Therefore,
the output of comparator ampliﬁes the small variation of RF envelope to the range of supply voltage
Vdd . After the inverter chain for pulse shaping, Evp is the recovered RF envelope in digital pattern.
In PWM demodulator, a self delayed integrator can easily generate the bit stream data. As
shown in Fig. 5.7, voltage V3 on capacitor is reseted to ground when Evp is low. When Evp
changes from 0 to Vdd , the capacitor begins to be charged by the pMOS transistor biased at Vb .
V3 starts to increase. With the control of Vb , the increment speed of V3 is designed as it cannot
reach VIH (the minimal voltage to be considered as high level for digital circuit) for the pulse
width of Data 0 while it can exceed VIH for the pulse width of Data 1. Note that Evp is also used
as the trigger clock for synchronizing data. At each negative edge, the resultant value of Data
which represents the bit stream data is triggered into shift register for SOF detection and decoding.
80

Voltage
doubler
Vrf

Envelope
extractor &
Low pass filter V b
V1

Comparator

PWM demodulator

delay

V2

V3

Data

Evp

t

∆
Evp

Vrf

V3
V1
Data
V2

Figure 5.7: Schematics of envelope recovery and PWM demodulator.
Thus a short delay is required to make sure enough holding time where Data is still stable at each
negative edge of Evp. After the bit stream data is stored, V3 is reseted to ground again and waiting
for the next positive pulse width from Evp.

5.2.4

load modulation

Figure 5.8 presents the simpliﬁed circuit model of external reading device and the inductive coupling between reader and sensor. For uplink, the 13.56MHz RF carrier signal is transmitted through
Power Ampliﬁer (PA) which provides auxiliary energy to activate sensor. Also, series command
can be modulated onto RF signal by ASK modulation to access and control sensor. C1 and L1
forms a serial resonance tank to increase the output energy level where R1 is the resistance loss of
L1 . For downlink, the sampled data from sensor is transmitted back by modulating the strength of
RF signal. Therefore, Envelope detector capture the variation and the data is recovered after noise
suppression from Low Pass Filter (LPF). The mechanism for the sensor to send back information
81

C1

i1

PA

i2

C1
U1 U2
R1

LPF

Envelope
detector

R1

M

R2

U0

C2
L1

L1

Zsensor

L2

Figure 5.8: Principle of load modulation.
is called load modulation which is discussed in this subsection.
In RF powered system based on 13.56MHz signal, inductive coupling is used for wireless
telemetry, whose principle can be explained with Fig. 5.8. The reader side is simpliﬁed with a
sinusoid signal source and a series resonance tank formed by C1 , R1 and L1 . On sensor side, a
parallel resonance tank formed by C2 , R2 and L2 is designed to be coupled with external reader,
where the sensor is modeled as an equivalent load impedance. L1 and L2 are implemented with
PCB coil while C1 and C2 are added to achieve resonance at the frequency of 13.56MHz. M is the
mutual inductance between two coils which is dependent on inductances and the distance between
reader and sensor. Due to the existence of M , the impedance of sensor, denoted as Zsensor , can
be reﬂected to reader side with inductive coupling mechanism. When U0 is normalized to unit,
voltage U1 at the present of sensor can be expressed as

U1 =

j · ω · L1 + Zt + R1

1
+ j · ω · L1 + Zt + R1
j · ω · C1

,

(5.6)

where
Zt =

ω 2 · k 2 · L1 · L2
.
1
R2 + j · ω · L2 +
||Zsensor
j · ω · C2
82

(5.7)

where M is replaced by k ·

L1 · L2 and k is coupling coefﬁcient.

In equation (5.6), U1 is found to be a function of Zt and the variance of Zsensor can be reﬂected
to Zt according to (5.7). The concept of load modulation is to modify U1 by varying the impedance
of sensor based on transmitted bit stream data. Since all the energy is coming from reader side, load
modulation is applicable to the wireless telemetry for energy harvesting or self-powered sensor
system. In Fig. 5.8, the impedance of sensor can be considered as the parallel combination of
resistor and capacitor, thus two different approaches for load modulation can be used.
In Fig. 5.9(a), the real part of impedance, resistor R, is modulated under different coupling
conditions to evaluate the corresponding change of U1 . Since the series tank on reader side has
been tuned to resonance frequency, the variation of U1 is signiﬁcant for larger coupling coefﬁcient
k when resistor R is changed from 0 to 10kΩ. However, the change becomes much smaller in the
case of small k. In Fig. 5.9(b), the imaginary part, capacitor C, is modiﬁed from 1 to 100pF and
the corresponding U1 is also plotted. The variation also reduced dramatically with k.
In the implementation, a straightforward approach for load modulation is achieved with an
nMOS transistor connected in parallel with the rest circuit, which is shown in Fig. 5.10(a). The
transistor is controlled by Mod at the gate according to transmitted bit stream data. When the
bit is Data 0, Mod is zero and the nMOS transistor is in cutoff region. The impedance seen from
sensor’s antenna is only Zsensor . When the bit is Data 1, Mod becomes Vdd which turns the nMOS
transistor into linear region and an relatively small resistor is in parallel with Zsensor . Thus the
real part of the impedance across the antenna is reduced whose variation can be detected according
to Fig. 5.8.
There are two drawbacks for the approach shown in Fig. 5.10(a). First, when the nMOS transistor is in linear region, L2 is almost shorted and the input voltage level is around zero. Therefore
83

Normalized envelope variance

18
17

k = 0.01

16

k = 0.02

15
k = 0.03

14
13

k = 0.04
12
11

k = 0.05

10
9
0

2

4

6

8

10

60

80

100

R (kΩ)

(a)
18

Normalized envelope variance

k = 0.01
17
16
k = 0.02
15

k = 0.03

14

k = 0.04
k = 0.05

13
12
11
10
9
0

20

40

C (pF)

(b)
Figure 5.9: (a) Load modulation with R; (b) load modulation with C.

the sensor can hardly scavenge energy at this moment. Second, since the nMOS transistor is directly connected to coil antenna, a parasitic pn junction can be formed between the p substrate and
drain terminal. Since the substrate is always connected to ground in fabrication process, the pn
84

R2

R2

Mod

(a)

Cm

C2

C2
L2

R2

Rm

L2

C2
Mod

(b)

L2

Mod

(c)

Figure 5.10: Different approaches for load modulation.
junction is forward biased when Vrf goes below −0.7V. When it happens, the strength of input RF
signal is limited.
In order to resolve the drawbacks, a resistor Rm is added in series with nMOS transistor which
is shown in Fig. 5.10(b). With the additional resistor, the resistance change is reduced when nMOS
transistor is switching and it results in a small variation of U1 on reader side. The third approach
can be used where Rm is replaced with Cm as shown in Fig. 5.10(c). The additional capacitor is
added to detune the parallel resonance tank formed by L2 and C2 . As shown in Fig. 5.9(b), there
is a tremendous variance on the envelope even for small capacitor. Finally, an n+ guard ring is
added close to nMOS transistor which is used to absorb minority carriers and to further reduce the
possibility of latch up. In our implementation, Cm consists of a capacitor bank which achieves a
tunable loading modulation after sensor is fabricated.

5.3

Floating-gate injector array

In chapter 4, the principle of controllable hot electron injection procedure is described for analog
signal processing. As the most important building block for self-powered sensor system, the analog
processor is formed with multiple FG injectors. The injection cell can be either basic or linear
85

injection circuit described in chapter 4. Injector array can be designed by speciﬁc mechanism to
detect different attribute of signal’s. For long-term fatigue prediction, the strain level and strain
rate information are of most importance. Based on the concept shown in Fig. 4.5, two approaches
are introduced in this section.

5.3.1

implementation of strain level monitoring

The CMOS implementation of self-powered strain level monitoring is presented in Fig. 5.11. It
consists of a cascoded current/voltage reference and an array of FG injectors (3 channels are shown
in Fig. 5.11 as demonstration). The supply voltage is generated from piezoelectric transducer
by ambient strain signal being monitored. Source-to-drain current and control-gate voltage are
generated by the current/voltage reference with startup circuit. The reference circuit is biased in
weak inversion region for low power consumption. The reference current can be expressed as

Iref =

Reference

UT · ln K
,
Rr

Channel 1

Channel 2

Mr1

Mr2

Mc1

Mc2

Mr4

Mc4

Mc5

Channel 3

Mc3

Mr3

Cs

(5.8)

Mc6

Ms1
Mr5

Mr6

Mr7

Mr8

Mr9
M s2

Rr

Msw1
Vs1

Vsw1
N1

Mr10
Cr

Vcg

Ib

Vl1
Md

Cfg
Ma

M fg1
N2

Vsw2

Vl2

Msw2
Vs2
Mfg2
N3

Vsw3

Mfg3
Vl3

Figure 5.11: Simpliﬁed schematics for self-powered strain level monitoring array.
86

M sw3
Vs3

where K is the size ratio for Mr1 and Mr2 and UT is thermal voltage. Biasing current is then
mirrored to each injection channel with Mc1 –Mc6 , etc. For each ﬂoating-gate transistor Mfgi ,
hot electron injection is controlled by switch Vswi where the control signal is generated from a
stack of diode-connected pMOS transistors followed by a single-stage common source ampliﬁer.
Taking Channel 1 as the example, there are N1 pMOS diodes connected in series where Vl1 can
be expressed as
Vl1 =

1
· Vdd − Vsat ,
N1

(5.9)

where Vdd is the output voltage from transducer and Vsat is the minimal voltage drop for the
cascoded current source (Vds of Mc1 and Mc4 ). Vl1 is afterward applied to the common source
ampliﬁer, and the output of Vsw1 can be simpliﬁed as



V
 dd

Vsw1 =


0


if Vl1 < Vm

(5.10)

otherwise

where Vm is the transition voltage level where the ampliﬁer’s output changes from Vdd to 0 which
depends on biasing condition and the size of Cc7 . From equation (5.9) and (5.10), hot electron
injection is trigger on Mfg1 once Vdd is above voltage level of,

Vdd = N1 · Vm + Vsat .

(5.11)

With different number of series pMOS diodes, different voltage level to trigger injection on
each FG transistor can be realized. The simulation results for strain level monitoring among each
channel are presented in Fig. 5.12. In Fig. 5.12(a), the gate voltages for Mswi are plotted when
Vdd is increased from 0 to 10V. After reference current/voltage is established, Mswi follows the
87

change of Vdd when Vdd has not reached the voltage level of Vm according to equation (5.10).
Once (5.11) is satisﬁed, the output of common source ampliﬁer drops from Vdd to 0 and pMOS
switch Mswi is closed to allow current to ﬂow from source to drain. In the implementation, the
number of series pMOS diodes is increased equally among each channel which results in the
trigger voltage level to be 5.8V, 6.7V and 7.6V respectively. The trigger of FG injection can be
demonstrated more directly from the responses of Ids shown in Fig. 5.12(b). The source-to-drain
current is copied from reference current and equals to 18nA in the design. Ids is shown to ﬂow
only after Vdd exceeds certain voltage level in Fig. 5.12(a); otherwise, it remains zero and no hot
electron injection occurs.
As mentioned in section 4.1.2, all injection channels have to be properly initialized before
deployment. The initialization procedure equalizes any post-fabrication residual charge on the
ﬂoating-gate by using FN tunneling to individual injectors. The details of initialization procedure
will be described together with the control logic in section 5.6.2. When the switch in each injector
channel is closed, the voltage different across Cfg and control-gate voltage Vcg are supposed to
achieve a source voltage above the minimal potential required for hot electron injection. In the 0.5µm CMOS process used, the minimal source voltage to achieve observable hot electron injection is
4.1V. Thus during the initialization procedure, Vs1 –Vs3 are programmed to be 4.8V when switches
are closed.
After properly initialized, the self-powered strain level monitoring is evaluated among three
injection channels whose measured results are presented in Fig. 5.13. In Fig. 5.13(a), supply
voltage Vdd is varied from 5V to 9V and Vs1 –Vs3 were measured. Before Vdd reaches certain
voltage level, the switch in each channel is open which makes source node ﬂoating. The measured
voltage depends on parasitic resistors and capacitors on each source node. Since no current is
88

8
7

Channel 1
Channel 2
Channel 3

6

Vswi (V)

5
4
3
2
1
0
0

2

4

6
dd

8

10

6

V

8

10

(V)

(a)
20
18
16

Channel 1
Channel 2
Channel 3

Ids (nA)

14
12
10
8
6
4
2
0
0

2

4

Vdd (V)

(b)
Figure 5.12: Simulation results for level crossing implementation: (a) Vsw1 -Vsw3 ; (b) source-todrain current for each channel.
ﬂowing at this moment, no injection can be triggered regardless source voltage. After Vdd exceeds
the trigger level for each channel, the switch is closed and source voltage increases to the initialized
value rapidly. The measured trigger voltage level for three injection channels are 5.75V, 6.78V and
89

7.69V. The offset from simulation results is due to the mismatch from current mirror and series
pMOS diodes in each channel. The total current for the 3-channel FG array with current/voltage

5
4.5
4

Vsi (V)

3.5
3
2.5
2
1.5
1

Channel 1
Channel 2
Channel 3

0.5
0
5

5.5

6

6.5

7

V

dd

7.5

8

8.5

9

(V)

(a)
100

Total current (nA)

90
80
70
60
50
40
30
3

4

5

6

7

8

Vdd (V)

(b)
Figure 5.13: Measurement results for level crossing implementation: (a) Vs1 –Vs3 ; (b) total current
consumption for ﬂoating-gate array with voltage/current reference.
90

reference is also plotted in Fig. 5.13(b). When Vdd is below 5.75V, only reference circuit is active.
At the point of each trigger level, one additional injection channel is triggered and additional
current starts to ﬂow which is 18nA copied from the current reference. Note that an exponential
trend is found for total current which is due to Ms1 of the startup circuit shown in Fig. 5.11. The
drain of Ms1 is connected directly to Vdd where a parasitic np junction is formed between drain
and p substrate. Such np junction is measured to breakdown after 7V which contributes additional
current for FG injector array. Such effect can be easily eliminated when a different startup circuit is
used. Even with the slightly breakdown current, the overall power consumption of the FG injection
array is still below 1µW which can be easily powered with piezoelectric transducer.
The next set of experiments was conducted to evaluate the performance of FG array for level
crossing algorithm. A 1s pulse signal was applied to the FG array as supply voltage. In four groups
of test, the magnitude of pulse signal was programmed to different level. The corresponding injection procedures were recorded from the output source voltage of each FG transistor during 3,000
loading cycles. At the starting point of each test, all channels were initialized back when all source
voltages were equalized (not precisely). Note that the initialized value for output source voltage is
around 3.1V instead of 4.8V (the reason will be explained in section 5.4). In Fig. 5.14(a), the magnitude of pulse signal was programmed to be 5V which is less than all three trigger level (5.75V,
6.78V and 7.69V). Thus there was no hot electron injection for all channels during 3,000 loading
cycles. In Fig. 5.14(b), the magnitude was programmed to 6V and Channel 1 was triggered for hot
electron injection according to equation (4.11) while the rest two channels had not been triggered.
Likewise, both Channel 1 and Channel 2 were measured to be triggered when Vdd = 7V [shown in
Fig. 5.14(c)] and all three channels could be triggered for Vdd = 8V [shown in Fig. 5.14(d)].
The next set of experiments was used to determine the resolution of a single FG injector to
91

count the number of level crossing events (when input strain level exceeds a certain threshold). For
this experiment, only Channel 1 was chosen and was subjected to voltage pulses from Vdd with the

Output source voltage (V)

3.2

3.1

3

2.9

2.8

2.7

2.6
100

Channel 1
Channel 2
Channel 3
101

102

103

Loading cycles (n)

(a)

Output source voltage (V)

3.2

3.1

3

2.9

2.8

2.7

2.6
100

Channel 1
Channel 2
Channel 3
101

102

103

Loading cycles (n)

(b)
Figure 5.14: Measurement results for different level of Vdd : (a) Vdd = 5V; (b) Vdd = 6V; (c) Vdd
= 7V; (d) Vdd = 8V.
92

Figure 5.14 (cont’d)

Output source voltage (V)

3.2

3.1

3

2.9

2.8

2.7

2.6
100

Channel 1
Channel 2
Channel 3
102

101

Loading cycles (n)

103

(c)

Output source voltage (V)

3.2

3.1

3

2.9

2.8

2.7

2.6
100

Channel 1
Channel 2
Channel 3
101

102

103

Loading cycles (n)

(d)

period of 1s and the magnitude of 6V. The injector channel was ﬁrst calibrated by applying 1,000
calibration pulses to eliminate any initialization/mismatch errors. The voltage pulses were then
programmed according to the following conditions: for the ﬁrst experiment, 256 voltage pulses
93

5
000/256 cycles
220/256 cycles
240/256 cycles
248/256 cycles
256/256 cycles

4.9

Output Voltage (V)

4.8
4.7
4.6
4.5
4.4
4.3
4.2
10

3

104
Loading cycles (n)

(a)
1
0.99

Parameter α

0.98
0.97
0.96

248/256

0.95
0.94
0.93
240/256
0.92
0.91

0.5

1

1.5

2

2.5

3

3.5

4

Loading cycle (x10 )

(b)
Figure 5.15: Measurement results to calculate the resolution for event counting: (a) various counting results for voltage pulses with different duty cycles; (b) different responses measured for α =
240/256 and α = 248/256 with the reference being the response corresponding to α = 256/256.
were directly applied to the injector [referred to as relative count α = 256/256 in Fig. 5.15(a)]; for
the second experiment, only 248 out of 256 pulses were applied to the injector; the experiment
94

was repeated using 240 out of 256 pulses till none pulse out of 256 was applied. As shown in
Fig. 5.15(a), the injector response (in the log-linear region) is monotonically separated from each
other for different relative counts (α = [256/256–0/256]). Mathematically, the relationship between
the change in output source voltage and the relative count α can be expressed as

∆Vs (t) = −

1
· ln
K2

t0 + α · ∆t
t0

,

(5.12)

where t0 is the calibration interval and ∆t is the total experiment duration. If the response corresponding to α = 1 is chosen as the reference, then the relative count α corresponding to any
arbitrary response can be inferred using equation (5.12) as

α=

exp [−K2 · ∆Vs (t)] − 1
,
exp −K2 · ∆Vsref (t) − 1

(5.13)

where ∆Vsref is the output source voltage measured for the case of α = 1. Figure 5.15(b) shows
the measured relative counts for two cases as a function of loading cycles. Also shown are the
ideal counts for the injection response which are 240/256 and 248/256 respectively. The measured
results veriﬁed that the deviation of measured α from the ideal value is less than ±8/256, which
implies that the resolution of the injector for level crossing events is more than 5-bit. The resolution
of the injector can be further improved by reducing any experiment artifacts that introduces error
in the measurement process.

95

5.3.2

implementation of strain rate monitoring

Besides the magnitude of strain signal, the impact rate is also an important attribute in the research
of long-term fatigue monitoring. Using the same principle of controllable hot electron injection,
another computation and storage block to monitor strain rate is presented in Fig. 5.16. The circuit is formed with the same current/voltage reference and 3-channel FG injection array which is
similar with the circuit in Fig. 5.11. However, instead of using multiple series pMOS diodes to
determine trigger level, a nonlinear high pass ﬁlter is adopted to detect different strain rate within
infrasonic region. The high pass ﬁlter consists of capacitor C and an equivalent high value resistor
implemented with Mri .
One signiﬁcant challenge to monitor different strain rate for long-term SHM or BIM application is that the strain signal of interest is within infrasonic range (DC–20Hz). The implementation
of high pass ﬁlter to deal with signal in such low frequency requires extremely large time constant
which results in large value of capacitance or resistance. In order to reduce chip area which is otherwise occupied by huge resistor, a pMOS transistor is chosen for designing a nonlinear, however,

Reference

Channel 1

Channel 2

M r1

M r2

Mc1

M c2

M r3

Cs

M r4

Mc3

Channel 3

M c4

Ms1

Vcg
M r5

M r6

M r7

M r8

Mr9
M s2

M r10
Cr

Rr

M sw1
Vs1

Vsw1
C
Vr1
M f1

C fg

Vsw2

M fg1 C

Vsw3

Mfg2 C
Vr2

Ma

Msw2
Vs2

Mf2

M fg3
Vr3
Mf3

Figure 5.16: Simpliﬁed schematics for self-powered strain rate monitoring array.
96

Msw3
Vs3

high value resistor for high pass ﬁlter. The principle of the FG array in Fig. 5.16 is as follows.
When supply voltage from transducer is increased below certain speed, the output of nonlinear
ﬁlter Vri cannot reach the minimal voltage required to make the output of common source ampliﬁer to be zero. Thus Vswi always follows supply voltage Vdd and no injection can be triggered.
Otherwise, when the rising speed of Vdd is fast enough, Vri is able to short Vswi to ground which
triggers switches Mswi to be closed for HEI.
After supply voltage Vdd stops increasing, the discharging process of Vri still continues which
contains two discharging stages. When Vri is still larger than threshold voltage of Mri , the pMOS
transistor is biased in strong inversion region and the discharging procedure is relatively fast. However, when Vri goes below threshold voltage of Mri , the discharging procedure is switched into
weak inversion region and becomes much slower. Assuming the source voltage of Vri is larger
than 200mV, the discharging current can be expressed as
∂Vs
Idis = −C ·
= S · I0 · exp
∂t

Vs
UT

,

(5.14)

where S is the aspect ratio of Mri , I0 is characteristic current and UT is thermal voltage. The
solution of (5.14) can be expressed as

∆t =

C · UT
Vs
· exp −
S · I0
UT

∆Vs

.

(5.15)

Since the discharging time in strong inversion region can be neglected compared with the much
longer duration in weak inversion region, equation (5.15) gives the approximation of total discharging delay which can be easily made in a few hundred ms. Such long time constant is applicable to
the detection of infrasonic signal.
97

The ﬁrst set of experiment for strain rate monitoring array was to evaluate the effective time
constant for each injection channel. A step signal is applied to the FG array with magnitude
of VH which is sufﬁciently large to trigger HEI once switch Mswi is closed. Ideally, Vr1 –Vr3
will ﬁrst follow the increment of Vdd due to capacitive coupling of C. For this moment, Vsw1 –
Vsw3 are zero. After Vdd remains at Vdd , the source voltages of Mri will quickly drop in strong
inversion discharging whose injection delay is neglected. After entering weak inversion region,
discharging procedure follows equation (5.14) and Vswi will increase from 0 to Vdd once Vr1 –Vr3
is reduced below Von of the common source ampliﬁer. Due to the low discharging current in weak
inversion region, extremely large time constants have been measured for each FG channel as show
in Fig. 5.17(a).
Another important factor in equation (5.15) is that ∆t can be controlled with the size of transistor S. In the implementation, the size ratio for Mr1 –Mr3 is 1:10:20, which ideally will generate
the time delay for ∆t1 –∆t3 in the ratio of 20:2:1. As shown in Fig. 5.17(a), ∆t1 –∆t3 were measured to be 140ms, 15ms and 8ms respectively (offset by the startup delay for current reference
circuit). The ratio of ∆t1 –∆t3 is in close agreement with theoretical values. The error arises
from Vth mismatch among Mr1 –Mr3 and the inﬂuence from discharging process within strong
inversion region.
Since the proposed control method can generate a time delay in ms level, the FG array can be
used to detect signal of interest within infrasonic region. A group of tests were further performed to
evaluate the frequency selection for the array. A periodic ramp signal was applied to Vdd with the
magnitude of 6V. The rising time for Vdd to increase from 0 to 6V was programmed to sweep from
20s to 0.5s and the responses among three channels were measured. Figure 5.17(b)–(c) presents
the comparison result between Channel 1 and Channel 2 in the case of rising time T = 1s. In
98

VH
VH
t3
t3

tstartup
tstartup t
startup
1
t2
t1
1
t2
2

Vdd
Vdd
dd

Vsw2
Vsw2
V sw2

Vsw1
Vsw1
sw1

sw3

Vsw3
sw3
(a)
(a)
(a)
(a)

Vdd
Vdd
Vdd
Vsw1
Vsw1
Vsw1
Vs1
Vs1
Vs1

(b)
(b)
(b)
(b)

Vdd
Vdd
dd
Vsw2
Vsw2
sw2
Vs2
Vs2
s2
(c)
(c)
Figure 5.17: Measurement results of step responses for 3 channels.
(c)
(c)
Figure 5.17: Measurement results of step responses for 3 channels.

Figure 5.17: Measurement results of step responses for 3 channels.
Figure 5.17: Measurement results of step responses for 3 channels.
Fig. 5.17(b), the response for Channel 1 is plotted. Since the high pass ﬁlter in Channel 1 contains
Channel 1 contains
Fig. largest time response for Channel 1 is plotted. Since the high passto 0 during the whole each
response V is always large enough to keep V pass ﬁlter in Channel 1 contains
the 5.17(b), the constant, for Channel 1 is plotted. Since the highsw1 ﬁlter in Channelwhole each
the 1 contains
r1
the largest time constant,inVr1 is always large enough to outputVsource voltage V the wholetoeach
the whole the
r1 is always always closed, keep sw1 to 0 durings1 equals each
cycle. Since theconstant, VChannel 1 is large enough to keep Vsw1 to 0 during s1 equals to the
switch
cycle. Since thewhen the magnitude1 isvoltage supply is output V + Vvoltage Vs1 equals to the
switch in Channel of always closed, above source
initialized value switch in Channel 1 is always closed, output source voltage Vs1 equals to the
sat .
s0
initialized value when the magnitude of voltage supply is above Vs0 + Vsat ..
when the magnitude of voltage supply is above V + Vsat
On the contrary, the ramp signal with rising time T = 1s iss0 sufﬁciently fast to trigger
not
On the contrary, the ramp signal with rising time T = 1s is not sufﬁciently fast to trigger
On the contrary, the ramp signal with rising time T = 1s is not sufﬁciently fast to trigger
contrary, the ramp signal With the time T = 1s
sufﬁciently fast to trigger
Channel 2 as shown in Figure 5.17(c).with risingincrement of Vis notr2 falls below Von quickly
Channel 2 as shown in Figure 5.17(c). With the increment of Vdd ,, Vr2 falls below Von quickly
dd V
Channel 2 as shown in Figure 5.17(c). With the increment of Vdd ,, Vr2 falls below Von quickly
shown in Figure 5.17(c). With the increment of Vdd Vr2 falls below Von quickly
99
which makes the output of common source ampliﬁer always follow Vdd . The switch in Channel
99
99
99

2 remains open which makes Vs2 never have the chance to reach Vs0 and thus no hot electron
injection occurs. After conducting multiple tests for the FG array, Channel 1 has been measured to
be triggered for ramp signal with T ≤ 10s; Channel 2 is triggered with T ≤ 1s and Channel 3 is

3.3

Output source voltage (V)

3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
100

Channel 1
Channel 2
Channel 3
101

102

Loading cycles (n)

103

104

103

104

(a)
3.3

Output source voltage (V)

3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
100

Channel 1
Channel 2
Channel 3
101

102

Loading cycles (n)

(b)
Figure 5.18: Measurement results for impact rate monitoring.
100

Figure 5.18 (cont’d)
3.3

Output source voltage (V)

3.2
3.1
3
2.9
2.8
2.7
2.6

Channel 1
Channel 2
Channel 3

2.5
100

101

102

103

104

Loading cycles (n)

(c)
100

0.5Hz

1Hz

2Hz

90

Total current (nA)

80
70
60
50
40
30
20
10
0
0

2

4

6

8

10

12

14

Time (s)

(d)

triggered with T ≤ 0.5s.
The next set of experiments were performed to evaluate the FG array for long-term event monitoring. An arbitrary signal is applied as Vdd : the signal increases from 0 to 6V in time of T and
101

drops back to zero, the period of each cycle of the signal is 2.5s. The corresponding measured
results are presented in Fig. 5.18. In Fig. 5.18(a), the rising time T is set to be 2s (denoted as
0.5Hz) and only Channel 1 can be triggered for hot electron injection. Vs1 is measured to follow
the theoretical prediction in equation (4.11) with a log-linear response for large loading cycles.
In Fig. 5.18(b), T is changed to 1s (denoted as 1Hz) and both Channel 1 and Channel 2 can be
injected. And all three channels start to be injected when T = 0.5s (denoted as 2Hz) as shown in
Fig. 5.18(c).
The power consumption was also measured during the experiments for the FG array and current/voltage reference whose transient responses are presented in Fig. 5.18(d). In the case of 0.5Hz,
only one injection channel is activated and the total current sources both reference circuit and Channel 1. In the case of 1Hz, one more injection channel can be triggered and thus the peak current
is increased by about 18nA which is copied from current reference. Likewise, the peak current
is increased to about 90nA for the case of 2Hz when all three channels are activated. During all
the tests, total current is below 100nA which guarantees the ultra-low power characteristics for hot
electron injection array.

5.3.3

linear injection array

As introduced in chapter 4, linear injection cell can also be used in FG based analog processor
to achieve stable and precise control. Linear injection array can be triggered by using the same
mechanism presented in Fig. 5.11 and Fig. 5.16 in the replacement of basic FG injector. One
advantage of linear injection cell is the injection rate can be easily controlled by changing Vref
which can greatly extend its applications. Figure 5.19 demonstrates an examples where linear
injection circuit can be used for both short-term and long-term applications. A 1s pulse signal
102

was applied to the injector as supply voltage and the responses were recorded. For same voltage
reduction from 3V to 2V, Vref was set to 5V for Fig. 5.19(a) and set to 4.4V for Fig. 5.19(b).

3

Output source voltage (V)

2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
0

50

100

150

200

250

300

Loading cycles (n)

(a)
3

Output source voltage (V)

2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
0

0.5

1

1.5

2
4

Loading cycles (x10 )

(b)
Figure 5.19: Measurement results of linear injection circuit for (a) short-term monitoring and (b)
long-term monitoring.
103

For higher Vref , voltage drop between each injection cycle is larger which can be implemented as
a strain gauge for strain detection. For lower Vref , the voltage decrease has been extended over
20,000 injection cycles which might takes years to reach its limitation. Thus lower Vref becomes

Voltage reduction (V)

0
−0.2
−0.4
−0.6
−0.8
−1

0

Channel1
Channel2
Channel3
Channel4
500

1000

1500

2000

2500

3000

3500

3000

3500

Injection cycles (n)

(a)

Voltage reduction (V)

0
−0.2
−0.4
−0.6
−0.8
−1

0

Channel1
Channel2
Channel3
Channel4
500

1000

1500

2000

2500

Injection cycles (n)

(b)
Figure 5.20: Measurement results for strain level monitoring with linear injector.
104

Figure 5.20 (cont’d)

Voltage reduction (V)

0
−0.2
−0.4
−0.6
−0.8
−1

0

Channel1
Channel2
Channel3
Channel4
500

1000

1500

2000

2500

3000

3500

3000

3500

Injection cycles (n)

(c)

Voltage reduction (V)

0
−0.2
−0.4
−0.6
−0.8
−1

0

Channel1
Channel2
Channel3
Channel4
500

1000

1500

2000

2500

Injection cycles (n)

(d)

105

applicable to long-term monitoring.
As the comparison to the measured responses in Fig. 5.14, a similar experiment for strain level
monitoring was performed on linear injection array. In Fig. 5.20, a 1s pulse signal was applied to a
4-channel linear injection array for strain level monitoring. Since injection rate is constant in this
case, it is not necessary to initialize each channel to same voltage level, so only the differential
voltage responses are plotted. The magnitude of supply voltage is increased from 6.5V to 9.5V
from Fig. 5.20(a) to Fig. 5.20(d) with 1V as the increment step. There is one additional injection
channel to be triggered for each run in Fig. 5.20, which veriﬁes the level crossing algorithm.
Figure 5.20(d) also indicates a design consideration when using linear injection cell. Since each
linear injection channel is using a separate opamp in the feedback loop, the mismatch results in
voltage offset at source terminal during linear injection. Indicated by equation (4.17), the voltage
offset generates different injection rate among injector array as shown in Fig. 5.20(d). Therefore,
calibration and gain correction are required when using linear injection array.

5.4

Analog-to-digital converter

As mentioned in section 4.1.3, the variation of output source voltage represents the accumulative
number of counted events during self-powered sensing. Due to the non-volatile characteristic for
FG array, the statistics information is stored onto ﬂoating-gate nodes even after the strain signal
vanishes. However, as an autonomous sensor system, additional method is required for data sampling and transmitting. Such operations can be activated during data interrogating mode when an
external reading device is provided. In this section, the readout mechanism of the FG array is
introduced as well as the design of single-slope ADC.
106

5.4.1

readout mechanism

The minimum voltage for hot electron injection in the fabrication process has been measured to be
4.1V. The output source voltage is required to be initialized above that level before operations (4.8V
for the design). Thus, the output range of source voltage is approximately from 4.8 to 4.2V for basic injection circuit with log-linear response. If output source voltage is directly sampled by ADC,
it requires an unnecessarily high supply voltage which results in poor energy efﬁciency. Therefore,
a level shift readout method for the FG array is described in Fig. 5.21. Since all ﬂoating-gate in the
array share the same control-gate, only one injection channel with current/voltage reference circuit
are shown in Fig. 5.21.
Different from the schematic shown in Fig. 5.11 and Fig. 5.16, the reference voltage is not
directly connected to control-gate node. Instead, a level shift switch formed by Mb1 and Mb2
is inserted in between. During long-term self-powered monitoring and initialization procedure,
Vsw cg is zero where reference voltage Vcg is routed to control-gate. However, before output

Reference
C s M r1

M r2

M r3

M r4

Ms1
M r5

M r6

M r7
Mr9
Ms2

M r8

5V

Vcg
Vsw
Mb1

Mr10
Cr

Rr

Cfg

Vs Vs
Mfg

Vcg

4V

3V
2V

M b2
Vsw_cg

Vdd
Vsw_cg

Figure 5.21: The proposed level shift readout method.
107

source voltage is sampled, Vsw cg becomes Vdd which turns off Mb1 and shorts the control-gate
to ground through Mb2 . In the reference circuit, three nMOS transistors are stacked for generating
the Vcg above 2V in weak inversion region. When Vsw cg is increased to Vdd , there is about 2V
level shift for Vs which modiﬁes the output voltage’s range from 4–5V to 2–3V. By the level shift
readout mechanism, the required supply voltage for data sampling can be reduced. Note that for
linear injection cell, the readout circuit in Fig. 5.21 is not necessary due to its control of feedback
loop. Linear cell contains a wider output range from 4.1V to 0.1V and source voltage can be easily
programmed between 2–3V.

5.4.2

single-slope analog-to-digital converter

In the application of long-term strain monitoring, the output source voltage is only accessed when
auxiliary RF signal is provided and thus the sampling data can be considered as DC value. Various
structures of low power ADC can be used for wireless sensor applications among which Successive
Approximation (SAR) ADC and integrating (single slope) ADC are widely used in the case for low
speed situations. For SAR ADC, multiple control switches and large capacitor array is required
which complicates the design and occupies much chip area. Thus, a fully differential single slope
ADC is proposed for data sampling. The architecture of ADC is presented in Fig. 5.22, which
includes the time sequences of 4-phase clock signals.
In the ﬁrst phase, both Vin and Vref are sampled on C1 and all the pre-charged values on C2
are reseted by S1 . When the analog-to-digital conversion starts, two C1 are disconnected with
input and the differential voltage between Vin and Vref is transferred onto C2 at the output which
becomes Vin − Vref . Since the input of opamp is ﬂoating, the charge on C2 can be hold for the
discharging in next phase. When S4 is increased to Vdd , the differential current starts to discharge
108

C2 through node p and n which is generated with a cascoded current reference. Meanwhile, an
8-bit counter is triggered for counting the total time before the differential output is reduced to
zero. Once the sign of opamp’s output becomes opposite, a positive pulse is generated from the
comparator to stop the counter. Therefore, the residual value stored in counter can be expressed as

N=

C · (Vin − Vref )
· f,
Iref

(5.16)

where Iref is the discharging current and f is the frequency of counting clock. From (5.16), N is
found to be proportional to Vin − Vref which is considered as the conversion result of differential
input. One of the challenges in designing single slope ADC for wireless sensor is how to design

S3 p S4
Vcm
Iref

S1

S3

Vin
p
n

S1

C2

C1

V1

S2
C1

C2

Vref
Vcm

S1

Vo

V2

S3
S3 n S4

S1

S1
S2
S3
S4
V1-2

Vin−Vref

Vo
Figure 5.22: Schematics of fully differential analog-to-digital converter.
109

a stable counting clock which is independent of supply voltage. Usually, clock generation block
in sensor is powered by voltage multiplier which varies dramatically in amplitude when reading
distance is changing. Therefore, the counting frequency might also be changed with Vdd which
results in errors for single slope ADC. For an 8-bit ADC with input range of 1V, the tolerance
of clock frequency is that the maximal counting result should not generate the error of one LSB,
which can be expressed as
1−

f
1
,
<
f
256

(5.17)

where f is the frequency tolerance. In the sensor, a current starved ring oscillator is designed
to provide counting clock which contains a weak dependency on Vdd . The design details are
described in later section.

5.4.3

fully differential opamp

The main component of the single slope ADC shown in Fig. 5.22 is the fully differential opamp.
The reference current Iref for discharging can be compromised with the input range and charging
capacitor. Therefore the opamp is the most power consumption block for ADC. In the design of
differential opamp, one challenge is to design Common Mode FeedBack (CMFB) which maintains
the average output voltage to proper value (usually in the middle of maximal output range).
There are several circuit topologies to capture the average output voltage (Vop + Von )/2. One
conventional approach is to use series capacitors and resistors connected with differential outputs
for generating average voltage between Vop and Von . The implementation of this approach is relatively easy, however, extremely large resistor is required in order not to affect the output impedance
and reduce gain, especially for opamp with cascoded output. Another option to capture average
voltage is by using two differential pairs whose inputs are connected to Vop , Vcm and Vcm , Von .
110

Vb1
Vb2

M 2 M3

Vin
Vip

M6

M 10

M7

M1

M 11
Von

Vop

C1

C2

M16
M 17 M 18

M14
Vb3

M21
M22 M23

Vcm

M4M8

M12

M 19

M5M9

M13

M20

Vb4
M24

M25

M15
Figure 5.23: Fully differential opamp used in single slope ADC.
In this case, the differential output is connected to gate which can be considered not affecting the
performance of opamp. However, additional current has to be provided to those differential pairs
for compared Vcm with (Vop + Von )/2. Due to the limited linear input range for differential pair,
the output range of opamp is signiﬁcantly reduced especially for low power circuit design. The
third option is by using switch capacitor technique to generate average voltage. However, digital
noise and complicated control clocks constraint its application for autonomous sensor system.
In order to solve the trade off between power consumption and large output range, a low power
fully differential opamp with new CMFB approach is presented in Fig. 5.23. The main opamp is a
single stage folded cascoded ampliﬁer which is used to achieve a relatively high gain at low current
level. Besides M8 , M9 , M12 and M13 , two more cascoded nMOS pairs are formed by M4 , M5 ,
M14 and M15 . The additional transistors in parallel with the output stage slightly reduces the gain.
However, the variation of the differential output can be reﬂected at the drain of M5 and M15 , in
an attenuated form. When the attenuated outputs are connected to the differential pairs (M17 ,
111

M18 , M22 and M23 ), the variation does not exceed the input range even the differential output is
rail-to-rail. Note that the common mode voltage Vcm is also applied to the same cascoded nMOS
transistor to convert to corresponding voltage level for CMFB. When the average output voltage is
higher than Vcm , the gate of M9 and M13 is increased due to feedback mechanism which lower
Vop and Von . Otherwise, CMFB will reduce the control-gate. Note that C1 and C2 is added as the
Miller capacitor to compensate the CMFB circuit.

5.5

High voltage generator

As the essential approach for programming ﬂoating-gate transistor, FN tunneling is often used to
remove electrons from ﬂoating-gate node which requires a sufﬁciently high voltage (>15V in the
design). Therefore an on-chip high voltage generator is necessary for the proposed self-powered
sensor system. The voltage generator can be controlled by baseband logic when auxiliary RF signal
is provided. In the design, 2V is generated from voltage multiplier for all baseband circuits for low
power consumption. Therefore, a charge pump circuit is included in sensor system to generate the
voltage for FN tunnel. The charge pump based on the structure from [79] is widely used to generate
an output voltage higher than supply voltage, however the conversion efﬁciency becomes quite low
when the supply voltage is reduced close to the threshold voltage of transistor. The performance of
low voltage charge pump is intensively investigated in [80] which is however difﬁcult to implement
the same structure on the fabrication process. Due to the lack of high voltage nMOS transistor, the
active region of nMOS starts to breakdown above 7V which limits the maximal output voltage
for charge pump. Therefore, the structure of an all-pMOS is employed in the design from [81] as
shown in Fig. 5.24.
For each stage of charge pump, four pMOS transistors with a capacitor form the equivalent
112

diode to replace the diode in Dickson’s charge pump. The switch bulk technique is used to make
sure the bulk potential is always the higher one between source and drain, which eliminates the
latch up from the parasitic pnp transistor. The function of charge pump requires four clock signals
shown in Fig. 5.24. Clk1 and Clk2 are non-overlap clocks for charging capacitor Cp and Clk3
and Clk4 are auxiliary clocks to reduce forward voltage drop for each stage. The function of
the second stage is described which is similar to the other stages. For the second stage, the bulk
voltage is connected to V2 when Clk1 is zero and Clk2 is Vdd . Since V2 is higher than V1 , the gate
of conducting pMOS transistor is also connected to V2 which turns off the transistor and thus no
current is ﬂowing from V2 to V1 . When Clk1 is Vdd and Clk2 is zero, the conducting transistor is
turned on and starts to charge Cp from V1 to V2 . Without the top capacitor, the charging procedure
will stop when V2 = V1 − Vth which gives a Vth voltage drop for each stage. In the 4-phase charge

Clk3
Clk4
Cg
M1
Vin

M2

M4

Cg

V1

V2

Cg

V3

V4

Vout

M3

Cp

Clk1
Clk2

Cg

Cp

Cp

Cp

Clk1
Clk2
Clk3
Clk4

Figure 5.24: Schematic of all-pMOS low voltage charge pump.
113

CL

Clk3
ClkIn
Clk1

EN

Clk2

Clk4

Figure 5.25: Schematic of clock generator for 4 phase low voltage charge pump.

pump case, Clk3 goes to zero after Clk1 stays at Vdd . Due to the capacitive coupling, the gate
voltage of conducting transistor becomes V2 − kVdd where k depends on the ratio of capacitor
Cg with parasitic capacitor. Therefore, the voltage at gate has an additional drop from the original
value which compensates Vth and guarantees V2 to be charged to V1 eventually. For an N-stage
charge pump, the output voltage can be expressed as

Vout = Vin + N ·

Cp
I
· η · Vdd − L
Cpar + Cp
Cp · f

,

(5.18)

where Cpar is parasitic capacitance, IL is loading current, f is the frequency of clock signals and
factor η comes from the energy loss when conducting transistor is turned on.
Figure 5.25 shows the schematic of clock generator for Clk1–Clk4. Two inverter chains generate required delay between Clk1 and Clk2 while additional delay is added between Clk1 (Clk2)
and Clk3 (Clk4) by similar topology. Note that the non-overlap clock generator is controlled by
signal EN. When EN is zero, no clock signal can be generated and the charge pump consumes zero
power.
114

5.6

Digital baseband

As shown in Fig. 5.1, the digital baseband of sensor system includes following functions: data
encoding/decoding, sampling control for single slope ADC and programming for FG injection
array. The digital baseband is powered by RF signal from Voltage multiplier2 and in this section,
the designs of ring oscillator and control logic are described.

5.6.1

ring oscillator

Ring oscillator generates global clock for digital baseband when an auxiliary RF signal provides
sufﬁcient power for the sensor. The global clock is not only used for the control logic in baseband,
it is also used as the counting clock for single slope ADC. Therefore, the precision requirement of
clock frequency becomes critical where the tolerance of the frequency must satisfy equation (5.17)
to achieve an 8-bit resolution. In most cases of RF powered system, the input energy level changes
dramatically depending on the distance from the source, which results in large ﬂuctuations of the
power supply from voltage multiplier. Thus a separate voltage regulator is added especially for the
ring oscillator to generate a clock signal which has weak dependency of Vdd .
As show in Fig. 5.26, a 3-stage current starved ring oscillator is proposed with the regulator and
pulse shaping circuit. A cascoded reference circuit is powered by Vdd for generating independent
Vref , Vb1 and Vb2 which is not shown in the ﬁgure. The regulator is formed by a low power 2stage ampliﬁer which is used as the unit gain buffer. As long as Vdd is large enough to power the
reference and regulator, node Vring is equal to Vref which is weakly dependent on Vdd . Capacitor
Cs is used to further eliminate ripples on Vring when it is applied to the ring oscillator. Another
simple current reference circuit is designed to generate the starved current for inverter chain. The
reference current Is is controlled by Rc which can be used to tune clock frequency after fabrication.
115

Regulator

Pulse shaping
Vring

Vb2
Ring oscillator
Is

Vref

Cs

D

Vb1

Clk

Rc

Figure 5.26: Schematic of ring oscillator.
Since Vring is considered to be constant when Vdd is varied, the frequency of generated clock
becomes a weak function of the supply voltage.
Powered by Vring , the output clock signal from ring oscillator has limited output range as well
as wide transition edge. The generated output has to be properly shaped before used as the global
clock. As shown in Fig. 5.26, a 2-stage current starved inverter buffer is inserted to extend the
magnitude to Vdd with limited power. The inverter and D-type Flip Flop (DFF) are used to achieve
a clock signal with reasonable rising/falling time with 50% duty cycle. Finally, a driver is added
to increase the loading capability.

5.6.2

control logic

A control logic is essential to sensor for two basic functions: data sampling and FG transistor
programming. As shown in Fig. 5.1, the digital baseband controls different building blocks such
as FG injection array, charge pump, ADC and coding/decoding. For the proper function of selfpowered sensor, a Finite State Machine (FSM) is implemented in baseband which is diagrammed
in Fig. 5.27. There are totally ﬁve working states for sensor system to perform all the operations.
Once powered, sensor stays in state S0 (Idle) and is ready to enter each state when a corresponding
116

Channel selection: current channel selected; sources
nodes for the other channels are shorted to ground
S1

S2
Injection: switch control gate
from 0 to Vcg to activate hot
electron injection
S3

Continuous sample: sample the source voltage for
current channel and switch to the next one ; repeat

S5
S0

Idle: wait for valid command

S4 Sample: sample the source voltage for current channel

Tunneling: enable the charge pump to generate high voltage for FN tunneling

Figure 5.27: Finite state machine for control logic.
command has been decoded from RF front-end.
Channel selection: FG injection array is formed by multiple channels which are used for
detecting different attributes of strain signal. At one time, only one output source voltage can be
selected and sampled by ADC. Thus a channel selection mechanism is designed to activate the
operations one injection channel while leaving the rest channels unaccessible. The mechanism
for channel selection among a 7-channel array is presented in Fig. 5.28 for demonstration. A pair
of complementary switches is added to each FG channel which is controlled by a one-hot shift
register. When Channel i is selected, Si is Vdd and the corresponding Si is zero while the values
of Si and Si is opposite for the rest channels. For the selected channel, output source voltage is
routed to node Vch for data sampling while the output source voltage is disconnected from Vch
and shorted to ground for the rest channels. Once a valid command is received, the sensor will
enter state S1 and select the next injection channel accordingly (go back to the ﬁrst channel after
selecting the last one).
Injection: As mentioned in section 5.4, the control-gate is shorted to ground to shift the output voltage level for ADC sampling. Moreover, another objective to use the switch is to control
hot electron injection procedure. Once the sensor is powered with RF signal, switch Inj is open
117

Inj
Vcg

__
Inj

S1

S2

S3

S4

S5

S6

S7
Vch

__
S1

__
S2

__
S3

__
S4

__
S5

__
S6

__
S7

Figure 5.28: Schematics of channel selection.

and switch Inj is closed in Fig. 5.28 to reduce output source voltage below the minimal voltage
level for HEI. Therefore, the resultant charge stored in all FG transistors remains constant during
RF accessing state. Once sensor receives the command to activate injection, the control-gate is
switched back to Vcg and output source voltage is restored back which is sufﬁciently high to trigger injection procedure. The switch of the control-gate node is thus used to enable/disable HEI.
Note that only the selected FG channel can be triggered for injection since the source nodes for
rest FG channels are shorted to ground at this moment. Such mechanism is adopted to control the
initialization process separately for multiple channels.
Tunneling: Since it is hard to switch a voltage as high as 15V in circuit operation, all FG
transistors share the same terminal for FN tunneling to remove electrons. In order to initialize FG
array, the global tunneling voltage is generated from high voltage charge pump and all the output
source voltages start to increase. When all source voltages are above the target level, each channel
can be selected to perform HEI separately which reduces source voltage back to the initialized
value. When sensor enters state S3 , the EN signal of the non-overlap clock generator is set to
Vdd as shown in Fig. 5.25. The generated clock signals start to drive charge pump whose output
is connected to global tunneling terminal. Setting EN back to zero will stop the operation of
tunneling.
Sample: In this state, the current output source voltage is sampled by single slope ADC. The
118

control signals are generated by digital baseband and the result is stored in an 8-bit data frame
after the counting is over. The result data are packaged with a valid preamble and 1-bit Cyclic
Redundancy Check (CRC) code and then sent to load modulation transistor for transmission.
Continuous Sample: This state is the combination of state S2 and S4 . When the data in all
FG transistors are required, the sensor will enter S5 and it no longer responses to other commands
from external reading device. Single slope ADC will sample the current output source voltage,
transmit the data frame, and then switch to the next channel to do the same operations again. The
continuous sampling can be stopped only when the sensor is powered off.

5.7

Evaluation for proposed self-powered sensor system

The sensor prototype has been fabricated in 0.5-µm standard CMOS process. Two separate experiments have been conducted to evaluate the function/performance of the proposed sensor. In
the ﬁrst experiment, the sensor is attached above a plexiglass beam where a Polyvinylidene Fluoride (PVDF) transducer is also attached to power the sensor from ambient vibration. In the experiment, a Mechanical Testing System (MTS) machine is used to generate strain signal with different
level where a real time long-term strain monitoring application is emulated. In the second test, an
external reading device is designed based on 13.56MHz RFID system for RF accessing and the
sensor shows good performance for energy harvesting and wireless telemetry.

5.7.1

long-term ambient vibration monitoring

In this subsection, a real time test is performed where the fabricated senor prototype is connected
to a piezoelectric transducer for mechanical usage monitoring. As mentioned in previous sections,
piezoelectric materials can generate large output voltage but exhibit limited current driving ca119

pability. This attribute makes the transducer ideal for operating FG injection in weak inversion
region. However, a piezoelectric transducer also acts as an AC coupled voltage source and the
frequency of loading condition is relatively low (< 1Hz) for long-term ambient vibration monitoring. To understand the limitations imposed by the low frequency operation, consider a simpliﬁed
equivalent circuit model of the FG array interfacing with a piezoelectric transducer as shown in
Fig. 5.29(a). The transducer has been modeled by an AC voltage source connected to a decoupling
capacitor C while the FG array has been modeled as a simple impedance of Rz . For a harmonic
mechanical loading of the transducer at the frequency of f , the magnitude of output voltage across
the load is given by
Vz (f ) =

2 · π · f · Rz · C · V
1/2
2
1 + 4 · π 2 · f 2 · Rz · C 2

(5.19)

.

2
The power from transducer is modeled as Pz = Vz (f )/Rz and the available output power can
be optimized with respect to Rz . The optimal value of the loading impedance Rz can be expressed
as
Rz =

1
.
2·π·f ·C

(5.20)

Vz

~1Hz

plexiglass

C
V

Iz

Rz

sensor

(a)

(b)

Figure 5.29: Setup for real-time experiment: (a) equivalent circuit model for piezoelectric transducer and FG array; (b) MTS setup used for real-time evaluation of the self-powered sensor interfacing with a PVDF transducer.
120

For a loading frequency of 1Hz and the typical capacitance (10nF) of a PVDF type piezoelectric
material, the optimal impedance Rz is calculated to be 15MΩ. Thus, for a 5V input voltage, this

Output source voltage (V)

5.1

5

4.9

4.8

4.7

4.6

4.5

Channel 1
Channel 2
Channel 3
103

104

Loading cycles (n)

(a)

Output source voltage (V)

5.1

5

4.9

4.8

4.7

4.6

4.5

Channel 1
Channel 2
Channel 3
103

104

Loading cycles (n)

(b)
Figure 5.30: Output responses measured for real-time experiments when the sensor is interfaced
with a PVDF transducer and subjected to controlled cyclic strain levels with magnitude (a) 2100µε
and (b) 2500µε.
121

loading condition is equivalent to a maximal output current of 300nA. It is worthy to point out that
the total current drawn by the FG array for both level crossing and impact rate monitoring has been
measured to be less than 100nA, which guarantees the possibility to power the sensor from low
frequency vibration.
For real time experiment, the sensor was interfaced with the PVDF transducer, both of which
were attached to a plexiglass beam. The beam was mounted on the MTS machine which is shown
in Fig. 5.29(b). The MTS machine was then programmed to generate two distinct strain levels of
2100µε and 2500µε respectively. The mechanical loading was cyclically applied to the plexiglass
beam. Figure 5.30(a) shows the measured results when 2100µε strain level was applied and only
Channel 1 is shown to be triggered for recording the variation in output source voltage. When
loading cycles corresponding to 2500µε was applied, both Channel 1 and Channel 2 recorded the
voltage variation while Channel 3 remained constant as shown in Figure 5.30(b). Although no
initialization was performed before each run of test, the offset in measured output source voltage
can be used to determine the count of loading cycles with different strain levels.

5.7.2

wireless telemetry

For the second experiment, RF energy harvesting approach and the wireless telemetry between
external reading device and sensor are evaluated. The setup of experiment is shown in Fig. 5.31,
where the reading device as well as the detail architecture of sensor prototype are presented. The
reader is designed based on the commercial chip TRF7960 from TI which is a fully integrated
13.56MHz RFID analog front-end and data framing reader system. Since the communication
protocol between reader and sensor is highly customized and different from commercial HF RFID
system, the protocol processing block in TRF7960 is disabled and another FPGA development
122

board (SPARTAN-3) is designed as the digital transceiver. TRF7960 is working under direct mode
where the PWM data is directly modulated onto RF envelope with 100% ASK modulation and the
transmitted data from sensor can be detected and recovered in digital form after band pass ﬁlter and
digitization. A PCB antenna is designed as the coil antenna and a matching network is designed
accordingly to increase the output level from reader. The transmitter has output power level of
200mW (23dBm) refer to a 50Ω load at 5V voltage supply.
In order to maximize energy conversion efﬁciency, the PCB coil antenna of sensor is tuned
to resonate at 13.56MHz with a parallel capacitor. Figure 5.32 demonstrates the impedance of
the matching network including sensor prototype. With the parallel capacitor, the imaginary
impedance was canceled out around 13.56MHz and only the real part of 218Ω was measured.
Although the antennas of reader and sensor have not been optimized to best coupling, the customized HF reader can still deliver enough power to the sensor where a maximal reading distance

OSC

ADC

CDR

Ref

VolMul

digital baseband

sensor

Figure 5.31: Experiment setup for wireless telemetry.
123

ASP

was measured to be 40mm. The output of Voltage multiplier1 and multiplier2 as shown in Fig. 5.1
were measured to be 6.2V and 2.5V respectively at 40mm. Note that reader can power and access
sensor at a much longer distance. However, the & protection between coil antennas became so weak
piezoelectric transducer emulator diode bridge coupling
R

R

that reader could not detect any data from sensor above 40mm.dd reader with better sensitivity can
V A
be used to extend reading distance.

zener

Vsin

The control logic in 2R
digital baseband has been evaluated and the sensor is able to perform
gnd
R
required operations correctly. In the test, external reader provided RF energy from the 13.56MHz

carrier signal which was used to activate all the operations of sensor. The signal was measured
at the baseband of reader where the variations on RF envelope were recorded. Once there is data
communication (uplink/downlink), the variation data can be detected. As shown in Fig. 5.33,

Figure 5.32: Impedance matching.
124

VH

readout
Channel 2 Channel 4

Δt1
Δt2

Δt3

Acquire Channel 1

Channel 3

injection

2.8V

1.9ms

Sinj

the transient responses is presented for wireless accessing and data sampling. Figure 5.33(a)–(b)

Vsw2 measured result for FG programming. After receiving valid command, source voltage can
present
cmd
Vsw1
Vsw3 according to readout mechanism in Fig. 5.21 to trigger injection. Also, on-chip charge
be raised
CH1
M 2.50ms 5.00V

CH1 2.00V

CH2 1.00V CH3 1.00V M 1.00ms

pump can generate a sufﬁciently high programming voltage for FN tunneling.

H1 2.00V CH2 2.00V CH3 2.00V M 25.0ms

The operations of data sampling are shown in Fig. 5.33(c)–(d). In Fig. 5.33(c), command was

sent in PWM from reader for data sampling on current FG channel. After the integrating time,

readout

VS

4.7V

injection

2.8V

Vout

1.9ms

Sinj

625μs

en

cmd

1

15V

cmd
CH1 5.00V CH2 5.00V CH3 5.00V M 250μs

CH1 5.00V CH2 1.00V CH3 1.00V M 1.00ms

(a)

(b)

5.0ms
Channel 2 Channel 4

ADC output

Command

Channel 2 Channel 4
Acquire Channel 1 Channel 3
Acquire Channel 1 Channel 3

ADC output

Command

Integrating time
625μs
Vout
Integrating time

en
CH1 2.00V

15V
CH1 2.00V

M 500μs

CH1 2.00V

(c)
M 500μs

CH1 2.00V

M 2.50ms

M 2.50ms

(d)

cmd

Figure 5.33: Measurement results for wireless telemetry between reader device and sensor: (a) enable/disable injection; (b) enable tunneling; (c) single channel sampling; (d) continuous sampling.

t

CH1 5.00V CH2 5.00V CH3 5.00V M 250μs
startup

tstartup
VH
VH

Δt1

Δt1 Δt2

Vdd

Vdd

125

readout
VS

VS

4.7V

4.7V

injection

readout 2.8V

1.9ms

the data frame is packaged and transmitted back by series Manchester code. In Fig. 5.33(d), the
response of continuous sampling is presented. After receiving valid command, the data sampling
is triggered and all the output source voltage is sampled and transmitted back one after another.

126

Chapter 6
Ultrasonic Powering and Communication
From the discussion in previous chapters, the concept of self-powered sensing and hybrid energy
harvesting topology have been validated from the sensor prototype for long-term ambient monitoring. In this chapter, an important extension is discussed for BIM application. When self-powered
sensor is embedded inside human body, RF powering becomes less efﬁcient due to the attenuation
from human tissue. Also, there is safety issue when using RF signal for medical application. On the
contrary, ultrasound has been widely accepted under BIM situation. In this chapter, the possibility
of ultrasonic powering and communication in hybrid energy harvesting system is investigated.

6.1

RF versus ultrasonic

The motivation to use ultrasonic powering in stead of RF powering is because the less attenuation
through human tissue with ultrasound. The comparison has been investigated thoroughly in [82]
between ultrasonic and inductive power delivery. For the simulation of ultrasonic case, two piezoelectric transducers are placed on both side of soft tissue with perfect alignment. Input voltage is
applied to transmitting transducer to induce vibration and receiving transducer is used to picked
127

up the energy across the tissue. For the simulation of RF case, two coil antennas are modeled at
13.56MHz and the power can be delivered from one coil to the other with inductive coupling. The

Efficiency (%)

100

10

Ultrasonic
RF
1

2

4

6

8

10

Receiver diameter (mm)

(a)
100

Efficiency (%)

10−1

10−2

10−3

10−4

10−5

Ultrasonic
RF
2

4

6

8

10

Receiver diameter (mm)

(b)
Figure 6.1: Efﬁciency as the function of receiver’s diameter: (a) at 1cm distance; (b) at 10cm
distance [82].
128

size of antenna is set to be same as the size of transducer.
For the ﬁrst comparison, transmitting transducer (or coil antenna) is ﬁxed and the diameter of
receiving transducer (or coil antenna) is varied. As shown in Fig. 6.1, the conversion efﬁciency is
increased as expected with larger size. When the interrogation distance is at 1cm, ultrasonic powering outperforms RF case when diameter is larger than 3.2mm. When the interrogation distance
is at 10cm, ultrasonic powering is at least one order better than RF case.
In Fig. 6.2, the comparison is performed when the diameter of receiving transducer (or coil
antenna) is ﬁxed and the interrogation distance is increased. The performance of ultrasonic powering is much better than RF case, especially when diameter is small and distance is large. Note
that the data for RF powering is simulated for operations in the air [82]. Considering the increased
parasitic capacitances as well as series resistance from human tissue, the overall performance of
RF powering will be reduced at least by a factor of 2 [83] for BIM, which even emphasizes the
advantages of ultrasonic powering.

6.2

Model for ultrasonic powering and communication

Besides delivering power to embedded sensor, ultrasonic system can also provide the capability
of wireless communication. The concept to use ultrasound as both power source and wireless
communication has been reported in recent research works [84, 85]. In this section, a detail ultrasonic powering and communication model is presented with Matlab simulation based on Mason’s
model [84].
The system diagram for simulation is presented in Fig. 6.3(a). Transmitting transducer is excited by voltage source Vin whose output impedance is Rs . The transducer is on the left side of soft
tissue and backed with air. Receiving transducer is assumed to be embedded with sensor which is
129

100
Ultrasonic
RF

Efficiency (%)

10

1

0.1

0.01
0

2

4

6

8

10

Distance (cm)

(a)
102
Ultrasonic
RF

Efficiency (%)

101
100
10−1
10−2
10−3
10−4
0

2

4

6

8

10

Distance (cm)

(b)
Figure 6.2: Efﬁciency as the function of source-receiver distance: (a) for 10mm diameter; (b) for
5mm diameter.
backed with the same tissue. The loading condition of sensor circuit is modeled as Rl . Matching
layer is added between both transducers with tissue to increase efﬁciency.
According to Mason’s model, the equivalent circuit model for Fig. 6.3(a) is redraw in Fig. 6.3(b).
130

Maching
layer

Maching
layer

Transmit
piezo

Air

Receive
piezo
Tissue

Tissue

Rs
Rl
V in

(a)
Piezo

Tissue backing

Air backing

ZP1
Rs

Tissue

ZP2

-C 0
1:N

ZAB
V in

ZP1

Matching
layer
Z M1
ZM1

ZM2

C0
ZS1

Vout

Z S2 Z
S1
Rl

C0

ZTB

ZM2

1:N
-C 0

ZP2
ZP1

ZP1

Z M1

ZM1

(b)
Figure 6.3: Ultrasonic powering and communication system using Mason’s model: (a) system
diagram; (b) equivalent circuit model based on Mason’s model [84].
The transformers represent the conversion between mechanical side and electrical side. Note that
parameter current and voltage in electrical domain are correspond parameter velocity and pressure in mechanical domain. Ratio N depends on the properties of transducer such as permittivity,
elastic stiffness and electromechanical coupling. The negative capacitor −C0 is required for Mason’s model. For each layer of material, a T-network is used to model the impedance shown in
131

Fig. 6.3(b). For particular layer L, impedance ZL1 and ZL2 can be expressed as

ZL1 = i · ZL0 · tan

ΓL · tL
2

ZL2 = −i · ZL0 · csc ΓL · tL

(6.1)

ZL0 = ρL · vL
ΓL =

2·π·f
vL

where tL is thickness, ρL is density, vL is velocity and f is the frequency of ultrasound. The properties used in simulation for each material are listed in Table 6.1. In order to know the efﬁciency of
energy delivery from Vin to Rl , the input impedance is required for calculating the actual energy
induced into transmitting transducer. Figure 6.4 is used for the calculation with all the labels of
internal nodes. Thus, from the output,

ZR1 = Rl || ZC0
ZR2 = ZR1 − ZC0
ZR3 = ZR2 · N 2
ZR4 = ZR3 + ZP2
ZR5 = ZTB + ZP1
ZR6 = ZR4 || ZR5
ZR7 = ZR6 + ZM1
ZR8 = ZR7 || ZM2
ZR9 = ZR8 + ZM1 + ZT1
ZR10 = ZR9 || ZS2 ,
132

(6.2)

Table 6.1: Material properties and geometric parameters used for simulation.
Properties/Parameters

Piezoelectric

Soft tissue

Matching layer

7750

1058

3650

Velocity of sound v (m/s)

4838

4821 · (1 + 0.00575 · j)

3650

Thickness t (mm)

3

1–100

λ/4

Density ρ

(kg/m3 )

Z T4
ZP1

Rs
ZAB
Vin

Z T8
ZT7
-C0
1:N

Z T3
ZP1
Z P2

ZT2
ZM1

ZT1
Z M1

ZT5
Z M2

Z T6

C0
ZS1
ZS2

V out

Rl

ZR9

C0

ZTB

1:N
ZR1

ZS1

ZR10

-C0

Z R2
ZP1
ZR5

ZR3
ZP2

Z M2
ZR4

ZP1
Z R6

ZM1
ZR7

Z M1
ZR8

Figure 6.4: Mason’s model with labels for calculations.

where ZC0 = 1/(j · ω · C0 ) and ZTB is acoustic impedance of tissue which can be express as

ZTB = A · ρTB · vTB ,

(6.3)

where A is contact area, ρTB and vTB can be found in Table 6.1. So far, the equivalent impedance
at the middle point has been calculated to be ZR10 . From here,
133

ZT1 = ZS1 + ZM1 + ZR10
ZT2 = ZT1 || ZM2
ZT3 = ZT2 + ZM1 + ZP1
ZT4 = ZAB + ZP1
ZT5 = ZT3 || ZT4

(6.4)

ZT6 = ZT5 + ZP2
ZT7 = ZT6 · N −2
ZT8 = ZT7 − ZC0
Zin = ZT8 || ZC0 ,
where ZTB is acoustic impedance of air which is (415 · A). Thus, the input current from voltage
source can be expressed as
Vin
Iin =
.
Rs + Zin

(6.5)

Applying input current to equation (6.2) and (6.4), the power delivered can be calculated from,
ZC0
IT1 = Iin ·
ZC0 + ZT8
VT2 = IT1 · N -1
ZT4
VT3 = VT2 ·
ZT4 + ZT3
ZM2
VT4 = VT3 ·
ZM2 + ZT1
ZS2
VT5 = VT4 ·
.
ZH2 + ZR9
134

(6.6)

Then across the soft tissue from transmitting to receiving,
ZM2
VR1 = VT5 ·
ZM2 + ZR7
ZR5
VR2 = VR1 ·
ZR5 + ZR4
IR3 = VR2 · N

(6.7)

ZC0
IL = IR3 ·
ZC0 + Rl
Vout = IR3 · ZR1 .
By using the equations from (6.4) to (6.7), input power and output power can be expressed as
the real part of voltage times current,

Pin = (Vin · IT1 )

(6.8)

Pout = (Vout · IL ).
Figure 6.5 plots the simulation result of the energy conversion efﬁciency (Pout /Pin ) when
the thickness t of soft tissue is changed from 1mm to 100mm. In the simulation, the diameter
of transducer is 10mm, Rs = 50Ω and Rl = 1kΩ. Due to the mechanical coupling between each
layer of material, the frequency of maximal conversion efﬁciency is also changed according to the
thickness t. Therefore, the frequency of input ultrasound signal is swept up to 2MHz for each t to
ﬁnd out the maximal efﬁciency. Similar to Fig. 6.1 and Fig. 6.2, ultrasonic powering can deliver
a certain amount of energy through soft tissue. Assuming source energy level is 100mW, there is
still 1.43mW can be delivered into the embedded transducer which can be used to power sensor
circuits.
Beside power delivery, the capability of wireless communication is also an essential part for
135

embedded application. By using the same idea of load modulation in inductive coupling system, the possibility of ultrasonic communication through soft tissue is investigated. As shown in
Fig. 6.6(a), the Mason’s model in Fig. 6.3(b) is simpliﬁed and only the coupling between electrical and mechanical side is presented. Similar to load modulation in inductive coupling system,
switch Sm is controlled by the transmitted bit stream which can short Rl to ground accordingly
when there are data transmitted from embedded sensor. Due to the mechanical coupling through
all layers, the modulated voltage can be expressed from equation (6.4) and (6.5) as

(6.9)

Vmod = Iin · Zin .

From the same Mason’s model, Rl is change from 1kΩ to 0 at the maximal energy efﬁciency
frequency. The variation of |Vmod | is plotted in Fig. 6.6(b) as a function of thickness t. When
t is relatively small, the coupling between two transducers is in near ﬁeld or Fresnell zone [86].

Power conversion efficiency (%)

40
35
30
25
20
15
10
5
0
0

20

40

60

80

100

Reading distance (mm)

Figure 6.5: Simulated energy conversion efﬁciency versus distance.
136

Vm
Vin

-C 0

-C 0
C0

C0

Rl

Sm

(a)
Normalized voltage modulation

0.025

0.02

0.015

0.01

0.005

0
0

20

40

60

80

100

Reading distance (mm)

(b)
Figure 6.6: Ultrasonic communication model. (a) simpliﬁed circuit model for load modulation; (b)
simulated result for normalized modulated voltage.
Therefore the variation of modulated voltage changes rapidly with t. When t becomes larger, the
variation gradually decreases with t as expected. It is believed that after properly optimized, load
modulation can also be used for ultrasonic communication.

137

Chapter 7
Conclusions
This dissertation is trying to answer one question: what is the minimal power requirement for
sensing applications. For existing energy harvesting technique, the inclusion of energy storage
and power management reduces total efﬁciency. Besides, MCU based sensor subsystem requires a
certain amount of energy for data sampling and computation.
To reduce the power consumption into sub-µW level, an analog signal processing architecture
is proposed to achieve ultra-low power signal processing and non-volatile storage by exploring the
physical characteristics of ﬂoating-gate transistor. When hot electron injection procedure is well
controlled, speciﬁc computation can be achieved with several nA current consumption. Plus, the
computation results can be retained on ﬂoating-gate without additional energy.
The hybrid energy harvesting architecture is also proposed in this dissertation to dissolve the
conﬂict between continuous operation and asynchronous interrogation. At system level, sensor
circuits have been divided into two categories based on operation modes. One type of circuits are
required for continuous operation to sense/record signal of interest. The circuits are designed with
the idea of self-powered. The other type of circuits consist of those power-hungry circuits which
138

Table 7.1: Main Speciﬁcations for self-powered sensor.

Fabrication process

0.5-µm standard CMOS

Die size

1.6mm×1.6mm

Level-crossing algorithm

3-channel strain level monitoring

6–8V

3-channel strain rate monitoring

0.5–2Hz

< 90nA

Power (monitoring mode)

Analog processor & ADC
Digital baseband

3.83µA@2V

Digital baseband (charge pump activated)

Power (interrogating mode)

2.48µA@6V
35.53µA@2V

RF Carrier frequency

13.56MHz

Reading distance

40mm
uplink

40kHz PWM

downlink

Wireless telemetry

150kHz Manchester

are only needed to be activated occasionally (e.g. during data accessing).
A sensor prototype has been designed and fabricated in 0.5-µm standard CMOS process to
prove these concepts whose main speciﬁcations are summarized in Table 7.1. The sensor can be
used for long-term ambient vibration monitoring and the ideas of self-powered solution and hybrid
energy harvesting have been evaluated in previous chapters.

7.1

Summary of contributions

To conclude, the contributions of this dissertation are summarized here:
• Exploiting the computational primitives inherent in hot electron injection on ﬂoating-gate
A computation cell has been invented using ﬂoating-gate transistor where non-volatile computation and storage can be achieved with a few nA current consumption [87]. With appropriate
139

circuit design, a log-linear response can be achieved with single electron per second operation
limit and 5-bit resolution. Speciﬁc data calculation and processing can be developed based on the
proposed cell for self-powered sensing [88].
• Developing linear injection technique for computation and programming
A linear injection technique has been proposed based on standard ﬂoating-gate injection cell [89].
The programming/computation resolution can be increased from 5-bit to 13-bit which is constrained by the thermal noise during injection procedure. Applying the proposed technique for
analog signal processing can greatly enlarge its operation range and resolution. Plus, the proposed
technique can be combined with other ﬂoating-gate programming circuits to generate a more precise control.
• Implementing a self-powered sensor with hybrid energy harvesting technique
A completed sensor prototype has been fabricated to validate the hypothesis of self-powered
sensing and hybrid energy harvesting topology [90, 91, 92]. During autonomous sensing, the
usage of energy storage and power management has been eliminated which achieves high energy
efﬁciency. The sensor is functioning as expected during both long-term self-powered monitoring
mode and wireless interrogating mode.
• Inventing novel circuit structures with ﬂoating-gate technique
In addition to the ﬂoating-gate charge pump introduced in chapter 5 [93], several other novel
circuit structures have been invented by using ﬂoating-gate technique. A dual-channel ﬂoatinggate architecture is proposed to reduce programming mismatch due to oxide degradation [94, 95].
A temperature compensated programming current reference is proposed to generate a temperature
independent nA reference current [96]

140

7.2

Future directions

Regarding to all preliminary results from current sensor prototype, several aspects which can be
further improved are listed as follows:
• More functional implementation based on controllable HEI
Linear injection circuit becomes a good choice of computation cell as well as storage unit. By
using different control mechanism, more sophisticated functions might be implemented with linear
injection structure such as correlation or FFT. Linear injection circuit can also be used with indirect
programming topology to achieve a ﬂoating-gate programming array with more precise control.
• New energy harvesting topology
The current version of self-powered sensor is based on 13.56MHz RFID system for RF energy
harvesting and wireless communication. Due to the limitation of inductive coupling, the interrogation distance between external reading device and sensor can not exceed several meters. Plus, RF
powering setup is not applicable to medical implant applications. The possibility to use ultrasonic
powering and communication system has been valuated with simulation results in chapter 6. More
experimental attempts can be performed to build new system.

141

BIBLIOGRAPHY

142

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