DESIGN, ANALYSIS AND CONTROL OF A SiC BIDIRECTIONAL G 2 V , V2 L AND V 2 G UNIVERSAL POWER CONVERTER IN NEXT GENERATION ELECTRIC VE H I C LE By X iaorui Wang A DISSERTATION Submitted to Michigan State University in partial fulfillment of the requirements for the degree of E lectrical Engineering D octor of Philosophy 201 9 ABSTRACT DESIGN, ANALYSIS AND CONTROL OF A SiC BIDIRECTIONAL G2V, V2 L AND V2 G UNIVERSAL POWER CONVERTER IN NEXT GENERATION ELECTRIC VEHICLE By Xiaorui Wang As the electric vehicle (EV) is becoming more and more popular, there exists an increasing need for more efficient charging facilities for both on - board and off - board chargers. High power density on - board charger can help reduce the weight of the vehicle and leading to higher miles per kilo - watt - hour (kwh). What is more, EV with tens of kilo - watt - hour battery is a perfect energy storage unit with mobility. Hence, in the next gene ration modern home - based microgrid system, EV can play multiple roles beyond transportation. For example, EV can send active power back to the grid, which can help reduce the power grid burden during peak hour. EV can also improve the distribution power gr id quality by sending reactive (either inductive or capacitive) power to the grid especially where the heavy unbalanced load is connected. The power flow interaction between the vehicle is often recognized as G2V (Grid to vehicle or charging mode) or V2G ( vehicle to grid). Not only does EV can help stabilize the grid, but also it can benefit the home appliance by providing robust AC (single - phase or three - phase) or DC voltage output for various loads whenever the mainline is not available. However, these ap plication scenarios would not be feasible if there is no such universal power converter to facilitate the power flow. A modular and universal power converter is of great need to achieve this goal. Hardware design flexibility and scalability are very import ant which allows configurations into different ways to accomplish various functions mentioned above. Hence, in this thesis, a hardware prototype with the mentioned property is built to prove the idea and solve the challenges of integrating all function in a single unit. The wide bandgap power device is used due to their excellence in the reduction of switching and conduction losses. Robust gate drive design with protection feature is explained and verified with experiments results. Galvanic isolation is re quired in such a converter and implemented by an isolation transformer. The nanocrystalline core material is selected to construct the isolation transformer in this prototype since it has higher saturation flux density and relatively low core losses at hig h frequency. Optimization algorithm for low conduction loss under variable operating modes is proposed. A generalized transformer design procedure is also discussed and verified with experimental results. To realize these multiple functions, sensors and di gital signal processors are used to control this converter. Detailed control strategy for each application scenario has been analyzed and verified with sim ulation or experimental results . iv Dedicated t o: My parents: Haisheng Wang, Xiaoling Zhang My wife : Ziyou Zhang iv ACKNOWLEDGEMENT S First , I would like to give my heartfelt thanks to my advisor, Dr. Fang Z. Peng. Thank you for giving me precious advices , pointing out the right directions and sharing actionable insights. I would not be able to learn that much and finish all these works without your guidance. You are such a great mentor who coached, helped and encouraged me to achieve long stride in this P hD program . I am so proud to be one of your students. sincere gratitude to my adviser Dr. Bingsen Wang who supported and guided me through the universal charger project. Your knowledge, kindness and patience help me to tackle the challenges and make progress . Meanwhile, I am also very thankful to my committee members Dr. Mitra , and Dr. Zhu . Thank you for giving me all the impressive lectures about power system and advanced control theory from which I built up my knowledge base . I would also like to thank Dr. Strangas for the vivid and lucid lectures on motor drives which are the best I have ever seen. Six - year generous help from all of you ta kes me to the final stage . Many thanks go to my colleagues in power group at MSU , for valuable discussions, and selfless help, as well as priceless friendships, Dr . Yunting Liu, Dr. Wei Qian , Prof . Allan Taylor, Dr. Shuitao Yang, Dr. Deepak Gunasekaran, Dr. Ujjwal Karki , Dr. Y aqub Mahnashi , Dr. Hulong Zeng , Yaodong Yu , Dr. Yang Liu, Xianhao Yu, Sisheng Liang , Petros Taskas, Nomar González - Santini, Dr. Lihua Chen, Dr. Baoming Ge, Dr. Dong Cao, Dr. Miaosen Shen, Dr. Shao Zhang, Dr. Shuai Jiang, Dr. Qin Lei, Dr. Runruo Chen, Dr. Liang Qin, Dr. Gujing Han, Dr. Liqing Tong, Ameer Janabi , Abdulrhman Lafi Alshaabani , Dr. Yuting Tian, Dr. Yantao Song, Dr. Niannian Cai, and other friends . Additional gratitude goes to Dr. Yunting Liu, who is my wonderful renders a phenomenal and crucial v contribution, and I really appreciate your brilliant explanation about digital control and converter modeling . To Dr. Wei Qian, who is so generous in sharing knowledge and I am feeling very fortunate to learn from such a senior with rich experience . To Dr. Shuitao Yang, who helped me enormously in the UPFC project and shared valuable discussions about converter control with me. To Prof. Alla n Taylor from whom I learned so much about DSP programming and PCB design and as whom I respected Power Electronics Hand book . It is my great honor to work with Dr. Xi Lu, Dr. Ke Zou, and Dr. Chingchi Chen from the Ford Motor Company on the bidirectional charger project. I sincerely appreciate this opportunity. I also want to accredit this work to my high school English teacher Mr. Weimin Zhang and Ms. We n jing Liu without whom I would lose interest of learning English . In the meantime, I would like to express my earnest gratitude to Prof. An Luo and Prof. John Shen for giving me enlightenment on power electronics which help s me embark on this amazing research journ ey . Meanwhile , I would like to thank my friends at MSU and from the industry , Dr. Bojian Cao, Dr. Jianfu Fu , Liming Li , Dr. Xiao Li, Dr. Pengchen Jiao, Dr. Yiquan Yang, Dr. Dezhi Feng , Dr. Suoming Zhang, Dr. Yuanchao Liu, Dr. Qi Tian, Dr. Shimeng Huang, Dr. Siming Yang, Dr. Fangzhou Wei, Yang Hu , Sameer Kher, and Dr. Pin Zhou . It has been 10 years since I came to US for study and work . Carnegie Mellon University is my first stop. I am so lucky to have the se friends at CMU . Being around with you folks feel like warm home and this feeling did not change at all over the past ten years . Special thanks go to the big brother - Dr. Xinghua Liang, Dr. Wenyan Wang, Dr. Jin Qian, Chen Zhang, Boyuan Li, Yiming Jing, Jun Ma, Dr. Tao Liao, CheongKin Ng , Yi Luo, Xiaoxin Su, Zhiwei Huang , Fangkai Zhu , Zonghui Su and other friends. vi I want to send cordial thankfulness to m y old friend (also my best man) since elementary school, Dr. Xiao Zhang . We have known each other more than decades. Your encouragement and support helped me to go through the tough moments and still inspire s me till now. I also want to thank my lifetime role models m y aunt Xiaomei Wang and my uncle Dr. Jing Xu . Thank you for being so supportive all the time. I am so grateful for everything you have done to this family . No words can express that. My father and mother are the best parent s on this planet, although I may not be the best son. Thank you for raising me up. It has been extremely difficult to be apart since day one I am away from home . There are ups and downs during th is PhD ride , b ut you are always available , being my cheerleader when I am upset and holding the strongest and peaceful nest to me whenever it is needed . You are wonderful teacher s and have been mentoring me to be a kind, thoughtful, and responsible man. I am living my entire life up to it. Last but not the least, I would like to thank m y gorgeous wife Ziyou Zhang . Y ou a re my si l ver lining to the cloudy sky and the pillar of my strength . You are pretty, considerate, and full of wisdom whose smile can ease the frustration. I could be happier to know you and to be with you. You are not only wife, but also my best friend who turns this PhD study to a more enjoyable one . At last, I also want to thank my pet cat Sushi who is such an adorable sweet piece to my life. vii TABLE OF CONTENTS LIST OF TABLES ................................ ................................ ................................ .............. ix LIST OF FIGURES ................................ ................................ ................................ .............. x Chapter 1 Introduction ................................ ................................ ................................ ........ 1 1.1 Research motivation of universal bidirectional converter ................................ ........... 1 1.2 Existing on - board charger review ................................ ................................ .............. 2 1.3 Proposed SiC bidirectional universal power converter ................................ ............... 3 1.4 Scope of the thesis ................................ ................................ ................................ ..... 5 Chapter 2 Hardware design of the PCBB ................................ ................................ ............ 7 2.1 Selection of Power MOSFET ................................ ................................ ........................ 7 2.1.1 Wide band gap devices ................................ ................................ ........................... 7 2.1.2 Selected SiC Power MOSFET Key Characteristics ................................ ................. 9 2.2 Design of SiC gate driver ................................ ................................ ............................ 13 2.2.1 Gate drive topology ................................ ................................ .............................. 13 2.2.2 Gate drive schematics ................................ ................................ ........................... 15 2.2.3 Gate drive test (Double pulse) results ................................ ................................ .... 18 2.2.4 Gate drive protection feature ................................ ................................ ................. 21 2.3 Controller board and controller interface board ................................ ........................... 24 2.3.1 DSP control board ................................ ................................ ................................ 24 2.3.2 Sensors in the prototype ................................ ................................ ........................ 24 2. 3.3 Interface board between DSP and Gate drive boards ................................ ............. 28 2.4 DC link capacitors selection ................................ ................................ ........................ 29 2.4.1 Electrolytic Capacitors bus bar ................................ ................................ .............. 30 2.4.2 Film Capacitors bus bar ................................ ................................ ........................ 31 2.5 Transformer design ................................ ................................ ................................ ..... 32 2.5.1 Single phase shift vs Dual phase shift ................................ ................................ ... 33 2.5.2 Turns ratio determination ................................ ................................ ...................... 36 2.5.3 Core Flux waveform ................................ ................................ ............................. 39 2.5.3 Design Steps ................................ ................................ ................................ ......... 40 2.5.5 Transfor mer test results ................................ ................................ ......................... 42 viii 2.6 Filters design ................................ ................................ ................................ ............... 44 2.6.1 Filter inductor design ................................ ................................ ............................ 44 2.6.2 Filter capacitor design ................................ ................................ ........................... 45 2.7 Complete prototype ................................ ................................ ................................ ..... 45 Chapter 3 Vehicle to Load (V2L) analysis and control ................................ ..................... 48 3.1 Operation principle of V2L mode ................................ ................................ ................ 48 3.2 Control analysis of V2L mode ................................ ................................ ..................... 49 3.2.1 DAB modeling ................................ ................................ ................................ ...... 52 3.2.2 VSI Inve rter modeling and Multiphase DC/DC (IBC) modeling ........................... 54 3.3 Simulation and Experimental results ................................ ................................ ........... 54 3.3.1 Three phase resistive load - Experimental and Simulation results .......................... 54 3.3.2 DC load Simulation and Experiment result ................................ ........................... 65 Chapter 4 Vehicle to Grid (V2G) analysis and control ................................ ..................... 71 4.1 Operation principle of V2G mode ................................ ................................ ............... 71 4.2 Grid imposed inverter modeling ................................ ................................ .................. 73 4.2.1 Three phase grid - tied inverter modeling ................................ ................................ 74 4.2.2 Single phase grid - tied inverter modeling ................................ ............................... 80 4.3 Control Analysis for V2G mode ................................ ................................ .................. 82 4.4 Simulation and Experiment results ................................ ................................ .............. 84 4.4.1 Three phase V2G simulation results ................................ ................................ ...... 84 Chapter 5 Grid to Vehicle (G2V) analysis and control ................................ ..................... 87 5.1 Operation principle of G2V charger ................................ ................................ ............ 87 5.2 Control analysis of G2V mode ................................ ................................ .................... 88 5.3 Simulation and Experimental results ................................ ................................ ........... 89 5.3.1 Three phase G2V simulation results ................................ ................................ ...... 89 5.3.2 Single phase G2V simulation and experiment results ................................ ............ 91 Chapter 6 Conclusions, and Future work ................................ ................................ .......... 97 6.1 Conclusions ................................ ................................ ................................ ................. 97 6.2 Future work ................................ ................................ ................................ ................. 97 BIBLIOGRAPHY ................................ ................................ ................................ ............. 100 ix LIST OF TABLES Table 1 - 1 PCBB Rated Power Under Different Applications ................................ ................. 4 Table 2 - 1 Maximum rating and electrical characteristics ................................ ...................... 10 Table 2 - 2 Operation modes ................................ ................................ ................................ .. 30 Table 2 - 3 DC link electrolytic cap specs ................................ ................................ .............. 31 Table 2 - 4 DC link film capacitor specs ................................ ................................ ................ 32 Table 2 - 5 Transformer design specs ................................ ................................ ..................... 41 Table 3 - 1 Open loop prototype test setup parameter ................................ ............................. 55 Table 3 - 2 Closed loop V2L test setup parameter ................................ ................................ .. 57 Table 3 - 3 Linear load step change simulation parameter ................................ ...................... 61 Table 3 - 4 Non - linear load step change simulation parameter ................................ ............... 62 Table 3 - 5 Simulation parameter for V2L DC mode ................................ .............................. 65 Table 3 - 6 Hardware setup parameter for V2L DC LOAD ................................ ................... 68 Table 4 - 1 Three phase V2G simulation parameter ................................ ............................... 85 Table 5 - 1 Three phase G2V simulation parameters ................................ .............................. 89 Table 5 - 2 Single phase G2V simulation parameters ................................ ............................. 92 Table 5 - 3 Single phase G2V hardware test parameters ................................ ......................... 94 x LIST OF FIGURES Figure 1 - 1 Existing traditional OBC ................................ ................................ ...................... 2 Figure 1 - 2 Single stage on OBC ................................ ................................ ............................ 3 Fi gure 1 - 3 Universal Power Converter Building Block (PCBB) Circuits ................................ 4 Figure 1 - 4 Proposed operation modes ................................ ................................ .................... 5 Figure 2 - 1 Materials property of Si Vs SiC Vs GaN ................................ ............................... 9 Figure 2 - 2 Indications of each features ................................ ................................ .................. 9 Figure 2 - 3 SiC Half bridge Power module ................................ ................................ ........... 10 Figure 2 - 4 Turn On/Off time ................................ ................................ ............................... 11 Figure 2 - 5 MOSFET Parasitic Capacitance ................................ ................................ .......... 12 Figure 2 - 6 Parasitic capacitance vs VDS ................................ ................................ .............. 12 Figure 2 - 7 Switching loss vs Drain current ................................ ................................ .......... 13 Figure 2 - 8 Typical Gate drive structure ................................ ................................ ................ 14 Figure 2 - 9 Gate Charge Curve ................................ ................................ ............................. 14 Figure 2 - 10 Gate drive isolated power supply ................................ ................................ ...... 15 Figure 2 - 11 Gate drive IC sections ................................ ................................ ....................... 16 Figure 2 - 12 Gate drive amplifier buffer section ................................ ................................ ... 17 Figure 2 - 13 Gate drive board with SiC power module ................................ ......................... 18 Fi gure 2 - 14 Double pulse test setup ................................ ................................ ..................... 18 Figure 2 - 15 Lower MOSFET Double pulse test result ................................ .......................... 19 Figure 2 - 16 Upper MOSFET Double pulse test setup ................................ .......................... 20 Figure 2 - 17 Vds and Drain Current ................................ ................................ ...................... 20 xi Figure 2 - 18 I - V electrical output characteristics ................................ ................................ ... 21 Figure 2 - 19 Desat trigger level verficiation ................................ ................................ .......... 22 Figure 2 - 20 Active miller current injection ................................ ................................ .......... 23 Figure 2 - 21 Sensors in the system ................................ ................................ ........................ 24 Figure 2 - 22 Current sensor signal conditioning circuit ................................ ......................... 25 Figure 2 - 23 AC Voltage sensor signal conditioning circuit ................................ .................. 26 Figure 2 - 24 DC Voltage sensor signal conditioning circuit ................................ .................. 27 Figure 2 - 25 Digital control system: control card and interface board ................................ .... 28 Figure 2 - 26 Energy density VS Power density (Electrolytic Cap and Film Cap) .................. 29 Figure 2 - 27 Hybrid DC link capacitors ................................ ................................ ................ 30 Figure 2 - 28 Electrolytic cap and Film Cap ................................ ................................ ........... 30 Figure 2 - 29 Dual active bridge ................................ ................................ ............................ 33 Figure 2 - 30 Power Flow Model of SPS ................................ ................................ ................ 34 Figure 2 - 31 Gating Signals and Voltage/Current Waveforms of SPS ................................ ... 34 Figure 2 - 32 Power Flow Model of DPS ................................ ................................ ............... 35 Figure 2 - 33 Gating Signals and Voltage/Current Waveforms for DPS ................................ . 35 Figure 2 - 34 Algorithm flowchart for optimal Turns ratio for minimum current stress .......... 37 Figure 2 - 35 Minimum Current Stress at one operating point . ................................ ............... 38 Figure 2 - 36 Turns ratio vs Current Stress over Battery Voltage range. ................................ . 38 Figure 2 - 37 Transformer T - Shape Model ................................ ................................ ............. 39 Figure 2 - 38 Core Flux Shape Under DPS ................................ ................................ ............ 39 Figure 2 - 39 Generalized transformer design flowchart ................................ ......................... 40 Figure 2 - 40 Core flux waveform ................................ ................................ .......................... 42 xii Figure 2 - 41 Isolation transformer ................................ ................................ ......................... 42 Figure 2 - 42 Transformer isolation test ................................ ................................ ................. 43 Figure 2 - 43 Transformer parameter measurement ................................ ................................ 43 Figure 2 - 44 Filtering inductor core AL value ................................ ................................ ....... 44 Figure 2 - 45 Complete Prototype ................................ ................................ .......................... 46 Figure 2 - 46 V2G Test setup ................................ ................................ ................................ . 46 Figure 2 - 47 V2L Test setup ................................ ................................ ................................ . 46 Figure 2 - 48 G2V Test setup ................................ ................................ ................................ . 47 Figure 3 - 1 V2L AC load ................................ ................................ ................................ ...... 48 Figure 3 - 2 V2L DC load ................................ ................................ ................................ ...... 48 Figure 3 - 3 V2L AC Linear Load control diagram ................................ ................................ 50 Figure 3 - 4 V2L DC Load control diagram ................................ ................................ ........... 51 Figure 3 - 5 Modeling workflow of power converter ................................ .............................. 52 Figure 3 - 6 Simplified model of DAB ................................ ................................ ................... 53 Figure 3 - 7 Waveforms of single phase shifted DAB ................................ ............................ 53 Figure 3 - rm ................................ ....................... 56 Figure 3 - 9 Open loop test DAB waveforms ................................ ................................ ......... 56 Figure 3 - 10 Inverter wavefrom during the change of primary voltage from 80V to 140V ..... 57 Fi gure 3 - 11 DAB waveform during the change of primary voltage from 80V to 140V ......... 58 Figure 3 - 12 Zoomed in verion of dynamic change during jump up ................................ ...... 58 Figure 3 - 13 Inverter wavefrom during the change of primary voltage from 140V to 80V ..... 59 Figure 3 - 14 D AB waveform during the change of primary voltage from 140V to 80V ......... 60 Figure 3 - 15 Zoomed in verion of dynamic change during jump down ................................ .. 60 xiii Figure 3 - 16 Simulation of Inverter under step linear load change ................................ ......... 61 Figure 3 - 17 Load voltage(top) and load current(bottom) under step load change .................. 62 Figure 3 - 18 Simulation of Inverter under step non - linear load change ................................ .. 63 Figure 3 - 19 L oad voltage(top) and load current(bottom) under step non - linear step load change ................................ ................................ ................................ ................................ .. 63 Figure 3 - 20 Large filtering inductance and with small resistance load ................................ .. 64 Figure 3 - 21 Bode plot of variance of internal filtering inductance ................................ ....... 65 Figure 3 - 22 Simulation of Interleaved Buck (Multiphase Buck) ................................ ........... 66 Figure 3 - 23 Gating signal of Leg 1, Leg 2 and Leg 3. ................................ .......................... 67 Figure 3 - 24 Inductor current of Leg 1, Leg 2, Leg 3 (Top), and output voltage (Bottom) ..... 67 Figure 3 - 25 Zoomed in version of inductor current and output voltage ................................ 68 Figure 3 - 26 Gating signal of multi - phase step down operation ................................ ............. 69 Figure 3 - 27 Output voltage and current waveform ................................ ............................... 69 Figure 3 - 28 Each phas e leg current and resultant current ................................ ..................... 70 Figure 4 - 1 V2G Three phase operation mode ................................ ................................ ....... 72 Figure 4 - 2 V2G Single phase operation mode ................................ ................................ ...... 72 Figure 4 - 3 Four operation modes of grid imposed VSI converter ................................ ......... 74 Figure 4 - 4 Three phase gr id - imposed averaged Model of VSC ................................ ............ 74 Figure 4 - 5 Phasor form of dynamics between VSC and grid ................................ ................ 75 Figure 4 - 6 Three phase phased - lock loop ................................ ................................ ............. 75 Figure 4 - 7 d - q frame grid - tied current controller ................................ ................................ .. 77 Figure 4 - 8 Decoupled d (q) axis current controller ................................ ............................... 77 Figure 4 - 9 Bode plot of the d (q) axis plant with PI controller ................................ .............. 79 Figure 4 - 10 Outer voltage loop with inner current loop ................................ ........................ 80 xiv Figure 4 - 11 Bode plot of voltage loop controller ................................ ................................ .. 80 Figure 4 - 12 Single phase phased - lock loop ................................ ................................ .......... 81 Figure 4 - 13 Single phase V2G control diagram ................................ ................................ ... 82 Figure 4 - 14 Three phase V2G control diagram ................................ ................................ .... 84 Figure 4 - 15 Three phase V2G simulation ................................ ................................ ............. 85 Figure 4 - 16 DC bus voltage during transients ................................ ................................ ...... 85 Figure 4 - 17 Battery current ................................ ................................ ................................ .. 86 Figure 4 - 18 Grid current and voltage ................................ ................................ ................... 86 Figure 5 - 1 Three phase G2V operation mode ................................ ................................ ....... 87 Figure 5 - 2 Single phase G2V operation mode ................................ ................................ ...... 87 Figure 5 - 3 Three phase G2V control diagram ................................ ................................ ...... 88 Figure 5 - 4 Single phase G2V control diagram ................................ ................................ ..... 89 Figure 5 - 5 Three phase active PWM rectfier simulation ................................ ....................... 90 Figure 5 - 6 Three phase PFC Grid voltage and current ................................ .......................... 90 Figure 5 - 7 Three phase Id and Iq current controller performance ................................ ......... 91 Figure 5 - 8 Three phase output voltage ................................ ................................ ................. 91 Figure 5 - 9 Single phase PWM rectifier simulation ................................ ............................... 92 Figure 5 - 10 Single phase grid voltage current (top) and output DC voltage (bottom) ........... 93 Figure 5 - 11 Single phase id and iq current controller performance ................................ ....... 93 Figure 5 - 12 Verification of PLL ................................ ................................ .......................... 94 Figure 5 - 13 Noisy Current controller ................................ ................................ ................... 95 Figure 5 - 14 Working current controller ................................ ................................ ............... 95 1 Chapter 1 Introduction 1.1 Research motivation of u niversal bidirectional converter Electric vehicle (EV) is gaining more attention from customers due to its ample compelling futures such as environment friendly technology, lower cost per mile, and competiti ve driving performance. What is more, EV can extend more functionalities besides of being only the transportation facility. Nowadays, EV with a few tens of kWh battery is the perfect candidate for smart and green home system. Hence, there is of great need to equip EV with certain power converters to make it qualified and capable for this important role as the power hub in such system. However, most of the designs are fixed output which increase more component cost whenever additional output or feature are n eeded. I n the next generation modern home - based micro grid system, EV can play multiple roles beyond transportation. For example, EV can send active power back to grid, which can help reduce the power grid burden during peak hour. EV can also improve the d istribution power grid quality by sending reactive (either inductive or capacitive) power to the grid especially where heavy unbalanced load is connected. The power flow interaction between the vehicle is often recognized as G2V (Grid to vehicle or chargin g mode) or V2G (vehicle to grid). Not only does EV can help stabilize the grid, but also it can benefit the home appliance by providing robust AC (single phase or three phase) or DC output for various loads whenever the main line is not available. However, these application scenarios would not be feasible if there is no such universal power converter to facilitate the power flow . A modular and universal power converter is of great need to achieve this goal. Hardware design flexibility and scalability is ver y important which allows configurations into different ways to accomplish various functions mentioned above. With different combinations of modularized power converter building block (PCBB), various voltage and power rating can be achieved. This 2 converter can output different types of voltage, such as AC or DC, high voltage or low voltage, single - phase or three - phase. limited space inside the EV, the converter needs to be as compact as possible. The size of the converter is determined by several factors, such as the cold plate, the power devices, the capacitors, and the magnetics components such as common mode chokes, the line inductor, and the transformer. The ideal format of switching is no conduction loss which means that there is no voltage drop and turn on resistance during on state, and no switching loss during on/off transition. However, there is no such ideal device. Fortunately, the appearance of wide band ga p device can improve the performance of switching power device and that will lead to faster switching with higher current and voltage while generating less power loss. To explore the potential of the benefit of adopting wide band device in the automotive a pplications, SiC power module is selected as the switching device of the converter. 1.2 Existing on - board charger review Figure 1 - 1 Existing traditional OBC The most common charger [1] in side EV is a two - stage single phase charger. The first stage is AC - DC which consists of rectifier and DC - DC converter to regulate the current to perfor m power factor correction function . Extensive review s of different PFC topologies are summarized in [ 2] ~ [4] . 3 The second stage is isolated DC - DC converter. Options for isolated are numerous, such as flyback , push - pull, full - bridge, resonant LLC, and dual active bridge converters. Some of them are good for low power applications, while others are more suitable for hig h power application. Comprehensive reviews of isolated DC - DC converter are summarized in [5] ~ [8]. There also exists single - stage on - board charger [9] ~ [19] . It chops the grid 50/60Hz power into much higher frequency and sends the power through a high f requency transformer whose secondary rectifies the AC power to DC charging the batter y shown in Fig 1 - 2. Figure 1 - 2 Single stage on OBC The common charging profiles used in the industry for Li - ion batteries are constant current (CC) and constant voltage (CV) charging. During CC charging, the current is regulated at a constant value until the battery cell voltage reaches a certain voltage level. Then, the charging is switched to CV charging, and the battery is charged with a trickle current applied by a CV . For OBC, it should be able to provide both CC and CV mode operation capability. 1.3 Proposed SiC bidirectional universal power converter In this thesis , a unique circuit topology with isolation is p roposed to perform various essential functions in single unit such as grid to vehicle on board charging (G2V), vehicle to grid connection (V2G), and vehicle to load (V2L). The proposed circuits in this thesis is composing 8 half bridge legs and it is shown in Fig1 - 3 . P1 to P4 and S1 to S4 along with the transformer in between are known as dual active bridge (DAB) . The Q1 ~ Q8 are acting as the grid side 4 switches or load switches. Q7 and Q8 serves the purpose of neutral connection when working with 3phase 4 wire system. Figure 1 - 3 Universal Power Converter Building Block (PCBB) Circuits The high voltage battery is connected between T9 and T0. The battery has a range of 250V to 450 V . The T1, T2, Tx, and Ty are referred as the load or grid terminals. Depending on what is the load , the PCB B will be configured into different ways as shown in Fig. 1 - 4 . Applications Connection Single Phase AC /Load T1, T2 paralleled as Line Tx, Ty paralleled as Neural Three Phase AC System / Load T1 as line, T2 as line Tx as line, Ty as neutral 48V (Low) DC Load T1 T2 paralleled as Positive T4 as negative Table 1 - 1 PCBB Rated Power Under Different Applications 5 Figure 1 - 4 Proposed operation modes 1.4 Scope of the thesis This thesis is to solve the challenges of integrating all functions into single unit. It covers the hardware design, modeling analysis and control design. The dissertation is focused on the following subjects to demonstrate the idea of universal power converter . Chapter 2 describes prototype hardware detail including the gate drive, passive components and the digital control platform . Chapter 3 explains the control principle and shows simulation and testing results of V2L (AC load or DC load) mode to verify the functionality . 6 Chapter 4 explains the control principle and shows simulation and testing results of V2G (ac tive power or reactive power) mode to verify the functionality . Chapter 5 explains the control principle and shows simulation and testing results of G2V (single phase or three phase) charger mode to verify the functionality . Chapter 6 discusses the conclusion and future work . 7 Chapter 2 Hardware design of the PCBB 2.1 Selection of Power MOSFET 2 . 1 .1 Wide band gap devices The advances in WBG power devices [43] enables deliver y of dramatic improvements in performance as well as new capabilities, which are not possible with silicon - based devices. Since SiC based semiconductor generally can endure higher voltage and carry larger current, SiC MOSFET is selected as the switching device in this work. An ideal power switch will possess the following characteristics: Able to carry large current with zero voltage drop in the on - state ; Block s high voltage with zero leakage in the offstate ; n duce s zero energy loss when switching fr om off - to on - state and vice versa With silicon, it is difficult to combine these desirable yet opposed characteristics, especially at high voltage and current. For example, at breakdown voltage 800V or even higher, the channel resistance along with forward voltage drop is very high because of the large drift region required to withstand such voltage. Insulated Gate Bipolar Transistor (IGBT) [43] devices were hence developed to address this problem. For the case of IGBTs, low resistance at high break down voltage is achieved at the cost of switching performance. Minority carriers are injected into the drift region to reduce conduction (on - ) resistance. Due ten times higher than that of silicon, SiC devices can be constructed to withstand the same breakdown with a much smaller drift region. which is the case with IGBTs when turned off and hence impose the switching speed of IGBT . SiC MOSFETs, 8 t herefore, combine and integrate all three desirable characteristics of power switch, such as low on - resistance, high breakdown voltage, and fast switching speed. size means smaller parasitic capacitances. The improvement in turn - off is due to absence of tail current in the MOSFET. The improvement in turn - on is due to the much lower recovery loss of the SiC diode . presents excellent reverse recovery pe rformance, which is equal to the performance of discrete SiC SBD. Due to the nature of . Additionally, properties can help lower cooling needs, making it simpler to cool SiC components. This leads to supporting thermal systems that can be smaller, lighter and lower cost. What is more , the electrical characteristics of SiC MOSFETs do not vary with temperatur e as much as silicon MOSFET [43]. The difference compared to silicon device can be summarized into Fig 2 - 1 and Fig 2 - 2. In general, low switching losses with SiC MOSFET can bring significant benefits and these are elaborated below: er losses can incur less heat generation, which leads into smaller, and even lighter cooling systems and ultimately higher power density. Reduced switching losses can enable switching frequency to increase to further shrink the sizes of passive components ( such as capacit ors, inductors and even transformers ), reducing system cost, size, and weight (higher power density) . temperature under which components do not have to be derated and permits smaller, less expensive components to be used. 9 Figure 2 - 1 Materials property of Si Vs SiC Vs GaN Feature Indication Breakdown Electric field [MV/cm] High Voltage Operation Band gap width [eV] Thermal Conductivity [W High Temperature applications Melting point [x 10 3 K] Saturation velocity [10 7 cm/s] High frequency operation Figure 2 - 2 Indications of each features 2 . 1 . 2 Selected SiC Power MOSFET Key Characteristics The selected MOSFET BSM120D12P2C005 shown in Fig 2 - 3 is from Rohm semiconductor [23] . Its key parameters have been summarized into table 2 - 1. 10 Figure 2 - 3 SiC Half bridge Power module Parameter Value Drain - source voltage 1200V Drain Current 134A (DC) 240A (Pulsed) Max Junction Temperature 175 °C Vgs Threshold Voltage 2.3V Td(on) turn on time 45 ns Td(off) turn off time 170 ns Gate charge 5 7 0 n c Rds ON 15 mOhm Turn on Loss 3.2 mJ Turn off Loss 1.5 mJ Table 2 - 1 Maximum rating and electrical c haracteristics 1200V and 134A SiC half bridge power module is selected since the maximum DC bus voltage is 700V (considering switching transient voltage spike 50% margin is given) and the maximum current under full load is 1 3 0A which is only happening for short intervals and will not incur thermal issue per the pulsed current rating . Vgs is indicating at what voltage level the MOSFET is start being ON which allows current to flow and rise. 11 Turn o n time and turn off time is defined as shown in Fig 2 - 4 per data sheet [23]. The double pulse result gives the actual switching transient in this setup. The gate charge is used to calculate the power needed to switch on the device at certain frequency. Associated with that is the input capacitance Ciss which is defined in Fig 2 - 5 . The parasitic capacitance is highly nonlinear regarding the drain - source voltage as shown in Fig 2 - 6. On resistance is another important factor when selecting MOSFET because it is indicating the conduction loss . Switching loss data can be calculated from the measurement on the actual prototype . Normally this information can be also found in the data sheet known as Eon and Eoff in Fig 2 - 7 . Figure 2 - 4 Turn On/Off time 12 Figure 2 - 5 MOSFET Parasitic Capacitance Figure 2 - 6 Parasitic capacitance vs VDS Symbol Expression Meaning Ciss Cgs+Cgd Input capacitance Coss Cds+Cgd Output capacitance Crss Cgd Feedback capacitance 13 Figure 2 - 7 Switching loss vs Drain current 2. 2 Design of SiC gate driver The gate drive serves an important role: turn on/off the power MOSFET with proper protection . The principle is to take the PWM signal (mA level) from the control and then amplify to driving current (A level). The gate drive should be isolated from the digital control system and provide enough protecti on features to prevent the converter from faulty operation. Detailed design can be found in the following sections. 2 . 2 .1 Gate drive topology The gate drive normally consists of two parts as shown in Fig 2 - 8 [ 47 ] : isolated power supply to power the gate drive and provide the power needed for switching on/off the device; gate drive IC (sometime with amplifier buffer IC) to amplify the current through an isolated channel (isolated methods can be capacitive or inductive) 14 Figure 2 - 8 Typical Gate drive structure For the selected SiC MOSFET, the positive turn ON gate bias voltage is Vdd2 = 19V, and the negative turn OFF gate bias voltage is Vss2 = - 5V. Based on the gate charge curve provided in the datas heet in Fig 2 - 9 , the power needed to drive the MOSFET at switching can be found. Figure 2 - 9 Gate Charge Curve 15 ( 2 - 1) 2.7W (2 - 2 ) Hence, we need a n isolated power supply whose power rating is 3W and can generate dual output. Final selection comes down to the PQMC3 - D24 - D12 - S [ 45 ] . Gate drive IC is another important piece which takes cares of switching ON/Off dynamics. There are several key factors which needs extra cautions such as isolation type, source/sink current level, propagation delay , common mode transient injection ( CMTI), undervoltage lockout protection, active miller clamp, D esat protection and soft shunt down . After detailed comparison , the final selection fall s to ADuM4135 [ 46 ]. Section 2.2.2 will disclose the gate drive design proposed in this thesis. 2 . 2 . 2 Gate drive schematics Figure 2 - 10 Gate drive isolated power supply In Fig 2 - 10, positive 19V and negative 5V is generated from the off - shelf power supply [ 45 ]. 5.1V Zener diode is placed between the power supply middle point output and the power supply negative rail output . 16 Figure 2 - 11 Gate drive IC sections The gate drive IC Vdd1 is connected to 5V. Ready signal ( ) is indicating the IC has no UVLO or Desat fault. Ready signal is not latched. It is pulled by R 2 (10kohm resistor). Fault is indicating that Desat fault is detected. Once detected, the IC will be latched. Reset can clear the fault. Both fault and reset are pulled by R3 and R4. The IC protects the circuit with extra caution to avoid shoot through under half - bridge configuration. V1+ is the PWM signal for the MOSFET being driven. V1 - is the PWM signal for complimentary MOSFET . When the IC detects both V1+ and V1 - are high, it will shut down the gating to prevent shoot through. In this design, extra deadtime compensat ion has been added to the PWM signal path of V1 - . R23, SD4, and C16 will determine the delay. SD2 and SD3 are Schottky diode which protects the V dd2 from voltage spike over the maximum rated voltage. Z3 and Z4 are Zener diode which functions the same. Th ey clamp the gate - source voltage not exceeding +22V and - 6V. R9, R7, C14, Z2, and D2 are for Desat protection which will be explained later. 17 Gate_Sense pin is connected to MOSFET Detailed explanation is the later section. In order to provide enough source/sink current for turning ON/OFF the switch, additional resistor are used as gate resistor (effective gate resistance 4 ) for thermal concern as shown in Fig 2 - 12. Final gate drive board with SiC half bridge is shown in Fig. 2 - 13. Figure 2 - 12 Gate drive amplifier buffer section 18 Figure 2 - 13 Gate drive board with SiC power module 2 . 2 . 3 Gate drive test (Double pulse) results Figure 2 - 14 Double pulse test setup Double pulse test is used to examine the gate drive driving capability, protection features, MOSFET on /off transient details and estimate the bus bar leakage inductance. In Fig 2 - 15, Ch1 is Vds , Ch3 is inductor current, and Ch4 is the Vgs. Fig 2 - 15 (a) Shows the double pulse results, (b) shows the turn on and the turn off detail. The gate drive can switch at 500V DC bus with 120A in the switch . (c) and (d) extends closer look at the ON/OFF transient , from which the turn on time can be found as 170ns and turn off time as 250ns. 19 (a) (b) (c) (d) Figure 2 - 15 Lower MOSFET Double pulse test result In order to examine the bus bar leakage inductance, the drain current from the MOSFET is measured using Rogowski coil. Due to the package limitation of the SiC power module, the double pulse test will be performed on the upper switch as shown in Fig 2 - 16 . To avoid the inductor saturation problem during high current test, air core inductor is adopted. 20 Figure 2 - 16 Upper MOSFET Double pulse test setup (a) (b) Figure 2 - 17 Vds and Drain Current In Fig 2 - 17, Ch1 is the upper switch Vds, Ch2 is the current (notice the polarity). Loop inductance can be calculated by finding the sharpest di/dt and the corresponding V ( ) . Estimated loop inductance is 100nH. 21 2 . 2 . 4 Gate drive protection feature Under voltage lockout (UVLO) : When the IC detects the primary side Vdd1 is below 2.3V, the Ready pin will be driven to Low. When the IC detects the secondary side Vdd2 is below 11V, the Read pin will be drive to Low. This is not a latch ed fault, when the voltage is above the thre shold level, the IC will be Ready again. Desat protection : Des at is used to detect the over current fault inside the MOSFET. The principle is that the Vds across the MOSFET when the device is conducting current will show different values depending the cur rent conducting . A nd this voltage value can be used in the desat protection loop to help indicate and detect whether there is over current happening. This relationship between current and voltage can be found in the I - V curve as shown in Fig 2 - 18. Figure 2 - 18 I - V electrical output characteristics 22 The designed desat trigger level is 1 7 0A and the 2. 6 V Vds can be found correspondingly. When the ON signal is applied to the gate drive, the internal desat comparator is enabled. When (set by the IC) , fault will be triggered. However, there is 6 . 8 V difference between the IC threshold value. R9, R7, Z2 and D2 will compensate that difference. Here is how: 7V ( 2 - 3) (close to 6.8 V, considering the components tolerance ) To verify the desat trigger level, double pulse test is performed. The pulse width is designed to incur 170A during the middle of the second pulse. Test r esults are summarized in Fig 2 - 19. Fig 2 - 19 (a) shows that 150A can not trigger the fault and the second pulse runs completely for 5us. Fig 2 - 20 (b) demonstrates that the during the middle of 2 nd pulse, 170A is reached and the 2 nd pulse stops the middle wh ich indicates the gate drive shunts down the gating. (a) (b) Figure 2 - 19 Desat trigger level verficiation 23 Active miller clamping : With high speed switching used in high voltage/power system, extra caution needs to be placed on the CMTI performance of the gate drive . For example, when the lower switch is off and the upper switch is turning on, there exists high dv/dt which will be imposed upon Cgd. The dv/dt will incur current (Active miller current) through Cgd and effectively generate voltage spike after Rg - 20. Figure 2 - 20 Active miller current injection Active miller clamping feature will be very important when the voltage spike is above switch threshold voltage. Hence, the IC selected has a 2V trigger level, which means that when Gate_sense gets above 2V when the switch is supposed off. The clamp switch inside IC will clamp the gate voltage to ground preventing false turning on. This protection also helps the eliminat ion of - - through. In this design, the peak DC bus voltage will be 700V and the top switching speed will be 200kHz, the effe ctive dv/dt is 3.5kV/us. The gate drive selected has a CMTI up to 100kV/us. 24 2. 3 Controller board and controller interface board 2 . 3 .1 DSP control board In this project, TI launch pad [ 62 ] is used as the DSP control platform , s ince it can provide 16+ PWM and 10+ ADC channels. The ADC range is 0~3V and additional sensor feedback signal conditioning is needed to process and do the level shifting before being sent to ADC. The PWM voltage level is 3V and the gate drive needs 3.5V to be recognized as High. Hence level shifting is required before PWM signal being sending to gate drive. 2 . 3 . 2 Sensors in the prototype Figure 2 - 21 Sensors in the system To fully control the system, there are 5 current sensors and 5 voltage sensors whose placement are shown in Fig 2 - 21. Current sensors: LEM LA205 - S is used to sense the current, the sensors output is connected to a signal conditioning circuits shown in Fig 2 - 22. The output of the current sensor i s also current whose conversion ratio is 1:2000, and the peak sensing current is set to be 150A. After passing through R1 60 ~ R1 63 , Vac will be imposed on R159 . Applying superposition of op - amp: 25 Assuming 1.5V - > 0 : ( 2 - 4) ( 2 - 5) Assuming - > 0 : ( 2 - 6 ) ( 2 - 7 ) In the end, the output voltage being sent to ADC is: ( 2 - 8) Hence, the signal sent to ADC will be a votlage signal whose amplitude is 3V and middle point is 1.5V . Figure 2 - 22 Current sensor signal conditioning circuit 26 AC Voltage sensors: The high voltage has been converted to a low voltage signal after being divided through a series of resistor . The signal condition circuit is shown in Fig 2 - 23. Figure 2 - 23 AC Voltage sensor signal conditioning circuit Applying superposition of op - amp: ( 2 - 9 ) ( 2 - 10 ) Assuming - > 0: ( 2 - 11 ) ( 2 - 12 ) Assuming - > 0: ( 2 - 1 3 ) 27 ( 2 - 14) In the end , the output voltage being sent to ADC is ( 2 - 1 5 ) D C Voltage sensors: T he high voltage has been converted to a low voltage signal after being divided through a series of resistor. The signal condition circuit is shown in Fig 2 - 2 4 . Figure 2 - 24 D C Voltage sensor signal conditioning circuit Applying superposition of op - amp: ( 2 - 16 ) ( 2 - 1 7 ) Assuming - > 0: ( 2 - 1 8 ) 28 ( 2 - 1 9 ) Assuming - > 0: ( 2 - 20 ) ( 2 - 21 ) In the end, the output voltage being sent to ADC is ( 2 - 22 ) 2 . 3 . 3 Interface board between DSP and Gate drive boards This interface board in Fig 2 - 25 carries other function s such as : Signal routing bridge between the control board and the gate drive boards; Provide 24V and 5V to the gate drive boards; o Off - shelf isolated 5V - 12W, 24V - 50W and ± 15V - 6W power supplies are use d on this board [63] ~ [65] . LED indications of gate drive status; Power supply for all the auxiliary circuits. Figure 2 - 25 Digital control system: control card and interface board 29 2. 4 DC link capacitors selection One of the challenges in the universal converter design is that the DC bus should be able to accommodate different working modes such as single - phase AC or three phase AC and handle various level of ripple current such as switching ripple and 2 ripple. He nce, hybrid bus bar is designed to host all the operation modes as shown and highlighted in Fig 2 - 27 . Figure 2 - 26 Energy density VS Power density ( Electrolytic Cap and Film Cap) To summarize, electrolytic caps are higher energy density compared to film cap and film caps are higher power density which means have higher ripple current rating as shown in Fig 2 - 2 6 which is generated from datasheet of different manufacturer by web crawling script . El ectrolytic caps are better option to absorb the 2 ripple power, and film caps with low ESL and ESR are considered t o absorb the high switching ripple power . From Table 2 - 2, the DC link caps needs to handle at least 700V. Another important information f or the DC link caps selection is the voltage on the DC bus since the converter needs to work under different operation modes which are summarized in Table 2 - 2 . The power level is defined per the design requirement. 30 Case Applications Power level DC Bus Voltage Peak A 120V Single Phase AC 3.2kW (Level 1) B 24 0V Single Phase AC 7.8kW (Level 2) C 208 V Three Phase AC 20kW (Level 2) 294V D 480 V Three Phase AC 25kW (Level 2) 678V E 48V DC 10kW 400V Table 2 - 2 Operation modes Figure 2 - 27 Hybrid DC link capacitors (a) (b) Figure 2 - 28 Electrolytic cap and Film Cap 2 . 4 . 1 Electrolytic Capacitors bus bar 2 c apacitance needed can be found in [36], [57] ~ [6 1 ]. 31 ( 2 - 23 ) ( 2 - 24 ) To leave some margin, two 6800u F caps [ 50 ] are put in series as C1 . C2 has the same capacitance value while theoreti cally there will be no 2w ripple and no need for more caps . If the DC bus voltage can be boosted to a higher value, the required capacitance is smaller. Ripple current: ( 2 - 25 ) ( 2 - 26 ) The electrolytic caps selected has ripple current of 18.6A which has enough safe margin . The electrolytic caps are shown in Fig 2 - 2 8 (a) and electrical characteristics are summarized in T able 2 - 3 . Parameter Value Voltage rating 450 V Capacitance value 6800u F Ripple current 1 8.6A ESR 15m Table 2 - 3 DC link electrolytic cap specs 2 . 4 . 2 Film Capacitors bus bar Switching current ripple absorption capacitance needed can be found in: ( 2 - 27 ) 32 ( 2 - 28 ) Ripple current: ( 2 - 29 ) ( 2 - 30 ) The film caps are shown in Fig 2 - 2 8 ( b ) and electrical characteristics are summarized in T able 2 - 4 . Hence, the primary side needs at least 7 of such capacitors in parallel to absorb the total switching ripple . The secondary side needs 5 of such capacitors to able to absorb the total switching ripple currents. Parameter Value Voltage rating 1000 V Capacitance value 20 uF Ripple current 1 4 A ESR 7m Table 2 - 4 DC link film capacitor specs 2.5 Transformer design The transformer in this unit serves several purposes: (1) galvanic isolation to protect the battery from the load/grid . (2) use leakage inductance as energy transfer component . 33 (3) voltage turns ratio to change voltage and power transfer relationship Figure 2 - 29 Dual active bridge The maximum power transfer inside the DAB [27] from V1 to load is given by ( 2 - 31 ) Some observation can be made (1) larger leakage inductance and switching frequency leads to smaller power transfer ; (2) larger turns ratio results in higher power transfer . Hence, transformer design specs need additional efforts which are explained in the following section s . 2 . 5 . 1 Single phase shift vs Dual phase shift Single Phase Shift (SPS) Single phase shift means that there is a phase shift D (D ) between the primary H bridge and secondary H bridge. Both H bridge legs are 50% duty ratio with no inner phase shift between the legs in one H - bridge. And this would lead to two level voltage waveforms across the transformer windings. Fig 2 - 30 shows the s implified model of DAB. 34 Figure 2 - 30 Power Flow Model of SPS Fig 2 - 3 1 presents a typical operating cycle of DAB. V1 is 700V, V2 (battery voltage) is 350V, the leakage inductance Ls is assumed to be 10 u H, the switching frequency is 100kHz, and the transmitted active power is 25kW which is the case D in Table 2 - 2 . Figure 2 - 31 Gating Signals and Voltage/Current Waveforms of SPS The transmitted power with SPS [27] is summarized in ( 2 - 32 ) Dual Phase Shift (DPS) 35 Dual phase shift means that there is a phase shift D2 between the primary H bridge and secondary H bridge. Both H bridge legs are 50% duty ratio with an inner phase shift D1 between the legs in one H - bridge. And this would lead to three level voltage waveforms across the transformer secondary windings. Fig 2 - 31 shows the simplified model of DAB. Fig 2 - 3 2 presents a typical operating cycle of DAB under DPS. Figure 2 - 32 Power Flow Model of DPS Figure 2 - 33 Gating Signals and Voltage/Current Waveforms for DPS The transmitted power is documented in these two equations 36 ( 2 - 33 - a) ( 2 - 33 - b) 2 . 5 . 2 Turns ratio determination In this converter, turns ratio is selected based on the minimum current stress under the peak power operating modes. Hence, the primary side voltage will be 700V (480V 3 phase) Based upon previous sections conclusion, DPS is selected for relatively small current stress. And the maximum current [ 25 ] is shown in ( 2 - 34 ) ( 2 - 35 ) This converter needs to deliver the rated power over a wide range of battery voltage for example, 275V ~ 375V. The algorithm for finding optimal turns ration over this range is show in Fig 2 - 34. 37 Figure 2 - 34 Algorithm flowchart for optimal Turns ratio for minimum current stress 38 Figure 2 - 35 Minimum Current Stress at one operating point . The black dot in Fig. 2 - 35 is the minimum current for one operating point (P = 25kW, V2= 300V, n = 1) Fig 2 - 3 6 is the plot for the summary of A rray(V2, n ) in Figure 2 - 34 . The x - axis is the battery voltage and the y - axis is the current stress. There are total ten curves from n = 1 to n =2 . T here is a red line which indicates the current limit of the SiC switch. In this design, 130A is chosen. Only the curves with all data points under the red curve can be valid solutions, and it only leave tur ns ratio 1 or 1.1 as the options. In order to have equal current stress and switching loss on both sides, N is chosen to be 1. Figure 2 - 36 Turns ratio vs Current Stress over Battery Voltage range. 39 2 . 5 . 3 Core Flux waveform T here is one equation ( 3 ) known as the transformer equation, where n is the number of turns, A is core are, B is the flux density, K = 4.44 (sine excitation) and K = 4 (square excitation). ( 2 - 36 ) It shows the relationship between core flux density and winding voltage. However, in DAB circuit, the transformer is not seeing either sine excitation or square wave. In this thesis, T - shape transformer model is used for transformer design and analysis as shown in Fig. 2 - 3 7 . Since N =1, total leakage inductance is distributed evenly on both sides. And magnetizing inductance is assumed to be 500uH. When using this T - shape model, design can be more generalized regardless of excitation waveform. Figure 2 - 37 Transformer T - Shape Model After using the T model in Simulink, the voltage across the magnetizing inductance can be found in Fig. 2 - 3 8 . Figure 2 - 38 Core Flux Shape Under DPS With the core flux information, the transformer design process can be started. 40 2 . 5 .3 Design Steps The procedure will be summarized below in the flow chart below in Fig 2 - 39 : Figure 2 - 39 Generalize d transformer design flowchart 2 . 5 . 4 Design example : 41 In order to achieve smaller size, higher saturation flux magnetic material is used. Since the DAB is switching at high frequency, low core loss is curial to improve the efficiency. Comparison of different magnetic material is summarized in previous work [61] . The design specs are listed in table 2 - 5 . Design Specs Value Voltage rating 700V Current rating 130A Leakage inductance 10uH Operating frequency 100kHz Table 2 - 5 Transformer design specs In this design, nanocrystalline material FINEMET F3CC0125 core from Hitachi [47] is used whose Bsat is 1.23T and core loss is lower than silicon - steel commonly used in power transformer . The core area is 545mm 2 , and this information can be appl ied to the algorithm above. The final selection of turns on each side is 10 . This results in Bmax is 0.5T which is smaller than Bsat. And the accumulated wire conductor area is less than the window area. This proves a valid design. The final core flux density is shown in Fig 2 - 40 . Litz wire (6*3*45 AWG 38 braid) is adopted for reduction on high frequency proximity loss . 42 Figure 2 - 40 Core flux waveform 2 . 5 . 5 Transformer test r esults The final transformer assembly result is shown in Fig 2 - 41 . Figure 2 - 41 Isolation t ransformer and secondary side is performed as shown in Fig 2 - 42. 43 Figure 2 - 42 Transformer isolation test Insulation meter shows minimal lea kage current under 2500V which verifies the insulation function. In order to verify the performance and key parameters, short circuit and open circuit test are conducted whose results are shown in Fig 2 - 43 . (a) (b) Figure 2 - 43 Transformer parameter measurement Fig 2 - 43 (a) is the short circuit test whose result indicate s leakage inductance value. 22uH is measure result. 44 Fig 2 - 43 (b) is the open circuit test whose result indicate s magnetizing inductance value and turns ratio . 750 uH is measure d result and the turns ratio 1:1 is also confirmed . 2. 6 Filter s design 2 . 6 . 1 Filter inductor design Inductance value is calculated based on work [ 52 ] ~ [54] ( 37 ) where is 100kHz * 2 since for 3 phase inverter the inductor is seeing twice the switching frequency ; is 10% of the rated current which is 0.1*30 = 3 A ; = 700V Using the core selected [55] whose A L is shown in Fig 2 - 4 4 Figure 2 - 44 Filtering inductor core AL value 45 ( 2 - 38 ) 2.6.2 Filter capacitor design The filtering capacitance value is selected based upon the switching frequency of the inverter. The LC filter cutoff frequency should be 1/10 of the . ( 2 - 39) Hence AC film capacitor [56] is selected. 2. 7 Complete prototype The complete prototype is shown in Fig 2 - 4 5 A bench power supply is used to provide auxiliary power needed for the converter. In this setup, a programmable DC source is used to represent the high voltage battery when the converter is operating as V2G and V2L modes. The setup is shown in Fig. 2 - 4 5 an d Fig 2 - 4 6 . Additional caution needs to put when setting up the V2G, since it is equal to connecting two voltage sources together. Current limiting resistors are placed on both grid side and battery side. High voltage diode is inserted before the DC sourc e to prevent current flowing back forward . A relay is also adopted and will be closed after the phased - lock loop is stable. Resistor load bank is adopted to simulate the high voltage battery when the converter is operating under G2V mode as shown in Fig. 2 - 4 7 . 46 Figure 2 - 45 Complete Prototype Figure 2 - 46 V2G Test setup Figure 2 - 47 V2L Test setup 47 Figure 2 - 48 G2V Test setup 48 Chapter 3 Vehicle to Load (V2L) analysis and control 3 . 1 Operation principle of V2L mode In th is operating mode, t he power is flowing from the battery to the load. In the next generation smart - green home, V2L will be a very typical operating case battery to power up the home appliance. Figure 3 - 1 V2L AC load Figure 3 - 2 V2L DC load 49 In this thesis, the AC load is assumed to be in linear nature which means the current will be sinusoidal as well and the current control will not be needed. However, it is common to see non - linear and u nbalanced load such as diode rectifier. To regulate the voltage to under such load conditions will need more advanced control techniques and it is not discussed in this thesis. In the chapter 6, some future work and solutions related to this topic will be discussed. The DC output operation will be able to provide 48V for some on - board appliance to use. Hence, in this thesis, the control will command the converter to generate 48V when the converter is controlled as an interleaved buck mode. 3 . 2 Control ana lysis of V2L mode The converter consists of two stages DAB and inverter, and these two stages are decoupled from each other by the control which will allow separate control. DAB is responsible for transferring power from the battery and stabilizing the pr imary DC bus. Closed loop control on the primary DC bus voltage is needed. Since a 3400uF cap is placed which means a large time constant, a relatively slow control loop whose bandwidth is around 1kHz is high enough to regulate the voltage Inverter is providing the AC voltage to the load by doing the PWM on these phase legs. In this thesis. the most classical s ine PWM is adopted. However, there exists other carrier based PWM which can perform better in terms of switching loss reduction and common mod e voltage re duction which are not covered in this thesis. AC load control objective: As shown in Fig 3 - 3. System control is divided two major loops. 50 DAB voltage loop: it works as inner loop whose bandwidth will be higher than the inverter voltage loop. T he primary DC bus voltage reference is not an easy decision. For example, it needs to be close enough to the battery voltage to minimize the reactive power and current stress inside the DAB to reduce the conduction loss. However, in this thesis, the dc bus voltage is not optimally selected considering this factor, instead the DC bus voltage reference can be modified by the load voltage reference if the DC bus is not high enough to provide the desired load line - line voltage when under highest modulation inde x. This idea is also summarized in Fig 3 - 3 as red loop . The main goal for this loop is to control the phase shift between primary bridge and secondary bridge to realize the power flow hence regulating the primary DC bus voltage. I nverter voltage loop: As mentioned above, the inverter loop may generate a feedforward value to change the DC voltage reference depending on the load voltage requirement. The main goal for this loop is to dynamically change the modulation index to regulate Figure 3 - 3 V2L AC Linear Load c ontrol diagram 51 DC load Control obje c tive : The inverter side switches are working as interleaved buck converter (also known as multiphase buck) . The gating signal is phase shifted between Q1 , Q3, and Q5 while they have the same duty ratio based on the r elationship of . Figure 3 - 4 V2L DC Load control diagram Modeling in power electronics : There are basically two ways to model the time - discontinuous dynamics of converters . One way is to model the converter as a sampled - data system . Another way is to apply the averaging theory to transform the converter as a time - continuous system . The most common averaging approach is to apply the moving average operator, which is also known as the state - space averaging method, to average out the switching dynamics. However, the state - space aver aging model can only indicate the information about converter dynamics 52 below half the switching frequency. To cover and include the switching ripple effect, there are other methods, such as , Krylov Bogoliubov Mitropolsky (KBM) and multifrequency averaging (MFA) . The small - signal linearization is working like approximating a non - linear system at a given operating point with small - signal perturbations. The small - signal averaged model is a good tool for controller design, but its accuracy suffers over high f requency range since it eliminates the high - frequency information through the process of the moving averaging . The small - sig nal averaged model is the most commonly used when analyzing the controller design. The modeling workflow is also summarized in Fig 3 - 5. Figure 3 - 5 Modeling workflow of power converter 3 . 2.1 DAB modeling Perform the state space averaging model analysis on DAB [100] . 53 Figu re 3 - 6 Simplified model of DAB Figure 3 - 7 Waveforms of single phase shifted DAB State space models during four different intervals have been summarized into 3 - 1 and 3 - 4. (3 - 1) 54 (3 - 2) (3 - 3) (3 - 4) 3 . 2.2 VSI Inverter modeling and Multiphase DC / DC (IBC) modeling Under V2L operation mode, VSI and the interleaved buck converter (IBC) can be modeled as the voltage amplifier with gain of duty ratio (modulation index) . When the VSI is interacting with the grid, more dynamics detail needs to be modeled which will be co vered in the next section. 3 . 3 Simulation and Experimental results 3 . 3.1 Three phase r esistive load - Experimental and S imulation results Before the closed loop control is implemented. Open loop test is performed with DAB and inverter together. 55 Hardware Setup Value DAB Switching frequency 10 0kHz Inverter switching frequency 100kHz Load resistance per phase 1 3 Filtering inductance 10u H Filtering capacitance 50uF DAB leakage inductance 22uH DC Source voltage 1 40V Constant phase shift 90 Inverter M odulation index 1 Power level 2kW Table 3 - 1 Open loop prototype test setup parameter Testing conditions: The battery voltage is 140V; the DAB is getting constant 90 phase shift. Since this is V2L operating modes, th e secondary phase legs should be leading the primary phase legs. Without control, the primary voltage is not 140V, it reaches to a stable voltage due to the system power balance with current load setup. The open loop test results are shown in Fig 3 - 8 and Fig 3 - 9. 56 Figure 3 - 8 Ch1 and Ch2 load line - line voltage; Ch3 DC bus voltage; Ch4 load phase current Figure 3 - 9 Open loop test DAB waveforms Ch1 and Ch 3 DAB primary and secondary voltage; Ch 2 Battery current ; Ch4 Leakage current In order to regulate the primary voltage, a PI controller is implemented. To tune and verify the PI gains, some experiments are performed. 57 Hardware Setup Value Switching frequency 100kHz Load resistance per phase 13 Filtering inductance 10uH Filtering capacitance 50uF DC Source voltage 120 V Kp 0.001 Ki 0.5 Inverter modulation index 1 Primary voltage reference 80V < - -- > 140V Table 3 - 2 Closed loop V2L test setup parameter Figure 3 - 10 shows the inverter output during the primary voltage jump up. Figure 3 - 11 shows the DAB waveform during the primary voltage jump up. Figure 3 - 12 shows the DAB zoomed in version of the dynamic jump - up change. It can clearly show that the phase shift angle is increasing and trying to regulate the voltage following the reference. Figure 3 - 10 Inverter wavefrom during the change of primary voltage from 80V to 140V 58 Ch1 and Ch2 load line - line voltage; Ch3 DC bus voltage; Ch4 load phase current Figure 3 - 11 DAB waveform during the change of primary voltage from 80V to 140V Ch1 and Ch 3 DAB primary and secondary voltage; Ch 2 Battery current ; Ch4 Leakage current Figure 3 - 12 Zoomed in verion of dynamic change during jump up Ch1 and Ch 3 DAB primary and secondary voltage; Ch 2 Battery current ; Ch4 Leakage current 59 Figure 3 - 10 shows the inverter output during the primary voltage jump down . Figure 3 - 11 shows the DAB waveform during the primary voltage jump down . Figure 3 - 12 shows the DAB zoomed in version of the dynamic jump - up change. It can clearly show that the phase shift angle is gradually decreas i ng and trying to regulate the voltage following the reference. Figure 3 - 13 Inverter wavefrom during the change of primary voltage from 140V to 80V Ch1 and Ch2 load line - line voltage; Ch3 DC bus voltage; Ch4 load phase current 60 Figure 3 - 14 DAB waveform during the change of primary voltage from 140V to 80V Ch1 and Ch 3 DAB primary and secondary voltage; Ch 2 Battery current ; Ch4 Leakage current Figure 3 - 15 Zoomed in verion of dynamic change during jump down Ch1 and Ch 3 DAB primary and secondary voltage; Ch 2 Battery current ; Ch4 Leakage current The above testes verify that the DAB voltage can be regulated. 61 When the converter operates under V2L modes, it needs to prov AC v oltage no matter what load is connected. Assuming the primary bus voltage is constant by regulating the DAB, simulation of dynamic load change including linear and non - linear load is carried out to help validate the inverter side control al gorithm. Figure 3 - 16 Simulation of Inverter under step linear load change Fig 3 - 1 6 and Fig 3 - 17 shows that the voltage seen by the load is very stiff even though the load current is larger after a load step change . The reason is that the DC source in the simulation is ideal. However, b achieved in the prototype as well . Simulation Parameter Value Switching frequency 100kHz Load resistance 13 Filtering inductance 10uH Filtering capacitance 50uF Table 3 - 3 Linear load step change simulation parameter 62 Table 3 - 3 Inverter modulation index 1 DC source voltage 400V Load step change 0.05s Change ratio 3 times Figure 3 - 17 Load voltage(top) and load current(bottom) under step load change In order to further prove the statement of stiff voltage source, non - linear load (diode bride) is inserted to the system as shown in Fig 3 - 18. The simulation result in Fig 3 - 19 shows that even the current is highly distorted, the output voltage seen by the load is still sinusoidal which is the same case as the grid voltage output. Simulation Parameter Value Switching frequency 100kHz Load resistance 13 Filtering inductance 10 uH Filtering capacitance 50 uF Table 3 - 4 Non - linear load step change simulation parameter 63 Table 3 - Inverter modulation index 1 DC source voltage 400V Load step change 0.05s Change type Add diode rectifier Figure 3 - 18 Simulation of Inverter under step non - linear load change Figure 3 - 19 Load voltage(top) and load current(bottom) under step non - linear step load change 64 Another reason behind the stiffness is the filtering inductance is small, which means the internal impedance of the voltage source is small. If t he load impedance is not comparable to internal impedance, the voltage source inverter can be viewed as ideal voltage source. To further verify the idea, filtering inductance is changed to 10mH and with load resistance is 0.1 ohm. Pronounced voltage drop can be observed in Fig. 3 - 20 , since the load and the internal impedance is working as a voltage divider. Figure 3 - 20 Large filtering inductance and with small resistance load It is also important to point that low filtering inductance can help to improve the system stability with LC filter and reduce the need for resistive damping. The Fig 3 - 21 shows the bode plot of the system LC filter with variable inductance. There is 0.4 resistance distributed on the system which works as the damping resistance in this 2 nd order system . 65 Figure 3 - 21 Bode plot of variance of internal filtering inductance 3 . 3 .2 DC load Simulation and Experiment result In order to verify the multiphase DC - DC operation, simulation is performed first. Assume the DC bus voltage is 200V, and the load voltage will be regulated to 48V. The inductor and capacitor value are the same as the setup which are 10uH and 50uF. The loa d is 1 2 ohm. The legs are switching at 100kHz. The simulation setup is shown in Fig 3 - 22 . Simulation Parameter Value Switching frequency 10 0kHz Phase shift among each leg 120 Load resistance 10 Filtering inductance 1 0u H Filtering capacitance 50uF *3 DC source voltage 2 0 0V Output Voltage reference 4 8 V Table 3 - 5 Simulation parameter for V2L DC mode 66 The legs are having the modulation and carrier signal phase shifted by which is 3.3us . It is also shown in Fig. 3 - 23 . Fig 3 - 2 4 shows each including the start up transient. Fig 3 - 2 1 shows the zoomed in version of the final voltage which shows very minimal voltage ripple. Figure 3 - 22 Simulation of Interleaved Buck (Multiphase Buck) 67 Figure 3 - 23 Gating signal of Leg 1, Leg 2 and Leg 3. Figure 3 - 24 Inductor current of Leg 1, Leg 2, Leg 3 (Top) , and output voltage (Bottom) 68 Figure 3 - 25 Zoomed in version of inductor current and output voltage Hardware experiments is carried out to verify the operation principle. The test setup is as follows: Hardware Setup Value Switching frequency 100kHz Phase shift among each leg 120 Load resistance 10 Filtering inductance 10uH Filtering capacitance 50uF *3 DC source voltage 200V Output Voltage reference 48V Table 3 - 6 Hardware setup parameter for V2L DC LOAD The measured output voltage is 48V with phase - shifted modulation signal. Each modulation signal is phase shifted by 120 and the modulation ratio which is shown in Fig 3 - 2 6 . 69 Figure 3 - 26 Gating signal of multi - phase step down operation The output voltage is 48V (blue curve in Fig 3 - 2 7 ), and the notch is due to the gap between Figure 3 - 27 Output voltage and current waveform 70 Ch1 Output voltage; Ch3 Primary bus voltage; Ch2 Phase leg current; Ch4 Load current Figure 3 - 28 Each p hase leg current and resultant current Ch1 Ch2 Ch3 Phase leg current; Ch4 Resultant current From the experiment results, the stepped down DC bus voltage is very stable, and the current flowing into the load is not sufferi ng huge current ripple. By configuring the inverter into multiphase buck converter enables its wide application in other scenarios . In this section, V2L operation under AC load and DC load are both analyzed and validated with experimental results. 71 Chapter 4 Vehicle to Grid (V2G) analysis and control 4. 1 Operation principle of V2G mode The power is flowing from the high voltage battery to the grid under V2G . In the home - based microgrid, V2G will be a very useful operating case, such as using the car reactive power compensation which can be used to offset the reactive power drawn by certain highly inductive load such as HVAC to save the utility bill. When providing the reactive power compensation and performing the voltage regulat ion, the converter loss is converter by the utility grid and the active power of the battery is not drained ( state of charge is not adversely affected) . What is more, less engagement with the battery can help preserve the battery life. Another important a pplication or feature to help the peak hour load shaving , for example at 6pm in the summer. There are some debates from the automotive company regarding the V2X operation since it will put more stress on the battery and will expediate the battery degrading. However, in this thesis, the adverse effect of V2X to battery will not be discussed. Three phase and single - phase operation modes are shown in Fig 4 - 1 and Fig 4 - 2. 72 Figure 4 - 1 V2G Three phase operation mode Figure 4 - 2 V2G Single phase operation mode To summarize, EV chargers can provide following services to the grid, that can be offered in V2G: 1) peak shaving, 2) harmonic filtering as APF (active power filter), 3) voltage stabilization and support, 4) power factor correction , and 5) reactive power compensation . Also, if the grid electricity is lost, the charger should be capable for islanded operation to feed emergency power which is often called vehicle - to - home (V2H) or vehicle - to - any load (V2X) and it has covered in section 3. Under this operation mode, the converter process power through two stages: 73 Grid - tied inverter : Unlike the inverter in V2L mode, it will need to control the grid current to realize the independent control of active power (P) and reactive power (Q). What is more important, the primary DC bus voltage also needs to be regulated by the inverter control. However, it can also be controlled by DAB and the difference of these two options is not being discussed in this thesis. Isolated dc - dc converter : Unlike the DAB in V2L mode, the DAB will fall into an open loop mode . It generates the phase shift signal b ased on the active power command, and voltage value on both sides of the transformer. In the next section, grid - imposed inverter current controller design and voltage controller design is analyzed thoroughly . 4.2 Grid imposed inverter modeling There are four typical operation modes for gird - connected voltage source inverter as shown in Fig 4 - 3 . V is the grid voltage and I is the gird current (or current out of converter) since VSI is normally operating under current controlled mode. Mode (a): The voltag e and current are in phase and the pf is 1. The active power is flowing into the converter and it is also known as PWM (active) rectifier. Mode (b): The voltage and current are 180 apart and the pf is - 1. The active power is flowing into the grid from the converter. Mode (c): The current is leading the voltage 90 and the pf is 0. The converter is providing capacitive reactive power to the grid. Mode (d): The current is lagging the voltage 90 and the pf is 0. The converter is providing inductive reactive power to the grid. 74 Figure 4 - 3 Four operation modes of grid imposed VSI converter 4 . 2.1 Three phase grid - tied inverter modeling Assumi ng the grid is strong which means the voltage sensed before the inductor is strong. Figure 4 - 4 Three phase grid - imposed averaged Model of VSC 75 Figure 4 - 5 Phasor form of dynamics between VSC and grid Dynamics of the AC side of the VSI can be described by Eq . 4 - 1 (4 - 1) Where L is the coupling inductor and R is the system resistance (distributed on the line or line) . Replace the rotating phasor expression to d - q frame reference system requires a phase - locked - loop. For 3 phase system, the PLL is structured in this way: Figure 4 - 6 Three phase phased - lock loop 76 With PLL, the phase angle and frequency can be applied to decompose rotating phasor form of Eq. 4 - 1 . (4 - 2 ) (4 - 3 ) By using the instantons power theory, the ac tive and reactive power delivered at PCC is (4 - 4 ) (4 - 5 ) If PLL is in a steady state and the grid is not unbalanced , Vsq = 0. The active and reactive power equation can be rewritten as (4 - 6 ) (4 - 7 ) To decouple the cross - dynamics in 4 - 2 and 4 - 3 , feedforward decouple needs to be designed: (4 - 8 ) (4 - 9 ) Hence, the dynamics inside the 4 - 2 and 4 - 3 can be simplified into 77 (4 - 10 ) (4 - 11 ) w here ud and uq are the output from the current controller. Figure 4 - 7 d - q frame grid - tied current controller T he d and q axis current control loop are the same and can be summarized into Fig 4 - 8 Figure 4 - 8 Decoupled d (q) axis current controller Set (4 - 12 ) 78 The open - loop gain is (4 - 12 ) To design the kp and ki to cancel the pole at - R/L. Set kp and ki (4 - 12 ) (4 - 13 ) where is the closed loop time constant and needs to be small for a fast current control response but adequately large such that the bandwidth of the closed - loop control is 10 times higher the switching frequency. The switching frequency is 2 0kHz and the coupling inductor is changed to 1 m H for reduc ed switching frequency. (L = 1mH and R = 0. 1 ohm) can be set to 1/ 2 00kHz which is 2 0 us . k p = 50 and ki = 500. The open - loop bode plot is shown in Fig 4 - 9. 79 Figure 4 - 9 Bode plot of the d (q) axis plant with PI controller This loop has a n 8 kHz open loop bandwidth (closed loop bandwidth will be higher) , infinite gain margin and 91 phase margin to insure the fast dynamics response and stability. ( Note: Gain and phase ma rgins are common terms to describe how stable a system is. Gain and phase margins are used more because they are simple than because they are ideal measurements of stability. Gain and phase margins are measured from the open loop frequency response of the system. Gain and phase margins cannot be acquired directly from a closed loop frequency response. ) DC Voltage loop : The current controller Gi d (s) can be simplified into a constant unity gain since the current loop as much higher bandwidth than the voltage loop (10 times higher) . 80 Figure 4 - 10 Outer v oltage loop with inner current loop We can adopt similar methods for current controller design to apply on voltage loop controller. Kp_v = 0.2 and Ki_v = 10. Figure 4 - 11 Bode plot of voltage loop controller 4 . 2.2 Single phase grid - tied inverter modeling For single phase system, the PL L is structured in a different way with additional orthogonal delay block to generate axis signal which is shown in Fig 4 - 12 . The instantons power definition is also different (4 - 14) 81 (4 - 15) Despite these differen ces , the current controller and voltage controller is the same as three phase system since all the AC voltage and current has been transformed d - q frame . Figure 4 - 12 Single phase phased - lock loop 82 4 . 3 Control Analysis for V2G mode From the discussion above, we can find out that independent active power and reactive power control can be achieved by id and iq respectively. The DAB is sending the phase shift information based on the active power com mand and the voltage levels sensed on both sides of the transformer which are shown in Fig 4 - 13 and Fig 4 - 14 . However, if the primary side DC bus voltage is not stable, power transfer would lose balance and leads to unstable even uncontrollable system. Figure 4 - 13 Single phase V2G control diagram 83 Hence, there is of need to add an other loop to regulate the DC link voltage in the inverter control. What is more, there is another option by regulating the DC link voltage through DAB. The difference of these two is not discussed in this thesis. Another important factor to consider is the DC link voltage. In theory, the DC link voltage cannot be smaller than , and ca n be controlled by id. The value of that als o matters to the following aspects: Current stress in DAB : As shown in Eq (4 - 16), the less difference between V1 and V2, current stress will be reduced which results in lower conduction. (4 - 16) Hence, DC link voltage reference can be set to track the battery to bring down the conduction loss. Switching loss in inverter side : As show in Eq (4 - 17) , the lower of Vds (the DC link voltage), the lower switching loss will be incurred. (4 - 17) Hence, optimum decision needs to be calculated carefully to balance the switching loss and conduction loss reduction. Three phase V2G control principle is only different from single phase V2G: Phase - locked loop design. Instantons power calculation. 84 Figure 4 - 14 Three phase V2G control diagram 4 . 4 Simulation and Experiment results Since V2G is the most complicated scenarios, simulation study is performed first to verify the control algorithm. 4 . 4 . 1 Three phase V2G s imulation results Full scale Simulink simulation is constructed to verify the V2G control algorithm . High level 25kW active power command is given. DC bus voltage is stabilized as shown in Fig 4 - 16 by additional control loop in the inverter current loop control. 85 Real power being sent to the grid is calculated based on the grid voltage and current shown in Fig 4 - 18. Simulation Parameter Value DAB Switching frequency 10 0kHz Inverter switching frequency 50kHz Three phase Grid voltage 480V Coupling inductor 10uH DAB leakage inductance 22 u H Battery voltage 350 V Active power reference 25 kW Reactive power reference 0 kVar Primary DC bus voltage 7 00V Table 4 - 1 Three phase V2G simulation parameter Figure 4 - 15 Three phase V2G simulation ( Time is from 0 to 0.33 s ) Figure 4 - 16 DC bus voltage during transients 86 (Time is from 0 to 0.33 s) Figure 4 - 17 Battery current Figure 4 - 18 Grid current and voltage In this section, V2G operation has been analyzed and validated with simulation results. 87 Chapter 5 Grid to Vehicle (G2V) analysis and control 5. 1 Operation principle of G2V charger The power is flowing from the grid to the high voltage battery in this charging mode . Figure 5 - 1 Three phase G2V operation mode Figure 5 - 2 Single phase G2V operation mode For battery charging operation mode, there are two stages: Front end PFC: The job for this PFC is to regulate the current to reduce the line current distortion, and to control the power factor. 88 Isolated DC - DC: The role for the DC - DC is to regulate the current (Constant current mode) or the voltage (Constant voltage mode) applied to the battery. 5 . 2 Control analysis of G 2 V mode Control principle: As mentioned above, the two stages are decoupled. The DC bus voltage is controlled by the front - end active rectifier. The DAB is controlling the current or voltage by changing the phase shift (Note that the primary gating signal is leading under this mode). Figure 5 - 3 Three phase G2V control diagram In this section, the active power flow at any moment is flowing in one direction. The operation details of r eactive power regeneration to the grid while the battery is being charged is not discussed i n this section. Both three phase and single phase G2V control diagrams are shown in Fig. 5 - 3 and Fig. 5 - 4. 89 Figure 5 - 4 Single phase G2V control diagram 5 . 3 Simulation and Experimental results Since the PFC and DAB is decoupled from the aspects of control, testes and simulation are performed separately. 5 . 3 . 1 Three phase G2V simulation results Simulation study is performed first for 3 phase system front end PFC. Simulation Parameter Value Switching frequency 20kHz Load resistance 10 Coupling inductance 1mH Three phase Grid Voltage 240V Kp 50 Ki 500 Voltage reference 400V Table 5 - 1 Three phase G2V simulation parameters 90 Figure 5 - 5 Three phase active PWM rectfier simulation Figure 5 - 6 Three phase PFC Grid voltage and current 91 Figure 5 - 7 Three phase Id and Iq current controller performance Figure 5 - 8 Three phase output voltage 5 . 3 . 2 Single phase G2V simulation and experiment results Before digital control was implemented, Simulink simulation is conducted first. 92 Simulation Parameter Value Switching frequency 20 kHz Load resistance 10 Coupling inductance 1mH Single phase Grid Voltage 120V Kp 50 Ki 500 Voltage reference 400V Table 5 - 2 Single phase G2V simulation parameters Figure 5 - 9 Single phase PWM rectifier simulation 93 Figure 5 - 10 Single phase grid voltage current (top) and output DC voltage (bottom) Figure 5 - 11 Single phase id and iq current controller performance Single phase G2V e xperimental results: 94 The first step for the PFC is to have a stable PLL. Hence, low voltage open loop test to calibrate the PLL is performed. From Fig 5 - 1 2 , the inverter output is aligned with the grid voltage which means the PLL is working. Hardware Se tup Value Switching frequency 100kHz Load resistance 27 Coupling inductance 100uH Single phase Grid Voltage 120V Kp 0.1 Ki 15 DC Voltage reference 160V Table 5 - 3 Single phase G2V hardware test parameters However, the current is adversely distorted. That is why a closed loop current controller is needed as shown in Fig 5 - 4 . Figure 5 - 12 Verification of PLL Ch1 grid voltage; Ch2 Inverter output; Ch3 grid current; Ch4 DC bus voltage 95 Fig 5 - 1 3 shows the result after a PI current controller is added into the loop. The current is in phase the grid voltage which is the unity power factor that is desired. However, the high frequency distortion is obvious. Fine tuning for the PI gain is perform ed and the result is shown in Fig 5 - 1 4 which clearly shows less distortion . Figure 5 - 13 Noisy Current controller Ch1 grid voltage; Ch2 Inverter output; Ch3 grid current; Ch4 DC bus voltage Figure 5 - 14 Working current controller 96 In this section, the operation of single phase and three phase G2V has been analyzed and validated by the experimental results. 97 Chapter 6 Conclusions , and Future work 6 . 1 Conclusions Robust gate drive with comprehensive protection feature was proposed. Its performance is tested under 600V/130A. Proposed o ptimal parameters design for isolation transformer to cover universal operation modes (3phase or single - phase V2X and G2V ) . Proposed a generalized transformer design method and tested the transformer to verify the design . Proposed the closed loop control algorithm for V2L working with both AC and DC load. Verified the control algorithm for AC load under 1kW total system power rating. Pr oposed the closed loop control algorithm for V2 G working with both single - phase and three - phase including independent P - Q control (active and reactive power) . Verified the control algorithm with Simulink . Proposed the closed loop control algorithm for G2V working with both single phase and three - phase . Verified the control algorithm with Simulink . 6 . 2 Future work Future work can be made in the following aspects: The a ccurate modeling of leakage inductance in transformer design is very important. Finite element analysis is a good approach for the leakage inductance estimation and modeling. Use dual phase shift and other for wider ZVS (zero voltage switching) range is the Dual Active bridge stage to further reduce the switching loss . 98 Configure the AC side switches to Totem - pole PFC to be compared with PWM PFC in terms of efficiency and passive components size . Design coupled inductor for the LC filtering instead of using three independent inductors to further reduce the passive component size. Analyze the influence on DC link voltage ripple by using different modulation methods on the inverter switches such as SPWM and SVPWM. Perform small signal analysis for the DAB bridge and design the controller analytically. When regulating the primary side DC bus voltage under V2G/G2V operating modes, there are two ways either by controlling the inverter/PFC or controlling the DAB. Study the c ontrol d ifference between using between these two options in terms of system stability. When operating under V2L modes, the control methods for providing stiff sinusoidal voltage output with n onlinear load and imbalance load . And there are some suggested approaches such as: Apply repetitive current or predictive control methods to perform fast tracking of the distorted current to do the dynamic compensation . Apply the fourth phase leg to absorb the negative sequence current. There lacks EMI filter in the system on both grid side filter such as common mode chok e and battery side filter for example , Y cap. The battery has a n operating range not a fixed voltage. To maintain low current stress inside DAB, the primary voltage and secondary voltage needs to be as same as possible. What is more , the primary side volt age also can be determined by the grid 99 when operating under V2G/G2V. It would be very important to find the optimum DC bus voltage to reduce the switching loss on both stages. factor when it comes to system optimization since it affects the power transfer, ZVS region, and maximum current stress. Besides that, the switching frequency of both inverter and DAB is another factor determining the system optimum operating point. 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