A MODULAR MULTILEVEL CONVERTER WITH SELF VOLTAGE BALANCING By Yunting Liu A DISSERTATION Submitted to Michigan State University in partial fulfillment of the requirements for the degree of Electrical Engineering—Doctor of Philosophy 2019 ABSTRACT A MODULAR MULTILEVEL CONVERTER WITH SELF VOLTAGE BALANCING By Yunting Liu Modular multilevel converter (MMC) was proposed in 2003 to extend power electronic converters to high voltage applications. Each MMC contains several identical submodules in series. MMC allows redundant submodules since its operation would not be disturbed by redundant submodules. This is a unique feature compared to other types of multilevel converters. In addition, the installation and uninstallation of submodules is easy. This modular feature makes MMC stand out for medium/high-voltage high-power applications. However, as the number of modules increases, the control complexity of voltage balance of each submodule sharply increases. Conventionally, the MMC submodule voltage cannot be balanced by open-loop modulation methods without voltage monitoring and control. This dissertation proposes a Γ-matrix modulation (ΓMM) that completely eliminates the voltage monitoring and control. In another word, the submodule voltage is self balanced. The MMC submodule voltage balancing nature with respect to each switching pattern is comprehensively analyzed in Chapter 2. The mathematical analysis reveals that the MMC is self balanced by nature if considering all possible switching patterns. Based on the enlightenment of Chapter 2, the ΓMM is proposed in Chapter 3 to bridge the gap between mathematical analysis and MMC switching operations. With this novel modulation, the MMC achieves self voltage balancing. The two-, three-, four-, and eleven- level MMCs are studied to verify the effectiveness of ΓMM. Also, compared to the conventional MMC, the ΓMM based MMC has smaller submodule capacitance and smaller arm inductance. This small capacitance and inductance feature extremely reduces the volume and weight of MMC. To understand the mechanisms of the self balance phenomena of MMC, a state-space model of MMC is proposed in Chapter 4. The existing MMC modeling are developed on different degrees of assumptions and simplifications. This makes them unsuitable for understanding the nature of this circuit from its physical basement. Compared to existing MMC modeling, the proposed state-space model well captured the MMC dynamics. With this state-space model, the MMC capacitor voltage convergence and divergence can be well observed. Four-level MMC with both full-rank Γ and non-full-rank Γ are studied to demonstrate that this model could explain both convergence and divergence of the capacitor voltage. In addition, a generalized MMC model is derived. The generalized model can be applied to higher level MMC. An eleven-level MMC case study is provided to verify the proposed model when extended to higher level. The arm inductor voltage assumption is discussed in Chapter 5. To Dr. K. P. Liu, Dr. June Li, Ms. F. Li, Prince Ding, and Mumu. You are and will always be the love of my life. iv ACKNOWLEDGMENTS First of all, I would like to express my sincere thanks to my guidance committee, Dr. Fang Zheng Peng, Dr. Bingsen Wang, Dr. Joydeep Mitra, and Dr. Ranjan Mukherjee. I am so grateful for your mentoring in the discipline of power electronics and helping me grow from a beginner to a professional researcher. I would not have known that I enjoyed doing research so much if I were not assigned with the modular multilevel converter research. Thank you so much for enlightening me to this great topic in my PhD journey. My gratitude also goes to my teaching assistant advisor Dr. Dean M. Aslam, whose help and encouragement always cheered me up. He convinced me that I could possibly become an educator, probably as good as he is. Special thanks go to the Department of Electrical and Computer Engineering and the Office of Institutional Equity at Michigan State University. I could not get my degree without their support. My PhD is partly supported by II-VI foundation and Ford-MSU alliance grant. It is my great honor to work with the research group from Ford. I would like to thank all my colleagues from MSU power group for their valuable inputs towards my research. I would also like to thank all my friends out of the area of power electronics for their caring and friendships in all these years. The last but not the least, I would like to proudly give my special thanks to my family. I have a family of six. Each of them, regardless of their age, gender or species, has set a role model for me in all aspects. There is no word can express my appreciation to them. Their love to me and my love to them are the greatest motivation in my life. v TABLE OF CONTENTS LIST OF TABLES ............................................................................................................. ix LIST OF FIGURES ............................................................................................................ x 1 INTRODUCTION ....................................................................................................... 1 1.1 BACKGROUND .................................................................................................. 1 1.2 PROBLEM DEFINITION ................................................................................... 3 1.3 MOTIVATION BEHIND THE RESEARCH...................................................... 4 1.4 CONTRIBUTION OF THE RESEARCH ........................................................... 5 1.5 DISSERTATION OUTLINE ............................................................................... 5 2 THE SELF-BALANCING NATURE OF MMC CAPACITOR VOLTAGE............. 7 INTRODUCTION ................................................................................................ 7 2.1 TWO-LEVEL MMC CAPACITOR VOLTAGE ................................................ 8 2.2 THREE-LEVEL MMC CAPACITOR VOLTAGE ........................................... 10 2.3 2.4 N-LEVEL MMC CAPACITOR VOLTAGE ..................................................... 14 2.4.1 MASSIVE DATA DILEMMA ................................................................... 17 SUBMATRIX EXTRACTION .................................................................. 18 2.4.2 N-LEVEL MMC CONJECTURE............................................................... 27 2.4.3 COMPUTER-AID PROOF ........................................................................ 28 2.4.4 2.5 CONCLUSION .................................................................................................. 30 3.1 3.2 3.3 3.4 3 Γ-MATRIX MODULATION (ΓMM) ....................................................................... 31 INTRODUCTION .............................................................................................. 31 ΓMM BASED TWO-LEVEL MMC ................................................................. 31 ΓMM BASED THREE-LEVEL MMC .............................................................. 40 ΓMM BASED N-LEVEL MMC ........................................................................ 49 CASE STUDY: ΓMM BASED FOUR-LEVEL MMC .............................. 52 CASE STUDY: ΓMM BASED FOUR-LEVEL MMC WITH NON-FULL- 3.4.1 3.4.2 RANK Γ MATRIX .................................................................................................... 61 3.4.3 CAPACITANCE DEVIATION ................................................................................ 67 3.4.4 CASE STUDY: ΓMM BASED ELEVEN-LEVEL MMC ......................... 68 3.5 DISCUSSIONS .................................................................................................. 76 3.6 CONCLUSION .................................................................................................. 77 CASE STUDY: ΓMM BASED FOUR-LEVEL MMC WITH 4 THE STATE-SPACE MODEL OF MODULAR MULTILEVEL CONVERTER .. 78 4.1 MOTIVATIONS ................................................................................................ 78 INTRODUCTION .............................................................................................. 80 4.2 4.3 PRIOR-ART MMC MODEL ............................................................................. 82 4.4 CONTRIBUTION .............................................................................................. 88 4.5 REVIEW OF Γ-MATRIX MODULATION ...................................................... 89 vi 4.6 4.8 4.7 4.5.1 4.5.2 LEVEL POINTER PREPARATION ......................................................... 90 Γ-MATRIX ADAPTATION ...................................................................... 93 STATE-SPACE MODEL OF TWO-LEVEL MMC ......................................... 95 4.6.1 STATE-SPACE MODEL ........................................................................... 96 4.6.2 STATE-SPACE MODEL WITH STRAY RESISTANCE ...................... 106 4.6.3 MODEL ANALYSIS AND SIMULATION ............................................ 117 4.6.4 STATE-SPACE MODEL WITH LOAD AS STATE VARIABLE ......... 126 STATE-SPACE MODEL OF THREE-LEVEL MMC .................................... 136 STATE-SPACE MODEL ......................................................................... 138 4.7.1 4.7.2 STATE SPACE MODEL WITH STRAY RESISTANCE ....................... 145 4.7.3 MODEL ANALYSIS AND SIMULATION ............................................ 153 STATE-SPACE MODEL OF N-LEVEL MMC .............................................. 164 4.8.1 STATE-SPACE MODEL ......................................................................... 165 4.8.2 MODEL ANALYSIS AND SIMULATION ............................................ 170 CASE STUDY: ΓMM BASED FOUR-LEVEL MMC..................... 170 4.8.2.1 4.8.2.2 CASE STUDY: ΓMM BASED FOUR-LEVEL MMC WITH NON- FULL-RANK MATRIX ...................................................................................... 179 4.8.2.3 CASE STUDY: ΓMM BASED ELEVEN-LEVEL MMC ................ 187 4.9 CONCLUSION ................................................................................................ 197 5.3 5.4 5.2.1 5.2.2 5 THE ARM INDUCTORS VOLTAGE DROP ASSUMPTION ............................. 198 5.1 INTRODUCTION ............................................................................................ 198 5.2 DYNAMIC RESPONSE OF MMC IN SWITCHING CYCLES .................... 198 STATE I .................................................................................................... 198 STATE II .................................................................................................. 205 ZERO VOLTAGE DROP ASSUMPTION ..................................................... 207 SIMULATION ................................................................................................. 208 τ / Tsw = 0.02 .............................................................................................. 209 τ / Tsw = 0.25 .............................................................................................. 213 τ / Tsw = 1 ................................................................................................... 218 τ / Tsw = 2 ................................................................................................... 223 τ / Tsw = 10 ................................................................................................. 228 5.5 CONCLUSION ................................................................................................ 233 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 6 CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK ........... 234 6.1 CONCLUSIONS .............................................................................................. 234 6.2 RECOMMENDATIONS FOR FUTURE WORK ........................................... 235 STATE-SPACE MODEL OF TWO-LEVEL MMC ................................ 236 6.2.1 6.2.2 MECHANISMS OF VOLTAGE CONVERGENCE OF TWO-LEVEL MMC ................................................................................................................... 239 THE SENSE OF SMELL OF A STATE MACHINE ....................... 239 UNDERSTAND TWO-LEVEL MMC BEHAVIORS ..................... 241 DISCUSSIONS ON HIGH LEVEL MMC............................................... 245 APPENDICES ................................................................................................................ 248 APPENDIX A: PROOF BY INDUCTION AND CONTRADICTION ..................... 249 APPENDIX B: MATLAB SCRIPT ............................................................................ 254 6.2.2.1 6.2.2.2 6.2.3 vii BIBLIOGRAPHY ........................................................................................................... 258 viii LIST OF TABLES Table 1 Two-level mmc simulation key parameters. ........................................................ 33 Table 2 Three-level MMC simulation key parameters. .................................................... 43 Table 3 Four-level MMC simulation key parameters. ...................................................... 54 Table 4 Eleven-level MMC simulation key parameters. .................................................. 69 Table 5 Initial values of state space at four time instants. .............................................. 118 Table 6 Two-level MMC simulation key parameters. .................................................... 120 Table 7 Initial values of state space at four time instants. .............................................. 154 Table 8 Three-level MMC simulation key parameters. .................................................. 156 Table 9 Initial values of state space at four time instants. .............................................. 171 Table 10 Four-level MMC simulation key parameters. .................................................. 173 Table 11 Initial values of state space at four time instants. ............................................ 180 Table 12 Initial values of state variables at four time instants. ....................................... 188 Table 13 Eleven-level MMC simulation key parameters. .............................................. 191 Table 14 Three-level MMC simulation key parameters. ................................................ 209 Table 15 Three-level MMC simulation key parameters. ................................................ 214 Table 16 Three-level MMC simulation key parameters. ................................................ 219 Table 17 Three-level MMC simulation key parameters. ................................................ 224 Table 18 Three-level MMC simulation key parameters. ................................................ 229 Table 19 Two-level MMC simulation key parameters for state machine study. ............ 243 ix LIST OF FIGURES Figure 1.1 The topology of a three-phase MMC. ............................................................... 2 Figure 1.2 The multilevel ac waveform at the MMC ac terminals. .................................... 3 Figure 2.1 Two-level MMC with pole connected to (a) positive dc rail (Level 1); and (b) negative dc rail (Level 2). ................................................................................................. 10 Figure 2.2 Three-level MMC with pole voltage of (a) Vdc (Level 1); (b)(c)(d)(e) zero volt (Level 2); and (f) –Vdc (Level 3). ...................................................................................... 11 Figure 2.3 N-level MMC with pole voltage of (a) (N–1)Vdc (Level 1); (b) (N–2)Vdc (Level 2); and (c) –(N–1)Vdc (Level N). ....................................................................................... 16 Figure 2.4 Numbering of levels in an N-level MMC, when (a) N is an odd number; and (b) N is an even number. ......................................................................................................... 17 Figure 2.5 The flowchart of checking the rank of Γ matrix. ............................................ 29 Figure 3.1 Relationship of ac-side voltage v* s and pole voltage va. .................................. 31 Figure 3.2 Two-level MMC simulation topology. ............................................................ 32 Figure 3.3 Two-level MMC (a) load voltage and (b) load current. .................................. 36 Figure 3.4 Two-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. ...................... 37 Figure 3.5 Submodule capacitor (a)/(c) voltage; and (b)/(d) current. ............................... 38 Figure 3.6 (a) Line current of phase-A and its corresponding (b) upper arm current, (c) lower arm current. ............................................................................................................. 39 Figure 3.7 Dc input voltage and current. .......................................................................... 39 Figure 3.8 Relationship of ac-side voltage v* s and pole voltage va. .................................. 40 Figure 3.9 Γ-matrix modulation strategy for three-level MMC. ....................................... 41 Figure 3.10 Three-level MMC simulation topology. ........................................................ 42 x Figure 3.11 Three-level MMC (a) load voltage and (b) load current. .............................. 45 Figure 3.12 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. .................. 46 Figure 3.13 Submodule capacitor (a)/(c) voltage; and (b)/(d) current. ............................. 47 Figure 3.14 (a) Line current of phase-A and its corresponding (b) upper arm current, (c) lower arm current. ............................................................................................................. 48 Figure 3.15 Dc input voltage and current. ........................................................................ 48 Figure 3.16 Ac-side voltage v* s and carriers, when (a) N is an odd number; and (b) N is an even number. ..................................................................................................................... 49 Figure 3.17 Ac-side voltage v* s and pole voltage va, when (a) N is an odd number; and (b) N is an even number. ......................................................................................................... 50 Figure 3.18 Γ-matrix modulation strategy for N-level MMC. .......................................... 52 Figure 3.19 Four-level MMC simulation topology........................................................... 53 Figure 3.20 Γ-matrix modulation strategy for four-level MMC. ...................................... 55 Figure 3.21 Four-level MMC (a) load voltage and (b) load current. ................................ 57 Figure 3.22 Four-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. ................... 58 Figure 3.23 Submodule capacitor (a)/(c) voltage; and (b)/(d) current. ............................. 59 Figure 3.24 (a) Line current in phase-A and its corresponding (b) upper arm current, (c) lower arm current. ............................................................................................................. 60 Figure 3.25 Dc input voltage and current. ........................................................................ 60 Figure 3.26 All submodule capacitor voltages in phase-A. .............................................. 61 Figure 3.27 Four-level MMC (a) load voltage and (b) load current. ................................ 63 Figure 3.28 Four-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. ................... 64 Figure 3.29 Submodule capacitor (a)/(c) voltage; and (b)/(d) current. ............................. 65 xi Figure 3.30 (a) Line current and its corresponding (b) upper arm current, (c) lower arm current. .............................................................................................................................. 66 Figure 3.31 Dc input voltage and current. ........................................................................ 66 Figure 3.32 All submodule capacitor voltages in phase-A. .............................................. 67 Figure 3.33 Submodule capacitor C3 voltage. .................................................................. 67 Figure 3.34 All submodule capacitor voltages in phase-A. .............................................. 68 Figure 3.35 Eleven-level MMC simulation topology. ...................................................... 68 Figure 3.36 Eleven-level MMC (a) load voltage and (b) load current. ............................ 72 Figure 3.37 Eleven-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. ................ 73 Figure 3.38 Submodule capacitor (a)/(c) voltage; and (b)/(d) current. ............................. 74 Figure 3.39 (a) Line current in phase-A and its corresponding (b) upper arm current, (c) lower arm current. ............................................................................................................. 75 Figure 3.40 Dc input voltage and current. ........................................................................ 75 Figure 3.41 All submodule capacitor voltages in phase-A. .............................................. 76 Figure 4.1 The VSC model of MMC. ............................................................................... 82 Figure 4.2 Five independent loop currents and six independent node voltages in topology. ........................................................................................................................................... 84 Figure 4.3 Loop current selection (a) single-phase oriented [47]-[48] (b) inductor current oriented [49]-[50] and (c) circulating current oriented [45],[51]-[52]. ............................. 84 Figure 4.4 Common-mode and differential-mode voltage as state variables [46]. ........... 86 Figure 4.5 State variable selections (a) dc current + common/differential-mode voltage oriented (b) inductor current + common/differential-mode voltage oriented and (c) circulating current + common/differential-mode voltage oriented. .................................. 86 Figure 4.6 The selection of MMC internal state variables................................................ 88 xii Figure 4.7 The state variable selection of [51]. ................................................................ 89 Figure 4.8 The state variable selection of this dissertation. .............................................. 89 Figure 4.9 N-level MMC circuit. ...................................................................................... 90 Figure 4.10 Numbering of levels in an N-level MMC, when (a) N is an odd number; and (b) N is an even number. ................................................................................................... 91 Figure 4.11 ac-side voltage v* s and carriers, when (a) N is an odd number; and (b) N is an even number. ..................................................................................................................... 92 Figure 4.12 ac-side voltage v* s and pole voltage va, when (a) N is an odd number; and (b) N is an even number. ......................................................................................................... 92 Figure 4.13 Γ-matrix modulation for N-level MMC......................................................... 95 Figure 4.14 two-level MMC with pole connected to (a) positive dc rail (Level 1); and (b) negative dc rail (Level 2). ................................................................................................. 95 Figure 4.15 two-level MMC model with pole connected to (a) positive dc rail; and (b) negative dc rail. ................................................................................................................. 96 Figure 4.16 Load inductor voltage modeling. ................................................................. 101 Figure 4.17 Two-level MMC with pole connected to (a) positive dc rail (Level 1); and (b) negative dc rail (Level 2). ............................................................................................... 107 Figure 4.18 Two-level MMC model with pole connected to (a) positive dc rail; and (b) negative dc rail. ............................................................................................................... 107 Figure 4.19 Two-level single-phase MMC circuit for simulation study. ....................... 119 Figure 4.20 Upper arm current (x1) simulation and state-space model comparison. ...... 121 Figure 4.21 Lower arm current (x2) simulation and state-space model comparison. ..... 122 Figure 4.22 Capacitor voltage (x3) simulation and state-space model comparison. ....... 123 Figure 4.23 Capacitor voltage (x4) simulation and state-space model comparison. ....... 124 xiii Figure 4.24 Comparison of simulation and state-space model in a long run. (a) upper arm current; (b) lower arm current; (c) capacitor voltage VC1; (d) capacitor voltage VC2. .... 125 Figure 4.25 Two-level MMC with pole connected to (a) positive dc rail (Level 1); and (b) negative dc rail (Level 2). ............................................................................................... 127 Figure 4.26 Two-level MMC model with pole connected to (a) positive dc rail; and (b) negative dc rail. ............................................................................................................... 127 Figure 4.27 Three-level MMC with pole voltage of (a) Vdc (Level I); (b)(c)(d)(e) zero volt (Level II); and (f) –Vdc (Level III). ................................................................................. 137 Figure 4.28 Load inductor voltage modeling. ................................................................. 144 Figure 4.29 Three-level MMC with pole connected to positive dc rail (Level 1). ......... 146 Figure 4.30 Three-level single-phase MMC circuit for simulation study. ..................... 155 Figure 4.31 Upper arm current (x1) simulation and state-space model comparison. ...... 157 Figure 4.32 Lower arm current (x2) simulation and state-space model comparison. ..... 158 Figure 4.33 Capacitor voltage (x3) simulation and state-space model comparison. ....... 159 Figure 4.34 Capacitor voltage (x4) simulation and state-space model comparison. ....... 160 Figure 4.35 Capacitor voltage (x5) simulation and state-space model comparison. ....... 161 Figure 4.36 Capacitor voltage (x6) simulation and state-space model comparison. ....... 162 Figure 4.37 Comparison of simulation and state-space model in a long run. (a) upper arm current; (b) lower arm current; (c) capacitor voltage VC1; (d) capacitor voltage VC2; (e) capacitor voltage VC3; (f) capacitor voltage VC4. ............................................................ 163 Figure 4.38 Accumulated error on load current. ............................................................. 164 Figure 4.39 A single-phase N-level MMC. ..................................................................... 165 Figure 4.40 Load inductor voltage modeling. ................................................................. 169 Figure 4.41 Four-level single-phase MMC circuit for simulation study. ....................... 172 xiv Figure 4.42 Upper arm current (x1) simulation and state-space model comparison. ...... 174 Figure 4.43 Lower arm current (x2) simulation and state-space model comparison. ..... 175 Figure 4.44 Capacitor voltage (x5) simulation and state-space model comparison. ....... 176 Figure 4.45 Capacitor voltage (x6) simulation and state-space model comparison. ....... 177 Figure 4.46 Comparison of simulation and state-space model in a long run. (a) upper arm current; (b) lower arm current; (c) capacitor voltage VC3; (d) capacitor voltage VC4. .... 178 Figure 4.47 Load current is = x1 – x2. .............................................................................. 179 Figure 4.48 Upper arm current (x1) simulation and state-space model comparison. ...... 182 Figure 4.49 Lower arm current (x2) simulation and state-space model comparison. ..... 183 Figure 4.50 Capacitor voltage (x5) simulation and state-space model comparison. ....... 184 Figure 4.51 Capacitor voltage (x6) simulation and state-space model comparison. ....... 185 Figure 4.52 Comparison of simulation and state-space model in a long run. (a) upper arm current; (b) lower arm current; (c) capacitor voltage VC3; (d) capacitor voltage VC4. .... 186 Figure 4.53 Load current is = x1 – x2. .............................................................................. 187 Figure 4.54 Eleven-level single-phase MMC circuit for state-space model study. ........ 190 Figure 4.55 Upper arm current (x1) simulation and state-space model comparison. ...... 192 Figure 4.56 Lower arm current (x2) simulation and state-space model comparison. ..... 193 Figure 4.57 Capacitor voltage (x12) simulation and state-space model comparison. ...... 194 Figure 4.58 Capacitor voltage (x13) simulation and state-space model comparison. ...... 195 Figure 4.59 Comparison of simulation and state-space model in a long run. (a) Upper arm current; (b) lower arm current; (c) capacitor voltage VC10; (d) capacitor voltage VC11. .. 196 Figure 4.60 Load current is = x1 – x2. .............................................................................. 197 xv Figure 5.1 Two-level MMC model with pole connected to (a) positive dc rail; and (b) negative dc rail. ............................................................................................................... 199 Figure 5.2 Phase inductor voltage modeling. .................................................................. 200 Figure 5.3 Three-level MMC simulation topology. ........................................................ 208 Figure 5.4 Three-level MMC (a) load voltage and (b) load current. .............................. 210 Figure 5.5 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. .................. 211 Figure 5.6 Sub-module capacitor (a)/(c) voltage; and (b)/(d) current. ........................... 212 Figure 5.7 (a) Line current and its corresponding (b) upper arm current, (c) lower arm current. ............................................................................................................................ 213 Figure 5.8 Three-level MMC (a) load voltage and (b) load current. .............................. 215 Figure 5.9 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. .................. 216 Figure 5.10 Sub-module capacitor (a)/(c) voltage; and (b)/(d) current. ......................... 217 Figure 5.11 (a) Line current and its corresponding (b) upper arm current, (c) lower arm current. ............................................................................................................................ 218 Figure 5.12 Three-level MMC (a) load voltage and (b) load current. ............................ 220 Figure 5.13 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. ................ 221 Figure 5.14 Sub-module capacitor (a)/(c) voltage; and (b)/(d) current. ......................... 222 Figure 5.15 (a) Line current and its corresponding (b) upper arm current, (c) lower arm current. ............................................................................................................................ 223 Figure 5.16 Three-level MMC (a) load voltage and (b) load current. ............................ 225 Figure 5.17 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. ................ 226 Figure 5.18 Sub-module capacitor (a)/(c) voltage; and (b)/(d) current. ......................... 227 xvi Figure 5.19 (a) Line current and its corresponding (b) upper arm current, (c) lower arm current. ............................................................................................................................ 228 Figure 5.20 Three-level MMC (a) load voltage and (b) load current. ............................ 230 Figure 5.21 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. ................ 231 Figure 5.22 Sub-module capacitor (a)/(c) voltage; and (b)/(d) current. ......................... 232 Figure 5.23 (a) Line current and its corresponding (b) upper arm current, (c) lower arm current. ............................................................................................................................ 233 Figure 6.1 Recommendations for future work. ............................................................... 236 Figure 6.2 Two-level single-phase MMC circuit for state machin study. ...................... 243 Figure 6.3 The < d0 , fi > resulting from the state machine proposed in Chapter 3. ....... 244 Figure 6.4 (a) Upper arm capacitor voltage; (b) lower arm capacitor voltage; and (c) the sense of smell . .................................................................................................... 245 xvii 1 INTRODUCTION The modular multilevel converter (MMC) is pioneeringly proposed by Lesnicar et al. [1] in 2003. The MMC has become the most attractive multilevel converter topology for medium/high-power applications, specifically for voltage-sourced converter high-voltage direct current (VSC-HVDC) transmission systems. Several identical submodules (SMs) with low-voltage ratings could be stacked up. Compared to other multilevel converter topologies, MMC features in modularity and scalability to meet any voltage level requirements. The topology of a three-phase MMC is shown in Figure 1.1. The MMC converts the dc system, normally high dc voltage source, to ac system, normally three phases, and feeds an ac load. The dc system of an MMC is often referred to as dc-bus or dc-link, connected to the positive and negative rails of the converter legs. The three-phase ac system is connected to the mid-point of each leg (va, vb, vc). Each leg of the MMC is divided into two arms. The arms connected to the positive rail are referred to as upper arms, and the arms connected to the negative rail are referred to as lower arms. Each arm has a group of submodules and an inductor (L). The arm inductor is connected in series with each group of submodules to limit the current due to the instantaneous voltage difference between submodules and the dc system. All submodules are identical, each corresponding to one voltage step in the resulting multilevel ac waveform at the MMC ac terminals. The multilevel ac waveform is shown in Figure 1.2. At each time instant, the controller determines how many submodules needed to create the voltage level that closest to the output sinusoidal voltage reference. The 1 topology is easy to adapt to any voltage level since the number of submodules can be adjusted. The resulting waveform has a very small total harmonic distortion (THD) as the number of submodules increases. Figure 1.1 The topology of a three-phase MMC. 2 LLidcva=+Vdc–VdcLLvbLLvcAC system(Phase a, b, c)Sub-moduleArmLegDC systemPositive railNegative rail Figure 1.2 The multilevel ac waveform at the MMC ac terminals. MMCs have two inherent properties: 1) bulky dc capacitors are needed to absorb the fundamental-frequency ripple power from ac side; 2) numerous voltage sensors and feedback control are needed to coordinate the dc capacitor voltage of each submodule. These two properties result in poor power density for MMC and computational inefficiency for control algorithm, especially in high-voltage/-power applications as the number of submodules increases. Many existing literatures have attempted to resolve the capacitor voltage balancing problems [2]-[30]. They can be classified into the following categories, 1) each submodule has a fast local dc voltage controller to prevent the individual voltage from deviation, while a slower upper controller balances the over-all arm voltages [2]-[8]; 2) the submodules are sorted, or compared, continuously in order of capacitor voltage value by controller, to determine which submodule(s) to be inserted, or by-passed, at each switching cycle [9]-[19]; 3 π2π0Vdc–VdcVava 3) the circuit topology is modified to have an inherent ability to self-balance without the need of control algorithms [20]-[27]; 4) the switching patterns are swap among the submodules in an arm within a fundamental cycle to guarantee the submodules with an equalized exposure to the loading conditions [27]-[29]. As discussed in Chapter 1.2, the existing solution for capacitor voltage balancing can be classified into four categories. Among these four categories, 1) and 2) require submodule voltage measuring, normally together with arm current measuring, to have a sophisticated closed-loop control on capacitor voltage; whereas 3) achieves the sensorless voltage balance, or self-balancing, by modifying the MMC topology, which usually results in complex circuitry; 4) has the potential to combine the merits of 1), 2) and 3), which are maintaining the basic MMC circuitry and also no need for feedback control to balance the capacitor voltage. However, none of the literatures in category 4) mathematically proves it no need of feedback control for MMC voltage balancing. Few literatures discussed the mitigation of voltage ripples on dc capacitors. Normally, the low-frequency voltage ripple on dc capacitor is deemed as unavoidable since each individual submodule is modeled as a single-phase inverter in existing literatures. Adam et al. [31] discusses the basic operation principle of MMCs and the capacitors voltage balancing technique for three-level and five-level MMCs. More importantly, it leaves a hint that the two-level MMC has a self voltage balancing ability and the low- frequency ripples on submodule capacitors are eliminated by nature. Adam et al. conclude that three-level, and above, MMCs have no such merits. 4 The overall objective of this research is to prove and develop the algorithms for MMC to achieve the self voltage balancing. This overall research goal was achieved with the following major contributions: ❖ Mathematically proved that MMCs have the self voltage balancing capability; ❖ Developed a novel modulation that secures the self voltage balancing for MMC, which allows the MMCs to become sensorless. ❖ Reduced the low-frequency voltage ripple on submodule dc capacitors, which allowed a smaller dc capacitance. ❖ Derived the general state-space model for MMC to catch the dynamics of the voltage convergence/divergence. This dissertation is organized as follows: Chapter 2 of this dissertation mathematically proves that MMCs have the self voltage balancing capability, regardless of the number of levels. Based on the mathematical proof in Chapter 2, a novel modulation is proposed in Chapter 3 to transform the mathematical analysis into engineering practice, which allows the MMCs to become sensorless. Since the proposed modulation guarantees less low- frequency ripple on dc capacitors, smaller capacitors can be utilized in MMC submodules. Simulation results are provided for verification purposes. Chapter 4 derives the general state-space model of MMC to capture the dynamics of the voltage convergence/divergence. Chapter 5 verifies the inductor voltage drop assumptions that proposed in Chapter 2. 5 Chapter 6 proposes the possible future works. 6 2 THE SELF-BALANCING NATURE OF MMC CAPACITOR VOLTAGE Modular multilevel converter (MMC) was proposed by Lesnicar et al. [1] in 2003. MMCs have an inherent property: numerous voltage sensors and feedback control are needed to coordinate the dc capacitor voltage of each submodule. This property results in computational inefficiency in control algorithms, especially for high-voltage applications where the MMC installations often consist of hundreds of submodules. Many existing literatures have attempted to resolve the capacitor voltage balancing problems [2]-[30]. They can be classified into the following categories, 1) Each submodule has a local dc voltage controller to prevent the individual voltage from deviation, while a slower upper controller balances the over-all arm voltages [2]-[8]; 2) The submodules are sorted, or compared, continuously in order of capacitor voltage value. A main controller determines which submodule(s) to be inserted, or by- passed, at each switching cycle [9]-[19]; 3) The circuit topology is modified to have an inherent capability to self balance without the need of control algorithms [20]-[27]; 4) The submodule patterns are swapped among the submodules in an arm to guarantee the submodules with an equalized exposure to the loading conditions [28]-[30]. Among the four categories, 1) and 2) require submodule voltage measuring, normally together with arm current measuring, to have a sophisticated closed-loop control on capacitor voltage; whereas 3) achieves the self voltage balancing by modifying the MMC topology, which usually results in complex circuitry; 4) has the potential to maintain the 7 basic MMC circuitry and also no need for feedback control to balance the capacitor voltage. However, this method is hard to extend to high level since it is impossible to identify all submodule patterns for high-level MMCs. Few literatures discussed the mitigation of voltage ripples on dc capacitors. Normally, the low-frequency voltage ripple on dc capacitor is deemed as unavoidable since each individual submodule is modeled as a single-phase inverter in existing literatures. Adam et al. [31] discusses the basic operation principle of MMCs and the capacitors voltage balancing technique for three-level and five-level MMCs. More importantly, it leaves a hint that the two-level MMC has a self voltage balancing ability and the low- frequency ripples on submodule capacitors are eliminated by nature. Adam et al. [31] conclude that three-level, and above, MMCs have no such merits. This Chapter mathematically proves that MMCs have the self voltage balancing capability, regardless of the number of levels. This implies that MMC voltage balancing control is unnecessary. The mathematical proof starts from two- and three-level MMCs. Then, the general N-level MMC analysis is derived thereafter. Based on the mathematical proof, a novel modulation will be proposed to transform the mathematical analysis into engineering practice in Chapter 3 of this dissertation. The pole voltage va of a two-level MMC can either be 1/2Vdc or –1/2Vdc as shown in Figure2.1. Assume that the voltage drop on arm inductors could be neglected. If the pole is attached to the positive dc rail, the lower arm capacitor C2 is clamped to the dc source voltage Vdc as shown in Figure2.1(a). If the pole is attached to the negative dc rail, the 8 upper arm capacitor C1 is clamped to the dc source voltage Vdc as shown in Figure2.1(b). C1 and C2 voltage could be formulated as, , (2.1) Re-write (2.1) into matrix form , (2.2) , where . Since the rank of Γ is two, [VC1 VC2]T has the only solution, . (2.3) The solution of (2.1) is Vc1 = Vc2 = Vdc. The two-level MMC has its capacitors’ voltages balanced by nature. Note that this capacitor voltage balance analysis assumes that the voltage drop of arm inductors could be neglected. It requires the inductor voltage to be stabilized to zero in every switching cycle. Normally, a smaller arm inductor results in faster convergence to zero. Here is the question. What is a reasonable value for the arm inductor to be regarded as neglectable in theoretical analysis without losing the practical sense? I would like to leave this topic in future. The arm inductance value needs to be determined based on the detailed model of a two-level MMC. 9 21dcCdcCVVVV==11220110==dcCCdcCCVVVVVVΓ0110=Γ112−==CdcdcCdcdcVVVVVVΓ (a) (b) Figure 2.1 Two-level MMC with pole connected to (a) positive dc rail (Level 1); and (b) negative dc rail (Level 2). Figure2.2 shows a three-level MMC. The pole voltage va of a three-level MMC can either be Vdc, zero, or –Vdc if all capacitor voltages are Vdc. For a three-level MMC, there are two, and only two, out of four submodules at inserting mode at any instant. The other two submodules are at by-pass mode meanwhile. If the voltage drop on arm inductors could be neglected, the sum of the voltages of the two inserting-mode submodules are clamped to the dc source voltage. For example, if the module three and four are at inserting mode, as shown in Figure2.2(a), the sum of capacitor C3 voltage and C4 voltage is clamped to 2Vdc. Figure2.2 shows all the possible states of a three-level MMC. The capacitor voltage of Figure2.2(a)-(f) could be formulated as, 10 VC11/2Vdc1/2VdcVsVC2vaC1C2VC11/2Vdc1/2VdcVsVC2vaC1C2isisi1i2VL1VL2VL1VL2i1i2 Figure 2.2 Three-level MMC with pole voltage of (a) Vdc (Level 1); (b)(c)(d)(e) zero volt (Level 2); and (f) –Vdc (Level 3). 11 VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4(a)(b)(c)(d)(e)(f) . (2.4) Re-write (2.4) into matrix form , (2.5) where , , and . Define the submodule state to be ‘1’ when at inserting mode; and the submodule to be ‘0’ when at by-pass mode. Γ1 contains all the possible combinations of submodule patterns when pole voltage va is at Level 1 [see Figure2.2(a)]. Γ2 contains all the possible combinations of submodule patterns when pole voltage va is at Level 2 [see Figure2.2(b)- (e)]. Γ3 contains all the possible combinations of submodule patterns when pole voltage va is at Level 3 [see Figure2.2(f)]. When MMC visits one of submodule patterns, one equation of equation set (2.4) is satisfied at a time. We can regard visiting a submodule combination as solving an equation of (2.4). Lemma 1 [32]: Consider the non-homogeneous system ΓVC = Vdc. Γ is the coefficient matrix. VC is unknown. The sizes of Γ, Vdc and VC are m×n, m×1 and n×1, respectively. ΓVC = Vdc has no more than one solution if rank[Γ] = n. 12 342414231312222222CCdcCCdcCCdcCCdcCCdcCCdcVVVVVVVVVVVVVVVVVV=+=+=+=+=+=+11122233344200112010121001011021010211002==dcdcCCdcCCCCdcCCdcdcVVVVVVVVVVVVVVΓΓΓ10011=Γ20101100101101010=Γ31100=Γ Now we need to check how many equations of (2.4) we need to solve to guarantee a solution for all capacitors’ voltages. First check the rank of Γ1, Γ2, and Γ3 respectively. , , , (2.6) which means Γ1 has one linearly independent row, Γ2 has three linearly independent rows, and Γ3 has one linearly independent row. In another word, we cannot find definite solutions for all capacitors’ voltages by solving the equations within same level. For example, if considering the equations within Level 2 only, Simplify (2.7) . . (2.7) (2.8) Eq.(2.7) and (2.8) have multiple solutions. There are no definite solutions for all capacitors’ voltages by solving the equations within Level 2. Then what about combining two levels together? For example [Γ1 Γ2]T or [Γ2 Γ3]T. Due to THD considerations, MMC pole voltage jumps between two adjacent levels at a time. Hence, checking the rank of two adjacent levels complies with practical sense. We are going to check the rank of two adjacent levels, to see whether we could find the solutions for all capacitors’ voltages. The ranks of [Γ1 Γ2]T and [Γ2 Γ3]T are 13 11=rankΓ23=rankΓ31=rankΓ142423132222CCdcCCdcCCdcCCdcVVVVVVVVVVVV=+=+=+=+1234142CCCCCCdcVVVVVVV===+ , and , (2.9) which guarantee that [Γ1 Γ2]T and [Γ2 Γ3]T have four linearly independent rows each. Hence, we could find no more than one set of solutions for all capacitors’ voltages if combining any two adjacent levels. There is one possible set of solutions for (2.4), . (2.10) These solutions of capacitor voltages are quite intuitive. Since (2.4) have no more than one solution, (2.10) must be the unique solution. Hence, the three-level MMC has its capacitors’ voltages balanced by nature. Figure2.3 shows an N-level MMC. Assume that all capacitor voltages are Vdc. The pole voltage va of an N-level MMC is an element of { (N–1)Vdc/2, (N–3)Vdc/2, (N–5)Vdc/2, …, Vdc, 0, –Vdc,…, –(N–3)Vdc/2, –(N–1)Vdc/2}, if N is an odd number. The pole voltage va of an N-level MMC is an element of {(N–1)Vdc/2, (N–3)Vdc/2, (N–5)Vdc/2, …, Vdc/2, –Vdc/2,…, –(N–3)Vdc/2, –(N–1)Vdc/2}, if N is an even number. Figure2.4 shows the numbering of levels in an N-level MMC, starting from the first level to the N-th level. For an N-level MMC, there are N–1, and only N–1, out of 2N–2 submodules at inserting mode at a time. The other N–1 submodules are at by-pass mode meanwhile. If the voltage drop on arm inductors could be ignored, the sum of the voltages of the N–1 inserting-mode submodules are clamped to the dc source voltage. For example, if the SMN through SM2N-2 are at inserting mode, as shown in Figure2.3(a), the sum of capacitor CN voltage through C2N-2 14 124=rankΓΓ234=rankΓΓ1234dcCCdcCdcCdcVVVVVVVV= voltage is clamped to (N-1)Vdc. Figure2.3(b) shows the sum of capacitor C1 and capacitor CN-1 through C2N-2 voltages is clamped to (N-1)Vdc; and Figure2.3(c) shows the sum of capacitor C1 through CN-1 voltages is clamped to (N-1)Vdc. All capacitor voltage balancing could be formulated as, , (2.11) where , 1 < k < N. 15 ()()()()()12121(22)2(22)12(22)1(22)(22)1(22)(1)(1)−−−+++−−−−=−kNNmNmNCdcCkmNdcmmmCNNNmNVNVVNVVΓΓΓΓ()211111kNkkNNkNmCCC−−−−−−== Figure 2.3 N-level MMC with pole voltage of (a) (N–1)Vdc (Level 1); (b) (N–2)Vdc (Level 2); and (c) –(N–1)Vdc (Level N). Define the submodule state to be ‘1’ when at inserting mode; and the submodule to be ‘0’ when at by-pass mode. k-th level is an arbitrary level, except for the first level and N- th level. In another word, 1 < k < N. Γk contains all the possible switching patterns when pole voltage va is at k-th level. Γk is an mk by (2N–2) matrix. When MMC visits one switching pattern, one equation in (2.11) is satisfied at a time. We can regard visiting a switching pattern as solving an equation in (2.11). From Chapter 2.3, we have already observed a unique feature of three-level MMC, which is the rank of any two adjacent levels is four. This guarantees the three-level MMC 16 SM1SM2SMN-1SMNSM2N-3SM2N-2VsisVL1VL2(N-1)Vdc/2i1i2vaVCkCkSMk=SM1SM2SMN-1SMNSM2N-3SM2N-2VsisVL1VL2i1i2vaSM1SM2SMN-1SMNSM2N-3SM2N-2VsisVL1VL2i1i2va(a)(b)(c)(N-1)Vdc/2(N-1)Vdc/2(N-1)Vdc/2(N-1)Vdc/2(N-1)Vdc/2 has its capacitors’ voltages balanced by nature. If we could extend this observation to N- level MMC, which means the rank of any two adjacent levels is 2N–2, this will guarantee that the N-level MMC has its capacitors’ voltages balanced by nature. Figure 2.4 Numbering of levels in an N-level MMC, when (a) N is an odd number; and (b) N is an even number. 2.4.1 MASSIVE DATA DILEMMA However, it is not always easy to obtain the Γ matrix. Notice that the Γk matrix of a N- level MMC is a mk-by-(2N–2) matrix, where . For example, the Γ5 matrix of a 9-level MMC is a 4900-by-16 matrix; the Γ50 matrix of a 100-level MMC is a 2.5×1057-by-198 matrix. In High-Voltage DC (HVDC) transmission applications, the MMC is built with 200 - 400 levels [33]. The Γ matrix expands rapidly as the MMC level increases, which becomes impossible for computers to process. However, it is not always 17 1.5Vdcπ2π0(N–1)Vdc/2–(N–1)Vdc/212k(N+1)/2(N–3 )/2(N+3)/2N–1N2VdcVsvaπ2π012kN/2N/2+1N–1NVsva(a)(b)(N–1)Vdc/2–(N–1)Vdc/2()211111kNkkkNNNmCCC−−−−−−== necessary to have a whole picture of Γ matrix. The only thing we care about Γ matrix is its rank. Lemma 2 [34]: The rank of an m×n matrix cannot exceed m or n. The maximum value possible is the smaller of m and n. Since Γk is an mk-by-(2N–2) matrix. The rank of Γk cannot exceed 2N–2. Γk should be able to extract a (2N–2)-by-(2N–2) submatrix, or even smaller than (2N–2)-by-(2N–2), while holding the same rank as the original Γk. In another word, if we could find a submatrix of Γk which guarantees that has a rank of 2N–2, we can conclude that [ Γk Γk+1 ] also has a rank of 2N – 2 and the N-level MMC has its capacitors’ voltages balanced by nature. 2.4.2 SUBMATRIX EXTRACTION Γ matrix extraction is critical before we proceed to calculate the rank of Γ matrix. To simplify the problem, let us first investigate the Γ matrix of two-level MMC. The Γ matrix of two-level MMC is as follows, . (2.12) Every specific column is always representing one certain submodule states (1 represents inserting mode and 0 represents by-pass mode). Since Γ1 (2) and Γ2 (2) are 1-by-2 matrix, there is no need to extract submatrices from these two. The Γ matrix of three-level MMC is as follows, 18 ˆkΓT1ˆˆ+kkΓΓ()()()2st122nd2011 level102 level==ΓΓΓ . (2.13) Eq.(2.13) could be interpreted as follows: The Γ(3) could be derived from Γ(2). For example, adding a “0” to the left of Γ1 (2) and a “1” to the right of Γ1 (2), the matrix [0 Γ1 (2) 1] becomes the Γ1 (3). Adding a “0” to the left of Γ2 (2) and a “1” to the right of Γ2 (2), the matrix [0 Γ2 (2) 1] becomes part of Γ2 (3). Adding a “1” to the left of Γ1 (2) and a “0” to the right of Γ1 (2), the matrix [1 Γ1 (2) 0] becomes part of Γ2 (3). Adding a “1” to the left of Γ2 (2) and a “0” to the right of Γ2 (2), the matrix [0 Γ2 (2) 1] becomes part of Γ2 (3). There are two submodule states that cannot be directly derived from Γ(2), which are [1 T1(a) (2) 1] and [0 T1(b) (2) 0]. T1(a) (2) is derived from Γ1 (2) by manipulating the right most “1” in Γ1 (2) to “0”. T1(b) (2) is derived from Γ1 (2) by manipulating the left most “0” in Γ1 (2) to “1”. Γ1 (3) and Γ3 (3) are 1-by-4 matrices. There is no need to extract submatrices from these two. Γ2 (3) is a 4-by-4 matrix with a rank of three. Γ2 (3) should be able to find a 3-by-4 submatrix which holds the same rank. Γ2 (3) is as follows . (2.14) There are four possible ways to extract a 3-by-4 submatrix from Γ2 (3). Two of them are selected as examples. Γ2 (3) can be segmented to 19 ()()()()()()()()()()()()st21nd2231213322133212200110011011 level01010101012 leve1001100111011001100010101010101100101100====abΓΓΓTΓΓTΓΓΓndndndrdl2 level2 level2 level3 level()()()()()()()2221322121010101100111011000101010==abΓTΓTΓ or , , (2.15) (2.16) where is the core matrix extracted from Γ2 (3). M2 (3) is the redundant submatrix to discard. Let us check the rank of . (2.17) holds the same rank as Γ3 (3). Instead of checking the rank of [Γ1 (3) Γ2 (3)]T and [Γ2 (3) Γ3 (3)]T, let us check the rank of and . , and . (2.18) Since and are submatrices of [Γ1 (3) Γ2 (3)]T and [Γ2 (3) Γ3 (3)]T, the rank of [Γ1 (3) Γ2 (3)]T and [Γ2 (3) Γ3 (3)]T should also be four. Let’s extend the similar matrix extraction procedure to the four-level MMC. The Γ matrix of four-level MMC is as follows, 20 ()()()()()()()()()2223123223122101ˆ110010==abΓTΓΓTMΓ()()()()()()()()()223221323221210111ˆ0010==abΓMTΓΓTΓ()32ˆΓ()32ˆΓ()32ˆ3=rankΓ()33ˆΓ()()T3312ˆΓΓ()()T3323ˆΓΓ()()31324ˆ=rankΓΓ()()3233ˆ4=rankΓΓ()()T3312ˆΓΓ()()T3323ˆΓΓ . (2.19) Γ1 (4) and Γ4 (4) are 1-by-6 matrices. There is no need to extract submatrices from these two. Γ2 (4) and Γ3 (4) are 9-by-6 matrices with a rank of 5. Γ2 (4) and Γ3 (4) should be able to find the 5-by-6 submatrices which hold the same rank. Γ2 (4) is as follows , (2.20) 21 ()()()()()414244344000111001011010011001101010101100101010110100011100110001110101010110010101100110100101001011010011001011100110001111000==ΓΓΓΓΓ()()()()()()()3231423142001011001011010011010011001101001101ˆ0101011001011110010101011000010110010101100011100011100110100110001110001110===ab0Y1TΓTM where follows (2.15). T1(a) (3) is derived from Γ1 (3) by manipulating the right most “1” in Γ1 (3) to “0”. T1(b) (3) is derived from Γ1 (3) by manipulating the left most “0” in Γ1 (3) to “1”. There are multiple ways to extract a submatrix from Γ2 (4). One of them is selected as example. This segmentation is similar to (2.15). Γ2 (4) can be segmented to , (2.21) where is the core submatrix extracted from Γ2 (4). M2 (4) is the redundant submatrix to discard. Let us check the rank of . (2.22) holds the same rank as Γ2 (4). Γ3 (4) is as follows , (2.23) where follows (2.15). T2(a) (3) is derived from by manipulating the right most “1” in first row of to “0”. T2(b) (3) is derived from by manipulating the left most “0” in first row of to “1”. There are multiple ways to extract a submatrix from Γ3 (4). One 22 ()32ˆΓ()()()()()()()()()32341242341242ˆˆ1100==ab0Γ1TYΓTMM()42ˆΓ()42ˆΓ()42ˆ5=rankΓ()42ˆΓ()()()()()()()3232433243101010101010110010110010101100101100ˆ1101001010011110100101101000011010110100011001011001011100011100110001110001===ab1Γ0TΓTM()32ˆΓ()32ˆΓ()32ˆΓ()32ˆΓ()32ˆΓ of them is selected as example. This segmentation logic is similar to (2.16). Γ3 (4) can be segmented to , (2.24) where is the core submatrix extracted from Γ2 (4). M2 (4) is the redundant submatrix to discard. Let us check the rank of . (2.25) holds the same rank as Γ3 (4). Instead of checking the rank of [Γ1 (4) Γ2 (4)]T, [Γ2 (4) Γ3 (4)]T, and [Γ3 (4) Γ4 (4)]T, let us check the rank of , and . , , and . (2.26) Since , and are submatrices of [Γ1 (4) Γ2 (4)]T, [Γ2 (4) Γ3 (4)]T, and [Γ3 (4) Γ4 (4)]T, the rank of [Γ1 (4) Γ2 (4)]T, [Γ2 (4) Γ3 (4)]T, and [Γ3 (4) Γ4 (4)]T should also be six. Here are some observations from four-level MMC: a. The first and last level matrices, Γ1 (4) and Γ4 (4), have no need to extract submatrices; b. The second level matrix, Γ2 (4), needs to extract a submatrix, and this core submatrix can be derived from and Γ1 (3); 23 ()()()()()()()()()4343324334233211ˆ00ˆ==abMMTΓTΓ1Γ0()43ˆΓ()43ˆΓ()43ˆ5=rankΓ()43ˆΓ()()T4412ˆΓΓ()()T4423ˆˆΓΓ()()T3334ˆΓΓ()()41426ˆ=rankΓΓ()()4243ˆ6ˆ=rankΓΓ()()4344ˆ6=rankΓΓ()()T4412ˆΓΓ()()T4423ˆˆΓΓ()()T3334ˆΓΓ(4)2ˆΓ(3)2ˆΓ c. The second to the last matrix, Γ3 (4), needs to extract a submatrix, and this core submatrix can be derived from only. Let’s extend this matrix extraction procedure to N-level MMC: a. The first and last level matrices, Γ1 (N) and ΓN (N), have no need to extract submatrices; b. The second to (N – 2)th level matrices, Γ2 (N) to ΓN-2 (N), need to extract submatrices, and these core submatrices, to , can be derived from and to ; c. The second to the last matrix, ΓN-1 (N), needs to extract a submatrix, and this core submatrix can be derived from only. Assume that the Γ matrix and its core submatrix of (N – 1)-level MMC are as follows, , , (2.27) Γ1 (N-1) and ΓN-1 (N-1) are 1-by-(2N – 4) matrices. There is no need to extract submatrices from these two. Γ2 (N-1) to ΓN-2 (N-1) are mk-by-(2N – 4) matrices, where as described in (2.11). is extracted from Γ(N-1) and holds the same rank as Γ(N-1). Assume that the Γ matrix and its core submatrix of N-level MMC are as follows, 24 (4)3ˆΓ(3)2ˆΓ()2ˆNΓ()2ˆ−NNΓ(1)1−NΓ(1)2ˆ−NΓ(1)2ˆ−−NNΓ()1ˆ−NNΓ(1)2ˆ−−NNΓˆΓ()()()()1112(1)111−−−−−−=NNNNkNNΓΓΓΓΓ()()()()()1112(1)11211ˆˆˆˆ−−−−−−−−=NNNNkNNNNΓΓYΓΓΓ()2111222kNkkkNNNmCCC−−−−−−−==()1ˆ−NΓˆΓ , , (2.28) Γ1 (N) and ΓN (N) are 1-by-(2N – 2) matrices. There is no need to extract submatrices from these two. Γ2 (N) to ΓN-1 (N) are mk-by-(2N – 2) matrices, where as described in (2.11). is extracted from Γ(N) and holds the same rank as Γ(N). Instead of extracting directly from Γ(N), could also be derived from . where 2 ≤ k ≤ N – 2. , (2.29) , , (2.30) (2.31) . (2.32) Eq.(2.31)-(2.32) demonstrate how to derive from . Γ1 (N) is a 1-by-(2N – 2) matrix with the first N – 1 elements to be zero and the last N – 1 elements to be one. consists of three parts. The first part is derived from by adding a zero vector to the left 25 ()()()()12()=NNNNkNNΓΓΓΓΓ()()()()()12()1ˆˆˆˆ−=NNNNkNNNNΓΓYΓΓΓ()211111kNkkkNNNmCCC−−−−−−==()ˆNΓ()ˆNΓ()ˆNΓ()1ˆ−NΓ()111[0011]−−=NNNΓk()()()()()()11111ˆˆ1100−−−−−=NkNNkkaNkb0Γ1ΓTT()()()()()()121211211ˆ00ˆ−−−−−−−=NNaNNNNbNNTTΓ1Γ0()11[1100]−−=NNNNΓk()ˆNΓ()1ˆN−Y()ˆNkΓ()1ˆ−NkΓ of and a one vector to the right of . The second part is derived from Tk-1(a) (N-1) by adding two “1”s to the left and right of Tk-1(a) (N-1), where Tk-1(a) (N-1) is derived from by manipulating the right most “1” in first row of to “0”. The third part is derived from Tk-1(b) (N-1) by adding two “0”s to the left and right of Tk-1(b) (N-1), where Tk-1(b) (N-1) is derived from by manipulating the left most “0” in first row of to “1”. consists of three parts. The first part is derived from TN-2(a) (N-1) by adding two “1”s to the left and right of TN-2(a) (N-1), where TN-2(a) (N-1) is derived from by manipulating the right most “1” in first row of to “0”. The second part is derived from TN-2(b) (N-1) by adding two “0”s to the left and right of TN-2(b) (N-1), where TN-2(b) (N-1) is derived from by manipulating the left most “0” in first row of to “1”. Both and are (2N – 3)- by-(2N – 2) matrix The third part is derived from by adding a zero vector to the left of and a one vector to the right of . ΓN (N) is a 1-by-(N – 1) matrix with the first N – 1 elements to be one and the last N – 1 elements to be zero. and are expected to be a (2N – 5)-by-(2N – 4) matrix, with an expected rank of 2N – 5. and are expected to be a (2N – 3)-by-(2N – 2) matrix, with an expected rank of 2N – 3. The reason why we cannot find a uniform formula for both and is that cannot be derived from . Remember that is a 1-by-(2N – 4) matrix. If is derived similar to (2.30) as follows, 26 ()1ˆ−NkΓ()1ˆ−NkΓ()11ˆ−−NkΓ()11ˆ−−NkΓ()11ˆ−−NkΓ()11ˆ−−NkΓ()1ˆ−NNΓ()12ˆ−−NNΓ()12ˆ−−NNΓ()12ˆ−−NNΓ()12ˆ−−NNΓ()1ˆ−NkΓ()1ˆ−NNΓ()12ˆ−−NNΓ()12ˆ−−NNΓ()12ˆ−−NNΓ()1ˆ−NkΓ()12ˆ−−NNΓ()ˆNkΓ()1ˆ−NNΓ()ˆNkΓ()1ˆ−NNΓ()1ˆ−NNΓ()11−−NNΓ()11−−NNΓ()1ˆ−NNΓ . (2.33) becomes a 3-by-(2N – 2) matrix. The rank of a 3-by-(2N – 2) matrix cannot exceed 3, which cannot satisfy the rank expectation. 2.4.3 N-LEVEL MMC CONJECTURE The rank of any two adjacent levels is expected to be 2N – 2 To secure the self voltage balancing for N-level MMC, which is the same as the number of submodules. To check the rank of any two adjacent levels, one option is analytically proving that: a. The rank of is 2N – 2; b. The rank of is 2N – 2, where 2 ≤ k ≤ N – 3; c. The rank of is 2N – 2; d. The rank of is 2N – 2. Or alternatively prove that a. If the rank of is m for an (N – 1)-level MMC, then the rank of is m + 2 for an N-level MMC; b. If the rank of is m for an (N – 1)-level MMC, then the rank of is m + 2 for an N-level MMC, where 2 ≤ k ≤ N – 3; c. If the rank of is m for an (N – 1)-level MMC, then the rank of is m + 2 for an N-level MMC; 27 ()()()()()()1111111ˆ1100−−−−−−−=NNNNNkaNkb0Γ1ΓTT()1ˆ−NNΓ()()T12ˆNNΓΓ()()T1ˆˆ+NNkkΓΓ()()T21ˆˆ−−NNNNΓΓ()()T1ˆ−NNNNΓΓ()()T1112ˆ−−NNΓΓ()()T12ˆNNΓΓ()()T111ˆˆ−−+NNkkΓΓ()()T1ˆˆ+NNkkΓΓ()()T1121ˆ−−−−NNNNΓΓ()()T21ˆˆ−−NNNNΓΓ d. If the rank of is m for an (N – 1)-level MMC, then the rank of is m + 2 for an N-level MMC. Since we have proved that two-, three-, and four-level MMCs have self voltage balancing feature, this feature can be extended to five-, six-, seven-level, and so on. The proof of the conjectures above requires comprehensive knowledge of linear algebra and is out of the scope of this dissertation. Some trials are included in Appendix A. The author of this dissertation would like to leave this proof for the future work. 2.4.4 COMPUTER-AID PROOF As per power electronics engineering, it is not always necessary to consider the operation of an MMC with more than 500 levels. In High-Voltage DC (HVDC) transmission applications, the MMC is built with 200–400 submodules in each arm [33]. The first HVDC installation Trans Bay Cable project utilized an MMC structure with around 200 submodules per arm [35]. Normally there are hundreds of submodules per arm in HVDC applications [36]. Thanks to the powerful computation capability of modern computers, they make it possible to generate the matrix of a hundreds-level MMC by giving the matrix of a three-level MMC. A Matlab script is created to generate the of 3-level MMC to 533-level MMC, and to justify the rank of any two adjacent levels. The flowchart of the Matlab script is shown in Figure2.5. The Matlab script is attached in Appendix B. 28 ()()T1121ˆ−−−−NNNNΓΓ()()T1ˆ−NNNNΓΓˆΓˆΓˆΓ Figure 2.5 The flowchart of checking the rank of Γ matrix. 29 Set NN = 533, N = 1StartIs k = 1?YesIs k < N – 1?NoInitialize the Y333 matrix with Y3YesIs k = N – 1?NoYesNoIs k = 1?YesNoIs k = N?k = k +1NoYesSet k = 1Set k = 1Print noticeNo%'The rank of kth level and (k+1)th level of a N-level MMC is < 2N-2'EndIs k = N-1?Yesk = k +1NoIs N = NN?YesPrint noticeYes%'All ranks checked!'N = N +1No()1ˆ−NΓ()3ˆΓ()11ˆ[0011]−−=NkNNΓk()ˆDerive from (2.30)NkΓ()ˆDerive from (2.31)NkΓ()11ˆ[1100]−−=NkNNΓk()ˆGenerate NΓ()()()ˆˆˆ=NNNkkkΓΓΓ()()ˆˆ=NNkΓΓ()()1ˆˆCheck rank +NNkkΓΓ()()1ˆˆUpdate with −NNΓΓ()()()1ˆˆˆRetrieve and from +NNNkkΓΓΓ()()1ˆˆCheck rank +NNkkΓΓ()()1ˆˆIs rank 22?+=−NNkkNΓΓ According to the MATLAB result, the rank of any two adjacent levels is 2N – 2, up to 533-level MMC. A rank of 2N – 2 guarantees that matrix of any two adjacent levels, from 2-level MMC to 533-level MMC, has 2N – 2 linearly independent rows. Hence, we could find no more than one set of solutions for 2N – 2 capacitors’ voltages if combining any two adjacent levels. There is one possible set of solutions for (2.11), . (2.34) These solutions of capacitor voltages are quite intuitive. Since (2.11) has no more than one set of solutions, (2.34) must be the only set of solutions. The author of this dissertation conjectures that this conclusion can be extended to any level MMC. If the conjecture is true, we can conclude that MMC has self voltage balancing by nature. If the conjecture is false, we can conclude that MMC has self voltage balancing by nature up to 533 levels at least. This chapter explores the self voltage balancing nature of MMC. Mathematically, MMC submodule voltage can balance If utilizing certain submodule patterns. A computer-aid procedure is given to guarantee that N-level MMC, where N < 534, has this self voltage balancing by nature. This chapter conjectures that this conclusion can be extended to any level of MMC. 30 ˆΓ12(22)(22)1(22)1CdcCdcCNdcNNVVVVVV−−−= 3 Γ-MATRIX MODULATION (ΓMM) As discussed in Chapter 2, the MMC structure has self voltage balancing feature in a mathematical sense. Here comes a question. How to realize this self voltage balancing feature over math to engineering? As mentioned in Chapter 2, when MMC visits one submodule pattern, one equation in (2.11) is satisfied at a time. When MMC visits all submodule patterns in the Γ, or the , it is said to have finished one iteration. MMC capacitor voltages are expected to converge to (2.34) after several iterations. This chapter focuses on developing an effective modulation, namely Γ-Matrix Modulation (ΓMM), to realize the self voltage balancing feature for MMC. With this novel Γ-Matrix Modulation, the low-frequency ripple on dc capacitors is highly reduced, which makes it possible to have an extremely small submodule capacitor to absorb only the switching-level ripples. As shown in Figure2.1, the pole voltage va of a two-level MMC can either be 1/2Vdc or –1/2Vdc if the VC1 = VC2 = Vdc. Assume the expected ac-side voltage to be v* s, and the pole voltage va to follow the PWM strategy. The relationship of v* s and va is plotted in Figure3.1. Figure 3.1 Relationship of ac-side voltage v* s and pole voltage va. 31 ˆΓ02π02πVdc/2–Vdc/2Vdc/2–Vdc/2carrier1st level2nd levelv*sva When the pole voltage va at first level, one of the rows in Γ1 (2) will be assigned to the MMC as the chosen submodule pattern to realize this first-level pole-voltage. Recall that there is only one row in Γ1 (2), which is [0 1]. This row can be interpreted as this: the SM1 is at by-pass mode and the SM2 is at inserting mode. The switches of each submodule need to follow this piece of Γ-matrix command accordingly. Similarly, when the pole voltage va at second level, one of the rows in Γ2 (2) will be assigned to MMC as the chosen submodule pattern to realize this second-level pole-voltage. Recall that there is only one row in Γ2 (2), which is [1 0]. This row can be interpreted as this: the SM1 is at inserting mode and the SM2 is at by-pass mode. The switches of each submodule need to follow this piece of Γ- matrix command accordingly. A MATLAB/Simulink simulation is conducted to demonstrate the ΓMM based two-level MMC. ❖ Case Study 2.1 ΓMM Based Two-Level MMC Objective: In this case study, the working principle and the performance of ΓMM based 2-level MMC are studied through MATLAB/Simulink. The simulation topology is shown in Figure3.2. Figure 3.2 Two-level MMC simulation topology. 32 VdcVaiaidciuapidaowniubpidbowniucpidcownibicvcavbcvabVbVcLarmLlineVC1C1iC1VC2C2iC2VC3C3iC3VC4C4iC4VC5C5iC5VC6C6iC6Rload Parameters: The key parameters of the MMC are as follows: rated apparent power S = 50 kVA, output phase voltage Va = Vb = Vc = 320 V, output line current Ia = Ib = Ic = 52 A, rated output fundamental frequency f0 = 60 Hz, rated load resistance Rload = 6.2 Ω, rated dc-bus voltage Vdc = 1 kV, number of submodules per arm: N – 1 = 1, submodule capacitance Ci = 85 µF (i = 1, 2, …, 6), line inductance Lline = 1 mH, and arm inductance Larm = 0.1 µH. The switching frequency is fsw = 10 kHz. The definition of switching frequency is the frequency of the MMC pole voltage jumping from one level to the other adjacent level. The key parameters are summarized in Table 1. Table 1 Two-level mmc simulation key parameters. Apparent Power, S 50 kVA Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 10 kHz DC-Bus Voltage, Vdc 1000 V Phase Voltage, Va, Vb, Vc Line Current, Ia, Ib, Ic 320 V 52 A Load Resistance, Rload 6.2 Ω (100% p.u.) Line Inductance, Lline 1 mH (6% p.u.) Arm Inductance, Larm 0.1 µH (0.0006% p.u.) Submodule Capacitance, Ci 85 µF (20% p.u.) Number of Submodules per Arm 1 where i = 1, 2, …, 6. 33 Analysis: This two-level MMC simulation follows the Γ-Matrix Modulation strategy. The load voltage and current are shown in Figure3.3. The mid-point voltage is shown in Figure3.4. The mid-point voltage of two-level MMC has three levels. Although the mid- point voltage of any single phase, va vb and vc, has only two levels, the differential voltage of any two phases, vab vbc and vca, has three levels. The submodule capacitor voltage and current are shown in Figure3.5. The capacitor voltage ripple is within 2%. The capacitor current consists mainly of fundamental component and switching-frequency harmonics. Note that the submodule capacitance is only 0.2 p.u.. The energy stored in capacitor is . (3.1) The total energy in all submodule capacitors is . (3.2) The two-level MMC power rating is 50 kVA. The total capacitor energy in respect to MMC power rating is . (3.3) Typically, the conventional MMC submodule capacitance is chosen such that the total stored energy in all submodule capacitors of the converter is approximately 30 – 40 kJ/MVA, where MVA refers to the converter rating, giving ripple in the range of 10% [35]. To have a voltage ripple within 2%, the conventional MMC needs to have submodule capacitors energy to be 150 – 200 kJ/MVA. Normally, the capacitor energy storage capability is proportional to the capacitor volume. The ΓMM based MMC features an extremely small capacitor volume compared to conventional MMC. 34 26210.58510100042.5 (J)2iiCiECV−===62116255 (J)2iiCitotaliEECV====33255105.1 (kJ/MVA)5010totalES−−=== The capacitor voltage is well balanced and converging to the expected value (1000 V) in Figure3.5. However, the fundamental ripples still exist. These fundamental ripples are introduced by the arm inductor and stray resistor. Note that the capacitor voltage balance analysis in previous sections does not consider the voltage drop on arm inductors and stray resistance. The effect of those passive components will be discussed in future work. Figure3.6 shows line current of phase-A and its corresponding arms’ current. The arm current contains not only fundamental component but also switching-frequency harmonics. Normally, the conventional MMC arm current does not contain many switching-frequency harmonics, and the arm inductance follows the equation [36] , (3.4) where ω0 = 2πf0, VCi = 1000 V, and I2ω is the peak value of the 2-ω component in arm current. For conventional MMC, Ci = 150/5.1×85 µF = 2550 µF to have a voltage ripple within 2%. I2ω is known to be 13.8 A from simulation. The arm inductance of conventional MMC should be 757 µH (4.6% p.u.) according to (3.4). The arm inductor of ΓMM based MMC is extremely small comparing to conventional MMC. Small arm inductance is critical to balance the capacitor voltage. This will be explained in future work. Figure3.7 shows the input dc voltage and current. As seen from Figure3.7, the input current consists of dc component and switching-frequency harmonics. These switching- frequency harmonics can be mitigated by adding a decoupling capacitor at dc bus. 35 220138armdciCiSVLICV+= Figure 3.3 Two-level MMC (a) load voltage and (b) load current. 36 Figure 3.4 Two-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. 37 Figure 3.5 Submodule capacitor (a)/(c) voltage; and (b)/(d) current. 38 Figure 3.6 (a) Line current of phase-A and its corresponding (b) upper arm current, (c) lower arm current. Figure 3.7 Dc input voltage and current. 39 As shown in Figure2.2, the pole voltage va of a three-level MMC can either be Vdc, zero volt, or –Vdc if all capacitor voltages are Vdc. Assume the expected ac-side voltage to be v* s. The pole voltage va follows the level-shifted modulation strategy. The relationship of v* s and va is plotted in Figure3.8. Figure 3.8 Relationship of ac-side voltage v* s and pole voltage va. When the pole voltage va at first level, one of the rows in Γ1 (3) will be assigned to the MMC as the chosen submodule pattern to realize this first-level pole-voltage. Recall that there is only one row in Γ1 (3), which is [0 0 1 1]. This row can be interpreted as this: SM1 and SM2 are at by-pass mode, and SM3 and SM4 are at inserting mode. The switches of each submodule need to follow this piece of Γ-matrix command accordingly. Similarly, when the pole voltage va at third level, one of the rows in Γ3 (3) will be assigned to MMC as the chosen submodule pattern to realize this third-level pole-voltage. Recall that there is only one row in Γ3 (3), which is [1 1 0 0]. This row can be interpreted as this: SM1 and SM2 are at inserting mode and SM3 and SM4 are at by-pass mode. The switches of each submodule need to follow this piece of Γ-matrix command accordingly. 40 02π02πVdc–VdcVdc–Vdc3rd levelcarrierv*sva1st level2nd level When the pole voltage va at second level, one of the rows in Γ2 (3) will be assigned to MMC as the chosen submodule pattern to realize this second-level pole-voltage. Recall that there are four rows in Γ2 (3) and the rank of Γ2 (3) is three, which means only three rows in Γ2 (3) are needed to achieve the capacitor voltage balance. There are four combinations of three rows in Γ2 (3) in total and all of them have a rank of three. Hence, we can choose any one of these four submatrices to compose the modulation table. The submatrix following (2.16) is selected in this chapter to demonstrate the three-level MMC modulation. The three-level MMC modulation can be explained with the aid of Figure3.9. When the pole voltage va is determined to be at second level by level-shifted modulation, the level pointer is pointed to Level 2. The gating signal generator is going to grab the current row of that the Γ-matrix pointer in level two is pointing to. After feeding the Γ-matrix command to gating signal generator, the level two pointer will point to the next row and wait for the next visit of level pointer. A MATLAB/Simulink simulation is conducted to demonstrate the ΓMM based three-level MMC. Figure 3.9 Γ-matrix modulation strategy for three-level MMC. 41 ()32ˆY()32ˆYLevel 1Level 2Level 30 0 1 11 0 1 00 1 1 01 0 0 11 1 0 0Level PointerΓ-matrix Pointer ❖ Case Study 2.2 ΓMM Based Three-Level MMC Objective: In this case study, the working principle and the performance of ΓMM based three-level MMC are studied through MATLAB/Simulink. The simulation topology is shown in Figure3.10. Figure 3.10 Three-level MMC simulation topology. Parameters: The key parameters of the MMC are as follows: rated apparent power S = 100 kVA, output phase voltage Va = Vb = Vc = 643 V, output line current Ia = Ib = Ic = 52 A, rated output fundamental frequency f0 = 60 Hz, rated load resistance Rload = 12.4 Ω, rated dc-bus voltage Vdc = 2 kV, number of submodules per arm: N – 1 = 2, submodule capacitance Ci = 85 µF (i = 1, 2, …, 12), line inductance Lline = 1 mH, and arm inductance Larm = 0.1 µH. The switching frequency is fsw = 20 kHz. The definition of switching frequency is the frequency of the MMC pole voltage jumping from one level to the other adjacent level. The key parameters are summarized in Table 2. 42 VdcVaiaidciuapidaowniubpidbowniucpidcownibicvcavbcvabVbVcLarmLlineVC2C2iC2VC3C3iC3VC6C6iC6VC7C7iC7VC10C10iC10VC11C11iC11RloadC1C5C9C4C8C12VC1VC5VC9VC4VC8VC12iC1iC5iC9iC4iC8iC12 Table 2 Three-level MMC simulation key parameters. Apparent Power, S 100 kVA Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 20 kHz DC-Bus Voltage, Vdc 2000 V Phase Voltage, Va, Vb, Vc 643 V Line Current, Ia, Ib, Ic 52 A Load Resistance, Rload 12.4 Ω (100% p.u.) Line Inductance, Lline 1 mH (3% p.u.) Arm Inductance, Larm 0.1 µH (0.0003% p.u.) Submodule Capacitance, Ci 85 µF (40% p.u.) Number of Submodules per Arm 2 where i = 1, 2, …, 12. Analysis: This three-level MMC simulation follows the Γ-Matrix Modulation strategy. The submatrix extraction follows (2.16). The load voltage and current are shown in Figure3.11. The mid-point voltage is shown in Figure3.12. The mid-point voltage of three- level MMC has five levels. Although the mid-point voltage of any single phase, va vb or vc, has only three levels, the differential voltage of any two phases, vab vbc and vca, has five levels. The submodule capacitor voltage and current are shown in Figure3.13. The capacitor voltage ripple is within 3%. The capacitor current consists mainly of fundamental 43 ()32ˆΓ component and switching-frequency harmonics. Note that the submodule capacitance is only 0.4 p.u.. The energy stored in capacitor is . (3.5) The total energy in all submodule capacitors is . (3.6) The three-level MMC power rating is 100 kVA. The total capacitor energy in respect to MMC power rating is . (3.7) Typically, the conventional MMC submodule capacitance is chosen such that the total stored energy in all submodule capacitors of the converter is approximately 30 – 40 kJ/MVA, where MVA refers to the converter rating, giving ripple in the range of 10% [37]. To have a voltage ripple within 3%, the conventional MMC needs to have submodule capacitors energy to be 100 – 130 kJ/MVA. Normally, the capacitor energy storage capability is proportional to the capacitor volume. The ΓMM based MMC features an extremely small capacitor volume compared to conventional MMC. The capacitor voltage is well balanced and converging to the expected value (1000 V) in Figure3.13. However, the fundamental ripples still exist. These fundamental ripples are introduced by the arm inductor and stray resistance. Note that the capacitor voltage balancing analysis in Chapter 1 did not consider the voltage drop on arm inductors and stray resistance. The effect of those passive components will be discussed in future work. Figure3.14 shows the line current of phase-A and its corresponding arms’ current. The arm current contains not only fundamental component but also switching-frequency 44 26210.58510100042.5 (J)2iiCiECV−===1221112510 (J)2iiCitotaliEECV====33510105.1 (kJ/MVA)10010totalES−−=== harmonics. Normally, the conventional MMC arm current does not contain many switching-frequency harmonics, and the arm inductance follows the equation (3.4) [38], where ω0 = 2πf0, VCi = 1000 V, and I2ω is the peak value of the 2-ω component in arm current. For conventional MMC, Ci = 100/5.1×85 µF = 16667 µF to have a voltage ripple within 3%. Assume I2ω to be 13.8 A (Ia×26.5%). The arm inductance of conventional MMC should be 2.33 mH (7.1% p.u.) according to (3.4). The arm inductor of ΓMM based MMC is extremely small comparing to conventional MMC. Small arm inductance is critical to balance the capacitor voltage. This will be explained in future work. Figure3.15 shows the input dc voltage and current. As seen from Figure3.15, the input current consists of dc component and switching-frequency harmonics. These switching- frequency harmonics can be mitigated by adding a decoupling capacitor at dc bus. Figure 3.11 Three-level MMC (a) load voltage and (b) load current. 45 Figure 3.12 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. 46 Figure 3.13 Submodule capacitor (a)/(c) voltage; and (b)/(d) current. 47 Figure 3.14 (a) Line current of phase-A and its corresponding (b) upper arm current, (c) lower arm current. Figure 3.15 Dc input voltage and current. 48 As shown in Figure2.3, The pole voltage va of an N-level MMC is an element of { (N– 1)Vdc/2, (N–3)Vdc/2, (N–5)Vdc/2, …, Vdc, 0, –Vdc,…, –(N–3)Vdc/2, –(N–1)Vdc/2}, if N is an odd number. The pole voltage va of an N-level MMC is an element of {(N–1)Vdc/2, (N– 3)Vdc/2, (N–5)Vdc/2, …, Vdc/2, –Vdc/2,…, –(N–3)Vdc/2, –(N–1)Vdc/2}, if N is an even number. Assume the expected ac-side voltage to be v* s. The pole voltage va follows the level-shifted modulation strategy. As shown in Figure3.16, N – 1 carriers are needed to determine N-level shape of va. The relationship of v* s and va is plotted in Figure3.17. Figure 3.16 Ac-side voltage v* s and carriers, when (a) N is an odd number; and (b) N is an even number. 49 1.5Vdc2π0(N–1)Vdc/2–(N–1)Vdc/212k(N–3 )/2(N+3)/2N–22Vdc2π012kN/2N/2+1N–2(a)(b)(N–1)Vdc/2–(N–1)Vdc/2v*sN–1v*sN–1carriercarrier Figure 3.17 Ac-side voltage v* s and pole voltage va, when (a) N is an odd number; and (b) N is an even number. When the pole voltage va at first level, one of the rows in Γ1 (N) will be assigned to the MMC as the chosen submodule pattern to realize this first-level pole-voltage. Recall that there is only one row in Γ1 (N), as formulated in (2.29). This row can be interpreted as this: SM1 to SMN – 1 are at by-pass mode, and SMN to SM2N – 2 are at inserting mode. The switches of each submodule need to follow this piece of Γ-matrix command accordingly. Similarly, when the pole voltage va at N-th level, one of the rows in ΓN (N) will be assigned to MMC as the chosen submodule pattern to realize this Nth-level pole-voltage. Recall that there is only one row in ΓN (N), as formulated in (2.32). This row can be interpreted as this: SM1 to SMN-1 are at inserting mode and SMN and SM2N-2 are at by-pass mode. The switches of each submodule need to follow this piece of Γ-matrix command accordingly. When the pole voltage va at k-th level, where 2 ≤ k ≤ N – 1, one of the rows in Γk (N) will be assigned to MMC as the chosen submodule pattern to realize this kth-level pole-voltage. 50 1.5Vdcπ2π0(N–1)Vdc/2–(N–1)Vdc/212k(N+1)/2(N–3 )/2(N+3)/2N–1N2Vdcvaπ2π012kN/2N/2+1N–1Nva(a)(b)(N–1)Vdc/2–(N–1)Vdc/2v*sv*s Recall that there are mk rows in Γk (N) where . The rank of Γk (N) is 2N – 3, which means only 2N – 3 rows in Γk (N) are needed to achieve the capacitor voltage balance. There are combinations of 2N – 3 rows in Γk (N) in total. However, not all of them have a rank of 2N – 3. Unlike two- and three-level MMC, N-level MMC submatrix, , needs careful selection. The extraction in this section follows the composition in Chapter 2.4 (2.30) - (2.31). The core submatrix, , of this composition procedure follows (2.16). This submatrix extraction may not be the optimal choice, but it is good enough to demonstrate the self voltage balancing of N-level MMC. The ΓMM procedure of N-level MMC are as follows, a. Determine the level of va by level-shifted modulation; b. Assign the instantaneous level number to the level pointer; c. Find the Γ-matrix pointer to which the level pointer points to; d. Read the Γ-matrix row (submodule pattern) which the Γ-matrix pointer points to; e. Generate the switching function for each submodule according to the current row of Γ matrix; f. Update Γ-matrix pointer to next row and wait for next call from level pointer. The N-level MMC modulation can also be explained with the aid of Figure3.18. To fully understand the self voltage balancing of N-level MMC, MATLAB/Simulink simulations are studied based on the Γ-matrix modulation. 51 ()211111kNkkkNNNmCCC−−−−−−==23kNmC−()ˆNkΓ()ˆNkΓ()ˆNkΓ()32ˆΓ Figure 3.18 Γ-matrix modulation strategy for N-level MMC. 3.4.1 CASE STUDY: ΓMM BASED FOUR-LEVEL MMC Objective: In this case study, the working principle and the performance of ΓMM based four-level MMC are studied through MATLAB/Simulink. The simulation topology is shown in Figure3.19. 52 Level 1Level 2Level NLevel PointerΓ-matrix PointerLevel k()1NΓ()2ˆNΓ()ˆNkΓ()NNΓ Figure 3.19 Four-level MMC simulation topology. Parameters: The key parameters of the MMC are as follows: rated apparent power S = 150 kVA, output phase voltage Va = Vb = Vc = 964 V, output line current Ia = Ib = Ic = 52 A, rated output fundamental frequency f0 = 60 Hz, rated load resistance Rload = 18.6 Ω, rated dc-bus voltage Vdc = 3 kV, number of submodules per arm: N – 1 = 3, submodule capacitance Ci = 171 µF (i = 1, 2, …, 18), line inductance Lline = 1 mH, and arm inductance Larm = 0.1 µH. The switching frequency is fsw = 30 kHz. The definition of switching frequency is the frequency of the MMC pole voltage jumping from one level to the other adjacent level. The key parameters are summarized in Table 3. 53 VdcVaiaidciuapidaowniubpidbowniucpidcownibicvcavbcvabVbVcLarmLlineVC3C3iC3VC4C4iC4VC9C9iC9VC15C15iC15VC16C16iC16RloadC1C7C6C18VC1VC7VC6VC18iC1iC7iC6iC18C2VC2iC2C8VC8iC8C5C17VC5VC17iC5iC17VC10C10iC10VC11C11iC11VC12C12iC12VC13C13iC13VC14C14iC14 Table 3 Four-level MMC simulation key parameters. Apparent Power, S 150 kVA Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 30 kHz DC-Bus Voltage, Vdc 3000 V Phase Voltage, Va, Vb, Vc 964 V Line Current, Ia, Ib, Ic 52 A Load Resistance, Rload 18.6 Ω (100% p.u.) Line Inductance, Lline 1 mH (2% p.u.) Arm Inductance, Larm 0.1 µH (0.0002% p.u.) Submodule Capacitance, Ci 171 µF (1.2 p.u.) Number of Submodules per Arm 3 where i = 1, 2, …, 18. Analysis: This four-level MMC simulation follows the Γ-Matrix Modulation strategy, as described in Figure3.20. The submatrices are as follows, , , (3.8) (3.9) 54 ()41000111=Γ()42010101010011ˆ001101100101010110=Γ (3.10) (3.11) , . Figure 3.20 Γ-matrix modulation strategy for four-level MMC. All submatrices are full rank. The load voltage and current are shown in Figure3.21. The mid-point voltage is shown in Figure3.22. The mid-point voltage of four-level MMC has seven levels. Although the mid-point voltage of any single phase, va vb or vc, has only four levels, the differential voltage of any two phases, vab vbc or vca, has seven levels. The submodule capacitor voltage and current are shown in Figure3.23. The capacitor voltage ripple is within 5%. The capacitor current consists mainly of fundamental component and switching-frequency harmonics. Note that the submodule capacitance is only 1.2 p.u.. The energy stored in capacitor is . (3.12) The total energy in all submodule capacitors is . (3.13) 55 ()43110100110010ˆ101100110001011100=Γ()44111000=ΓLevel 1Level 2Level 40 0 0 1 1 1Level PointerΓ-matrix PointerLevel 30 1 0 1 0 11 1 0 1 0 01 1 1 0 0 026210.517110100085.5 (J)2−===iiCiECV18211181539 (J)2====iiCitotaliEECV The four-level MMC power rating is 150 kVA. The total capacitor energy in respect to MMC power rating is . (3.14) Typically, the conventional MMC submodule capacitance is chosen such that the total stored energy in all submodule capacitors of the converter is approximately 30 – 40 kJ/MVA, where MVA refers to the converter rating, giving ripple in the range of 10% [37]. To have a voltage ripple within 5%, the conventional MMC needs to have submodule capacitors energy to be 60 – 80 kJ/MVA. Normally, the capacitor energy storage capability is proportional to the capacitor size. The ΓMM based MMC features an extremely small capacitor volume compared to conventional MMC. The capacitor voltage is well balanced and converging to the expected value (1000 V) in Figure3.23. However, the fundamental ripples still exist. These fundamental ripples are introduced by the arm inductor and stray resistance. Note that the capacitor voltage balance analysis in Chapter 1 does not consider the voltage drop on arm inductors and stray resistance. The effect of those passive components will be discussed in future work. Figure3.24 shows one line current and its corresponding arm current. The arm current contains not only fundamental component but also switching-frequency harmonics. Normally, the conventional MMC arm current does not contain many switching-frequency harmonics, and the arm inductance follows the equation (3.4) [38], where ω0 = 2πf0, VCi = 1000 V, and I2ω is the peak value of the 2-ω component in arm current. For conventional MMC, Ci = 60/10.26×171 µF = 1000 µF is needed to have a voltage ripple within 5%. Assume I2ω to be 13.8 A (Ia×26.5%). The arm inductance of conventional MMC should be 4.1 mH (8.24% p.u.) according to (3.4). The arm inductor of ΓMM based MMC is 56 3315391010.26 (kJ/MVA)15010−−===totalES extremely small comparing to conventional MMC. Small arm inductance is critical to balance the capacitor voltage. This will be explained in future work. Figure3.25 shows the input dc voltage and current. As seen from Figure3.25, the input current consists of dc component and switching-frequency harmonics. These switching- frequency harmonics can be mitigated by adding a decoupling capacitor at dc bus. Figure3.26 shows all capacitor voltages at phase-A. The capacitor voltages do not deviate from nominal value. Figure 3.21 Four-level MMC (a) load voltage and (b) load current. 57 Figure 3.22 Four-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. 58 Figure 3.23 Submodule capacitor (a)/(c) voltage; and (b)/(d) current. 59 Figure 3.24 (a) Line current in phase-A and its corresponding (b) upper arm current, (c) lower arm current. Figure 3.25 Dc input voltage and current. 60 Figure 3.26 All submodule capacitor voltages in phase-A. 3.4.2 CASE STUDY: ΓMM BASED FOUR-LEVEL MMC WITH NON-FULL- RANK Γ MATRIX Objective: In this case study, a non-full-rank Γ matrix is selected for the four-level MMC. Compared with case study in Chapter 3.4.1, the necessity of full-rank Γ matrix selection is addressed. The simulation topology is shown in Figure3.19. Parameters: All the converter parameters are the same as case study in Chapter 3.4.1. The key parameters of the MMC are as follows: rated apparent power S = 150 kVA, output phase voltage Va = Vb = Vc = 964 V, output line current Ia = Ib = Ic = 52 A, rated output fundamental frequency f0 = 60 Hz, rated load resistance Rload = 18.6 Ω, rated dc-bus voltage Vdc = 3 kV, number of submodules per arm: N – 1 = 3, submodule capacitance Ci = 171 µF (i = 1, 2, …, 18), line inductance Lline = 1 mH, and arm inductance Larm = 0.1 µH. The switching frequency is fsw = 30 kHz. The definition of switching frequency is the frequency of the MMC pole voltage jumping from one level to the other adjacent level. The key parameters are summarized in Table 3. Analysis: This four-level MMC simulation follows the Γ-Matrix Modulation strategy, as described in Figure3.20. The submatrices are as follows, , (3.15) 61 ()41000111=Γ , , (3.16) (3.17) . (3.18) The rank of each matrix are as follows, , , , and . (3.19) The rank of any two adjacent matrices are as follows, , , and . (3.20) The load voltage and current are shown in Figure3.27. The mid-point voltage is shown in Figure3.28. The mid-point voltage of four-level MMC has more than seven levels as the capacitor voltage deviates from its nominal value. The submodule capacitor voltage and current are shown in Figure3.29. The capacitor voltage has deviated from its nominal value over 30% after five fundamental cycles. Figure3.30 shows phase-A line current and its corresponding arms’ current. Figure3.31 shows the input dc voltage and current. As seen from Figure3.31, the input current consists of dc component and switching-frequency harmonics. These switching- frequency harmonics can be mitigated by adding a decoupling capacitor at dc bus. 62 ()42001101010011ˆ100110010101001011=Γ()43101100110010ˆ011001101010110100=Γ()44111000=Γ()411=rankΓ()42ˆ4=rankΓ()43ˆ4=rankΓ()441=rankΓ()()41425ˆ=rankΓΓ()()4243ˆ5ˆ=rankΓΓ()()4344ˆ5=rankΓΓ Figure3.32 shows all capacitor voltages at phase-A. The initial voltage of all capacitors is 1000 V. Capacitor voltage VC1 and VC6 are gradually reduced to 0 while VC2 to VC5 increase to 1500 V. Figure 3.27 Four-level MMC (a) load voltage and (b) load current. 63 Figure 3.28 Four-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. 64 Figure 3.29 Submodule capacitor (a)/(c) voltage; and (b)/(d) current. 65 Figure 3.30 (a) Line current and its corresponding (b) upper arm current, (c) lower arm current. Figure 3.31 Dc input voltage and current. 66 Figure 3.32 All submodule capacitor voltages in phase-A. 3.4.3 CASE STUDY: ΓMM BASED FOUR-LEVEL MMC WITH CAPACITANCE DEVIATION In this case study, one submodule capacitance is 50% larger than the other submodules to show that the proposed ΓMM has a good immunity to capacitance deviation. It is common that submodule capacitances are not exactly equal. The simulation topology is shown in Figure3.19. All the converter parameters and core submatrices are the same as Chapter 3.4.1, except for C3 is 257 µF. The capacitor voltages are self balanced as expected. The submodule capacitor C3 voltages is shown in Figure3.33. Figure3.34 shows all capacitor voltages in phase-A. All capacitor voltages are well balanced and converging to nominal value (1000 V). Figure 3.33 Submodule capacitor C3 voltage. 67 0.040.050.06Time (s)80010001200 VC30.0620.0621100510150.050.0501992994Capacitor Voltage (V) Figure 3.34 All submodule capacitor voltages in phase-A. 3.4.4 CASE STUDY: ΓMM BASED ELEVEN-LEVEL MMC Objective: In this case study, the working principle and the performance of ΓMM based eleven-level MMC are studied through MATLAB/Simulink. The simulation topology is shown in Figure3.35. Figure 3.35 Eleven-level MMC simulation topology. 68 00.050.10.150.20.25Time (s)800900100011001200 VC1 VC2 VC3 VC4 VC5 VC6Capacitor Voltage (V)VdcVaiaidciuapidaowniubpidbowniucpidcownibicvcavbcvabVbVcLarmLlineVC10C10iC10VC11C11iC11VC30C30iC30VC50C50iC50VC51C51iC51RloadC1C21C6C60VC1VC21VC20VC60iC1iC21iC20iC60VC31C31iC31VC40C40iC40VC41C41iC41 Parameters: The key parameters of the MMC are as follows: rated apparent power S = 500 kVA, output phase voltage Va = Vb = Vc = 3200 V, output line current Ia = Ib = Ic = 52 A, rated output fundamental frequency f0 = 60 Hz, rated load resistance Rload = 62 Ω, rated dc-bus voltage Vdc = 10 kV, number of submodules per arm: N – 1 = 10, submodule capacitance Ci = 769 µF (i = 1, 2, …, 60), line inductance Lline = 1 mH, and arm inductance Larm = 0.1 µH. The switching frequency is fsw = 60 kHz. The definition of switching frequency is the frequency of the MMC pole voltage jumping from one level to the other adjacent level. The key parameters are summarized in Table 4. Table 4 Eleven-level MMC simulation key parameters. Apparent Power, S 500 kVA Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 60 kHz DC-Bus Voltage, Vdc 10 kV Phase Voltage, Va, Vb, Vc 3200 V Line Current, Ia, Ib, Ic 52 A Load Resistance, Rload 62 Ω (100% p.u.) Line Inductance, Lline 1 mH Arm Inductance, Larm 0.1 µH (0.61% p.u.) (0.00006% p.u.) Submodule Capacitance, Ci 770 µF (18 p.u.) Number of Submodules per Arm 10 69 where i = 1, 2, …, 60. Analysis: This eleven-level MMC simulation follows the Γ-Matrix Modulation strategy, as described in Figure3.18. The extraction in this section follows the composition in Chapter 2.4 Eq.(2.30) and (2.31). The initial core submatrix, , of this composition procedure follows (2.16). The load voltage and current are shown in Figure3.36. The mid-point voltage is shown in Figure3.37. The mid-point voltage of eleven-level MMC has 17 levels. Although the mid-point voltage of any single phase, va vb or vc, has only 11 levels, the differential voltage of any two phases, vab vbc or vca, has 17 levels. The submodule capacitor voltage and current are shown in Figure3.38. The capacitor voltage ripple is within 6%. The capacitor current consists mainly of fundamental component and switching-frequency harmonics. Note that the submodule capacitance is 18 p.u.. The energy stored in capacitor is The total energy in all submodule capacitors is . . (3.21) (3.22) The eleven-level MMC power rating is 500 kVA. The total capacitor energy in respect to MMC power rating is . (3.23) Typically, the conventional MMC submodule capacitance is chosen such that the total stored energy in all submodule capacitors of the converter is approximately 30 – 40 kJ/MVA, where MVA refers to the converter rating, giving ripple in the range of 10% [37]. 70 ()ˆNkΓ()ˆNkΓ()32ˆΓ26210.5770101000385 (J)2iiCiECV−===602116023100 (J)2====iiCitotaliEECV33231001046.2 (kJ/MVA)50010−−===totalES To have a voltage ripple within 6%, the conventional MMC needs to have submodule capacitors energy to be 50 – 67 kJ/MVA. Normally, the capacitor energy storage capability is proportional to the capacitor size. The ΓMM based MMC features smaller capacitor volume compared to conventional MMC. The capacitor voltage is well balanced and converging to the expected value (1000 V) in Figure3.38. However, the fundamental ripples still exist. These fundamental ripples are introduced by the arm inductor and stray resistor. Note that the capacitor voltage balance analysis in previous sections did not consider the voltage drop on arm inductors and stray resistors. The effect of those passive components will be discussed in future work. Figure3.39 shows line current in phase-A and its corresponding arm current. The arm current contains not only fundamental component but also switching-frequency harmonics. Normally, the conventional MMC arm current does not contain many switching-frequency harmonics, and the arm inductance follows the equation (3.4) [38], where ω0 = 2πf0, VCi = 1000 V, and I2ω is the peak value of the 2-ω component in arm current. For conventional MMC, Ci = 50/46.2×770 µF = 833 µF to have a voltage ripple within 6%. Assume I2ω to be 13.8 A (Ia×26.5%). The arm inductance of conventional MMC should be 23.3 mH (14.2% p.u.) according to (3.4). The arm inductor of ΓMM based MMC is extremely small compared to conventional MMC. Small arm inductance is critical to balance the capacitor voltage. This will be explained in future work. Figure3.40 shows the input dc voltage and current. As seen from Figure3.40, the input current consists of dc component and switching-frequency harmonics. These switching- frequency harmonics can be mitigated by adding a decoupling capacitor at dc bus. 71 Figure3.41 shows all capacitor voltages at phase-A. The capacitor voltages do not deviate from nominal value. Figure 3.36 Eleven-level MMC (a) load voltage and (b) load current. 72 Figure 3.37 Eleven-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. 73 Figure 3.38 Submodule capacitor (a)/(c) voltage; and (b)/(d) current. 74 Figure 3.39 (a) Line current in phase-A and its corresponding (b) upper arm current, (c) lower arm current. Figure 3.40 Dc input voltage and current. 75 Figure 3.41 All submodule capacitor voltages in phase-A. The process of MMC operation is similar to the calculation of the power flow by iterations. In the first iteration of power flow calculation, an initial estimation of the unknowns will be provided to the first equation of the equation set. This initial estimation does not necessarily be the solution for the first equation. A specific iteration law, Newton-Raphson for example, will be provided to find a solution for the first equation based on the initial estimation. Once we have a solution for the first equation, this solution is inserted into the next equation as the initial estimation. Then the iteration law will again be applied to find the solution for the second equation. This iteration will be repeated until the solution converges. That is to say, the solution only makes a slight change each time of the iteration. So, this solution is deemed to be close enough to the analytical solution we are looking for. The difference between power flow calculation and MMC voltage balancing calculation we set up in this Chapter is that the iterations are done by software in power flow calculation, whereas the iterations are done by hardware in MMC. MMC model provides an iteration law, which is equivalent to Newton-Raphson, so that the solution gets closer to the analytical solution after each iteration. In another word, MMC operation is emulating the software iteration to find the solution for capacitor voltage equations set up in Part I. 76 So, the capacitor voltage equations are actually a virtual equation set. The inductor voltage could be regarded as a computation error, or measurement error, during these iterations. This iteration law provided by MMC physical nature is robust enough to immune to the error introduced by arm inductor. This Chapter proposed a Γ-Matrix Modulation for MMC. With this novel modulation, the MMC achieves self voltage balancing. This can extremely simplify, or even eliminate, the capacitor voltage balancing control for MMC. Conventionally, either a complicated voltage balancing control, or extra components must be embedded to MMC to balance the capacitor voltage, which increases the MMC cost. Compared to conventional MMC capacitor voltage balancing strategies, ΓMM features extremely simple algorithms and good reachability to high-level MMCs while maintaining the original half-bridge submodule topology. Four- and eleven-level MMC cases are studied to verify the effectiveness of ΓMM. 77 4 THE STATE-SPACE MODEL OF MODULAR MULTILEVEL CONVERTER In Figure3.32, we have seen a mysterious phenomenon: capacitor voltage VC1 and VC6 are gradually reduced to 0 while VC2 to VC5 increase to 1500 V. Although the capacitor voltages diverge as we expect, we do not expect the voltages end up with these values from our previous analysis. The Γ-matrix selected for Chapter 3.4.3 are as follows , , , . (4.1) (4.2) (4.3) (4.4) The rank of each matrix are as follows, , , , and . (4.5) The rank of any two adjacent matrices are as follows, , , and . (4.6) The voltage balancing equations of this Γ-matrix are as follows 78 ()41000111=Γ()42001101010011ˆ100110010101001011=Γ()43101100110010ˆ011001101010110100=Γ()44111000=Γ()411=rankΓ()42ˆ4=rankΓ()43ˆ4=rankΓ()441=rankΓ()()41425ˆ=rankΓΓ()()4243ˆ5ˆ=rankΓΓ()()4344ˆ5=rankΓΓ The solutions of (4.7)-(4.9) are as follows (4.7) (4.8) (4.9) (4.10) These solutions are not unique. In another word, Eq.(4.7)-(4.9) have infinite many solutions. VC1 and VC6 could be zero as observed in Figure3.32. They could also be other numbers. For example, (4.11) Another example (4.12) Eq.(4.11) and (4.12) are just two possible solutions for (4.7)-(4.9). Actually, (4.7)-(4.9) should have infinite many solutions since they are non-full-rank. Among (4.11) and (4.12), Eq.(4.12) could be observed in Figure3.32 during the transition of the capacitor voltage to 79 ()()1412426163ˆ3=CdcCdcCVVVVVΓY()()14224310163ˆˆ3=CdcCdcCVVVVVΓΓ()()1423446163ˆ3=CdcCdcCVVVVVΓΓ162345123 3CCCCCCCCCdcVVVVVVVVVV====++=1623450 3CCdcCCCCVVVVVVV======162345 01.2.6CCdcCCCCdcVVVVVVVV====== the new steady state. Eq.(4.11) does not ever exist either during the transition or in the steady state. Our previous analysis could not explain this phenomenon. We need to set up a proper dynamic model for MMC to understand this phenomenon, so that we might have a chance to predict and control the behavior of those capacitors in the future. Many literatures have modeled MMC for different purposes and scenarios. For example, i) The MMC is modeled as a whole system in order to understand the interaction between MMCs and other objectives (power grid, load, etc.) [39]-[41]. Normally, this type of models is for system level controller design. ii) The MMC is modeled by arm or submodules in order to understand the internal state variables dynamics [42]-[52]. Normally, this type of modeling ends up with internal state variable regulations. iii) The MMC is modeled to evaluate a specific state variable at steady state[53]- [55]. This type of MMC modeling loses most of the dynamic properties of MMC but becomes an effective guidance for parameter design. iv) The MMC is modeled for real-time simulation [56]-[61]. The existing literature proposes numerous simplified and computationally-efficient equivalent models for MMC to meet with the fast calculation of real-time simulation. Most of the models developed so far differ from each other on the basis of different degree of assumptions and simplification. This makes them unsuitable for understanding the nature of this circuit from its physical basement. Wang et. [51] proposed a state-space switching model, which is derived from accurate mathematical model without losing any characteristics of MMC. However, the aim of [51] is to develop a control to minimize the 80 submodule capacitance and arm inductance. Therefore, the state variables selected in [51] are control oriented. This made it unsuitable for understanding the dynamics of MMC. [45] proved that the arm voltage converges to equilibrium point by nature from Lyapunov method. The model in [45] reduces the dimension of the system by assuming that all submodules per arm have identical dynamics. The Lyapunov energy function proposed in [45] has the potential to evaluate the system stability quantitively, however, the composition of the Lyapunov energy function is complicated for high order systems. The existing models are not suitable for understanding the MMC circuit from its physical basement. We need to have a model that is accurate enough to demonstrate the mechanism of the self balance nature of MMC. Switched circuits in power electronics naturally present hybrid behavior. Such circuits can be described by a set of discrete states with associated continuous dynamics. All power electronic systems can be categorized to hybrid system from control theory point of view. However, we seldomly evaluate our power electronic systems using the knowledge from hybrid system analysis. [62] set a good example for how to apply hybrid system analysis on a boost converter. This Chapter proposes a comprehensive state-space model for MMC system that consistent with hybrid system analysis. With this state-space model, the mechanism of the self balance nature of MMC system could be well explained. This Chapter is organized as follows: The prior art of MMC modeling is summarized in Chapter 4.3. The contribution of this Chapter is summarized in Chapter 4.4. The principle of Γ-Matrix Modulation is reviewed in Chapter 4.5. The state-space model of 2-level MMC is derived in Chapter 4.6. The model 81 is extended to 3-level MMC in Chapter 4.7. A general state-space model of N-level MMC is derived in Chapter 4.8. The effectiveness of the proposed stability analysis is verified by comparing the proposed state-space model with simulation studies. In the stability analysis of an MMC-HVDC system, MMC is normally modeled as a voltage-source converter (VSC) [39]-[41]. The VSC model is shown in Figure4.1. The model can well interpret the oscillation of a certain state under the controller and the corresponding power network or load. This type of modeling is usually established on the small signal modeling and focused on the phasor/magnitude dynamics. This MMC model can well serve the controller design, especially the DC voltage control (DVC) in timescale around 10Hz. However, the simplified VCS model contains only one equivalent dc link capacitor, either time invariant or time variant. This simplification is suitable for high-level MMC since all the submodule capacitors are reduced to one equivalent dc-link capacitor. One limitation for the VSC model is that the dynamics of individual cells cannot be differentiated from the others in the given model as all of them assumed to be identical. Figure 4.1 The VSC model of MMC. The MMC is modeled by selecting different internal states in order to understand the internal state variables dynamics [42]-[52]. The selection of the states can be classified into time domain[45]-[52] and frequency domain[42]-[44], [63]-[64]. The frequency domain 82 ModulationControl loop 1Control loop 2PLLInternal statesInternal statesEttUiitXeqXgMMC ModelPower Network/ Load state variables contain the independent harmonic states. This will increase the complexity of the Harmonic State Space (HSS). The effects of a zero-sequence voltage are included in some HSS MMC models [63]-[64]. They are all three-phase models with a large number of state variables. Therefore, a single-phase MMC model considering zero-sequence voltage is proposed in [42] to reduce the number of state variables. The time domain models different from each other by selecting different state variables. The most common time domain model is arm averaged model (AAM)[45]-[50]. AAM assumes that the voltage distribution among the submodules in each arm is equal. This assumption implies that the capacitor voltage is well balanced among each arm. AAM can significantly reduce the complexity of MMC model while maintaining an accurate representation of the internal dynamics. For three-phase MMC, there are five independent loop currents and six independent node voltages in topology as shown in Figure4.2. These eleven states can be selected as state variables to derive the state-space model of MMC. Other than selecting these eleven state variables, these states can be manipulated into other states by linear operations, for example sum and difference of any two states. Figure4.3 shows several ways to select loop currents. Figure4.4 shows the node voltages are manipulated to be common-mode and differential-mode states. Figure4.5 shows combinations of loop current selection and node voltage selection. 83 Figure 4.2 Five independent loop currents and six independent node voltages in topology. (a) Figure 4.3 Loop current selection (a) single-phase oriented [47]-[48] (b) inductor current oriented [49]-[50] and (c) circulating current oriented [45],[51]-[52]. 84 iL5iL4iL3iL2iL1+–+–+–+–+–+–VdcvC1vC2vC3vC4vC5vC6iL5iL4iL3iL2iL1+–+–+–+–+–+–VdcvC1vC2vC3vC4vC5vC6 Figure 4.3 (cont’d) (b) (c) 85 iL5iL2iL1+–+–+–+–+–+–VdcvC1vC2vC3vC4vC5vC6iL3iL4iL5iL4iL3iL2iL1+–+–+–+–+–+–VdcvC1vC2vC3vC4vC5vC6 Figure 4.4 Common-mode and differential-mode voltage as state variables [46]. (a) Figure 4.5 State variable selections (a) dc current + common/differential-mode voltage oriented (b) inductor current + common/differential-mode voltage oriented and (c) circulating current + common/differential-mode voltage oriented. 86 iL5iL4iL3iL2iL1VdcvC2vC1+–+–+–+–+–+–+–+–+–+–+–+–vC1vC2vC4vC3vC6vC5vC3vC4vC5vC6VdcvC2vC1+–+–+–+–+–+–+–+–+–+–+–+–vC1vC2vC4vC3vC6vC5vC3vC4vC5vC6iL5iL4iL3iL2iL1Vdc Figure 4.5 (cont’d) (b) (c) AAM eliminates most of the dynamic difference among the submodule voltages. [51] proposed a switching cycle model (SCM) that discriminates the dynamics of submodule voltages. The SCM assigns each submodule with an independent state. MMCs are also model for other purposes. The MMC is modeled to evaluate a specific state variable at steady state[53]-[55]. This type of MMC modeling loses most of the dynamic properties of MMC but becomes an effective guidance for parameter design. The 87 VdcvC2vC1+–+–+–+–+–+–+–+–+–+–+–+–vC1vC2vC4vC3vC6vC5vC3vC4vC5vC6iL5iL2iL1iL3iL4VdcvC2vC1+–+–+–+–+–+–+–+–+–+–+–+–vC1vC2vC4vC3vC6vC5vC3vC4vC5vC6iL5iL4iL3iL2iL1 MMC is modeled for real-time simulation [56]-[61]. The existing literature proposes numerous simplified and computationally efficient equivalent models for MMC to meet with the fast calculation of real-time simulation. The selection of MMC internal state variables are summarized in Figure4.6. Figure 4.6 The selection of MMC internal state variables. The model proposed in this Chapter falls into the category of SCM. The SCM assigns each submodule with an independent state. The state variables selected in [51] focus on the circulating current and three-phase MMC, which increase the number of state variables. This dissertation proposes a comprehensive state-space model for single-phase MMC system that reduces the number of state variables compared to [51]. With this state-space model, the convergence/divergence of submodule voltage could be well captured. The state variable selection of [51] is shown in Figure4.7. The selection of state variables of this Chapter is shown in Figure4.8. For an N-level MMC, there are 6N – 1 states needed in [51], whereas only 2N states needed in this dissertation. 88 Internal State Variable SelectionTime DomainFrequency DomainSwitching Cycle Model (SCM)• Assign each submodule with an independent state• Most accurate model of MMC• State variable selected on the basis of control/observing interest• Increased state space complexityFocus of this dissertationArm Averaged Model (AAM)• Assume the dynamics of submodules are identical in each arm• Focus on the certain internal state variables • Suitable for controller design to regulate internal states of interests• Reduced state space complexitynode voltageloop currentcommon/diferential-mode voltagecommon/differential-mode currentd-q Frame• Focus on fundamental frequency• Derived from AAM• Assume the dynamics of submodules are identical• Prerequisite for linearization at equilibrium Harmonic State Space (HSS)• Focus on harmonic components• Derived from AAM• Assume the dynamics of submodules are identical • Assign each harmonic with an independent state• Increase state space complexitysingle-phase• Simple in state space• Low accuracy in catching dynamicsthree-phase• Complex in state space• High accuracy in catching dynamics Figure 4.7 The state variable selection of [51]. Figure 4.8 The state variable selection of this dissertation. Γ-Matrix Modulation (ΓMM) was proposed in Chapter 3 [65]-[66]. This novel modulation utilizes the self balance nature of MMC so that the voltage balancing control of MMC is eliminated. ΓMM contains two stages. Namely, level pointer preparation and Γ-matrix adaptation. 89 VdciL5iL4iL3iL2iL1VdcVC1C1VC3C3VC5C5VC2C2VC4C4VC6C6VdcVdcVC1C1VC2C2iL1iL2 4.5.1 LEVEL POINTER PREPARATION An N-level MMC is plotted in Figure4.9. A N-level MMC contains N – 1 submodules on upper arm and N – 1 submodules on lower arm. For an N-level MMC, there are N – 1, and only N – 1, out of 2N – 2 submodules at inserting mode at a time. The other N – 1 submodules are at by-pass mode meanwhile. Therefore, there are N possible levels on pole voltage va. The numbering of levels in an N-level MMC is shown in Figure4.10. Figure 4.9 N-level MMC circuit. 90 SM1SM2SMN-1SMNSM2N-3SM2N-2VsisVL1VL2i1i2vaVC2C2(N-1)Vdc/2(N-1)Vdc/2 Figure 4.10 Numbering of levels in an N-level MMC, when (a) N is an odd number; and (b) N is an even number. There are multiple ways to determine the pole voltage level[67]. Phase-disposition (PD) modulation is adopted in this Chapter to determine the pole voltage level. Other methods should also work properly for level pointer preparation. N – 1 carriers are needed to determine N-level shape of va. The carriers are plotted in Figure4.11. The relationship of v* s and va is plotted in Figure4.12. 91 1.5Vdcπ2π0(N–1)Vdc/2–(N–1)Vdc/212k(N+1)/2(N–3 )/2(N+3)/2N–1N2VdcVsvaπ2π012kN/2N/2+1N–1NVsva(a)(b)(N–1)Vdc/2–(N–1)Vdc/2 Figure 4.11 ac-side voltage v* s and carriers, when (a) N is an odd number; and (b) N is an even number. Figure 4.12 ac-side voltage v* s and pole voltage va, when (a) N is an odd number; and (b) N is an even number. The outcome of PD modulation is assigned to the level pointer. 92 1.5Vdc2π0(N–1)Vdc/2–(N–1)Vdc/212k(N–3 )/2(N+3)/2N–22Vdc2π012kN/2N/2+1N–2(a)(b)(N–1)Vdc/2–(N–1)Vdc/2v*sN–1v*sN–1carriercarrier1.5Vdcπ2π0(N–1)Vdc/2–(N–1)Vdc/212k(N+1)/2(N–3 )/2(N+3)/2N–1N2Vdcvaπ2π012kN/2N/2+1N–1Nva(a)(b)(N–1)Vdc/2–(N–1)Vdc/2v*sv*s 4.5.2 Γ-MATRIX ADAPTATION There are always no less than one switching pattern to achieve an arbitrary level of va. One possible selection of switching pattern, namely Γ-Matrix subtraction, is proposed in [61]. The method extremely reduces the Γ dimension to a practical number. MMC achieves self balancing with this Γ-matrix selection[62]. The submatrix extracted from Γ is a mk- by-(2N – 2) matrix, where . There are still no less than one switching pattern to achieve an arbitrary level of va if using . The Γ-matrix adaptor determines the specific row in to achieve a certain level of va. Recall that of an N-level MMC are as follows, (4.13) is a matrix that contains all the selected switching patterns to achieve level k for an N-level MMC. When the level pointer at first level, Γ1 (N) is chosen as the switching pattern to implement this first-level pole-voltage. Similarly, when the pole voltage va at N-th level, ΓN (N) is chosen as the switching pattern to implement this level-N pole-voltage. Recall that Γ1 (N) and ΓN (N) are as follows, , (4.14) 93 ˆΓ1122−−−−−=kNkkNNmCCˆΓˆΓˆΓ()()()()()12()1ˆˆˆˆ−=NNNNkNNNNΓΓΓΓΓΓ()ˆNkΓ()111[0011]−−=NNNΓk . (4.15) When the level pointer at k-th level, where 2 ≤ k ≤ N – 1, is chosen to implement this kth-level pole-voltage. There are multiple ways to compose . The composition in this Chapter follows Chapter 3, which is where 2 ≤ k ≤ N – 2. where k = N – 1. , , (4.16) (4.17) and are core submatrices from (N – 1)-level MMC. Tk-1(a) (N-1) is derived from by manipulating the right most “1” in first row of to “0”. Tk-1(b) (N-1) is derived from by manipulating the left most “0” in first row of to “1”. There are multiple switching patterns to achieve k-th level. Γ-matrix adaptor determines the exact switching pattern for MMC when level pointer visits level k. Γ-matrix adaptor reads the current switching pattern that the Γ-matrix pointer points to. Then, reassign the Γ-matrix pointer to the next switching pattern and wait for the next call from level pointer. The ΓMM for N-level MMC can also be explained with the aid of Figure4.13. 94 ()11[1100]−−=NNNNΓk()ˆNkΓ()ˆNkΓ()ˆNkΓ()()()()()()11111ˆˆ1100−−−−−=NkNNkkaNkb0Γ1ΓTT()()()()()()11111111ˆ00ˆ−−−−−−=NkaNNkkbNkTTΓ1Γ0()1ˆ−NkΓ()11ˆ−−NkΓ()11ˆ−−NkΓ()11ˆ−−NkΓ()11ˆ−−NkΓ()11ˆ−−NkΓ Figure 4.13 Γ-matrix modulation for N-level MMC. We need to find the state-space model of MMC to demonstrate the dynamics of the system. Figure4.14 shows a two-level MMC that is under analysis in this section. Figure4.15 shows the simplified MMC model. For a two-level MMC, there are two feasible switching patterns. Either the upper submodule or the lower submodule is inserted. The following section will model the two-level MMC for each switching pattern. (a) (b) Figure 4.14 two-level MMC with pole connected to (a) positive dc rail (Level 1); and (b) negative dc rail (Level 2). 95 Level 1Level 2Level NLevel PointerΓ-matrix PointerLevel k()1NΓ()2ˆNΓ()ˆNkΓ()NNΓVC11/2Vdc1/2VdcVsVC2vaC1C2VC11/2Vdc1/2VdcVsVC2vaC1C2isisi1i2VL1VL2VL1VL2i1i2 (a) (b) Figure 4.15 two-level MMC model with pole connected to (a) positive dc rail; and (b) negative dc rail. 4.6.1 STATE-SPACE MODEL Figure4.15(a) can be formulated as . (4.18) The corresponding switching pattern is . (4.19) Define the state variables to be 96 1/2Vdc1/2VdcVC2C2isVL1VL2i1i2is1/2Vdc1/2VdcVC1C1isVL1i1i2isVL2LLLL112222212122LLCsdcLLCdiVLdtdiVLdtdViCdtkiiiVVVVkk====+=++()2101=Γ , . (4.20) Rewrite (4.18) into state equation form, , (4.21) 97 11221324CCixixVxVx==X11221342CCdidtxdixdtdVxdtxdVdt==X14244221112221112221sdcsdcdixxVLLdtdixxVLLdtxxCk=−++=−+−= or . (4.22) 98 1123421234312341412342111100222211110022221001010100010000sdcsdcdixxxxxVLLLdtdixxxxxVLLLdtxxxxxCxxxxxC=++−+−++=++−+−+−=++++=++++ Rewrite (4.22) into matrix form, . (4.23) The coefficient marked in red contains the information from switching patter Γ1 (2). The system matrices are , , and . (4.24) The coefficient matrix could be decomposed as follows, 99 112233144211002211112200221112200000001000101010dcsLLxxLVLLxxdiLxxdtCxxC−−−−−=+1201010111002211002210001000LLLLCC−−−−=A112211220000LL−=BdcsVdidt=U . (4.25) . (4.26) . (4.27) . . (4.28) (4.29) diag operator returns a column vector of the main diagonal elements of the objective matrix. contains the parameters from arm inductance. and contains the parameters from submodule capacitance. The reason to decompose the state space in such form is to save the work for programming. It will be easy to extent to high level state space by decomposing the matrix into such form. 100 1211002211002210001010101000LCLLLLCC−−−−==0AAA0()21111222ˆ111212201001−−−===−−−LLLLLLLLAAΓ1210ˆ1010CCCCC==AAA()()2111ˆˆ01'0==CCCdiagdiagAAΓ()()212001'1==CCdiagdiagCAAΓˆLAˆ'CA'CA Note that U contains . reflects the voltage across the load inductor. That is , (4.30) as modeled in Figure4.16. Figure 4.16 Load inductor voltage modeling. If the pole is attached to the positive dc rail, as shown in Figure4.14(a) and Figure4.15(a), va = 1/2Vdc. Eq.(4.30) can be modified as Replace the in (4.23) by (4.31) Figure4.15(b) can be formulated as . . . The corresponding switching pattern is 101 (4.31) (4.32) (4.33) sdidtsdidtsaasdiLvVdt=−isVsvaLa11()2sdcsadiVVdtL=−sdidt11()2=−dcdcsaVVVLkkkkkU112211112121LLCsdcLLCdiVLdtdiVLdtdViCdtkiiiVVVVkk====+=++ . (4.34) Define the state variables to be , . (4.35) Rewrite (4.33) into state equation, (4.36) 102 ()2210=Γ11221324CCixixVxVx==X11221342CCdidtxdixdtdVxdtxdVdt==X13233111112221112221sdcsdcdixxVLLdtdixxVLLdtxxCk=−++=−+−= or . (4.37) 103 1123421234312341412342111100222211110022221010101000010000sdcsdcdixxxxxVLLLdtdixxxxxVLLLdtxxxxxCxxxxxC=++−+−++=++−+−+−=++++=++++ Rewrite (4.37) into matrix form, . (4.38) The coefficient marked in red contains the information from switching patter Γ2 (2). The system matrices are , , and . (4.39) The coefficient matrix could be decomposed as follows, 104 112233144211002211112200221112200000001001010100dcsLLxxLVLLxxdiLxxdtCxxC−−−−−=+1210101011002211002210001000LLLLCC−−−−=A112211220000LL−=BdcsVdidt=U . (4.40) . (4.41) . (4.42) . . (4.43) (4.44) diag operator returns a column vector of the main diagonal elements of the objective matrix. contains the parameters from arm inductance. and contains the parameters from submodule capacitance. The reason to decompose the state space in such form is to save the work for programming. It will be easy to extent to high level state space by decomposing the matrix into such form. 105 1211002211002210010101001000LCLLLLCC−−−−==0AAA0()21111222ˆ111202210110−−−===−−−LLLLLLLLAAΓ1210ˆ1100CCCCC==AAA()()212101ˆˆ'0==CCCdiagdiagAAΓ()()222100'1==CCdiagdiagCAAΓˆLAˆ'CA'CA Note that U contains . reflects the voltage across the load inductor. That is , (4.45) as modeled in Figure4.16. If the pole is attached to the negative dc rail, as shown in Figure4.14(b) and Figure4.15(b), va = – 1 /2Vdc. Eq.(4.45) can be modified as Replace the in (4.39) by (4.46) . . (4.46) (4.47) 4.6.2 STATE-SPACE MODEL WITH STRAY RESISTANCE The stray resistance is essential in the real MMC installations or simulations. The pole voltage va of a two-level MMC can either be 1/2Vdc or -1/2Vdc as shown in Figure4.17. To calculate the arm inductor voltage, we need to find the state equation of MMC. Figure4.18 shows the simplified MMC model. Figure4.18(a) can be formulated as . (4.48) 106 sdidtsdidtsaasdiLvVdt=−11()2sdcsadiVVdtL=−−sdidt11()2dcdcsaVVVL=−−U11222221211222LLCsdcLRRLCdiVLdtdiVLdtdViCdtVkkkiiiVVVVV====+=++++ (a) (b) Figure 4.17 Two-level MMC with pole connected to (a) positive dc rail (Level 1); and (b) negative dc rail (Level 2). (a) (b) Figure 4.18 Two-level MMC model with pole connected to (a) positive dc rail; and (b) negative dc rail. The corresponding switching pattern is . (4.49) Define the state variables to be 107 Vdc1/2Vdc1/2VdcVsVdcvaC1C2VL1VR1VR2VL2i1i2isVdc1/2Vdc1/2VdcVsVdcvaC1C2VL1VR1VR2VL2i1isi21/2Vdc1/2VdcVC2C2isVL1VR2i1i2isLRRVR1VL2L1/2Vdc1/2VdcisVR1i1i2isRVC1C1VL1LVR2RVL2L()2101=Γ , . (4.50) Rewrite (4.48) into state equation form, , (4.51) 108 11221324==CCixixVxVxX11221342CCdidtxdixdtdVxdtxdVdt==X1124212442211122222111222221sdcsdcdiRRxxxxVLLLLdtdiRRxxxxVLtkLLLdxxC=−−−++=−−−+−= or . (4.52) 109 1123421234312341111122222211112222221010000010sdcsdcRRdixxxxxVLLLLLdtRRdixxxxxVLLLLLdtxxxxxCx=−+−+−+−++=−+−+−+−+−=++++412342100100xxxxC=++++ Rewrite (4.52) into matrix form, . (4.53) The coefficient marked in red contains the information from switching patter Γ1 (2). The system matrices are , , and . (4.54) The coefficient matrix could be decomposed as follows, 110 112233144211222211112222221112200000001000010101dcRRLLLLRRxxLVLLLLxxdiLxxCxxC−−−−−−−−−=+sdt1211222211222210001010101000RRLLLLRRLLLLCC−−−−−−−−=A112211220000LL−=BdcsVdidt=U . (4.55) . (4.56) . (4.57) . (4.58) . . (4.59) (4.60) diag operator returns a column vector of the main diagonal elements of the objective matrix. contains the parameters from arm inductance. and contains the parameters from submodule capacitance. The reason to decompose the state space in such 111 1211222211222210001000101001RLCRRLLLLRRLLLLCC−−−−−−−−==AAAA02222RRRLLRRLL−−=−−A()21111222ˆ111212201001−−−===−−−LLLLLLLLAAΓ1210ˆ1010CCCCC==AAA()()2111ˆˆ01'0==CCCdiagdiagAAΓ()()212001'1==CCdiagdiagCAAΓˆLAˆ'CA'CA form is to save the work for programming. It will be easy to extent to high level state space by decomposing the matrix into such form. Note that U contains . reflects the voltage across the load inductor. That is , (4.61) as modeled in Figure4.16. If the pole is attached to the positive dc rail, as shown in Figure4.17(a) and Figure4.18(a), va = 1/2Vdc. Eq.(4.61) can be modified as Replace the in (4.54) by (4.62) Figure4.18(b) can be formulated as . . (4.62) (4.63) . (4.64) The corresponding switching pattern is . (4.65) 112 sdidtsdidtsaasdiLvVdt=−11()2sdcsadiVVdtL=−sdidt11()2dcdcsaVVkVLkkkk=−U11221211211221LLCsdcLRRLCdiVLdtdiVLdtdViCdtVkkkiiiVVVVV====+=++++()2210=Γ Define the state variables to be , . (4.66) Rewrite (4.64) into state equation, (4.67) 113 11221324CCixixVxVx==X11221342CCdidtxdixdtdVxdtxdVdt==X1123212331111122222111222221sdcsdcdiRRxxxxVLLLLdtdiRRxxxxVLtkLLLdxxC=−−−++=−−−+−= or . (4.68) 114 1123421234312341111122222211112222221000101100sdcsdcRRdixxxxxVLLLLLdtRRdixxxxxVLLLLLdtxxxxxCx=−+−+−+−++=−+−+−+−+−=++++412342100000xxxxC=++++ Rewrite (4.68) into matrix form, . (4.69) The coefficient marked in red contains the information from switching pattern Γ2 (2). The system matrices are , , and . (4.70) The coefficient matrix could be decomposed as follows, 115 112233144211222211112222221112200000001000101010dcRRLLLLRRxxLVLLLLxxdiLxxCxxC−−−−−−−−−=+sdt1211222211222210001101010000RRLLLLRRLLLLCC−−−−−−−−=A112211220000LL−=BdcsVdidt=U . (4.71) . (4.72) . (4.73) . (4.74) . . (4.75) (4.76) diag operator returns a column vector of the main diagonal elements of the objective matrix. contains the parameters from arm inductance. and contains the parameters from submodule capacitance. The reason to decompose the state space in such 116 1211222211222210001001010100RLCRRLLLLRRLLLLCC−−−−−−−−==AAAA02222RRRLLRRLL−−=−−A()22111222ˆ111202210110−−−===−−−LLLLLLLLAAΓ1210ˆ1100CCCCC==AAA()()212101ˆˆ'0==CCCdiagdiagAAΓ()()222100'1==CCdiagdiagCAAΓˆLAˆ'CA'CA form is to save the work for programming. It will be easy to extent to high level state space by decomposing the matrix into such form. Note that U contains . reflects the voltage across the load inductor. That is , (4.77) as modeled in Figure4.16. If the pole is attached to the negative dc rail, as shown in Figure4.17(b) and Figure4.18 (b), va = – 1 /2Vdc. Eq.(4.77) can be modified as Replace the in (4.70) by (4.78) . . (4.78) (4.79) 4.6.3 MODEL ANALYSIS AND SIMULATION To prove the correctness of the proposed state-space model, the simulation of a two- level single phase MMC model in MATLAB/Simulink is conducted for comparison. To simulate the proposed model, the differential equations of the state-space model (4.53) and (4.69) are discretized as follows, , , 117 (4.80) (4.81) (4.82) (4.83) , , sdidtsdidtsaasdiLvVdt=−11()2sasadivVdtL=−−sdidt11()2dcdcsaVVVL=−−UddtX=AX+BUddtdtX=AX+BU()()()()()1111kkkkTkT−−−−−XX=AX+BU()()()()()1111kkkTkTk−−−+−X=AX+BUX A time-step of ∆T = 0.1 μs was used to make sure the approximation is accurate enough. The system matrix A is a function of switching patterns. The switching pattern of this modeling follows the modulation discussed Chapter 3. The initial values of the state space are extracted from the simulations. Four initial times are selected. The state space values at the specific time are extracted from simulation and substituted into (4.83) as initial state. The state space initial values are summarized in Table 5. Four initial times are selected to verify the state space derivation with the MATLAB/Simulink simulation. Table 5 Initial values of state space at four time instants. t1 = 10 ms t2 = 15 ms t3 = 20 ms t4 = 25 ms i1 (A) – 39.5 – 48.7 i2 (A) – 1.4 – 3.7 66.9 – 0.2 4.2 – 1.0 VC1 (V) 995.6 994.8 1007.9 999.9 VC2 (V) 1004.1 1005.2 993.3 999.7 A switching model is built in MATLAB/Simulink. The simulation circuit is shown in Figure4.19. The key parameters of the system are summarized in Table 6. Ideal switches, inductors, and capacitors with no parasitic parameters as well as ideal voltage sources were used. Any controller delays are not included in the model. In the simulation setup, discrete- Tustin/Backward Euler (TBE) with a sample time of 0.1 μs is selected. The initial values of capacitor voltages are 1000V. The initial values of the inductor current are determined by MATLAB/Simulink. 118 Figure 4.19 Two-level single-phase MMC circuit for simulation study. The comparison results are shown in Figs. 4.20-4.23. The proposed state space model and the simulation results are matched at t1, t2, and t4, whereas a minor mismatch happens at t3. This mismatch at t3 accumulated along with time. This is caused by the dis/dt term in U. We treat dis/dt as an input since this term contains information from load instead of the information from MMC. We could have an even accurate state-space model by adding dis/dt as the fifth state variable. This accumulation error becomes notable in a long run. Figure4.24 shows the Simulink simulation along with the state-space model in two fundamental cycles. The accumulated error can be observed from this figure. Although there is minor mismatch between the simulation and the state-space model in this specific case study, the main features of the simulation curves are well captured by state-space model. This indicates that the mathematical derivation of the proposed model is correct. The dis/dt term contains the information of load. This term could vary from load to load. But this has nothing to do with the MMC parameters. It is better to regard the dis/dt as an input instead of a state variable when later on we move on to the stability analysis. Please 119 1/2Vdc1/2VdcVsvaC1C2i1 (x1)i2 (x2)isLlineRloadLarmLarmRstrayRstrayVC1 (x3)VC2 (x4) notice that stability analysis should have a general idea of how MMC respond to a specific load model and its load change. Table 6 Two-level MMC simulation key parameters. Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 10 kHz DC-Bus Voltage, Vdc 1000 V Load Resistance, Rload 6.2 Ω (100% p.u.) Line Inductance, Lline 1 mH (6% p.u.) Arm Inductance, Larm 0.1 µH (0.0006% p.u.) Stray Resistance, Rstray 0.1 Ω (1.6% p.u.) Submodule Capacitance, Ci 85 µF (20% p.u.) Number of Submodules per Arm 1 where i = 1, 2. 120 Figure 4.20 Upper arm current (x1) simulation and state-space model comparison. 121 0.010.0150.020.025Time (s)-10001000.01010.01020.01030.0104-5000.01510.01520.01530.0154-5000.02010.02020.02030.02040500.02510.02520.02530.0254020Upper Arm Current (A)t1t1t1t1Initialization timei1 (x1)t1SimulinkState-Space Modeli1 (x1)t2SimulinkState-Space Modeli1 (x1)t3SimulinkState-Space Modeli1 (x1)t4SimulinkState-Space Modeli1 (x1)Time (s)Simulink Figure 4.21 Lower arm current (x2) simulation and state-space model comparison. 122 0.010.0150.020.025Time (s)-10001000.01010.01020.01030.01040500.01510.01520.01530.01540500.02010.02020.02030.0204-5000.02510.02520.02530.0254010i2 (x2)t1t2t3t4Initialization timet1SimulinkState-Space Modeli2 (x2)t2i2 (x2)SimulinkState-Space Modelt3SimulinkState-Space Modeli2 (x2)t4SimulinkState-Space Modeli2 (x2)Time (s)Lower Arm Current (A)Simulink Figure 4.22 Capacitor voltage (x3) simulation and state-space model comparison. 123 0.010.0150.020.025Time (s)980100010200.01010.01020.01030.01049959960.01510.01520.01530.01549959960.02010.02020.02030.0204100810090.02510.02520.02530.02549991000VC1 (x3)Capacitor Voltage (V)t1t2t3t4Initialization timeSimulinkt1SimulinkState-Space ModelVC1 (x3)t2SimulinkState-Space ModelVC1 (x3)t3SimulinkState-Space ModelVC1 (x3)t4SimulinkState-Space ModelVC1 (x3)Time (s) Figure 4.23 Capacitor voltage (x4) simulation and state-space model comparison. 124 0.010.0150.020.025Time (s)980100010200.01010.01020.01030.0104100410050.01510.01520.01530.0154100410050.02010.02020.02030.02049929930.02510.02520.02530.02549991000Capacitor Voltage (V)t1t2t3t4SimulinkVC2 (x4)Initialization timet1SimulinkState-Space ModelVC2 (x4)t2SimulinkState-Space ModelVC2 (x4)t3SimulinkState-Space ModelVC2 (x4)t4SimulinkState-Space ModelVC2 (x4)Time (s) (a) (b) (c) (d) Figure 4.24 Comparison of simulation and state-space model in a long run. (a) upper arm current; (b) lower arm current; (c) capacitor voltage VC1; (d) capacitor voltage VC2. 125 0.0050.010.0150.020.0250.03-5000500SimulinkState-Space Model0State variables are initialized at t = 0.Time t (s)Upper Arm Current (A)i1 (x1)0.0050.010.0150.020.0250.03-50005000Lower Arm Current (A)i2 (x2)Time t (s)SimulinkState-Space ModelState variables are initialized at t = 0.0.0050.010.0150.020.0250.039901000101010200Capacitor Voltage (V)VC1 (x3)Time t (s)SimulinkState-Space ModelState variables are initialized at t = 0.0.0050.010.0150.020.0250.03980100010200Capacitor Voltage (V)VC2 (x4)Time t (s)SimulinkState-Space ModelState variables are initialized at t = 0. 4.6.4 STATE-SPACE MODEL WITH LOAD AS STATE VARIABLE This section includes the derivation of the state space when considering the load as a state variable. We can see how complicated the state space could be. The pole voltage va of a two-level MMC can either be 1/2Vdc or -1/2Vdc as shown in Figure4.25. To calculate the arm inductor voltage, we need to find the state equation of MMC. Figure4.26 shows the simplified MMC model. Figure4.26(a) can be formulated as . (4.84) 126 112222212112222201/2LLCsdcLRRLCsLaadcdcLRLassssdiVLdtdiVLdtdViCdtiiiVVVVVVdiVLdtVVVVVVVikRkkk====+=++++==−−−++= (a) (b) Figure 4.25 Two-level MMC with pole connected to (a) positive dc rail (Level 1); and (b) negative dc rail (Level 2). (a) (b) Figure 4.26 Two-level MMC model with pole connected to (a) positive dc rail; and (b) negative dc rail. The corresponding switching pattern is . (4.85) Define the state variables to be 127 Vdc1/2Vdc1/2VdcVsVdcvaC1C2VL1VR1VR2VL2i1i2isVdc1/2Vdc1/2VdcVsVdcvaC1C2VL1VR1VR2VL2i1isi21/2Vdc1/2VdcVC2C2isVL1VR2i1i2isLRRVR1VL2L1/2Vdc1/2VdcisVR1i1i2isRVC1C1VL1LVR2RVL2L()2101=Γ , . (4.86) Rewrite (4.84) into state equation form, 128 112231425CCsxixixVxVix==X121213425CCsdidtdixdtxdVxdtxdVxdtdidt==X11222241211224522501/2LLsdcLRRLLaadcLRLasssVLxVLxxCxiiiVVVVVxVLxVVVVVVxR====+=++++==−−−++=2241211224225501/2sdcdcasxCxiiiVLxRxRxLxxVLxRxLxRx==+=++++=−−−++()224125251224225501/2dcdcasxCxxxxVLxxRxRxLxxVLxRxLxRx==+=+++++=−−−++ 129 ()2241252512425525124522222222dcdcasdcasxCxxxxVLxLxRxRxxVLxLxRxRxVLLxRxRxxRx==+=++++=−++−=++−++()()()()()224125251242552512452222221222222dcdcassdcaaaaaxCxxxxVLxLxRxRxxVLxLxRxRxRRRxxxxxVLLLLLLLLLL==+=++++=−++−−−−=+++++++++()()()()()22412525124251245124521112222221222222dcdcsdcaaaaaxCxxxxVLxLxRxRxxRRxxxxxVLLLLRRRxxxxxVLLLLLLLLLL==+=++++−−−−=++++−−−=+++++++++ 130 ()()()()()()()()()()2241252512421245512452222222221222222dcaaasadcaaaaasdcaaaaaxCxxxxVLxLxRxRxxRLRLLRLLxxxxxVLLLLLLLLLLLLLLRRRxxxxxVLLLLLLLLLL==+=++++−−−−+=+++++++++−−−=+++++++++()()()()()()()()()()()()()()()22411245212455124322222222222222212222aaasadcaaaaaaaasadcaaaaasaaaxCxRLLRLLLLRLLxxxxxVLLLLLLLLLLLLLLRLRLLRLLxxxxxVLLLLLLLLLLLLLLRRRxxxxLLLLLLL=−+−+−−−+=+++++++++−−−−+=+++++++++−−−=+++++++()()522dcaaxVLLL++ (4.87) 131 ()()()()()()()()()()()()()()()11245212454225124322222222222222121222aaasadcaaaaaaaasadcaaaaasaaaRLLRLLLLRLLxxxxxVLLLLLLLLLLLLLLRLRLLRLLxxxxxVLLLLLLLLLLLLLLxxCRRRxxxxLLLLLLL−+−+−−−+=+++++++++−−−−+=+++++++++=−−−=+++++++()()5222dcaaxVLLL++ Where Rs is the load resistance, and La is the load inductance. Figure4.26(b) can be formulated as 132 112211112112212201/2LLCsdcLRRLCsLaadcLRLassssdiVLdtdiVLdtdViCdtiiiVVVVVVdiVLdtVVVVVVikRkkk====+=++++==−−++=112211312511223522501/2LLdcLRRLLaadcLRLasssVLxVLxxCxxxxVVVVVxVLxVVVVVVxR====+=++++==−−++=11312511223225501/2dcdcasxCxxxxVLxRxRxLxxVLxRxLxxR==+=++++=−−++ 133 ()11312511223225501/2dcdcasxCxxxxVLxRxRxLxxVLxRxLxxR==+=++++=−−++()11312525123225522222dcdcasxCxxxxVLxLxRxRxxVLxRxLxxR==+=++++=+−−()1131252512325255123522222022dcdcasasxCxxxxVLxLxRxRxxVLxLxRxxRLLxRxRxxxR==+=++++=−+−=−+−+−−()()()()1131252512325255123522222212222dcdcassaaaaxCxxxxVLxLxRxRxxVLxLxRxxRRRRxxxxxLLLLLLLL==+=++++=−+−−−−=+++++++ 134 ()()()()1131252512325255123522222212222dcdcassaaaaxCxxxxVLxLxRxRxxVLxLxRxxRRRRxxxxxLLLLLLLL==+=++++=−+−−−−=+++++++()()()()11312525123252551235111222222222212222dcdcassaaaaxCxxxxRRxxxxxVLLLLVLxLxRxxRRRRxxxxxLLLLLLLL==+−−−−=++++=−+−−−−=+++++++ (4.88) 135 ()()()()()()()()()()()()()()113112352123551235122222122222212222aaasdcaaaaaaasdcaaaasaaaaxCxRLLRLLLRxxxxxVLLLLLLLLLLLLRLLRLLRxxxxxVLLLLLLLLLLLLRRRxxxxxLLLLLLLL=−+−−−−=++++++++−+−−=++++++++−−−=+++++++()()()()()()()()()()()()()()1123521235311512351222221222221212222aaasdcaaaaaaasdcaaaasaaaaRLLRLLLRxxxxxVLLLLLLLLLLLLRLLRLLRxxxxxVLLLLLLLLLLLLxxCRRRxxxxxLLLLLLLL−+−−−−=++++++++−+−−=++++++++=−−−=+++++++ The corresponding switching pattern is . (4.89) Equation (4.87) and (4.88) has a complete representation of MMC and RL load together. However, they are hard to decompose as we did in previous sections. Analyzing the dynamics and stability of the system considering load model is worth doing. I would like to leave this for future work. We are going to derive the state-space model for three-level MMC in this section. Figure4.27 shows a single-phase three-level MMC that is under analysis. For a three-level MMC, there are six feasible switching patterns. The following section will model the three- level MMC for each switching pattern. 136 ()2210=Γ Figure 4.27 Three-level MMC with pole voltage of (a) Vdc (Level I); (b)(c)(d)(e) zero volt (Level II); and (f) –Vdc (Level III). 137 VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4VC2VdcVdcVsVC3vaC2C3isVL1VL2i1i2VC1C1VC4C4(a)(b)(c)(d)(e)(f) 4.7.1 STATE-SPACE MODEL Figure4.27(a) can be formulated as . (4.90) The corresponding switching pattern is . (4.91) Define the state variables to be , . (4.92) Rewrite (4.90) into state equation form, 138 1122323424121234LLCCsdcLLCCdiVLdtdiVLdtdViCdtdViCdtikkiiVVVVkVk=====+=+++()310011=Γ112231425364CCCCxixixVxVxVxV==X121213425364CCCCdidtdixdtxdVxdtxdVdtxdVxdtdVdt==X , (4.93) 139 1122235246121256LLsdcLLVLxVLxxCxxCxxxiVVVxx=====+=+++1562565236241112222111222211sdcsdcdiVxxxdtLLLdiVxxxdtLLLxxCxxC−−=+++−−−=+++== Or (4.94) 140 1123456212345631111111100222222111111002222221001100110sdcsdcdixxxxxxxVLLLLLdtdixxxxxxxVLLLLLdtxxC=++−+−+−+−++=++−+−+−+−+−=23456412345625123456361234564000000100000010000001000000110xxxxxxxxxxxxCxxxxxxxCxxxxxxxC++++++=++++++=++++++=++++++ Rewrite (4.94) into matrix form, . (4.95) 141 121342563411110022122111100222210000010000010000010000110010011LLLLLLLLxxCxxCxxCC−−−−−−−−=1234561122112200000000000dcsxLxVLxdixdtxx−+ The coefficient marked in red contains the information from switching patter Γ1 (3). The system matrices are , , . (4.96) The coefficient matrix could be decomposed as follows, 142 123400110011011110022221111002222100000100000100001000000011LLLLLLLLCCCC−−−−−−−−=A1122112200000000LL−=BdcsVdidt=U . (4.97) . (4.98) . (4.99) 143 123400110011011110022221111002222100000100000100001000000011LLLLLLLLCCCC−−−−−−−−=ALC=0AA0()311111222211112220011001100111212ˆ2−−−−=−−−−−==−LLLLLLLLLLLLAAΓ123400010111ˆ1010CCCCCCC==AAA . (4.100) . (4.101) diag operator returns a column vector of the main diagonal elements of the objective matrix. contains the parameters from arm inductance. and contain the parameters from submodule capacitance. contain the parameters from upper arm submodules. contains the parameters from lower arm submodules. The reason to decompose the state space in such form is to save the work for programming. It will be easy to extent to high level state space by decomposing the matrix into such form. Note that U contains . reflects the voltage across the load inductor. That is , (4.102) as modeled in Figure4.28. Figure 4.28 Load inductor voltage modeling. 144 ()()13120011ˆˆ'0110==CCCdiagdiagCAAΓ()()213400001'111==CCdiagdiagCCAAΓˆLAˆ'CA'CAˆ'CA'CAsdidtsdidtsaasdiLvVdt=−isVsvaLa If the pole is attached to the positive dc rail, as shown in Figure4.27(a), va = Vdc. Eq.(4.102) can be modified as Replace the in (4.96) by (4.103) . . (4.103) (4.104) The other five feasible state space models [Figure4.27(b)-(f)] are omitted since the derivations are similar. 4.7.2 STATE SPACE MODEL WITH STRAY RESISTANCE The stray resistance always exists in the real MMC installations or simulations. Figure4.29 shows single-phase MMC model with stray resistance R. Figure4.29 can be formulated as . (4.105) 145 1()sdcsadiVVdtL=−sdidt1()dcdcsaVVVL=−U11223234241211222LLCCsdcLRRLCdiVLdtdiVLdtdViCdtdViCdktiiiVVVVVVkkk=====+=++++ Figure 4.29 Three-level MMC with pole connected to positive dc rail (Level 1). The corresponding switching pattern is . (4.106) Define the state variables to be 146 VC2Vdc/2Vdc/2VsVC3vaC2C3isi1i2VC1C1VC4C4VL1VL2VR2VR1()310011=Γ , . (4.107) Rewrite (4.105) into state equation form, , (4.108) 147 112231425364CCCCxixixVxVxVxV==X121213425364CCCCdidtdixdtxdVxdtxdVdtxdVxdtdVdt==X112562125652362411122222211122222211sdcsdcdiVRRxxxxxLLdtLLLdiVRRxxxxxLLdtLLLxxCxxC−−=−−++++−−−=−−++++== or (4.109) 148 1123456212345611111122222222111122222001100211sdcRRdixxxxxxxVLLLLLLLdtRRxxxxxxxLLLLLL=−+−+−+−+−+−++=−+−+−+−+−+−31234561412345625123456361234564112210000001000000100000010000000011sdcdiVLdtxxxxxxxCxxxxxxxCxxxxxxxCxxxxxxxC+−=++++++=++++++=++++++=++++++ Rewrite (4.109) into matrix form, . (4.110) 149 12134256311111222222111122222000102100000100000100000001101RRLLLLLLRRLLLLLLxxCxxCxxC−−−−−−−−−−−−=12345640111221122000000010000dcsxLxVLxdixdtxxC−+ The coefficient marked in red contains the information from switching patter Γ1 (3). The system matrices are , , . (4.111) 150 123411112222221111222222100000100000100000001000000011001111RRLLLLLLRRLLLLLLCCCC−−−−−−−−−−−−=A1122112200000000LL−=BdcsVdidt=U The coefficient matrix could be decomposed as follows, . (4.112) . (4.113) . (4.114) 151 123411112222221111222222100000100000100000001000000011001111RRLLLLLLRRLLLLLLCCCC−−−−−−−−−−−−=ARLC=AAA0()311111222211112220011001100111212ˆ2−−−−=−−−−−==−LLLLLLLLLLLLAAΓ123400010111ˆ1010CCCCCCC==AAA . (4.115) . (4.116) diag operator returns a column vector of the main diagonal elements of the objective matrix. contains the parameters from arm inductance. and contain the parameters from submodule capacitance. contain the parameters from upper arm submodules. contains the parameters from lower arm submodules. The reason to decompose the state space in such form is to save the work for programming. It will be easy to extent to high level state space by decomposing the matrix into such form. Note that U contains . reflects the voltage across the load inductor. That is , (4.117) as modeled in Figure4.28. If the pole is attached to the positive dc rail, as shown in Figure4.29, va = 1/2Vdc. Eq.(4.117) can be modified as . (4.118) 152 ()()13120011ˆˆ'0110==CCCdiagdiagCAAΓ()()213400001'111==CCdiagdiagCCAAΓˆLAˆ'CA'CAˆ'CA'CAsdidtsdidtsaasdiLvVdt=−1()sdcsadiVVdtL=− Replace the in (4.111) by (4.118) . (4.119) The other five feasible state space models [Figure4.27(b)-(f)] are omitted since the derivations are similar. 4.7.3 MODEL ANALYSIS AND SIMULATION To prove the correctness of the proposed state-space model, the simulation of a three- level single phase MMC model in MATLAB/Simulink is conducted for comparison. To simulate the proposed model, the differential equations of the state-space model (4.110) are discretized as follows, , , (4.120) (4.121) (4.122) (4.123) , , A time-step of ∆T = 0.1 μs was used to make sure the approximation is accurate enough. The system matrix A is a function of switching patterns. The switching pattern of this modeling follows the modulation discussed in Chapter 3. The initial values of the state space are extracted from the simulations. Four initial times are selected. The state space values at the specific time are extracted from simulation and substituted into (4.123) as initial state. The state space initial values are summarized in Table 7. Four initial times are selected to verify the state space derivation with the MATLAB/Simulink simulation. 153 sdidt1()dcdcsaVVkVLkkkk=−UddtX=AX+BUddtdtX=AX+BU()()()()()1111kkkkTkT−−−−−XX=AX+BU()()()()()1111kkkTkTk−−−+−X=AX+BUX Table 7 Initial values of state space at four time instants. t1 = 10 ms t2 = 15 ms t3 = 20 ms t4 = 25 ms i1 (A) – 34.5 i2 (A) 5.6 60.6 16.9 70.7 2.2 0.7 – 0.7 VC1 (V) 984.8 983.3 1012.5 1009.5 VC2 (V) 1004.1 999.0 1018.7 1011.0 VC3 (V) 1012.3 1007.9 988.9 990.5 VC4 (V) 1017.8 1023.4 1003.7 994.0 A switching model is built in MATLAB/Simulink. The simulation circuit is shown in Figure4.30. The key parameters of the system are summarized in Table 8. Ideal switches, inductors, and capacitors with no parasitic parameters as well as ideal voltage sources were used. Any controller delays are not included in the model. In the simulation setup, discrete- Tustin/Backward Euler (TBE) with a sample time of 0.1 μs is selected. The initial values of capacitor voltages are 1000V. The initial values of the inductor current are determined by MATLAB/Simulink. 154 Figure 4.30 Three-level single-phase MMC circuit for simulation study. The comparison results are shown in Figs. 4.31-4.36. The proposed state space model and the simulation results are matched at t1, t2, and t4, whereas a minor mismatch happens at t3. This mismatch at t3 accumulated along with time. This is caused by the dis/dt term in U. We treat dis/dt as an input since this term contains information from load instead of the information from MMC. We could have a more accurate state-space model by adding dis/dt as the fifth state variable. This accumulation error becomes notable in a long run. Figure4.37 shows the Simulink simulation along with the state-space model in five fundamental cycles. The accumulated error can be observed from this figure. Figure4.38 shows the load current derived from the state space model (x1 – x2). The load current has a dc offset. This is because the state space model only catches the derivative of load current 155 VsvaC2C3isC1C4i1 (x1)i2 (x2)LarmRstrayRstrayLarmLlineRloadVC1 (x3)VC2 (x4)VC3 (x5)VC4 (x6)Vdc/2Vdc/2 (dis/dt). The dc component of load current is neglected. This is the major weakness of this model. Although there is minor mismatch between the simulation and the state-space model in this specific case study, the main features of the simulation curves are well captured by state-space model. This indicates that the mathematical derivation of the proposed model is correct. The dis/dt term contains the information of load. This term could vary from load to load. But this has nothing to do with the MMC parameters. It is better to regard the dis/dt as an input instead of a state variable when later on we move on to the stability analysis. Please notice that stability analysis should have a general idea of how MMC respond to a specific load model and its load change. Table 8 Three-level MMC simulation key parameters. Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 20 kHz DC-Bus Voltage, Vdc 2000 V Load Resistance, Rload 12.4 Ω (100% p.u.) Line Inductance, Lline 1 mH (3% p.u.) Arm Inductance, Larm 0.1 µH (0.0003% p.u.) Stray Resistance, Rstray 0.1 Ω (0.8% p.u.) Submodule Capacitance, Ci 85 µF (40% p.u.) Number of Submodules per 2 Arm where i = 1, 2, …, 4. 156 Figure 4.31 Upper arm current (x1) simulation and state-space model comparison. 157 0.010.0150.020.025Time (s)-10001000.010050.01010.010150.0102-10000.015050.01510.015150.0152-10000.020050.02010.020150.020201000.025050.02510.025150.0252-500Upper Arm Current (A)i1 (x1)t1t2t3t4SimulinkInitialization timeSimulinkState-Space Modelt1i1 (x1)t2SimulinkState-Space Modeli1 (x1)t3SimulinkState-Space Modeli1 (x1)t4SimulinkState-Space Modeli1 (x1)Time (s) Figure 4.32 Lower arm current (x2) simulation and state-space model comparison. 158 0.010.0150.020.025Time (s)-10001000.010050.01010.010150.010201000.015050.01510.015150.015201000.020050.02010.020150.0202-10000.025050.02510.025150.0252-500Lower Arm Current (A)Simulinki2 (x2)t1t3t4t2Initialization timet1i2 (x2)SimulinkState-Space Modelt2i2 (x2)SimulinkState-Space Modelt3SimulinkState-Space Modeli2 (x2)t4SimulinkState-Space Modeli2 (x2)Time (s) Figure 4.33 Capacitor voltage (x3) simulation and state-space model comparison. 159 0.010.0150.020.025Time (s)950100010500.010050.01010.010150.01029859900.015050.01510.015150.01529809900.020050.02010.020150.02020.025050.02510.025150.0252t1t2t3t4Capacitor Voltage (V)Initialization timeVC1 (x3)t1SimulinkState-Space ModelVC1 (x3)t2SimulinkState-Space ModelVC1 (x3)10131015t3SimulinkState-Space ModelVC1 (x3)10081003t4SimulinkState-Space ModelVC1 (x3)Time (s) Figure 4.34 Capacitor voltage (x4) simulation and state-space model comparison. 160 0.010.0150.020.025Time (s)950100010500.010050.01010.010150.01020.015050.01510.015150.0152100010100.020050.02010.020150.02021018.510190.025050.02510.025150.0252100510109951005Capacitor Voltage (V)t1t2t3t4Initialization timeSimulinkt1VC2 (x4)SimulinkState-Space Modelt2SimulinkState-Space ModelVC2 (x4)t3SimulinkState-Space ModelVC2 (x4)t4SimulinkState-Space ModelVC2 (x4)Time (s) Figure 4.35 Capacitor voltage (x5) simulation and state-space model comparison. 161 0.010.0150.020.025Time (s)950100010500.010050.01010.010150.0102101010150.015050.01510.015150.0152101010150.020050.02010.020150.02029900.025050.02510.025150.0252990995Capacitor Voltage (V)t2t3t4Simulinkt1SimulinkState-Space ModelVC3 (x5)t2SimulinkState-Space ModelVC3 (x5)985SimulinkState-Space ModelVC3 (x5)t3t4SimulinkState-Space ModelVC3 (x5)Time (s)t1Initialization timeVC3 (x5) Figure 4.36 Capacitor voltage (x6) simulation and state-space model comparison. 162 0.010.0150.020.025Time (s)950100010500.010050.01010.010150.0102101810200.015050.01510.015150.0152102210230.020050.02010.020150.0202100010050.025050.02510.025150.0252992994Capacitor Voltage (V)Initialization timeVC4 (x6)t1t2t3t4t1SimulinkState-Space ModelVC4 (x6)t3SimulinkState-Space ModelVC4 (x6)t3SimulinkState-Space ModelVC4 (x6)t4SimulinkState-Space ModelVC4 (x6)Time (s) (a) (b) (c) (d) Figure 4.37 Comparison of simulation and state-space model in a long run. (a) upper arm current; (b) lower arm current; (c) capacitor voltage VC1; (d) capacitor voltage VC2; (e) capacitor voltage VC3; (f) capacitor voltage VC4. 163 0.010.020.030.040.050.060.070.08-5000500Upper Arm Current (A)State variables are initialized at t = 0.SimulinkState-Space Modeli1 (x1)Time t (s)0.010.020.030.040.050.060.070.08-5000500Lower Arm Current (A)State variables are initialized at t = 0.SimulinkState-Space Modeli2 (x2)Time t (s)0.010.020.030.040.050.060.070.0895010001050Capacitor Voltage (V)State variables are initialized at t = 0.SimulinkState-Space ModelVC1 (x3)Time t (s)0.010.020.030.040.050.060.070.08980100010201040Capacitor Voltage (V)State variables are initialized at t = 0.SimulinkState-Space ModelVC2 (x4)Time t (s) Figure 4.37 (cont’d) (e) (f) Figure 4.38 Accumulated error on load current. We are going to derive the state-space model for N-level MMC in this section. Figure4.39 shows the single-phase N-level MMC under analysis. We have derived the state-space model for two-level and three-level MMC in previous sections. There are some common in their derivations. The law of derivations is summarized in this chapter. 164 0.010.020.030.040.050.060.070.0896098010001020Capacitor Voltage (V)State variables are initialized at t = 0.State-Space ModelSimulinkVC3 (x5)Time t (s)0.010.020.030.040.050.060.070.0895010001050Capacitor Voltage (V)State variables are initialized at t = 0.State-Space ModelSimulinkVC4 (x6)Time t (s)0.010.020.030.040.050.060.070.08-1000100Load Current (A)State variables are initialized at t = 0.State-Space ModelSimulinkisTime t (s) Figure 4.39 A single-phase N-level MMC. 4.8.1 STATE-SPACE MODEL Define the state variables to be 165 SM1SM2SMN-1SMNSM2N-3SM2N-2Vsisi1i2vaVC2C2(N-1)Vdc/2(N-1)Vdc/2RloadLarmRstrayRstrayLarmLline , . (4.124) The state equation are as follows, Where . (4.125) ym is an element of switching pattern; and 166 . (4.126) ()11221324222CCNCNixixVxVxVx−==X()12121342222CCNCNdidtdixdtxdVxdtxdVdtxdVdt−==XX=AX+BU12221222112221121112222211122222100000100000100000100000−−−−−−−−−−−−−−−−=NNNNNNNNRRLLLLLRRLLLLLCCCCA22NN , (4.127) . (4.128) The coefficient matrix could be decomposed as follows, . (4.129) 167 2211221122000000NLL−=BdcsVdidt=U12221222112221121112222211122222100000100000100000100000−−−−−−−−−−−−−−−−=NNNNNNNNRRLLLLLRRLLLLLCCCCA22=NNRLCAAA0 . (4.130) . (4.131) . (4.132) . (4.133) 168 ()12221222122211122211122212ˆ12−−−−−−=−−−−==−LNNLyNNLLLLLLLLAAΓ111221221010ˆ1010−−−−==NCCCNNNNNCCCCAAA()()()21212221111ˆˆ'00−−−==NyNNCCNCdiagdiagCAAY()()()212222122001'1−−−==NNCCyNNNdiagdiagCCAAΓ diag operator returns a column vector of the main diagonal elements of the objective matrix. contains the parameters from arm inductance. and contain the parameters from submodule capacitance. contain the parameters from upper arm submodules. contains the parameters from lower arm submodules. The reason to decompose the state space in such form is to save the work for programming. It will be easy to extent to high level state space by decomposing the matrix into such form. Note that U contains . reflects the voltage across the load inductor. That is , (4.134) as modeled in Figure4.40. Figure 4.40 Load inductor voltage modeling. If the pole is attached to the positive dc rail, va = (N – 1)Vdc/2. Eq.(4.124) can be modified as . (4.135) For other switching patterns, va is determined by the number of the submodule at inserted mode in upper arm. Replace the in (4.128) by (4.134) . (4.136) 169 ˆLAˆ'CA'CAˆ'CA'CAsdidtsdidtsaasdiLvVdt=−isVsvaLa()()11/2sdcsadiNVVdtL=−−sdidt1()dcasaVvVL=−U 4.8.2 MODEL ANALYSIS AND SIMULATION To simulate the proposed model, the differential equations of the state-space model (4.125) are discretized as follows, , , (4.137) (4.138) (4.139) (4.140) , , The system matrix A is a function of switching patterns. The switching pattern of this modeling follows the modulation discussed in [62]. 4.8.2.1 CASE STUDY: ΓMM BASED FOUR-LEVEL MMC To prove the correctness of the proposed state-space model, the simulation of a single- phase four-level MMC model in MATLAB/Simulink is conducted for comparison. This four-level MMC simulation follows the ΓMM strategy. The submatrices are as follows, (4.141) (4.142) (4.143) , , , 170 ddtX=AX+BUddtdtX=AX+BU()()()()()1111kkkkTkT−−−−−XX=AX+BU()()()()()1111kkkTkTk−−−+−X=AX+BUX()41000111=Γ()42010101010011ˆ001101100101010110=Γ()43110100110010ˆ101100110001011100=Γ . (4.144) Eq.(4.141)-(4.144) are all in full rank. The initial values of the state space are extracted from the simulations. Four initial times are selected. The state space values at the specific time are extracted from simulation and substituted into (4.140) as initial state. The state space initial values are summarized in Table 9. Four initial times are selected to verify the state space derivation with the MATLAB/Simulink simulation. Table 9 Initial values of state space at four time instants. t1 = 10 ms t2 = 15 ms t3 = 20 ms t4 = 25 ms i1 (A) – 3.4 – 14.8 i2 (A) 37.7 28.8 70.1 0.8 27.9 26.5 VC1 (V) 991.0 989.4 1016.7 994.2 VC2 (V) 986.3 985.6 1008.2 1010.6 VC3 (V) 1001.3 1005.0 1014.1 1008.4 VC4 (V) 1003.9 1001.8 995.5 988.9 VC5 (V) 1019.7 1020.9 1006.9 991.6 VC6 (V) 1019.1 1020.2 995.4 999.9 A simulation is built in MATLAB/Simulink. The simulation circuit is shown in Figure4.41. The key parameters of the system are summarized in Table 10. Ideal switches, inductors, and capacitors with no parasitic parameters as well as ideal voltage sources were used. Any controller delays are not included in the model. In the simulation setup, discrete- 171 ()44111000=Γ Tustin/Backward Euler (TBE) with a sample time of 0.167 μs is selected. The initial values of capacitor voltages are 1000V. The initial values of the inductor current are determined by MATLAB/Simulink. Figure 4.41 Four-level single-phase MMC circuit for simulation study. The comparison results are shown in Figs. 4.42-4.45. The proposed state space model and the simulation results are matched at all time slots. Figure4.46 shows the Simulink simulation along with the state-space model in five fundamental cycles. The proposed 172 Vdc/2Vdc/2VsvaC2C3isC1C4i1 (x1)i2 (x2)LarmRstrayRstrayLarmLlineRloadVC1 (x3)VC2 (x4)VC4 (x6)VC5 (x7)C2VC3 (x5)C4VC6 (x8) state-space model matches with simulation in a long run. Figure4.47 shows the load current derived from the state space model (x1 – x2). This indicates that the mathematical derivation of the proposed model is correct. The dis/dt term contains the information of load. This term could vary from load to load. But this has nothing to do with the MMC parameters. It is better to regard the dis/dt as an input instead of a state variable when later on we move on to the stability analysis. Please notice that stability analysis should have a general idea of how MMC respond to a specific load model and its load change. Table 10 Four-level MMC simulation key parameters. Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 30 kHz DC-Bus Voltage, Vdc 3000 V Load Resistance, Rload 18.6 Ω (100% p.u.) Line Inductance, Lline 1 mH (3% p.u.) Arm Inductance, Larm 0.1 µH (0.0002% p.u.) Stray Resistance, Rstray 0.1 Ω (0.5% p.u.) Submodule Capacitance, Ci 171 µF (1.2 p.u.) Number of Submodules per Arm 3 where i = 1, 2, …, 6. 173 Figure 4.42 Upper arm current (x1) simulation and state-space model comparison. 174 0.010.0150.020.025Time (s)-400-20002004000.010050.01010.01015-20000.015050.01510.01515-20000.020050.02010.0201502000.025050.02510.025150200Upper Arm Current (A)Simulinkt1t2t3t4SimulinkState-Space Modeli1 (x1)i1 (x1)Initialization timet1SimulinkState-Space Modeli1 (x1)t2SimulinkState-Space Modeli1 (x1)t3t4SimulinkState-Space Modeli1 (x1)Time (s) Figure 4.43 Lower arm current (x2) simulation and state-space model comparison. 175 0.010.0150.020.025Time (s)-400-20002004000.010050.01010.0101505000.015050.01510.0151505000.020050.02010.0201502000.025050.02510.025150200Lower Arm Current (A)Initialization timeSimulinki2 (x2)t1t2t3t4t1i2 (x2)SimulinkState-Space ModelSimulinkState-Space Modeli2 (x2)t2SimulinkState-Space Modeli2 (x2)t3t4SimulinkState-Space Modeli2 (x2)Time (s) Figure 4.44 Capacitor voltage (x5) simulation and state-space model comparison. 176 0.010.0150.020.025Time (s)800100012000.010050.01010.01015100510100.015050.01510.01515101010200.020050.02010.0201510141014.50.025050.02510.0251510061008Capacitor Voltage (V)t1t2t3t4Initialization timeVC3 (x5)SimulinkState-Space ModelVC3 (x5)t1t2SimulinkState-Space ModelVC3 (x5)t3SimulinkState-Space ModelVC3 (x5)t4SimulinkState-Space ModelVC3 (x5)Time (s) Figure 4.45 Capacitor voltage (x6) simulation and state-space model comparison. 177 0.010.0150.020.025Time (s)800100012000.010050.01010.01015100510100.015050.01510.01515100510100.020050.02010.0201599510000.025050.02510.02515990995t1t2t3t4SimulinkInitialization timeVC4 (x6)Capacitor Voltage (V)t1SimulinkState-Space ModelVC4 (x6)t2SimulinkState-Space ModelVC4 (x6)t3SimulinkState-Space ModelVC4 (x6)t4SimulinkState-Space ModelVC4 (x6)Time (s) (a) (b) (c) (d) Figure 4.46 Comparison of simulation and state-space model in a long run. (a) upper arm current; (b) lower arm current; (c) capacitor voltage VC3; (d) capacitor voltage VC4. 178 0.010.020.030.040.050.060.070.08-1000010002000i1 (x1)State variables are initialized at t = 0.SimulinkState-Space ModelTime t (s)Upper Arm Current (A)0.010.020.030.040.050.060.070.08-1000010002000i2 (x2)Time t (s)State variables are initialized at t = 0.SimulinkState-Space ModelLower Arm Current (A)0.010.020.030.040.050.060.070.0895010001050VC3 (x5)Time t (s)SimulinkState-Space ModelState variables are initialized at t = 0.Capacitor Voltage (V)0.010.020.030.040.050.060.070.0895010001050VC4 (x6)Time t (s)State variables are initialized at t = 0.State-Space ModelSimulinkCapacitor Voltage (V) Figure 4.47 Load current is = x1 – x2. 4.8.2.2 CASE STUDY: ΓMM BASED FOUR-LEVEL MMC WITH NON-FULL- RANK MATRIX To prove the proposed state-space model can effectively demonstrate the deviation of the non-full-rank Γ matrix, the simulation of a single-phase four-level MMC model in MATLAB/Simulink is conducted for comparison. This four-level MMC simulation follows the ΓMM strategy. The submatrices are as follows, , , , . (4.145) (4.146) (4.147) (4.148) Eq.(4.145)-(4.148) are non-full-rank. The rank of each matrix are as follows, , , , and . (4.149) 179 0.010.020.030.040.050.060.070.08-1000100isTime t (s)State-Space ModelSimulinkLoad Current (A)()41000111=Γ()42001101010011ˆ100110010101001011=Γ()43101100110010ˆ011001101010110100=Γ()44111000=Γ()411=rankΓ()42ˆ4=rankΓ()43ˆ4=rankΓ()441=rankΓ The rank of any two adjacent matrices are as follows, , , and . (4.150) The initial values of the state space are extracted from the simulations. Four initial times are selected. The state space values at the specific time are extracted from simulation and substituted into (4.140) as initial state. The state space initial values are summarized in Table 11. Four initial times are selected to verify the state space derivation with the MATLAB/Simulink simulation. Table 11 Initial values of state space at four time instants. t1 = 10 ms t2 = 15 ms t3 = 20 ms t4 = 25 ms i1 (A) – 9.8 – 19.7 i2 (A) 30.7 23.2 67.3 – 1.4 18.0 18.0 VC1 (V) 921.9 888.9 868.2 829.2 VC2 (V) 1028.6 1048.9 1075.4 1087.2 VC3 (V) 1032.9 1051.0 1075.7 1089.2 VC4 (V) 1042.6 1057.7 1069.8 1082.2 VC5 (V) 1046.7 1061.5 1071.1 1083.2 VC6 (V) 958.9 906.8 860.1 830.2 A simulation is built in MATLAB/Simulink. The simulation circuit is shown in Figure4.41. The key parameters of the system are the same as Chapter 4.8.2.1, which is summarized in Table 10. Ideal switches, inductors, and capacitors with no parasitic 180 ()()41425ˆ=rankΓΓ()()4243ˆ5ˆ=rankΓΓ()()4344ˆ5=rankΓΓ parameters as well as ideal voltage sources were used. Any controller delays are not included in the model. In the simulation setup, discrete-Tustin/Backward Euler (TBE) with a sample time of 0.167 μs is selected. The initial values of capacitor voltages are 1000V. The initial values of the inductor current are determined by MATLAB/Simulink. The comparison results are shown in Figs. 4.48-4.51. The proposed state-space model and the simulation results are matched at all time slots. Figure4.52 shows the Simulink simulation along with the state-space model in five fundamental cycles. The proposed state-space model matches with simulation in a long run. Figure4.53 shows the load current derived from the state variables (x1 – x2). This indicates that the mathematical derivation of the proposed model is correct. The dis/dt term contains the information of load. This term could vary from load to load. But this has nothing to do with the MMC parameters. It is better to regard the dis/dt as an input instead of a state variable when later on we move on to the stability analysis. Please notice that stability analysis should have a general idea of how MMC responds to a specific load model and its load change. 181 Figure 4.48 Upper arm current (x1) simulation and state-space model comparison. 182 0.010.0150.020.025Time (s)-400-20002004000.010050.01010.01015-20000.015050.01510.01515-20000.020050.02010.0201501000.025050.02510.02515-500Upper Arm Current (A)Simulinki1 (x1)t1t2t3t4Initialization timet1SimulinkState-Space Modeli1 (x1)t2SimulinkState-Space Modeli1 (x1)t3SimulinkState-Space Modeli1 (x1)SimulinkState-Space Modeli1 (x1)t4Time (s) Figure 4.49 Lower arm current (x2) simulation and state-space model comparison. 183 0.010.0150.020.025Time (s)-400-20002004000.010050.01010.0101505000.015050.01510.0151502000.020050.02010.0201502000.025050.02510.025150100Lower Arm Current (A)Initialization timei2 (x2)Simulinkt1t2t3t4i2 (x2)SimulinkState-Space Modelt1SimulinkState-Space Modeli2 (x2)t2SimulinkState-Space Modeli2 (x2)t3SimulinkState-Space Modeli2 (x2)t4Time (s) Figure 4.50 Capacitor voltage (x5) simulation and state-space model comparison. 184 0.010.0150.020.025Time (s)800100012000.010050.01010.01015103010350.015050.01510.01515105010550.020050.02010.0201510761076.50.025050.02510.0251510861088Capacitor Voltage (V)Initialization timeVC3 (x5)t1t2t3t4SimulinkState-Space ModelVC3 (x5)t1SimulinkState-Space ModelVC3 (x5)t2SimulinkState-Space ModelVC3 (x5)t3t4SimulinkState-Space ModelVC3 (x5)Time (s)Simulink Figure 4.51 Capacitor voltage (x6) simulation and state-space model comparison. 185 0.010.0150.020.025Time (s)800100012000.010050.01010.01015104410460.015050.01510.01515106010650.020050.02010.02015106810700.025050.02510.0251510821084Capacitor Voltage (V)Initialization timeVC4 (x6)Simulinkt1t2t3t4SimulinkState-Space Modelt1VC4 (x6)SimulinkState-Space ModelVC4 (x6)t3t3SimulinkState-Space ModelVC4 (x6)t4SimulinkState-Space ModelVC4 (x6)Time (s) (a) (b) (c) (d) Figure 4.52 Comparison of simulation and state-space model in a long run. (a) upper arm current; (b) lower arm current; (c) capacitor voltage VC3; (d) capacitor voltage VC4. 186 0.010.020.030.040.050.060.070.08-500005000Upper Arm Current (A)State variables are initialized at t = 0.i1 (x1)SimulinkState-Space ModelTime t (s)0.010.020.030.040.050.060.070.08-500005000Lower Arm Current (A)State variables are initialized at t = 0.i2 (x2)SimulinkState-Space ModelTime t (s)0.010.020.030.040.050.060.070.08800100012001400Capacitor Voltage (V)State variables are initialized at t = 0.VC3 (x5)SimulinkState-Space ModelTime t (s)0.010.020.030.040.050.060.070.08800100012001400Capacitor Voltage (V)State variables are initialized at t = 0.VC4 (x6)SimulinkState-Space ModelTime t (s) Figure 4.53 Load current is = x1 – x2. 4.8.2.3 CASE STUDY: ΓMM BASED ELEVEN-LEVEL MMC To prove that this model can be extended to higher level a simulation of a single-phase eleven-level MMC model in MATLAB/Simulink is conducted for comparison with the proposed state-space model. This eleven-level MMC simulation follows the ΓMM strategy. The submatrices extraction follows the case study in Chapter 3.4.4. The initial values of the state space are extracted from the simulations. Four initial times are selected. The state space values at the specific time are extracted from simulation and substituted into (4.140) as initial state. The state space initial values are summarized in Table 12. Four initial times are selected to verify the state space derivation with the MATLAB/Simulink simulation. 187 0.010.020.030.040.050.060.070.08-1000100Load Current (A)SimulinkState-Space ModelisTime t (s) Table 12 Initial values of state variables at four time instants. i1 (A) i2 (A) t1 = 25 ms t2 = 30 ms t3 = 35 ms t4 = 40 ms 76.1 77.5 – 18.8 127.3 180.1 50.8 84.3 137.5 VC1 (V) 1017.5 1001.7 1001.6 1015.3 VC2 (V) 1023.5 998.2 1010.2 1023.6 VC3 (V) 1020.0 997.7 1002.4 1020.3 VC4 (V) 1025.7 997.4 1000.8 1023.6 VC5 (V) 1012.5 995.9 995.8 1021.6 VC6 (V) 1013.2 996.8 996.0 1024.4 VC7 (V) 1019.0 998.8 999.2 1023.9 VC8 (V) 1029.4 1002.1 1003.1 1024.1 VC9 (V) 1040.1 1002.0 992.3 1039.7 VC10 (V) 1033.1 1005.0 994.3 1029.5 VC11 (V) 989.4 1012.2 1008.4 998.4 VC12 (V) 1000.0 1011.4 1018.5 1012.3 VC13 (V) 997.7 1009.4 1007.6 999.7 VC14 (V) 1001.4 1010.8 1003.0 990.9 VC15 (V) 995.8 1013.2 995.2 987.9 VC16 (V) 998.4 1014.0 996.4 990.7 VC17 (V) 971.4 1013.8 995.6 984.0 VC18 (V) 973.0 1013.0 1.0020 991.3 188 Table 12 (cont’d) VC19 (V) 968.1 1015.1 998.1 982.1 VC20 (V) 970.0 1017.8 1012.5 989.3 A simulation is built in MATLAB/Simulink. The simulation circuit is shown in Figure4.54. The key parameters of the system are summarized in Table 13. Ideal switches, inductors, and capacitors with no parasitic parameters as well as ideal voltage sources were used. Any controller delays are not included in the model. In the simulation setup, discrete- Tustin/Backward Euler (TBE) with a sample time of 0.167 μs is selected. The initial values of capacitor voltages are 1000V. The initial values of the inductor current are determined by MATLAB/Simulink. 189 Figure 4.54 Eleven-level single-phase MMC circuit for state-space model study. The comparison results are shown in Figs. 4.55-4.58. The proposed state space model and the simulation results are matched at all time slots. Figure4.59 shows the Simulink simulation along with the state-space model in four fundamental cycles. The proposed state-space model matches with simulation in a long run. Figure4.60 shows the load current derived from the state variables (x1 – x2). This indicates that the mathematical derivation of the proposed model is correct. The dis/dt term contains the information of load. This term could vary from load to load. But this has nothing to do with the MMC parameters. It is better to regard the dis/dt as an input instead of a state variable when later on we move 190 Vdc/2Vdc/2VsvaC3isC1i1 (x1)i2 (x2)LarmRstrayRstrayLarmLlineRloadVC1 (x3)VC11 (x13)C10VC10 (x12)C4VC20 (x22) on to the stability analysis. Please notice that stability analysis should have a general idea of how MMC respond to a specific load model and its load change. Table 13 Eleven-level MMC simulation key parameters. Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 60 kHz DC-Bus Voltage, Vdc Load Resistance, Rload 10 kV 62 Ω (100% p.u.) Line Inductance, Lline 1 mH (0.61% p.u.) Arm Inductance, Larm 0.1 µH (0.00006% p.u.) Stray Resistance, Rstray 0.2 Ω (0.32% p.u.) Submodule Capacitance, Ci 770 µF (18 p.u.) Number of Submodules per Arm 10 where i = 1, 2, …, 20. 191 Figure 4.55 Upper arm current (x1) simulation and state-space model comparison. 192 0.0250.030.0350.04Time (s)-50005000.025020.025040.025060.0250805000.030020.030040.030060.0300801000.035020.035040.035060.0350802000.040020.040040.040060.040080500t1t2t3t4Initialization timei1 (x1)Upper Arm Current (A)SimulinkState-Space Modeli1 (x1)t1t2SimulinkState-Space Modeli1 (x1)SimulinkState-Space Modeli1 (x1)t3t4SimulinkState-Space Modeli1 (x1)Time (s)Simulink Figure 4.56 Lower arm current (x2) simulation and state-space model comparison. 193 0.0250.030.0350.04Time (s)-50005000.025020.025040.025060.0250805000.030020.030040.030060.0300802000.035020.035040.035060.0350802000.040020.040040.040060.040080500Lower Arm Current (A)t1t2t3t4SimulinkInitialization timei2 (x2)t1i2 (x2)SimulinkState-Space Modeli2 (x2)SimulinkState-Space Modelt2i2 (x2)SimulinkState-Space Modelt3t4i2 (x2)SimulinkState-Space ModelTime (s) Figure 4.57 Capacitor voltage (x12) simulation and state-space model comparison. 194 0.0250.030.0350.04Time (s)800100012000.025020.025040.025060.02508103410350.030020.030040.030060.030081004.510050.035020.035040.035060.035089959960.040020.040040.040060.0400810291030Capacitor Voltage (V)t1t2t3t4Initialization timeVC10 (x12)SimulinkState-Space ModelVC10 (x12)t1SimulinkState-Space ModelVC10 (x12)t2SimulinkState-Space ModelVC10 (x12)t3t4SimulinkState-Space ModelVC10 (x12)Time (s)Simulink Figure 4.58 Capacitor voltage (x13) simulation and state-space model comparison. 195 0.0250.030.0350.04Time (s)800100012000.025020.025040.025060.025089909920.030020.030040.030060.030081012.510130.035020.035040.035060.03508100610080.040020.040040.040060.04008998999Capacitor Voltage (V)t1t2t3t4VC11 (x13)Initialization timeSimulinkt1SimulinkState-Space ModelVC11 (x13)SimulinkState-Space ModelVC11 (x13)t3SimulinkState-Space ModelVC11 (x13)t3SimulinkState-Space ModelVC11 (x13)t4Time (s) (a) (b) (c) (d) Figure 4.59 Comparison of simulation and state-space model in a long run. (a) Upper arm current; (b) lower arm current; (c) capacitor voltage VC10; (d) capacitor voltage VC11. 196 0.020.030.040.050.060.070.08-100001000State variables are initialized at t = 0.SimulinkState-Space Modeli1 (x1)Time t (s)Upper Arm Current (A)0.020.030.040.050.060.070.08-100001000State variables are initialized at t = 0.SimulinkState-Space Modeli2 (x2)Time t (s)Lower Arm Current (A)0.020.030.040.050.060.070.0895010001050State variables are initialized at t = 0.SimulinkState-Space ModelVC10 (x12)Time t (s)Capacitor Voltage (V)0.020.030.040.050.060.070.08980100010201040State variables are initialized at t = 0.SimulinkState-Space ModelVC11 (x13)Time t (s)Capacitor Voltage (V) Figure 4.60 Load current is = x1 – x2. This Chapter proposed a state-space model for MMC. With this state-space model, the MMC capacitor voltage convergence and divergence can be well captured. This state-space model can be used for stability analysis and understanding the mechanism of the self balance phenomenon in the future. The existing MMC modeling are developed on the basis of certain degree of assumptions and simplification. This makes them unsuitable for understanding the nature of this circuit from its physical basement. Compared to existing MMC modeling, the proposed state-space model well captured the MMC dynamics. Four- level MMC with both full-rank Γ and non-full-rank Γ are studied to demonstrate that this model could explain both convergence and divergence of the capacitor voltage. A generalized MMC model is derived, which can be applied to higher level. An eleven-level MMC case study is provided to verify the proposed model when extended to higher level. 197 0.020.030.040.050.060.070.08-1000100SimulinkState-Space ModelisTime t (s)Load Current (A) 5 THE ARM INDUCTORS VOLTAGE DROP ASSUMPTION The arm inductors are assumed to have zero voltage drop in the analysis of previous Chapters. This Chapter is going to address the critical value of inductor in terms of validating the assumption. In another word, this Chapter will address how large is this arm inductor to drive the system from convergence to divergence. This Chapter will start with the assumption of VL= 0. Then some simulations will be provided to verify the analysis. To calculate the arm inductor voltage, we need to find the state equation of MMC. Figure5.1 shows the simplified MMC model. For a two-level MMC, there are two states at steady state, either the upper sub-module inserted, or the lower sub-module inserted. The following section will model the two-level MMC for each state. 5.2.1 STATE I Figure5.1(a) can be formulated as . (5.1) Define the state variables to be 198 112222212122====+=++LLCsdcLLCdiVLdtdiVLdtdViCdtiiiVVkkkVV , . (5.2) (a) (b) Figure 5.1 Two-level MMC model with pole connected to (a) positive dc rail; and (b) negative dc rail. Rewrite (5.1) into state equation form, , (5.3) . (5.4) Notice that reflects the voltage across the phase inductor. That is 199 112232==CxixixVX112232==CdidtxdixdtxdVdtX1/2Vdc1/2VdcVC2C2isVL1VL2i1i2is1/2Vdc1/2VdcVC1C1isVL1i1i2isVL2LLLL13233221112221112221=−++=−+−=sdcsdcdixxVLLdtdixxkVLLdtxxC1122332111002221110022210000−−=+−dcskkkkkkkkkkkkLLxxVxxdiLLxxdtkkkkkkkkkkkkkCsdidt , (5.5) as modeled in Figure5.2. Figure 5.2 Phase inductor voltage modeling. If the pole is attached to the positive dc rail, as shown in Figure5.1(a), va = 1/2Vdc. Eq.(5.5) can be modified as . (5.6) Replace the in (5.4) by (5.6) . (5.7) The system matrices are , , and . (5.8) State equation (5.7) could be re-written as . (5.9) Apply the Laplace transform to (5.2), (5.8), and (5.9) 200 =−saasdiLvVdtisVsvaLa11()2=−sdcsadiVVdtLsdidt1122332111002221110011()222210000−=−+−−dcdcsakkkkkkkkkkkkkkkkLLxxVxxVVLLkCkkkkkkkkLxkkxkkk210021002100−=−kkkkkkkkkkkkkkkkLLCA1122112200=−kkkkkkkkkLLB11()2=−dcdcsaVVVLkkkkkUX=AX+BU , , (5.10) , (5.11) , , , , (5.12) (5.13) (5.14) (5.15) , (5.16) , (5.17) where . To solve for , where . 201 ()()=tsXX()()(0)=−tssXXx()()11()2==−dcdcsakVstsVLkkkkVsUU()(0)()()−ssssXx=AX+BUT(0)0=−sdcikVkkx()sX()()(0)()−sssIAX=x+BU()1()()(0)()−−sssX=IAx+BU()()(0)()ssX=Φx+BU()1−=−sΦIA222222222222222211(21)212021212202121−−++−++++CsssLCsLCsLCCsLCsLCskkkkkkkkLkkkkkkkkkkkkkLCskLCsLCkkΦ=1122011(0)()1122()2000.5220.522+−+−−−+=−−+−dcsdcsdcadcdcsadcdcssadcVLssiLVVVsLVVVsLsLVVVisLskVkkkkkkkkLxBU= Hence, Laplace inverse transform, . (5.18) 202 ()()()()()2222222222222222222124()(0)()2214422221−+−+−+−−=+−−+++sdcasdcsasdcasaadcasdcsadcaVVsLisLCVsLCVsLsLCLCVVsLissLsLCsLLCVsLLiLVLVLVsLsLCX=Φx+BU (5.19) , (5.20) , (5.21) 203 ()()122222222222()()2sin22cos2sin2220.522sin22cos2sin2222cos20.5−+−−−++=−+−−++dcassdcssaadcassadcsdcadcatstLCVLCttLiLCVLCLCVVtiLLtLCVLCttLiLCVLCLCLtLCVLVLVLVLX=X222222cos22sin222−−sasattLCVLLiLCLCLCLC()()2212SteadyStateTranksient0.52sin20.5()cos22−−=−−++dcsdcsssaatVVLCLCtVVtitiiLCLL()rk2222TansientSteadyState0.52sin2()cos02200−=−−+dcssatVVLCLCtikkkkkkkkkLCLkktik . (5.22) 204 ()()2222SteadyStateTransienkt2()0.5cossin0.522=−−+−−CdcssdcdcsaattLLLVtVViVVVLCLCLCL Eq. (5.20), (5.21), and (5.22) are the dynamic response of upper arm current, lower arm current, and C2 voltage, respectively, in State I. All these three functions can be divided by two components, the transient component and the steady-state components. 5.2.2 STATE II The dynamic response of State II is similar to State I. Therefore, the derivation is omitted. Figure5.1(b) can be formulated by . (5.23) Apply the Laplace transform and Laplace inverse transform to (5.23), yields 205 1122331111002221110022210000−−=+−dcskkkkkkLLxxVkxxdkiLLkxxdtkkkkkkkkkkkkCkkk (5.24) , (5.25) , (5.26) . (5.27) 206 ()()11111111111()()2sin4cos22sin22242sin4cos22sin2220.540.5−−−+−+=+−−+−−+dcassadcassdcssaasdcadcatstttLCVLiLCVLCLCLCLtttLCVLiLCVLCLCLCVVtiLLLLVLVLVLX=X111111cos2cos22sin2222++dcsasatttCVLCVLLiLCLCLCLC()rk1111TansientSteadyState0.52sin2()cos02200+=−+dcssatVVLCLCtikkkkkkkkkLCLkktik()()1121SteadyStateTransienkt0.52sin20.5()cos22++=−+−dcsdcsssaatVVLCLCtVVtitiiLCLL()()1111SteadyStateTransienkt2()0.5cossin0.522=+++−+CdcssdcdcsaattLLLVtVViVVVLCLCLCL Eq.(25), (26), and (27) are the dynamic response of upper arm current, lower arm current, and C1 voltage, respectively, in State II. All these three functions can be divided by two components, the transient component and the steady-state components. The transient component will be damped with a coefficient of e – t/τ, where τ = 2L/Req. L is the arm inductance and Req is the equivalent resistance of power loss. The transient component should be damped down to zero if resistance exists in circuit. In real MMC prototype, there always 2-4% power loss and this power dissipation can be modeled by resistance. In order to assume the inductor voltage to be zero, the transient needs to be much faster than the switching frequency. From (5.20)-(5.22) and (5.25)-(5.27), we can see that the oscillation frequency and the damping time constant of the transient are (5.28) (5.29) Where ω0 is the resonance frequency. L is the arm inductor and Ceq is the equivalent capacitance of the submodules. τ is the time constant. Req is the equivalent converter loss. Therefore, τ < Tsw is the condition that guarantees the assumption to hold true, where Tsw is the switching period. When L is small, e.g., zero, then the above condition will automatically hold true. and at each switching instant, charging balance occurs. However, the charging and discharging current would be inrush (or impulse) current that may be not good for devices and noises. Then in order to limit inrush charging/discharging current, we have to have a minimum 207 01=eqLC2/=eqLR inductance to make sure the inrush charging/discharging current below 3 times rated load current. In this chapter, several simulations with various arm inductances are examined to verify the analysis in Chapter 5.3 and 5.4. The simulation topology is shown in Figure5.3. Figure 5.3 Three-level MMC simulation topology. Parameters: The key parameters of the MMC are as follows: rated apparent power S = 100 kVA, output phase voltage Va = Vb = Vc = 643 V, output line current Ia = Ib = Ic = 52 A, rated output fundamental frequency f0 = 60 Hz, rated load resistance Rload = 12.4 Ω, rated dc-bus voltage Vdc = 2 kV, number of sub-modules per arm: N – 1 = 2, sub-module capacitance Ci = 85 µF (i = 1, 2, …, 12), line inductance Lline = 4 mH. The switching frequency is fsw = 5 kHz. The power loss is modeled by a stray resistor R = 0.4 Ω (3.6% p.u.). The arm inductance Larm varies case by case. 208 VdcVaiaidciuapidaowniubpidbowniucpidcownibicvcavbcvabVbVcLarmLlineVC2C2iC2VC3C3iC3VC6C6iC6VC7C7iC7VC10C10iC10VC11C11iC11RloadC1C5C9C4C8C12VC1VC5VC9VC4VC8VC12iC1iC5iC9iC4iC8iC12 5.4.1 τ / Tsw = 0.02 The time constant of the system is smaller than switching period in this case study. VL = 0 holds true in this case. The key parameters are summarized in Table 14. Table 14 Three-level MMC simulation key parameters. Apparent Power, S 100 kVA Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 5 kHz DC-Bus Voltage, Vdc 2000 V Phase Voltage, Va, Vb, Vc 643 V Line Current, Ia, Ib, Ic 52 A Load Resistance, Rload Line Inductance, Lline Arm Inductance, Larm 12.4 Ω 4 mH 0.8 µH Stray Resistance, R 0.4 Ω (3.2% p.u.) Sub-Module Capacitance, Ci 85 µF Number of Sub-Modules per Arm 2 Time Ratio τ / Tsw 0.02 Resonant Frequency, f0 27 kHz where i = 1, 2, …, 12. The capacitor voltage is well balanced and converging to the expected dc voltage (1000 V) in Figure5.6. The load voltage and current are shown in Figure5.4. The mid-point voltage is shown in Figure5.5. The sub-module capacitor voltage and current are shown in 209 Figure5.6 The arm inductor current is shown in Figure5.7. The arm inductor current is limited within 2 times the load current. Figure 5.4 Three-level MMC (a) load voltage and (b) load current. 210 Figure 5.5 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. 211 Figure 5.6 Sub-module capacitor (a)/(c) voltage; and (b)/(d) current. 212 Figure 5.7 (a) Line current and its corresponding (b) upper arm current, (c) lower arm 5.4.2 τ / Tsw = 0.25 current. The time constant of the system is smaller than switching period in this case study. VL = 0 holds true in this case. The key parameters are summarized in Table 15. 213 Table 15 Three-level MMC simulation key parameters. Apparent Power, S 100 kVA Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 5 kHz DC-Bus Voltage, Vdc 2000 V Phase Voltage, Va, Vb, Vc 643 V Line Current, Ia, Ib, Ic 52 A Load Resistance, Rload Line Inductance, Lline Arm Inductance, Larm 12.4 Ω 4 mH 10 µH Stray Resistance, R 0.4 Ω (3.2% p.u.) Sub-Module Capacitance, Ci 85 µF Number of Sub-Modules per Arm 2 Time Ratio τ / Tsw 0.25 Resonant Frequency, f0 7.7 kHz where i = 1, 2, …, 12. The capacitor voltage is well balanced and converging to the expected dc voltage (1000 V) in Figure5.10. The load voltage and current are shown in Figure5.8. The mid-point voltage is shown in Figure5.9. The sub-module capacitor voltage and current are shown in Figure5.10. The arm inductor current is shown in Figure5.11. The arm inductor current is limited within 2 times the load current. 214 Figure 5.8 Three-level MMC (a) load voltage and (b) load current. 215 Figure 5.9 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. 216 Figure 5.10 Sub-module capacitor (a)/(c) voltage; and (b)/(d) current. 217 Figure 5.11 (a) Line current and its corresponding (b) upper arm current, (c) lower arm 5.4.3 τ / Tsw = 1 current. The time constant of the system is equal to the switching period in this case study. VL = 0 does not hold true in this case. The key parameters are summarized in Table 16. 218 Table 16 Three-level MMC simulation key parameters. Apparent Power, S 100 kVA Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 5 kHz DC-Bus Voltage, Vdc 2000 V Phase Voltage, Va, Vb, Vc 643 V Line Current, Ia, Ib, Ic 52 A Load Resistance, Rload Line Inductance, Lline Arm Inductance, Larm 12.4 Ω 4 mH 40 µH Stray Resistance, R 0.4 Ω (3.2% p.u.) Sub-Module Capacitance, Ci 85 µF Number of Sub-Modules per Arm 2 Time Ratio τ / Tsw 1 Resonant Frequency, f0 3.8 kHz where i = 1, 2, …, 12. The capacitor voltage is well balanced and converging to the expected dc voltage (1000 V) in Figure5.14. However, the voltage ripple is around 40%. Normally, this voltage ripple is deemed to be abnormal operation. The load voltage and current are shown in Figure5.12. The load voltage and current are distorted since the high voltage ripple on capacitors. The mid-point voltage is shown in Figure5.13. The sub-module capacitor voltage and current 219 are shown in Figure5.14. The arm inductor current is shown in Figure5.15. The arm inductor current is limited within 2 times the load current. Figure 5.12 Three-level MMC (a) load voltage and (b) load current. 220 Figure 5.13 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. 221 Figure 5.14 Sub-module capacitor (a)/(c) voltage; and (b)/(d) current. 222 Figure 5.15 (a) Line current and its corresponding (b) upper arm current, (c) lower arm 5.4.4 τ / Tsw = 2 current. The time constant of the system is greater than switching period in this case study. VL = 0 does not hold true in this case. The key parameters are summarized in Table 17. 223 Table 17 Three-level MMC simulation key parameters. Apparent Power, S 100 kVA Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 5 kHz DC-Bus Voltage, Vdc 2000 V Phase Voltage, Va, Vb, Vc 643 V Line Current, Ia, Ib, Ic 52 A Load Resistance, Rload Line Inductance, Lline Arm Inductance, Larm 12.4 Ω 4 mH 80 µH Stray Resistance, R 0.4 Ω (3.2% p.u.) Sub-Module Capacitance, Ci 85 µF Number of Sub-Modules per Arm 2 Time Ratio τ / Tsw 2 Resonant Frequency, f0 2.7 kHz where i = 1, 2, …, 12. The capacitor voltage is well balanced and converging to the expected dc voltage (1000 V) in Figure5.18. However, the voltage ripple is around 40%. Normally, this voltage ripple is deemed to be abnormal operation. The load voltage and current are shown in Figure5.16. The load voltage and current are distorted since the high voltage ripple on capacitors. The mid-point voltage is shown in Figure5.17. The sub-module capacitor voltage and current 224 are shown in Figure5.18. The arm inductor current is shown in Figure5.19. The arm inductor current is limited within 1.5 times the load current. Figure 5.16 Three-level MMC (a) load voltage and (b) load current. 225 Figure 5.17 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. 226 Figure 5.18 Sub-module capacitor (a)/(c) voltage; and (b)/(d) current. 227 Figure 5.19 (a) Line current and its corresponding (b) upper arm current, (c) lower arm 5.4.5 τ / Tsw = 10 current. The time constant of the system is smaller than switching period in this case study. VL = 0 does not hold true in this case. The key parameters are summarized in Table 18. 228 Table 18 Three-level MMC simulation key parameters. Apparent Power, S 100 kVA Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 5 kHz DC-Bus Voltage, Vdc 2000 V Phase Voltage, Va, Vb, Vc 643 V Line Current, Ia, Ib, Ic 52 A Load Resistance, Rload Line Inductance, Lline 12.4 Ω 4 mH Arm Inductance, Larm 400 µH Stray Resistance, R 0.4 Ω (3.2% p.u.) Sub-Module Capacitance, Ci 85 µF Number of Sub-Modules per Arm 2 Time Ratio τ / Tsw 10 Resonant Frequency, f0 1.2 kHz where i = 1, 2, …, 12. The capacitor voltage is diverging from the nominal dc voltage (1000 V) in Figure5.22. Normally, this voltage ripple is deemed to be abnormal operation. The load voltage and current are shown in Figure5.20. The load voltage and current are distorted since the high voltage ripple on capacitors. The mid-point voltage is shown in Figure5.21. The sub- module capacitor voltage and current are shown in Figure5.22. The arm inductor current is shown in Figure5.23. 229 Figure 5.20 Three-level MMC (a) load voltage and (b) load current. 230 Figure 5.21 Three-level MMC mid-point voltage (a) vab; (b) vbc; and (c) vca. 231 Figure 5.22 Sub-module capacitor (a)/(c) voltage; and (b)/(d) current. 232 Figure 5.23 (a) Line current and its corresponding (b) upper arm current, (c) lower arm current. This Chapter theoretically analyzes the dynamic response of the MMC in switching cycles. To assume the voltage drop on inductor to be zero, transient should be faster than the switching period. In another word, τ < Tsw. Some simulations results are provided to verify the analysis. 233 6 CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK This dissertation presents a modular multilevel converter with self voltage balancing. This work has made the following contributions: ❖ This dissertation mathematically proves that MMC capacitor voltage is self- balanced by nature if considering certain submodule patterns. This implies that MMC could achieve the submodule capacitor voltage balancing without any monitoring or control. The mathematical proof starts from observing the two- and three-level MMCs. Mathematically, two- and three-level MMCs are proved to be self-balanced. Then, the similar observation is extended to N-level MMC. A computer-aid procedure is given to prove that N-level MMC, where N ≤ 533, is self balanced by nature. This dissertation conjectures that this observation can be extended to arbitrary-level of MMC. ❖ To utilize this merit of MMC, a novel modulation, namely Γ-Matrix Modulation (ΓMM), is proposed to transform the math analysis of Chapter 2 into modulation practice. With the proposed ΓMM, MMCs are secured self voltage balancing. Conventionally, either a complicated voltage balancing control, or extra components must be embedded to MMC to balance the capacitor voltage. Compared to conventional MMC capacitor voltage balancing strategies, ΓMM features extremely simple algorithms and good reachability to high-level MMCs while maintaining the original half-bridge submodule topology. To simplify the analysis, ΓMM is introduced to two-level and three-level MMCs as examples. Then, 234 the generalized ΓMM is derived, which is suitable for high-level MMCs. Several ΓMM based MMC case studies are provided for verification purposes. ❖ The general state-space model of MMC is proposed to understand the mechanisms of the self balance phenomena of MMC. The existing MMC modeling are developed on different degrees of assumptions and simplification. This makes them unsuitable for understanding the nature of this circuit from its physical basement. Compared to existing MMC modeling, the proposed state-space model well captured the MMC dynamics. With this state-space model, the MMC capacitor voltage convergence and divergence can be well observed. Four-level MMC with both full-rank Γ and non-full-rank Γ are studied to demonstrate that this model could explain both convergence and divergence of the capacitor voltage. In addition, a generalized MMC model is derived. The generalized model can be applied to higher level MMC. An eleven-level MMC case study is provided to verify the proposed model when extended to higher level. Although we have developed a general state-space model for MMC, MMC still remains a black box in terms of the understanding how this model interacts with the Γ matrix (see Figure5.1). We observed the self balance phenomenon and gave a reasonable math explanation in Chapter 2. Then, we proposed a modulation that could trigger this self balance phenomenon in Chapter 3. After that, we developed a general state-space model for MMC to catch the detailed dynamics in Chapter 4. After this dissertation, we have a lot of interesting works to do. We need to explain the trajectory of the convergence/divergence by using the model derived from Chapter 4. One 235 more step, we need to predict the trajectory without the aid of simulation. Once we could predict the trajectory, we could come up with a general guidance for this type of sensor- less operation to evaluate its stability. Figure 6.1 Recommendations for future work. 6.2.1 STATE-SPACE MODEL OF TWO-LEVEL MMC Take the two level MMC for example. We have known that there are two continuous state spaces for two-level MMC. The first state space is 236 MMCYVdcYVdc▪ Convergence/divergence mechanisms▪ Stability analysis▪ Observability/controllability▪ Limited measurements/state estimation▪ Γ-matrix searching▪ Inrush current reduction▪ Arm inductor design▪ Submodule capacitor design▪ Compact MMC▪ H-bridge cascaded multilevel converter▪ Flying capacitor▪ Three-phase MMC modeling▪ Circulating current reductionConventional power electronics topicsUnconventional power electronics topics . (6.1) The system matrices are The corresponding switching pattern is We denote by A1. State equation (6.1) could be re-written as 237 , (6.2) , (6.3) . . (6.4) (6.5) 112233144211002211112200221112200000001000101010dcsLLxxLVLLxxdiLxxdtCxxC−−−−−=+()()122111002211002210101000010001−−−−=LLLLCCΓA112211220000LL−=BdcsVdidt=U()2101=Γ()()21AΓ . This state space dynamics could be denoted by f1, . The other state space is (6.6) (6.7) . (6.8) The corresponding switching pattern is . (6.9) The system matrices are , , 238 1X=AX+BU()11f=X=XAX+BU112233144211002211112200221112200000001001010100dcsLLxxLVLLxxdiLxxdtCxxC−−−−−=+()2210=Γ()()122211002211002211010100010000−−−−=LLLLCCΓA112211220000LL−=B and . (6.10) We denote by A2. State equation (6.8) could be re-written as . (6.11) This state space dynamics could be denoted by f2, . (6.12) 6.2.2 MECHANISMS OF VOLTAGE CONVERGENCE OF TWO-LEVEL MMC 6.2.2.1 THE SENSE OF SMELL OF A STATE MACHINE Before we discuss the MMC behavior, we first introduce the concept of the sense of smell of a state machine. For example, a two-level MMC contains two continuous state spaces (f1, f2). The transition between A1 and A2 is governed by a state machine H. In another word, H determines the moment that MMC should jump out of current continuous state space, and which continuous state space MMC should jump into at that moment. Let i1 0, i2 0, and be the initial value of state variables. Suppose that and . The location (coordinates) of initial state variables is denoted by p0, (6.13) Similarly, location (coordinates) of balance point is denoted by p, (6.14) * denotes no specific definition of balance value for certain state variables. The displacement from p to p0 is denoted by d0, 239 dcsVdidt=U()()22AΓ2X=AX+BU()22f=X=XAX+BU01CV02CV01CdcVV02CdcVVT000001112CCpiiVV=TdcdcpVV= (6.15) Since we do not have specific balance value for i1 and i2, the first two entries in d0 are set to zero to simplify the analysis. Therefore, (6.16) Definition: Suppose the state machine H determines the continues dynamics fi to be applied at moment t0. H is said to have a good sense of smell if the inner product of d0 and fi is no greater than zero. In another word, (6.17) This definition is consistent with our intuitions. fi represents the dynamics of state variables. For example, suppose fi to be This means . (6.18) . (6.19) This indicates that VC1 has a trend to decrease. Suppose p0 to be Suppose the balance point p to be . . (6.20) (6.21) This indicates that VC1 (1001 V) is greater than the expected balance point voltage (1000 V). Therefore, (6.22) 240 T0000001212CdcCdcdppiiVVVV=−=−−−−T00001200CdcCdcdppVVVV=−=−−0,0idfT0010if=−11CdVdt=−T010011000p=T10001000p=T000010dpp=−= And (6.23) Although the initial value of VC1 is greater than the balance value, VC1 has a trend to decrease. We could expect VC1 to come closer to the balance point after a while. This indicates that H has chosen a good fi to kick in at the right moment. We can claim that H has a good sense of smell. Otherwise, H is said to have a bad sense of smell if the inner product of d0 and fi is greater than zero. In another word, (6.24) 6.2.2.2 UNDERSTAND TWO-LEVEL MMC BEHAVIORS We are going to test the sense of smell for the state machine H of a two-level MMC. The state machine H follows the law set up in Chapter 3, which is i. Determine the level of va; ii. Assign the level number to the level pointer at every switching cycle; iii. Find the Γ-matrix pointer which the level pointer points to; iv. Read the row (submodule pattern) which the Γ-matrix pointer points to; v. Generate the gating signal for each submodule according to the submodule pattern; vi. Reassign the Γ-matrix pointer to the next row and wait for the next call from level pointer. For the two-level MMC case, this state machine law can be interpreted as follows, 241 ()T0000,00101010iidfdf===−−0,0idf i. The state machine always choses the state space from the adjacent levels as the next state space; ii. The kick-off time of next state space is arbitrary within one switching cycle. We should also notice some properties of U. i. The first entry of U is Vdc, which is a constant; ii. The second entry of U is dis/dt = (va – Vs)/L. this entry is a bounded number since va, Vs and L are all bounded. We should always have these conditions in mind when we evaluate the state machine. A single-phase two-level MMC is studied to verify the state machine proposed in Chapter 3. A switching model is built in MATLAB/Simulink. The simulation circuit is shown in Figure6.2. The key parameters of the system are summarized in Table 19. Ideal switches, inductors, and capacitors with no parasitic parameters as well as ideal voltage sources were used. In the simulation setup, discrete-Tustin/Backward Euler (TBE) with a sample time of 0.1 μs is selected. The initial values of capacitor voltages are 1000V. The initial values of the inductor current are determined by MATLAB/Simulink. 242 Figure 6.2 Two-level single-phase MMC circuit for state machin study. Table 19 Two-level MMC simulation key parameters for state machine study. Fundamental Frequency, f0 60 Hz Switching Frequency, fsw 10 kHz DC-Bus Voltage, Vdc Load Resistance, Rload Line Inductance, Lline 1000 V 6.2 Ω 1 mH Arm Inductance, Larm 0.1 µH Stray Resistance, Rstray 0.1 Ω Submodule Capacitance, Ci 85 µF Number of Submodules per Arm 1 where i = 1, 2. We are going to calculate the < d0 , fi > along with time. 243 1/2Vdc1/2VdcVsvaC1C2i1 (x1)i2 (x2)isLlineRloadLarmLarmRstrayRstrayVC1 (x3)VC2 (x4) A time-step of ∆T = 0.1 μs was used to match with the simulation. The system matrix A is a function of switching patterns. The state machine decision (instantaneous switching patterns) and the input value (U) are extracted from simulation. Then < d0 , fi > is calculated accordingly. Figure6.3 shows the < d0 , fi > results from the state machine proposed in Chapter 3. Figure 6.3 The < d0 , fi > resulting from the state machine proposed in Chapter 3. If we zoom in to see the details of the state machine and the dynamics of capacitor voltage, we will find that H always has a good sense of smell. Figure6.4 gives an example to show that H makes eight decisions in five switching cycles. < d0 , fi > is always negative when H launches a new decision [see red arrow in Figure6.4 (c)]. We can conclude that the proposed H has a good sense of smell. 244 0.020.030.040.050.060.070.08-50510< d0, fi >× 106Time t (s) (a) (b) (c) Figure 6.4 (a) Upper arm capacitor voltage; (b) lower arm capacitor voltage; and (c) the sense of smell . 6.2.3 DISCUSSIONS ON HIGH LEVEL MMC I hope that the similar analysis could also be applied to higher level MMCs. We have introduced a concept of sense of smell in Chapter 6.2.2. This could be one index to evaluate a state machine. However, when we go to high level MMC, this index might not be strong enough to guarantee the stability of the system. We need to introduce other indices to help assess the state machine. 245 0.03340.03350.03360.03379991000Capacitor Voltage (V)Time t (s)VC1 (x3)0.03340.03350.03360.033799899910001001Capacitor Voltage (V)Time t (s)VC2 (x4)0.03340.03350.03360.0337-10-505× 104< d0, fi >Time t (s)Good sense of smell Once we have a tool to assess the state machine we propose, we can move on to minimize the inrush current on the arm inductor without losing stability. There might be a chance that we need to look for a proper algorithm that can searching in the pool of Γ matrix. I have come up with some interesting topics to work on after finishing the stability analysis. Just list a few here, ❖ The inrush current is large in this dissertation. It is possible to look for a better Γ matrix to reduce the inrush current. Due to the massive data in Γ matrix, we might need to rely on some algorithms to search for the optimized Γ matrix. ❖ Although there is no sensor in this dissertation, it is possible that we add some sensors to the system and increase the stability. So, checking the controllability and the observability is critical. It is also possible to use state estimation to help us stabilize the system. ❖ We have demonstrated that ΓMM based MMC could reduce the dc capacitance. Since the arm current waveform is totally different from convention MMC, the component design needs to be re-considered. There is a chance we can have a compact MMC by using ΓMM. ❖ The ΓMM philosophy can also be applied to other type of multilevel converters, for example H-bridge cascaded multilevel converter. But when it comes to H- bridge, the entries in Γ matrix is no longer just 1 and 0. It is going to be 1, 0, and – 1. It is promising to extend the ΓMM philosophy to other type of multilevel converter as well. 246 ❖ In this dissertation I only discussed about single-phase model. The circulating current is missed out from this model. We need to have three-phase model in order to evaluate the circulating current. I apologize that I have to stop here in this dissertation. This is definitely not the end of understanding the nature of MMC. Instead, I believe this is just a beginning. There are many mysterious phenomena hidden in MMC. There will be a day that MMC is no longer a black box. And we will have a thorough understanding of MMC nature at that time. Not now but some day in future. 247 APPENDICES 248 The conjectures provided in Chapter 2.4.3 summarized two angles to approach to this math problem. We are going to take second conjecture b as example to proof since second conjecture b contains the majority levels compared to the other three items. If second conjecture b is proved, the other three proofs are trivial. The item that under analysis are as follows, • If the rank of is m for an (N – 1)-level MMC, then the rank of is m + 2 for an N-level MMC, where 2 ≤ k ≤ N – 3 and ; This conjecture can be decomposed as follows, • Row independent: let be full rank, where , then is full rank, where . • Column independent: let and be row independent, then is column vector independent. The reason to decompose the original conjecture into two parts is that the rows of should linearly independent if is full rank since is (2N – 3)×(2N – 2). The columns of should be linearly independent if is full rank since is (4N – 6)×(2N – 2). 249 ()()T111ˆˆ−−+NNkkΓΓ()()T1ˆˆ+NNkkΓΓ()()()()()()11111ˆˆ1100−−−−−=NkNNkkaNkb0Γ1ΓTT()()()()()()11111ˆˆ1100−+−+−=NkNNkkaNkb0Γ1ΓTT()1ˆ−NkΓ()()1ˆ25−=−NkrankNΓ()ˆNkΓ()()ˆ23=−NkrankNΓ()ˆNkΓ()1ˆ+NkΓ()()T111ˆˆ−−+NNkkΓΓ()ˆNkΓ()ˆNkΓ()ˆNkΓ()()T111ˆˆ−−+NNkkΓΓ()()T111ˆˆ−−+NNkkΓΓ()()T111ˆˆ−−+NNkkΓΓ We are going to prove the above conjectures by contradiction. A classic proof by contradiction from mathematics is the proof that the square root of 2 is irrational[69]. If it were rational, it could be expressed as a fraction a/b in lowest terms, where a and b are integers, at least one of which is odd. But if a/b= √2, then a2 = 2b2. Therefore, a2 must be even. Because the square of an odd number is odd, that in turn implies that a is even. This means that b must be odd because a/b is in lowest terms. On the other hand, if a is even, then a2 is a multiple of 4. If a2 is a multiple of 4 and a2 = 2b2, then 2b2 is a multiple of 4, and therefore b2 is even, and so is b. So b is odd and even, a contradiction. Therefore, the initial assumption—that √2 can be expressed as a fraction— must be false. A.1 ROW INDEPENDENT Let , , (A.1) Where αi is row vector of , βi is row vector of , λ is a column vector. Let be full rank, where . If is non full rank, ∃ λ ∈ R(2N- 3) × 1 : – λiαi = λ1α1 + λ2α2 +… + λi – 1αi – 1 + λi + 1αi + 1 +… + λ2N – 3α2N – 3 ⇔ . Therefore 250 ()()()12232322ˆ−−−=NkNNNΓ()()()121252524ˆ−−−−=NkNNNΓ()1223231−−=NNλ()ˆNkΓ()1ˆ−NkΓ()1ˆ−NkΓ()()1ˆ25−=−NkrankNΓ()ˆNkΓ()Tˆ=NkλΓ0 Therefore, Therefore, . (A.2) (A.3) (A.4) (A.5) (A.6) 251 ()()()()()()()()()()()()()()()()()()()()()()1TT111112512512524T1123112411124ˆˆ1100ˆ1100−−−−−−−−−−−−−−−−−===NkNNkkaNkbNkNNNNNNkaNNkbN0Γ1λΓλTT0Γ1Tλ0T()()()()()()()()()()()()()()()()()()()()()()12512512524T112311241112411241112112225252423232ˆ1100−−−−−−−−−−−−−−−−−−−−−−−+++=++−=NkNNNNNNkaNNNkbNNNNNkkabNNNN0Γ1TλλTTT0()()()()112225252423232411110−−−−−−−−−−=++==+++NNNkNNNNNkabTT0λ()()111222522153−−−−−++++=NNNkbNT0()()()()()()()()()()()()()()2111112225252311222525125231122125253125211112112251−−−−−−−−−−−−−−−−−−−−−−+=+++++=++++++++++++++=+++=NkbNNkbNNkkNNNNNNNNNNbNbbNkTTTTT0 Note that is derived from by manipulating the left most “0” in first row of to “1”. Therefore, contains at least one entry to be one. Therefore, . Therefore, (A.7) (A.8) A contradiction appears since is full rank. is full rank⇔ . Therefore, the initial assumption—that is non full rank—must be false. then is linearly dependent to . is derived from by manipulating the left most “0” in first row of to “1”. The definition of does not guarantee that is linearly independent to . If the definition of guarantees that is linearly independent to , then a contradiction appears. Therefore, the initial assumption—that is non full rank—must be false. A.2 DISCUSSION We have two sets of conjectures from Chapter 2.4.3. They are equivalent to each other. We have presented the math analysis regarding the second conjecture. The overall logic of the second conjecture is proof by induction. In fact, it is unnecessary to prove the conjecture by induction. The logic of the first conjecture is direct proof. The matrices presented in Chapter 2 have a property, which is the matrices contains only ones and zeros. These matrices were the subject of intensive study during the late 1950s and early 1969s by H. J. Ryser, D. Ft. Fulkerson, R. M. Haber, and D. Gale, and many remarkable theorems were 252 ()()11−−NkbT()11ˆ−−NkΓ()11ˆ−−NkΓ()()11−−NkbT()()11−−NkbT021250−+++=N11222525−−++=+NN0()1ˆ−NkΓ()1ˆ−NkΓ11222525−−+++NN0()ˆNkΓ()()11−−NkbT()1ˆ−NkΓ()()11−−NkbT()11ˆ−−NkΓ()11ˆ−−NkΓ()()11−−NkbT()()11−−NkbT()1ˆ−NkΓ()()11−−NkbT()()11−−NkbT()1ˆ−NkΓ()ˆNkΓ proved [70]. The original Γ before submatrix extraction has a property that the row and column sum vectors are fixed. This special matrix is discussed in [70]. Many remarkable theorems were proved in [70]. 253 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % - It takes 30s to run this script on my laptop % if NN = 100; % - It takes 12 hours if NN = 433; % - It takes 36 hours if NN = 533. % Yunting 6-7-18 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% clc; clear all; % generate the Y matrix % initiate the Y(N-1) matrix with 3-level MMC YN_1 = [0 0 1 1; % first level 0 1 0 1; % second level 1 0 0 1; % second level 0 1 1 0; % second level 1 1 0 0]; % third level % initiate the maximum level NN you hope to check NN = 1000; % generate the Y matrix of N-level MMC for N = 1:NN % generate the kth level Yk matrix for k = 1:N if k == 1 Yk = [zeros(1, N-1) ones(1, N-1)]; % fist level else if k < N-1 % extract the kth level matrix from the (N-1)-level MMC Y matrix N_1 = N-1; % (N-1)-level MMC m = 1 + (k-2) * (2*N_1 - 3) + 1; % starting row n = m + (2*N_1 - 3) - 1; % ending row Yk = YN_1(m:n,:); % have a zero vector to the left zero = zeros(2*N_1 - 3, 1); Yk = [zero Yk]; % have a one vector to the right one = ones(2*N_1 - 3, 1); Yk = [Yk one]; % extract Y(k-1) if k-1 == 1 Yk_1 = YN_1(1,:); else 254 m = 1 + (k-3) * (2*N_1 - 3) + 1; % starting row Yk_1 = YN_1(m,:); end % generate T(k-1)a [a, b] = size(Yk_1); for i = 1:b if Yk_1(b-i+1) == 1 % search for the right most "1" Tk_1a = Yk_1; % convert the right most "1" to "0" Tk_1a(b-i+1) = 0; break end end % generate T(k-1)b for i = 1:b if Yk_1(i) == 0 % search for the left most "0" Tk_1b = Yk_1; % convert the right most "0" to "1" Tk_1b(i) = 1; break end end % finalize Yk Yk = [Yk; 1 Tk_1a 1; 0 Tk_1b 0]; else if k == N-1 % extract the (k-1)th level matrix from the (N-1)-level MMC Y matrix N_1 = N-1; % (N-1)- level MMC m = 1 + (k-3) * (2*N_1 - 3) + 1; % starting row n = m + (2*N_1 - 3) - 1; % ending row Yk_1 = YN_1(m:n,:); % have a zero vector to the right zero = zeros(2*N_1 - 3, 1); Yk = [Yk_1 zero]; % have a one vector to the left one = ones(2*N_1 - 3, 1); Yk = [one Yk]; % extract first row of Y(k-1) row_Yk_1 = Yk_1(1,:); % generate T(k-1)a 255 [a, b] = size(row_Yk_1); for i = 1:b % search for the right most "1" if row_Yk_1(b-i+1) == 1 Tk_1a = row_Yk_1; % convert the right most "1" to "0" Tk_1a(b-i+1) = 0; break end end % generate T(k-1)b for i = 1:b % search for the left most "0" if row_Yk_1(i) == 0 Tk_1b = row_Yk_1; % convert the right most "0" to "1" Tk_1b(i) = 1; break end end % finalize Yk Yk = [Yk; 1 Tk_1a 1; 0 Tk_1b 0]; else Yk = [ones(1, N-1) zeros(1, N-1)]; % fist level end end end if k == 1 YN = Yk; else YN = [YN; Yk]; end end % update Y(N-1). save YN to Y(N-1) YN_1 = YN; % check the rank of any two adjacent levels for k = 1:N-1 if k == 1 Y1 = YN(1,:); % extract the kth level Y1 Y2 = YN(2:2*N-2, :); % extract the next level Y2 else if k < N-1 % extract the kth level Y1 256 m = 1 + (k-2) * (2*N - 3) + 1; % starting row of Y1 n = m + (2*N - 3) - 1; % ending row of Y1 Y1 = YN(m:n,:); % extract the kth level Y1 % extract the kth level Y2 m2 = n + 1; % starting row of Y2 % ending n2 = m2 + (2*N - 3) - 1; row of Y2 Y2 = YN(m2:n2,:); else % extract the kth level Y1 m = 1 + (k-2) * (2*N - 3) + 1; % starting row of Y1 n = m + (2*N - 3) - 1; % ending row of Y1 % extract the kth level Y1 Y1 = YN(m:n,:); % extract the kth level Y2 Y2 = YN(n+1,:); end end Y12 = [Y1;Y2]; % check the rank of any two adjacent levels Y12rank = rank(Y12); if Y12rank ~= (2*N-2) formatSpec = 'The rank of %dth level and %dth level of a %d-level MMC is %d\n'; fprintf(formatSpec,k,k+1,N,Y12rank) break end end end formatSpec = 'All ranks checked!\n'; fprintf(formatSpec) 257 BIBLIOGRAPHY 258 BIBLIOGRAPHY [1] A. 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