VIRTUAL - IMPEDANCE CONTROL & COMPENSATION FOR GRID - CONNECTED INVERTER SYSTEMS By Allan R . Taylor Jr A D ISSERTATION Submitted to Michigan State University in partial fulfillment of the requirements for the degree of Electrical Engineering Doctor of Philosophy 201 9 ABSTRACT VIRTUAL - IMPEDANCE CONTROL & COMPENSATION FOR GRID - CONNECTED INVERTER SYSTEMS By Allan R. Taylor Jr Interface inductors are a commonly used coupling component for grid - connected DC/AC voltage - sourced power - electronics converters. T he y provide two main benefits: a voltage - sensing point for converter synchronization and , to gether with the grid impedance, t hey filter out the converter voltage - switching - harmonics from influencing the grid - currents . Despite the se benefits, the interface inductors add additional cost, weight, volume, and power loss es to the system. Furthermore , the measurement of the synchron ization voltage requires additional voltage sensors to be used, further increasing system cost and complexity. In recent years, m uch has been /or weight without compromising filtering performance, such as the use of different magnetic materials , planar windings, or higher converter - switching - frequencies. Also, voltage - sensor - less algorithms have been proposed, such as the Direct Power Control method (which is similar to the Direct Torque Control of induction m achines) . However, the reduction/elimination of these two items (inductors and sensors) are usually not considered together. Furthermore, many sensor - less control methods usually rely on knowledge of the source impedance, which may be difficult to estimate in grid - connected systems. To eliminate the voltage sensors , t he concept of virtual impedance can be employed to fabricate a synchronization point f or the converter within software . Since the virtualized synchronization - voltage is b ased on information from already - available AC current sensors, the external voltage sensors can be removed from the system. In addition to synchronization , additional virtu al impedance s or transfer functions can be fabricated to enhance the dynamic performance of the system , reduce computational complexity, and/or enhance the stability range . Lastly, if the AC source impedance alone is suitable to provide adequate harmonic f iltering of the current (e.g. in a motor/generator connection) and the synchronization point is virtualized , the physical interfacing inductance can be completely removed from the system. The main focus of this research work is to investigate the theory a nd implement ation of using virtual impedance s in DC/AC converter control system s. The self - synchronized inductor - less DC/AC converter system utilizing the concept of virtual - impedance is proposed . Also, a method of using only a virtual interfacing - resistance to alter the current control loop, eliminate cross - coupling terms, and reduce computational complexity is proposed. In addition, a method of virtual - impedance - compensating PLL algorithms with better transient response is proposed. Finally, t he m ain application considered for this proposed control method is grid - connected systems , but an alternate virtual - impedance - based method for high - speed sensor - less control of permanent magnet AC machines is also proposed. A 1 k VA three - phase two - level invert er prototype has been designed to experimental ly validate some of the proposed control strategies. A description of the experimental setup and experimental results are included within this report. iv T o my parents , Allan R Taylor and Blanca L Taylor . Thank you for your constant support throughout my life and my academic career. v ACKNOWLEDGEMENTS I would like to express my gratitude and thanks to my advisor, Dr. Fang Z. Peng for hi s guidance, his support , and for serving as my advisor , even after his departure from Michigan State University ( MSU ) . I would also like to thank Dr. Elias Strangas, Dr. Bingsen Wang, Dr. Guoming Zhu, and Dr. Tim Hogan for their support and for serving as part of my committee. I would like to extend special thanks to those at Kettering University (KU) who helped to make this research , as well as my Ph.D. career , possible. I would like to thank Dr. Jim MacDonald for his help enrolling me into the Faculty Doc toral Development Program at Kettering University. I would also like to thank Dr. Kevin Bai for his support and for the knowledge I gained from him during our years working in the Advanced Power Electronics Lab. I would also like to thank Dr. Mark Thompson , Dr. Karen Rogers , Dr. Dave Foster, Dr. Ken Kaiser, Dr. Ravi Warrier, Dr. Huseyin Hiziroglu, Dr. Doug Melton, Dr. Jim Gover, Dr. Mo Torfeh, a nd the rest of the KU ECE department faculty for their help, who have bec o me my colleagues over the past few years. I would also like to thank Jerry Kozlowski, Amy Owens, and the rest of the KU ECE staff for their ongoing support. Special words of thanks go to my colleagues within the MSU Power Electronics and Motor Drives Laboratory: Dr. Xiaorui Wang, Dr. Nomar Santini, Dr. Ujjwal Karki, Dr. Yaqub Mahnashi , Dr. Deepak Gunasekaran , and other lab members who have helped me over the years at MSU. I would also like to thank the MSU ECE and ERC department staff for their support. Finally, I owe thanks to: my father, A llan Taylor, my mother, Blanca Taylor, my brother, David Robles, and especially my wife, Wallee Keating, whose love, support , and encouragement helped make my graduate studies and the completion of this dissertation possible. vi TABLE OF CONTENTS List of Tables ................................ ................................ ................................ ............................ viii List of Figures ................................ ................................ ................................ ............................. ix Key to Abbreviations ................................ ................................ ................................ ............... xiii 1 Introductio n & Background Material ................................ ................................ .................... 1 1.1 Overview of Grid - Connected Inverters ................................ ................................ ............. 1 1.1.1 The Need for Synchronization ................................ ................................ .................. 3 1.1.2 The Need for Inductive Filtering ................................ ................................ .............. 4 1.2 Converter Synchronizatio n using a PLL ................................ ................................ ............ 6 1.3 Line - C urrent Regulation ................................ ................................ ................................ .. 12 1.4 Control - System Stability Analysis ................................ ................................ ................... 16 1.4.1 Coordinate System & Reference - Frame Modeling ................................ ................. 19 1.4.2 Circuit - Dynamics Modeling ................................ ................................ ................... 21 1.4.3 Phase - Locked Loop Modeling ................................ ................................ ................ 21 1.4.4 Current - Controller Modeling ................................ ................................ .................. 22 1.4.5 Overall Control System Model ................................ ................................ ............... 22 1.5 Issues with Conventional DC/AC Systems ................................ ................................ ...... 25 1.6 Research Scope and Contributions ................................ ................................ .................. 30 1.7 Report Organization ................................ ................................ ................................ ......... 3 1 2 Virtual - Interface - Impedance Synchronization Methods ................................ .................... 33 2.1 Virtual - Impedance Implementation & Limitations ................................ ......................... 33 2.2 Removal of the Interfacing Inducto r s & Voltage Sensors ................................ ............... 37 2.3 Virtual - Interface - Impedance System Stability Analysis ................................ ................. 44 2.3.1 Control - System Sampling - Delay Modeling ................................ ........................... 44 2.3.2 Virtual Interface - Impedance Modeling ................................ ................................ ... 47 2.3.3 PID - Current - Controller Modeling ................................ ................................ .......... 49 2.3.4 Linear System Model for Virtual Interface - Impedances ................................ ........ 50 2.3.5 Current - C ontroller T uning using Padé Approximant ................................ ............. 53 2.4 Current Control - Loop Simplification Using Virtual Resistance ................................ ..... 56 2.5 Computational Complexity Comparison of Control Methods ................................ ......... 62 2.6 Virtual - Resistance Simulat ion & Experimental Results ................................ .................. 66 2.7 Chapter 2 S ummary ................................ ................................ ................................ .......... 75 3 Applying Virtual Impedance at the Synchronization Point ................................ ................ 77 3.1 Imped ance - Compensated Phase - Locked Loops ................................ .............................. 77 3.2 Quasi - Static Stability Range of SRF - PL L for Weak Grids ................................ ............. 82 3.3 Impedance - Compensated System Stability Analysis ................................ ....................... 90 3.4 Enhancement of Stability using Impedance - Compensation ................................ ............ 95 3.5 Sensor - less PMAC Motor Terminal - Voltage Synchronization ................................ ....... 97 3.6 Chapter 3 S ummary ................................ ................................ ................................ ....... 101 vii 4 Conclusions a nd Future Work ................................ ................................ ............................. 103 4.1 C onclusions ................................ ................................ ................................ .................... 103 4.2 Future Work ................................ ................................ ................................ ................... 104 Appendices ................................ ................................ ................................ ................................ 107 Appendix A : MATLAB Simulink Simulation Mode ls ................................ ........................ 108 Appendix B : Details on 1 kW Experimental Prototype ................................ ....................... 114 Appendix C : List of Scholarly Works ................................ ................................ ................. 120 References ................................ ................................ ................................ ................................ . 123 viii LIST OF TABLES Table 2 . 1 : Assumed number of FPU clock - cycles required for basic mathematical operations. ................................ ................................ ................................ ............ 63 Table 2 . 2 : Number of FPU operations and clock - cycles required for common control - system tasks. ................................ ................................ ................................ ........ 63 Table 2 . 3 : Comparison of computational - load for three different dq - c ontrol systems. ........ 64 Table 2 . 4 : Virtual - resistance simulation electrical parameters. ................................ ............ 67 Table 2 . 5 : Virtual - resistance simulation control system parameters. ................................ ... 68 ix LIST OF FIGURES Figure 1 . 1 : Block diagram of a typical solar power grid - connected system wi th interface inductor. ................................ ................................ ................................ ................. 1 Figure 1 . 2 : Equivalent single - wire circuit model of a grid - connected power electronics system . ................................ ................................ ................................ ................... 2 Figure 1 . 3 : M agnitude vs. frequency responses: (a) Bode magnitude plot of grid current ; (b) s implified frequency spectrum of PWM voltage waveform. ........................... 4 Figure 1 . 4 : Bl ock diagram of the basic phase - locked loop structure. ................................ ...... 7 Figure 1 . 5 : Block diagram of the Synchronous Reference Frame PLL. ................................ .. 9 Figure 1 . 6 : Block diagram of the normalized SRF - PLL. ................................ ....................... 10 Figure 1 . 7 : Linearized model of the normalized SRF - PLL. ................................ ................... 11 Figure 1 . 8 : Classical dq - frame current controller with decoupling terms. ............................. 15 Figure 1 . 9 : Equivalent PI - control system diagram of the dq - cur rent controllers. .................. 15 Figure 1 . 10 : Illustration of rotating and stationary coordinate system reference - frames . ........ 19 Figure 1 . 11 : Three - phase nine - level cascaded multi - level inverter topology. ......................... 27 Figure 1 . 12 : Alternate equivalent circuit models: (a) capacitively filtered voltage sensing ................................ . 29 Figure 2 . 1 : Inve rter control algorithm augmented with virtual impedance calculation . ........ 34 Figure 2 . 2 : Bode magnitude plots of (a) a pure deri vative and (b) a unity - gain high - pass filter. ................................ ................................ ................................ ..................... 35 Figure 2 . 3 : Classical dq - frame current controller with inductive - decoupling terms highlighted. ................................ ................................ ................................ .......... 36 Figure 2 . 4 : Classica l inverter control block diagram with interfacing impedance. ................ 39 Figure 2 . 5 : Inductor - less inverter control block diagram utilizing virtual impedance. .......... 40 Figure 2 . 6 : Proposed i nductor - less AC voltage - sensor - less inverter control diagram u sing virtual interface - impedance. ................................ ................................ ................ 41 x Figure 2 . 7 : Capacitive line - line load configuration for voltage - sensor - less start - up synchroni zation. ................................ ................................ ................................ ... 42 Figure 2 . 8 : Block diagram of a single - phase nonlinear PLL which includes magnitude detection . ................................ ................................ ................................ .............. 43 Figure 2 . 9 : Illustration of input & output signal delays in a digital control system. .............. 44 Figure 2 . 10 : Location of PWM delay in a virtual - interface - impedance control system . ......... 46 Figure 2 . 11 : Equivalent dynamic system model of virtual - impedance control algorithm. ...... 54 Figure 2 . 12 : Equivalent dynamic system model of virtual - impedance control algorithm. ...... 55 Figure 2 . 13 : Padé - approximated dynamic system model of virtual - resistance control algorithm. ................................ ................................ ................................ ............. 58 Figure 2 . 14 : Simplified dq - frame current - controller without decoupling terms. ..................... 60 Figure 2 . 15 : Equivalent PID - control system of the dq - current controllers using virtual - resistance. ................................ ................................ ................................ ............. 60 Figure 2 . 16 : Simplified I - control system of the dq - current controllers using virtual - resistance. ................................ ................................ ................................ .............. 61 Figure 2 . 17 : MATLAB Simulink inductor - less voltage - sensor - less virtual - resistance simulation. ................................ ................................ ................................ ............ 66 Figure 2 . 18 : Top - level control diagram for virtual - resistance Simulink model. ...................... 68 Figure 2 . 19 : Simulink virtual - resistance simulation; 5 Hz frequency step change. ................. 69 Figure 2 . 20 : Simulink virtual - resistance simulation; 36 - degree phase step change. ............... 70 Figure 2 . 21 : Simulink virtual - resistance simulation; 10% voltage step change. ..................... 70 Figure 2 . 22 : Experimental test bench for the virtual - resistance control algorithm. ................. 71 Figure 2 . 23 : R esults for over - damped step - change in load current: (a) simulatio n, (b) experiment . ................................ ................................ ................................ ........... 72 Figure 2 . 24 : R esults for under - damped step - change in load current: (a) simulation, (b) experiment . ................................ ................................ ................................ ........... 73 Figure 2 . 25 : Comparison between full PWM - based simulation & simplified 2 nd - order transfer function when driven by: (a) a pure step - input, (b) a 1000 A/s ramped step - input. ................................ ................................ ................................ ............. 75 xi Figure 3 . 1 : Addition or subtraction of virtual voltages from: (a) the inverter voltage; (b) the voltage sensing point. ................................ ................................ ..................... 77 Figure 3 . 2 : Space - vector diagram of system voltage s and current (ignoring resistance) at: (a) light load; (b) load - increase transient scenario; and ( c ) heavy load. .............. 78 Figure 3 . 3 : Inverter control block diagram utilizing rotating - frame virtual impedance at the voltage - sensing point. ................................ ................................ .................... 79 Figure 3 . 4 : Inverter control block diagram utilizing stationary - frame virtual impedance at the voltage - sensing point. ................................ ................................ .................... 80 Figure 3 . 5 : Simulink simulation comparison of impedance compensation methods . ............ 81 Figure 3 . 6 : Nonlinear SRF - PLL control - system model showing the grid - impedance interaction. ................................ ................................ ................................ ........... 83 Figure 3 . 7 : Qu a si - static SRF - PLL control system including the grid - impedance interaction. ................................ ................................ ................................ ........... 85 Figure 3 . 8 : Quasi - s tability & power transfer capability for DC/AC converter vs. grid impedance with: (a) no reactive power generation; (b) sensing voltage magnitude regulation via reactive power . ................................ ............................ 88 Figure 3 . 9 : Quasi - stability vs. power transfer capability for weak - grid connection : (a) no compensation, (b) 0.5 pu resistive compensation . ................................ ............... 89 Figure 3 . 10 : Space - vector plot of voltages & currents in the IC - PLL algorithm in: (a) the xy - frame, (b) the dq - frame. ................................ ................................ .................. 94 Figure 3 . 11 : Small - signal stability vs. power transfer capability without impedance compensation. ................................ ................................ ................................ ...... 95 Figure 3 . 12 : Small - signal stability vs. power transfer capability with 25% impedance compensation. ................................ ................................ ................................ ...... 96 Figure 3 . 13 : Pr oposed sensor - less PMAC control block diagram utilizing virtual impedance compensations. ................................ ................................ .................. 97 Figure 3 . 14 : Mathematical progression of proposed sensor - less PMAC control, showing: (a) the original control system; (b) the impedance - compensated system for observing the back - EMF; (c) the resulting control system w ith virtual interfacing resistance. ................................ ................................ ........................ 100 Figure 4 . 1 : Low - voltage PMAC dynamometer test bench at Kettering University. ............ 106 xii Figure A . 1 : Top - level diagram of the MATLAB Simulink virtual - resistance simulation. .... 108 Figure A . 2 : MATLAB Simulink model for generating three - phase AC g rid voltages . ........ 109 Figure A . 3 : MATLAB Simulink mod el of PWM hardware with deadband insertion . ......... 109 Figure A . 4 : Top - level control system diagram of MATLAB Simulink virtual - resistance simulation . ................................ ................................ ................................ .......... 110 Figure A . 5 : MATLAB Simulink model of dq - controllers with decoupling terms . .............. 111 Figure A . 6 : MATLAB Simulink model of PID controller implemented with a high - pass filter . ................................ ................................ ................................ ................... 112 Figure A . 7 : MATLAB Simulink model of Phase - Locked Loop subsystem . ........................ 113 Figure B . 1 : PCB layout of a three - phase 1 kW 400 VDC inverter f or experiments . ............ 114 Figure B . 2 : . .............. 115 Figure B . 3 : Datasheet of the SCT3060AL SiC - MOSFET used in the inverter prototype . ... 116 Figure B . 4 : Electrical schematic showing MOSFET gate driver and gat e - drive amplifier circuit s . ................................ ................................ ................................ ............... 117 Figure B . 5 : L ayout of the DSP PCB. ................................ ................................ ................................ ................... 118 xiii KEY TO ABBREVIATIONS AC Alternating Current A2D Analog - to - Digital ADC Analog - to - Digital Converter APEL Advanced Power Electronics Lab ASIC Application - Specific Integrated Circuit CAN Controller - Area Network CMI Cascaded Multi - Level Inverter CSC Current - Sourced Converter DC Direct Current DSP Digital Signal Processor EEPROM Electronically - Erasable Programmable Read - Only Memory EV Electric Vehicle FPU Floating - Point Unit FLOP FLoating - point OPeration HEV Hybrid - Electric Vehicle HPF High - Pass Filter IC Integrated Circuit IC - PLL Impedance Compensated Phase Locked Loop KCL Kirchh KVL KU Kettering University LPF Low - Pass Filter xiv MCU Micro - Controller Unit MSU Michigan State University NPC Neutral - Point Clamped PCB Printed Circuit Board PEMDL Power Electronics & Motor Drives Lab PI Proportional - Integral PID Proportional - Integral - Derivative PR Proportional - Resonant PLL Phase - Locked Loop PV Photo - Voltaic PWM Pulse - Width Modulation RS - 232 Recommended Standard 232 SiC Silicon - Carbide SOGI Second - Order Generalized Integrator SRF - PLL Synchronous Reference Frame Phase - Locked Loop TI Texas Instruments USB Universal Serial Bus VS C Voltage - Sourced Conv erter 1 1. INTRODUCTIO N & BACKGROUND MATER IAL In this chapter, the basics of pulse - width - modulated (PWM) DC/AC power - electronics converter systems are reviewed and the need for converter synchronization and harmonic filtering are discussed. Af terwards, the typical synchronization methods u sing a phase - locked loop (PLL) and current control methods using rotating - frame proportional - integral (PI) controllers are reviewed. Next, the stability, as well as the main benefits and issues with the conven tional synchronization and harmonic - filtering methods using interface - inductors are summarized. The chapter concludes by introducing the key topic of this research, virtual impedance , as an alternate soluti on to converter synchronization and control . This technique can eliminate the need for external voltage sensors and enable inductor - less converter operat ion . In addition , the dynamic performance of a converter system can also be improved in some cases . 1.1. OVERVIEW OF GRID - CONNECTED INVERTERS In the case of grid - connected energy systems, such as solar pow er generation systems or hybrid - el ectric - vehicle (HEV) battery chargers, a DC - AC power electronics converter and an interface inductor are typically placed between the energy system and a step - up transformer connected to the utility grid . I n Figure 1 . 1 , a typical solar three - phase inverter system is outlined . The inverter in such a three - phase system is typi cally a six - switch two - level voltage - sourced converter (VSC) but can b e a multi - level design if high er phase - voltages and/or low er voltage - Figure 1 . 1 : Block diagram of a typical solar power grid - connected system wi th interface inductor. 2 harmonics are needed. The transformer is used to step - up the low - voltages of the converter and energy system (typically around ~400 V) to higher utility - level voltages (around ~10 kV or so ). The interfacing inductor s are placed between the converter and the transformer , primar ily to block the high - frequency voltage harmonics of the converter from reaching the grid or the voltage - sensing point . In addition to the interface inductance , the leakage flux of the transformer and grid also help s to filter the line currents. This leaka ge flux effectively acts as an additional inductance in a series - connection with the interface inductance. Both, a balanced three - phase and a single - phase DC/AC converter system can be modeled as an equivalent single - phase circuit with two AC voltage sources separated by an impedance ; this is shown in Figure 1 . 2 . The grid voltage, v G , is modeled as an independent voltage source. The inverter output voltage, v I , is modeled as a dependent voltage source; it is controlled to regulate the line current, i . T he interface and tran sformer/ grid resistances , denoted R I and R G , as well as the interface and t ransformer /grid inductances , denoted L I and L G , are placed in series between v G and v I . v I , can be written as following : ( 1 . 1 ) The mid - point voltage in Figure 1 . 2 , v S , is sensed by external AC voltage sensors , to be used within the control algorithm in a phase - locked loop . This is used for synchronization of the converter system , to be discussed later. The DC - side of the inverter will be ignored; it will be considered to be a constant DC voltage value and will not influence the AC - side control. Figure 1 . 2 : Equivalent single - wire circuit model of a grid - connected power electronics system . 3 1.1.1. THE NEED FOR SYNCHRO NIZATION The utility grid voltage is usually assumed to be sinusoidal it is typically ge nerated by the back - electro - motive force (EMF) of large rotating electrical machines driven by turbines . To enable a non - zero average power flow from the utility grid, we can deduce that the line currents must also be sinusoidal. We can argue this from exa mining the following average power expression ; assuming v G = V G m sin( v t + v ) and i = I m sin( i t + i ), the average power, P , can be expressed as the sum of two cosine terms (after applying a trig - substitution) as shown: ( 1 . 2 ) where v and i ; V G m and I m ; and v and i are the frequencies, peak magnitudes, and phase - shift angles, respectively, of the grid voltage and current, respectively. In the case that the two frequencies are equal, i.e., v = i = , the power expression simplifies to a non - zero value : ( 1 . 3 ) In the case that the frequencies are not equal, v i , the integration in the power expression above will equal zero and there will be no average power transfer from the grid. Relaxing the definition of the current waveform to be any periodic shape, we can argue based on the Fourier Series expansion of the current, i , that all other harmonics of current with frequencies not equal to the voltage frequency, v , will not produce any net average power . Therefore, the line current must also be sinusoidal with the same frequency as the grid . Combining this co nclusion with equation ( 1.1 ) , we can determine that the inverter voltage, v I , must also be sinusoidal for non - zero power flow. Therefore, the inverter output voltage must be synchronized to the grid frequency for prop er operation. 4 1.1.2. THE NEED FOR INDUCTIVE FILTERING From equation ( 1.1 ) , we can solve for the line - current in the Laplace domain , yielding the following first - order differential - equation result : ( 1 . 4 ) T he inductive impedances essentially function as a low - pass filter for the line - current s . The cut - off frequency , C , of the expression for the current above is given as the following: ( 1 . 5 ) Thus, any high - frequency components of the inverter voltage or grid voltage above C will be attenuated in the current. The Bode magnitude plot of the current is shown in Figure 1 . 3 (a ). The actual magnitude of the output current depends on the magnitudes of the applied voltages multiplied by the gain values given by the expression abo ve (as shown in the Bode plot). The sinusoidal output voltage is generated through the use of PWM. A partial frequency spectrum of a sine - PWM voltage waveform is shown below in Figure 1 . 3 ( b) . Assuming the fundamental grid frequency to be f g , the PWM voltage will contain a desired low - frequency component with frequency f g and magnitude V I m , as well as several undesired (a) (b) Figure 1 . 3 : M agnitude vs. frequency responses: (a) Bode magnitude plot of grid current ; (b) s implified frequency spectrum of PWM voltage waveform. 5 voltage harmonics at the switching frequency, f sw , at the side - band frequencies, ( f sw ± f g ), and at multiples of the switching and side - band frequencies (as well as other, smaller harmonics) . If the cut - off frequency of the current due to the impedances , C , is well below the converter switching frequency, f sw , then the hi gh - frequency components of the voltages will be mostly filtered from the current. However, the magnitude of these high - frequency harmonics will not be zero; some small ripples will remain. These high - frequency current ripples are undesired, since they do n ot contribute to any active power transfer (as explained previously). In addition, any large di / dt along the utility lines can cause electro - magnetic interference (EMI) issues with other devices connected to the grid. The relative amount of ripple currents as compared to the desired fundamental current is typically quantified by the Total Harmonic Distortion (THD) value ; one general definition of THD for current is given below , where each I k is a k th harmonic current : ( 1 . 6 ) A lower THD value is generally better; a THD value of zero indicates a purely sinusoidal signal. The inductance value of the interface inductor s is usually selected to limit the total h armonic distortion (THD) of the grid current to an acceptable level, usually below 5% THD or less [ 1 ] . As seen from equation ( 1.5 ) , a larger inductance value will lower the cut - off frequency, providing a better filtering of harmonics. Finally, one additional need for filtering the voltage harmonics using interfacing impe dances (in addition to eliminating potential EMI issues and zero - power - producing currents ) is to provide a clean voltage - sensing point for converter synchronization. Measurement of the grid voltage is traditionally used for synchronization and control of t he inverter output voltage, as mentioned previously. The voltage - sensing point, v S , is typically measured at the transformer low - voltage 6 (LV) side using galvanically - isolated voltage sensors . Ideally, the sensed voltage should be free of harmonics, contain ing only the fundamental AC voltage sinusoidal waveform. If the interfacing inductance is too small, it is possible that some of the high - frequency PWM voltage will appear at the sensing mid - point voltage , v S . If left unchecked, this can add extra high - fre quency noise into the inverter control system , possibly caus ing instability due to positive feedback through feed - forward - like path s within the control loop. 1.2. CONVERTER SYNCHRONIZATIO N USING A PLL The synchronization of the inverter voltage is typically done using a P hase - L ocked L oop (PLL) algorithm . Some non - PLL - based converter synchronization methods exist, such as a sel f - synchronized synchronverter [ 2 ] and the second - order - generalized - integrator (SOGI) algorithm [ 3 ] , but these will not be covered here. A PLL is essentially a feedback control sys tem which tries to produce an exact replica of a periodic input signal, or one of its harmonic s , excluding noise . They can be hardware - based or software - based, usually implemented within a D igital S ignal P rocessor (DSP). The input and output signals of a P LL are periodic (they can be analog or digital), where the output signal is phase - aligned with the input signal. The PLL typically consists of three main pieces [ 4 - 6 ] : Phase Detector: this is usually a mathematical expression which produces an error signal, , related to the phase difference between the input and output signals. In a digital PLL, the phase detector may be as simple as an XOR gate. In an analog PLL, it may be the multiplication of two signals or an other non - linear mathematical calculation. Filter / Controller: a typical PLL might have a low - pass filter and controller following the phase detector (note: some controller s ha ve a similar form to a low - pass filter). Th eir purpose 7 is to produce an estimate of the frequency, , of the input signal w hich drives the phase - error output signals to eventually match in phase. When the phase error (and its derivative) reaches zero, the frequency will stabilize and the PLL Oscillator: sometimes labeled as a VCO (voltage - controlled oscillator), this is where the , found earlier. The oscillator could be a digital clock circuit, or it could be an integrator and a trigonometric sin( · ) function. The output is usually fed back to the phase - detector block. The general block diagram of a PLL is shown below in Figure 1 . 4 , consisting of the three main components describe d above. pose in a DC/AC converter is to track the frequency , phase angle , and the magnitude of the AC grid voltage. These values are used within the control . In addition, the use of a PLL can help to reduce noise coming from the terminal voltage measurements, allowing clean feed - forward - like signals to be used within the control algorithm. The input to the PLL in this study will be the mid - point measurement voltage, v S , which may contain harmonics. However, the output of the PLL (ideally) will only contain the fundamental component of the measurement voltage. The PLL can also help make the c ontrol system more immune to disturbances in the grid, as the bandwidth of a PLL is generally quite narrow. Figure 1 . 4 : Bl ock diagram of the basic phase - locked loop structure. 8 One of the most commonly used PLL topologies is the synchronous reference frame (SRF) PLL [ 7 ] . It is more commonly used in three - phase converter systems but can be implemented in single - phase systems as well with minor adjustments [ 8 ] . The SRF - PLL obtains its name from its use of the Clarke and Park coordinate transformations, used to convert a sinusoidal (rotating) three - phase system into a stationary two - phase system by means of using a rotating reference frame (he nce the name). The Clarke and Park transforms , respectfully, are presented below : ( 1 . 7 ) ( 1 . 8 ) where v Sa , v Sb , and v Sc are the three - phase stationary - frame inputs, v and v are the two - phase stationary - frame signals, v is the mean value, and v Sd and v Sq are the rotating - frame outputs. The angle, , is the estimated angle of the rotating reference fr ame. N - here . Since the PLL operates in the rotating dq - frame, it is also sometimes referred to as the dq - PLL topology. A block diagram of the basic SRF - PLL is shown in Figure 1 . 5 on the next page . The Park transform effectively serves as the phase detector here (and could also be consi dered part of the oscillator). The error signal , , in this case (which we wish to drive to zero) is simply the q - axis value of the sensed voltage, v Sq . The controller sh own in the figure , used to drive the error signal to zero , is simply a Propor tional - I ntegral (PI) controller. However, other controllers, such as a Proportional - Integral - Derivative (PID) controller, can also be used. From the estimate d 9 frequency, , the oscillator - portion of the PLL generates the phase - angle estimate, , through an integ ration. The phase - angle estimate is then fed back to the Park transformation. The inputs to the PLL, the variables v Sa , v Sb , and v Sc in equation ( 1.7 ) , are the three - phase components of the sensed mid - point voltage, v S . Assuming the three - phase components are balanced, the - compo nents of the sensed mid - point voltage can be expressed as ( 1 . 9 ) where V Sm and S are the magnitude and phase angle of the sensed voltage, respectively . W e ignore the - term here , assuming it to be zero. Ideally, if the angle estimate of the PLL is correct, the Park transform outputs should produce the values v Sd = V Sm and v Sq = 0. We assume that the voltage will be aligned to the d - axis of the rotating coordinate system (as oppose d to the q - axis , as done in motor control theory). If we examine the Park transformation output terms more closely, we can see that the error signal (the v Sq - component) can be expressed as ( 1 . 10 ) which, after plugging in equation ( 1.9 ) and a bit of simplification , we can express v Sq as the sine of the angle - er ror, scaled by a constant: ( 1 . 11 ) Figure 1 . 5 : Block diagram of the Synchronous Reference Frame PLL. 10 If the angle - error is small, we can use the Taylor - series approximation of sin( x ) near x = 0 to linearly approximate the q - axis voltage as: ( 1 . 12 ) Thus, if the grid voltage (and measurement voltage) has a relatively c onstant magnitude, then the q - axis voltage is approximately equal to the angle error, multiplied by a constant . In a simple scenario, the voltage magnitude constant can be absorbed into the PI - controller coefficients, k and k . A more proper way to correct for the gain is to simply divide it out. Note that the voltage magnitude can be computed using the dq - frame components: ( 1 . 13 ) Thus, the normalized angle - error can be expressed as: ( 1 . 14 ) The overall normalized SRF - PLL block diagram is shown in Figure 1 . 6 below. To tune the PI - controller of the SRF - PLL, we must first linearize the model. The sine and cosine terms inside of the Park transformation make the system nonlinear we cannot directly apply feedback control theory to nonlinear systems. As described above in equation ( 1.14 ) , the angle error is approximately being applied to the inpu t of the PI - controller. Therefore, we can simplify the PLL feedback control diagram to remove the Park transform, hypotenuse calculation, inverse, and multiplication blocks and replace them with simply the angle - error. This Figure 1 . 6 : Block diagram of the normalized SRF - PLL. 11 is shown in Figure 1 . 7 below. With this linearized model, we can analyze the dynamics. The closed - loop transfer function of the linearized SRF - PLL algorithm is given as : ( 1 . 15 ) Examining the denominator of the transfer function, we can determine t hat the PLL will always be stab le so long as both coefficients are positive. If we compare the denominator to the standar d form of a second - order system , ( 1 . 16 ) and apply the basic theory of second - order systems, we can compute the settling time, T , of the PLL and from it, determine an expression for the k coefficient: ( 1 . 17 ) By examining the roots of the denominator polynomial, ( 1 . 18 ) we can also obtain an expression for the k coefficient to make the system critically damped , having little or no overshoot (ideally). By setting the expression under the radical equal to zero, we can solve for the k coefficient: ( 1 . 19 ) Note: because the transfer function contains a first - order numerator (a zero), some overshoot may still occur even when the system has been made critically damped. Typical values for the Figure 1 . 7 : Linearized model of the normalized SRF - PLL. 12 illi - seconds. Usually, the dynamics of the PLL are made to be much slower than other system dynamics (such as the current), so that the two systems may be analyzed independently of each other. While this PLL theory presented here proves to be a simple anal ysis, it is not the complete picture. It provides only an initial starting point for analyzing the T o obtain a more accurate understanding of the stability and dynamics, the effects of the current control loop and /or the circuit impedances must also be taken into account. 1.3. LINE - C URRENT REGULATION The control of the grid current in a three - phase DC/AC converter system is commonly done using proportional - integral (PI) controllers in each axis of the synchronous frame. The line - curre nts are usually measured using isolated analog Hall - effect sensors. The sampled line currents are converted to the synchronous frame using the Clarke and Park transformations, t ogether with the observed angle - output of the PLL. During normal operation, the output voltage of the inverter is controlled to be synchronous with the grid and its fundamental magnitude and phase are adjusted to be slightly different than that of the grid. This difference in voltage shows up across the interfacing impedance and drives a current through the system; this is how the controller is able to source or sink the desir ed active and/or reactive power . In addition to co ntrol , the sensing of the AC line current s is also for protection purposes. To eliminate the any effects of the transformer or grid impedances affecting the current, the sensed terminal voltage, v S , is usually passed through the converter in a feed - forward - like path. In this sense, the control algorithm is focused solely around the interfacing impedance. To show this mathematically, recall the simplified equivalent circuit diagram ( Figure 1 . 2 ) of the converter - grid system . Recall that t he same line current , i , flows through both impedances. Thus, 13 the PLL voltage , v S , will be influenced by not only the grid voltage and the commanded inverter voltage, but also the relativ e impedance values. Using the Superposition principle, we can express the PLL voltage in the phasor Laplace domain as : ( 1 . 20 ) where the quantities Z I = R I + j L I and Z G = R G + j G are the simplified interface and grid impedances, respectively. T he terminal voltage dynamics are governed by the voltage divider which is formed from the interface impedance and transformer impedance. By reworking equation ( 1.20 ) ( 1 . 21 ) The same results can also be obtained from applying KVL. From this, we can see that the three voltages , v I , v S , and v G , will be near ly equal at light loads , but will differ at heavy loading conditions. The fact that the two voltages, v I and v G , both influence the PLL input vol tage will play an important role in the stability of the converter control algorithm, as we will later see. Also, to ensure that KVL equation ( 1.21 ) voltage should be controlled to be equal to the following: ( 1 . 22 ) This equation shows that the inverter voltage is nothing more than the sum o f the sensed mid - point voltage and the voltage drop across the interfacing impedance. The converter output voltage does not depend upon the transformer/grid impedance or the gr id voltage in this case. Considering only the interfacing impedance, we can rewrite equation ( 1.22 ) in a space - vector notation and expand the impedan ce terms: ( 1 . 23 ) 14 the - subscripts denote the space vectors are in the stationary frame. Next , we can apply the space - vector form of the Park transformation , moving the inverter voltage s to the dq - frame : ( 1 . 24 ) Simplifying this will give a result similar to the classical r esult from motor control theory . Moving differential - terms from one re ference - frame to another results in extra terms due to the Product Rule of Calculus, (or in this case, the Frequency Shifting property of Laplace transforms might be more applicable): ( 1 . 25 ) T he above equation can be simplified and split in to rea l and imaginary parts, yielding ( 1 . 26 ) where = d / dt is the estimated grid - frequency. The main difference here from motor control - ( v Sd in this case) is assumed to be in the d - axis rather than the q - axis. At steady - state, the value of v Sq should be equal to zero. From this result, the classical synchronous - frame current cont rol scheme is derived. This is shown in Figure 1 . 8 on the next page . The dq - frame currents are decoupled from each other using a direct calculation of the cross - linke d voltages. The pseudo - feed - forward path for the sensed d - axis voltage is shown at the top of the figure this voltage is directly added t o the An equivalent pseudo - feed - forward voltage is also added to the q - axis output to help during transient events ( although the q - axis voltage should be zero at steady - state). We - forward signals since they technically are voltages fed back from 15 voltage - sensor measurements , but are not directly related to the currents in a stiff - grid condition . The only terms which are not compensated for are th e resistor and inductor voltage - drop terms. These are left to the PI - controller s to generate the appropriate error voltage s to cancel these remaining voltage - terms and determine the system dynamics . The e quivalent system as seen by the PI - controllers after decoupling i s nothing more than a series RL - load. Therefore, the equivalent control system block diagram for both axes will be as in Figure 1 . 9 . The closed - loop transfer function of the equivalent PI - control loop is given below : ( 1 . 27 ) Since both axes will be symmetric ( L d = L q ) , usually the same tuning parameters can be used for both PI - controllers. Examining the denominator of the transfer function, we can determine that Figure 1 . 8 : Classical dq - frame current controller with decoupling terms. Figure 1 . 9 : Equivalent PI - control system diagram of the dq - cur rent controllers. 16 the control system will always be stable so long as both PI - coefficients are positive (the interface impedance values should always be real and positive) . If we compare the denominator of the transfer function to the standard form of a second - order system , ( 1 . 28 ) and apply the basic dynamic results of second - order systems, we can compute the settling time, T st , c , of the dq - currents and from it, determine an expression for the k p , c coefficient: ( 1 . 29 ) By examining the roots of the denominator polynomial, ( 1 . 30 ) we can also obtain an expression for the k i , c coefficient to make the system critically damped (setting the radical expression equal to zero): ( 1 . 31 ) Note: because the transfer function contains a first - order numerator (a zero), some overshoot may still occur even when the system has been made critically damped. Typical values for the settling time of the dq - current control system are usually in the sin gle - milli - second range. Usually, the dynamics of the current are the fastest in the whole control system. 1.4. CONTROL - SYSTEM STABILITY ANA LYSIS To truly gain an insight into the stability of the overall inverter control system, we must consider both the PLL an d the dq - control loops together. In addition, we must also consider the 17 dynamics caused by the source and interface impedance s . Unfortunately, this makes the traditional transfer - function approach very difficult to use in this case, since the overall cont r ol system will be of very high order. In addition, relating the impedance s , dq - control, and PLL together requires shifting the mathematics into different coordinate reference - frames using the Park transformation. The use of trigonometric quantities within the control loop will make the system non - linear , which voids the use of traditional feedback - control theory . The cross - linking terms which result from the use of rotating reference - frames will also pose additional difficulty, as we will essentially have t wo dynamic systems which interact with each other. Because of these complexity and non - linearity issues, an alternate approach is required. As a tradeoff , rather than analyzing the stability of a non - linear system over all of the we can lineariz e the system at an equilibrium point and then analyze the stability of just the equilibrium point . To do this, we use an approach similar to a state - space representation ; instead of working with a single higher - order differential equation , s uppose that we express the dynamics of the control system as a set of ordinary 1 st - order differential equations. Written in vector form, we have: ( 1 . 32 ) where f ( ) is the array of differential equations and is an array of state variables. Suppose that a particular set of state variable values, , is an equilibrium point of the system. By definition, we can say that f ( ) = 0 . Now, by taking the Taylor - series expansion of th e right - hand side of equation ( 1.32 ) at an equilibrium point gives us the following : ( 1 . 33 ) 18 The 1 st - order partial - derivative in the previous equation i s denoted as the Jacobian matrix. If the components of the state vector are ( x 1 , x 2 x n ) and the com ponents of the vector of system - differential - equations f ( ) are ( f 1 , f 2 f n ), then we can express the Jacobian matrix, J , as: ( 1 . 34 ) Next, suppose we define a vector , , which represents a small perturbation of the state variables from the equilibrium point ; w e can express . Taking the derivat ive of the state perturbation, we have: ( 1 . 35 ) since is defined as an equilibrium point. If the perturbation, , is small, then only the first term of equation ( 1.33 ) is significant since the higher terms will involve powers of our displacement from the equilibrium point. Thus, assuming the Jacobian to be non - zero, the first term of equation ( 1.33 ) should be useful in telling whether the equilibrium point is stable. Rewriting equation ( 1.33 ) in terms of the perturbation vector, we have: ( 1 . 36 ) where the matrix J * is the Jacobian evaluated at the equilibrium point. The matrix J * is constant, so the above equation is simply a linear differential equation which can be analyzed for stability. According to linear dynamic system theory, a solution to a set of linear di fferential equations can be expressed as a superposition of terms of the form , where is the set of eigenvalues of the Jacobian in the system above . The eigenvalues of the Jacobian are, in general, complex numbers. We can express the eigenvalu es as k = k + k , where k and k are the real 19 and imaginary parts of the k th eigenvalue, respectively. After expanding the complex exponential, e ach term of the homogeneous solution to the differential equation can be expressed as: ( 1 . 37 ) From here we can see that only the real - part of the eigenvalues of the Jacobian is of importance. If we have k < 0 for all k , then the homogeneous solution will decay with time, which is the definition of a BIBO - stable ( bounded - input - bounded - output - stable ) system. 1.4.1. COORDINATE SYSTEM & REFERENCE - FRAME MODELING Now that we have established a method for determining the local stability of a system, we must begin describing the differential equations of that system. We will start with the coordinate - system d efinitions . In an effort to simpli fy the modeling equations and notation, we will introduce an additional rotating reference - frame which we will call the xy - frame. This will be the reference frame which is phase - aligned to the true grid voltage, v G (rather than the sensing voltage, v S ). Fu rthermore, the xy - frame will rotate at the grid frequency, G , which may be different than the estimated frequency, , during a transient event. This is shown in Figure 1 . 10 . Figure 1 . 10 : Illustration of rotating and stationary coordinate system reference - frames . 20 The phase angle of both rotating frames (the xy - frame and the dq - frame) are measured relative to the - axis of the stationary - frame ( - frame). Note that the phase angle of the dq - frame, , may be different than that of the sensing voltage angle, S ; however the two angles will be the same at steady - state (i.e., = S . The angle represents the phase difference between the angle of the sensing - point voltage, v S , and true grid voltage, v G , i.e.: ( 1 . 38 ) The value of depends on the voltage drop across the grid impedance, Z G ; thus, the value of should be zero when there is no load current. With these definitions, we can define the grid voltage in its own synchronized reference frame as: ( 1 . 39 ) We can also transform oth er quantities, such as the sensing - point voltage, v S , the inverter voltage, v I , and the current, i , into the xy - frame using the same transformation above. To convert from the synchronous grid - voltage frame ( xy ) to the synchronous sensing - voltage frame ( dq ), we can again use the Park transformation: ( 1 . 40 ) This may be easier to understand by examining the space - vector notation of these quantities, together with the Park transforms . We can express both transform - equations for v G and v S as: ( 1 . 41 ) ( 1 . 42 ) We can also apply a similar logic to describe the AC current in any of the reference frames: ( 1 . 43 ) 21 1.4.2. CIRCUIT - DYNAMICS MODELING With the coordinate systems defined, we can begin to describe the circuit parameters and their dynamics in the form of 1 st - order differential equations. Starting from our KVL circuit analysis, which gave us equation ( 1.21 ) , we can further describe the sensing - point voltage in the grid - oriented xy - frame as: ( 1 . 44 ) Distributing the Park transformation to the previous equation gives us the following: ( 1 . 45 ) which we can spli t into real and imaginary parts. Solving for the derivative terms in both cases, we obtain the following cross - linked differential equations: ( 1 . 46 ) The benefit of describing the currents in the grid - oriented - frame is that the dynamics here do not depend on the PLL or any of its internal parameters. 1.4.3. PHASE - LOCKED LOOP MODELING Next, we can describe the phase - st - order differential equations. The first equation is simple to obtain; differentiating equation ( 1.38 ) gives us : ( 1 . 47 ) Next, we must model the estimated frequency, , which is the output of the PI - controller within the PLL. To do this, we define an arbitrary quantity, , which represents the integral of the angle - 22 error. This will b e used to represent the internal value of the integrator used in the PI - controller. Taking the derivative of , our second differential equation for the PLL system will be: ( 1 . 48 ) From these definitions, we can define the estimated PLL frequency as an algebraic equation: ( 1 . 49 ) 1.4.4. CURRENT - CONTROLLER MODELING Moving on, we will describe the PI - controllers of the current regulation loops. For these, we will take a similar approach to what was done with the PLL. We can define two quantities which are the integral of the error signal of the currents, d and q . These will represent the values of the integrators used in the PI - controllers for the current - regulation. Since the integration of current yields a charge, we will denote these integration variables as Q d and Q q , defined below: ( 1 . 50 ) From these definitions, we can express the output of the PI - controllers, which, when combined with the axis - decoupling terms, form the inverter output voltages. ( 1 . 51 ) 1.4.5. OVERALL CONTROL SYST EM MODEL information of the inverter voltage back to the circuit to influence the current. However, the differ ential equations of the current are expressed in terms of only the sensing - point voltage, v S , and the grid voltage, v G . This was intentionally done so that the set of equations ( 1.46 ) will 23 remain true in later chapters. The grid impedance theoretically will never be zero and thus these equations should always hold. To relate the inverter voltage back to the currents, we start with the KVL expression betwe en the inverter voltage and sensing - point voltage, expressed in the xy - frame: ( 1 . 52 ) Next, we can split this equation above into real and imaginary parts and plug in the set of equations ( 1.46 ) to cancel out the derivative terms. After a bit of manipulation, we arrive with the following expressions for the sensing - point voltages: ( 1 . 53 ) This set of equations can be interpreted as an alternate form of the voltag e - divider equation ( 1.20 ) , written in the xy - frame of reference. The complete set of differential equations which describe the inverter system are as follows: ( 1 . 54 ) 24 The complete set of auxiliary algebraic equations to accompany the previous set of differential equations are also listed below . The first set here describes the coordinate transformations between the grid and sensing - point frames: ( 1 . 55 ) The following set of equations describes the relationships between the sensing - point, inverter, and grid voltages: ( 1 . 56 ) To summarize, we have found here that the dynamics of the system are 6 th - order. If additional details or features are included in the modeling, this order will increase. If the decoupling voltages can accurately cancel out the cross - coupling terms, then the system could potentially reduce to a 4 th - order system at best. To verify the small - signal stability of the system at any equilibrium point which satisfies the non - linear model, a small - signal state - space model can be obtained by linearizing ( 1.54 ) . This will result in the linearize d system written in the form: ( 1 . 57 ) 25 where the matrix A is the Jacobian, evaluated at the equilibrium point, J * , and the matrix B consists of the partial derivatives of the equations which relate the state - variables to the input values , evaluated at the equilibrium point: ( 1 . 58 ) The state - variable vector, , and input - variable vector, , can be expressed as: ( 1 . 59 ) 1.5. ISSUES WITH CONVENTI ONAL DC/AC SYSTEMS To review , interface inductors are a commonly used coupling component for grid - connected DC/AC voltage - sourced power - electronics converters. Placed between the inverter output terminals and the grid - voltage connection/sensing point, t hey provide two main benefits to the converter system (mentioned in the previous sections and repeated again here) . Interface inductors, t ogether with the grid impedance, help low - pass filter the grid line - currents , improving the THD of the system and reducing potential EM - interference . I nterface inductors help to provide a clean sinusoidal voltage - sensing point for converter synchronization by dropping the high - frequency PWM voltage harmonics of the inverter. Due to the second benefit above, we are able to use external voltage sensors to detect the phase angle, frequency, and magnitude of the grid voltage. It is worth noting that increasing the value of the interfacing inductance , L I , helps to further improve both of these benefits above. 26 Despite these benefits, the use of l arge interface - inductors is undesirable, since this leads to additional cost, volume, weight, and power losses (due to added resistance) with in the system. In without comprom ising filtering performance, such as the use of different magnetic materials or 9 - 10 ]. The transformer leakage and line leakage impedances also help in reducing current ripples, but their size is usually not a design parameter; the leakage is usually minimized during the transformer design. Note that if the transformer and grid impedances are suitably sized large enough (potentially in a weak - grid or motor/generator scenario), then the interfacing inductance could be heavily reduced. The Laplace expre ssion for the curr ent and its low - pass cut - off frequency, C , effectively reduce to: ; ( 1 . 60 ) . ( 1 . 61 ) The size of the transformer leakage inductance depends on the transformer size and construction, but typical values range from 5% to 10% per - unit ( pu ) [ 11 - 12 ]. Also, t he inductance of the grid varies based on loading conditions and other factors, but is also generally around a few percent pu [ 13 - 14 ]. It is important to note as well that the grid impedance can be either inductive for ove r - head cables or capacitive for underground cables [ 15 ]. A capacitive cable would not be able to provide harmonic voltage filtering as is desired. Therefore, we w ill limit our discussions to applications considering only over - head (inductive) cables. Alternatively, i nstead of increasing inductance to obtain a lower cut - off frequency, C , of the current, the switching harmonics of the inverter can be shifted up in f requency. The use of higher switching frequencies , f sw , will effectively reduce the magnitude of the ripple current s (since they 27 will be easier to filter at higher frequencies) , enabling the use of smaller inductance values . However, the disadvantage to in creased switching frequencies is that the converter will exhibit additional switching power losses. In addition, the converter will exhibit stronger di / dt and dv / dt radiated emissions, potentially causing more EMI issues. Another power - electronics approach to enable smaller inductances is to reduce the amplitude of the generated voltage harmonics, rather than increasing the switching frequency. This can be achieved using multi - level converter structures, such as the neutral - point - clamped (NPC) multi - level inverter or the cascaded multi - level inverter (CMI), the latter of which is shown in Figure 1 . 11 below . However, this drastically comp licates the system design. In addition to the disadvantages associated with large interfacing inductances, another undesirable fea ture of the traditional control system is the use of dedicated voltage sens ors for grid synchronization. The grid - voltage measurement requires the use of isolated (usually Hall - Effect - based) voltage sensors . The use of these discrete sensors increases the overall system cost and physical complexity (while arguably simplifies the software complexity). In very high - voltage systems, the voltage sensors may also be extremely bulky and costly. Work has also been pr eviously done to mitigate these issues; voltage - sensor - less control algorithms for grid - Figure 1 . 11 : Three - phase nine - level cascaded multi - level inverter topology. 28 connected systems have been developed, such as the Direct Power Control algorithm proposed in [ 16 - 17 ] (which is similar to the Direct Torque Control algorithm of induction machines). However, these algorithms usually depend on a somewhat a ccurate estimation of the total impedance between the converter and grid. Our interest is to reduce Z I and, a s discussed previously, the grid impedance , Z G , can vary depending on various operating conditions, especially in a weak - grid situation. These algo rithms may have other disadvantages as well, such as a variable switching - frequency or require a very fast sampling rate and control loop. It is important to note that these two issues (the use of large interface inductors and discrete voltage sensors) are somewhat coupled together. By reducing the size of the inductors to reduce the system size, weight, and cost, the switching harmonics present at the voltage - sensing point will be increased. The placement of analog filters on sensor lines and digital filte rs within software can be used to remove this noise, but at an increased cost and circuit - board area or an increased computational complexity. Also, both analog and digital filtering approaches can introduce a slight phase delay in the measured voltages. T o help reduce measurement noise, c apacitors are sometimes added to the power circuit Figure 1 . 12 (a). If the transformer/grid impedance , Z G , is small, the circuit model in Figure 1 . 12 (a) effectively reduces to Figure 1 . 12 (b). However, this is a step in the wrong direction; the interest here is to reduce R I and L I while taking advantage of any R G and L G for filte ring , as mentioned previously . In this scenario of having small Z I and large Z G impedances, adding the interfacing capacitor, C I , may also add additional switching losses to the converter since more harmonic voltage will be present at the mid - point node, c ausing increased common - mode currents to flow through the capacitor and the converter. Thus, we will not consider the LC filter scenario in this report. 29 To summarize, the reasons for filtering the high - frequency PWM voltages generated by the inverter include the elimination of potential EMI issues, the removal of reactive - power - producing harmonic components in the current, and preventing noise from entering the control system. However there is a trade - off taking place; an increased inductance or switching frequency can help to e liminate the harmonics, but at increased cost, size, weight, or power loss. Furthermore, algorithms using discrete voltage - sensors rely on having a clean voltage - sensing point. Reducing the inductance adds noise to the measurements (since less filtering is achieved). Control method s which do not rely on grid voltage sensors instead rely on knowledge of the interfacing - impedance value . To avoid these issues, an algorithm which could operate without either of these detrimental components (interface inductors or voltage sensors) would be ideal. However, such an algorithm would need to be able to synchronize to the grid voltage without voltage sensor s and regulate the current without knowledge of the grid or interface impedance s . Such an algorithm can be realize d by the use of virtual impedances impedances which are connected between the inverter and AC grid within software. These impedances allow for regulation of the current and can provide a virtual voltage - sensing point which is free of PWM switching noise, as we will soon If the physical voltage - sensing point is no longer needed, the voltage sensors can be removed from the system . Furthermore, if reasonable filtering of the current can still be achieved (a) (b) Figure 1 . 12 : Alternate equivalent circuit models: (a) capacitively filtered voltage sensing point; (b) 30 by the grid impedance alone, i.e., if the cut - off frequency, C , in equation ( 1.61 ) is still suitably low enough, then the interfacing inductors can also be removed from the system ! 1.6. RESEARCH SCOPE AND CONTRIBUTIONS The main objective of this research is to investigate alternative method s for DC/AC converter synchronization and control, which utilize virtualized impedance s in software , based on the sensed AC currents . This is followed by the design and implementation of a n experimental control system and DC/AC converter prototype which supports an inductor - less voltage - sensor - less operation. The key contributions of this research can be summarized as follows : 1. A self - synchronizing algorithm for PLL - based DC/AC converters , based on the concept of virtual impedance s , is proposed. With this method, the AC voltage sensors can be removed and the physical interfacing inductors ca n be removed in specific cases. 2. A new method to reduce the computational complexity of the synchronous - frame dq - current control algorithm, using the concept of a virtual resistance, is proposed. A simple computational comparison is provided to quantify the complexity reduction. 3. An alternate method to implement an impedance - compensated PLL , based on fully - implemented stationary - frame virtual impedances, is proposed. The proposed method has better transient performance than the traditional partially - implemented rotating - frame virtual - impedance method. Additional research contributions, which were not experimentally verified but have been theoretically developed within this dissertation , are also listed below. These topics are listed with the potential to be developed further as future works. 31 4. A more generalized expression for the quasi - static stability of PLL synchronization loop is proposed. The analysis extend s the stability criteria to the full range of converter operating points (real and reactive). 5. A combination of the self - synchronizing virtual - impeda nce algorithm, together with the impedance - compensation of the PLL using virtual impedance, is proposed as a new technique for the position - sensor - less control of permanent - magnet AC machines operating at high - speed ranges. A means for on - line parameter es timation can also be implemented using a low - frequency injection current, together with this technique. 1.7. REPORT ORGANIZATION The remainder of this dissertation examines the benefits of utilizing virtualized impedances within the synchronization and control loops of a DC/AC converter. The primary focus will be on three - phase DC/AC converter systems but the concepts covered here can be extended to single - phase DC/AC converter systems . In Chapter 2, the theoretical framework and implementation of virtual impeda nce s is first discussed. Afterwards, a method of replacing the physical interface - impedances with virtual ized interfacing - impedances is investigated. Together with this, the feasibility of removing the AC voltage sensors is also discussed. The chapter then introduces the proposed concept of using only a virtual interfacing - resistance for self - synchronization and computational simplification of the common dq - current control algorithm. The stability of the control system is analyzed, focusing on proper tuning of the PID controllers. Afterwards, the experimental test setup used to validate the control method is introduced. The chapter concludes with comparisons between simulated and experimental waveforms showing the dynamic performance of the algorithm. 32 Chapte r 3 introduces the concept of utilizing virtual impedance s to modify the synchronization voltage (as opposed to the inverter voltage , as discussed in Chapter 2). A newly proposed method to impedance - compensate the PLL, which has better transient response a nd is verified through simulation results . Next, it is shown how impedance - compensation (IC) of the PLL algorithm can enhanc e the quasi - static stability of the PLL algorithm. Finally, a more rigorous approach to show the IC - PLL stability is also developed, following [ 19 ]. Next , Chapter 4 presents , recommendations , and ideas for future work. A nine - level (four - module per phase) cascaded multi - level inverter (CMI) is introduced as a possible candidate to enable a true sensor - less inductor - less connection to the 208 V low - voltage utility grid. Also, the combination o f impedance - compensation with a virtualized self - synchronization method is proposed for position - sensor - less high - speed (back - EMF - based) motor control applications. A low - voltage dynamometer test bench located at Kettering University is also introduced as a possible candidate to test the proposed impedance - compensated self - synchronized sensor - less permanent magnet AC motor control algorithm. In conclusion , some details on the MATLAB Simulink simulation model, used to validate some of the developed Appendix A . Information and further details on the 1 kW experimental three - phase invert er prototype are presented in Appendix B . In Appendix C , done over the past several years a re presented . This list includes several journal publications, conference papers, and one patent. 33 2. VIRTUAL - INTERFACE - IMPEDANCE SYNCHRONIZ ATION METHODS In this chapter, the theoretical framework and implementation of virtual impedance s are first discussed. The limitations involved with implementing virtual - inductors are then examined. Afterwards, the concept of replacing the physical interface - impedances with virtualized interfacing - impedances and the removal of the AC voltage sensors for self - synchronizati on is proposed and investigated. A n idea for synchronizing during the start - up process using current sensors is also outlined. The chapter concludes with the proposed concept of using only a virtual interfacing - resistance for PLL self - synchronization, whic h can be used to reduce the computational complexity of the common ly used dq - current control algorithm. The stability and dynamics of these methods are examined and confirmed by simulation and experimental results. 2.1. VIRTUAL - IMPEDANCE IMPLEMENTA TION & LIMITATIONS The concept of virtual impedance has been us ed in many prior applications [ 18 - 20 ]. However, in most of these applications, the virtual impedance is not fully implemented . The within the software of the converter to change In the case of a Voltage - Sourced Converter (VSC), the output is a controlled voltage waveform, usually in the for m of a PWM - voltage. The control - inputs to a VSC are typically currents, other voltages, or other contro l signals. To implement a virtual impedance , assuming that current is one of the sampled input signals , the normal output voltage, v I , can be augmented to become v I ' by subtracting (or adding ) the voltage drop across a virtual interface impedance , Z V I , : ( 2 . 1 ) 34 This concept is also portrayed in Figure 2 . 1 above . The remainder of the control system can remain unaltered, with the virtual impedance calculation occurring alongside it. A similar approach could be used within a Current - Sou rced Converter (CSC), where the voltage of the converter could be measured and the output current could be augmented by adding the product of a voltage and a virtual - admittance . The implementation of these impedances is generally straightforward if done in the stationary - frame . All of the sensor inputs to the controller will ultimately originate in the stationary - frame time - domain so we can directly compute the impedance voltage - drops using the v R = iR , v L = L di / dt ; and v C = 1/ C i dt ; t he exception to this is the inductance. Because the sampled current - sensor inputs will undoubtedly contain sampling noise, the calculated inductor voltage will be extremely erratic if computed directly using a pure derivative. To remedy this, the sampled current can first be passed through a low - pass filter with a unity ga in before taking the derivative. Combining these two operations ultimately results in a high - pass filter. We can express the approximated inductor voltage in the Laplace domain as: ( 2 . 2 ) The high - - off frequency, HP , is multiplied on the numerator to preserve the low - frequency unity - gain and the value of HP is chosen to be substantially higher than the frequency of operation . This make s the response very similar to a pure derivative at low frequencies. This is shown graphically in the Bode magnitude plots of a pure derivative and a unity - gain high - pass Figure 2 . 1 : Inve rter control algorithm augmented with virtual impedance calculation . 35 filter, presented in Figure 2 . 2 . In the vicinity of the grid frequency, f g , the high - magnitude in Figure 2 . 2 (b) look s nearly identical to the magnitude in (a ) . The phase plots of both transfer functions (not shown) also look the same near the grid frequency. Thus, in a low - frequency sense, the two calculations produce identical results. The high - - off frequency , HP , must be chosen so that it is well above the desired grid operating frequency ( f g = 60 Hz typically ); at least one decade above ( f HP = 600 Hz) is recommended so that the phase shift of the filter will not have much impact . However, care must also be taken not to set the cut - off frequency too high, as this will allow more high - frequency noise to be amplified by the derivative - like features of the filter. In practice, one should select a cut - off frequency which is below the switching frequency of the converter. This will ensure that the switching harmonics which are present in the sensed line - current s are not amplified excessive ly (as Figure 2 . 2 (a) depicts). For example, if the grid frequency is f g = 60 Hz and the converter switching frequency is f sw = 10 kHz, an acceptable high - pass - filter cut - off frequency might be around f HP = 1 kHz. Another form of virtual impedance , which is more commonly used , is the implementation within a rotating reference - frame. Using the Clarke and Park transformations to move to a referenc e - frame which is syn chronous to the grid, a virtual - impedance can be partially implemented by examining the mathematical result of moving a derivative into a rotating - frame. (a) (b) Figure 2 . 2 : Bode magnitude plots of (a) a pure deri vative and (b) a unity - gain high - pass filter. 36 The example provided in equation ( 2.3 ) shows the results of moving an inductive voltage from the stationary - frame to a rotating - frame: ( 2 . 3 ) Usually, only the second term , dq , at the end of equation ( 2.3 ) is directly implemented; the derivative term is excluded for the same reasons men tioned previously with derivatives in the stationary - frame. Thus, it should be noted that this second term in equation ( 2.3 ) only represents the stead y - state voltage - drop across the inductance. This is the reasoning behind the claim that This implementation of partial - virtual - impedance is commonly used within dq - current regulators for motor controls or active rectifiers; it is used for decoupling the dq - axis currents by subtracting this steady - state voltage from the respective axes. It has also been used for impedance - compensation of PLL algorithms [ 19 ] ; this will be explored in more detail within Chapter 3. The remaining derivative - voltage term is left usually to a PI - controller to cancel its Figure 1 . 8 ; it has been restated below as Figure 2 . 3 with the partial - virtual - impedance terms highlighted in red. Partial virtual - capacitance can be implemented in a similar fashion. Figure 2 . 3 : Classical dq - frame current controller with inductive - decoupling terms highlighted. 37 Finally, it should be noted that, the main limitation of using partial or fully - implemented virtual impedance s, specifically virtual - inductors in a PWM - based VSC and virtual - capacitors in a PWM - based CSC, is that they can not be used to respond to signals at frequencies equal to or - inductors within a VSC, the voltage drop caused by the virtual - inductor is being reconstructed through the approximate PWM voltage output of the power - to an input signal whose oscillation - period is shorter than one PWM cycle of the converter , the converter will be unable to generate this response accurately . In other words, the use of PWM only allows for different average - output - voltage values to be computed and generated once per switching period. Ideally, the highest - frequency of a signal that could be applied to the output of a PWM - based converter without being aliased should be ½ the switching frequency, based on a similar reasoning to the Nyquist - Shannon Sampling Theorem. Therefore, to summarize, virtual - inductors cannot be used to filter out PWM switching harmonics from a system (this would require some method of producing opposing PWM voltage - drops this is what real physical inductors do). 2.2. REMOVAL OF THE INTER FACING INDUCTO R S & VOLTAGE SENSORS As discussed in Chapter 1, the interfacing - inductor provides two main benefits: a separate voltage sensing poi nt and filtering of the PWM voltage harmonics. Using the concept of virtual impedance, the first item (the voltage sensing point) can be fabricated within software. If the PWM voltage harmonics can be safely ignored (if other inductance s exists in the syst em), then the real impedance can be safely replaced by a virtual one! From a control - standpoint , there is little difference between a DC/AC inverter system which uses a real, physical inductor and one which uses a fully virtualized one. Even though the hig h - frequency content may be slightly 38 different (since a virtualized inductor using the high - pass - filter approximation looks like a resistor above HP ), the high - frequency harmonics do not usually play a role with in the control system ( it is assumed that the se harmonics will be filtered out anyways ). With this in mind, if we can argue that if the high - us e of a virtualized inductor will not impact the r emainder of the control system; this is a reasonable assumpt ion in most cases. For example, i f a high - pass - filter is used to compute an interface - inductor voltage and the bandwidth ( the cut - off frequency) of the filter is selected to be f HP = 1 kHz, the dynamic response of this inductor can be roughly 10x greater than the bandwidth of the dq - current PI - controllers which ar e tuned to a settling time of 5 ms (a reasonable speed for the currents) . Using the analysis from Chapter 1, we can rewrite equation ( 1.3 ) (which is the expression for the closed - loop poles of the dq - current PI - control loops) to be in terms of the dq - current settling time, T st , c : ( 2 . 4 ) If a settling time of 5 ms is selected for the current s and the controllers are critically damped, the bandwidth of the dq - current loops will be roughly 4 12 7 Hz, nearly a decade below f H P . Usually, the dq - currents are con trolled to have the fastest dynamics in the control system. Thus, in this example, it should be acceptable to ignore the effects of the high - pass filter on the remainder of the The standard cont rol system block diagram is shown in Figure 2 . 4 on the next page . Again, the only difference between the inverter output voltage, v I , and the sensing voltage, v S , is the voltage drop across the interfacing impedance, Z I = R I + I , which we will denote as v Z I : ( 2 . 5 ) 39 Now, if we temporarily ignore the PWM harmonic content of the inverter voltage, v I , and assume that the inverter could generate a pure sine - wave output voltage, then we could argue that there should be no difference between the control system above in Figure 2 . 4 , and the modified control system shown in Figure 2 . 5 , on the next page. In Figure 2 . 5 , the physical interfacing impedance has been removed and the voltage - drop of this impedance has been computed within the digital controller. This virtual - impedance voltage - drop is the output voltage, v I , ( computed by the dq - current controllers ,) to generate a n voltage, v I ' , which accounts for the drop. With the inverter output voltage augmented and the physical impedance repla ced by a short - circuit, the sensing voltage, v S , remains the same as it was in Figure 2 . 4 and is now also equal to the inverter output: v S = v I ' . From a low - frequency standpoint, the control scheme of Figure 2 . 5 should work identical to that of Figure 2 . 4 . The problem here, however, is when we relax our previous assumption and Figure 2 . 4 : Classica l inverter control block diagram with interfacing impedance. 40 consider the inverter PWM harm onics. These are now being directly fed by the voltage sensors into the Clarke/Park transformations, which then in turn feeds to the PLL and the dq - current controller s . The PLL may be able to withstand /filter the excessive PWM harmonic content, but the dq - current controller cannot. Any feed - forward - like paths from the PLL to the dq - control will be plagued with excessive noise, requiring the use of additional low - pass filters ( as in Figure 2 . 5 ) or the use of other methods to eliminate the PWM noise from the control system. However, a simple r and more convenient solution exists to solve this harmonic noise problem. It is only the low - frequency component of the sensing voltage which is needed by the PLL and dq - controller (the PWM harmonics are the problem). Again, note that the inverter out put voltage is now equal to the sensing voltage: v S = v I ' (since the two nodes are shorted). The harmonics are only added to the output by the PWM algorithm. The input to the PWM block will only be the low - frequency component of the inverter voltage. Thus, the desired voltage signals Figure 2 . 5 : Inductor - less inverter control block diagram utilizing virtual impedance. 41 (without PWM) already exist within the control algorithm! This means that we can directly bypass the PWM - to - inverter - to - sensor path and directly feed this augmented inverter voltage , v I ' , within software back into the cont rol system ; this proposed control technique is shown below in Figure 2 . 6 . Again, this works because the v I ' voltage signals in software are the same as only the low - f requency component of the sensing voltage (no PWM has been added yet). With this control technique, the AC voltage sensors can be completely removed from the system ! The only new complication that arises from this proposed control algorithm is the method of synchronization during the start - up process. Of course, there also still exists the is sue of having adequate filtering inductance to smoothen the shape of the AC current note the consistent inclusion of the grid inductor L G . Since there is no longer any voltage - sensing on the AC side, when the converter is not operating, there is no direc t way to measure the grid voltage to synchronize to it. Starting the converter without proper synchronization can cause start - up Figure 2 . 6 : Proposed i nductor - less AC voltage - sensor - less inverter control diagram u sing virtual interface - impedance. 42 transient issues, which could trigger fault protections built into the converter, grid, or both. To solve the start - up synchron ization problem, the on - board current sensors could be used to detect the frequency, phase angle, and approximate voltage magnitude of the grid. To do this, a small load could be applied to the AC - lines to generate some small AC current through the current - sensors. A separate single - phase PLL algorithm could then be used to lock onto the AC current waveform to infer the magnitude, phase, and frequency of the grid. The load could be inductive, capacitive, or resistive, however a capacitive load is recommende d to avoid the bulkiness of a 60 Hz inductive load and the power losses of a resistive load. A configuration such as the one in Figure 2 . 7 could be used, where the capacitive load could be connected from line - to - line through a small (low - current - rated) bi - d irectional switch. During the start - up process, the start - up switch , S SU , could be closed, placing a start - up capacitor, C SU , across two of the lines. This start - up capacitor will draw a capacitive current through two of the current sensors. After synchronization , th e S SU switch could be opened and the converter could start generating PWM while simultaneously enabling the self - synchronization algorithm. If the capacitor was connected across phases B and C, the current flowing through the phase - C current sensor will ha ve the exact same phase as the phase - A line - Figure 2 . 7 : Capacitive line - line load configuration for voltage - sensor - less start - up synchroni zation. 43 to - neutral voltage (the capacitor current will have a 30° shift because the applied voltage is line - to - line and another 90° shift since the load is capacitive). Thus, a single - phase PLL could be used to lock onto the phase - C current to obtain the grid frequency and phase angle. To detect the grid voltage magnitude, the start - up capacitor, C SU , could be carefully selected to produce a reasonable current magnitude which could still be sensed. For example, suppose an inverter system was designed with bidirectional current sensors ha ving a maximum sensing range of ±100 A (this would be adequate for a three - phase 208 V AC , 20 k VA system). Assuming the microprocessor used in the converter had an Analog - to - Digital Converter (ADC) with 12 - bit resolution, the per - bit resolution of the ADC c hannels connected to the current sensors would be equal to : 200 A / 2 12 bits = 48.82 mA/bit. To allow a few bits of sensing range, the peak phase current, I m , (which is equal to the capacitor current) could be limited to ~250 mA. This will cause the ADC va lues to vary by about ± 5 bits (which may be barely enough for the algorithm to detect and synchronize to) . Working the phasor analysis, the required capacitance to produce a current of 250 mA peak on a 60 Hz grid with 208 V LL RMS would be: ( 2 . 6 ) Such a capacitor of the polyethylene - film - type can easily be found. For the synchronization method, a single - phase nonlinear - variation of the SRF - PLL algorithm, shown in Figure 2 . 8 , can Figure 2 . 8 : Block diagram of a single - phase nonlinear PLL which includes magnitude detection . 44 be used. Once the magnitude of the current is detected, the voltage magnitude could be computed by reversing equation ( 2.6 ) above. 2.3. VIRTUAL - INTERFACE - IMPEDANCE SYSTEM STABILITY ANA LYSIS To maintain similarity with the traditional control method, we will consider the case of using a virtual - impedance composed of a virtual resistance, R V I , and a virtual inductance, L V I . As stated in the previous section, the overall control of such a system should be practically identical to that of the system with real interfacing impedances. However, we must exercise caution when considering the stability of the system, since there is an inherent algebraic loop present in the control system shown above in Figure 2 . 6 . T - feed - forward decoupling paths. 2.3.1. CONTROL - SYSTEM SAMPLING - DELAY MODELING To deal with the algebraic loop , we must place single - cycle delays within the control alg orithm . Luckily, such delays are conveniently already present within the digital implementation of the control algorithm, since most Analog - to - Digital Converter (ADC) hardware and PWM hardware within a Digital Signal Processor (DSP) usually require a t leas t a few clock cycles of delay before reading or writing values . In some cases, these delays are intentionally enlarged to maintain synchronization with the PWM switching of the converter. These delays are illustrated in the block diagram shown in Figure 2 . 9 . Thus, a total of two switching - period delays will accumulate in the control algorithm. In the traditional control Figure 2 . 9 : Illustration of input & output signal delays in a digital control system. 45 system, the sensing - point voltage , v S , would also experience a one - cycle delay (not shown here). Note that the delays are effectively applied in the stationary - frame of the system (the real sensor and PWM signals will be three - phase sinusoidal signals). Applying delays to sinusoidal signals w ill cause a slight phase - shift in the measured values. This will show up as a slight rotation of the values in the dq - frame (or the xy - frame). The se delays will also affect the dynamics of the system, potentially causing instability issues. As was done in Chapter 1, we can model all of the system dynamics as a set of 1 st - order non - linear differential equations. From this set of equations , we can linearize the system at an equilibrium point by computing the Jacobian matrix, and from here, we can assess the l ocal stability. However, a n approximation must be made for these discrete - time unit - delays to move all terms to continuous - time. One method of capturing the behavior of discrete delays in a continuous - time system is to use the Taylor - series approximation on the Laplace - transform of the unit - delay . The Laplace transform of the time - shifted unit - impulse function can be expressed using the time - shifting property of Laplace transforms, as shown below: ( 2 . 7 ) The issue here is that the Laplace transform of the unit delay cannot be easily expressed as a rational polynomial of complex frequency, s (due to the exponential). However, by u sing a first - order Taylor - series approximatio n , we can express the Laplace transform of the time - delay as simply a low - pass filter. The transfer function approximation is given as equation ( 2.8 ) . U sing the first - order Taylor series approximation of e x near x = 0; we can say e x x , as shown: ( 2 . 8 ) where the time delay, t 0 , in this case will be the inverter /switching period, T s w . 46 Applying this concept to our control system, we must include additional state variables to model the time - delay low - pass filters, which were not present in our control system model developed in Chapter 1. To be consistent with our p revious modeling in Chapter 1, we will first transfer the unit - delays to a rotating frame . Applying the frequency - shifting property of Laplace transforms, we obtain: ( 2 . 9 ) As illustrated in Figure 2 . 9 , we will need to apply this complex low - pass filter to the sampled input currents and the outputted inverter voltages. For the currents, we can introduce a new space - vector variable, . Applying the delay in the xy - frame gives the following: ( 2 . 10 ) Splitting the above equation into real and imaginary parts gives us ( 2 . 11 ) For the output voltage delay, realize that because of the structure of our virtual - interface impedance system, the only difference between our augmented inverter voltage, v I ' , and the virtual sensing - point voltage, v S , is a single - cycle delay. This is illu strated in Figure 2 . 10 below. Figure 2 . 10 : Location of PWM delay in a virtual - interface - impedance control system . 47 This arrangement is required to prevent an algebraic loop from forming when computing v S within the control system. Therefore, the inverter output voltage and the sensing - point voltage are technically not equal, but should be very similar to each other. R ather than introducing new variables, we will define the PWM delay using existing variabl es within this particular control scheme. Modeling the delay in the dq - frame gives us the following relationship: ( 2 . 12 ) which after splitting into real and imaginary parts gives us ( 2 . 13 ) Accounting for these delays, we must also update our Park - transform definitions of moving between the grid - aligned xy - frame and the PLL - aligned dq - frame. The set of equations ( 1.55 ) will be modified to use the low - pass - filtered values instead of the actual values. This is sho wn below. Note that eq uations (5) and (6 ) of the set have been removed since the theoretical inverter voltage, v I , is no longer needed in the differential equations describing the currents . Also note that the reference - frame directions of equations (3) and (4) of the set have b een reversed. ( 2 . 14 ) 2.3.2. VIRTUAL INTERFACE - IMPEDANCE MODELING In addition to the sampling delays, we must develop equations to express the virtual - interface - impedance voltages in ter ms of a set of 1 st - order differential equations. We start from 48 the s - domain KVL expression of the virtual - impedance voltage, where the inductor voltage is calculated using a high - pass filter: ( 2 . 15 ) where HP is the high - pass filter cut - off frequency. We can rewrite this equation to express th e voltage, , in the dq - frame by using the frequency - shifting property of Laplace transforms : ( 2 . 16 ) Note that this also results in a complex low - pass filter, a s seen in the previous section: ( 2 . 17 ) To accommodate this filter , we can create an additional space - vector state - variable, , to represent the stationary - frame low - pass filter of the current (to be used in the high - pass filter) . Using this low - pass filter variable, we can rewrite the previous equation as: ( 2 . 18 ) The relationship between the low - , and output, , is expr essed below: ( 2 . 19 ) which, when split into real an imaginary parts, gives us ( 2 . 20 ) 49 From here, we can substitute the set of equations ( 2.20 ) into equation ( 2.18 ) to obtain the total expression for the virtual interface - inductor voltage in the dq - frame. Splitting into real and imaginary parts gives us the following: ( 2 . 21 ) Notice that the last two terms in both equations will cancel, leaving us with: ( 2 . 22 ) 2.3.3. PID - CURRENT - CONTROLLER MODELING Next, we will describe the modeling of two dq - frame PID controllers. Because t he voltage - sensor - less virtual interface - impedance control algorithm requires some small amount of derivative gain in the control loop for stability (explained in a later section ), we must augment the mod el developed in Chapter 1 to include a derivative term. As done in the previous section, to implement a derivative, we can use a high - pass filter with a high cut - off frequency. Building from what was developed in Chapter 1, w e can define two quantities wh ich are the low - pass - filtered values of the error signal of the currents, d ,LP and q ,LP . These will be used in the PI D - controller derivative calculation. The space - vector version of the low - pass filtered error signals can be expressed as : ( 2 . 23 ) where D is the cut - off frequency of the low - pass filter. Rearranging and expanding this into real and imaginary parts gives: 50 ( 2 . 24 ) With the low - pass filter of the error defined, we can express the total derivative component of the PID - controller output as follows: ( 2 . 25 ) With the derivative modeled, w e can express the output of the PI D - controllers, which, when combined with the axis - decoupling terms, form the inverter output voltages. We will use the other definitions of Q d and Q q from Chapter 1 as well: ( 2 . 26 ) Note that the decoupling terms have also been modified here to be based on the sum of the real interface inductance, L I , and any virtualized interface inductance, L VI . In the proposed control algorithm, the value of L I = 0, so the decoupling term will reduce to only respond to L VI . 2.3.4. LINEAR SYSTEM MODEL FOR VIRTUAL INTERFAC E - IMPEDANCES After defining the additional state variables in the previous sections, we can summarize all of developed mathematical relationships and provide a complete set of all the differential equations used to describe the proposed control algorithm. The other def initions from Chapter 1 regarding the PLL dynamics and the xy - frame current dynamics remain unchanged. The set of algebraic equations which relate various values to the state variables are summarized below. These are in addition to the four reference - fr ame translation equations in ( 2.14 ) : 51 ( 2 . 27 ) Altogether, the complete contr ol algorithm ends up being a 14 th - order non - linear dynamic system! This will undoubtedly be very difficult to analyze by hand and will require computer - aided analysis. The set of differential equations and a short phrase indicating where each equation is used are presented in ( 2.28 ) below . 52 ( 2 . 28 ) From here, the 14 × 14 Jacobian matrix can be computed and evaluated at an equilibrium point. This can then be used to check for local stability. While useful, this analytical procedure does not offer much insight on the limitations f or tuning the PI/PID - controllers, or for selecting the values of the high - pass filter cut - off frequencies. In the next section, we will attempt to provide some rough guidelines on the tuning of the PID parameters to maintain stability. 53 2.3.5. CURRENT - C ONTROLLER T UNING USING PADÉ APP ROXIMANT In an effort to reduce the complexity of the control system down to something which can be analyzed by hand, allowing us to gain some insight on the limitations for tuning the PID - controllers, we will make the following simplifications to the previous dynamic system model: (a) transfer all differential equations into the dq - frame, (b) assume that all of the cross - coupling terms are negligible or cancellable , and (c) assume that pure derivatives are used for the virtual inductance and PID - controller. The first two assumptions will allow us to remove the PLL dynamics from our analysis and completely decouple the two axes of the dq - frame. Thus, this will allow us to ignore 8 of the 14 differential equations from the previous page . The last assumption will allow us to further eliminate the two low - pass filters, eliminating another 2 differential equations. The resulting system will be only 4 th - order, which should be much easier to analyze. However, it will only tell us some information regarding the tuning of the PID - controllers. A depiction of the simplified virtual - impedance control system is shown in Figure 2 . 11 . The just the transformer/grid impedance, Z G , since the real interfacing impedance, Z I , has been removed (as previously discussed and shown in Figure 2 . 6 ); the inverter output is now directly connected to the PLL sensing point (the transformer terminals). The control system in Figure 2 . 11 is expressed in the dq - frame; the plant represents the transfer function of an RL circuit moved to the dq - frame without t he cross - axis coupling: ( 2 . 29 ) where R G and L G 54 To improve the model somewhat, after all of the simplifications above, we can use a different approximation for the unit - time delays. Another method of capturing the behavior of discrete delays in a continuous system is to use the Pad é approximant. While similar to the Taylor Series, - linear functions by a rational function of a given order (i.e. a ratio of polynomials with some given order). Using a first - order Padé approximant, we can express the Laplace transform of the time - delay as the following transfer function: ( 2 . 30 ) After applying the first - order Padé approximation, the control system of Figure 2 . 11 can be redrawn as shown in Figure 2 . 12 on the next page . The positive - feedback loop at the top has been c ollapsed , based on its equivalent transfer function , A ( s ) , which is very similar to an integrator with a very large gain. This is expressed below in equation ( 2.31 ) , where the time - delay parameter, T sw , is the switching period of the inverter PWM outputs (which corresponds to the PWM duty cycle and ADC update rates within the control software); ( 2 . 31 ) Figure 2 . 11 : Equivalent dynamic system model of virtual - impedance control algorithm. 55 With the system approximated, we can collapse the system to obtain the transfer functio n of the current - control loop. The details are o mitted here, but the resulting 4 th - order transfer function will have a form as given below: ( 2 . 32 ) where the denominator polynomial coefficients are: ( 2 . 33 ) For stability, the numerator coefficients, b n , are of less importance and are not mentioned here. From the denominator coefficients, we can ob tain some requirements for stability, based on the Routh - Horwitz Stability Criterion. Written in terms of the polynomial coefficients, the stability of a 4 th - order system is given by the following set of inequalities: Figure 2 . 12 : Equivalent dynamic system model of virtual - impedance control algorithm. 56 and ( 2 . 34 ) Assuming the device parameters, R G , L G , R V I , and L V I , to all be much smaller than 1/ T sw , we can make the following observations for the stability: From a 3 > 0 : ( 2 . 35 ) From a 2 > 0 : ( 2 . 36 ) From a 1 > 0 : ( 2 . 37 ) Additional stability requirements can be obtained by examining the higher - order inequalities presented in ( 2.34 ) . How ever, from the simple inequalities above, we can determine that there are upper and lower - limits to the quantity ( L V I + k d ,c ) and a lower - limit to the quantity ( R V I + k p ,c ). It is interesting to note that the virtual - inductance, L V I , is somewhat related t o the k d ,c derivative - gain of the controller. The two terms frequently show up together within the system transfer function. Likewise, the virtual - resistance, R V I , is somewhat related to the k p ,c proportional - gain and we could infer that a virtual - capacita nce, C V I , would be related to the k i ,c integral - gain. The important thing to note here is that some small (less than ~ L S ) but non - zero derivative - gain is needed for stability (but it does not matter whether it comes from L V I , from k d ,c , or a little from both) . This will become of more importan ce in the following section. 2.4. CURRENT CONTROL - LOOP SIMPLIFICATION USING VIRTUAL RESIST ANCE In a voltage - sensor - less control algorithm, t he real purpose of the measurement voltage being ut voltage (on the other side of the interfacing impedance) is to relate the information from the current sensors to the PLL. If a current is applied in the wrong 57 axis (or in a different space - vector direction than estimated), a non - zero voltage will appea r in the q - axis of the measurement point. T he PLL will try to reduce this voltage to zero, realigning the system. However, f or synchronization, there is no requirement that the interfac ing - impedance needs to be inductive. Any type of impedance or transfer function may be used to convey the current - sensor information to the PLL. The typically - used impedance is inductive merely because of its ability to also filter the PWM voltage - harmonics from the inverter . Wi th the interfacing impedance becoming virtualized and the synchronization voltage measurement bypassing the PWM - stage and voltage sensors (eliminating any filtering needs), we are free to select any interfacing impedance we wish. For simplicity, the most o bvious choice , which is proposed here, is to use a resistance . This will have the following two benefits: 1) The calculation of the virtual voltage - drop will be very straightforward, only consisting of three multiplication and three addition operations (i f i n the abc - frame) . No integration or derivative approximations will be required, reducing computational complexity. 2) The control of the dq - currents can be simplified. The commonly - used decoupling terms are implemented to cancel the steady - state voltage drop o f an inductance in the system. With that inductance removed , the decoupling terms are no longer needed. The dq - axis currents and voltag es will inherently be decoupled from each other. This further reduces computational complexity of the overall control alg orithm. The regulation of the dq - currents can still be done using a PI D - controller in each axis . The derivative - term in the controller is needed to ensure the stability; this was hinted at in the previous section and will be shown again here soon . T he dyna mics will also change due to the interfacing impedance now being just a resistor. The equivalent virtual - resistance control system (with the delays substituted by the 1 st - order Padé approximation) is shown below in Figure 2 . 13 . 58 In the figure, the positive - feedback loop of the sensing - point voltage has already been collapsed, as discussed previously and shown in equation ( 2.31 ) . The transfer function of this system will also be a 4 th - order system, having a form the same as in equation ( 2.32 ) . The denominator coefficients are given below: ( 2 . 38 ) From the transfer function, we can make some similar observations on the stability, as was R G and R V I , to be larger than the grid inductance, L G , or sampling period, T sw than or equal to the grid inductance: T sw L G . From these assumptions, we can make the following observations for the stability: From a 3 > 0 : ( 2 . 39 ) From a 2 > 0 : ( 2 . 40 ) Figure 2 . 13 : Padé - approximated dynamic system model of virtual - resistance control algorithm. 59 From a 1 > 0 : ( 2 . 41 ) Here, we reach very similar conclusions as were found in the previous sec tion. The derivative controller - gain, k d ,c , itself now has an upper and lower limit. Also, the sum of proportional gain and virtual resistance must exceed some value, k i ,c T sw . The mai n difference here, with L V I = 0, is that now the derivative - gain, k d ,c , must be non - zero to ensure stability of the system . If we can further assume that the positive - feedback - path from the inverter output - voltage to the sensing - voltage is sufficient so th at the KVL equation ( 1.21 ) still holds , then we can further approximate the control system to only incorporate the PWM and ADC delays while letting the virtual - impedance function as the system plant. Equation ( 1.21 ) has been rewritten below as equation ( 2.42 ) , except now Z I has been replaced with Z V I : ( 2 . 42 ) This requires that the sampling rate of the control loop be sufficiently small, such that the phase delay between v S and v I ' is negligible. As mentioned previously, the use of a virtual interfacing - resistance means that the inductive decoupling - terms of t he dq - control algorithm can be eliminated. Thus, the proposed dq - control system will effectively reduce to the system shown in Figure 2 . 14 . Conveniently, with the dec oupling terms removed, the estimated frequency, , is no longer needed by the control system. With this, a low - pass filter can potentially be removed from the PLL system as well (in some cases, the estimated frequency may be low - pass filtered to remove no ise coming from the PLL voltage inputs). The addition of the sensing - point voltage, v S , is accounted for already in the previous control system diagram ( Figure 2 . 13 ), bu t it is included here for comparison to the traditional method. 60 Going one step further, if the KVL equation ( 2.42 ) holds, then we can also develop an equivalent control - system model where the virtual - impedance functions as the plant. In this equivalent model, we will assume that the dynamics of the current will be tuned to be much slower than the single - cycle Padé - approximated del ays. This allows us to also ignore the delay blocks, yielding a lower - order system with which we can analyze and easily estimate the dynamics. This simplified control system is shown below in Figure 2 . 15 . T he closed - loop transfer function of this system will be the following: ( 2 . 43 ) The poles of this approximated system can be easily found; they depend only on the PID controller tuning and the virtual resistance value (as expected from the original proposed system description). The values of the poles are listed here: Figure 2 . 14 : Simplified dq - frame current - controller without decoupling terms. Figure 2 . 15 : Equivalent PID - control system of the dq - current controllers using virtual - resistance. 61 ( 2 . 44 ) F urther simplification can be made by setting the proportional - gain to zero: k p ,c = 0. The virtual resistance acts similarly to a proportional gai n; the two parameters , R V I and k p ,c , show up constantly together within the system transfer - function s with in this chapter . Fro m the previous stability analyse s, there should be no issue having k p ,c = 0 so long as R V I is sufficiently chosen . Next, recall that the derivative gain has an upper - bound, related to the inductance, L G . Since the grid inductance may usual ly be in the milli - Henry range or smaller, we can approximate this value to be roughly equal to zero. With k p ,c = 0 and k d ,c 0 , the two left - half - plane zero s on the numerator of the transfer function in ( 2.43 ) will become negligibl y large . Furthermore, one of the poles on the denominator will become extremely fast , making the other closed - loop pole dominate (and the transfer function will be overdamped, have a simple , almost first - order response ) . The control loop for the current will take the form shown in Figure 2 . 16 an d the transfer function will reduce to : ( 2 . 45 ) Based on these results, the control of the current (if a pure integral - controller is used) will always take the form of a first - order low - pass filter, maki ng the system have no overshoot, while being very easy to tune. The bandwidth of the current (the cut - off frequency) will be : Figure 2 . 16 : Simplified I - control system of the dq - current controllers using virtual - resistance. 62 ( 2 . 46 ) Assuming rou ghly four time - constants for the settling time, we also can get the expression: ( 2 . 47 ) The limitation of this tuning approximation depends on the 2 nd - order poles listed in equation ( 2.44 ) . As the expression under the radical becomes closer to zero or less than zero, the system will become critically or under - damped, causing overshoot and ringing in the response of the current. The system can be maintained to have a first - order - like over - damped response so long as the following condition holds: ( 2 . 48 ) These claims are verified at the end of this chapter through MATLAB Simulink simulation and experimental results. 2.5. COMPUTATIONAL COMPLE XITY COMPARISON OF C ONTROL METHODS Moving on, a s a means for comparison, the total number of m athematical calculations (add, subtract, multiply , divide, square - root, and table look - ups ) required by the different control system variations can be examined . Before performing this comparison however, we must make some assumptions on the number of clock cycles required to perform each mathematical operation. A common platform for controlling a power - electronics system is to use a Digital Signal Processor (DSP) which has floating - point calculation support. The implementation of the Floating - Point Unit (FP U) is often unevenly distributed among the mathematical calculations extremely efficient, while other operations like division and square - roots are somewhat slow 63 [ 21 ]. To form a basis for comparison, the number of clock cycles required to perform each mathematical operation will be assumed to have the values listed in Table 2 . 1 . Addition, subtraction, multiplication, and table look - ups will be penalized by only 1 clock cycle. Computing saturation limits (used within PI D - controllers) will be penalized 6 clock cycles, since this usually involves the use of two if - statements requiring a logical check, a branch statement, and the execution of the saturation. Division will be arbitrarily penalized by 20 clock cycles and the square - root op eration will be 40 clock cycles. From the assumptions in Table 2 . 1 , we can examine the total number of clock cycles required to implement some basic control - system tasks . These are presented in Table 2 . 2 . The first several columns of the table list the frequency of each type of mathematical operation occurring in the listed task. The last column of the table lists the number of clock cycles required to implement each task , which is the product of the number of occurrences of each operation and the number of cycles required for each operation, each summed together. For example, a PI - controller Table 2 . 1 : Assumed number of FPU clock - cycles required for basic mathematical operations. Add/Sub Multiply Look - Up Saturate Divide Sqr - Root # Clk Cycles 1 1 1 6 20 40 Table 2 . 2 : Number of FPU operations and clock - cycles required for common control - system tasks. Task Add/Sub Multiply Look - Up Saturate Divide Sqr - Root # Cycles Clarke Xfrm 3 4 7 Park Xfrm 2 4 2 8 Integrator 1 1 2 LPF / HPF 2 2 4 P I - Controller 2 3 2 17 PI D - Controller 5 6 2 23 Inv. Hypot. 1 2 1 1 63 64 requires 2 additions, 3 multiplications, and 2 saturation checks. The number of c lock cycles required to implement a PI - controller will therefore be: (2 × 1) + (3 × 1) + ( 2 × 6 ) = 17 cycles. The last row of Table 2 . 2 h is used within the PLL to normalize the angle error, described previously in equation ( 1.14 ) . With this basis for comparison, w e will consider here three systems: a traditional inverter control system (using a physical inductor and voltage sensors ), one with a virtualized inductor, and one using a virtualized resistor. Th e computational loads for each system are presented below in Table 2 . 3 . Note that the PWM calculations and the outer control - loop, which is used to generate the dq - cu rrent references , i dq * , will be excluded. The three main columns of each system in Table 2 . 3 , labeled as dq - - phase - locked loop, dq - current controllers, and any virtual impedance s, respectively. The improvements or deg radations to the computational times (against the classical control) are color - coded and bolded in green or red, respectively. Detailed explanations for the modification Table 2 . 3 : Comparison of computational - load for three different dq - c ontrol systems. Task (#cyc) Classical System Virtual Inductance Virtual Resistance PLL dq - con Vir - Im PLL dq - con Vir - Im PLL dq - con Vir - Im Add/Sub/Mult ( × 1) 1 10 0 1 10 12 1 4 6 Clarke Xfrm ( × 7) 1 2 0 2 0 2 Park Xfrm ( × 8) 1 2 0 2 0 2 Integrator ( × 2) 1 1 1 LPF / HPF ( × 4) 1 0 1 3 0 0 P I - Controller ( × 17 ) 1 2 1 0 1 0 PI D - Controller ( × 23 ) 0 2 2 Inv. Hypot. ( × 63) 1 1 1 Subt otal Cycles: 102 7 4 0 87 8 6 24 83 80 6 Total Cycles: 17 6 197 169 65 of values in the table are provided below: PLL: in both virtualized systems, the Park & Clarke transforms are not needed since no voltage sensors are used. The voltage values from the dq - control algorithm can directly be used. In the virtual - resistance case, the PLL no longer needs to send the frequency estimate, , to the dq - controllers f or decoupling, so a low - pass filter can be removed . dq - Con: in both virtualized systems, a PID controller must be used to guarantee stability. (The virtual - inductor algorithm could potentially omit the derivative - term if the virtual inductance, L V I , is suf ficiently chosen.) The virtual - resistance algorithm sees a small improvement since the decoupling terms are no longer needed. Vir - Im: both virtualized systems experience a loss in speed due to the added calculations for the virtual - voltages. The virtual - re sistance case is more efficient than the virtual - inductance case since the high - pass filters (for derivative approximation) are not needed. The two virtualized cases also assume that the virtual - voltages are computed in the abc - frame. From this comparison, we can see that the implementation of the virtual - resistance control algorithm actually saves a few clock cycles (about 4 .0 %) over the traditional non - virtualized control, even when considering the added computation of the virtualized components. Thi s is because of the removal of the low - pass filter in the PLL (since is no longer needed or filtered) , the removal of the Park & Clarke transforms in the PLL, and the simplification of the dq - current control (the removal of the k p ,c te rms and decoupling terms). To further simplify the virtual - resistance - based control algorithm and make it even more computationally efficient, we can arbitrarily select an interfacing - resistance of R V I the three V × I multiplications needed to c ompute the virtual voltage - drops will vanish. Oddly enough, the calculation of the sensing - point voltage will now be mathematically equivalent to 66 simply subtracting the measured current - sensor values from the computed inverter output voltage. This will the n be fed to the PWM and PLL blocks; while seemingly strange, this method does work! Th e result listed in Table 2 . 3 for a virtual - resistance system , 16 9 cycles, can be further reduced to 1 65 cycles ( now a 6.2 % reduction from the classical method ) if a virtual n is done within the - frame or dq - frame , rather than the abc - frame. This eliminates 3 multiplications and 1 subtraction (a reduction of 4 floating - point operations) . Implementing a virtual - resistance in either a stationary or rotating frame should be equ ivalent since no additional voltage terms arise voltage from the stationary - frame to a rotating - frame (as compared to the case for the voltage - drop of a virtual inductor or capacitor). Further improvement can be made if the k p,c pr oportional - gain terms are removed; an extra 4 cycles can be saved, increasing the reduction to 8.5%. 2.6. VIRTUAL - RESISTANCE SIMULAT ION & EXPERIMENTAL RESULTS To validate the concepts discussed in this chapter, a MATLAB Simulink time - domain simulation model has been generated to simulate the inductor - less sensor - less control algorithm using a virtual - resistance for self - synchronization. The top - level diagram of the simulation model is shown in Figure 2 . 17 . The inverter is simulated using MOSFETs with low on - state resistance ( to match the experimental prototype (introduced later in this section) . The inverter is directly connected to the grid impedance, R G + L G , which connects to an ideal AC voltage Figure 2 . 17 : MATLAB Simulink inductor - less voltage - sensor - less virtual - resistance simulation. 67 source. Only the inverter DC - bus voltage and line currents are sensed an d fed to the control algorithm. The true grid voltage is also sensed but not used by the control ler . The inverter PWM signals are generated from the duty cycle outputs of the dq - controller. - frequency triangle carrier wave used to generate the gate - switching signals. An inverter deadband of t DB = 500 ns is simulated and the inverter switching frequency is set to 1 0 kHz ( T sw = 10 0 µs). The se and other parameters of the simulation are summarized in Table 2 . 4 below. Smaller - than - usual values for the grid phase - voltage magnitude ( 3 0 V RMS) and inverter DC bus voltage magnitude ( 1 00 V) were used. This was done to ma ke the impedances have a more significant influence on the control system since the currents were small . The total grid impedance magnitude, | Z G |, was selected to be roughly 1 4 % pu. The simulated converter was operated at a rated power output of ~ 1 kW. Table 2 . 4 : Virtual - resistance simulation electrical parameters. Parameter Symbol Value Per - Unit Grid line - neutral peak voltage V G m 30 V 100% pu Inverter DC - bus voltage V DC 100 V --- D - axis current reference i d * 1 0 A 100% pu Q - axis current reference i q * 0 A 0% pu Rated power output S 0 . 9 k VA 100% pu Per - Unit Base Impedance Z base --- Grid parasitic inductance L G 1 m H 12.5 % pu Virtual interfacing inductance L V I 0 m H 0% pu Grid parasitic resistance R G 200 6.6 % pu Virtual interfacing resistance R V I 33.0 % pu Nominal grid frequency f g 60 Hz --- Inverter switching frequency f sw 10 kHz --- Inverter deadband time t DB 500 ns --- 68 The top - level diagram of the control system block is presented in Figure 2 . 18 . The voltage drop of the virtual resistance is subtracted from the dq - controller output voltage before being sent to the PLL and output of the inverter. The PLL uses only t he calculated inverter output voltage to synchronize; no external AC voltage measurements are used. A basic S ine - PWM (SPWM) algorithm is used for simplicity of the duty cycle calculations. The duty tioned previously. Additional details on the simulation model are provided within Appendix A . The control - system parameters of the simulation are presented in Table 2 . 5 . The dq - control was tuned so the current would be over - damped with a settling time of T stl, c = 50 ms. Meanwhile, Figure 2 . 18 : Top - level control diagram for virtual - resistance Simulink model. Table 2 . 5 : Virtual - resistance simulation control system parameters. Parameter Symbol Value dq - control Proportional Gain k p, c 0 dq - control Integral Gain k i, c 80 dq - control Derivative Gain k d, c 5×10 4 PLL Proportional Gain k 80 PLL Integral Gain k 1600 High - pass Filter Frequency f HP 1 kHz Derivative F ilter F requency f D 3 kHz Algorithm Sampling Rate T s 50 µs 69 the PLL was tuned to have a critically - damped settling time of T = 100 ms. The corresponding controller coefficients used to achieve these dynamic responses are listed in the table . The time - domain s imulation results of three different grid - disturbance cases are presented in the following figures . In each simulation output figure , the true phase - A grid voltage, v Ga , the generated phase - A inverter voltage, v Ia , and the phase - A grid current, i A , are plotted vs. time. The list below describes the grid - disturbances and their corresponding figures: Figure 2 . 19 shows results of a 5 Hz frequency step - change at t = 400 ms; Figure 2 . 20 shows results of a 10% phase - angle jump (36 - degrees) at t = 600 ms; Figure 2 . 21 shows results of a 10% magnitude drop in grid voltage at t = 800 ms. In all of the simulation cases, the regulation of the current is very good during the disturbance. This is due to the very quick response of the virtual resistance (r ecall the virtual resistance acts similar to a proportional gain). Any change in the current immediately causes a change in the Figure 2 . 19 : Simulink virtual - resistance simulation; 5 Hz frequency step change. 70 applied inverter voltage; this helps to make the control system immune to grid disturbances. Figure 2 . 20 : Simulink virtual - resistance simulation; 36 - degree phase step change. Figure 2 . 21 : Simulink virtual - resistance simulation; 10% voltage step change. 71 The phase alignment of the current during the disturbances is governed by the PLL. In the frequency - jump and phase - angle - jump simulations, the PLL realigns with the grid voltage after about 100 ms, as designed. Note that the PLL is unable to regulate the p hase - angle error in Figure 2 . 20 completely to zero. This is because of the phase - lag between the true grid voltage and the inverter connection point (which is also the sensing point) caused by Z G . This issue can be addressed by using impedance - compensation within the PLL; this is discussed in Chapter 3. In addition to simulation, an experimental test setup was con structed to validate the theory. The experimental setup consists of: a TDK - Lambda GEN 600 - 8.5 DC power supply, a SiC - based three - phase inverter, three 50A - rated 1 mH interface inductors (to simulate a non - zero grid impedance), a Staco Energy 1210B - 3 variac, and a Yokogawa DL850 isolated oscilloscope. An image of the experimental test bench is shown in Figure 2 . 22 . Here, the power supply, inverter, inductors, variac, and oscilloscope can be seen. A laptop, connected via a USB cable, was used as the man - machine interface to the inverter control software. An additional 5 V power supply was also u sed to power the inverter DSP, gate driver ICs, isolated gate - drive supplies, current sensors, and voltage sensors. Additional details on the experimental test bench and the design of Figure 2 . 22 : Experimental test bench for the virtual - resistance control algorithm. 72 the three - phase inverter are presented in Appendix B . To confirm the theory presented in this chapter, two key experiments were performed. The first experiment was a step - change in load (the d - axis current) where the controller had the same tuning parameters as the previous simulation. The values in Table 2 . 4 and Table 2 . 5 (excluding k and k ) were chosen to exactly match those of the hardware test bench for this test. The PI - controller coefficients of the PLL were revised to k = 16 and k dynamics and make T = 500 ms. These simulated and experimental results are shown below in Figure 2 . 23 . The dq - control of the current was tuned to set the settling time of the AC current to be ~50 ms (as previously mentioned). From equation ( 2.47 ) , we had: ( 2 . 49 ) The experimental results below agree very well with the simulated results and with the theory. There is a slight steady - state error in the magnitude of the experimental currents, but this is (a) (b) Figure 2 . 23 : R esults for over - damped step - change in load current: (a) simulatio n, (b) experiment . 73 believed to be simply a n ADC - sensor - gain calibration error with t he current sensors on the prototype. In both plots below, we can also see the sharp spike in the current at the moment of the step - change; this is due to the derivative - component of the PID - controllers. Again, some small value of derivative - control was req uired to ensure the stability of the system. We can also confirm that the first - order approximation of the system dynamics should still hold, based on equation ( 2.48 ) . Plugging in values gives us : 1 > 0. 16 , which satisfies the condition: ( 2 . 50 ) In the second experiment, the controller tuning and virtual - resistance value s were altered to yield a similar settling - time of the current, but produce an under - damped res ponse. Specifically, the virtual resistance and integral gain were set to the following: R V I k i ,c = 100 . As done previously, the simulated and experimental waveforms for a step - change in load (the d - axis current) are shown below in Figure 2 . 24 . Using the simplified 2 nd - order analysis, we can see that (a) (b) Figure 2 . 24 : R esults for under - damped step - change in load current: (a) simulation, (b) experiment . 74 the dynamics should be under - damped (the inequality below is false) : ( 2 . 51 ) In both Figure 2 . 23 and Figure 2 . 24 , we see that the q - axis current was not regulated to zero; some small steady - state error began to accumulate after the step - change in the d - axis current. As mentioned previously, this discrepancy is due to the actual inductance of the grid affect ing the phase angle of the terminal voltage (a phase - shift develops between the true grid voltage and the sensing - point voltage). Again, this issue can be addressed by impedance - compensating the PLL, to be discussed in the following chapter. We can also co mpare the dynamic performance of the virtual - resistance system to the simplified 2 nd - order transfer function model described by equation ( 2.43 ) . However, to make this comparison fair, we must be mindful of any nonlinearities present in the real system. The PI - controllers are usually implemented to include saturation blocks; this helps to prevent integrator - wind - up and can help reduce transient curr ent spikes by limiting the output voltage of the PI - controllers. However, t he transfer function listed in ( 2.43 ) does not contain any saturation of i ts internal states. To get around the saturation issue, we can instead look at a rate - limited step - response of both systems. A comparison between the full PWM - based simulation model and the simplified 2 nd - order transfer function model is provided in Figure 2 . 25 , where the true step - response is shown in ( a) and the rate - limited step - response is shown in (b). The rate of the reference current was limited to ±1000 A/s in th e second case. We can see from Figure 2 . 25 (a) that applying a true step - input causes a large discrepancy between the realistic and simplified simulations. This is bec ause of the derivative - term in the PID - controller. The unsaturated output from the PID - controller would normally be very large in 75 this case, causing a swift jump in the current. Due to the saturations added to the realistic PWM - based model, the voltage out put of the PID - controller is limited to only ± 25 V, causing the output current to only slightly rise before the transient response begins. This phenomenon can also be seen in the previous simulated and experimental results, shown in Figure 2 . 24 . In the rate - limited step - response simulation, shown in Figure 2 . 25 (b), the two responses are practically identical. The saturation blocks do not take effect in this case, since the slope of the error signal multiplied by the k d,c value is still quite small (recall that typical k d,c values should be roughly less than the magnitude of the grid inductance, L G , which was around 10 4 ). Thus, we can conclude that the 2 nd - order model can provide a reasonable estimate of the response dynamics in the case of low ramp - rate transient conditions. 2.7. CHAPTER 2 S UMMARY To conclude, virtual impedances are a useful mathematical tool to help synchronize a DC/AC power electronics converter to an AC grid. Using approximated derivatives, virtual - inductances can be used to emulate the behavior of interfacing inductors. If adequate grid - filtering is available , a virtual interfacing - impedance can be used to fully replace a physical interface impedance, simplifying the physical system and reducing the cost, size, weight, and power loss. (a) (b) Figure 2 . 25 : Comparison between full PWM - based simulation & simplified 2 nd - order transfer function when driven by: (a) a pure step - input, (b) a 1000 A/s ramped step - input. 76 AC voltage sensors can also be removed from the system, being replaced by virtua l voltage - sensing - points. This can further reduce system costs and complexity. Any range of virtual impedances or transfer functions may be selected to generate a virtual voltage - sensing - point. However, the most advantageous is the use of simply a virtual resistance. The computation of the virtual - resistor voltage - drops and the regulation of the dq - frame currents can be greatly simplified in this case, resulting in roughly 8.5 % less computational load than the original system. Simulation and experimental re sults of a virtual - resistance self - synchronizing inverter system confirm the functionality of the algorithm and its tolerance to grid disturbances. It should be noted that all of the virtual impedance topics presented here were applied to the inverter outp ut voltage, without altering the voltage - synchronization point seen by the PLL . The purpose of this is to affect the perceived interfacing impedance b etween the inverter and voltage - sensing point . Even with the removal of the real interfacing impedance, th e PLL sens ing - voltage was still placed at the grid terminals , v S . In the next chapter, we will explore some benefits of applying virtual impedances to influence the voltage - synchronization point ; the purpose is to affect the total impedance between the sen sing point and Thévenin - equivalent voltage source of the grid . This can impact the stability and dynamic performance of the PLL and converter, as we wi ll soon see. 77 3. APPLYING VIRTUAL IMPEDANCE AT THE SYNCHRONIZATION POINT In this chapter, some additional u ses and benefits of implementing virtual impedances within DC/AC converter control algorithms are presented. First, the impedance - compensat ion of a PLL algorithm is discussed. This can be used to cancel out the phase - angle difference between the measurement point and the AC source, allowing for unity - power - factor at the source. A novel method is proposed and is compared with an alternate method which uses only a partially - virtualized impedance. Next, a more general approach to estimate the quasi - static stability of the SRF - PLL algorithm in a DC/AC converter system using virtual impedances is proposed . This is followed by a thorough analysis of the small - signal stability using locally linearized models. Finally, the impedance - compensated PLL algorithm , together with the virtual - resistance - based inductor - less self - synchronizing algorithm, is examined and proposed as an alternate means for implementing position - sensor - less Back - EMF - based permanent magnet (PM) motor control. 3.1. IMPED ANCE - COMPENSATED PHASE - LOCKED LOOPS The topics presented here in this chapter differ from those in Chapter 2 by the location in which a virtual - impedance is applied within the system . As shown in Figure 3 . 1 , we can apply a virtual impedance voltage either to the inverter output voltage or to the PLL input voltage. In (a) (b) Figure 3 . 1 : Addition or subtraction of virtual voltages from: (a) the inverter voltage; (b) the voltage sensing point. 78 Figure 3 . 1 (a), a virtual impedance applied to the inverter output voltage, denoted Z VI , can shift the apparent connection point of the inverter to the grid (as seen by the controller). However, in (b), we can apply a virtual impedance to the vol tage - sensing point, denoted Z VS , which can shift the apparent measurement point of the PLL to be closer or further from the true grid voltage. S hifting the apparent measurement point can be thought of as equivalent ly add ing or cancel ling out grid - side impedances. As discussed previously , along with equation ( 1.21 ) , when the line current s are near zero, the PLL will synchronize to the true grid angle ; the relative angle between the PLL frame and grid - frame, , will be small . However, at heavy loading conditions, the larger voltage drop across the grid impedance will introduce a larger phase shift at the PLL measu rement point. This is illustrated in Figure 3 . 2 below ( only inductive line impedances are considered) . By applying virtual impedances at the measurement point, we can cancel out some of the voltage drop produced by the grid impedance, effectively reducing the steady - state angle - error between the PLL and the true grid angle. This can make the PLL appear to be connected to a stiffer point in the grid, moving it closer to the true Thévenin - equivalent grid voltage. In addition, this impedance cancellation (or compensation) can also alter performance. (a) (b) (c) Figure 3 . 2 : Space - vector diagram of system voltage s and current (ignoring resistance) at: (a) light load; (b) load - increase transient scenario; and ( c ) heavy load. 79 To implement virtual impedances at the voltage sensing point requires modifying the PLL input voltage using impedance voltage - drop s within the control software . Note that this impedance - voltage - drop can be either added or subtracted and this can be done in either the stationary - frame (fully virtualized) or the rotating - frame ( usually partially virtualized). To d o v S , can be augmented to become v S ' by adding (or subtracting) the voltage - drop across a virtual impedance, Z V S ( 3 . 1 ) A block diagram illustrating the application of virtual i in the dq - frame is shown in Figure 3 . 3 below . This approach was previously proposed by J. Suul, et al. in [ 19 ] , using only partially implemented virtual impedances. In [ 19 ] th e voltage s of a virtual resistance and partial virtual Figure 3 . 3 : Inverter control block diagram utilizing rotating - frame virtual impedance at the voltage - sensing point. 80 inductance were subtracted to move the PLL voltage closer to the true grid voltage, v G . This is expressed by the following equation: ( 3 . 2 ) However, there are two main drawbacks with this approach. First, the virtual inductor voltage is not fully implemented . A s described in Chapter 2 with equation ( 2.3 ) , virtual inductors implemented in the dq - frame usually only include the steady - state voltage - drop term. The derivative term is ignored. This means that if the outer control loop of the inverter controller ch anges the dq - current reference values (and thus changing the actual currents), the PLL will experience a transient disturbance in its synchronization angle, until the currents again stabilize. Second, the implementation of the steady - state inductor voltage - drop relies on the estimated frequency of the PLL, . This not only makes analysis of the dynamics more challenging, but also means that the compensation of impedance voltages during a transient event may be slightly stimate stabilizes. Figure 3 . 4 : Inverter control block diagram utilizing stationary - frame virtual impedance at the voltage - sensing point. 81 A proposed alternative is to impedance - compensate the PLL in the sta tionary - frame, using the high - pass filter method described in Chapter 2. The control system block diagram for this method is shown below in Figure 3 . 4 . With this method, the inductor voltages are fully implemented and the calculation of these inductor voltages does not rely on any inputs from the PLL, effectively decoupling the two. As a means of comparing these two approaches, a time - domain simulation was performed in MATLAB Simulink , using similar parameters to those presented in Table 2 . 4 . The results are shown in Figure 3 . 5 . To emphasize the effects in a weak - grid connection , the grid inductance, L G , was increased from 10% pu to 80 % pu. In Figure 3 . 5 (a) and (b), the simulation results using no impe dance compensation (no comp), 5 0% dq - frame compensa tion (dq comp), and 5 0% abc - Figure 3 . 5 : Simulink simulation comparison of impedance compensation methods . 82 frame compensation (abc comp) are shown. Figure 3 . 5 (a) shows the q - axis voltag e as sensed by the PLL and Figure 3 . 5 (b) shows the PLL angle error from the true grid angle. The axis of the applied current also influences the performance of the tw o different impedance compensation methods. For this reason, the values of the dq - currents vs. time are also shown i n Figure 3 . 5 (c). Any injected current which causes a significant change in the q - axis voltage will more strongly affect the PLL, causing a transient in the estimation angle. For this reason, the current applied in the simulation is all reactive, in the q - axis. Thus, roughly 20 kVAR of reactive power is compensation methods, a high ramp rate of the current was used; the current references in the simulation varied by 2000 A/s. T his will cause the derivative term of the inductor voltage to be more significant, which only the proposed compensation method can address. As shown in the figure , both the dq - frame and abc - frame impedance compensation methods are effective at eliminating some of the steady - state angle error. With no compensation, the steady - state angle error is roughly 3 degrees at full load . Both compensation methods reduce this by 50% and have a steady - state angle error of about 1.5 degrees . However, during the transi ent periods of the current, the abc - frame compensation method is affected less . We see a strong transient in the sensed q - axis voltage (roughly 10 V) in the uncompensated and dq - frame - compensated systems. The proposed abc - frame - compensated system has a smalle r voltage spike and smaller angle - shifts during the ramps in current. 3.2. QUASI - STATIC STABILITY RANGE OF SRF - PL L FOR WEAK GRIDS Here, we revisit the analysis of the basic SRF - PLL, presented in Chapter 1. The typical assumption is that the grid impedance, Z G , will not affect the control of the dq - currents, so long as the inverter voltage is controlled to satisfy the KVL expression ( 1.22 ) , restated here: 83 ( 1.22 ) Restated another way, we can say that if the inverter voltage , v I , and current, i , are controlled properly and the interface impedance , Z I , is known, then the voltage difference between the inverter voltage and sensing - point voltage , v S , will also be known. The grid impedance , Z G , will not influence the voltage between inverter and sensors. It is the job of the dq - controllers to regulate the current and in the process, regulate this voltage difference. In this section, we now consider the interaction between the sensing voltage, v S , the grid impedance, Z G , and grid voltage, v G . Applying KVL in the other direction, we can express the sensing point voltage in terms of the grid voltage and grid impedance, as shown below: ( 3 . 3 ) The PLL, which is driven by the sensing voltage, v S , is trying to lock to the grid voltage, v G . However, the grid impedance , Z G , can influence t he sensing voltage; t ability to synchronize, as we ll soon see. Following a similar analysis proposed by D. Dong et al. in [ 22 ], we can modify the basic SRF - PLL control model (shown previously in Figure 1 . 5 ) to accommodate the additional voltage of the grid impedance, Z G , which augments the sensing voltage. This is shown in Figure 3 . 6 below; note that here we assume the current references, i dq * , to be approximately equal to the real currents, i dq . Th is assumption should be safe, since the Figure 3 . 6 : Nonlinear SRF - PLL control - system model showing the grid - impedance interaction. 84 dynamics of the current are usually much faster than the PLL control loop. This also means that it is the magnitude, phase, and frequency of the current (the latter of which is derived from the PLL) which influences Z G i impedance - voltage - drop term this will be important soon. simplify the previous model. Beforehand, we will first define some of the space - vector componen ts; we will represent the grid voltage in a stationary - frame space - vector form as: ( 3 . 4 ) where V G m is the grid voltage peak - magnitude and G represent the grid current in a stationary - frame space - vector form, defined as: ( 3 . 5 ) where I m is the grid current peak - magnitude, is the estimated angle from the PLL, and i is the relative angle of the current, with respect to the PLL angle . The parameters of the current can also be described as follows: where ( 3 . 6 ) Lastly, we also need to define the magnitude and phase angle of the impedance: where ( 3 . 7 ) Now, i f we a pply the Clarke/Park transforms to the sensing voltage, v S , and examine the expression for the q - axis voltage (which is used to obtain the angle - error), ( 3 . 8 ) and then substitute the sensing voltage with equation ( 3.3 ) , we will obtain the following: 85 ( 3 . 9 ) where the voltage v Z G is the voltage drop on the grid impedance. After some simplification of the Park transform , the resulting q - axis voltage can be expressed as: ( 3 . 10 ) Note that the time - varying components of the second terms (involving v Z G ) cancel, since both the current and the Park transform rotate with the same angle, ; only the constant phase - shift terms remain. From equation ( 3.10 ) , we can develop a new quasi - static PLL model , shown below in Figure 3 . 7 , which includes the grid - impe dance interaction. From this model, we can see that there are two feedback loops which influence the PI - controller of the PLL. Following from [ 22 ], t he top loop, in blue, is the traditional negative feedback loop used to synchronize to the true grid angle , G , which generates a q - axis voltage labeled as v S q . Meanwhile, the bottom loop, in red, is a positive feedback loop which aims to desynchronize the PLL from the grid and synchronize to the inverter voltage, which generates a q - axis voltage labeled v S q+ . The influence of the self - synchronization loop is de termined by I m , Figure 3 . 7 : Qu a si - static SRF - PLL control system including the grid - impedance interaction. 86 i , | Z G |, and Z G . A higher injection current, larger grid impedance (a weaker grid), and a larger combined current and impedance angle (larger i + Z G ) give a stronger self - synchronization feedback effect. The sign of the self - synchroniza tion voltage, v S q+ , is determined by both the power - flow direction ( related to i Z G ). One proposed change to the analysis shown here from [ 22 ] is the inclusion of i ; this allows us to consider the dq - operating points , providing a more generalized view . Due to the pure integrator within the PI - controller, the PLL will always try to drive the total q - axis voltage to zero, v Sq = 0. At any loaded operating point, t he self - synchronization loop will generate a constant voltage which the grid - synchronization loop must counteract. This means that a fi nite angle error, ( G ) = , must exist to have some non - zero v Sq to cancel out the disturbance of v Sq + . With the trigonometric sine function in both loop paths (a residual of the Park transform), the grid - synchronization voltage, v Sq , is limited by the grid voltage magnitude: ( 3 . 11 ) When the disturbance, v Sq + , is larger than the maximum output of v Sq , no steady - state equilibrium point, ( G ), can be found to ensure v Sq = 0. Therefore, the large - signal stability requirement for the PLL in a weak - grid condition can be expressed as the following: ( 3 . 12 ) The result of equation ( 3.12 ) shows that a larger grid voltage, a lower grid current magnitude, a smaller grid impedance magnitude, and a smaller net sum of grid - current and grid - impedance angles will result in a more stable operation of the PLL. An existing method, discussed in [ 19 ], - static stability in a weak - v S , by subtracting a virtual - impedance voltage 87 to counteract the grid impedance, Z G . By virtually shifting sensing - point voltage closer to the true Thévenin - equivalent voltage of the grid, the PLL will behave as if it is connected to a more stiff - grid. This technique was discussed in the previous section, and agrees with the analysis above. However, the proposed alteration to this technique is to consider alternate combinations of virtual impedances to further enhance the stability in certain operating cases. In the cases of connecting active loads and sources to the grid , such as electric vehicle (EV) battery chargers and photo - voltaic (PV) installations, only the grid - voltage magnitude, V G m , the gr id impedance, Z G , and the real power flow from the converter may be fixed values. In this simple scenario, the only other control variable may be the reactive power generation, which in turn affects the angle of the current, i . The valid range of operatin g points can be found by simultaneously solving the system of nonlinear equations below, which represent the power balance between the inverter, grid impedance, and the Thévenin grid voltage , given as: ( 3 . 13 ) where R G and X G are the resistance and reactance of the grid, respectively, P I and Q I are the real and reactive output power of the inverter, respectively, V G is the grid voltage, and I is the line current. The grid voltag e is usually assumed to have a magnitude of 1 pu and a phase angle of 0 ° . The interfacing impedance is usually much smaller than the grid impedance in a weak - grid scenario and will be ignored here ( Z I could be considered to be lumped into Z G ) . As a simple example, we can consider the case where the reactive power of the inverter is set to also be 0 VAR. If we also assume the grid impedance is highly inductive (assuming a phase angle of 80°), we can generate the plot shown in Figure 3 . 8 (a) on the next page. From this plot, we can see the range of possible operating points of the converter. The dark shaded areas 88 indicate operating conditions which do not have a numerical solution to the power - balance equations. The lightly shaded areas are operating points which fail the quasi - static stability requirements. The white regions represent operating conditions where a valid power solution is found, and the operatin g point is stable according to equation ( 3.12 ) . We can see in Figure 3 . 8 (a) that with a highly inductive grid impedance, the power transfer capability cannot exceed roughly P I = 1 pu with a grid impedance | Z G | > 0.6 pu in the inverter - case. For the rectifier - case , the limit of P I = 1 pu is reached around | Z G | > 0.45 pu . If we now relax these requirements by allowing the converter to generate reactive power, we can observe that more valid operating points exist, which stil l satisfy the power balance equations. The new system of equations used ensures the real power is balanced and the voltage magnitude at the sensing side (or inverter side) is controlled to a magnitude of 1 .15 pu (avoiding over - modulation under Space - Vector PWM ) . T he system of equations in ( 3.13 ) is revised to : (a) (b) Figure 3 . 8 : Quasi - s tability & power transfer capability for DC/AC converter vs. grid impedance with: (a) no reactive power generation; (b) sensing voltage magnitude regulation via reactive power . 89 ( 3 . 14 ) The resul ting stable points of the relaxed system are shown in Figure 3 . 8 (b); from here, we can clearly see that the valid operating ranges of the converter increase by allowing reactive power. To obtain an even more generalized view, we can hold the magnitude of the grid impedance constant and simply sweep the real and reactive power values, P I and Q I . We will revert back to equation set ( 3.13 ) for defining valid operating conditions. Figure 3 . 9 below shows the results of sweeping real and reactive power operating with a grid impedance magnitude of | Z G | = 0.8 pu and a grid impedance angle of Z G = 80 degrees. The range of possible operating points maps PQ - pl ane. We can see in the figure that, of this range of possible operating points, the quasi - static stability analysis shows that there are some operating points where the PLL will be unable to synchronize to the grid voltage. In Figure 3 . 9 (a), no impedance compensation is applied. However, in Figure 3 . 9 (b), a (0.5 + j 0) pu resistive c ompensation is applied. The compensation allows us to shift the range of quasi - stable operating (a) (b) Figure 3 . 9 : Quasi - stability vs. power transfer capability for weak - grid connection : (a) no compensation, (b) 0.5 pu resistive compensation . 90 points so that different operating conditions can be achieved. As mentioned previously, the compensation impedance, Z VS , need not cancel out the grid impedance entirely. By simply shifting the total phase or total magnitude of ( Z G Z VS ), we can alter the range of quasi - stable operating points. By applying virtual impedances at the sensing - point, equation ( 3.12 ) will effectively change to: ( 3 . 15 ) Thus, a change in the combined phase angle or combined magnitude may be all th at is needed to enhance the quasi - stability of a particular operating range. Also note from the equation above, that if we select Z VS = Z G , the PLL will be perfectly compensated to synchronize to the true grid voltage and all of the valid operating points will become quasi - stable. 3.3. IMPEDANCE - COMPENSATED SYSTEM S TABILITY ANALYSIS The quasi - stability analysis in the previous section provides a rough estimate of which operating points may be possible when running a DC/AC inverter system. However, the previous a nalysis does not take into account any small - signal behavior of the system. Furthermore, much of the control system has been omitted. The resulting quasi - static stability equations also do not dq - D coefficients! To assess the small - signal stability of the control algorithm, a complete dynamic system model can be developed, as was done in Chapters 1 and 2 previously. In this section, we will develop the necessary system of 1 st - order differential equ ations to model an inverter system using and impedance - compensated PLL. We will again start with the model presented in Chapter 1 and modify it to match the present control system. First, we will incorporate the single - cycle delays into the model. Assuming that a phy sical interfacing - impedance, Z I , is still used, we will now have three delays within the control 91 system: two ADC delays for the sampling of v S and i , and one PWM delay for outputting v I . Building off of Chapter 2, we can introduce a new space - ve ctor variable, , to represent the low - pass filtered sensing - point voltages. Applying the delay in the xy - frame gives the following: ( 3 . 16 ) Splitting the above equation into real and imaginary parts gives us ( 3 . 17 ) The remainder of the dynamics will actually be very similar to the model developed in Chapter 2, with a few exceptions. The use of a physical interface - inductor, Z I , means that the current control loops can revert back to using a simpler PI - controller. Thi s will eliminate two state variables from the system. The overall system dynamics will still be 14 th - order however, due to the addition of the two differential equations above. Furthermore, we will need to redefine the inverter output voltage and the PLL e rror - input signal to be in terms of the augmented sensing - point voltage, v S ' , rather than v S . - vector quantities, , to model the PWM delays. A summary of the modeling equations is provided below, st arting with the coordinate - frame transformation equations: ( 3 . 18 ) 92 On the following page, the set of differential equations used to describe the system dynamics is provided. The two equations above in ( 3.17 ) are list ed as equations (9) and (10 ) in the set: ( 3 . 19 ) Note that equation (14) in the set has been modified to use the augmented sensing - point voltage, v S ' . To be consistent with the previous chapters, equation (14) in the set is still normalized by dividing out the magnitude of the sensing - point voltage. However, in the analysis presented in 93 the previous section, following D. Dong et al. in [ 22 ], simply uses the q - axis voltage as the angle - error signal. This will introduce a gain in the PI - controller coefficients of the PLL proportional to the magnitude of the sensed voltage. To cancel out this gain and make the analysis follow that of the previous section, equation (14) of the previous set could be revised to the following: ( 3 . 20 ) where k v is simply a constant equal to the nominal magnitude of the grid voltage (~170 V). Since this redefines the angle - error signal, equation (13) of the set will also be affected. In addition to the set of differential equations, we also can describe the remain ing algebraic equations which relate the other various quantities in the control system ; t hese are listed below . As mentioned above, the augmented sensing - point voltage also has an effect on v I , but this is shown in the calculation of the inverter voltage s, which are equations (7) and (8) in the set: ( 3 . 21 ) Note that, in the dq - frame inverter voltage calculations, the sum of virtual sensing - point impedance and interface impedance should be used for decoupling the currents. This is due to the fact that, by impedance - compensating the PLL, the impedance voltage - drops that were removed 94 (subtracted) Thus, by decrea sing the effective Z G , we increase the total effective Z I . This is summarized in the following equations. The use of virtual interface - impedance does not affect the sensing - point - to - grid impedance, but altering the sensing point using a virtual - sensing - imp edance does affect the interface - impedance. We can define the effective interface impedance, Z I,eff , and effective sensing - point - to - grid impedance, Z G , eff , as follows: ( 3 . 22 ) Another item worth noting is the reoccurrence of the voltage - divider equations for calculating the xy - frame sensing - point voltages, equations (9) and (10) in the set ( 3.21 ) . These return since we have a physical interfacing impedance once again. To help the reader grasp the different delays and space - vector relationships in this control system model, a MATLAB vector plot has been produced for a system running with some (a) (b) Figure 3 . 10 : Space - vector plot of voltages & currents in the IC - PLL algorithm in: (a) the xy - frame, (b) the dq - frame. 95 positive d - axis current reference and a zero q - axis reference (i.e. i d * > 0 and i q * = 0). This is shown in Figure 3 . 10 below. The impedance voltage - drops are also shown, as well as some of the low - pass filter variab les , and some other vectors which have not been previously defined . 3.4. ENHANCEMENT OF STABILITY USING IMPE DANCE - COMPENSATION With the dynamic system model developed in the previous section, a computer - aided stability analysis was performed on the impedance - c ompensated PLL. To relate the results back to Section 3.2 (and the work in [ 22 ]) , the PLL error signal, , was defined to be simply v Sq ' / k v , as described previously in equation ( 3.20 ) . The value of the constant was set to be k v = 17 (providing a gain of ~10x to the PI - controller coefficients). The Jacobian matrix was formed from the equation set ( 3 . 19 ) and was computed symbolically using MATLAB. The Jacobian was then evaluated at many operating points, corresponding to the P I and Q I values presented previously in Figure 3 . 9 . At each operating point, the eigenvalues of the Jacobian were found numerically and the eigenvalue with the largest real - part was checked for stability (to see if it was greater or le ss than zero) . The plot in Figure 3 . 9 was regenerated with the small - signal stability information being added to the plot , based on the localized stability analysis. The results corresponding to the case Figure 3 . 11 : Small - signal stability vs. power transfer capability without impedance compensation. 96 in Figure 3 . 9 (a), without any impedance comp ensation, are presented here in Figure 3 . 11 . From the results in Figure 3 . 11 , we can see that the quasi - static stability developed with in Section 3.2 actual stable operating capability of the inverter. When taking into consideration the dynamics of the current controllers, the PLL, and the time - delays introduced in the digital system implementation, the range of stable operating points is actually only a small subset of the range predicted by the quasi - static stability analysis. To see the benefits of impedance - compensation, w e can re - run the computational model used to generate Figure 3 . 11 , this time with some amount of compensation applied . This is shown below in Figure 3 . 12 . Here, the value of Z VS is set to ¼ of the grid impedance, Z G . We can see that, not only does the quasi - static stability range increase (as expected), but the predicted small - signal stability range has also been enlarged! Thus, we have shown that the use of impedance - compensation can improve the stability of a converter, by allowing the conver ter to synchronize to a more - stable point within the electrical system. Note that other parameters will also obviously affect the stability. The tunings of the PI - controllers and the selection of the high - pass filter frequencies for the derivative - approxi mations will also affect the range of small - signal stability. Figure 3 . 12 : Small - signal stability vs. power transfer capability with 25% impedance compensation. 97 3.5. SENSOR - LESS PMAC MOTOR TERMINAL - VOLTAGE SYNCHRONIZAT ION One additional application of virtual - impedances within DC/AC converters is in the control of three - phase AC machines. We have shown previ ously in Chapter 2 that self - synchronization of a converter to its own terminal voltage (while still regulating current) is possible. However, because the self - synchronizing algorithm aligns the PLL to the d - axis of the terminal voltage, some phase - angle e rror will exist between the terminal voltage and the Thévenin - equivalent voltage of the AC source. This has been discussed in the previous sections of this chapter. However, if we combine this self - synchronizing algorithm together with the impedance - compen sation method to shift the PLL angle to the true Thévenin - equivalent - voltage angle, we can control the current from the reference - frame of the Thévenin AC source, using only the terminal voltage and current sensor information! This is the main objective in many back - EMF - based sensor - less motor control algorithms for permanent - magnet AC machines [ 23 ]. Figure 3 . 13 : Pr oposed sensor - less PMAC control block diagram utilizing virtual impedance compensations. 98 A block diagram of the proposed control algorithm is shown in Figure 3 . 13 . To be consistent, we will use the same variable - names as before. In this case, the grid voltage, v G , represents the back - EMF of the machine due to the time - varying flux linkages. The impedances R G and L G represent the motor winding resistance and inductance, respectively. To completely cancel out the motor impedance and synchronize the PLL at the back - EMF voltage point, a virtual impedance, Z VS , can be subtracted from the sensing voltage. Note that the unadjusted sensing voltage , v S , in this case is the same , v I ' , as in Chapter 2 : ( 3 . 23 ) where we could select R VS = R G and L VS = L G . To implement this, the winding impedance must be known. The winding impedances do vary with temperature and loading conditions, but are generally more predictable than the parasitic impedance of the grid. Even with some small errors in parameter values, th e application of equation ( 3.23 ) true angle of the back - EMF. Subtracting a virtual - the PLL does not eliminate the impedance from the virtual system ; it simply gets shifted to the other side of the measurement point. In other words, the act of impedance - compensating the PLL effectively puts the sensing - virtual - impedance, Z VS , between the perceived sensing point and the inverter output, makin g it appear like an interfacing - impedance. Therefore, the impedance - compensation of the PLL is really all that is r equired to apply an interfacing - impedance to the system for the inner dq - current loop t o respond to. This alteration alone will work for sensor - less control of a PM machine. However, if a different interfacing - impedance , other than Z VS , is desired, we can further alter the control system to adjust the computed inverter output voltage, v I , as previously shown in Figure 3 . 13 . For example, if we wish to use only an interfacing resistor between the voltage 99 sensing point and inverter output, we can augment the inverter output voltage computed by the dq - current controllers, v I , by subtracting the desired interfacing - impedance voltages and adding the undesired interfacing - impedance voltages. This can be used to effectively cancel out the Z VS impedance from the interfacing location and replace it with another impedance, Z VI . As an example, the cancellation of the motor winding impedance, Z G , and addition of a virtual interfacing resistance, R V I , can be performed . With this approach, the same simplifications to the dq - current control algorithm can be made, reducing some of the computational complexity of the control loop. This example is shown mathematically below: ( 3 . 24 ) where again, we could set R VS = R G and L VS = L G . With this second modification to the control system, the effects of the Z VS impedance (and the Z G impedance) will be completely removed. To help visualize the changes, we can follow the progression of applying equations ( 3.23 ) and ( 3.24 ) as illustrated in Figure 3 . 14 . In Figure 3 . 14 (a), we have the original system. The sensing voltage is located at the inverter terminals. In Figure 3 . 14 (b), the sensing voltage is moved to the Thévenin - equivalent voltage of the machine by impedance - compensating the PLL. Note that this places the winding impedance, Z G , between the inverter an d measurement point, making it beha ve as if it were an interfacing - impedance. Lastly, in Figure 3 . 14 (c), the winding impedance is cancelled out from the inverter vol tage and a virtual interfacing resistance, R V I , is added, effectively placing it between the inverter and voltage sensing point. Note that if the last step is omitted, the traditional dq - current control algorithm with decoupling terms can be used. In the c ase of parameter variation or estimation error, the virtualized sens ing - point voltage will not be equal to the true back - EMF voltage; some steady - state angle error will remain. However, this can be observed during a change in the operating point. If the mo tor impedance is 100 not properly canceled out, a ny change in the operating - point will cause a slight change in the , causing the PLL to realign itself. This is the same phenomenon described in S ection 3.1 previously. These PLL error adjustments can be used to identify/update the estimated motor parameters to perfectly align the sensing point with the back - EMF of the machine. To generate this PLL re - alignment signal, we can inject a time - varying current reference into the d - axis. (To follow convention, n ote that the PLL should be modified to eliminate d - axis voltage and align to the q - axis . ) This injection current does not need to be high - frequency; it simply needs to be somewhat faster than the response time of the PLL (otherwise, the PLL will realign and the error signal will vanish). Alternatively, the PLL could be temporarily detuned durin g the injection phase and then retuned for normal operation. If either the resistance estimate, , is incorrect or if the inductance estimate, , is incorrect , the low - frequency injection current will cause a non - zero low - frequency voltage to appear in one or both of the machine axes . The Figure 3 . 14 : Mathematical progression of proposed sensor - less PMAC control, showing: (a) the original control system; (b) the impedance - compensated system for observing the back - EMF; (c) the resulting control system w ith virtual interfacing resistance. 101 polarities of these voltages will change if the impedances have been over - compensated. From the observed voltages, the machine parameter estimates can be adjusted until the PLL is perfectly compensated and the angle - - parameter estimation algorithm will be left as a future work. 3.6. CHAPTER 3 S UMMARY In this chapter, we have outlined the theory of impedance - compensation for phase - locked loops within DC/AC converter systems. Using virtual - impedance - compensation, the effective measurement point of the PLL can be moved to another location in the circuit. This can alter the dynamics and steady - st ate synchronization of the PLL. A proposed stationary - frame compensation method was introduced and shown to have better transient performance than the traditional rotating - frame compensation. This is due to using a fully implemented inductor voltage - drop, rat her than only a partial implementation. Furthermore, an analysis on the quasi - static stability of the PLL, considering the grid impedance, was also given. The proposed analysis was slightly modified from an existing analysis to incorporate the phase angle of the line current. This was examined together with the power transfer capabilities of a DC/AC converter system con nected in a weak - grid scenario. Next, a full dynamic - system model was developed for the impedance - compensated converter system. The circuit dynamics, current - controller dynamics, PLL dynamics, and digital sampling delays were incorporated into the model. From the dynamic system model, the localized linear stability of the system could be assessed. Using MATLAB, the local stability at several d ifferent operating points were be obtained and plotted against the quasi - static stability ranges. From this model, it was shown that impedance - compensation of the PLL system can enhance the small - signal stability range of the overall converter system. 102 Last ly, an alternate method for sensor - less control of permanent magnet AC machines was presented, using the concept of virtual - impedance - compensation together with a virtual interfacing - impedance . This was introduced as a possible alternative to the typical B ack - EMF observer method for position - sensor - less control of PMAC motors. The virtual - impedance - based method could be potentially much simpler mathematically than the observer - based system. In the last chapter, the conclusions of this report are summarized . Afterwards, proposed future research works are outlined. 103 4. CONCLUSIONS A ND FUTURE WORK In this chapter, the recommendations to extend this work. A method to truly test the inductor - less self - synchronization method with a direct - connection to the grid is first discussed. Afterwards, a means of testing the combined impedance - compensated PLL algorithm and virtual - resistance - based inductor - less self - sy nchronizing algorithm is examined and proposed as a future work. 4.1. C ONCLUSIONS In this report, some common and some novel approaches for the synchronization and current - regulation algorithms used within DC/AC power - electronics converters have been discussed. While the primary focus of this work was on grid - connected systems, the extension to electric motor drive systems is also briefly mentioned. In the following paragraphs, a summary of the work and contributions provided in each chapter are outlin ed. Chapter 1 provided some background on DC/AC converters and discussed the typical synchronization and current - control strategy used in three - phase DC/AC converters . This overview was followed w and contributions . In Chapte r 2, the concept of virtual impedance was first reviewed. Afterwards, a novel control strategy was interfacing inductors can be replaced by virtualized ones. In addition, it was s hown that this control algorithm could be modified to allow the physical AC voltage sensors to be eliminated. Finally, some novel alterations to the previous control algorithm were proposed to utilize a virtual resistance as the interfacing impedance. With the use of a virtual interface - resistance, many parts of the dq - current control algorithm could be simplified, reducing the computational 104 complexity of the overall control system. The dynamics of the proposed control system were confirmed using simulated and experimental results. In Chapter 3, the concept of altering the synchronization voltage using virtual impedances, - was first discussed. Next, a proposed method of impedance - compensating an SRF - PLL in the stationa ry - frame was shown to have better transient performance as compared to an existing method of partial impedance - compensation in the synchronous - frame. Afterwards, the large - signal stability of SRF - PLL - controlled inverter systems used in weak - grid applicatio ns was reviewed . The analysis was further generalized by the proposed inclusion of the grid current angle . Afterwards, a thorough linearized stability analysis was then conducted to show how impedance compensation can be used to improve the small - signal st ability of the PLL and control system . Finally, the concept of using a virtual interfacing - impedance and an impedance - compensated PLL were proposed as a novel control strategy for the back - EMF - based position - sensor - less control of permanent - magnet AC machi nes at high speeds. 4.2. FUTURE WORK As a continuation of the work presented here, the author recommends the following tasks as a me ans to further validate and extend these research contributions: 1. Construct a cascaded multi - level inverter (CMI) system to reduce the PWM voltage harmonics generated by the inverter system. With very low harmonics, a direct inverter - to - grid connection could be made without any interfacing inductance, and the self - synchronization algorithm could be further tested and verified. 2. Experimentally test the combined virtual - impedance + impedance - compensated PLL algorithm, proposed in Chapter 3, for the sensor - less control of a PM machine at high 1 05 speed. This experiment will provide some confirmation on the ability to cancel out a s winding impedance and obtain the correct phase angle of the back - EMF. If proven successful, this could be used as a simpler alternative to the commonly - used back - EMF observer method, which is mathematically more intensive. Regarding the development of a cascaded multi - level inverter system (task #1), the CMI topology, which was briefly mentioned in Chapter 1 , could be used . To operate on a typical 208 V three - phase AC grid, a four - stage nine - level CMI, as shown in Figure 1 . 11 , could be constructed. Each module could be powered by isolated 50 V, 1 kW bi - directional DC - DC converters. In a Y - connected configuration, the same line - to - neutral voltage magnitude, ±200 V, cou ld be generated as compared to a traditional 400 VDC two - level inverter. However, the reduced size of the voltag e - steps and the use of unipolar PWM in the CMI (as opposed to bipolar PWM of the two - level inverter) will reduce the voltage ripple by a factor of 8x! Together w ith the use of a high switching - frequency (e.g. 50 kHz), an interfacing inductance of 200 / 8 = 25 µH would be sufficient to maintain a reasonable amount of ripple current. This estimate is based on a previously designed two - level 400 V, 1 0 kW, 50 kHz inverter using 200 µH inductors [ 24 ]. For the experimental testing of the sensor - less motor control algorithm (task # 2 ) , an existing 48 V PMAC motor/ dynamometer test bench, located at Kettering University, could be used. A photo of the test bench is provided in Figure 4 . 1 . The motors used in the setup are both Motenergy ME1117 4 - kW three - phase 8 - pole axial - flux PM machines. They are equipped with analog sin/cos position sensors; the sensors can be used to compare the estimated angle in the control algorithm with t he true angle of the back - EMF waveform. The dynamometer is equipped with a Transcell TSA50 50 - lb load cell to measure the torque difference between the two motors (one motor is gimbal - mounted) and a rotating mass is mounted to the intermediate shaft to 106 pro vide some mechanical inertia. To drive the motors, some existing 48 V inverter hardware at Kettering University can be utilized. These inverters also utilize the same F28069 TI DSP used in the experimental setup that was developed and used in Chapter 2 , so much of the software written in other tasks can be reused. Figure 4 . 1 : Low - voltage PMAC dynamometer test bench at Kettering University. 107 APPENDICES 108 APPENDIX A : MATLAB SIMULINK SI MULATION MODE LS In Chapter 2, a MATLAB Simulink model of a virtual - resistance control algorithm was presented and used to compare its results with experimental data. In this appendix, additional details and information will be given regarding this simulation model. The s imulation uses the Simscape library package of MATLAB Simulink to model the DC voltage source, two - level MOSFET inverter, grid impedances, and grid AC voltage sources. The top - level diagram showing the Simscape blocks in the simulation is shown below in Figure A . 1 . The top - level components are simulated at the fastest sampling rate (smallest sampling time) , usually 1 or ½ control loop). A discrete - time solver is used for integration within the components (for inductor currents in this case). The three AC grid voltages are generated using con trolled Simscape voltage sources. This is shown in Figure A . 2 on the next page. The frequency is assumed to be a given constant (from the step - function source block). T he phase - angles are computed by integration of the frequency and an offset adjustment. From the angles, a trigonometric block is used to compute the shape of the signals and they are then scaled to the appropriate magnitude. Constructing the voltages this way Figure A . 1 : Top - level diagram of the MATLAB Simulink virtual - resistance simulation. 109 allows for easy manipulation of the frequency, phase, or magnitude of the grid voltage while the simulation is running. With the use of step - function source blocks, each of these parameters can be adjusted at different simulation time instants. This is how the transient responses shown in Section 2.6 were generated. To generate the PWM signals, the internals of a typical microprocessor PWM module were emulated. This is shown in Figure A . 3 below. For the switching state of each phase leg, a logical - - cycle values calculated by the controller and a high - frequency (e.g. 10 kHz) triangle signal which is shifted to have values from 0 to 1. From the switching state of each phase, logical inversion blocks are used to generate the equivalent low - side gating signals. The three switching signals are demuxed, inverted, and then muxed back together to yield the six different gate switching signals. From the ideal gating signals, a rising - edge deadband delay is generated by comparing each switching signal with its Figure A . 2 : MATLAB Simulink model for generating three - phase AC g rid voltages . Figure A . 3 : MATLAB Simulink mod el of PWM hardware with deadband insertion . 110 previous value. Only when both are true is the actual gating s ignal set high. The deadband delay z why the simulation time is usually set to around 1 µs, as it makes simulating deadband easy. As mentioned in Chapter 2, only the grid currents and the DC - bus voltage are supplied to the dq - control algorithm in the sensor - less virtual - impedance contro l method. The dq - controller ultimately outputs three duty - cycle values for the three bridges of the MOSFET inverter. The top - level diagram of the dq - control algorithm is shown in Figure A . 4 . Here, rate - transition blocks are used to change the sampling time from the very - fast simulation time - step (around 1 µs) to the typical algorithm time - step (around 100 µs) used in the digital signal processor (DSP). The virtual - resistance calculation can be seen at the top of the diagram, in parallel to the dq - control block. Meanwhile, the PLL block is shown at the bottom , being fed by the previously calculated phase voltages. To compute the du ty cycles, the basic Sine - PWM (SPWM) method is used. The outputs from the dq - control and virtual - resistance blocks are already in the stationary abc - frame. No third - harmonics have been added to these signals (they are computed using the inverse Park/Clarke transformations). To obtain the duty ratio, the algorithm simply divides by V DC and then offsets by 50% to center the common - mode voltage of the PWM output. Within the dq - control block, we have the basic PID controllers which regulate the currents in Figure A . 4 : Top - level control system diagram of MATLAB Simulink virtual - resistance simulation . 111 the dq - frame. This is shown in Figure A . 5 . The controllers are preceded by the Clarke & Park transformations and followed by the inverse Park & Clarke transformations. The outputs from the PI D - controllers are the voltages used to correct any errors in the regulation of the current. These voltages are added to the pseudo - feed - forward voltage terms, which traditionally would come from the AC voltage sensors but now are fed fro m the PLL. These voltages are simply passed through the PLL block however inverter output voltages. The partial - inductive decoupling terms can also be seen in Figure A . 5 . These are used when implementing virtual - inductors in the control system. For the virtual - resistance simulations, the value of L V I = 0 so these terms resulted in a zero - output. A manual switch was also placed in - line with the PLL frequency, allowing the user to switch the frequency input to zero and eliminate the decoupling . In the cases where L V I to see what effects the decoupling terms had on the dynamics of the control system. The PID - controllers themselves are also Simulink subsystems. The subsystem for one of the Figure A . 5 : MATLAB Simulink model of dq - controllers with decoupling terms . 112 controllers is shown in Figure A . 6 . They simply consist of the basic mathematical blocks needed to compute the output of the basic PID transfer - function , shown below: ( A . 1 ) Saturation block s were also used within the PID - subsystems to limit the output of the controllers to reasonable values. However, one key difference in the PID - subsystems is the implementation of the derivative term. Since it is usually desirable to avoid pure derivatives (as discussed in Chapter 2), the calculation of the derivative here actually uses a high - pass filter, si milar to what was done for computing the voltage - drop of a virtual inductance. Thus, the transfer function above is effectively changed to the following: ( A . 2 ) This approach was used to help reduce high - frequency noise from propagating through the control system. Ideally, the filter cut - off frequ ency, D , should be chosen high enough that the simulations, a cut - off frequency around f D 3 kHz was used to approximate the derivative. Figure A . 6 : MATLAB Simulink model of PID controller implemented with a high - pass filter . 113 Finally, the block - diagram for the Phase - Locked Loop (PLL) is presented in Figure A . 7 . The structure of the PLL is basically the same as was described back in Section 1.2 . Additional features were added to for debugging purposes, and to see their effect on the system dynamics. These features, most of them being low - pass filters, can be enabled or disabled through the toggling of manual switches by the user. Alternate norma signal were also examined. In the figure, the two options to compute the angle - error are to 1) compute the arctangent of the dq - voltages, or 2) simply divide the q - axis component by the magnitude (absolute - value) of the d - axis component. This second method should function very similarly to the hypotenuse calculation described by equation ( 1.14 ) in Chapter 1; ( A . 3 ) The angle - error can also be directly added to the estimated angle through a derivative - like control path, but this was not used in the simulations or experiments. A standard PI - controller was used to regulate the angle - error to zero. Figure A . 7 : MATLAB Simulink model of Phase - Locked Loop subsystem . 114 APPENDIX B : DETAILS ON 1 KW EX PERIMENTAL PROTOTYPE As discussed in Chapter 2, a Silicon - Carbide (SiC) three - phase inverter was developed to validate the proposed virtual - resistance self - synchronization control algorithm. In this appendix, additional details specific to the design of the inverter will be shared. The inverter prototype consisted of two printed circuit board s (PCB s ) . Both were developed was designed to carry the main power - transistors and sens ors. A 3D CAD model of the designed PCB is shown in Figure B . 1 below. The overall dimensions of th is PCB were Figure B . 1 : PCB layout of a three - phase 1 kW 400 VDC inverter f or experiments . 115 164 × 200 mm. The PCB is composed of four cop per l ayers, each manufactured with a 2 - oz copper thickness to help conduct heavy currents (the load currents are conducted through the board traces in some areas ) . Some components, whose 3D models were not obtained (such as the common - mode choke), are not shown in the CAD model, but they can be seen in t he physically - populated board; t his is shown in Figure B . 2 below. Other components which are visible in Figure B . 2 are the heatsinks for the MOSFETs, the wiring of power connections, and the second control board which holds the DSP and peripheral circuitry. The USB communication cable can also be seen here in the figure . Figure B . 2 : . Current Sensor Isolated DCDC CM Choke DSP Board Heatsinks SiC MOSFETs Gate Driver IC Y - Caps X - Caps Voltage Sensor 116 : isolated sensor and gate - drive power supplies ; isolated current sensors (AC and DC); isolated voltage sensors (AC and DC); isolated gate - driver ICs ; the main SiC power MOSFETs ; and other passive components such as the DC - link capacitors, X - caps and Y - caps for filtering the grid connection, and the common - mode choke (used to filter out common - mode PWM voltages from the inverter). The gate driver IC used is the ISO5500 by Texas Instruments (TI). The specific SiC - MOSFETs used were the SCT3060AL devices by ROHM Semiconductor. The cover - page of the component datasheet is shown below in Figure B . 3 . The inverter was designed to use two of Figure B . 3 : Datasheet of the SCT3060AL SiC - MOSFET used in the inverter prototype . 117 these SiC - MOSFETs in parallel for each switching cell in the inverter. Thus, the effective R DS (on) The system was intentio nally over - designed to avoid potential power - loss issues or thermal issues during testing ; the expected currents during testing would be no more than ~20 A. A p art of the schematics for the gate - drive circuitry is shown in Figure B . 4 . To enhance the gate - drive current capability, a BJT Common - Collector (push - pull) amplifier was placed between the gate - driver IC and MOSFET gates. This can be seen in the figure. The BJTs sel ected were the ZXTC2063E6 complementary NPN + PNP paired devices by Diodes Incorporated. Besides enhancing the gate - drive current beyond the capability of the driver output, another ma in benefit of using the discrete BJT amplifier circuits is that the effective gate - source loops of each MOSFET can be made extremely small in the PCB layout. The power supplies for the gate - drive Figure B . 4 : Electrical schematic showing MOSFET gate driver and gat e - drive amplifier circuit s . 118 amplifiers are regulated to +19 V and 5 V; the use of a hig h turn - on voltage helps to ensure a low R DS (on) value and the use of a negative turn - off voltage helps to prevent erroneous turn - on events caused by the Miller capacitance (the C GD capacitance) of the MOSFETs. used with other future projects. - layer PCB design. include : the main Digital Signal Processor (DSP); communication circuits and ICs for Controller - Area Network (CAN) and RS - 232 (Se rial) connections; a local 3.3 V power supply for the DSP; several RC filter circuits for low - pass filtering of the analog input pins; an external Electronically - Erasable Programmable Read - Only Memory (EEPROM) for storing calibration values; and several he (a) (b) Figure B . 5 : L ayout of the DSP 119 Figure B . 5 . TMS320F28069 floating - point DSP by TI. It features a 90 MHz rated clock - speed, a 12 - bit analog - to - digital ( A2D ) converter , a built - in hardware floating - point unit (FPU), and several PWM - capable output pins. The FPU is exceptionally useful in speeding up code execution time, as the main control algorithm is written using 32 - bit floating - point variables and mathematical operat ions. During testing, th e DSP was actually over - clocked to 100 MHz to help speed up the control algorithm and simplify some of the calculations (since the cycle - time would change from 11.11 ns to simply 10 ns). The main control algorithm which runs on the DSP was written in the C - programming language; it consists of over 1000 lines of code. The main control loop , which calculates the PWM duty cycles and regulates the AC current s, runs via a CPU - timer interrupt which triggers at a rate of 20 kHz, or every 50 µs (as mentioned previously in Table 2 . 5 ). At the time of writing, the algorithm require s roughly 65% of the CPU resources (requiring about 32 µs) to process the virtual - resistance control algorithm . This means that the algorithm speed could potentially be safely increased to 25 kHz (40 µs) using the same DSP and clock speed . 120 APPENDIX C : LIST OF SCHOLARLY WO RKS Withi n this section, a list of previous scholarly works developed by the author and other scholars is provided. They are sorted in chronological order from newest to oldest. JOURNAL PAPERS : 1. A. Taylor , J. Lu, L. Zhu, K. Bai, M. McAmmond and A. Brown, "Comparison of SiC MOSFET - based and GaN HEMT - based high - efficiency high - power - density 7.2 kW EV battery chargers," in IET Power Electronics , vol. 11, no. 11, pp. 1849 - 1857, 18 9 2018. 2. L. Zhu, A. R. Taylor , G. Liu and K. Bai, "A Multiple - Phase - Shift Control for a SiC - Based EV Charger to Optimize the Light - Load Efficiency, Current Stress, and Power Quality," in IEEE Journal of Emerging and Selected Topics in Power Electronics , vol. 6, no. 4, pp. 2262 - 2272, Dec. 2018. 3. J. Lu, H. Bai, A. Taylor , G. Liu, A. Brown, P. M. Jo hnson and M. McAmmond, "A Modular - Designed Three - Phase High - Efficiency High - Power - Density EV Battery Charger Using Dual/Triple - Phase - Shift Control," in IEEE Transactions on Power Electronics , vol. 33, no. 9, pp. 8091 - 8100, Sept. 2018. 4. A. Taylor , G. Liu, H. Bai, A. Brown, P. M. Johnson and M. McAmmond, "Multiple - Phase - Shift Control for a Dual Active Bridge to Secure Zero - Voltage Switching and Enhance Light - Load Performance," in IEEE Transactions on Power Electronics , vol. 33, no. 6, pp. 4584 - 4588, June 2018. 5. J. Lu, G. Liu, H. Bai, A. Brown, P. M. Johnson, M. McAmmond and A. R. Taylor , "Applying Variable - Switching - Frequency Variable - Phase - Shift Control and E - Mode GaN HEMTs to an Indirect Matrix Converter - Based EV Battery Charger," in IEEE Transactions on Trans portation Electrification , vol. 3, no. 3, pp. 554 - 564, Sept. 2017. 6. A. Traore, A. Taylor , M. Zohdy and F. Peng, " Modeling and Simulation of a Hybrid Energy Storage System for Residential Grid - Tied Solar Microgrid Systems, " Journal of Power and Energy Engine ering , vol. 5, no. 5, pp. 28 - 39, May 2017. 7. F. Yang, A. R. Taylor , H. Bai, B. Cheng and A. A. Khan, "Using d q Transformation to Vary the Switching Frequency for Interior Permanent Magnet Synchronous Motor Drive Systems," in IEEE Transactions on Transportat ion Electrification , vol. 1, no. 3, pp. 277 - 286, Oct. 2015. 8. F. Yang, C. Jiang, A. Taylor , H. Bai, A. Kotrba, A. Yetkin and A. Gundogan, "Design of a High - Efficiency Minimum - Torque - Ripple 12 - V/1 - kW Three - Phase BLDC Motor Drive System for Diesel Engine Emiss ion Reductions," in IEEE Transactions on Vehicular Technology , vol. 63, no. 7, pp. 3107 - 3115, Sept. 2014. 121 9. C. Duan, C. Jiang, A. Taylor and K. Bai, "Design of a zero - voltage - switching large - air - gap wireless charger with low electric stress for electric vehicles," in IET Power Electronics , vol. 6, no. 9, pp. 1742 - 1750, November 2013. 10. H. Bai, A. Taylor, W. Guo, G. Szatmari - Voicu, N. Wang, J . Patterson and J. Kane, "Design of an 11 kW power factor correction and 10 kW ZVS DC/DC converter for a high - efficiency battery charger in electric vehicles," in IET Power Electronics , vol. 5, no. 9, pp. 1714 - 1722, November 2012. CONFERENCE PAPERS: 1. X. Wan g, D. Gunasekaran, A. Taylor , W. Qian and F. Z. Peng, "Comprehensive Design and Control of Electric Powertrain Evaluation Platform for Next Generation EV/HEV Development," 2018 IEEE Transportation Electrification Conference and Expo (ITEC) , Long Beach, CA, 2018, pp. 237 - 242. 2. G. Liu, H. Bai, M. McAmmond, A. Brown, P. M. Johnson, A. Taylor and J. Lu., "Comparison of SiC MOSFETs and GaN HEMTs based high - efficiency high - power - density 7.2kW EV battery chargers," 2017 IEEE 5th Workshop on Wide Bandgap Power Devic es and Applications (WiPDA) , Albuquerque, NM, 2017, pp. 391 - 397. 3. A. Taylor , J. Lu, H. K. Bai, A. Brown and M. McAmmond, "A model - based buck - type active filter using proportional - resonant controller and GaN HEMTs," 2017 IEEE Applied Power Electronics Confer ence and Exposition (APEC) , Tampa, FL, 2017, pp. 3195 - 3199. 4. K. Berry, A. Traore, A. Krishna, P. Gangadhar and A. Taylor , "Power Systems Infrastructure of Hybrid Electric Fuel Cell Competition Go Kart," SAE 2017 International Powertrains, Fuels & Lubricants Meeting , SAE Technical Paper, 2017 - 01 - 2452, 2017. 5. F. Yang, A. Taylor , H. Bai, B. Cheng, A. Khan, Y. J. Lee and Z. Nie, "Using D - Q transformation to variable switching frequency PWM control for interior permanent magnet synchronous motor drives," 2014 IEEE Energy Conversion Congress and Exposition (ECCE) , Pittsburgh, PA, 2014, pp. 5192 - 5197. 6. Fei Yang, A. Taylor , H. Bai, B. Cheng, A. Khan, Y. J. Lee and Z. Nie , "Application of variable switching frequency PWM control with power loss prediction in surfaced - mounted permanent magnet synchronous motor," 2014 IEEE Conference and Expo Transportation Electrification Asia - Pacific (ITEC Asia - Pacific) , Beijing, 2014, pp. 1 - 4. 7. Y. Li, A. Taylor and K. Bai, "A hybrid observer for the full - speed - range sensorless control of interior permanent magnet motor drives," 2014 IEEE Transportation Electrification Conference and Expo (ITEC) , Dearborn, MI, 2014, pp. 1 - 5. 8. A. Taylor , C. Ji ang, K. H. Bai, A. Kotrba, A. Yetkin and A. Gundogan, "Design of a high - efficiency 12V/1kW 3 - phase BLDC motor drive system for diesel engine emissions reductions," 2013 IEEE Energy Conversion Congress and Exposition , Denver, CO, 2013, pp. 1077 - 1081. 122 9. C. Jia ng, A. Taylor , C. Duan and K. Bai, "Extended Kalman Filter based battery state of charge (SOC) estimation for electric vehicles," 2013 IEEE Transportation Electrification Conference and Expo (ITEC) , Detroit, MI, 2013, pp. 1 - 5. 10. C. Duan, C. Jiang, A. Taylor and K. Bai, "Design of a zero - voltage - switching large - air - gap wireless charger with low electrical stress for Plugin Hybrid Electric Vehicles," 2013 IEEE Transportation Electrification Conference and Expo (ITEC) , Detroit, MI, 2013, pp. 1 - 5. 11. W. Guo, K. Bai, A. Taylor , J. Patterson and J. Kane, "A novel soft starting strategy of an LLC resonant DC/DC converter for plug - in hybrid electric vehicles," 2013 Twenty - Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC) , Long Beach, CA, 2013, pp. 2012 - 2015. 12. Wei Guo, H. Bai, G. Szatmari - Voicu, A. Taylor , J. Patterson and J. Kane, "A 10kW 97% - efficiency LLC resonant DC/DC converter with wide range of output voltage for Plug - in Hybrid Electric Vehicles," 2012 IEEE Transportation Electrification C onference and Expo (ITEC) , Dearborn, MI, 2012, pp. 1 - 4. 13. A. Taylor , Xuntuo Wang, Hua Bai, G. Szatmari - Voicu, J. Patterson and J. Kane, "Design of A 97% - efficiency 10kW power factor correction for fast electric chargers of Plug - in Hybrid Electric Vehicles," 2012 IEEE Transportation Electrification Conference and Expo (ITEC) , Dearborn, MI, 2012, pp. 1 - 6. PATENTS: 1. A. R. Taylor , A. W. Brown, P. M. Johnson, " Multi - Phase - Shift Control of a Power Converter, " U.S. Patent No. WO2019064259A1. Washington, DC: U.S. Patent and Trademark Office, 2019. 123 REFERENCES 124 REFERENCES [ 1 ] J. W. Kolar and T. Friedli, "The Essence of Three - Phase PFC Rectifier Systems Part I," in IEEE Transactions on Power Electronics, vol. 28, no. 1 , pp. 176 - 198, Jan. 2013. [ 2 ] - synchronized Synchronverter Technology for Technol., vol. 2, no. 5, pp. 2 4 29, 2015. [ 3 ] - Phase PLL Structure Specialists Conference, 2006, no. July, pp. 1 6. [ 4 ] - vol. 1, no. May, pp. 5 11, 2000. [ 5 ] S. Long, "Phase Locked Loop Circuits," University of California, Santa Barbra, 2005. [ 6 ] G. Nash, "Phase - Locked Loop Design Fundamentals," Application Note, Freescale Semiconductor, 2006. [ 7 ] ree - Phase and Single - Phase PLL Algorithms for Grid - INDUSCON Conference, 2006, pp. 1 7. [ 8 ] Frame Current Control for Single - Electronics Specialists, 2005., 2005, vol. 2005, pp. 1377 1381. [ 9 ] ron - based Amorphous Metal and 6.5% Silicon Steel for High - Current Inductors in Low - Medium Frequency DC - 2007, pp. 1781 1786. [ 10 ] A. Stadler, T. Stolzke, and C. G Control Conference and Exposition, 2014, pp. 289 292. [ 11 ] "Leakage inductance." Wiki pedia. Wikimedia Foundation, n.d. Web. 9 Oct. 2018. https://en.wikipedia.org/wiki/Leakage_inductance. [ 12 ] A. E. Fitzgerald, C. Kingsley, and S. D. Umans. "Chapter 2. Transformers." Electric Machinery. 6th ed. New York: McGraw - H ill, 2014. pg96. Print. 125 [ 13 ] J. - H. Cho, K. - Y. Choi, Y. - W. Kim, and R. - - Q variations method using 2014 IEEE Energy Conv ersion Congress and Exposition (ECCE), 2014, pp. 5059 5064. [ 14 ] - connected PV inverters with nics Specialists Conference, 2004, vol. 6, pp. 4773 4779. [ 15 ] presentation, NEI Electric Power Engineering, https://www.puc.nh.gov/2008IceStorm/ST&E Pr esentations/NEI Underground Presentation 06 - 09 - 09.pdf [ 16 ] converter without power - pp . 473 479, 1998. [ 17 ] th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2000, vol. 2 , pp. 832 838. [ 18 ] - Impedance - Based Control for Voltage - Source and Current - 12, pp. 7019 7037, Dec. 2015. [ 19 ] - compensated grid synchronisation for extending the stability range of weak grids with voltage source 1315 1326, Apr. 2016. [ 20 ] Smart Grid Technol. Conf. E ur., pp. 1 9, 2012. [ 21 ] T. - - point division and square root using a Taylor - series 1605, Nov. 2009. [ 22 ] - Locked Loop Low - Frequency Stability in Three - Phase Grid - Connected Power Converters 3 21, Jan. 2015. [ 23 ] T. Kim, H. - [ 24 ] A. Taylor, X. Wang, H. Bai, G. Szatmari - 97% - efficiency 10kW power factor correction for fast electric chargers of plug - in hybrid xpo, ITEC 2012, 2012, pp. 1 6.