EFFICIENCY AND LINEARITY ENHANCEMENT TECHNIQUES FOR SWITCHED - CAPACITOR POWER AMPLIFIER S AND TRANSMITTERS By Si - Wook Yoo A DISSERTATION Submitted to Michigan State University in partial fulfillment of the requirements for the degree of Electric al Engineering Doctor of Philosophy 2020 ABSTRACT EFFICIENCY AND LINEARITY ENHANCEMENT TECHNIQUES FOR SWITCHED - CAPACITOR POWER AMPLIFIER S AND TRANSMITTERS By Si - Wook Yoo As wireless communication standards evolve, radio frequency (RF) transmitter (T X) systems with higher linearity and wider bandwidth at increased output power ( P OUT ) are required to meet the high demand for faster communication speed s and increased data traffic. Meanwhile , mobile and wearable applications require a smaller form factor and low - cost solution s . L ow power consumption is also critical for increased battery life, which improves user experience. D igital TX is a promising arch itecture for a small area and low power consumption because conventional TX sub - blocks , such as digita l - to - analog converter (DAC), mixer, driving amplifier, and power amplifier ( PA ) , can be merged into a single block. Furthermore, the linearity, area, and power consumption of a digital TX can be significantly enhanced with the evolution of complementary me tal oxide semiconductor ( CMOS ) technology that provi des faster operation and finer segmentation at lower power dissipation. I t is eas y to migrate to the next generation CMOS process because the digital TX mostly comprises digital circuits . These advantages are more critical when there are multiple TX s in a single system, such as multi - standard and multi - in multi - out systems. A s witched - c apacitor (SC) PA or a n SC RFDAC is employed as a base architecture in this study, ideally providing 100% peak efficiency a s a segmented switching - mode PA ; further , unlike conventional PAs, it does not suffer from a large output signal swing that modulates output impedance , causing amplitude and phase nonlinearities. This study demonstrates various architectures and design te chniques for compact, highly efficient, and highly linear digital TX s . The contributions of this study are as follows : First, a w att - level highly efficient and highly linear quadrature digital TX with a dual - supply Class - G quadrature IQ - cell - shared SCPA a rchitecture is proposed , which maximize s the P OUT and efficiency of the quadrature digital TX. T o enable the C lass - G operation in the quadrature IQ - cell - shared SCPA architecture , a merged - cell - switching technique is proposed . L inearization techniques for t he Class - G operation are proposed to compensate for the amplitude and phase mismatches between the two Class - G modes. Second , a compact and highly linear quadrature digital TX based on quadrature IQ - cell - shared SC RFDAC with linearization techniques is pro posed ; t he linearization techniques increase the TX dynamic range by improving the TX linearity in both high and low P OUT regions. Impedance linearization techniques for the output stage and an offset mid - tread code mapping technique improve the TX lineari ty in the high and low P OUT regions, respectively. The area and power consumption of the RFDAC are minimized by sharing sub - circuits between the two RFDAC cells. Finally , a multimode multi - effi ciency - peak SCPA architecture i s proposed to maximiz e power bac k - off (PBO) efficiency in a polar digital TX . The multimode operation is achieved through an efficient combination of the dual - supply Class - G, Doherty, and 2 - way time - interleaving techniques , thus, maximizing the PBO efficiency by introducing six efficienc y peaks down to 18 - dB PBO . A single - supply current - reuse Class - G switch is proposed for the highly efficient Class - G opera tion without any additional power management unit . Moreover , a LO - signal - restoration technique is presented to minimize both the power dissipation and area for the LO signal distribution . iv ACKNOWLEDGEMENT S First of all, I am grateful to the Lord for guiding me to pursue my Ph.D. degree and taking care of me and my family every moment. I dedicate this dissertation to the Lord, who is t he shepherd of my life . Also, I supplicate to the Lord that every moment of my life will be in his plan. My gratitude to my family is boundless . My parents prayer and sacrifice made me finish my Ph.D . successfully . M y wife, Seunghee, my two daughters Dain and Dajeong, and my son Seojin always made me happy and strong during my Ph.D . Their presence and love e nabled me to overcome all difficulties. I would like to thank my advisor, Dr. Sangmin Yoo , for introducing me to the radio frequency circuit design and inspiring me to pursue this path . I was fortunate to research a switched - capacitor power amplifier with him. I also thank my committee members , Dr. Prem Chahal , Dr. Wen Li , and Dr. Junghoon Yeom , for guiding me throughout my Ph.D . I send many thanks to la b mates at MSU. I am fortunate to have met with wonderful colleagues: Asad , Ibrahim , Xenofon, Shih - Chang, Jubaid, and Adamantia. They always stood by me and gave me plenty of precious memories. I learned many things from Asad, and he helped me every time for my research. Xenofon always helped me revise my papers. I am also thankful to Saints, members of young adult group, and friends in New hope Baptist church. From the start to the end of my Ph.D., they helped my family a lot in both materially and spirit ually a nd prayed for us. I am most grateful that my Ph.D. study has been done in the Lord with them. v TABLE OF CONTENTS LIST OF TABLES ................................ ................................ ................................ ........................ vii LIST OF FIGURES ................................ ................................ ................................ ..................... viii 1 INTRODUCTION ................................ ................................ ................................ .................. 1 1.1 Basics of Wireless Communication System ................................ ................................ ..... 1 1.2 Modern Wireless Communication System ................................ ................................ ....... 3 1.3 Motivation for Digital TX ................................ ................................ ................................ 4 1.4 Challenges facing Digital TX Des i gn ................................ ................................ .............. 5 1.5 Switched - Capacitor Power Amplifier ................................ ................................ .............. 6 1.6 Polar and Quadrature Transmitters ................................ ................................ .................. 7 1.7 Efficiency Enhancement Techniques for Digital TX/PA ................................ ............... 10 1.7.1 Class - G SCPA ................................ ................................ ................................ ......... 11 1.7.2 Transformer - based Doherty SC P A ................................ ................................ ......... 12 1.7.3 Time - Interleaved SCPA ................................ ................................ .......................... 14 1.8 Outline of the Dissertation ................................ ................................ ............................. 15 2 WATT - LEVEL QUADRATURE CLASS - G SWITCHED - CAPACITOR POWER AMPLIFIER ................................ ................................ ................................ ................................ . 18 2.1 Conventional Polar SCPA ................................ ................................ .............................. 19 2.2 Enhanced - Efficiency Clas s - G SCPA ................................ ................................ ............. 21 2 .3 Quadrature SCPA With Dedicated I/Q Cells ................................ ................................ . 22 2.4 Quadrature IQ - Cell - Shared SCPA ................................ ................................ ................. 23 2.5 Quadrature Class - G IQ - Cell - Shared SCPA ................................ ................................ ... 24 2.6 Merged Cell Switching Technique ................................ ................................ ................. 28 2.6.1 Proposed Merg e d SCPA Cell ................................ ................................ .................. 28 2.6.2 Merged Cell Switching Operation ................................ ................................ .......... 30 2.7 Linearization Techniques for Class - G SCPA ................................ ................................ . 36 2.7.1 Supply Voltage Mismatch Insensitive Class - G SCPA ................................ ........... 36 2.7.2 Delay Mismatch Compensation Scheme for Class - G SCPA ................................ .. 40 2.8 Measurement Results ................................ ................................ ................................ ..... 41 2.8.1 CW Signal Measurement ................................ ................................ ........................ 43 2.8.2 Modulated Signal Measurement ................................ ................................ ............. 44 2.9 Summary ................................ ................................ ................................ ........................ 49 3 COMPACT QUADRATURE DIGITAL TRANSMITTER BASED ON SWITCHED - CAPACITOR RFDAC WITH LINEARIZATION TECHNIQUES ................................ ............ 52 3.1 Overall Architecture ................................ ................................ ................................ ....... 52 3.2 Output Switch Linearization Techniques ................................ ................................ ....... 54 3.3 Code Mapping T echnique for RFDAC Linearization ................................ .................... 58 3.3.1 Digital - Code - Mapping Techniques for RFDAC ................................ .................... 58 3.3.2 Mid - Rise and Offset Mid - Tread Code Map p ing Techniques in Complex Domain 60 vi 3.3.3 Implementation of RFDAC with Offset Mid-Tread Code Mapping ...................... 64 3.4 Proposed Merged SC RFDAC Cell................................................................................ 66 3.5 Measurement Results ..................................................................................................... 67 3.6 Summary ........................................................................................................................ 71 4 MULTIMODE MULTI-EFFICIENCY-PEAK DIGITAL POWER AMPLIFIER .............. 73 4.1 Efficiency of the Switched-Capacitor Power Amplifier with Efficiency-Enhancement Techniques ................................................................................................................................ 74 4.1.1 Dual-Supply Class-G SCPA ................................................................................... 76 4.1.2 Doherty SCPA ........................................................................................................ 79 4.1.3 2-Way TI SCPA...................................................................................................... 80 4.1.4 Evaluation of the Efficiency-Boosting Techniques ................................................ 81 4.2 Output Power and Efficiency of the Multimode Switched-Capacitor Power Amplifier 83 4.2.1 Dual-Supply Class-G Doherty SCPA ..................................................................... 84 4.2.2 Dual-Supply Class-G 2-Way TI SCPA................................................................... 86 4.2.3 2-Way TI Doherty SCPA........................................................................................ 87 4.2.4 Multimode SCPA with the Three Efficiency-Enhancement Techniques ............... 88 4.3 Circuit Implementation .................................................................................................. 90 4.3.1 Single-Supply Current-Reuse Class-G Switch ....................................................... 93 4.3.2 LO Signal Distribution............................................................................................ 96 4.4 Measurement Results ..................................................................................................... 97 4.4.1 CW Signal Measurement ........................................................................................ 98 4.4.2 Modulated Signal Measurement ........................................................................... 100 4.5 Summary ...................................................................................................................... 102 5 CONCLUSION................................................................................................................... 104 BIBLIOGRAPHY....................................................................................................................... 106 vii Table 2 - 1 Performance summary and comparison with the state - of - the - art ................................ . 51 Table 3 - 1 Performance su mmary and comparison with the state - of - the - art ................................ . 72 Table 4 - 1 Performance summary an d comparison with the state - of - the - art ............................... 103 viii Figure 1 - 1. Block diagram of a wireless communication system. ................................ .................. 2 Figure 1 - 2. Example of multiple TRXs in a single system. ................................ ............................ 3 Figure 1 - 3. (a) Large PAPR and (b) TPC. ................................ ................................ ...................... 4 Figure 1 - 4. Area - and power - efficient digital TX. ................................ ................................ .......... 5 Figure 1 - 5. Schematic and operation of the SCPA. ................................ ................................ ........ 6 Figure 1 - 6. (a) P olar, (b) conventional quad rature, and (c) quadrature IQ - cell - shared digital TX architectures. ................................ ................................ ................................ ................................ ... 8 Figure 1 - 7. (a) IQ - combined unit vectors of quadrature IQ - cell - shared digital TX. (b) An Example of 3 - bit quadrature IQ - cel l - shared digital TX. ................................ ................................ ................ 9 Figu re 1 - 8. Examples of (a) ideal constellation and (b) constellation with 2 - D distortion. ........... 9 Figure 1 - 9. Dr ain efficiency of switching - mode PA with multiple efficiency peaks. .................. 10 Figure 1 - 10. Operation and drain efficiency of Class - G SCP A. ................................ ................... 12 Figure 1 - 11. Operation and drain efficiency of XFMR - based Doherty SCPA. ............................ 13 Figure 1 - 12. XFMR - based Doherty SCPA with (a) unbalanced XFMR power combining and (b) balanced XFMR power combini ng. ................................ ................................ .............................. 13 Figure 1 - 13. Concept of TI SCPA. ................................ ................................ ............................... 14 Figure 2 - 1. Schematic of the basic SCPA architecture. ................................ ................................ 18 Figu re 2 - 2. SCPA operation in the polar TX. (a) Conventional SCPA and (b) Class - G SCPA with the dual - supply voltage. ................................ ................................ ................................ ................ 20 Figure 2 - 3. T heo retical 2 - D drain effici ency map for quadrant 1 when Q LOAD is 3. (a) Conventional polar SCPA. (b) Class - G polar SCPA. ................................ ................................ .......................... 21 Figure 2 - 4. SCPA operation in quadrature transmitter. (a) SCPA with d edicated I / Q cells, (b) IQ - cell - shared SCPA, and (c) Class - G IQ - cell - shared SCPA. ................................ ........................... 25 ix Figure 2 - 5. Theoretical 2 - D drain efficiency map for quadrant 1 when Q LOAD is 3. (a) Conventional quadratur e SCPA. (b) Quadrature IQ - c ell - shared SCPA. (c) Quadrature Class - G IQ - cell - shared SCPA. ................................ ................................ ................................ ................................ ............ 27 Figure 2 - 6. Quadrature SCPA cells with two thermometer codes. (a) Four cells of quadrature SCPA with d edicated I / Q cells, (b) two cells of quadrature IQ - cel l - shared SCPA, and (c) one merged cell for quadrature dual - supply Class - G IQ - cell - shared SCPA. ................................ ...... 29 Figure 2 - 7. Operation of the MCS t echniqu e. (a) VAS and (b) VPS. ................................ .......... 33 Figure 2 - 8. Implemented VAS pairs for 6b unary cells. ................................ ............................... 34 Figure 2 - 9. SCPA operation without VAS and wit h VAS. ................................ ........................... 35 Figure 2 - 10. Switch cells for Class - G dual - supply voltage SCPA. (a) conventional switch and (b) proposed switch cell for amplitude mismatch compensation. ................................ ...................... 38 Figure 2 - 11. Area - and power - efficient Class - G SCPA switch. ................................ ................... 39 Figure 2 - 12. Phase mismatch compensation technique for Class - G SCPA. ................................ . 41 Figure 2 - 13. Chip implementation. (a) Block diagram. (b) Micrograph. ................................ ..... 42 Figure 2 - 14. Simulated (a) DE vs. P OUT and (b) SE vs. P OUT for a CW signal. ............................ 43 Figure 2 - 15. Measured SE vs. P OUT for a CW signal. ................................ ................................ .. 43 Figure 2 - 16. (a) EVM versus average P OUT and (b) its spectrum at average P OU T of 19.5 dBm (after DPD) m easured with 802.11g OFDM signal. ................................ ................................ ............... 45 Figure 2 - 17. (a) Constellation and (b) spectrum at average P OUT of 17.7dBm (after DPD) measured with 802.11ax 1024 - QAM OFDM signa l with 12.4 - dB PAPR. ................................ ................... 46 Figure 2 - 18 . Measured OOB frequency spectrum for 802.11g 64 - QAM OFDM signal. (a) Data interpolation OFF and (b) Data interpolation ON . ................................ ................................ .......... 47 Figure 2 - 19. (a) EVM versus V DD variation and varactor control voltage (before DPD) and (b) Constellation (after DPD) measured with 20 - MHz single - carrier 256 - QAM signal. ................... 48 Figure 3 - 1. Ove rall architecture of the proposed 13b SC RFDAC. ................................ .............. 53 Figure 3 - 2. Schematic of SC RFDA C with nonlinear switch resistance. ................................ ..... 54 Figure 3 - 3. Switch impedance of the conventional SC RFDAC. ................................ ................. 56 Figure 3 - 4. Switch impedance of the proposed SC RFDAC. ................................ ....................... 57 x Figure 3 - 5. Example of linearity degradation from the mismatch between unary and binar y cell groups. ................................ ................................ ................................ ................................ ........... 59 Figure 3 - 6. Comparison between (a) Mid - rise, (b) mid - tread, and (c) offset mid - t read code mapping techniques for a 1 - D DAC. ................................ ................................ ............................ 59 Figure 3 - 7. Comparison between (a) Mid - rise, (b) mid - tread, and (c) offset mid - tread code mapping techniques for a 2 - D D AC. ................................ ................................ ............................ 60 Figure 3 - 8. Conventional mid - rise code mapping. ................................ ................................ ....... 61 Figure 3 - 9. Conventional mid - rise code mapping with a phase mismatch ( MIS ) between unary and binary cell groups. ................................ ................................ ................................ ......................... 62 Figure 3 - 10. Offset mid - tread code mapping with a phase mismatch ( MIS ) between unary and binary cell groups. ................................ ................................ ................................ ......................... 63 Figure 3 - 11. Implementatio n of the offset mid - tread code mapping. ................................ ........... 65 Figure 3 - 12. Proposed quadrature IQ - cell - shared SC RFDAC cell and its 1b IQ mixer. ............. 66 F igure 3 - 13 . Examples of the proposed quadrature IQ - cell - shared SC RFDAC operation. (a) Without vector switching and (b) with vector switching. ................................ ............................. 67 Figure 3 - 14. Constellation and EVM vs. P OUT for 1024 - QAM signal before/after linearization techniques for high P OUT (HP) and low P OUT (LP) applied. ................................ ......................... 68 Figure 3 - 15. EVM and constellati on for an 802.11ax 20/40 MHz.1024 - QAM OFDM signal. ... 69 Figure 3 - 16. Spectra f or an 80211ax 20/40 MHz 1024 - QAM OFDM signal. ............................. 70 Figur e 3 - 17. Chip micrograph. ................................ ................................ ................................ ...... 71 Figure 4 - 1. Ideal efficiency of the proposed multimode SCPA with a combination of three efficiency enhancement techniques: dual - supply Class - G, transformer - based Doh erty, and 2 - way TI. ................................ ................................ ................................ ................................ .................. 73 Figure 4 - 2. Schematic of the basic SCPA architecture. ................................ ................................ 74 Figure 4 - 3. SCPA operations with two sub - SCPAs wit h (a) dual - supply Class - G, (b) Doherty, and (c) 2 - way TI techniques. (a) can be implemented in a single SCPA, whereas (b) and (c) need two sub - SCPAs. ................................ ................................ ................................ ................................ ... 77 Figure 4 - 4. Comparison of the dual - suppl y Class - G, Doherty, and 2 - way TI SCPAs in terms of (a) d rain effic iency, (b) dynamic power dissipation in the capacitor array ( P SC ), and (c) switching loss ( P SW ) ( Q LOAD = 1, = 0.71, = 0.83, R ON f SW = 24 GHz, and f = 2.4 GHz). ................ 82 xi Figure 4 - 5. Combinations of the two single efficiency - enhancement techniques: (a) A - based B and (b) B - based A. ................................ ................................ ................................ ............................... 83 Figure 4 - 6. SCPA operations with four sub - SCPAs with the following combinations: (a) dual - supply Class - G and Doherty, (b) dual - supply Class - G and 2 - way TI, and (c) 2 - way TI and Doherty techniques. (a) and ( b) can be implemented with two sub - SCPAs, and (c) needs four sub - SCPAs. ................................ ................................ ................................ ................................ ....................... 85 Figure 4 - 7. Comparison of the dual - s upply Class - G Doherty, dual - supply Class - G 2 - way TI, and 2 - way TI Doherty SCPAs i n terms of (a) drain efficiency, (b) dynamic power dissipation in the capacitor array ( P SC ), and (c) switching loss ( P SW ) ( Q LOAD = 1, = 0.71, = 0.83, R ON f SW = 24 GHz, and f = 2.4 GHz). ................................ ................................ ................................ ... 88 Figure 4 - 8. Multimode SCPA operation. ................................ ................................ ...................... 89 Figure 4 - 9. Comparison between the multimode, Doherty - based Class - G, and Class - G SCPAs in terms of (a) drain efficiency, (b) dynamic power diss ipat ion in the capacitor array ( P SC ), and (c) switching loss ( P SW ) ( Q LOAD = 1, = 0.71, = 0.83, R ON f SW = 24 GHz, and f = 2.4 GHz). ................................ ................................ ................................ ................................ ....................... 90 Figure 4 - 10. (a) Overall architecture and (b) operation of the proposed multimode SCPA. ........ 92 Figure 4 - 11. Class - G switches: (a) conventional and (b) proposed switch structures. ................. 94 Figure 4 - 12. (a) Supply voltage mismatch insensitive Class - G switch and (b) d yna mic path delay control for phase mismatch compensation. ................................ ................................ ................... 95 Figure 4 - 13. LO signal distribution: (a) conventional and (b) proposed the LO signal restoration technique. ................................ ................................ ................................ ................................ ...... 96 Figure 4 - 14. Chip micrograph. ................................ ................................ ................................ ...... 97 Figure 4 - 15. Measured DE vs. P OUT for a CW signal. ................................ ................................ .. 99 Figure 4 - 16. Measured AM AM and AM PM vs. normalized input code for a CW signal. ...... 99 Figure 4 - 17. EVM vs. average P OUT measured with 10 - MHz 64 - QAM OFDM signal. ............ 100 Figure 4 - 18. EVM vs. average P OUT measured with a 10 - MHz single - carrier 1024 - QAM signal. ................................ ................................ ................................ ................................ ..................... 101 1 1 INTRODUCTION In the recent times, s mall for m factor , low power consumption , and low cost along with large - scale integration are essential for several mobile and wearable systems with wireless communication . Of late , t he demand for cutting - edge cellular applications, such as fifth - generation (5G) ce llular communications providing high data rates, and wireless connection a m ong several devices over the internet , such as the Internet of Things (IoT) , has rapidly increased . Therefore, to keep pace with technological innovation and benefit more people, it is crucial to develop compact , power - efficient, and low - cost wireless communication solutions. The advancement of complementary metal oxide semiconductor ( CMOS ) technology is expediting the development of these solutions by mean s of enabl ing high density, low cost, and low power consumption for digital integrated circuits . A significant part of wireless communication systems comprises digital circuits such as digital signal processor s (DSP s ). However, in a wireless communication system, if the bulky and hi gh power - consuming analog and radio frequency (RF) functions can be replaced with th e maximum number of digital functions as possible, the wireless communication system can significantly benefit from the advancement of CMOS techn ology . This study focuses o n the realization of the digital transmitter architecture in wireless communication system s . 1.1 Basic s of Wireless Co m munication System Wireless communication is a method of transmitting and receiving information between two or more points , without electrical conductor s such as wires or cables , and information is transmitted in the form of radio waves from transmitter s (TXs) to receiver s (RXs) . The distance between the TX and RX can range from tens of centimeters for near - field commu nication (NFC) 2 or even thou sands of kilometers for satellite communication. A block diagram of a conventional wireless communication system is presented in Figure 1 - 1 . Figure 1 - 1 . B lock diagram of a wireles s communication system. A conventional quadrature RF TX comprises digital - to - analog converter s (DAC s ), reconstruction filter s , up - conversion mixer s , a driving amplifier (DA), and a power amplifier (PA), as illustrated in Figure 1 - 1 . I n - phase ( I ) and quadra ture ( Q ) d igital baseband signals from a DSP are converted to sam pled analog signals through DAC s ; thereafter, the reconstruction filter suppresses the spectral images of the sampled analog signals. The mixer upconverts the baseb and analog signal to an RF signal by mixing the l ocal o scillator (LO) signal. The DA and PA amplify and transmit the RF signal through the antenna. C onventional RF RX comprises a low - noise amplifier (LNA), down - conversion mixer s , lowpass filter s , and analo g - to - digital converter s (AD C s ), as illustrated in Figure 1 - 1 . The RX operation is performed in a manner complementary to the TX operation . The LNA amplifies the weak signal received by the antenna ; thereafter, the mixer s downconvert the RF signal to the ba seband I and Q analog signa l s by mixing the orthogonal LO signal s . Th e lowpass filter s reject other out - of - band signals that could be present in the received spectrum. Finally , t he filter ed analog output signal s are converted to digital signals through the ADC s . Subsequently, t he co nverted digital signals are processed in t he DSP. 3 1.2 Modern Wireless Communication System As wireless communication standards evolve, TX systems with a higher linearity and wider bandwidth at increased output power ( P OUT ) are requir ed to meet the high demand for enhanced communication speed s and increased data traffic. Meanwhile , mobile and wearable applications demand a smaller form factor and low - cost solution. L ow power consumption is also critical for increased battery life, enha nced user experience, and m ulti - standard and multi - in put mul ti - out put (MIMO) systems with multiple transceivers (TRXs) in a single system. An example of multiple TRXs in a single system is presented in Figure 1 - 2 . Figure 1 - 2 . E xample of m ultiple TRXs in a single system . Additionally , h igh energy efficiency , especially at power back - off (PBO), is also required . Furthermore, along with the increasing demand for high data rates with t he finite freq uency bandwid th, highly - spectrally - efficient modulation schemes such as high - order quadrature amplitude modulation (QAM) orthogonal frequency - division multiplexing (OFDM) are essential 4 for wireless communication systems. However, the complex modulation sch emes usually require a large peak - to - average power ratio (PAPR) (e.g., 10 to 13 dB) , as illustrated in Figure 1 - 3(a) , and this forces the TX to operate in the deep PBO region . Furthermore, TX P OUT changes with the requirement for a transmit p ower control (TPC) , as illu strated in Figure 1 - 3(b) , and high efficiency for a wide range of P OUT is required in the modern communication systems. Figure 1 - 3 . (a) Large P APR and (b) TPC . 1.3 M otivation for Dig ital T X The demand for a high - performance TX with energy - , area - , and spectral - efficiency has increased in the era of multi - standards and MIMO wireless communication systems , which provide very high data throughput. Driven by the continuous evolution of pr ocess technology, digital TXs have garnered significant attention in the modern wireless communication system. Th e conventional TX architecture has long been the standard architecture because it enables easy and efficient analog signal processing such as c ontrol gain and filtering. However, the conventional TX sub - blocks occupy a large area an d consume high static current even when delivering a low P OUT . Moreover, it is difficult to benefit from the CMOS process migration because the process scaling cannot be directly applied to the analog sub - blocks. 5 However, the d igital TX s or digital PA s , wh ich use an array of small unit PA cell s controlled by a digital code word to modulate amplitude and phase , have exhibited significant promis e toward s small and low - pow er TX s [1] [43] . The digital TXs can save a significant amount of power consumption and area because they combine the function of the DAC, upconversion mixer, DA , and PA into a single circuit block , as illustrated in Figure 1 - 4 . The digital TX with the adv anced process technology is even more beneficial , providing faster switching and finer segmentation at a lower power dissipation. Figure 1 - 4 . Area - and power - efficient digital TX. 1.4 Challenges facing Digital T X Design I t is significantly more challenging to design a RFDAC in the digital TX than the baseband DAC in the conventional TX for the following reasons : First, an additional resolution is required fo r the RFDAC to achieve the same resolution iden tical the conventional TX in the PBO region because the digital TX does not have any gain stage in the TX chain. Second, it is not easy to maintain high linearity in RFDAC because P OUT and the operating freque ncy of the RFDAC are typica lly much higher than those of the baseband DAC. Third, unlike the conventional TX, the digital TX can emit spectral images because it does not have a n analog low pass filter . To suppress 6 the spectral image s and meet the federal c ommunications commission (F CC) emission limits and spectral mask requirements , digital signal processing for filtering function or increased sampling rates are required. 1.5 Switched - Capacitor Power Amplifier Among the digital PA architectures, switched - capaci tor PA (SCPA) [11] has adva ntages in eff iciency, linearity, and compatibility for several efficiency enhancement techniques. The SCPA provides high efficiency based on switching operations. Moreover , unlike conventional PAs, SCPA does not suffer from the l arge output signal swing th at modulates output impedance and degrades the amplitude and phase linearities such as amplitude modulation (AM) AM and AM phase modulation (PM) distortions. Additionally, it achieve s good linearity because capacitors provide exc ellent matching in a CMOS p rocess. Fig ure 1 - 5 . Schematic and operation of the SCPA . 7 In Figure 1 - 5 , the schematic and operation principle of the SCPA are presented. The number of capacitors switching between V DD and V SS in the capacit or array determines the P OUT of the SCPA, as illustrated in Figure 1 - 5 . For example, if four capacitors are switching simultaneously , the SCPA generates the hig hest voltage. When only two capacitors are switching among the four c apacitors , the SCPA generat es only half the voltage. In this case, there is power dissipation in the capacitor array for charging and discharging the capacitors at RF. Efficiency - enhancem ent techniques such as Class - G [12][23][27][33], Doherty [34] [38], a nd subharmonic switching [3 9][40] have been employed to improve the average efficiency of the SCPA. 1.6 Polar and Quadrature Transmitter s The polar PA [1] [15] [28][31][34] [40][42] , illustrated in Figure 1 - 6 (a) , exhibits high P OUT and high efficiency because it can transmit maximum P O UT to every angle with high energy efficiency , but it requires a complex coordinate rotation digital computer (CORDIC) and wideband phase modulator. In addition, it is not easy to precisely align amplitude and phase data in two s eparate paths, and the mism atch between the two paths leads to signal distort ion [11]. Meanwhile , a quadrature architecture, as illustrated in Figure 1 - 6 (b), demonstrates a simple structure and a wide bandwidth without a supply modulator or CORDIC. However , this architecture exhibit s a lower P OUT with degraded efficiency because th e output signal requires representation using two orthogonal I and Q vectors. Consequently , this conventional fixed I / Q array architecture provides 3 6 dB lower P OUT and a degra ded drain efficiency than t hose of the equivalent polar digital TX . A quadrature IQ - cell - shared digital TX architecture [25] [27] [33][41] [43] , as illustrated in Figure 1 - 6 (c), provides increased P OUT and energy efficiency in a quadrature architecture with an 8 I / Q input signal. Fir st, this architecture combines I and Q unit vectors in the digital domain and then generates a set of new IQ - combined unit vectors that are 45° phase - shifted from I and Q . The architecture delivers the maximum P OUT at 45°/135°/22 5°/315° in which signals ca n be represented with a single IQ - combined unit vector. Figure 1 - 7 presents the four - phase unit vectors generated from the I / Q combination. The IQ - combined unit vectors and their I and Q component vectors are denoted by [ i , q ], [ i , 0], and [0, q ], respect ively, where both i and q are ± 1. In Figure 1 - 7 , 25% duty cycle LO signal s are employed for the I / Q vectors that yield 50% duty cycle IQ - combined LO signal s [25]. Figure 1 - 6 . (a) Polar, (b) conventional quadrature, and (c) quadrature IQ - cell - shared digital TX architectures. Second, all the digital TX cells can be assigned to the same vector simultaneously because there are no dedicated I / Q arrays, as il lustrated in Figure 1 - 7 . Fo r example, a 3 - bit digital TX 9 operates with seven pairs of thermometer codes I < 6 : 0 > and Q < 6 : 0 > that comprise IQ data set [ I < n > , Q < n > ] of each digital TX cell , as described in Figure 1 - 7 (a). Each cell outputs one of the fou r IQ - combined unit vectors , as illustrated in Figure 1 - 7 (b), and they are combined at the summing node of the digital TX . Consequently , the quadrature IQ - cell - shared digital TX achieves an increased P OUT and drain efficiency without any designated I / Q arr ays. Figure 1 - 7 . (a) IQ - combined unit vectors of quadrature IQ - cell - shared digital TX. (b) An Example of 3 - bit quadrature IQ - cell - shared digital TX . Figure 1 - 8 . Examples of (a) ideal constellation and (b) constellation with 2 - D distortion. 10 Among the digital TX architectures, p olar architecture is complex in both digital and analog domains owing to the COR DIC and phase modulator, re spectively. However, the RFDAC in a polar digital TX is simple and generates only amplitude data. Alternatively, a quadrature digita l TX realizes a complete TX system without the need for additional circuits and can support a wid e bandwidth . However, its R FDAC is significantly more complex than that of the polar digital TX owing to the two - dimensional (2 - D) I/Q data. The linearity of t wo one - dimensional (1 - D) RFDACs; quadrature RFDAC cells operate with 90 phase - shifted signals tha t dynamically modulate the output impedance, causing 2 - D distortion illustrated in Figure 1 - 8 and typically require complex, 2 - D digital pre - distortion ( DPD ) . Furthermore, compared to a polar RFDAC with phase rotation in the system, a quadrature RFDAC has 1.5b less - effective resolut ion to represent signals with random distribution (e.g., OFDM). High - density modulation (e.g. , 1024 QAM) for modern wireless standards such as IEEE 802.11ax requires - 35 dB error vector magnitude ( EVM ) , and < - 40 dB EVM is preferr ed, considering additional phase noise and other nonlinearities. Moreover, for 20 to 30 dB of TPC, the RFDAC requires an additional 3 - to - 5b of the resol ution , which significantly complicates the design. 1.7 Efficiency Enhancement Techniques for Digital TX /PA Figure 1 - 9 . Drain efficiency of switching - mode PA with multiple efficiency peaks. 11 A switch - mode PA combined with efficiency - enhancement techniques is a suitable architecture for high average efficiency becau se a switch - mode PA has ide ally 100% efficiency at the peak P OUT . Meanwhile , digital TX or digital PA [1] [43] has been extensively investigated with the advances of CMOS technology. Digital PA architectures correspond with the switch - mode PA because the d igital PA can be implemente d with a segmented switch - mode PA . Furthermore, efficiency - enhancement techniques can be easily integrated into digital PAs to enhance PBO efficiency by providing additional efficiency peaks. For a digital PA, each segmented PA c ell can independently chang e the operation mode for efficien cy enhancement, resulting in a significantly improved, seamless efficiency , and linearity at PBO [12][15] [ 33 ] [4 2 ]. Multiple efficiency peaks with a seamless efficiency curve connecting them can r ealize a near - ideal efficie ncy for a wide range of P OUT , as illustrated in Figure 1 - 9. 1.7.1 Class - G SCPA The Class - G technique significantly enhances average efficiency by employ ing multiple supply voltages. In the SCPA architecture, the Class - G technique not o nly introduces additional e fficiency peaks but also seamless transitions between the peaks such as Doherty, as illustrated in Figure 1 - 10 [ 12 ]. The seamless efficiency curve can be achieved in the SCPAs because each capacitor can switch with different supp ly voltages owing to the ca pacitor as a direct current ( DC ) blocking component , as illustrated in Figure 1 - 10 . However, multiple supply voltages require extra hardware, such as external PMUs, leading to increased power consumption and cost. Multiple supply voltages may also cause li nearity degradation owing to the mismatch between the supply voltages. 12 Figure 1 - 10 . Operation and drain efficiency of Class - G SCPA. 1.7.2 Transformer - based Doherty SCPA The transforme r (XFMR) based Doherty tech nique achieves load modulation and introduces additional efficiency peaks with seamless transitions between the peaks in the PBO region through the sequential operation of peak SCPA cells , as illustrated in Figure 1 - 11 . With an N - way XFMR power combining, for example, N - 1 additional efficiency peaks can be achieved in the PBO region [3 4 ]. However, owing to the unideal and unbalanced XFMR power combining, efficiency enhancement can be limited [ 30 ][3 5 ]. The concept of unideal and un balanced XFMR power 13 combini ng is illustrated in Figure 1 - 12 (a). The P OUT of the main - PA is coupled to the XFMR and back to the peak - PA through the reverse coupling at PBO. Accordingly , energy is lost in the unideal XFMR and switched capacitor network. Mean while , better efficiency ca n be achieved through balanced power combining while suppressi ng the reverse co upling, as illustrated in Figure 1 - 12 (b). However, this approach experiences difficulties with the configuration of multiple PAs. Figure 1 - 11 . Operation and drain efficiency of XFMR - based Doherty SCPA. Figure 1 - 12 . XFMR - based Doherty SCPA with (a) u nbalance d XFMR power combining and (b) b alanced XFMR powe r combining. 14 1.7.3 Time - Interleav ed SCPA S ubharmonic switching technique [39] [ 40 ] can provide additional efficiency peaks with seamless transitions at PBO by sequentially switching digital PA cells between fundamental LO signal and LO signals with subharmonic f requency components (LO1 and LO2) . The subharmonic switching technique with phase interleaving [ 40 ] can be understood as a time - interleaving ( TI ) technique in the time domain , operating PA cells in the PA in a time - interleaved ma nner. Figure 1 - 13 . Concept of TI SCPA . As presented i n the upper - left figure in Figure 1 - 13 , the 50% duty - cycle LO signal can be split into two time - interleaved 25% duty - cycle LO signals operating at half frequency . In the figure on the right , a frequency domain analysis is demonstrated. T he sum of the harmonics of the time - interleaved 25% LO signals at half RF frequency match es the harmonics of the normal LO signal. This harmonic analysis indicates the fun ction of time - interleaved L O signals in the frequency domain. The t ime - interleaved LO signals can be used to introduce an efficiency peak for 6 dB lower P OUT . For example, whe n the normal LO signals in the SCPA are replaced with the time - 15 interleaved LO si gnals, the P OUT of the SCPA reduces by 6 dB, as presented in the lower - left figure in Figure 1 - 13 . If all the SCPA cells are operating with the time - interleaved LO signals, the re is no power dissipation in the capacitor array resulting in an efficiency pea k at the 6 - dB PBO. The TI t echnique can provide not only additional efficiency peaks but also seamless transitions such as Class - G and Doherty. The seamless efficiency can be achieved by applying the sequential switching of the SCPA cells from the fundamen tal LO signal to the time - i nterleaved LO signal , comparable to the operation of the enhanced - efficiency Class - G SCPA illustrated in Figure 1 - 10 . 1.8 O utline of t he Dissertation T his study propose s design techniques for small, highly efficient , and highly linea r digital TX s that replace the conventional TX s . T he proposed digital TX techniques can be employed in the overall wireless communication system s including cellular and wireless connectivity applications , such as fourth - generation l ong - t erm e volution (LTE) , sub - 6 GHz 5G communicatio ns , Wi - Fi, IoT, and Bluetooth . Chapter 2 presents a w att - level quadrature digital TX wi th a quadrature dual - supply Class - G IQ - cell - shared SCPA architecture. An extensive review o f the digital TX architectures based on the SCPA is provided . A detailed and t horough analysis regarding P OUT and drain efficiency is demonstrated for the following conventional and proposed SCPA architectures: i) conventional polar SCPA, ii) enhanced - efficiency Class - G SCPA, iii) quadrature SCPA with dedi cated IQ cells, iv) quadrat ure IQ - c ell - shared SCPA , and v) quadrature Class - G IQ - c ell - shared SCPA. For the circuit implementation, a m erged c ell s witching (MCS) technique employed to achieve dual - supply Class - G operation in the quadrature IQ - cell - shared S CPA is described. Furthermo re, 16 l inearization techniques to compensate for amplitude and phase mismatches in Class - G operation are presented. Chapter 3 presents a compact quadrature digital TX based on IQ - cell - shared SC RFDAC with linearization techniques. N onlinearities in SC RFDAC are investigated , and three linearization techniques are proposed , which are aimed at minimiz ing impedance variation at the output stage and systematic nonlinearity between unary and binary cell groups in RFDAC . For the circuit i mplementation , on - resistanc e linearization t echniques for the RFDAC output switch es and an offset mid - tread code mapping technique are presented to minimize the output impedance variation and RFDAC error in unary/binary cell groups in the deep PBO region . Furthermore, the number of logic circuits is minimized by sharing digital circuits between the two RFDAC cells to reduce the chip area and power consumption . Chapter 4 presents a multimode multi - efficiency - peak SCPA architecture for maximiz ed PBO efficienc y in a polar digital TX. A d etail ed and thorough analysis o f the ideal and practical drain efficiency of the SCPA with three different efficiency - enhancement techniques is presented . Efficiency - enhancement techniques such as dual - supply Class - G, Doherty, a nd 2 - way TI are discussed a nd com pared. After the review and comparison of s ix combinations of the two different efficiency - enhancement techniques , an efficient combination of the three techniques is proposed. The discussed efficiency - enhancement technique s are as follows: i) dual - s upply Class - G, ii) Doherty, iii) two - way TI, iv) Class - G - based Doherty, v) Doherty - based Class - G, vi) Class - G - based TI, vii) TI - based Class - G, viii) TI - based Doherty, ix) Doherty - based TI, and x) Class - G, Doherty, and TI. For the circuit implementation, a single - supply current - reuse Class - G switch for linear and efficient dual - supply Class - G operation is introduced . In addition, a n LO - signal - 17 restoration technique is presented to minimize power dissipation and area for the LO signa ls distribution . Chapter 5 presents the conclusion of this study . 18 2 WATT - LEVEL QUADRATURE CLASS - G SWITCHED - CAPACITOR POWER AMPLIFIER Figure 2 - 1 present s a basic schematic of the conventional SCPA architecture. The unit capacitors in the capaci tor array are selectively s witched at RF for the generation RF P OUT . Assuming that an ideal inductor is in series with the capacitor array, t he square wave at the capacitor top plate is filtered by an ideal bandpass network. Further assuming that the filte r is ideal, o nly a fundamen tal component is delivered at the output. T he equivalent circuit of the capacitor array is connected in series wi th an inductor L and output resistor R OPT for calculat ing the P OUT and ideal drain efficiency of the SCPA, as illus trated in Figure 2 - 1 . The c apacitor array in both polar and quadrature architectures are detailed in Figure s 2 - 2 and 2 - 4 . For simplicity, the numbers of capacitors switched at RF ( O N ) and unswitched ( O FF ) are depicted in a bar chart that demonstrates the o peration of capacitors in t he capacitor array. The vectors with different phases are illustrated as square waves with different delays at the top of the bar chart. A vector distribution from the switched to unswitched capacitors for enhanced - efficiency Cla ss - G operation [ 12 ] is illu strated with arrows and square waves in Figure s 2 - 2 (b) and 2 - 4 (c). Figure 2 - 1 . Schematic of the basic SCPA architecture. 19 2.1 Conventional Polar SCPA The fun damental component of outpu t voltage ( V OUT ) and P OUT in the conventional polar SCPA [11], as shown in Figure 2 - 2 (a), is as follows: where N , n , and R OPT denote the total number of SCPA capacitors ( C TOT ), the number of capacitors switched between V DD and V SS , a nd the output resistance [11] for the desired peak P OUT , respectively. Term denotes the Fourier coefficient for the fundamental frequency of the square wave. Assuming very fast switching operation, the dynamic power dissipation of the SCPA in the capac itor array ( P SC ) is determined as follows: where C IN denotes the series capacitance of the selected n and unselected N n capacitors, as illustrated in Figure 2 - 2 (a). The ideal d rain efficiency of the SCPA is determined as follows: Substitution of ( 2. 2) and ( 2. 3) into ( 2. 4) yield s the drain efficiency, as illustrated in Figure 2 - 3 (a) in 2 - D IQ domain and in 1 - D as depicted in Path A. A loaded quality factor ( Q LOAD ) of three for the output matching network is used for the efficiency calculation [11] throughout this chapter . The Q LO AD is defined as follows: 20 For higher drain eff iciency, a high Q LOAD is preferred because P SC is proportional to C TOT which is the capacitance of the output matching network. Figure 2 - 2 . SCPA operation in the polar TX . (a) Conventional SCPA and (b) Clas s - G SCPA with the dual - supply voltage. 21 Figure 2 - 3 . Theoretical 2 - D drain efficiency map for quadrant 1 when Q LOAD is 3. (a) Co nventional polar SCPA. (b) Class - G polar SCPA. 2.2 Enhanced - Efficiency Class - G SCPA The drain efficiency of a Class - G SCPA using a dual - supply voltage, V DD2 and V DD , is detailed in [12] [ Figure 2 - 2 (b)]. Ideally, V DD2 is double V DD . The total number of capacito rs and input codes are defined as N and M , respectively, where M = 2 N . The numbe r of selected cells is n , where 0 n N and the selected code is m, where 0 m M . In the case of m N , V OUT , P OUT , and ideal drain efficiency can be expressed in a simila r manner to the conventional SCPA ( 2. 1) ( 2. 4) because the operation o f both SCPAs is similar . 22 When m > N , V OUT and P OUT are determined using the following expressions: The dynamic power dissipation of the Class - G S CPA is as follows: The ideal drain efficiency calculated from ( 2. 4), ( 2. 7 ), and ( 2. 8) is shown in Figure 2 - 3 (b). 2.3 Quadrature SCPA With Dedicated I/Q Cells The conventional quadrature SCPA has two sub - SCPAs for I and Q signals, as illustrated in Figure 1 - 6 (b). The total number of capacitors is N , and each sub - SCPA for the dedicat ed I and Q has half of the array, as illustrated in Figure 2 - 4 (a). Because the I and Q signals are orthogonal, the amplitude of the V OUT and P OUT can be determined as follows: where 0 i 0 . 5 N and 0 q 0 . 5 N denote the number of capacitors switched between V DD and V SS for the I and Q SCPAs, respectively. In the quadrature SCPA, the total dynamic power dissipation can be expressed as the sum of each dynamic power because the two independent quadrature signals operate with a different charge and discharge tim ing for their capacitors as follows: 23 Therefore, the ideal drain efficiency is obtained from ( 2. 4) and ( 2. 10) ( 2. 13) and is illustrated in Fig ure 2 - 5 (a). 2.4 Quadrature IQ - Cell - Shared SCPA As illustrated in Figure 2 - 4 (b), the quadrature IQ - cell - shared SCPA uses two orthogonal vectors as in the conventional quadrature SCPA. Therefore, the V OUT and P OUT can be obtained in a similar manner to the conve ntional quadrature SCPA as follows: where a and b denote the number of capacitors switched between V DD and V SS , representin g vectors A and B , respectively. In this architecture, the relationship among a , b , and N can be expressed as 0 a + b N because a and b can be flexibly allocated within the total number of capacitors N , as illustrated in Figure 2 - 4 (b). The dynamic powe r dissipation can also be calculated using a similar method to the conventional quadrature SCPA as follows: 24 T he ideal drain efficiency can therefore be obtained from ( 2. 4) and ( 2. 15) ( 2. 18). Al though the equations seem to be similar to that of the quadrature SCPA with fixed I / Q cells, the IQ - combined unit vectors with flexible vector allocation result in a different efficiency map, as illustrated in Figure 2 - 5 (b). With no dedicated, half - sized I / Q cells, it exhibit s an increased V OUT ( P OUT ) and better efficiency in the PBO region. 2.5 Quadrature Class - G IQ - Cell - Shared SCPA Figure 2 - 4 (c) shows the Class - G opera tion in a quadrature IQ - cell - shared SCPA. Unlike polar SCPA and conventional quadrature SCPA with dedicated I / Q c ells, the input digital code to IQ - shared cells has not only amplitude but also phase information. Consequently , the Class - G technique introdu ced in [12] for a polar SCPA and in [23] for a conventional quadrature SCPA that processes only amplitude informat ion cannot be directly applied to the quadrature IQ - cell - shared architecture. For the enhanced - efficiency Class - G operation with an efficiency peak at 6 - dB PBO in the efficiency contour in the quadrature IQ - cell - shared architecture, the output vectors with an amplitude of V DD2 in the SCPA cell are distributed to the turned - off cells , as depicted in Figure 2 - 4 (c). The number of turned - on cells fo r vectors A and B with an amplitude of V DD2 is defined as a and b , respectively, and turned - off cells are defined as k . The range of k is chosen as less than half of the total number of cells, N , for the Class - G operation within 0 6 - dB PBO region. k is div ided into two groups and that receives the distributed vectors A and B with an amplitude of V DD , respectively, where 0 a , 0 b , and + = k . After vector distribution, the amp litude of the vectors A and B are ( a ) V DD2 + 2 DD and ( b ) V DD2 + 2 DD , respectively, as illustrated in Figure 2 - 4 (c). The V OUT and P OUT of the quadrature Class - G IQ - cell - shared SCPA can be obtained by replacing V DD with V DD2 in ( 2. 14) and ( 2. 15) for the quadrature IQ - cell - shared SCPA 25 Figure 2 - 4 . SCPA operation in quadrature transmitter. (a) SCPA with dedicated I / Q cells , (b) IQ - cell - shared SCPA , and (c) Class - G IQ - cell - shared SCPA. 26 In the region deeper than the 6 - dB PBO, the operation is similar to the quadrature IQ - cell - shared SCPA without Class - G ( Chapter 2.4 ), because all the vectors with an amplitude of V DD2 have been distributed and only the vectors with an amplitude of V DD remain. The ideal drain efficiency can be obtained from similar equations. For calculating the ideal drain efficiency in the 0 6 - dB PBO region, the dynamic power dissipation of the Class - G operating cells for the vectors A and B needs to be analyzed. In Figure 2 - 4 (c), the equivalent capacitor arrays of the SCPA and their input voltages are demonstrated to calculate the dynamic power dissipation. Unlike other architectures discussed, thus f ar, in Chap ter 2 , the dynamic power dissipation cannot be derived directly with C IN because the capacitor network has three ports with different potentials. Thus , the dynamic power dissipation for each capacitor switched between V DD2 and V SS , V DD and V SS , and unswi tched capacitors can be calculated separately as follows: where P SC_A1 ( P SC_B1 ) , P SC_A2 ( P SC_B2 ) , and P SC_A3 ( P SC_B3 ) denote the powers dissipated to charge/discharge the capacitors switched between V DD2 and V SS , V DD and V SS , and unswitched capacitors , respectively. The total dynamic power dissipation is determined as follows: 27 Figure 2 - 5 . Theoretical 2 - D drain efficiency map for qua drant 1 when Q LOAD is 3. (a) Conventional quadrature SCPA. (b) Quadrature IQ - cell - shared SCPA. (c) Quadrature Class - G IQ - cell - shared SCPA. 28 where 0 a , 0 b , and N = a + b + + . The ideal drain efficiency is obtained from ( 2. 4) and ( 2. 20) ( 2. 25), as illus trated in Figure 2 - 5 (c). 2.6 Merged Cell Switching Technique In contrast to the conventional dual - supply Class - G SCPAs that process 1 - D amplitude information in a polar architecture or a quadrature architecture with dedicated I / Q cells, the Class - G technique cannot be directly applied to the IQ - cell - shared architecture because various vectors with different amplitude s and phase s require process ing in a single SCPA cell. The operation theory is detailed in this C hapter 2.6 . The high average drain efficiency is achieved with an additional efficiency peak associated with the Class - G operation. Furthermore, power dissipation in the digital logic circuit s operating at RF such as the digital mixer, level shifter, and control blocks can be reduced by half, leading to an improved system efficiency (SE) as well. 2.6.1 Proposed Merged SCPA C ell To achieve a reduced chip area and an enhanced drain efficiency associat ed with the efficien c y Class - G operation in quadrature architecture, four conventional quadrature SCPA cells, pres ented in Figure 2 - 6 (a), are merged into two cells by adopting the IQ - cell - shared architecture [25], as illustrated in Figure 2 - 6 (b) ; thereafter , the two cells are further merged into a single cell that operates with a dual - supply voltage, as illustrated in Figure 2 - 6 (c), and discussed in this section. After the merger , a Class - G operation is performed using the merged cell switching ( MC S ) technique described in Chapter 2.6.2 . 29 Figure 2 - 6 . Quadrature SCPA cells with two thermometer codes. (a) Four cells of quadrature SCPA with dedicated I / Q cells, (b) two cells of quadrature IQ - cell - shared SCPA, and (c) one merged cell for quadrature dual - supply Class - G IQ - cell - shared SCPA. The merged cell for the Class - G operation presented in Figure 2 - 6 (c) processes two input IQ data sets, [ I < 0 > , Q < 0 > ] and [ I < 1 > , Q < 1 > ]. Because each SCPA cell has just one digital mixer that processes a single IQ - combined unit vector, it cannot process the two IQ da ta sets simultaneously . Accordingly, multiplexers select only one IQ data set out of the two using a selection signal from the control logic in each SCPA cell. The basic operation of the merged cell is as follows : 1) If the two IQ data sets are the same , the output switch delivers the signal with an amplitude of V DD2 regardless of the multiplexer selection signal. 2) If the two IQ data sets that the multiplexers receive are different, the multiplexers select o ne or the other, based on the code selection scheme di scussed in Chapter 2.6.2 . 30 3) If the two IQ data sets of the SCPA cell are deactivated, the switch is not switched and connected to signal ground. 2.6.2 Merged Cell Switching Operation The MCS technique, comprise d the vector amplitude switching (VAS) and vector phas e switching (VPS) techniques as illustrated in Figure 2 - 7 , is implemented on chip along with other digital control logic gates. The MCS technique enables an enhanced - efficiency Class - G operation in the quadrature IQ - cell - shared SCPA architecture. The VAS e nables the vector distribution introduced in Chapter 2.5 , and the VPS conserves the amplitude and phase information when the cells are merged. First, the SCPA cell is turned off by the 180° out - of - phase (OOP) data removal operation [25] in the IQ - shared ce lls. The pairs of IQ data sets that are deactivated are as follows: [1, 0], [0, 1] or [1, 1], [0, 0]. Examples of the 180° OOP operation are presented in the pairs of gray dashed rectangles in Figure 2 - 7 . The VAS operation is described in Figure 2 - 7 (a). If the two input IQ data sets of the SCPA cell are the same and their VAS paired cell is turned off, the VAS operation splits a vector with an amplitude of V DD2 into two smaller vectors with a n amplitude of V DD , distributing half of the vector from the fully turned - on ( V DD2 ) cell to the paired turned - off (O FF ) cell. This operation maintain s the same output voltage at the top plate of the capacitors after the vector distribution. The VPS operation is presented in Figure 2 - 7 (b). It maintains the vector informat ion when one of the SCPA cells has two different input IQ data sets. Each SCPA cell can process only one IQ data set because it has only one IQ mixer, and the unselected data require compensation . The unselected data are transferred to the cell with an aux iliary (AUX) input that processes the extra 31 IQ data set. The AUX input is controlled by the digital phase comparator that detects the difference between the two IQ data sets. If the two data sets to an SCPA cell are different, the AUX input is activated to compensate for the unselected data. The detailed SCPA operation with both VAS and VPS is directly related to the merged SCPA cell described in Chapter 2 . 6. 1 and is as follows : 1) If the two input IQ data sets are the same, the SCPA cell outputs a square - wave signal of amplitude V DD2 modulated with the IQ data set. Otherwise, it distributes one of the two data sets to the VAS - paired cell that is O FF . In this case, both operate with V DD for better drain efficiency. 2) If one of the two input IQ data sets is cancel ed by the 180° OOP data removal, the SCPA cell d elivers a signal of amplitude V DD modulated with the remaining IQ data set. 3) If both IQ data sets are deactivated by the 180° OOP data removal operation, the SCPA cell remains O FF and connected to a signal gro und because there is no IQ data set to be distri buted from the paired cell in the deep PBO region. In the case of 0 6 - dB PBO, the SCPA cell outputs the distributed signal with an amplitude of V DD from its VAS - paired cell. 4) If the two IQ data sets are not th e same, only one of them is selected in the SCPA cell to generate a modulated signal of amplitude V DD , and the unselected IQ data set is distributed to the cell with the AUX input through the VPS operation. The VAS operation is performed between the VAS pa ired SCPA cells as illustrated in Figure 2 - 8 . Figure 2 - 9 shows a comparison of t he SCPA operation s between the without VAS and with VAS cases . For the former case, when the P OUT of the SCPA is shrinking , the cells are turned off two by two and the output c apacitors of the turned - off cells become a capacitive loading for the 32 operating cells. Meanwhile , for the latter case, from 0 to 6 - dB PBO , the cells in group s 2 and 3 provide vector information to group s 4 and 1 , respectively. After finish ing the amplitude vector d istribution, all cells operat e in V DD mode. In this case, ideally, there is no capacitive loading between the SCPA cells , resulting in an efficiency peak at 6 - dB PBO . From 6 - dB to the deepest PBO , the SCPA cells are turned off two by two , which is the same operation to the without VAS case. 33 Figure 2 - 7 . Operation of the MCS techni que. (a) VAS and (b) VPS. 34 Figure 2 - 8 . Implemented VAS pa i r s for 6b una ry cells. 35 Figure 2 - 9 . SCPA operation without VAS and with VAS. 36 2.7 Linearization Techniques for Class - G SCPA As discussed in Chapter 2 .2 , the enhanced - efficiency Class - G SCPA has a si gnificant advantage in improving the drain efficiency. Class - G with multiple supply voltages in SCPA is more linear than in the conventional Class - G PAs because the abrupt switching produce s glitches. The power - domain change is very smoothly and seamlessly made in SCPA because: 1) the voltage domain changes when the switches are disabled and is not connected to any supply voltage and 2) the voltage does not change abruptly f or the entire PA, but rather changes in a continuous manner while using both supply voltages simultaneously for enhanced efficiency and linearity. However, the multiple supply voltages still result in signal distortion owing to the mismatches in the supply voltages and different signal paths, necessitating compensation with predistortion. The linearization techniques for the amplitude and phase discussed in this section improve the linearity and minimize the requirement of DPD. 2.7.1 Supply Voltage Mismatch Insen sitive Class - G SCPA Figure 2 - 10 present s a conventional switch for a dual - supply Cla ss - G SCPA [12] and the proposed switch that is insensitive to the supply voltage mismatch. In Figure 2 - 10 , the matching network for the output stage is not provided . The Cl ass - G switches employ the two different voltages, V DD2 and V DD , to generate an outpu t voltage for large/small output power. In the conventional switch in Figure 2 - 10 (a), V DD2 should be equal to 2 × V DD to generate an accurate output voltage. However, the value of V DD is not always one half of V DD2 and can differ owing to process (P), volt age (V) and temperature (T) (PVT) variation. Any mismatch generates nonlinearity and should be corrected with DPD. Ev en after DPD, it is still susceptible to any dynamic change if there are uncorrelated changes or glitches in both voltages during actual 37 op eration. The amplitude of the distorted output voltage in the V DD mode for low power, shown in Figure 2 - 10 (a), can be expressed as follows: where V denotes the mismatch between the two supply voltages. The proposed switch for Class - G SCPA depicted in Figure 2 - 10 (b), however, is very robust to any supply voltage mismatch. It use s the average of V DD2 V DD a nd V DD V SS to generate V DD2 / 2 instead of V DD in the low power mode ( V DD mode). It splits a conventional Class - G switch cell into two half - sized cells that operate between V DD V SS and V DD2 V DD , and shares the outputs at the capacitor top plates throug h capacitor combining using a half - sized capacitor ( C S ) . The mismatch vol tage can be canceled out at the summing node at the top plate of the capacitors. The amplitude of the linearized output voltage in the V DD mode can be expressed as follows: The reduction of the dynamic power consumption in the output switches and switch drivers is essential in improv ing the efficiency of the SCPA. The dynamic p ower is dissipated to charge and discharge the capacitor array and parasitic capacitance at the tran sistor switch itself. The power consumption to charge/discharge the capacitor array can be reduced by using the Class - G technique or using small capacitors as discussed in Chapter s 2 .1 5 . However, owing to the additional transistors for the Class - G operati on, the drain efficiency improvement can be compromised, especially in the deep PBO region. To maximize efficiency improvement, an area and power - efficient switch is proposed for the Class - G SCPA, as illustrated in Figure 2 - 11 . 38 Figure 2 - 10 . Switch cells for Class - G dual - supply voltage SCPA. (a) conventional switch and (b) proposed s witch cell for amplitude mismatch compensation. 39 Figure 2 - 11 . Area - and power - efficient Class - G SCPA switch. For a simplified explanation, we describe the proposed switch without t he supply - voltage - insensitive switch structure, but it is applied to both split switches as illustrated in Figure 2 - 10 . For the low power mode in the conventional switch for the Class - G operation, MP3 switches at carrier frequency while MN3 is ON to provid e V DD to the switching network. The proposed swi tch architecture removes MP3 from the conventional switch and reuses an existing cascode transistor, 40 MP2, as a switching device in V DD mode to reduce the parasitic capacitance at the switch output. Furthermor e, if the ON - resistance of MN3 is small, only a part of MP2 require s switching when it operates from V DD to save the dynamic power consumption in the buffer chain driv ing MP2. In this design, only half of the MP2 is used for the MP2A that switches in the V DD mode. The gate of the remaining transistor, M P2B, is biased at V DD and is turned off in the V DD mode. 2.7.2 Delay Mismatch Compensation Scheme for Class - G SCPA Although there is no amplitude mismatch between V DD2 and V DD modes when V DD2 and V DD are ideally ma tched, a delay mismatch can exist because the proposed SCPA operates with two different supply voltages. The delay mismatch in the two different signal paths will directly result in a phase mismatch. Notably, any difference in buffer size fo r driv ing NMOS/ PMOS switches of different sizes will make a difference in the switching time. Additionally, t he parasitic capacitance cannot be exactly matched with a different fan out. Furthermore, the supply voltage difference can result in an even large r variation in signal delay due to different switching time s . An ideal switch can be the best solution for eliminat ing the phase mismatch. However, an efficient compensation technique for the delay (phase) mismatch is required with finite switch performanc e. It is more s ignificant at a higher frequency because the same delay mismatch results in a larger phase mismatch at the higher operating frequency. In this design, a dynamic path delay control scheme is proposed to compensate for the non - ideal switching performance of the transistor switch, as illustrated in Figure 2 - 12 . A path - dependent adjustable delay is introduced to match the delay in both V DD2 and V DD modes. The proposed delay control technique minimizes the mismatch by aligning the output signals f rom different s upply voltages. The signal path is dynamically changing according to the two Class - G operation modes, and each of the paths has its own delay cell to control the delay independently. 41 Figure 2 - 12 . Phase mismatch compensation technique for Class - G SCPA. 2.8 Measurement Results Figure 2 - 13 (a) present s a block diagram of the quadrature Class - G SCPA with MCS and linearization techniques. It has two 11 - bit SCPAs with a power - combining transf ormer for deliver ing more than 30 - dBm P OUT . The 11 - bit array comprises 6 - bit unary and 5 - bit binary cells. IQ data are interpolated with the two SCPAs in a time - interleaved manner to suppress the spectral image s result ing from a low sampling rate. A four - p hase clock generator and a low - voltage differential signaling (LVDS) receiver are implemented on the chip for generat ing four - phase IQ - combined unit vectors. The prototype quadrature SCPA is fabricated in a 65 - nm RF CMOS process and occupies an area of 2 . 0 × 1 . 5 mm 2 , including a power - combining transformer, two SCPAs, a four - phase clock generator, an LVDS receiver, decoupling capacitors, and bonding pads. The chip micrograph is presented in Figure 2 - 13 (b). 42 (a) (b) Figure 2 - 13 . Chip implementation. (a) Block diagram. (b) Micrograph. 43 Figure 2 - 14 . Simulated (a) DE vs. P OUT and (b) SE vs. P OUT for a CW signal. Figure 2 - 15 . Measured SE vs. P OUT for a CW signal. 2.8.1 CW Signal Measurement Figure 2 - 14 illustrate s the extracted simulat ion results for drain efficiency (DE) versus P OUT and SE versus P OUT with a continuous - wave (CW) signal. Figure 2 - 15 illustrate s the measur ed SE 44 versus P OUT with the CW signal. The prototype SCPA transmits a peak P OUT of 30.1 dBm with a peak SE of 37.0% at 2.2 GHz. With VAS applied for the Class - G operation, the measured S E at 6 - dB PBO is 26.1% , which is 1.25 times better than the SE of 20.8% without VAS owing to an additional efficiency peak. In addition, the graph also indicate s that the proposed VAS technique for the Class - G SCPA improves SE within 0 6 - dB PBO region with out any abrupt discontinuity in the efficiency curve [12]. Further SE i mprovement can be achieved in advanced fine - line CMOS technology because of the reduced power dissipation in digital logic and buffers for driv ing switches. 2.8.2 Modulated Signal Measurement Figure 2 - 16 (a) illustrates the EVM versus the average P OUT measured wi th a 20 - MHz, 802.11g 64 - QAM OFDM signal with PAPR of 10.6 dB. P OUT is adjusted by changing the digital I / Q input signal. The prototype exhibit s an excellent EVM of better than - 40 dB for more than 20 dB of P OUT range after DPD. It achieves an EVM of - 40.7 dB at an average P OUT of 19.5 dBm. The EVM degradation above 19.5 dBm is due to the hard clipping of signal which also reduces PAPR. A wider dyn amic range can be achieved with increased system resolution and accuracy. Figure 2 - 16 (b) illustrate s a close - in frequency spectrum at an average P OUT of 19.5 dBm. Figure 2 - 17 demonstrates the measured data with a modern 802.11ax 1024 - QAM OFDM signal. Figur e 2 - 17 (a) and (b) illustrate a constellation and a close - in frequency spectrum, respectively, at an average P OU T of 17.7 dBm after DPD. Figure 2 - 18 present s the out - of - band (OOB) frequency spectrum of the 802.11g with a baseband I / Q data sampling rate of 400 MS/s. The images at 2.2 GHz ± 400 MHz are suppressed by more than 10 dB with interpolated I / Q data. The sp ectral image can be significantly reduced with a high sampling rate, signal processing techniques, and filtering. 45 (a) (b) Figure 2 - 16 . (a) EVM versus average P OUT and (b) its spectrum at average P OUT of 1 9.5 dBm (after DPD) measured with 802.11g OFDM signal. 46 (a) (b) Figure 2 - 17 . (a) Constellation and (b) spectrum at average P OUT of 17.7dBm (after DPD) measured with 802.11ax 1024 - QAM OFDM signal with 12.4 - dB PAPR. 47 (a) (b) Figure 2 - 18 . Measured OOB frequency spectrum for 802.11g 64 - QAM OFDM signal. (a) Data interpolation OFF and ( b) Data interpolation ON . The performances of the proposed linearization techn iques are also verified over V DD variation using a 20 - MHz single - carrier 256 - QAM signal with a PAPR of 7.6 dB. Figure 2 - 19 (a) present s two EVM curves with the supply voltage and delay mismatches in the V DD2 and V DD modes for the Class - G operation. DPD is n ot applied for demonstrating the effectiveness of the linearization techniques. For the experiment, ± 10% of V DD supply voltage is varied while V DD2 is fixed to maintain a constant P OUT . 48 (a) (b) Figure 2 - 19 . (a) EVM versus V DD variation and varactor control voltage (before DPD) and (b) Constellation (after DPD) measured with 20 - MHz single - carrier 256 - QAM signal. 49 The measured EVM, represented as a red dashed line, demonstrates excellent linearity , better tha n - 32 dB , across the ± 5% of V DD variation. D elay ed mismatch in the V DD2 and V DD modes causes t he degradation in EVM. The two separate signal paths operat ing with different supply voltages of V DD2 V DD and V DD V SS are directly affected by a dif ferent delay and rise/fall time. Notably , the advanced CMOS technology can improve the EVM . The switching speed in advanced CMOS is significantly fast ; thus , the transition time and associated delay mismatc h can be minimized. A delay calibration using varactors compensates t he phase mismatch between the two Class - G modes, and EVM versus varactor control range is depicted as a red dashed line in Figure 2 - 19 (a). Owing to the insufficient delay control range i n this design, the EVM improvement is limited. The measured constellation and EVM are presented in Figure 2 - 19 (b). A t an average P OUT of 22.5 dBm after DPD for a 20 - MHz 256 - QAM signal , t he EVM is - 40.3 dB. 2.9 Summary A quadrature Class - G IQ - cell - shared SCPA wi th MCS and linearization techniques is implemented in a 65 - nm RF CMOS process. The MCS technique, comprising VAS and VPS, improves SE through enabling a Class - G operation that seamlessly employs dual - supply voltages for a quadrature SCPA. The linearization technique s also enhance the linearity by compensating amplitude and phase mismatches when the PA is driven from two separate supply voltages with the Class - G operation. T he outputs of two time - interleaved SCPAs are coupled using a power - combining transfor mer t o achi eve watt - level peak output power and minimized spectral image. The prototype 11 - bit SCPA achieves peak P OUT and SE of 30.1 dBm and 37.0%, respectively. With an 802.11g 64 - QAM OFDM signal, it shows an average P OUT and SE of 19.5 dBm and 14.7%, re spectively, while achieving EVM of - 40.7 dB after DPD. The prototype with a novel supply - voltage mismatch insensitive output switch cell exhibit s EVM better t han - 32 dB across 50 ± 5% V DD variation while delivering an average P OUT and SE of 22.5 d Bm and 18.3%, respectively, with a 20 - MHz single - carrier 256 - QAM signal. A summary of the performance and comparison with the current state of t he art is shown in Table 2 - 1 . 51 Table 2 - 1 Performance summary and comparison w ith the state - of - the - art 52 3 COMPACT QUADRATURE DIGITAL TRANSMITTER BASED ON SWITCHED - CAPACITOR RFDAC WITH LINEARIZATION TECHNIQUES In this chapter , we present a highly linear digital quadrature IQ - cell - shared TX with a small area and low power consumptio n. For the digital TX architecture, an SC RFDAC is employed [ 1 1], and an operation al example of the IQ - cell - shared SC RFDAC is demonstrated in Figure 1 - 7 and [25] [27] [33] [41][43] . The proposed digi tal TX employs three linearization techniques and can tran smit a 1024 - QAM signal with up to 40 - MHz bandwidth . The prototype of the quadrature digital TX achieves better than - 40 - dB EVM over 32 - dB P OUT range and uses neither external phase modulator n or DPD. 3.1 Overall Architecture The overall architecture of the 13 - b it d igital TX is presented in Fig ure 3 - 1 . T he digital I/Q bits are directly converted in to the corresponding RF signal by a single quadrature SC RFDAC . An IQ cell sharing with a 25% duty cycle LO signal is used [ 2 5]. 6 - b it unary cells along with 7 - b it bin ary cells are utilized t o achieve a 13 - bit resolution in a small area with low power consumption . For an RFDAC with low P OUT , chip area and power consumption a re dominated by the total number of unary/binary cells, logic gates and flip - flops, and associate d LO distribution in a less advanced CMOS technology node . Even though many u nary cells are preferred for excellent linearity, the complexity, area, and power consumption double with each additional bit. The number of unary cells can be reduced by using mo re binary cells. Besides careful layout techniques, linearity is improved significantly using on - resistance lineariz ation techniques for both switched and unswitched transistors in the DAC array with an RFDAC code - mapping technique. 53 Figure 3 - 1 . Overall architecture of the proposed 13b SC RFDAC . 54 3.2 Output Switch Linearization Techniques L inearity goals for information - dense, wideband standards such as 802.11ax , without DPD have not been attained by convention al digital TXs . A n equivalent circuit that includes unideal resistive parasitics in both switched and unswitched capacitors is illustrated in Fig ure 3 - 2. Nonlinearity is introduced if the source resistance in the Th é venin equivalent circuit , R S , changes ac cording to the number of switched cells [ 11 ]. However, if R S is either very low , or high even though constant, excellent linearity can be achieved. The combined impedance of switched/unswitched P - type metal - oxide - semiconductor ( P MOS ) and N - type metal - oxide - semiconductor ( N MOS ) transistors changing with the input codes determines R S , as illustrated Figure 3 - 3. The dynamic changes in R S are attributed to following two major factors : (1) finite switching duration with changing impedance and (2) on - resistance m ismatch between the P M OS and N MOS switches. Figure 3 - 2 . Schematic of SC RFDAC with nonlinear switch resistance . 55 In Figure 3 - 4, t wo switch linearization techniques are employed for the high P OUT region. For the switching transistors, partially overlapping clocks provide a more constant on - resistance compared to the on - resistance provided by regular clocks during switching transition s while minimizing dynamic high - impedance states to achieve better linearity. Unwanted large impedance fluctuations are avoided. Assuming a 50% duty cycle and a minimal high - impedance period, the parasitic resistance of each switch pair ( R SO ) connected to a unit capacitor is approximately ( R P + R N )/2. In a c onventional SC RFDAC in which all unswitched capacitors are connected to V GND , the ground - path parasitic resistance is a function of R N only, as illustrated Figure 3 - 3. In this design, half of the unswitched capacitors are connected to V GND and the other h alf to V DD , as illustrated in Figure 3 - 4. Thus , the R SO for each unswitched capacitor is also approximately ( R P + R N )/2. Furthermore, in differential implementation, the alternate array has exac tly the opposite connection to V DD and V GND . These techniques pr ovide enhanced switch linearity over a wide P OUT range, especially for d igital TX in older CMOS technologies with slow switches (e.g., 65 nm vs. 28 nm) or at higher operating frequencies. 56 Figure 3 - 3 . Switch impedance of the conventional SC RFDAC . 57 Figure 3 - 4 . Switch impedance of the proposed SC RFDAC. 58 3.3 Code Mapping Technique for RFDAC Linearization For a DAC, cells require segmentation into unary and binary cell groups for optimiz ing area and power consumption , while maintaining the required accuracy. The linearity of the DAC can be degraded due to the mismatch between the unary and binary cell groups a nd among the binary cells. For the digital TX with an RFDAC, nonlinearity occurs in both amplitude and phase do main owing to the mismatches. Even though the mismatches can be reduced by careful design and layout, the mismatches that are retained due to the PVT variation and imperfect phase calibration among the cells still limit the linearity of the digital TX. 3.3.1 Di gital - Code - Mapping Techniques for RFDAC Fig ure 3 - 5 demonstrates an instance of the mismatch between the unary and binary cell groups for 1 - D/2 - D DACs with 3 - b it unary cells; each coarse unary - code region (red) is divided into finer binary - code regions (blu e). At a low P OUT , the RFDAC operation involves the switching of a few unary cells and relatively more binary cells. Assuming the unary and binar y cells do not match perfectly, maximum mismatch occurs at unary cell transitions where all the binary cells ar e also switching. A n offset - mid - tread mapping technique for the RFDAC that achieves high linearity at low P OUT is introduced. A conventional mid - rise mapping [ 2 5] [ 27 ] [33] presented in Figure 3 - 6(a) has an abrupt unary code transition at the origin, which dominates nonlinearity at low P OUT . Conventional mid - tread mapping Figure 3 - 6(b) with no unary - code transition at the origin improves linearity, b ut the adjacent transitions still occur at relatively low P OUT . The low P OUT linearity is increased using the proposed offset mid - tread code - mapping method presented in Figure 3 - 6(c) wherein no unary cell transition occurs at the origin and code distances to the first transitions are doubled compared to conv entional mid - tread mapping. In a similar manner, t he 59 delay (phase) nonlinearities are reduced , as illustrated in Figure 3 - 7 . The presented mapping is especially effective for a RFDAC that does not use a conventional mixer with its attendant transmit LO lea kage and concomitant DC offset calibration. Figure 3 - 5 . E xample of linearity degradation from the mismatch between unary and binary cell groups . Figure 3 - 6 . Comparison between (a) Mid - rise, (b) mid - tread, and (c) offset mid - tread code mapping techniques for a 1 - D DAC. 60 Figure 3 - 7 . Comparison between (a) Mid - rise, (b) mid - tread, and (c) offset mid - tread code mapping techniques for a 2 - D DAC. 3.3.2 Mid - Rise and Offset Mid - Tread Code Mapping Technique s in Complex Domain As illustrated in Figure 3 - 8 , t he conventional mid - rise code mapping [25][27][33] represents the deepest PBO region by merging a single unary vector and multiple binary vectors , which are 180º OOP from each other. Therefore, the mismatch between the unary and binary vectors leads to an abrupt transiti on near the origin in the IQ plane , as illustrated in Figure 3 - 9 . In this example, for simplicity, it is assumed that there is only phase mismatch ( MIS ) between the two cell groups, and all the binary vectors are ideally matched . Unlike the conventional mid - rise technique, the proposed offset mid - tread technique represents the deepest PBO region only with the binary - weighted vectors, preventing the a brupt transition near the origin in the IQ plane as illustrated in Figure 3 - 10. Eve n if the MIS between the unary and binary cell groups in Figure s 3 - 9 and 3 - 10 are the same , the phase distortion ( ERR ) of the vector sum is considerably improved by the of fset mid - tread code mapping , as illustrated in Figure 3 - 10. The ERR is the same as MIS in the proposed offset mid - tread code mapping. 61 Figure 3 - 8 . Conventional mid - rise code mapping . 62 Figure 3 - 9 . Conventional mid - rise code mapping with a phase mismatch ( MIS ) between unary and binary cell groups. 63 Figure 3 - 10 . Offset mid - tread code mapping with a pha se mismatch ( MIS ) between unary and binary cell groups. 64 3.3.3 Implementation of RFDAC with Offset Mid - Tread Code Mapping T o implement the proposed mid - tread code mapping , a single unary vector is split into multiple bi nary - weighted vectors with the same resolu tion as the binary vectors in the SC RFDAC . Therefore, vector cancellation occurs between the split unary and corresponding binary - weighted split - unary vectors when they have 180º OOP relations. Because the split - unary vector better match es the binary vect ors than a single unary vector, the linearity at the deepest PBO region significantly improves , as shown in Figure 3 - 10 . For further enhanced line arity, a digital domain vector removal technique [2 5 ] is applied between the split - unary and binary vectors , a s illustrated in Figure 3 - 11 . Even if the split - unary vector matc h es the binary vectors better than a single unary vector, mismatches between the split - unary and binary vectors can persist . The digital domain vector removal technique completely cancels out the errors and leaves no residual mismatches by pa i ring the vector with 180º OOP relations and deactivating those cells. By employing the offset mid - tread code mapping , t he unary code of the TX output can be defined without any discontinuity at the origin in the IQ plane , and the discontinu ity due to the unary code transition shifts to the higher P OUT region. This is because the unary vector s only become activate d after both split - unary and binary vectors are fully turned on with the same phase . 65 Figure 3 - 11 . Implementation of the offset mid - tread code mapping. 66 3.4 Proposed Merged SC RFDAC Cell In addition to the area - and power - efficient unary and binary cell segmentation, the sub - circuit sharing technique between the two quadrature IQ - cell - shared SC RFDAC cells is proposed for further reduct ion of the area and power consumption. As illustrated in Figure 3 - 12 , the two quadrature IQ - cell - shared SC RFDAC cells are merged into a single cell , halving the number of the sub - circuits that operate at RF , such as digital mixers, logic gates, and signal buffers. Figure 3 - 12 . Proposed quad rature IQ - cell - shared SC RFDAC cell and its 1b IQ mixer. Because each merged SC RFDAC cell has only one IQ mixer, it cannot process the two input IQ data sets [ I , Q ] simultaneously . Therefore, only one of the two IQ data sets is selected as an input of the SC RFDAC cell by a control signal. The proposed SC RFDAC cell operation is as follows : i) If the two IQ data sets are the same, the multiplexers select any one of them , and the control signal activates both output switches in the SC RFDAC . ii) If th e two dat a sets are different 67 or iii) one of them is disabled by the 180º OOP data removal as illustrated in Figure s 3 - 13 (a) and (b), the control signal only selects the enabled IQ data set and deactivates one of the two output switches. In case ii), the u nselected IQ data set can be compensated by the reserved SC RFDAC cell with the vector switching operation as presented in [ 27 ] [33] and Figure 3 - 13 (b). iv) If both data sets are disabled, the cell is turned off , as illustrated in Figure 3 - 13 (b). Figure 3 - 13 . Examples of the proposed quadrature IQ - cell - shared SC RFDAC operation. (a) Without vector switching and (b) with vector switching. 3.5 Measurement Results The d igital TX incorporat ing all three linearization techniques is implemented in a 65 - nm CMOS. A measured constellation for single - carrier 1024 - QAM signals is presented in Figure 3 - 14 . 68 Figure 3 - 14 . Constellation and EVM vs. P OU T for 1024 - QAM signal before/after linearization techniques for high P OUT (HP) and low P OUT (LP) applied. 69 Figure 3 - 15 . EVM and constellation for an 802.11ax 20/40 MHz . 1024 - QAM OFDM signal. 70 Figure 3 - 16 . Spectra for an 80211ax 20/40 MHz 1024 - QAM OFDM signal. Additionally, measured EVM vs. P OUT , in which the separated and combined effects of the three linearization techniques are illustrated , has been shown ; EVM is improved by more than 3 dB for both high and low P OUT . At 2.2 GHz, the design demonstrates an excellent EVM of better than - 40 dB over 32 - dB P OUT range with a minimum EVM of - 46.6 dB without any DPD. For 802.11ax 20 - /40 - MHz 1024 - QAM OFDM signals w ith 12.5 - /13.1 - dB PAPR, the quadrature RFDAC - based TX demonstrates excellent EVM of - 42.5/ - 42.2 dB (Figure 3 - 15) at - 3.0 - dBm P OUT , without any DPD. The measured spectra with the 802.11ax 20 - /40 - MHz 1024 - QAM OFDM signals are demonstrated in Figure 3 - 16. Com pared to recent prior - art designs in more advanced 28 - nm CMOS technologies ( Table 3 - 1 ), the prototype Digital TX , even in a 65 - nm CMOS, consumes reduced chip area and achieves higher linearity over a greater P OUT range and wider bandwidth. A die micrograph is presented in Fig ure 3 - 17 . 71 Figure 3 - 17 . Chip micrograph. 3.6 Summary For the small and low - power digital TX solution, a compact, highly - linear quadrature digital TX that achiev es better than - 40 - dB EVM over 3 2 - dB P OUT range without any DPD is presented. High lineari ty over the complete P OUT range is achieved with three linearization techniques for minimized impedance variation and systematic enhancement in unary/binary cell utilization. This prototype in a 65 - nm CMOS occupies only 0.26 mm 2 with on - chip matching and exhibits - 42.5/ - 42.2 - dB EVM for an 802.11ax 20/40 - MHz 1024 - QAM OFDM signal at - 3 - dBm P OUT at 2.2 GHz without any DPD. 72 Table 3 - 1 Performance summary and comparison with the state - of - the - art 73 4 MULTIMODE MULTI - EFFICIENCY - PEAK DIGITAL POWER AMPLIFIER Figure 4 - 1 . I deal efficiency of the proposed multimode SCPA with a combination o f three efficiency enhancement techniques: dual - supply Class - G, transformer - based Doherty, and 2 - way TI. In this study , a multimode multi - efficiency - peak digital PA with six outstanding efficiency peaks down to 18 - dB PBO is proposed by utilizing three dif ferent efficiency - enhancement techniques, namely, Class - G, Doherty, and TI , as shown in Figure 4 - 1 . The overall efficiency can be improved without any substantial hardware burden using various techniques in different switching sequence s . D ifferent combinat ions can be accomplished using different efficiency - enhancement techniques. In the proposed SCPA with various efficiency - enhancement techniques, the Class - G technique is used to present an additional efficiency peak at 6 - dB PBO. Next, the combination of Cl ass - G and Doherty provides two additional efficiency peaks at 2.5 - and 12 - dB 74 PBO s . Finally, by using the TI technique, two additional efficiency peaks are introduced at 8.5 - and 18 - dB P BO s . Moreover, the continuous efficiency curves between the efficiency peaks are attained by the seamless transitions between the operation modes. To further boost the system - level efficiency and linearity, we propose a single - supply current - reuse Class - G switch that enables a dual - supply Class - G operation from a single suppl y without any additional supply voltage. The c onventional Class - G technique with multiple supply voltages usually entail s an additional supply voltage from extra hardware, such as exter nal PMU. An LO signal restoration technique for the TI operation is pro posed to lessen the chip area and power consumption for the LO signal distribution. 4.1 Efficiency of the Switched - Capacitor Power Amplifier with Efficiency - Enhancement Techniques Figure 4 - 2 . Schematic of the basic SCPA architecture. 75 Fig ure 4 - 2 display s a diagram of the conventional SCPA [ 1 1]. The number of capacitors switching between V DD and V SS at RF regulate s the P OUT of the SCPA. An ideal bandpass network, which is an ideal induct or in series with the capacitor array, filters the square wave and provide s a fundamental component at the o utput. The o utput voltage ( V OUT ) , output power ( P OUT ) , dynamic power dissipation in the capacitor array ( P SC ), and ideal drain efficiency ( ) are detailed in [ 1 1] and summarized as follows : where N , n , C TOT , R OPT , and Q LOAD are the total number of capacitors, number of switching capacitors, total capacitance of the capacitor array, optimum load resistance, and loaded quality factor of the matching network, respectively. In Chapter 4 - 2 , the efficienc ies of the dual - supply Cla ss - G, Doherty, and 2 - way TI SCPAs are introduced . The efficienc ies of the SCPAs with each efficiency - enhancement technique are evaluat ed and compared with one another . In Chapter 4 - 3 , a detailed theoretical analysis on the efficiency and implementation of the multimode SCPA and the manner by which these efficiency - enhancement techniques improve SCPA efficiency at PBO are presented . The efficiencies of the S CPAs with a combination of two different techniques, such as Class - G Doherty, Class - G TI, and TI Doherty are examined and compared one another to determine the optimum combination of the three techniques . For a comprehensive comparison, the efficiencies of the SCPAs are 76 calculated , including non - ideal components , such as the switching loss ( P SW ) of th e output switch with the parasitic capacitance of the output node , transformer insertion loss ( ), and output voltage division across the switch resistance ( ) due to the parasitic on - resistance ( R ON ) [ 1 1][ 32 ]. The practical DE ( ) of the SCPA with the nonideal components is expressed as where R PAR is the parasitic switch resistance and is 2 R ON for a differential configuration. In Fig ure 4 - 3, the operation s of an SCPA with dual - supply Class - G, Doherty, and 2 - way TI techniques are presented. A pair of sub - SCPAs are utilized to apply the Doherty technique employing th e main and peak PA and the 2 - way TI technique using an even number of sub - SC PAs. For a reasona ble comparison of the efficiencies between each efficiency - enhancement technique, the dual - supply Class - G SCPA is evaluated as a pair. The maximum output powers o f the three efficiency - enhancement techniques are equal if all capacitors in the capacitor arr ays are switching between V DD2 and V SS altogether. 4.1.1 Dual - S upply Class - G SCPA The operation of the dual - supply Class - G SCPA is exemplified in Fig ure 4 - 3(a) and deta iled in [ 12 ]. From 0 - to 6 - dB PBO, the supply voltages of the switching capacitors in both sub - SCPAs are successively altered from V DD2 to V DD . Preferably , V DD is precisely half of V DD2 . If all the capacitors are switching only with V DD , there is no power dissipation in the capacitor arrays , resulting in an additional efficiency peak at 6 - dB PBO. , , P SC , and P SW of the differential dual - supply Class - G SCPA with two sub - SCPAs shown in Fig ure 4 - 3(a) are stated as follows : 77 Figure 4 - 3 . SCPA operations with two sub - SCPAs with (a) dual - supply Class - G, (b) Doherty, and (c) 2 - way TI techniques. (a) can be implemented in a single SCPA, whereas (b) and (c) need two sub - SCPAs. 78 where n , C TOT , and C SW are the number of capacitors switching between V DD2 and V SS , total capacitance of the capacitor array in each sub - SCPA, and total parasitic capacitance at all switch output nodes connec ted to the capacitor array in each sub - SCPA, respectively. C SW comprises the overall junction capacitance and other parasitic capa citance at the switch output nodes . Here, C SW is presumed to be common to V DD2 and V DD operation modes in the same Class - G swi tch structure . Basically , C SW of the V DD2 and V DD operation modes can be dissimilar due to varying switch structures. P SW can be assessed with a figure of merit of the output switch ( f SW ), which is R ON C SW ) because R ON C SW is constant in a certain process technology [3 5 ]. Then , P SW is expressed as From 6 - dB to the deepest PBO, the capacitors switching bet ween V DD and V SS in both sub - SCPAs are successively unswitched as in the conventional SCPA. P SW is given by where n is the number of capacitors switching between V DD and V SS . Assuming = 0.71, = 0. 83 ( R ON = 0.1 R OPT ), and f SW = 24 GHz, the calculated , , P SC , and P SW of the Class - G SCPA 79 are presented in Fig ure 4 - 4. at 6 - dB PBO is the same as that at peak P OUT because P SW scales well with P OUT, as shown in Fig ure 4 - 4. 4.1.2 Doherty SCPA The o peration of the Doherty SCPA is shown in Fig ure 4 - 3(b) and detailed in [3 5 ]. From 0 to 6 - dB PBO, the capacitors switching between V DD2 and V SS of the peak ing PA are unswitched successively , whereas the main PA stays fully turned on. The unswitched capacito rs are connected to the signal ground. In this way, the load impedance perceived by the main and peak ing PA s is modulated from R OPT /2 to R OPT and from R OPT /2 to 0, respectively. If all capacitors in the main and peak ing SCPAs are switching with V DD2 and re main unswitched, respectively, then no power is dissipated in the capacitor arrays , resulting in an additional efficiency peak at 6 - dB PBO. V OUT , P OUT , P SC , and P SW of the Doherty SCPA presented in Fig ure 4 - 3(b) are expressed as follows : where m is the number of capacitors switching between V DD2 and V SS in the peak ing SCPA. From 6 - dB to the deepest PBO, the peak ing SCPA is fully turned off, and the capacitors switching between V DD2 and V SS in the main SCPA are sequentially unswitched , similar with the peak ing SCPA in the 0 6 - dB PBO region. P SW is given by 80 where n is the number of capacitors switching between V DD2 and V SS in the main PA. The calculated , , P SC , and P SW of the Doherty SCPA are displayed in Fig ure 4 - 4. Particularly, the efficiency at 6 - dB PBO is degraded because P SW stay s relatively high when P OUT is decreased by 6 dB, as shown in Fig ure 4 - 4. 4.1.3 2 - Way TI SCPA The operation of the 2 - way TI SCPA is shown in Fig ure 4 - 3(c) , and the underlying theory is presented in [ 40 ]. The normal 50% duty - cycle LO signal can be split into two time - interleaved 25% duty - cycle LO signals operating at half frequency, as shown in Fig ure 4 - 1. The sum of the harmonics of t he time - interleaved LO signals matches that of the normal LO signal [ 40 ]. The harmonic analysis shows that the split and time - interleaved LO signals can produce 6 dB lower P OUT without any spu rs. For example, when the normal LO signals in both sub - SCPAs ar e substituted with the time - interleaved LO signals, P OUT of the 2 - way TI SCPA decreases by 6 dB, as shown in Fig ure 4 - 3(c). If all the SCPA cells are functioning in a time - interleaved manner, then there will be no power dissipation in the capacitor arrays , resulting in an additional efficiency peak at 6 - dB PBO. The 2 - way TI operation can provide not only an additional efficiency peak but also a continuous efficiency curve between the efficiency peaks , similar with the Class - G and Doherty operations. From 0 - to 6 - dB PBO, the seamless efficiency curve can be attained by sequentially altering the toggling signals of the capacitors from the normal LO signals to the time - interleaved LO signals, as shown in Fig ure 4 - 3(c). V OUT , P OUT , P SC , and P SW of the 2 - way TI S CPA displayed in Fig ure 4 - 3(c) are expressed as follows : 81 where n is the number of capacitors switching between V DD2 and V SS with the normal LO signal in a sub - SCPA. From 6 - dB to the deepest PBO, the number of capacitors switching with the time - interleaved LO signals in both sub - SCPAs is sequentially decreased , whose operation is similar as in the conventional SCPA. P SW is given by where n is the number of capacitors switching between V DD2 and V SS with the time - interleaved LO signals in a sub - SCPA. The calculated , , P SC , and P SW of the 2 - way TI SCPA are presented in Fig ure 4 - 4. T he efficiency at 6 - dB PBO is degraded because P SW remains relati vely high when P OUT is reduced by 6 dB, as shown in Fig ure 4 - 4. 4.1.4 Evaluation of the Efficiency - Boosting Techniques and of the SCPAs with a single efficiency - enhancement technique are presented in Fig ure 4 - 4(a). The transparent and opaque solid lines represent and , respectively, and the blue, red, and green colors stand for the dual - supply Class - G, Doherty, and 2 - way TI SCPA s , respectively. T he Doherty and 2 - way TI SCPA s have similar efficiency , as discussed in Chapter 4.1.2 and 4.1 .3 . The efficiency of the conventional SCPA indicated by the gray dotted line is also presented for the comparison. Among the SCPAs, the Class - G SCPA shows the highest DE at PBO due to the lea st P SC 82 and P SW , as shown in Fig ure 4 - 4(b) and (c). P SC of the C lass - G SCPA is exactly half that of the Doherty and 2 - way TI SCPAs. For all SCPAs, there is no P SC at half of the maximum V OUT , resulting in an additional efficiency peak at 6 - dB PBO. Figure 4 - 4 . Comparison of the dual - supply Class - G, Doherty, and 2 - way TI SCPAs in terms of (a) drain efficiency, (b) dynamic power dissipation in the capacitor array ( P SC ), and (c) switching loss ( P SW ) ( Q LOAD = 1, = 0.71, = 0.83, R ON f SW = 24 GHz, and f = 2.4 GHz). For the dual - supply Class - G SCPA, in the 0 - to 6 - dB PBO region, P SW changes linearly from the maximum P SW at 0 - dB PBO to a quarter of the maximum P SW at 6 - dB PBO, representing a noteworthy improvement in P SW at PBO , as shown in the blue solid line in Fig ure 4 - 4(c). A lower P SW is attained because the supply voltage of all SCPA cells sequentially changes from V DD2 to V DD , assuming identical C SW for the V DD2 and V DD operation modes. It results in the same at 6 - dB PBO with that of the peak P OUT . From 6 - dB to the deepest PBO, P SW also decreases in proportion to V OUT from a quarter of maximum P SW to 0. Meanwhile , for the D oherty and 2 - way TI SCPA s , P SW decreases in proportion to V OUT from the 0 - dB PBO to th e deepest PBO as in the conventional SCPA , as shown in the red and green dashed lines in Fig ure 4 - 4(c), which results in a more substantial roll - off of the efficiency curve at PBO. Thus , at 6 - dB PBO is always lower than at peak P OUT in the Doherty a nd 2 - way TI SCPA s , as shown in Fig ure 4 - 4(a). 83 4.2 Output Power and Efficiency of the Multimode Switched - Capacitor Power Amplifier Two distinct effici ency - enhancement techniques can be combined to produce three additional efficiency peaks at 2.5 - , 6 - , and 12 - dB PBO [ 41 ]. T echniques A and B can be combined in two ways: a technique can be used as a local efficiency - enhancement technique , while the other technique can be used as a global one , i.e., A - based B and B - based A, as shown in Fig ure 4 - 5. In the A - based B, A and B are presented as a local and global efficiency - enhancement technique , respectively . The transition at 6 - dB PBO integrat es the change in the global efficiency - enhancement technique B, whereas the local enhancement technique A is employed within 0 6 - dB and deeper than 6 - dB PBOs. Figure 4 - 5 . Combinations of the two single efficiency - enhancement techniques: (a) A - based B and (b) B - based A. 84 4.2.1 Dual - Supply Class - G Doherty SCPA For t he dual - supply Class - G and Doherty techniques, the Class - G - based Doherty approach usin g Doherty as a global efficiency - enhancement technique was introduced in prior papers [ 15 ] and [ 41 ]. In this chapter , the Doherty - based Class - G approach is introduced, an d the two techniques are compared in terms of PBO efficiency. The SCPA operations with the two different combinations are presented in Fig ure 4 - 6(a). From 0 - to 2.5 - dB PBO, for both combinations, the supply voltages of the switching capacitors in the peak i ng PA are sequentially changed from V DD2 to V DD . When all capa citors in the main and peak ing PAs are switching only with V DD2 and V DD , respectively, there is no power dissipation in the capacitor arrays , resulting in an additional efficiency peak at 2.5 - dB PBO. From 2.5 - to 6 - dB PBO, for the Class - G - based Doherty cas e, the switching capacitors in the peak ing PA are sequentially unswitched. At 6 - dB PBO, the main and peak ing PAs are fully turned on and off respectively, demonstrating no power dissipation in t he capacitor arrays and an additional efficiency peak. Meanwhile , for the Doherty - based Class - G case, the supply voltages of the switching capacitors in the main PA are sequentially changed from V DD2 to V DD . When all capacitors in the main and peak ing PAs are switched only with V DD , there is no power dissipati on in the capacitor array s resulting in an additional efficiency peak at 6 - dB PBO. From 6 - to 12 - dB PBO, for the Class - G - based Doherty case, only the main PA operates in the Class - G mode. F or the Doher ty - based Class - G case, the main and peak ing PAs operate in Doherty configuration with only V DD supply voltage. A t 12 - dB PBO, for both cases, the main PAs are fully turned on with V DD , and peaking PAs are turned off. Therefore, no power is dissipated in the capacitor array s , resulting in an additional efficiency peak. Below 12 - dB PBO, the number of operating cells gradually decreases as in the conventional SCPA. 85 Figure 4 - 6 . SCPA op erations with four sub - SCPAs with the following combination s: (a) dual - supply Class - G and Doherty, (b) dual - supply Class - G and 2 - way TI, and (c) 2 - way TI and Doherty techniques. (a) and (b) can be implemented with two sub - SCPAs, and (c) needs four sub - SCPA s. 86 Because the SCPA operation change according to the four PBO regions, different power loss es need to be considered for each PBO region to calculate . P SC of both combinations can be calculated using ( 4 . 9) for each region. P SW of t he Class - G - based Doherty combination follows ( 4 . 11) in the 0 2.5 - dB and 6 12 - dB PBO regions, and ( 4 . 12) in the 2.5 6 - dB and deeper - than - 12 - dB PBO regions. Furthermore , P SW of the Doherty - based Class - G combination follows ( 4 . 11) and ( 4 . 12) in the 0 6 - dB and deeper - than - 6 - dB PBO regions, respectively. The calculated , P SC , and P SW of the d ual - supply Class - G Doherty SCPA are presented in Fig ure 4 - 7. 4.2.2 Dual - Supply Class - G 2 - Way TI SCPA The SCPA operations with the dual - supply Class - G and 2 - way TI are shown in Fig ure 4 - 6(b). For the dual - supply Glass - G 2 - way TI architecture, dynamic supply voltage or the dynamic voltage difference for the switching capacitors changes between V DD2 and V DD every other normal LO cycle. From 0 - to 2.5 - dB PBO, for Class - G - based TI and TI - based Class - G cases, the dynamic supply voltages for the switching capacitors are sequentially changed in a time - interleaved manner between the sub - SCPAs, as shown in F ig ure 4 - 6(b). When all capacitors in each capacitor array are switching with the same dynamic supply voltage, there is no power dissipation in the capacitor array resulting in an additional efficiency peak at 2.5 - dB PBO. From 2.5 - to 6 - dB PBO , for the Clas s - G - based TI case, the toggling signals of the capacitors operating with the dynamic supply voltage are sequentially changed to the time - interleaved LO signals toggling between V DD2 and V SS . At 6 - dB PBO, all sub - SCPAs are fully turned on with the time - inte rleaved LO signals toggling between V DD2 and V SS , and the sub - SCPAs have no power consumption in the capacitor arrays, resulting in an additional efficiency peak. Meanwhile , for the TI - based Class - G case, the tog gling signals of the capacitors operating wi th the dynamic supply voltage are sequentially changed to the normal LO signals toggling between V DD and V SS . When 87 all capacitors in the SCPAs are toggling only with the normal LO signal with V DD , no power is dis sipated in the capacitor array, resulting in an additional efficiency peak at 6 - dB PBO. From 6 - to 12 - dB PBO, for the Class - G - based TI case, the supply voltages of the switching capacitors in all sub - SCPAs are sequentially changed from V DD2 to V DD . For the TI - based Class - G case, the normal LO sign als of the capacitors are sequentially changed to the time - interleaved LO signals. At 12 - dB PBO, for both cases, the sub - SCPAs are fully turned on with the time - interleaved LO signals. Therefore, no power i s dissipated in the capacitor array, resulting in an additional efficiency peak. Below 12 - dB PBO, the number of operating cells gradually decreases as in the conventional SCPA. P SC of both cases can be calculated using ( 4 . 9) for each PBO region . The amplit ude of the toggling signal of the switching capac itors in all sub - SCPAs is sequentially changed as much as V DD . For the same reason as the P SC calculation, P SW of the Class - G - based TI case can be calculated using ( 4 . 11) in the 0 2.5 - dB and 6 12 - dB PBO regions, and ( 4 . 12) in the 2.5 6 - dB and deeper - than - 12 - dB PBO regions. Likewise, P SW of the TI - based Class - G case can be obtained using ( 4 . 11) and ( 4 . 12) in the 0 6 - dB and deeper - than - 6 - dB PBO regions, respectively. The calculated , P SC , and P SW of the d ual - supply Class - G 2 - way TI SCPA are presented in Fi g ure 4 - 7. 4.2.3 2 - Way TI Doherty SCPA The operations of the 2 - way TI Doherty SCPAs illustrated in Figure 4.6(c) are comparable to those of the dual - supply Class - G Doherty SCPAs. The transition between the normal LO and time - interleaved LO signals in the 2 - way TI Doherty SCPAs can be similarly understood as the transition between V DD2 and V DD in the dual - supply Clas s - G Doherty SCPAs presented in Chapter 4.2.1 . Here, the LO signals toggle between V DD2 and V SS . 88 The TI - based Doherty and Doherty - based TI combinations have the same P SC and P SW . P SC can be calculated using ( 4 . 20) for each PBO region. P SW of the TI - based Do herty case follows ( 4 . 21) in the 0 2.5 - dB and 6 12 - dB PBO regions and ( 4 . 22) in the 2.5 6 - dB and deeper - than - 12 - dB PBO regions. Furthermore , P SW of th e Doherty - based TI case follows ( 4 . 21) and ( 4 . 22) in the 0 6 - dB and deeper - than - 6 - dB PBO regions, respectively. The calculated , P SC , and P SW of the 2 - way TI Doherty SCPA are presented in Fig ure 4 - 7. Figure 4 - 7 . Comparison of the dual - supply Class - G Doherty, dual - supply Class - G 2 - way TI, and 2 - way TI Do herty SCPAs in terms of (a) drain efficiency, (b) dynamic power dissipation in the capacitor array ( P SC ), and (c) switching loss ( P SW ) ( Q LOAD = 1, = 0.71, = 0.83, R ON f SW = 24 GHz, and f = 2.4 GHz). 4.2.4 Multimode SCPA with the Three Efficiency - Enh ancement Techniques As shown in Fig ure 4 - 7(a), the Doherty/TI - based Class - G cases show the highest at PBO among the six combinations. The Class - G - based Doherty / TI cases also have the advantages o f the Class - G technique, but both demonstrate less PBO ef ficiency than that of the Doherty/TI - based Class - G cases, as shown in Fig ure 4 - 7(a), due to increased P SW , as shown in Fig ure 4 - 7(c). The 2 - way TI and Doherty combinations show the lowest at PBO b ecause it consumes the largest P SC and P SW due to the use of a single supply voltage V DD2 for the entire PBO region. Furthermore, among the Doherty/TI - based Class - G cases, the TI - based Class - G can be less efficient because the supply voltage changes every other normal LO cycle. 89 Figu re 4 - 8 . Multimode SCPA operation. For this reason, the Doherty - based Class - G is chosen as a base efficiency - enhancement technique , and the 2 - way TI technique is applied in the selective PBO region for a highl y - efficient multimode SCPA operation. In this design, the 2 - way TI technique is applied onl y to deeper than 6 - dB PBO because high efficiency can be achieved in the 0 6dB PBO region even without the TI considering the seamless efficiency curve between the p eaks. The combination of the three efficiency - enhancement techniques provides six efficienc y peaks at 0 - , 2.5 - , 6 - , 8.5 - , 12 - , 18 - dB PBO s . However, a total of eight efficiency peaks can theoretically be realized with a combination of the three efficiency - enhancement techniques: dual - supply Class - G, Doherty, and 2 - way TI. The operation of the multimode SCPA is illustrated in Fig ure 4 - 8, and the calculated , P SC , and P SW of the multimode SCPA are compared to those of the Class - G and Doherty - based Class - G S CPAs in Fig ure 4 - 9. 90 Figure 4 - 9 . Comparison between the multimode, Doherty - based Class - G, and Class - G SCPAs in terms of (a) drain efficiency, (b) dynamic power dissipation in the c apacitor array ( P SC ), and (c) switching loss ( P SW ) ( Q LOAD = 1, = 0.71, = 0.83, R ON f SW = 24 GHz, and f = 2.4 GHz). 4.3 Circuit Implementation A bloc k diagram of the multimode multi - efficiency - peak SCPA is shown in Fig ure 4 - 10(a). In this design, four differential sub - SCPAs are combined with a parallel series transformer. The 10 - bit digital PA consists of 5 - bit unary and 5 - bit binary cell groups for the optimized area and power consumption in a 65 - nm CMOS process. More unary bits are beneficial for better linearity over a wide P OUT range because the matching be tween the una ry - weighted cells is significantly better than that of the binary - weighted cells. However, the number of unary cells doubles with each additional unary bit, which leads to high power consumption and large area. In more advanced CMOS technolog y, a larger number of unary bits can be employed without a significant area and power consumption penalty for an improved linearity. Each sub - SCPA cell has a linear single - supply current - reuse Class - G switch. An LO signal restoration technique is proposed to r educe the area and power consumption for LO signal distribution. Fig ure 4 - 10(b) shows the operation of the prototype multimode multi - efficiency - peak SCPA. In this work, six efficiency peaks with continuous transitions are realized by combining the 91 dua l - supply Class - G, Doherty, and 2 - way TI techniques. Even if the PA operation is explained in a single - ended mode, a differ ential PA architecture is employed for an improved linearity. Moreover , the two transformer inputs are balanced because unbalanced inp uts in an unideal transformer power - combining network can result in an unideal energy loss and efficiency degradation in t he PA [ 30 ][3 5 ]. 92 Figure 4 - 10 . (a) Overall architecture and (b) operation of the pro posed multimode SCPA. 93 4.3.1 Single - Supply Current - Reuse Class - G Switch In Fig ure 4 - 11(a), a conventional dual - supply Class - G switch is presented [ 12 ]. Conventional Class - G techniques necessitate various supply voltages for multiple efficiency peaks. A supplement ary supply voltage requires an additional accurate, high - current regulator, which results in bigger complexity and system cost . Moreover , in conventional Class - G architectures, any supply voltage mismatch between multiple supply voltages can result in a li nearity degradation. The Class - G switch in Fig ure 4 - 11(b), initially proposed in [33] , can provide a high - accuracy dual - supply Class - G operation from a single high - current supply voltage, V DD2 , by dividing a Class - G cell into two, taking the average of tw o split cells at the output using two split capacitors, and reusing the current from V DD2 for V DD . As shown in Fig ure 4 - 11(b), the sinking current of the upper switches between V DD2 and V DD can be reused as the sourcing current of the lower switches betwee n V DD and V SS . Therefore, there is no high current flow required for V DD from an external PMU or v oltage supply. The current reuse occurs between the upper and lower switches and also between the differential architectures every half - RF cycle. In the propo sed prototype, reservoir capacitors are added to stabilize the virtual V DD , as shown in Fig ure 4 - 1 1(b), and the external voltage supply for V DD is removed. A s mall low - dropout ( LDO ) regulator can be used to accurately regulate V DD , but the precise control of V DD is not required due to the inherent accuracy of the proposed architecture. The proposed Class - G switch is insensitive to the supply voltage mismatch using the average of V DD2 V DD and V DD V SS for the V DD mode. Any mismatch voltage between V DD2 and V D D can be averaged and canceled out at the capacitor summing node , as shown in Fig u re 4 - 12(a) [3 3 ]. As a result, the virtual V DD does not need to be exactly half of V DD2 . Moreover , a remaining phase mismatch can be compensated through the dynamic signal delay control by employing separate 94 signal paths with different delays according to t he Class - G operation , as shown in Fig ure 4 - 12(b) [3 3 ]. Figure 4 - 11 . Class - G switch es : (a) conventional and (b) proposed switch structures . 95 ( a ) ( b ) Figure 4 - 12 . (a) Suppl y voltage mismatch insensitive Class - G switch and (b) dynamic path delay control for phase mismatch compensation . 96 4.3.2 LO Signal Distribution Figure 4 - 13 . LO signal distribution: (a) c onventional and (b) proposed the LO signal restoration technique. The LO signal distribution is important to the linearity of the time - interleaved digital PA and need s additional area and power consumption. Distributing normal LO signal and time - interleave d LO signals necessitates additional area and power consumption, as shown in Fig ure 4 - 13(a) [ 40 ]. 97 In this prototype, the LO signal restoration technique is suggested to realize a small area and low power consumption, as shown in Fig ure 4 - 13(b). A normal LO signal is synthesized from the two time - interleaved LO signals at each SCPA cell. In this case, the area and power consumption can be significantly reduced because only the time - interleaved LO signals need to be distributed. For an accurate normal LO sign al synthesis and linear TI operation, a precise timi ng matching between the time - interleaved LO signals is required. The timing mismatches between the time - interleaved LO signals cause undesired in - band and out - of - band nonlinearities. Because the time - inte rleaved LO signals are generated from the same input LO signal, the precise matching between the time - interleaved LO signals can be realized with a symmetrical signal path design. 4.4 Measurement Results Figure 4 - 14 . Chip micrograph. 98 Fig ure 4 - 14 shows a chip micrograph of the fully integrated multimode multi - efficiency - peak SCPA. The prototype fabricated in a 65 - nm RF CMOS process occupies 2.1 × 1.6 mm 2 , including a power - combing trans former, four sub - SCPAs, a low - voltage differential signaling (LVDS) receiver, time - interleaved LO signals generator, decoupling capacitors, and wire - bonding pads. Four differential SCPAs are combined with a parallel series transformer to realize a Doherty operation and 10 - bit resolution. Only a single supply voltage of 2.5 V is used to generate an output power in the Class - G switch . 4.4.1 CW Signal Measurement The DE, AM AM, and AM PM are measured with a continuous - wave (CW) signal at 2.4 GHz. The measured DE ve rsus P OUT is shown in Fig ure 4 - 15. The prototype SCPA delivers a peak P OUT of 30.0 dBm with a peak DE of 40.2% at 2.4 GHz. With an efficient combination of the dual - supply Cla ss - G, Doherty, and 2 - way TI techniques, six efficiency peaks with continuous effi ciency curves between the peaks are realized down to 18 - dB PBO. The prototype achieves DE (normalized DE) of 40.2% (100%), 37.9% (94.3%), 38.8% (96.3%), 36.3% (90.2%), 29.4% ( 73.0%), and 19.7% (48.9%) at 0 - , 2.5 - , 6 - , 8.5 - , 12 - , and 18 - dB PBOs, respectivel y. The proposed techniques substantially improve the efficiency both at and between the peaks for a wide range of P OUT . Further DE enhancement can be realized in advanced fine line CMOS technology due to the less parasitic capacitance, less on - resistance, and reduced crowbar current in switches. The measured AM AM and AM PM versus the normalized input code are shown in Fig ure 4 - 16. Due to the seamless transitions between the operation modes, there is no abrupt nonlinearity. The measured AM PM distortion is less than ±1º, indicating an excellent linearity. 99 Figure 4 - 15 . Measured DE vs. P OUT for a CW signal. Figure 4 - 16 . Measured AM AM and AM PM vs. normalized input code for a CW signal. 100 4.4.2 Modulated Signal Measurement Figure 4 - 17 . EVM vs. average P OUT measured with 10 - MHz 64 - QAM OFDM signal. Fig ure 4 - 17 illustrates the constellation and EVM versus the average P OUT measured with a 10 - MHz 64 - QAM OFDM signal with a PAPR of 10.9 dB. The prototype demonstrates an excellent linearity better than 40 - dB EVM over around 25 - dB P OUT range without any digital pre - distortion (DPD). It achieves 41.7 - dB EVM at an average P OUT o f 19.1 dBm, and the EVM is degraded above 19.1 - dBm due to the hard clipping of the modulated signal. 101 Figure 4 - 18 . EVM vs. average P OUT measured with a 10 - MHz single - carrier 1024 - QAM signal. Fig ure 4 - 18 dem onstrates the measured constellation and close - in frequency spectrum with a 10 - MHz single - carrier 1024 - QAM signal with 6.8 - dB PAPR. The prototype attains an excellent EVM of 44.5 dB and a clear constellation at a high average P OUT of 23.2 dBm without any DPD. It shows no sign of any substantial AM AM and AM PM distortion s in conventional 102 transconductance - based PAs. The measured data evidently prove the excellent linearity of the single - supply current - reuse Class - G technique and digital PA architecture base d on SCPA. 4.5 Summary A multimode multi - efficiency - peak SCPA is implemented in a 65 - nm RF CMOS process. A multimode operation is proposed to attain multiple efficiency peaks with continuous efficiency curves between the peaks in the PBO region. The combinati on s of the du al - supply Class - G, Doherty, and 2 - way TI techniques are employed in an efficient manner to maximize PBO efficiency. Six outstanding efficiency peaks are realized . A single - supply current - reuse Class - G switch is presented to allow a highly line ar Class - G op eration without any external supply voltage regulators. Moreover , a n LO signal restoration technique is suggested to lessen the power dissipation and area for the LO distribution. The normalized DE remains above 50% over around 18 - dB P OUT rang e. The measur ed AM PM distortion is less than ±1º, and the measured EVM is better than 40 dB over around 25 - dB P OUT range for an OFDM signal even without any DPD. A summary of the performance and comparison of the proposed SCPA with other state - of - the - art is shown in Table 4 - 1 . 103 Table 4 - 1 Performance summary and comparison with the state - of - the - art 104 5 CONCLUSION This study demonstrates very promising solutions of compact, highly efficient, and highly linear di gital TX systems for modern communication standards. For a high P OUT , highly efficient and linear quadrature digital TX solution , a dual - supply Class - G IQ - cell - shared SCPA architecture is realized in a 65 - nm CMOS process . The proposed MCS technique enable s t he Class - G operation in the quadrature IQ - cell - shared SCPA architecture and significantly improves PBO efficiency. The proposed Class - G linearization technique s enhance t he Class - G SCPA linearity by compensating the amplitude and phase mismatches betwee n the two Class - G modes. The prototype with the proposed Class - G switch achieves EVM better than - 32 dB without any DPD over ± 5% V DD variation while delivering an average P OUT and SE of 22.5 dBm and 18.3%, respectively, with a 20 - MHz single - carrier 256 - QAM signal. For a low P OUT , c ompact, highly - linear digital TX solution , an IQ - cell - shared SC RFDAC with linearization techniques for minimized output impedance variation and systematic enhancement in unary/binary cell utilization is implemented in a 65 - nm CMO S process. The proposed linearization techniques fundamentally enhance the TX dynamic range by improving the TX linearity in both high and low P OUT region s . T he on - resistance linearization techniques for the output switches and the offset mid - tread code ma pping technique improve the TX linearity in the high and low P OUT region s , respectively . T he prototype achieves better than - 40 - dB EVM over 30 - dB P OUT range with a 20 - MHz single - carrier 1024 - QAM signal without any DPD. T he prototype occupies only 0.26 mm 2 , including an on - chip matching by sharing the sub - circuits between the two RFDAC cells . 105 For a highly - efficient, highly - linear polar digital TX solution , a multimode multi - efficiency - peak SCPA architecture is designed and fabricated in a 65 - nm CMOS process. T he multimode operation maximizes the PBO efficiency by efficiently combining dual - supply Class - G, Doherty, and 2 - way TI techniques. The seamless transitions between the operation modes result in six efficiency peaks with a continuous efficiency c urve bet ween the peaks in the PBO region. The proposed single - supply current - reuse Class - G switch enables highly linear and efficient Class - G operation without any external PMU. Additionally , the LO - signal - restoration technique minimizes the power dissipation and area for the LO signals distribution. T he normalized DE remains greater than 50% over around 18 - dB P OUT range. The AM PM distortion is less than ±1º, and the EVM is better than - 40 d B over around 25 - dB P OUT range for a 10 - MHz 64 - QAM OFDM signal without any DPD. The proposed digital TX and PA solutions demonstrate very promising results for future TX architectures with excellent efficiency and linearity . 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