ADVANCED ELECTRIC VEHICLE DRIVES TOPOLOGY AND CONTROL

By

Ameer Janabi

A DISSERTATION

Submitted to

Michigan State University

in partial fulfillment of the requirements

for the degree of

Electrical Engineering - Doctor of Philosophy

2021

ADVANCED ELECTRIC VEHICLE DRIVES TOPOLOGY AND CONTROL

ABSTRACT

By

Ameer Janabi

In the thesis, the author focuses on solving three problems related to voltage source inverter

(VSI) in general and VSI used in an electric and hybrid electric vehicle in particular.

The first problem is related to the fact that using pulse width modulated (PWM) voltage to

supply the motor causes a common-mode voltage (CMV) at the motor bearings. To solve this

problem, a hybrid space vector PWM is proposed that reduces the CMV amplitude and frequency

to the maximally allowable extent. This can be done by utilizing a special switching sequence that

takes into consideration the phase angle between the load voltage and current.

The second problem is related to the optimal PWM sequence that allows the elimination of

selected low order odd harmonics. Previously, this optimization problem used to be solved using

an offline approach. There have been several attempts to implement the control algorithm in real-

time. All of the proposed methods in the literature, at some points, use initial guessing or iteration.

This leads to an online approach with non-deterministic execution time and with the possibility to

fail to reach convergence. The author shows that the optimal PWM can be implemented in real-

time with deterministic execution time and without compromise. Furthermore, a significantly more

generalized algorithm is proposed that allows the modulation of selected harmonics rather than

merely eliminating them. The opportunities opened up by the generalized algorithm are limitless

and currently being explored. The potential applications include wireless charging and digital

wave generation. Modulation of several harmonics to arbitrarily prescribed values is impossible to

implement using an offline approach.

The third problem is to address the limitations associated with the fact that VSI is a buck

converter. For applications where the available dc voltage is limited, an additional dc-dc boost

converter is needed to obtain the desirable ac voltage. Commercial hybrid vehicles typically use an

inductor based dc-dc converter to boost the voltage. At higher power, the dc-dc converter becomes

inefficient. Therefore, the application of the boost stage is seen only in hybrid vehicles with a

battery of a few kWh. The author proposes a new family of bidirectional dc-ac boost converters

that utilizes a switched-capacitor network to boost the voltage. The switched-capacitor and the

inverter are modulated as one unit, which allows the removal of the large output filtering capacitor

and the reverse blocking diode required by a typical switched-capacitor converter. This effort

results in extending the power level of switched-capacitor based converters from existing sub kW

range to tens kW and beyond with much mitigated penalty on device utilization.

Copyright by
AMEER JANABI
2021

For my parents

Hussein and Zahrah

v

ACKNOWLEDGMENTS

First of all, I would like to express my appreciation to my advisor, Dr. Bingsen Wang, for his

guidance and support during my study at Michigan State University. Working with Dr. Wang for

the past six years was one of the most rewarding experiences of my life.

I would also like to thank Dr. Elias Strangas, Dr. Joydeep Mitra, and Dr. Guoming Zhu for

their support and for serving as part of my committee.

I owe a big thanks to Dr. Wei Qian for her valuable technical guidance and support.

I also would like to thank my colleagues within the power group at Michigan State University,

Abdulrhman Alshaabani, Shukai Wang, Jacob Buys, Matt Meier, Dr. Xiaorui Wang, Dr. Yunting

Liu, Dr. Deepak Gunasekaran, Dr. Ujjwal Karki, Dr. Yaqub Mahnashi and other lab members who

have helped me over the years at MSU.

I would like to extend my thanks to my friends, Mohammad Al-Rubaiai, Maher Al-Sahlany,

Khalil Sinjari, Montassar Sharif, Hussam Jabbar, Mohaned Alzuhiri, Ali MH Al-Hajjar, and Petros

Taskas.

Last but not least, I would like to thank my parents, my brothers and my sisters for their constant

support and encouragement along the way. Special thanks to Emily Higuera for her company and

for editing my research articles.

vi

TABLE OF CONTENTS

LIST OF TABLES .

.

LIST OF FIGURES .

.

.

.

.

Chapter 1 Introduction .

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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ix

x

1

. . . . . . . . . . . . . .

.
2.2.1 HSVPWMS I .
.
2.2.2 HSVPWMS II .
2.2.3 HSVPWMS III
.
2.2.4 HSVPWMS IV .

2.1 Conventional SVPWM .
2.2 Hybrid Space Vector Pulse With Modulation Synthesis

Chapter 2 Hybrid SVPWM Scheme to Minimize the Common-mode Voltage Frequency
3
and Amplitude in VSI Drives . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
.
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Dead-time Effect and Narrow CMV Pulse Avoidance . . . . . . . . . . . . . . . . 13
2.4 Proposed commutation Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5 Performance Analysis .
. 21
2.5.1 Common-mode Voltage Characteristics
. . . . . . . . . . . . . . . . . . . 21
2.5.2 Harmonic Distortion Factor . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5.3 DC-Link Current Harmonics . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5.4
Switching Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Experimental results .

.

.

.

.

Chapter 3 Model Predictive Approach to Control the Amplitude and Frequency of

CMV in VSI Drives .

3.1.2.1 Adding Weighting Factor
3.1.2.2

3.1 Conventional Model Predictive Common-mode Reduction Methods

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
. . . . . . . . 45
3.1.1 Reducing the Sampling Time . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.1.2 Cost Function Redesign (CFR-MPC) . . . . . . . . . . . . . . . . . . . . . 48
. . . . . . . . . . . . . . . . . . . . . 48
Frequency Domain Control of the Cost Function . . . . . . . . . 49
. . . . . . . . . . . . . . . . . . . . . . 50
3.1.3.1 Using Only the Active Vectors . . . . . . . . . . . . . . . . . . . 50
3.1.3.2 Using Only the Odd or the even Active Vectors . . . . . . . . . . 50
3.2 Proposed Selective Voltage-sets Commutation MPC Method . . . . . . . . . . .
. 51
3.3 Bearing Current Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4 Experimental Results .

3.1.3 Zero-vectors Removal (6V-MPC)

Chapter 4 Generalized Chudnovsky Algorithm for Real-time PWM Selective Harmonic

Elimination/Modulation: Two-Level VSI Example . . . . . . . . . . . . . . . 69
4.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.2 The Proposed Real-Time Selective Harmonic Elimination . . . . . . . . . . . . . . 72

Introduction .

. .

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vii

4.2.1 Converting the Transcendental Equations to Algebraic Equations . . . . . . 73
4.2.2 Converting the Algebraic Equations to a Single Polynomial . . . . . . . . . 74
4.2.3 Obtaining the Optimal Switching Angles . . . . . . . . . . . . . . . . . .
. 81
. . . . . . . . . . . 82
4.3 Comparison with the Offline Selective Harmonic Elimination
4.4 Selective Harmonic Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.5 Experimental Results .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

.

Introduction .

. .

.
.

Chapter 5 Switched-Capacitor Voltage Boost Converter for Electric and Hybrid Elec-

.

.

tric Vehicle Drives .
.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
.
5.1
. 102
5.2 Space Vector Pulse Width Modulation of SC Converter
5.3 Analysis of the Capacitor Voltage Ripple and the Charging Current Using SVPWM 107
5.4 Carrier-based Modulation of SC Converter . . . . . . . . . . . . . . . . . . . . . . 117
5.5 Simulation Results, Experimental Test, and Hardware Design . . . . . . . . . . . . 118

. . . . . . . . . . . . . .

Chapter 6 Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . 132

BIBLIOGRAPHY .

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

viii

LIST OF TABLES

Table 2.1 The feasible voltage vectors and the corresponding DMV and CMV.

. . . . .

5

Table 2.2 The vector combinations used in the three segments of each sector using

HSVPWMS I.

.

.

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2.3 The vector combinations used in the three segments of each sector using

HSVPWMS II.

.

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2.4 The vector combinations used in the three segments of each sector using

HSVPWMS III.

.

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 2.5 The vector combinations used in the three segments of each sector using

HSVPWMS IV.

. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 2.6 Effective switching states in case of only odd modulation. . . . . . . . . . . . 16

Table 2.7 Effective states in case of only even modulation. . . . . . . . . . . . . . . . . 17

Table 2.8 Effective switching frequency fs defined as a function of the modulation index. 33
Table 3.1 Voltage vectors and the corresponding differential-mode voltage vdm and

CMV vcm amplitudes.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 3.2 Experimental test patameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 4.1 Summary of the comparison between the conventional offline method and the

proposed RTSHE.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 5.1 The generation of the reference waveforms from the dwell times in each sector.118

ix

LIST OF FIGURES

Figure 2.1 Three-phase voltage source inverter. . . . . . . . . . . . . . . . . . . . . . .

Figure 2.2 Eight stationary vectors in the complex plane for a VSI.

. . . . . . . . . . .

Figure 2.3 Sector I is divided into three segments: (a) odd triangle, (b) odd-even trian-

gle, and (c) even triangle.

. . . . . . . . . . . . . . . . . . . . . . . . . . .

6

6

8

Figure 2.4 Vector synthesis for HSVPWM I of (a) odd triangle, (b) odd-even triangle,

and (c) even triangle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2.5 Vector synthesis of odd-even triangle for HSVPWMS II.

. . . . . . . . . . . 12

Figure 2.6 Vector synthesis of odd-even triangle for HSVPWMS III.

. . . . . . . . . . 13

Figure 2.7 Vector synthesis of odd-even triangle for HSVPWMS IV. . . . . . . . . . . . 13

Figure 2.8 Dead-time effect on CMV. During the dead-times, the CMV is dependent on

the sign of the three-phase load current, CMV ∈ {Vdc,

3 ,−Vdc
Vdc

3 ,−Vdc}. . 14

Figure 2.9 During td13 and ia > 0, ib < 0, and ic > 0, the CMV is equal to −Vdc
3 .
Figure 2.10 During td13 and ia > 0, ib > 0, and ic < 0, the CMV is equal to −Vdc.
Figure 2.11 During td13 and ia < 0, ib < 0, and ic > 0, the CMV is equal to Vdc
3 .
Figure 2.12 There are six regions in which the three-phase load currents do not change

. . . 16

. . 15

. . 15

sign. .

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.

.

.

.

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2.13 The current sectors (in which the three-phase load currents do not change
sign) in relation to the voltage vectors when (a) P F = 1 and (b) P F = 0.866
lagging. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

. .

.

. .

Figure 2.14 Modified control block diagram to account for the current sectors position.

. 19

Figure 2.15 The commutation sequences that do not cause a change in CMV during
dead-time intervals. Each current sector has two safe sequences: one for
only odd and one for only even syntheses. This allows the use of only odd
and only even vectors without any constraints imposed by the P F . . . . . . . 20

x

Figure 2.16 Common-mode voltage waveforms and their corresponding frequency spec-

trum using the regular SVPWM. . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 2.17 Common-mode voltage waveforms and their corresponding frequency spec-

trum using HSVPWMS I.

. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 2.18 Common-mode voltage waveforms and their corresponding frequency spec-

trum using HSVPWMS II.

. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 2.19 Common-mode voltage waveforms and their corresponding frequency spec-

trum using HSVPWMS III.

. . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 2.20 Common-mode voltage waveforms and their corresponding frequency spec-

trum using HSVPWMS IV.

. . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 2.21 The fundamental component of the CMV. The fundamental frequency of the
CMV in SVPWM is equal to fc = 5 kHz. Whereas in HSVPWMS methods
the frequency of the fundamental component is equal to 3f1 = 180 Hz.

. . . 28

Figure 2.22 Harmonic distortion factor for the HSVPWMS methods compared with the

conventional PWMS methods. . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 2.23 DC-link current ripple coefficient (Kdc) for various PWM methods. . . . . . 31
. 33
Figure 2.24 Switching on and off events for an IGBT.

. . . . . . . . . . . . . . . . . .

Figure 2.25 Switching losses for the HSVPWMS methods compared with the conven-

tional PWM methods.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 2.26 Experimental results for CMV at M I = 0.75 of 1 - HSVPWMS I, 2 - HSVP-

WMS II, 3 - HSVPWMS III, 4 - HSVPWMS IV.

. . . . . . . . . . . . . . . 35

Figure 2.27 FFT of the CMV waveforms of 1 - HSVPWMS I, 2 - HSVPWMS II, 3 -
. . . . . . . . . . . . . . . . . . . . .

HSVPWMS III, 4 - HSVPWMS IV.

. 36

Figure 2.28 Experimental results of CMV waveforms at M I = 0.85 for 1 - SVPWM, 2
- HSVPWMS I, 3 - HSVPWMS II, 4 - HSVPWMS III, 5 - HSVPWMS IV,
6 - AZSPWM1-2, 7 - NSPWM, 8 - AZSPWM3, and 9 - DPWM1. . . . . .

. 37

Figure 2.29 FFT of the CMV waveforms at M I = 0.85 for 1 - SVPWM, 2 - HSVP-
WMS I, 3 - HSVPWMS II, 4 - HSVPWMS III, 5 - HSVPWMS IV, 6 -
AZSPWM1-2, 7 - NSPWM, 8 - AZSPWM3, and 9 - DPWM1. . . . . . . . . 38

Figure 2.30 Experimental results of CMV waveforms at M I = 1 for 1 - SVPWM, 2 -
HSVPWMS I, 3 - HSVPWMS II, 4 - HSVPWMS III, 5 - HSVPWMS IV, 6
- AZSPWM1-2, 7 - NSPWM, 8 - AZSPWM3, and 9 - DPWM1. . . . . . . . 39

xi

Figure 2.31 FFT of the CMV waveforms at M I = 1 for 1 - SVPWM, 2 - HSVPWMS I,
3 - HSVPWMS II, 4 - HSVPWMS III, 5 - HSVPWMS IV, 6 - AZSPWM1-2,
7 - NSPWM, 8 - AZSPWM3, and 9 - DPWM1. . . . . . . . . . . . . . . . . 40

Figure 2.32 Experimental results of the load current ia(t) at (a) M I = 0.85 and (b)

M I = 1 for 1 - SVPWM+20A, 2 - HSVPWMS I+15A, 3 - HSVPWMS II+10A,
4 - HSVPWMS III+5A, 5 - HSVPWMS IV, 6 - AZSPWM1-2-5A, 7-NSPWM-
10A, 8-AZSPWM3-15A, and 9-DPWM1-20A.

. . . . . . . . . . . . . . . . 41

Figure 2.33 Experimental results of (a) the HSVPWMS II without implementing the safe
commutation algorithm. During the dead-times the effective switching state
could be one of the zero vectors V(0,0,0) or V(1,1,1) and the CMV will be
similar to type 1, or it could be similar to type 2 when the effective switch-
ing state result in one of the odd or even vectors; (b) the HSVPWMS II
with implementing the safe commutation algorithm, both type 1 and type 2
unwanted transitions are successfully avoided. M I = 0.85.

. . . . . . . . . 42

Figure 3.1 Three-phase voltage source inverter. . . . . . . . . . . . . . . . . . . . . . . 46

Figure 3.2 Model predictive CMV reduction methods diagram.

. . . . . . . . . . . .

. 48

Figure 3.3 The highlighted region is the available linear region in: (a) using the even

vectors only; (b) using the odd vectors only. . . . . . . . . . . . . . . . . . . 50

Figure 3.4 Control block diagram of the three-phase VSI with SVS-MPC controller.

. . 52

Figure 3.5 Load current prediction.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 3.6 Objective function in a form of mean square error (MSE).

. . . . . . . . . . 52

Figure 3.7 Simulation results of MPC-SC at 60 Hz fundamantal frequency. Ts = 10 µs,

1/nTs = 5 kHz, Doe = 50%. Load current THD= 4.2%.

. . . . . . . . . . 54

Figure 3.8 Simulation results of MPC-PWM at 60 Hz fundamantal frequency. Ts =
10 µs, CMV reference amplitude= 0.45, CMV carrier frequency = 50 kHz.
CMV carrier phase-shift= −8o. Load current THD= 4%.

. . . . . . . . . . 55

Figure 3.9 The trade-off between the reference amplitude (RA) and the THD of the
load current. As the reference amplitude increases the CMV amplitued ad
the reference frequency increases with some sucrifice on the load current
THD. M I = 1. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

.

Figure 3.10 The transient behavior of the load current during a step change from 5 A

(M I = 0.45) to 10 A (M I = 0.9) (a) MPC-SC and (b) MPC-PWMC. . . . . 57

Figure 3.11 Equivelent circuit of the main capacitances of an induction machine or PM

machine that are important in high frequencies.

. . . . . . . . . . . . . . . . 57

xii

Figure 3.12 Equivalent circuit of EDM current discharge.

. . . . . . . . . . . . . . . . . 58

Figure 3.13 Comparsion of bearing currents ib of the conventional MPC methods and
the proposed selective voltage set MPC methods. Vdc = 250 V, f = 60 Hz,
and M I = 0.9.. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

.

Figure 3.14 Frequency spectrum of CMV and the load current THD with changing the

weighting factor λ.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 3.15 The experimental setup.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 3.16 Experimental results of MPC method load current ia,b,c, CMV vcm, and

FFT of CMV. .

. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 3.17 Experimental results of CFR-MPC method load current ia,b,c, CMV vcm,

and FFT of CMV. .

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 3.18 Experimental results of 6V-MPC method load current ia,b,c, CMV vcm, and

FFT of CMV. .

. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 3.19 Experimental results for the proposed MPC-SC method load current ia,b,c,

CMV vcm, and FFT of CMV.

. . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 3.20 Experimental results for the proposed MPC-PWMC method load current

ia,b,c, CMV vcm, and FFT of CMV.

. . . . . . . . . . . . . . . . . . . . . 67

Figure 3.21 Load Current transient behaviour during a step change from 3 A to 6 A. . . . 68

Figure 4.1 Two-level voltage source inverter drive.

. . . . . . . . . . . . . . . . . . . . 70

Figure 4.2 Illustration of obtaining the value of the optimal switching angles by solving

the polynomial in real-time.

. . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 4.3 Matlab script solving the example. . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 4.4 The zero crossing occurs at the optimal switching angle.

. . . . . . . . . .

. 81

Figure 4.5 Numerical results show a comparison between the proposed real-time method
and the conventional offline method eliminated harmonics magnitude when
eliminating the first three odd harmonics. The results shown are in two fun-
damental frequencies 60 Hz and 120 Hz.

. . . . . . . . . . . . . . . . . . . 84

Figure 4.6 Numerical results show a comparison between the proposed real-time method
and the conventional offline method eliminated harmonics magnitude when
eliminating the first five odd harmonics. The results shown are in two fun-
damental frequencies 60 Hz and 120 Hz.

. . . . . . . . . . . . . . . . . . . 85

xiii

Figure 4.7 Total harmonic content divided by the fundamental component for both the
offline SHE and the proposed real-time SHE. Note that this number does
not change by changing the number of eliminated harmonics, instead, the
harmonics get shifted to the right of the last eliminated harmonic and this
result in a better load current performance. This is due to the fact that higher-
frequency harmonics face higher impedance in an inductive load.

. . . . . . 86

Figure 4.8 Experimental results of the line current ia, line-neutral voltage va and the
spectrum of va using the proposed real-time algorithm. The fundamental
frequency is 60 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 4.9 Experimental results of the line current ia, line-neutral voltage va and the
spectrum of va using the conventional offline method. The fundamental
frequency is 60 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 4.10 Experimental results of the line current ia, line-neutral voltage va and the
spectrum of va using the proposed real-time algorithm. The fundamental
frequency is 120 Hz.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 4.11 Experimental results of the line current ia, line-neutral voltage va and the
spectrum of va using the conventional offline method. The fundamental
frequency is 120 Hz.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 4.12 Experimental results of RTSHE load current ia and the phase voltage va at

a fundamental frequency of 60 Hz.

. . . . . . . . . . . . . . . . . . . . . . 92

Figure 4.13 Experimental results of RTSHE load current ia and the phase voltage va at

a fundamental frequency of 120 Hz. . . . . . . . . . . . . . . . . . . . . . . 92

Figure 4.14 The transient behavior of the load current ia and the phase voltage va when
changing the switching frequency. . . . . . . . . . . . . . . . . . . . . . .

. 93

Figure 4.15 The transient behavior of the load current ia and the phase voltage va when

changing MI.

.

.

.

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 4.16 The transient behavior of the load current ia and the phase voltage va when

changing both fundamental and switching frequencies at the same instant. . . 95

Figure 4.17 The transient behavior of the proposed RTSHE load currents ia, ib, and ic
when a concurrent change in the fundamental and switching frequencies are
randomly requested. No current spike is detected. . . . . . . . . . . . . . . . 96

Figure 4.18 The transient behavior of the conventional offline SHE load currents ia, ib,
and ic when a concurrent change in the fundamental and switching frequen-
cies are randomly requested. . . . . . . . . . . . . . . . . . . . . . . . . . . 97

xiv

Figure 4.19 The real-time controllability of the third harmonic: (a) vb3

4 ∗ Vdc/2 = π0.4
πb3

4

=

4 ∗Vdc/2 =
πb3
∗ 50 = 15.71 V, and

π0.2

4
(c) vb3

∗ 50 = 7.855 V, (b) vb3
4 ∗ Vdc/2 = π0.6
πb3

=

=

4 ∗ 50 = 23.565 V. . . . . . . . . . . . . . . . 98

Figure 5.1 The schematics of (a) the conventional inverter-converter topology and of

(b) the proposed switched-capacitor voltage boost converter.

. . . . . . . . . 101

Figure 5.2 (a) Charging and (b) discharging equivalent circuits of SC converter. . . . . . 104

Figure 5.3 Space vector hexagon for SC converter with the annotated switching states
in the order of (Sg, Sa, Sb, Sc). The vector synthesis is a graphical repre-
sentation of the algebraic summation and not the actual sequence in which
the states are applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 105

Figure 5.4 Illustration of the switching sequence of SVPWM in sector I.

. . . . . . . . 108

Figure 5.5 The relationship between the location of ∆Vmax and the power factor angle
φ. φ does not change the value of ∆Vmax; it only changes the location
within the sector in which ∆Vmax occurs.

. . . . . . . . . . . . . . . . . . 111

Figure 5.6 The charging time tch with respect to the minimum charging time tch−min

wtih diffrent values of Mi, A = 0.3. . . . . . . . . . . . . . . . . . . . . . . 111

Figure 5.7 The charging time tch with respect to the minimum charging time tch−min

wtih diffrent values of Mi, A = 0.5. . . . . . . . . . . . . . . . . . . . . . . 112

Figure 5.8 The charging time tch with respect to the minimum charging time tch−min

wtih diffrent values of Mi, A = 0.8. . . . . . . . . . . . . . . . . . . . . . . 112

Figure 5.9 The charging time tch with respect to the minimum charging time tch−min

wtih diffrent values of Mi, A = 0.9. . . . . . . . . . . . . . . . . . . . . . . 113

Figure 5.10 Simulation results of one fundamental cycle showing the behavior of the
charging current icap with respect to the instantaneous voltage drop across
the capacitor vcap.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

.

Figure 5.11 (Zoom in of Fig. 5.10); Simulation results of the charging current showing
R ≈ 18 A;

that when the ∆V ≈ 0.02 V the charging current icap = ∆V
given that the series resistance in the simulation model is set to R = 0.0011 Ω.116

Figure 5.12 The reference waveforms synthesized from the SVPWM algorithm, Mi =
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.5774, A = 0.

.

.

. 119

Figure 5.13 The reference waveforms synthesized from the SVPWM algorithm, Mi =

0.5774, A = 0.25.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

xv

Figure 5.14 The reference waveforms synthesized from the SVPWM algorithm,Mi =
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.5774, A = 0.5.

.

.

. 120

Figure 5.15 The reference waveforms synthesized from the SVPWM algorithm, Mi =

0.5774, A = 0.75.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 5.16 The carrier-based modulation of the SC converter.

. . . . . . . . . . . . .

. 121

Figure 5.17 The carrier-based modulation of the SC converter. Abstemious mode, Mi =

0.5 and A = 0.

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

.

.

Figure 5.18 The carrier-based modulation of the SC converter. Gluttonous mode, Mi =

0.5 and A = 0.5.

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 5.19 Isometric view of the SC converter layout.

. . . . . . . . . . . . . . . . . . 125

Figure 5.20 Exploded view of the SC converter layout.

. . . . . . . . . . . . . . . . . . 126

Figure 5.21 Exploded view of the SC converter layout.

. . . . . . . . . . . . . . . . . . 127

Figure 5.22 Experimental results of (a) abstemious mode, Mi = 0.5 and A = 0.
Figure 5.23 Experimental results of gluttonous mode, Mi = 0.5774 and A = 0.5.
Figure 5.24 Experimental results of abstemious mode, Mi = 0.5 and A = 0. . . . . . . . 128
. 129
Figure 5.25 Experimental results of gluttonous mode, Mi = 0.5774 and A = 0.5.
Figure 5.26 Experimental results showing the charging current with respect to the switch-

. . . . . 127

. . . . 128

. . .

ing functions of the SC converter. (Ch2: 1 A/V).

. . . . . . . . . . . . . . . 130

Figure 5.27 Experimental results showing the switching transient of the SC converter at

1 kHz switching frequency. (Ch2: 1 A/V). . . . . . . . . . . . . . . . . . . . 131

xvi

Chapter 1

Introduction

Over the last 800,000 years, the global average atmospheric carbon dioxide (CO2) levels, as in-

dicated by the ice-core data, have fluctuated between 170 and 300 parts per million by volume

(ppmv). CO2 in 2018 was 407.4 ppmv, with a range of uncertainty of plus or minus 0.1 ppmv.

Carbon dioxide levels today are higher than at any point in at least the past 800,000 years.

The way the climate reacts is also complex; The main reason is that climate is a sum of three

contributing factors: cyclical effect, random noise, and anthropic activities (human activities). If

the anthropic term becomes significant, it drowns out the other two terms, and it would be too

late to do anything. The strict correlation between the rise of greenhouse gasses and the rise of

temperature is a well-understood phenomenon since 1824.

In the united states, the primary contributor of greenhouse emissions is transportation (29% in

2017). The largest sources of transportation-related greenhouse gas emissions include passenger

cars and light-duty trucks, including sport utility vehicles, pickup trucks, and minivans. These

sources account for over half of the emissions from the transportation sector. The remaining

greenhouse gas emissions from the transportation sector come from other modes of transporta-

tion, including freight trucks, commercial aircraft, ships, boats, and trains, as well as pipelines and

lubricants.

Form this stems the unique importance of vehicle electrification. EVs typically produce fewer

1

life-cycle emissions than conventional vehicles because most emissions are lower for electricity

generation than burning gasoline or diesel. The exact amount of these emissions depends on the

electricity mix, which varies by geographic location.

One important factor of expediting electric vehicle adoption is the technology advancement and

the substantial cost cut resulting from it. Key enablers are developments in battery chemistry and

the expansion of production capacity in manufacturing plants. Other important solutions include

the design of vehicle power electronic units, which mainly consists of the motor drive inverter

and the on-board battery charger. In this thesis, the author focuses on advancing the motor driver

inverter from both control and topology perspectives. From the control perspective, the author

shows that it is possible to tackle several optimization problems without any additional cost or

additional hardware. In the first part, the common-mode voltage (CMV) is addressed. CMV is

one of the most common failure causes in electric motors. Mitigating the CMV effects leads to

improved reliability of the motor and longer lifetime. In the second part, the optimization of the

PWM pattern is addressed. A real-time approach is developed that allows eliminating the low-order

odd harmonics with deterministic execution time. The elimination of the low-order harmonics

leads to a close-to-sinusoidal load current with minimized switching losses. In the last part of

this thesis, a new type of boost converter is presented. The switched-capacitor boost converter

increases the effective dc-link voltage without relaying of bulky inductors. This approach has the

benefit of potentially increasing the power density of the converter.

2

Chapter 2

Hybrid SVPWM Scheme to Minimize the

Common-mode Voltage Frequency and

Amplitude in VSI Drives

Voltage source inverters (VSIs) are widely used in motor drive applications. The use of VSI ranges

from high power (e.g., wind turbines) to medium power (e.g., electric and hybrid electric vehicles).

Ever since the invention of the insulated gate bipolar transistor (IGBT), increasing the switch-

ing frequency of the power converter has been a trend due to the reduction of the footprint and

the increase of power density [1, ?]. Recent development of wide bandgap devices has equipped

the power switches with even faster switching speed [3]. However, the increase in the switch-

ing frequency has generated several unwanted consequences, one of which is the high-frequency

common-mode voltage (CMV) [4], [6]. The high-frequency CMV can cause electromagnetic in-

terference (EMI) that adversely affects the other components of the system [7]. The induced over-

voltage stresses the winding insulation of the drives and also can increase the shaft current [8].

In particular, the shaft current is the result of the fluctuation of the CMV, which is strictly related

to the sequence of the inverter switching states [9]. Several studies presented in the literature

discussed the reduction of CMV effects. They can be classified into hardware solutions and algo-

3

rithmic solutions. The hardware ones require either increasing the number of switches [10]- [15],

passive components [16]- [25], or both [26, 27]. The study in this chapter is mostly related to the

algorithmic approaches that require no additional hardware.

The early attempt to reduce the CMV proposed in [9] uses only the odd or only the even voltge

vectors. This approach results in DC CMV. However, the linear region in this approach is reduced
√
to M I ≤ 4
3
zero states PWM (AZSPWM1-2 and AZSPWM3), remote state PWM (RSPWM1, RSPWM2, and

. Later a number of CMV reduction methods were proposed such as the active

3

RSPWM3), and near-state PWM (NSPWM) [28]- [31]. In each one, several active voltage vectors

are utilized to meet the voltage second requirements and avoid using the zero vectors. The non-

zero switching vectors generate lower magnitude CMV but the conventional space vector PWM

uses zero vectors as it helps in reducing the THD [32, 35]. The latter methods, except for NSPWM,

utilize all of the linear region, which leaves the high frequency of the CMV remaining an issue.
The high common-mode dv
dt causes electric discharge machining (EDM) across the bearing races.
Furthermore, the CMV reduction methods assume ideal switches and fail when non-idealties such

as the dead-time and line-line voltage reversal are considered [34].

On the other hand, to further improve the performance of CMV reduction methods, combined

approaches are used in different operating conditions. For instance, to make full use of NSPWM,

another CMV reduction method is activated at low modulation index such as AZSPWM1 [36].

The modified SVPWM presented in [37] combines both RSPWM and regular SVPWM at low

and high modulation index, respectively. This method makes a trade-off between DC-link voltage

utilization and common-mode current (CMC) reduction. However, the dead-time effect causes

CMV amplitude to reach half of DC-link voltage [38]- [40].

In this chapter, a hybrid approach for minimizing the amplitude and the frequency of the CMV

is proposed. The control concept is based on dividing the space vector hexagon into various seg-

ments and synthesizing the reference voltage vector by using vectors that correspond to a minimal

CMV. Full treatment of the dead-time effect is presented. The proposed method avoids any CMV

peaks or unwanted variations during the dead-time intervals.

4

The rest of the chapter is organized as follows. In section 2.1, the regular SVPWM is briefly

revisited. The proposed control method is presented in Section 2.2. Dead-time effect is presented

in Section 2.3. A complete solution to the dead-time effect is presented in Section 2.4. Performance

analyses including CMV characteristics, harmonic distortion factor (HDF), DC current ripple, and

the switching losses are presented in Section 2.5. Hardware results and conclusion are presented

in section 2.6 and 2.7, respectively.

2.1 Conventional SVPWM

For the two-level, three-phase voltage source inverter shown in Fig. 2.1, the reference value of the

inverter output voltage can be represented by the following space vector:

Vref =

2
3

(va + vbe

j 2π

3 + vce

−j 2π
3 )

(2.1)

where va, vb, and vc are the three phase voltages. Since the DC-link should not be shorted, each
phase voltage can only attain either Vdc or −Vdc. This also restricts the feasible switching states to
only eight states. The eight converter states as well as the corresponding differential-mode voltage

(DMV) and common-mode voltage are shown in Table 3.1. The linear combination of the possible

eight vectors span a hexagonal area as shown in Fig. 2.2.

Table 2.1 The feasible voltage vectors and the corresponding DMV and CMV.

Dwell time Voltage vector

tv0
tv1
tv2

tv3

tv4
tv5

tv6
tv7

V(0,0,0)
V(1,0,0)
V(1,1,0)
V(0,1,0)
V(0,1,1)
V(0,0,1)
V(1,0,1)
V(1,1,1)

vb

va
vc
−Vdc −Vdc −Vdc
Vdc −Vdc −Vdc
Vdc −Vdc
Vdc
Vdc −Vdc
−Vdc
−Vdc
Vdc
Vdc
−Vdc −Vdc
Vdc
Vdc −Vdc
Vdc
Vdc

Vdc
Vdc

5

vdm
0

vcm
−Vdc
−Vdc
3
Vdc
)Vdc
3
)Vdc −Vdc
3
Vdc
3
)Vdc −Vdc
3
3
Vdc
)Vdc
3
Vdc

3

4
3Vdc
3 + j 2√
(2
3 + j 2√
(−2
3
−4
3Vdc
3 − j 2√
(−2
3 − j 2√
(2

3

0

Figure 2.1 Three-phase voltage source inverter.

Figure 2.2 Eight stationary vectors in the complex plane for a VSI.

The reference vector Vref is synthesized at each sampling period Ts using the two adjacent
active vectors and the zero vectors. This leads to six equal sectors. Because the circular trajec-
tory of Vref in the complex plane corresponds to a sinusoidal three-phase voltage, the maximum
achievable sinusoidal output voltage amplitude is ≤ 2√
Vdc. Therefore, the modulation index M I
3
can be defined as the per unit output voltage vector using Vdc as the base voltage M I ∈ [0, 2√
].
For instance, when the trajectory of the reference voltage Vref is passing though the first

3

sector where θ ∈ [0, π

3 ], the following volt-seconds equality holds:

TsVref = tv1V(1,0,0) + tv2V(1,1,0) + tv0V(0,0,0) + tv7V(1,1,1)

(2.2)

6

iaibics1s2s3s4s5s6vavbvcn0Vdc-VdcLRvcm=vn0V(1,0,0)V(0,1,0)V(0,0,1)V(1,1,0)V(1,0,1)V(0,1,1)V(0,0,0)V(1,1,1)IIIIIIIVVVI4/3Vdc4/3cos(π/6 )Ts = tv1 + tv2 + tv0 + tv7.

(2.3)

By equating the real part and the imaginary part in (2.2), the following dwell times can be obtained:

tv1 =

3
4

TsM I[cos(θ) − sin(θ)]

√

3
2

tv2 =

TsM I sin(θ)

tv0 = tv7 = T s − tv1 − tv2.

(2.4)

(2.5)

(2.6)

The same rules can be applied for calculating the dwell times of the vectors for sectors 2

through 6 if the following modified θk is used:

θk = θ − (k − 1)

π
3

(2.7)

where k is the number of the sector in which the Vref resides.

2.2 Hybrid Space Vector Pulse With Modulation Synthesis

The method of hybrid space vector pulse width modulation synthesis (HSVPWMS) further subdi-

vides each sector into three segments. In each segment, a group of active voltage vectors is selected

to match the output reference volt-seconds and achieve minimal CMV amplitude and frequency.

The location of the reference voltage vector can be defined in correspondence to the modulation

index M I and its angle θ.

sponding CMV. They can be categorized into: i) six odd segments that result in CMV −Vdc
even segments that result in CMV Vdc

The total eighteen segments of the space vector hexagon are are obtained based on their corre-
3 , ii) six
3 , and iii) six odd-even segments that result in CMV ±Vdc
3 .
To understand the navigation of the reference voltage through those segments, the author thor-
3 ) with

oughly explains the synthesis of the reference voltage vector via the first sector θ ∈ [0, π

7

Figure 2.3 Sector I is divided into three segments: (a) odd triangle, (b) odd-even triangle, and (c)
even triangle.

reference to Fig. 2.3.

The sector includes three segments (triangles). The reference vector in the bottom trian-
gle (odd-triangle) can be synthesized using only the odd vectors {V(1,0,0), V(0,1,0), V(0,0,1)}
as shown in Fig. 2.3 (a). The reference vector in the upper-right triangle (odd-even triangle)
can be synthesized using the odd and even vectors {V(1,0,0), V(1,1,0), ..., V(1,0,1)} as shown
Fig. 2.3 (b). The reference vector in the upper-left triangle (even triangle) can be synthesized using
only the even vectors {V(1,1,0), V(0,1,1), V(1,0,1)} as shown Fig. 2.3 (c).

The line dividing the odd triangle from the odd-even triangle can be parameterized as follows:

edge =

2√
3

(1 − θ
π/6

);

(2.8)

When the M I is greater than the value of edge, the reference voltage vector is in the odd triangle.

Similar logic can be followed to identify all other segments.

The synthesis of the reference voltage vector in the odd triangle and even triangle is unique,

whereas the synthesis for the reference voltage vector in the odd-even triangle can be realized using

different groups of vectors. The groups are classified into four groups with each group producing

similar harmonic content and switching losses. The four groups are delineated in the following

subsections.

8

V(1,0,0)V(0,1,0)V(0,0,1)V(1,1,0)V(1,0,1)V(0,1,1)V(1,0,0)V(0,0,1)V(0,1,0)V(1,1,0)V(1,0,1)V(0,1,1)Odd triangleOdd-even triangleEven triangle(a)(b)(c)2.2.1 HSVPWMS I

The voltage reference vector passing through the odd-even triangles can be synthesized by using

the two adjacent voltage vectors and the two voltage vectors of the neighboring states to match

the output and reference volt-seconds as shown in Fig. 2.4 (b). For the odd triangle shown in
Fig. 2.4 (a), the time intervals in which the inverter states {(V(1,0,0), V(0,1,0), V(0,0,1)} are
applied can be calculated by solving the following algebraic equations:

Vref Ts = V(1,0,0)tv1 + V(0,1,0)tv3 + V(0,0,1)tv5

Ts = tv1 + tv3 + tv5.

This leads to the following dwell times:

tv1 =

Ts
3

+

TsM I cos(θ)

2
√

tv3 =

tv5 =

Ts
3

Ts
3

− TsM I cos(θ)

4

− TsM I cos(θ)

4

√

+

−

3TsM I sin(θ)

4

3TsM I sin(θ)

4

.

(2.9)

(2.10)

(2.11)

(2.12)

(2.13)

For the odd-even triangle shown in Fig. 2.4 (b), the time intervals in which the inverter states
{(V(1,0,1), V(1,0,0), V(1,1,0),
V(0,1,0)} are applied can be calculated by solving the following algebraic equations:

Vref Ts = V(1,0,1)tv6 + V(1,0,0)tv1 + V(1,1,0)tv2 + V(0,1,0)tv3

Ts = tv6 + tv1 + tv2 + tv3.

(2.14)

(2.15)

To solve the algebraic equations, it is assumed tv6 is equal to tv3. This leads to the following

9

Figure 2.4 Vector synthesis for HSVPWM I of (a) odd triangle, (b) odd-even triangle, and (c) even
triangle.

dwell times:

tv1 =

√
3TsM I sin(θ)

4

−

3TsM I cos(θ)

4

√

tv2 =

3TsM I sin(θ)
√

2

tv6 = tv3 =

Ts
2

− 3TsM I cos(θ)

−

8

3TsM I sin(θ)

8

.

(2.16)

(2.17)

(2.18)

For the even triangle shown in Fig. 2.4 (c), the time intervals in which the inverter states
{(V(1,1,0), V(0,1,1), V(1,0,1)} are applied can be calculated by solving the following algebraic
equations:

Vref Ts = V(1,1,0)tv2 + V(0,1,1)tv4 + V(1,0,1)tv6

Ts = tv2 + tv4 + tv6.

This leads to the following dwell times:

tv2 =

Ts
3

+

TsM I cos(θ)

4

√

+

3TsM I sin(θ)

4

(2.19)

(2.20)

(2.21)

10

(a)(b)(c)Tss3s2s1tv1/3 tv3/2tv5/2tv1/3tv5/2tv3/2tv1/3Tss3s2s1vcm-Vdc/3  Vdc/3tv3/2tv1/2tv2/2tv6tv2/2tv1/2tv3/3vcm-Vdc/3  Vdc/3s3s2s1vcm-Vdc/3  Vdc/3tv2/3tv4/2tv6/2tv2/3tv6/2tv4/2tv2/3TsV(1,0,0)V(0,1,0)V(1,1,0)V(1,0,1)V(1,0,0)V(0,1,0)V(0,0,1)V(1,1,0)V(1,0,1)V(0,1,1)tv4 =

Ts
3

− TsM I cos(θ)

tv6 =

Ts
3

+

TsM I cos(θ)

4

−

2
√
3TsM I sin(θ)

4

(2.22)

(2.23)

.

The similar calculation can be conducted for the other five sectors by employing the appropriate

vectors as listed in Table 2.2.

Table 2.2 The vector combinations used in the three segments of each sector using HSVPWMS I.

Sector Odd triangle

Odd-even triangle

Even triangle

I
II
III
IV
V
VI

{V(1,0,0), V(0,1,0), V(0,0,1)} {V(1,0,1), V(1,0,0), V(1,1,0), V(0,1,0)}{V(1,1,0), V(0,1,1), V(1,0,1)}
{V(1,0,0), V(0,1,0), V(0,0,1)} {V(1,0,0), V(1,1,0), V(0,1,0), V(0,1,1)}{V(1,1,0), V(0,1,1), V(1,0,1)}
{V(1,0,0), V(0,1,0), V(0,0,1)} {V(1,1,0), V(0,1,0), V(0,1,1), V(0,0,1)}{V(1,1,0), V(0,1,1), V(1,0,1)}
{V(1,0,0), V(0,1,0), V(0,0,1)} {V(0,1,0), V(0,1,1), V(0,0,1), V(1,0,1)}{V(1,1,0), V(0,1,1), V(1,0,1)}
{V(1,0,0), V(0,1,0), V(0,0,1)} {V(0,1,1), V(0,0,1), V(1,0,1), V(1,0,0)}{V(1,1,0), V(0,1,1), V(1,0,1)}
{V(1,0,0), V(0,1,0), V(0,0,1)} {V(0,0,1), V(1,0,1), V(1,0,0), V(1,1,0)}{V(1,1,0), V(0,1,1), V(1,0,1)}

2.2.2 HSVPWMS II

The voltage reference vector passing through the odd-even triangles can be synthesized by using

the two adjacent voltage vectors and one voltage vector of either neighboring state to match the

output and reference volt-seconds as shown in Fig. 2.5. Table 2.3 shows the vector combinations

used in the three segments of each sector for HSVPWMS II.

Table 2.3 The vector combinations used in the three segments of each sector using HSVPWMS II.

Sector Odd-even triangle

I
II
III
IV
V
VI

{V(1,0,0), V(1,1,0), (V(0,1,0) ∨ V(1,0,1))}
{V(1,1,0), V(0,1,0), (V(0,1,1) ∨ V(1,0,0))}
{V(0,1,0), V(0,1,1), (V(0,0,1) ∨ V(1,1,0))}
{V(0,1,1), V(0,0,1), (V(1,0,1) ∨ V(0,1,0))}
{V(0,0,1), V(1,0,1), (V(1,0,0) ∨ V(0,1,1))}
{V(1,0,1), V(1,0,0), (V(1,1,0) ∨ V(0,0,1))}

2.2.3 HSVPWMS III

The voltage reference vector passing through the odd-even triangles can be synthesized by using

the two adjacent voltage vectors and the two voltage vectors of the far states to match the output

11

and reference volt-seconds as shown in Fig. 2.6. Table 2.4 shows the vector combinations used in

the three segments of each sector for HSVPWMS III.

Table 2.4 The vector combinations used in the three segments of each sector using HSVPWMS III.

Sector Odd-even triangle

I
II
III
IV
V
VI

{V(0,0,1), V(1,0,0), V(1,1,0), V(0,1,1)}
{V(1,0,1), V(1,1,0), V(0,1,0), V(0,0,1)}
{V(1,0,0), V(0,1,0), V(0,1,1), V(1,0,1)}
{V(1,1,0), V(0,1,1), V(0,0,1), V(1,0,0)}
{V(0,1,0), V(0,0,1), V(1,0,1), V(1,1,0)}
{V(0,1,1), V(1,0,1), V(1,0,0), V(0,1,0)}

2.2.4 HSVPWMS IV

The voltage reference vector passing through the odd-even triangles can be synthesized by using

the two adjacent voltage vectors and one voltage vectors of either far state to match the output and

reference volt-seconds as shown in Fig. 2.7. Table 2.5 shows the vector combinations used in the

three segments of each sector for HSVPWMS IV.

Figure 2.5 Vector synthesis of odd-even triangle for HSVPWMS II.

Table 2.5 The vector combinations used in the three segments of each sector using HSVPWMS IV.

Sector Odd-even triangle

I
II
III
IV
V
VI

{V(1,0,0), V(1,1,0), (V(0,1,1) ∨ V(0,0,1))}
{V(1,1,0), V(0,1,0), (V(0,0,1) ∨ V(1,0,1))}
{V(0,1,0), V(0,1,1), (V(1,0,1) ∨ V(1,0,0))}
{V(0,1,1), V(0,0,1), (V(1,0,0) ∨ V(1,1,0))}
{V(0,0,1), V(1,0,1), (V(1,1,0) ∨ V(0,1,0))}
{V(1,0,1), V(1,0,0), (V(0,1,0) ∨ V(0,1,1))}

12

Tss3s2s1vcm-Vdc/3  Vdc/3tv3/3tv1/2tv2/2tv1/2tv3/3tv2/2tv3/3V(1,0,0)V(0,1,0)V(1,1,0)Figure 2.6 Vector synthesis of odd-even triangle for HSVPWMS III.

Figure 2.7 Vector synthesis of odd-even triangle for HSVPWMS IV.

2.3 Dead-time Effect and Narrow CMV Pulse Avoidance

The implementation of only odd or only even vectors requires simultaneous switching of two con-

verter legs. In practice, this could be challenging because of the dead-times and the differences

in the gate delay [30]. The dead-time mismatch causes a narrow pulse in the CMV. The narrow

pulse frequency increases as the switching frequency increases. To further assess the situation,

consider Fig. 2.8. During the dead-times, the resulting CMV is no longer a function of the switch-

ing commands. Instead it is strictly dependent on the signs of the three-phase load currents. In this

13

Tss3s2s1vcm-Vdc/3  Vdc/3tv4/2tv2/2tv1/2tv5tv1/2tv2/2tv4/2V(1,0,0)V(0,0,1)V(1,1,0)V(0,1,1)Tss3s2s1vcm-Vdc/3  Vdc/3tv5/2tv1/3tv2/2tv1/3tv5/2tv1/2tv2/2V(1,0,0)V(0,0,1)V(1,1,0)case, the CMV ∈ {Vdc,
dead-times must be analyzed for each transition.

3 ,−Vdc
Vdc

3 ,−Vdc}. Therefore, the effective switching state during the

Figure 2.8 Dead-time effect on CMV. During the dead-times, the CMV is dependent on the sign of
the three-phase load current, CMV ∈ {Vdc,

3 ,−Vdc}.

3 ,−Vdc
Vdc

Consider these three examples:

Example 1

Suppose the transition from the odd vector V(1,0,0) to the odd vector V(0,1,0) is taking place
while the three-phase load currents ia > 0, ib < 0, and ic > 0. The effective switching state
during the dead-time td13 will be the same as the destination vector state (0, 1, 0). This is because
of the current polarities as shown in Fig. 2.9: ia is positive and will flow through the freewheeling
diode of S4 when S1 turns off; ib is negative and will flow through the freewheeling diode of
S2; and ic is positive and will flow through the freewheeling diode of S6. This is equivalent to
connecting two of the load phases to the lower DC rail Vdc and only one phase to the upper DC
rail Vdc. In this case, the resulting CMV during td13 is as expected and equal to −Vdc
3 .

Example 2

If the same transition occurs while the the three-phase load currents ia > 0, ib > 0, and ic < 0, the
effective switching state during the dead-time td13 will not be the same as the destination vector

14

s3s2s1tv1tv3tv5s6s5s4vcm-Vdc/3  Vdc/3td13td51td35Figure 2.9 During td13 and ia > 0, ib < 0, and ic > 0, the CMV is equal to −Vdc
3 .

state (0, 1, 0). Instead it will be (0, 0, 0), and the resulting CMV during td13 will be equal to −Vdc
as shown in Fig 2.10.

Figure 2.10 During td13 and ia > 0, ib > 0, and ic < 0, the CMV is equal to −Vdc.

Example 3

If the same transition occurs while the the three-phase load currents ia < 0, ib < 0, and ic > 0,
the effective switching state at the dead-time td13 will not be the same as the destination vector
state (0, 1, 0). Instead it will be (1, 1, 0), and resulting CMV will be Vdc

3 as shown in Fig. 2.11.

By considering all of the possible intervals in which the three-phase load currents do not change

sign, six current sectors can be defined as shown in Fig. 2.12. The calculations for the effective

switching states during the other dead-times are performed in the same manner as illustrated in

the examples and listed in Tables 2.6 and 2.7 for odd and even states, respectively. It is important

to note that the effective switching state is the same as the effective switching state when the

transition is reversed (tdxy = tdyx). For this reason, the calculations for this type of transition are

15

ia>0ib<0ic>0Vdc-VdcS1S2S3S4S5S6Vdc-VdcS1S2S3S4S5S6ic<0ib>0ia>0Figure 2.11 During td13 and ia < 0, ib < 0, and ic > 0, the CMV is equal to Vdc
3 .

not included in the tables.

Table 2.6 Effective switching states in case of only odd modulation.

vcm
−Vdc
−Vdc
3
−Vdc
3
−Vdc
3
−Vdc
3
Vdc
3
−Vdc
3
−Vdc
−Vdc
3
Vdc
3
−Vdc
3
−Vdc
3
−Vdc
3
−Vdc
3
−Vdc
−Vdc
3
Vdc
3
−Vdc
3

Sector Dead-time

Eff. state
(S1,S2,S3)

S-I

S-II

S-III

S-IV

S-V

S-VI

td13
td35
td51
td13
td35
td51
td13
td35
td51
td13
td35
td51
td13
td35
td51
td13
td35
td51

(0,0,0)
(0,1,0)
(0,1,0)

(0,0,1)
(0,1,0)
(0,1,1)

(0,0,1)
(0,0,0)
(0,0,1)

(1,0,1)
(1,0,0)
(0,0,1)

(1,0,0)
(1,0,0)
(0,0,0)
(1,0,0)
(1,1,0)
(0,1,0)

16

ib<0Vdc-VdcS1S2S3S4S5S6ia<0ic>0Table 2.7 Effective states in case of only even modulation.

Sector Dead-time

Eff. state
(S1,S2,S3)

S-I

S-II

S-III

S-IV

S-V

S-VI

td24
td46
td62
td24
td46
td62
td24
td46
td62
td24
td46
td62
td24
td46
td62
td24
td35
td62

(1,1,0)
(0,1,0)
(0,1,1)
(1,1,1)
(0,1,1)
(0,1,1)

(1,0,1)
(0,1,1)
(0,0,1)

(1,0,1)
(1,1,1)
(1,0,1)

(1,0,0)
(1,1,0)
(1,0,1)

(1,1,0)
(1,1,0)
(1,1,1)

vcm
Vdc
3
−Vdc
3
Vdc
3
Vdc
Vdc
3
Vdc
3
Vdc
3
Vdc
3
−Vdc
3
Vdc
3
Vdc
Vdc
3
−Vdc
3
Vdc
3
Vdc
3
Vdc
3
Vdc
3
Vdc

It is evident from Tables 2.6 and 2.7 that the CMV is not limited to |Vdc

3 | even if only odd
or only even states are used. Therefore, to avoid the unwanted CMV peaks (|Vdc|), the control
algorithm must be modified to use only odd states in S-II, S-IV, and S-VI and only even states in

S-I, S-III, and S-V. The current sectors are shown in Fig. 2.13(a).

It is important to note the connection between the current sectors {S-I to S-VI} and the power
factor (P F ). In machine drive applications the current space vector (i) is lagging. This causes the

current sectors to rotate clockwise and changes the feasible regions of using only odd or only even

states. Fig. 2.13(b) shows the rotated current space vector when the P F = 0.866 lagging.

17

Figure 2.12 There are six regions in which the three-phase load currents do not change sign.

Figure 2.13 The current sectors (in which the three-phase load currents do not change sign) in
relation to the voltage vectors when (a) P F = 1 and (b) P F = 0.866 lagging.

Modifying the control algorithm to avoid the peak CMV is not difficult as long as the load

current signals are available in the loop. Fig. 2.14 shows the modified control block diagram.

The current sectors are determined by measuring the load currents and checking the sign of

each phase current. Although this modification allows one to avoid the maximum CMV peaks,
high dvcm
dt

is still possible during some dead-times. Furthermore, the availability of only odd or

only even vectors is linked to the P F . When the P F = 1, the current sectors are completely

out of sync. Whereas if the P F = 0.866, the current sectors are completely in sync. To avoid

this limitation, the authors propose a new commutation method in the next section. The new

commutation method allows a complete decoupling of the effect of P F , and it avoids the narrow

18

iaibicS-VIS-IS-IIS-IIIS-IVS-V0ia,ic>0ib<0ia>0ib,ic<0ia,ib>0ic<0ib>0ia,ic<0ib,ic>0ia<0ic>0ia,ib<0iV(1,0,0)V(0,1,0)V(0,0,1)V(1,1,0)V(1,0,1)V(0,1,1)S-IVS-IS-IIS-IIIS-IVS-VV(1,0,0)V(0,1,0)V(0,0,1)V(1,1,0)V(1,0,1)V(0,1,1)S-IVS-IS-IIS-IIIS-IVS-V(a)(b)Figure 2.14 Modified control block diagram to account for the current sectors position.

CMV pulse during dead-time intervals.

2.4 Proposed commutation Algorithm

As shown in the previous section, by including the load current signals in the control loop, one

can determine when it is safe to use only odd or only even vectors without causing peak CMV.
However, there are unwanted transitions in the CMV from Vdc
3 or vice versa during
3
some dead-time intervals. As Tables 2.6 and 2.7 demonstrate, in each current sector there are two

to −Vdc

dead-time intervals in which no change in the CMV occurs. These two dead-times can be utilized

to make a proper commutation sequence among the odd vectors or even vectors. Fig. 2.15 shows

the commutation sequences that achieve no change in the CMV during the dead-time intervals.

Furthermore, the rotation of the current sectors due to the P F will not affect the availability of

only odd or only even vectors because in each current sector there are two safe sequences: one for

only odd states and one for only even states. The safe sequences also allow to equalize switching

losses per fundamental cycle among the IGBTs. Therefore, there is no unbalanced temperature

distribution in inverter switches.

19

Figure 2.15 The commutation sequences that do not cause a change in CMV during dead-time
intervals. Each current sector has two safe sequences: one for only odd and one for only even
syntheses. This allows the use of only odd and only even vectors without any constraints imposed
by the P F .

20

V(0,1,0)V(0,0,1)V(1,1,0)V(1,0,1)S-IVS-IS-IIS-IIIS-IVS-VV(0,1,1)V(1,0,0)s3s2s1tv3/2tv1tv5/2tv3/2Tstv5/2td35td51td15td53Only odds3s2s1tv1/2tv5tv3/2tv1/2Tstv3/2td13td35td53td31Only odds3s2s1tv1/2tv5tv3/2tv1/2Tstv3/2td13td35td53td31Only odds3s2s1tv3/2tv1tv5/2tv3/2Tstv5/2td35td51td15td53Only odds3s2s1tv5/2tv3tv1/2tv5/2Tstv1/2td51td13td31td15Only odds3s2s1tv5/2tv3tv1/2tv5/2Tstv1/2td51td13td31td15Only odds3s2s1tv6/2tv4tv2/2tv6/2Tstv2/2td62td24td42td26Only evens3s2s1tv6/2tv4tv2/2tv6/2Tstv2/2td62td24td42td26Only evens3s2s1tv4/2tv2tv6/2tv4/2Tstv6/2td46td62td26td64Only evens3s2s1tv4/2tv2tv6/2tv4/2Tstv6/2td46td62td26td64Only evens3s2s1tv2/2tv6tv4/2tv2/2Tstv4/2td24td46td64td42Only evens3s2s1tv2/2tv6tv4/2tv2/2Tstv4/2td24td46td64td42Only even2.5 Performance Analysis

HSVPWMS methods utilize different voltage vectors with different possible sequences. Each

synthesis and combination corresponds to a different number of commutations, output current

quality, CMV characteristics, DC-link current harmonics, and switching losses. Therefore, to

understand the full potential of each method, a fair comparison with the CMV reduction PWM

methods in terms of CMV characteristics, HDF, DC-link current, and switching losses is presented

next.

2.5.1 Common-mode Voltage Characteristics

Common-mode behavior for induction machines is mostly capacitive [41]. Therefore, it does

not require an extensive high-frequency machine modeling to determine the relationship between

CMV characteristics and the resulting CM current. Early studies showed that the parasitic machine

capacitances can be measured [42] or calculated by finite element methods [43, 44]. A machine

model for high frequencies is develeoped in [45] and shows that the CM current is directly propor-

tional to the frequency of the CMV.

Fig. 2.16 shows the CMV and its spectrum for the conventional SVPWM. The amplitude of

the CMV is Vdc and is high due to the use of zero vectors. Another fundamental component of the
CMV at the PWM carrier frequency (fc).

√
All of the other HSVPWMS methods have similar CMV waveforms for M I ≤ 4
3

3

, where the

main harmonic components are at 3f1 and 6f1, where f1 is the system fundmantal frequency (for
instance 60 Hz). These two frequency components result in a very small common-mode current

because the impedance is very high prior to the resonance region [41]. HSVPWMS I and HSVP-

WMS III have harmonic components around the carrier frequency fc with an amplitude lower

than that of the conventional SVPWM method. The fc component increases as the MI increases as

shown in Fig. 2.17 and Fig. 2.19. HSVPWMS II and HSVPWMS IV have high-frequency CMV

components around 2fc that increase as the M I increases. Most of the CMV harmonic compo-

21

nents are concentrated in the fundamental component 3f1 and base band harmonic 6f1 as shown in
Fig. 2.18 and Fig. 2.20. Generally, HSVPWMS methods have a maximum CMV amplitude equal
to Vdc
3 , which is three times less than the regular SVPWM. More importantly, the amplitudes of
CMV at high frequencies are reduced tremendously, especially at M I ≤ M Imax. Therefore, the
resulting CM current in the HSVPWMS method is significantly reduced as compared against the

other methods..

Fig. 2.21 gives a clear representation of how the fundamental component of the CMV is behav-

ing versus MI within the linear modulation region. The simulation parameters: DC-link voltage

60 V, carrier frequency fc = 5 kHz, and system fundamental frequency f1 = 60 Hz.
been observed through multiple simulations that the characteristic of each harmonic is relatively

It has

constant to those parameters, therefore, the plots are given in terms of the DC-link voltage, fun-

damental frequency, and the carrier frequency. The high-frequency CMV of the regular SVPWM

has a very high amplitude when the MI is low because of the high duty ratio of the zero vector.

The suitable HSVPWMS can be selected based on the level of the MI and the characteristics of the

machine common-mode impedance.

2.5.2 Harmonic Distortion Factor
In the motor winding fsw/f ≥ 20, the harmonic current is directly proportional to the harmonic
flux. Therefore, the current quality can be studied by using only the information of the applied

voltage vector independent of the load ratings. The concept of harmonic distortion factor intro-

duced in [46] is further expanded to account for the transitions between different syntheses. The

harmonic flux for the Nth carrier cycle can be defined as [29]

(cid:90) (N +1)Ts

N Ts

λh(M I, θ, V(.,.,.)) =

(V(.,.,.) − Vref )dt

(2.24)

where V(.,.,.) is the applied voltage vector during the sampling time N Ts. Normalizing the har-
monic flux results in the harmonic flux voltage vector

22

(a) M I = 0.6667

(b) M I = 0.866

Figure 2.16 Common-mode voltage waveforms and their corresponding frequency spectrum using
the regular SVPWM.

(c) M I = 1

23

0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)10401020|vcm| (V)0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)10401020|vcm| (V)0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)10401020|vcm| (V)(a) M I = 0.6667

(b) M I = 0.866

Figure 2.17 Common-mode voltage waveforms and their corresponding frequency spectrum using
HSVPWMS I.

(c) M I = 1

24

0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)(a) M I = 0.6667

(b) M I = 0.866

Figure 2.18 Common-mode voltage waveforms and their corresponding frequency spectrum using
HSVPWMS II.

(c) M I = 1

25

0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)10405|vcm| (V)(a) M I = 0.6667

(b) M I = 0.866

Figure 2.19 Common-mode voltage waveforms and their corresponding frequency spectrum using
HSVPWMS III.

(c) M I = 1

26

0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)(a) M I = 0.6667

(b) M I = 0.866

Figure 2.20 Common-mode voltage waveforms and their corresponding frequency spectrum using
HSVPWMS IV.

(c) M I = 1

27

0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)0.020.030.040.05t (S)-20020vcm (V)012345f (Hz)1040510|vcm| (V)Figure 2.21 The fundamental component of the CMV. The fundamental frequency of the CMV in
SVPWM is equal to fc = 5 kHz. Whereas in HSVPWMS methods the frequency of the funda-
mental component is equal to 3f1 = 180 Hz.

Each voltage utilization method results in a unique harmonic voltage vector trajectory. The nor-

λhn =

π

VdcTs

λh.

(2.25)

malized harmonic flux RMS value over a PWM (duty cycle δ of 0 to 1) is calculated as follows:

λhn−rms(M I, θ) = K2
f

λ2
hn

dδ

(2.26)

(cid:115)(cid:90) 1

0

where Kf is the is the ratio of the switching per PWM cycle between the regular SVPWM and
the HSVPWMS methods. In order to attain a fair comparison between HSVPWMS methods and

the regular SVPWM method, all HSVPWMS methods are set to operate at the same switching

frequency by dividing the carrier frequency of each method by Kf . Taking the average value of
the RMS harmonic flux function over a full fundamental cycle results in the a harmonic distortion

factor (HDF), which is a measure of the AC current ripple:

HDF =

288
π2

1
2π

λhn−rmsdθ.

(2.27)

(cid:90) 2π

0

28

0.20.40.60.81MI0.20.40.60.811.21.4CMV/VdcSVPWMHSVPWMS IHSVPWMS IIHSVPWMS IIIHSVPWMS IVThe hybrid harmonic distortion factor HDFH is obtained by averaging the HDFs of each sequence
based on the value of the modulation index as follows:

HDF(O∨E)

HDFH =

√
M I ≤ 4
3
√
MpHDF(O∨E) + (1 − Mp)HDF(E∧O) M I > 4
3
3

3

(2.28)

(2.29)

where Mp is the modulation parametric factor defined as

Mp =

M Imax − M I

√
2
3

3

HDF(O∨E) is HDF calculated when only the odd vectors {V(1,0,0), V(0,1,0), V(0,0,1)} are ap-
plied or only the even vectors {V(1,1,0), V(0,1,1), V(1,0,1)} are applied, depending on the loca-
tion of the segments as described previously for each HSVPWMS. HDF(O∧E) is HDF calculated
when both odd and even vectors are applied {V(1,0,0), V(1,1,0), V(0,1,0), V(0,1,1), V(0,0,1),
√
V(1,0,1)}, depending on the selected group of vectors. When the MI is less than or equal to
4
3
3
the HDFH is identical to the HDF resulting from only odd vectors or only even vectors. When
, the HDFF is averaged based on the definition in (2.28). Fig. 2.22
the M I is greater then
shows the numerical results of HDFH for all HSVPWMS along with the regular SVPWM. All
√
the HSVPWMS methods present similar HDF in the region where M I ≤ 4
. Although the
3
3
HDF for HSVPWMS II is lower than the other hybrid methods, it presents higher CMV frequency

√
4
3

3

,

as will be seen later in the results.

2.5.3 DC-Link Current Harmonics

The rms current on the DC side is important factor in determining the DC-link capacitor sizing [47].

To compare the behavior of the PWM methods, Kdc is defined in [29] as

Kdc =

I2
in−h−rms
I2
1−rms

29

(2.30)

Figure 2.22 Harmonic distortion factor for the HSVPWMS methods compared with the conven-
tional PWMS methods.

where Iin−h−rms is the rms value of the DC-link current and I1−rms is the fundamental com-
ponent of the output rms current. The calculations for Kdc are performed numerically for different
power factors. Fig. 2.23 (a) to (c) show Kdc for the HSVPWMS methods compared with the
conventional SVPWM and CMV reduction methods. When the P F is high, Kdc for the hybrid
methods is higher than the other methods. However, when operating at low P F , Kdc for the hy-
brid methods surpasses Kdc for all of the other CMV reduction methods. In general, Kdc for the
all hybrid method is almost identical and decreases with decreasing the power factor.

2.5.4 Switching Losses

The switching losses for the VSI using HSVPWMS are calculated analytically by taking into

account the effect of changing different vector syntheses over the switching frequency. The IGBT

current and voltage do not abruptly change their values. Instead there is a transition interval in

which both the current and voltage across the IGBT have values larger than zero [48, 50]. The

30

0.20.40.60.81MI00.511.522.533.544.55HDFHHSVPWMS IHSVPWMS IIHSVPWMS IIIHSVPWMS IVSVPWMAZSPWM-2NSPWMAZSPWM-3(a) P F = 1

(b) P F = 0.8

(c) P F = 0.6

(d) P F = 0.4

Figure 2.23 DC-link current ripple coefficient (Kdc) for various PWM methods.

31

00.20.40.60.81MI00.20.40.60.811.21.41.6KdcSVPWMRSPWMAZSPWM1-2NSPWMHSVPWMS IHSVPWMS IIHSVPWMS IIIHSVPWMS IV00.20.40.60.81MI00.20.40.60.811.21.41.6KdcSVPWMRSPWMAZSPWM1-2NSPWMHSVPWMS IHSVPWMS IIHSVPWMS IIIHSVPWMS IV00.20.40.60.81MI00.20.40.60.811.21.41.6KdcSVPWMRSPWMAZSPWM1-2NSPWMHSVPWMS IHSVPWMS IIHSVPWMS IIIHSVPWMS IV00.20.40.60.81MI00.20.40.60.811.21.41.6KdcSVPWMRSPWMAZSPWM1-2NSPWMHSVPWMS IHSVPWMS IIHSVPWMS IIIHSVPWMS IVaverage value of the switching losses can be calculated as follows:

Psw−IGBT = fs(M I)

iC (t)vCE (t)dt +

(cid:20)(cid:90) t+tr

t

(cid:90) t+tf

t

(cid:21)

iC (t)vCE (t)dt

(2.31)

where fs is the effective switching frequency that represents the number of switching instants for

one IGBT in one fundamental frequency period, unlike the regular SVPWM. fs in HSVPWMS is
a function of the modulation index as shown in Table 2.8. iC is the collector current, and vCE
is the voltage across the collector-emitter. tr and tf are the rising and falling times, respectively.
The average switching losses per one IGBT can be integrate as follows: Equation (2.31) can be

expanded by simple linear approximation of iC and vCE, except during turn off events, in which
case iC can be approximated as an exponentially decaying function as follows [48]

iC (t) = ILe−a(t−ti)

(2.32)

where ti is the initial value of time in which the turn off event started and a is a constant that
can be adjusted to achieve the best function approximation. To solve (2.32), it is assumed that at

t = ti + tf , 95% of the collector current iC vanishes. Therefore, a can be defined as a function of
the falling time tf as follows:

(2.33)

Therefore, the integral becomes

a =

3
tf

0
tr

(cid:34)(cid:90) tr
(cid:20)1

0

iC (2Vdc − t
tr

2Vdc)dt +

(cid:90) tf

0

ILe−at t
tf

(cid:35)

2Vdcdt

(2.34)

1 − e

−atf (atf + 1)

a2

(cid:21)

)

.

ILVdctr +

2ILVdc

tf

(

(2.35)

3

Psw−IGBT = fs(M I)

Psw−IGBT = fs(M I)

Substituting (2.33) in (2.35) leads to

32

Figure 2.24 Switching on and off events for an IGBT.

Table 2.8 Effective switching frequency fs defined as a function of the modulation index.

Modulation method

SVPWM
HSVPWM I
HSVPWM II
HSVPWM III
HSVPWM IV

fs(M I)|

√
M I≤ 4
3

3

fc
2fc
2fc
2fc
2fc

fs(M I)|

√
M I> 4
3
3

fc
2Mpfc + (1 − Mp)10
6 fc
2Mpfc + (1 − Mp)4
3 fc
2Mpfc + (1 − Mp)10
6 fs
2Mpfc + (1 − Mp)3
2 fc

Psw−IGBT = fs(M I)

(cid:20)1

3

ILVdctr +

The integration results leads to

Psw−IGBT = fs(M I)[

1
3

ILVdctr +

(cid:21)

ILVdctf

.

(2.36)

ILVdctf ].

(2.37)

9
50

9
50

The total switching losses also include the reverse recovery losses associated with the diode

turn-off process:

Prr−D =

1
2

fs(M I)IrrVdctrr

(2.38)

where Irr is the maximum value of the reverse recovery current, and trr is the reverse recovery

time.

To obtain the effective switching frequency, the number of commutations per sampling time is

counted as shown in the Table 2.8.

33

Figure 2.25 Switching losses for the HSVPWMS methods compared with the conventional PWM
methods.

2.6 Experimental results

The experimental work has been carried out using the following parameters and operating con-

ditions: DC-link voltage 100 V carrier frequency fc = 5 kHz and an RL load with 5 Ω and 2

mH. The system consists of three inverter legs with each leg being realized by the IGBT module

CM100DY-24A. The control algorithm is implemented using DSpace CP1103.

Fig. 2.26 shows the resulting CMV with M I = 0.75. The reference voltage vector is synthe-

sized using only odd and only even states. This results in a square wave CMV with a frequency

equal to 3f1 (three times the fundamental frequency of the system 180 Hz). Fig. 2.27 shows
the FFT for the CMV with M I = 0.75. All of the CMV is concentrated at 180 Hz. The CMV
frequency spectrum is the similar to the one in Fig. 2.27 at any M I ∈ {0, 0.766}.

Fig. 2.28 shows the CMV with M I = 0.85 for the proposed hybrid approach and several

PWM methods. For the M I > 0.766, the reference voltage vector starts entering the odd-even
region, leading to a CMV that fluctuates between the values of Vdc
3 . However, the
3
CMV spectrum is still concentrated at 180 Hz frequency as shown in Fig. 2.29. The frequency

and −Vdc

spectrum for the conventional SVPWM and DPWM1 includes high amplitude CMV due to the use

of the zero vector. This high amplitude is located at the carrier frequency (normally in kHz). The

conventional CMV reduction PWM methods have lower CMV amplitudes, but they are still located

at the carrier frequency. The main difference between the proposed method and the conventional

CMV reduction methods is that the CMV frequency is decreased. A lower frequency CMV has

34

00.20.40.60.81Load current p.u.00.0050.010.0150.020.025Switching losses p.u.SVPWMHSVPWMS IHSVPWMS IIHSVPWMS IIIHSVPWMS IVRSPWMAZSPWM1-2NSPWMFigure 2.26 Experimental results for CMV at M I = 0.75 of 1 - HSVPWMS I, 2 - HSVPWMS II,
3 - HSVPWMS III, 4 - HSVPWMS IV.

two main advantages over a high frequency CMV. First, less CMV fluctuation corresponds to less

EDM in the bearings. Second, a low frequency CMV can help meet the EMC standards because the

amplitude limit for low frequencies is much higher than the amplitude limit for high frequencies.

Fig. 2.30 shows the CMV at M I = 1 for the proposed hybrid approach and several PWM

methods. As the M I increases higher the implementation of only odd or only even synthesis

decreases leading to high frequency CMV frequency components. However, the high frequency

CMV components are still less than the ones resulting from the conventional CMV reduction

methods as shown in Fig. 2.31.

Fig. 2.32 (a) and (b) show the load currents for the proposed methods along with the conven-

tional PWM methods. Although the load is mostly resistive with P F = 0.988, current ripples

resulting from the proposed hybrid methods are still comparable with the current ripples resulting

from the conventional PWM methods. As the M I increases, the HDF of load currents for the

proposed hybrid method improves because the reference voltage vector synthesis shifts from only

odd and only oven to odd-even.

Fig 2.33 (a) shows the CMV waveform without implementing the safe commutation algorithm.

35

0.0130.0140.0150.0160.0170.0180.0190.020.0210.0220.023t(s)-50050100150200250300350CMV vcm(t) (V)Figure 2.27 FFT of the CMV waveforms of 1 - HSVPWMS I, 2 - HSVPWMS II, 3 - HSVP-
WMS III, 4 - HSVPWMS IV.

There are two types of unwanted transitions during the dead-time intervals: Type 1, result in CMV
equal to |Vdc|, and Type 2, result in CMV that changes sign from Vdc
3 or vice versa.
These unwanted CMV pulses can be fully avoided when the proposed commutation sequences is

3 to −Vdc

implemented as shown in Fig 2.33 (b).

36

HSVPWMS IVHSVPWMS IIIHSVPWMS II0104012HSVPWMS I34551015Figure 2.28 Experimental results of CMV waveforms at M I = 0.85 for 1 - SVPWM, 2 - HSVP-
WMS I, 3 - HSVPWMS II, 4 - HSVPWMS III, 5 - HSVPWMS IV, 6 - AZSPWM1-2, 7 - NSPWM,
8 - AZSPWM3, and 9 - DPWM1.

37

0.0130.0140.0150.0160.0170.0180.0190.020.0210.0220.023t(s)-500-400-300-200-1000100200300400500CMV vcm(t) (V)345267891Figure 2.29 FFT of the CMV waveforms at M I = 0.85 for 1 - SVPWM, 2 - HSVPWMS I, 3
- HSVPWMS II, 4 - HSVPWMS III, 5 - HSVPWMS IV, 6 - AZSPWM1-2, 7 - NSPWM, 8 -
AZSPWM3, and 9 - DPWM1.

38

SVPWMDPWM1AZSPWM3NSPWMAZSPWM1-2HSVPWMS IVHSVPWMS III0HSVPWMS II10401HSVPWMS I2345102030Figure 2.30 Experimental results of CMV waveforms at M I = 1 for 1 - SVPWM, 2 - HSVP-
WMS I, 3 - HSVPWMS II, 4 - HSVPWMS III, 5 - HSVPWMS IV, 6 - AZSPWM1-2, 7 - NSPWM,
8 - AZSPWM3, and 9 - DPWM1.

39

0.0130.0140.0150.0160.0170.0180.0190.020.0210.0220.023t(s)-500-400-300-200-1000100200300400500CMV vcm(t) (V)345267891Figure 2.31 FFT of the CMV waveforms at M I = 1 for 1 - SVPWM, 2 - HSVPWMS I, 3 - HSVP-
WMS II, 4 - HSVPWMS III, 5 - HSVPWMS IV, 6 - AZSPWM1-2, 7 - NSPWM, 8 - AZSPWM3,
and 9 - DPWM1.

40

SVPWMDPWM1AZSPWM3NSPWMAZSPWM1-2HSVPWMS IVHSVPWMS III0HSVPWMS II104012HSVPWMS I3451020(a)

(b)

Figure 2.32 Experimental results of the load current ia(t) at (a) M I = 0.85 and (b) M I = 1 for
1 - SVPWM+20A, 2 - HSVPWMS I+15A, 3 - HSVPWMS II+10A, 4 - HSVPWMS III+5A, 5 -
HSVPWMS IV, 6 - AZSPWM1-2-5A, 7-NSPWM-10A, 8-AZSPWM3-15A, and 9-DPWM1-20A.

41

0.0140.0160.0180.020.022-30-20-100102030400.0140.0160.0180.020.022t(s)-30-20-10010203040Load current ia(t) (A)(a)

(b)

Figure 2.33 Experimental results of (a) the HSVPWMS II without implementing the safe com-
mutation algorithm. During the dead-times the effective switching state could be one of the zero
vectors V(0,0,0) or V(1,1,1) and the CMV will be similar to type 1, or it could be similar to type 2
when the effective switching state result in one of the odd or even vectors; (b) the HSVPWMS II
with implementing the safe commutation algorithm, both type 1 and type 2 unwanted transitions
are successfully avoided. M I = 0.85.

42

Chapter 3

Model Predictive Approach to Control the

Amplitude and Frequency of CMV in VSI

Drives

Ever since the invention of the IGBT increasing the switching frequency of the power converter

has been a trend due to the reduction of the footprint and the increase of power density [1]. Recent

development of wide-bandgap devices has equipped the power switches with even faster switch-

ing speed [3]. However, the increase in the switching frequency has generated several unwanted

consequences, one of which is the high-frequency common-mode voltage (CMV) [4]. The high-

frequency CMV can cause electromagnetic interference (EMI) that adversely affects the other

components of the system [7]. The induced over-voltage stress to the winding insulation of the

drives can also increase the shaft current [8]. In particular, the shaft current is the result of the fluc-

tuation of the CMV, which is strictly related to the sequence of the inverter switching states [9].

Several studies presented in the literature discussed the methods of mitigating CMV effects. They

can be classified into hardware solutions and algorithmic solutions. Before using the addtional

passive components, it is essential to provide proper earthing paths to allow the stray current to

return to the inverter frame rather than through the machine bearings [51].

43

The hardware ones require either increasing the number of the inverter switches [11], passive

components [16], or both [26]. The study in this chapter is mostly related to the algorithmic

approaches that require no additional hardware.

On the other hand, algorithmic approaches can be implemented on the exisiting hardware and

offer minimization of the CMV without any additional costs. The early attempt to reduce the CMV

proposed in [9] uses only the odd or only the even voltage vectors. Utilizing only odd or even vector
√
has several drawbacks, such as decreasing the linear region to M I ≤ 4
3
efficiency by increasing the switching losses, and increasing the total harmonic distortion (THD).

, degrading the inverter

3

Later a number of CMV reduction methods were proposed such as the active zero states PWM

(AZSPWM1-2 and AZSPWM3), remote state PWM (RSPWM1, RSPWM2, and RSPWM3) [29],

and near-state PWM (NSPWM) [28]. In each one, several active voltage vectors are utilized to

meet the voltage second requirements and avoid using the zero vectors. The non-zero switching

vectors generate lower magnitude CMV but the conventional space vector PWM uses zero vectors

as it helps in reducing the THD [32]. Although the latter methods utilize all of the linear region

(except for NSPWM), the high frequency of the CMV remains an issue. The high common-mode
dv
dt causes electric discharge machining (EDM) across the bearing races. Furthermore, the CMV
reduction methods assume ideal switches and fail when nonlinearities such as the dead-time and

line-line voltage reversal are considered [34].

Recently, model predictive control (MPC) method has been developed as a simple and effec-

tive control technique for power converters without using PWM modulator [52]. The MPC method

shows that it is very easy to implement all of the six-active-vector approaches and the three-active-

vector approaches [53]. Also, it is possible to apply a restriction on the CMV by adding a penalty

term in the objective function. However, those methods did not bring much improvement over

the conventional PWM methods and did not fully demonstrate the capabilities of MPC methods.

Instead, all of the proposed MPC CMV reduction methods were a direct translation to what previ-

ously proposed using PWM methods. None of the CMV reduction methods in the literature offer

the ability to arbitrarily shape the frequency and the amplitude of the CMV.

44

In this chapter, a novel approach to control the amplitude and the frequency of the CMV,

rather than minimizing it, is proposed. The control concept is based on modifying the existing

MPC method such that CMV can be generated at any arbitrarily set frequency and with minimized

amplitude. Its shown that the proposed algorithm allows arbitrarily adjusting the amplitude and

the frequency of CMV with maintaining low load current THD. The ability to shape the spectrum

of CMV makes it possible to use the high-frequency machine impedance as a filter and reduce the

resulting common-mode current.

The proposed method can be considered as a generalization of the existing approaches that

include the three-active-vector methods, when the CMV frequency is set to zero and the six-active-

vector methods, when the CMV frequency is set to maximum. Therefore, the proposed method

can offer optimal trade-off between the two control areas.

The rest of the chapter is organized as follows. Following the introduction, the conventional

MPC common-mode reduction method are reviewed in Section 3.1. The proposed MPC method is

presented in Section 3.2. The reduction of bearing current is presented in Section 3.3. Finally, the

experimental results presented in Section 3.4.

3.1 Conventional Model Predictive Common-mode Reduction

Methods

The model predictive controller for the three-phase inverter shown in Fig. 3.1 is dependent on

accurate modeling of the load dynamics. For three-phase resistive-inductive (RL) load, the load

voltage equation can be written in the space vector notation as follows:

v = L

di
dt

+ Ri

(3.1)

where v and i are the voltage vector and the current vector in the complex plane, respectively.

L and R are the inductance and the resistance of the load, respectively. Replacing load current

45

Figure 3.1 Three-phase voltage source inverter.

derivative di
the future load current

dt in (3.1) by Euler forward approximation results in the following discrete equation for

(cid:16)

(cid:17)

i(k+1) =

1 − RTs
L

i(k) +

Ts
L

v(k)

(3.2)

where Ts is the sampling period, i(k + 1) is the one step horizon predicted current. In some cases
the second step horizon current i(k + 2) is used to compensate the calculation delay. The objective

of the model predictive controller is to minimize the error between the measured load current

and command reference value through a proper formulation of the objective function. Which is

typically in the form of mean square error between the current command and the predicted currents

resulting from all the eight possible voltage vectors;

(cid:104)(cid:60)i∗
(k+N ) − (cid:60)i(k+N )

(cid:105)2

(cid:104)(cid:61)i∗
(k+N ) − (cid:61)i(k+N )

(cid:105)2

(3.3)

+

J =

where i∗
equal to one because the calculations delay is negligible for high sampling frequency. The voltage

is the reference current and N is number of prediction horizon. In our case N is

(k+N )

vector that minimize J is applied during the entire sampling period Ts can be obtained as follows:

vopt
(k+N )

= arg minv(.,.,.)

{J}

(3.4)

46

iaibics1s2s3s4s5s6vavbvcn0Vdc-VdcLRvcm=vn0where v(.,.,.) is to be chosen from the eight available voltage vectors shown in Table 3.1.

Table 3.1 Voltage vectors and the corresponding differential-mode voltage vdm and CMV vcm
amplitudes.

Voltage vector

V(0,0,0)
V(1,0,0)
V(1,1,0)
V(0,1,0)
V(0,1,1)
V(0,0,1)
V(1,0,1)
V(1,1,1)

vbn

van
vcn
−Vdc −Vdc −Vdc
Vdc −Vdc −Vdc
Vdc −Vdc
Vdc
−Vdc
Vdc −Vdc
−Vdc
Vdc
Vdc
−Vdc −Vdc
Vdc −Vdc
Vdc
Vdc

Vdc
Vdc

Vdc

vdm
0

3

4
3Vdc
3 + j 2√
(2
3 + j 2√
(−2
3
−4
3Vdc
3 − j 2√
(−2
3 − j 2√
(2

3

vcm
−Vdc
−Vdc
3
Vdc
)Vdc
3
)Vdc −Vdc
3
Vdc
3
)Vdc −Vdc
3
3
Vdc
)Vdc
3
Vdc

0

The CMV vcm is defined as the voltage between the n and 0 in Fig. 3.1. It can be expressed in

terms of the phase voltages as follows:

vcm = vn0 =

van + vbn + vcn

3

(3.5)

since we have a very good idea of what would be the phase voltages during each switching com-

bination we can calculate all of the corresponding valued of the CMV using (3.5) as shown in
Table. 3.1. The highest CMV vcm = ±Vdc corresponds to the zero vectors when all of the
three-phase loads are connected to either the upper or the lower DC-rail. Furthermore, there
Vdc
3 and three odd voltage vectors result in
are three even voltage vectors that result in vcm =
vcm = −Vdc
3 . In the conventional MPC method the choice of the voltage vector strictly depends
on the objective function. Therefore, the CMV can potentialy have any value from the ones shown

in Table 3.1. To restrict this drawback various approaches have been presented in the literature.

Fig. 3.2 shows the classification of model predictive CMV reduction methods. The authors briefly

explain the merits and demerits of each approach. It is important to note that the point of interest

here is the MPC methods and not the PWM method. The interested reader may check [28] for

PWM CMV reduction methods analysis.

47

Figure 3.2 Model predictive CMV reduction methods diagram.

3.1.1 Reducing the Sampling Time

The maximum switching frequency of a converter controlled by MPC method is unknown param-
eter but it is upper bounded by the sampling frequency fsw ≤ fs/2 where fs = 1
Ts
from the hardware implementation show that the switching frequency of VSI with RL load is al-
ways between 1
4 fs. Furthermore, results from [54] and [55] show that the area of the
ultimate invariant set in which the error value converge to is inversely proportional to the sam-

5 fs and 1

. Observations

pling frequency. Therefore, reducing the sampling frequency fs leads to more substantial current

tracking error and reduced stability margin.

3.1.2 Cost Function Redesign (CFR-MPC)

One of many benefits of MPC is that the cost function can include all kinds of complex nonlinear-

ities which makes the MPC method a multi-objective optimal control method. The design of the

cost function can be blue divided into two subcategories:

3.1.2.1 Adding Weighting Factor

A secondary term can be added to the cost function to add another control objective beside the

main control objective, which is in our case the current reference tracking. The dominance of the

48

secondary term or terms is adjusted via weighting factor λ as follows:

(cid:124)

(cid:123)(cid:122)

Jmulti-obj. = Jsingle-obj.
primery term

(cid:125)

(cid:124)

+ λ1Jsingle-obj.1 + ... + λnJsingle-obj.n

(3.6)

(cid:123)(cid:122)

secondery terms

(cid:125)

cm| and λ1 is the
where Jsingle-obj.1 can be the predicted value of the CMV |vcm − v
weighting factor. The first formulation for the secondary objective function restricts the change

cm| or |v
p

p

in CMV when making a control decision. As the value of λ increases the frequency of the CMV

decreases with some sacrifice on the THD of the load current. The second formulation makes the

MPC controller chose the vectors that correspond to a low CMV, immediately disregarding the

use of the zero vectors. However the second formulation becomes unnecessary when λ increases
3 |. The reduction of CMV
since the CMV for all of the active vectors of the VSI is equal to | Vdc
can also be achieved in less direct way by adding constrain on the switching frequency or the

number of actuation [56]. In spite of using weighting factor is easy to implement, the stability

of the converter is comprised. The weighting factor should be tested empirically by starting from

zero and increasing it in a very small steps until the desired behavior is obtained. Furthermore, it

has been shown that in most cases the control over the secondary term is not linearly related to the

change in the weighting factor which makes the behavior of the inverter unpredictable [57].

3.1.2.2 Frequency Domain Control of the Cost Function

The cost function can be controlled by augmenting a filter to achieve additional degree of objective

function. Although this was initially proposed to shape the load current spectrum [59] and control

the thermal stress [60], they both used to control the switching frequency of the converter and

hence controlling the CMV.

49

Figure 3.3 The highlighted region is the available linear region in: (a) using the even vectors only;
(b) using the odd vectors only.

3.1.3 Zero-vectors Removal (6V-MPC)
As it has been shown that the zero-vectors V(0,0,0) and V(1,1,1) produce −Vdc and Vdc CMV
amplitudes, respectively. This is three time greater than the CMV amplitude produced when em-

ploying any of the other six active-vectors. There are few methods based on the zero-vector re-

moval such as

3.1.3.1 Using Only the Active Vectors

Only the nonzero voltage vector can be used to minimize the current error [61]. This limit the
CMV amplitude to |Vdc
3 |.

3.1.3.2 Using Only the Odd or the even Active Vectors

Although, the previous method reduceds the CMV to |Vdc
3 |, it’s switching frequency is relatively
high due to the switching between the nonadjacent vectors [58]. The CMV can be a constant DC

value if either only the odd or only the even active vectors are included in the finite-set of the
objective function. However, this results in a significant reduction in the linear region to M I ≤ 2
3
as shown in Fig. 3.3.

The recently proposed zero-vector removal methods are all translation from what it have been

proposed by Hava [28] using PWM. They do not fully exploit the effectiveness and abilities of the

MPC method. Therefore, a new selective voltage-set MPC (SVS-MPC) method is proposed next.

50

V(1,0,0)V(0,1,1)(a)(b)4/3Vdc2/3VdcAvailable region when using only the odd active vectorsAvailable region when using only the even active vectors3.2 Proposed Selective Voltage-sets Commutation MPC Method

The odd active vectors {V(1,0,0), V(0,1,0), V(0,0,1)} produce CMV amplitude equal to −Vdc
3
and the even active vectors {V(0,1,1), V(1,0,1), V(1,1,0)} produce CMV amplitude equal to +
Vdc
3 .
Therefore, by selecting one of these two voltage set at a time, the concept of voltage-sets commu-

tation can be realized. The selective voltage set MPC achieve control over the amplitude and the

frequency of the CMV. Furthermore, the linear region can be extend such that the modulation index

can be increased to maximum based on the rate of the commutation. The commutation between

odd set to even set or even set to odd set can be easily implemented by defining three virtual voltage

vectors as follows:

vx = hV(1,0,0) + (1 − h)V(0,1,1)
vy = hV(0,1,0) + (1 − h)V(1,0,1)
vz = hV(0,0,1) + (1 − h)V(1,1,0)

(3.7)

(3.8)

(3.9)

where vx,vy, and vz belong to the set of the active non zero vectors {V1,0,0, V1,1,0, ..., V1,0,1}.
h ∈ {0, 1} is a discrete-valued function of the CMV modulation signal. It can be either one or
zero. When h = 1, only the odd active-vectors are used. When h = 0, only the even active-vectors

are used. By only controlling h in (3.7), (3.8) and (3.9) the concept of commutation between the

odd and the even vectors can be extended such that the entire linear region is available and the

control over the frequency of the CMV is realized as shown in Fig. 3.4.

The load current predictive model bock diagram is illustrated in Fig 3.5 and the means square

error (MSE) objective function is illustrated in Fig 3.6. Note that the measured load current is trans-

formed from abc to αβ stationary reference frame using Clarke transformation. The algorithms as

well have the flexibility to extrapolate the input reference current and increase the number of pre-

diction horizon N.

1. Sequenced Commutation (SC): In which the commutation between odd and even vector

occurs every n sampling times. Therefore, we can define the ratio between the odd vector

51

Figure 3.4 Control block diagram of the three-phase VSI with SVS-MPC controller.

Figure 3.5 Load current prediction.

Figure 3.6 Objective function in a form of mean square error (MSE).

52

implementation and the even vectors implementation as

nT s = noTs + neTs

Doe =

no

no + ne

(3.10)

(3.11)

where {no, ne ∈ N : no, ne ≤ n}. In our case the realization is simplified by comparing
triangular carrier with a constant number and Doe is set to 50%. In contrary, when Doe =

100% only the odd vectors are used and when Doe = 0% only the even vectors are used.

2. Pulse Width Modulation Commutation (PWMC): In which the the frequency and amplitude

of the CMV are modulated by using sinusoidal duty ratio Doe.

A Simulink model for the system shown in Fig. 3.1 is built to simulate the two approaches.

Fig. 3.7 shows the sequenced commutation approach when the system fundamental frequency is

60 Hz and the M I = 0.9. Although the sampling time for the MPC algorithm is set to 10 µs the

CMV frequency spectrum is concentrated at the commutation frequency 5 kHz.

Fig. 3.10 shows the PWM approach when the system fundamental frequency is 60 and the

M I = 0.9. The CMV is concentrated at the CMV carrier frequency 5 kHz. For the PWM method,

the CMV amplitude at the carrier frequency can be changed based on the CMV reference level. At

high modulation index the CMV reference amplitude should not exceed 0.45 in order to achieve

acceptable load current THD. Fig. 3.9 shows the trade-off between the reference amplitude setting

and the corresponding load current THD. As the reference amplitude increases the CMV at the

corresponding frequency (60 Hz) increases with some sacrifice on the load current THD.

Decoupling the frequency of the CMV from the sampling frequency of the MPC method pro-

vides an extra degree of freedom to limit the bearing current. In the next section the bearing current

for the proposed method will be compared with the ones from the conventional MPC methods.

53

(a)

(b)

(c)

Figure 3.7 Simulation results of MPC-SC at 60 Hz fundamantal frequency. Ts = 10 µs, 1/nTs = 5
kHz, Doe = 50%. Load current THD= 4.2%.

54

0234-100100123451040510commutation frequency(a)

(b)

(c)

Figure 3.8 Simulation results of MPC-PWM at 60 Hz fundamantal frequency. Ts = 10 µs, CMV
reference amplitude= 0.45, CMV carrier frequency = 50 kHz. CMV carrier phase-shift= −8o.
Load current THD= 4%.

55

0234-1001010*v*cm0123451040510carrier frequencyfundamental frequencyFigure 3.9 The trade-off between the reference amplitude (RA) and the THD of the load current.
As the reference amplitude increases the CMV amplitued ad the reference frequency increases
with some sucrifice on the load current THD. M I = 1.

3.3 Bearing Current Reduction

The different bearing currents vary with the motor size and grounding configuration. Therefore, the

mitigation technique have to be chosen for different drive specifications. Recent years have seen

rising number of electric discharge machining (EDM) type of bearing failure in AC drive system,

sometimes, the failure happens few months after start-up [51]. The source of the EDM current is

the voltage induced over the bearing vb which is the potential between the inner and the outer race
of the bearing. The bearing voltage mirror the CMV at the motor terminal by a capacitive voltage

divider

vb
vcm

=

Cwr

Cwr + Crf + 2Cb

= BV R

(3.12)

where Cwr is the stator winding-to-frame capacitance, Crf is the rotor-to-frame capacitance, and
Cb is the bearing capacitance as shown in Fig. 3.11. BV R is the bearing voltage ratio.

The electrically loaded lubrication film between the balls breaks down when a threshold voltage
of vb,th ≈ (5...30) V is reached. The exact break down voltage of the lubricant can only be

56

05RA=0.4510RA=0.415RA=0.3RA=0.25104432RA=0.110THD of ia,b,c=2.6%THD of ia,b,c=3.2%THD of ia,b,c=3.9%THD of ia,b,c=4.3%THD of ia,b,c=4.6%(a)

(b)

Figure 3.10 The transient behavior of the load current during a step change from 5 A (M I = 0.45)
to 10 A (M I = 0.9) (a) MPC-SC and (b) MPC-PWMC.

Figure 3.11 Equivelent circuit of the main capacitances of an induction machine or PM machine
that are important in high frequencies.

57

CwrCb, DECrfCb,NDE3Cwfvcmvbestimated because it changes with the machine speed and the bearing temperature.

All the parasitic capacitances are assumed not to change with the operating conditions. Due to

the fast switching, vb build up repeatedly and discharge at vb ≈ (5...15) V.

Figure 3.12 Equivalent circuit of EDM current discharge.

The process of calculating the bearing current discharge is well presented in ( [62], section

7.4). Although the bearing current can not be measured, the current measured in the copper loop

shown in Fig. 3.14 can be utilized indirectly to verify the simulation model. The high frequency

machine model shown in Fig. 3.14 is used to calculate the bearing discharge current ib. EDM
bearing current does not occur with each switching instant, but when the lubricant film has been

loaded [62]. Here we assume the worst case scenario by assuming that vb reaches vb,th every
CMV switching instant. Reducing the number of EDM discharges occurrence results in smaller

average value of bearing current [63]. The average value of the bearing current can be reduced

enormously by reducing the frequency of the CMV. Fig. 3.13 shows the bearing current resulting

from the conventional MPC methods and the proposed selective voltage set methods. It is evident
that because the selective voltage set methods can reduce the CMV frequency below 1
2fs, the

resulting bearing charge is reduced and hence the number of the electric discharges.

Furthermore, there is an optimal common-mode frequency in which the minimum common-

mode current can be achieved for high switching frequency setting. This could be a very attractive

feature in high-frequency applications that utilize the wide-band-gap devices. Furthermore, new

machine design objectives could be considered to increase the dip effect in the machine impedance

so that a low admittance path can be provided to the CM current. One of the main differences

between the proposed selective voltage set and the conventional CFR-MPC method is that the

58

DischargeSwitch when vb = vb, thLcuicCb, DECrfCb, NDEvbibLRbibRcuCi(a)

(b)

(c)

(d)

(e)

Figure 3.13 Comparsion of bearing currents ib of the conventional MPC methods and the proposed
selective voltage set MPC methods. Vdc = 250 V, f = 60 Hz, and M I = 0.9..

59

5678910111210-3-101MPC5678910111210-3-1016V-MPC5678910111210-3-101CFR-MPC, =0.015678910111210-3-101MPC-SC5678910111210-3-101MPC-PWMClater method is unable to control the frequency of the CMV. The frequency of the CMV can be

only reduced by increasing the weighting factor in the objective function. This result in unpre-

dictable behavior by the converter when the weighting factor increased above the limits. Fig. 3.14

shows that as the weighting factor increases the CMV frequency decreases and the THD of the

load current increases. Increasing λ to 0.021 results in inferior current tracking performance. It

is essential to calibrate the weighting factor range on the hardware itself. This uncertainty puts

stringent limitations on the practical viability of this approach.

]

Figure 3.14 Frequency spectrum of CMV and the load current THD with changing the weighting
factor λ.

3.4 Experimental Results

The experimental work to validate the simulation results has been carried out using the rated pa-

rameters and operating conditions. Fig. 3.15 shows the experimental setup. The system consists of

60

0100200300400500f(kHz)-20020406080CMV Magnitude (dB)=0, THD of ia,b,c=1%=0.01, THD of ia,b,c=1.65%=0.02, THD of ia,b,c=2.3%three inverter legs with each leg being realized with IGBT module CM100DY-24A. The control al-

gorithm is implemented using DSpace CP1103. The CMV is measured as the voltage between the

three-phase star connection and the center tap of the DC-link as shown in Fig. 3.1. The parameters

used for the experiment are listed in table 3.2. First the experimental results for the conventional

Table 3.2 Experimental test patameters.

Parameter
DC-link voltage
Load inductance
Load resistance
Load current reference range
Sampling time

Value

50 and 60 V
1 and 2 mH
2.5 and 5 Ω
3 and 10A

10 µs

MPC method is shown in Fig. 3.16. The amplitude of the CMV is |Vdc| with frequency spectrum
ranges all across the sampling frequency spectrum. In our case the sampling time is 10 µS, there-

fore, the frequency spectrum of the CMV is between (0, 50) kHz. The cost function redesign is

presented in Fig. 3.17. The added weight (λ=0.01) in the cost function reduces the use of the zero

vector, therefore, the amplitude of the CMV is lower than the one from the conventional MPC

method. Fig. 3.18 shows the experimental results when both zero vectors are not used. In this case
the amplitude of the CMV is reduced to |Vdc
3 |. However, the frequency of the CMV still within
the entire range of half the sampling frequency. None of the previously proposed methods can

control the frequency of the CMV to reduce the number of current discharges in the bearing. The

normal range of the DC-link voltage is large enough to accumulate charge across the bearing races.

Therefore, it is not possible to reduce or limit the number of current discharges in the bearing using

the previous methods.

On the other hand, the experimental results of sequenced commutation method when the fun-

damental frequency is 60 Hz are shown in Fig. 3.19(a) and (b), where the period of the CMV is set

to 0.0033 s. The characteristic of the CMV is completely decoupled from the other operating con-

ditions. The spectrum of the CMV shows that the CMV is concentrated at the chosen commutation

frequency 3.3 kHz.

61

The experimental results of pulse width modulation commutation method when the funda-

mental frequency is 60 Hz are shown in Fig. 3.20(a) and (b), where reference waveform is 0.2,

frequency 2 Hz, and the carrier frequency is 5 kHz. The characteristic of the CMV is completely

decoupled from the other operating conditions. The spectrum of the CMV shows that the CMV is

concentrated at the chosen carrier frequency 5 kHz.

The MPC-PWMC is more capable than the MPC-SC method in concentrating the frequency

of the CMV at the carrier frequency. The simulations and experimental results show that MPC-

SC and MPC-PWMC method produce similar current tracking performance. The THD of the

load current can be further reduced when the commutation frequency is increased. The choice of

which control method is better in implementation is solely dependent on the characteristic of the

impedance of the machine. Generally, reducing the CMV frequency as minimum as it possible

without sacrificing much of the load current quality is the goal. In a very high switching frequency

applications the resonance dip in the frequency response of the machine impedance can be utilized

as a filtering factor. The proposed method is the only method that allows to arbitrarily select the

frequency of the common-mode voltage at any region below half the sampling frequency.

The implementation of only odd or only even vectors requires simultaneous switching of two

converter legs. In practice, this could be challenging because of the dead-times and the differences

in the gate delay [60]. The dead-time mismatch causes a narrow pulse in the CMV. The narrow

pulse frequency increases as the switching frequency increases. During the dead-times, the result-

ing CMV is no longer a function of the switching commands. Instead, it is strictly dependent on

the signs of the load currents. The interested reader may check [60] for examples and solutions for

the dead-time problem when using only odd and only even. In this study the sampling time is set to

10 µs, therefore, by observation, the switching frequency of the converter is approximately 15kHz.

By increasing the dead time from 0.5 µs to 1 µs The effect of deadtime can be more evident as
shown in Fig. 3.21 (a) and (b). The high peaks (Vdc and −Vdc) are occurring because at some
deadtime intervals the zero vectors are activated.

The implementation of only odd or only even vectors requires simultaneous switching of two

62

Figure 3.15 The experimental setup.

63

Figure 3.16 Experimental results of MPC method load current ia,b,c, CMV vcm, and FFT of CMV.

Figure 3.17 Experimental results of CFR-MPC method load current ia,b,c, CMV vcm, and FFT of
CMV.

64

Figure 3.18 Experimental results of 6V-MPC method load current ia,b,c, CMV vcm, and FFT of
CMV.

converter legs. In practice, this could be challenging because of the dead-times and the differences

in the gate delay [60]. The dead-time mismatch causes a narrow pulse in the CMV. The narrow

pulse frequency increases as the switching frequency increases. For instance, consider Fig. 2.8,

during the dead-times, the resulting CMV is no longer a function of the switching commands.

Instead, it is strictly dependent on the signs of the load currents. The interested reader may check

[60] for examples and solutions for the dead-time problem when using only odd and only even. In

this study the sampling time is set to 10µs, therefore, by observation, the switching frequency of

the converter is approximately 15kHz. The dead-time is reduced to less than 0.5µ to reduce the

effect of short pulsed in the CMV.

65

(a) M I = 0.5, T HD = 4.8%

(b) M I = 0.9, T HD = 4%

Figure 3.19 Experimental results for the proposed MPC-SC method load current ia,b,c, CMV vcm,
and FFT of CMV.

66

(a) M I = 0.5, T HD = 4.8%

(b) M I = 0.9, T HD = 3.8%.

Figure 3.20 Experimental results for the proposed MPC-PWMC method load current ia,b,c, CMV
vcm, and FFT of CMV.

67

(a)

(b)

Figure 3.21 Load Current transient behaviour during a step change from 3 A to 6 A.

68

Chapter 4

Generalized Chudnovsky Algorithm for

Real-time PWM Selective Harmonic

Elimination/Modulation: Two-Level VSI

Example

4.1

Introduction

The selective harmonic elimination (SHE) technique effectively reduces the low-order harmonic

content of inverter output waveform and generates a high-quality spectrum through the elimination

of specific low-order harmonics [64] [65]. Therefore, it has been applied in power electronic

controllers extensively, and many related techniques have been proposed in recent years [66]- [70].

The traditional implementation of SHE is to use a lookup table and a modulator driven by a

very slow control loop to ensure steady-state stability [71]. Offline SHE implementations share

the crucial drawback: the switching angles could not be calculated in real-time and one has to

rely on loading the optimal switching angles for each specific modulation index (Mi). During the
transient state of a low switching-frequency drive, the low-frequency component of the reference

69

Figure 4.1 Two-level voltage source inverter drive.

voltage becomes nonsinusoidal [72]. The switching sequence will then be implemented with the

optimal angles saved in the lookup table, which is only valid for steady-state conditions. The

resulting current dynamic will be far from optimal. Furthermore, there are other sub-transient

conditions such as changing the number of switching events per cycle and changing Mi, which
will result in the sub-optimal current performance.

It is important to make the distinction between different types of real-time or online solutions of

SHE. Some online SHE algorithms solve the optimization problem in the controller using an itera-

tive process with guessed initial values. Although these methods reduce the memory requirement,

they suffer from a poor dynamic performance that is typically inferior to the dynamic performance

of the look-up table implementations. For instance, the supposedly real-time method in [73] is

unable to perform rapid changes in Mi. It would take 58 ms to change Mi from 0.96 to 0.64.
Furthermore, the presented implementation results in larger total harmonic distortion (T HD) than

the offline solution. Other methods also claim the real-time feature while the solution requires

an initial guess and an indeterminate number of iterations [74]. In [75], the switching angles are

70

vbLRMotorVdcSaSbScSaSbScvavcibiaicapproximated using curve fitting of the offline solution. Then a carrier waveform is calculated by

a cosine function based on the modulation depth. This approach requires saving the curve fitting

coefficients for each modulation index. If 1% resolution is desired, it would require 100 polyno-

mials to describe each switching angle. Not to mention that if the switching frequency is changed,

a new set of equations is required for each angle. In [76], Chebyshev polynomials are used to

convert a set of the transcendental equations into algebraic polynomials. Then the algebraic equa-

tions are rearranged through a change of variables to solve for the switching angles. However,

the transformation of the transcendental equations is not systematic, and no generalization was

given to simplify the process of transforming the transcendental equations to algebraic equations.

The complexity of the derivation increases as the number of the selected harmonics increases.

Furthermore, the set of the algebraic equations is solved using inverse cosine function, but the

computational effort could be reduced by converting the set of the algebraic equations to a single

polynomial. All these drawbacks with the strict operating requirements of high power industrial

drives pose serious limitations on the practical viability of the existing approaches.

A new implementation of the real-time selective harmonic elimination (RTSHE) is proposed in

this paper. The original contributions of the proposed RTSHE are the following:

1· Presenting the generalized Chudnovsky algorithm. The new algorithm allows modulating

the selected harmonics rather than only eliminating them.

2· Presenting a new method of obtaining the values of the optimal switching angles from the

polynomial in real-time without resorting to any iterations or guesses.

Preliminary results were published in [64] show that the real-time approach could be a suit-

able replacement for the conventional offline method. In this article, the authors expand the real-

time algorithm to a generalized form without increasing the computational effort. The algorithm

is demonstrated through the experiment of the two-level voltage source inverter (VSI) shown in

Fig. 4.1. A comparison between the proposed RTSHE method and the conventional offline method

is presented throughout the paper.

71

The rest of the paper is organized as follows: The proposed RTSHE method is presented in

section II. The comparison between the proposed RTSHE and the conventional offline method

is presented in section III. The selective harmonic modulation (RTSHM) method is presented in

section IV. The experimental results are presented in section V. Finally, the conclusion is presented

in section VI.

4.2 The Proposed Real-Time Selective Harmonic Elimination

The development of RTSHE starts from manipulating the transcendental equations. Owing to the

symmetry of the PWM waveform, only odd harmonics exist. By chopping the PWM waveform n

times per quarter cycle, the Fourier coefficients of the odd harmonics are given by

(cid:20)

bk = −4Vdc

kπ

1 − 2

(cid:21)
(−1)i−1 cos(kαi)

n(cid:88)

i=1

,

(4.1)

where k is the harmonic order number {1, 3, 5, ...}, n is the total number of the switching angles
per quarter fundamental cycle, Vdc is the DC-link voltage, and αi is the optimal switching angle.
In SHE, the fundamental component (k = 1) is set to a desired amplitude, and the other selected

odd harmonics are set to zero. This formulation of the optimization problem leads to the following

set of transcendental equations:

1 − 2 cos(α1) + ... + (−1)n2 cos(αn) = − πb1
4Vdc
1 − 2 cos(3α1) + ... + (−1)n2 cos(3αn) = − 3πb3
4Vdc

.

.

1 − 2 cos(kα1) + ... + (−1)n2 cos(kαn) = −kπbk
4Vdc

.

(4.2)

72

4.2.1 Converting the Transcendental Equations to Algebraic Equations

By using Chebyshev polynomials, the transcendental equations in (4.2) can be transformed to
algebraic equations [77]- [78]. This can be achieved by letting xo = cos(αo) and xe = − cos(αe),
where the subscripts o and e denote the odd and even numbers, respectively. This leads to the

following set of algebraic polynomials:

x1 + x2 + ... + xn = s1
x3
1 + x3

2 + ... + x3

n = s3

.

.

x2n−1

1

+ x2n−1

2

+ ... + x2n−1

n

= s2n−1,

(4.3)

where x1, x2, ..., xn, hold the solution of the switching angles α1, α2, and αn, respectively.
s1, s3, ..., s2n−1 can be obtained using the proposed recursive algorithm:

T2n−1(x)|

(x2n−1=s2n−1)

=

1
2

+

πb2n−1
8Vdc

,

(4.4)

where T2n−1(x) is a Chebyshev polynomial of the first kind [80]. This can be found through the
recursive formula

Tn+1(x) = 2xTn(x) − Tn−1(x),

(4.5)

where T0(x) = 1 and T1(x) = x. For instance, if the desired fundamental component is set to a
specific value b1 and the rest of the odd harmonics are set to zero, the following values for s can
be obtained:

73

(cid:20)
(cid:20)

1 +

1 +

(cid:21)

πb1
4Vdc
πb1
3
4
4Vdc

(cid:21)

1
2
1
2

s1 =

s3 =

.

.
s2n−1 =

(cid:34)

1
2

1 +

πb1

4n−14Vdc

(cid:19)(cid:35)
(cid:18)2n − 1

n − 1

.

(4.6)

In the case of a three-level VSI such as the neutral point clamped (NPC) inverter or the single phase

inverter [79], the following equation can be used to calculate s:

(cid:18)2n − 1
(cid:19)

n − 1

.

s2n−1 =

πb1

4n−14Vdc

(4.7)

The generalized formulas (4.6) and (4.7) circumvent the offline recursive derivation effort. The

remarkable fact is that the definition of s becomes explicit, rather than recursive. One can now

start the optimization problem from writing down the algebraic polynomials (4.3) directly, without

going through the earlier steps.

4.2.2 Converting the Algebraic Equations to a Single Polynomial

The set of algebraic polynomials in (2) is a symmetric sum of powers. Therefore, it can be further

reduced to the following form of the single polynomial using Newton’s identities:

P (x) = p0xn + p1xn−1 + ... + pn = 0,

(4.8)

74

where p0 = 1, and p1 to pn can be obtained using the generalized version of Newton’s identity
first presented in [79]. If the series expansion for the desired polynomial is

n(cid:89)

i=1

P (x) =

(x − xi),

then by algebraically manipulating the polynomial terms we get

P (x) = xn exp(−

sm
mxm ),

∞(cid:88)

m=1

(4.9)

(4.10)

where sm is the power series representation of the polynomials in (4.3). As in [79], one can
eliminate the multiplication xn term by dividing (4.10) by P (−x). This leads to the following
expression:

where

P (x) = (−1)nP (−x)G(1/x),

(cid:18)

(cid:19)

G(1/x) = exp

V (1/x)

= exp

(cid:18)

− 2

∞(cid:88)

m=1,3,5,...

(cid:19)

.

sm
mxm

(4.11)

(4.12)

It is possible to analytically express G(1/x) using the generating function approximation:

G(x) = g0 + g1x + g2x2 + ... =

gnxn.

(4.13)

Generating functions are a single quantity that represents the whole sequence. They were intro-

duced by De Moivre to solve a class of general recurrence problems [81]. We can recover the

individual value of g1, g2, ... from G(x) by assuming that the infinite sum (4.13) exists for some
value of x. The exponential term eV (1/x) in (4.12) can also be represented by the following

generating function:

V (x) = v0 + v1x + v2x2 + ... =

75

vnxn.

(4.14)

(cid:88)

n≥0

(cid:88)

n≥0

After calculating the values of (4.13) and (4.14), each x in the equation will be replaced by its re-

ciprocal to match (4.12). The coefficients of G(x) can be obtained by using the binomial theorem.

However, Euler discovered an efficient method to obtain the power series powers [82]. Consider

the following equation:

G(x) = eV (x).

By taking the derivative for both sides

dG(x)

dx

=

dV (x)

dx

G(x),

(4.15)

(4.16)

expanding both sides

g1 + 2g2x + 3g3x2 + ... =

rearranging the RHS

g1 + 2g2x + 3g3x2 + ... =

(v1 + 2v2x + 3v3x2 + ...)(g0 + g1x + g2x2 + ...),

(4.17)

(v1g0) + (2v2g0 + v1g1)x + (3v3g0 + 2v2g1 + v1g2)x2 + ...,

(4.18)

and by equating the coefficients of the LHS with the RHS, we find that

n(cid:88)

k=1

gn =

k
n

vkgn−k,

(4.19)

where g0 = ev0 = 1. This leads to a simple real-time algorithm by which we can successively
determine the coefficients of G(x). To avoid the forbidden abstract way of presenting results, the

authors provide the following non-trivial example.

76

Figure 4.2 Illustration of obtaining the value of the optimal switching angles by solving the poly-
nomial in real-time.

Example

Suppose that for a three-phase voltage source inverter, we are required to eliminate the first three

odd harmonics 3rd, 5th, and 7th, and set the modulation index to 0.6283 =

voltage is 100V.

πb1
4Vdc

. The DC-link

The first step is to calculate the value of s for each polynomial in (4.3) using the proposed

generalized formula (4.6) as follows:

s1 =

1
2

(cid:34)

1 +

(cid:19)(cid:35)
(cid:18)1

0.6283

40

0

= 0.8141.

By plugging in (4.6) n = 2, n = 3, and n = 4, we can find that s3 = 0.7356, s5 = 0.6963, and
s7 = 0.6718, respectively. Now the symmetric power sum (4.3) can be written as

x1 + x2 + x3 + x4 = 0.8141
1 + x3
x3
x5
1 + x5
x7
1 + x7

3 + x3
3 + x5
3 + x7

2 + x3
2 + x5
2 + x7

4 = 0.7356

4 = 0.6963

4 = 0.6718.

77

(4.20)

The next step is to reduce the system of equation in (4.20) to a single polynomial of order 4

such that the roots of the polynomial are the values of x1, x2, x3, and x4 in (4.20). Using the
expression in (4.12) for V (1/x), we can calculate the coefficients of the V (x) series as follows:

V (1/x) = −2

∞(cid:88)

m=1,3,5,...

sm
mxm

⇒ V (x) = −2

∞(cid:88)

m=1,3,5,...

sm
m

xm,

where the term −2 sm
are set to zero, v0=0. The calculations lead to the following vector:

m is equal to the coefficient vm+1

2

in the generating function (4.14). s2, s4,...

v = [v0, v1, v2, v3, v7, v5, v6, v7, v8]T =

[0,−1.6283, 0,−0.4904, 0 − 0.2785, 0,−0.1919, 0]T .

After obtaining V (x), eV (x) can be calculated using (4.19), where g0 = eV (0) = 1,

1(cid:88)

k=1

g1 =

2(cid:88)

k=1

g2 =

k
2

vkg2−k =

vkg1−k = v1g0 = v1 = −1.6283,

k
1

1
2

v1g1 +

2
2

v2g0 =

1
2

(−1.6283) ∗ (−1.6283) + 0 = 1.3257.

78

By calculating all of the coefficients, one can obtain the following vector:

g = [g0, g1, g2, g3, g7, g5, g6, g7, g8]T =

[1,−1.6283, 1.3257,−1.2099, 1.0914,

− 1.0240, 0.9525,−0.9067, 0.8570]T .

Now we have all the elements to evaluate the single polynomial by expanding (4.11) and negat-

ing the coefficient of the same power from both sides. Note that p0 = 1

P (x) = (−1)nP (−x)G(1/x)

p0x4 + p1x3 + p2x2 + p3x + p4 =

(p0x4 − p1x3 + p2x2 − p3x − p4)(1 + g1/x + g2/x2 + ... + g8/x8).

This leads to the following trapezoidal system:

 =





p1

p2

p3

p4

g4 −g3 g2 −g1
g5 −g4 g3 −g2
g6 −g5 g4 −g3
g7 −g6 g5 −g4


−1

g5

g6

g7

g8

 =



 .

−0.8142
−0.6135

0.4342

0.0192

The polynomial is

P (x) = x4 − 0.8142x3 − 0.6135x2 + 0.4342x + 0.0192.

(4.21)

The same example can be solved using the script shown in Fig. 4.3.

Now we know how to calculate the polynomial, a novel technique of determining the switching

angles from the single polynomial in real-time will be presented in the next section.

79

Figure 4.3 Matlab script solving the example.

80

Figure 4.4 The zero crossing occurs at the optimal switching angle.

4.2.3 Obtaining the Optimal Switching Angles

The implementation of the RTSHE can be divided into two routines. A short routine is used when

there is a change in the output voltage fundamental frequency, and a longer routine is used when

there is a change in either the modulation index, or the number of switching events per fundamental

cycle. Typically, under the steady-state conditions, the short routine will be executed. When there

is a change in the modulation index, a subroutine to calculate the new polynomial coefficients is

triggered as shown in Fig. 4.2.

First, the reference voltage angles of the three-phase reference voltage are extracted. Then the
optimal switching angles are obtained by a simple substitution of x = cos(φ) and x = − cos(φ)
in P (x), where φ is the reference angle of the phase voltage. When the value of the polynomial is

equal to zero, a root of the polynomial is detected as shown in Fig. 4.4. To extract the switching

81

02t (rad)-101command Sa in real-time, the authors present a technique similar to Descartes’ sign rule as shown

in the large square in Fig. 4.2.

The proposed technique allows for obtaining the actuation commands in real-time without the

need to solve the roots of the polynomial, which cannot be done in determinate real-time.

There is no need to worry about sorting the optimal switching angles from lower value to larger

value. The direct substitution produces the switching angles with the correct order. The solution

of the polynomial does not require great computational effort as it is a direct substitution and does

not involve an iterative process or initial guessing. Furthermore, the proposed algorithm is valid

for multilevel inverters. The only thing that needs to be changed is to use (4.7) instead of (4.6) and

rearrange the logic in Fig. 4.2 to provide the switching functions for all of the switches.

The straightforward evaluation of a polynomial using a floating point controller would follow
this form: p0xn is calculated, then p1xn−1, . . . , pn−2x, and finally all the terms are added.
Such a process requires 2n − 1 multiplications and n additions. To optimize this process, one
can use Horner’s rule to rearrange the computation of the polynomial. Horner’s rule requires n

multiplications and n additions [83]. Furthermore, there is no need to store the partial results since

each quantity arising during the calculation can be used immediately after it has been computed.

The computational effort can be further reduced by adaptation of the coefficients [83]. Since

the leading coefficient in RTSHE polynomials has the largest value, the division by the leading

coefficient will never lead to instability.

4.3 Comparison with the Offline Selective Harmonic Elimina-

tion

The traditional approach of implementing the selective harmonic elimination method is by solving

the transcendental system of equations (4.2) using an iterative method. Since the solution needs to

be evaluated for each possible modulation index, it is more convenient to solve for a limited num-

ber of modulation indices and extrapolate the values of the optimal switching angles between every

82

two solutions and store the data in the form of curve fitting polynomials. The interested reader may

check [84] where the Newton-Raphson iterative method is used to solve the transcendental equa-

tions. As the number of selected harmonics increases, Newton’s method becomes more sensitive

to the initial conditions. For instance, to achieve convergence for six switching angles per quarter

fundamental cycle, one needs to use the solution from the previous few steps instead of the most

recent step. The uncertainty of the initial guess along with the indeterminate convergence time, if

any, makes the real-time implementation of the transcendental equations an unattractive approach.

Since the real-time selective harmonic elimination involves more mathematical processes, it is es-

sential to check the numerical difference between the real-time solution and the solution obtained

by offline calculation. Fig. 4.5 shows the numerical difference of the first three odd harmonic mag-

nitudes of the real-time approach and the offline approach in both 60 Hz and 120 Hz fundamental

frequencies. Fig. 4.6 shows similar results when eliminating the first six odd harmonics.

In Fig. 4.5, the value of the third harmonic in the offline approach is larger than the one from

the real-time implementation. This due to the inaccuracy of the curve fitting. It can be improved by

creating a higher order polynomial to represent the curve. In our case, the order of the curve fitting

polynomial is kept equal to the order of the univalent polynomial of the real-time implementation.

The norm of residuals along with other error-contributing factors are quantified in Table I. Fig. 4.7

shows the total harmonic content divided by the fundamental component. This number does not

change when n is increased from 4 to 6 to 8,..., etc. The benefit of increasing n is that all of the

harmonics concentration will be located to the right of the last eliminated harmonic. This result in

harmonic content with higher frequency. Therefore, the current resulting from these harmonic will

have less amplitude due to the inductive nature of the load impedance (ZL = 2πf L). Furthermore,
it is important to note that the total harmonic content is exactly the same as the one produced by

the offline SHE.

83

Figure 4.5 Numerical results show a comparison between the proposed real-time method and the
conventional offline method eliminated harmonics magnitude when eliminating the first three odd
harmonics. The results shown are in two fundamental frequencies 60 Hz and 120 Hz.

84

Figure 4.6 Numerical results show a comparison between the proposed real-time method and the
conventional offline method eliminated harmonics magnitude when eliminating the first five odd
harmonics. The results shown are in two fundamental frequencies 60 Hz and 120 Hz.

85

Figure 4.7 Total harmonic content divided by the fundamental component for both the offline SHE
and the proposed real-time SHE. Note that this number does not change by changing the number of
eliminated harmonics, instead, the harmonics get shifted to the right of the last eliminated harmonic
and this result in a better load current performance. This is due to the fact that higher-frequency
harmonics face higher impedance in an inductive load.

4.4 Selective Harmonic Modulation

So far the intent behind implementing the RTSHE is to achieve a desired modulation index and

to eliminate the lower order harmonics. In this section, we show that the proposed RTSHE can

be generalized such that the lower order harmonics can have any arbitrary value rather than zero.

Hence the generalized method is called the real-time selective harmonic modulation RTSHM.

Starting from the system of algebraic polynomials in (4.3), s1, s3, ..., s2n−1 can be obtained

using the proposed recursive algorithm:

T2n−1(x)|

(x2n−1=s2n−1)

=

1
2

+

nπb2n−1

8Vdc

.

(4.22)

86

0.10.20.30.40.50.60.70.80.91MI*4/051015T.H.C./Fund.Comp.To better understand the proposed algorithm, we apply it to the earlier example: for that matter

the modulation index is kept at 0.6283 and the third harmonic b3 = 0.2. The substitution of the

Chebyshev’s first polynomial (T1 = x) in (4.22) yields

s1 =

1
2

+

πb1
8Vdc

.

Similarly, the substitution of Chebyshev’s third polynomial (T3 = 4x3 − 3x) in (4.22) yields

4s3 − 3s1 =

1
2

+

3πb3
8Vdc

s3 =

3s1
4

+

3πb3
32Vdc

+

1
8

and

s5 =

5s3
4

− 5s1
16

+

s7 =

7s1
64

− 7s3
8

+

7s5
4

+

5πb5
128Vdc
7πb7
512Vdc

+

1
32

+

1
128

.

As it can be seen, the value of s in (4.6) is only dependent on the value of b1 while in (4.22)
it is dependent on the value of each harmonic including b1. Therefore, we can assign any value
to any harmonic and the rest of the algorithm, remains unchanged. Note that if the modulation of

several harmonics is needed to be implemented using the offline approach, with each modulated

harmonic, the size of the look-up table will be doubled. This makes it impossible to solve and store

within the limited memory of the microcontroller.

4.5 Experimental Results

Experimental tests have been performed to validate the efficacy of the proposed method. The

three-phase, two-level voltage source inverter shown in Fig. 4.1 is used. The DC-link voltage

is Vdc = 100 V. The motor is replaced with equivalent RL load R = 5 Ω and L = 2 mH.

87

The controller used in the experiment is dSPACE CP1103. The digital output pins were used

to generate the switching signals. Therefore, the calculations of the algorithm are done by the

dSPACE PowerPC PCC 750GX and Xilinx Spartan 6 FPGA.

The first test is conducted to investigate the effect of the sampling frequency on the accuracy

of the generated switching signals. The RTSHE algorithm was set to calculate the new polyno-

mial coefficients and substitute the value of the reference voltage angle into the new polynomial

(long routine). Since the algorithm requires approximately 6 µs, the fixed sampling time is set to

8 µs. Fig. 4.8 and Fig. 4.9 show a comparison between the waveforms resulting from the real-

time algorithm and the waveforms resulting from using the offline method. Note that the offline

method uses a curve fitting polynomial to obtain the optimal switching angle. The order of the

curve fitting polynomial is set to the same order as the polynomial in the real-time algorithm. The

offline method requires approximately 4 µs turnaround time. For comparison, the fixed sampling

frequency for the offline method is also set to 8 µs. The experimental waveform shows that the

value of the eliminated harmonics is still very close to zero. This is justifiable because at 60 Hz

frequency, it takes 0.0167 s to complete one cycle. An update for the switching angle can be made

by the controller every 8 µs. This leads to 2087 updates per fundamental cycle. Therefore, the er-
ror of the generated switching angle cannot be larger than ±0.172 degrees. Fig. 4.10 and Fig. 4.11
show similar results when the fundamental frequency is set to 120 Hz. In this case, the error of the
switching angles of the real-time method is bounded by ±0.345 degrees. Slight difference in the
spectrum can be observed at the frequencies beyond the eliminated harmonics on the right side of

the FFT window.

Fig. 4.12 and Fig. 4.13 show the steady-state performance of the proposed RTSHE method

when the fundamental frequency is 60 Hz and 120 Hz, respectively, and the first eight odd har-

monics are eliminated.

It is clear from the FFT results that the first seven odd harmonics are

successfully eliminated for both cases.

Fig. 4.14 shows the transient behavior of the RTSHE method when the switching frequency

of the system is changed from 32 Hz to 16 Hz. Fig. 4.15 shows the transient behavior when Mi

88

Figure 4.8 Experimental results of the line current ia, line-neutral voltage va and the spectrum of
va using the proposed real-time algorithm. The fundamental frequency is 60 Hz.

Figure 4.9 Experimental results of the line current ia, line-neutral voltage va and the spectrum of
va using the conventional offline method. The fundamental frequency is 60 Hz.

89

Figure 4.10 Experimental results of the line current ia, line-neutral voltage va and the spectrum of
va using the proposed real-time algorithm. The fundamental frequency is 120 Hz.

Figure 4.11 Experimental results of the line current ia, line-neutral voltage va and the spectrum of
va using the conventional offline method. The fundamental frequency is 120 Hz.

90

Table 4.1 Summary of the comparison between the conventional offline method and the proposed
RTSHE.

Trade
Error Due Numerical Conv. ≈ 10−15
Error Due Implementation

Conventional Offline Method

Error Due Sampling

Offline Complexity

Norm of residuals = 0.076104.
0.08 degree and it is proportional
to the fundamental frequency and n
Requires solving difficult mixed integer
programming problem. Especially for n is large. No offline solution required

Proposed RTSHE
≈ 10−15
No implementation error
0.172 degree and it is proportional
to the fundamental frequency and n

Online Complexity

Minimal

Transient Behaviour

Ablity to Remove the
Selected Harmonics

Standard, My suffer high current transient when
transferring from a set of angles to another due
to change in MI

Able to remove the selected harmonic.

The additional calculation almost
double the turn around time compared
to the offline method

Improved due to the high achievable
MI precision

Able to remove the selected harmonic.
THD is the same as the one from the
offline method

is increased from 0.6 to 0.8. Fig. 4.16 shows the transient behavior when the inverter reduces the

switching frequency and concurrently increases the fundamental frequency. This is very common

in high power inverters when the high power GTOs are only able to switch at a rate less than 100

Hz. The load current shows a seamless transition in all of these cases. The concurrent change

in the fundamental and switching frequencies is tested at random instants within the fundamental

period to inspect any possible current spikes. As shown in Fig. 4.17, no current spike was ever

observed. For comparison, the current transient behavior of the conventional offline method is

shown in Fig. 4.18.

Fig. 4.19(a) to (c) demonstrate the ability to achieve control over the third harmonic without

affecting the fundamental component of the phase voltage and the T HD of the load current.

To further reduce the execution effort, the coefficients of the polynomial can be pre-calculated

and hard-coded in the controller. To have the flexibility to operate at any Mi, the algorithm that
calculates the polynomial coefficient needs to be executed by the controller in real-time. Note that

this is required only when the Mi changes. The execution time of the control algorithm only takes
6 µs, which leaves ample room to increase the system fundamental frequency while maintaining

high-quality waveforms. Furthermore, the calculation of the polynomial and the actuation com-

mand extraction can be done by the external FPGA, especially when the order of the polynomial is

large. Using an external FPGA allows parallel schemes for software realization, and based on the

number of the available parallel units, the overall turnaround time can be further reduced [85].

91

Figure 4.12 Experimental results of RTSHE load current ia and the phase voltage va at a funda-
mental frequency of 60 Hz.

Figure 4.13 Experimental results of RTSHE load current ia and the phase voltage va at a funda-
mental frequency of 120 Hz.

92

Figure 4.14 The transient behavior of the load current ia and the phase voltage va when changing
the switching frequency.

93

Figure 4.15 The transient behavior of the load current ia and the phase voltage va when changing
MI.

94

Figure 4.16 The transient behavior of the load current ia and the phase voltage va when changing
both fundamental and switching frequencies at the same instant.

95

Figure 4.17 The transient behavior of the proposed RTSHE load currents ia, ib, and ic when
a concurrent change in the fundamental and switching frequencies are randomly requested. No
current spike is detected.

96

Figure 4.18 The transient behavior of the conventional offline SHE load currents ia, ib, and ic
when a concurrent change in the fundamental and switching frequencies are randomly requested.

97

(a)

(b)

(c)

Figure 4.19 The real-time controllability of the third harmonic: (a) vb3
50 = 7.855 V, (b) vb3
4 ∗ 50 = 23.565 V.
π0.6

4 ∗ Vdc/2 = π0.4
πb3

=

4

∗
4 ∗ Vdc/2 = π0.2
πb3
4 ∗ Vdc/2 =
∗ 50 = 15.71 V, and (c) vb3
πb3

=

=

4

98

Chapter 5

Switched-Capacitor Voltage Boost

Converter for Electric and Hybrid Electric

Vehicle Drives

5.1

Introduction

In May 2017, the International Monetary Fund (IMF) published a white paper regarding energy

transition and the oil market beyond 2040. In the paper, the authors concluded that a fast adaptation

scenario for electric vehicles is likely to happen. By 2042, around 93% (290 million) of all vehicles

in the U.S. will be electric [86]. At that time, the internal combustion-based automakers that fail

to transition to electric cars (EVs) will soon have a Kodak moment.

In ideal world, the fast adaptation of EVs depends on how fast the EVs will outperform the

internal combustion-based cars in mileage and price. The potential development of EV technology

falls broadly into three categories: battery chemistry, autonomous driving, and the power electronic

units. With regard to the last category, one of the most critical power conversion units is the drive

train. The improvement of the drive train results in size reduction, fast speed/torque dynamic, and

better utilization of battery power. Most of the existing EVs utilize a two-level voltage source

99

inverter (VSI) with or without boost stage due to its reliability [87] [88]. The opportunities to

improve the EV power train can be addressed by exploring the limitations of VSIs.

VSIs are inherently buck converters. Therefore, the dc-link voltage has to be higher than the

dc or ac input voltage. For applications where the available dc voltage is limited, an additional dc-

dc boost converter is needed to obtain the desirable ac voltage [89]. For the commercial traction

electric drive system, two configurations are commonly used: the first one is a battery directly pow-

ering a two-level inverter; the second one is a battery connected to the inverter with an intermediate

dc-dc boost stage as shown in Fig. 5.1(a) [90].

The first configuration of a battery directly connected to the dc-bus offers minimum stress on

the inverter side, but it requires an expensive battery with a large number of cells in series to

achieve the necessary dc-link voltage [91]. The series connection of battery cells poses a challenge

in terms of the slow charge equalization speed [92]. Furthermore, the isolation of one faulty cell

in the series connection leads to a voltage drop in the overall series connection. In this case, the

entire series row of batteries needs to be disconnected from the dc-link to avoid a short circuit with

other non-faulty series rows of cells. The first configuration is seen only in extended-range electric

vehicles (with large batteries) such as Tesla (75 to 100 kWh) [93].

The second configuration shown in Fig. 5.1(a) is used in hybrid electric vehicles (HEVs) and

plug-in HEVs (PHEVs) where the battery energy rating ranges from 5 to 50 kWh. While the current

limit in the machine is dependent on its ability to dissipate the heat, the voltage limit is dependent

on the dc-link voltage level. Therefore, using a dc-dc boost converter extends the constant torque

region [94]. Owing to the superior current density characteristics of the SiC-MOSFET compared

to the Si-IGBT, the current density of the 1200V SiC-MOSFET is similar to the current density

of the lower-voltage 600V Si-IGBT [95]. This advantage leads to a reduction in semiconductor

die area by a factor of two, and this is accomplished by utilizing high-voltage motors and SiC-

MOSFETs [96]. Furthermore, the reduced current peak at a higher voltage leads to smaller peak

losses by a factor of four [96]. Since power loss translates directly into cooling system capacity, a

significant reduction in cooling system size and weight, as well as an improvement in EV range,

100

(a)

(b)

Figure 5.1 The schematics of (a) the conventional inverter-converter topology and of (b) the pro-
posed switched-capacitor voltage boost converter.

101

MMBoost converterBatterySaSbScSaSbSc~ ~ ~ SdSd~ InverterMMSC converterBatterySaSbScSaSbSc~ ~ ~ SgSg~ SRCbCcan be achieved.

The conventional boost stage depicted in Fig. 5.1(a) is not quite perfect. The power rating of

the dc-dc converter must match the battery pack power, leading to a proportionally large inductor.

The inductor is a heavy and costly component. Furthermore, the inductor copper and core losses

increase proportionally with the size of the inductor. When boosted by a high-voltage ratio, the

boost converter must operate with a high duty cycle where the efficiency is relatively low [97].

The partial power efficiency is also reduced, because the ac losses (switching loss and ac magnetic

loss) depend on voltage but are nearly independent of current. At high duty cycles, the rms current

applied to the bus capacitor is also quite high, which impacts the size and cost of the capacitor [96].

To overcome the above limitations of the traditional drive trains, this paper presents the switched-

capacitor voltage boost (SC) converter and its control methods. Fig. 5.1(b) shows one version of the

proposed SC converter. It employs a switched-capacitor circuit with the inverter to form a unified

circuit. The switched capacitor circuit is used to create a multi-leveled dc-link voltage. Therefore,

the proposed switched-capacitor circuit differs from the conventional one by not having the reverse

blocking diode at the load side or the large filtering capacitor. The regulation of the output current

and voltage is realized by unified control of both the inverter and the switched-capacitor stages.

The rest of the paper is organized as follows: After the introduction, the space vector operating

principle of the SC converter is presented in Section II. The design and analysis of the SC converter

are presented in Section III. The carrier-based modulation of the SC converter is presented in

Section IV. Finally, simulation results, prototype, experimental results, and the conclusion are

presented in section V and VI.

5.2 Space Vector Pulse Width Modulation of SC Converter

The switched-capacitor circuit at Fig. 5.1 (b) can have two possible states: one when the capacitor

is charging shown in Fig. 5.2 (a)

Vbat = vcap = vi,

(5.1)

102

and one when the capacitor is discharging shown in Fig. 5.2 (b)

Vbat = vcap; vi = 2Vbat,

ii = Saia + Sbib + Scic.

(5.2)

(5.3)

In addition to these options, the other phase legs feature the eight known inverter states. There

are fourteen overall feasible states in the SC converter, and they are depicted in the space vector

hexagon shown in Fig. 5.3. One can observe that the states of the SC converter resemble a four-
level inverter with phase voltage possibilities {±Vbat,±2Vbat}.

To derive the dwell time for each vector, a few assumptions are made. First, in each sector, the

four adjacent active vectors and the two zero vectors are used to synthesize the reference voltage

vector. Second, during the discharge time, the capacitor voltage is assumed to be constant and

equal to the battery voltage. Therefore, the dwell time during the discharge time needs to be

minimized to allow minimum voltage drop during the capacitor discharge.

Assume that the reference voltage vector Vref can be synthesized using the following virtual

vectors:

where

and

Vref Ts = Vxtx + Vyty + V0t0

Vxtx = V11t11 + V12t12

Vyty = V21t21 + V22t22.

(5.4)

(5.5)

(5.6)

With some algebraic manipulation, the following dwell time for the four active vectors can be

obtained:

t11 = (1 − A)tx

t12 = Atx

103

(5.7)

(5.8)

(a)

(b)

Figure 5.2 (a) Charging and (b) discharging equivalent circuits of SC converter.

104

SgSg~ SRvcapisiiicapviVbatSgSg~ SRvcapisiiicapviVbatFigure 5.3 Space vector hexagon for SC converter with the annotated switching states in the order
of (Sg, Sa, Sb, Sc). The vector synthesis is a graphical representation of the algebraic summation
and not the actual sequence in which the states are applied.

where

and

where

√

tx =

3TsMi sin(

− θ)

π
3

t21 = (1 − A)ty

t22 = Aty

√
3TsMi sin(θ).

ty =

The factor A ∈ [0, 1] is the boost factor and is expressed as follows:

0,

√

A =

0 ≤ Mi ≤ 1√
< Mi ≤ 2√
1√
3

3

3

3Mi − 1,

105

(5.9)

(5.10)

(5.11)

(5.12)

(5.13)

(0,1,0,0)(0,0,1,0)(0,0,0,1)(0,1,1,0)(0,1,0,1)(0,0,1,1)(0,0,0,0)(0,1,1,1)IIIIIIIVVVI(1,1,1,0)(1,1,0,0)(1,0,1,1)(1,0,0,1)(1,1,0,1)(1,0,1,0)V11V12V21V22V42V41V31V32V51V52V61V622/3Vbat4/3Vbat(0,1,0,0)(0,1,1,0)(0,0,0,0)(0,1,1,1)(1,1,1,0)(1,1,0,0)V11V12V21V222/3Vbat4/3VbatVrefV11t11/TsV22t22/Ts1/4V01t0/TsV21t21/TsSector IV12t12/Ts1/4V01t0/Ts1/2V0t71/Tswhere the modulation Mi is defined as

|Vref|
Vbat

.

Mi =

(5.14)

From this result, it easy to see that when the modulation index Mi ≤ 1√

, t11 = tx, t21 = ty
and t12 = t22 = 0. The capacitor is maintained in parallel with the dc source, and no discharge
occurs at any time. The SC converter operation in this case is identical to the operation of a

3

conventional two-level inverter. The authors refer to this operation mode as abstemious mode.

On the other hand, when 1√
3

, then 0 < A ≤ 1, and the capacitor is charged and
discharged with a rate proportional to the value of A. The authors refer to this operation mode as

< Mi ≤ 2√

3

gluttonous mode.

When Mi = 2√

, t11 = t21 = 0, t12 = tx, t22 = ty. In this case, the capacitors are
only charged during the zero vector implementation. Therefore, the six-step operation cannot be

3

performed in the gluttonous mode, and the minimum zero vector time must be ensured to maintain

the capacitor charge level.

The same rules in (5.9) and (5.12) can be applied for calculating the dwell times of the vectors

in sectors II to VI if modified θk for the kth sector is used instead of θ used in the calculations.

θk = θ − (k − 1)

π
3

.

(5.15)

The space vector sequence should assure that the load line voltage has the quarter-wave sym-

metry to reduce the even harmonics in their spectra. To reduce the switching frequency, it is also

necessary to execute the switching sequence in such a way that the transition from one to the next

is performed by switching only one inverter leg at a time. For instance, if the reference vector

falls in sector I, the switching sequence is shown in Fig. 5.4. The capacitor discharge intervals are

placed in the middle of the active vectors intervals to maintain the switching of only one inverter

leg at a time. The zero vector time is distributed at the beginning, the middle, and the end of the

sampling period Ts. This placement has the particular advantage of limiting the capacitor charging

106

current as we show in the following sections.

5.3 Analysis of the Capacitor Voltage Ripple and the Charging

Current Using SVPWM

The capacitor connection with the source and inverter falls into one of the following two config-

urations: the pre-discharge state and the discharge state. In the pre-discharge state as shown in

Fig. 5.2(a), the capacitor is charged with voltage equal to

Vcap = Vbat − (VD + Vp) = Vdc

(5.16)

where VD is the forward voltage drop across the diode. Vp refers to the summation of the par-
asitic voltages drop along the charging path, including the voltage drop across the series resistance

of the capacitor and the on-resistance of the switch. For simplicity’s sake, we will refer to the fully
charged capacitor as Vdc, where Vdc ≈ Vbat.

In the discharge state, the capacitor is discharged to the load as shown in Fig. 5.2(b). During

this time, the capacitor is connected in series with the source and the load. Therefore,

icap = is = ii = Saia + Sbib + Scic.

(5.17)

The voltage drop in the capacitor voltage is a function of the capacitor size and the discharge

time,

∆vcap =

icaptdch

C

,

(5.18)

where tdch is the discharge time. During the discharge time the capacitor becomes in series

with the source, icap = ii, and

∆vcap = vcap(k) − vcap(k+1) =

iitdch

C

,

(5.19)

107

Figure 5.4 Illustration of the switching sequence of SVPWM in sector I.

To estimate the charging current of the capacitor, we must consider the sequence in which the

capacitor is charged and discharged with respect to the inverter states.

Consider the switching sequence in Fig. 5.4. The capacitor is discharged in two separate in-
tervals per sampling time Ts. The first interval produces V12 and V22 and the second interval
produces V22 and V12. First, we assume that equation (5.16) holds, and therefore, before every
discharge state, vcap(1) = Vdc. Using (5.19), the capacitor voltage at point 2 vcap(2) can be
predicted as follows:

vcap2 = Vdc − iat12

2C

.

Similarly, the capacitor voltage at point 3 vcap3 can be expressed as

vcap3 = Vdc − iaAtx

2C

+

icAty

2C

.

108

(5.20)

(5.21)

Note that

ia = Iacos(θ − φ)
ib = Ibcos(θ − φ +
2π
3
ic = Iccos(θ − φ − 2π
3

)

)

(5.22)

where ia, ib and ic are phase shifted from the reference voltage by φ, which is the power factor
angle. Ia = Ib = Ic = I are the phase currents amplitudes. Note that tx and ty are functions of
the modulation index Mi and the angle θ as expressed in (5.9) and (5.12), respectively.

For any assigned value of the modulation index, the capacitor voltage drop in the first discharge

interval shown in Fig. 5.4 is

∆V = Vdc − vcap3 =

A
2C

(cid:18)

txia − tyic

(cid:19)

(5.23)

and the maximum value of ∆V (∆Vmax) can be obtained be taking the gradient of (5.23) with

respect to θ,

√

3MiTsI

C

∂∆V
∂θ

=

(cid:18)

(cid:19)

cos(2θ − φ − π
3

) + cos(2θ − φ − 2π
3

)

.

(5.24)

Note that there exists an angle ˆθ ∈ {0, π
zero

3} that causes maximum ∆V and makes the gradient equal

∂∆V
∂θ

= 0 = cos(2ˆθ − φ − π
3

) + cos(2ˆθ − φ − 2π
3

).

By using the following identity

cos(x − y) + cos(x + y) = 2 cos(x) cos(y),

(5.25)

(5.26)

equation (5.25) can be expressed as

cos(2ˆθ − φ − π
2

+

π
6

) + cos(2ˆθ − φ − π
2

− π
6

) = 2 cos(2ˆθ − φ − π
2

) cos(π/6).

(5.27)

109

Obviously, cos(π/6) (cid:54)= 0; therefore, cos(2θ − φ − π

2 ) = 0. This leads to the following conditions:

2ˆθ − φ − π
π
=
2
2
= −π
2

2ˆθ − φ − π
2

,

and θ that causes maximum ∆V is one of the two solutions

π+φ

φ
2 ,

2 ,

ˆθ =

0 > φ ≥ −π
2
0 ≤ φ ≤ π
2 .

(5.28)

(5.29)

The formulation of the angle ˆθ gives the insight that for any power factor P F from 0 to 1, the

angle that causes maximum ∆V always lies between 0o and 45o of sector I.

The maximum voltage drop using the pattern in Fig. 5.4 can be expressed as

(cid:18)
txia − tyic

(cid:19)

∆V |

θ=
A
2C

=

φ
2
√

= ∆Vmax =

(cid:20)

3TsMiI

sin(

A
2C
− φ
2

π
3

) cos(

) − sin(

φ
2

φ
2

) cos(

φ
2

− φ − 2π
3

(cid:21)

)

.

(5.30)

So far it has been shown that the maximum voltage drop location within the sector is solely

dependent on the power factor P F of the load. However, the power factor P F does not affect the

value of the maximum voltage drop ∆Vmax as shown in Fig. 5.5. As a consequence, the final

expression of ∆Vmax can be described in the following compact form:

∆Vmax =

3AMiI
4Cfsw

.

(5.31)

To complete the analysis, we must make sure that the capacitor reaches ≈ Vdc voltage during
the charging time. This can be understood by obtaining the minimum charging time location within

the sector and its value dependency. Consider tch indicated in Fig. 5.4. The charging time tch is a
function of Mi and A:

110

Figure 5.5 The relationship between the location of ∆Vmax and the power factor angle φ. φ does
not change the value of ∆Vmax; it only changes the location within the sector in which ∆Vmax
occurs.

Figure 5.6 The charging time tch with respect to the minimum charging time tch−min wtih
diffrent values of Mi, A = 0.3.

111

0/8/4  (rad)00.20.40.60.811.2 V/VmaxVmaxV at =0V at =/4V at =/20/12/63/12/3  (rad)012345678910 tch/tch-minMI=0.1155MI=0.2887MI=0.4907MI=0.5774Figure 5.7 The charging time tch with respect to the minimum charging time tch−min wtih
diffrent values of Mi, A = 0.5.

Figure 5.8 The charging time tch with respect to the minimum charging time tch−min wtih
diffrent values of Mi, A = 0.8.

112

0/12/63/12/3  (rad)012345678910 tch/tch-minMI=0.1155MI=0.2887MI=0.4907MI=0.57740/12/63/12/3  (rad)012345678910 tch/tch-minMI=0.1155MI=0.2887MI=0.4907MI=0.5774Figure 5.9 The charging time tch with respect to the minimum charging time tch−min wtih
diffrent values of Mi, A = 0.9.

tch =

=

t0
2
Ts
2

+ (1 − A)ty
−

3TsMi

√

(cid:20)1

2

sin(

π
3

− θ) − (

1
2

− A) sin(θ)

(cid:21)

.

(5.32)

Taking the gradient for (5.32) and equating it to zero results in the angle ˆˆθ at which the mini-

mum charging time is experienced tch−min

∂tch
∂θ

= 0 = cos(

π
3

− ˆˆθ) − (A − 1
2

) cos(

ˆˆθ).

The optimal angle is determined to be

ˆˆθ = tan−1

(cid:18)4A − 3√

3

(cid:19)

.

(5.33)

(5.34)

Note that the angle ˆˆθ lies in sector I only when 3

4, the resulting
angle is negative, and it does not reside in sector I. However, a small segment of a sinusoidal

4 ≤ A ≤ 1. When 0 ≤ A < 3

113

0/12/63/12/3  (rad)012345678910 tch/tch-minMI=0.1155MI=0.2887MI=0.4907MI=0.5774function has a linear behavior. It is observed that ˆˆθ = 0 when 0 ≤ A < 3
description for ˆˆθ is

4. Therefore, the general

0,

tan−1

(cid:18)

(cid:19)

,

4A−3√

3

0 ≤ A < 3
4

3

4 ≤ A ≤ 1.

As a result, the minimum charging time tch−min is expressed as follows:



ˆˆθ =



(5.35)

(5.36)

tch−min =

1

2 Mi),

2Ts(1 − 3
2 − √
(cid:20)
(cid:16) π
Ts
3TsMi
3 − tan−1(4A−3√
(cid:16)
1
2 sin
tan−1(4A−3√
2 − A) sin
(1

3

3

(cid:17)−
(cid:17)(cid:21)

)

,

)

0 ≤ A < 3
4

3

4 ≤ A ≤ 1.

Because of the symmetry of the sector, the other charging intervals have a similar expression
for tch−min. In order for the capacitor to retain the full voltage after each charging period, the
following condition must be met:

tch−min ≥ RC ln(

Vdc − Vcap
3
4C ATsMiI

).

(5.37)

Under these conditions, the maximum charging current amplitude passing through the diode of

SR and the IGBT of ˜Sg can be estimated as:

Icharging−max =

3AMiI
4RCfsw

(5.38)

where R is the resistance along the charging path including the on-resistance of the switches and

the ESR of the switched-capacitor. The power losses resulting from the additional resistance must

be very small and can be estimated as follow:

114

Figure 5.10 Simulation results of one fundamental cycle showing the behavior of the charging
current icap with respect to the instantaneous voltage drop across the capacitor vcap.

115

SaSbScSg-20020icap(A)199.14199.16199.18vcap(V)02 (rad)-5000500vab(V)Figure 5.11 (Zoom in of Fig. 5.10); Simulation results of the charging current showing that when
the ∆V ≈ 0.02 V the charging current icap = ∆V
R ≈ 18 A; given that the series resistance in the
simulation model is set to R = 0.0011 Ω.

116

SaSbScSg-20020icap(A)199.16199.17199.18vcap(V)1.351.41.45Time (S)10-30200400vab(V) VVbat(cid:18)3AMiI

4Cfsw

(cid:19)2

.

1
R

PR−losses =

(5.39)

The presented guidelines allow better understanding of the charging current and how the se-

lection of the switching frequency, the capacitor size, Mi, and A will determine the current rating
of the switched-capacitor half-bridge. Fig. 5.6 to Fig. 5.9 show the normalized charging time in
different values of Mi and A. Note that the expressions of ∆Vmax and tch−min for the second
tch interval is the mirror image of the one shown in Fig. 5.6 to Fig. 5.9.

Fig. 5.10 shows the simulation results of one fundamental cycle. The capacitor voltage vcap
experiences the maximum voltage drop ∆Vmax when the angle within the sector is near 10o when
the power factor of the load is 0.93. This observation is well supporting the analytic analysis of the

of the maximum voltage drop location within the sector shown in Fig. 5.5.

Fig. 5.11 shows a zoom-in of Fig. 5.10 to one sampling period. As it can be seen, the charging

current is a function of the voltage drop across the capacitor in the previous discharging event and

the series resistance of the charging path. The total on-resistance of the diode and the lower switch

is set to 0.0011 Ω. Increasing the series resistance will limit the charging current, but it will also

lead to an increase in conduction losses. Therefore, the viable solution to limit the charging current

is to limit the voltage drop occurring in the discharge period. This can be done by either increasing

the switching frequency or increasing the capacitor size or both as indicated by (5.31).

5.4 Carrier-based Modulation of SC Converter

The generation of the switching function for the SC converter can be further simplified by adopting

the carrier-based method. The carrier-based method gives the exact switching sequence obtained

by the SVPWM. In fact, the carrier waveforms are directly derived from the dwell times developed

in Section II. To generate the switching signals, five modulation waveforms are derived from the
dwell times. The first three v∗
c are used to modulate the three phase legs of the
inverter a, b, and c, respectively, and it is dependent on Mi. The last two are used to modulate

b , and v∗

a, v∗

117

Table 5.1 The generation of the reference waveforms from the dwell times in each sector.

a

v∗
tx + ty +
t0
2

tx +
t0
2
t0
2
ty +

t0
2
tx + ty +

t0
2

t0
2

v∗
b
ty +

t0
2
tx + ty +
tx + ty +
t0
2

tx +
t0
2
t0
2

t0
2
t0
2

v∗
c
t0
2
t0
2
ty +

t0
2
tx + ty +
tx + ty +
t0
2

tx +

t0
2
t0
2

Sector

I
II
III
IV
V
VI

v∗
l
t11 +
t21 +
t11 +
t21 +
t11 +
t21 +

t0
2
t0
2
t0
2
t0
2
t0
2
t0
2

v∗

h

tx + t22 +
ty + t12 +
tx + t22 +
ty + t12 +
tx + t22 +
ty + t12 +

t0
2
t0
2
t0
2
t0
2
t0
2
t0
2

the switching capacitor leg, and it is dependent on both Mi and A. The equations to obtain those
reference waveforms are listed in Table 5.1.

Fig. 5.12 to Fig. 5.15 show how the reference signals behave as A changes from 0 to 0.75, where

Mi in the figures is maximum (0.5774). If Mi is reduced, then the envelope of v∗
c will
be reduced with the same shape being maintained. After calculating the five reference waveforms,

b , and v∗

a, v∗

the simplified control diagram shown in Fig. 5.16 can be used to generate the switching signals.

The reference waveform can be either calculated or stored in a sine look-up table for minimum

computational effort.

In our case, the logic block diagram shown in Fig. 5.16 is implemented

using an FPGA.

5.5 Simulation Results, Experimental Test, and Hardware De-

sign

To verify the proposed design equation and control, a simulation model of the SC converter is built

using Saber RD simulation software. Fig. 5.1(b) shows the circuit configuration and Fig. 5.17 and

5.18 show the simulation waveform in various operating regions. The battery voltage is set to 200

V. RL load is used with Rload = 10 Ω and L = 10 mH. The switching frequency of the inverter
legs is set to 10 kHz, and the switching frequency of the SC leg is set to 20kHz. The switched-

capacitor is 9000 uF. The total series resistance along the charging path shown in Fig 5.2(a) is

118

Figure 5.12 The reference waveforms synthesized from the SVPWM algorithm, Mi = 0.5774,
A = 0.

Figure 5.13 The reference waveforms synthesized from the SVPWM algorithm, Mi = 0.5774,
A = 0.25.

119

02 (rad)00.20.40.60.81t{.}/Tsva*vb*vc*vl*vh*02 (rad)00.20.40.60.81t{.}/TsFigure 5.14 The reference waveforms synthesized from the SVPWM algorithm,Mi = 0.5774,
A = 0.5.

Figure 5.15 The reference waveforms synthesized from the SVPWM algorithm, Mi = 0.5774,
A = 0.75.

120

02 (rad)00.20.40.60.81t{.}/Ts02 (rad)00.20.40.60.81t{.}/TsFigure 5.16 The carrier-based modulation of the SC converter.

0.25 Ω, which serves to limit the charging current of the capacitor.

Fig. 5.17 shows the result when Mi = 0.5 and A = 0. The converter is operating in the
abstemious mode, and the operation is identical to the one of two-level VSI. The diode in SR
and the IGBT in ˜Sg experience continuous conduction. However, the current flowing through the
IGBT in ˜Sg is negligible in the steady-state operation, and it does not contribute to increasing the
conduction losses. Fig. 5.18 shows the simulation results when A = 0.5 Mi = 0.5. The converter
is operating in the gluttonous mode. The capacitor voltage is fluctuating between 200 V and 400

V during the charging and discharging intervals, respectively.

In the abstemious mode, the inverter switches have voltage stress equal Vdc instead of 2Vdc,
a feature that is unavailable to inverters with non-adjustable dc-link voltage. For instance, if the

conventional VSI is fed by 400 V dc-link voltage, then the voltage stress across the switches is

always 400 V regardless of the value of the M I. Whereas an equivalent system of SC converter

will have a dc-link voltage equal to 200 V and the voltage stress across the switches during all

of the abstemious mode is only 200. The voltage stress becomes 400 V only when the inverter

is operating in the gluttonous region. This cut the voltage stress of the switches to half in half

of the operating region of the SC converter. Furthermore, the PWM operation under very low

modulation index presents maximum total harmonic distortion (T HD). Therefore, by operating

121

Figure 5.17 The carrier-based modulation of the SC converter. Abstemious mode, Mi = 0.5 and
A = 0.

122

Figure 5.18 The carrier-based modulation of the SC converter. Gluttonous mode, Mi = 0.5 and
A = 0.5.

123

in the abstemious mode, the converter Mi remains at the higher area of the linear region and the
reduction in T HD can reach 60% lower than the T HD of an equivalent fixed dc-link inverter

system. The experimental results show that the T HD of the SC converter is within less than 3%

across the entire operating region. Fig. 5.19 Fig. 5.20 show the dc-link design of the SC converter.

Note that laminated copper strips can be used instead of the narrow strips to further minimize the

loop inductance.

Fig. 5.21 shows the experimental prototype. Fig. 5.23 shows the experimental results when

the battery voltage is 100V, the maximum dc-link voltage seen by the inverter bridge is 200 V, the

operating switching frequency is set to 10 kHz, the switched-capacitor used is 9000 uF. In Fig. 5.22,

Mi = 0.5774, and A = 0. The converter in this case is operating in the abstemious mode. The
switched capacitor becomes in parallel with the dc-link capacitor and the current flowing though

the the IGBT in ˜Sg is near zero.

Fig. 5.24 Fig. 5.25 show the experimental results when the battery voltage is raised to 200 V,

the dc-link voltage seen by the inverter bridge is 400V, the operating switching frequency is set to

20 kHz, Mi = 0.5, and A = 0.5.

Fig. 5.26 shows the experimental results focusing on the switching transient of the charging

current and the output line voltage. The top image shows the switching function sent by the FPGA.

It is essential to know that the charging current is dangerous only at the charging period, right when

Sg turns off. The negative peaks of the charging current occur when the capacitor is in a series

configuration with the input battery source. In this case, the capacitor current is equal to the inverter

input current.

Fig. 5.27 shows the load current waveform when the switching frequency of the converter

is only 1 kHz. Thanks to the large size of the switched-capacitor, the charging current is still

within the design limit of the converter. The significance of being able to operate at low switching

frequency is to achieve high efficiency or the possibility of implementing low-frequency optimal

PWM.

124

Figure 5.19 Isometric view of the SC converter layout.

125

Figure 5.20 Exploded view of the SC converter layout.

126

Figure 5.21 Exploded view of the SC converter layout.

Figure 5.22 Experimental results of (a) abstemious mode, Mi = 0.5 and A = 0.

127

Figure 5.23 Experimental results of gluttonous mode, Mi = 0.5774 and A = 0.5.

Figure 5.24 Experimental results of abstemious mode, Mi = 0.5 and A = 0.

128

Figure 5.25 Experimental results of gluttonous mode, Mi = 0.5774 and A = 0.5.

129

Figure 5.26 Experimental results showing the charging current with respect to the switching func-
tions of the SC converter. (Ch2: 1 A/V).

130

Figure 5.27 Experimental results showing the switching transient of the SC converter at 1 kHz
switching frequency. (Ch2: 1 A/V).

131

Chapter 6

Conclusions and Future Work

In first chapter, a set of new HSVPWMS control methods are proposed to minimize the amplitude

and frequency of the CMV. A detailed comparison shows the relative performance of the conven-

tional PWM methods and the proposed HSVPWMS methods in terms of CMV characteristics,

HDF, switching losses, and DC ripples. The conventional PWM methods have a CMV harmonic

component with high frequency equal to the carrier frequency fc. The new HSVPWMS method
proposed in the chapter limits the CMV amplitude to Vdc
3 and concentrates the CMV harmonics
to a low frequency equal to three times the fundamental frequency 3f1. A new commutation al-
gorithm that avoids nonlinear behavior during dead-time intervals is proposed. The performance

of the proposed HSVPWMS algorithms has been verified via simulations and validated by labora-

tory experiments. The new HSVPWMS method can potentially enable converters to operate at a

very high switching frequency using the newly emerging wide bandgap devices while effectively

mitigating the adverse CMV effects associated with conventional high-frequency PWM schemes.

In second chapter, an MPC-based control method is proposed to fully control the amplitude and

the frequency of the CMV. Two approaches were implemented to govern the commutation between

odd and even voltage vectors to shape the characteristic of the CMV. The first one is sequenced

commutation (SC) and the second one is pulse width modulation commutation (PWMC) method.

Both of which can cover all the linear region with full modulation index. The previously proposed

132

methods are summarized and compared with the proposed method. The ability to fully control the

CMV frequency allows us to minimize the resulting shaft current without reducing the switching

frequency of the system. A high frequency machine model to investigate the bearing current is

presented.

The proposed method gives an extra degree of freedom over the CMV and shows that all of

the previously proposed methods are special cases of the proposed method. This additional control

freedom can potentially enable MPC controlled converters to operate at a very high sampling

frequency without having the CMV effects associated with conventional MPC methods. The MPC-

PWMC is more capable than MPC-SC method in concentrating the frequency of the CMV at the

carrier frequency. The simulations and experimental results show that MPC-SC and MPC-PWMC

methods produce similar current tracking performance. The THD of the load current can be further

reduced when the commutation frequency is increased.

In this third chapter, a new real-time SHE implementation method is presented. By the trans-

formation of variables, the transcendental equations of the optimization problem are converted to

a set of algebraic equations using Chebyshev polynomials. Then the set of algebraic equations

is reduced to a single univalent polynomial using generalized Newton’s identities. The roots of

this polynomial hold the values of the switching angles. The switching angles are calculated in

real-time by simple substitution of the reference phase. The original contributions of the proposed

RTSHE/M are the following:

1- Presenting the generalized Chudnovsky algorithm. The new algorithm allows modulating

the selected harmonics rather than only eliminating them. In the near future, this feature will

be utilized for the wireless energy transfer of the multi-receiver case.

2- Presenting a new method of obtaining the values of the optimal switching angles from the

polynomial in real-time without resorting to any iterations or guesses. This enabled the

implementation in the microcontroller with a determinate execution time.

The proposed method requires minimal computational effort by the controller because it is not

133

an iterative process and does not involve any guessing of initial conditions. Hardware experiments

show the superior dynamic performance of the proposed method during a change in the modula-

tion index, switching frequency, and both switching and fundamental frequencies. The proposed

method has the efficacy to be a viable replacement for the offline approach and the existing online

approaches.

The last chapter has presented a new switched-capacitor power converter (SC) for implement-

ing dc-ac and ac-dc power conversion. The SC converter employs a switched-capacitor circuit

augmented with the main converter circuit to the power source, thus providing unique features that

cannot be attained by the traditional VSI or boost VSI. One of these unique features is doubling

the area of the linear modulation region.

The SC converter eliminates the need for the cumbersome and costly inductor to boost the

voltage. Instead, it relies on only the capacitors to achieve voltage boost, which allows higher

power density.

The formulation of the maximum voltage drop across the capacitor and the minimum charg-

ing current are analytically derived. The analytical results provide a clear insight into the design

elements that affect the behavior of the charging current, thus allowing the operation at higher

power.

The carrier-based modulation method for the new SC converter is derived from the SVPWM

and employs the exact switching sequence of the SVPWM method with minimal computational

effort.

The analytic derivations, simulation, and experimental results have validated the operating prin-

ciple and modulation methods of the proposed converter. The SC converter can boost or buck

voltage, minimize component count, increase power density, and reduce cost.

134

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