ADDITIVE MANUFACTURING FOR RAPID PROTOTYPING OF MM-WAVE CIRCUITS

By

Cameron Austin Crump

A THESIS

Submitted to

Michigan State University

in partial fulfillment of the requirements

for the degree of

Electrical Engineering – Master of Science

2021

ABSTRACT

ADDITIVE MANUFACTURING FOR RAPID PROTOTYPING OF MM-WAVE CIRCUITS

By

Cameron Austin Crump

Additive manufacturing (AM) has recently attracted significant interest to meet the need of next

generation of wireless systems, and the growing demand for customization and rapid prototyping

of electronic systems. In addition, AM is being investigated to supplement and in some cases re-

place traditional microelectronic fabrication techniques. This is to lessen the ecological impact of

electronics manufacturing as well as to reduce cleanroom facility costs. This research work focuses

on the use of AM for the design and fabrication of microwave and millimeter wave components

and systems, leading to heterogeneous integration. For systems integration, two major challenges

to tackle are: (1) rapid printing of conductive regions with high precision and high conductiv-

ity; (2) selective deposition of dielectrics with varying geometries surrounding active and passive

components. In this work, printing of both conductors and dielectrics was carried out using aerosol
jet printing (AJP). AJP allows for high resolution printing (∼10 µm) at a large standoff distance
(∼10 mm). Silver (Ag) based inks were investigated to achieve high conductivity and polymers
(benzocyclobutene, BCB and Polyimide, PI) as low-loss dielectric materials.

Copyright by
CAMERON AUSTIN CRUMP
2021

ACKNOWLEDGEMENTS

This work is funded in part by the Department of Energy’s Kansas City National Security Campus,

operated by Honeywell Federal Manufacturing & Technologies, LLC under contract number DE-

NA0002839.

iv

TABLE OF CONTENTS

LIST OF TABLES .

LIST OF FIGURES .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

CHAPTER 1

1.1

1.2 Conductive Materials .
. .

.
.

.
.

. .

.
.
. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTRODUCTION .
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction .
.
1.1.1 Motivation .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 Review of Additive Manufacturing . . . . . . . . . . . . . . . . . . . . . .
1.1.3 Review of Aerosol Jet Printing . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Overview .
1.2.2 Traditional Fabrication Methods . . . . . . . . . . . . . . . . . . . . . . .
1.2.3 Additive Manufacturing Conductors . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . .
Embedded Actives . . . . . . . . . . . . . . . . . . . . . . . . .

1
1
1
2
2
4
4
4
5
7
7
7
8
1.3.2.1 Different chip thickness
8
1.3.2.2 Minimal Interconnect Losses
1.3.2.3
9
1.3.2.4 Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . 10
1.3.3 High Density Integration Techniques . . . . . . . . . . . . . . . . . . . . . 11
1.3.4 Coating Substrates
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.5 AM Techniques .

.
1.3.1 Overview .
. .
1.3.2 Applications . .

.
.
.

.

1.3 Dielectric Materials .

.
.

.
.
.

.
.
.

.
.
.

. .
. .

.
2.1
Introduction .
2.2 Applications .
.
2.3 Experimental Setup .

CHAPTER 2 STREAMLINING CONDUCTORS USING AJP . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 Aerosol Jet Printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2
Flash Sintering System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.3 Thermal Sintering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.4 DC Measurements
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4 Measured Results: Physical Properties and Conductivity . . . . . . . . . . . . . . 23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Exposure and Film Thickness . . . . . . . . . . . . . . . . . . . 25
Surface Roughness and Conductivity . . . . . . . . . . . . . . . 30
2.4.2 Thermal Sintering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
. 32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
.

2.5 Measured Results: RF Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Discussion .
2.7 Conclusion .

Flash Sintering .
2.4.1.1
2.4.1.2

. .
.

2.4.1

. .

. .

.
.

.
.

.
.

v

.
.

.
.

.
.

.
.

.

.
.

.

.

.

3.3.1

. .
. .

3.3 Dam Process .

3.1
Introduction .
3.2 Overview . .

.
Filling Process
3.4 Conductor Deposition .

CHAPTER 3 THICK DIELECTRICS USING AJP . . . . . . . . . . . . . . . . . . . . . 40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.1 High Density Heterogeneous Integration . . . . . . . . . . . . . . . . . . . 42
3.2.2 Dielectric filling (Chip Scale Packaging) . . . . . . . . . . . . . . . . . . . 43
3.2.3 Thick Structures with varying heights
. . . . . . . . . . . . . . . . . . . . 45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Substrate processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.5 Dielectric Property Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.6 RF Circuits
3.6.1 Embedded Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Patch Antenna .
3.6.2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.3
Substrate-less Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.7 Results .
. .
3.8 Future Work . .
3.9 Conclusion .

. .
. .
.

3.4.1

. .

. .

. .

.
.
.

.

.

.
.
.

.
.
.

.

.

.

.
.
.

.

.

4.1 Conclusions .

CHAPTER 4 CONCLUSIONS .
.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.1.1 Limitations Overcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.1.2

Future Work .

. .

.

.

.

.

.

.

APPENDIX .

.

.

.

BIBLIOGRAPHY .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 74

vi

LIST OF TABLES

Table 2.1: Correlation of DC conductivity versus number of flash exposures on AJP de-

posited AgNP specimen.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 2.2: Optimal exposure distance and number of flashes for conductivity.

. . . . . . . 28

Table 2.3: Comparison of DC conductivity against reported results.

. . . . . . . . . . . . . 31

Table 2.4: RF Structures using AgNPs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

vii

LIST OF FIGURES

Figure 1.1:

Cutaway view of Optomec 5x print head. . . . . . . . . . . . . . . . . . . . .

3

Figure 1.2:

Figure 1.3:

Figure 1.4:

Figure 1.5:

Left: mechanical polishing of unwanted metal layers must be performed,
alongside pattern and etch lithography to reach desired metal patterns. Right:
AM methods allow for the final metal pattern to be achieved in the first
steps, without removal of unwanted material. . . . . . . . . . . . . . . . . .

.

Proposed Reel to Reel fabrication using AJP and flash sintering for con-
ductive traces.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

.

.

.

.

Various embedded and integrated MMIC circuits formed as integral active
MMW systems.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

.

.

5

6

9

Diagram of GE High Density Interconnect fabrication technique used in
the 1990s [1].

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

. .

Figure 1.6:

Diagram of Chip First/Chip Last fabrication technique used to encapsulate
devices on substrate surfaces.

. . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 1.7:

Diagram of Embedded Devices fabrication technique used to encapsulate
devices embedded in cavities etched into substrate surfaces.

. . . . . . . . . . 13

Figure 1.8:

Diagram of Substrate-Less fabrication technique used in this research to
print packages with fully AM processes.

. . . . . . . . . . . . . . . . . . . . 13

Figure 1.9:

Diagram of Substrate-Less on PCB fabrication technique as compliment to
Chip Last fabrication approach. . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 1.10: Left: dielectric material is spin-coated and processed one layer at a time,
involving patterning and etching. Right: AM processes allows for final
dimensions to be fabricated in as few steps as needed.

. . . . . . . . . . . .

. 15

Figure 2.1:

Illustration of the flash sintering system.

. . . . . . . . . . . . . . . . . . .

. 21

Figure 2.2:

Illustration of the flash sintering symptoms. (a) As deposited Ag ink. (b)
Fully sintered film. (c) Sintered particles with air-pockets. (d) Sintered
outer-layer of particles with wet defects below. (e) delamination of Ag film
from substrate. (f) Thin Ag film on rough surface.

. . . . . . . . . . . . . .

. 23

viii

Figure 2.3:

Figure 2.4:

Figure 2.5:

(a) Wet AJP Ag ink. (b) Flash UV sintered AJP Ag ink. (c) Delamination
of Ag ink under flash UV sintered layers. (d) Bubbles formed under Ag ink
during flash UV sintering.

. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Demonstrated process to achieve highly conductive samples of AgNP ink.
Printing and sintering is repeated with thin layers until desired thickness
and conductivity is achieved.

. . . . . . . . . . . . . . . . . . . . . . . . . . 26

SEM images of as-printed (left) and UV Flash Sintered (right) AJP Silver
NPs on Si.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

.

.

.

.

.

.

Figure 2.6:

Cross-section SEM image of UV Flash Sintered AgNP ink (light grey) on
LCP (dark grey). .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 2.7:

SEM images of AgNPs sintered into tight clusters with average 30 nm di-
ameters (left: X 170,000, right: X 330,000).

. . . . . . . . . . . . . . . . . . 30

Figure 2.8:

FIB cross-section SEM image of Thermal (Oven) Sintered AgNP ink (light
grey) on LCP (dark grey).

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 2.9:

34 mm long microstrip transmission line printed on LCP. S-parameters
shown for both the UV and oven sintered samples.

. . . . . . . . . . . . .

. 35

Figure 2.10: Connectorized Ag transmission line on LCP.

. . . . . . . . . . . . . . . . .

. 35

Figure 2.11: S-Parameters of patch antenna sintering comparison. . . . . . . . . . . . . . . 36

Figure 2.12: Polar pattern of UV sample patch with gain 6.69dBi. . . . . . . . . . . . . . . 37

Figure 2.13: UV sintered AJP printed antenna on an LCP substrate. . . . . . . . . . . . .

. 38

Figure 3.1:

Selective dielectric deposition using a dam and filling process.

. . . . . . . . 44

Figure 3.2:

Simulation of 94 GHz patch antenna on BCB with thickness from 25 to
100 µm. Superimposed gain at resonance.

. . . . . . . . . . . . . . . . . . . 44

Figure 3.3:

(a) Top-down view of dam; (b) Cross-section view of brim and wall; (c) 2D
scanned profile of the dam wall. . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 3.4:

Fabricated cells for varied height dielectric dams, no fill material placement
in this step. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

. .

. .

Figure 3.5:

Dielectric array with varying BCB thickness, 5 µm to 45 µm (1 - 9 layers)

. . 47

Figure 3.6:

3 mm x 3 mm Dielectric dam fill with 45 µm BCB thickness.

. . . . . . . . . 48

ix

Figure 3.7:

3D profile of an example structure.

. . . . . . . . . . . . . . . . . . . . . . . 48

Figure 3.8:

(a) S-Parameters of embedded 0 dB GaAs single chip in BCB with inter-
connection to LCP. (b) Photo image of the measured circuit. . . . . . . . . . . 51

Figure 3.9:

(a) S-Parameters of embedded 0 dB GaAs 215 µm chip-to-chip separation
in BCB with interconnection to LCP. (b) Photo image of the measured circuit.

51

Figure 3.10:

(a) S-Parameters of 2 mm BCB fill with transmission line interconnection
to LCP. (b) Photo image of measurement setup for GSG probe station.

. . . . 52

Figure 3.11: Measured S-Parameters of embedded chip in a cavity.

. . . . . . . . . . . . . 52

Figure 3.12: Microscope photo images of manual placement chips before removal of
protective PMMA film and printing of AgNP interconnects. Left show pur-
posefully offset angles, while right show careful alignment and appropriate
distancing of chips.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

.

Figure 3.13: Losses: Chip Spacing over DC - 67 GHz. Distance between the chips were

varied from 85 to 250 µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 3.14: Patch antenna 3D model exported from HFSS simulation.

. . . . . . . . . . . 54

Figure 3.15: Left: 2D Profile of the dam with multiple fillings; Right: Printed Ag patch

antenna on filled BCB.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 3.16: Left: 2D Profile of the dam with multiple fillings; Right: Printed Ag patch

antenna on filled BCB.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 3.17: Process Camera capture of 30-degree angle printing on Patch Antenna

ground connection using Ag ink.

. . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 3.18: Measured and simulated S11 of the patch antenna, including a re-simulation

with series resistance added for probe to silver contact.

. . . . . . . . . . . . 56

Figure 3.19: Measuring the patch antenna on the PNA . . . . . . . . . . . . . . . . . . .

. 57

Figure 3.20: Fabrication steps used to make a substrateless package for bare die chip devices. 58

Figure 3.21: Fabricated substrateless package. Left: face side of the dice. Right: ground

plane printed on back with AgNP ink.

. . . . . . . . . . . . . . . . . . . . . 58

Figure 3.22:

(a) S-Parameters of substrate-less BCB package containing two devices.
(b) Photo image of the measurement.

. . . . . . . . . . . . . . . . . . . . . . 60

x

Figure 3.23: Losses: Substrate-less package over DC - 67 GHz. Distance between the

chips were 23 µm [77 µm pad-to-pad spacing]. . . . . . . . . . . . . . . . . . 60

Figure A.1.1: Dielectric Verification using 14 GHz unloaded and loaded ring resonator

on etched LCP. .

.

.

.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure A.1.2: Set of 10, 15, 25 GHz ring resonators on 4 MIL thickness LCP. Measured
with no surface dielectric loading and then after dielectric loading to deter-
mine dielectric permittivity of printed BCB films.

. . . . . . . . . . . . . .

. 67

Figure A.1.3: First Prototype of Liftoff Process . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure A.2.4: Photograph of LED Sintering Device . . . . . . . . . . . . . . . . . . . . .

. 69

Figure A.2.5: Patch with BCB lens 3D model from HFSS simulation . . . . . . . . . . . .

. 70

Figure A.2.6: Patch With 50 µm Dielectric Lens 3D model from HFSS simulation . . . . . . 70

Figure A.2.7: Profile of BCB lens printed on top of patch antenna.

. . . . . . . . . . . . . . 71

Figure A.2.8: Lens Barrier Fabrication.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure A.2.9: Lens Dielectric Fabrication. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure A.2.10:3D render of Coaxial Chip Interconnection . . . . . . . . . . . . . . . . . . . 73

xi

CHAPTER 1

INTRODUCTION

1.1 Introduction

An approach to fabrication of fine resolution printed circuit components with rapid annealing

of conductive materials and rapid fabrication of thick film dielectric substrates is presented in this

thesis. These techniques for rapid processing include hardware design and processing of materials,

which are described in detail. Sample circuits are fabricated and measured with results shown

along with simulation data. Radio Frequency (RF) ranges up to millimeter-wave (MMW) circuit

fabrication are the primary motivation for this work.

1.1.1 Motivation

Interest in Additive Manufacturing (AM) techniques for the fabrication of electronic devices has

increased greatly in recent years. Coupled with a desire to fabricate devices with green or eco-

friendly materials: research has focused heavily on reduction of waste during the fabrication of

electronic devices and packaging. Historical fabrication methods included many caustic, hazardous

materials, and expensive equipment. By moving away from traditional subtractive manufacturing,

the requirements for masking techniques, lithography equipment, evaporation and sputter deposi-

tion machinery, and etching chemicals or chambers is drastically reduced. By using AM methods

to fabricate electronic devices, virtually no waste can be achieved by building up work pieces

with the precise amount of materials required on-demand. AM techniques also allow for far fewer

pieces of equipment, such as 3D printing to replace injection molding equipment or inkjet and

aerosol jet printers to replace photoresist mask alignment and developing equipment for patterning

of materials [2].

1

1.1.2 Review of Additive Manufacturing

Most common practices for fabrication of printed circuit boards (PCBs) involve placement of a

pattern onto conductive materials clad to either side of a dielectric or insulating material. The

conductors are systematically removed to leave a desired pattern forming the electrical pathways

for devices and components that make up a circuit. This process can involve toxic chemicals,

expensive equipment or laboratory time invoking many steps to yield a patterned material on a

substrate or wafer. With the use of AM techniques, portions of a circuit or even the entire substrate

can be fabricated from the ground up using basic materials. This is where 3D printing has gained

most traction in the past decade, as plastic components can be fabricated layer by layer to create

a physical part that can be touched and used with very few steps and materials required [3, 4,

5, 6, 7]. This is the power behind additive manufacturing; a single machine has the potential to

fabricate most or all an electronic circuit for use by a consumer, requiring less laboratory space and

less material waste to create similar products in comparison to traditional manufacturing methods.

Relating to the first example of PCB fabrication, a conductive ink may be deposited in the exact

final pattern and thickness designed by the user with 3D printing. Once processed, this conductive

layer can be used in the same way a PCB fabricated with pattern, developing, etching, and plating

steps used by subtractive methods but realized in one or two steps with far less waste, equipment,

or laboratory space.

1.1.3 Review of Aerosol Jet Printing

Aerosol jet printing (AJP) has gained a lot of traction within the AM fabrication world in the

recent decade. Offered commercially through Optomec, research and development of new AM

processes have created new methods for the deposition of conductive, dielectric, magnetic, and

semiconducting materials on-demand without the requirement for pattern and etching processes.

Virtually an entire laboratory of expensive and specialized equipment can be replaced by a printer

and few supporting equipment for processing of the deposited materials. Fine resolution patterns

can be created on the fly with little programming skills required by using an AJP. This makes AJP

2

Figure 1.1: Cutaway view of Optomec 5x print head.

highly desirable for RF circuit prototyping and fabrication, as very small features ranging from 10

µm to 100 µm can be easily reproduced. Material characterization and processing of the deposited

films is the most challenging aspect in relation to the use of AJP for electronic circuit fabrication.

A lot of focus and attention have been in this particular area recently. This thesis makes use of the

advantages of AJP and draws best practice for how to overcome some of the challenges involved

with rapid processing of these materials for RF and MMW circuits.

Figure 1.1 demonstrates the 3D structure of the print head used in the Optomec AJP process.

Atomizers containing liquid inks form an aerosol mist which then route to the print head. This

mix of aerosolized particle mist and nitrogen from the atomizer is introduced into the print head

through the top inlet. A sheath gas of nitrogen is also inserted into the body of the assembly (shown

on the left). This sheath gas defines the size of the feature to be printed by exerting pressure on

the mist stream in the lower funnel chamber before exiting through a print nozzle to be installed

at the bottom of the head. The print nozzle (not shown in the figure) can range from 100 µm to

300 µm exit orifices in steps of 50 µm. These various nozzle tips allow for intermediate ranges

of orifice sizes between the neighboring size. The smallest nozzle yields the smallest feature size,

3

and the largest nozzle yields the largest feature size. Increasing the flow rate of the ink or the

sheath gas may drastically increase or reduce the feature size and deposited thickness according to

experimental procedures.

1.2 Conductive Materials

1.2.1 Overview

Conductors are a valued component when it comes to deciding the fabrication of a PCB. Cost of

materials and ease of fabrication are often the key deciding factors when metal is being considered.

Choices of metal conductors for circuits can vary between Gold (Au), Silver (Ag), Copper (Cu),

Tin (Sn), Titanium (Ti), and Aluminum (Al), for most common applications. Copper is a soft,

malleable, ductile metal that has been historically chosen for use by the electronics industry for its

low cost in comparison to its rarer, high conductivity relatives such as silver. Copper is often used

for most printed circuit interconnects or traces found on substrates. When passivated for protection

from oxidation, copper can be used for high current and low resistance of PCB conductors. More

valuable conductors are often much thinner and used either as oxidation protection or for high con-

ductivity applications. For environments where oxidation or exposure to atmospheric conditions

cannot be avoided, other conductive materials such as gold may be used as a plated layer on top of

nickel and copper to protect underlying surfaces, or as a complete replacement for the conductor

as a whole.

1.2.2 Traditional Fabrication Methods

There are various methods for application of conductive metals onto substrates for the basis of

conductive paths or traces. Common techniques used for large scale fabrication of conductors

involve either deposition of metals at a molecular scale or the adhesion of large films or sheets of

metals to a board surface. While these methods of conductor application are additive in nature, they

also require subtractive methods in order to pattern and remove unwanted materials to leave the

desired conductive features on the substrate. These methods have been tried and true for decades

4

Figure 1.2: Left: mechanical polishing of unwanted metal layers must be performed, alongside
pattern and etch lithography to reach desired metal patterns. Right: AM methods allow for the
final metal pattern to be achieved in the first steps, without removal of unwanted material.

and have high levels of repeat-ability and predictable outcomes. However, the downside to such

methods is the cost of equipment, materials, waste, and chemicals required for the entire process.

Green or eco-friendly solutions are difficult to achieve with a subtractive process. See Fig. 1.2 for

illustration of traditional methods and additive methods proposed below.

1.2.3 Additive Manufacturing Conductors

A desire to remove the subtractive process completely from printed circuit fabrication has been ex-

panding with the introduction of 3D printing. Rapid prototyping of designs with short turnaround

time and lowered cost is highly desired. In order for additive manufacturing circuit fabrication to

be practical, it must be highly comparable and cost-competitive with traditional methods. For high

frequency operations, conductors must be low ohmic resistance, maintain controllable impedance

matching, and have minimal electrical noise [8]. Pattern and etch lithography processes have

yielded consistent and accurate fine resolutions of conductors for decades. In recent years, tech-

nologies such as injket and aerosol-jet printing have become popular due to relative low-cost of

5

Metallization and PolishingAdditive-Only MetallizationFigure 1.3: Proposed Reel to Reel fabrication using AJP and flash sintering for conductive traces.

materials and post-processing required. These two printing techniques have been the at the front

of attention, as they can fabricate fine resolution circuit components with precision in the micron

(µm) range on nearly any surface.

The leading challenge brought forth by AM conductor fabrication is the nature of the materi-

als being used. In comparison to traditional methods, AM conductive materials have the unique

challenge of requiring processing steps to form high conductivity films after being deposited. The

most common technique for printing conductive materials is in the form of a nanoparticle (NP) ink

or nanoink. These inks are formed of conductive molecules on the scale of nanometers to fractions

of a micrometers, suspended in a dispersion of liquid to prevent clumping and oxidation. In order

for this ink to become conductive on a scale comparable to sputtered, plated, or rolled films of

metal (known as "bulk" conductivity) they must be annealed or sintered to form conductive net-

works of molecules. This process can have many different approaches with varied outcomes and

results, which are discussed within. The desire for AM conductive materials is to be a successful

replacement or substitute to a compatible process for use in large scale processing. In Chapter

1, literature review of various types are compared and contrasted, and an optical flash sintering

6

system is described in detail for conductive silver nanoinks deposited by AJP. Ultimately, this al-

lows for a reel-to-reel fabrication method to be integrated using AJP and flash sintering. Printing,

drying, and sintering steps can be performed with individual machines connected via rollers as the

substrate is fed through them. A brief description of this process can be seen in Fig. 1.3.

1.3 Dielectric Materials

1.3.1 Overview

Dielectric materials are the second critical component for circuit fabrication. Substrates for nearly

all printed circuits are formed using dielectric compounds. For RF circuits, dielectric substrates

with low loss and high performance characteristics are chosen for each specific application. Both

rigid and flexible substrates can be fabricated with the use of polymers, hydrocarbons, elastomers,

fibers, glasses, and even ceramics. One of the most common substrates used for electronic circuits

is woven fiberglass board such as FR4 [8]. While common substrates may be inexpensive to mass

produce and have many uses, they are not always the best choice for RF applications. As technol-

ogy has advanced and frequency requirements for communication have pushed past microwaves

and into millimeter-wave frequencies, dielectric substrates with much lower losses have been re-

quired to meet performance demands. While many RF substrates are designed with particular uses

in mind, the application may dictate which materials are appropriate. As with other fabrication pro-

cesses, both subtractive and additive manufacturing methods have been developed to meed those

needs.

1.3.2 Applications

Using the 3D printing approach with AJP described in this thesis allows for rapid design and

development of thick film dielectrics, and new fundamental applications can be achieved with ease.

Relative to traditional processes, AM has the potential to reduce processing time of dielectrics

from weeks or days to hours or less with few or single steps [9]. With AM, various thickness films

may be created, allowing for step structures and ramps to interconnect and route around chips

7

with different thicknesses and material properties. Interconnection distance between chips can be

reduced to the absolute minimum on the same z-plane. Active and passive devices can be placed

into embedded cavities, and heterogeneous integration of hybrid RF and MMW circuits can be

achieved with minimal number of steps and vastly reduced processing time [10].

1.3.2.1 Different chip thickness

Active and passive devices of various technologies range from ceramics, organics, and metal films,

to semiconductors of varying elements and alloys. Each of these technologies may vastly differ in

x and y dimensions as well as z-thickness when placed and processed on boards. Many traditional

hybridized circuits comprise of a combination of etched distributed-elements, surface mount de-

vices (SMD), bare die, chip capacitors, resistors, inductors and baluns. In order to interconnect

these devices, a mix of microstrip traces or waveguides and transitions weave and route through a

board plane or multiple planes using vias in order to make connections to devices with rigid con-

nectors or pads with wirebonded leads. This mix of technologies allow for an engineer to pick and

place components on demand from many different manufacturers and subset families within those

groups. By using a substrate as a carrier plane of either planar or non-planar z-height, devices may

be attached or glued in place ahead of interconnection. The challenge introduced with mixing of

technologies is the interconnect, which can be improved with 3D printing. By placing components

onto a carrier substrate and then printing dielectric filling in moats, valleys, and dams around the

parts, 3D printed interconnects may be formed to make the electrical connection hybridization. For

these various devices with vast ranges of z-height, AM allows for material agnosticism.

1.3.2.2 Minimal Interconnect Losses

One major challenge when utilizing a hybrid circuit design with multiple thickness chips is the

format used for interconnection. Wirebonding of two chips with a large difference in z-height

or added x and y distance between chips will increase the parasitic properties of the wirebond

such as series inductance and resistance. One solution is to use dielectric embedding of chips or

8

Figure 1.4: Various embedded and integrated MMIC circuits formed as integral active MMW
systems.

dielectric ramps to bridge connections for 3D printed conductive interconnects. By allowing for

devices to be placed closely together with minimal x, y, and z distancing, the minimal interconnect

loss can be achieved for DC and RF circuits. Allowing for custom 3D printed shapes, routes,

and materials to be used increases the fabrication efficiency and robustness as well as reducing

potential interconnect loss over traditional connections. AM processing removes the difficulty

in mask alignment required for hybrid designs that are not one-off fabrications; as component

placement machines have certain tolerances, 3D printing greatly reduces the requirement for such

tolerances with tailored deposition.

1.3.2.3 Embedded Actives

Embedding of devices in dielectric materials allows for improved hybrid designs of mixed tech-

nologies. Embedded actives as well as passive biasing components allow for systems to become

packaged into the substrate rather than sitting exposed on the surface of a card. While card and

panel technologies are heavily used and popular for RF circuits, the implementation of hybrid

9

IPD AntennaIPD AntennaHornMMICViaMMICResonant Cavity AntennaMMICMMICMMICPatch AntennaMMICDielectric LensAntennacomponents sourced from various manufacturers increases the challenge of hybrid circuits without

fully packaged devices. Embedding active devices into a self-package improves reliability and

robustness of the system and reduces the difficulty of designing hybrid circuits. This concept was

heavily used in the 1990s by companies such as General Electric for the High Density Interconnect

(HDE) fabrication assembly [8, 11]. Embedding of active devices also allows for self-packaging

in ways which were challenging before, but now would allow for integration of active compo-

nents with 3D structures. One such structure is a monolithic microwave integrated circuit (MMIC)

embedded in a horn antenna (see Fig. 1.4).

1.3.2.4 Heterogeneous Integration

Heterogeneous integration has traditionally been a wafer level technology involving many diffi-

cult steps and requiring expensive masking techniques [1, 12, 13]. With the use of 3D printing

on substrates and wafer surfaces, this type of close device integration can be achieved without the

tedious masking, liftoff, coating, and oxide growing processes used in wafer fabrication to develop

membranes, bridges, and layer interconnects. Instead, by using 3D printing, devices can be closely

placed either with automation or manually for one-off designs. These placed components can vary

in distance between as well as z-height differences and still be interconnected, integrated, and pack-

aged in similar manors with far less steps and less expensive equipment. The application of this in

the future could allow for integration of microelectromechanical systems (MEMS), surface mount

or 3D printed transistors, and both packaged and unpackaged devices within the same vicinity to be

housed on a carrier substrate or even non-planar surfaces. These technology improvements allow

for a direct chip integration regardless of thickness and size without the complications included

with wafer level fabrication. Various methods of achieving high density interconnected devices

have been shown by industry for RF MEMS devices and other small footprint circuits which re-

quire integration of varied technology chips. Benzocylobutene (BCB) polymers have been used

for the packaging of such devices for RF MEMS [14]. While traditional wafer level fabrication

requires large masking areas in order to develop only a small number of delicate membrane struc-

10

Figure 1.5: Diagram of GE High Density Interconnect fabrication technique used in the 1990s [1].

tures, similar fabrication can be done utilizing a dam and fill method with a lift off step on substrate

of choice.

1.3.3 High Density Integration Techniques

Traditional methods for achieving these desired properties was lead by research and fabrication

techniques utilized by high density integration [1]. Shown in Fig. 1.5. The main challenges sought

to overcome here include the proximity of chip placement, varied chip heights on a single carrier,

depositing as many layers with 3D printing as possible, and tailoring dielectric material to vary

across the substrate as needed for each chip.

1) In order to significantly reduce proximity of chip placement, cells can be fabricated sur-

rounding chips or sets of chips with minimal distancing allowing for the shortest possible intercon-

nection between devices. One early method for this type of multichip module (MCM) fabrication

was the chip first and chip last approach to interconnects [15, 16]. Chip first places the device face

up and then involves the fabrication of interconnects on the face of the chips. Demonstration of

this process is shown in Fig. 1.6

11

Base Substrate (alumina, or other)Mill SubstrateDeposit Ground / Die Attach Bond Chip DevicesLaminate / Epoxy DevicesDrill / Etch ViasSputter Deposit, Pattern Interconnects (Al, Cu, etc)Apply Dielectric Layer / PassivationPackage and Wire BondFigure 1.6: Diagram of Chip First/Chip Last fabrication technique used to encapsulate devices on
substrate surfaces.

Using AM techniques, the dielectric walls to form as bridges for interconnects can be selec-

tively printed around the chips in order to form rigid support. This allows for a tailored package

on the carrier with the best choice dielectric materials to interface with the chip technology being

used. Shown in Fig. 1.7 is another example of chip first approach, in which active components are

embedded in a cavity formed on the substrate surface.

2) To overcome the varying heights of chips on the same carrier board, different methods have

been used to approach this issue. Dielectric ramps, bumps, and bridges have been 3D printed

from one height to another in order to gap the distance between chips. These methods incur a few

parasitic losses similarly to wire bonding, but often with far less negative effects. The most desired

approach would involve having the face of two chips at the same height and minimum proximity

placement. To do this, the best approach taken by this thesis was to fabricate chips together in

a custom tailored package starting with the chips face down on a release agent and building the

package around them. This method allowed for closest chip placement with both faces at level

heights to create the shortest possible distance between chips. Shown in Fig. 1.8 is one solution to

12

Base Substrate (alumina, or other)Deposit Ground / Die Attach Bond Chip DevicesDeposit Dielectric Infill and RampsSputter Deposit, Pattern Interconnects (Al, Cu, etc)Apply Dielectric Layer / PassivationPackage and Wire BondSame Process, if Wire Bonds UsedFigure 1.7: Diagram of Embedded Devices fabrication technique used to encapsulate devices em-
bedded in cavities etched into substrate surfaces.

Figure 1.8: Diagram of Substrate-Less fabrication technique used in this research to print packages
with fully AM processes.

this problem best described as a substrate-less approach.

3) For active devices with different heights, the substrate-less packaging can be utilized to

13

Base Substrate (alumina, or other)Mill SubstrateDeposit Ground / Die Attach Bond Chip DevicesDeposit Embedding Dielectric (BCB)Deposit Dielectric Bridge (BCB), Deposit Metal InterconnectsApply Dielectric Layer / PassivationPackage and Wire BondSame Process, if Wire Bonds UsedCarrier Substrate (borosilicate glass)Deposit Release Agent (PMMA) Thermally Bond Chip Devices (face down)Deposit Dielectric Dams (polyimide)Deposit Infill Dielectric (BCB)Deposit Ground ConnectionsDeposit Infill Dielectric Seal (BCB)Etch Release Agent (PMMA soluble in Acetone)Deposit Dielectric Bridges Between Devices (BCB), Deposit InterconnectsFigure 1.9: Diagram of Substrate-Less on PCB fabrication technique as compliment to Chip Last
fabrication approach.

deposit or 3D print all of the materials on the bottom face of the chips (excluding heat sinking

materials at this time). The complexity of fabricating a conductive heatsink microns at a time to

overcome height differences of more than 10 µm was not undertaken in this work. Conductive

plugs of metal could be placed on the contacts used for heatsinking in order to transfer heat (and

current if not electrically isolated) away from the chip and to the same z-plane as the entire tailored

package [14]. Shown in Fig. 1.9 is another form for substrate-less approach which resembles the

chip first approach to MCM fabrication on the surface of a substrate. The major difference here

is that substrate-less allows for self-packaged systems of devices with various thicknesses and

technologies directly onto a PCB if desired.

4) By utilizing cells of dams with infilled dielectric materials, the dielectric can be varied across

the carrier board to allow for multiple substrates tailored for a truly hybridized, highly dense in-

tegration. With chip technology that may require flexibility in its surrounding dielectric well, a

rigid polymer with vastly different coefficient of thermal expansion (CTE) will likely cause delam-

ination or cracking of printed interconnects as well as the dielectric fill around the chip. In order

14

Prefab Substrate (LTCC, laminate, etc.)Deposit Ground ConnectionsDeposit Infill Dielectric Seal (BCB)Deposit Dielectric Bridges Between Devices (BCB)Deposit InterconnectsPassivate, Package and Wire BondDeposit Dielectric Dams (polyimide)Deposit Ground ConnectionsDeposit Ground ConnectionsDeposit Ground / Die Attach Figure 1.10: Left: dielectric material is spin-coated and processed one layer at a time, involving
patterning and etching. Right: AM processes allows for final dimensions to be fabricated in as few
steps as needed.

to avoid this issue, CTE matching and mechanical requirements can be met around each device

uniquely and then interconnected to the neighboring cell. This process easily allows for hybridiza-

tion that would have been made impractical with traditional methods due to cost or complexity to

fabricate multiple dielectric thick films on a single board.

1.3.4 Coating Substrates

One very common method for dielectric film fabrication used for decades in the semiconductor

industry is the spin coating and patterning process. This process involves the application of dielec-

tric materials (often polymers) onto a carrier substrate via a high speed spinner and then processed

to remove areas where the dielectric is unnecessary. This process has been used to fabricate many

structures from simple RF elements to complex MEMS circuits. But, the process is complex and

requires the use of specialized equipment and often very hazardous chemical processes. In most

cases, thin films of dielectric material are fabricated with ease in this process and then patterned

with fine resolution to achieve the detail required for the circuit. What is extremely challenging is

15

Spin-Coating, EtchingAM Processthe fabrication of small, fine featured details, with thick films. The fabrication of thick films (tens

to hundreds of microns) for polymer materials is very time consuming as it may require many steps

to achieve desired thickness of films in only certain areas of a circuit, or incur planarity issues as

the z-height increases over many layers. See Fig. 1.10 for illustration of traditional methods and

additive methods proposed below.

1.3.5 AM Techniques

Because traditional methods make fine resolution thick film dielectrics challenging, new approaches

with fully additive manufacturing methods are key to solving problems in the electronics packag-

ing and RF communication communities. By eliminating the need to process a circuit with harmful

chemicals and expensive equipment, rapid fabrication can be achieved with relatively few steps.

The technique approached within and discussed in detail involves the use of a dam and fill process.

This dam and filling process or selective dielectric deposition allows for creative and unique de-

signs where non-uniform thickness of dielectrics throughout a printed circuit may be achieved with

ease. Components that require encapsulation or potting can be surrounded with a dielectric dam

material and then filled with the desired polymer or epoxy at virtually any thickness and shape.

This allows for devices of dissimilar heights to be placed directly next to one another with shortest

possible interconnects and even fully packaged hybrid systems on a substrate. Chapter 3 describes

in detail how this dam and fill process is performed using AJP 3D printing for rapid fabrication of

thick film dielectrics and chip scale packaging (CSP) to achieve highly dense integration of hybrid

circuit components.

16

CHAPTER 2

STREAMLINING CONDUCTORS USING AJP

2.1 Introduction

Recently there has been significant research focus towards the design of high functional den-

sity electronic systems, especially for 5G applications.

In parallel, to address accurate, high-

quality, fine-resolution circuit geometry requirements: increased research into additive manufac-

turing (AM) printing techniques, such as Aerosol Jet Printing (AJP), has emerged. The issues

are complicated by low-loss flexible substrates, such as liquid crystal polymers (LCP), which are

commonly used in the design of high frequency circuits and systems. These substrates cannot be

taken through high sintering temperature processes that are commonly required for silver nanoinks.

To avoid permanent damage, it is essential that the sintering temperature remains below the glass

transition temperature (Tg) of the substrates. Recent work on LCP substrates has demonstrated 10

- 20% bulk silver (Ag) conductivity by using low-temperature thermal sintering techniques. This

paper investigates the use of a rapid ultra-violet (UV) flash annealing technique to achieve high

conductivity of Ag on LCP for use in high frequency circuits while maintaining the integrity of the

substrate. Results are compared against thermally sintered films. The resulting conductivity was

studied as a function of UV exposure time and energy, printed film thickness, surface roughness of

the substrate, and multilayer deposition.

2.2 Applications

Additive Manufacturing (AM), often referred to as 3D printing, is a process of building parts

layer by layer rather than using traditional molding or subtractive lithographic methods. It is rev-

olutionizing how critical parts get manufactured and enables rapid prototyping, reduced waste,

quick-turn custom designs, rework adjustments, and parts can be printed as they are packaged into

a single unit. Recent advances in higher print resolution, the ability to print multiple materials, and

17

the ability to print combinations of low and high-temperature materials open up the opportunity

to design and manufacture next generation electronic systems without long and expensive cycle

times [17, 5, 18, 19]. High density features and geometric structures that cannot be fabricated con-

ventionally have now become realizable using AM technologies. Among the many printing tech-

nologies, Aerosol Jet Printing (AJP) and inkjet printing are commonly applied to deposit structures

requiring fine line resolutions (10 - 100 µm). The range of inks (conductive, dielectric, magnetic,

and mixtures) that have been printed to achieve desired electrical properties has rapidly increased

in recent years with many more options under development.

Inks comprised of conductive nanoparticles (NPs) have been printed using a range of tech-

niques [20, 21, 22]. One major obstacle to overcome has been the realized conductivity of printed

metals on polymers and plastics that have low temperature limits or undesirably rough surface mor-

phologies. NP-based conductive inks consist of metal particles of raw elements such as silver (Ag)

which are smaller than 0.1 µm. They are suspended in a solvent, and the particles are often coated

with organic stabilizing agents and encapsulants. Metallic NPs provide a reduced melting temper-

ature compared to their bulk material forms [23, 24, 25, 26]. However, the organic coatings hinders

lowering of this temperature [27]. These organics must be removed by sintering. The metallic NPs

become more tightly packed after sintering which enhances conductivity by minimizing the contact

resistance between the NPs. Conventionally, an oven is used to sinter printed Ag inks. The ink and
the substrate may be exposed to temperatures as high as 200 to 300 ◦C to achieve high conductiv-
ity. However, many substrates, such as liquid crystal polymer (LCP), cannot withstand such high

temperatures without a change in their physical state or being irreparably damaged. Low thermal

budget processing of metal inks would enable access to these high frequency substrate materials

for a range of microwave and millimeter wave applications.

To meet the challenge of low temperature processing, different approaches to sintering Ag

nanoparticles (AgNP) have been investigated over the last decade [27, 28, 29, 24]. These include

curing using lasers [30], intense pulse light (IPL) [31, 32, 33, 22, 21, 34], plasmas [29], [35], mi-

crowaves [27, 23, 36, 37], as well as electrical [24] or chemical [38] methods. All techniques are

18

capable of sintering at a relatively low processing temperature that is compatible with common

flex substrates. Among these processes, the IPL, also called broadband-UV (ultra-violet) sinter-

ing, allows for sintering over a large area and can be incorporated with existing printing process

equipment, especially AJP [21, 22]. IPL uses a Xenon arc-discharge lamp as a source of high

intensity energy directed at a printed surface to achieve high conductivity on substrates. Photother-

mal processes in metal particles (thermoplasmonics) plays an important role in the sintering of

nanoparticles [39, 40, 41, 26]. It has been shown that the magnitude of photonic heating depends

on the shape and density of deposited nanoparticles [39, 42]. Using optical flash techniques, the

resulting conductivities for silver inks have been reported up to 25 MS/m [33, 22, 43, 44, 31].

IPL has mainly been investigated in the fabrication of low-frequency circuits, and little or

no work has been reported for the fabrication of circuits operating at radio-frequencies (RF) or

higher frequencies. In this paper, we investigate the use of UV flash annealing to achieve high

conductivity Ag structures on LCP for use in high frequency circuits within the LCP thermal

tolerances. Ultimately, IPL can be integrated with AJP machines to meet the needs of multi-

material (conductors and dielectrics) deposition for rapid prototyping.

2.3 Experimental Setup

2.3.1 Aerosol Jet Printing

AJP has gained significant interest as an accurate alternative to photolithography for RF circuits,

integration, and packaging. Circuits that cannot be realized or are impracticable using mainstream

coarse-feature AM methods are potentially feasible with the use of AJP, e.g., printing on non-

planar structures [45]. An Optomec 5-axis AJP was used in this work. It is equipped with two

types of atomizers, an ultrasonic atomizer for low viscosity inks and a pneumatic atomizer for

higher viscosity inks [46, 20]. Inks consisting of NPs dispersed in solvents are placed into an

atomizer to be aerosolized into an inert carrier gas (nitrogen). This aerosol combination of nitrogen

and atomized particles are then transported via tubing to the print head and jet nozzle. In the print

head, a sheath gas (nitrogen) flow rate is varied to change the shape and force of the carried aerosol

19

stream through the jet print nozzle. Features as small as 10 µm and as large as 100 µm may be

printed using various nozzle sizes and AJP operating conditions [47].

The AgNP ink in this work was Clariant Prelect TPS 50G2, with an average NP diameter of 30

to 50 nm (as listed by the manufacturer). It is comprised of a silver colloid of 50 wt. %, with 10 -

20 wt. % of ethanediol (ethylene glycol) in H2O. The ink was further diluted before printing with
deionized (DI) water by volume with ratio of water:ink::3:1. The dilution was done to decrease

viscosity from 15 cP (centipoise) closer to the viscosity of water for the ease of atomization in the

ultrasonic atomizer. According to the manufacturer, the ink can be diluted with either DI water

or ethanediol. We chose water due to a lower boiling point as well as ease of cleaning which is

important for robust AJP operation.

After printing, all samples were dried in an inert−gas oven for 1 hour at 110 ◦C with nitrogen
included to allow drying with reduced oxidation of the specimen. Samples were allowed to cool
down for 60 min before removing from the oven at 40 ◦C or less. Drying was done to allow
for proper evaporation of solvents to reduce the likelihood of cracks and delamination of films

[48, 49, 50, 51]. All samples were stored in a vacuum desiccator to limit moisture and oxygen

intake prior to the next step in processing.

2.3.2 Flash Sintering System

A simple optical flash sintering system was assembled using components purchasable through

common suppliers. It consists of a high voltage DC power supply, a capacitor bank allowing for

1000 J or greater, a germicidal Xenon (Xe) flash lamp, a 10 kV auto-transformer to trigger the arc

lamp. Fig. 2.1 illustrates the flash sintering system setup.

The process for exposing a specimen for UV flash sintering was maintained with the following

control parameters: constant flash distance (h) no greater than 35 mm, single flash exposure, and

consistent energy discharged. Irradiation energy was measured to be the same for each sample

using a Coherent FieldMaxII digital power/energy meter. With a 2 inch diameter filter, the exposure

measured 1.120 J at a 90-degree angle from various distances in front of the Xe lamp. Distances

20

Figure 2.1: Illustration of the flash sintering system.

further than 35 mm did not yield conductive samples. Repeatable measurements were made this

way, giving an estimated minimum amount of energy that is applied to a specimen during a single

flash. Because of the inability to measure a direct exposure to a power meter, it is unknown how

high of a dose of energy a sample receives. Other studies have shown that the pulse time and peak

power are important controls for thermal dosing [40, 52, 41]. Here, the peak power was fixed and

the dosage was controlled by varying the distance between the sample and the lamp. During the

discharge of the capacitor bank, roughly 1800 J is released through the flash system. It is currently

unknown how efficient the system is at delivering power to the specimen versus the energy lost

due to the various components of the system.

2.3.3 Thermal Sintering

As a comparison to flash sintering, thermal sintering of the samples was also carried out and

reported in this paper. Thermal sintering has been the most widely used method to achieve good

conductivity from AgNP inks regardless of a deposition technique. Thermal sintering can take

place with simple equipment such as a hotplate, convection oven [53], inert-gas oven, or vacuum

oven [54]. Here, an inert-gas oven was used for thermal sintering of samples. A Yamato DN411IE
Inert Gas Forced Convection Oven was used to sinter AgNP ink samples at 190 ◦C for 5 hours with
a flow rate of 5 SCCM nitrogen mixed to limit oxidation of samples. Experiments showed warping

and heavy discoloration of the LCP substrate with prolonged exposure to temperatures above 190
◦C.

21

hXenon LampSubstrateReflectorTable2.3.4 DC Measurements

A Lucas Labs Pro4 four-point probe designed for wafer resistivity measurements using a Keithley

2400 source meter was used for rapid and accurate measurement of conductive samples. The

probe pin pitch is 1.588 mm, allowing for a square specimen of 5 mm x 5 mm minimum size to be

measured. This type of resistivity structure was chosen to efficiently print many samples with the

AJP. Step height and average thickness of a sample were determined using an AEP NanoMap 500

stylus contact surface profiler. The average thickness and known area of the square allow for the

resistivity (ρ) of the sample to be calculated from the measured voltage and current on the probe

station. For accurate thickness measurements, similar samples were also printed on smooth glass

substrates under the same AJP print conditions. Resistivity (ρ) can be calculated for a square film

of known thickness (t) where the meter output of V/I is seen as resistance (R): ρ = R * t. In order

to remove the effects of the film shape and distance between the probes used, a correction factor

(CF) is multiplied by the resulting value of ρ. The conductivity (σ) of a sample is the reciprocal of

its resistivity.

In order to verify measurement accuracy, the same resistivity geometries were patterned and

etched out of copper clad LCP. Measurements of these geometries verified the correct CF to be

used in the 5 mm square samples. Measured conductivity of the 10 mm x 10 mm etched copper

standards with this correction factor were between 93 - 98% of the value for bulk annealed copper.

With the process used by Rogers Corp. to manufacture the copper, this measurement is reasonable.

For verification, a measurement was also taken of a photolithographically etched copper specimen

in order to calibrate the measurements made using the same 5 mm x 5 mm squares.

Several papers cited here use different resistivity values of bulk Ag. This thesis uses a value
from a NIST standard document, a measured total resistivity of bulk silver to be 1.466x10-8 Ω/m at

room temperature [55]. The conductivity of bulk silver is then described as 68.21 MS/m throughout

this thesis. Where possible, conductivity comparisons are referred to in Siemens/meter rather than

by percentage (%Ag) of bulk conductivity to limit confusion when comparing with other published

measurements using different bulk standards.

22

Figure 2.2: Illustration of the flash sintering symptoms. (a) As deposited Ag ink. (b) Fully sintered
film. (c) Sintered particles with air-pockets. (d) Sintered outer-layer of particles with wet defects
below. (e) delamination of Ag film from substrate. (f) Thin Ag film on rough surface.

In order to make accurate conductivity measurements of the AJP Ag films on LCP substrates,

similar DC structures were printed on both smooth borosilicate glass and LCP substrates in the

same AJP print session. Films were determined to have poor adhesion to the glass substrate. How-

ever, the minimal surface roughness of glass allows for accurate measurement of film thickness.

Based on film thickness from glass substrates and four-point probe measurements from LCP sub-

strates the conductivity of the film was calculated.

2.4 Measured Results: Physical Properties and Conductivity

Figure 2.2 shows an illustration of physical properties of the films observed with and without

drying steps taken with AJP AgNP ink. Fig. 2.3 shows microscope images of the various results.

Films prior to sintering show a darker appearance in color and may exhibit a sheen on the surface

23

LCPLCPLCPLCP(a)(b)(c)(d)LCP(e)LCP(f)teffFigure 2.3: (a) Wet AJP Ag ink. (b) Flash UV sintered AJP Ag ink. (c) Delamination of Ag ink
under flash UV sintered layers. (d) Bubbles formed under Ag ink during flash UV sintering.

(Fig. 2.3a). AgNP ink that has been properly sintered shows a condensed pattern of particles that

are more tightly bunched together and become more reflective (Fig. 2.3b). Delamination can occur

with features that did not adhere well to the substrate. This occurs when the deposited film is not

sufficiently dried before exposing to UV flashes. Local blisters can also occur when the film is

not properly dried, and this leads to darker oxidized spots due to super-heat (Fig. 2.3c). Stress

delamination can occur on some corners and small features such as transmission lines, where there

may be less surface contact area between the Ag film and the substrate. Other defects as a result of

inadequate drying are bubbles and blisters formed between printed layers, leading to a “popcorn

effect" (Fig. 2.3d). Proper drying of the AgNP ink requires the reduction of the solvent from the

ink in order to promote adhesion and reduce defects in the fabricated circuit. This step is not fully

24

(a)(b)(c)(d)necessary for oven sintering when a slow ramp in temperature is done (10 ◦C/min.). However,
to be consistent in comparison of results between oven and UV flash sintering, a drying step was

carried out to remove moisture from the ink for both techniques. To avoid oxidation of silver film,

all drying was carried out in nitrogen atmosphere.

Both the DC and RF measurements were performed on films sintered using the two techniques,

flash and thermal. To minimize any variation in film deposition using AJP, all samples were de-

posited under similar conditions and all samples were dried under similar conditions. Both DC

measurements and physical analysis was carried out on films that were flash sintered.

2.4.1 Flash Sintering

Key parameters that were determined to affect the properties of the films are surface roughness of

the substrate, thickness of the deposited film and optical exposure power. These parameters were

studied and are discussed below.

2.4.1.1 Exposure and Film Thickness

Sintering of films under UV flash was carried out for film thicknesses ranging between 0.5 µm

to 5 µm. The samples were initially placed 45 mm in distance from the lamp. Once dried, the

printed Ag sample was exposed directly to UV in the optical flash system a single exposure at a

time. From the first measurements it was determined that the optimal thickness for flash power

penetration was approximately 1 µm with 2 µm as the absolute maximum for the Clariant AgNP

ink. Thicker films (delta of >1.5 µm) had poor adhesion to the substrate and also led to poor

conductivity. This was determined to be due to poor penetration of the UV light into the film. Fig.

2.5 shows the Scanning Electron Microscope (SEM) images of 1 µm thick silver films on a silicon

(Si) substrate before and after flash UV exposure. SEM images show that thin films of AgNP

ink can become discontinuous after flash UV exposure and some areas even ablate if adhesion is

poor. Table 2.1 lists the measured conductivity of silver films deposited in layers on LCP. Each

layer was treated (exposed) with single or multiple flashes. The sample was allowed to cool down

25

Figure 2.4: Demonstrated process to achieve highly conductive samples of AgNP ink. Printing
and sintering is repeated with thin layers until desired thickness and conductivity is achieved.

to room temperature between the flashes. It can be noted that the conductivity does not improve

significantly as a function of number of flashes, however repeating the flash and print process did

increase conductivity (see Fig. 2.4).

Since the sintering of nanoparticles is closely tied to the magnitude of photonic heating which

depends on the shapes and densities of deposited nanoparticles [39, 42], it is reasonable that thicker

films saturate in response to further flashes. This happens as the thin sintered layer loses its thermo-

plasmonic interaction and less heat is generated during flashes, the light does not penetrate deeper

to further heat the film. To overcome this challenge, the power in the first flash can be increased or

the film thickness can be limited based on the available power. Increasing the initial pulse is also

limited by the damage threshold of the sample.

It was also noted that thin films on LCP substrate had poor effective conductivity, see Table

2.1. LCP has an average roughness of 0.5 µm and peaks of 1 µm. This leads to variation in film

thickness across the substrate as depicted in Fig. 2.2. To achieve thicker conductive films, to meet

the challenge of surface roughness and thermoplasmonic effect, a multi-layer deposition technique

26

1Table 2.1: Correlation of DC conductivity versus number of flash exposures on AJP deposited
AgNP specimen.

Layer Exposure Thick. (µm) σ (MS/m) % Bulk (Ag)

1
2
2
3
3
3
4
4
4

1
1
2
1
2
3
1
2
3

0.889
1.247
1.247
1.969
1.969
1.969
2.436
2.436
2.436

0.17
0.44
1.24
1.75
1.84
4.96
6.93
7.12
8.03

0.25
0.65
1.81
2.56
2.7
7.27
10.16
10.44
11.77

was followed. Here, each layer was dried and flash sintered before the deposition of the next layer.

The surface morphology of the final AgNP ink deposit layer was measured to be less influenced

by the surface of the substrate, and instead solely by the deposition pattern and layering done by

the AJP. Layers following the same printing pattern and flow rates exhibit a “corn row" effect with

consistent peaks and valleys in the final layers. In order to overcome this effect, 90-degree rotations

in print patterns were also made to reduce overall surface roughness and achieve planarity in the

final layers of samples. Average surface roughness <0.3 µm was achieved consistently on LCP

substrates for two or more layers.

The distance from the flash tube to the surface of sample was highly critical for the preferred

amount of energy transferred. Too close to the conductive ink and the particles ablated from the

substrate (Fig. 2.5, right). Too far from the conductive ink, and single or double exposures did

not induce enough energy to sinter the NPs. In order to fix the distance from the flash tube, an

adjustable table was placed in the exposure drawer of the flash system with a height determined by

successive experimental data. Starting from 45 mm, an optimal distance of 35 mm was determined

to provide good conductivity with a limited number of flashes. Table 2.2 shows the measured

conductivity of films exposed under this optimal setup, and this distance was used in all subsequent

experiments. With these refined and optimized parameters, the highest conductivity of the samples

27

Table 2.2: Optimal exposure distance and number of flashes for conductivity.

Layer Exposure Thick. (µm) σ (MS/m) % Bulk (Ag)

1
1
2
2
2

1
2
1
2
3

1.312
1.312
2.239
2.239
2.239

7.5
8.2
3.4
13.2
12.5

11.04
11.96
5.04
19.36
18.36

Note: Effect of surface roughness is not accounted in these calculations.

Figure 2.5: SEM images of as-printed (left) and UV Flash Sintered (right) AJP Silver NPs on Si.

measured to date was 1.48x107 S/m (roughly 21% bulk Ag, Table 2.3).

The total amount of energy that a AgNP film can be exposed to has its limitations. Too few

exposures yielded poor conductivity, while too many exposures lead to high resistivity due to

ablation, cracking, or delamination. For example, the conductivity of a 2 µm layer (delta of 0.927

µm atop the first layer) of AgNP ink on LCP (Table 2.2) was found to be 3.44 MS/m (5% bulk

Ag) with a single flash exposure. After a second exposure it measured 13.2 MS/m (20% bulk Ag).

Additionally, a third flash damaged the film, forming microcracks, and the conductivity reduced to

12.55 MS/m (19% bulk Ag). The number of exposures before damage occurs depends on thickness

of the conductive ink as well as the substrate characteristics.

With optimized flash sintering, the brief period of exposure to high intensity energy the damage

to the substrate material can be minimized. This reduced exposure time is especially helpful for

28

Figure 2.6: Cross-section SEM image of UV Flash Sintered AgNP ink (light grey) on LCP (dark
grey).

materials that have strong absorption bands in the UV spectral region. Here, no damage to LCP

substrate was noted under multiple flashes. Using a Carl Zeiss Auriga dual column Focused Ion

Beam (FIB) – Secondary Electron Microscope (SEM), cross-sectional image of the sintered film

was taken, see Figure 2.6 and 2.7. Such images allows for much better understanding of the

underlying layers of Ag nanoparticles [56, 57, 58].

It can be noted that the film is uniformly

sintered in depth. Also, the sintered film is porous, which leads to reduced conductivity. Also,

the deposited film is self-planarizing on the LCP substrate. Figure 2.6 shows a closeup view of

sintered Ag cluster. It shows that the nanoparticles are fused together in a tight arrangement. The

porosity is only present between these large clusters.

29

Figure 2.7: SEM images of AgNPs sintered into tight clusters with average 30 nm diameters (left:
X 170,000, right: X 330,000).

2.4.1.2 Surface Roughness and Conductivity

As seen in Figure 2.6, LCP has a large surface roughness. Although this roughness helps improve

the mechanical adhesion of the Ag particles to the substrate, it is detrimental to the effective con-

ductivity of the film. Conductivity of the silver film is expected to be higher if this roughness is

accounted for in the calculations. For example, the first exposure showed 5.04% bulk Ag with 2.24

µm of thickness; it will be 6.5% bulk Ag when the thickness is adjusted to 1.74 µm due to surface

roughness. Similarly, the measured 18.36% bulk Ag will be closer to 23.6% bulk Ag. More accu-

rate step-height and conductivity measurements can be obtained if the ratio of metal thickness to

surface roughness of the substrate is large. This was not practical, as aerosol-jet printing deposits

only a few microns at a time of ink, having a ratio on average of 3:1 or 4:1 aspect. The estimated

conductivity of the optical flash sintered AgNP ink is expected to be greater than 30% bulk Ag

conductivity if effective thickness is reduced by 0.5 µm, which is due to surface roughness. After

FIB analysis, it was determined that the profiler estimate of the AgNP film thickness introduces an

unknown that can only be solved with a cross-section measurement.

30

Table 2.3: Comparison of DC conductivity against reported results.

Reference

[53]

This Work

[47]
[45]
[59]
[31]
[44]

This Work

[43]
[22]
[33]
[24]
[37]
[35]
[27]
[30]

Sintering Method
Oven (300 ◦C)
Oven (190 ◦C)

Oven

Hotplate (180 ◦C)
Photonic (N-IR)
Optical Flash
Optical Flash
Optical Flash
Photonic (N-IR)
Optical Flash
Optical Flash
Electrical (DC)

µ-wave

Plasma (Ar/SF6)

µ-wave
Laser

Substrate
Polyimide

LCP
LCP
Resin
Paper

Polyimide

Glass
LCP
Paper
PET
PET

Photopaper

PEN

Resin [60]
Polyimide

PEN

σ(MS/m)

25.0
15.4
12.0
10.0
25.0
20.0
17.9
14.8
10.0
9.4
6.5
37.0
16.9
5.1
3.3
3.3

2.4.2 Thermal Sintering

Thermal sintering of the AgNP ink was chosen as the best comparison between commonly used

techniques and this optical UV flash sintering method. High conductivity yields can be achieved

with high temperatures on a hotplate or in an oven [61]. Because of the desire to use a low loss RF

substrate for this comparison, an inert-gas oven was used for the experiment. By using an inert-

gas such as nitrogen in the oven for sintering, oxidation was reduced for 5 hour exposure to the
190 ◦C temperature environment. The temperature chosen was also due to the low glass transition
temperature (Tg) of the LCP substrate [62, 63], which exhibited warping and discoloration at
temperatures greater than 200 ◦C. Rogers Corp. lists the melting point for ULTRALAM 3850HT
substrate at 330 ◦C, which we maintained with substantial margin. After thermal sintering, the
specimen were gently cleaned using a hi-polymer eraser to polish the sintered silver and remove

31

any oxidation from the conductive films. They were then rinsed with isopropyl alcohol to remove

any polymer and organic debris. Polishing the films also verified that the silver nanoparticles

adhered well to the substrate surfaces.

Thermal sintered AJP Ag ink showed to have a similar surface morphology to what was measured

with flash sintered samples. Surface roughness and thickness per printed layer were also similar

using the same printing parameters. The specimen measured 2.0 µm thickness with conductivity

of 15.4 MS/m (22.5% bulk Ag), and a possible effective conductivity of 30% bulk Ag with 0.5

µm thickness removed due to surface roughness of the LCP. Figure 2.8 shows FIB milled SEM

image of the thermal sintered samples. Thermal sintered films show less porosity than the flash

sintered films, this in turn leads to higher measured conductivity. By having a comparable surface

roughness and DC conductivity to the flash sintered samples, the thermal sintering method was

shown to be a good experimental control for this process. The same processes were repeated for

RF structures to demonstrate the differences and advantages between the two.

2.5 Measured Results: RF Circuits

In the literature, a range of high frequency circuits fabricated using different AgNP inks as

well as different substrate types has been reported. Table 2.4 lists several high frequency circuits

fabricated using AgNPs and their results. The most common sintering method was found to be

thermal, with a variety of substrates ranging from Liquid Crystal Polymers (LCP) [20, 47] and

Polyimide (PI) [61], to Polyethylene terephthalate (PET) [54], and Pyrex glass [64]. For thermally

sintered AgNPs on LCP and PI, the highest frequencies ranged upwards of 210 GHz with maxi-

mum insertion losses of 25 dB for filters [20], and insertion losses of 0.366 dB/mm for coplanar

waveguide (CPW) transmission lines [61]. For Xe broadband flash sintering, the only publication

known at this time used a spraying technique to deposit AgNPs onto PET substrates [22]. The

authors of that publication fabricated a 5 GHz coplanar antenna spraying the film with 4 layers

which shown a mean thickness of less than 1 µm. These publications set a baseline for expressing

this method of optical UV flash sintering of AgNPs deposited by AJP for fine resolution on LCP

32

Figure 2.8: FIB cross-section SEM image of Thermal (Oven) Sintered AgNP ink (light grey) on
LCP (dark grey).

RF substrates. The frequencies chosen demonstrate useful applications in 5G technologies and

mm-wave RF circuits.

In order to draw a direct comparison between traditional oven sintering and the optical flash

method described in this thesis, microstrip transmission lines were fabricated on LCP substrates.

The sample set for optical flash exposure required twice as many print sessions to achieve the same

thickness as the thermal sample set. Once dried and after a second sintering was performed, both

sets were measured using a Keysight N5227A PNA Microwave Network Analyzer from 1 GHz to

67 GHz (Fig. 2.9). The AJP fabricated transmission lines were 240 µm width by 34 mm length

on 4 mil LCP with a copper ground plane. The measured S-Parameters show a reasonable amount

of loss to be expected for a long length transmission line with roughly 20% bulk Ag. Dividing the

measured S-Parameters by 34 mm, Table 2.4 shows that at 40 GHz the transmission line had an

33

Table 2.4: RF Structures using AgNPs

Ref.

Deposited

Sintering

Substrate

Ink Formulation

Insertion Loss

This work

AJP

Xe (broad)

LCP

PRELECT TPS 50

Transmission Lines

Inkjet

Bake

Pyrex

CCI-300 Cabot

AJP

Bake 140 ◦C

LCP
Kapton

PRELECT TPS 50

Other RF Circuits: Antennas and Filters

Xe (broad)

LCP

PRELECT TPS 50

Ar Plasma

VeroWhite

PRELECT TPS 50

AJP

AJP

Inkjet

Bake 120 ◦C

[60]
PET

0.11 dB/mm @ 40 GHz
0.16 dB/mm @ 60 GHz
0.162 dB/mm @ 10 GHz
0.265 dB/mm @ 20 GHz
0.366 dB/mm @ 110 GHz
0.546 dB/mm @ 110 GHz

-11.62 dB @ 16.3 GHz
Patch, Gain: 6.69 dBi
-14.6 dB @ 25.8 GHz

Quasi-Yagi-Uda

[64]

[61]

This work

[35]

[54]

[22]

[20]

[45]

Novele IJ-220

-35.49 dB @ 2.49 GHz

Spray

Xe (broad)

PET

Lab made (TGME)

AJP

AJP

Bake 160 ◦C

Bake 168 ◦C

LCP

PRELECT TPS 50

FormLabs

PRELECT TPS 50

Multi-band antenna
-27 dB @ 5 GHz

Patch, Gain: 3.3 dBi
-25 dB @ 210 GHz
THz Band-stop filter
-10 dB @ 140 GHz

THz Curved Lens filter

insertion loss of 0.11 dB/mm and 0.16 dB/mm at 60 GHz. This demonstrates the comparison of

the oven and flash-sintering methods for the same AJP circuits, which yielded very similar results.

Three patch antennas were also fabricated using the optical UV Flash sintering technique as

well as three using the oven sintering method described in the above section. While the data showed

repeatability for each, the data sets were reduced to one patch of each method to prevent crowding

of data in the figure. The patch antennas were measured on a PNA to demonstrate S11 at the center
frequency from the range of 14 GHz to 17 GHz. The main focus of Fig. 2.11 was to compare

how the two sintering methods effected the RF parameters of AJP printed silver nanoparticle ink

on LCP substrates which radiate power.

The patch antennas were also fabricated using 4 mil thickness LCP sheets with 17.5 µm copper

cladding on the back for ground plane. This design was consistent with the transmission line

fabrication. The antenna was designed using Ansoft HFSS simulation software. The antennas

were simulated having a resonant frequency of 16 GHz, while using 25% bulk conductivity for the

34

Figure 2.9: 34 mm long microstrip transmission line printed on LCP. S-parameters shown for both
the UV and oven sintered samples.

Figure 2.10: Connectorized Ag transmission line on LCP.

printed transmission feed line and patch of antenna. As with the transmission lines, two sets of

antennas were fabricated with the Optomec AJP in order to draw a comparison between sintering

methods. Using a Satimo Starlab near field measurement system, results of the antenna showed

a gain of 6.69 dBi for a single patch antenna which was flash sintered, see Fig. 2.12 and 2.13.

Measured S11 parameters show that the frequency was 16.3 GHz rather than the designed 16 GHz.
This was accounted for in simulation due to a reduced size of the patch antenna parameters by 50

µm on each side. The oven sintered antennas had similar results as the flash UV sintered antennas.

Simulation was adapted to best fit the measured results using a finite conductivity boundary

35

010203040506070Frequency (GHz)-60-50-40-30-20-10S11 (dB)-7-6-5-4-3-2-10S21 (dB)Flash Sintered S11Oven Sintered S11Flash Sintered S21Oven Sintered S21Figure 2.11: S-Parameters of patch antenna sintering comparison.

with 14.8 MS/m (21.7% bulk Ag) and a surface roughness of 800 nm for the patch antenna and

feedline, with an overall reduced dimension of 50 µm on each feature. To further increase accuracy

of the simulation, an impedance boundary was added for the surface area of the pin contact from

the connector (Southwest 1092-01A-6 2.92 mm Female End Launch Connector, Fig. 2.10) using

1 Ω of series resistance to show the effects of pin contact resistance to the printed Ag.

These two additively manufactured circuits demonstrate the usefulness of optical UV flash

sintering for RF circuits which require fine patterning on low-loss substrates. This work shows that

RF circuits can be fabricated using a combination of AJP and flash sintering without damaging the

substrate or reducing its integrity.

2.6 Discussion

A flash sintering technique along with aerosol printing was demonstrated for rapid prototyp-

ing of RF circuits. Further studies are needed to determine the optimal power transfer into the

36

1414.51515.51616.517Frequency (GHz)-20-18-16-14-12-10-8-6-4-20S11 (dB)00.0.0.0.0.0.0.0.0.1AJP Ag Patch Antenna ComparisonSimulationFlash SinteredOven SinteredFigure 2.12: Polar pattern of UV sample patch with gain 6.69dBi.

silver film. In particular, it is believed that the power absorption by non-sintered film is higher as

compared to partially or fully sintered films due to change in optical absorption properties. While

currently unable to investigate the occurrence of the densification process and related photonic heat

changes, other studies have shown that particle size and temperature induced by photonic sintering

are directly related [65, 39]. In addition, the porosity of sintered film was not fully considered in

this work. FIB milled cross-sections of both thermal and UV flash sintering show that the limita-

tion of AgNP ink conductivity can be related to factors of surface roughness, porosity, and particle

size. If porosity and surface roughness of the substrate are to be considered in conductivity, the

estimated conductivity of the sample is greater than 30% of bulk silver conductivity. Porosity

in the films appeared to range from 50 to 200 nm in some areas of measured samples. Bimodal

or trimodal particle distribution can potentially be used to reduce porosity. Porosity in the film

leads to lower conductivity and also degrades RF performance. Parameters such as porosity and

spectral response are closely coupled to the ink nanocompositions and will require unique process

37

Figure 2.13: UV sintered AJP printed antenna on an LCP substrate.

developments to optimize conductivity versus thermal loading and damage thresholds. It was also

determined that the surface roughness of the substrates effects the conductivity calculations. Better

models should be used to calculate the conductivity of deposited films that accounts for substrate

surface roughness and the porosity of the deposited film. In conclusion, flash sintering of AgNPs

is a process which can be further improved and optimized as potential processes for reel-to-reel

and other manufacturing techniques to improve circuit fabrication in the future. In brief, detailed

material analysis needs to be carried out to further understand the properties of silver ink deposited

and sintered using the flash technique.

2.7 Conclusion

A direct comparison between optical (UV) flash and thermal sintering of AJP AgNP inks was

made. The advantage of flash sintering is that it is rapid and it can be incorporated as integral part of

the AJP system. Similar conductive values and RF performance can be achieved between the two

38

techniques. DC conductivity values were shown to be comparable for both techniques: 22.5% bulk

Ag for thermal sintering, and 21.7% bulk Ag for flash sintering. The flash technique is compatible

with sintering of thin layers (<1.5 µm thick), and multiple layers have to deposited and sintered

to achieve a desired thickness. The primary advantage of thermal sintering is that it allows for
processing of many layers (>10 µm thick) simultaneously. However, the process time is long (∼1
hr) and the process temperature is high, and thus not compatible with low temperature substrates.

The flash technique does not affect the properties of the substrate, which LCP was studied here.

Transmission lines operating up to 67 GHz and a patch antenna with center frequency of 16.3 GHz

was demonstrated with good RF characteristics.

39

CHAPTER 3

THICK DIELECTRICS USING AJP

3.1 Introduction

High functional density is highly desired for the next generation of electronics systems. Het-

erogeneous integration of many semiconductor technologies are needed to meet the need of high

functional density systems, esp. microwave and millimeter wave systems.

In the open liter-

ature, any approaches have been demonstrated to meet the need of heterogeneous integration

[66, 67, 68, 69, 70]. This includes integration of different semiconductor technologies on a single

chip or a common substrate. For RF systems, a range of semiconductor technologies are needed

including Silicon (Si), InP, GaAs, GaN, SiC, etc. bringing all these on a single chip is very chal-

lenging and cost prohibitive [67]. Thus, integration on a common substrate is attractive [70].

Along with different semiconductor technologies, many passive elements are needed in the

design of a RF system. For example, the RF front-end design requires passive elements such

as filters, antennas, directional couplers, etc. These passive elements have to be placed in close

proximity to the active elements (e.g., amplifiers, oscillators, switches and detectors). In a typical
RF system, the majority of the area (∼90%) is occupied by the passive elements. Thus, it is not
economical to carry out RF system integration on a chip and integration on substrates is desired

[71, 10]. Apart from component needs, there are many other challenges that needs to be tackled to

design a truly high functional density system.

The mechanical compatibility of dielectric materials used for substrates is often a large chal-

lenge to meet when it comes to high density fabrication. In an RF system, there is often an intermix

of technologies for each device in the RF signal chain. This intermixing of material differences

and physical size differences (such as height or shape) requires materials for encapsulation, filling,

dielectric bridging, and interconnect supports to be uniquely tailored to the application at hand.

Different substrate chemistry supports different expansions and contractions of materials under

40

thermal stress, leading to difficulties in fabrication approaches.

For RF circuits, often choices of dielectric materials can be made by finding the desired per-

mittivity, loss tangent, and thermal capacity. Material choice for substrates can have many factors

not limited to: coefficient of thermal expansion (CTE), heatsinking methods, external DC biasing

components, environmental requirements (moisture intake, chemical resistance, thermal shock,

flexibility), and material adhesion. CTE mismatch in a hybrid circuit is a very real occurrence, not

just with differing technologies being integrated, but also where material interfaces occur with 3D

printed components, ramps, interconnects, and packages. As temperatures increase during fabrica-

tion steps or during environmental interactions, differing CTE properties will expand or contract,

causing breaks in 3D printed sections of circuits.

Finding the appropriate intermediate materials for dielectric substrates can also cause difficulty

with dispensing the raw materials to develop the high density circuit. Most commonly this diffi-

culty is found in the viscosity of the material precursor or uncured polymer resin. The difficulty

with using low viscosity materials which may have other highly desired properties becomes how to

dispense large quantities in short periods of time with high resolution. This is challenging, as spin

coating fabrication process often used on wafer level packaging will only yield very thin films after

many processing steps. 3D printing becomes the obvious choice for low viscosity materials, but

the resolution capability is lost with spillage of the material as it flows easily without constraint.

In order to overcome this challenge, a dam and fill process can be utilized for fabrication of thick

film dielectrics tailored with high resolution to a vast number of substrates and surfaces.

To meet all of the above challenges, here a new process is introduced, referred to as a dam and

fill process. The dam and fill process can take advantage of minimal spacing between components,

and allow for endless design potential. One major advantage of fabricating the substrate around the

devices is that the substrate can be formed on a carrier surface for shape, and then later removed

by using a release agent. This substrate-less fabrication step allows for planar, level interconnects

between devices of differing technologies and thickness. All supporting components such as DC

bias networks can be tightly bound to the active device and form a unique package that is easily

41

fabricated for custom applications. By utilizing these methods, high density interconnects can be

achieved more easily with minimal space placement of devices. Shortest distance interconnects

allow for the elimination of parasitic losses introduced through wire bond interconnects. This

method allows for the custom tailoring of dielectrics to all surrounding materials regardless of the

viscosity of the dielectric. Benzocylcobutene was utilized here due to its highly desired properties,

of which low viscosity has caused problems with accurately dispensing before utilization of this

method. Designs also permit the tailoring of dielectric to the metal interconnects and contacts

being used, or for integration with other dielectrics with various thermal processing requirements.

3.2 Overview

Selective dielectric deposition using a dam and filling process utilizing additive manufacturing

(AM) is presented in this thesis. It is used here for the design of millimeter wave (MMW) circuits.

For this process, Aerosol jet printing (AJP) is utilized for the building of dams and filling with

polyimide and benzocyclobutene (BCB), respectively. Dielectric islands with different thicknesses

and high aspect ratios can readily be deposited with good print resolution. Fully AM printed patch

antenna (center frequency = 94.08 GHz) was demonstrated on these dielectric structures using

silver conductive ink also deposited using AJP. Embedded circuits are discussed with a demon-

strated 0 dB attenuator die placed in liquid crystal polymer (LCP) cavity filled with BCB. Building

upon each of these circuit fabrication techniques, a unique substrate-less packaging approach was

demonstrated with the use of lift-off post processing to form a self-packaged chip-to-chip sys-

tem. Details of design, fabrication, and measurement are presented and discussed. This process

is attractive where a mix and match of substrates are desired in the design of high density MMW

packages.

3.2.1 High Density Heterogeneous Integration

Wireless systems are growing exponentially to support larger and more diverse applications rang-

ing from sensor networks for smart integration to telemedicine and distributed data storage. From a

42

systems integration point of view, it is economical to build large systems out of smaller functions.

This technique leads to the construction of a variety of products both rapidly and economically

[71]. These smaller functional components can be separately designed, fabricated and tested, and

packaged. Heterogeneous Integration will be the key technology direction to meet the future chal-

lenges of MMW circuits and systems of 5G and 6G communication.

Packaging techniques that allow the integration of active and passive devices with arbitrary

location and rotation are needed to meet the need of the next generation of RF systems. Additive

manufacturing (AM) provides the flexibility to meet this challenge. Recently, AM has attracted the

interest of RF circuit and systems designers [5, 72, 73, 74, 6]. Among the many AM technologies,

AJP is attractive as it allows fine line printing on planar and non-planar surfaces from a large stand

off distance from the surface and offers tailored alignment [47].

Fine line resolution is necessary for the fabrication of MMW circuits. One of the major chal-

lenges with AJP is that there is a trade-off between resolution and material deposition speed. AJP

is commonly used in the deposition of thin films with high resolution printing or on non-planar sur-

faces which traditional printing methods are incompatible. Many layers are deposited to achieve

thicker films and this requires long processing time [75]. Here, we propose a new processing

technique that allows the deposition of thick dielectric regions, and an approach to embed active

devices within the dielectric to meet the need for high functional density RF systems.

3.2.2 Dielectric filling (Chip Scale Packaging)

Fig. 3.1 shows this approach for selective dielectric deposition using a dam and filling process

utilizing AJP. AJP is used for both building of the dam and filling with polyimide (PI) and ben-

zocyclobutene (BCB), respectively. Dam and fill encapsulation is commonly employed in chip

scale packaging (CSP) [76, 77, 78, 79, 80]. Benefits of this process include package miniaturiza-

tion, planar surfaces, rapid prototyping, and use of a common tool for packaging of different chip

sizes. This process allows the use of low viscosity liquids that can readily flow around the chips

and minimizes the formation of voids. Damming provides a barrier that keeps the dispensed low

43

Figure 3.1: Selective dielectric deposition using a dam and filling process.

Figure 3.2: Simulation of 94 GHz patch antenna on BCB with thickness from 25 to 100 µm.
Superimposed gain at resonance.

viscosity fill liquid in a bounded region. This process was adopted here to package the chip and

to form dielectric islands that can be used to form passive MMW circuits. The flow rate can be

significantly increased during the filling process, and thick fills can be printed and cured in one

session.

This technique allows the design of novel RF circuits and systems, and provides a significant

benefit in antenna design. As an example, Fig. 3.2 shows the simulated results of a W-band patch

antenna on different thickness BCB. From scattering parameters, it can be noted that the gain and

bandwidth of the antenna can readily be tailored using dielectric thickness [81].

44

3.2.3 Thick Structures with varying heights

Utilizing the dielectric filling method, structures of thick dielectric films can be fabricated with

varying heights on the same substrate. This allows for custom tailored films without the use of

tedious, complex, and expensive mask techniques to build thick substrate and 3D structures with

dielectric materials. One major benefit of this process is that it can be used to fabricate thick dielec-

tric films for antenna substrates to allow for improved gain or tailored multi-dielectrics. Antennas

built upon thick dielectric have better efficiency and higher gain than with thin or a base substrate.

Another application would allow for complex geometric structures with step profiles to form

waveguides, low-loss air cavities, and horn antennas with the substrate materials being 3D printed

[82, 83]. Such devices shown in Fig. 1.4 could be fabricated with much less difficulty by printing

stepped dams of dielectric material and filling them with low-loss dielectric in layers, allowing for

more control and custom processing of individual layers and sections of the board rather than an

entire layer of LTCC fabricated at a time.
3.3 Dam Process

Polyimide (PI) is commonly used in many electronic devices as a robust dielectric layer. How-

ever, polyimide has a high moisture absorption rate which increases the risk of delamination during

thermal processing, and was therefore used as a barrier material rather than a fill material [8]. The
high viscosity of PI ink allows for ease of fabrication of 3D structures. With the use of a 100 ◦C
heated platen, the drying time is significantly reduced during printing. The deposited film quickly

dries and allows further build up of layers to form dam structures for containing of lower viscosity

materials.

Premixed Sigma Aldrich Poly(pyromellitic dianhydride-co-4,4'-oxydianiline) polyamic acid

(PAA) dissolved in N-Methyl-2-Pyrrolidone (NMP) was used. The material was further diluted by

weight to achieve between 5 - 7% of PAA to NMP. Using 300 µm size AJP nozzle, feature widths

of 50 µm and 400 - 500 nm thickness per layer were created. For fine features, the use of a 200 µm

size print nozzle was able to yield 30 µm widths with 600 - 700 nm thickness per layer.

45

Figure 3.3: (a) Top-down view of dam; (b) Cross-section view of brim and wall; (c) 2D scanned
profile of the dam wall.

3D printing using Fused Deposition Modeling (FDM) utilizes a "brim" printed to the base of

an item to enhance mechanical properties and improve adhesion. Similarly, a brim was used here

to improve adhesion and to support a high-aspect ratio walled dam. Fig. 3.3 demonstrates the

resulting cross-section and top-down views of a printed dam. An example profile of a dam is also

shown in Fig. 3.4.

Support structures are often removed from 3D printed parts; here, this structure is made an

integral part of the final design and not removed. The dam was constructed with a 50 µm line width

feature and supported by printing a brim outside with a 5:1 aspect ratio. Fig. 3.3(a) illustrates how

the printing of a dam with 1 feature width should have 5 feature widths at the base to form the

brim. The brim was printed with multiple layers to form a gradual slope. Printing the brim and

the wall in a single print session significantly improved the adhesion of the PI layers to each other.

Without the brim, samples showed good structural integrity during printing but would break due

to stress induced during the curing of the fill material.

3.3.1 Filling Process

B-staged bisbenzocylobutene (DVS-bis-BCB; BCB), Cyclotene 3022-35 from DOW Chemicals,

was selected due to its low viscosity of 15 cP at room temperature. The dielectric constant of

2.65 and a dissipation factor (DF) of 0.0008 - 0.002 are highly desired for RF and MMW circuits

[84, 85, 86, 87]. BCB also has good chemical and mechanical properties [88], which can be used

46

Figure 3.4: Fabricated cells for varied height dielectric dams, no fill material placement in this
step.

Figure 3.5: Dielectric array with varying BCB thickness, 5 µm to 45 µm (1 - 9 layers)

47

Figure 3.6: 3 mm x 3 mm Dielectric dam fill with 45 µm BCB thickness.

Figure 3.7: 3D profile of an example structure.

for encapsulation or passivation, and to form air bridges in planar inductors.

BCB was printed with the platen heated to 50 ◦C to remove some solvent from the ink. BCB
was printed with a 200 µm nozzle yielding 5 µm thick layers per pass after curing. Multiple layers
were first deposited and then dried in one step on a hotplate in the atmosphere set to 100 ◦C for
10 minutes. Soft cure was performed at 200 ◦C for 5 hours in an inert gas oven with nitrogen. A
hard cure was done at 250 ◦C for 3 hours under the same conditions. BCB flows during soft cure
leading to self planarization [89]. In contrast, self planarization is difficult to achieve using AJP

printed PI films [87]. Fig. 3.5 shows an array of BCB filled dielectrics with heights ranging from

48

5 µm to 45 µmm, increasing by 5 µm per layer.

3.4 Conductor Deposition

Silver nanoparticle (AgNP) ink from Clariant has been commonly used in the fabrication of

RF circuits using AJP [90, 35, 20, 61, 47, 91]. PRELECT TPS 50G2 ink is an AgNP dispersed in

water with a 50 wt% of silver colloid. Ink preparation for printing in the UA consisted of dilution

below 10 cP using a 3:1 ratio of deionized water (DI) to Ag ink by volume (25% AgNP to 75%

DI). Using a small 150 µm size nozzle, feature sizes of 20 - 30 µm and 1 - 2 µm thickness can

readily be attained. The silver structures were deposited on the dielectrics after curing. Thermal
sintering of the deposited silver was performed at 180 ◦C for 5 hours in a nitrogen based oven.
For the RF structures, 2.5 µm thick silver features for transmission lines, ground pads, and patch

antenna were printed.

3.4.1 Substrate processing

A 1 mm thick copper (Cu) sheet coated with 600 nm of sputtered titanium (Ti) was used. Ti coating

ensures good adhesion between the deposited layer and the substrate, and also Ti minimizes the

oxidation of Cu. The filler material, BCB, shows good adhesion to metal surfaces such as copper

(Cu) and titanium (Ti) often used as contacts for many electronics [84].

Optomec 5x Aerosol Jet five-axis printer with two atomizers was used. The pneumatic atomizer

is designed for material handling of various viscosity, upwards of 1000 cP. The ultrasonic atomizer

(UA) is designed for materials of low viscosity up to roughly 15 cP. The aerosol mist is directed to

the print head and print jet nozzle to be focused and deposited onto the desired substrate surface

(see Fig. 1.1).

3.5 Dielectric Property Verification

The very first application of BCB before printing with the Optomec 5x printer was to spin coat

a film onto an RF substrate and measure the dielectric constant. This was done using a laminated

49

4-mil thickness LCP with copper cladding etched on one side to form a ring resonant structure at 14

GHz. By measuring the ring resonator with and without BCB film deposited on top, the difference

between the resonant frequency shift and the scattering parameters allowed for a rough extrapola-

tion of the dielectric constant of the BCB. This was done for verification purposes to ensure that

the material purchased would behave as expected through the thermal curing profiles used in the

subsequent experimental data. A dielectric constant of roughly 2.6 was determined, and with the

use of literature published for frequencies upwards of 60 GHz it was decided to use 2.65 for all

future simulation and designs using BCB.

3.6 RF Circuits

To demonstrate the effectiveness of this dam and fill process, two simple RF structures were

chosen for fabrication operating in the MMW frequency bands: (1) embedded devices and (2) W-

band patch antenna. With success of the process, more RF structures were fabricated, including

the aforementioned substrate-less package demonstrated here. RF structures were probed using

a Ground-Signal-Ground (GSG) probe (120 µm pitch) on an MPI TS150-THZ probe station and
measured using the Keysight N5227 vector network analyzer (VNA \ PNA).

3.6.1 Embedded Devices

As illustrated in Fig. 3.1, chips can be embedded directly into the fill material or embedded in a

cavity formed in the substrate. The second technique is demonstrated here using a liquid crystal

polymer (LCP) substrate. The cavity was formed in LCP with Cu backing using a wet-etch process

[92]. A Mini-Circuits KAT-0-D+ transmission line on GaAs die with gold (Au) contacts (0 dB

attenuator) was mounted in the cavity using conductive epoxy. The edge between the chip and the

LCP was filled with BCB using AJP, allowing a short and smooth transition. Granular polymethyl

methacrylate (PMMA) suspended in solvent was printed on top of the chip faces in order to create

a resist mask for the BCB printing to reduce overspray dielectric coating the contact pads. PMMA

50

Figure 3.8: (a) S-Parameters of embedded 0 dB GaAs single chip in BCB with interconnection to
LCP. (b) Photo image of the measured circuit.

Figure 3.9: (a) S-Parameters of embedded 0 dB GaAs 215 µm chip-to-chip separation in BCB with
interconnection to LCP. (b) Photo image of the measured circuit.

was later removed using acetone before printing conductive traces with the AJP.

Three embedded RF circuits were demonstrated: (1) substrate to embedded chip transition,

(2) substrate to embedded chip-to-chip, (3) substrate to dielectric transition. The first circuit was

performed in order to achieve transition from substrate to device and back to the substrate for

measurement using a microstrip transmission line (Fig. 3.8). This demonstrated the basic function

of 3D printed interconnect over a BCB infilled cavity, with the second circuit demonstrating the

previous interconnect with an additional chip-to-chip interconnect for hybrid circuits (Fig. 3.9).

The third circuit was to demonstrate the losses associated with impedance mismatch if matching

is not taken into account for the transition period across varying dielectric constants (Fig. 3.10).

This loss shows up in the scattering parameters where the return loss is above -10 dB for S11 and
S22, which can be seen in the figures.

A 50 Ω transmission line was printed across the structure as shown in Fig. 3.11 that can be

probed using a GSG probe. Fig. 3.11 also shows the measured S-parameter. This data includes the

51

10203040506070Frequency (GHz)-30-25-20-15-10-50S11 (dB)-10-8-6-4-20S21 (dB)BCB Sample "002" S11BCB Sample "002" S2110203040506070Frequency (GHz)-35-30-25-20-15-10-50S11 (dB)-10-8-6-4-20S21 (dB)BCB Sample "014" S11BCB Sample "014" S21Figure 3.10: (a) S-Parameters of 2 mm BCB fill with transmission line interconnection to LCP. (b)
Photo image of measurement setup for GSG probe station.

effect of the microstrip transmission line on LCP. Results show that low-loss transition can readily

be designed using this fill process.

Figure 3.11: Measured S-Parameters of embedded chip in a cavity.

Of the demonstrated embedded devices, various parameters were modified to show how cus-

tom tailoring of the fabrication process can be made to fit geometry challenges that a 3D printed

AM process is well suited to solve. For manual chip placement that is not precise, transmission

lines and interconnects can printed with offset angles or curves allowing for pinpoint accuracy on

52

10203040506070Frequency (GHz)-35-30-25-20-15-10-50S11 (dB)-10-8-6-4-20S21 (dB)BCB Sample "009" S11BCB Sample "009" S2105101520253035404550Frequency (GHz)-1.2-1-0.8-0.6-0.4-0.20S21 (dB)-45-40-35-30-25-20-15-10-5S22 (dB)Measured S21Measured S22BCBChipFigure 3.12: Microscope photo images of manual placement chips before removal of protective
PMMA film and printing of AgNP interconnects. Left show purposefully offset angles, while right
show careful alignment and appropriate distancing of chips.

the finished product (Fig. 3.12). While this is similar to one of the benefits of wire bonded in-

terconnects, the ability to print the interconnect and the transmission line trace to the device from

its termination point with custom tailoring allows for a higher yield from the fabrication steps

without concerns for errors such as mask misalignment. Chips were also placed at varied dis-

tances to show the losses associated from creating a metal interconnect without proper impedance

matching over three distances between the RF chips (Fig. 3.13 shows the gap distance varied be-

tween two chips and the S-Parameters differing for each distance). Some tolerance in fabrication

processed can lead to lowered yields, which this process helps to improve those statistics by tai-

loring custom interconnects to misaligned chips. The loss in decibels is shown by the calculation:
LOSS = 1− [mag(S11)2 + mag(S12)2]

3.6.2 Patch Antenna

A 94 GHz patch antenna was fabricated on a 65 µm thick film of BCB having PI dam on a 1

mm thick Ti coated Cu substrate. Figs. 3.15 and 3.16 show the profile of the dielectrics and the

picture of the patch antenna. The feed point of the GSG launch was optimized to be as close to the

width of the 50 Ω transmission line. The signal is fed into the transmission line through a 120 µm

53

Figure 3.13: Losses: Chip Spacing over DC - 67 GHz. Distance between the chips were varied
from 85 to 250 µm.

Figure 3.14: Patch antenna 3D model exported from HFSS simulation.

pitch GSG probe. The filling step was performed in 3 print and cure steps to precisely control the

resulting thickness. Fig. 3.15 shows that the BCB dielectric may not be perfectly flat after printing

and is dictated by the planarization of the sample in the oven during curing.

Rather than forming vias, to achieve good connection, the grounds of the GSG pad were con-
nected along the PI wall by printing at a 30◦ angle on the tilted platen of the Optomec 5x (Fig.
3.17).

54

Figure 3.15: Left: 2D Profile of the dam with multiple fillings; Right: Printed Ag patch antenna
on filled BCB.

Figure 3.16: Left: 2D Profile of the dam with multiple fillings; Right: Printed Ag patch antenna
on filled BCB.

Fig. 3.18 shows the measured S11 of the patch antenna. It has a return loss of 22 dB at 94.08
GHz, and the simulated gain is 4.8 dBi. Simulation results are also included in the figure. It was

determined by simulation parameters that there is approximately 2 Ω of contact resistance between

the GSG probe and the pad. Simulation results of the antenna including a 2 Ω series resistance

is also shown in the figure. The VNA measurement and simulation results match closely. These

results show that the proposed process can be used to design MMW patch antennas with good

performance.

Multi-layered circuits: by using process compatible materials in this circuit which can with-

55

Figure 3.17: Process Camera capture of 30-degree angle printing on Patch Antenna ground con-
nection using Ag ink.

Figure 3.18: Measured and simulated S11 of the patch antenna, including a re-simulation with
series resistance added for probe to silver contact.

stand thermal cycling and multiple AJP depositions, multiple layers are fully achievable to allow

for designs such as focused antennas, capacitive coupled conductors, and dielectric lenses. The

previously discussed patch antenna can be loaded with a dielectric on the patch to change the

resonant frequency of the antenna and improve the gain characteristics or directionality of the an-

tenna. With the novelty of 3D printing a barrier to dam the dielectric material only where it is

needed, a resonator was formed atop of the 94.3 GHz patch antenna. Simulation in HFSS of a

56

7580859095100105Frequency (GHz)-30-25-20-15-10-50S11 (dB)Measured S11Simulated S11Re-Simulated S11 "ohmic contact"Figure 3.19: Measuring the patch antenna on the PNA

domed lens of BCB shifted the resonant frequency downward in frequency to 89.46 GHz. This not

only changes the gain pattern of the antenna, but also allows for the ability to miniaturize lower

frequency antennas with the same footprint of very small antennas.

3.6.3 Substrate-less Packaging

The final demonstrated RF circuit involved the use of the substrate-less 3D printed package ap-

proach. This self-packaging 3D printing method using the dam and fill steps described above, with

an additional lift-off process included (See Fig. 3.20 ). Polymethyl methacrylate (PMMA) was

used as the release material as it easily dissolves under acetone solution. PMMA was first printed

onto a carrier substrate of borosilicate glass, with the film measuring 5 µm. This thickness was

required in order to form adequate seal to the die structures. GaAs devices were placed face down
onto the PMMA film and placed on a hotplate at 160 ◦C until the devices sunk into the PMMA
and allowed for a seal around the passivation layer and contact pads. This sealing step is important

to prevent the flow of low-viscosity materials onto the face of the die. Once component placement

was achieved, the same dam and fill process used for the other RF circuits was repeated around

the chips on the PMMA film. Ag ink was printed onto the back side of the chips to connect the

ground plane of both chips and the BCB package. Acetone was used to dissolve the PMMA layer

and allow for the package to float off of the glass substrate leaving only the packaged chips. This

57

Figure 3.20: Fabrication steps used to make a substrateless package for bare die chip devices.

Figure 3.21: Fabricated substrateless package. Left: face side of the dice. Right: ground plane
printed on back with AgNP ink.

package with BCB and PI structure allowed for ease of handling and was placed face up on a board

to process the interconnect. One final BCB layer was printed on the edge of the two chips to fill

a small 5 µm valley leftover from processing. Then, Ag ink was printed to connect the two chips

and measurement was taken to demonstrate a fully AM package which can now be attached to any

surface and used as a hybrid component for RF circuitry.

By utilizing this process, the absolute minimum distance between two devices was shown with

a planar face surface regardless of the semiconductor technology being used. Both chips were

GaAs with a thickness of 100 µm for ease of demonstration. This process would allow for varied

58

1: Print PMMA Resist Material2: Determine Chip Placement3: Flip Chip Face Down4: Print Polyimide Dam5: Print BCB Fill Material6: Dissolve Resist Material5 optional: Print Backside Ground Connectionthickness dice, as the devices are placed face-down onto the lift-off material prior to dielectric

printing. This insures that the faces of the dice are both level and at the absolute minimum distance

for the printed interconnect that the device design allows. This process utilized standard chips

designed for wire bond interconnects without an impedance match tailored to 3D printed metal

traces. This impedance mismatch is the largest obstacle to the process, and future devices could be

designed with wideband transitions for printed interconnects as the intended fabrication step for

hybridized applications.

The printed package has overall dimensions of 2.5 mm x 3.5 mm and physical separation

between the devices of 23 µm. Shown in Figure 3.22, the package allows for the minimum distance

between the interconnect pads of these chips. Each chip has a passivation layer and exposed street

of 15 µm as part of the manufacturing process. This leaves the pads inset by roughly 25 µm from

the edge of the die. Because these chips were designed to be probed and wirebonded, the pads are

sized to the requirements of those tools and thus the structure itself is not fully matched from one

side to the other. The pads are larger than the width of a 50 Ω transmission line, causing a low

impedance at the pad, and the transmission line on the GaAs substrate is thinner, corresponding to

a high impedance in the middle of the die. This limits the high frequency capability of the device,

and impedance matching to overcome this was not part of this demonstrated work. With loss due

to impedance mismatch as a concern, the loss of the circuit was calculated for this package as well,

and is shown in Fig. 3.23. The loss remained below 1 dB through the designed frequency range

for the chip, keeping in mind that this is 2 chips connected together. Loss increased above 50 GHz,

which is beyond the rating of the attenuator chip.

3.7 Results

High density integration of devices on a chip-scale level are highly desired by many electronics

manufacturers. Recently, the common use for high density fabrication was utilized heavily by

MEMS and multilayer PCB manufacturing [8]. RF and MMW circuits can also benefit from rapid

production techniques for high density integration and interconnects with RF substrates and 3D

59

Figure 3.22: (a) S-Parameters of substrate-less BCB package containing two devices. (b) Photo
image of the measurement.

Figure 3.23: Losses: Substrate-less package over DC - 67 GHz. Distance between the chips were
23 µm [77 µm pad-to-pad spacing].

printing. With MMW circuit design, the substrates must be carefully chosen in order to meet

requirements for signal integrity, environmental compatibility, and mechanical compatibility with

varied fabrication technologies (such as GaAS, SiN, GaN, SiC, etc.). As the envelope for frequency

and physical size limitations of devices continues to be pushed, the production methods also must

be pushed past limitations in order to meet increasing demands.

60

                                                                                                                                                                                     3.8 Future Work

This work discussed the applications which can be utilized today in hybrid RF and MMW

circuits, and also introduced a few future concepts that can be improved upon in following research.

The major benefit to all of the above methods leads majorly to the tailored design of shapes both

planar and non-planar on substrates or self-packaged substrates. Mentioned prior, substrate based

hollow waveguides and waveguided antennas can be fabricated using the substrate or a 3D printed

substrate built upon itself using low-loss dielectric materials. While this process has been shown

with LTCC, it can be redesigned with any low-viscosity dielectric with desired loss parameters

for the chosen frequency band, making the process much more versatile for application-specific

designs.
3.9 Conclusion

A new dam and fill process to selectively deposit dielectric patches with varying dimensions

on a common substrate using AJP was demonstrated for additive manufacturing. This process has

many advantages: 1) rapid deposition of dielectrics with varying geometries using AJP, 2) allows

the use of materials that readily flow during deposition, drying or curing, 3) allows for embed-

ding (self-packaging) of chips and other components, 4) allows self-planarization of dielectrics,

5) allows for the design of complex RF circuits. A millimeter wave embedded 0 dB attenuator

and a W-band patch antenna were demonstrated, with improvements leading to a substrate-less

design package using this process. This process allows for many high density MMW circuits to be

fabricated with ease using AJP.

61

CHAPTER 4

CONCLUSIONS

4.1 Conclusions

In this thesis, two major approaches have been developed and discussed for rapid additive

manufacturing of microwave and millimeter-wave RF circuits utilizing AJP 3D printing. Both

high conductivity Ag circuits and self-packaging processes have been demonstrated with current

and future applications in order to meet the demand of high speed communications and component

manufacturing.

In Chapter 2, optical UV flash sintering was demonstrated as a viable alternative to thermal

baking of silver nanoparticle ink in order to achieve high conductivity required for RF applica-

tions. Traditional thermal methods as well as other novel processes were compared to this sintering

technique at both DC ohmic performance and for microwave applications using a microstrip patch

antenna based on LCP substrate technology. The combination of multiple print and sinter steps

were shown to achieve the high conductivity for microwave applications using AJP 3D printed

Ag. SEM cross-sectional measurements were made to show that this multilayered approach solves

issues of delamination and deformation of conductive inks with thick single layer sintering.

In Chapter 3, a new approach to fabricating AJP thick film dielectric films and self-packaged

chips was shown in order to drastically reduce the difficulty and time required to form chip scale

packages. This dam and fill process was used to demonstrate multiple cell selective dielectric

deposition on a carrier substrate with BCB material thickness spanning 5 µm to 45 µm within a 1

cm x 1 cm area. This process was used to fabricate a W-band patch antenna on BCB printed using

AJP for both dielectric and Ag conductor. To show the novelty of packaging, embedded circuits

were fabricated to introduce selective dielectric deposition as a viable addition to hybrid circuit

design. Finally, a self-packaged chip was demonstrated with a substrate-less process involving

a release agent in order to produce the absolute minimal spacing between two RF chips for 3D

62

printed interconnection and packaging with low loss.

This work demonstrates how chip scale packaging and rapid prototyping can take advantage

of additive manufacturing using aerosol-jet printing for reel-to-reel compatible applications and

reduced laboratory expenses for future works. Commercially available materials were used in order

to demonstrate relatively inexpensive fabrication with common choice conductive and dielectric

inks.

4.1.1 Limitations Overcome

Thermal processing limitations for both conductive and dielectric materials are a major issue for

most additive manufacturing goals. Low temperature substrates are often used in RF circuits, and

thus material compatible processes must be chosen within those limits. For conductive inks, optical

UV flash sintering allows for the single or multiple doses of high energy transfer to the nanomateri-

als with little damage to the delicate substrates. This is a major improvement over low conductivity

achievable by only room temperature drying and sintering of conductive nanoparticles. Dielectric

materials printed using AM processes may also struggle with compatibility of other materials dur-

ing thermal cycling. Traditional methods of achieving thick dielectric films requires many layers

of wet resin and drying or curing steps to build layers. This repeated thermal cycling cause stress

to the carrier and other sections of the fabricated item. By reducing thermal cycling to a single or a

few cure steps with thick deposition of resin in a single print session, the thermal stress is reduced

with the side effect of drastic reduction of processing time. Hybrid circuits can be formed with

multiple technologies and various z-heights with few limitations seen by traditional fabrication

methods.

4.1.2 Future Work

Many opportunities were explored in the work that lead up to this thesis topic. Several techniques

were tried and noted for potential future application. Noted in the Appendix section are methods

for room temperature sintering of Ag nanoparticle ink using select-able color spectrum LEDs for

63

plastics and other low temperature materials. This short term project involved use of UV, full

spectrum white, near-infrared and infrared 100 W light-emitting diodes to help determine which

spectrum band from 300 nm to 900 nm would cause energy absorption in the silver inks. No direct

conclusion was made from this work, but it has potential for future expansion if plastics are a

desired material for additive manufacturing.

Another area of future work is custom tailoring of dielectric geometries on top of patch anten-

nas useful either for gain focusing or frequency selection. An experimental BCB lens was printed

on top of a W-band patch antenna in order to observe the effect of resonance frequency shift. Sim-

ulation and preliminary data shown a reduction in the resonance of the antenna and proved that

this method can be further improved upon. It was mentioned chapter 3, but it was not explored in

depth.

Finally, simulation and first experimental fabrication of a hybrid chip on board process was

created to utilize a wide-band transition of microstrip to chip with 3D printed coaxial via was

explored. This topic was only explored briefly as it was too application specific to be included in

the thesis work.

The high resolution and speed of fabrication which can be achieved using AJP 3D printing can

allow for increasingly reduced size for printed circuits and reduced loss for interconnection of bare

die components. Packaging improvements will continue to be made as further exploration into

these areas increase. Complete hybridized RF circuits can be realized within hours of computer

aided design. By expanding the topics demonstrated in this work, many difficult to achieve circuits

can be fabricated with reduced time, cost, and waste in comparison to traditional methods. Reel to

reel printing of conductive materials and sintering can potentially include the use of AJP for fine

resolution features and optical UV flash sintering for high conductivity required for microwave and

millimeter-wave technologies.

64

APPENDIX

65

APPENDIX

A.1 Extra Information

A.1.1 Dielectric Verification

Verification of dielectric constants for BCB were performed for laboratory processing used in

Chapter 3. This verification was performed using measurements of an unloaded ring resonator

structure on LCP, followed by dielectric loading with BCB, curing processes, and further mea-

surement to determine the shift in resonant frequency and extrapolate the dielectric constant from

scattering parameters.

Figure A.1.1: Dielectric Verification using 14 GHz unloaded and loaded ring resonator on etched

LCP.

66

Figure A.1.2: Set of 10, 15, 25 GHz ring resonators on 4 MIL thickness LCP. Measured with no

surface dielectric loading and then after dielectric loading to determine dielectric permittivity of

printed BCB films.

A.1.2 Substrateless Package Prototypes

First prototypes for proof of concept to show substrate-less packaging involved a single die. This

chip was placed face-side down onto a film of PMMA which was previously printed with AJP onto

a borosilicate slide. The chip was placed by hand, and allowed demonstration of the AJP process to

custom tailor a printing pattern regardless of the placement orientation. Photos shown were taken

from the reverse side of the slide through various steps of the process. Melting of the PMMA

allowed to form a hermetic-like seal around the top and side edges of the die to prevent dielectric

filling to flow onto the top surface and cover traces or contact pads. A pattern was designed

for the desired size of the PI dam, and then printed to the same height as the device. BCB was

then printed to infill the dam structure and curing was performed as discussed in Chapter 3. The

structural experiment lead to the design of a two-device interconnection described and measured

in Chapter 3.

67

Figure A.1.3: First Prototype of Liftoff Process

A.2 Future Work

Specific wavelengths of concentrated light may be particularly useful in the curing of materials

or sintering of nanoparticles. Selecting filters for the wavelength may be challenging, so a se-

lectable wavelength system was built utilizing 100W LED lamps of various wavelengths including

395mn, 425nm, 440nm, 660nm, 730nm, 850nm, 940nm, and a broad spectrum 380-840nm white

LED. For materials that absorb these wavelengths, it is possible to use photonic sintering at the

specific wavelength. Early experiments shown that AgNP inks react to various selected LEDs, but

it is yet unknown how thick of a film can be dried or sintered with this system.

68

A.2.1 Ag Sintering With Broad Spectrum LEDs

Figure A.2.4: Photograph of LED Sintering Device

A.2.2 BCB Patch Antenna with Dielectric Lens

Two improvements to the dielectric dam antenna presented in Section VII B. can be explored

further with tailored shapes printed in conjunction with the patch antenna. First, dielectric dams

can be printed on the surface of the patch conductor to allow focusing and shaping of the beam

pattern. Second, multiple layered dielectric and conductors can be utilized to fabricate reflectors

below the patch antenna in order to increase gain and directivity of the antenna.

69

Figure A.2.5: Patch with BCB lens 3D model from HFSS simulation

The first of the two described was explored briefly, where the same dam and fill method with PI

and BCB were used to form a simple dielectric micro-lens as a proof-of-concept. Fig. A.2.7 shows

that the micro-lens had feature height as much as 50 µm over the distance of nearly 2 mm. Fine

tuning of parameters could allow for frequency shifting and direction changes to the gain pattern

of the antenna.

Figure A.2.6: Patch With 50 µm Dielectric Lens 3D model from HFSS simulation

70

Figure A.2.7: Profile of BCB lens printed on top of patch antenna.

Figure A.2.8: Lens Barrier Fabrication.

71

Figure A.2.9: Lens Dielectric Fabrication.

A.2.3

3D Printed Coaxial Interconnection

First proposed before the dam and fill process had been utilized for packaging of a chip on a surface

substrate, a chip to microstrip transmission line transition circuit was explored. The goal of this

experiment was to perform a coaxial via interconnect from two different z-heights on a substrate

using AJP. The 0 dB attenutator chip would be placed onto a printed ground pad and die attach

section, followed by the 3D printed structure of a via and coaxial ring. This demonstrated the

potential of high aspect ratio AgNP with AJP, but proved to be challenging. The BCB dielectric

dam shown in the 3D render from HFSS was the first design of a dam and fill thick dielectric film

as part of this research. As the goal was experimental, the application was ultimately not used,

but instead lead to further research into the dam and fill process for self packaging of chips and

interconnections as described in Chapter 3.

72

Figure A.2.10: 3D render of Coaxial Chip Interconnection

73

BIBLIOGRAPHY

74

BIBLIOGRAPHY

[1] MJ Wolf, P Ramm, A Klumpp, and H Reichl. Technologies for 3D wafer level hetero-
In 2008 Symposium on Design, Test, Integration and Packaging of

geneous integration.
MEMS/MOEMS, pages 123–126. IEEE, 2008.

[2] Min Liang, Junqiang Wu, Xiaoju Yu, and Hao Xin. 3D printing technology for RF and THz
In 2016 International Symposium on Antennas and Propagation (ISAP), pages

antennas.
536–537. Ieee, 2016.

[3] Amanpreet Kaur, Joshua C Myers, Mohd Ifwat Mohd Ghazali, Jennifer Byford, and Premjeet
Chahal. Affordable terahertz components using 3D printing. In 2015 IEEE 65th Electronic
Components and Technology Conference (ECTC), pages 2071–2076. IEEE, 2015.

[4]

[5]

Jennifer A Byford and Premjeet Chahal. Ultra-wideband hybrid substrate integrated ribbon
waveguides using 3D printing. In 2016 IEEE MTT-S International Microwave Symposium
(IMS), pages 1–4. IEEE, 2016.

Jennifer A Byford, Mohd Ifwat Mohd Ghazali, Saranraj Karuppuswami, Brian L Wright, and
Premjeet Chahal. Demonstration of RF and microwave passive circuits through 3-D printing
and selective metalization. IEEE Transactions on Components, Packaging and Manufactur-
ing Technology, 7(3):463–471, 2017.

[6] M. I. Mohd Ghazali, S. Mondal, S. Karuppuswami, and P. Chahal. 3d printed substrates for
the design of compact rf systems. In 2019 IEEE 69th Electronic Components and Technology
Conference (ECTC), pages 113–118, May 2019.

[7] Vincens Gjokaj, Cameron Crump, Brian Wright, and Premjeet Chahal. Direct Printing of
Antennas on Large 3D Printed Plastic Structures. In 2020 IEEE 70th Electronic Components
and Technology Conference (ECTC), pages 666–670. IEEE, 2020.

[8] Robert J Hannemann, Allan D Kraus, and Michael Pecht. Semiconductor packaging: a

multidisciplinary approach. J. Wiley and Sons, 1994.

[9] Eric Macdonald, Rudy Salas, David Espalin, Mireya Perez, Efrain Aguilera, Dan Muse, and
Ryan B Wicker. 3D printing for the rapid prototyping of structural electronics. IEEE access,
2:234–242, 2014.

[10] Rao R Tummala. Packaging: past, present and future. In 2005 6th International Conference

on Electronic Packaging Technology, pages 3–7. IEEE, 2005.

[11] RJ Wojnarowski, RA Fillion, B Gorowitz, and R Saia. Three dimensional hybrid wafer scale
In 1993 Proceedings Fifth
integration using the ge high density interconnect technology.
Annual IEEE International Conference on Wafer Scale Integration, pages 309–317. IEEE,
1993.

75

[12] Xing Dai, Binh-Minh Nguyen, Yoontae Hwang, Cesare Soci, and Shadi A Dayeh. Novel het-
erogeneous integration technology of III–V layers and InGaAs finFETs to silicon. Advanced
Functional Materials, 24(28):4420–4426, 2014.

[13] Timir Datta-Chaudhuri, Pamela Abshire, and Elisabeth Smela. Packaging commercial cmos

chips for lab on a chip integration. Lab on a Chip, 14(10):1753–1766, 2014.

[14] S. Seok, J. Kim, M. Fryziel, N. Rolland, B. Grandchamp, W. Simon, and R. Baggen. Bcb
cap packaging of mems switches integrated with 100- µm mmic wafer. IEEE Transactions
on Components, Packaging and Manufacturing Technology, 3(11):1799–1803, 2013.

[15] C-L Chen, R Wayne Johnson, Richard C Jaeger, MB Cornelius, and WA Foster. Multichip
thin-film technology for low temperature packaging (CCD image sensors). In 40th Confer-
ence Proceedings on Electronic Components and Technology, pages 571–579. IEEE, 1990.

[16] C Neugebauer, RO Carlson, RA Fillion, and TR Haller. Multichip module designs for high

performance applications. Microelectronics International, 1990.

[17] Ludger Overmeyer, Arndt Hohnholz, Oliver Suttmann, and Stefan Kaierle. Multi-material

laser direct writing of aerosol jet layered polymers. CIRP Annals, 68(1):217–220, 2019.

[18] Mohd Ifwat Mohd Ghazali, Saranraj Karuppuswami, Saikat Mondal, Amanpreet Kaur, and
Premjeet Chahal. Embedded Actives Using Additive Manufacturing for High-Density RF
IEEE Transactions on Components, Packaging and Manufacturing
Circuits and Systems.
Technology, 9(8):1643–1651, 2019.

[19] Vincens Gjokaj, John Papapolymerou, John D Albrecht, Brian Wright, and Premjeet Cha-
IEEE Transactions on

hal. A Compact Receive Module in 3-D Printed Vivaldi Antenna.
Components, Packaging and Manufacturing Technology, 10(2):343–346, 2019.

[20] Christopher Oakley, Amanpreet Kaur, Jennifer A Byford, and Premjeet Chahal. Aerosol-
In 2017 IEEE 67th Electronic Components and

jet printed quasi-optical terahertz filters.
Technology Conference (ECTC), pages 248–253. IEEE, 2017.

[21] KC Yung, X Gu, CP Lee, and HS Choy. Ink-jet printing and camera flash sintering of silver
tracks on different substrates. Journal of Materials Processing Technology, 210(15):2268–
2272, 2010.

[22] Marco Bobinger, Michael Haider, Yash Goliya, Andreas Albrecht, Markus Becherer, Paolo
Lugli, Almudena Rivadeneyra, and Johannes Russer. On the sintering of solution-based silver
nanoparticle thin-films for sprayed and flexible antennas. Nanotechnology, 29(48):485701,
2018.

[23] Mark Allen, Ari Alastalo, Mika Suhonen, Tomi Mattila, Jaakko Leppaniemi, and Heikki
Seppa. Contactless electrical sintering of silver nanoparticles on flexible substrates. IEEE
Transactions on Microwave Theory and Techniques, 59(5):1419–1429, 2011.

[24] Mark L Allen, Mikko Aronniemi, Tomi Mattila, Ari Alastalo, Kimmo Ojanperä, Mika Suho-
nen, and Heikki Seppä. Electrical sintering of nanoparticle structures. Nanotechnology,
19(17):175201, 2008.

76

[25] CL Chen, J-G Lee, K Arakawa, and H Mori. Comparative study on size dependence
of melting temperatures of pure metal and alloy nanoparticles. Applied Physics Letters,
99(1):013108, 2011.

[26] Roozbeh Danaei, Tony Varghese, Mostafa Ahmadzadeh, John McCloy, Courtney Hollar, Mo-
hammad Sadeq Saleh, Jonghyun Park, Yanliang Zhang, and Rahul Panat. Ultrafast fabrica-
tion of thermoelectric films by pulsed light sintering of colloidal nanoparticles on flexible and
rigid substrates. Advanced Engineering Materials, 21(1):1800800, 2019.

[27] Jolke Perelaer, B-J De Gans, and Ulrich S Schubert. Ink-jet printing and microwave sintering

of conductive silver tracks. Advanced materials, 18(16):2101–2104, 2006.

[28] Sebastian Wünscher, Robert Abbel, Jolke Perelaer, and Ulrich S Schubert. Progress of al-
ternative sintering approaches of inkjet-printed metal inks and their application for manufac-
turing of flexible electronic devices. Journal of Materials Chemistry C, 2(48):10232–10261,
2014.

[29] Franziska M Wolf, Jolke Perelaer, Steffi Stumpf, Dirk Bollen, Frank Kriebel, and Ulrich S
Schubert. Rapid low-pressure plasma sintering of inkjet-printed silver nanoparticles for RFID
antennas. Journal of Materials Research, 28(9):1254–1261, 2013.

[30] I Theodorakos, F Zacharatos, R Geremia, D Karnakis, and I Zergioti. Selective laser sintering
of Ag nanoparticles ink for applications in flexible electronics. Applied surface science,
336:157–162, 2015.

[31] JS Kang, J Ryu, Hak-Sung Kim, and HT Hahn. Sintering of inkjet-printed silver nanoparticles
at room temperature using intense pulsed light. Journal of electronic materials, 40(11):2268,
2011.

[32] Dana Weise, Kalyan Yoti Mitra, Peter Ueberfuhr, and Reinhard R Baumann. Effect of the
light spectrum of various substrates for inkjet printed conductive structures sintered with
In AIP Conference Proceedings, volume 1646, pages 101–105. AIP,
intense pulsed light.
2015.

[33] Josué JP Valeton, Ko Hermans, Cees WM Bastiaansen, Dirk J Broer, Jolke Perelaer, Ulrich S
Schubert, Gregory P Crawford, and Patrick J Smith. Room temperature preparation of con-
ductive silver features using spin-coating and inkjet printing. Journal of Materials Chemistry,
20(3):543–546, 2010.

[34] Harish Devaraj and Rajiv Malhotra. Scalable forming and flash light sintering of polymer-
supported interconnects for surface-conformal electronics. Journal of Manufacturing Science
and Engineering, 141(4), 2019.

[35] Yuxiao He, Chris Oakley, Premjeet Chahal, John Albrecht, and John Papapolymerou. Aerosol
Jet printed 24 GHz end-fire quasi-Yagi-Uda antenna on a 3-D printed cavity substrate. In 2017
International Workshop on Antenna Technology: Small Antennas, Innovative Structures, and
Applications (iWAT), pages 179–182. IEEE, 2017.

77

[36] Jolke Perelaer, Mark Klokkenburg, Chris E Hendriks, and Ulrich S Schubert. Microwave
flash sintering of inkjet-printed silver tracks on polymer substrates. Advanced Materials,
21(47):4830–4834, 2009.

[37] Jolke Perelaer, Robin Jani, Michael Grouchko, Alexander Kamyshny, Shlomo Magdassi, and
Ulrich S Schubert. Plasma and microwave flash sintering of a tailored silver nanoparticle
ink, yielding 60% bulk conductivity on cost-effective polymer foils. Advanced Materials,
24(29):3993–3998, 2012.

[38] Mohammad Abu Hasan Khondoker, Seong Cheol Mun, and Jaehwan Kim. Synthesis and
characterization of conductive silver ink for electrode printing on cellulose film. Applied
Physics A, 112(2):411–418, 2013.

[39] Yeon-Taek Hwang, Wan-Ho Chung, Yong-Rae Jang, and Hak-Sung Kim.

Intensive plas-
monic flash light sintering of copper nanoinks using a band-pass light filter for highly elec-
trically conductive electrodes in printed electronics. ACS applied materials & interfaces,
8(13):8591–8599, 2016.

[40] Michael Dexter, Zhongwei Gao, Shalu Bansal, Chih-Hung Chang, and Rajiv Malhotra. Tem-
perature, crystalline phase and influence of substrate properties in intense pulsed light sinter-
ing of copper sulfide nanoparticle thin films. Scientific reports, 8(1):1–14, 2018.

[41] Hyun-Jun Hwang, Wan-Ho Chung, and Hak-Sung Kim.

In situ monitoring of flash-light
sintering of copper nanoparticle ink for printed electronics. Nanotechnology, 23(48):485205,
2012.

[42] Alexander O Govorov and Hugh H Richardson. Generating heat with metal nanoparticles.

Nano today, 2(1):30–38, 2007.

[43] Daniel Tobjörk, Harri Aarnio, Petri Pulkkinen, Roger Bollström, Anni Määttänen, Petri Iha-
lainen, Tapio Mäkelä, Jouko Peltonen, Martti Toivakka, Heikki Tenhu, et al. IR-sintering of
ink-jet printed metal-nanoparticles on paper. Thin solid films, 520(7):2949–2955, 2012.

[44] Hyun-Jun Hwang and Rajiv Malhotra. Shape-tuned junction resistivity and self-damping
dynamics in intense pulsed light sintering of silver nanostructure films. ACS applied materials
& interfaces, 11(3):3536–3546, 2018.

[45] Jennifer A Byford, Christopher Oakley, and Premjeet Chahal. Additively Manufactured Fre-
quency Selective Structures on Curved Surfaces. In 2018 48th European Microwave Confer-
ence (EuMC), pages 671–674. IEEE, 2018.

[46] Bruce King and Mike Renn. Aerosol Jet direct write printing for mil-aero electronic applica-

tions. In Lockheed Martin Palo Alto Colloquia, Palo Alto, CA, 2009.

[47] Christopher Oakley and Premjeet Chahal. Aerosol jet printed quasi-optical terahertz compo-

nents. IEEE Transactions on Terahertz Science and Technology, 8(6):765–772, 2018.

[48] Hui-Ju Chan, Bo-Cin Huang, Li-Wen Wang, Kuan-Hsun Liao, and Cheng-Yao Lo. Porosity
reduction in inkjet-printed copper film by progressive sintering on nanoparticles. Thin Solid
Films, 627:33–38, 2017.

78

[49] PS Liu, TF Li, and C Fu. Relationship between electrical resistivity and porosity for porous

metals. Materials Science and Engineering: A, 268(1-2):208–215, 1999.

[50] Sung-Jun Joo, Sung-Hyeon Park, Chang-Jin Moon, and Hak-Sung Kim. A highly reliable
copper nanowire/nanoparticle ink pattern with high conductivity on flexible substrate pre-
pared via a flash light-sintering technique. ACS applied materials & interfaces, 7(10):5674–
5684, 2015.

[51] Christopher Lefky, Avinash Mamidanna, Yiwen Huang, and Owen Hildreth. Impact of sol-
vent selection and temperature on porosity and resistance of printed self-reducing silver inks.
physica status solidi (a), 213(10):2751–2758, 2016.

[52] M Dexter, R Bhandari, CH Chang, and Rajiv Malhotra. Controlling processing tempera-
tures and self-limiting behaviour in intense pulsed sintering by tailoring nanomaterial shape
distribution. RSC advances, 7(89):56395–56405, 2017.

[53] Eerik Halonen, Tanja Viiru, Kauko Ostman, Ana Lopez Cabezas, and Matti Mantysalo. Oven
sintering process optimization for inkjet-printed Ag nanoparticle ink. IEEE Transactions on
Components, Packaging and Manufacturing Technology, 3(2):350–356, 2012.

[54] Jiri Matyas, Lukas Munster, Robert Olejnik, Karel Vlcek, Petr Slobodian, Petr Krcmar, Pavel
Urbanek, and Ivo Kuritka. Antenna of silver nanoparticles mounted on a flexible polymer
substrate constructed using inkjet print technology. Japanese Journal of Applied Physics,
55(2S):02BB13, 2016.

[55] Richard Allen Matula. Electrical resistivity of copper, gold, palladium, and silver. Journal of

Physical and Chemical Reference Data, 8(4):1147–1298, 1979.

[56] A Sheidaei, M Baniassadi, M Banu, P Askeland, M Pahlavanpour, Nick Kuuttila, F Pour-
boghrat, LT Drzal, and H Garmestani. 3-D microstructure reconstruction of polymer nano-
composite using FIB–SEM and statistical correlation function. Composites Science and Tech-
nology, 80:47–54, 2013.

[57] Gregor Neusser, Stefan Eppler, J Bowen, Chris J Allender, Paul Walther, Boris Mizaikoff, and
Christine Kranz. FIB and MIP: understanding nanoscale porosity in molecularly imprinted
polymers via 3D FIB/SEM tomography. Nanoscale, 9(38):14327–14334, 2017.

[58] CR Perrey, CB Carter, JR Michael, PG Kotula, EA Stach, and VR Radmilovic. Using the

FIB to characterize nanoparticle materials. Journal of microscopy, 214(3):222–236, 2004.

[59] Cristina Gaspar, Soile Passoja, Juuso Olkkonen, and Maria Smolander.

IR-sintering effi-
ciency on inkjet-printed conductive structures on paper substrates. Microelectronic Engi-
neering, 149:135–140, 2016.

[60] Stratasys. Vero: A Realistic Multi-Color 3D Printing Material, 2019.

[61] Marvin Abt, Aljoscha Roch, Jubaid A Qayyum, Svenja Pestotnik, Lukas Stepien, Atef Abu-
Ageel, Brian Wright, Ahmet Cagri Ulusoy, John Albrecht, Lee Harle, et al. Aerosol-printed
highly conductive Ag transmission lines for flexible electronic devices. IEEE Transactions
on Components, Packaging and Manufacturing Technology, 8(10):1838–1844, 2018.

79

[62] D Dutta, RA Weiss, and K Kristal. Blends containing liquid crystalline polymers: Prepara-
tion and properties of melt-drawn fibers, unidirectional prepregs, and composite laminates.
Polymer composites, 13(5):394–401, 1992.

[63] Bryan B Sauer, Richard Beckerbauer, and Lixiao Wang. Thermally stimulated current and
DSC studies of the broadened glass transition in liquid crystalline polymers. Journal of
Polymer Science Part B: Polymer Physics, 31(12):1861–1872, 1993.

[64] Oscar Azucena, Joel Kubby, Derek Scarbrough, and Chuck Goldsmith.

Inkjet printing of

passive microwave circuitry. pages 1075–1078, 2008.

[65] William MacNeill, Chang-Ho Choi, Chih-Hung Chang, and Rajiv Malhotra. On the self-
damping nature of densification in photonic sintering of nanoparticles. Scientific reports,
5:14845, 2015.

[66] Tao Li, Jie Hou, Jinli Yan, Rulin Liu, Hui Yang, and Zhigang Sun. Chiplet heterogeneous

integration technology—status and challenges. Electronics, 9(4):670, 2020.

[67] John U Knickerbocker, R Budd, B Dang, Q Chen, E Colgan, LW Hung, S Kumar, KW Lee,
M Lu, JW Nah, et al. Heterogeneous integration technology demonstrations for future health-
care, IoT, and AI computing solutions. In 2018 IEEE 68th electronic components and tech-
nology conference (ECTC), pages 1519–1528. IEEE, 2018.

[68] Ming-Fa Chen, Fang-Cheng Chen, Wen-Chih Chiou, and CH Doug. System on integrated
chips (SoIC (TM) for 3D heterogeneous integration. In 2019 IEEE 69th Electronic Compo-
nents and Technology Conference (ECTC), pages 594–599. IEEE, 2019.

[69] Subramanian S Iyer. Heterogeneous integration for performance and scaling. IEEE Transac-

tions on Components, Packaging and Manufacturing Technology, 6(7):973–982, 2016.

[70] RJ Gutmann, AY Zeng, S Devarajan, JQ Lu, and K Rose. Wafer-Level Three-Dimensional
Monolithic Integration for Intelligent Wireless Terminals. JSTS: Journal of Semiconductor
Technology and Science, 4(3):196–203, 2004.

[71] Rao R Tummala et al. Fundamentals of microsystems packaging. 2001.

[72] V. Gjokaj, J. Papapolymerou, J. D. Albrecht, B. Wright, and P. Chahal. A Compact receive
module in 3D printed Vivaldi antenna. IEEE Transactions on Components, Packaging and
Manufacturing Technology, pages 1–1, 2019.

[73] V. Gjokaj, C. Crump, J. Papapolymerou, J. Albrecht, and P. Chahal. Vivaldi antenna array
fabricated using a hybrid process. In 2019 IEEE 69th Electronic Components and Technology
Conference (ECTC), pages 948–953, May 2019.

[74] V. Gjokaj, P. Chahal, J. Papapolymerou, and J. D. Albrecht. A novel 3d printed vivaldi an-
tenna utilizing a substrate integrated waveguide transition. In 2017 IEEE International Sym-
posium on Antennas and Propagation USNC/URSI National Radio Science Meeting, pages
1253–1254, July 2017.

80

[75] Michael Thomas Craton, Xenofon Konstantinou, John D Albrecht, Premjeet Chahal, and
John Papapolymerou. A chip-first microwave package using multimaterial aerosol jet print-
ing. IEEE Transactions on Microwave Theory and Techniques, 2020.

[76] Akhilesh Kumar Singh, Nishant Lakhera, and Chee Seng Foong. Hybrid package, January 9

2020. US Patent App. 16/030,108.

[77] G Aspar, B Goubault, O Lebaigue, JC Souriau, G Simon, L Di Cioccio, and Y Bréchet. 3D
printing as a new packaging approach for MEMS and electronic devices. In 2017 IEEE 67th
Electronic Components and Technology Conference (ECTC), pages 1071–1079. IEEE, 2017.

[78] Salman Akram, David R Hembree, and Warren M Farnworth. Micromachined chip scale

package, June 6 2000. US Patent 6,072,236.

[79] Min-Chih Hsuan and Cheng-Te Lin. Multi-chip chip scale package, May 29 2001. US Patent

6,239,367.

[80] Osamu Suzuki. Recent advances in underfill for new package architectures. In 2020 Pan

Pacific Microelectronics Symposium (Pan Pacific), pages 1–7. IEEE, 2020.

[81] Constantine A Balanis. Antenna theory: analysis and design. John wiley & sons, 2016.

[82] Takuro Tajima, Ho-Jin Song, Makoto Yaita, Katsuhiro Ajito, and Naoya Kukutsu. 300-GHz
LTCC horn antennas based on antenna-in-package technology. In 2013 European Microwave
Conference, pages 231–234. IEEE, 2013.

[83] Takuro Tajima, Ho-Jin Song, Katsuhiro Ajito, Makoto Yaita, and Naoya Kukutsu. 300-GHz
step-profiled corrugated horn antennas integrated in LTCC. IEEE Transactions on antennas
and propagation, 62(11):5437–5444, 2014.

[84] DuPont. CYCLOTENE* 3000 Series Advanced Electronic Resins, 2019.

[85] L. Marigo-Lombart, C. Viallon, A. Rumeau, A. Arnoult, A. Lecestre, L. Mazenq, A. Ghan-
nam, H. Thienpont, K. Panajotov, and G. Almuneau. Electro-absorption modulator vertically
integrated on a vcsel: Microstrip-based high-speed electrical injection on top of a bcb layer.
Journal of Lightwave Technology, 37(15):3861–3868, 2019.

[86] Sandra Costanzo, Ignazio Venneri, Giuseppe Di Massa, and Antonio Borgia. Benzocy-
clobutene as substrate material for planar millimeter-wave structures: dielectric characteri-
zation and application. Journal of Infrared, Millimeter, and Terahertz Waves, 31(1):66, 2010.

[87] F. Cai, S. Pavlidis, J. Papapolymerou, Y. H. Chang, K. Wang, C. Zhang, and B. Wang. Aerosol
jet printing for 3-d multilayer passive microwave circuitry. In 2014 44th European Microwave
Conference, pages 512–515, 2014.

[88] J. Wu, R. Pike, C. P. Wong, D. Scheck, W. B. Rogers, and P. Garrou. Evaluation of the
environmental protection of photo bcb polymers (cyclotene/sup tm/ 4000). In Proceedings
International Symposium on Advanced Packaging Materials Processes, Properties and Inter-
faces (Cat. No.00TH8507), pages 90–96, 2000.

81

[89] T.M. Stokich, C.C. Fulks, M.T. Bernius, D.C. Burdeaux, P.E. Garrou, and R.H. Heistand.
Planarization with Cyclotene™ 3022 (BCB) polymer coatings. MRS Proceedings, 308:517,
1993.

[90] Cameron Crump, Vincens Gjokaj, Brian Wright, John Papapolymerou, John D Albrecht, and
Premjeet Chahal. UV Flash Sintering of Aerosol Jet Printed Silver Conductors for Microwave
IEEE Transactions on Components, Packaging and Manufacturing
Circuit Applications.
Technology, 2020.

[91] Shweta Agarwala, Guo Liang Goh, and Wai Yee Yeong. Optimizing aerosol jet printing
process of silver ink for printed electronics. In IOP Conference Series: Materials Science
and Engineering, volume 191, page 012027. IOP Publishing, 2017.

[92] Christopher Oakley, John D Albrecht, John Papapolymerou, and Premjeet Chahal. Low-
loss aerosol-jet printed wideband interconnects for embedded devices. IEEE Transactions on
Components, Packaging and Manufacturing Technology, 9(11):2305–2313, 2019.

82