POWER-AREA EFFICIENT RAPID-RESPONSE CMOS FRONTEND FOR HIGHTHROUGHPUT ION-CHANNEL SENSOR ARRAY MICROSYSTEMS
By
Sina Parsnejad

A THESIS
Submitted to
Michigan State University
in partial fulfillment of the requirements
for the degree of
Electrical Engineering – Master of Science
2017

ABSTRACT
POWER-AREA EFFICIENT RAPID-RESPONSE CMOS FRONTEND FOR HIGHTHROUGHPUT ION-CHANNEL SENSOR ARRAY MICROSYSTEMS
By
Sina Parsnejad
From the dawn of the nineteenth’s century, pioneers such as Faraday have been studying
the effects and consequences of charge transfer on chemical reactions. This field is now widely
recognized as electrochemistry. The fact that thanks to electrochemistry tracking a reaction and
imposing one has become so feasible has spawned a new wave of electrochemical enabled sensors
for various applications from personal health tracking to mine safety monitoring. The next logical
leap for electrochemical sensing would be to expand to single molecule detection and control.
However, fundamental limiting factors in electrochemistry such as probe size and noise impose
restrictions on the number of individual tracked molecules. One way to mitigate this issue is
through the use of nano-sized holes that allow for the target molecule to pass through them called
nano-pores. This dissertation discusses the principals of nano-pore sensing with a focus on
interfacing requirements and principals and provide the reader with a solution for interfacing ionchannels (a sub-category of nano-pores) in an array form. The goal is to understand the conditions
that would facilitate proper detection and the CMOS approach that would help us do so. Section 1
will focus on varieties of nano-pores and the definition and operation principals of ion-channels.
Section 2 will focus on challenges interfacing these ion-channels and solutions from literature.
Section 3 will focus on an array challenges implementing an array of ion-channels and provide
unique solutions. Chapter 4 describes a test chip implemented to test the solution proposed in
chapter 3 and provide users with test results supporting our claims.

Dedicated to my adorable nieces Anil, Sevilay and Lara.

iii

TABLE OF CONTENTS

LIST OF TABLES ....................................................................................................................... vi
LIST OF FIGURES .................................................................................................................... vii
1.

Introduction to nano-pore sensing ....................................................................................... 1
1.1. The definition of nano-pores and their significance literature ......................................... 1
1.2. Nano-pore types and introduction to ion-channels .......................................................... 2
1.3. Challenges in ion channel based sensing ......................................................................... 5
1.4. Thesis goals, planned contributions ................................................................................. 6
1.5
Thesis outline ................................................................................................................... 6

2.

Ion-channels structure and sensing methods ...................................................................... 7
2.1. Interfacing ion-channels ................................................................................................... 7
2.1.1. Tethering mechanisms for studying ion-channels .................................................... 7
2.1.2. Methods for studying ion-channels ........................................................................... 9
2.2. Electrochemical modeling and instrumentation of ion-channels ................................... 10
2.3. Nano-pore and ion-channel instrumentation and challenges ......................................... 12
2.3.1. Amperometric sensing with nano-pores ................................................................. 12
2.3.2. Noise limitations in amperometric interfacing of nano-pores ................................ 13
2.3.3. Other limitations for amperometric sensing ........................................................... 17
2.4. Multichannel nano-pore arrays....................................................................................... 17
2.5. CMOS instrumentation for ion-channel sensing ............................................................ 19
2.6. High throughput array implementation, opportunities and challenges .......................... 21
2.7. Conclusion...................................................................................................................... 23

3.

A CMOS current amplifier for high throughput ion-channel arrays ............................ 24
3.1. An array solution for ion-channel sensing ..................................................................... 24
3.2. Noise limitations for interfacing ion-channels ............................................................... 26
3.3. Area and power limitations for interfacing a high throughput ion-channel arrays ........ 28
3.4. A CMOS current amplifier design ................................................................................. 28
3.4.1. Fundamental noise limitations of an op-amp .......................................................... 29
3.4.2. An op-amp sharing technique to address the area and power limitations of
interfacing high throughput ion channel arrays ..................................................................... 33
3.4.3. A low-noise compact feedback Structure ............................................................... 40
3.5. A shared amplifier topology for optimum area usage .................................................... 43

4.

Evaluation of current amplifier performance................................................................... 47
4.1. CMOS test chip contents and functionalities ................................................................. 47
4.2. A testing platform for the extremely sensitive instrumentation circuit.......................... 49
4.3. Test results...................................................................................................................... 51
4.4. Conclusion...................................................................................................................... 59

iv

5.

Summary and Future work ................................................................................................ 60
5.1. Summary ........................................................................................................................ 60
5.2. Contribution ................................................................................................................... 60
5.3. Future work .................................................................................................................... 61

REFERENCES ............................................................................................................................ 62

v

LIST OF TABLES

Table 1 the input sinusoidal range for various isolation capacitances .......................................... 51
Table 2 Comparison of the state of art pore interface circuit performance. ................................. 58

vi

LIST OF FIGURES

Figure 1-1 Typical BLM populated with various membrane proteins source. ............................... 3
Figure 1-2 Solid-state nano-pore fabricated on a silicon substrate. ................................................ 4
Figure 2-1 Conceptual illustration of patch-clamp ion channel tethering. ..................................... 8
Figure 2-2 Synthetic BLM containing an ion channel formed over artificial beams presented in
[26]. ................................................................................................................................................. 9
Figure 2-3 Example current response of an ion channel............................................................... 11
Figure 2-4 A standard TIA structure with a resistive and capacitive feedback interfacing a
standard electrical model for an ion channel ................................................................................ 13
Figure 2-5 A classic TIA amplifier with resistive feedback and all possible noise sources. The
terms iIN and vOUT represent the input-referred and output total noise. ........................................ 14
Figure 2-6 Noise spectrum and the contributing elements obseved with nano-pore interface
circuits adapted from [36]............................................................................................................. 16
Figure 2-7 Capacitive interfacing of amperometric current using reseting switches adapted from
[58]. ............................................................................................................................................... 21
Figure 3-1 An array of BLMs implemented over pixels adjacent to a microfluidic chamber built
on a CMOS chip for direct readout of the ion channel incidents with minimal noise .................. 26
Figure 3-2 3D view of the proposed pixels for the proposed lab-on-CMOS concept .................. 28
Figure 3-3 Local heating of pixels due to power consumed in the target pixel and it’s adjacent
pixels ............................................................................................................................................. 30
Figure 3-4 Noise sources influencing a typical amplifier circuit .................................................. 32
Figure 3-5 Pixel interfaces for nano-pore current sensing with (a) typical TIA structure and (b)
shared TIA structure ..................................................................................................................... 34
Figure 3-6 Shared op-amp structure circuitry and the corresponding op-amp elements .............. 35
Figure 3-7 Equivalent circuit structure for the internal feedback loop placed within shared
segment of proposed op-amp ........................................................................................................ 36
Figure 3-8 Proposed shared op-amp with only one gain stage and a negative feedback loop ..... 38

vii

Figure 3-9 Noise and interface sources of the proposed share op-amp structure ......................... 40
Figure 3-10 The implemented active feedback network for nano pore current interfacing ......... 42
Figure 3-11 The difference between having a single stage with a gain of 100 and having two
stages with two stages with a gain of 10 resulting in a total gain of 100...................................... 44
Figure 3-12 The topology in which pixel amplifiers would be implemented to interface a large
number of pixels ........................................................................................................................... 46
Figure 4-1 The fabricated test chip with all the various blocks implemented .............................. 48
Figure 4-2 The shared op-amp stages and how they are placed within the test chip .................... 49
Figure 4-3 The test configuration for input parasitic noise compensation ................................... 50
Figure 4-4 Test setup for input DC response test ......................................................................... 52
Figure 4-5 The circuit response to a DC input current ................................................................. 53
Figure 4-6 The circuit response to individual positive and negative stimulation ......................... 53
Figure 4-7 System frequency response to incoming input sinusoidal current at 1 kHz and 10 kHz
frequencies with and without input membrane capacitance ......................................................... 56
Figure 4-8 The pulsed input scheme for creating clean 10 pA pulse currents for feeding the
circuit ............................................................................................................................................ 57
Figure 4-9 The input pulse waveform recorded from channel 1 (ch1) and the system response to
the pulsed input current in channel 2 (ch2) ................................................................................... 58

viii

1. Introduction to nano-pore sensing
1.1.

The definition of nano-pores and their significance literature

Recently great research effort has been put into chemistry-enabled sensing systems such as
air pollutant detectors, biosensors for antibody detection as well as more complex emerging areas
such as silicon nano-wires [1] and carbon nano-tubes [2]. All these methods are subsets of a greater
family called electrochemical sensors. Electrochemical sensors utilize tracking and exploit charge
transfer in chemical reactions for discovering a sensing target. In recent years, new opportunities
for mainstream utilization of these techniques are emerging throughout the literature. For example,
electrochemical sensing has received a lot of attention in developing biosensors in the recent years
[3][4]. They are also being used in fields such as environmental sensing, safety monitoring and
clinical diagnosis in both stationary and portable systems. The popularity of electrochemical
sensors is due to reliability, simplicity, low cost, and portability of these systems [5].
Electrochemical bio-sensors are a subset that associate with and detect a biological event or a
marker using charge transfer. Amperometric electrochemical biosensors detect this event by
receiving the said charge through an electrode, and transducing it into a current signal.
The information retrieved from electrochemical biosensors is usually integrated over a
large number of charge transfers and integrated over time from individual electrodes [6]. This is
however, contrary to the growing demand for tracking the charge transfer of individual molecules
in a quantitative manner. This is not possible with traditional electrochemical systems due to the
fact that electrochemical electrodes form a layer of charge known as double layer capacitance on
their surface shared with the solution. This capacitance is noisy and thus masks the passing of low
doses of charge created by a single molecule electrochemical event [6].

1

To enable single molecule electrochemical detection, several methods have been proposed
including redox cycling, Nano-particles and nano-pores. A nano-pore is basically a nano-scale
sized path for charged or neutral particle transfer with well-defined flow characteristics [7]. The
operation principles of nano-pores revolve around the fact that an open pore can demonstrate
constant ion flow under the right circumstances and any disruption to this flow would be
detectable. One way to utilize this configuration for detecting particles is to observe the changes
in charge flow through the nano-pore due to the presence of particles with certain sizes.
Furthermore, this method can also be utilized to observe the behavior of the nano-pore under
certain environmental and internal stimulation conditions, enabling characterization of the pore.
Nano-pores have been reported for use in fields including single molecule bio-sensing and protein
detection and ultrafast label free DNA sequencing [8][9] as well as more specific aplications such
as detection of microRNAs [10], measurement of molecular forces [11] and identifying Anthrax
toxins [12]. As the demand to bring these technologies to the mainstream advances, there is a
growing need for better understanding of nano-pores and their interfacing circuitry. The next
sections of this chapter discuss the structure of nano-pores, especially ion-channel proteins, and
overview some of the challenges in developing electronic interfaces for nano-pores.

1.2.

Nano-pore types and introduction to ion-channels

Two main types of nano-pores are currently being used for amperometric measurements: ionchannels and solid-state nano-pores. The first practical implementation of nano-pores was
detection of single stranded DNA molecules by passing them through a staphylococcal Îąhaemolysin ion-channel protein acting as a nano-pore gate [13]. An ion channel is a pore-forming
membrane protein that form on cell’s bilayer lipid membrane (BLM). A BLM is a continuous sheet
that forms a barrier around the cell and is populated with membrane proteins that are responsible

2

for communication with the outside world. A typical BLM populated by various membrane
proteins where each is performing a specific function is depicted in Figure 1-1. The bulk of BLM
is composed of amphiphilic phospholipids that are hydrophilic on one tail and hydrophobic on the
other side. Accompanying these cells are the membrane proteins that are anchored to the surface
and perform various tasks. Ion channels are one class of membrane protein, and they are the
fundamental excitable elements in most cell

jobs include establishing a resting membrane

potential and enabling action potentials by gating ions through the BLM. Thus, they are
responsible for regulating cell volume and controlling ion flow across secretory and epithelial
cells. Due to their rich history and ease of implementation, ion-channels are going to be the main
focus of the presented thesis. Further details about the principals of sensing using ion-channels
will be discussed in the coming chapters.

Bilayer Lipid Membrane (BLM)

Various other BLM proteins

Ion channel

Figure 1-1 Typical BLM populated with various membrane proteins source.
Solid-state nano-pores are another approach to nano-pore sensing. Due to recent
advancements in microfabrication techniques, it is possible to implement micro-fabricated solidstate pores with nano-meter sized openings. An example of a nano-pore created on a silicon nitride
3

surface is discussed in [14] and shown in Figure 1-2. These pores are typically implemented in
dielectric materials such as glass, silicon dioxide (SiO2), silicon nitride (Si3N4) and polymers [15]
and shown in Two example methods for creating these openings are ion-bean sculpting to create
pores at a Si3N4 substrate [16] and implementation of precise nano-pores in a SiO2 substrate by
shrinking a large hole (~20 nm – 200 nm) to single nano-meter precision using the surface tension
created by high energy electron beam together with a visual feedback [17]. In terms of electrical
properties and performance, there is not much difference between an ion channel and a microfabricated pore. Thus, throughout this chapter, the term nano-pores will generally refer to either of
these structures.

Figure 1-2 Solid-state nano-pore fabricated on a silicon substrate.

Ion-channels have been receiving a lot of attention within the last two decades [18]. It is
worth stating that 15% of world’s 100 top selling drugs target ion-channels [5]. Serious research
is being put into turning such ion-channels into sensor modules due to them being capable of
providing sensing continuously and label free with electrochemical techniques [19]. There are
various instances of research is being conducted using ion-channels as a mean of sensing. [20] and
4

[21] are examples of efforts to utilize ion-channels on BLMs. Hence, the presented dissertation
will primarily focus on methods for utilization and instrumentation of ion-channels.

1.3.

Challenges in ion channel based sensing

Nano-pores transduce bio/chemical events into variations in ionic current flow that can
vary in magnitude depending on factors such as the pore dimensions, viscosity of the analytes,
capacitances stemming from the isolating layers or the electrodes, etc. Typically these ionic
currents have an amplitude in pA region with timing characteristics, e.g. pulse width, as short as
tens of microseconds. This imposes stringent limitations on the nano-pore interface system since
the noise floor should at least be 10 dB lower than the signal level for it to be detectable. Hence a
typical noise floor of fA levels is required for effective nano-pore sensing. For example, sodium
ion channels typically have a conductance of 100 pS resulting in a current in the order of 10 pA
when excited with a biasing voltage of 100 mV. As a result, they require a root-mean-square (r.m.s)
noise level of less than 100 fA in a 1 kHz bandwidth [22]. Another example is a micro-fabricated
glass and polyethylene terephthalate membrane that demonstrates an r.m.s. noise ranging from 5
pA to 25 pA, depending on membrane resistance, at a bandwidth of 40 kHz [23]. The benchmark
instrument for current sensing in electrophysiology is the Axon Axopatch 200B, which provides a
noise floor of 25 fA r.m.s. at 1 kHz frequency (0.7 fA/√Hz until 1 kHz) [22]. However, this device
is bulky, expensive and designed for specific lab environments and experienced users. The limited
existing instrumentation has created an obstacle for the development of nano-pores sensor that
exploit their capabilities for precision measurement and single-molecule detection. However, as
discussed in the next section of this chapter, recent advancements in CMOS technology and
microfabrication techniques have enabled the opportunity to utilize custom CMOS circuitry for

5

high-speed, low-noise, and cost effective customizable alternatives to interfacing with nano-pore
sensors.

1.4.

Thesis goals, planned contributions

The goals of this dissertation revolve around solutions for characterization of ion-channels
and sensing ion-channel events with a focus on addressing the challenge of facing interfacing these
ion channels through CMOS design. To drive this point home, through dissertation ion channel
working principals and conditions, methods of utilizing these ion-channels from a physical and
structural point of view, and the most effective readout methods will be studied. Scientific
contributions are expected in the area of electrochemical instrumentation of ion-channels.

1.5.

Thesis outline

Chapter 2 will focus on interfacing principals of ion-channels. Their electrochemical model
and popular CMOS interfacing mechanisms will be discussed. Utilizing ion-channels in an array
format as well as the CMOS challenges of interfacing ion channels will be focused on. Chapter 3
reports a unique solution for the CMOS challenges of interfacing high counting arrays of ionchannels with a focus on noise, area and power consumption. Chapter 4 will focus on a CMOS
chip built to test the ideas presented in chapter 3 and provide the reader with detailed explanation
of our testing methods and results to support any claims made. Chapter 5 presents contribution and
future work.

6

2. Ion-channels structure and sensing methods
The following section dives into details about physical methods which ion-channels are
being implemented and studied. This would entail the methods in which ion-channels are
physically utilized in a sensing environment. This is a challenge because ion channels are nanometer sized proteins that would require a surface or an isolating layer to operate. Later, some of
the non-electrochemical methods that use ion-channels will be briefly discussed. Sections 2.2 &
2.3 will discuss electrochemical properties of ion-channels and discuss the possibility of using
them in an array format. Section 2.4 will give a brief glimpse into the CMOS challenges of
interfacing ion-channels and conduct a literature research on works trying to solve this issue.

2.1.

Interfacing ion-channels

2.1.1. Tethering mechanisms for studying ion-channels
Studying ion-channels in a physical format would obviously require the investigator to
physically have access to the BLM layer. After all, ion-channels are only viable when operating
along an isolating layer which is usually a BLM. Hence, in order to study ion-channel functionality
the researchers need to bring the sensing equipment to the living BLM surface. Thus there is a
need for proper tethering mechanism for studying ion-channels and other membrane proteins.
There are two prominent methods of doing so, patch-clamp and synthetic BLM. The patch-clamp
method is shown in Figure 2-1. As indicated, a small heat-polished pipette is pressed against the
BLM containing an ion-channel. The glass edges and the cell membrane form an isolating layer
with a resistance of the order of 50 MΩ effectively building a “patch” [24]. The seal restricts ion
flow across BLM only through the ion-channels located inside the seal. Despite patch-clamp being
one of the easiest and most implemented methods for studying BLM since 1970s, there are major

7

drawbacks to this method such as lack of control over captured protein and lipid composition and
being extremely laborious and slow.

Electrode
Micro-pippet
Ion channel
Cell membrane

Figure 2-1 Conceptual illustration of patch-clamp ion channel tethering.
As shown in Figure 2-2, an alternative method of tethering ion-channels is forming a
synthetic membrane over a nano-sized chamber containing a controlled number target membrane
proteins, or in this case only ion-channels[25]. Synthetic BLMs have a simple structure and welldefined electrical characteristics. There are certain drawback to this method as well. Chances of
forming a fully sealed and operative BLM with the desired number of ion-channels are currently
very low [26].

8

Figure 2-2 Synthetic BLM containing an ion channel formed over artificial beams
presented in [26].

2.1.2. Methods for studying ion-channels
There are various ways of integrating biological sensors. It is possible to classify these
methods into four categories of electrochemical, optical, mechanical, and magnetic. Since the main
duty of ion-channels is transporting ions across membrane and detecting an event when this ion
flow is interrupted, electrochemical measurement methods are preferred for interfacing ionchannels. This is due to the fact that electrochemistry revolves around observing and measuring
electric charges that may be produced by a chemical reaction or are readily available in the solution
delivered to an electrode [27]. Optical methods utilize light based techniques such as Surface
plasmon [28] [29], fluorescence and ELSIA [30]. Mechanical methods include using quartz
crystals [30] microbalance and resonant cantilever [29]. Magnetic methods use magnetic particles
as elements of sensing as discussed in [31]. The discussions in this theses will be conducted over
electrochemical sensing.

9

2.2.

Electrochemical modeling and instrumentation of ion-channels

Electrochemical sensing measures changes in current (amperometry and voltammetry),
voltage (potentiometry), and impedance resulting from a chemical reaction that either transfers or
separates electric charge with reasonable selectivity and sensitivity [27]. Among these methods
Amperometric sensors measure a current that is proportional to the concentration of the analytes
available. Hence, amperometric method is a perfect solution for characterizing the actions of an
ion-channel passing ion active analytes from one isolated chamber to another.
It is entirely possible to estimate the electrical behavior of a conducting ion channel as
electrical components even though the component values would vary based on the overall nanopore working conditions. The electrical model is valuable for understanding the basic behavior of
ion channels under a given input voltage. The circuit equivalent of an ion channel implanted on a
membrane is shown in Figure 2-3 (left). The parallel capacitance and resistance depicts a low-pass
filter-like operation with a time constant of RchCM, where Rch represents the voltage-current
behavior of the channel and CM represents the capacitance of the exposed cell membrane area.
Based on empirical evidence, CM has a typical capacitance of 1 ÂľF/cm2 if the target nano-pore is
an ion-channel with a typical BLM structure [32].
A model for the voltage to current relationship of the conducting ion channel shown in Fig.
2.1 under equilibrium conditions is given by Figure 2-3 under equilibrium conditions is given by
[32].
𝐼𝐼𝑖𝑖𝑖𝑖𝑖𝑖 = 𝑔𝑔𝑐𝑐ℎ (𝐸𝐸 − 𝐸𝐸𝑖𝑖𝑖𝑖𝑖𝑖 )

(2-1)

where Ipore is the total ionic current passing through the nano-pore under a given input voltage of
E, gion is the total channel conductance and Epore is the equilibrium potential of the conducting

10

nano-pore. By definition, if the nano-pore is conducting only a certain type of ion, Epore would be
the total voltage gradient created inside the nano-pore due to the presence of ions passing through
it, i.e. if the net voltage over the nano-pore is Epore then the flux of ions through the pore will be
zero. Notice that (2-1) only represents the equilibrium state of nano-pore operation and does not
factor in the time constant RchCM. Furthermore the current-voltage relationship of nano-pores is
non-linear. For example, in case of an ion-channel, the relationship is affected by variables such
as diffusion currents due to higher concentration of permanent ions on one side of the pore.
The current response of a typical ion channel on a synthetic BLM layer formed on a silicon
structure is depicted in Figure 2-3 (top). Depending on the membrane size and type as well as the
electrolyte conditions, ion channel event responses may vary in amplitude from ~1 pA to 200 pA
with an offset depending on the aperture size and other environmental variables. For ion channels,
the incident pulse length can be anywhere between 1 Âľs to 1 ms [33], and the incidents generally
occurs in a pulse-like format that indicates the opening and closing events of the ion channel or
particle passing through. The analog interface for ion-channel incidents must have proper
performance characteristics to accurately measure such fast changing and small amplitude signals.

A

~10Âľs
~10ps

Rch
CM
Epore

Figure 2-3 Example current response of an ion channel.

11

2.3.

Nano-pore and ion-channel instrumentation and challenges

2.3.1. Amperometric sensing with nano-pores
One of the most prevalent electrochemical detection methods is amperometry. First used
in ion chromatography, amperometry is accomplished in the presence of a target analyte by
applying a voltage between a working and auxiliary (reference) electrode in a two electrode system
or a working and reference electrode in a three electrode system. The response is signified by a
current that passes through the working electrode. This current is directly proportional to the mole
concentration of the analyte oxidized or reduced on the electrode surface at a given input voltage,
as described by Faraday’s law [34]:
𝑖𝑖𝑡𝑡 =

𝑑𝑑𝑑𝑑
𝑑𝑑𝑑𝑑

= 𝑛𝑛𝑛𝑛

𝑑𝑑𝑑𝑑
𝑑𝑑𝑑𝑑

(2-2)

where it is the current generated at the working electrode surface at the time t, Q is the charge
stored at the electrode surface in form of a double layer capacitance, t is time, n is the number of
electrons transferred per mole of analyte, N is the number of moles of analyte oxidized or reduced,
and F is the Faraday constant (96 485.33 C/mol). In a normal electrochemical reaction, selectivity
is achieved through selection of an input voltage that causes oxidation or reduction of different
target analytes.
Performing amperometry in nano-pores is slightly different from the normal process in that
the input voltage between the working and reference electrodes does not aim to oxidize or reduce
analytes. Rather, this voltage is used to facilitate the electrostatic transportation of ions through
the nano-pore. For some ion-channels, this voltage may also impact the behavior of the pore, for
example the open or closed state of a voltage-gated channel. Regardless, the basic amperometry
function is the same: measure a response current at a given working electrode potential. Thus, the
working electrode is usually connected to a buffer state that performs two fundamental actions: it
12

controls the voltage on working electrode through a feedback loop and converts the Faraday
response current into an electrically viable signal.
The most widely used amperometric readout circuit is a trans-impedance amplifier (TIA).
A TIA consists of a standard operational amplifier with a negative feedback element that regulates
the negative input of the operational amplifier without saturating the op-amp output voltage. The
most commonly used feedback element is a resistor in parallel with a capacitor for stability. Thus,
the output voltage to input current ratio would be equal to (–R). TIAs are widely used as
amperometric sensor interfaces due to their simplicity, linearity and input-output voltage isolation
[35]. Figure 2-4 depicts a standard TIA structure with a resistive and capacitive feedback
interfacing to an equivalent nano-pore circuit model. This model will be used as the basis for noise
discussion below.

Figure 2-4 A standard TIA structure with a resistive and capacitive feedback interfacing a
standard electrical model for an ion channel.

2.3.2. Noise limitations in amperometric interfacing of nano-pores
The amperometric current produced by a nano-pore is small and has a short duration. The
bandwidth required for the interface circuit to be able to capture these fast transitioning signals
spans from DC to hundreds of kHz. Thus, the interface circuit is susceptible to both low frequency

13

noise element such as flicker noise as well as high frequency noise elements. Consequently, the
interface circuit must demonstrate exemplary noise performance.
The ideal input-output relationship of the resistive and capacitive feedback shown in
Figure 2-5 can be expressed as:
𝑅𝑅

𝐹𝐹
𝑣𝑣𝑂𝑂𝑂𝑂𝑂𝑂 = − 1+𝑗𝑗2𝜋𝜋𝜋𝜋𝑅𝑅

𝐹𝐹 𝐶𝐶𝐹𝐹

× 𝑖𝑖𝐼𝐼𝐼𝐼

(2-3)

where Rf and Cf are the feedback elements, vOUT and iIN are the output and input elements of the
TIA and f is the system frequency. The feedback capacitance acts as a low-pass filter, ensuring
interface circuit stability in higher frequencies given the presence of an input capacitance CIN [35].
A detailed noise model of Figure 2-4 circuit is shown in Figure 2-5 where CIN represents the sum
of the equivalent nano-pore capacitance (CM from Figure 2-3) and any parasitic capacitance at the
input.

Figure 2-5 A classic TIA amplifier with resistive feedback and all possible noise sources.
The terms iIN and vOUT represent the input-referred and output total noise.
The total noise observed at the input, in-IN, is composed of three main elements:

14

2
�2 �2 ����
2
𝚤𝚤�������
𝑛𝑛−𝐼𝐼𝐼𝐼 = 𝚤𝚤𝐷𝐷 + 𝚤𝚤𝐹𝐹 + 𝚤𝚤𝑜𝑜𝑜𝑜

(2-4)

where 𝑖𝑖𝐷𝐷2 represents noise created by environmental elements and the sensor itself, 𝚤𝚤�2𝐹𝐹 represents

2
the noise created by the feedback loop and 𝑖𝑖𝑜𝑜𝑜𝑜
is the input-referred noise created by the op-amp
2
2 . For resistive feedback, the term 𝚤𝚤�
circuitry ����
𝑒𝑒𝑜𝑜𝑜𝑜
𝐹𝐹 can be written as:
4𝑘𝑘𝑘𝑘
𝚤𝚤�2𝐹𝐹 = 𝑅𝑅

(2-5)

𝐹𝐹

2
����������
where k is the Boltzmann constant and T is temperature in Kelvin. If 𝑣𝑣
𝑜𝑜𝑜𝑜−𝑜𝑜𝑜𝑜𝑜𝑜 the total output
2
voltage noise created by 𝑒𝑒����
𝑜𝑜𝑜𝑜 , it can be inferred that:
2 +4𝜋𝜋2 𝑓𝑓2 𝑅𝑅 2 𝑅𝑅 2 (𝐶𝐶 +𝐶𝐶 )2
𝐼𝐼𝐼𝐼
𝐹𝐹 𝐼𝐼𝐼𝐼 𝐹𝐹
2 2 2 2
𝐼𝐼𝐼𝐼 (1+4𝜋𝜋 𝑓𝑓 𝑅𝑅𝐹𝐹 𝑅𝑅𝐼𝐼𝐼𝐼 )

𝑍𝑍𝐹𝐹
(𝑅𝑅𝐼𝐼𝐼𝐼 +𝑅𝑅𝐹𝐹 )
2
���������
2
2
����
����
𝑣𝑣
𝑛𝑛−𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑒𝑒𝑜𝑜𝑜𝑜 × �1 + 𝑍𝑍 � = 𝑒𝑒𝑜𝑜𝑜𝑜 ×
𝑅𝑅 2
𝐼𝐼𝐼𝐼

(2-6)

where ZF and ZIN represent the total feedback and input impedance seen on the feedback loop and
input node, respectively. (2-6) can be simplified to:
(1+
2
���������
2
����
𝑣𝑣
𝑛𝑛−𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑒𝑒𝑜𝑜𝑜𝑜 ×

𝑅𝑅𝐹𝐹
2
�𝑅𝑅 )2 +4𝜋𝜋2 𝑓𝑓2 𝑅𝑅𝐹𝐹
(𝐶𝐶𝐹𝐹 +𝐶𝐶𝐼𝐼𝐼𝐼 )2
𝐼𝐼𝐼𝐼
2 𝑅𝑅 2
1+4𝜋𝜋 2 𝑓𝑓 2 𝑅𝑅𝐹𝐹
𝐼𝐼𝐼𝐼

(2-7)

where the term with RF⁄RIN dictates the interface circuit noise performance at lower frequencies.
Hence, a high input resistance is very beneficial to the interface circuit at lower frequencies. For
nano-pore interfaces, RIN can generally be assumed to be much greater than RF, which permits the
input-referred current noise generated by the op-amp to be expressed as:
������������
2

𝑣𝑣
2 = 𝑜𝑜𝑜𝑜−𝑜𝑜𝑜𝑜𝑜𝑜 = ����
2 × � 1 + (2𝜋𝜋𝜋𝜋)2 (𝐶𝐶 + 𝐶𝐶 )2 �
𝚤𝚤����
𝑒𝑒𝑜𝑜𝑜𝑜
𝑜𝑜𝑜𝑜
𝐹𝐹
𝐼𝐼𝐼𝐼
|𝑍𝑍 |2
𝑅𝑅 2
𝐹𝐹

𝐹𝐹

(2-8)

Thus, the total input referred noise at input IIN is:

1
2
2
2
�2 4𝑘𝑘𝑘𝑘 ����
2
𝚤𝚤�������
𝑛𝑛−𝐼𝐼𝐼𝐼 = 𝚤𝚤𝐷𝐷 + 𝑅𝑅 + 𝑒𝑒𝑜𝑜𝑜𝑜 × �𝑅𝑅 2 + (2𝜋𝜋𝜋𝜋) (𝐶𝐶𝐹𝐹 + 𝐶𝐶𝐼𝐼𝐼𝐼 ) �
𝐹𝐹

𝐹𝐹

(2-9)

The noise spectrum seen at the output of a typical TIA system interfacing with a nano-pore
is depicted in Figure 2.6 [36]. The flicker noise and dielectric loss are produced by the input
capacitance. The dielectric loss noise is due to thermal dissipation in lossy dielectric materials [36]

15

which has a direct correlation with frequency. The white noise and the capacitive noise are,
2 . The interface circuit bandwidth should be on the order of hundreds of
however, caused by ����
𝑒𝑒𝑜𝑜𝑜𝑜

kHz, which means that the capacitive noise created by the terms containing f2 will definitely hinder
the sensitivity of the interface circuit and is a common concern in the nano-pore interface circuit

Noise

literature [37].

f2

f
1/

f

White noise
Frequency

Figure 2-6 Noise spectrum and the contributing elements obseved with nano-pore interface
circuits adapted from [36].
Based on (2-9), the two best ways to solve the capacitive noise issue using a TIA are to
2
2
����
decrease 𝑒𝑒����
𝑜𝑜𝑜𝑜 or to decrease the overall capacitance seen at the TIA input. The term 𝑒𝑒𝑜𝑜𝑜𝑜 can be

improved by dedicating more circuit area and/or power to the TIA or using novel op-amp

techniques. Decreasing the capacitance can usually be achieved by system miniaturization.
Generally, miniaturization of sensor area and electrode dimensions is desirable because it reduces
the parasitic capacitances as well as the double layer capacitance formed on the electrode [37].

16

Furthermore, reducing sensor dimensions decreases the impact of electrolyte resistance on
amperometric instrument noise performance [27].

2.3.3. Other limitations for amperometric sensing
Noise performance is one of the main challenges to interfacing nano-pores, but other major
issues must also be addressed. One of the main issues is input offset currents. As mentioned before,
nano-pores monitor ionic current flow and variations in current due to the presence of target
molecules. The background ionic current can have constant or variable amplitude and can be as
much as 10× the amplitude of sensing event currents. This background current creates and input
offset that can challenge coherent sensing of the nano-pore event. Most modern amperometric
interface circuits utilize a TIA with capacitive feedback due to its simplicity, low use of hardware
resources, and good noise performance [37]. However, a large input offset can saturate a basic TIA
interface circuit. For example, a large input offset will force a switched-capacitor interface circuit
to dramatically increase its clock rate, compromising the SNR performance of the system.

2.4.

Multichannel nano-pore arrays

Due to recent advances in microfabrication and biological science techniques, a trend has
developed to use microarrays for parallel sensing [38][39]. These structures accelerate the
development time by quickly extracting valuable experimental data. Similarly, combining nanopores with microfluidic delivery systems offers great potential for enabling parallel recording of
biological signals. Integrated arrays are especially suitable for ion-channels formed on a BLM
structure due to their self-assembling nature that enables them to automatically form in designated
spots within a microfluidic system [40]. Parallel array implementation is also appealing to
overcome the inherently low yield in forming functional nano-pore interfaces, especially ionchannels. The patch-clamp extraction method for ion channels is very laborious and time

17

consuming with low odds of extracting the correct target ion channels. Even using synthetic BLMs,
the chances of successfully forming an interface with the desired number of functional ionchannels is very low [41]. Hence, a logical use for self-forming ion channel nano-pores would be
in the form of an array where a large number of nano-pore are implemented simultaneously,
increasing the odds of successful formation of ion-channels.
Electrically interfacing with arrays of nano-pore introduces a new set of design challenges
that need to be addressed. The works presented in [42] and [43] demonstrate parallel recording
functionality with very limited number of array channels and sub kHz bandwidth. These systems
are not able to detect single molecule events due to the plethora of parasitic capacitances and lack
of noise fine-tuning. These challenges could be overcome by integrating the sensing circuitry
within a microfluidic system containing the nano-pores through an approach dubbed lab-onCMOS [19]. Implementing array sensing by integrating CMOS interface circuitry in close
proximity of a nano-pore array system [44] can greatly reduce environmental and wiring noise.
However, this high level of integration sets severe limitations in terms of the power and area
consumed by the CMOS nano-pore interface circuitry. These limitations are thoroughly discussed
in [44] and [26] which seek to implement arrays of hundreds of ion-channel in a microfluidic
system implemented on the surface of a CMOS interface chip. In both these works, each nanopore is assigned to a pixel amplifier stage that is in very close physical proximity to mitigate the
effects of excessive input capacitance. As a results, the pixel amplifiers have very strict limitations
in terms of the area they consume. Furthermore, because this approach enables hundreds of pixel
amplifier stages right beneath (microns away from) the ion channel sensors, the potential for the
CMOS circuitry to heat or even thermally denature the nano-pores must be considered. As a result,
strict power consumption limitations must be met by the CMOS pixel circuitry.

18

2.5.

CMOS instrumentation for ion-channel sensing

The idea of implementing ion-channels in a self-assembled array format for parallel
sensing of multiple well-formed channels over very small pixels has been discussed so far. Despite
the enormous potential impact of such approach, there is no report of implementation of such idea
throughout the literature. This can be attributed to the physical challenges in interfacing such an
array of ion-channels. The primary issue is the fact that the ion-channel amperometric signal is
fast and has a low amplitude in a very noisy environment which is a departure from norms of
traditional electrochemistry. Based on our calculations the signal we are expecting to receive from
an ion-channel event is a pulse shaped signal with an amplitude of about 10 pA and a pulse-width
of 10 ÂľS. This would not be hard to address as is shown later in the literature review section.
However, the signal shape issue is corroborated by the fact that addressing this level of noise would
require a lot of resources which is not desirable in an array format implementation. Consequently,
the purpose of this work is to address the practical implementation of the suggested array of ionchannels from a CMOS standpoint addressing the noise limits of the interface in a resource limited
environment.
Although the development of interface circuits for both solid-state and ion-channel nanopores is a relatively new field of study [37], several prominent works have already been reported
in the literature with a focus on three main issues: offset cancelation, noise performance and array
implementation. Based on (2 9) there are only a few options for improving noise performance in a
classic TIA structure. However, many approaches have been reported to improve noise by stepping
away from the classic TIA structure. To begin analyzing these, let’s express (2 9) in a simplified
and more generalized form as:

19

1
2
2
2
�2 �2 ����
2
𝚤𝚤����
𝐼𝐼𝐼𝐼 = 𝚤𝚤𝐷𝐷 + 𝚤𝚤𝐹𝐹 + 𝑒𝑒𝑜𝑜𝑜𝑜 × �𝑅𝑅 2 + (2𝜋𝜋𝜋𝜋) (𝐶𝐶𝐼𝐼𝐼𝐼 ) �
𝐹𝐹

(2-10)

Based on (2-10), the methods for improving nano-pore interfacing noise can be classified as:
•

Improving 𝚤𝚤�2𝐹𝐹 and increasing 𝑅𝑅𝐹𝐹2 by enhancing feedback constructs such as capacitive
feedback, enhanced feedback and active feedback amplifiers

•
•

2
Decreasing total input-referred noise of the op-am (𝑒𝑒����
𝑜𝑜𝑜𝑜 )

Decreasing total input capacitance, 𝐶𝐶𝐼𝐼𝐼𝐼 , and 𝚤𝚤�2𝐷𝐷 by using a Lab-on-CMOS approach

The capacitive feedback approach forgoes the feedback resistor to avoid resistive feedback

noise, effectively making the value of RF approach infinity at DC. Assuming that RIN also has a
large value, capacitive feedback would decrease the noise floor significantly and save the circuit
area of a large feedback resistor. Note that the feedback capacitance should be significantly lower
than the total input capacitance to avoid introducing another noise performance factor. The area
saved by eliminating the feedback resistor can be utilized for noise reduction on the CMOS
circuitry. However, implementing capacitive feedback will leave the interface vulnerable to input
DC offset signals that could saturate the op-amp if left unchecked [37]. One solution to this issue
is to incorporate an input current DC offset canceling mechanism as shown in Figure 2-7 [45].
This is an integrator structure with periodic reset switching to stop the integrator from saturating,
followed by a gain stage and a low-pass filter. The circuit was designed for measuring DNA strands
passing through a silicon-based nano-pore implemented in a 0.5Âľm bulk CMOS technology. While
this circuit displays exemplary performance for its intended purpose, the periodic reset limits its
bandwidth to a maximum of 10 kHz, which is not ideal for nano-pores with faster transition times.
This integrating structure consumes 1.5 mW of power and 0.1386 mm2 for each channel.

20

Reset Integrator
Reset Post Amp
𝐈𝐢𝐧

𝐂𝐅

𝐂𝟐

𝐂𝟏 = 𝐧𝐂𝟐

Low-pass
filter

𝐕𝐨𝐮𝐭

Figure 2-7 Capacitive interfacing of amperometric current using reseting switches adapted

A popular method for enhancing the basic TIA noise performance is to use a feedback with
a relatively small resistance coupled with an active current attenuator as shown in Fig. 2.6.

2.6.

High throughput array implementation, opportunities and challenges

Due to recent advancements in microfabrication techniques and biological sciences, using
microarrays for parallel sensing is developing into a new trend [38][39]. These structures
accelerate the development time and extracted valuable data in various scientific instrumentations.
Nano-pores in conjugation with microfluidic delivery systems demonstrate great potential for
enabling parallel recording of biological signals. This is especially the case for ion-channels
formed on a BLM structure due to their self-assembling nature that enables them to automatically
form in designated spots in a microfluidic system [25]. A Flip side of this case is the fact the
chances of successfully forming a BLM with appropriate number of functional ion channels is
very low [46]. Alternative methods suffer from the same fate as well. A patch-clamp extraction
method for ion channels would be very laborious and time consuming without having better odds
of extracting the correct target ion channels. Hence, a logical use for self-forming ion channel

21

Nano-pores would be in form of an array where a large number of Nano-pore are implemented
simultaneously, increasing the odds of successful formation of ion-channels.
Interfacing with Nano-pore arrays brings about a new set of design challenges that need to
be addressed. The works presented in [42] and [43] both demonstrate parallel recording
functionality with very limited number of arrays and sub kHz bandwidth. Thus they are not able
to detect single molecule events. This is due to the fact that the sensing circuitry is not integrated
within the microfluidic system containing the Nano-pres. Consequently, the results are obscured
due to the plethora of parasitic capacitances and lack of noise fine-tuning. There exists a push to
bring about a lab-on-CMOS approach to array sensing by integrating CMOS readout circuitry in
close proximity of a Nano-pore array system [44]. Doing so would produce limitations in terms of
the power and area consumed by the Nano-pore interface circuitry.
A prime example of these limitations is evident in the work presented in [44] and [26].
These papers seek to implement arrays of hundreds of Ion-channel in a microfluidic system
implemented on the chip surface. Each Nano-pore has a pixel amplifier stage in close proximity
to mitigate the effects of excessive input capacitance. As a results, the pixel amplifiers have very
strict limitations in terms of the area they consume. Furthermore, since there are hundreds of pixel
amplifier stages right beneath the ion channels, there is the possibility of the CMOS circuitry
heating up the pores and thus destroying hem in the process. As a result, strict power consumption
limitations are to be implemented for the CMOS buffer circuitry.
A solution to this issue is presented in [44] and [26] in form of a shared op-amp structure.
This concept was first presented in a body of work for bio-sensing presented in [47] where multiple
OP-amps working in a TIA configuration with a set positive terminal input. The solution is to share
the positive segment and only use half of the op-amp body for each TIA structure. As a result, the
22

saved power and area resources act as a resource that can be allocated to enhancing noise
performance or ensuring system feasibility.

2.7.

Conclusion

All in all, there is much being done in the field of bio-electrochemistry. This is true
especially in the field of nano-pore and ion-channel interfacing for DNA detection, protein
characterization, etc. Even though most work in this field present novel ideas and approaches to
solve numerous issues, none are compatible with the vision that is introduced for a lab-on-CMOS
mass ion-channel arrays. Most of the work presented usually focus on single target detection and
have no concern for circuit area or power consumption. Next chapter will attend this and try to
solve the noise, power and area issues that stem from mass implementation of ion-channels on the
lab-on-CMOS platform.

23

3. A CMOS current amplifier for high throughput ion-channel arrays
So far, the nature of ion-channels located in synthetic BLMs and their electrical
characteristics have been discussed so far in this thesis. It is evident that a new CMOS topology is
needed for a full system implementation of arrays of synthetic BLMs. The works conducted in the
field so far have all been concentrating on a single nano-pore structures. Hence, this chapter will
focus on defining the challenges of implementing arrays of ion-channels and propose solutions for
a successful Implementation.

3.1.

An array solution for ion-channel sensing

Despite the recent advancements in proteomics and tethering mechanisms there are still
major issue that need to be addressed. Even though the patch-clamp method is a scientific
community favorite since 1970s, the process is laborious. The patch-clam user does not have any
control over what membrane proteins are clamped from the cell. Hence, performing a successful
test would be a laborious experience with long waiting and testing times. Although still in
experimental phase, synthetic membrane formation suffers from similar issues. The odds of
forming an effective membrane layer are extremely low. Hence performing a characterization test
on a synthetic BLM regarding their membrane proteins and lipid composition may take a tens of
hours [48]. However, synthetic BLM formation has a certain advantage over patch-clamp methods.
It is entirely possible to form these synthetic BLMs in an array format in presence of microfluidic
channels and electrodes. Hence, the idea of implementing and characterizing synthetic BLMs in
arrays presents itself [26].
Due to their nature, implementing and tethering synthetic BLMs would require a selfassembling technique with a microfluidic approach. One of the earlier approaches in doing so,

24

involves flowing lipid solutions across an aperture containing a BLM chamber with a 500 Âľm hole
through a glass slide in a microfluidic structure [49]. More recent techniques try to eliminate the
use of heavy non-volatile solvents by passing an aqueous solution with a thin layer of phospholipid
stock solution at the gas-lipid interface on both sides of the chamber. Doing so would merge the
phospholipid monolayers, forming a BLM across the aperture. The formed devices have
microfluidic channels on one or both sides of the substrate containing the aperture [50][51].
A design using these principals is depicted in Figure 3 1. It is composed of multiple
independent microfluidic channels each containing hundreds of chambers that are called pixels.
Each pixel houses a single synthetic BLM, an isolated electrolyte solution and WE electrode. There
is a shared RE electrode in each microfluidic channel that acts as a common analog ground
potential. The analog chip beneath the microfluidic channels interfaces each pixel and senses any
ion movement through the ion channels existing on pixel synthetic BLM layer using the WE
electrode. The analog chip is implemented using AMI C5N 0.5 Âľm technology. This system is
designed to be high throughput with the goal of housing ~100 synthetic BLM pixels on a single
chip. This brings about one of the biggest issues for the feasibility of this project. Aside
implementation of the synthetic BLMs and the microfluidic channel, placing ~100 pixels on a
2.5mm × 2.5mm chip would bring about a serious CMOS design challenge. Later sections would
try to shine light on some of these issues.

25

Microfluidics

CMOS
sensor/
readout

chip
Electrical
Connections

Synthetic membrane

Microfluidics

RE

We

Pixel

Figure 3-1 An array of BLMs implemented over pixels adjacent to a microfluidic chamber
built on a CMOS chip for direct readout of the ion channel incidents with minimal noise.

3.2.

Noise limitations for interfacing ion-channels

The signal that is generated through membrane protein is in pA levels and has a very short
duration [52]. The bandwidth required of the circuit for it to be able to capture the fast transitioning
signals spans from DC to hundreds of kHz. What this means is that the system is susceptible to
low frequency noise such as flicker as well as high frequency noise elements. Consequently, it is
expected of the system to demonstrate exemplary performance in terms of noise. One of the
benchmark instruments for current sensing in electrophysiology is Axon Axopatch 200B. It has an
26

r.m.s. noise floor of 25fA at 1 kHz frequency (0.7fA/√Hz until 1 kHz) [53]. However, the presented
instrument is bulky, expensive and used under specific laborious conditions. The ideal input-output
relationship of a resistive and capacitive feedback as shown in Figure 2-6 TIA can be formulated
as:
𝑅𝑅

𝐹𝐹
𝑣𝑣𝑂𝑂𝑂𝑂𝑂𝑂 = − 1+𝑗𝑗2𝜋𝜋𝜋𝜋𝑅𝑅

𝐹𝐹 𝐶𝐶𝐹𝐹

× 𝑣𝑣𝐼𝐼𝐼𝐼

(3-1)

where RF and CF are the TIA feedback elements. The capacitance acts as a low-pass filter, ensuring
system stability in higher frequencies given the presence of an input capacitance 𝐶𝐶𝐼𝐼𝐼𝐼

Given the noise spectrum dependency on input capacitance, implementing the idea of an array

of synthetic BLMs poses a new challenges. Interfacing hundreds and thousands of electrodes over
the chip surface would not be possible without producing excessive parasitic input capacitances
for the amperometric readout circuit endangering system feasibility. Our lab has proposed a
solution in [40] in which a very small CMOS circuit is place beneath the synthetic membrane as
shown in Figure 3-4. Each chamber containing a WE electrode and a synthetic membrane is called
a pixel. As shown in Figure 3-2, each pixel is encapsulate by a WE electrode and a planar BLM
containing an ion-channel. The global RE electrode maintains the microfluidic potential, providing
the system with electrolytes that can travel through the ion-channel. The target microfluidics are
passes through the channel and interact with the membranes and their ion-channels. Placing the
CMOS buffer right beneath the corresponding pixel has two significant advantage. It minimizes
the interface and wiring capacitance, reducing the noise requirement on the first stage buffer by a
large margin. Moreover, due to the fact that the synthetic BLM has a fairly predictable capacitance,
it would be easier to match the CMOS interface with the noise requirements for interfacing the
pixel. The implemented CMOS pixel interface also amplifies the low input current enough so that

27

it would be connected to less noise sensitive components like multiplexers and gain-focused
amplifiers. This makes multiplexing thousands of pixels into a few clear outputs possible.

Figure 3-2 3D view of the proposed pixels for the proposed lab-on-CMOS concept.

3.3.

Area and power limitations for interfacing a high throughput ion-channel arrays

So far, it has been suggested to put a CMOS interface circuit under each pixel to mitigate
the effects of unwanted noisy capacitances. However, doing so is not an easy task mainly due to
the fact that placing the interface right beneath the pixel would impose area, power and noise
restrictions on the circuit. These issues are not going to hinder the feasibility of the proposed
concept however, they will cause major circuit challenges. Hence, design limits and trade-offs are
needed to be considered before designing the CMOS circuitry. Unfortunately, challenges arising
from a lab-on-CMOS approach are a very niche field in the area of membrane characterization or
nano-pore studies. As a result, not a lot of literature has been focused on solving the challenge
introduced in Chapter 2.4.

28

A big limitation in terms of CMOS realization of the system proposed in Figure 3-2 is the
maximum area dedicated to each pixel amplifiers. The CMOS will be implemented in AMI 0.5
Âľm technology with dimensions bigger than 25mm2. Since currently we are planning to put a 1000
of pixels in this chip area, approximately 0.025 mm2 of space would be dedicated to each pixel
which is enough for the physical pixel area. As depicted in Figure 3-2 the maximum area dedicated
to each pixel amplifier is not going to be greater than the corresponding pixel. Hence, not
considering the complementary circuit blocks such as bias and MUX, the approximate area
dedicated to each pixel amplifier is estimated to be 0.025 mm2. It is worth noting that this area
limitation is imposed on AMI 0.5Âľm technology. There are only three metal layer available in the
said technology with limited use on metal 3 layer due to the possibility of it causing difficulties
implementing the microfluidic channels.
Limitations on power consumption are another factor than need to be considered moving
forward with the design. As indicated before, each pixel is equipped with an interface circuit placed
right beneath it. This is due to the fact the interface circuit has the potential to act as a heater for
the pixel. Too much power consumption on each circuit would mean that the pixel will be locally
heated. High temperature has a chance to damage the synthetic BLM at the gate of the pixel. As
pointed out in [54] a heat flux of 80 mW/mm2 has the chance to damage the BLM tissue. Hence,
for a hypothetical area of 0.025 mm2 for a pixel that is surrounded by 5 other ones as shown in
Figure 3-3, the maximum allowable power consumption by each pixel can be deduced as:

29

𝑚𝑚𝑚𝑚

𝑃𝑃𝑚𝑚𝑚𝑚𝑚𝑚 = 80 𝑚𝑚𝑚𝑚2 × 0.025𝑚𝑚𝑚𝑚2 ÷ 5 = 400𝜇𝜇𝜇𝜇

(3-2)

Hence the each pixel interface has a maximum allowable power consumption of 400 ÂľW. Having
such low maximum power consumption and area would result in stringent limitations on circuit
design aspects.

Target pixel
RE
heat

heat

RE
Neighbor pixels
Figure 3-3 Local heating of pixels due to power consumed in the target pixel and it’s
adjacent pixels.

3.4.

A CMOS current amplifier design

So far it has been established that we wish to implement synthetic BLMs containing a
particular number of ion-channels in an array format. The fact that the signal current indicating
ion-channel action is very short and fast has been discussed. Since a typical ion-channel event
would be a 10 pA pulse spanning 10 Âľs, system noise performance becomes critical because noise
is directly correlated with input capacitance, as established in Figure 3-2, it was decided to place
the interface circuit right beneath the chamber. As a result, the power and area performance of the

30

system are added to the challenges that need to be answered. This section will proposed a solution
to the said issues.

3.4.1. Fundamental noise limitations of an op-amp
There are four main contributors to overall system noise which consist of flicker noise
created by the pore, flicker and white noise created by electrical components, dielectric noise
created by the input capacitance and the capacitive noise, which is most potent in higher
frequencies. The dielectric and the capacitive noise are mitigated adopting the proposed lab-onCMOS structure, reducing the stray capacitances as much as possible. However, the noise
stemming from the circuitry still remains to be addressed, especially since this noise is
intermingled with capacitive noise according to (3.7). In order to understand the basics of circuit
noise, it is always good to study the noise elements in a basic amplifier, one as such depicted in
Figure 3-4 with all the possible noise sources. The total input referred noise of the amplifier from
Figure 3-4 can be expressed as shown below [55]:
𝑔𝑔𝑚𝑚3
2
2
2
2
2
������
������
������
������
������
𝑣𝑣𝑒𝑒𝑒𝑒𝑒𝑒
= 𝑣𝑣
𝑒𝑒𝑒𝑒1 + 𝑣𝑣𝑒𝑒𝑒𝑒2 + �𝑔𝑔 � �𝑣𝑣𝑒𝑒𝑒𝑒3 + 𝑣𝑣𝑒𝑒𝑒𝑒4 �
𝑚𝑚1

(3-3)

2 represents the overall input referred noise of each transistor shown as a voltage source
where ����
𝑣𝑣𝑒𝑒𝑒𝑒

at their gate and the term 𝑔𝑔𝑚𝑚 is the transconductance of the corresponding transistor. The presented

formula assumes that transconductances on matching pairs are similar. It is clear that in order to
negate the effects of transistors M3 and M4, their transconductances should be significantly lower
than that of M1 and M2. The transistor input referred noise can be presented as:
2 = 4𝑘𝑘𝑘𝑘( 2 )∆𝑓𝑓
����
𝑣𝑣𝑒𝑒𝑒𝑒
3𝑔𝑔
𝑚𝑚

where k is the Boltzmann constant, T is the temperature and ∆f represents bandwidth.

31

(3-4)

vin

M2

M1

iout

M3

M4

Figure 3-4 Noise sources influencing a typical amplifier circuit.
It is clear that the only way to decrease the thermal noise is to increase gm as much as
possible. The term gm can be represented as:
𝑔𝑔𝑚𝑚 = �2𝜇𝜇𝐶𝐶𝑖𝑖𝑚𝑚 𝜇𝜇�𝐿𝐿 𝐼𝐼𝐷𝐷

(3-5)

where µ is the corresponding charge carrier mobility, 𝐶𝐶𝑖𝑖𝑚𝑚 is the MOSFET gate oxide capacitance,

W and L are the width and length of the transistor, and ID is the bias current of the transistor. Hence
to increase the gm of M1 and M2, the width and the bias currents are to be increased as much as
possible. Doing so would decrease the input equivalent thermal noise. The electrical flicker noise
is another issue that needs to be addressed. The input referred thermal noise of each transistor at
their gate can be presented as:

𝑓𝑓

𝑜𝑜𝑜𝑜

(3-6)

𝑊𝑊

𝐾𝐾 ∆𝑓𝑓
�����
𝑣𝑣12� = 𝐶𝐶 𝑓𝑓𝑊𝑊𝑊𝑊

where kf is the flicker noise coefficient. Placing (3.11) in (3.8) the following equation is extracted.

32

2𝐾𝐾𝑝𝑝
𝑘𝑘𝑛𝑛 𝜇𝜇𝑛𝑛 𝐿𝐿21
2
���������
𝑣𝑣
=
ďż˝
� ∆𝑓𝑓
1
𝑒𝑒𝑒𝑒− �
𝑓𝑓𝑊𝑊 𝐿𝐿 𝐶𝐶
𝑘𝑘 𝜇𝜇 𝐿𝐿2
𝑓𝑓

1 1 𝑜𝑜𝑜𝑜

𝑝𝑝 𝑝𝑝 3

(3-7)

where 𝐾𝐾𝑝𝑝 and 𝐾𝐾𝑛𝑛 are the flicker noise coefficients for PMOS and NMOS transistors respectively.

It is clear that in order to achieve better flicker noise performance, the input transistor needs to be
larger and have shorter length compared with subsequent transistors. All in all, it is easy to infer
that increasing input transistor area, and current are key to improving noise performance of the
amplifier. However, it was stated in previous sections that there is a limit to power and area due to
the lab-on-CMOS implementation. Hence, a prominent circuit feature trade-off emerges from this
argument. It is desirable to increase the pixel interface circuit area and power consumption as much
as possible without crossing the limits placed by the restrains in place due to the lab-on-CMOS
approach. It is worth noting that increasing the size of input transistors would also increase the
input capacitance of the pixel, meaning that capacitive noise would be made worse.
All in all, there are major trade-offs that need to be addressed moving forward with the
pixel interface design. There are certain limitations as to what are the maximum allowable CMOS
area and power consumption. However, in order to clearly analyze the pixel currents, noise
performance of the circuit needs to be optimized which in return is in conflict with power and area
restrains.

3.4.2. An op-amp sharing technique to address the area and power limitations of
interfacing high throughput ion channel arrays
A requirement for this project would be to have op-amps working in parallel to interface
the pixels as depicted in Figure 3-5 Pixel interfaces for nano-pore current sensing with (a) typical
TIA structure and (b) shared TIA structure.Figure 3-5 (a). It is clearly observable that all these opamp have the same voltage on their positive inputs. This voltage is the analog ground voltage that

33

is shared globally throughout the whole CMOS chip, keeping WE at the analog ground. The
stimulation is done through the RE electrode for clusters of pixels. Now if we are to hypothetically
assume that the positive segment of the op-amp could be shared with a local cluster of negative
input halves, as shown in Figure 3-5 (b), the power and area consumption of each individual
segment would drop by half. There are multitude of benefits arising from such configuration. It
would make it possible for all the extra resources to be dedicated to enhancing noise performance
or the feasibility of design dimensions. The proposed shared op-amp circuit is depicted in Figure
3-6.

feedback

Pixel segment 3

feedback

Pixel segment 2

feedback

Pixel segment 1

Shared segment

(a)

(b)

Figure 3-5 Pixel interfaces for nano-pore current sensing with (a) typical TIA structure and
(b) shared TIA structure.

34

Vdd
Vbp

Mpb-1 Vdd

Vdd

Vdd

Vbp

VF

M6

Vbp

VC
Vip

Mps

M5

Vin-n

Vin-1
Mp-1

Vo-1

Mp-n

Vo-n

M4
Vbn

Vbn

Vbn

M3

Shared stage

Stage 1

Stage n

Pixel #N

Pixel #1
Shared Stage
Figure 3-6 Shared op-amp structure circuitry and the corresponding op-amp elements.

The shared stage shown in Figure 3-6 is essentially the positive segment of the n shared
stages. It provides them with a voltage, VC, which helps maintain the semi-differential status of
the system. The voltage at VC is constant as shown below:

35

𝐼𝐼
𝑉𝑉𝐶𝐶 = 𝑉𝑉𝑡𝑡ℎ−𝑀𝑀𝑀𝑀𝑀𝑀 + � 𝑏𝑏�𝜇𝜇𝐶𝐶 𝑊𝑊/𝐿𝐿
𝑜𝑜𝑜𝑜

(3-8)

where Vth-Mps is threshold voltage of transistor Mps, Ib is the bias current going through Mps and
𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑊𝑊/𝐿𝐿 are the characteristics of Mps.

An in depth look at the shared stage indicates that it has an internal feedback loop. The

loop is shown in more details in Figure 3-7. The current source IS can be considered to be the input
of this loop while the output node is chosen to be VC. Hence, the transistors Mps, M3 and M4 are
considered to be the feedback components. As a result the feedback type can be considered a
parallel output, parallel input with β = gc. As a result, the open loop feedback can is as follows:
𝐴𝐴𝑂𝑂 =

Vdd
Vbp

M6

𝑉𝑉𝐶𝐶
𝐼𝐼𝑆𝑆

= 𝑔𝑔𝑐𝑐 𝑅𝑅𝑠𝑠−𝑝𝑝𝑝𝑝 𝑅𝑅𝑖𝑖𝑖𝑖

Mpb-1 Vdd
VF

Rin

Mc

Vip

Mps

Rout
Vc

Vc
M5

(3-9)

gcRs-psVs

Vs
IS
M4

Vs
M4

IS

Vbn
Vbn

M3

gcVc

feedback

M3

Figure 3-7 Equivalent circuit structure for the internal feedback loop placed within shared
segment of proposed op-amp.

36

where Rin is the resistance seen on the drain of M5 which is a great number because M5 and M6 are
in parallel. Rs-ps is the total resistance seen at the node Vc which is equal to the source resistance
of Mps and gc is the trans-conductance of Mc. As a result, the feedback overall gain is:
𝐴𝐴𝐹𝐹 =

𝑉𝑉𝐶𝐶
𝐼𝐼𝑆𝑆

𝑔𝑔 𝑅𝑅𝑖𝑖𝑖𝑖

= 1+𝑔𝑔𝑐𝑐

𝑐𝑐 𝑅𝑅𝑖𝑖𝑖𝑖

𝑅𝑅𝑠𝑠−𝑝𝑝𝑝𝑝

(3-10)

Furthermore, the output resistance seen at node Vc is:
𝑅𝑅𝑠𝑠−𝑝𝑝𝑝𝑝

𝑅𝑅𝑂𝑂𝑂𝑂𝑂𝑂−𝐹𝐹 = 1+𝑔𝑔

𝑐𝑐 𝑅𝑅𝑖𝑖𝑖𝑖

(3-11)

Which means that the resistance seen at node Rs is extremely small due to the fact that both gc and
Rin are a big trans-conductance and resistance. Thus the voltage VC is held constantly by feedback
loop present at the shared stage. This is because VC is a node with a very low resistance connected
to a voltage source. Hence, the resistance in the node VC is so small that every shared stage can
act as fully differential stage without affecting the other op-amp stages.
As a result, each shared stage sees a very small resistance at the source of their input
transistors and operate as a single op-amp with their positive input fixed to a certain voltage. If a
pixel amplifier has a feedback as shown on Figure 3-8, if Mp-1 and Mps are matched, it would try
to equate Ib-ps and Ib-p1 since Ib-bp and Ib-bn are similar. As a result, the loop will try to make Vin-1 be
equal to Vip.
If a current input signal iin is injected to stage n among N stages is called imn then it is easy
to infer that:

37

Vdd
Vbp

Mpb-1 Vdd

Vdd
Vbp

VF

Ib-bp

VC
Vip

Ib-bp

Vin-1

Mps

Mp-1

Vo-1

Ib-p1

Ib-ps
Vbn

Vbn

Ib-bn

Ib-bn

feedback

Shared stage

Figure 3-8 Proposed shared op-amp with only one gain stage and a negative feedback loop.

1

= 1+𝑁𝑁+𝑔𝑔

𝑐𝑐 𝑅𝑅𝑖𝑖

(3-12)
𝑖𝑖

𝑖𝑖𝑖𝑖

𝑖𝑖

𝑖𝑖𝑚𝑚𝑚𝑚

which is due to the fact that iin is shared among N stages and a very low feedback output resistance
which takes a huge chunk of the current. As a result, the total noise injected by another shared
stages to a sample stage, n is as follows:
�������
𝚤𝚤𝑚𝑚𝑚𝑚 2
����������
𝚤𝚤𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 2

1

= (1+𝑁𝑁+𝑔𝑔

2
𝑐𝑐 𝑅𝑅𝑖𝑖𝑖𝑖 )

(3-13)

Where inoise is produced by another shared stage. As a result it is possible to infer that it is possible
to infer that N-1 other shared stages have the following effect on stage n:

38

�������
𝚤𝚤𝑚𝑚𝑚𝑚 2
����������
𝚤𝚤𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 2

𝑁𝑁−1

= (1+𝑁𝑁+𝑔𝑔

(3-14)

2
𝑐𝑐 𝑅𝑅𝑖𝑖𝑖𝑖 )

which is completely negligible. As for the shared stage, based on Figure 3-9 which is a simplified
version of the shared op-amp structure, the noise injected into stage n from shared stage can be
calculated as:
�������
𝚤𝚤𝑚𝑚𝑚𝑚 2
���������������������
𝚤𝚤𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛−𝑠𝑠ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 2

2

(𝑔𝑔𝑐𝑐 𝑅𝑅𝑖𝑖𝑖𝑖 )
2
����2 �����2
= �𝚤𝚤����
3 + 𝚤𝚤6 + 𝚤𝚤𝑝𝑝𝑝𝑝 � (1+𝑁𝑁+𝑔𝑔 𝑅𝑅

𝑐𝑐 𝑖𝑖𝑖𝑖

)2

1
2
+ �𝚤𝚤��������
𝑝𝑝𝑝𝑝−1 � (1+𝑁𝑁+𝑔𝑔

(3-15)

2
𝑐𝑐 𝑅𝑅𝑖𝑖𝑖𝑖 )

however since the term gcRin is very big, it is possible to infer that the effects the shared stage has
on any other stage, namely n is as shown below:
�������
𝚤𝚤𝑚𝑚𝑚𝑚 2
2
���������������������
𝚤𝚤
𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛−𝑠𝑠ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎

2
= ����
𝚤𝚤3 2 + ����
𝚤𝚤6 2 + 𝚤𝚤�����
𝑝𝑝𝑝𝑝

(3-16)

which indicates that the shared stage has a similar effect on the shared stage to that of a normal
folded cascade.
As a result, the proposed shared circuit reduces the power and area required for implementing an
interface op-amp with slightly better noise performance when compared with a typical similar
telescopic cascade structure.

39

Vdd

Mpb-1 Vdd

Vbp

Vdd
Vbp

VF

M6

Mps

Vbn

Vbp

M6-1

VC
Vip

Vdd

Vin-1

M6-n

Vo-1

Mp-1

Vbn

M3

Shared stage

Vin-n
Mp-n

Vo-n

Vbn

M3-1

M3-n

Stage 1

Stage n

Figure 3-9 Noise and interface sources of the proposed share op-amp structure.

3.4.3. A low-noise compact feedback Structure
As indicated in previous sections the main focus of the pixel amplifier stage is to improve
its power, area noise performance as was evident with the choice of adopting shared op-amp
structure. Based on the discussions in 2.4.1, , the best option would be to go for a fully active
amplifier structure introduced in [56]. The feedback structure would work as a current buffer
structure with relatively low gain. However, this would not cause much problems for the
implementation since the pixel amplifier stage is not meant to demonstrate such characteristic.
Let’s imagine that the feedback loop is as shown in Figure 3-10. If the input current Iin is
zero, then all feedback transistors Mp1, Mn1, Mp2 and Mn2 are operating in sub threshold region
since their gate-source voltage (overdrive voltage) is normally zero [57]. Hence they are not
contributing to system noise. It is worth noting that the input current is always considered to be
40

zero since there is no ionic current flowing through membrane while the ion-channel is closed.
However, despite the fact that the feedback transistors are operating in sub-threshold region the
input voltage on the WE node is always equal to the analog ground since the current that the
feedback loop is required to provide is very small and does not affect the feedback transistors
extensively. Now if there was an input current Iin present, depending on the polarity of the input
current, the voltage Vo1 would vary the overdrive voltage of feedback transistors Mp1 and Mn1 so
that they would produce a current equal to Iin. As a result, the transistors would uphold their duty
as feedback components, keeping the positive and negative inputs of op-amp equal. The
relationship between the op-amp output voltage Vo1 and the input current can be expressed as:
𝐼𝐼

𝑉𝑉𝑜𝑜𝑜𝑜 = ∓𝑛𝑛𝑉𝑉𝑇𝑇 ln(𝐼𝐼 𝑖𝑖𝑖𝑖 )
𝐷𝐷0

(3-17)

where VT is the thermal voltage, Vod is the overdrive voltage, ID0 is the drain current at Vod = 0,
and n is:
𝑛𝑛 = 1 +

𝐶𝐶𝐷𝐷
�𝐶𝐶
𝑂𝑂𝑂𝑂

(3-18)

where CD is the capacitance of the depletion layer and COX is the capacitance of the oxide layer.
The transistors Mn2 and Mp2 are exactly Z times bigger than Mn1 and Mp1 in terms of transistor
width. However, the overdrive voltage, Vod, they see is the same as Mp1 and Mn1. As a result the
ID0 and subsequently ID on transistors Mn2 and Mp2 is Z times bigger than input current Iin. Since
the drain-source voltage on all the transistors is the same, it is safe to assume that the gain of this
circuit is exactly Z. As a result, the proposed structure acts as a current buffer with a gain of Z. It
should be noted that the transistors only operate well in lower frequency ranges [56]. Hence, the
capacitances C1 and C2 are incorporated to maintain the gain Z at higher frequency ranges.

41

Mp1

Z×Iin
C1

Iin
WE

Z

Mn1

Mp2
C2

Vo2

Vo1

Z

Mn2

Figure 3-10 The implemented active feedback network for nano pore current interfacing.

An inherent benefit of the proposed structure is the fact that the op-amp output voltage has
I

a logarithmic relationship with input current as indicated in Vod = ∓nVT ln(I in )
D0

(3-24). As a

result, the circuit is able to interface a wide range of input currents. It is worth noting that it is
preferred for the feedback transistors to stay in sub-threshold region through the entirety of the
input current range. However it is not possible to uphold this at very high input currents. Ideally,
it is preferred to make the input transistors very long so that they would be able to interface larger
currents without turning on. As for extremely large input currents, the system performance at such
great input currents is not critical. Hence, the transistors are allowed to turn on.
As mentioned earlier, there are major benefits in adopting the active transistor only
feedback architecture introduced in 2.4. These benefits include saving power and area due to the
fact that the contrary to the literature, the active feedback structure does not require any passive
components, supporting circuitry or active power consumption. Moreover, this architecture

42

displays exemplary noise performance due to the fact that the feedback transistors are operating in
sub-threshold region.
Despite all the discussed benefits, there are issues that need to be mentioned. The biggest
issues may be classified as gain certainty and output data format. Due to the fact that transistors
Mp2 and Mn2 are Z times bigger than Mp1 and Mn1, it is very challenging to match the said
transistors perfectly especially if the transistor sizes are close to the technology minimum. As a
result, it is very difficult to obtain a consistent gain Z over a multitude of stages. This is
corroborated by the fact that the positive and negative gains demonstrated by the pMOS and nMOS
transistors may differ. The reason is that pMOS transistors only handle the negative input currents
while the nMOS transistors only interface the positive input currents and it is very hard to
completely match pMOS and nMOS area ratios individually. This issue can be solved by making
the feedback transistors bigger, sacrificing power. As a result, there is a trade-off between pixel
amplifier area and gain accuracy. Fortunately, the gain required of the first stage is only about 20
dB. As a result, it would be much easier to match transistor ratios correctly with such low gain
limits. Another issue that arises from this implementation is the fact that depending on feedback
transistor operation region the op-amp output voltage Vo1 is correlated to input current
logarithmically or linearly and thus, is not usable for data acquisition. Other stages are needed to
turn the output current into a coherent readable signal. These stages and the topology required to
run them are discussed in the next section.
3.5.

A shared amplifier topology for optimum area usage
So far the principals of the circuit being implemented have been established. This section

will be concentrating on the topology that our team came up trying to implement this architecture.
Let’s imagine that our desired gain is 100. If the topology suggested in Figure 3-11(a) is used, the

43

total area consumed by the feedback transistors would be 101×Mp1. In C5N technology the
minimum legal transistor width and length 1.5 Âľm and 600 nm respectively. However, the
minimum size is opted for 6 Âľm of width and 1.2 Âľm of length due to the fact that the system gain
is dependent on the ratio of these transistors and we would prefer avoid any possible mismatch
due to minimum sizing. The fact that such big transistors exist in every pixel amplifier would rob
the design of its area budget. One way to mitigate this issue is using multiple gain stages in cascade
as shown in Figure 3-11(b). Assuming Mp1 and Mp3 have the same sizes, the total area consumed
by gain transistors is reduced to 22×Mp1.

Mp1
C1
Iin

100×Mp1

Mn1

100×C1

WE
Vo1

a

100×Mn1
Mp1
C1

Iin

Mn1

WE

100×Iin

Mp3
10×Mp1

10×C1

C3
10×Iin

Mn3

10×Mp3
10×C3
100×Iin

b

10×Mn3
10×Mn1

Figure 3-11 The difference between having a single stage with a gain of 100 and having two
stages with two stages with a gain of 10 resulting in a total gain of 100.

44

Upon further investigation, the only truly essential part of the circuit depicted in Figure
3-11(b) is the first stage. This is due to the fact that this stage is responsible for isolating the input
capacitance caused by the membrane capacitance, keeping the noise levels low. Hence, the second
stage can be further shared to optimize the system area. A suitable topology to implement these
changes is shown in Figure 3-12. The topology is divided into independent clusters which contain
M stages of N pixel interfaces. Each stage of N pixel interfaces are multiplexed. The resulting M
signals are fed to a gain stage that multiplexes this signals to an off-chip signal processing unit.
Implementing the system with this topology opens the way for putting great numbers of pixel
amplifiers in a single chip. The total number of pixel amplifiers implemented with this method is
M×N×K. If each of these parameters is 8, the total pixel amplifiers covered would be 512 which
is more than enough for an initial implementation.

45

Noise sensitive stage

Gain stage

Pixel #1

External signal processing

MUX

Pixel #2

Gain #1
MUX
Gain #2

Pixel #N

Gain #M

Stage 2

MUX

Stage M

MUX

Cluster #1
Cluster #2

●●●

Cluster #K

Figure 3-12 The topology in which pixel amplifiers would be implemented to interface a
large number of pixels.

All in all, the presented op-amp structure and topology seem to be suitable for interfacing
an array of ion-channels. However, before any practical efforts are made implementing a lab-onCMOS approach implementing this system, the functionality of the proposed CMOS solution
needs to be tested in a real-world test environment. As a result, a chip for evaluate and verification
of the proposed CMOS approach is fabricated in standard ON C5N technology and tested. Chapter
4 will cover this topic extensively.

46

4. Evaluation of current amplifier performance
So far it’s been established that with the use of nano-pores such as ion-channels, the issue
of single molecule detection reduces to a simple instrumentation issue. A solution is discussed
with a shared op-amp structure and a subthreshold transistor-only feedback structure. To prove
that this architecture would perform adequately under an array of ion-channels, the architecture
needs to be tested in a real world environment. Thus, a test chip was fabricated in AMI 0.5 Âľm
C5N CMOS technology incorporating some variations of the proposed architecture which will be
discussed in this chapter.

4.1.

CMOS test chip contents and functionalities

Various functionalities of the proposed design need to be tested. This include the viability
of the share op-amp as a basic block, the possibility of sharing these op-amps, the functionality of
the transistor-only feedback and system’s ability to tolerate a membrane input capacitive noise
while interfacing ionic current. To this end, as shown in Figure 4-1, a test chip containing various
blocks has been fabricated and tested in AMI 0.5 Âľm C5N CMOS technology. The main test target
in the chip would be the shared block with the gain of 1000 and a capacitive input. This block is
composed of 4 shared stages followed by a gain stage as is used to confirm that all the aspects of
the proposed circuit work well together. The capacitive input is only for isolation of input from
any external capacitance and will be discussed in detail later. Other segments include a shared
stage without capacitive input, single op-amp interface stages as well as bias circuit and a test opamp. Figure 4-2 sheds more light about the placement of stages in a shared structure. The shared
op-amp is places in the middle of four gain stages to minimize op-amp mismatch and offset
between the stages. The resulting signals are passed through a very small MUX stage that connects
the output to an additional gain stage resulting in a grand total gain of 1000. Segments 3 and 4

47

have an input capacitance of 5 pF which is an estimated value for a BLM cell with an ion-channel
over a 5 um wide channel [40].
Shared op-amp buffer
stage with gain of 100
and direct inputs

Shared op-amp buffer
stage with gain of 1000
and capacitive input

Single buffer stage
with capacitive input

Bias stage
Test op-amp

Figure 4-1 The fabricated test chip with all the various blocks implemented.

48

Figure 4-2 The shared op-amp stages and how they are placed within the test chip.

4.2.

A testing platform for the extremely sensitive instrumentation circuit

The implemented circuit is designed to be able to read amperometric input currents under
a maximum input load capacitances of 5 pF which is the estimation of a BLM layer’s capacitance
over a 5 Âľm wide chamber gate. As a result, any input capacitance over this limit would limit the
functionality of the circuit. Thus, this makes connecting any test probes directly to the input gate
impossible. The reason is that connecting any current source probes would create an excessive
amount of parasitic capacitances that would impair the functionality of the amperometric current
reader. This would make any direct test impossible. The solution embedded on the chip is as shown
in Figure 4-3. The input to the current buffer is isolated from the input port by a very small

49

capacitance Ciso (100 fF). As a result, any external capacitance connected to the input port would
be in series with Ciso and will be automatically ignored. The input membrane capacitance is
modeled with the capacitance Cmem. This capacitive input method has been implemented for all
input channels mentioned in Figure 4-1 except for the ones dubbed direct input.

feedback

Figure 4-3 The test configuration for input parasitic noise compensation.
The input current is generated from input voltage Vin as shown below:
𝑖𝑖𝑖𝑖𝑖𝑖 = 𝐶𝐶𝑖𝑖𝑖𝑖𝑖𝑖

∆𝑉𝑉𝑖𝑖𝑖𝑖
∆𝑡𝑡

(4-1)

Where ∆Vin is the amplitude of input pulse signals and ∆t is the pulse rising/falling time. With ∆t
of 10 Âľsec and a pulse amplitude of 1 mV over, a 100 fF capacitance, it is possible to generate a
clean current input pulse of 10pA. If a sin input is being used, the current will be shaped as shown
below:
𝑖𝑖𝑖𝑖𝑖𝑖 = 𝐴𝐴𝑠𝑠𝑠𝑠𝑠𝑠 𝐶𝐶𝑖𝑖𝑖𝑖𝑖𝑖 2𝜋𝜋𝜋𝜋cos(2𝜋𝜋𝜋𝜋𝜋𝜋)

(4-2)

Where Asin is the input sinusoidal signal amplitude and f represents frequency. As a result, it is
clear that the input capacitance and signal capacitance play a major role in determining input
current amplitude. As a result, two different Ciso capacitances were utilized, a 10 fF and a 100 fF.

50

Their input operation range for generating a steady 100 pA input sinusoidal current is as shown
below:
Table 1 the input sinusoidal range for various isolation capacitances
Frequency

100 fF

10 fF

100 Hz

Asin= 1.591 V

Asin= 15.91 V

1 kHz

Asin= 159.1 mV

Asin= 1.591 V

10 kHz

Asin= 15.91 mV

Asin= 159.1 mV

100 kHz

Asin= 1.591 mV

Asin= 15.91 mV

Based on Table 1, the amplitudes 1.591 mV and 15.91 V are impossible to implement. This
is due to it being very difficult to produce a clean 1.591 mV input sinusoidal current and 15.91 V
being way above the tolerable voltages that AMI 0.5 Âľm C5N CMOS technology allows. A
combination of both these input capacitances needs to be implemented. Hence, pixel segment 1
and 3 are equipped with a 10 fF metallic capacitance while 2 and 4 have a 100 fF poly capacitance.

4.3.

Test results

The first step in testing the implemented chip would be to evaluate overall chip
functionality and measure the response of the implemented buffer under various DC input currents.
To do so, the input to one of the direct input current buffers, i.e. the ones not isolated from input
through an isolating capacitance, is used. The test setup is as depicted in Figure 4-4.

51

feedback

Chip
Figure 4-4 Test setup for input DC response test.
Rin is a 1 GΊ resistor with an accuracy of less than 1%. The input voltage deviates from
the analog ground in multiples of 10 mV steps. As a results, the variation is in increments of 10
pA. The system response to the input resistance is very noisy due to the parasitic capacitance
present due to the probe connection and the structure of the resistance. The direct mode current
buffer has a gain of 100. Hence, the output current is passed through a The results are passed
through a low-pass filter and averaged over 1024 cycles using an Agilent Technologies DSO-X
2012A oscilloscope device. The results are shown in Figure 4-5. The response is linear whether
the input stimuli is positive or negative, however, there is a difference between the slopes of the
responses under positive and negative imputs as shown in Figure 4-6. This is due to the fact that
based on the feedback structure introduced in Figure 3-11, the positive input currents are handled
through a set of NMOS transistors while the negative inputs are handled but the input PMOS pair.
Hence the two slopes do not necessarily have to match. The reason for the variations in the slopes
could be attributed to the differences in threshold voltages and systematic mismatches between
similar MOS transistors. It should be noted that the function that this circuit is designed to perform
is merely detecting input pulses. Hence, the linearity matching between positive and negative
inputs is of no consequence for the scope of this project. The results shown indicate that the system
is functional and ready for high-frequency testing.

52

Output current (A)

-1000

-500

9.00E-10
8.00E-10
7.00E-10
6.00E-10
5.00E-10
4.00E-10
3.00E-10
2.00E-10
1.00E-10
0.00E+00
-1.00E-10
-2.00E-10
-3.00E-10
-4.00E-10
-5.00E-10
-6.00E-10
-7.00E-10
-8.00E-10
-9.00E-10
-1.00E-09

0

500

1000

y = -8E-13x + 3E-11

Input voltage (mV)
Figure 4-5 The circuit response to a DC input current.

Figure 4-6 The circuit response to individual positive and negative stimulation.

After establishing system functionality, the next priority falls in proving the noise
performance required to interrogate ion-channels established BLMs over the 100 kHz bandwidth.
To do so, a sinusoidal input waveform is played over the input isolation capacitance in a shared

53

stage with a total current gain of 1000. The results are converted to a voltage signal through a
trans-impedance stage and passed through a second order filter with a 3-dB frequency of 50 kHz.
This value is chosen due to simulations trying to find the best filtering scheme trying to observe a
100 kHz pulse input signal. The output voltage is recoded with a keysight spectrum analyzer over
100 kHz with a sampling interval of 10Hz. Two sets of input sinusoidal frequency is given to the
system, a 1 kHz signal and a 10 kHz signal. The sin signal amplitude is selected based on the
values shown in Table 1 for a 10 fF input capacitance. The results are shown in Figure 4-7. As
suggested in Figure 3-2, the increase in noise power over frequency spectrum due to the addition
of the input 5 pF capacitance is observed by the difference in the shape of the response spectrum
as suggested in Figure 4-7.
The system noise performance can be evaluated using waveforms in Figure 4-7. The input
current amplitude is 50 pA. Hence, the peak signal values in all waveforms in Figure 4-7 are the
result of the 50 pA sinusoidal input. This opens the path to calculating the noise floor by calculating
the SNR and acquiring noise power through the following formula:

𝑁𝑁𝑟𝑟𝑟𝑟𝑟𝑟 =

(𝐴𝐴𝑠𝑠𝑠𝑠𝑠𝑠 )2�
2
𝑆𝑆𝑆𝑆𝑆𝑆

(4-3)

Where Asin is the input current signal amplitude and Nrms is the r.m.s. noise power. The spectrum
shown in Figure 4-7 is composed of discrete frequency elements. Each value E depicted in this
figure is an average of all signal powers over the frequency step df, which is 10 Hz in this case.
As a result, the depicted signal power is Epeakdf and the total noise power is calculated through the
following formula:

54

100 𝑘𝑘𝑘𝑘𝑘𝑘

𝑁𝑁 = ∫0

𝑆𝑆𝑆𝑆𝑆𝑆 = ∑ 𝑆𝑆𝑆𝑆𝑆𝑆

(4-4)

Where S represents the signal values presented in Figure 4-7. The Total SNR can be calculated
using the following formula:
𝑆𝑆𝑆𝑆𝑆𝑆 =

𝐸𝐸𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑑𝑑𝑑𝑑
∑ 𝑆𝑆𝑆𝑆𝑆𝑆

9.1900×10−6

= 6.8475×10−7 = 13.421

(4-5)

The total signal value and N for a 1 kHz input spectrum are 9.19e-6 and 6.85e-7 respectively.
Hence, the total noise power can be calculated as follows:

𝑁𝑁𝑟𝑟𝑟𝑟𝑟𝑟 =

(𝐴𝐴𝑠𝑠𝑠𝑠𝑠𝑠 )2�
2
𝑆𝑆𝑆𝑆𝑆𝑆

=

(50 𝑝𝑝𝑝𝑝)2�
2
13.421

= 9.3138 × 10−23

(4-6)

Hence, the total input-referred noise current 9.65 pA which is very close to the simulation
estimated current of 3 pA. This proves that the presented system is capable of observing 10 pA
pulse inputs at a 100 kHz bandwidth with the presence of a 5 pF input capacitance.

55

Without membrane
capacitance

membrane
capacitance included

Without membrane
capacitance

membrane
capacitance included

Figure 4-7 System frequency response to incoming input sinusoidal current at 1 kHz and 10
kHz frequencies with and without input membrane capacitance.

To confirm overall system functionality, a pulsed input current that mimics that of an ion
channel event is given to the input channels with isolation capacitances of 100 fF. The pulse
amplitude needed to test this phenomenon should be about 10 pA which is possible to produce
thanks to the isolation input capacitances. Using (4-1) with a pulsed input voltage amplitude of 1

56

mV and a rising/falling time of 10 Âľs, it is possible to produce the desired 10 pA input current
pulses as suggested in Figure 4-7.

Figure 4-8 The pulsed input scheme for creating clean 10 pA pulse currents for feeding the
circuit.

The input pulsed waveform is generated with an Agilent 33120A series function generator
and decimated with a precise voltage divider resistive scheme. The system response to this input
is shown Figure 4-9. The results are captured and stored using an Agilent DSO-X 2012A
Oscilloscope. These results are recorded with the presence of a 5 pF input capacitance emulating
a BLM layer with an ion-channel embedded inside and they indicate that the presented system is
capable of observing pulses as small as 10 pA with a width of 10 Âľs. A comparison of the results
and circuit dimensions are shown in Table 2. The presented circuit has comparable specs in terms
of bandwidth and noise performance to the works presented in literature. However, the strength of
this work relies in the fact that the area and power consumption of the presented circuit is much
lower than what is usually presented in the literature despite the fact that this work has been

57

implemented in a much bigger technology. As a result, the presented buffer topology is suitable
for interfacing arrays and ion channels in a lab-on-CMOS configuration.

Pulse width= 500 ÂľS

∆V= 1 mV

Response to
10 pA input

Noise floor of
approximately 9.65 pA
20 mV for ch2
1 mV for ch1
Figure 4-9 The input pulse waveform recorded from channel 1 (ch1) and the system
response to the pulsed input current in channel 2 (ch2).

Table 2 Comparison of the state of art pore interface circuit performance.
[59]

[60]

[61]

[62]

[56]

This Work

Membrane
Capacitance

-

<20 pF

750 pF

<6 pF

10 pF

5 pF

Bandwidth

10 kHz

10 kHz

100 kHz

100 kHz

100 kHz

100 kHz

Area

0.3 mm2

<1.25 mm2

-

0.2 mm2

-

0.05 mm2

Power

502 ÂľW

40 mW

-

5 mW

-

380 ÂľW

RMS noise

4.2 pA@10 kHz

1.2 pA@10 kHz

90 pA@100 kHz

3.2 pA@100
kHz

7.57 pA@100
kHz

9.65pA @
100kHz

Technology

0.35Âľm

0.35Âľm

-

0.13Âľm

0.35Âľm

0.5Âľm

58

4.4.

Conclusion

This chapter presents a CMOS cheap for testing an instrumentation circuit that is aimed for
interfacing ion-channels. Circuit characterization results show that the presented circuit presents
adequate noise performance to interface an ion-channel with an estimated input capacitance of 5
over a bandwidth of 100 kHz with pA level input range.

59

5. Summary and Future work
5.1.

Summary

A lab-on-CMOS design concept for high throughput analysis of ion channel proteins was
described. A CMOS electrochemical interface circuit was presented to simultaneously achieve
stringent requirements in terms of resolution, speed, power and area. The circuit is aimed to be
used in a array structure of thousands of isolated chambers each containing a BLM layer with an
ion-channel nano-pore embedded inside. The BLM layer has an intrinsic capacitance that creates
a noise element that increases with frequency. This issue combined with the fact that there are
stringent limitations on interface circuit area and power creates a unique challenge that has not
been addressed in literature. The presented work provides a unique solution to this issue through
a technique called op-amp sharing together with a transistor-only feedback structure and a unique
op-amp placement topology. A test chip was implemented in AMI 0.5 Âľm C5N CMOS technology
to test the presented design before it is implemented in an actual biological environment. The
results suggest that the presented interface is capable to detect pulsed input currents in a noisy
environment with the presence of input capacitance while keeping the total are and power to a
minimum.

5.2.

Contribution

This dissertation bridges the gap between the world of electrochemistry, especially the
effort to detect single molecule events through ion-channels, and the world of microelectronics.
This innovative approach can be worded as:

60

•

Developed a new CMOS current sensing instrumentation circuit with superior area, power
performance over works presented in literature with adequate noise performance and
bandwidth to interface ion channels
A new CMOS instrument is designed that addresses the existing challenges in interfacing

high throughput arrays of ion channels implemented on a bio-sensor chip. This circuit is able to
read single molecule events on an ion-channel with an estimated BLM capacitance of 5 pf that are
as low as 10 pA and as fast as 10 Âľs. Compared to circuits made for similar purposes, the presented
design has superior performance in area and power while having a comparable accuracy and
bandwidth. At its current state this new circuit would enable building a high throughput (over 500)
ion-channels on a biosensor chip with the interface circuit situated right below each ion-channel.
This method can be used to address the disadvantages of traditional ion-channels by helping
characterize massive arrays or help detect molecules in a microfluidic solution such as DNA
strands.

5.3.

Future work

The future work for this project would involve perfecting the technique required for
implementing the ion-channels efficiently over a lab-on-chip platform so this instrumentation
technique would be used for observing the variations in ion-channel current and possibly
characterizing these nano-pores.

61

REFERENCES

62

REFERENCES

[1]

G. Zheng and C. M. Lieber, “Nanowire Biosensors for Label-Free, Real-Time,
Ultrasensitive Protein Detection,” in Nanoproteomics: Methods and Protocols, S. A. Toms
and R. J. Weil, Eds. Totowa, NJ: Humana Press, 2011, pp. 223–237.

[2]

J. Wang, “Carbon-Nanotube Based Electrochemical
Electroanalysis, vol. 17, no. 1, pp. 7–14, 2005.

[3]

D. Zhang and Q. Liu, “Biosensors and bioelectronics on smartphone for portable
biochemical detection,” Biosens. Bioelectron., vol. 75, pp. 273–284, 2016.

[4]

J. Wang, “Electrochemical biosensors: Towards point-of-care cancer diagnostics,” Biosens.
Bioelectron., vol. 21, no. 10, pp. 1887–1892, 2006.

[5]

H. Li, X. Liu, L. Li, X. Mu, R. Genov, and A. J. Mason, “CMOS Electrochemical
Instrumentation for Biosensor Microsystems: A Review,” Sensors, vol. 17, no. 1, 2017.

[6]

X.-S. Zhou and E. Maisonhaute, Electrochemistry to record single events, vol. 11. The
Royal Society of Chemistry, 2013.

[7]

K. Z. and J. M. P. and S. C. Jacobson, “Transport and sensing in nanofluidic devices,” Annu.
Rev. Anal. Chem., vol. 4, no. 1, pp. 321–41, 2011.

[8]

C. Dekker, “Solid-state nanopores,” Nat Nano, vol. 2, no. 4, pp. 209–215, Apr. 2007.

[9]

J. J. Kasianowicz, J. W. Robertson, E. R. Chan, J. E. Reiner, and V. M. Stanford,
“Nanoscopic Porous Sensors,” Annu. Rev. Anal. Chem., vol. 1, no. 1, pp. 737–766, 2008.

Biosensors:

A

Review,”

[10] M. Wanunu, T. Dadosh, V. Ray, J. Jin, L. McReynolds, and M. Drndic, “Rapid electronic
detection of probe-specific microRNAs using thin nanopore sensors,” Nat Nano, vol. 5, no.
11, pp. 807–814, Nov. 2010.
[11] O. K. Dudko, J. Mathé, A. Szabo, A. Meller, and G. Hummer, “Extracting kinetics from
single-molecule force spectroscopy: nanopore unzipping of DNA hairpins,” Biophys. J.,
vol. 92, no. 12, pp. 4188–4195, 2007.
[12] K. M. Halverson, R. G. Panchal, T. L. Nguyen, R. Gussio, S. F. Little, M. Misakian, S.
Bavari, and J. J. Kasianowicz, “Anthrax biosensor, protective antigen ion channel
asymmetric blockade,” J. Biol. Chem., vol. 280, no. 40, pp. 34056–34062, 2005.
[13] D. W. Deamer and D. Branton, “Characterization of nucleic acids by nanopore analysis,”
Acc. Chem. Res., vol. 35, no. 10, pp. 817–825, 2002.
[14] W. Asghar, A. Ilyas, J. A. Billo, and S. M. Iqbal, “Shrinking of Solid-state Nanopores by
63

Direct Thermal Heating,” Nanoscale Res. Lett., vol. 6, no. 1, p. 372, 2011.
[15] J. D. Uram, K. Ke, and M. Mayer, “Noise and Bandwidth of Current Recordings from
Submicrometer Pores and Nanopores,” ACS Nano, vol. 2, no. 5, pp. 857–872, 2008.
[16] J. Li, D. Stein, C. McMullan, D. Branton, M. J. Aziz, and J. A. Golovchenko, “Ion-beam
sculpting at nanometre length scales,” Nature, vol. 412, no. 6843, pp. 166–169, Jul. 2001.
[17] A. J. Storm, J. H. Chen, X. S. Ling, H. W. Zandbergen, and C. Dekker, “Fabrication of
solid-state nanopores with single-nanometre precision.,” Nat. Mater., vol. 2, pp. 537–540,
2003.
[18] Y. Liu, Z. Matharu, M. C. Howland, A. Revzin, and A. L. Simonian, “Affinity and enzymebased biosensors: Recent advances and emerging applications in cell analysis and point-ofcare testing,” Anal. Bioanal. Chem., vol. 404, no. 4, pp. 1181–1196, 2012.
[19] Y. Huang, Y. Liu, B. L. Hassler, R. M. Worden, and A. J. Mason, “A protein-based
electrochemical biosensor array platform for integrated microsystems,” IEEE Trans.
Biomed. Circuits Syst., vol. 7, no. 1, pp. 43–51, 2013.
[20] S. R. Jadhav, D. Sui, R. M. Garavito, and R. M. Worden, “Fabrication of highly insulating
tethered bilayer lipid membrane using yeast cell membrane fractions for measuring ion
channel activity,” J. Colloid Interface Sci., vol. 322, no. 2, pp. 465–472, 2008.
[21] J. Prashar, P. Sharp, M. Scarffe, and B. Cornell, “Making lipid membranes even tougher,”
J. Mater. Res., vol. 22, no. 8, pp. 2189–2194, 2011.
[22] M. Crescentini, M. Bennati, M. Carminati, and M. Tartagni, “Noise limits of CMOS current
interfaces for biosensors: a review.,” IEEE Trans. Biomed. Circuits Syst., vol. 8, no. 2, pp.
278–292, Apr. 2014.
[23] M. Uram, Jeffrey D. and Ke, Kevin and Mayer, “Noise and Bandwidth of Current
Recordings from Submicrometer Pores and Nanopores,” ACS Nano, vol. 2, no. 5, pp. 857–
872, 2008.
[24] F. Hamill, Owen P and Marty, A and Neher, Erwin and Sakmann, Bert and Sigworth,
“Improved patch-clamp techniques for high-resolution current recording from cells and
cell-free membrane patches,” Pflugers Arch., vol. 391, no. 2, pp. 85–100, 1981.
[25] X. Liu, “CMOS INSTRUMENTATION FOR ELECTROCHEMICAL BIOSENSOR
ARRAY MICROSYSTEMS,” Michigan State University, 2014.
[26] S. Parsnejad, H. Li, and A. J. Mason, “Compact CMOS amperometric readout for nanopore
arrays in high throughput lab-on-CMOS,” Proc. - IEEE Int. Symp. Circuits Syst., vol. 2016–
July, pp. 2851–2854, 2016.
[27] D. Wei, M. J. a Bailey, P. Andrew, and T. Ryhänen, “Electrochemical biosensors at the
nanoscale.,” Lab Chip, vol. 9, no. 15, pp. 2123–2131, 2009.

64

[28] J. Homola, S. S. Yee, and G. Gauglitz, “Surface plasmon resonance sensors: review,”
Sensors Actuators B Chem., vol. 54, no. 1–2, pp. 3–15, 1999.
[29] H. Sharma and R. Mutharasan, “Review of biosensors for foodborne pathogens and toxins,”
Sensors Actuators, B Chem., vol. 183, pp. 535–549, 2013.
[30] C. I. Cheng, Y.-P. Chang, and Y.-H. Chu, “Biomolecular interactions and tools for their
recognition: focus on the quartz crystal microbalance and its diverse surface chemistries and
applications.,” Chem. Soc. Rev., vol. 41, no. 5, pp. 1947–1971, 2012.
[31] R. S. Gaster, D. A. Hall, C. H. Nielsen, S. J. Osterfeld, H. Yu, K. E. Mach, R. J. Wilson, B.
Murmann, J. C. Liao, S. S. Gambhir, and S. X. Wang, “Matrix-insensitive protein assays
push the limits of biosensors in medicine.,” Nat. Med., vol. 15, no. 11, pp. 1327–32, 2009.
[32] B. and others Hille, Ion channels of excitable membranes. Sinauer Sunderland, MA, 2001.
[33] H. Li, “compact, low-power microelectronic instrumentation for wearable electrochemical
sensor arrays in health hazard monitoring,” Michigan State University, 2016.
[34] R. S. Martin, S. M. Lunte, W. Vandaveer, and S. Pasas-Farmer, “Recent developments in
amperometric detection for microchip capillary electrophoresis,” Electrophoresis, vol. 23,
pp. 3667–3677, 2002.
[35] A. Bhat, “Stabilized TIAs Key To Reliable Performance,” Electronic Design, 2011.
[Online].
Available:
http://electronicdesign.com/analog/stabilized-tias-key-reliableperformance.
[36] J. K. Rosenstein and K. L. Shepard, “Temporal Resolution of Nanopore Sensor
Recordings,” in 35th Annual International Conference of the IEEE Engineering in Medicine
and Biology Society, 2013, pp. 4110–4113.
[37] M. Crescentini, M. Bennati, M. Carminati, and M. Tartagni, “Noise limits of CMOS current
interfaces for biosensors: a review.,” IEEE Trans. Biomed. Circuits Syst., vol. 8, no. 2, pp.
278–292, Apr. 2014.
[38] M. F. Lopez and M. G. Pluskal, “Protein micro- and macroarrays: digitizing the proteome,”
J. Chromatogr. B, vol. 787, no. 1, pp. 19–27, 2003.
[39] B. B. Haab, M. J. Dunham, and P. O. Brown, “Protein microarrays for highly parallel
detection and quantitation of specific proteins and antibodies in complex solutions,”
Genome Biol., vol. 2, no. 2, p. research0004.1, 2001.
[40] Xiaowen Liu, “CMOS INSTRUMENTATION FOR ELECTROCHEMICAL
BIOSENSOR ARRAY MICROSYSTEMS,” Michigan State University, 2014.
[41] L. Li and A. Mason, “Development of an Integrated CMOS-Microfluidic Instrumentation
Array for High Throughput Membrane Protein Studies,” in Circuits and Systems (ISCAS),
2014 IEEE International Symposium on, 2014, pp. 638–641.

65

[42] F. Thei, M. Rossi, M. Bennati, M. Crescentini, F. Lodesani, H. Morgan, and M. Tartagni,
“Parallel recording of single ion channels: A heterogeneous system approach,” IEEE Trans.
Nanotechnol., vol. 9, no. 3, pp. 295–302, 2010.
[43] B. Le Pioufle, H. Suzuki, K. V Tabata, H. Noji, and S. Takeuchi, “Lipid Bilayer Microarray
for Parallel Recording of Transmembrane Ion Currents,” Anal. Chem., vol. 80, no. 1, pp.
328--332, 2008.
[44] H. Li, S. Parsnejad, E. Ashoori, C. Thompson, E. Purcell, and A. J. Mason, “Ultra-compact
Micro-watt CMOS Current Readout with Pico-ampere Noise for Biosensor Arrays,” IEEE
Sensors J. Prep., 2017.
[45] B. Goldstein, G. S. Member, D. Kim, J. Xu, T. K. Vanderlick, E. Culurciello, and S.
Member, “CMOS Low Current Measurement System for Biomedical Applications,”
Biomed. Circuits Syst. IEEE Trans., vol. 6, no. 2, pp. 111–119, 2012.
[46] L. Li and A. Mason, “Development of an integrated CMOS-microfluidic instrumentation
array for high throughput membrane protein studies,” in IEEE International Symposium on
Circuits and Systems, 2014, pp. 638–641.
[47] S. Ayers, S. Member, K. D. Gillis, M. Lindau, and B. A. Minch, “Design of a CMOS
Potentiostat Circuit for Electrochemical Detector Arrays,” Circuits Syst. I Regul. Pap. IEEE
Trans., vol. 54, no. 4, pp. 736–744, 2007.
[48] A. J. Liu, Xiaowen and Li, Lin and Mason, “High Throughput Single-Ion-Channel Array
Microsystem with CMOS Instrumentation,” in 36th Annual International Conference of the
IEEE Engineering in Medicince and Biology Society, 2014, pp. 2765–2768.
[49] T. Mach, C. Chimerel, J. Fritz, N. Fertig, M. Winterhalter, and C. Fütterer, “Miniaturized
planar lipid bilayer: increased stability, low electric noise and fast fluid perfusion,” Anal.
Bioanal. Chem., vol. 390, no. 3, pp. 841–846, 2008.
[50] H. Suzuki, B. Le Pioufle, and S. Takeuhci, “Ninety-six-well planar lipid bilayer chip for ion
channel recording Fabricated by hybrid stereolithography,” Biomed. Microdevices, vol. 11,
no. 1, p. 17, 2008.
[51] B. Le Pioufle, H. Suzuki, K. V Tabata, H. Noji, and S. Takeuchi, “Lipid bilayer microarray
for parallel recording of transmembrane ion currents,” Anal. Chem., vol. 80, no. 1, pp. 328-332, 2008.
[52] Lin Li, Xiaowen Liu, W. a Qureshi, and a J. Mason, “CMOS Amperometric
Instrumentation and Packaging for Biosensor Array Applications.,” IEEE Trans. Biomed.
Circuits Syst., vol. 5, no. 5, pp. 439–48, Oct. 2011.
[53] M. Crescentini, M. Bennati, M. Carminati, and M. Tartagni, “Noise limits of CMOS current
interfaces for biosensors: a review.,” IEEE Trans. Biomed. Circuits Syst., vol. 8, no. 2, pp.
278–92, Apr. 2014.

66

[54] C. R. Seese, Timothy M and Harasaki, Hiroaki and Saidel, Gerald M and Davies,
“Characterization of tissue morphology, angiogenesis, and temperature in the adaptive
response of muscle tissue to chronic heating,” Lab. Invest., vol. 78, no. 12, pp. 1553--1562,
1998.
[55] S. Gray, Paul R and Hurst, Paul and Meyer, Robert G and Lewis, Analysis and design of
analog integrated circuits. Wiley, 2001.
[56] P. Ciccarella, M. Carminati, G. Ferrari, and P. Milano, “Integrated Low-Noise Current
Amplifier for Glass-Based Nanopore Sensing,” in 10th Conference on Ph.D. Research in
Microelectronics and Electronics (PRIME), 2014, pp. 1–4.
[57] C. Jakobson, I. Bloom, and Y. Nemirovsky, “1 / F Noise in Cmos Transistors for Analog
Applications From Subthreshold To Saturation,” Solid. State. Electron., vol. 42, no. 10, pp.
1807–1817, 1998.
[58] B. Goldstein, G. S. Member, D. Kim, J. Xu, T. K. Vanderlick, E. Culurciello, and S.
Member, “CMOS Low Current Measurement System for Biomedical Applications,”
Biomed. Circuits Syst. IEEE Trans., vol. 6, no. 2, pp. 111–119, 2012.
[59] J. Kim, R. Maitra, K. D. Pedrotti, and W. B. Dunbar, “A patch-clamp ASIC for nanoporebased DNA analysis.,” IEEE Trans. Biomed. Circuits Syst., vol. 7, no. 3, pp. 285–95, Jun.
2013.
[60] M. T. M. Crescentini, F. Thei, M. Bennati, S. Saha, M. R. R. de Planque, H. Morgan, “A
Distributed Amplifier System for Bilayer Lipid Membrane (BLM) Arrays with Noise and
Individual Offset Cancellation,” Biomed. Circuits Syst. IEEE Trans., vol. 9, no. 3, pp. 334–
344, 2015.
[61] M. Carminati, G. Ferrari, A. P. Ivanov, T. Albrecht, and M. Sampietro, “Design and
characterization of a current sensing platform for silicon-based nanopores with integrated
tunneling nanoelectrodes,” Analog Integr. Circuits Signal Process., vol. 77, no. 3, pp. 333–
343, Oct. 2013.
[62] J. K. Rosenstein, M. Wanunu, C. a Merchant, M. Drndic, and K. L. Shepard, “Integrated
nanopore sensing platform with sub-microsecond temporal resolution.,” Nat. Methods, vol.
9, no. 5, pp. 487–92, May 2012.

67