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Electronic Theses & Dissertations
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A placement methodology for low power VLSI circuits
Jiménez-Cedeño, Manuel A.
Text (1999)
Part of
Electronic Theses & Dissertations
A VLSI chip architecture for the B-spline surface evaluation
Maa, Chia-Yiu
Text (1987)
Part of
Electronic Theses & Dissertations
Acceleration of simulated annealing building block placement process
Vai, Man Kuan
Text (1987)
Part of
Electronic Theses & Dissertations
Performance tradeoffs in the hierarchical design of regular VLSI structures
Leung, Yu-Ying Jackson
Text (1986)
Part of
Electronic Theses & Dissertations
On partitioning of algorithms for parallel execution on VLSI circuit architectures
Driscoll, Michael A.
Text (1988)
Part of
Electronic Theses & Dissertations
Theory and implementation of computer graphic drawing algorithms and routing tools in a VLSI design environment
Chen, Yu-Tse
Text (1989)
Part of
Electronic Theses & Dissertations
Evaluation of a single VLSI chip algorithm for triangulating large band form matrices
Hsü, Wen-chʻang
Text (1982)
Part of
Electronic Theses & Dissertations
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